diff options
| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2012-06-06 06:42:36 -0400 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2012-07-09 12:37:35 -0400 |
| commit | 3169663ac5902f2228ea0eb8cc34eb52cbd4b283 (patch) | |
| tree | 5eb1d323c4a268e77ce39fdd20c3f243667f736e /arch/arm/mach-pxa/include/mach | |
| parent | bcccc50ce8fcc833cfed4bb71ede211a6ef5b84a (diff) | |
ARM: sa11x0/pxa: convert OS timer registers to IOMEM
Make the OS timer registers have IOMEM like properities so they can
be passed to readl_relaxed/writel_relaxed() et.al. rather than being
straight volatile dereferences. Add linux/io.h includes where
required.
linux/io.h includes added to arch/arm/mach-sa1100/cpu-sa1100.c,
arch/arm/mach-sa1100/jornada720_ssp.c, arch/arm/mach-sa1100/leds-lart.c
drivers/input/touchscreen/jornada720_ts.c, drivers/pcmcia/sa1100_shannon.c
from Arnd.
This fixes these warnings:
arch/arm/mach-sa1100/time.c: In function 'sa1100_timer_init':
arch/arm/mach-sa1100/time.c:104: warning: passing argument 1 of 'clocksource_mmio_init' discards qualifiers from pointer target type
arch/arm/mach-pxa/time.c: In function 'pxa_timer_init':
arch/arm/mach-pxa/time.c:126: warning: passing argument 1 of 'clocksource_mmio_init' discards qualifiers from pointer target type
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-pxa/include/mach')
| -rw-r--r-- | arch/arm/mach-pxa/include/mach/regs-ost.h | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/arch/arm/mach-pxa/include/mach/regs-ost.h b/arch/arm/mach-pxa/include/mach/regs-ost.h index a3e5f86ef67e..628819995c52 100644 --- a/arch/arm/mach-pxa/include/mach/regs-ost.h +++ b/arch/arm/mach-pxa/include/mach/regs-ost.h | |||
| @@ -7,17 +7,17 @@ | |||
| 7 | * OS Timer & Match Registers | 7 | * OS Timer & Match Registers |
| 8 | */ | 8 | */ |
| 9 | 9 | ||
| 10 | #define OSMR0 __REG(0x40A00000) /* */ | 10 | #define OSMR0 io_p2v(0x40A00000) /* */ |
| 11 | #define OSMR1 __REG(0x40A00004) /* */ | 11 | #define OSMR1 io_p2v(0x40A00004) /* */ |
| 12 | #define OSMR2 __REG(0x40A00008) /* */ | 12 | #define OSMR2 io_p2v(0x40A00008) /* */ |
| 13 | #define OSMR3 __REG(0x40A0000C) /* */ | 13 | #define OSMR3 io_p2v(0x40A0000C) /* */ |
| 14 | #define OSMR4 __REG(0x40A00080) /* */ | 14 | #define OSMR4 io_p2v(0x40A00080) /* */ |
| 15 | #define OSCR __REG(0x40A00010) /* OS Timer Counter Register */ | 15 | #define OSCR io_p2v(0x40A00010) /* OS Timer Counter Register */ |
| 16 | #define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */ | 16 | #define OSCR4 io_p2v(0x40A00040) /* OS Timer Counter Register */ |
| 17 | #define OMCR4 __REG(0x40A000C0) /* */ | 17 | #define OMCR4 io_p2v(0x40A000C0) /* */ |
| 18 | #define OSSR __REG(0x40A00014) /* OS Timer Status Register */ | 18 | #define OSSR io_p2v(0x40A00014) /* OS Timer Status Register */ |
| 19 | #define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */ | 19 | #define OWER io_p2v(0x40A00018) /* OS Timer Watchdog Enable Register */ |
| 20 | #define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */ | 20 | #define OIER io_p2v(0x40A0001C) /* OS Timer Interrupt Enable Register */ |
| 21 | 21 | ||
| 22 | #define OSSR_M3 (1 << 3) /* Match status channel 3 */ | 22 | #define OSSR_M3 (1 << 3) /* Match status channel 3 */ |
| 23 | #define OSSR_M2 (1 << 2) /* Match status channel 2 */ | 23 | #define OSSR_M2 (1 << 2) /* Match status channel 2 */ |