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authorRussell King <rmk+kernel@arm.linux.org.uk>2012-06-06 06:42:36 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2012-07-09 12:37:35 -0400
commit3169663ac5902f2228ea0eb8cc34eb52cbd4b283 (patch)
tree5eb1d323c4a268e77ce39fdd20c3f243667f736e /arch
parentbcccc50ce8fcc833cfed4bb71ede211a6ef5b84a (diff)
ARM: sa11x0/pxa: convert OS timer registers to IOMEM
Make the OS timer registers have IOMEM like properities so they can be passed to readl_relaxed/writel_relaxed() et.al. rather than being straight volatile dereferences. Add linux/io.h includes where required. linux/io.h includes added to arch/arm/mach-sa1100/cpu-sa1100.c, arch/arm/mach-sa1100/jornada720_ssp.c, arch/arm/mach-sa1100/leds-lart.c drivers/input/touchscreen/jornada720_ts.c, drivers/pcmcia/sa1100_shannon.c from Arnd. This fixes these warnings: arch/arm/mach-sa1100/time.c: In function 'sa1100_timer_init': arch/arm/mach-sa1100/time.c:104: warning: passing argument 1 of 'clocksource_mmio_init' discards qualifiers from pointer target type arch/arm/mach-pxa/time.c: In function 'pxa_timer_init': arch/arm/mach-pxa/time.c:126: warning: passing argument 1 of 'clocksource_mmio_init' discards qualifiers from pointer target type Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-pxa/include/mach/regs-ost.h22
-rw-r--r--arch/arm/mach-pxa/reset.c7
-rw-r--r--arch/arm/mach-pxa/time.c52
-rw-r--r--arch/arm/mach-sa1100/assabet.c2
-rw-r--r--arch/arm/mach-sa1100/cpu-sa1100.c1
-rw-r--r--arch/arm/mach-sa1100/cpu-sa1110.c1
-rw-r--r--arch/arm/mach-sa1100/include/mach/SA-1100.h16
-rw-r--r--arch/arm/mach-sa1100/include/mach/gpio.h1
-rw-r--r--arch/arm/mach-sa1100/include/mach/hardware.h6
-rw-r--r--arch/arm/mach-sa1100/include/mach/uncompress.h2
-rw-r--r--arch/arm/mach-sa1100/irq.c1
-rw-r--r--arch/arm/mach-sa1100/jornada720_ssp.c1
-rw-r--r--arch/arm/mach-sa1100/leds-cerf.c1
-rw-r--r--arch/arm/mach-sa1100/leds-lart.c1
-rw-r--r--arch/arm/mach-sa1100/pm.c1
-rw-r--r--arch/arm/mach-sa1100/time.c48
16 files changed, 88 insertions, 75 deletions
diff --git a/arch/arm/mach-pxa/include/mach/regs-ost.h b/arch/arm/mach-pxa/include/mach/regs-ost.h
index a3e5f86ef67e..628819995c52 100644
--- a/arch/arm/mach-pxa/include/mach/regs-ost.h
+++ b/arch/arm/mach-pxa/include/mach/regs-ost.h
@@ -7,17 +7,17 @@
7 * OS Timer & Match Registers 7 * OS Timer & Match Registers
8 */ 8 */
9 9
10#define OSMR0 __REG(0x40A00000) /* */ 10#define OSMR0 io_p2v(0x40A00000) /* */
11#define OSMR1 __REG(0x40A00004) /* */ 11#define OSMR1 io_p2v(0x40A00004) /* */
12#define OSMR2 __REG(0x40A00008) /* */ 12#define OSMR2 io_p2v(0x40A00008) /* */
13#define OSMR3 __REG(0x40A0000C) /* */ 13#define OSMR3 io_p2v(0x40A0000C) /* */
14#define OSMR4 __REG(0x40A00080) /* */ 14#define OSMR4 io_p2v(0x40A00080) /* */
15#define OSCR __REG(0x40A00010) /* OS Timer Counter Register */ 15#define OSCR io_p2v(0x40A00010) /* OS Timer Counter Register */
16#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */ 16#define OSCR4 io_p2v(0x40A00040) /* OS Timer Counter Register */
17#define OMCR4 __REG(0x40A000C0) /* */ 17#define OMCR4 io_p2v(0x40A000C0) /* */
18#define OSSR __REG(0x40A00014) /* OS Timer Status Register */ 18#define OSSR io_p2v(0x40A00014) /* OS Timer Status Register */
19#define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */ 19#define OWER io_p2v(0x40A00018) /* OS Timer Watchdog Enable Register */
20#define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */ 20#define OIER io_p2v(0x40A0001C) /* OS Timer Interrupt Enable Register */
21 21
22#define OSSR_M3 (1 << 3) /* Match status channel 3 */ 22#define OSSR_M3 (1 << 3) /* Match status channel 3 */
23#define OSSR_M2 (1 << 2) /* Match status channel 2 */ 23#define OSSR_M2 (1 << 2) /* Match status channel 2 */
diff --git a/arch/arm/mach-pxa/reset.c b/arch/arm/mach-pxa/reset.c
index b4528899ef08..3fab583755d4 100644
--- a/arch/arm/mach-pxa/reset.c
+++ b/arch/arm/mach-pxa/reset.c
@@ -77,9 +77,10 @@ static void do_gpio_reset(void)
77static void do_hw_reset(void) 77static void do_hw_reset(void)
78{ 78{
79 /* Initialize the watchdog and let it fire */ 79 /* Initialize the watchdog and let it fire */
80 OWER = OWER_WME; 80 writel_relaxed(OWER_WME, OWER);
81 OSSR = OSSR_M3; 81 writel_relaxed(OSSR_M3, OSSR);
82 OSMR3 = OSCR + 368640; /* ... in 100 ms */ 82 /* ... in 100 ms */
83 writel_relaxed(readl_relaxed(OSCR) + 368640, OSMR3);
83} 84}
84 85
85void pxa_restart(char mode, const char *cmd) 86void pxa_restart(char mode, const char *cmd)
diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c
index 3d6c9bd90de6..4bc47d63698b 100644
--- a/arch/arm/mach-pxa/time.c
+++ b/arch/arm/mach-pxa/time.c
@@ -35,7 +35,7 @@
35 35
36static u32 notrace pxa_read_sched_clock(void) 36static u32 notrace pxa_read_sched_clock(void)
37{ 37{
38 return OSCR; 38 return readl_relaxed(OSCR);
39} 39}
40 40
41 41
@@ -47,8 +47,8 @@ pxa_ost0_interrupt(int irq, void *dev_id)
47 struct clock_event_device *c = dev_id; 47 struct clock_event_device *c = dev_id;
48 48
49 /* Disarm the compare/match, signal the event. */ 49 /* Disarm the compare/match, signal the event. */
50 OIER &= ~OIER_E0; 50 writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
51 OSSR = OSSR_M0; 51 writel_relaxed(OSSR_M0, OSSR);
52 c->event_handler(c); 52 c->event_handler(c);
53 53
54 return IRQ_HANDLED; 54 return IRQ_HANDLED;
@@ -59,10 +59,10 @@ pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev)
59{ 59{
60 unsigned long next, oscr; 60 unsigned long next, oscr;
61 61
62 OIER |= OIER_E0; 62 writel_relaxed(readl_relaxed(OIER) | OIER_E0, OIER);
63 next = OSCR + delta; 63 next = readl_relaxed(OSCR) + delta;
64 OSMR0 = next; 64 writel_relaxed(next, OSMR0);
65 oscr = OSCR; 65 oscr = readl_relaxed(OSCR);
66 66
67 return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0; 67 return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
68} 68}
@@ -72,15 +72,15 @@ pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev)
72{ 72{
73 switch (mode) { 73 switch (mode) {
74 case CLOCK_EVT_MODE_ONESHOT: 74 case CLOCK_EVT_MODE_ONESHOT:
75 OIER &= ~OIER_E0; 75 writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
76 OSSR = OSSR_M0; 76 writel_relaxed(OSSR_M0, OSSR);
77 break; 77 break;
78 78
79 case CLOCK_EVT_MODE_UNUSED: 79 case CLOCK_EVT_MODE_UNUSED:
80 case CLOCK_EVT_MODE_SHUTDOWN: 80 case CLOCK_EVT_MODE_SHUTDOWN:
81 /* initializing, released, or preparing for suspend */ 81 /* initializing, released, or preparing for suspend */
82 OIER &= ~OIER_E0; 82 writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
83 OSSR = OSSR_M0; 83 writel_relaxed(OSSR_M0, OSSR);
84 break; 84 break;
85 85
86 case CLOCK_EVT_MODE_RESUME: 86 case CLOCK_EVT_MODE_RESUME:
@@ -108,8 +108,8 @@ static void __init pxa_timer_init(void)
108{ 108{
109 unsigned long clock_tick_rate = get_clock_tick_rate(); 109 unsigned long clock_tick_rate = get_clock_tick_rate();
110 110
111 OIER = 0; 111 writel_relaxed(0, OIER);
112 OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3; 112 writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR);
113 113
114 setup_sched_clock(pxa_read_sched_clock, 32, clock_tick_rate); 114 setup_sched_clock(pxa_read_sched_clock, 32, clock_tick_rate);
115 115
@@ -122,7 +122,7 @@ static void __init pxa_timer_init(void)
122 122
123 setup_irq(IRQ_OST0, &pxa_ost0_irq); 123 setup_irq(IRQ_OST0, &pxa_ost0_irq);
124 124
125 clocksource_mmio_init(&OSCR, "oscr0", clock_tick_rate, 200, 32, 125 clocksource_mmio_init(OSCR, "oscr0", clock_tick_rate, 200, 32,
126 clocksource_mmio_readl_up); 126 clocksource_mmio_readl_up);
127 clockevents_register_device(&ckevt_pxa_osmr0); 127 clockevents_register_device(&ckevt_pxa_osmr0);
128} 128}
@@ -132,12 +132,12 @@ static unsigned long osmr[4], oier, oscr;
132 132
133static void pxa_timer_suspend(void) 133static void pxa_timer_suspend(void)
134{ 134{
135 osmr[0] = OSMR0; 135 osmr[0] = readl_relaxed(OSMR0);
136 osmr[1] = OSMR1; 136 osmr[1] = readl_relaxed(OSMR1);
137 osmr[2] = OSMR2; 137 osmr[2] = readl_relaxed(OSMR2);
138 osmr[3] = OSMR3; 138 osmr[3] = readl_relaxed(OSMR3);
139 oier = OIER; 139 oier = readl_relaxed(OIER);
140 oscr = OSCR; 140 oscr = readl_relaxed(OSCR);
141} 141}
142 142
143static void pxa_timer_resume(void) 143static void pxa_timer_resume(void)
@@ -151,12 +151,12 @@ static void pxa_timer_resume(void)
151 if (osmr[0] - oscr < MIN_OSCR_DELTA) 151 if (osmr[0] - oscr < MIN_OSCR_DELTA)
152 osmr[0] += MIN_OSCR_DELTA; 152 osmr[0] += MIN_OSCR_DELTA;
153 153
154 OSMR0 = osmr[0]; 154 writel_relaxed(osmr[0], OSMR0);
155 OSMR1 = osmr[1]; 155 writel_relaxed(osmr[1], OSMR1);
156 OSMR2 = osmr[2]; 156 writel_relaxed(osmr[2], OSMR2);
157 OSMR3 = osmr[3]; 157 writel_relaxed(osmr[3], OSMR3);
158 OIER = oier; 158 writel_relaxed(oier, OIER);
159 OSCR = oscr; 159 writel_relaxed(oscr, OSCR);
160} 160}
161#else 161#else
162#define pxa_timer_suspend NULL 162#define pxa_timer_suspend NULL
diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c
index d1dc7f1a239c..d673211f121c 100644
--- a/arch/arm/mach-sa1100/assabet.c
+++ b/arch/arm/mach-sa1100/assabet.c
@@ -362,7 +362,7 @@ static void __init assabet_init(void)
362static void __init map_sa1100_gpio_regs( void ) 362static void __init map_sa1100_gpio_regs( void )
363{ 363{
364 unsigned long phys = __PREG(GPLR) & PMD_MASK; 364 unsigned long phys = __PREG(GPLR) & PMD_MASK;
365 unsigned long virt = io_p2v(phys); 365 unsigned long virt = (unsigned long)io_p2v(phys);
366 int prot = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_DOMAIN(DOMAIN_IO); 366 int prot = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_DOMAIN(DOMAIN_IO);
367 pmd_t *pmd; 367 pmd_t *pmd;
368 368
diff --git a/arch/arm/mach-sa1100/cpu-sa1100.c b/arch/arm/mach-sa1100/cpu-sa1100.c
index 19b2053f5af4..e8f4d1e19233 100644
--- a/arch/arm/mach-sa1100/cpu-sa1100.c
+++ b/arch/arm/mach-sa1100/cpu-sa1100.c
@@ -87,6 +87,7 @@
87#include <linux/types.h> 87#include <linux/types.h>
88#include <linux/init.h> 88#include <linux/init.h>
89#include <linux/cpufreq.h> 89#include <linux/cpufreq.h>
90#include <linux/io.h>
90 91
91#include <asm/cputype.h> 92#include <asm/cputype.h>
92 93
diff --git a/arch/arm/mach-sa1100/cpu-sa1110.c b/arch/arm/mach-sa1100/cpu-sa1110.c
index 675bf8ef97e8..48c45b0c92bb 100644
--- a/arch/arm/mach-sa1100/cpu-sa1110.c
+++ b/arch/arm/mach-sa1100/cpu-sa1110.c
@@ -19,6 +19,7 @@
19#include <linux/cpufreq.h> 19#include <linux/cpufreq.h>
20#include <linux/delay.h> 20#include <linux/delay.h>
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/io.h>
22#include <linux/kernel.h> 23#include <linux/kernel.h>
23#include <linux/moduleparam.h> 24#include <linux/moduleparam.h>
24#include <linux/types.h> 25#include <linux/types.h>
diff --git a/arch/arm/mach-sa1100/include/mach/SA-1100.h b/arch/arm/mach-sa1100/include/mach/SA-1100.h
index 3f2d1b60188c..0ac6cc08a19c 100644
--- a/arch/arm/mach-sa1100/include/mach/SA-1100.h
+++ b/arch/arm/mach-sa1100/include/mach/SA-1100.h
@@ -830,14 +830,14 @@
830 * (read/write). 830 * (read/write).
831 */ 831 */
832 832
833#define OSMR0 __REG(0x90000000) /* OS timer Match Reg. 0 */ 833#define OSMR0 io_p2v(0x90000000) /* OS timer Match Reg. 0 */
834#define OSMR1 __REG(0x90000004) /* OS timer Match Reg. 1 */ 834#define OSMR1 io_p2v(0x90000004) /* OS timer Match Reg. 1 */
835#define OSMR2 __REG(0x90000008) /* OS timer Match Reg. 2 */ 835#define OSMR2 io_p2v(0x90000008) /* OS timer Match Reg. 2 */
836#define OSMR3 __REG(0x9000000c) /* OS timer Match Reg. 3 */ 836#define OSMR3 io_p2v(0x9000000c) /* OS timer Match Reg. 3 */
837#define OSCR __REG(0x90000010) /* OS timer Counter Reg. */ 837#define OSCR io_p2v(0x90000010) /* OS timer Counter Reg. */
838#define OSSR __REG(0x90000014 ) /* OS timer Status Reg. */ 838#define OSSR io_p2v(0x90000014) /* OS timer Status Reg. */
839#define OWER __REG(0x90000018 ) /* OS timer Watch-dog Enable Reg. */ 839#define OWER io_p2v(0x90000018) /* OS timer Watch-dog Enable Reg. */
840#define OIER __REG(0x9000001C ) /* OS timer Interrupt Enable Reg. */ 840#define OIER io_p2v(0x9000001C) /* OS timer Interrupt Enable Reg. */
841 841
842#define OSSR_M(Nb) /* Match detected [0..3] */ \ 842#define OSSR_M(Nb) /* Match detected [0..3] */ \
843 (0x00000001 << (Nb)) 843 (0x00000001 << (Nb))
diff --git a/arch/arm/mach-sa1100/include/mach/gpio.h b/arch/arm/mach-sa1100/include/mach/gpio.h
index a38fc4f54241..6a9eecf3137e 100644
--- a/arch/arm/mach-sa1100/include/mach/gpio.h
+++ b/arch/arm/mach-sa1100/include/mach/gpio.h
@@ -24,6 +24,7 @@
24#ifndef __ASM_ARCH_SA1100_GPIO_H 24#ifndef __ASM_ARCH_SA1100_GPIO_H
25#define __ASM_ARCH_SA1100_GPIO_H 25#define __ASM_ARCH_SA1100_GPIO_H
26 26
27#include <linux/io.h>
27#include <mach/hardware.h> 28#include <mach/hardware.h>
28#include <asm/irq.h> 29#include <asm/irq.h>
29#include <asm-generic/gpio.h> 30#include <asm-generic/gpio.h>
diff --git a/arch/arm/mach-sa1100/include/mach/hardware.h b/arch/arm/mach-sa1100/include/mach/hardware.h
index 99f5856d8de4..cbedd75a9d65 100644
--- a/arch/arm/mach-sa1100/include/mach/hardware.h
+++ b/arch/arm/mach-sa1100/include/mach/hardware.h
@@ -32,7 +32,7 @@
32#define PIO_START 0x80000000 /* physical start of IO space */ 32#define PIO_START 0x80000000 /* physical start of IO space */
33 33
34#define io_p2v( x ) \ 34#define io_p2v( x ) \
35 ( (((x)&0x00ffffff) | (((x)&0x30000000)>>VIO_SHIFT)) + VIO_BASE ) 35 IOMEM( (((x)&0x00ffffff) | (((x)&0x30000000)>>VIO_SHIFT)) + VIO_BASE )
36#define io_v2p( x ) \ 36#define io_v2p( x ) \
37 ( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START ) 37 ( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START )
38 38
@@ -47,6 +47,8 @@
47#define CPU_SA1110_ID (0x6901b110) 47#define CPU_SA1110_ID (0x6901b110)
48#define CPU_SA1110_MASK (0xfffffff0) 48#define CPU_SA1110_MASK (0xfffffff0)
49 49
50#define __MREG(x) IOMEM(io_p2v(x))
51
50#ifndef __ASSEMBLY__ 52#ifndef __ASSEMBLY__
51 53
52#include <asm/cputype.h> 54#include <asm/cputype.h>
@@ -56,7 +58,7 @@
56#define cpu_is_sa1100() ((read_cpuid_id() & CPU_SA1100_MASK) == CPU_SA1100_ID) 58#define cpu_is_sa1100() ((read_cpuid_id() & CPU_SA1100_MASK) == CPU_SA1100_ID)
57#define cpu_is_sa1110() ((read_cpuid_id() & CPU_SA1110_MASK) == CPU_SA1110_ID) 59#define cpu_is_sa1110() ((read_cpuid_id() & CPU_SA1110_MASK) == CPU_SA1110_ID)
58 60
59# define __REG(x) (*((volatile unsigned long *)io_p2v(x))) 61# define __REG(x) (*((volatile unsigned long __iomem *)io_p2v(x)))
60# define __PREG(x) (io_v2p((unsigned long)&(x))) 62# define __PREG(x) (io_v2p((unsigned long)&(x)))
61 63
62static inline unsigned long get_clock_tick_rate(void) 64static inline unsigned long get_clock_tick_rate(void)
diff --git a/arch/arm/mach-sa1100/include/mach/uncompress.h b/arch/arm/mach-sa1100/include/mach/uncompress.h
index 6cb39ddde656..5cf71da60e42 100644
--- a/arch/arm/mach-sa1100/include/mach/uncompress.h
+++ b/arch/arm/mach-sa1100/include/mach/uncompress.h
@@ -8,6 +8,8 @@
8 8
9#include "hardware.h" 9#include "hardware.h"
10 10
11#define IOMEM(x) (x)
12
11/* 13/*
12 * The following code assumes the serial port has already been 14 * The following code assumes the serial port has already been
13 * initialized by the bootloader. We search for the first enabled 15 * initialized by the bootloader. We search for the first enabled
diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c
index 516ccc25d7fd..2124f1fc2fbe 100644
--- a/arch/arm/mach-sa1100/irq.c
+++ b/arch/arm/mach-sa1100/irq.c
@@ -12,6 +12,7 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/interrupt.h> 14#include <linux/interrupt.h>
15#include <linux/io.h>
15#include <linux/irq.h> 16#include <linux/irq.h>
16#include <linux/ioport.h> 17#include <linux/ioport.h>
17#include <linux/syscore_ops.h> 18#include <linux/syscore_ops.h>
diff --git a/arch/arm/mach-sa1100/jornada720_ssp.c b/arch/arm/mach-sa1100/jornada720_ssp.c
index b412fc09c80c..7f07f08d8968 100644
--- a/arch/arm/mach-sa1100/jornada720_ssp.c
+++ b/arch/arm/mach-sa1100/jornada720_ssp.c
@@ -18,6 +18,7 @@
18#include <linux/module.h> 18#include <linux/module.h>
19#include <linux/platform_device.h> 19#include <linux/platform_device.h>
20#include <linux/sched.h> 20#include <linux/sched.h>
21#include <linux/io.h>
21 22
22#include <mach/hardware.h> 23#include <mach/hardware.h>
23#include <mach/jornada720.h> 24#include <mach/jornada720.h>
diff --git a/arch/arm/mach-sa1100/leds-cerf.c b/arch/arm/mach-sa1100/leds-cerf.c
index 040540fb7d8a..30fc3b2bf555 100644
--- a/arch/arm/mach-sa1100/leds-cerf.c
+++ b/arch/arm/mach-sa1100/leds-cerf.c
@@ -4,6 +4,7 @@
4 * Author: ??? 4 * Author: ???
5 */ 5 */
6#include <linux/init.h> 6#include <linux/init.h>
7#include <linux/io.h>
7 8
8#include <mach/hardware.h> 9#include <mach/hardware.h>
9#include <asm/leds.h> 10#include <asm/leds.h>
diff --git a/arch/arm/mach-sa1100/leds-lart.c b/arch/arm/mach-sa1100/leds-lart.c
index a51830c60e53..50a5b143b460 100644
--- a/arch/arm/mach-sa1100/leds-lart.c
+++ b/arch/arm/mach-sa1100/leds-lart.c
@@ -10,6 +10,7 @@
10 * pace of the LED. 10 * pace of the LED.
11 */ 11 */
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/io.h>
13 14
14#include <mach/hardware.h> 15#include <mach/hardware.h>
15#include <asm/leds.h> 16#include <asm/leds.h>
diff --git a/arch/arm/mach-sa1100/pm.c b/arch/arm/mach-sa1100/pm.c
index 690cf0ce5c0c..6645d1e31f14 100644
--- a/arch/arm/mach-sa1100/pm.c
+++ b/arch/arm/mach-sa1100/pm.c
@@ -23,6 +23,7 @@
23 * Storage is local on the stack now. 23 * Storage is local on the stack now.
24 */ 24 */
25#include <linux/init.h> 25#include <linux/init.h>
26#include <linux/io.h>
26#include <linux/suspend.h> 27#include <linux/suspend.h>
27#include <linux/errno.h> 28#include <linux/errno.h>
28#include <linux/time.h> 29#include <linux/time.h>
diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c
index 6af26e8d55e6..80702c9ecc77 100644
--- a/arch/arm/mach-sa1100/time.c
+++ b/arch/arm/mach-sa1100/time.c
@@ -22,7 +22,7 @@
22 22
23static u32 notrace sa1100_read_sched_clock(void) 23static u32 notrace sa1100_read_sched_clock(void)
24{ 24{
25 return OSCR; 25 return readl_relaxed(OSCR);
26} 26}
27 27
28#define MIN_OSCR_DELTA 2 28#define MIN_OSCR_DELTA 2
@@ -32,8 +32,8 @@ static irqreturn_t sa1100_ost0_interrupt(int irq, void *dev_id)
32 struct clock_event_device *c = dev_id; 32 struct clock_event_device *c = dev_id;
33 33
34 /* Disarm the compare/match, signal the event. */ 34 /* Disarm the compare/match, signal the event. */
35 OIER &= ~OIER_E0; 35 writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
36 OSSR = OSSR_M0; 36 writel_relaxed(OSSR_M0, OSSR);
37 c->event_handler(c); 37 c->event_handler(c);
38 38
39 return IRQ_HANDLED; 39 return IRQ_HANDLED;
@@ -44,10 +44,10 @@ sa1100_osmr0_set_next_event(unsigned long delta, struct clock_event_device *c)
44{ 44{
45 unsigned long next, oscr; 45 unsigned long next, oscr;
46 46
47 OIER |= OIER_E0; 47 writel_relaxed(readl_relaxed(OIER) | OIER_E0, OIER);
48 next = OSCR + delta; 48 next = readl_relaxed(OSCR) + delta;
49 OSMR0 = next; 49 writel_relaxed(next, OSMR0);
50 oscr = OSCR; 50 oscr = readl_relaxed(OSCR);
51 51
52 return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0; 52 return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
53} 53}
@@ -59,8 +59,8 @@ sa1100_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *c)
59 case CLOCK_EVT_MODE_ONESHOT: 59 case CLOCK_EVT_MODE_ONESHOT:
60 case CLOCK_EVT_MODE_UNUSED: 60 case CLOCK_EVT_MODE_UNUSED:
61 case CLOCK_EVT_MODE_SHUTDOWN: 61 case CLOCK_EVT_MODE_SHUTDOWN:
62 OIER &= ~OIER_E0; 62 writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
63 OSSR = OSSR_M0; 63 writel_relaxed(OSSR_M0, OSSR);
64 break; 64 break;
65 65
66 case CLOCK_EVT_MODE_RESUME: 66 case CLOCK_EVT_MODE_RESUME:
@@ -86,8 +86,8 @@ static struct irqaction sa1100_timer_irq = {
86 86
87static void __init sa1100_timer_init(void) 87static void __init sa1100_timer_init(void)
88{ 88{
89 OIER = 0; 89 writel_relaxed(0, OIER);
90 OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3; 90 writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR);
91 91
92 setup_sched_clock(sa1100_read_sched_clock, 32, 3686400); 92 setup_sched_clock(sa1100_read_sched_clock, 32, 3686400);
93 93
@@ -100,7 +100,7 @@ static void __init sa1100_timer_init(void)
100 100
101 setup_irq(IRQ_OST0, &sa1100_timer_irq); 101 setup_irq(IRQ_OST0, &sa1100_timer_irq);
102 102
103 clocksource_mmio_init(&OSCR, "oscr", CLOCK_TICK_RATE, 200, 32, 103 clocksource_mmio_init(OSCR, "oscr", CLOCK_TICK_RATE, 200, 32,
104 clocksource_mmio_readl_up); 104 clocksource_mmio_readl_up);
105 clockevents_register_device(&ckevt_sa1100_osmr0); 105 clockevents_register_device(&ckevt_sa1100_osmr0);
106} 106}
@@ -110,26 +110,26 @@ unsigned long osmr[4], oier;
110 110
111static void sa1100_timer_suspend(void) 111static void sa1100_timer_suspend(void)
112{ 112{
113 osmr[0] = OSMR0; 113 osmr[0] = readl_relaxed(OSMR0);
114 osmr[1] = OSMR1; 114 osmr[1] = readl_relaxed(OSMR1);
115 osmr[2] = OSMR2; 115 osmr[2] = readl_relaxed(OSMR2);
116 osmr[3] = OSMR3; 116 osmr[3] = readl_relaxed(OSMR3);
117 oier = OIER; 117 oier = readl_relaxed(OIER);
118} 118}
119 119
120static void sa1100_timer_resume(void) 120static void sa1100_timer_resume(void)
121{ 121{
122 OSSR = 0x0f; 122 writel_relaxed(0x0f, OSSR);
123 OSMR0 = osmr[0]; 123 writel_relaxed(osmr[0], OSMR0);
124 OSMR1 = osmr[1]; 124 writel_relaxed(osmr[1], OSMR1);
125 OSMR2 = osmr[2]; 125 writel_relaxed(osmr[2], OSMR2);
126 OSMR3 = osmr[3]; 126 writel_relaxed(osmr[3], OSMR3);
127 OIER = oier; 127 writel_relaxed(oier, OIER);
128 128
129 /* 129 /*
130 * OSMR0 is the system timer: make sure OSCR is sufficiently behind 130 * OSMR0 is the system timer: make sure OSCR is sufficiently behind
131 */ 131 */
132 OSCR = OSMR0 - LATCH; 132 writel_relaxed(OSMR0 - LATCH, OSCR);
133} 133}
134#else 134#else
135#define sa1100_timer_suspend NULL 135#define sa1100_timer_suspend NULL