Merge branch 'kirkwood/addr_decode' of git://git.infradead.org/users/jcooper/linux into late/kirkwood

* 'kirkwood/addr_decode' of git://git.infradead.org/users/jcooper/linux: arm: mvebu: add address decoding controller to the DT arm: mvebu: add basic address decoding support to Armada 370/XP arm: plat-orion: make bridge_virt_base non-const to support DT use case arm: plat-orion: introduce PLAT_ORION_LEGACY hidden config option arm: plat-orion: use void __iomem pointers for addr-map functions arm: plat-orion: use void __iomem pointers for time functions arm: plat-orion: use void __iomem pointers for MPP functions arm: plat-orion: use void __iomem pointers for UART registration functions arm: mach-mvebu: use IOMEM() for base address definitions arm: mach-orion5x: use IOMEM() for base address definitions arm: mach-mv78xx0: use IOMEM() for base address definitions arm: mach-kirkwood: use IOMEM() for base address definitions arm: mach-dove: use IOMEM() for base address definitions arm: mach-orion5x: use plus instead of or for address definitions arm: mach-mv78xx0: use plus instead of or for address definitions arm: mach-kirkwood: use plus instead of or for address definitions arm: mach-dove: use plus instead of or for address definitions This branch had quite a few conflicts, in particular with the PCI static map rework from Rob Herring, and a few other context conflicts due to changes in Kconfig, etc. I fixed up conflicts in: arch/arm/Kconfig arch/arm/mach-dove/common.c arch/arm/mach-dove/include/mach/dove.h arch/arm/mach-kirkwood/common.c arch/arm/mach-kirkwood/include/mach/kirkwood.h arch/arm/mach-mv78xx0/common.c arch/arm/mach-mv78xx0/include/mach/mv78xx0.h arch/arm/mach-orion5x/common.c arch/arm/mach-orion5x/include/mach/orion5x.h Signed-off-by: Olof Johansson <olof@lixom.net>
author: Olof Johansson <olof@lixom.net> 2012-09-22 17:09:21 -0400
committer: Olof Johansson <olof@lixom.net> 2012-09-22 17:22:47 -0400
commit: 0d601f613b8557cf6489f06251ae5dc383b811d0 (patch)
tree: 05f3a4d054e0bddc308af479918ce67cd02e8eba /arch/arm/mach-orion5x/include
parent: d7ffa2234c186ce040e79b43639628c1c482b115 (diff)
parent: 5b40baee4a39d96d4d6a48a2b2383982912c429b (diff)
2 files changed, 38 insertions, 38 deletions
diff --git a/arch/arm/mach-orion5x/include/mach/bridge-regs.h b/arch/arm/mach-orion5x/include/mach/bridge-regs.h
index 11a3c1e9801f..461fd69a10ae 100644
--- a/arch/arm/mach-orion5x/include/mach/bridge-regs.h
+++ b/arch/arm/mach-orion5x/include/mach/bridge-regs.h
@@ -13,27 +13,27 @@
 #include <mach/orion5x.h>
-#define CPU_CONF                (ORION5X_BRIDGE_VIRT_BASE | 0x100)
+#define CPU_CONF                (ORION5X_BRIDGE_VIRT_BASE + 0x100)
-#define CPU_CTRL                (ORION5X_BRIDGE_VIRT_BASE | 0x104)
+#define CPU_CTRL                (ORION5X_BRIDGE_VIRT_BASE + 0x104)
-#define RSTOUTn_MASK            (ORION5X_BRIDGE_VIRT_BASE | 0x108)
+#define RSTOUTn_MASK            (ORION5X_BRIDGE_VIRT_BASE + 0x108)
 #define WDT_RESET_OUT_EN        0x0002
-#define CPU_SOFT_RESET          (ORION5X_BRIDGE_VIRT_BASE | 0x10c)
+#define CPU_SOFT_RESET          (ORION5X_BRIDGE_VIRT_BASE + 0x10c)
-#define BRIDGE_CAUSE            (ORION5X_BRIDGE_VIRT_BASE | 0x110)
+#define BRIDGE_CAUSE            (ORION5X_BRIDGE_VIRT_BASE + 0x110)
-#define POWER_MNG_CTRL_REG      (ORION5X_BRIDGE_VIRT_BASE | 0x11C)
+#define POWER_MNG_CTRL_REG      (ORION5X_BRIDGE_VIRT_BASE + 0x11C)
 #define WDT_INT_REQ             0x0008
 #define BRIDGE_INT_TIMER1_CLR   (~0x0004)
-#define MAIN_IRQ_CAUSE          (ORION5X_BRIDGE_VIRT_BASE | 0x200)
+#define MAIN_IRQ_CAUSE          (ORION5X_BRIDGE_VIRT_BASE + 0x200)
-#define MAIN_IRQ_MASK           (ORION5X_BRIDGE_VIRT_BASE | 0x204)
+#define MAIN_IRQ_MASK           (ORION5X_BRIDGE_VIRT_BASE + 0x204)
-#define TIMER_VIRT_BASE         (ORION5X_BRIDGE_VIRT_BASE | 0x300)
+#define TIMER_VIRT_BASE         (ORION5X_BRIDGE_VIRT_BASE + 0x300)
-#define TIMER_PHYS_BASE         (ORION5X_BRIDGE_PHYS_BASE | 0x300)
+#define TIMER_PHYS_BASE         (ORION5X_BRIDGE_PHYS_BASE + 0x300)
 #endif
diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h
index 1b60131b7f60..d265f5484a8e 100644
--- a/arch/arm/mach-orion5x/include/mach/orion5x.h
+++ b/arch/arm/mach-orion5x/include/mach/orion5x.h
@@ -37,7 +37,7 @@
 * fd000000     f0000000        16M     PCIe WA space (Orion-1/Orion-NAS only)
 ****************************************************************************/
 #define ORION5X_REGS_PHYS_BASE          0xf1000000
-#define ORION5X_REGS_VIRT_BASE          0xfe000000
+#define ORION5X_REGS_VIRT_BASE          IOMEM(0xfe000000)
 #define ORION5X_REGS_SIZE               SZ_1M
 #define ORION5X_PCIE_IO_PHYS_BASE       0xf2000000
@@ -53,7 +53,7 @@
 /* Relevant only for Orion-1/Orion-NAS */
 #define ORION5X_PCIE_WA_PHYS_BASE       0xf0000000
-#define ORION5X_PCIE_WA_VIRT_BASE       0xfd000000
+#define ORION5X_PCIE_WA_VIRT_BASE       IOMEM(0xfd000000)
 #define ORION5X_PCIE_WA_SIZE            SZ_16M
 #define ORION5X_PCIE_MEM_PHYS_BASE      0xe0000000
@@ -66,42 +66,42 @@
 * Orion Registers Map
 ******************************************************************************/
-#define ORION5X_DDR_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x00000)
+#define ORION5X_DDR_VIRT_BASE           (ORION5X_REGS_VIRT_BASE + 0x00000)
-#define  ORION5X_DDR_WINDOW_CPU_BASE    (ORION5X_DDR_VIRT_BASE | 0x1500)
+#define  ORION5X_DDR_WINDOW_CPU_BASE    (ORION5X_DDR_VIRT_BASE + 0x1500)
-#define ORION5X_DEV_BUS_PHYS_BASE       (ORION5X_REGS_PHYS_BASE | 0x10000)
+#define ORION5X_DEV_BUS_PHYS_BASE       (ORION5X_REGS_PHYS_BASE + 0x10000)
-#define ORION5X_DEV_BUS_VIRT_BASE       (ORION5X_REGS_VIRT_BASE | 0x10000)
+#define ORION5X_DEV_BUS_VIRT_BASE       (ORION5X_REGS_VIRT_BASE + 0x10000)
-#define ORION5X_DEV_BUS_REG(x)          (ORION5X_DEV_BUS_VIRT_BASE | (x))
+#define ORION5X_DEV_BUS_REG(x)          (ORION5X_DEV_BUS_VIRT_BASE + (x))
 #define  GPIO_VIRT_BASE                 ORION5X_DEV_BUS_REG(0x0100)
-#define  SPI_PHYS_BASE                  (ORION5X_DEV_BUS_PHYS_BASE | 0x0600)
+#define  SPI_PHYS_BASE                  (ORION5X_DEV_BUS_PHYS_BASE + 0x0600)
-#define  I2C_PHYS_BASE                  (ORION5X_DEV_BUS_PHYS_BASE | 0x1000)
+#define  I2C_PHYS_BASE                  (ORION5X_DEV_BUS_PHYS_BASE + 0x1000)
-#define  UART0_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE | 0x2000)
+#define  UART0_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE + 0x2000)
-#define  UART0_VIRT_BASE                (ORION5X_DEV_BUS_VIRT_BASE | 0x2000)
+#define  UART0_VIRT_BASE                (ORION5X_DEV_BUS_VIRT_BASE + 0x2000)
-#define  UART1_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE | 0x2100)
+#define  UART1_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE + 0x2100)
-#define  UART1_VIRT_BASE                (ORION5X_DEV_BUS_VIRT_BASE | 0x2100)
+#define  UART1_VIRT_BASE                (ORION5X_DEV_BUS_VIRT_BASE + 0x2100)
-#define ORION5X_BRIDGE_VIRT_BASE        (ORION5X_REGS_VIRT_BASE | 0x20000)
+#define ORION5X_BRIDGE_VIRT_BASE        (ORION5X_REGS_VIRT_BASE + 0x20000)
-#define ORION5X_BRIDGE_PHYS_BASE        (ORION5X_REGS_PHYS_BASE | 0x20000)
+#define ORION5X_BRIDGE_PHYS_BASE        (ORION5X_REGS_PHYS_BASE + 0x20000)
-#define ORION5X_PCI_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x30000)
+#define ORION5X_PCI_VIRT_BASE           (ORION5X_REGS_VIRT_BASE + 0x30000)
-#define ORION5X_PCIE_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x40000)
+#define ORION5X_PCIE_VIRT_BASE          (ORION5X_REGS_VIRT_BASE + 0x40000)
-#define ORION5X_USB0_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0x50000)
+#define ORION5X_USB0_PHYS_BASE          (ORION5X_REGS_PHYS_BASE + 0x50000)
-#define ORION5X_USB0_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x50000)
+#define ORION5X_USB0_VIRT_BASE          (ORION5X_REGS_VIRT_BASE + 0x50000)
-#define ORION5X_XOR_PHYS_BASE           (ORION5X_REGS_PHYS_BASE | 0x60900)
+#define ORION5X_XOR_PHYS_BASE           (ORION5X_REGS_PHYS_BASE + 0x60900)
-#define ORION5X_XOR_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x60900)
+#define ORION5X_XOR_VIRT_BASE           (ORION5X_REGS_VIRT_BASE + 0x60900)
-#define ORION5X_ETH_PHYS_BASE           (ORION5X_REGS_PHYS_BASE | 0x70000)
+#define ORION5X_ETH_PHYS_BASE           (ORION5X_REGS_PHYS_BASE + 0x70000)
-#define ORION5X_ETH_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x70000)
+#define ORION5X_ETH_VIRT_BASE           (ORION5X_REGS_VIRT_BASE + 0x70000)
-#define ORION5X_SATA_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0x80000)
+#define ORION5X_SATA_PHYS_BASE          (ORION5X_REGS_PHYS_BASE + 0x80000)
-#define ORION5X_SATA_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x80000)
+#define ORION5X_SATA_VIRT_BASE          (ORION5X_REGS_VIRT_BASE + 0x80000)
-#define ORION5X_CRYPTO_PHYS_BASE        (ORION5X_REGS_PHYS_BASE | 0x90000)
+#define ORION5X_CRYPTO_PHYS_BASE        (ORION5X_REGS_PHYS_BASE + 0x90000)
-#define ORION5X_USB1_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0xa0000)
+#define ORION5X_USB1_PHYS_BASE          (ORION5X_REGS_PHYS_BASE + 0xa0000)
-#define ORION5X_USB1_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0xa0000)
+#define ORION5X_USB1_VIRT_BASE          (ORION5X_REGS_VIRT_BASE + 0xa0000)
 /*******************************************************************************
 * Device Bus Registers
author	Olof Johansson <olof@lixom.net>	2012-09-22 17:09:21 -0400
committer	Olof Johansson <olof@lixom.net>	2012-09-22 17:22:47 -0400
commit	0d601f613b8557cf6489f06251ae5dc383b811d0 (patch)
tree	05f3a4d054e0bddc308af479918ce67cd02e8eba /arch/arm/mach-orion5x/include
parent	d7ffa2234c186ce040e79b43639628c1c482b115 (diff)
parent	5b40baee4a39d96d4d6a48a2b2383982912c429b (diff)

diff --git a/arch/arm/mach-orion5x/include/mach/bridge-regs.h b/arch/arm/mach-orion5x/include/mach/bridge-regs.h index 11a3c1e9801f..461fd69a10ae 100644 --- a/arch/arm/mach-orion5x/include/mach/bridge-regs.h +++ b/arch/arm/mach-orion5x/include/mach/bridge-regs.h
@@ -13,27 +13,27 @@
13		13
14	#include <mach/orion5x.h>	14	#include <mach/orion5x.h>
15		15
16	#define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE \| 0x100)	16	#define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100)
17		17
18	#define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE \| 0x104)	18	#define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104)
19		19
20	#define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE \| 0x108)	20	#define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108)
21	#define WDT_RESET_OUT_EN 0x0002	21	#define WDT_RESET_OUT_EN 0x0002
22		22
23	#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE \| 0x10c)	23	#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c)
24		24
25	#define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE \| 0x110)	25	#define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110)
26		26
27	#define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE \| 0x11C)	27	#define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C)
28		28
29	#define WDT_INT_REQ 0x0008	29	#define WDT_INT_REQ 0x0008
30		30
31	#define BRIDGE_INT_TIMER1_CLR (~0x0004)	31	#define BRIDGE_INT_TIMER1_CLR (~0x0004)
32		32
33	#define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE \| 0x200)	33	#define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200)
34		34
35	#define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE \| 0x204)	35	#define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204)
36		36
37	#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE \| 0x300)	37	#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE + 0x300)
38	#define TIMER_PHYS_BASE (ORION5X_BRIDGE_PHYS_BASE \| 0x300)	38	#define TIMER_PHYS_BASE (ORION5X_BRIDGE_PHYS_BASE + 0x300)
39	#endif	39	#endif


diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h index 1b60131b7f60..d265f5484a8e 100644 --- a/arch/arm/mach-orion5x/include/mach/orion5x.h +++ b/arch/arm/mach-orion5x/include/mach/orion5x.h
@@ -37,7 +37,7 @@
37	* fd000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only)	37	* fd000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only)
38	****************************************************************************/	38	****************************************************************************/
39	#define ORION5X_REGS_PHYS_BASE 0xf1000000	39	#define ORION5X_REGS_PHYS_BASE 0xf1000000
40	#define ORION5X_REGS_VIRT_BASE 0xfe000000	40	#define ORION5X_REGS_VIRT_BASE IOMEM(0xfe000000)
41	#define ORION5X_REGS_SIZE SZ_1M	41	#define ORION5X_REGS_SIZE SZ_1M
42		42
43	#define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000	43	#define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000
@@ -53,7 +53,7 @@
53		53
54	/* Relevant only for Orion-1/Orion-NAS */	54	/* Relevant only for Orion-1/Orion-NAS */
55	#define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000	55	#define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000
56	#define ORION5X_PCIE_WA_VIRT_BASE 0xfd000000	56	#define ORION5X_PCIE_WA_VIRT_BASE IOMEM(0xfd000000)
57	#define ORION5X_PCIE_WA_SIZE SZ_16M	57	#define ORION5X_PCIE_WA_SIZE SZ_16M
58		58
59	#define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000	59	#define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000
@@ -66,42 +66,42 @@
66	* Orion Registers Map	66	* Orion Registers Map
67	******************************************************************************/	67	******************************************************************************/
68		68
69	#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE \| 0x00000)	69	#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x00000)
70	#define ORION5X_DDR_WINDOW_CPU_BASE (ORION5X_DDR_VIRT_BASE \| 0x1500)	70	#define ORION5X_DDR_WINDOW_CPU_BASE (ORION5X_DDR_VIRT_BASE + 0x1500)
71	#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE \| 0x10000)	71	#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x10000)
72	#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE \| 0x10000)	72	#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x10000)
73	#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE \| (x))	73	#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE + (x))
74	#define GPIO_VIRT_BASE ORION5X_DEV_BUS_REG(0x0100)	74	#define GPIO_VIRT_BASE ORION5X_DEV_BUS_REG(0x0100)
75	#define SPI_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE \| 0x0600)	75	#define SPI_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x0600)
76	#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE \| 0x1000)	76	#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x1000)
77	#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE \| 0x2000)	77	#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x2000)
78	#define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE \| 0x2000)	78	#define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE + 0x2000)
79	#define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE \| 0x2100)	79	#define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x2100)
80	#define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE \| 0x2100)	80	#define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE + 0x2100)
81		81
82	#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE \| 0x20000)	82	#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x20000)
83	#define ORION5X_BRIDGE_PHYS_BASE (ORION5X_REGS_PHYS_BASE \| 0x20000)	83	#define ORION5X_BRIDGE_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x20000)
84		84
85	#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE \| 0x30000)	85	#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x30000)
86		86
87	#define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE \| 0x40000)	87	#define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x40000)
88		88
89	#define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE \| 0x50000)	89	#define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x50000)
90	#define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE \| 0x50000)	90	#define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x50000)
91		91
92	#define ORION5X_XOR_PHYS_BASE (ORION5X_REGS_PHYS_BASE \| 0x60900)	92	#define ORION5X_XOR_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x60900)
93	#define ORION5X_XOR_VIRT_BASE (ORION5X_REGS_VIRT_BASE \| 0x60900)	93	#define ORION5X_XOR_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x60900)
94		94
95	#define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE \| 0x70000)	95	#define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x70000)
96	#define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE \| 0x70000)	96	#define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x70000)
97		97
98	#define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE \| 0x80000)	98	#define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x80000)
99	#define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE \| 0x80000)	99	#define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x80000)
100		100
101	#define ORION5X_CRYPTO_PHYS_BASE (ORION5X_REGS_PHYS_BASE \| 0x90000)	101	#define ORION5X_CRYPTO_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x90000)
102		102
103	#define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE \| 0xa0000)	103	#define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0xa0000)
104	#define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE \| 0xa0000)	104	#define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0xa0000)
105		105
106	/*******************************************************************************	106	/*******************************************************************************
107	* Device Bus Registers	107	* Device Bus Registers