aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-omap2
diff options
context:
space:
mode:
authorSage Weil <sage@inktank.com>2013-08-15 14:11:45 -0400
committerSage Weil <sage@inktank.com>2013-08-15 14:11:45 -0400
commitee3e542fec6e69bc9fb668698889a37d93950ddf (patch)
treee74ee766a4764769ef1d3d45d266b4dea64101d3 /arch/arm/mach-omap2
parentfe2a801b50c0bb8039d627e5ae1fec249d10ff39 (diff)
parentf1d6e17f540af37bb1891480143669ba7636c4cf (diff)
Merge remote-tracking branch 'linus/master' into testing
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/Kconfig165
-rw-r--r--arch/arm/mach-omap2/Makefile30
-rw-r--r--arch/arm/mach-omap2/am33xx-restart.c3
-rw-r--r--arch/arm/mach-omap2/am33xx.h1
-rw-r--r--arch/arm/mach-omap2/board-4430sdp.c765
-rw-r--r--arch/arm/mach-omap2/board-cm-t35.c3
-rw-r--r--arch/arm/mach-omap2/board-devkit8000.c1
-rw-r--r--arch/arm/mach-omap2/board-flash.c3
-rw-r--r--arch/arm/mach-omap2/board-generic.c39
-rw-r--r--arch/arm/mach-omap2/board-igep0020.c31
-rw-r--r--arch/arm/mach-omap2/board-ldp.c3
-rw-r--r--arch/arm/mach-omap2/board-omap3evm.c4
-rw-r--r--arch/arm/mach-omap2/board-omap3pandora.c1
-rw-r--r--arch/arm/mach-omap2/board-omap4panda.c455
-rw-r--r--arch/arm/mach-omap2/board-overo.c3
-rw-r--r--arch/arm/mach-omap2/board-rx51-peripherals.c1
-rw-r--r--arch/arm/mach-omap2/board-rx51-video.c2
-rw-r--r--arch/arm/mach-omap2/cclock33xx_data.c79
-rw-r--r--arch/arm/mach-omap2/cclock3xxx_data.c11
-rw-r--r--arch/arm/mach-omap2/clockdomain.h1
-rw-r--r--arch/arm/mach-omap2/clockdomains54xx_data.c464
-rw-r--r--arch/arm/mach-omap2/cm-regbits-54xx.h1737
-rw-r--r--arch/arm/mach-omap2/cm1_44xx.h7
-rw-r--r--arch/arm/mach-omap2/cm1_54xx.h213
-rw-r--r--arch/arm/mach-omap2/cm2_44xx.h7
-rw-r--r--arch/arm/mach-omap2/cm2_54xx.h389
-rw-r--r--arch/arm/mach-omap2/cm33xx.h2
-rw-r--r--arch/arm/mach-omap2/cm_44xx_54xx.h36
-rw-r--r--arch/arm/mach-omap2/common.h22
-rw-r--r--arch/arm/mach-omap2/control.c1
-rw-r--r--arch/arm/mach-omap2/control.h12
-rw-r--r--arch/arm/mach-omap2/devices.c161
-rw-r--r--arch/arm/mach-omap2/dma.h61
-rw-r--r--arch/arm/mach-omap2/dss-common.c2
-rw-r--r--arch/arm/mach-omap2/fb.c5
-rw-r--r--arch/arm/mach-omap2/gpmc-nand.c44
-rw-r--r--arch/arm/mach-omap2/gpmc.c84
-rw-r--r--arch/arm/mach-omap2/hsmmc.c103
-rw-r--r--arch/arm/mach-omap2/id.c34
-rw-r--r--arch/arm/mach-omap2/io.c28
-rw-r--r--arch/arm/mach-omap2/mailbox.c430
-rw-r--r--arch/arm/mach-omap2/mux.h3
-rw-r--r--arch/arm/mach-omap2/mux44xx.c1356
-rw-r--r--arch/arm/mach-omap2/mux44xx.h298
-rw-r--r--arch/arm/mach-omap2/omap-headsmp.S10
-rw-r--r--arch/arm/mach-omap2/omap-mpuss-lowpower.c71
-rw-r--r--arch/arm/mach-omap2/omap-smp.c10
-rw-r--r--arch/arm/mach-omap2/omap-wakeupgen.c4
-rw-r--r--arch/arm/mach-omap2/omap2-restart.c2
-rw-r--r--arch/arm/mach-omap2/omap3-restart.c3
-rw-r--r--arch/arm/mach-omap2/omap4-common.c17
-rw-r--r--arch/arm/mach-omap2/omap4-restart.c28
-rw-r--r--arch/arm/mach-omap2/omap_device.c34
-rw-r--r--arch/arm/mach-omap2/omap_device.h10
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c2
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.h51
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2420_data.c14
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c13
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c21
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c6
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_33xx_data.c1080
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c41
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c1549
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_54xx_data.c2151
-rw-r--r--arch/arm/mach-omap2/pm44xx.c58
-rw-r--r--arch/arm/mach-omap2/pmu.c5
-rw-r--r--arch/arm/mach-omap2/powerdomain.c5
-rw-r--r--arch/arm/mach-omap2/powerdomain.h3
-rw-r--r--arch/arm/mach-omap2/powerdomains3xxx_data.c62
-rw-r--r--arch/arm/mach-omap2/powerdomains54xx_data.c331
-rw-r--r--arch/arm/mach-omap2/prcm-common.h11
-rw-r--r--arch/arm/mach-omap2/prcm44xx.h6
-rw-r--r--arch/arm/mach-omap2/prcm_mpu44xx.h14
-rw-r--r--arch/arm/mach-omap2/prcm_mpu54xx.h87
-rw-r--r--arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h36
-rw-r--r--arch/arm/mach-omap2/prm-regbits-54xx.h2701
-rw-r--r--arch/arm/mach-omap2/prm33xx.c7
-rw-r--r--arch/arm/mach-omap2/prm44xx.h33
-rw-r--r--arch/arm/mach-omap2/prm44xx_54xx.h58
-rw-r--r--arch/arm/mach-omap2/prm54xx.h421
-rw-r--r--arch/arm/mach-omap2/scrm54xx.h231
-rw-r--r--arch/arm/mach-omap2/serial.c21
-rw-r--r--arch/arm/mach-omap2/sleep44xx.S6
-rw-r--r--arch/arm/mach-omap2/smartreflex-class3.c8
-rw-r--r--arch/arm/mach-omap2/soc.h26
-rw-r--r--arch/arm/mach-omap2/sram.c3
-rw-r--r--arch/arm/mach-omap2/timer.c6
-rw-r--r--arch/arm/mach-omap2/twl-common.c1
-rw-r--r--arch/arm/mach-omap2/usb-host.c300
-rw-r--r--arch/arm/mach-omap2/usb-musb.c3
-rw-r--r--arch/arm/mach-omap2/voltage.h2
-rw-r--r--arch/arm/mach-omap2/voltagedomains33xx_data.c43
-rw-r--r--arch/arm/mach-omap2/voltagedomains54xx_data.c92
93 files changed, 9922 insertions, 6875 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index f49cd51e162a..3eed0006d189 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -1,61 +1,10 @@
1config ARCH_OMAP 1config ARCH_OMAP
2 bool 2 bool
3 3
4config ARCH_OMAP2PLUS
5 bool "TI OMAP2/3/4/5 SoCs with device tree support" if (ARCH_MULTI_V6 || ARCH_MULTI_V7)
6 select ARCH_HAS_CPUFREQ
7 select ARCH_HAS_HOLES_MEMORYMODEL
8 select ARCH_OMAP
9 select ARCH_REQUIRE_GPIOLIB
10 select CLKDEV_LOOKUP
11 select CLKSRC_MMIO
12 select GENERIC_CLOCKEVENTS
13 select GENERIC_IRQ_CHIP
14 select HAVE_CLK
15 select OMAP_DM_TIMER
16 select PINCTRL
17 select PROC_DEVICETREE if PROC_FS
18 select SOC_BUS
19 select SPARSE_IRQ
20 select USE_OF
21 help
22 Systems based on OMAP2, OMAP3, OMAP4 or OMAP5
23
24
25if ARCH_OMAP2PLUS
26
27menu "TI OMAP2/3/4 Specific Features"
28
29config ARCH_OMAP2PLUS_TYPICAL
30 bool "Typical OMAP configuration"
31 default y
32 select AEABI
33 select HIGHMEM
34 select I2C
35 select I2C_OMAP
36 select MENELAUS if ARCH_OMAP2
37 select NEON if ARCH_OMAP3 || ARCH_OMAP4 || SOC_OMAP5
38 select PM_RUNTIME
39 select REGULATOR
40 select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
41 select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4
42 select VFP
43 help
44 Compile a kernel suitable for booting most boards
45
46config SOC_HAS_OMAP2_SDRC
47 bool "OMAP2 SDRAM Controller support"
48
49config SOC_HAS_REALTIME_COUNTER
50 bool "Real time free running counter"
51 depends on SOC_OMAP5
52 default y
53
54config ARCH_OMAP2 4config ARCH_OMAP2
55 bool "TI OMAP2" 5 bool "TI OMAP2"
56 depends on ARCH_OMAP2PLUS
57 depends on ARCH_MULTI_V6 6 depends on ARCH_MULTI_V6
58 default y 7 select ARCH_OMAP2PLUS
59 select CPU_V6 8 select CPU_V6
60 select MULTI_IRQ_HANDLER 9 select MULTI_IRQ_HANDLER
61 select SOC_HAS_OMAP2_SDRC 10 select SOC_HAS_OMAP2_SDRC
@@ -63,9 +12,8 @@ config ARCH_OMAP2
63 12
64config ARCH_OMAP3 13config ARCH_OMAP3
65 bool "TI OMAP3" 14 bool "TI OMAP3"
66 depends on ARCH_OMAP2PLUS
67 depends on ARCH_MULTI_V7 15 depends on ARCH_MULTI_V7
68 default y 16 select ARCH_OMAP2PLUS
69 select ARCH_HAS_OPP 17 select ARCH_HAS_OPP
70 select ARM_CPU_SUSPEND if PM 18 select ARM_CPU_SUSPEND if PM
71 select CPU_V7 19 select CPU_V7
@@ -79,9 +27,8 @@ config ARCH_OMAP3
79 27
80config ARCH_OMAP4 28config ARCH_OMAP4
81 bool "TI OMAP4" 29 bool "TI OMAP4"
82 default y
83 depends on ARCH_OMAP2PLUS
84 depends on ARCH_MULTI_V7 30 depends on ARCH_MULTI_V7
31 select ARCH_OMAP2PLUS
85 select ARCH_HAS_OPP 32 select ARCH_HAS_OPP
86 select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP 33 select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
87 select ARM_CPU_SUSPEND if PM 34 select ARM_CPU_SUSPEND if PM
@@ -106,12 +53,87 @@ config ARCH_OMAP4
106config SOC_OMAP5 53config SOC_OMAP5
107 bool "TI OMAP5" 54 bool "TI OMAP5"
108 depends on ARCH_MULTI_V7 55 depends on ARCH_MULTI_V7
56 select ARCH_OMAP2PLUS
109 select ARM_CPU_SUSPEND if PM 57 select ARM_CPU_SUSPEND if PM
110 select ARM_GIC 58 select ARM_GIC
111 select CPU_V7 59 select CPU_V7
60 select HAVE_ARM_SCU if SMP
61 select HAVE_ARM_TWD if LOCAL_TIMERS
112 select HAVE_SMP 62 select HAVE_SMP
113 select COMMON_CLK 63 select COMMON_CLK
114 select HAVE_ARM_ARCH_TIMER 64 select HAVE_ARM_ARCH_TIMER
65 select ARM_ERRATA_798181 if SMP
66
67config SOC_AM33XX
68 bool "AM33XX support"
69 depends on ARCH_MULTI_V7
70 select ARCH_OMAP2PLUS
71 select ARM_CPU_SUSPEND if PM
72 select CPU_V7
73 select MULTI_IRQ_HANDLER
74 select COMMON_CLK
75
76config SOC_AM43XX
77 bool "TI AM43x"
78 depends on ARCH_MULTI_V7
79 select CPU_V7
80 select ARCH_OMAP2PLUS
81 select MULTI_IRQ_HANDLER
82 select ARM_GIC
83 select COMMON_CLK
84 select MACH_OMAP_GENERIC
85
86config ARCH_OMAP2PLUS
87 bool
88 select ARCH_HAS_BANDGAP
89 select ARCH_HAS_CPUFREQ
90 select ARCH_HAS_HOLES_MEMORYMODEL
91 select ARCH_OMAP
92 select ARCH_REQUIRE_GPIOLIB
93 select CLKDEV_LOOKUP
94 select CLKSRC_MMIO
95 select GENERIC_CLOCKEVENTS
96 select GENERIC_IRQ_CHIP
97 select HAVE_CLK
98 select OMAP_DM_TIMER
99 select PINCTRL
100 select PROC_DEVICETREE if PROC_FS
101 select SOC_BUS
102 select SPARSE_IRQ
103 select TI_PRIV_EDMA
104 select USE_OF
105 help
106 Systems based on OMAP2, OMAP3, OMAP4 or OMAP5
107
108
109if ARCH_OMAP2PLUS
110
111menu "TI OMAP2/3/4 Specific Features"
112
113config ARCH_OMAP2PLUS_TYPICAL
114 bool "Typical OMAP configuration"
115 default y
116 select AEABI
117 select HIGHMEM
118 select I2C
119 select I2C_OMAP
120 select MENELAUS if ARCH_OMAP2
121 select NEON if ARCH_OMAP3 || ARCH_OMAP4 || SOC_OMAP5
122 select PM_RUNTIME
123 select REGULATOR
124 select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
125 select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4
126 select VFP
127 help
128 Compile a kernel suitable for booting most boards
129
130config SOC_HAS_OMAP2_SDRC
131 bool "OMAP2 SDRAM Controller support"
132
133config SOC_HAS_REALTIME_COUNTER
134 bool "Real time free running counter"
135 depends on SOC_OMAP5
136 default y
115 137
116comment "OMAP Core Type" 138comment "OMAP Core Type"
117 depends on ARCH_OMAP2 139 depends on ARCH_OMAP2
@@ -140,15 +162,6 @@ config SOC_TI81XX
140 depends on ARCH_OMAP3 162 depends on ARCH_OMAP3
141 default y 163 default y
142 164
143config SOC_AM33XX
144 bool "AM33XX support"
145 depends on ARCH_MULTI_V7
146 default y
147 select ARM_CPU_SUSPEND if PM
148 select CPU_V7
149 select MULTI_IRQ_HANDLER
150 select COMMON_CLK
151
152config OMAP_PACKAGE_ZAF 165config OMAP_PACKAGE_ZAF
153 bool 166 bool
154 167
@@ -167,12 +180,6 @@ config OMAP_PACKAGE_CUS
167config OMAP_PACKAGE_CBP 180config OMAP_PACKAGE_CBP
168 bool 181 bool
169 182
170config OMAP_PACKAGE_CBL
171 bool
172
173config OMAP_PACKAGE_CBS
174 bool
175
176comment "OMAP Board Type" 183comment "OMAP Board Type"
177 depends on ARCH_OMAP2PLUS 184 depends on ARCH_OMAP2PLUS
178 185
@@ -378,22 +385,6 @@ config MACH_TI8148EVM
378 depends on SOC_TI81XX 385 depends on SOC_TI81XX
379 default y 386 default y
380 387
381config MACH_OMAP_4430SDP
382 bool "OMAP 4430 SDP board"
383 default y
384 depends on ARCH_OMAP4
385 select OMAP_PACKAGE_CBL
386 select OMAP_PACKAGE_CBS
387 select REGULATOR_FIXED_VOLTAGE if REGULATOR
388
389config MACH_OMAP4_PANDA
390 bool "OMAP4 Panda Board"
391 default y
392 depends on ARCH_OMAP4
393 select OMAP_PACKAGE_CBL
394 select OMAP_PACKAGE_CBS
395 select REGULATOR_FIXED_VOLTAGE if REGULATOR
396
397config OMAP3_EMU 388config OMAP3_EMU
398 bool "OMAP3 debugging peripherals" 389 bool "OMAP3 debugging peripherals"
399 depends on ARCH_OMAP3 390 depends on ARCH_OMAP3
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 55a9d6777683..d4f671547c37 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
22obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common) 22obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
23obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common) 23obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common)
24obj-$(CONFIG_SOC_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common) 24obj-$(CONFIG_SOC_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common)
25obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common)
25 26
26ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),) 27ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
27obj-y += mcbsp.o 28obj-y += mcbsp.o
@@ -34,10 +35,10 @@ obj-$(CONFIG_SOC_HAS_OMAP2_SDRC) += sdrc.o
34 35
35smp-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o 36smp-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o
36smp-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o 37smp-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o
37omap-4-5-common = omap4-common.o omap-wakeupgen.o \ 38omap-4-5-common = omap4-common.o omap-wakeupgen.o
38 sleep44xx.o 39obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common) $(smp-y) sleep44xx.o
39obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common) $(smp-y) 40obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common) $(smp-y) sleep44xx.o
40obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common) $(smp-y) 41obj-$(CONFIG_SOC_AM43XX) += $(omap-4-5-common)
41 42
42plus_sec := $(call as-instr,.arch_extension sec,+sec) 43plus_sec := $(call as-instr,.arch_extension sec,+sec)
43AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec) 44AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec)
@@ -58,12 +59,13 @@ obj-$(CONFIG_SOC_OMAP2420) += omap2-restart.o
58obj-$(CONFIG_SOC_OMAP2430) += omap2-restart.o 59obj-$(CONFIG_SOC_OMAP2430) += omap2-restart.o
59obj-$(CONFIG_SOC_AM33XX) += am33xx-restart.o 60obj-$(CONFIG_SOC_AM33XX) += am33xx-restart.o
60obj-$(CONFIG_ARCH_OMAP3) += omap3-restart.o 61obj-$(CONFIG_ARCH_OMAP3) += omap3-restart.o
62obj-$(CONFIG_ARCH_OMAP4) += omap4-restart.o
63obj-$(CONFIG_SOC_OMAP5) += omap4-restart.o
61 64
62# Pin multiplexing 65# Pin multiplexing
63obj-$(CONFIG_SOC_OMAP2420) += mux2420.o 66obj-$(CONFIG_SOC_OMAP2420) += mux2420.o
64obj-$(CONFIG_SOC_OMAP2430) += mux2430.o 67obj-$(CONFIG_SOC_OMAP2430) += mux2430.o
65obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o 68obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o
66obj-$(CONFIG_ARCH_OMAP4) += mux44xx.o
67 69
68# SMS/SDRC 70# SMS/SDRC
69obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o 71obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o
@@ -93,10 +95,6 @@ obj-$(CONFIG_POWER_AVS_OMAP_CLASS3) += smartreflex-class3.o
93AFLAGS_sleep24xx.o :=-Wa,-march=armv6 95AFLAGS_sleep24xx.o :=-Wa,-march=armv6
94AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a$(plus_sec) 96AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a$(plus_sec)
95 97
96ifeq ($(CONFIG_PM_VERBOSE),y)
97CFLAGS_pm_bus.o += -DDEBUG
98endif
99
100endif 98endif
101 99
102ifeq ($(CONFIG_CPU_IDLE),y) 100ifeq ($(CONFIG_CPU_IDLE),y)
@@ -110,6 +108,7 @@ obj-$(CONFIG_ARCH_OMAP2) += prm2xxx_3xxx.o prm2xxx.o cm2xxx.o
110obj-$(CONFIG_ARCH_OMAP3) += prm2xxx_3xxx.o prm3xxx.o cm3xxx.o 108obj-$(CONFIG_ARCH_OMAP3) += prm2xxx_3xxx.o prm3xxx.o cm3xxx.o
111obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o 109obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o
112obj-$(CONFIG_SOC_AM33XX) += prm33xx.o cm33xx.o 110obj-$(CONFIG_SOC_AM33XX) += prm33xx.o cm33xx.o
111obj-$(CONFIG_SOC_AM43XX) += prm33xx.o cm33xx.o
113omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \ 112omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \
114 prcm_mpu44xx.o prminst44xx.o \ 113 prcm_mpu44xx.o prminst44xx.o \
115 vc44xx_data.o vp44xx_data.o 114 vc44xx_data.o vp44xx_data.o
@@ -125,8 +124,9 @@ obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o
125obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common) 124obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common)
126obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o 125obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o
127obj-$(CONFIG_SOC_AM33XX) += $(voltagedomain-common) 126obj-$(CONFIG_SOC_AM33XX) += $(voltagedomain-common)
128obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o 127obj-$(CONFIG_SOC_AM43XX) += $(voltagedomain-common)
129obj-$(CONFIG_SOC_OMAP5) += $(voltagedomain-common) 128obj-$(CONFIG_SOC_OMAP5) += $(voltagedomain-common)
129obj-$(CONFIG_SOC_OMAP5) += voltagedomains54xx_data.o
130 130
131# OMAP powerdomain framework 131# OMAP powerdomain framework
132powerdomain-common += powerdomain.o powerdomain-common.o 132powerdomain-common += powerdomain.o powerdomain-common.o
@@ -140,7 +140,9 @@ obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common)
140obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o 140obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o
141obj-$(CONFIG_SOC_AM33XX) += $(powerdomain-common) 141obj-$(CONFIG_SOC_AM33XX) += $(powerdomain-common)
142obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o 142obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o
143obj-$(CONFIG_SOC_AM43XX) += $(powerdomain-common)
143obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common) 144obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common)
145obj-$(CONFIG_SOC_OMAP5) += powerdomains54xx_data.o
144 146
145# PRCM clockdomain control 147# PRCM clockdomain control
146clockdomain-common += clockdomain.o 148clockdomain-common += clockdomain.o
@@ -155,7 +157,9 @@ obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common)
155obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o 157obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o
156obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common) 158obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common)
157obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o 159obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o
160obj-$(CONFIG_SOC_AM43XX) += $(clockdomain-common)
158obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common) 161obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common)
162obj-$(CONFIG_SOC_OMAP5) += clockdomains54xx_data.o
159 163
160# Clock framework 164# Clock framework
161obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o 165obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
@@ -198,14 +202,12 @@ obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_interconnect_data.o
198obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o 202obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
199obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o 203obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o
200obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o 204obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
205obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o
201 206
202# EMU peripherals 207# EMU peripherals
203obj-$(CONFIG_OMAP3_EMU) += emu.o 208obj-$(CONFIG_OMAP3_EMU) += emu.o
204obj-$(CONFIG_HW_PERF_EVENTS) += pmu.o 209obj-$(CONFIG_HW_PERF_EVENTS) += pmu.o
205 210
206obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o
207mailbox_mach-objs := mailbox.o
208
209iommu-$(CONFIG_OMAP_IOMMU) := omap-iommu.o 211iommu-$(CONFIG_OMAP_IOMMU) := omap-iommu.o
210obj-y += $(iommu-m) $(iommu-y) 212obj-y += $(iommu-m) $(iommu-y)
211 213
@@ -251,8 +253,6 @@ obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o
251obj-$(CONFIG_MACH_CM_T3517) += board-cm-t3517.o 253obj-$(CONFIG_MACH_CM_T3517) += board-cm-t3517.o
252obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o 254obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o
253obj-$(CONFIG_MACH_TOUCHBOOK) += board-omap3touchbook.o 255obj-$(CONFIG_MACH_TOUCHBOOK) += board-omap3touchbook.o
254obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o
255obj-$(CONFIG_MACH_OMAP4_PANDA) += board-omap4panda.o
256 256
257obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o 257obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o
258 258
diff --git a/arch/arm/mach-omap2/am33xx-restart.c b/arch/arm/mach-omap2/am33xx-restart.c
index 88e4fa8af031..1eae96212315 100644
--- a/arch/arm/mach-omap2/am33xx-restart.c
+++ b/arch/arm/mach-omap2/am33xx-restart.c
@@ -6,6 +6,7 @@
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 */ 7 */
8#include <linux/kernel.h> 8#include <linux/kernel.h>
9#include <linux/reboot.h>
9 10
10#include "common.h" 11#include "common.h"
11#include "prm-regbits-33xx.h" 12#include "prm-regbits-33xx.h"
@@ -19,7 +20,7 @@
19 * Resets the SoC. For @cmd, see the 'reboot' syscall in 20 * Resets the SoC. For @cmd, see the 'reboot' syscall in
20 * kernel/sys.c. No return value. 21 * kernel/sys.c. No return value.
21 */ 22 */
22void am33xx_restart(char mode, const char *cmd) 23void am33xx_restart(enum reboot_mode mode, const char *cmd)
23{ 24{
24 /* TODO: Handle mode and cmd if necessary */ 25 /* TODO: Handle mode and cmd if necessary */
25 26
diff --git a/arch/arm/mach-omap2/am33xx.h b/arch/arm/mach-omap2/am33xx.h
index 43296c1af9ee..5eef093e6738 100644
--- a/arch/arm/mach-omap2/am33xx.h
+++ b/arch/arm/mach-omap2/am33xx.h
@@ -21,6 +21,7 @@
21#define AM33XX_SCM_BASE 0x44E10000 21#define AM33XX_SCM_BASE 0x44E10000
22#define AM33XX_CTRL_BASE AM33XX_SCM_BASE 22#define AM33XX_CTRL_BASE AM33XX_SCM_BASE
23#define AM33XX_PRCM_BASE 0x44E00000 23#define AM33XX_PRCM_BASE 0x44E00000
24#define AM43XX_PRCM_BASE 0x44DF0000
24#define AM33XX_TAP_BASE (AM33XX_CTRL_BASE + 0x3FC) 25#define AM33XX_TAP_BASE (AM33XX_CTRL_BASE + 0x3FC)
25 26
26#endif /* __ASM_ARCH_AM33XX_H */ 27#endif /* __ASM_ARCH_AM33XX_H */
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
deleted file mode 100644
index 56a9a4f855c7..000000000000
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ /dev/null
@@ -1,765 +0,0 @@
1/*
2 * Board support file for OMAP4430 SDP.
3 *
4 * Copyright (C) 2009 Texas Instruments
5 *
6 * Author: Santosh Shilimkar <santosh.shilimkar@ti.com>
7 *
8 * Based on mach-omap2/board-3430sdp.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/platform_device.h>
18#include <linux/io.h>
19#include <linux/gpio.h>
20#include <linux/usb/otg.h>
21#include <linux/spi/spi.h>
22#include <linux/i2c/twl.h>
23#include <linux/mfd/twl6040.h>
24#include <linux/gpio_keys.h>
25#include <linux/regulator/machine.h>
26#include <linux/regulator/fixed.h>
27#include <linux/pwm.h>
28#include <linux/leds.h>
29#include <linux/leds_pwm.h>
30#include <linux/pwm_backlight.h>
31#include <linux/irqchip/arm-gic.h>
32#include <linux/platform_data/omap4-keypad.h>
33#include <linux/usb/musb.h>
34#include <linux/usb/phy.h>
35
36#include <asm/mach-types.h>
37#include <asm/mach/arch.h>
38#include <asm/mach/map.h>
39
40#include "common.h"
41#include "omap4-keypad.h"
42#include <linux/wl12xx.h>
43#include <linux/platform_data/omap-abe-twl6040.h>
44
45#include "soc.h"
46#include "mux.h"
47#include "mmc.h"
48#include "hsmmc.h"
49#include "control.h"
50#include "common-board-devices.h"
51#include "dss-common.h"
52
53#define ETH_KS8851_IRQ 34
54#define ETH_KS8851_POWER_ON 48
55#define ETH_KS8851_QUART 138
56#define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184
57#define OMAP4_SFH7741_ENABLE_GPIO 188
58
59#define GPIO_WIFI_PMENA 54
60#define GPIO_WIFI_IRQ 53
61
62static const int sdp4430_keymap[] = {
63 KEY(0, 0, KEY_E),
64 KEY(0, 1, KEY_R),
65 KEY(0, 2, KEY_T),
66 KEY(0, 3, KEY_HOME),
67 KEY(0, 4, KEY_F5),
68 KEY(0, 5, KEY_UNKNOWN),
69 KEY(0, 6, KEY_I),
70 KEY(0, 7, KEY_LEFTSHIFT),
71
72 KEY(1, 0, KEY_D),
73 KEY(1, 1, KEY_F),
74 KEY(1, 2, KEY_G),
75 KEY(1, 3, KEY_SEND),
76 KEY(1, 4, KEY_F6),
77 KEY(1, 5, KEY_UNKNOWN),
78 KEY(1, 6, KEY_K),
79 KEY(1, 7, KEY_ENTER),
80
81 KEY(2, 0, KEY_X),
82 KEY(2, 1, KEY_C),
83 KEY(2, 2, KEY_V),
84 KEY(2, 3, KEY_END),
85 KEY(2, 4, KEY_F7),
86 KEY(2, 5, KEY_UNKNOWN),
87 KEY(2, 6, KEY_DOT),
88 KEY(2, 7, KEY_CAPSLOCK),
89
90 KEY(3, 0, KEY_Z),
91 KEY(3, 1, KEY_KPPLUS),
92 KEY(3, 2, KEY_B),
93 KEY(3, 3, KEY_F1),
94 KEY(3, 4, KEY_F8),
95 KEY(3, 5, KEY_UNKNOWN),
96 KEY(3, 6, KEY_O),
97 KEY(3, 7, KEY_SPACE),
98
99 KEY(4, 0, KEY_W),
100 KEY(4, 1, KEY_Y),
101 KEY(4, 2, KEY_U),
102 KEY(4, 3, KEY_F2),
103 KEY(4, 4, KEY_VOLUMEUP),
104 KEY(4, 5, KEY_UNKNOWN),
105 KEY(4, 6, KEY_L),
106 KEY(4, 7, KEY_LEFT),
107
108 KEY(5, 0, KEY_S),
109 KEY(5, 1, KEY_H),
110 KEY(5, 2, KEY_J),
111 KEY(5, 3, KEY_F3),
112 KEY(5, 4, KEY_F9),
113 KEY(5, 5, KEY_VOLUMEDOWN),
114 KEY(5, 6, KEY_M),
115 KEY(5, 7, KEY_RIGHT),
116
117 KEY(6, 0, KEY_Q),
118 KEY(6, 1, KEY_A),
119 KEY(6, 2, KEY_N),
120 KEY(6, 3, KEY_BACK),
121 KEY(6, 4, KEY_BACKSPACE),
122 KEY(6, 5, KEY_UNKNOWN),
123 KEY(6, 6, KEY_P),
124 KEY(6, 7, KEY_UP),
125
126 KEY(7, 0, KEY_PROG1),
127 KEY(7, 1, KEY_PROG2),
128 KEY(7, 2, KEY_PROG3),
129 KEY(7, 3, KEY_PROG4),
130 KEY(7, 4, KEY_F4),
131 KEY(7, 5, KEY_UNKNOWN),
132 KEY(7, 6, KEY_OK),
133 KEY(7, 7, KEY_DOWN),
134};
135static struct omap_device_pad keypad_pads[] = {
136 { .name = "kpd_col1.kpd_col1",
137 .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
138 },
139 { .name = "kpd_col1.kpd_col1",
140 .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
141 },
142 { .name = "kpd_col2.kpd_col2",
143 .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
144 },
145 { .name = "kpd_col3.kpd_col3",
146 .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
147 },
148 { .name = "kpd_col4.kpd_col4",
149 .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
150 },
151 { .name = "kpd_col5.kpd_col5",
152 .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
153 },
154 { .name = "gpmc_a23.kpd_col7",
155 .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
156 },
157 { .name = "gpmc_a22.kpd_col6",
158 .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
159 },
160 { .name = "kpd_row0.kpd_row0",
161 .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
162 OMAP_MUX_MODE1 | OMAP_INPUT_EN,
163 },
164 { .name = "kpd_row1.kpd_row1",
165 .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
166 OMAP_MUX_MODE1 | OMAP_INPUT_EN,
167 },
168 { .name = "kpd_row2.kpd_row2",
169 .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
170 OMAP_MUX_MODE1 | OMAP_INPUT_EN,
171 },
172 { .name = "kpd_row3.kpd_row3",
173 .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
174 OMAP_MUX_MODE1 | OMAP_INPUT_EN,
175 },
176 { .name = "kpd_row4.kpd_row4",
177 .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
178 OMAP_MUX_MODE1 | OMAP_INPUT_EN,
179 },
180 { .name = "kpd_row5.kpd_row5",
181 .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
182 OMAP_MUX_MODE1 | OMAP_INPUT_EN,
183 },
184 { .name = "gpmc_a18.kpd_row6",
185 .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
186 OMAP_MUX_MODE1 | OMAP_INPUT_EN,
187 },
188 { .name = "gpmc_a19.kpd_row7",
189 .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
190 OMAP_MUX_MODE1 | OMAP_INPUT_EN,
191 },
192};
193
194static struct matrix_keymap_data sdp4430_keymap_data = {
195 .keymap = sdp4430_keymap,
196 .keymap_size = ARRAY_SIZE(sdp4430_keymap),
197};
198
199static struct omap4_keypad_platform_data sdp4430_keypad_data = {
200 .keymap_data = &sdp4430_keymap_data,
201 .rows = 8,
202 .cols = 8,
203};
204
205static struct omap_board_data keypad_data = {
206 .id = 1,
207 .pads = keypad_pads,
208 .pads_cnt = ARRAY_SIZE(keypad_pads),
209};
210
211static struct gpio_led sdp4430_gpio_leds[] = {
212 {
213 .name = "omap4:green:debug0",
214 .gpio = 61,
215 },
216 {
217 .name = "omap4:green:debug1",
218 .gpio = 30,
219 },
220 {
221 .name = "omap4:green:debug2",
222 .gpio = 7,
223 },
224 {
225 .name = "omap4:green:debug3",
226 .gpio = 8,
227 },
228 {
229 .name = "omap4:green:debug4",
230 .gpio = 50,
231 },
232 {
233 .name = "omap4:blue:user",
234 .gpio = 169,
235 },
236 {
237 .name = "omap4:red:user",
238 .gpio = 170,
239 },
240 {
241 .name = "omap4:green:user",
242 .gpio = 139,
243 },
244
245};
246
247static struct gpio_keys_button sdp4430_gpio_keys[] = {
248 {
249 .desc = "Proximity Sensor",
250 .type = EV_SW,
251 .code = SW_FRONT_PROXIMITY,
252 .gpio = OMAP4_SFH7741_SENSOR_OUTPUT_GPIO,
253 .active_low = 0,
254 }
255};
256
257static struct gpio_led_platform_data sdp4430_led_data = {
258 .leds = sdp4430_gpio_leds,
259 .num_leds = ARRAY_SIZE(sdp4430_gpio_leds),
260};
261
262static struct pwm_lookup sdp4430_pwm_lookup[] = {
263 PWM_LOOKUP("twl-pwm", 0, "leds_pwm", "omap4::keypad"),
264 PWM_LOOKUP("twl-pwm", 1, "pwm-backlight", NULL),
265 PWM_LOOKUP("twl-pwmled", 0, "leds_pwm", "omap4:green:chrg"),
266};
267
268static struct led_pwm sdp4430_pwm_leds[] = {
269 {
270 .name = "omap4::keypad",
271 .max_brightness = 127,
272 .pwm_period_ns = 7812500,
273 },
274 {
275 .name = "omap4:green:chrg",
276 .max_brightness = 255,
277 .pwm_period_ns = 7812500,
278 },
279};
280
281static struct led_pwm_platform_data sdp4430_pwm_data = {
282 .num_leds = ARRAY_SIZE(sdp4430_pwm_leds),
283 .leds = sdp4430_pwm_leds,
284};
285
286static struct platform_device sdp4430_leds_pwm = {
287 .name = "leds_pwm",
288 .id = -1,
289 .dev = {
290 .platform_data = &sdp4430_pwm_data,
291 },
292};
293
294/* Dummy regulator for pwm-backlight driver */
295static struct regulator_consumer_supply backlight_supply =
296 REGULATOR_SUPPLY("enable", "pwm-backlight");
297
298static struct platform_pwm_backlight_data sdp4430_backlight_data = {
299 .max_brightness = 127,
300 .dft_brightness = 127,
301 .pwm_period_ns = 7812500,
302};
303
304static struct platform_device sdp4430_backlight_pwm = {
305 .name = "pwm-backlight",
306 .id = -1,
307 .dev = {
308 .platform_data = &sdp4430_backlight_data,
309 },
310};
311
312static int omap_prox_activate(struct device *dev)
313{
314 gpio_set_value(OMAP4_SFH7741_ENABLE_GPIO , 1);
315 return 0;
316}
317
318static void omap_prox_deactivate(struct device *dev)
319{
320 gpio_set_value(OMAP4_SFH7741_ENABLE_GPIO , 0);
321}
322
323static struct gpio_keys_platform_data sdp4430_gpio_keys_data = {
324 .buttons = sdp4430_gpio_keys,
325 .nbuttons = ARRAY_SIZE(sdp4430_gpio_keys),
326 .enable = omap_prox_activate,
327 .disable = omap_prox_deactivate,
328};
329
330static struct platform_device sdp4430_gpio_keys_device = {
331 .name = "gpio-keys",
332 .id = -1,
333 .dev = {
334 .platform_data = &sdp4430_gpio_keys_data,
335 },
336};
337
338static struct platform_device sdp4430_leds_gpio = {
339 .name = "leds-gpio",
340 .id = -1,
341 .dev = {
342 .platform_data = &sdp4430_led_data,
343 },
344};
345static struct spi_board_info sdp4430_spi_board_info[] __initdata = {
346 {
347 .modalias = "ks8851",
348 .bus_num = 1,
349 .chip_select = 0,
350 .max_speed_hz = 24000000,
351 /*
352 * .irq is set to gpio_to_irq(ETH_KS8851_IRQ)
353 * in omap_4430sdp_init
354 */
355 },
356};
357
358static struct gpio sdp4430_eth_gpios[] __initdata = {
359 { ETH_KS8851_POWER_ON, GPIOF_OUT_INIT_HIGH, "eth_power" },
360 { ETH_KS8851_QUART, GPIOF_OUT_INIT_HIGH, "quart" },
361 { ETH_KS8851_IRQ, GPIOF_IN, "eth_irq" },
362};
363
364static int __init omap_ethernet_init(void)
365{
366 int status;
367
368 /* Request of GPIO lines */
369 status = gpio_request_array(sdp4430_eth_gpios,
370 ARRAY_SIZE(sdp4430_eth_gpios));
371 if (status)
372 pr_err("Cannot request ETH GPIOs\n");
373
374 return status;
375}
376
377static struct regulator_consumer_supply sdp4430_vbat_supply[] = {
378 REGULATOR_SUPPLY("vddvibl", "twl6040-vibra"),
379 REGULATOR_SUPPLY("vddvibr", "twl6040-vibra"),
380};
381
382static struct regulator_init_data sdp4430_vbat_data = {
383 .constraints = {
384 .always_on = 1,
385 },
386 .num_consumer_supplies = ARRAY_SIZE(sdp4430_vbat_supply),
387 .consumer_supplies = sdp4430_vbat_supply,
388};
389
390static struct fixed_voltage_config sdp4430_vbat_pdata = {
391 .supply_name = "VBAT",
392 .microvolts = 3750000,
393 .init_data = &sdp4430_vbat_data,
394 .gpio = -EINVAL,
395};
396
397static struct platform_device sdp4430_vbat = {
398 .name = "reg-fixed-voltage",
399 .id = -1,
400 .dev = {
401 .platform_data = &sdp4430_vbat_pdata,
402 },
403};
404
405static struct platform_device sdp4430_dmic_codec = {
406 .name = "dmic-codec",
407 .id = -1,
408};
409
410static struct platform_device sdp4430_hdmi_audio_codec = {
411 .name = "hdmi-audio-codec",
412 .id = -1,
413};
414
415static struct omap_abe_twl6040_data sdp4430_abe_audio_data = {
416 .card_name = "SDP4430",
417 .has_hs = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
418 .has_hf = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
419 .has_ep = 1,
420 .has_aux = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
421 .has_vibra = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
422
423 .has_dmic = 1,
424 .has_hsmic = 1,
425 .has_mainmic = 1,
426 .has_submic = 1,
427 .has_afm = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
428
429 .jack_detection = 1,
430 /* MCLK input is 38.4MHz */
431 .mclk_freq = 38400000,
432};
433
434static struct platform_device sdp4430_abe_audio = {
435 .name = "omap-abe-twl6040",
436 .id = -1,
437 .dev = {
438 .platform_data = &sdp4430_abe_audio_data,
439 },
440};
441
442static struct platform_device *sdp4430_devices[] __initdata = {
443 &sdp4430_gpio_keys_device,
444 &sdp4430_leds_gpio,
445 &sdp4430_leds_pwm,
446 &sdp4430_backlight_pwm,
447 &sdp4430_vbat,
448 &sdp4430_dmic_codec,
449 &sdp4430_abe_audio,
450 &sdp4430_hdmi_audio_codec,
451};
452
453static struct omap_musb_board_data musb_board_data = {
454 .interface_type = MUSB_INTERFACE_UTMI,
455 .mode = MUSB_OTG,
456 .power = 100,
457};
458
459static struct omap2_hsmmc_info mmc[] = {
460 {
461 .mmc = 2,
462 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
463 .gpio_cd = -EINVAL,
464 .gpio_wp = -EINVAL,
465 .nonremovable = true,
466 .ocr_mask = MMC_VDD_29_30,
467 .no_off_init = true,
468 },
469 {
470 .mmc = 1,
471 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
472 .gpio_cd = -EINVAL,
473 .gpio_wp = -EINVAL,
474 },
475 {
476 .mmc = 5,
477 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
478 .pm_caps = MMC_PM_KEEP_POWER,
479 .gpio_cd = -EINVAL,
480 .gpio_wp = -EINVAL,
481 .ocr_mask = MMC_VDD_165_195,
482 .nonremovable = true,
483 },
484 {} /* Terminator */
485};
486
487static struct regulator_consumer_supply sdp4430_vaux_supply[] = {
488 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
489};
490
491static struct regulator_consumer_supply omap4_sdp4430_vmmc5_supply = {
492 .supply = "vmmc",
493 .dev_name = "omap_hsmmc.4",
494};
495
496static struct regulator_init_data sdp4430_vmmc5 = {
497 .constraints = {
498 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
499 },
500 .num_consumer_supplies = 1,
501 .consumer_supplies = &omap4_sdp4430_vmmc5_supply,
502};
503
504static struct fixed_voltage_config sdp4430_vwlan = {
505 .supply_name = "vwl1271",
506 .microvolts = 1800000, /* 1.8V */
507 .gpio = GPIO_WIFI_PMENA,
508 .startup_delay = 70000, /* 70msec */
509 .enable_high = 1,
510 .enabled_at_boot = 0,
511 .init_data = &sdp4430_vmmc5,
512};
513
514static struct platform_device omap_vwlan_device = {
515 .name = "reg-fixed-voltage",
516 .id = 1,
517 .dev = {
518 .platform_data = &sdp4430_vwlan,
519 },
520};
521
522static struct regulator_init_data sdp4430_vaux1 = {
523 .constraints = {
524 .min_uV = 1000000,
525 .max_uV = 3000000,
526 .apply_uV = true,
527 .valid_modes_mask = REGULATOR_MODE_NORMAL
528 | REGULATOR_MODE_STANDBY,
529 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
530 | REGULATOR_CHANGE_MODE
531 | REGULATOR_CHANGE_STATUS,
532 },
533 .num_consumer_supplies = ARRAY_SIZE(sdp4430_vaux_supply),
534 .consumer_supplies = sdp4430_vaux_supply,
535};
536
537static struct regulator_init_data sdp4430_vusim = {
538 .constraints = {
539 .min_uV = 1200000,
540 .max_uV = 2900000,
541 .apply_uV = true,
542 .valid_modes_mask = REGULATOR_MODE_NORMAL
543 | REGULATOR_MODE_STANDBY,
544 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
545 | REGULATOR_CHANGE_MODE
546 | REGULATOR_CHANGE_STATUS,
547 },
548};
549
550static struct twl6040_codec_data twl6040_codec = {
551 /* single-step ramp for headset and handsfree */
552 .hs_left_step = 0x0f,
553 .hs_right_step = 0x0f,
554 .hf_left_step = 0x1d,
555 .hf_right_step = 0x1d,
556};
557
558static struct twl6040_vibra_data twl6040_vibra = {
559 .vibldrv_res = 8,
560 .vibrdrv_res = 3,
561 .viblmotor_res = 10,
562 .vibrmotor_res = 10,
563 .vddvibl_uV = 0, /* fixed volt supply - VBAT */
564 .vddvibr_uV = 0, /* fixed volt supply - VBAT */
565};
566
567static struct twl6040_platform_data twl6040_data = {
568 .codec = &twl6040_codec,
569 .vibra = &twl6040_vibra,
570 .audpwron_gpio = 127,
571};
572
573static struct i2c_board_info __initdata sdp4430_i2c_1_boardinfo[] = {
574 {
575 I2C_BOARD_INFO("twl6040", 0x4b),
576 .irq = 119 + OMAP44XX_IRQ_GIC_START,
577 .platform_data = &twl6040_data,
578 },
579};
580
581static struct twl4030_platform_data sdp4430_twldata = {
582 /* Regulators */
583 .vusim = &sdp4430_vusim,
584 .vaux1 = &sdp4430_vaux1,
585};
586
587static struct i2c_board_info __initdata sdp4430_i2c_3_boardinfo[] = {
588 {
589 I2C_BOARD_INFO("tmp105", 0x48),
590 },
591 {
592 I2C_BOARD_INFO("bh1780", 0x29),
593 },
594};
595static struct i2c_board_info __initdata sdp4430_i2c_4_boardinfo[] = {
596 {
597 I2C_BOARD_INFO("hmc5843", 0x1e),
598 },
599};
600static int __init omap4_i2c_init(void)
601{
602 omap4_pmic_get_config(&sdp4430_twldata, TWL_COMMON_PDATA_USB,
603 TWL_COMMON_REGULATOR_VDAC |
604 TWL_COMMON_REGULATOR_VAUX2 |
605 TWL_COMMON_REGULATOR_VAUX3 |
606 TWL_COMMON_REGULATOR_VMMC |
607 TWL_COMMON_REGULATOR_VPP |
608 TWL_COMMON_REGULATOR_VANA |
609 TWL_COMMON_REGULATOR_VCXIO |
610 TWL_COMMON_REGULATOR_VUSB |
611 TWL_COMMON_REGULATOR_CLK32KG |
612 TWL_COMMON_REGULATOR_V1V8 |
613 TWL_COMMON_REGULATOR_V2V1);
614 omap4_pmic_init("twl6030", &sdp4430_twldata, sdp4430_i2c_1_boardinfo,
615 ARRAY_SIZE(sdp4430_i2c_1_boardinfo));
616 omap_register_i2c_bus(2, 400, NULL, 0);
617 omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo,
618 ARRAY_SIZE(sdp4430_i2c_3_boardinfo));
619 omap_register_i2c_bus(4, 400, sdp4430_i2c_4_boardinfo,
620 ARRAY_SIZE(sdp4430_i2c_4_boardinfo));
621 return 0;
622}
623
624static void __init omap_sfh7741prox_init(void)
625{
626 int error;
627
628 error = gpio_request_one(OMAP4_SFH7741_ENABLE_GPIO,
629 GPIOF_OUT_INIT_LOW, "sfh7741");
630 if (error < 0)
631 pr_err("%s:failed to request GPIO %d, error %d\n",
632 __func__, OMAP4_SFH7741_ENABLE_GPIO, error);
633}
634
635#ifdef CONFIG_OMAP_MUX
636static struct omap_board_mux board_mux[] __initdata = {
637 OMAP4_MUX(USBB2_ULPITLL_CLK, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
638 /* NIRQ2 for twl6040 */
639 OMAP4_MUX(SYS_NIRQ2, OMAP_MUX_MODE0 |
640 OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE),
641 /* GPIO_127 for twl6040 */
642 OMAP4_MUX(HDQ_SIO, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT),
643 /* McPDM */
644 OMAP4_MUX(ABE_PDM_UL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
645 OMAP4_MUX(ABE_PDM_DL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
646 OMAP4_MUX(ABE_PDM_FRAME, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
647 OMAP4_MUX(ABE_PDM_LB_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
648 OMAP4_MUX(ABE_CLKS, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
649 /* DMIC */
650 OMAP4_MUX(ABE_DMIC_CLK1, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
651 OMAP4_MUX(ABE_DMIC_DIN1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
652 OMAP4_MUX(ABE_DMIC_DIN2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
653 OMAP4_MUX(ABE_DMIC_DIN3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
654 /* McBSP1 */
655 OMAP4_MUX(ABE_MCBSP1_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
656 OMAP4_MUX(ABE_MCBSP1_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
657 OMAP4_MUX(ABE_MCBSP1_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT |
658 OMAP_PULL_ENA),
659 OMAP4_MUX(ABE_MCBSP1_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
660 /* McBSP2 */
661 OMAP4_MUX(ABE_MCBSP2_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
662 OMAP4_MUX(ABE_MCBSP2_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
663 OMAP4_MUX(ABE_MCBSP2_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT |
664 OMAP_PULL_ENA),
665 OMAP4_MUX(ABE_MCBSP2_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
666
667 { .reg_offset = OMAP_MUX_TERMINATOR },
668};
669
670#else
671#define board_mux NULL
672 #endif
673
674static void __init omap4_sdp4430_wifi_mux_init(void)
675{
676 omap_mux_init_gpio(GPIO_WIFI_IRQ, OMAP_PIN_INPUT |
677 OMAP_PIN_OFF_WAKEUPENABLE);
678 omap_mux_init_gpio(GPIO_WIFI_PMENA, OMAP_PIN_OUTPUT);
679
680 omap_mux_init_signal("sdmmc5_cmd.sdmmc5_cmd",
681 OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP);
682 omap_mux_init_signal("sdmmc5_clk.sdmmc5_clk",
683 OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP);
684 omap_mux_init_signal("sdmmc5_dat0.sdmmc5_dat0",
685 OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP);
686 omap_mux_init_signal("sdmmc5_dat1.sdmmc5_dat1",
687 OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP);
688 omap_mux_init_signal("sdmmc5_dat2.sdmmc5_dat2",
689 OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP);
690 omap_mux_init_signal("sdmmc5_dat3.sdmmc5_dat3",
691 OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP);
692
693}
694
695static struct wl12xx_platform_data omap4_sdp4430_wlan_data __initdata = {
696 .board_ref_clock = WL12XX_REFCLOCK_26,
697 .board_tcxo_clock = WL12XX_TCXOCLOCK_26,
698};
699
700static void __init omap4_sdp4430_wifi_init(void)
701{
702 int ret;
703
704 omap4_sdp4430_wifi_mux_init();
705 omap4_sdp4430_wlan_data.irq = gpio_to_irq(GPIO_WIFI_IRQ);
706 ret = wl12xx_set_platform_data(&omap4_sdp4430_wlan_data);
707 if (ret)
708 pr_err("Error setting wl12xx data: %d\n", ret);
709 ret = platform_device_register(&omap_vwlan_device);
710 if (ret)
711 pr_err("Error registering wl12xx device: %d\n", ret);
712}
713
714static void __init omap_4430sdp_init(void)
715{
716 int status;
717 int package = OMAP_PACKAGE_CBS;
718
719 if (omap_rev() == OMAP4430_REV_ES1_0)
720 package = OMAP_PACKAGE_CBL;
721 omap4_mux_init(board_mux, NULL, package);
722
723 omap4_i2c_init();
724 omap_sfh7741prox_init();
725 regulator_register_always_on(0, "backlight-enable",
726 &backlight_supply, 1, 0);
727 platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
728 omap_serial_init();
729 omap_sdrc_init(NULL, NULL);
730 omap4_sdp4430_wifi_init();
731 omap4_twl6030_hsmmc_init(mmc);
732
733 usb_bind_phy("musb-hdrc.2.auto", 0, "omap-usb2.3.auto");
734 usb_musb_init(&musb_board_data);
735
736 status = omap_ethernet_init();
737 if (status) {
738 pr_err("Ethernet initialization failed: %d\n", status);
739 } else {
740 sdp4430_spi_board_info[0].irq = gpio_to_irq(ETH_KS8851_IRQ);
741 spi_register_board_info(sdp4430_spi_board_info,
742 ARRAY_SIZE(sdp4430_spi_board_info));
743 }
744
745 pwm_add_table(sdp4430_pwm_lookup, ARRAY_SIZE(sdp4430_pwm_lookup));
746 status = omap4_keyboard_init(&sdp4430_keypad_data, &keypad_data);
747 if (status)
748 pr_err("Keypad initialization failed: %d\n", status);
749
750 omap_4430sdp_display_init();
751}
752
753MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
754 /* Maintainer: Santosh Shilimkar - Texas Instruments Inc */
755 .atag_offset = 0x100,
756 .smp = smp_ops(omap4_smp_ops),
757 .reserve = omap_reserve,
758 .map_io = omap4_map_io,
759 .init_early = omap4430_init_early,
760 .init_irq = gic_init_irq,
761 .init_machine = omap_4430sdp_init,
762 .init_late = omap4430_init_late,
763 .init_time = omap4_local_timer_init,
764 .restart = omap44xx_restart,
765MACHINE_END
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index ee6218c74807..d4622ed26252 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -293,7 +293,8 @@ static struct regulator_consumer_supply cm_t35_vsim_supply[] = {
293static struct regulator_consumer_supply cm_t35_vio_supplies[] = { 293static struct regulator_consumer_supply cm_t35_vio_supplies[] = {
294 REGULATOR_SUPPLY("vcc", "spi1.0"), 294 REGULATOR_SUPPLY("vcc", "spi1.0"),
295 REGULATOR_SUPPLY("vdds_dsi", "omapdss"), 295 REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
296 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), 296 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dpi.0"),
297 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"),
297}; 298};
298 299
299/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ 300/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 576420544178..f1d91ba5d1ac 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -222,6 +222,7 @@ static struct twl4030_gpio_platform_data devkit8000_gpio_data = {
222 222
223static struct regulator_consumer_supply devkit8000_vpll1_supplies[] = { 223static struct regulator_consumer_supply devkit8000_vpll1_supplies[] = {
224 REGULATOR_SUPPLY("vdds_dsi", "omapdss"), 224 REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
225 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dpi.0"),
225 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"), 226 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"),
226}; 227};
227 228
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index c33adea0247c..fc20a61f6b2a 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -112,6 +112,9 @@ struct gpmc_timings nand_default_timings[1] = {
112 .cs_rd_off = 36, 112 .cs_rd_off = 36,
113 .cs_wr_off = 36, 113 .cs_wr_off = 36,
114 114
115 .we_on = 6,
116 .oe_on = 6,
117
115 .adv_on = 6, 118 .adv_on = 6,
116 .adv_rd_off = 24, 119 .adv_rd_off = 24,
117 .adv_wr_off = 36, 120 .adv_wr_off = 36,
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 88aa6b1835c3..be5d005ebad2 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -15,6 +15,7 @@
15#include <linux/of_irq.h> 15#include <linux/of_irq.h>
16#include <linux/of_platform.h> 16#include <linux/of_platform.h>
17#include <linux/irqdomain.h> 17#include <linux/irqdomain.h>
18#include <linux/clk.h>
18 19
19#include <asm/mach/arch.h> 20#include <asm/mach/arch.h>
20 21
@@ -35,6 +36,21 @@ static struct of_device_id omap_dt_match_table[] __initdata = {
35 { } 36 { }
36}; 37};
37 38
39/*
40 * Create alias for USB host PHY clock.
41 * Remove this when clock phandle can be provided via DT
42 */
43static void __init legacy_init_ehci_clk(char *clkname)
44{
45 int ret;
46
47 ret = clk_add_alias("main_clk", NULL, clkname, NULL);
48 if (ret) {
49 pr_err("%s:Failed to add main_clk alias to %s :%d\n",
50 __func__, clkname, ret);
51 }
52}
53
38static void __init omap_generic_init(void) 54static void __init omap_generic_init(void)
39{ 55{
40 omap_sdrc_init(NULL, NULL); 56 omap_sdrc_init(NULL, NULL);
@@ -45,10 +61,15 @@ static void __init omap_generic_init(void)
45 * HACK: call display setup code for selected boards to enable omapdss. 61 * HACK: call display setup code for selected boards to enable omapdss.
46 * This will be removed when omapdss supports DT. 62 * This will be removed when omapdss supports DT.
47 */ 63 */
48 if (of_machine_is_compatible("ti,omap4-panda")) 64 if (of_machine_is_compatible("ti,omap4-panda")) {
49 omap4_panda_display_init_of(); 65 omap4_panda_display_init_of();
66 legacy_init_ehci_clk("auxclk3_ck");
67
68 }
50 else if (of_machine_is_compatible("ti,omap4-sdp")) 69 else if (of_machine_is_compatible("ti,omap4-sdp"))
51 omap_4430sdp_display_init_of(); 70 omap_4430sdp_display_init_of();
71 else if (of_machine_is_compatible("ti,omap5-uevm"))
72 legacy_init_ehci_clk("auxclk1_ck");
52} 73}
53 74
54#ifdef CONFIG_SOC_OMAP2420 75#ifdef CONFIG_SOC_OMAP2420
@@ -185,3 +206,19 @@ DT_MACHINE_START(OMAP5_DT, "Generic OMAP5 (Flattened Device Tree)")
185 .restart = omap44xx_restart, 206 .restart = omap44xx_restart,
186MACHINE_END 207MACHINE_END
187#endif 208#endif
209
210#ifdef CONFIG_SOC_AM43XX
211static const char *am43_boards_compat[] __initdata = {
212 "ti,am43",
213 NULL,
214};
215
216DT_MACHINE_START(AM43_DT, "Generic AM43 (Flattened Device Tree)")
217 .map_io = am33xx_map_io,
218 .init_early = am43xx_init_early,
219 .init_irq = omap_gic_of_init,
220 .init_machine = omap_generic_init,
221 .init_time = omap3_sync32k_timer_init,
222 .dt_compat = am43_boards_compat,
223MACHINE_END
224#endif
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index b54562d1235e..87e65dde8e13 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -553,6 +553,37 @@ static struct usbhs_omap_platform_data igep3_usbhs_bdata __initdata = {
553 553
554#ifdef CONFIG_OMAP_MUX 554#ifdef CONFIG_OMAP_MUX
555static struct omap_board_mux board_mux[] __initdata = { 555static struct omap_board_mux board_mux[] __initdata = {
556 /* Display Sub System */
557 OMAP3_MUX(DSS_PCLK, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
558 OMAP3_MUX(DSS_HSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
559 OMAP3_MUX(DSS_VSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
560 OMAP3_MUX(DSS_ACBIAS, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
561 OMAP3_MUX(DSS_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
562 OMAP3_MUX(DSS_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
563 OMAP3_MUX(DSS_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
564 OMAP3_MUX(DSS_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
565 OMAP3_MUX(DSS_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
566 OMAP3_MUX(DSS_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
567 OMAP3_MUX(DSS_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
568 OMAP3_MUX(DSS_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
569 OMAP3_MUX(DSS_DATA8, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
570 OMAP3_MUX(DSS_DATA9, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
571 OMAP3_MUX(DSS_DATA10, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
572 OMAP3_MUX(DSS_DATA11, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
573 OMAP3_MUX(DSS_DATA12, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
574 OMAP3_MUX(DSS_DATA13, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
575 OMAP3_MUX(DSS_DATA14, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
576 OMAP3_MUX(DSS_DATA15, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
577 OMAP3_MUX(DSS_DATA16, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
578 OMAP3_MUX(DSS_DATA17, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
579 OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
580 OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
581 OMAP3_MUX(DSS_DATA20, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
582 OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
583 OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
584 OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
585 /* TFP410 PanelBus DVI Transmitte (GPIO_170) */
586 OMAP3_MUX(HDQ_SIO, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
556 /* SMSC9221 LAN Controller ETH IRQ (GPIO_176) */ 587 /* SMSC9221 LAN Controller ETH IRQ (GPIO_176) */
557 OMAP3_MUX(MCSPI1_CS2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), 588 OMAP3_MUX(MCSPI1_CS2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
558 { .reg_offset = OMAP_MUX_TERMINATOR }, 589 { .reg_offset = OMAP_MUX_TERMINATOR },
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index d0d17bc58d9b..62e4f701b63b 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -272,7 +272,8 @@ static struct regulator_init_data ldp_vaux1 = {
272 272
273static struct regulator_consumer_supply ldp_vpll2_supplies[] = { 273static struct regulator_consumer_supply ldp_vpll2_supplies[] = {
274 REGULATOR_SUPPLY("vdds_dsi", "omapdss"), 274 REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
275 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), 275 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dpi.0"),
276 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"),
276}; 277};
277 278
278static struct regulator_init_data ldp_vpll2 = { 279static struct regulator_init_data ldp_vpll2 = {
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index f76d0de7b406..8c026269baca 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -174,6 +174,7 @@ static struct panel_sharp_ls037v7dw01_data omap3_evm_lcd_data = {
174 .ud_gpio = OMAP3EVM_LCD_PANEL_UD, 174 .ud_gpio = OMAP3EVM_LCD_PANEL_UD,
175}; 175};
176 176
177#ifdef CONFIG_BROKEN
177static void __init omap3_evm_display_init(void) 178static void __init omap3_evm_display_init(void)
178{ 179{
179 int r; 180 int r;
@@ -193,6 +194,7 @@ static void __init omap3_evm_display_init(void)
193 else 194 else
194 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1); 195 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
195} 196}
197#endif
196 198
197static struct omap_dss_device omap3_evm_lcd_device = { 199static struct omap_dss_device omap3_evm_lcd_device = {
198 .name = "lcd", 200 .name = "lcd",
@@ -715,7 +717,9 @@ static void __init omap3_evm_init(void)
715 717
716 omap_ads7846_init(1, OMAP3_EVM_TS_GPIO, 310, NULL); 718 omap_ads7846_init(1, OMAP3_EVM_TS_GPIO, 310, NULL);
717 omap3evm_init_smsc911x(); 719 omap3evm_init_smsc911x();
720#ifdef CONFIG_BROKEN
718 omap3_evm_display_init(); 721 omap3_evm_display_init();
722#endif
719 omap3_evm_wl12xx_init(); 723 omap3_evm_wl12xx_init();
720 omap_twl4030_audio_init("omap3evm", NULL); 724 omap_twl4030_audio_init("omap3evm", NULL);
721} 725}
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 28133d5b4fed..b1547a0edfcd 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -343,6 +343,7 @@ static struct regulator_consumer_supply pandora_vmmc3_supply[] = {
343static struct regulator_consumer_supply pandora_vdds_supplies[] = { 343static struct regulator_consumer_supply pandora_vdds_supplies[] = {
344 REGULATOR_SUPPLY("vdds_sdi", "omapdss"), 344 REGULATOR_SUPPLY("vdds_sdi", "omapdss"),
345 REGULATOR_SUPPLY("vdds_dsi", "omapdss"), 345 REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
346 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dpi.0"),
346 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"), 347 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"),
347}; 348};
348 349
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
deleted file mode 100644
index 1e2c75eee912..000000000000
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ /dev/null
@@ -1,455 +0,0 @@
1/*
2 * Board support file for OMAP4430 based PandaBoard.
3 *
4 * Copyright (C) 2010 Texas Instruments
5 *
6 * Author: David Anders <x0132446@ti.com>
7 *
8 * Based on mach-omap2/board-4430sdp.c
9 *
10 * Author: Santosh Shilimkar <santosh.shilimkar@ti.com>
11 *
12 * Based on mach-omap2/board-3430sdp.c
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/clk.h>
23#include <linux/io.h>
24#include <linux/leds.h>
25#include <linux/gpio.h>
26#include <linux/usb/otg.h>
27#include <linux/i2c/twl.h>
28#include <linux/mfd/twl6040.h>
29#include <linux/regulator/machine.h>
30#include <linux/regulator/fixed.h>
31#include <linux/ti_wilink_st.h>
32#include <linux/usb/musb.h>
33#include <linux/usb/phy.h>
34#include <linux/usb/nop-usb-xceiv.h>
35#include <linux/wl12xx.h>
36#include <linux/irqchip/arm-gic.h>
37#include <linux/platform_data/omap-abe-twl6040.h>
38
39#include <asm/mach-types.h>
40#include <asm/mach/arch.h>
41#include <asm/mach/map.h>
42
43#include "common.h"
44#include "soc.h"
45#include "mmc.h"
46#include "hsmmc.h"
47#include "control.h"
48#include "mux.h"
49#include "common-board-devices.h"
50#include "dss-common.h"
51
52#define GPIO_HUB_POWER 1
53#define GPIO_HUB_NRESET 62
54#define GPIO_WIFI_PMENA 43
55#define GPIO_WIFI_IRQ 53
56
57/* wl127x BT, FM, GPS connectivity chip */
58static struct ti_st_plat_data wilink_platform_data = {
59 .nshutdown_gpio = 46,
60 .dev_name = "/dev/ttyO1",
61 .flow_cntrl = 1,
62 .baud_rate = 3000000,
63 .chip_enable = NULL,
64 .suspend = NULL,
65 .resume = NULL,
66};
67
68static struct platform_device wl1271_device = {
69 .name = "kim",
70 .id = -1,
71 .dev = {
72 .platform_data = &wilink_platform_data,
73 },
74};
75
76static struct gpio_led gpio_leds[] = {
77 {
78 .name = "pandaboard::status1",
79 .default_trigger = "heartbeat",
80 .gpio = 7,
81 },
82 {
83 .name = "pandaboard::status2",
84 .default_trigger = "mmc0",
85 .gpio = 8,
86 },
87};
88
89static struct gpio_led_platform_data gpio_led_info = {
90 .leds = gpio_leds,
91 .num_leds = ARRAY_SIZE(gpio_leds),
92};
93
94static struct platform_device leds_gpio = {
95 .name = "leds-gpio",
96 .id = -1,
97 .dev = {
98 .platform_data = &gpio_led_info,
99 },
100};
101
102static struct omap_abe_twl6040_data panda_abe_audio_data = {
103 /* Audio out */
104 .has_hs = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
105 /* HandsFree through expansion connector */
106 .has_hf = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
107 /* PandaBoard: FM TX, PandaBoardES: can be connected to audio out */
108 .has_aux = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
109 /* PandaBoard: FM RX, PandaBoardES: audio in */
110 .has_afm = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
111 /* No jack detection. */
112 .jack_detection = 0,
113 /* MCLK input is 38.4MHz */
114 .mclk_freq = 38400000,
115
116};
117
118static struct platform_device panda_abe_audio = {
119 .name = "omap-abe-twl6040",
120 .id = -1,
121 .dev = {
122 .platform_data = &panda_abe_audio_data,
123 },
124};
125
126static struct platform_device panda_hdmi_audio_codec = {
127 .name = "hdmi-audio-codec",
128 .id = -1,
129};
130
131static struct platform_device btwilink_device = {
132 .name = "btwilink",
133 .id = -1,
134};
135
136/* PHY device on HS USB Port 1 i.e. nop_usb_xceiv.1 */
137static struct nop_usb_xceiv_platform_data hsusb1_phy_data = {
138 /* FREF_CLK3 provides the 19.2 MHz reference clock to the PHY */
139 .clk_rate = 19200000,
140};
141
142static struct usbhs_phy_data phy_data[] __initdata = {
143 {
144 .port = 1,
145 .reset_gpio = GPIO_HUB_NRESET,
146 .vcc_gpio = GPIO_HUB_POWER,
147 .vcc_polarity = 1,
148 .platform_data = &hsusb1_phy_data,
149 },
150};
151
152static struct platform_device *panda_devices[] __initdata = {
153 &leds_gpio,
154 &wl1271_device,
155 &panda_abe_audio,
156 &panda_hdmi_audio_codec,
157 &btwilink_device,
158};
159
160static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
161 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
162};
163
164static void __init omap4_ehci_init(void)
165{
166 int ret;
167
168 /* FREF_CLK3 provides the 19.2 MHz reference clock to the PHY */
169 ret = clk_add_alias("main_clk", "nop_usb_xceiv.1", "auxclk3_ck", NULL);
170 if (ret)
171 pr_err("Failed to add main_clk alias to auxclk3_ck\n");
172
173 usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
174 usbhs_init(&usbhs_bdata);
175}
176
177static struct omap_musb_board_data musb_board_data = {
178 .interface_type = MUSB_INTERFACE_UTMI,
179 .mode = MUSB_OTG,
180 .power = 100,
181};
182
183static struct omap2_hsmmc_info mmc[] = {
184 {
185 .mmc = 1,
186 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
187 .gpio_wp = -EINVAL,
188 .gpio_cd = -EINVAL,
189 },
190 {
191 .name = "wl1271",
192 .mmc = 5,
193 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
194 .gpio_wp = -EINVAL,
195 .gpio_cd = -EINVAL,
196 .ocr_mask = MMC_VDD_165_195,
197 .nonremovable = true,
198 },
199 {} /* Terminator */
200};
201
202static struct regulator_consumer_supply omap4_panda_vmmc5_supply[] = {
203 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.4"),
204};
205
206static struct regulator_init_data panda_vmmc5 = {
207 .constraints = {
208 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
209 },
210 .num_consumer_supplies = ARRAY_SIZE(omap4_panda_vmmc5_supply),
211 .consumer_supplies = omap4_panda_vmmc5_supply,
212};
213
214static struct fixed_voltage_config panda_vwlan = {
215 .supply_name = "vwl1271",
216 .microvolts = 1800000, /* 1.8V */
217 .gpio = GPIO_WIFI_PMENA,
218 .startup_delay = 70000, /* 70msec */
219 .enable_high = 1,
220 .enabled_at_boot = 0,
221 .init_data = &panda_vmmc5,
222};
223
224static struct platform_device omap_vwlan_device = {
225 .name = "reg-fixed-voltage",
226 .id = 1,
227 .dev = {
228 .platform_data = &panda_vwlan,
229 },
230};
231
232static struct wl12xx_platform_data omap_panda_wlan_data __initdata = {
233 .board_ref_clock = WL12XX_REFCLOCK_38, /* 38.4 MHz */
234};
235
236static struct twl6040_codec_data twl6040_codec = {
237 /* single-step ramp for headset and handsfree */
238 .hs_left_step = 0x0f,
239 .hs_right_step = 0x0f,
240 .hf_left_step = 0x1d,
241 .hf_right_step = 0x1d,
242};
243
244static struct twl6040_platform_data twl6040_data = {
245 .codec = &twl6040_codec,
246 .audpwron_gpio = 127,
247};
248
249static struct i2c_board_info __initdata panda_i2c_1_boardinfo[] = {
250 {
251 I2C_BOARD_INFO("twl6040", 0x4b),
252 .irq = 119 + OMAP44XX_IRQ_GIC_START,
253 .platform_data = &twl6040_data,
254 },
255};
256
257/* Panda board uses the common PMIC configuration */
258static struct twl4030_platform_data omap4_panda_twldata;
259
260/*
261 * Display monitor features are burnt in their EEPROM as EDID data. The EEPROM
262 * is connected as I2C slave device, and can be accessed at address 0x50
263 */
264static struct i2c_board_info __initdata panda_i2c_eeprom[] = {
265 {
266 I2C_BOARD_INFO("eeprom", 0x50),
267 },
268};
269
270static int __init omap4_panda_i2c_init(void)
271{
272 omap4_pmic_get_config(&omap4_panda_twldata, TWL_COMMON_PDATA_USB,
273 TWL_COMMON_REGULATOR_VDAC |
274 TWL_COMMON_REGULATOR_VAUX2 |
275 TWL_COMMON_REGULATOR_VAUX3 |
276 TWL_COMMON_REGULATOR_VMMC |
277 TWL_COMMON_REGULATOR_VPP |
278 TWL_COMMON_REGULATOR_VANA |
279 TWL_COMMON_REGULATOR_VCXIO |
280 TWL_COMMON_REGULATOR_VUSB |
281 TWL_COMMON_REGULATOR_CLK32KG |
282 TWL_COMMON_REGULATOR_V1V8 |
283 TWL_COMMON_REGULATOR_V2V1);
284 omap4_pmic_init("twl6030", &omap4_panda_twldata, panda_i2c_1_boardinfo,
285 ARRAY_SIZE(panda_i2c_1_boardinfo));
286 omap_register_i2c_bus(2, 400, NULL, 0);
287 /*
288 * Bus 3 is attached to the DVI port where devices like the pico DLP
289 * projector don't work reliably with 400kHz
290 */
291 omap_register_i2c_bus(3, 100, panda_i2c_eeprom,
292 ARRAY_SIZE(panda_i2c_eeprom));
293 omap_register_i2c_bus(4, 400, NULL, 0);
294 return 0;
295}
296
297#ifdef CONFIG_OMAP_MUX
298static struct omap_board_mux board_mux[] __initdata = {
299 /* WLAN IRQ - GPIO 53 */
300 OMAP4_MUX(GPMC_NCS3, OMAP_MUX_MODE3 | OMAP_PIN_INPUT),
301 /* WLAN POWER ENABLE - GPIO 43 */
302 OMAP4_MUX(GPMC_A19, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT),
303 /* WLAN SDIO: MMC5 CMD */
304 OMAP4_MUX(SDMMC5_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
305 /* WLAN SDIO: MMC5 CLK */
306 OMAP4_MUX(SDMMC5_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
307 /* WLAN SDIO: MMC5 DAT[0-3] */
308 OMAP4_MUX(SDMMC5_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
309 OMAP4_MUX(SDMMC5_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
310 OMAP4_MUX(SDMMC5_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
311 OMAP4_MUX(SDMMC5_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
312 /* gpio 0 - TFP410 PD */
313 OMAP4_MUX(KPD_COL1, OMAP_PIN_OUTPUT | OMAP_MUX_MODE3),
314 /* dispc2_data23 */
315 OMAP4_MUX(USBB2_ULPITLL_STP, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
316 /* dispc2_data22 */
317 OMAP4_MUX(USBB2_ULPITLL_DIR, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
318 /* dispc2_data21 */
319 OMAP4_MUX(USBB2_ULPITLL_NXT, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
320 /* dispc2_data20 */
321 OMAP4_MUX(USBB2_ULPITLL_DAT0, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
322 /* dispc2_data19 */
323 OMAP4_MUX(USBB2_ULPITLL_DAT1, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
324 /* dispc2_data18 */
325 OMAP4_MUX(USBB2_ULPITLL_DAT2, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
326 /* dispc2_data15 */
327 OMAP4_MUX(USBB2_ULPITLL_DAT3, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
328 /* dispc2_data14 */
329 OMAP4_MUX(USBB2_ULPITLL_DAT4, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
330 /* dispc2_data13 */
331 OMAP4_MUX(USBB2_ULPITLL_DAT5, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
332 /* dispc2_data12 */
333 OMAP4_MUX(USBB2_ULPITLL_DAT6, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
334 /* dispc2_data11 */
335 OMAP4_MUX(USBB2_ULPITLL_DAT7, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
336 /* dispc2_data10 */
337 OMAP4_MUX(DPM_EMU3, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
338 /* dispc2_data9 */
339 OMAP4_MUX(DPM_EMU4, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
340 /* dispc2_data16 */
341 OMAP4_MUX(DPM_EMU5, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
342 /* dispc2_data17 */
343 OMAP4_MUX(DPM_EMU6, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
344 /* dispc2_hsync */
345 OMAP4_MUX(DPM_EMU7, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
346 /* dispc2_pclk */
347 OMAP4_MUX(DPM_EMU8, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
348 /* dispc2_vsync */
349 OMAP4_MUX(DPM_EMU9, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
350 /* dispc2_de */
351 OMAP4_MUX(DPM_EMU10, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
352 /* dispc2_data8 */
353 OMAP4_MUX(DPM_EMU11, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
354 /* dispc2_data7 */
355 OMAP4_MUX(DPM_EMU12, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
356 /* dispc2_data6 */
357 OMAP4_MUX(DPM_EMU13, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
358 /* dispc2_data5 */
359 OMAP4_MUX(DPM_EMU14, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
360 /* dispc2_data4 */
361 OMAP4_MUX(DPM_EMU15, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
362 /* dispc2_data3 */
363 OMAP4_MUX(DPM_EMU16, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
364 /* dispc2_data2 */
365 OMAP4_MUX(DPM_EMU17, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
366 /* dispc2_data1 */
367 OMAP4_MUX(DPM_EMU18, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
368 /* dispc2_data0 */
369 OMAP4_MUX(DPM_EMU19, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
370 /* NIRQ2 for twl6040 */
371 OMAP4_MUX(SYS_NIRQ2, OMAP_MUX_MODE0 |
372 OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE),
373 /* GPIO_127 for twl6040 */
374 OMAP4_MUX(HDQ_SIO, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT),
375 /* McPDM */
376 OMAP4_MUX(ABE_PDM_UL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
377 OMAP4_MUX(ABE_PDM_DL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
378 OMAP4_MUX(ABE_PDM_FRAME, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
379 OMAP4_MUX(ABE_PDM_LB_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
380 OMAP4_MUX(ABE_CLKS, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
381 /* McBSP1 */
382 OMAP4_MUX(ABE_MCBSP1_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
383 OMAP4_MUX(ABE_MCBSP1_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
384 OMAP4_MUX(ABE_MCBSP1_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT |
385 OMAP_PULL_ENA),
386 OMAP4_MUX(ABE_MCBSP1_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
387
388 /* UART2 - BT/FM/GPS shared transport */
389 OMAP4_MUX(UART2_CTS, OMAP_PIN_INPUT | OMAP_MUX_MODE0),
390 OMAP4_MUX(UART2_RTS, OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
391 OMAP4_MUX(UART2_RX, OMAP_PIN_INPUT | OMAP_MUX_MODE0),
392 OMAP4_MUX(UART2_TX, OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
393
394 { .reg_offset = OMAP_MUX_TERMINATOR },
395};
396
397#else
398#define board_mux NULL
399#endif
400
401
402static void omap4_panda_init_rev(void)
403{
404 if (cpu_is_omap443x()) {
405 /* PandaBoard 4430 */
406 /* ASoC audio configuration */
407 panda_abe_audio_data.card_name = "PandaBoard";
408 panda_abe_audio_data.has_hsmic = 1;
409 } else {
410 /* PandaBoard ES */
411 /* ASoC audio configuration */
412 panda_abe_audio_data.card_name = "PandaBoardES";
413 }
414}
415
416static void __init omap4_panda_init(void)
417{
418 int package = OMAP_PACKAGE_CBS;
419 int ret;
420
421 if (omap_rev() == OMAP4430_REV_ES1_0)
422 package = OMAP_PACKAGE_CBL;
423 omap4_mux_init(board_mux, NULL, package);
424
425 omap_panda_wlan_data.irq = gpio_to_irq(GPIO_WIFI_IRQ);
426 ret = wl12xx_set_platform_data(&omap_panda_wlan_data);
427 if (ret)
428 pr_err("error setting wl12xx data: %d\n", ret);
429
430 omap4_panda_init_rev();
431 omap4_panda_i2c_init();
432 platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
433 platform_device_register(&omap_vwlan_device);
434 omap_serial_init();
435 omap_sdrc_init(NULL, NULL);
436 omap4_twl6030_hsmmc_init(mmc);
437 omap4_ehci_init();
438 usb_bind_phy("musb-hdrc.2.auto", 0, "omap-usb2.3.auto");
439 usb_musb_init(&musb_board_data);
440 omap4_panda_display_init();
441}
442
443MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
444 /* Maintainer: David Anders - Texas Instruments Inc */
445 .atag_offset = 0x100,
446 .smp = smp_ops(omap4_smp_ops),
447 .reserve = omap_reserve,
448 .map_io = omap4_map_io,
449 .init_early = omap4430_init_early,
450 .init_irq = gic_init_irq,
451 .init_machine = omap4_panda_init,
452 .init_late = omap4430_init_late,
453 .init_time = omap4_local_timer_init,
454 .restart = omap44xx_restart,
455MACHINE_END
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 4ca6b680aa72..5748b5d06c23 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -68,6 +68,7 @@
68 68
69#define OVERO_SMSC911X_CS 5 69#define OVERO_SMSC911X_CS 5
70#define OVERO_SMSC911X_GPIO 176 70#define OVERO_SMSC911X_GPIO 176
71#define OVERO_SMSC911X_NRESET 64
71#define OVERO_SMSC911X2_CS 4 72#define OVERO_SMSC911X2_CS 4
72#define OVERO_SMSC911X2_GPIO 65 73#define OVERO_SMSC911X2_GPIO 65
73 74
@@ -122,7 +123,7 @@ static struct omap_smsc911x_platform_data smsc911x_cfg = {
122 .id = 0, 123 .id = 0,
123 .cs = OVERO_SMSC911X_CS, 124 .cs = OVERO_SMSC911X_CS,
124 .gpio_irq = OVERO_SMSC911X_GPIO, 125 .gpio_irq = OVERO_SMSC911X_GPIO,
125 .gpio_reset = -EINVAL, 126 .gpio_reset = OVERO_SMSC911X_NRESET,
126 .flags = SMSC911X_USE_32BIT, 127 .flags = SMSC911X_USE_32BIT,
127}; 128};
128 129
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 18ca61e300b3..9c2dd102fbbb 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -553,6 +553,7 @@ static struct regulator_consumer_supply rx51_vio_supplies[] = {
553 553
554static struct regulator_consumer_supply rx51_vaux1_consumers[] = { 554static struct regulator_consumer_supply rx51_vaux1_consumers[] = {
555 REGULATOR_SUPPLY("vdds_sdi", "omapdss"), 555 REGULATOR_SUPPLY("vdds_sdi", "omapdss"),
556 REGULATOR_SUPPLY("vdds_sdi", "omapdss_sdi.0"),
556 /* Si4713 supply */ 557 /* Si4713 supply */
557 REGULATOR_SUPPLY("vdd", "2-0063"), 558 REGULATOR_SUPPLY("vdd", "2-0063"),
558 /* lis3lv02d */ 559 /* lis3lv02d */
diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c
index bd74f9f6063b..bdd1e3a179e1 100644
--- a/arch/arm/mach-omap2/board-rx51-video.c
+++ b/arch/arm/mach-omap2/board-rx51-video.c
@@ -61,7 +61,7 @@ static struct omap_dss_board_info rx51_dss_board_info = {
61 61
62static int __init rx51_video_init(void) 62static int __init rx51_video_init(void)
63{ 63{
64 if (!machine_is_nokia_rx51()) 64 if (!machine_is_nokia_rx51() && !of_machine_is_compatible("nokia,omap3-n900"))
65 return 0; 65 return 0;
66 66
67 if (omap_mux_init_gpio(RX51_LCD_RESET_GPIO, OMAP_PIN_OUTPUT)) { 67 if (omap_mux_init_gpio(RX51_LCD_RESET_GPIO, OMAP_PIN_OUTPUT)) {
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
index af3544ce4f02..ba6534d7f155 100644
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -431,15 +431,11 @@ DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null);
431 * - Driver code is not yet migrated to use hwmod/runtime pm 431 * - Driver code is not yet migrated to use hwmod/runtime pm
432 * - Modules outside kernel access (to disable them by default) 432 * - Modules outside kernel access (to disable them by default)
433 * 433 *
434 * - debugss
435 * - mmu (gfx domain) 434 * - mmu (gfx domain)
436 * - cefuse 435 * - cefuse
437 * - usbotg_fck (its additional clock and not really a modulemode) 436 * - usbotg_fck (its additional clock and not really a modulemode)
438 * - ieee5000 437 * - ieee5000
439 */ 438 */
440DEFINE_CLK_GATE(debugss_ick, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
441 AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
442 0x0, NULL);
443 439
444DEFINE_CLK_GATE(mmu_fck, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0, 440DEFINE_CLK_GATE(mmu_fck, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
445 AM33XX_CM_GFX_MMUDATA_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT, 441 AM33XX_CM_GFX_MMUDATA_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
@@ -862,6 +858,69 @@ static struct clk_hw_omap wdt1_fck_hw = {
862 858
863DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops); 859DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);
864 860
861static const char *pwmss_clk_parents[] = {
862 "dpll_per_m2_ck",
863};
864
865static const struct clk_ops ehrpwm_tbclk_ops = {
866 .enable = &omap2_dflt_clk_enable,
867 .disable = &omap2_dflt_clk_disable,
868};
869
870DEFINE_CLK_OMAP_MUX_GATE(ehrpwm0_tbclk, "l4ls_clkdm",
871 NULL, NULL, 0,
872 AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
873 AM33XX_PWMSS0_TBCLKEN_SHIFT,
874 NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
875
876DEFINE_CLK_OMAP_MUX_GATE(ehrpwm1_tbclk, "l4ls_clkdm",
877 NULL, NULL, 0,
878 AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
879 AM33XX_PWMSS1_TBCLKEN_SHIFT,
880 NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
881
882DEFINE_CLK_OMAP_MUX_GATE(ehrpwm2_tbclk, "l4ls_clkdm",
883 NULL, NULL, 0,
884 AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
885 AM33XX_PWMSS2_TBCLKEN_SHIFT,
886 NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
887
888/*
889 * debugss optional clocks
890 */
891DEFINE_CLK_GATE(dbg_sysclk_ck, "sys_clkin_ck", &sys_clkin_ck,
892 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
893 AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT, 0x0, NULL);
894
895DEFINE_CLK_GATE(dbg_clka_ck, "dpll_core_m4_ck", &dpll_core_m4_ck,
896 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
897 AM33XX_OPTCLK_DEBUG_CLKA_SHIFT, 0x0, NULL);
898
899static const char *stm_pmd_clock_mux_ck_parents[] = {
900 "dbg_sysclk_ck", "dbg_clka_ck",
901};
902
903DEFINE_CLK_MUX(stm_pmd_clock_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0,
904 AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_STM_PMD_CLKSEL_SHIFT,
905 AM33XX_STM_PMD_CLKSEL_WIDTH, 0x0, NULL);
906
907DEFINE_CLK_MUX(trace_pmd_clk_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0,
908 AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
909 AM33XX_TRC_PMD_CLKSEL_SHIFT,
910 AM33XX_TRC_PMD_CLKSEL_WIDTH, 0x0, NULL);
911
912DEFINE_CLK_DIVIDER(stm_clk_div_ck, "stm_pmd_clock_mux_ck",
913 &stm_pmd_clock_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
914 AM33XX_STM_PMD_CLKDIVSEL_SHIFT,
915 AM33XX_STM_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
916 NULL);
917
918DEFINE_CLK_DIVIDER(trace_clk_div_ck, "trace_pmd_clk_mux_ck",
919 &trace_pmd_clk_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
920 AM33XX_TRC_PMD_CLKDIVSEL_SHIFT,
921 AM33XX_TRC_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
922 NULL);
923
865/* 924/*
866 * clkdev 925 * clkdev
867 */ 926 */
@@ -899,7 +958,6 @@ static struct omap_clk am33xx_clks[] = {
899 CLK("481cc000.d_can", NULL, &dcan0_fck), 958 CLK("481cc000.d_can", NULL, &dcan0_fck),
900 CLK(NULL, "dcan1_fck", &dcan1_fck), 959 CLK(NULL, "dcan1_fck", &dcan1_fck),
901 CLK("481d0000.d_can", NULL, &dcan1_fck), 960 CLK("481d0000.d_can", NULL, &dcan1_fck),
902 CLK(NULL, "debugss_ick", &debugss_ick),
903 CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk), 961 CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk),
904 CLK(NULL, "mcasp0_fck", &mcasp0_fck), 962 CLK(NULL, "mcasp0_fck", &mcasp0_fck),
905 CLK(NULL, "mcasp1_fck", &mcasp1_fck), 963 CLK(NULL, "mcasp1_fck", &mcasp1_fck),
@@ -942,6 +1000,16 @@ static struct omap_clk am33xx_clks[] = {
942 CLK(NULL, "clkout2_div_ck", &clkout2_div_ck), 1000 CLK(NULL, "clkout2_div_ck", &clkout2_div_ck),
943 CLK(NULL, "timer_32k_ck", &clkdiv32k_ick), 1001 CLK(NULL, "timer_32k_ck", &clkdiv32k_ick),
944 CLK(NULL, "timer_sys_ck", &sys_clkin_ck), 1002 CLK(NULL, "timer_sys_ck", &sys_clkin_ck),
1003 CLK(NULL, "dbg_sysclk_ck", &dbg_sysclk_ck),
1004 CLK(NULL, "dbg_clka_ck", &dbg_clka_ck),
1005 CLK(NULL, "stm_pmd_clock_mux_ck", &stm_pmd_clock_mux_ck),
1006 CLK(NULL, "trace_pmd_clk_mux_ck", &trace_pmd_clk_mux_ck),
1007 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck),
1008 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck),
1009 CLK(NULL, "clkout2_ck", &clkout2_ck),
1010 CLK("48300200.ehrpwm", "tbclk", &ehrpwm0_tbclk),
1011 CLK("48302200.ehrpwm", "tbclk", &ehrpwm1_tbclk),
1012 CLK("48304200.ehrpwm", "tbclk", &ehrpwm2_tbclk),
945}; 1013};
946 1014
947 1015
@@ -952,6 +1020,7 @@ static const char *enable_init_clks[] = {
952 "l4hs_gclk", 1020 "l4hs_gclk",
953 "l4fw_gclk", 1021 "l4fw_gclk",
954 "l4ls_gclk", 1022 "l4ls_gclk",
1023 "clkout2_ck", /* Required for external peripherals like, Audio codecs */
955}; 1024};
956 1025
957int __init am33xx_clk_init(void) 1026int __init am33xx_clk_init(void)
diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
index 45cd26430d1f..334b76745900 100644
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -3329,11 +3329,7 @@ static struct omap_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
3329 CLK(NULL, "cpefuse_fck", &cpefuse_fck), 3329 CLK(NULL, "cpefuse_fck", &cpefuse_fck),
3330 CLK(NULL, "ts_fck", &ts_fck), 3330 CLK(NULL, "ts_fck", &ts_fck),
3331 CLK(NULL, "usbtll_fck", &usbtll_fck), 3331 CLK(NULL, "usbtll_fck", &usbtll_fck),
3332 CLK("usbhs_omap", "usbtll_fck", &usbtll_fck),
3333 CLK("usbhs_tll", "usbtll_fck", &usbtll_fck),
3334 CLK(NULL, "usbtll_ick", &usbtll_ick), 3332 CLK(NULL, "usbtll_ick", &usbtll_ick),
3335 CLK("usbhs_omap", "usbtll_ick", &usbtll_ick),
3336 CLK("usbhs_tll", "usbtll_ick", &usbtll_ick),
3337 CLK("omap_hsmmc.2", "ick", &mmchs3_ick), 3333 CLK("omap_hsmmc.2", "ick", &mmchs3_ick),
3338 CLK(NULL, "mmchs3_ick", &mmchs3_ick), 3334 CLK(NULL, "mmchs3_ick", &mmchs3_ick),
3339 CLK(NULL, "mmchs3_fck", &mmchs3_fck), 3335 CLK(NULL, "mmchs3_fck", &mmchs3_fck),
@@ -3343,7 +3339,6 @@ static struct omap_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
3343 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck), 3339 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck),
3344 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck), 3340 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck),
3345 CLK(NULL, "usbhost_ick", &usbhost_ick), 3341 CLK(NULL, "usbhost_ick", &usbhost_ick),
3346 CLK("usbhs_omap", "usbhost_ick", &usbhost_ick),
3347}; 3342};
3348 3343
3349/* 3344/*
@@ -3463,12 +3458,6 @@ static struct omap_clk omap3xxx_clks[] = {
3463 CLK(NULL, "utmi_p2_gfclk", &dummy_ck), 3458 CLK(NULL, "utmi_p2_gfclk", &dummy_ck),
3464 CLK(NULL, "xclk60mhsp1_ck", &dummy_ck), 3459 CLK(NULL, "xclk60mhsp1_ck", &dummy_ck),
3465 CLK(NULL, "xclk60mhsp2_ck", &dummy_ck), 3460 CLK(NULL, "xclk60mhsp2_ck", &dummy_ck),
3466 CLK(NULL, "usb_host_hs_utmi_p1_clk", &dummy_ck),
3467 CLK(NULL, "usb_host_hs_utmi_p2_clk", &dummy_ck),
3468 CLK("usbhs_omap", "usb_tll_hs_usb_ch0_clk", &dummy_ck),
3469 CLK("usbhs_omap", "usb_tll_hs_usb_ch1_clk", &dummy_ck),
3470 CLK("usbhs_tll", "usb_tll_hs_usb_ch0_clk", &dummy_ck),
3471 CLK("usbhs_tll", "usb_tll_hs_usb_ch1_clk", &dummy_ck),
3472 CLK(NULL, "init_60m_fclk", &dummy_ck), 3461 CLK(NULL, "init_60m_fclk", &dummy_ck),
3473 CLK(NULL, "gpt1_fck", &gpt1_fck), 3462 CLK(NULL, "gpt1_fck", &gpt1_fck),
3474 CLK(NULL, "aes2_ick", &aes2_ick), 3463 CLK(NULL, "aes2_ick", &aes2_ick),
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 2da37656a693..daeecf1b89fa 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -216,6 +216,7 @@ extern void __init omap243x_clockdomains_init(void);
216extern void __init omap3xxx_clockdomains_init(void); 216extern void __init omap3xxx_clockdomains_init(void);
217extern void __init am33xx_clockdomains_init(void); 217extern void __init am33xx_clockdomains_init(void);
218extern void __init omap44xx_clockdomains_init(void); 218extern void __init omap44xx_clockdomains_init(void);
219extern void __init omap54xx_clockdomains_init(void);
219 220
220extern void clkdm_add_autodeps(struct clockdomain *clkdm); 221extern void clkdm_add_autodeps(struct clockdomain *clkdm);
221extern void clkdm_del_autodeps(struct clockdomain *clkdm); 222extern void clkdm_del_autodeps(struct clockdomain *clkdm);
diff --git a/arch/arm/mach-omap2/clockdomains54xx_data.c b/arch/arm/mach-omap2/clockdomains54xx_data.c
new file mode 100644
index 000000000000..1a3c69d2e14c
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains54xx_data.c
@@ -0,0 +1,464 @@
1/*
2 * OMAP54XX Clock domains framework
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * Abhijit Pagare (abhijitpagare@ti.com)
7 * Benoit Cousson (b-cousson@ti.com)
8 * Paul Walmsley (paul@pwsan.com)
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#include <linux/kernel.h>
22#include <linux/io.h>
23
24#include "clockdomain.h"
25#include "cm1_54xx.h"
26#include "cm2_54xx.h"
27
28#include "cm-regbits-54xx.h"
29#include "prm54xx.h"
30#include "prcm44xx.h"
31#include "prcm_mpu54xx.h"
32
33/* Static Dependencies for OMAP4 Clock Domains */
34
35static struct clkdm_dep c2c_wkup_sleep_deps[] = {
36 { .clkdm_name = "abe_clkdm" },
37 { .clkdm_name = "emif_clkdm" },
38 { .clkdm_name = "iva_clkdm" },
39 { .clkdm_name = "l3init_clkdm" },
40 { .clkdm_name = "l3main1_clkdm" },
41 { .clkdm_name = "l3main2_clkdm" },
42 { .clkdm_name = "l4cfg_clkdm" },
43 { .clkdm_name = "l4per_clkdm" },
44 { NULL },
45};
46
47static struct clkdm_dep cam_wkup_sleep_deps[] = {
48 { .clkdm_name = "emif_clkdm" },
49 { .clkdm_name = "iva_clkdm" },
50 { .clkdm_name = "l3main1_clkdm" },
51 { NULL },
52};
53
54static struct clkdm_dep dma_wkup_sleep_deps[] = {
55 { .clkdm_name = "abe_clkdm" },
56 { .clkdm_name = "dss_clkdm" },
57 { .clkdm_name = "emif_clkdm" },
58 { .clkdm_name = "ipu_clkdm" },
59 { .clkdm_name = "iva_clkdm" },
60 { .clkdm_name = "l3init_clkdm" },
61 { .clkdm_name = "l3main1_clkdm" },
62 { .clkdm_name = "l4cfg_clkdm" },
63 { .clkdm_name = "l4per_clkdm" },
64 { .clkdm_name = "l4sec_clkdm" },
65 { .clkdm_name = "wkupaon_clkdm" },
66 { NULL },
67};
68
69static struct clkdm_dep dsp_wkup_sleep_deps[] = {
70 { .clkdm_name = "abe_clkdm" },
71 { .clkdm_name = "emif_clkdm" },
72 { .clkdm_name = "iva_clkdm" },
73 { .clkdm_name = "l3init_clkdm" },
74 { .clkdm_name = "l3main1_clkdm" },
75 { .clkdm_name = "l3main2_clkdm" },
76 { .clkdm_name = "l4cfg_clkdm" },
77 { .clkdm_name = "l4per_clkdm" },
78 { .clkdm_name = "wkupaon_clkdm" },
79 { NULL },
80};
81
82static struct clkdm_dep dss_wkup_sleep_deps[] = {
83 { .clkdm_name = "emif_clkdm" },
84 { .clkdm_name = "iva_clkdm" },
85 { .clkdm_name = "l3main2_clkdm" },
86 { NULL },
87};
88
89static struct clkdm_dep gpu_wkup_sleep_deps[] = {
90 { .clkdm_name = "emif_clkdm" },
91 { .clkdm_name = "iva_clkdm" },
92 { .clkdm_name = "l3main1_clkdm" },
93 { NULL },
94};
95
96static struct clkdm_dep ipu_wkup_sleep_deps[] = {
97 { .clkdm_name = "abe_clkdm" },
98 { .clkdm_name = "dsp_clkdm" },
99 { .clkdm_name = "dss_clkdm" },
100 { .clkdm_name = "emif_clkdm" },
101 { .clkdm_name = "gpu_clkdm" },
102 { .clkdm_name = "iva_clkdm" },
103 { .clkdm_name = "l3init_clkdm" },
104 { .clkdm_name = "l3main1_clkdm" },
105 { .clkdm_name = "l3main2_clkdm" },
106 { .clkdm_name = "l4cfg_clkdm" },
107 { .clkdm_name = "l4per_clkdm" },
108 { .clkdm_name = "l4sec_clkdm" },
109 { .clkdm_name = "wkupaon_clkdm" },
110 { NULL },
111};
112
113static struct clkdm_dep iva_wkup_sleep_deps[] = {
114 { .clkdm_name = "emif_clkdm" },
115 { .clkdm_name = "l3main1_clkdm" },
116 { NULL },
117};
118
119static struct clkdm_dep l3init_wkup_sleep_deps[] = {
120 { .clkdm_name = "abe_clkdm" },
121 { .clkdm_name = "emif_clkdm" },
122 { .clkdm_name = "iva_clkdm" },
123 { .clkdm_name = "l4cfg_clkdm" },
124 { .clkdm_name = "l4per_clkdm" },
125 { .clkdm_name = "l4sec_clkdm" },
126 { .clkdm_name = "wkupaon_clkdm" },
127 { NULL },
128};
129
130static struct clkdm_dep l4sec_wkup_sleep_deps[] = {
131 { .clkdm_name = "emif_clkdm" },
132 { .clkdm_name = "l3main1_clkdm" },
133 { .clkdm_name = "l4per_clkdm" },
134 { NULL },
135};
136
137static struct clkdm_dep mipiext_wkup_sleep_deps[] = {
138 { .clkdm_name = "abe_clkdm" },
139 { .clkdm_name = "emif_clkdm" },
140 { .clkdm_name = "iva_clkdm" },
141 { .clkdm_name = "l3init_clkdm" },
142 { .clkdm_name = "l3main1_clkdm" },
143 { .clkdm_name = "l3main2_clkdm" },
144 { .clkdm_name = "l4cfg_clkdm" },
145 { .clkdm_name = "l4per_clkdm" },
146 { NULL },
147};
148
149static struct clkdm_dep mpu_wkup_sleep_deps[] = {
150 { .clkdm_name = "abe_clkdm" },
151 { .clkdm_name = "dsp_clkdm" },
152 { .clkdm_name = "dss_clkdm" },
153 { .clkdm_name = "emif_clkdm" },
154 { .clkdm_name = "gpu_clkdm" },
155 { .clkdm_name = "ipu_clkdm" },
156 { .clkdm_name = "iva_clkdm" },
157 { .clkdm_name = "l3init_clkdm" },
158 { .clkdm_name = "l3main1_clkdm" },
159 { .clkdm_name = "l3main2_clkdm" },
160 { .clkdm_name = "l4cfg_clkdm" },
161 { .clkdm_name = "l4per_clkdm" },
162 { .clkdm_name = "l4sec_clkdm" },
163 { .clkdm_name = "wkupaon_clkdm" },
164 { NULL },
165};
166
167static struct clockdomain l4sec_54xx_clkdm = {
168 .name = "l4sec_clkdm",
169 .pwrdm = { .name = "core_pwrdm" },
170 .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
171 .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
172 .clkdm_offs = OMAP54XX_CM_CORE_CORE_L4SEC_CDOFFS,
173 .dep_bit = OMAP54XX_L4SEC_STATDEP_SHIFT,
174 .wkdep_srcs = l4sec_wkup_sleep_deps,
175 .sleepdep_srcs = l4sec_wkup_sleep_deps,
176 .flags = CLKDM_CAN_HWSUP_SWSUP,
177};
178
179static struct clockdomain iva_54xx_clkdm = {
180 .name = "iva_clkdm",
181 .pwrdm = { .name = "iva_pwrdm" },
182 .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
183 .cm_inst = OMAP54XX_CM_CORE_IVA_INST,
184 .clkdm_offs = OMAP54XX_CM_CORE_IVA_IVA_CDOFFS,
185 .dep_bit = OMAP54XX_IVA_STATDEP_SHIFT,
186 .wkdep_srcs = iva_wkup_sleep_deps,
187 .sleepdep_srcs = iva_wkup_sleep_deps,
188 .flags = CLKDM_CAN_HWSUP_SWSUP,
189};
190
191static struct clockdomain mipiext_54xx_clkdm = {
192 .name = "mipiext_clkdm",
193 .pwrdm = { .name = "core_pwrdm" },
194 .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
195 .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
196 .clkdm_offs = OMAP54XX_CM_CORE_CORE_MIPIEXT_CDOFFS,
197 .wkdep_srcs = mipiext_wkup_sleep_deps,
198 .sleepdep_srcs = mipiext_wkup_sleep_deps,
199 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
200};
201
202static struct clockdomain l3main2_54xx_clkdm = {
203 .name = "l3main2_clkdm",
204 .pwrdm = { .name = "core_pwrdm" },
205 .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
206 .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
207 .clkdm_offs = OMAP54XX_CM_CORE_CORE_L3MAIN2_CDOFFS,
208 .dep_bit = OMAP54XX_L3MAIN2_STATDEP_SHIFT,
209 .flags = CLKDM_CAN_HWSUP,
210};
211
212static struct clockdomain l3main1_54xx_clkdm = {
213 .name = "l3main1_clkdm",
214 .pwrdm = { .name = "core_pwrdm" },
215 .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
216 .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
217 .clkdm_offs = OMAP54XX_CM_CORE_CORE_L3MAIN1_CDOFFS,
218 .dep_bit = OMAP54XX_L3MAIN1_STATDEP_SHIFT,
219 .flags = CLKDM_CAN_HWSUP,
220};
221
222static struct clockdomain custefuse_54xx_clkdm = {
223 .name = "custefuse_clkdm",
224 .pwrdm = { .name = "custefuse_pwrdm" },
225 .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
226 .cm_inst = OMAP54XX_CM_CORE_CUSTEFUSE_INST,
227 .clkdm_offs = OMAP54XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS,
228 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
229};
230
231static struct clockdomain ipu_54xx_clkdm = {
232 .name = "ipu_clkdm",
233 .pwrdm = { .name = "core_pwrdm" },
234 .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
235 .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
236 .clkdm_offs = OMAP54XX_CM_CORE_CORE_IPU_CDOFFS,
237 .dep_bit = OMAP54XX_IPU_STATDEP_SHIFT,
238 .wkdep_srcs = ipu_wkup_sleep_deps,
239 .sleepdep_srcs = ipu_wkup_sleep_deps,
240 .flags = CLKDM_CAN_HWSUP_SWSUP,
241};
242
243static struct clockdomain l4cfg_54xx_clkdm = {
244 .name = "l4cfg_clkdm",
245 .pwrdm = { .name = "core_pwrdm" },
246 .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
247 .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
248 .clkdm_offs = OMAP54XX_CM_CORE_CORE_L4CFG_CDOFFS,
249 .dep_bit = OMAP54XX_L4CFG_STATDEP_SHIFT,
250 .flags = CLKDM_CAN_HWSUP,
251};
252
253static struct clockdomain abe_54xx_clkdm = {
254 .name = "abe_clkdm",
255 .pwrdm = { .name = "abe_pwrdm" },
256 .prcm_partition = OMAP54XX_CM_CORE_AON_PARTITION,
257 .cm_inst = OMAP54XX_CM_CORE_AON_ABE_INST,
258 .clkdm_offs = OMAP54XX_CM_CORE_AON_ABE_ABE_CDOFFS,
259 .dep_bit = OMAP54XX_ABE_STATDEP_SHIFT,
260 .flags = CLKDM_CAN_HWSUP_SWSUP,
261};
262
263static struct clockdomain dss_54xx_clkdm = {
264 .name = "dss_clkdm",
265 .pwrdm = { .name = "dss_pwrdm" },
266 .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
267 .cm_inst = OMAP54XX_CM_CORE_DSS_INST,
268 .clkdm_offs = OMAP54XX_CM_CORE_DSS_DSS_CDOFFS,
269 .dep_bit = OMAP54XX_DSS_STATDEP_SHIFT,
270 .wkdep_srcs = dss_wkup_sleep_deps,
271 .sleepdep_srcs = dss_wkup_sleep_deps,
272 .flags = CLKDM_CAN_HWSUP_SWSUP,
273};
274
275static struct clockdomain dsp_54xx_clkdm = {
276 .name = "dsp_clkdm",
277 .pwrdm = { .name = "dsp_pwrdm" },
278 .prcm_partition = OMAP54XX_CM_CORE_AON_PARTITION,
279 .cm_inst = OMAP54XX_CM_CORE_AON_DSP_INST,
280 .clkdm_offs = OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS,
281 .dep_bit = OMAP54XX_DSP_STATDEP_SHIFT,
282 .wkdep_srcs = dsp_wkup_sleep_deps,
283 .sleepdep_srcs = dsp_wkup_sleep_deps,
284 .flags = CLKDM_CAN_HWSUP_SWSUP,
285};
286
287static struct clockdomain c2c_54xx_clkdm = {
288 .name = "c2c_clkdm",
289 .pwrdm = { .name = "core_pwrdm" },
290 .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
291 .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
292 .clkdm_offs = OMAP54XX_CM_CORE_CORE_C2C_CDOFFS,
293 .wkdep_srcs = c2c_wkup_sleep_deps,
294 .sleepdep_srcs = c2c_wkup_sleep_deps,
295 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
296};
297
298static struct clockdomain l4per_54xx_clkdm = {
299 .name = "l4per_clkdm",
300 .pwrdm = { .name = "core_pwrdm" },
301 .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
302 .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
303 .clkdm_offs = OMAP54XX_CM_CORE_CORE_L4PER_CDOFFS,
304 .dep_bit = OMAP54XX_L4PER_STATDEP_SHIFT,
305 .flags = CLKDM_CAN_HWSUP_SWSUP,
306};
307
308static struct clockdomain gpu_54xx_clkdm = {
309 .name = "gpu_clkdm",
310 .pwrdm = { .name = "gpu_pwrdm" },
311 .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
312 .cm_inst = OMAP54XX_CM_CORE_GPU_INST,
313 .clkdm_offs = OMAP54XX_CM_CORE_GPU_GPU_CDOFFS,
314 .dep_bit = OMAP54XX_GPU_STATDEP_SHIFT,
315 .wkdep_srcs = gpu_wkup_sleep_deps,
316 .sleepdep_srcs = gpu_wkup_sleep_deps,
317 .flags = CLKDM_CAN_HWSUP_SWSUP,
318};
319
320static struct clockdomain wkupaon_54xx_clkdm = {
321 .name = "wkupaon_clkdm",
322 .pwrdm = { .name = "wkupaon_pwrdm" },
323 .prcm_partition = OMAP54XX_PRM_PARTITION,
324 .cm_inst = OMAP54XX_PRM_WKUPAON_CM_INST,
325 .clkdm_offs = OMAP54XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS,
326 .dep_bit = OMAP54XX_WKUPAON_STATDEP_SHIFT,
327 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
328};
329
330static struct clockdomain mpu0_54xx_clkdm = {
331 .name = "mpu0_clkdm",
332 .pwrdm = { .name = "cpu0_pwrdm" },
333 .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION,
334 .cm_inst = OMAP54XX_PRCM_MPU_CM_C0_INST,
335 .clkdm_offs = OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS,
336 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
337};
338
339static struct clockdomain mpu1_54xx_clkdm = {
340 .name = "mpu1_clkdm",
341 .pwrdm = { .name = "cpu1_pwrdm" },
342 .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION,
343 .cm_inst = OMAP54XX_PRCM_MPU_CM_C1_INST,
344 .clkdm_offs = OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS,
345 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
346};
347
348static struct clockdomain coreaon_54xx_clkdm = {
349 .name = "coreaon_clkdm",
350 .pwrdm = { .name = "coreaon_pwrdm" },
351 .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
352 .cm_inst = OMAP54XX_CM_CORE_COREAON_INST,
353 .clkdm_offs = OMAP54XX_CM_CORE_COREAON_COREAON_CDOFFS,
354 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
355};
356
357static struct clockdomain mpu_54xx_clkdm = {
358 .name = "mpu_clkdm",
359 .pwrdm = { .name = "mpu_pwrdm" },
360 .prcm_partition = OMAP54XX_CM_CORE_AON_PARTITION,
361 .cm_inst = OMAP54XX_CM_CORE_AON_MPU_INST,
362 .clkdm_offs = OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS,
363 .wkdep_srcs = mpu_wkup_sleep_deps,
364 .sleepdep_srcs = mpu_wkup_sleep_deps,
365 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
366};
367
368static struct clockdomain l3init_54xx_clkdm = {
369 .name = "l3init_clkdm",
370 .pwrdm = { .name = "l3init_pwrdm" },
371 .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
372 .cm_inst = OMAP54XX_CM_CORE_L3INIT_INST,
373 .clkdm_offs = OMAP54XX_CM_CORE_L3INIT_L3INIT_CDOFFS,
374 .dep_bit = OMAP54XX_L3INIT_STATDEP_SHIFT,
375 .wkdep_srcs = l3init_wkup_sleep_deps,
376 .sleepdep_srcs = l3init_wkup_sleep_deps,
377 .flags = CLKDM_CAN_HWSUP_SWSUP,
378};
379
380static struct clockdomain dma_54xx_clkdm = {
381 .name = "dma_clkdm",
382 .pwrdm = { .name = "core_pwrdm" },
383 .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
384 .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
385 .clkdm_offs = OMAP54XX_CM_CORE_CORE_DMA_CDOFFS,
386 .wkdep_srcs = dma_wkup_sleep_deps,
387 .sleepdep_srcs = dma_wkup_sleep_deps,
388 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
389};
390
391static struct clockdomain l3instr_54xx_clkdm = {
392 .name = "l3instr_clkdm",
393 .pwrdm = { .name = "core_pwrdm" },
394 .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
395 .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
396 .clkdm_offs = OMAP54XX_CM_CORE_CORE_L3INSTR_CDOFFS,
397};
398
399static struct clockdomain emif_54xx_clkdm = {
400 .name = "emif_clkdm",
401 .pwrdm = { .name = "core_pwrdm" },
402 .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
403 .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
404 .clkdm_offs = OMAP54XX_CM_CORE_CORE_EMIF_CDOFFS,
405 .dep_bit = OMAP54XX_EMIF_STATDEP_SHIFT,
406 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
407};
408
409static struct clockdomain emu_54xx_clkdm = {
410 .name = "emu_clkdm",
411 .pwrdm = { .name = "emu_pwrdm" },
412 .prcm_partition = OMAP54XX_PRM_PARTITION,
413 .cm_inst = OMAP54XX_PRM_EMU_CM_INST,
414 .clkdm_offs = OMAP54XX_PRM_EMU_CM_EMU_CDOFFS,
415 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
416};
417
418static struct clockdomain cam_54xx_clkdm = {
419 .name = "cam_clkdm",
420 .pwrdm = { .name = "cam_pwrdm" },
421 .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
422 .cm_inst = OMAP54XX_CM_CORE_CAM_INST,
423 .clkdm_offs = OMAP54XX_CM_CORE_CAM_CAM_CDOFFS,
424 .wkdep_srcs = cam_wkup_sleep_deps,
425 .sleepdep_srcs = cam_wkup_sleep_deps,
426 .flags = CLKDM_CAN_HWSUP_SWSUP,
427};
428
429/* As clockdomains are added or removed above, this list must also be changed */
430static struct clockdomain *clockdomains_omap54xx[] __initdata = {
431 &l4sec_54xx_clkdm,
432 &iva_54xx_clkdm,
433 &mipiext_54xx_clkdm,
434 &l3main2_54xx_clkdm,
435 &l3main1_54xx_clkdm,
436 &custefuse_54xx_clkdm,
437 &ipu_54xx_clkdm,
438 &l4cfg_54xx_clkdm,
439 &abe_54xx_clkdm,
440 &dss_54xx_clkdm,
441 &dsp_54xx_clkdm,
442 &c2c_54xx_clkdm,
443 &l4per_54xx_clkdm,
444 &gpu_54xx_clkdm,
445 &wkupaon_54xx_clkdm,
446 &mpu0_54xx_clkdm,
447 &mpu1_54xx_clkdm,
448 &coreaon_54xx_clkdm,
449 &mpu_54xx_clkdm,
450 &l3init_54xx_clkdm,
451 &dma_54xx_clkdm,
452 &l3instr_54xx_clkdm,
453 &emif_54xx_clkdm,
454 &emu_54xx_clkdm,
455 &cam_54xx_clkdm,
456 NULL
457};
458
459void __init omap54xx_clockdomains_init(void)
460{
461 clkdm_register_platform_funcs(&omap4_clkdm_operations);
462 clkdm_register_clkdms(clockdomains_omap54xx);
463 clkdm_complete_init();
464}
diff --git a/arch/arm/mach-omap2/cm-regbits-54xx.h b/arch/arm/mach-omap2/cm-regbits-54xx.h
new file mode 100644
index 000000000000..e83b8e352b6e
--- /dev/null
+++ b/arch/arm/mach-omap2/cm-regbits-54xx.h
@@ -0,0 +1,1737 @@
1/*
2 * OMAP54xx Clock Management register bits
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley (paul@pwsan.com)
7 * Rajendra Nayak (rnayak@ti.com)
8 * Benoit Cousson (b-cousson@ti.com)
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H
22#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H
23
24/* Used by CM_DSP_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_MPU_DYNAMICDEP */
25#define OMAP54XX_ABE_DYNDEP_SHIFT 3
26#define OMAP54XX_ABE_DYNDEP_WIDTH 0x1
27#define OMAP54XX_ABE_DYNDEP_MASK (1 << 3)
28
29/*
30 * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
31 * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
32 */
33#define OMAP54XX_ABE_STATDEP_SHIFT 3
34#define OMAP54XX_ABE_STATDEP_WIDTH 0x1
35#define OMAP54XX_ABE_STATDEP_MASK (1 << 3)
36
37/*
38 * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_IVA,
39 * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO1,
40 * CM_AUTOIDLE_DPLL_UNIPRO2, CM_AUTOIDLE_DPLL_USB
41 */
42#define OMAP54XX_AUTO_DPLL_MODE_SHIFT 0
43#define OMAP54XX_AUTO_DPLL_MODE_WIDTH 0x3
44#define OMAP54XX_AUTO_DPLL_MODE_MASK (0x7 << 0)
45
46/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
47#define OMAP54XX_C2C_DYNDEP_SHIFT 18
48#define OMAP54XX_C2C_DYNDEP_WIDTH 0x1
49#define OMAP54XX_C2C_DYNDEP_MASK (1 << 18)
50
51/* Used by CM_MPU_STATICDEP */
52#define OMAP54XX_C2C_STATDEP_SHIFT 18
53#define OMAP54XX_C2C_STATDEP_WIDTH 0x1
54#define OMAP54XX_C2C_STATDEP_MASK (1 << 18)
55
56/* Used by CM_IPU_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
57#define OMAP54XX_CAM_DYNDEP_SHIFT 9
58#define OMAP54XX_CAM_DYNDEP_WIDTH 0x1
59#define OMAP54XX_CAM_DYNDEP_MASK (1 << 9)
60
61/*
62 * Used by CM_DMA_STATICDEP, CM_DSP_STATICDEP, CM_IPU_STATICDEP,
63 * CM_MPU_STATICDEP
64 */
65#define OMAP54XX_CAM_STATDEP_SHIFT 9
66#define OMAP54XX_CAM_STATDEP_WIDTH 0x1
67#define OMAP54XX_CAM_STATDEP_MASK (1 << 9)
68
69/* Used by CM_ABE_CLKSTCTRL */
70#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13
71#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_WIDTH 0x1
72#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_MASK (1 << 13)
73
74/* Used by CM_ABE_CLKSTCTRL */
75#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_SHIFT 12
76#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_WIDTH 0x1
77#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_MASK (1 << 12)
78
79/* Used by CM_ABE_CLKSTCTRL */
80#define OMAP54XX_CLKACTIVITY_ABE_GICLK_SHIFT 9
81#define OMAP54XX_CLKACTIVITY_ABE_GICLK_WIDTH 0x1
82#define OMAP54XX_CLKACTIVITY_ABE_GICLK_MASK (1 << 9)
83
84/* Used by CM_WKUPAON_CLKSTCTRL */
85#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_SHIFT 9
86#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_WIDTH 0x1
87#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_MASK (1 << 9)
88
89/* Used by CM_ABE_CLKSTCTRL */
90#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_SHIFT 11
91#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_WIDTH 0x1
92#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_MASK (1 << 11)
93
94/* Used by CM_ABE_CLKSTCTRL */
95#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_SHIFT 8
96#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_WIDTH 0x1
97#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8)
98
99/* Used by CM_DSS_CLKSTCTRL */
100#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_SHIFT 13
101#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_WIDTH 0x1
102#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_MASK (1 << 13)
103
104/* Used by CM_C2C_CLKSTCTRL */
105#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_SHIFT 9
106#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_WIDTH 0x1
107#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_MASK (1 << 9)
108
109/* Used by CM_C2C_CLKSTCTRL */
110#define OMAP54XX_CLKACTIVITY_C2C_GICLK_SHIFT 10
111#define OMAP54XX_CLKACTIVITY_C2C_GICLK_WIDTH 0x1
112#define OMAP54XX_CLKACTIVITY_C2C_GICLK_MASK (1 << 10)
113
114/* Used by CM_C2C_CLKSTCTRL */
115#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_SHIFT 8
116#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_WIDTH 0x1
117#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_MASK (1 << 8)
118
119/* Used by CM_CAM_CLKSTCTRL */
120#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_SHIFT 11
121#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_WIDTH 0x1
122#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_MASK (1 << 11)
123
124/* Used by CM_CAM_CLKSTCTRL */
125#define OMAP54XX_CLKACTIVITY_CAM_GCLK_SHIFT 8
126#define OMAP54XX_CLKACTIVITY_CAM_GCLK_WIDTH 0x1
127#define OMAP54XX_CLKACTIVITY_CAM_GCLK_MASK (1 << 8)
128
129/* Used by CM_CAM_CLKSTCTRL */
130#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_SHIFT 12
131#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_WIDTH 0x1
132#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_MASK (1 << 12)
133
134/* Used by CM_COREAON_CLKSTCTRL */
135#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_SHIFT 12
136#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_WIDTH 0x1
137#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_MASK (1 << 12)
138
139/* Used by CM_COREAON_CLKSTCTRL */
140#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_SHIFT 14
141#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_WIDTH 0x1
142#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_MASK (1 << 14)
143
144/* Used by CM_COREAON_CLKSTCTRL */
145#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_SHIFT 8
146#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_WIDTH 0x1
147#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_MASK (1 << 8)
148
149/* Used by CM_CAM_CLKSTCTRL */
150#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_SHIFT 9
151#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_WIDTH 0x1
152#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_MASK (1 << 9)
153
154/* Used by CM_CUSTEFUSE_CLKSTCTRL */
155#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_SHIFT 8
156#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_WIDTH 0x1
157#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_MASK (1 << 8)
158
159/* Used by CM_CUSTEFUSE_CLKSTCTRL */
160#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_SHIFT 9
161#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_WIDTH 0x1
162#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_MASK (1 << 9)
163
164/* Used by CM_EMIF_CLKSTCTRL */
165#define OMAP54XX_CLKACTIVITY_DLL_GCLK_SHIFT 9
166#define OMAP54XX_CLKACTIVITY_DLL_GCLK_WIDTH 0x1
167#define OMAP54XX_CLKACTIVITY_DLL_GCLK_MASK (1 << 9)
168
169/* Used by CM_DMA_CLKSTCTRL */
170#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_SHIFT 8
171#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_WIDTH 0x1
172#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_MASK (1 << 8)
173
174/* Used by CM_DSP_CLKSTCTRL */
175#define OMAP54XX_CLKACTIVITY_DSP_GCLK_SHIFT 8
176#define OMAP54XX_CLKACTIVITY_DSP_GCLK_WIDTH 0x1
177#define OMAP54XX_CLKACTIVITY_DSP_GCLK_MASK (1 << 8)
178
179/* Used by CM_DSS_CLKSTCTRL */
180#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_SHIFT 9
181#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_WIDTH 0x1
182#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_MASK (1 << 9)
183
184/* Used by CM_DSS_CLKSTCTRL */
185#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_SHIFT 8
186#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_WIDTH 0x1
187#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_MASK (1 << 8)
188
189/* Used by CM_DSS_CLKSTCTRL */
190#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_SHIFT 10
191#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_WIDTH 0x1
192#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_MASK (1 << 10)
193
194/* Used by CM_EMIF_CLKSTCTRL */
195#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_SHIFT 8
196#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_WIDTH 0x1
197#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_MASK (1 << 8)
198
199/* Used by CM_EMIF_CLKSTCTRL */
200#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_SHIFT 11
201#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_WIDTH 0x1
202#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_MASK (1 << 11)
203
204/* Used by CM_EMIF_CLKSTCTRL */
205#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_SHIFT 10
206#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_WIDTH 0x1
207#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_MASK (1 << 10)
208
209/* Used by CM_EMU_CLKSTCTRL */
210#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_SHIFT 8
211#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_WIDTH 0x1
212#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_MASK (1 << 8)
213
214/* Used by CM_CAM_CLKSTCTRL */
215#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_SHIFT 10
216#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_WIDTH 0x1
217#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_MASK (1 << 10)
218
219/* Used by CM_ABE_CLKSTCTRL */
220#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT 10
221#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_WIDTH 0x1
222#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_MASK (1 << 10)
223
224/* Used by CM_GPU_CLKSTCTRL */
225#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_SHIFT 9
226#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_WIDTH 0x1
227#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_MASK (1 << 9)
228
229/* Used by CM_GPU_CLKSTCTRL */
230#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_SHIFT 10
231#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_WIDTH 0x1
232#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_MASK (1 << 10)
233
234/* Used by CM_GPU_CLKSTCTRL */
235#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_SHIFT 8
236#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_WIDTH 0x1
237#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_MASK (1 << 8)
238
239/* Used by CM_DSS_CLKSTCTRL */
240#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_SHIFT 12
241#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_WIDTH 0x1
242#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_MASK (1 << 12)
243
244/* Used by CM_DSS_CLKSTCTRL */
245#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_SHIFT 11
246#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_WIDTH 0x1
247#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_MASK (1 << 11)
248
249/* Used by CM_L3INIT_CLKSTCTRL */
250#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20
251#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_WIDTH 0x1
252#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20)
253
254/* Used by CM_L3INIT_CLKSTCTRL */
255#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26
256#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_WIDTH 0x1
257#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26)
258
259/* Used by CM_L3INIT_CLKSTCTRL */
260#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21
261#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_WIDTH 0x1
262#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21)
263
264/* Used by CM_L3INIT_CLKSTCTRL */
265#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27
266#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_WIDTH 0x1
267#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27)
268
269/* Used by CM_L3INIT_CLKSTCTRL */
270#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_SHIFT 6
271#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_WIDTH 0x1
272#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_MASK (1 << 6)
273
274/* Used by CM_L3INIT_CLKSTCTRL */
275#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_SHIFT 7
276#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_WIDTH 0x1
277#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_MASK (1 << 7)
278
279/* Used by CM_L3INIT_CLKSTCTRL */
280#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_SHIFT 16
281#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_WIDTH 0x1
282#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_MASK (1 << 16)
283
284/* Used by CM_IPU_CLKSTCTRL */
285#define OMAP54XX_CLKACTIVITY_IPU_GCLK_SHIFT 8
286#define OMAP54XX_CLKACTIVITY_IPU_GCLK_WIDTH 0x1
287#define OMAP54XX_CLKACTIVITY_IPU_GCLK_MASK (1 << 8)
288
289/* Used by CM_IVA_CLKSTCTRL */
290#define OMAP54XX_CLKACTIVITY_IVA_GCLK_SHIFT 8
291#define OMAP54XX_CLKACTIVITY_IVA_GCLK_WIDTH 0x1
292#define OMAP54XX_CLKACTIVITY_IVA_GCLK_MASK (1 << 8)
293
294/* Used by CM_L3INIT_CLKSTCTRL */
295#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_SHIFT 12
296#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_WIDTH 0x1
297#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_MASK (1 << 12)
298
299/* Used by CM_L3INIT_CLKSTCTRL */
300#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_SHIFT 28
301#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_WIDTH 0x1
302#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_MASK (1 << 28)
303
304/* Used by CM_L3INIT_CLKSTCTRL */
305#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_SHIFT 29
306#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_WIDTH 0x1
307#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_MASK (1 << 29)
308
309/* Used by CM_L3INIT_CLKSTCTRL */
310#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_SHIFT 8
311#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_WIDTH 0x1
312#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_MASK (1 << 8)
313
314/* Used by CM_L3INIT_CLKSTCTRL */
315#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_SHIFT 9
316#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_WIDTH 0x1
317#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_MASK (1 << 9)
318
319/* Used by CM_L3INIT_CLKSTCTRL */
320#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_SHIFT 11
321#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_WIDTH 0x1
322#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_MASK (1 << 11)
323
324/* Used by CM_L3INSTR_CLKSTCTRL */
325#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_SHIFT 9
326#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_WIDTH 0x1
327#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_MASK (1 << 9)
328
329/* Used by CM_L3INSTR_CLKSTCTRL */
330#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_SHIFT 8
331#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_WIDTH 0x1
332#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_MASK (1 << 8)
333
334/* Used by CM_L3INSTR_CLKSTCTRL */
335#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_SHIFT 10
336#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_WIDTH 0x1
337#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_MASK (1 << 10)
338
339/* Used by CM_L3MAIN1_CLKSTCTRL */
340#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_SHIFT 8
341#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_WIDTH 0x1
342#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_MASK (1 << 8)
343
344/* Used by CM_L3MAIN2_CLKSTCTRL */
345#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_SHIFT 8
346#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_WIDTH 0x1
347#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_MASK (1 << 8)
348
349/* Used by CM_L4CFG_CLKSTCTRL */
350#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_SHIFT 8
351#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_WIDTH 0x1
352#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_MASK (1 << 8)
353
354/* Used by CM_L4PER_CLKSTCTRL */
355#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_SHIFT 8
356#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_WIDTH 0x1
357#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_MASK (1 << 8)
358
359/* Used by CM_L4SEC_CLKSTCTRL */
360#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_SHIFT 8
361#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_WIDTH 0x1
362#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_MASK (1 << 8)
363
364/* Used by CM_L4SEC_CLKSTCTRL */
365#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_SHIFT 9
366#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_WIDTH 0x1
367#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_MASK (1 << 9)
368
369/* Used by CM_MIPIEXT_CLKSTCTRL */
370#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_SHIFT 8
371#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_WIDTH 0x1
372#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_MASK (1 << 8)
373
374/* Used by CM_MIPIEXT_CLKSTCTRL */
375#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_SHIFT 11
376#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_WIDTH 0x1
377#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_MASK (1 << 11)
378
379/* Used by CM_L3INIT_CLKSTCTRL */
380#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_SHIFT 2
381#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_WIDTH 0x1
382#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_MASK (1 << 2)
383
384/* Used by CM_L3INIT_CLKSTCTRL */
385#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_SHIFT 17
386#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_WIDTH 0x1
387#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_MASK (1 << 17)
388
389/* Used by CM_L3INIT_CLKSTCTRL */
390#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_SHIFT 18
391#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_WIDTH 0x1
392#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_MASK (1 << 18)
393
394/* Used by CM_MPU_CLKSTCTRL */
395#define OMAP54XX_CLKACTIVITY_MPU_GCLK_SHIFT 8
396#define OMAP54XX_CLKACTIVITY_MPU_GCLK_WIDTH 0x1
397#define OMAP54XX_CLKACTIVITY_MPU_GCLK_MASK (1 << 8)
398
399/* Used by CM_ABE_CLKSTCTRL */
400#define OMAP54XX_CLKACTIVITY_PAD_CLKS_SHIFT 14
401#define OMAP54XX_CLKACTIVITY_PAD_CLKS_WIDTH 0x1
402#define OMAP54XX_CLKACTIVITY_PAD_CLKS_MASK (1 << 14)
403
404/* Used by CM_ABE_CLKSTCTRL */
405#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_SHIFT 15
406#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_WIDTH 0x1
407#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_MASK (1 << 15)
408
409/* Used by CM_L3INIT_CLKSTCTRL */
410#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_SHIFT 3
411#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_WIDTH 0x1
412#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_MASK (1 << 3)
413
414/* Used by CM_L3INIT_CLKSTCTRL */
415#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_SHIFT 4
416#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_WIDTH 0x1
417#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_MASK (1 << 4)
418
419/* Used by CM_L4PER_CLKSTCTRL */
420#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_SHIFT 15
421#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_WIDTH 0x1
422#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_MASK (1 << 15)
423
424/* Used by CM_L4PER_CLKSTCTRL */
425#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17
426#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_WIDTH 0x1
427#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17)
428
429/* Used by CM_L4PER_CLKSTCTRL */
430#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18
431#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_WIDTH 0x1
432#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18)
433
434/* Used by CM_L4PER_CLKSTCTRL */
435#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19
436#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_WIDTH 0x1
437#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19)
438
439/* Used by CM_L3INIT_CLKSTCTRL */
440#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_SHIFT 19
441#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_WIDTH 0x1
442#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_MASK (1 << 19)
443
444/* Used by CM_COREAON_CLKSTCTRL */
445#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_SHIFT 11
446#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_WIDTH 0x1
447#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_MASK (1 << 11)
448
449/* Used by CM_COREAON_CLKSTCTRL */
450#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_SHIFT 10
451#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_WIDTH 0x1
452#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_MASK (1 << 10)
453
454/* Used by CM_COREAON_CLKSTCTRL */
455#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_SHIFT 9
456#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_WIDTH 0x1
457#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_MASK (1 << 9)
458
459/* Used by CM_WKUPAON_CLKSTCTRL */
460#define OMAP54XX_CLKACTIVITY_SYS_CLK_SHIFT 8
461#define OMAP54XX_CLKACTIVITY_SYS_CLK_WIDTH 0x1
462#define OMAP54XX_CLKACTIVITY_SYS_CLK_MASK (1 << 8)
463
464/* Used by CM_WKUPAON_CLKSTCTRL */
465#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_SHIFT 15
466#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_WIDTH 0x1
467#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_MASK (1 << 15)
468
469/* Used by CM_WKUPAON_CLKSTCTRL */
470#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_SHIFT 14
471#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_WIDTH 0x1
472#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_MASK (1 << 14)
473
474/* Used by CM_L4PER_CLKSTCTRL */
475#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_SHIFT 9
476#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_WIDTH 0x1
477#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_MASK (1 << 9)
478
479/* Used by CM_L4PER_CLKSTCTRL */
480#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_SHIFT 10
481#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_WIDTH 0x1
482#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_MASK (1 << 10)
483
484/* Used by CM_L4PER_CLKSTCTRL */
485#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_SHIFT 11
486#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_WIDTH 0x1
487#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_MASK (1 << 11)
488
489/* Used by CM_L4PER_CLKSTCTRL */
490#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_SHIFT 12
491#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_WIDTH 0x1
492#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_MASK (1 << 12)
493
494/* Used by CM_L4PER_CLKSTCTRL */
495#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_SHIFT 13
496#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_WIDTH 0x1
497#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_MASK (1 << 13)
498
499/* Used by CM_L4PER_CLKSTCTRL */
500#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_SHIFT 14
501#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_WIDTH 0x1
502#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_MASK (1 << 14)
503
504/* Used by CM_L3INIT_CLKSTCTRL */
505#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22
506#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_WIDTH 0x1
507#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22)
508
509/* Used by CM_L3INIT_CLKSTCTRL */
510#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23
511#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_WIDTH 0x1
512#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23)
513
514/* Used by CM_L3INIT_CLKSTCTRL */
515#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24
516#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_WIDTH 0x1
517#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24)
518
519/* Used by CM_MIPIEXT_CLKSTCTRL */
520#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_SHIFT 10
521#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_WIDTH 0x1
522#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_MASK (1 << 10)
523
524/* Used by CM_MIPIEXT_CLKSTCTRL */
525#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_SHIFT 13
526#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_WIDTH 0x1
527#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_MASK (1 << 13)
528
529/* Used by CM_MIPIEXT_CLKSTCTRL */
530#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_SHIFT 12
531#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_WIDTH 0x1
532#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_MASK (1 << 12)
533
534/* Used by CM_L3INIT_CLKSTCTRL */
535#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_SHIFT 10
536#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_WIDTH 0x1
537#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_MASK (1 << 10)
538
539/* Used by CM_L3INIT_CLKSTCTRL */
540#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_SHIFT 13
541#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_WIDTH 0x1
542#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_MASK (1 << 13)
543
544/* Used by CM_L3INIT_CLKSTCTRL */
545#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_SHIFT 5
546#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_WIDTH 0x1
547#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_MASK (1 << 5)
548
549/* Used by CM_L3INIT_CLKSTCTRL */
550#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14
551#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_WIDTH 0x1
552#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14)
553
554/* Used by CM_L3INIT_CLKSTCTRL */
555#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15
556#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_WIDTH 0x1
557#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15)
558
559/* Used by CM_L3INIT_CLKSTCTRL */
560#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_SHIFT 31
561#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_WIDTH 0x1
562#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_MASK (1 << 31)
563
564/* Used by CM_L3INIT_CLKSTCTRL */
565#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30
566#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_WIDTH 0x1
567#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30)
568
569/* Used by CM_L3INIT_CLKSTCTRL */
570#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25
571#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_WIDTH 0x1
572#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25)
573
574/* Used by CM_WKUPAON_CLKSTCTRL */
575#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_SHIFT 11
576#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_WIDTH 0x1
577#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_MASK (1 << 11)
578
579/* Used by CM_WKUPAON_CLKSTCTRL */
580#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_SHIFT 12
581#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_WIDTH 0x1
582#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_MASK (1 << 12)
583
584/* Used by CM_WKUPAON_CLKSTCTRL */
585#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_SHIFT 13
586#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_WIDTH 0x1
587#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_MASK (1 << 13)
588
589/* Used by CM_COREAON_IO_SRCOMP_CLKCTRL, CM_WKUPAON_IO_SRCOMP_CLKCTRL */
590#define OMAP54XX_CLKEN_SRCOMP_FCLK_SHIFT 8
591#define OMAP54XX_CLKEN_SRCOMP_FCLK_WIDTH 0x1
592#define OMAP54XX_CLKEN_SRCOMP_FCLK_MASK (1 << 8)
593
594/*
595 * Used by CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL,
596 * CM_ABE_TIMER8_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL,
597 * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL,
598 * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL
599 */
600#define OMAP54XX_CLKSEL_SHIFT 24
601#define OMAP54XX_CLKSEL_WIDTH 0x1
602#define OMAP54XX_CLKSEL_MASK (1 << 24)
603
604/*
605 * Renamed from CLKSEL Used by CM_CLKSEL_ABE_DSS_SYS, CM_CLKSEL_ABE_PLL_REF,
606 * CM_CLKSEL_USB_60MHZ, CM_CLKSEL_WKUPAON
607 */
608#define OMAP54XX_CLKSEL_0_0_SHIFT 0
609#define OMAP54XX_CLKSEL_0_0_WIDTH 0x1
610#define OMAP54XX_CLKSEL_0_0_MASK (1 << 0)
611
612/* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */
613#define OMAP54XX_CLKSEL_0_1_SHIFT 0
614#define OMAP54XX_CLKSEL_0_1_WIDTH 0x2
615#define OMAP54XX_CLKSEL_0_1_MASK (0x3 << 0)
616
617/* Renamed from CLKSEL Used by CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL */
618#define OMAP54XX_CLKSEL_24_25_SHIFT 24
619#define OMAP54XX_CLKSEL_24_25_WIDTH 0x2
620#define OMAP54XX_CLKSEL_24_25_MASK (0x3 << 24)
621
622/* Used by CM_MPU_MPU_CLKCTRL */
623#define OMAP54XX_CLKSEL_ABE_DIV_MODE_SHIFT 26
624#define OMAP54XX_CLKSEL_ABE_DIV_MODE_WIDTH 0x1
625#define OMAP54XX_CLKSEL_ABE_DIV_MODE_MASK (1 << 26)
626
627/* Used by CM_ABE_AESS_CLKCTRL */
628#define OMAP54XX_CLKSEL_AESS_FCLK_SHIFT 24
629#define OMAP54XX_CLKSEL_AESS_FCLK_WIDTH 0x1
630#define OMAP54XX_CLKSEL_AESS_FCLK_MASK (1 << 24)
631
632/* Used by CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL */
633#define OMAP54XX_CLKSEL_DIV_SHIFT 25
634#define OMAP54XX_CLKSEL_DIV_WIDTH 0x1
635#define OMAP54XX_CLKSEL_DIV_MASK (1 << 25)
636
637/* Used by CM_MPU_MPU_CLKCTRL */
638#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_SHIFT 24
639#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_WIDTH 0x2
640#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_MASK (0x3 << 24)
641
642/* Used by CM_CAM_FDIF_CLKCTRL */
643#define OMAP54XX_CLKSEL_FCLK_SHIFT 24
644#define OMAP54XX_CLKSEL_FCLK_WIDTH 0x1
645#define OMAP54XX_CLKSEL_FCLK_MASK (1 << 24)
646
647/* Used by CM_GPU_GPU_CLKCTRL */
648#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_SHIFT 24
649#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_WIDTH 0x1
650#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_MASK (1 << 24)
651
652/* Used by CM_GPU_GPU_CLKCTRL */
653#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_SHIFT 25
654#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_WIDTH 0x1
655#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_MASK (1 << 25)
656
657/* Used by CM_GPU_GPU_CLKCTRL */
658#define OMAP54XX_CLKSEL_GPU_SYS_CLK_SHIFT 26
659#define OMAP54XX_CLKSEL_GPU_SYS_CLK_WIDTH 0x1
660#define OMAP54XX_CLKSEL_GPU_SYS_CLK_MASK (1 << 26)
661
662/*
663 * Used by CM_ABE_DMIC_CLKCTRL, CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL,
664 * CM_ABE_MCBSP2_CLKCTRL, CM_ABE_MCBSP3_CLKCTRL
665 */
666#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT 26
667#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH 0x2
668#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_MASK (0x3 << 26)
669
670/* Used by CM_CLKSEL_CORE */
671#define OMAP54XX_CLKSEL_L3_SHIFT 4
672#define OMAP54XX_CLKSEL_L3_WIDTH 0x1
673#define OMAP54XX_CLKSEL_L3_MASK (1 << 4)
674
675/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
676#define OMAP54XX_CLKSEL_L3_1_1_SHIFT 1
677#define OMAP54XX_CLKSEL_L3_1_1_WIDTH 0x1
678#define OMAP54XX_CLKSEL_L3_1_1_MASK (1 << 1)
679
680/* Used by CM_CLKSEL_CORE */
681#define OMAP54XX_CLKSEL_L4_SHIFT 8
682#define OMAP54XX_CLKSEL_L4_WIDTH 0x1
683#define OMAP54XX_CLKSEL_L4_MASK (1 << 8)
684
685/* Used by CM_EMIF_EMIF1_CLKCTRL */
686#define OMAP54XX_CLKSEL_LL_SHIFT 24
687#define OMAP54XX_CLKSEL_LL_WIDTH 0x1
688#define OMAP54XX_CLKSEL_LL_MASK (1 << 24)
689
690/* Used by CM_CLKSEL_ABE */
691#define OMAP54XX_CLKSEL_OPP_SHIFT 0
692#define OMAP54XX_CLKSEL_OPP_WIDTH 0x2
693#define OMAP54XX_CLKSEL_OPP_MASK (0x3 << 0)
694
695/* Renamed from CLKSEL_OPP Used by CM_L3INIT_UNIPRO2_CLKCTRL */
696#define OMAP54XX_CLKSEL_OPP_24_24_SHIFT 24
697#define OMAP54XX_CLKSEL_OPP_24_24_WIDTH 0x1
698#define OMAP54XX_CLKSEL_OPP_24_24_MASK (1 << 24)
699
700/*
701 * Used by CM_ABE_DMIC_CLKCTRL, CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL,
702 * CM_ABE_MCBSP2_CLKCTRL, CM_ABE_MCBSP3_CLKCTRL
703 */
704#define OMAP54XX_CLKSEL_SOURCE_SHIFT 24
705#define OMAP54XX_CLKSEL_SOURCE_WIDTH 0x2
706#define OMAP54XX_CLKSEL_SOURCE_MASK (0x3 << 24)
707
708/*
709 * Renamed from CLKSEL_SOURCE Used by CM_L3INIT_MMC1_CLKCTRL,
710 * CM_L3INIT_MMC2_CLKCTRL
711 */
712#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_SHIFT 24
713#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_WIDTH 0x1
714#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_MASK (1 << 24)
715
716/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
717#define OMAP54XX_CLKSEL_UTMI_P1_SHIFT 24
718#define OMAP54XX_CLKSEL_UTMI_P1_WIDTH 0x1
719#define OMAP54XX_CLKSEL_UTMI_P1_MASK (1 << 24)
720
721/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
722#define OMAP54XX_CLKSEL_UTMI_P2_SHIFT 25
723#define OMAP54XX_CLKSEL_UTMI_P2_WIDTH 0x1
724#define OMAP54XX_CLKSEL_UTMI_P2_MASK (1 << 25)
725
726/*
727 * Used by CM_DIV_H11_DPLL_CORE, CM_DIV_H11_DPLL_IVA, CM_DIV_H11_DPLL_PER,
728 * CM_DIV_H12_DPLL_CORE, CM_DIV_H12_DPLL_IVA, CM_DIV_H12_DPLL_PER,
729 * CM_DIV_H13_DPLL_CORE, CM_DIV_H13_DPLL_PER, CM_DIV_H14_DPLL_CORE,
730 * CM_DIV_H14_DPLL_PER, CM_DIV_H21_DPLL_CORE, CM_DIV_H22_DPLL_CORE,
731 * CM_DIV_H23_DPLL_CORE, CM_DIV_H24_DPLL_CORE, CM_DIV_M2_DPLL_ABE,
732 * CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER,
733 * CM_DIV_M2_DPLL_UNIPRO1, CM_DIV_M2_DPLL_UNIPRO2, CM_DIV_M2_DPLL_USB,
734 * CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER
735 */
736#define OMAP54XX_CLKST_SHIFT 9
737#define OMAP54XX_CLKST_WIDTH 0x1
738#define OMAP54XX_CLKST_MASK (1 << 9)
739
740/*
741 * Used by CM_ABE_CLKSTCTRL, CM_C2C_CLKSTCTRL, CM_CAM_CLKSTCTRL,
742 * CM_COREAON_CLKSTCTRL, CM_CUSTEFUSE_CLKSTCTRL, CM_DMA_CLKSTCTRL,
743 * CM_DSP_CLKSTCTRL, CM_DSS_CLKSTCTRL, CM_EMIF_CLKSTCTRL, CM_EMU_CLKSTCTRL,
744 * CM_GPU_CLKSTCTRL, CM_IPU_CLKSTCTRL, CM_IVA_CLKSTCTRL, CM_L3INIT_CLKSTCTRL,
745 * CM_L3INSTR_CLKSTCTRL, CM_L3MAIN1_CLKSTCTRL, CM_L3MAIN2_CLKSTCTRL,
746 * CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL, CM_L4SEC_CLKSTCTRL,
747 * CM_MIPIEXT_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_WKUPAON_CLKSTCTRL
748 */
749#define OMAP54XX_CLKTRCTRL_SHIFT 0
750#define OMAP54XX_CLKTRCTRL_WIDTH 0x2
751#define OMAP54XX_CLKTRCTRL_MASK (0x3 << 0)
752
753/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER */
754#define OMAP54XX_CLKX2ST_SHIFT 11
755#define OMAP54XX_CLKX2ST_WIDTH 0x1
756#define OMAP54XX_CLKX2ST_MASK (1 << 11)
757
758/* Used by CM_L4CFG_DYNAMICDEP */
759#define OMAP54XX_COREAON_DYNDEP_SHIFT 16
760#define OMAP54XX_COREAON_DYNDEP_WIDTH 0x1
761#define OMAP54XX_COREAON_DYNDEP_MASK (1 << 16)
762
763/* Used by CM_DSP_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */
764#define OMAP54XX_COREAON_STATDEP_SHIFT 16
765#define OMAP54XX_COREAON_STATDEP_WIDTH 0x1
766#define OMAP54XX_COREAON_STATDEP_MASK (1 << 16)
767
768/* Used by CM_L4CFG_DYNAMICDEP */
769#define OMAP54XX_CUSTEFUSE_DYNDEP_SHIFT 17
770#define OMAP54XX_CUSTEFUSE_DYNDEP_WIDTH 0x1
771#define OMAP54XX_CUSTEFUSE_DYNDEP_MASK (1 << 17)
772
773/* Used by CM_DSP_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */
774#define OMAP54XX_CUSTEFUSE_STATDEP_SHIFT 17
775#define OMAP54XX_CUSTEFUSE_STATDEP_WIDTH 0x1
776#define OMAP54XX_CUSTEFUSE_STATDEP_MASK (1 << 17)
777
778/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
779#define OMAP54XX_CUSTOM_SHIFT 6
780#define OMAP54XX_CUSTOM_WIDTH 0x2
781#define OMAP54XX_CUSTOM_MASK (0x3 << 6)
782
783/*
784 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
785 * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO1,
786 * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
787 */
788#define OMAP54XX_DCC_EN_SHIFT 22
789#define OMAP54XX_DCC_EN_WIDTH 0x1
790#define OMAP54XX_DCC_EN_MASK (1 << 22)
791
792/*
793 * Used by CM_CORE_AON_DEBUG_CM_CORE_AON_FD_TRANS,
794 * CM_CORE_AON_DEBUG_DSS_FD_TRANS, CM_CORE_AON_DEBUG_EMIF_FD_TRANS,
795 * CM_CORE_AON_DEBUG_L4SEC_FD_TRANS
796 */
797#define OMAP54XX_CM_DEBUG_OUT_SHIFT 0
798#define OMAP54XX_CM_DEBUG_OUT_WIDTH 0xd
799#define OMAP54XX_CM_DEBUG_OUT_MASK (0x1fff << 0)
800
801/*
802 * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_ABE_FD_TRANS,
803 * CM_CORE_AON_DEBUG_L3INIT_FD_TRANS, CM_CORE_AON_DEBUG_L4PER_FD_TRANS
804 */
805#define OMAP54XX_DEBUG_OUT_0_31_SHIFT 0
806#define OMAP54XX_DEBUG_OUT_0_31_WIDTH 0x20
807#define OMAP54XX_DEBUG_OUT_0_31_MASK (0xffffffff << 0)
808
809/*
810 * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_C2C_FD_TRANS,
811 * CM_CORE_AON_DEBUG_COREAON_FD_TRANS, CM_CORE_AON_DEBUG_L4CFG_FD_TRANS
812 */
813#define OMAP54XX_DEBUG_OUT_0_8_SHIFT 0
814#define OMAP54XX_DEBUG_OUT_0_8_WIDTH 0x9
815#define OMAP54XX_DEBUG_OUT_0_8_MASK (0x1ff << 0)
816
817/*
818 * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_CUSTEFUSE_FD_TRANS,
819 * CM_CORE_AON_DEBUG_DMA_FD_TRANS, CM_CORE_AON_DEBUG_L3MAIN1_FD_TRANS
820 */
821#define OMAP54XX_DEBUG_OUT_0_4_SHIFT 0
822#define OMAP54XX_DEBUG_OUT_0_4_WIDTH 0x5
823#define OMAP54XX_DEBUG_OUT_0_4_MASK (0x1f << 0)
824
825/*
826 * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_DSP_FD_TRANS,
827 * CM_CORE_AON_DEBUG_IPU_FD_TRANS, CM_CORE_AON_DEBUG_MPU_FD_TRANS
828 */
829#define OMAP54XX_DEBUG_OUT_0_5_SHIFT 0
830#define OMAP54XX_DEBUG_OUT_0_5_WIDTH 0x6
831#define OMAP54XX_DEBUG_OUT_0_5_MASK (0x3f << 0)
832
833/*
834 * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_CAM_FD_TRANS,
835 * CM_CORE_AON_DEBUG_MIPIEXT_FD_TRANS
836 */
837#define OMAP54XX_DEBUG_OUT_0_10_SHIFT 0
838#define OMAP54XX_DEBUG_OUT_0_10_WIDTH 0xb
839#define OMAP54XX_DEBUG_OUT_0_10_MASK (0x7ff << 0)
840
841/*
842 * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_IVA_FD_TRANS,
843 * CM_CORE_AON_DEBUG_L3MAIN2_FD_TRANS
844 */
845#define OMAP54XX_DEBUG_OUT_0_6_SHIFT 0
846#define OMAP54XX_DEBUG_OUT_0_6_WIDTH 0x7
847#define OMAP54XX_DEBUG_OUT_0_6_MASK (0x7f << 0)
848
849/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_ABE_FD_TRANS2 */
850#define OMAP54XX_DEBUG_OUT_0_19_SHIFT 0
851#define OMAP54XX_DEBUG_OUT_0_19_WIDTH 0x14
852#define OMAP54XX_DEBUG_OUT_0_19_MASK (0xfffff << 0)
853
854/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_GPU_FD_TRANS */
855#define OMAP54XX_DEBUG_OUT_0_9_SHIFT 0
856#define OMAP54XX_DEBUG_OUT_0_9_WIDTH 0xa
857#define OMAP54XX_DEBUG_OUT_0_9_MASK (0x3ff << 0)
858
859/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L3INIT_FD_TRANS2 */
860#define OMAP54XX_DEBUG_OUT_0_26_SHIFT 0
861#define OMAP54XX_DEBUG_OUT_0_26_WIDTH 0x1b
862#define OMAP54XX_DEBUG_OUT_0_26_MASK (0x7ffffff << 0)
863
864/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L3INSTR_FD_TRANS */
865#define OMAP54XX_DEBUG_OUT_0_13_SHIFT 0
866#define OMAP54XX_DEBUG_OUT_0_13_WIDTH 0xe
867#define OMAP54XX_DEBUG_OUT_0_13_MASK (0x3fff << 0)
868
869/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L4PER_FD_TRANS2 */
870#define OMAP54XX_DEBUG_OUT_0_21_SHIFT 0
871#define OMAP54XX_DEBUG_OUT_0_21_WIDTH 0x16
872#define OMAP54XX_DEBUG_OUT_0_21_MASK (0x3fffff << 0)
873
874/*
875 * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
876 * CM_SSC_DELTAMSTEP_DPLL_IVA, CM_SSC_DELTAMSTEP_DPLL_MPU,
877 * CM_SSC_DELTAMSTEP_DPLL_PER
878 */
879#define OMAP54XX_DELTAMSTEP_SHIFT 0
880#define OMAP54XX_DELTAMSTEP_WIDTH 0x14
881#define OMAP54XX_DELTAMSTEP_MASK (0xfffff << 0)
882
883/*
884 * Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_UNIPRO1,
885 * CM_SSC_DELTAMSTEP_DPLL_UNIPRO2, CM_SSC_DELTAMSTEP_DPLL_USB
886 */
887#define OMAP54XX_DELTAMSTEP_0_20_SHIFT 0
888#define OMAP54XX_DELTAMSTEP_0_20_WIDTH 0x15
889#define OMAP54XX_DELTAMSTEP_0_20_MASK (0x1fffff << 0)
890
891/*
892 * Used by CM_DIV_H11_DPLL_CORE, CM_DIV_H11_DPLL_IVA, CM_DIV_H11_DPLL_PER,
893 * CM_DIV_H12_DPLL_CORE, CM_DIV_H12_DPLL_IVA, CM_DIV_H12_DPLL_PER,
894 * CM_DIV_H13_DPLL_CORE, CM_DIV_H13_DPLL_PER, CM_DIV_H14_DPLL_CORE,
895 * CM_DIV_H14_DPLL_PER, CM_DIV_H21_DPLL_CORE, CM_DIV_H22_DPLL_CORE,
896 * CM_DIV_H23_DPLL_CORE, CM_DIV_H24_DPLL_CORE
897 */
898#define OMAP54XX_DIVHS_SHIFT 0
899#define OMAP54XX_DIVHS_WIDTH 0x6
900#define OMAP54XX_DIVHS_MASK (0x3f << 0)
901
902/*
903 * Renamed from DIVHS Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
904 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M3_DPLL_ABE,
905 * CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER
906 */
907#define OMAP54XX_DIVHS_0_4_SHIFT 0
908#define OMAP54XX_DIVHS_0_4_WIDTH 0x5
909#define OMAP54XX_DIVHS_0_4_MASK (0x1f << 0)
910
911/*
912 * Renamed from DIVHS Used by CM_DIV_M2_DPLL_UNIPRO1, CM_DIV_M2_DPLL_UNIPRO2,
913 * CM_DIV_M2_DPLL_USB
914 */
915#define OMAP54XX_DIVHS_0_6_SHIFT 0
916#define OMAP54XX_DIVHS_0_6_WIDTH 0x7
917#define OMAP54XX_DIVHS_0_6_MASK (0x7f << 0)
918
919/* Used by CM_DLL_CTRL */
920#define OMAP54XX_DLL_OVERRIDE_SHIFT 0
921#define OMAP54XX_DLL_OVERRIDE_WIDTH 0x1
922#define OMAP54XX_DLL_OVERRIDE_MASK (1 << 0)
923
924/* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */
925#define OMAP54XX_DLL_OVERRIDE_2_2_SHIFT 2
926#define OMAP54XX_DLL_OVERRIDE_2_2_WIDTH 0x1
927#define OMAP54XX_DLL_OVERRIDE_2_2_MASK (1 << 2)
928
929/* Used by CM_SHADOW_FREQ_CONFIG1 */
930#define OMAP54XX_DLL_RESET_SHIFT 3
931#define OMAP54XX_DLL_RESET_WIDTH 0x1
932#define OMAP54XX_DLL_RESET_MASK (1 << 3)
933
934/*
935 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
936 * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO1,
937 * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
938 */
939#define OMAP54XX_DPLL_BYP_CLKSEL_SHIFT 23
940#define OMAP54XX_DPLL_BYP_CLKSEL_WIDTH 0x1
941#define OMAP54XX_DPLL_BYP_CLKSEL_MASK (1 << 23)
942
943/* Used by CM_CLKSEL_DPLL_CORE */
944#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20
945#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_WIDTH 0x1
946#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20)
947
948/* Used by CM_SHADOW_FREQ_CONFIG1 */
949#define OMAP54XX_DPLL_CORE_DPLL_EN_SHIFT 8
950#define OMAP54XX_DPLL_CORE_DPLL_EN_WIDTH 0x3
951#define OMAP54XX_DPLL_CORE_DPLL_EN_MASK (0x7 << 8)
952
953/* Used by CM_SHADOW_FREQ_CONFIG2 */
954#define OMAP54XX_DPLL_CORE_H12_DIV_SHIFT 2
955#define OMAP54XX_DPLL_CORE_H12_DIV_WIDTH 0x6
956#define OMAP54XX_DPLL_CORE_H12_DIV_MASK (0x3f << 2)
957
958/* Used by CM_SHADOW_FREQ_CONFIG1 */
959#define OMAP54XX_DPLL_CORE_M2_DIV_SHIFT 11
960#define OMAP54XX_DPLL_CORE_M2_DIV_WIDTH 0x5
961#define OMAP54XX_DPLL_CORE_M2_DIV_MASK (0x1f << 11)
962
963/*
964 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
965 * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER
966 */
967#define OMAP54XX_DPLL_DIV_SHIFT 0
968#define OMAP54XX_DPLL_DIV_WIDTH 0x7
969#define OMAP54XX_DPLL_DIV_MASK (0x7f << 0)
970
971/*
972 * Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_UNIPRO1,
973 * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
974 */
975#define OMAP54XX_DPLL_DIV_0_7_SHIFT 0
976#define OMAP54XX_DPLL_DIV_0_7_WIDTH 0x8
977#define OMAP54XX_DPLL_DIV_0_7_MASK (0xff << 0)
978
979/*
980 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
981 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
982 */
983#define OMAP54XX_DPLL_DRIFTGUARD_EN_SHIFT 8
984#define OMAP54XX_DPLL_DRIFTGUARD_EN_WIDTH 0x1
985#define OMAP54XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
986
987/*
988 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
989 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
990 * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
991 */
992#define OMAP54XX_DPLL_EN_SHIFT 0
993#define OMAP54XX_DPLL_EN_WIDTH 0x3
994#define OMAP54XX_DPLL_EN_MASK (0x7 << 0)
995
996/*
997 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
998 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
999 */
1000#define OMAP54XX_DPLL_LPMODE_EN_SHIFT 10
1001#define OMAP54XX_DPLL_LPMODE_EN_WIDTH 0x1
1002#define OMAP54XX_DPLL_LPMODE_EN_MASK (1 << 10)
1003
1004/*
1005 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
1006 * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER
1007 */
1008#define OMAP54XX_DPLL_MULT_SHIFT 8
1009#define OMAP54XX_DPLL_MULT_WIDTH 0xb
1010#define OMAP54XX_DPLL_MULT_MASK (0x7ff << 8)
1011
1012/*
1013 * Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_UNIPRO1,
1014 * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
1015 */
1016#define OMAP54XX_DPLL_MULT_UNIPRO1_SHIFT 8
1017#define OMAP54XX_DPLL_MULT_UNIPRO1_WIDTH 0xc
1018#define OMAP54XX_DPLL_MULT_UNIPRO1_MASK (0xfff << 8)
1019
1020/*
1021 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
1022 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
1023 */
1024#define OMAP54XX_DPLL_REGM4XEN_SHIFT 11
1025#define OMAP54XX_DPLL_REGM4XEN_WIDTH 0x1
1026#define OMAP54XX_DPLL_REGM4XEN_MASK (1 << 11)
1027
1028/* Used by CM_CLKSEL_DPLL_UNIPRO1, CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB */
1029#define OMAP54XX_DPLL_SD_DIV_SHIFT 24
1030#define OMAP54XX_DPLL_SD_DIV_WIDTH 0x8
1031#define OMAP54XX_DPLL_SD_DIV_MASK (0xff << 24)
1032
1033/* Used by CM_CLKSEL_DPLL_UNIPRO1, CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB */
1034#define OMAP54XX_DPLL_SELFREQDCO_SHIFT 21
1035#define OMAP54XX_DPLL_SELFREQDCO_WIDTH 0x1
1036#define OMAP54XX_DPLL_SELFREQDCO_MASK (1 << 21)
1037
1038/*
1039 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
1040 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
1041 * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
1042 */
1043#define OMAP54XX_DPLL_SSC_ACK_SHIFT 13
1044#define OMAP54XX_DPLL_SSC_ACK_WIDTH 0x1
1045#define OMAP54XX_DPLL_SSC_ACK_MASK (1 << 13)
1046
1047/*
1048 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
1049 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
1050 * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
1051 */
1052#define OMAP54XX_DPLL_SSC_DOWNSPREAD_SHIFT 14
1053#define OMAP54XX_DPLL_SSC_DOWNSPREAD_WIDTH 0x1
1054#define OMAP54XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)
1055
1056/*
1057 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
1058 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
1059 * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
1060 */
1061#define OMAP54XX_DPLL_SSC_EN_SHIFT 12
1062#define OMAP54XX_DPLL_SSC_EN_WIDTH 0x1
1063#define OMAP54XX_DPLL_SSC_EN_MASK (1 << 12)
1064
1065/* Used by CM_L4CFG_DYNAMICDEP */
1066#define OMAP54XX_DSP_DYNDEP_SHIFT 1
1067#define OMAP54XX_DSP_DYNDEP_WIDTH 0x1
1068#define OMAP54XX_DSP_DYNDEP_MASK (1 << 1)
1069
1070/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */
1071#define OMAP54XX_DSP_STATDEP_SHIFT 1
1072#define OMAP54XX_DSP_STATDEP_WIDTH 0x1
1073#define OMAP54XX_DSP_STATDEP_MASK (1 << 1)
1074
1075/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
1076#define OMAP54XX_DSS_DYNDEP_SHIFT 8
1077#define OMAP54XX_DSS_DYNDEP_WIDTH 0x1
1078#define OMAP54XX_DSS_DYNDEP_MASK (1 << 8)
1079
1080/* Used by CM_DMA_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */
1081#define OMAP54XX_DSS_STATDEP_SHIFT 8
1082#define OMAP54XX_DSS_STATDEP_WIDTH 0x1
1083#define OMAP54XX_DSS_STATDEP_MASK (1 << 8)
1084
1085/*
1086 * Used by CM_C2C_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
1087 * CM_MIPIEXT_DYNAMICDEP, CM_MPU_DYNAMICDEP
1088 */
1089#define OMAP54XX_EMIF_DYNDEP_SHIFT 4
1090#define OMAP54XX_EMIF_DYNDEP_WIDTH 0x1
1091#define OMAP54XX_EMIF_DYNDEP_MASK (1 << 4)
1092
1093/*
1094 * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
1095 * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
1096 * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
1097 * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
1098 */
1099#define OMAP54XX_EMIF_STATDEP_SHIFT 4
1100#define OMAP54XX_EMIF_STATDEP_WIDTH 0x1
1101#define OMAP54XX_EMIF_STATDEP_MASK (1 << 4)
1102
1103/* Used by CM_SHADOW_FREQ_CONFIG1 */
1104#define OMAP54XX_FREQ_UPDATE_SHIFT 0
1105#define OMAP54XX_FREQ_UPDATE_WIDTH 0x1
1106#define OMAP54XX_FREQ_UPDATE_MASK (1 << 0)
1107
1108/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
1109#define OMAP54XX_FUNC_SHIFT 16
1110#define OMAP54XX_FUNC_WIDTH 0xc
1111#define OMAP54XX_FUNC_MASK (0xfff << 16)
1112
1113/* Used by CM_SHADOW_FREQ_CONFIG2 */
1114#define OMAP54XX_GPMC_FREQ_UPDATE_SHIFT 0
1115#define OMAP54XX_GPMC_FREQ_UPDATE_WIDTH 0x1
1116#define OMAP54XX_GPMC_FREQ_UPDATE_MASK (1 << 0)
1117
1118/* Used by CM_L3MAIN2_DYNAMICDEP */
1119#define OMAP54XX_GPU_DYNDEP_SHIFT 10
1120#define OMAP54XX_GPU_DYNDEP_WIDTH 0x1
1121#define OMAP54XX_GPU_DYNDEP_MASK (1 << 10)
1122
1123/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */
1124#define OMAP54XX_GPU_STATDEP_SHIFT 10
1125#define OMAP54XX_GPU_STATDEP_WIDTH 0x1
1126#define OMAP54XX_GPU_STATDEP_MASK (1 << 10)
1127
1128/*
1129 * Used by CM_ABE_AESS_CLKCTRL, CM_ABE_DMIC_CLKCTRL, CM_ABE_L4_ABE_CLKCTRL,
1130 * CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, CM_ABE_MCBSP2_CLKCTRL,
1131 * CM_ABE_MCBSP3_CLKCTRL, CM_ABE_MCPDM_CLKCTRL, CM_ABE_SLIMBUS1_CLKCTRL,
1132 * CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL,
1133 * CM_ABE_TIMER8_CLKCTRL, CM_ABE_WD_TIMER3_CLKCTRL, CM_C2C_C2C_CLKCTRL,
1134 * CM_C2C_C2C_OCP_FW_CLKCTRL, CM_C2C_MODEM_ICR_CLKCTRL, CM_CAM_CAL_CLKCTRL,
1135 * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CM_CORE_AON_PROFILING_CLKCTRL,
1136 * CM_CM_CORE_PROFILING_CLKCTRL, CM_COREAON_SMARTREFLEX_CORE_CLKCTRL,
1137 * CM_COREAON_SMARTREFLEX_MM_CLKCTRL, CM_COREAON_SMARTREFLEX_MPU_CLKCTRL,
1138 * CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL,
1139 * CM_DSP_DSP_CLKCTRL, CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL,
1140 * CM_EMIF_DMM_CLKCTRL, CM_EMIF_EMIF1_CLKCTRL, CM_EMIF_EMIF2_CLKCTRL,
1141 * CM_EMIF_EMIF_OCP_FW_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL,
1142 * CM_EMU_MPU_EMU_DBG_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL,
1143 * CM_IVA_IVA_CLKCTRL, CM_IVA_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL,
1144 * CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
1145 * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MPHY_UNIPRO2_CLKCTRL,
1146 * CM_L3INIT_OCP2SCP1_CLKCTRL, CM_L3INIT_OCP2SCP3_CLKCTRL,
1147 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_UNIPRO2_CLKCTRL,
1148 * CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_OTG_SS_CLKCTRL,
1149 * CM_L3INIT_USB_TLL_HS_CLKCTRL, CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL,
1150 * CM_L3INSTR_DLL_AGING_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
1151 * CM_L3INSTR_L3_MAIN_3_CLKCTRL, CM_L3INSTR_OCP_WP_NOC_CLKCTRL,
1152 * CM_L3MAIN1_L3_MAIN_1_CLKCTRL, CM_L3MAIN2_GPMC_CLKCTRL,
1153 * CM_L3MAIN2_L3_MAIN_2_CLKCTRL, CM_L3MAIN2_OCMC_RAM_CLKCTRL,
1154 * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL,
1155 * CM_L4CFG_OCP2SCP2_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
1156 * CM_L4CFG_SPINLOCK_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
1157 * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
1158 * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL,
1159 * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL,
1160 * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL,
1161 * CM_L4PER_L4_PER_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
1162 * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMC3_CLKCTRL,
1163 * CM_L4PER_MMC4_CLKCTRL, CM_L4PER_MMC5_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL,
1164 * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL,
1165 * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_L4PER_UART1_CLKCTRL,
1166 * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL,
1167 * CM_L4PER_UART5_CLKCTRL, CM_L4PER_UART6_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
1168 * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
1169 * CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_L4SEC_FPKA_CLKCTRL, CM_L4SEC_RNG_CLKCTRL,
1170 * CM_L4SEC_SHA2MD5_CLKCTRL, CM_MIPIEXT_LLI_CLKCTRL,
1171 * CM_MIPIEXT_LLI_OCP_FW_CLKCTRL, CM_MIPIEXT_MPHY_CLKCTRL, CM_MPU_MPU_CLKCTRL,
1172 * CM_MPU_MPU_MPU_DBG_CLKCTRL, CM_WKUPAON_COUNTER_32K_CLKCTRL,
1173 * CM_WKUPAON_GPIO1_CLKCTRL, CM_WKUPAON_KBD_CLKCTRL,
1174 * CM_WKUPAON_L4_WKUP_CLKCTRL, CM_WKUPAON_SAR_RAM_CLKCTRL,
1175 * CM_WKUPAON_TIMER12_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL,
1176 * CM_WKUPAON_WD_TIMER1_CLKCTRL, CM_WKUPAON_WD_TIMER2_CLKCTRL
1177 */
1178#define OMAP54XX_IDLEST_SHIFT 16
1179#define OMAP54XX_IDLEST_WIDTH 0x2
1180#define OMAP54XX_IDLEST_MASK (0x3 << 16)
1181
1182/* Used by CM_L3MAIN2_DYNAMICDEP */
1183#define OMAP54XX_IPU_DYNDEP_SHIFT 0
1184#define OMAP54XX_IPU_DYNDEP_WIDTH 0x1
1185#define OMAP54XX_IPU_DYNDEP_MASK (1 << 0)
1186
1187/* Used by CM_DMA_STATICDEP, CM_MPU_STATICDEP */
1188#define OMAP54XX_IPU_STATDEP_SHIFT 0
1189#define OMAP54XX_IPU_STATDEP_WIDTH 0x1
1190#define OMAP54XX_IPU_STATDEP_MASK (1 << 0)
1191
1192/* Used by CM_DSP_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP */
1193#define OMAP54XX_IVA_DYNDEP_SHIFT 2
1194#define OMAP54XX_IVA_DYNDEP_WIDTH 0x1
1195#define OMAP54XX_IVA_DYNDEP_MASK (1 << 2)
1196
1197/*
1198 * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
1199 * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
1200 * CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
1201 */
1202#define OMAP54XX_IVA_STATDEP_SHIFT 2
1203#define OMAP54XX_IVA_STATDEP_WIDTH 0x1
1204#define OMAP54XX_IVA_STATDEP_MASK (1 << 2)
1205
1206/* Used by CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
1207#define OMAP54XX_L3INIT_DYNDEP_SHIFT 7
1208#define OMAP54XX_L3INIT_DYNDEP_WIDTH 0x1
1209#define OMAP54XX_L3INIT_DYNDEP_MASK (1 << 7)
1210
1211/*
1212 * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
1213 * CM_IPU_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
1214 */
1215#define OMAP54XX_L3INIT_STATDEP_SHIFT 7
1216#define OMAP54XX_L3INIT_STATDEP_WIDTH 0x1
1217#define OMAP54XX_L3INIT_STATDEP_MASK (1 << 7)
1218
1219/*
1220 * Used by CM_DSP_DYNAMICDEP, CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP,
1221 * CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP
1222 */
1223#define OMAP54XX_L3MAIN1_DYNDEP_SHIFT 5
1224#define OMAP54XX_L3MAIN1_DYNDEP_WIDTH 0x1
1225#define OMAP54XX_L3MAIN1_DYNDEP_MASK (1 << 5)
1226
1227/*
1228 * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
1229 * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
1230 * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
1231 * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
1232 */
1233#define OMAP54XX_L3MAIN1_STATDEP_SHIFT 5
1234#define OMAP54XX_L3MAIN1_STATDEP_WIDTH 0x1
1235#define OMAP54XX_L3MAIN1_STATDEP_MASK (1 << 5)
1236
1237/*
1238 * Used by CM_C2C_DYNAMICDEP, CM_CAM_DYNAMICDEP, CM_DMA_DYNAMICDEP,
1239 * CM_DSS_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GPU_DYNAMICDEP, CM_IPU_DYNAMICDEP,
1240 * CM_IVA_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP,
1241 * CM_L4CFG_DYNAMICDEP, CM_L4SEC_DYNAMICDEP, CM_MIPIEXT_DYNAMICDEP
1242 */
1243#define OMAP54XX_L3MAIN2_DYNDEP_SHIFT 6
1244#define OMAP54XX_L3MAIN2_DYNDEP_WIDTH 0x1
1245#define OMAP54XX_L3MAIN2_DYNDEP_MASK (1 << 6)
1246
1247/*
1248 * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
1249 * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
1250 * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
1251 * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
1252 */
1253#define OMAP54XX_L3MAIN2_STATDEP_SHIFT 6
1254#define OMAP54XX_L3MAIN2_STATDEP_WIDTH 0x1
1255#define OMAP54XX_L3MAIN2_STATDEP_MASK (1 << 6)
1256
1257/* Used by CM_L3MAIN1_DYNAMICDEP */
1258#define OMAP54XX_L4CFG_DYNDEP_SHIFT 12
1259#define OMAP54XX_L4CFG_DYNDEP_WIDTH 0x1
1260#define OMAP54XX_L4CFG_DYNDEP_MASK (1 << 12)
1261
1262/*
1263 * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
1264 * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
1265 */
1266#define OMAP54XX_L4CFG_STATDEP_SHIFT 12
1267#define OMAP54XX_L4CFG_STATDEP_WIDTH 0x1
1268#define OMAP54XX_L4CFG_STATDEP_MASK (1 << 12)
1269
1270/* Used by CM_L3MAIN2_DYNAMICDEP */
1271#define OMAP54XX_L4PER_DYNDEP_SHIFT 13
1272#define OMAP54XX_L4PER_DYNDEP_WIDTH 0x1
1273#define OMAP54XX_L4PER_DYNDEP_MASK (1 << 13)
1274
1275/*
1276 * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
1277 * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
1278 * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
1279 */
1280#define OMAP54XX_L4PER_STATDEP_SHIFT 13
1281#define OMAP54XX_L4PER_STATDEP_WIDTH 0x1
1282#define OMAP54XX_L4PER_STATDEP_MASK (1 << 13)
1283
1284/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
1285#define OMAP54XX_L4SEC_DYNDEP_SHIFT 14
1286#define OMAP54XX_L4SEC_DYNDEP_WIDTH 0x1
1287#define OMAP54XX_L4SEC_DYNDEP_MASK (1 << 14)
1288
1289/*
1290 * Used by CM_DMA_STATICDEP, CM_IPU_STATICDEP, CM_L3INIT_STATICDEP,
1291 * CM_MPU_STATICDEP
1292 */
1293#define OMAP54XX_L4SEC_STATDEP_SHIFT 14
1294#define OMAP54XX_L4SEC_STATDEP_WIDTH 0x1
1295#define OMAP54XX_L4SEC_STATDEP_MASK (1 << 14)
1296
1297/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
1298#define OMAP54XX_MIPIEXT_DYNDEP_SHIFT 21
1299#define OMAP54XX_MIPIEXT_DYNDEP_WIDTH 0x1
1300#define OMAP54XX_MIPIEXT_DYNDEP_MASK (1 << 21)
1301
1302/* Used by CM_MPU_STATICDEP */
1303#define OMAP54XX_MIPIEXT_STATDEP_SHIFT 21
1304#define OMAP54XX_MIPIEXT_STATDEP_WIDTH 0x1
1305#define OMAP54XX_MIPIEXT_STATDEP_MASK (1 << 21)
1306
1307/*
1308 * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
1309 * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
1310 * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO1,
1311 * CM_SSC_MODFREQDIV_DPLL_UNIPRO2, CM_SSC_MODFREQDIV_DPLL_USB
1312 */
1313#define OMAP54XX_MODFREQDIV_EXPONENT_SHIFT 8
1314#define OMAP54XX_MODFREQDIV_EXPONENT_WIDTH 0x3
1315#define OMAP54XX_MODFREQDIV_EXPONENT_MASK (0x7 << 8)
1316
1317/*
1318 * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
1319 * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
1320 * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO1,
1321 * CM_SSC_MODFREQDIV_DPLL_UNIPRO2, CM_SSC_MODFREQDIV_DPLL_USB
1322 */
1323#define OMAP54XX_MODFREQDIV_MANTISSA_SHIFT 0
1324#define OMAP54XX_MODFREQDIV_MANTISSA_WIDTH 0x7
1325#define OMAP54XX_MODFREQDIV_MANTISSA_MASK (0x7f << 0)
1326
1327/*
1328 * Used by CM_ABE_AESS_CLKCTRL, CM_ABE_DMIC_CLKCTRL, CM_ABE_L4_ABE_CLKCTRL,
1329 * CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, CM_ABE_MCBSP2_CLKCTRL,
1330 * CM_ABE_MCBSP3_CLKCTRL, CM_ABE_MCPDM_CLKCTRL, CM_ABE_SLIMBUS1_CLKCTRL,
1331 * CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL,
1332 * CM_ABE_TIMER8_CLKCTRL, CM_ABE_WD_TIMER3_CLKCTRL, CM_C2C_C2C_CLKCTRL,
1333 * CM_C2C_C2C_OCP_FW_CLKCTRL, CM_C2C_MODEM_ICR_CLKCTRL, CM_CAM_CAL_CLKCTRL,
1334 * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CM_CORE_AON_PROFILING_CLKCTRL,
1335 * CM_CM_CORE_PROFILING_CLKCTRL, CM_COREAON_SMARTREFLEX_CORE_CLKCTRL,
1336 * CM_COREAON_SMARTREFLEX_MM_CLKCTRL, CM_COREAON_SMARTREFLEX_MPU_CLKCTRL,
1337 * CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL,
1338 * CM_DSP_DSP_CLKCTRL, CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL,
1339 * CM_EMIF_DMM_CLKCTRL, CM_EMIF_EMIF1_CLKCTRL, CM_EMIF_EMIF2_CLKCTRL,
1340 * CM_EMIF_EMIF_OCP_FW_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL,
1341 * CM_EMU_MPU_EMU_DBG_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL,
1342 * CM_IVA_IVA_CLKCTRL, CM_IVA_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL,
1343 * CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
1344 * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MPHY_UNIPRO2_CLKCTRL,
1345 * CM_L3INIT_OCP2SCP1_CLKCTRL, CM_L3INIT_OCP2SCP3_CLKCTRL,
1346 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_UNIPRO2_CLKCTRL,
1347 * CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_OTG_SS_CLKCTRL,
1348 * CM_L3INIT_USB_TLL_HS_CLKCTRL, CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL,
1349 * CM_L3INSTR_DLL_AGING_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
1350 * CM_L3INSTR_L3_MAIN_3_CLKCTRL, CM_L3INSTR_OCP_WP_NOC_CLKCTRL,
1351 * CM_L3MAIN1_L3_MAIN_1_CLKCTRL, CM_L3MAIN2_GPMC_CLKCTRL,
1352 * CM_L3MAIN2_L3_MAIN_2_CLKCTRL, CM_L3MAIN2_OCMC_RAM_CLKCTRL,
1353 * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL,
1354 * CM_L4CFG_OCP2SCP2_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
1355 * CM_L4CFG_SPINLOCK_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
1356 * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
1357 * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL,
1358 * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL,
1359 * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL,
1360 * CM_L4PER_L4_PER_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
1361 * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMC3_CLKCTRL,
1362 * CM_L4PER_MMC4_CLKCTRL, CM_L4PER_MMC5_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL,
1363 * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL,
1364 * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_L4PER_UART1_CLKCTRL,
1365 * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL,
1366 * CM_L4PER_UART5_CLKCTRL, CM_L4PER_UART6_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
1367 * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
1368 * CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_L4SEC_FPKA_CLKCTRL, CM_L4SEC_RNG_CLKCTRL,
1369 * CM_L4SEC_SHA2MD5_CLKCTRL, CM_MIPIEXT_LLI_CLKCTRL,
1370 * CM_MIPIEXT_LLI_OCP_FW_CLKCTRL, CM_MIPIEXT_MPHY_CLKCTRL, CM_MPU_MPU_CLKCTRL,
1371 * CM_MPU_MPU_MPU_DBG_CLKCTRL, CM_WKUPAON_COUNTER_32K_CLKCTRL,
1372 * CM_WKUPAON_GPIO1_CLKCTRL, CM_WKUPAON_KBD_CLKCTRL,
1373 * CM_WKUPAON_L4_WKUP_CLKCTRL, CM_WKUPAON_SAR_RAM_CLKCTRL,
1374 * CM_WKUPAON_TIMER12_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL,
1375 * CM_WKUPAON_WD_TIMER1_CLKCTRL, CM_WKUPAON_WD_TIMER2_CLKCTRL
1376 */
1377#define OMAP54XX_MODULEMODE_SHIFT 0
1378#define OMAP54XX_MODULEMODE_WIDTH 0x2
1379#define OMAP54XX_MODULEMODE_MASK (0x3 << 0)
1380
1381/* Used by CM_L4CFG_DYNAMICDEP */
1382#define OMAP54XX_MPU_DYNDEP_SHIFT 19
1383#define OMAP54XX_MPU_DYNDEP_WIDTH 0x1
1384#define OMAP54XX_MPU_DYNDEP_MASK (1 << 19)
1385
1386/* Used by CM_DSS_DSS_CLKCTRL */
1387#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_SHIFT 11
1388#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_WIDTH 0x1
1389#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_MASK (1 << 11)
1390
1391/* Renamed from OPTFCLKEN_32KHZ_CLK Used by CM_L3INIT_MMC1_CLKCTRL */
1392#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_SHIFT 8
1393#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_WIDTH 0x1
1394#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_MASK (1 << 8)
1395
1396/* Used by CM_DSS_DSS_CLKCTRL */
1397#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_SHIFT 9
1398#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_WIDTH 0x1
1399#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9)
1400
1401/* Used by CM_COREAON_USB_PHY_CORE_CLKCTRL */
1402#define OMAP54XX_OPTFCLKEN_CLK32K_SHIFT 8
1403#define OMAP54XX_OPTFCLKEN_CLK32K_WIDTH 0x1
1404#define OMAP54XX_OPTFCLKEN_CLK32K_MASK (1 << 8)
1405
1406/* Used by CM_CAM_ISS_CLKCTRL */
1407#define OMAP54XX_OPTFCLKEN_CTRLCLK_SHIFT 8
1408#define OMAP54XX_OPTFCLKEN_CTRLCLK_WIDTH 0x1
1409#define OMAP54XX_OPTFCLKEN_CTRLCLK_MASK (1 << 8)
1410
1411/*
1412 * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL,
1413 * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL,
1414 * CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL, CM_WKUPAON_GPIO1_CLKCTRL
1415 */
1416#define OMAP54XX_OPTFCLKEN_DBCLK_SHIFT 8
1417#define OMAP54XX_OPTFCLKEN_DBCLK_WIDTH 0x1
1418#define OMAP54XX_OPTFCLKEN_DBCLK_MASK (1 << 8)
1419
1420/* Used by CM_EMIF_EMIF_DLL_CLKCTRL */
1421#define OMAP54XX_OPTFCLKEN_DLL_CLK_SHIFT 8
1422#define OMAP54XX_OPTFCLKEN_DLL_CLK_WIDTH 0x1
1423#define OMAP54XX_OPTFCLKEN_DLL_CLK_MASK (1 << 8)
1424
1425/* Used by CM_DSS_DSS_CLKCTRL */
1426#define OMAP54XX_OPTFCLKEN_DSSCLK_SHIFT 8
1427#define OMAP54XX_OPTFCLKEN_DSSCLK_WIDTH 0x1
1428#define OMAP54XX_OPTFCLKEN_DSSCLK_MASK (1 << 8)
1429
1430/* Used by CM_ABE_SLIMBUS1_CLKCTRL */
1431#define OMAP54XX_OPTFCLKEN_FCLK0_SHIFT 8
1432#define OMAP54XX_OPTFCLKEN_FCLK0_WIDTH 0x1
1433#define OMAP54XX_OPTFCLKEN_FCLK0_MASK (1 << 8)
1434
1435/* Used by CM_ABE_SLIMBUS1_CLKCTRL */
1436#define OMAP54XX_OPTFCLKEN_FCLK1_SHIFT 9
1437#define OMAP54XX_OPTFCLKEN_FCLK1_WIDTH 0x1
1438#define OMAP54XX_OPTFCLKEN_FCLK1_MASK (1 << 9)
1439
1440/* Used by CM_ABE_SLIMBUS1_CLKCTRL */
1441#define OMAP54XX_OPTFCLKEN_FCLK2_SHIFT 10
1442#define OMAP54XX_OPTFCLKEN_FCLK2_WIDTH 0x1
1443#define OMAP54XX_OPTFCLKEN_FCLK2_MASK (1 << 10)
1444
1445/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1446#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_SHIFT 15
1447#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_WIDTH 0x1
1448#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_MASK (1 << 15)
1449
1450/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1451#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13
1452#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_WIDTH 0x1
1453#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13)
1454
1455/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1456#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14
1457#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_WIDTH 0x1
1458#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14)
1459
1460/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1461#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_SHIFT 7
1462#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_WIDTH 0x1
1463#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_MASK (1 << 7)
1464
1465/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1466#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11
1467#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_WIDTH 0x1
1468#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11)
1469
1470/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1471#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12
1472#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_WIDTH 0x1
1473#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12)
1474
1475/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1476#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_SHIFT 6
1477#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_WIDTH 0x1
1478#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_MASK (1 << 6)
1479
1480/* Used by CM_L3INIT_USB_OTG_SS_CLKCTRL */
1481#define OMAP54XX_OPTFCLKEN_REFCLK960M_SHIFT 8
1482#define OMAP54XX_OPTFCLKEN_REFCLK960M_WIDTH 0x1
1483#define OMAP54XX_OPTFCLKEN_REFCLK960M_MASK (1 << 8)
1484
1485/* Used by CM_L3INIT_SATA_CLKCTRL */
1486#define OMAP54XX_OPTFCLKEN_REF_CLK_SHIFT 8
1487#define OMAP54XX_OPTFCLKEN_REF_CLK_WIDTH 0x1
1488#define OMAP54XX_OPTFCLKEN_REF_CLK_MASK (1 << 8)
1489
1490/* Used by CM_WKUPAON_SCRM_CLKCTRL */
1491#define OMAP54XX_OPTFCLKEN_SCRM_CORE_SHIFT 8
1492#define OMAP54XX_OPTFCLKEN_SCRM_CORE_WIDTH 0x1
1493#define OMAP54XX_OPTFCLKEN_SCRM_CORE_MASK (1 << 8)
1494
1495/* Used by CM_WKUPAON_SCRM_CLKCTRL */
1496#define OMAP54XX_OPTFCLKEN_SCRM_PER_SHIFT 9
1497#define OMAP54XX_OPTFCLKEN_SCRM_PER_WIDTH 0x1
1498#define OMAP54XX_OPTFCLKEN_SCRM_PER_MASK (1 << 9)
1499
1500/* Used by CM_ABE_SLIMBUS1_CLKCTRL */
1501#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_SHIFT 11
1502#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_WIDTH 0x1
1503#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_MASK (1 << 11)
1504
1505/* Used by CM_DSS_DSS_CLKCTRL */
1506#define OMAP54XX_OPTFCLKEN_SYS_CLK_SHIFT 10
1507#define OMAP54XX_OPTFCLKEN_SYS_CLK_WIDTH 0x1
1508#define OMAP54XX_OPTFCLKEN_SYS_CLK_MASK (1 << 10)
1509
1510/* Used by CM_MIPIEXT_LLI_CLKCTRL */
1511#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_SHIFT 8
1512#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_WIDTH 0x1
1513#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_MASK (1 << 8)
1514
1515/* Used by CM_MIPIEXT_LLI_CLKCTRL */
1516#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_SHIFT 9
1517#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_WIDTH 0x1
1518#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_MASK (1 << 9)
1519
1520/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */
1521#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_SHIFT 8
1522#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_WIDTH 0x1
1523#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8)
1524
1525/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */
1526#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_SHIFT 9
1527#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_WIDTH 0x1
1528#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9)
1529
1530/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */
1531#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_SHIFT 10
1532#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_WIDTH 0x1
1533#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10)
1534
1535/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1536#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8
1537#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_WIDTH 0x1
1538#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8)
1539
1540/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1541#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9
1542#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_WIDTH 0x1
1543#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9)
1544
1545/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1546#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10
1547#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_WIDTH 0x1
1548#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10)
1549
1550/* Used by CM_CORE_AON_DEBUG_OUT, CM_CORE_DEBUG_OUT */
1551#define OMAP54XX_OUTPUT_SHIFT 0
1552#define OMAP54XX_OUTPUT_WIDTH 0x20
1553#define OMAP54XX_OUTPUT_MASK (0xffffffff << 0)
1554
1555/* Used by CM_CLKSEL_ABE */
1556#define OMAP54XX_PAD_CLKS_GATE_SHIFT 8
1557#define OMAP54XX_PAD_CLKS_GATE_WIDTH 0x1
1558#define OMAP54XX_PAD_CLKS_GATE_MASK (1 << 8)
1559
1560/* Used by CM_RESTORE_ST */
1561#define OMAP54XX_PHASE1_COMPLETED_SHIFT 0
1562#define OMAP54XX_PHASE1_COMPLETED_WIDTH 0x1
1563#define OMAP54XX_PHASE1_COMPLETED_MASK (1 << 0)
1564
1565/* Used by CM_RESTORE_ST */
1566#define OMAP54XX_PHASE2A_COMPLETED_SHIFT 1
1567#define OMAP54XX_PHASE2A_COMPLETED_WIDTH 0x1
1568#define OMAP54XX_PHASE2A_COMPLETED_MASK (1 << 1)
1569
1570/* Used by CM_RESTORE_ST */
1571#define OMAP54XX_PHASE2B_COMPLETED_SHIFT 2
1572#define OMAP54XX_PHASE2B_COMPLETED_WIDTH 0x1
1573#define OMAP54XX_PHASE2B_COMPLETED_MASK (1 << 2)
1574
1575/* Used by CM_DYN_DEP_PRESCAL */
1576#define OMAP54XX_PRESCAL_SHIFT 0
1577#define OMAP54XX_PRESCAL_WIDTH 0x6
1578#define OMAP54XX_PRESCAL_MASK (0x3f << 0)
1579
1580/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
1581#define OMAP54XX_R_RTL_SHIFT 11
1582#define OMAP54XX_R_RTL_WIDTH 0x5
1583#define OMAP54XX_R_RTL_MASK (0x1f << 11)
1584
1585/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_TLL_HS_CLKCTRL */
1586#define OMAP54XX_SAR_MODE_SHIFT 4
1587#define OMAP54XX_SAR_MODE_WIDTH 0x1
1588#define OMAP54XX_SAR_MODE_MASK (1 << 4)
1589
1590/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
1591#define OMAP54XX_SCHEME_SHIFT 30
1592#define OMAP54XX_SCHEME_WIDTH 0x2
1593#define OMAP54XX_SCHEME_MASK (0x3 << 30)
1594
1595/* Used by CM_L4CFG_DYNAMICDEP */
1596#define OMAP54XX_SDMA_DYNDEP_SHIFT 11
1597#define OMAP54XX_SDMA_DYNDEP_WIDTH 0x1
1598#define OMAP54XX_SDMA_DYNDEP_MASK (1 << 11)
1599
1600/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */
1601#define OMAP54XX_SDMA_STATDEP_SHIFT 11
1602#define OMAP54XX_SDMA_STATDEP_WIDTH 0x1
1603#define OMAP54XX_SDMA_STATDEP_MASK (1 << 11)
1604
1605/* Used by CM_CORE_AON_DEBUG_CFG */
1606#define OMAP54XX_SEL0_SHIFT 0
1607#define OMAP54XX_SEL0_WIDTH 0x7
1608#define OMAP54XX_SEL0_MASK (0x7f << 0)
1609
1610/* Renamed from SEL0 Used by CM_CORE_DEBUG_CFG */
1611#define OMAP54XX_SEL0_0_7_SHIFT 0
1612#define OMAP54XX_SEL0_0_7_WIDTH 0x8
1613#define OMAP54XX_SEL0_0_7_MASK (0xff << 0)
1614
1615/* Used by CM_CORE_AON_DEBUG_CFG */
1616#define OMAP54XX_SEL1_SHIFT 8
1617#define OMAP54XX_SEL1_WIDTH 0x7
1618#define OMAP54XX_SEL1_MASK (0x7f << 8)
1619
1620/* Renamed from SEL1 Used by CM_CORE_DEBUG_CFG */
1621#define OMAP54XX_SEL1_CORE_DEBUG_CFG_SHIFT 8
1622#define OMAP54XX_SEL1_CORE_DEBUG_CFG_WIDTH 0x8
1623#define OMAP54XX_SEL1_CORE_DEBUG_CFG_MASK (0xff << 8)
1624
1625/* Used by CM_CORE_AON_DEBUG_CFG */
1626#define OMAP54XX_SEL2_SHIFT 16
1627#define OMAP54XX_SEL2_WIDTH 0x7
1628#define OMAP54XX_SEL2_MASK (0x7f << 16)
1629
1630/* Renamed from SEL2 Used by CM_CORE_DEBUG_CFG */
1631#define OMAP54XX_SEL2_CORE_DEBUG_CFG_SHIFT 16
1632#define OMAP54XX_SEL2_CORE_DEBUG_CFG_WIDTH 0x8
1633#define OMAP54XX_SEL2_CORE_DEBUG_CFG_MASK (0xff << 16)
1634
1635/* Used by CM_CORE_AON_DEBUG_CFG */
1636#define OMAP54XX_SEL3_SHIFT 24
1637#define OMAP54XX_SEL3_WIDTH 0x7
1638#define OMAP54XX_SEL3_MASK (0x7f << 24)
1639
1640/* Renamed from SEL3 Used by CM_CORE_DEBUG_CFG */
1641#define OMAP54XX_SEL3_CORE_DEBUG_CFG_SHIFT 24
1642#define OMAP54XX_SEL3_CORE_DEBUG_CFG_WIDTH 0x8
1643#define OMAP54XX_SEL3_CORE_DEBUG_CFG_MASK (0xff << 24)
1644
1645/* Used by CM_CLKSEL_ABE */
1646#define OMAP54XX_SLIMBUS1_CLK_GATE_SHIFT 10
1647#define OMAP54XX_SLIMBUS1_CLK_GATE_WIDTH 0x1
1648#define OMAP54XX_SLIMBUS1_CLK_GATE_MASK (1 << 10)
1649
1650/*
1651 * Used by CM_ABE_AESS_CLKCTRL, CM_C2C_C2C_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
1652 * CM_CAM_ISS_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL, CM_DSP_DSP_CLKCTRL,
1653 * CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL,
1654 * CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL, CM_IVA_IVA_CLKCTRL,
1655 * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_IEEE1500_2_OCP_CLKCTRL,
1656 * CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_SATA_CLKCTRL,
1657 * CM_L3INIT_UNIPRO2_CLKCTRL, CM_L3INIT_USB_HOST_HS_CLKCTRL,
1658 * CM_L3INIT_USB_OTG_SS_CLKCTRL, CM_L4SEC_DMA_CRYPTO_CLKCTRL,
1659 * CM_MIPIEXT_LLI_CLKCTRL, CM_MPU_MPU_CLKCTRL
1660 */
1661#define OMAP54XX_STBYST_SHIFT 18
1662#define OMAP54XX_STBYST_WIDTH 0x1
1663#define OMAP54XX_STBYST_MASK (1 << 18)
1664
1665/*
1666 * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA,
1667 * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1,
1668 * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB
1669 */
1670#define OMAP54XX_ST_DPLL_CLK_SHIFT 0
1671#define OMAP54XX_ST_DPLL_CLK_WIDTH 0x1
1672#define OMAP54XX_ST_DPLL_CLK_MASK (1 << 0)
1673
1674/*
1675 * Used by CM_CLKDCOLDO_DPLL_UNIPRO1, CM_CLKDCOLDO_DPLL_UNIPRO2,
1676 * CM_CLKDCOLDO_DPLL_USB
1677 */
1678#define OMAP54XX_ST_DPLL_CLKDCOLDO_SHIFT 9
1679#define OMAP54XX_ST_DPLL_CLKDCOLDO_WIDTH 0x1
1680#define OMAP54XX_ST_DPLL_CLKDCOLDO_MASK (1 << 9)
1681
1682/*
1683 * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA,
1684 * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1,
1685 * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB
1686 */
1687#define OMAP54XX_ST_DPLL_INIT_SHIFT 4
1688#define OMAP54XX_ST_DPLL_INIT_WIDTH 0x1
1689#define OMAP54XX_ST_DPLL_INIT_MASK (1 << 4)
1690
1691/*
1692 * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA,
1693 * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1,
1694 * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB
1695 */
1696#define OMAP54XX_ST_DPLL_MODE_SHIFT 1
1697#define OMAP54XX_ST_DPLL_MODE_WIDTH 0x3
1698#define OMAP54XX_ST_DPLL_MODE_MASK (0x7 << 1)
1699
1700/* Used by CM_CLKSEL_SYS */
1701#define OMAP54XX_SYS_CLKSEL_SHIFT 0
1702#define OMAP54XX_SYS_CLKSEL_WIDTH 0x3
1703#define OMAP54XX_SYS_CLKSEL_MASK (0x7 << 0)
1704
1705/*
1706 * Used by CM_C2C_DYNAMICDEP, CM_DSP_DYNAMICDEP, CM_EMU_DYNAMICDEP,
1707 * CM_IPU_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP,
1708 * CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP, CM_MIPIEXT_DYNAMICDEP,
1709 * CM_MPU_DYNAMICDEP
1710 */
1711#define OMAP54XX_WINDOWSIZE_SHIFT 24
1712#define OMAP54XX_WINDOWSIZE_WIDTH 0x4
1713#define OMAP54XX_WINDOWSIZE_MASK (0xf << 24)
1714
1715/* Used by CM_L3MAIN1_DYNAMICDEP */
1716#define OMAP54XX_WKUPAON_DYNDEP_SHIFT 15
1717#define OMAP54XX_WKUPAON_DYNDEP_WIDTH 0x1
1718#define OMAP54XX_WKUPAON_DYNDEP_MASK (1 << 15)
1719
1720/*
1721 * Used by CM_DMA_STATICDEP, CM_DSP_STATICDEP, CM_IPU_STATICDEP,
1722 * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP
1723 */
1724#define OMAP54XX_WKUPAON_STATDEP_SHIFT 15
1725#define OMAP54XX_WKUPAON_STATDEP_WIDTH 0x1
1726#define OMAP54XX_WKUPAON_STATDEP_MASK (1 << 15)
1727
1728/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
1729#define OMAP54XX_X_MAJOR_SHIFT 8
1730#define OMAP54XX_X_MAJOR_WIDTH 0x3
1731#define OMAP54XX_X_MAJOR_MASK (0x7 << 8)
1732
1733/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
1734#define OMAP54XX_Y_MINOR_SHIFT 0
1735#define OMAP54XX_Y_MINOR_WIDTH 0x6
1736#define OMAP54XX_Y_MINOR_MASK (0x3f << 0)
1737#endif
diff --git a/arch/arm/mach-omap2/cm1_44xx.h b/arch/arm/mach-omap2/cm1_44xx.h
index 1bc00dc4876c..5ae8fe39d6ee 100644
--- a/arch/arm/mach-omap2/cm1_44xx.h
+++ b/arch/arm/mach-omap2/cm1_44xx.h
@@ -25,6 +25,8 @@
25#ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H 25#ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
26#define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H 26#define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
27 27
28#include "cm_44xx_54xx.h"
29
28/* CM1 base address */ 30/* CM1 base address */
29#define OMAP4430_CM1_BASE 0x4a004000 31#define OMAP4430_CM1_BASE 0x4a004000
30 32
@@ -217,9 +219,4 @@
217#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088 219#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088
218#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088) 220#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088)
219 221
220/* Function prototypes */
221extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
222extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);
223extern u32 omap4_cm1_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
224
225#endif 222#endif
diff --git a/arch/arm/mach-omap2/cm1_54xx.h b/arch/arm/mach-omap2/cm1_54xx.h
new file mode 100644
index 000000000000..90b3348e6672
--- /dev/null
+++ b/arch/arm/mach-omap2/cm1_54xx.h
@@ -0,0 +1,213 @@
1/*
2 * OMAP54xx CM1 instance offset macros
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley (paul@pwsan.com)
7 * Rajendra Nayak (rnayak@ti.com)
8 * Benoit Cousson (b-cousson@ti.com)
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 *
20 */
21
22#ifndef __ARCH_ARM_MACH_OMAP2_CM1_54XX_H
23#define __ARCH_ARM_MACH_OMAP2_CM1_54XX_H
24
25#include "cm_44xx_54xx.h"
26
27/* CM1 base address */
28#define OMAP54XX_CM_CORE_AON_BASE 0x4a004000
29
30#define OMAP54XX_CM_CORE_AON_REGADDR(inst, reg) \
31 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE + (inst) + (reg))
32
33/* CM_CORE_AON instances */
34#define OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST 0x0000
35#define OMAP54XX_CM_CORE_AON_CKGEN_INST 0x0100
36#define OMAP54XX_CM_CORE_AON_MPU_INST 0x0300
37#define OMAP54XX_CM_CORE_AON_DSP_INST 0x0400
38#define OMAP54XX_CM_CORE_AON_ABE_INST 0x0500
39#define OMAP54XX_CM_CORE_AON_RESTORE_INST 0x0e00
40#define OMAP54XX_CM_CORE_AON_INSTR_INST 0x0f00
41
42/* CM_CORE_AON clockdomain register offsets (from instance start) */
43#define OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS 0x0000
44#define OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS 0x0000
45#define OMAP54XX_CM_CORE_AON_ABE_ABE_CDOFFS 0x0000
46
47/* CM_CORE_AON */
48
49/* CM_CORE_AON.OCP_SOCKET_CM_CORE_AON register offsets */
50#define OMAP54XX_REVISION_CM_CORE_AON_OFFSET 0x0000
51#define OMAP54XX_CM_CM_CORE_AON_PROFILING_CLKCTRL_OFFSET 0x0040
52#define OMAP54XX_CM_CM_CORE_AON_PROFILING_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST, 0x0040)
53#define OMAP54XX_CM_CORE_AON_DEBUG_CFG_OFFSET 0x0080
54#define OMAP54XX_CM_CORE_AON_DEBUG_OUT_OFFSET 0x0084
55#define OMAP54XX_CM_CORE_AON_DEBUG_MPU_FD_TRANS_OFFSET 0x0090
56#define OMAP54XX_CM_CORE_AON_DEBUG_DSP_FD_TRANS_OFFSET 0x0094
57#define OMAP54XX_CM_CORE_AON_DEBUG_ABE_FD_TRANS_OFFSET 0x0098
58#define OMAP54XX_CM_CORE_AON_DEBUG_ABE_FD_TRANS2_OFFSET 0x009c
59#define OMAP54XX_CM_CORE_AON_DEBUG_CM_CORE_AON_FD_TRANS_OFFSET 0x00a0
60#define OMAP54XX_CM_CORE_AON_DEBUG_C2C_FD_TRANS_OFFSET 0x00a4
61#define OMAP54XX_CM_CORE_AON_DEBUG_CAM_FD_TRANS_OFFSET 0x00a8
62#define OMAP54XX_CM_CORE_AON_DEBUG_COREAON_FD_TRANS_OFFSET 0x00ac
63#define OMAP54XX_CM_CORE_AON_DEBUG_CUSTEFUSE_FD_TRANS_OFFSET 0x00b0
64#define OMAP54XX_CM_CORE_AON_DEBUG_DMA_FD_TRANS_OFFSET 0x00b4
65#define OMAP54XX_CM_CORE_AON_DEBUG_DSS_FD_TRANS_OFFSET 0x00b8
66#define OMAP54XX_CM_CORE_AON_DEBUG_EMIF_FD_TRANS_OFFSET 0x00bc
67#define OMAP54XX_CM_CORE_AON_DEBUG_GPU_FD_TRANS_OFFSET 0x00c0
68#define OMAP54XX_CM_CORE_AON_DEBUG_IPU_FD_TRANS_OFFSET 0x00c4
69#define OMAP54XX_CM_CORE_AON_DEBUG_IVA_FD_TRANS_OFFSET 0x00c8
70#define OMAP54XX_CM_CORE_AON_DEBUG_L3INIT_FD_TRANS_OFFSET 0x00cc
71#define OMAP54XX_CM_CORE_AON_DEBUG_L3INIT_FD_TRANS2_OFFSET 0x00d0
72#define OMAP54XX_CM_CORE_AON_DEBUG_L3INSTR_FD_TRANS_OFFSET 0x00d4
73#define OMAP54XX_CM_CORE_AON_DEBUG_L3MAIN1_FD_TRANS_OFFSET 0x00d8
74#define OMAP54XX_CM_CORE_AON_DEBUG_L3MAIN2_FD_TRANS_OFFSET 0x00dc
75#define OMAP54XX_CM_CORE_AON_DEBUG_L4CFG_FD_TRANS_OFFSET 0x00e0
76#define OMAP54XX_CM_CORE_AON_DEBUG_L4PER_FD_TRANS_OFFSET 0x00e4
77#define OMAP54XX_CM_CORE_AON_DEBUG_L4PER_FD_TRANS2_OFFSET 0x00e8
78#define OMAP54XX_CM_CORE_AON_DEBUG_L4SEC_FD_TRANS_OFFSET 0x00ec
79#define OMAP54XX_CM_CORE_AON_DEBUG_MIPIEXT_FD_TRANS_OFFSET 0x00f0
80
81/* CM_CORE_AON.CKGEN_CM_CORE_AON register offsets */
82#define OMAP54XX_CM_CLKSEL_CORE_OFFSET 0x0000
83#define OMAP54XX_CM_CLKSEL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0000)
84#define OMAP54XX_CM_CLKSEL_ABE_OFFSET 0x0008
85#define OMAP54XX_CM_CLKSEL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0008)
86#define OMAP54XX_CM_DLL_CTRL_OFFSET 0x0010
87#define OMAP54XX_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020
88#define OMAP54XX_CM_CLKMODE_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0020)
89#define OMAP54XX_CM_IDLEST_DPLL_CORE_OFFSET 0x0024
90#define OMAP54XX_CM_IDLEST_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0024)
91#define OMAP54XX_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028
92#define OMAP54XX_CM_AUTOIDLE_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0028)
93#define OMAP54XX_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c
94#define OMAP54XX_CM_CLKSEL_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x002c)
95#define OMAP54XX_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030
96#define OMAP54XX_CM_DIV_M2_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0030)
97#define OMAP54XX_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034
98#define OMAP54XX_CM_DIV_M3_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0034)
99#define OMAP54XX_CM_DIV_H11_DPLL_CORE_OFFSET 0x0038
100#define OMAP54XX_CM_DIV_H11_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0038)
101#define OMAP54XX_CM_DIV_H12_DPLL_CORE_OFFSET 0x003c
102#define OMAP54XX_CM_DIV_H12_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x003c)
103#define OMAP54XX_CM_DIV_H13_DPLL_CORE_OFFSET 0x0040
104#define OMAP54XX_CM_DIV_H13_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0040)
105#define OMAP54XX_CM_DIV_H14_DPLL_CORE_OFFSET 0x0044
106#define OMAP54XX_CM_DIV_H14_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0044)
107#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048
108#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c
109#define OMAP54XX_CM_DIV_H21_DPLL_CORE_OFFSET 0x0050
110#define OMAP54XX_CM_DIV_H21_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0050)
111#define OMAP54XX_CM_DIV_H22_DPLL_CORE_OFFSET 0x0054
112#define OMAP54XX_CM_DIV_H22_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0054)
113#define OMAP54XX_CM_DIV_H23_DPLL_CORE_OFFSET 0x0058
114#define OMAP54XX_CM_DIV_H23_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0058)
115#define OMAP54XX_CM_DIV_H24_DPLL_CORE_OFFSET 0x005c
116#define OMAP54XX_CM_DIV_H24_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x005c)
117#define OMAP54XX_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060
118#define OMAP54XX_CM_CLKMODE_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0060)
119#define OMAP54XX_CM_IDLEST_DPLL_MPU_OFFSET 0x0064
120#define OMAP54XX_CM_IDLEST_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0064)
121#define OMAP54XX_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068
122#define OMAP54XX_CM_AUTOIDLE_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0068)
123#define OMAP54XX_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c
124#define OMAP54XX_CM_CLKSEL_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x006c)
125#define OMAP54XX_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070
126#define OMAP54XX_CM_DIV_M2_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0070)
127#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088
128#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c
129#define OMAP54XX_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c
130#define OMAP54XX_CM_BYPCLK_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x009c)
131#define OMAP54XX_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0
132#define OMAP54XX_CM_CLKMODE_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a0)
133#define OMAP54XX_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4
134#define OMAP54XX_CM_IDLEST_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a4)
135#define OMAP54XX_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8
136#define OMAP54XX_CM_AUTOIDLE_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a8)
137#define OMAP54XX_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac
138#define OMAP54XX_CM_CLKSEL_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00ac)
139#define OMAP54XX_CM_DIV_H11_DPLL_IVA_OFFSET 0x00b8
140#define OMAP54XX_CM_DIV_H11_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00b8)
141#define OMAP54XX_CM_DIV_H12_DPLL_IVA_OFFSET 0x00bc
142#define OMAP54XX_CM_DIV_H12_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00bc)
143#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8
144#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc
145#define OMAP54XX_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc
146#define OMAP54XX_CM_BYPCLK_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00dc)
147#define OMAP54XX_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0
148#define OMAP54XX_CM_CLKMODE_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e0)
149#define OMAP54XX_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4
150#define OMAP54XX_CM_IDLEST_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e4)
151#define OMAP54XX_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8
152#define OMAP54XX_CM_AUTOIDLE_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e8)
153#define OMAP54XX_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec
154#define OMAP54XX_CM_CLKSEL_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00ec)
155#define OMAP54XX_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0
156#define OMAP54XX_CM_DIV_M2_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00f0)
157#define OMAP54XX_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4
158#define OMAP54XX_CM_DIV_M3_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00f4)
159#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108
160#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c
161#define OMAP54XX_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160
162#define OMAP54XX_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164
163#define OMAP54XX_CM_DYN_DEP_PRESCAL_OFFSET 0x0170
164#define OMAP54XX_CM_RESTORE_ST_OFFSET 0x0180
165
166/* CM_CORE_AON.MPU_CM_CORE_AON register offsets */
167#define OMAP54XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000
168#define OMAP54XX_CM_MPU_STATICDEP_OFFSET 0x0004
169#define OMAP54XX_CM_MPU_DYNAMICDEP_OFFSET 0x0008
170#define OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020
171#define OMAP54XX_CM_MPU_MPU_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_MPU_INST, 0x0020)
172#define OMAP54XX_CM_MPU_MPU_MPU_DBG_CLKCTRL_OFFSET 0x0028
173#define OMAP54XX_CM_MPU_MPU_MPU_DBG_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_MPU_INST, 0x0028)
174
175/* CM_CORE_AON.DSP_CM_CORE_AON register offsets */
176#define OMAP54XX_CM_DSP_CLKSTCTRL_OFFSET 0x0000
177#define OMAP54XX_CM_DSP_STATICDEP_OFFSET 0x0004
178#define OMAP54XX_CM_DSP_DYNAMICDEP_OFFSET 0x0008
179#define OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET 0x0020
180#define OMAP54XX_CM_DSP_DSP_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_DSP_INST, 0x0020)
181
182/* CM_CORE_AON.ABE_CM_CORE_AON register offsets */
183#define OMAP54XX_CM_ABE_CLKSTCTRL_OFFSET 0x0000
184#define OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET 0x0020
185#define OMAP54XX_CM_ABE_L4_ABE_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0020)
186#define OMAP54XX_CM_ABE_AESS_CLKCTRL_OFFSET 0x0028
187#define OMAP54XX_CM_ABE_AESS_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0028)
188#define OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET 0x0030
189#define OMAP54XX_CM_ABE_MCPDM_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0030)
190#define OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET 0x0038
191#define OMAP54XX_CM_ABE_DMIC_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0038)
192#define OMAP54XX_CM_ABE_MCASP_CLKCTRL_OFFSET 0x0040
193#define OMAP54XX_CM_ABE_MCASP_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0040)
194#define OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048
195#define OMAP54XX_CM_ABE_MCBSP1_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0048)
196#define OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050
197#define OMAP54XX_CM_ABE_MCBSP2_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0050)
198#define OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058
199#define OMAP54XX_CM_ABE_MCBSP3_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0058)
200#define OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL_OFFSET 0x0060
201#define OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0060)
202#define OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET 0x0068
203#define OMAP54XX_CM_ABE_TIMER5_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0068)
204#define OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET 0x0070
205#define OMAP54XX_CM_ABE_TIMER6_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0070)
206#define OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET 0x0078
207#define OMAP54XX_CM_ABE_TIMER7_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0078)
208#define OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET 0x0080
209#define OMAP54XX_CM_ABE_TIMER8_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0080)
210#define OMAP54XX_CM_ABE_WD_TIMER3_CLKCTRL_OFFSET 0x0088
211#define OMAP54XX_CM_ABE_WD_TIMER3_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0088)
212
213#endif
diff --git a/arch/arm/mach-omap2/cm2_44xx.h b/arch/arm/mach-omap2/cm2_44xx.h
index b9de72da1a8e..ee5136d7cdda 100644
--- a/arch/arm/mach-omap2/cm2_44xx.h
+++ b/arch/arm/mach-omap2/cm2_44xx.h
@@ -25,6 +25,8 @@
25#ifndef __ARCH_ARM_MACH_OMAP2_CM2_44XX_H 25#ifndef __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
26#define __ARCH_ARM_MACH_OMAP2_CM2_44XX_H 26#define __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
27 27
28#include "cm_44xx_54xx.h"
29
28/* CM2 base address */ 30/* CM2 base address */
29#define OMAP4430_CM2_BASE 0x4a008000 31#define OMAP4430_CM2_BASE 0x4a008000
30 32
@@ -449,9 +451,4 @@
449#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020 451#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020
450#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020) 452#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020)
451 453
452/* Function prototypes */
453extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx);
454extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx);
455extern u32 omap4_cm2_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
456
457#endif 454#endif
diff --git a/arch/arm/mach-omap2/cm2_54xx.h b/arch/arm/mach-omap2/cm2_54xx.h
new file mode 100644
index 000000000000..2683231b299b
--- /dev/null
+++ b/arch/arm/mach-omap2/cm2_54xx.h
@@ -0,0 +1,389 @@
1/*
2 * OMAP54xx CM2 instance offset macros
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley (paul@pwsan.com)
7 * Rajendra Nayak (rnayak@ti.com)
8 * Benoit Cousson (b-cousson@ti.com)
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#ifndef __ARCH_ARM_MACH_OMAP2_CM2_54XX_H
22#define __ARCH_ARM_MACH_OMAP2_CM2_54XX_H
23
24#include "cm_44xx_54xx.h"
25
26/* CM2 base address */
27#define OMAP54XX_CM_CORE_BASE 0x4a008000
28
29#define OMAP54XX_CM_CORE_REGADDR(inst, reg) \
30 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE + (inst) + (reg))
31
32/* CM_CORE instances */
33#define OMAP54XX_CM_CORE_OCP_SOCKET_INST 0x0000
34#define OMAP54XX_CM_CORE_CKGEN_INST 0x0100
35#define OMAP54XX_CM_CORE_COREAON_INST 0x0600
36#define OMAP54XX_CM_CORE_CORE_INST 0x0700
37#define OMAP54XX_CM_CORE_IVA_INST 0x1200
38#define OMAP54XX_CM_CORE_CAM_INST 0x1300
39#define OMAP54XX_CM_CORE_DSS_INST 0x1400
40#define OMAP54XX_CM_CORE_GPU_INST 0x1500
41#define OMAP54XX_CM_CORE_L3INIT_INST 0x1600
42#define OMAP54XX_CM_CORE_CUSTEFUSE_INST 0x1700
43#define OMAP54XX_CM_CORE_RESTORE_INST 0x1e00
44#define OMAP54XX_CM_CORE_INSTR_INST 0x1f00
45
46/* CM_CORE clockdomain register offsets (from instance start) */
47#define OMAP54XX_CM_CORE_COREAON_COREAON_CDOFFS 0x0000
48#define OMAP54XX_CM_CORE_CORE_L3MAIN1_CDOFFS 0x0000
49#define OMAP54XX_CM_CORE_CORE_L3MAIN2_CDOFFS 0x0100
50#define OMAP54XX_CM_CORE_CORE_IPU_CDOFFS 0x0200
51#define OMAP54XX_CM_CORE_CORE_DMA_CDOFFS 0x0300
52#define OMAP54XX_CM_CORE_CORE_EMIF_CDOFFS 0x0400
53#define OMAP54XX_CM_CORE_CORE_C2C_CDOFFS 0x0500
54#define OMAP54XX_CM_CORE_CORE_L4CFG_CDOFFS 0x0600
55#define OMAP54XX_CM_CORE_CORE_L3INSTR_CDOFFS 0x0700
56#define OMAP54XX_CM_CORE_CORE_MIPIEXT_CDOFFS 0x0800
57#define OMAP54XX_CM_CORE_CORE_L4PER_CDOFFS 0x0900
58#define OMAP54XX_CM_CORE_CORE_L4SEC_CDOFFS 0x0a80
59#define OMAP54XX_CM_CORE_IVA_IVA_CDOFFS 0x0000
60#define OMAP54XX_CM_CORE_CAM_CAM_CDOFFS 0x0000
61#define OMAP54XX_CM_CORE_DSS_DSS_CDOFFS 0x0000
62#define OMAP54XX_CM_CORE_GPU_GPU_CDOFFS 0x0000
63#define OMAP54XX_CM_CORE_L3INIT_L3INIT_CDOFFS 0x0000
64#define OMAP54XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS 0x0000
65
66/* CM_CORE */
67
68/* CM_CORE.OCP_SOCKET_CM_CORE register offsets */
69#define OMAP54XX_REVISION_CM_CORE_OFFSET 0x0000
70#define OMAP54XX_CM_CM_CORE_PROFILING_CLKCTRL_OFFSET 0x0040
71#define OMAP54XX_CM_CM_CORE_PROFILING_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_OCP_SOCKET_INST, 0x0040)
72#define OMAP54XX_CM_CORE_DEBUG_CFG_OFFSET 0x0080
73#define OMAP54XX_CM_CORE_DEBUG_OUT_OFFSET 0x0084
74
75/* CM_CORE.CKGEN_CM_CORE register offsets */
76#define OMAP54XX_CM_CLKSEL_USB_60MHZ_OFFSET 0x0004
77#define OMAP54XX_CM_CLKSEL_USB_60MHZ OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0004)
78#define OMAP54XX_CM_CLKMODE_DPLL_PER_OFFSET 0x0040
79#define OMAP54XX_CM_CLKMODE_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0040)
80#define OMAP54XX_CM_IDLEST_DPLL_PER_OFFSET 0x0044
81#define OMAP54XX_CM_IDLEST_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0044)
82#define OMAP54XX_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0048
83#define OMAP54XX_CM_AUTOIDLE_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0048)
84#define OMAP54XX_CM_CLKSEL_DPLL_PER_OFFSET 0x004c
85#define OMAP54XX_CM_CLKSEL_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x004c)
86#define OMAP54XX_CM_DIV_M2_DPLL_PER_OFFSET 0x0050
87#define OMAP54XX_CM_DIV_M2_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0050)
88#define OMAP54XX_CM_DIV_M3_DPLL_PER_OFFSET 0x0054
89#define OMAP54XX_CM_DIV_M3_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0054)
90#define OMAP54XX_CM_DIV_H11_DPLL_PER_OFFSET 0x0058
91#define OMAP54XX_CM_DIV_H11_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0058)
92#define OMAP54XX_CM_DIV_H12_DPLL_PER_OFFSET 0x005c
93#define OMAP54XX_CM_DIV_H12_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x005c)
94#define OMAP54XX_CM_DIV_H13_DPLL_PER_OFFSET 0x0060
95#define OMAP54XX_CM_DIV_H13_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0060)
96#define OMAP54XX_CM_DIV_H14_DPLL_PER_OFFSET 0x0064
97#define OMAP54XX_CM_DIV_H14_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0064)
98#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068
99#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c
100#define OMAP54XX_CM_CLKMODE_DPLL_USB_OFFSET 0x0080
101#define OMAP54XX_CM_CLKMODE_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0080)
102#define OMAP54XX_CM_IDLEST_DPLL_USB_OFFSET 0x0084
103#define OMAP54XX_CM_IDLEST_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0084)
104#define OMAP54XX_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0088
105#define OMAP54XX_CM_AUTOIDLE_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0088)
106#define OMAP54XX_CM_CLKSEL_DPLL_USB_OFFSET 0x008c
107#define OMAP54XX_CM_CLKSEL_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x008c)
108#define OMAP54XX_CM_DIV_M2_DPLL_USB_OFFSET 0x0090
109#define OMAP54XX_CM_DIV_M2_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0090)
110#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8
111#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00ac
112#define OMAP54XX_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4
113#define OMAP54XX_CM_CLKDCOLDO_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00b4)
114#define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO2_OFFSET 0x00c0
115#define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c0)
116#define OMAP54XX_CM_IDLEST_DPLL_UNIPRO2_OFFSET 0x00c4
117#define OMAP54XX_CM_IDLEST_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c4)
118#define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO2_OFFSET 0x00c8
119#define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c8)
120#define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO2_OFFSET 0x00cc
121#define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00cc)
122#define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO2_OFFSET 0x00d0
123#define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00d0)
124#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_UNIPRO2_OFFSET 0x00e8
125#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_UNIPRO2_OFFSET 0x00ec
126#define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO2_OFFSET 0x00f4
127#define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00f4)
128#define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO1_OFFSET 0x0100
129#define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0100)
130#define OMAP54XX_CM_IDLEST_DPLL_UNIPRO1_OFFSET 0x0104
131#define OMAP54XX_CM_IDLEST_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0104)
132#define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO1_OFFSET 0x0108
133#define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0108)
134#define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO1_OFFSET 0x010c
135#define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x010c)
136#define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO1_OFFSET 0x0110
137#define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0110)
138#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_UNIPRO1_OFFSET 0x0128
139#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_UNIPRO1_OFFSET 0x012c
140#define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO1_OFFSET 0x0134
141#define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0134)
142
143/* CM_CORE.COREAON_CM_CORE register offsets */
144#define OMAP54XX_CM_COREAON_CLKSTCTRL_OFFSET 0x0000
145#define OMAP54XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET 0x0028
146#define OMAP54XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0028)
147#define OMAP54XX_CM_COREAON_SMARTREFLEX_MM_CLKCTRL_OFFSET 0x0030
148#define OMAP54XX_CM_COREAON_SMARTREFLEX_MM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0030)
149#define OMAP54XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET 0x0038
150#define OMAP54XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0038)
151#define OMAP54XX_CM_COREAON_USB_PHY_CORE_CLKCTRL_OFFSET 0x0040
152#define OMAP54XX_CM_COREAON_USB_PHY_CORE_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0040)
153#define OMAP54XX_CM_COREAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0050
154#define OMAP54XX_CM_COREAON_IO_SRCOMP_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0050)
155
156/* CM_CORE.CORE_CM_CORE register offsets */
157#define OMAP54XX_CM_L3MAIN1_CLKSTCTRL_OFFSET 0x0000
158#define OMAP54XX_CM_L3MAIN1_DYNAMICDEP_OFFSET 0x0008
159#define OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET 0x0020
160#define OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0020)
161#define OMAP54XX_CM_L3MAIN2_CLKSTCTRL_OFFSET 0x0100
162#define OMAP54XX_CM_L3MAIN2_DYNAMICDEP_OFFSET 0x0108
163#define OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET 0x0120
164#define OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0120)
165#define OMAP54XX_CM_L3MAIN2_GPMC_CLKCTRL_OFFSET 0x0128
166#define OMAP54XX_CM_L3MAIN2_GPMC_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0128)
167#define OMAP54XX_CM_L3MAIN2_OCMC_RAM_CLKCTRL_OFFSET 0x0130
168#define OMAP54XX_CM_L3MAIN2_OCMC_RAM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0130)
169#define OMAP54XX_CM_IPU_CLKSTCTRL_OFFSET 0x0200
170#define OMAP54XX_CM_IPU_STATICDEP_OFFSET 0x0204
171#define OMAP54XX_CM_IPU_DYNAMICDEP_OFFSET 0x0208
172#define OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET 0x0220
173#define OMAP54XX_CM_IPU_IPU_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0220)
174#define OMAP54XX_CM_DMA_CLKSTCTRL_OFFSET 0x0300
175#define OMAP54XX_CM_DMA_STATICDEP_OFFSET 0x0304
176#define OMAP54XX_CM_DMA_DYNAMICDEP_OFFSET 0x0308
177#define OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET 0x0320
178#define OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0320)
179#define OMAP54XX_CM_EMIF_CLKSTCTRL_OFFSET 0x0400
180#define OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET 0x0420
181#define OMAP54XX_CM_EMIF_DMM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0420)
182#define OMAP54XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET 0x0428
183#define OMAP54XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0428)
184#define OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET 0x0430
185#define OMAP54XX_CM_EMIF_EMIF1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0430)
186#define OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET 0x0438
187#define OMAP54XX_CM_EMIF_EMIF2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0438)
188#define OMAP54XX_CM_EMIF_EMIF_DLL_CLKCTRL_OFFSET 0x0440
189#define OMAP54XX_CM_EMIF_EMIF_DLL_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0440)
190#define OMAP54XX_CM_C2C_CLKSTCTRL_OFFSET 0x0500
191#define OMAP54XX_CM_C2C_STATICDEP_OFFSET 0x0504
192#define OMAP54XX_CM_C2C_DYNAMICDEP_OFFSET 0x0508
193#define OMAP54XX_CM_C2C_C2C_CLKCTRL_OFFSET 0x0520
194#define OMAP54XX_CM_C2C_C2C_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0520)
195#define OMAP54XX_CM_C2C_MODEM_ICR_CLKCTRL_OFFSET 0x0528
196#define OMAP54XX_CM_C2C_MODEM_ICR_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0528)
197#define OMAP54XX_CM_C2C_C2C_OCP_FW_CLKCTRL_OFFSET 0x0530
198#define OMAP54XX_CM_C2C_C2C_OCP_FW_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0530)
199#define OMAP54XX_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600
200#define OMAP54XX_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608
201#define OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620
202#define OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0620)
203#define OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET 0x0628
204#define OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0628)
205#define OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET 0x0630
206#define OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0630)
207#define OMAP54XX_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638
208#define OMAP54XX_CM_L4CFG_SAR_ROM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0638)
209#define OMAP54XX_CM_L4CFG_OCP2SCP2_CLKCTRL_OFFSET 0x0640
210#define OMAP54XX_CM_L4CFG_OCP2SCP2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0640)
211#define OMAP54XX_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700
212#define OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET 0x0720
213#define OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0720)
214#define OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728
215#define OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0728)
216#define OMAP54XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET 0x0740
217#define OMAP54XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0740)
218#define OMAP54XX_CM_L3INSTR_DLL_AGING_CLKCTRL_OFFSET 0x0748
219#define OMAP54XX_CM_L3INSTR_DLL_AGING_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0748)
220#define OMAP54XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL_OFFSET 0x0750
221#define OMAP54XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0750)
222#define OMAP54XX_CM_MIPIEXT_CLKSTCTRL_OFFSET 0x0800
223#define OMAP54XX_CM_MIPIEXT_STATICDEP_OFFSET 0x0804
224#define OMAP54XX_CM_MIPIEXT_DYNAMICDEP_OFFSET 0x0808
225#define OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL_OFFSET 0x0820
226#define OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0820)
227#define OMAP54XX_CM_MIPIEXT_LLI_OCP_FW_CLKCTRL_OFFSET 0x0828
228#define OMAP54XX_CM_MIPIEXT_LLI_OCP_FW_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0828)
229#define OMAP54XX_CM_MIPIEXT_MPHY_CLKCTRL_OFFSET 0x0830
230#define OMAP54XX_CM_MIPIEXT_MPHY_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0830)
231#define OMAP54XX_CM_L4PER_CLKSTCTRL_OFFSET 0x0900
232#define OMAP54XX_CM_L4PER_DYNAMICDEP_OFFSET 0x0908
233#define OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET 0x0928
234#define OMAP54XX_CM_L4PER_TIMER10_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0928)
235#define OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET 0x0930
236#define OMAP54XX_CM_L4PER_TIMER11_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0930)
237#define OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET 0x0938
238#define OMAP54XX_CM_L4PER_TIMER2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0938)
239#define OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET 0x0940
240#define OMAP54XX_CM_L4PER_TIMER3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0940)
241#define OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET 0x0948
242#define OMAP54XX_CM_L4PER_TIMER4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0948)
243#define OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET 0x0950
244#define OMAP54XX_CM_L4PER_TIMER9_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0950)
245#define OMAP54XX_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0958
246#define OMAP54XX_CM_L4PER_ELM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0958)
247#define OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0960
248#define OMAP54XX_CM_L4PER_GPIO2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0960)
249#define OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0968
250#define OMAP54XX_CM_L4PER_GPIO3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0968)
251#define OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0970
252#define OMAP54XX_CM_L4PER_GPIO4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0970)
253#define OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0978
254#define OMAP54XX_CM_L4PER_GPIO5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0978)
255#define OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0980
256#define OMAP54XX_CM_L4PER_GPIO6_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0980)
257#define OMAP54XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0988
258#define OMAP54XX_CM_L4PER_HDQ1W_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0988)
259#define OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x09a0
260#define OMAP54XX_CM_L4PER_I2C1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09a0)
261#define OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x09a8
262#define OMAP54XX_CM_L4PER_I2C2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09a8)
263#define OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x09b0
264#define OMAP54XX_CM_L4PER_I2C3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09b0)
265#define OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x09b8
266#define OMAP54XX_CM_L4PER_I2C4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09b8)
267#define OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET 0x09c0
268#define OMAP54XX_CM_L4PER_L4_PER_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09c0)
269#define OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x09f0
270#define OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09f0)
271#define OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x09f8
272#define OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09f8)
273#define OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0a00
274#define OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a00)
275#define OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0a08
276#define OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a08)
277#define OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET 0x0a10
278#define OMAP54XX_CM_L4PER_GPIO7_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a10)
279#define OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET 0x0a18
280#define OMAP54XX_CM_L4PER_GPIO8_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a18)
281#define OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET 0x0a20
282#define OMAP54XX_CM_L4PER_MMC3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a20)
283#define OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET 0x0a28
284#define OMAP54XX_CM_L4PER_MMC4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a28)
285#define OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0a40
286#define OMAP54XX_CM_L4PER_UART1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a40)
287#define OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0a48
288#define OMAP54XX_CM_L4PER_UART2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a48)
289#define OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0a50
290#define OMAP54XX_CM_L4PER_UART3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a50)
291#define OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0a58
292#define OMAP54XX_CM_L4PER_UART4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a58)
293#define OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET 0x0a60
294#define OMAP54XX_CM_L4PER_MMC5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a60)
295#define OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET 0x0a68
296#define OMAP54XX_CM_L4PER_I2C5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a68)
297#define OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET 0x0a70
298#define OMAP54XX_CM_L4PER_UART5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a70)
299#define OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET 0x0a78
300#define OMAP54XX_CM_L4PER_UART6_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a78)
301#define OMAP54XX_CM_L4SEC_CLKSTCTRL_OFFSET 0x0a80
302#define OMAP54XX_CM_L4SEC_STATICDEP_OFFSET 0x0a84
303#define OMAP54XX_CM_L4SEC_DYNAMICDEP_OFFSET 0x0a88
304#define OMAP54XX_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x0aa0
305#define OMAP54XX_CM_L4SEC_AES1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0aa0)
306#define OMAP54XX_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x0aa8
307#define OMAP54XX_CM_L4SEC_AES2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0aa8)
308#define OMAP54XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x0ab0
309#define OMAP54XX_CM_L4SEC_DES3DES_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ab0)
310#define OMAP54XX_CM_L4SEC_FPKA_CLKCTRL_OFFSET 0x0ab8
311#define OMAP54XX_CM_L4SEC_FPKA_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ab8)
312#define OMAP54XX_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x0ac0
313#define OMAP54XX_CM_L4SEC_RNG_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ac0)
314#define OMAP54XX_CM_L4SEC_SHA2MD5_CLKCTRL_OFFSET 0x0ac8
315#define OMAP54XX_CM_L4SEC_SHA2MD5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ac8)
316#define OMAP54XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL_OFFSET 0x0ad8
317#define OMAP54XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ad8)
318
319/* CM_CORE.IVA_CM_CORE register offsets */
320#define OMAP54XX_CM_IVA_CLKSTCTRL_OFFSET 0x0000
321#define OMAP54XX_CM_IVA_STATICDEP_OFFSET 0x0004
322#define OMAP54XX_CM_IVA_DYNAMICDEP_OFFSET 0x0008
323#define OMAP54XX_CM_IVA_IVA_CLKCTRL_OFFSET 0x0020
324#define OMAP54XX_CM_IVA_IVA_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_IVA_INST, 0x0020)
325#define OMAP54XX_CM_IVA_SL2_CLKCTRL_OFFSET 0x0028
326#define OMAP54XX_CM_IVA_SL2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_IVA_INST, 0x0028)
327
328/* CM_CORE.CAM_CM_CORE register offsets */
329#define OMAP54XX_CM_CAM_CLKSTCTRL_OFFSET 0x0000
330#define OMAP54XX_CM_CAM_STATICDEP_OFFSET 0x0004
331#define OMAP54XX_CM_CAM_DYNAMICDEP_OFFSET 0x0008
332#define OMAP54XX_CM_CAM_ISS_CLKCTRL_OFFSET 0x0020
333#define OMAP54XX_CM_CAM_ISS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0020)
334#define OMAP54XX_CM_CAM_FDIF_CLKCTRL_OFFSET 0x0028
335#define OMAP54XX_CM_CAM_FDIF_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0028)
336#define OMAP54XX_CM_CAM_CAL_CLKCTRL_OFFSET 0x0030
337#define OMAP54XX_CM_CAM_CAL_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0030)
338
339/* CM_CORE.DSS_CM_CORE register offsets */
340#define OMAP54XX_CM_DSS_CLKSTCTRL_OFFSET 0x0000
341#define OMAP54XX_CM_DSS_STATICDEP_OFFSET 0x0004
342#define OMAP54XX_CM_DSS_DYNAMICDEP_OFFSET 0x0008
343#define OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020
344#define OMAP54XX_CM_DSS_DSS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_DSS_INST, 0x0020)
345#define OMAP54XX_CM_DSS_BB2D_CLKCTRL_OFFSET 0x0030
346#define OMAP54XX_CM_DSS_BB2D_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_DSS_INST, 0x0030)
347
348/* CM_CORE.GPU_CM_CORE register offsets */
349#define OMAP54XX_CM_GPU_CLKSTCTRL_OFFSET 0x0000
350#define OMAP54XX_CM_GPU_STATICDEP_OFFSET 0x0004
351#define OMAP54XX_CM_GPU_DYNAMICDEP_OFFSET 0x0008
352#define OMAP54XX_CM_GPU_GPU_CLKCTRL_OFFSET 0x0020
353#define OMAP54XX_CM_GPU_GPU_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_GPU_INST, 0x0020)
354
355/* CM_CORE.L3INIT_CM_CORE register offsets */
356#define OMAP54XX_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000
357#define OMAP54XX_CM_L3INIT_STATICDEP_OFFSET 0x0004
358#define OMAP54XX_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008
359#define OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028
360#define OMAP54XX_CM_L3INIT_MMC1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0028)
361#define OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030
362#define OMAP54XX_CM_L3INIT_MMC2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0030)
363#define OMAP54XX_CM_L3INIT_HSI_CLKCTRL_OFFSET 0x0038
364#define OMAP54XX_CM_L3INIT_HSI_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0038)
365#define OMAP54XX_CM_L3INIT_UNIPRO2_CLKCTRL_OFFSET 0x0040
366#define OMAP54XX_CM_L3INIT_UNIPRO2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0040)
367#define OMAP54XX_CM_L3INIT_MPHY_UNIPRO2_CLKCTRL_OFFSET 0x0048
368#define OMAP54XX_CM_L3INIT_MPHY_UNIPRO2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0048)
369#define OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET 0x0058
370#define OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0058)
371#define OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET 0x0068
372#define OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0068)
373#define OMAP54XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL_OFFSET 0x0078
374#define OMAP54XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0078)
375#define OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088
376#define OMAP54XX_CM_L3INIT_SATA_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0088)
377#define OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET 0x00e0
378#define OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00e0)
379#define OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET 0x00e8
380#define OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00e8)
381#define OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET 0x00f0
382#define OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00f0)
383
384/* CM_CORE.CUSTEFUSE_CM_CORE register offsets */
385#define OMAP54XX_CM_CUSTEFUSE_CLKSTCTRL_OFFSET 0x0000
386#define OMAP54XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL_OFFSET 0x0020
387#define OMAP54XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CUSTEFUSE_INST, 0x0020)
388
389#endif
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
index 64f4bafe7bd9..9d1f4fcdebbb 100644
--- a/arch/arm/mach-omap2/cm33xx.h
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -383,7 +383,7 @@ extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs);
383extern void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs); 383extern void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs);
384extern void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs); 384extern void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs);
385 385
386#ifdef CONFIG_SOC_AM33XX 386#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
387extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, 387extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
388 u16 clkctrl_offs); 388 u16 clkctrl_offs);
389extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, 389extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
diff --git a/arch/arm/mach-omap2/cm_44xx_54xx.h b/arch/arm/mach-omap2/cm_44xx_54xx.h
new file mode 100644
index 000000000000..cbb211690321
--- /dev/null
+++ b/arch/arm/mach-omap2/cm_44xx_54xx.h
@@ -0,0 +1,36 @@
1/*
2 * OMAP44xx and OMAP54xx CM1/CM2 function prototypes
3 *
4 * Copyright (C) 2009-2013 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 *
21 */
22
23#ifndef __ARCH_ARM_MACH_OMAP2_CM_44XX_54XX_H
24#define __ARCH_ARM_MACH_OMAP2_CM_44XX_55XX_H
25
26/* CM1 Function prototypes */
27extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
28extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);
29extern u32 omap4_cm1_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
30
31/* CM2 Function prototypes */
32extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx);
33extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx);
34extern u32 omap4_cm2_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
35
36#endif
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index d555cf2459e1..dfcc182ecff9 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -31,6 +31,7 @@
31#include <linux/i2c.h> 31#include <linux/i2c.h>
32#include <linux/i2c/twl.h> 32#include <linux/i2c/twl.h>
33#include <linux/i2c-omap.h> 33#include <linux/i2c-omap.h>
34#include <linux/reboot.h>
34 35
35#include <asm/proc-fns.h> 36#include <asm/proc-fns.h>
36 37
@@ -96,6 +97,7 @@ void am33xx_init_early(void);
96void am35xx_init_early(void); 97void am35xx_init_early(void);
97void ti81xx_init_early(void); 98void ti81xx_init_early(void);
98void am33xx_init_early(void); 99void am33xx_init_early(void);
100void am43xx_init_early(void);
99void omap4430_init_early(void); 101void omap4430_init_early(void);
100void omap5_init_early(void); 102void omap5_init_early(void);
101void omap3_init_late(void); /* Do not use this one */ 103void omap3_init_late(void); /* Do not use this one */
@@ -118,33 +120,33 @@ static inline void omap_soc_device_init(void)
118#endif 120#endif
119 121
120#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430) 122#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
121void omap2xxx_restart(char mode, const char *cmd); 123void omap2xxx_restart(enum reboot_mode mode, const char *cmd);
122#else 124#else
123static inline void omap2xxx_restart(char mode, const char *cmd) 125static inline void omap2xxx_restart(enum reboot_mode mode, const char *cmd)
124{ 126{
125} 127}
126#endif 128#endif
127 129
128#ifdef CONFIG_SOC_AM33XX 130#ifdef CONFIG_SOC_AM33XX
129void am33xx_restart(char mode, const char *cmd); 131void am33xx_restart(enum reboot_mode mode, const char *cmd);
130#else 132#else
131static inline void am33xx_restart(char mode, const char *cmd) 133static inline void am33xx_restart(enum reboot_mode mode, const char *cmd)
132{ 134{
133} 135}
134#endif 136#endif
135 137
136#ifdef CONFIG_ARCH_OMAP3 138#ifdef CONFIG_ARCH_OMAP3
137void omap3xxx_restart(char mode, const char *cmd); 139void omap3xxx_restart(enum reboot_mode mode, const char *cmd);
138#else 140#else
139static inline void omap3xxx_restart(char mode, const char *cmd) 141static inline void omap3xxx_restart(enum reboot_mode mode, const char *cmd)
140{ 142{
141} 143}
142#endif 144#endif
143 145
144#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) 146#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
145void omap44xx_restart(char mode, const char *cmd); 147void omap44xx_restart(enum reboot_mode mode, const char *cmd);
146#else 148#else
147static inline void omap44xx_restart(char mode, const char *cmd) 149static inline void omap44xx_restart(enum reboot_mode mode, const char *cmd)
148{ 150{
149} 151}
150#endif 152#endif
@@ -237,8 +239,8 @@ extern void omap_do_wfi(void);
237 239
238#ifdef CONFIG_SMP 240#ifdef CONFIG_SMP
239/* Needed for secondary core boot */ 241/* Needed for secondary core boot */
240extern void omap_secondary_startup(void); 242extern void omap4_secondary_startup(void);
241extern void omap_secondary_startup_4460(void); 243extern void omap4460_secondary_startup(void);
242extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask); 244extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
243extern void omap_auxcoreboot_addr(u32 cpu_addr); 245extern void omap_auxcoreboot_addr(u32 cpu_addr);
244extern u32 omap_read_auxcoreboot0(void); 246extern u32 omap_read_auxcoreboot0(void);
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 2adb2683f074..31e0dfe4a4ea 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -249,6 +249,7 @@ void omap_ctrl_write_dsp_boot_addr(u32 bootaddr)
249 u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTADDR : 249 u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTADDR :
250 cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTADDR : 250 cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTADDR :
251 cpu_is_omap44xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR : 251 cpu_is_omap44xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR :
252 soc_is_omap54xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR :
252 0; 253 0;
253 254
254 if (!offset) { 255 if (!offset) {
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index e6c328128a0a..f7d7c2ef1b40 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -358,6 +358,18 @@
358#define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH 0x2 358#define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH 0x2
359#define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22) 359#define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22)
360 360
361/* AM33XX PWMSS Control register */
362#define AM33XX_PWMSS_TBCLK_CLKCTRL 0x664
363
364/* AM33XX PWMSS Control bitfields */
365#define AM33XX_PWMSS0_TBCLKEN_SHIFT 0
366#define AM33XX_PWMSS1_TBCLKEN_SHIFT 1
367#define AM33XX_PWMSS2_TBCLKEN_SHIFT 2
368
369/* DEV Feature register to identify AM33XX features */
370#define AM33XX_DEV_FEATURE 0x604
371#define AM33XX_SGX_MASK BIT(29)
372
361/* CONTROL OMAP STATUS register to identify OMAP3 features */ 373/* CONTROL OMAP STATUS register to identify OMAP3 features */
362#define OMAP3_CONTROL_OMAP_STATUS 0x044c 374#define OMAP3_CONTROL_OMAP_STATUS 0x044c
363 375
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 4269fc145698..3c1279f27d1f 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -19,8 +19,8 @@
19#include <linux/of.h> 19#include <linux/of.h>
20#include <linux/pinctrl/machine.h> 20#include <linux/pinctrl/machine.h>
21#include <linux/platform_data/omap4-keypad.h> 21#include <linux/platform_data/omap4-keypad.h>
22#include <linux/platform_data/omap_ocp2scp.h> 22#include <linux/wl12xx.h>
23#include <linux/usb/omap_control_usb.h> 23#include <linux/platform_data/mailbox-omap.h>
24 24
25#include <asm/mach-types.h> 25#include <asm/mach-types.h>
26#include <asm/mach/map.h> 26#include <asm/mach/map.h>
@@ -37,7 +37,6 @@
37#include "mux.h" 37#include "mux.h"
38#include "control.h" 38#include "control.h"
39#include "devices.h" 39#include "devices.h"
40#include "dma.h"
41 40
42#define L3_MODULES_MAX_LEN 12 41#define L3_MODULES_MAX_LEN 12
43#define L3_MODULES 3 42#define L3_MODULES 3
@@ -66,7 +65,7 @@ static int __init omap3_l3_init(void)
66 65
67 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name); 66 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
68 67
69 return IS_ERR(pdev) ? PTR_ERR(pdev) : 0; 68 return PTR_RET(pdev);
70} 69}
71omap_postcore_initcall(omap3_l3_init); 70omap_postcore_initcall(omap3_l3_init);
72 71
@@ -100,7 +99,7 @@ static int __init omap4_l3_init(void)
100 99
101 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name); 100 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
102 101
103 return IS_ERR(pdev) ? PTR_ERR(pdev) : 0; 102 return PTR_RET(pdev);
104} 103}
105omap_postcore_initcall(omap4_l3_init); 104omap_postcore_initcall(omap4_l3_init);
106 105
@@ -253,49 +252,6 @@ static inline void omap_init_camera(void)
253#endif 252#endif
254} 253}
255 254
256#if IS_ENABLED(CONFIG_OMAP_CONTROL_USB)
257static struct omap_control_usb_platform_data omap4_control_usb_pdata = {
258 .type = 1,
259};
260
261struct resource omap4_control_usb_res[] = {
262 {
263 .name = "control_dev_conf",
264 .start = 0x4a002300,
265 .end = 0x4a002303,
266 .flags = IORESOURCE_MEM,
267 },
268 {
269 .name = "otghs_control",
270 .start = 0x4a00233c,
271 .end = 0x4a00233f,
272 .flags = IORESOURCE_MEM,
273 },
274};
275
276static struct platform_device omap4_control_usb = {
277 .name = "omap-control-usb",
278 .id = -1,
279 .dev = {
280 .platform_data = &omap4_control_usb_pdata,
281 },
282 .num_resources = 2,
283 .resource = omap4_control_usb_res,
284};
285
286static inline void __init omap_init_control_usb(void)
287{
288 if (!cpu_is_omap44xx())
289 return;
290
291 if (platform_device_register(&omap4_control_usb))
292 pr_err("Error registering omap_control_usb device\n");
293}
294
295#else
296static inline void omap_init_control_usb(void) { }
297#endif /* CONFIG_OMAP_CONTROL_USB */
298
299int __init omap4_keyboard_init(struct omap4_keypad_platform_data 255int __init omap4_keyboard_init(struct omap4_keypad_platform_data
300 *sdp4430_keypad_data, struct omap_board_data *bdata) 256 *sdp4430_keypad_data, struct omap_board_data *bdata)
301{ 257{
@@ -327,25 +283,31 @@ int __init omap4_keyboard_init(struct omap4_keypad_platform_data
327 return 0; 283 return 0;
328} 284}
329 285
330#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE) 286#if defined(CONFIG_OMAP2PLUS_MBOX) || defined(CONFIG_OMAP2PLUS_MBOX_MODULE)
331static inline void __init omap_init_mbox(void) 287static inline void __init omap_init_mbox(void)
332{ 288{
333 struct omap_hwmod *oh; 289 struct omap_hwmod *oh;
334 struct platform_device *pdev; 290 struct platform_device *pdev;
291 struct omap_mbox_pdata *pdata;
335 292
336 oh = omap_hwmod_lookup("mailbox"); 293 oh = omap_hwmod_lookup("mailbox");
337 if (!oh) { 294 if (!oh) {
338 pr_err("%s: unable to find hwmod\n", __func__); 295 pr_err("%s: unable to find hwmod\n", __func__);
339 return; 296 return;
340 } 297 }
298 if (!oh->dev_attr) {
299 pr_err("%s: hwmod doesn't have valid attrs\n", __func__);
300 return;
301 }
341 302
342 pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0); 303 pdata = (struct omap_mbox_pdata *)oh->dev_attr;
304 pdev = omap_device_build("omap-mailbox", -1, oh, pdata, sizeof(*pdata));
343 WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n", 305 WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n",
344 __func__, PTR_ERR(pdev)); 306 __func__, PTR_ERR(pdev));
345} 307}
346#else 308#else
347static inline void omap_init_mbox(void) { } 309static inline void omap_init_mbox(void) { }
348#endif /* CONFIG_OMAP_MBOX_FWK */ 310#endif /* CONFIG_OMAP2PLUS_MBOX */
349 311
350static inline void omap_init_sti(void) {} 312static inline void omap_init_sti(void) {}
351 313
@@ -374,10 +336,8 @@ static void __init omap_init_mcpdm(void)
374 struct platform_device *pdev; 336 struct platform_device *pdev;
375 337
376 oh = omap_hwmod_lookup("mcpdm"); 338 oh = omap_hwmod_lookup("mcpdm");
377 if (!oh) { 339 if (!oh)
378 printk(KERN_ERR "Could not look up mcpdm hw_mod\n");
379 return; 340 return;
380 }
381 341
382 pdev = omap_device_build("omap-mcpdm", -1, oh, NULL, 0); 342 pdev = omap_device_build("omap-mcpdm", -1, oh, NULL, 0);
383 WARN(IS_ERR(pdev), "Can't build omap_device for omap-mcpdm.\n"); 343 WARN(IS_ERR(pdev), "Can't build omap_device for omap-mcpdm.\n");
@@ -395,10 +355,8 @@ static void __init omap_init_dmic(void)
395 struct platform_device *pdev; 355 struct platform_device *pdev;
396 356
397 oh = omap_hwmod_lookup("dmic"); 357 oh = omap_hwmod_lookup("dmic");
398 if (!oh) { 358 if (!oh)
399 pr_err("Could not look up dmic hw_mod\n");
400 return; 359 return;
401 }
402 360
403 pdev = omap_device_build("omap-dmic", -1, oh, NULL, 0); 361 pdev = omap_device_build("omap-dmic", -1, oh, NULL, 0);
404 WARN(IS_ERR(pdev), "Can't build omap_device for omap-dmic.\n"); 362 WARN(IS_ERR(pdev), "Can't build omap_device for omap-dmic.\n");
@@ -421,10 +379,8 @@ static void __init omap_init_hdmi_audio(void)
421 struct platform_device *pdev; 379 struct platform_device *pdev;
422 380
423 oh = omap_hwmod_lookup("dss_hdmi"); 381 oh = omap_hwmod_lookup("dss_hdmi");
424 if (!oh) { 382 if (!oh)
425 printk(KERN_ERR "Could not look up dss_hdmi hw_mod\n");
426 return; 383 return;
427 }
428 384
429 pdev = omap_device_build("omap-hdmi-audio-dai", -1, oh, NULL, 0); 385 pdev = omap_device_build("omap-hdmi-audio-dai", -1, oh, NULL, 0);
430 WARN(IS_ERR(pdev), 386 WARN(IS_ERR(pdev),
@@ -557,80 +513,38 @@ static void omap_init_vout(void)
557static inline void omap_init_vout(void) {} 513static inline void omap_init_vout(void) {}
558#endif 514#endif
559 515
560#if defined(CONFIG_OMAP_OCP2SCP) || defined(CONFIG_OMAP_OCP2SCP_MODULE) 516#if IS_ENABLED(CONFIG_WL12XX)
561static int count_ocp2scp_devices(struct omap_ocp2scp_dev *ocp2scp_dev)
562{
563 int cnt = 0;
564 517
565 while (ocp2scp_dev->drv_name != NULL) { 518static struct wl12xx_platform_data wl12xx __initdata;
566 cnt++;
567 ocp2scp_dev++;
568 }
569 519
570 return cnt; 520void __init omap_init_wl12xx_of(void)
571}
572
573static void __init omap_init_ocp2scp(void)
574{ 521{
575 struct omap_hwmod *oh; 522 int ret;
576 struct platform_device *pdev;
577 int bus_id = -1, dev_cnt = 0, i;
578 struct omap_ocp2scp_dev *ocp2scp_dev;
579 const char *oh_name, *name;
580 struct omap_ocp2scp_platform_data *pdata;
581
582 if (!cpu_is_omap44xx())
583 return;
584
585 oh_name = "ocp2scp_usb_phy";
586 name = "omap-ocp2scp";
587
588 oh = omap_hwmod_lookup(oh_name);
589 if (!oh) {
590 pr_err("%s: could not find omap_hwmod for %s\n", __func__,
591 oh_name);
592 return;
593 }
594 523
595 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); 524 if (!of_have_populated_dt())
596 if (!pdata) {
597 pr_err("%s: No memory for ocp2scp pdata\n", __func__);
598 return; 525 return;
599 }
600 526
601 ocp2scp_dev = oh->dev_attr; 527 if (of_machine_is_compatible("ti,omap4-sdp")) {
602 dev_cnt = count_ocp2scp_devices(ocp2scp_dev); 528 wl12xx.board_ref_clock = WL12XX_REFCLOCK_26;
603 529 wl12xx.board_tcxo_clock = WL12XX_TCXOCLOCK_26;
604 if (!dev_cnt) { 530 wl12xx.irq = gpio_to_irq(53);
605 pr_err("%s: No devices connected to ocp2scp\n", __func__); 531 } else if (of_machine_is_compatible("ti,omap4-panda")) {
606 kfree(pdata); 532 wl12xx.board_ref_clock = WL12XX_REFCLOCK_38;
533 wl12xx.irq = gpio_to_irq(53);
534 } else {
607 return; 535 return;
608 } 536 }
609 537
610 pdata->devices = kzalloc(sizeof(struct omap_ocp2scp_dev *) 538 ret = wl12xx_set_platform_data(&wl12xx);
611 * dev_cnt, GFP_KERNEL); 539 if (ret) {
612 if (!pdata->devices) { 540 pr_err("error setting wl12xx data: %d\n", ret);
613 pr_err("%s: No memory for ocp2scp pdata devices\n", __func__);
614 kfree(pdata);
615 return;
616 }
617
618 for (i = 0; i < dev_cnt; i++, ocp2scp_dev++)
619 pdata->devices[i] = ocp2scp_dev;
620
621 pdata->dev_cnt = dev_cnt;
622
623 pdev = omap_device_build(name, bus_id, oh, pdata, sizeof(*pdata));
624 if (IS_ERR(pdev)) {
625 pr_err("Could not build omap_device for %s %s\n",
626 name, oh_name);
627 kfree(pdata->devices);
628 kfree(pdata);
629 return; 541 return;
630 } 542 }
631} 543}
632#else 544#else
633static inline void omap_init_ocp2scp(void) { } 545static inline void omap_init_wl12xx_of(void)
546{
547}
634#endif 548#endif
635 549
636/*-------------------------------------------------------------------------*/ 550/*-------------------------------------------------------------------------*/
@@ -651,17 +565,18 @@ static int __init omap2_init_devices(void)
651 omap_init_mbox(); 565 omap_init_mbox();
652 /* If dtb is there, the devices will be created dynamically */ 566 /* If dtb is there, the devices will be created dynamically */
653 if (!of_have_populated_dt()) { 567 if (!of_have_populated_dt()) {
654 omap_init_control_usb();
655 omap_init_dmic(); 568 omap_init_dmic();
656 omap_init_mcpdm(); 569 omap_init_mcpdm();
657 omap_init_mcspi(); 570 omap_init_mcspi();
658 omap_init_sham(); 571 omap_init_sham();
659 omap_init_aes(); 572 omap_init_aes();
573 } else {
574 /* These can be removed when bindings are done */
575 omap_init_wl12xx_of();
660 } 576 }
661 omap_init_sti(); 577 omap_init_sti();
662 omap_init_rng(); 578 omap_init_rng();
663 omap_init_vout(); 579 omap_init_vout();
664 omap_init_ocp2scp();
665 580
666 return 0; 581 return 0;
667} 582}
diff --git a/arch/arm/mach-omap2/dma.h b/arch/arm/mach-omap2/dma.h
deleted file mode 100644
index 65f80cacf178..000000000000
--- a/arch/arm/mach-omap2/dma.h
+++ /dev/null
@@ -1,61 +0,0 @@
1/*
2 * OMAP2PLUS DMA channel definitions
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#ifndef __OMAP2PLUS_DMA_CHANNEL_H
20#define __OMAP2PLUS_DMA_CHANNEL_H
21
22
23/* DMA channels for 24xx */
24#define OMAP24XX_DMA_NO_DEVICE 0
25#define OMAP24XX_DMA_EXT_DMAREQ0 2 /* S_DMA_1 */
26#define OMAP24XX_DMA_EXT_DMAREQ1 3 /* S_DMA_2 */
27#define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */
28#define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */
29#define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */
30#define OMAP242X_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */
31#define OMAP242X_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */
32#define OMAP242X_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */
33#define OMAP34XX_DMA_I2C3_TX 25 /* S_DMA_24 */
34#define OMAP34XX_DMA_I2C3_RX 26 /* S_DMA_25 */
35#define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */
36#define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */
37#define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */
38#define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */
39#define OMAP24XX_DMA_MMC2_TX 47 /* S_DMA_46 */
40#define OMAP24XX_DMA_MMC2_RX 48 /* S_DMA_47 */
41#define OMAP24XX_DMA_UART1_TX 49 /* S_DMA_48 */
42#define OMAP24XX_DMA_UART1_RX 50 /* S_DMA_49 */
43#define OMAP24XX_DMA_UART2_TX 51 /* S_DMA_50 */
44#define OMAP24XX_DMA_UART2_RX 52 /* S_DMA_51 */
45#define OMAP24XX_DMA_UART3_TX 53 /* S_DMA_52 */
46#define OMAP24XX_DMA_UART3_RX 54 /* S_DMA_53 */
47#define OMAP24XX_DMA_MMC1_TX 61 /* S_DMA_60 */
48#define OMAP24XX_DMA_MMC1_RX 62 /* S_DMA_61 */
49#define OMAP242X_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */
50#define OMAP34XX_DMA_AES2_TX 65 /* S_DMA_64 */
51#define OMAP34XX_DMA_AES2_RX 66 /* S_DMA_65 */
52#define OMAP34XX_DMA_SHA1MD5_RX 69 /* S_DMA_68 */
53
54#define OMAP36XX_DMA_UART4_TX 81 /* S_DMA_80 */
55#define OMAP36XX_DMA_UART4_RX 82 /* S_DMA_81 */
56
57/* Only for AM35xx */
58#define AM35XX_DMA_UART4_TX 54
59#define AM35XX_DMA_UART4_RX 55
60
61#endif /* __OMAP2PLUS_DMA_CHANNEL_H */
diff --git a/arch/arm/mach-omap2/dss-common.c b/arch/arm/mach-omap2/dss-common.c
index 393aeefaebb0..043e5705f2a6 100644
--- a/arch/arm/mach-omap2/dss-common.c
+++ b/arch/arm/mach-omap2/dss-common.c
@@ -42,7 +42,7 @@
42 42
43/* Using generic display panel */ 43/* Using generic display panel */
44static struct tfp410_platform_data omap4_dvi_panel = { 44static struct tfp410_platform_data omap4_dvi_panel = {
45 .i2c_bus_num = 3, 45 .i2c_bus_num = 2,
46 .power_down_gpio = PANDA_DVI_TFP410_POWER_DOWN_GPIO, 46 .power_down_gpio = PANDA_DVI_TFP410_POWER_DOWN_GPIO,
47}; 47};
48 48
diff --git a/arch/arm/mach-omap2/fb.c b/arch/arm/mach-omap2/fb.c
index 190ae493c6ef..2ca33cc0c484 100644
--- a/arch/arm/mach-omap2/fb.c
+++ b/arch/arm/mach-omap2/fb.c
@@ -83,10 +83,7 @@ static int __init omap_init_vrfb(void)
83 pdev = platform_device_register_resndata(NULL, "omapvrfb", -1, 83 pdev = platform_device_register_resndata(NULL, "omapvrfb", -1,
84 res, num_res, NULL, 0); 84 res, num_res, NULL, 0);
85 85
86 if (IS_ERR(pdev)) 86 return PTR_RET(pdev);
87 return PTR_ERR(pdev);
88 else
89 return 0;
90} 87}
91 88
92omap_arch_initcall(omap_init_vrfb); 89omap_arch_initcall(omap_init_vrfb);
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index d9c27195caf0..662c7fd633cc 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -43,44 +43,6 @@ static struct platform_device gpmc_nand_device = {
43 .resource = gpmc_nand_resource, 43 .resource = gpmc_nand_resource,
44}; 44};
45 45
46static int omap2_nand_gpmc_retime(
47 struct omap_nand_platform_data *gpmc_nand_data,
48 struct gpmc_timings *gpmc_t)
49{
50 struct gpmc_timings t;
51 int err;
52
53 memset(&t, 0, sizeof(t));
54 t.sync_clk = gpmc_t->sync_clk;
55 t.cs_on = gpmc_t->cs_on;
56 t.adv_on = gpmc_t->adv_on;
57
58 /* Read */
59 t.adv_rd_off = gpmc_t->adv_rd_off;
60 t.oe_on = t.adv_on;
61 t.access = gpmc_t->access;
62 t.oe_off = gpmc_t->oe_off;
63 t.cs_rd_off = gpmc_t->cs_rd_off;
64 t.rd_cycle = gpmc_t->rd_cycle;
65
66 /* Write */
67 t.adv_wr_off = gpmc_t->adv_wr_off;
68 t.we_on = t.oe_on;
69 if (cpu_is_omap34xx()) {
70 t.wr_data_mux_bus = gpmc_t->wr_data_mux_bus;
71 t.wr_access = gpmc_t->wr_access;
72 }
73 t.we_off = gpmc_t->we_off;
74 t.cs_wr_off = gpmc_t->cs_wr_off;
75 t.wr_cycle = gpmc_t->wr_cycle;
76
77 err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t);
78 if (err)
79 return err;
80
81 return 0;
82}
83
84static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) 46static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
85{ 47{
86 /* support only OMAP3 class */ 48 /* support only OMAP3 class */
@@ -131,7 +93,7 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
131 gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT); 93 gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);
132 94
133 if (gpmc_t) { 95 if (gpmc_t) {
134 err = omap2_nand_gpmc_retime(gpmc_nand_data, gpmc_t); 96 err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t);
135 if (err < 0) { 97 if (err < 0) {
136 dev_err(dev, "Unable to set gpmc timings: %d\n", err); 98 dev_err(dev, "Unable to set gpmc timings: %d\n", err);
137 return err; 99 return err;
@@ -140,8 +102,6 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
140 if (gpmc_nand_data->of_node) { 102 if (gpmc_nand_data->of_node) {
141 gpmc_read_settings_dt(gpmc_nand_data->of_node, &s); 103 gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);
142 } else { 104 } else {
143 s.device_nand = true;
144
145 /* Enable RD PIN Monitoring Reg */ 105 /* Enable RD PIN Monitoring Reg */
146 if (gpmc_nand_data->dev_ready) { 106 if (gpmc_nand_data->dev_ready) {
147 s.wait_on_read = true; 107 s.wait_on_read = true;
@@ -149,6 +109,8 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
149 } 109 }
150 } 110 }
151 111
112 s.device_nand = true;
113
152 if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16) 114 if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
153 s.device_width = GPMC_DEVWIDTH_16BIT; 115 s.device_width = GPMC_DEVWIDTH_16BIT;
154 else 116 else
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 6c4da1254f53..f3fdd6afa213 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -30,6 +30,7 @@
30#include <linux/of_mtd.h> 30#include <linux/of_mtd.h>
31#include <linux/of_device.h> 31#include <linux/of_device.h>
32#include <linux/mtd/nand.h> 32#include <linux/mtd/nand.h>
33#include <linux/pm_runtime.h>
33 34
34#include <linux/platform_data/mtd-nand-omap2.h> 35#include <linux/platform_data/mtd-nand-omap2.h>
35 36
@@ -155,6 +156,7 @@ static struct resource gpmc_cs_mem[GPMC_CS_NUM];
155static DEFINE_SPINLOCK(gpmc_mem_lock); 156static DEFINE_SPINLOCK(gpmc_mem_lock);
156/* Define chip-selects as reserved by default until probe completes */ 157/* Define chip-selects as reserved by default until probe completes */
157static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1); 158static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1);
159static unsigned int gpmc_cs_num = GPMC_CS_NUM;
158static unsigned int gpmc_nr_waitpins; 160static unsigned int gpmc_nr_waitpins;
159static struct device *gpmc_dev; 161static struct device *gpmc_dev;
160static int gpmc_irq; 162static int gpmc_irq;
@@ -521,8 +523,10 @@ static int gpmc_cs_remap(int cs, u32 base)
521 int ret; 523 int ret;
522 u32 old_base, size; 524 u32 old_base, size;
523 525
524 if (cs > GPMC_CS_NUM) 526 if (cs > gpmc_cs_num) {
527 pr_err("%s: requested chip-select is disabled\n", __func__);
525 return -ENODEV; 528 return -ENODEV;
529 }
526 gpmc_cs_get_memconf(cs, &old_base, &size); 530 gpmc_cs_get_memconf(cs, &old_base, &size);
527 if (base == old_base) 531 if (base == old_base)
528 return 0; 532 return 0;
@@ -545,9 +549,10 @@ int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
545 struct resource *res = &gpmc_cs_mem[cs]; 549 struct resource *res = &gpmc_cs_mem[cs];
546 int r = -1; 550 int r = -1;
547 551
548 if (cs > GPMC_CS_NUM) 552 if (cs > gpmc_cs_num) {
553 pr_err("%s: requested chip-select is disabled\n", __func__);
549 return -ENODEV; 554 return -ENODEV;
550 555 }
551 size = gpmc_mem_align(size); 556 size = gpmc_mem_align(size);
552 if (size > (1 << GPMC_SECTION_SHIFT)) 557 if (size > (1 << GPMC_SECTION_SHIFT))
553 return -ENOMEM; 558 return -ENOMEM;
@@ -582,7 +587,7 @@ EXPORT_SYMBOL(gpmc_cs_request);
582void gpmc_cs_free(int cs) 587void gpmc_cs_free(int cs)
583{ 588{
584 spin_lock(&gpmc_mem_lock); 589 spin_lock(&gpmc_mem_lock);
585 if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) { 590 if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
586 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs); 591 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
587 BUG(); 592 BUG();
588 spin_unlock(&gpmc_mem_lock); 593 spin_unlock(&gpmc_mem_lock);
@@ -777,7 +782,7 @@ static void gpmc_mem_exit(void)
777{ 782{
778 int cs; 783 int cs;
779 784
780 for (cs = 0; cs < GPMC_CS_NUM; cs++) { 785 for (cs = 0; cs < gpmc_cs_num; cs++) {
781 if (!gpmc_cs_mem_enabled(cs)) 786 if (!gpmc_cs_mem_enabled(cs))
782 continue; 787 continue;
783 gpmc_cs_delete_mem(cs); 788 gpmc_cs_delete_mem(cs);
@@ -798,7 +803,7 @@ static void gpmc_mem_init(void)
798 gpmc_mem_root.end = GPMC_MEM_END; 803 gpmc_mem_root.end = GPMC_MEM_END;
799 804
800 /* Reserve all regions that has been set up by bootloader */ 805 /* Reserve all regions that has been set up by bootloader */
801 for (cs = 0; cs < GPMC_CS_NUM; cs++) { 806 for (cs = 0; cs < gpmc_cs_num; cs++) {
802 u32 base, size; 807 u32 base, size;
803 808
804 if (!gpmc_cs_mem_enabled(cs)) 809 if (!gpmc_cs_mem_enabled(cs))
@@ -1245,7 +1250,6 @@ void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
1245 1250
1246 p->sync_read = of_property_read_bool(np, "gpmc,sync-read"); 1251 p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
1247 p->sync_write = of_property_read_bool(np, "gpmc,sync-write"); 1252 p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
1248 p->device_nand = of_property_read_bool(np, "gpmc,device-nand");
1249 of_property_read_u32(np, "gpmc,device-width", &p->device_width); 1253 of_property_read_u32(np, "gpmc,device-width", &p->device_width);
1250 of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data); 1254 of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
1251 1255
@@ -1345,6 +1349,13 @@ static const char * const nand_ecc_opts[] = {
1345 [OMAP_ECC_BCH8_CODE_HW] = "bch8", 1349 [OMAP_ECC_BCH8_CODE_HW] = "bch8",
1346}; 1350};
1347 1351
1352static const char * const nand_xfer_types[] = {
1353 [NAND_OMAP_PREFETCH_POLLED] = "prefetch-polled",
1354 [NAND_OMAP_POLLED] = "polled",
1355 [NAND_OMAP_PREFETCH_DMA] = "prefetch-dma",
1356 [NAND_OMAP_PREFETCH_IRQ] = "prefetch-irq",
1357};
1358
1348static int gpmc_probe_nand_child(struct platform_device *pdev, 1359static int gpmc_probe_nand_child(struct platform_device *pdev,
1349 struct device_node *child) 1360 struct device_node *child)
1350{ 1361{
@@ -1374,6 +1385,13 @@ static int gpmc_probe_nand_child(struct platform_device *pdev,
1374 break; 1385 break;
1375 } 1386 }
1376 1387
1388 if (!of_property_read_string(child, "ti,nand-xfer-type", &s))
1389 for (val = 0; val < ARRAY_SIZE(nand_xfer_types); val++)
1390 if (!strcasecmp(s, nand_xfer_types[val])) {
1391 gpmc_nand_data->xfer_type = val;
1392 break;
1393 }
1394
1377 val = of_get_nand_bus_width(child); 1395 val = of_get_nand_bus_width(child);
1378 if (val == 16) 1396 if (val == 16)
1379 gpmc_nand_data->devsize = NAND_BUSWIDTH_16; 1397 gpmc_nand_data->devsize = NAND_BUSWIDTH_16;
@@ -1513,6 +1531,20 @@ static int gpmc_probe_dt(struct platform_device *pdev)
1513 if (!of_id) 1531 if (!of_id)
1514 return 0; 1532 return 0;
1515 1533
1534 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
1535 &gpmc_cs_num);
1536 if (ret < 0) {
1537 pr_err("%s: number of chip-selects not defined\n", __func__);
1538 return ret;
1539 } else if (gpmc_cs_num < 1) {
1540 pr_err("%s: all chip-selects are disabled\n", __func__);
1541 return -EINVAL;
1542 } else if (gpmc_cs_num > GPMC_CS_NUM) {
1543 pr_err("%s: number of supported chip-selects cannot be > %d\n",
1544 __func__, GPMC_CS_NUM);
1545 return -EINVAL;
1546 }
1547
1516 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins", 1548 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
1517 &gpmc_nr_waitpins); 1549 &gpmc_nr_waitpins);
1518 if (ret < 0) { 1550 if (ret < 0) {
@@ -1577,7 +1609,8 @@ static int gpmc_probe(struct platform_device *pdev)
1577 return PTR_ERR(gpmc_l3_clk); 1609 return PTR_ERR(gpmc_l3_clk);
1578 } 1610 }
1579 1611
1580 clk_prepare_enable(gpmc_l3_clk); 1612 pm_runtime_enable(&pdev->dev);
1613 pm_runtime_get_sync(&pdev->dev);
1581 1614
1582 gpmc_dev = &pdev->dev; 1615 gpmc_dev = &pdev->dev;
1583 1616
@@ -1610,12 +1643,14 @@ static int gpmc_probe(struct platform_device *pdev)
1610 /* Now the GPMC is initialised, unreserve the chip-selects */ 1643 /* Now the GPMC is initialised, unreserve the chip-selects */
1611 gpmc_cs_map = 0; 1644 gpmc_cs_map = 0;
1612 1645
1613 if (!pdev->dev.of_node) 1646 if (!pdev->dev.of_node) {
1647 gpmc_cs_num = GPMC_CS_NUM;
1614 gpmc_nr_waitpins = GPMC_NR_WAITPINS; 1648 gpmc_nr_waitpins = GPMC_NR_WAITPINS;
1649 }
1615 1650
1616 rc = gpmc_probe_dt(pdev); 1651 rc = gpmc_probe_dt(pdev);
1617 if (rc < 0) { 1652 if (rc < 0) {
1618 clk_disable_unprepare(gpmc_l3_clk); 1653 pm_runtime_put_sync(&pdev->dev);
1619 clk_put(gpmc_l3_clk); 1654 clk_put(gpmc_l3_clk);
1620 dev_err(gpmc_dev, "failed to probe DT parameters\n"); 1655 dev_err(gpmc_dev, "failed to probe DT parameters\n");
1621 return rc; 1656 return rc;
@@ -1628,10 +1663,30 @@ static int gpmc_remove(struct platform_device *pdev)
1628{ 1663{
1629 gpmc_free_irq(); 1664 gpmc_free_irq();
1630 gpmc_mem_exit(); 1665 gpmc_mem_exit();
1666 pm_runtime_put_sync(&pdev->dev);
1667 pm_runtime_disable(&pdev->dev);
1631 gpmc_dev = NULL; 1668 gpmc_dev = NULL;
1632 return 0; 1669 return 0;
1633} 1670}
1634 1671
1672#ifdef CONFIG_PM_SLEEP
1673static int gpmc_suspend(struct device *dev)
1674{
1675 omap3_gpmc_save_context();
1676 pm_runtime_put_sync(dev);
1677 return 0;
1678}
1679
1680static int gpmc_resume(struct device *dev)
1681{
1682 pm_runtime_get_sync(dev);
1683 omap3_gpmc_restore_context();
1684 return 0;
1685}
1686#endif
1687
1688static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
1689
1635static struct platform_driver gpmc_driver = { 1690static struct platform_driver gpmc_driver = {
1636 .probe = gpmc_probe, 1691 .probe = gpmc_probe,
1637 .remove = gpmc_remove, 1692 .remove = gpmc_remove,
@@ -1639,6 +1694,7 @@ static struct platform_driver gpmc_driver = {
1639 .name = DEVICE_NAME, 1694 .name = DEVICE_NAME,
1640 .owner = THIS_MODULE, 1695 .owner = THIS_MODULE,
1641 .of_match_table = of_match_ptr(gpmc_dt_ids), 1696 .of_match_table = of_match_ptr(gpmc_dt_ids),
1697 .pm = &gpmc_pm_ops,
1642 }, 1698 },
1643}; 1699};
1644 1700
@@ -1678,7 +1734,7 @@ static int __init omap_gpmc_init(void)
1678 pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0); 1734 pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0);
1679 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name); 1735 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
1680 1736
1681 return IS_ERR(pdev) ? PTR_ERR(pdev) : 0; 1737 return PTR_RET(pdev);
1682} 1738}
1683omap_postcore_initcall(omap_gpmc_init); 1739omap_postcore_initcall(omap_gpmc_init);
1684 1740
@@ -1701,7 +1757,6 @@ static irqreturn_t gpmc_handle_irq(int irq, void *dev)
1701 return IRQ_HANDLED; 1757 return IRQ_HANDLED;
1702} 1758}
1703 1759
1704#ifdef CONFIG_ARCH_OMAP3
1705static struct omap3_gpmc_regs gpmc_context; 1760static struct omap3_gpmc_regs gpmc_context;
1706 1761
1707void omap3_gpmc_save_context(void) 1762void omap3_gpmc_save_context(void)
@@ -1715,7 +1770,7 @@ void omap3_gpmc_save_context(void)
1715 gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1); 1770 gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
1716 gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2); 1771 gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
1717 gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL); 1772 gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
1718 for (i = 0; i < GPMC_CS_NUM; i++) { 1773 for (i = 0; i < gpmc_cs_num; i++) {
1719 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i); 1774 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
1720 if (gpmc_context.cs_context[i].is_valid) { 1775 if (gpmc_context.cs_context[i].is_valid) {
1721 gpmc_context.cs_context[i].config1 = 1776 gpmc_context.cs_context[i].config1 =
@@ -1747,7 +1802,7 @@ void omap3_gpmc_restore_context(void)
1747 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1); 1802 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
1748 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2); 1803 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
1749 gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control); 1804 gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
1750 for (i = 0; i < GPMC_CS_NUM; i++) { 1805 for (i = 0; i < gpmc_cs_num; i++) {
1751 if (gpmc_context.cs_context[i].is_valid) { 1806 if (gpmc_context.cs_context[i].is_valid) {
1752 gpmc_cs_write_reg(i, GPMC_CS_CONFIG1, 1807 gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
1753 gpmc_context.cs_context[i].config1); 1808 gpmc_context.cs_context[i].config1);
@@ -1766,4 +1821,3 @@ void omap3_gpmc_restore_context(void)
1766 } 1821 }
1767 } 1822 }
1768} 1823}
1769#endif /* CONFIG_ARCH_OMAP3 */
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 2ef1f8714fcf..07d4c7b35754 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -29,7 +29,6 @@
29 29
30static u16 control_pbias_offset; 30static u16 control_pbias_offset;
31static u16 control_devconf1_offset; 31static u16 control_devconf1_offset;
32static u16 control_mmc1;
33 32
34#define HSMMC_NAME_LEN 9 33#define HSMMC_NAME_LEN 9
35 34
@@ -121,57 +120,6 @@ static void omap_hsmmc1_after_set_reg(struct device *dev, int slot,
121 } 120 }
122} 121}
123 122
124static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
125 int power_on, int vdd)
126{
127 u32 reg;
128
129 /*
130 * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
131 * card with Vcc regulator (from twl4030 or whatever). OMAP has both
132 * 1.8V and 3.0V modes, controlled by the PBIAS register.
133 */
134 reg = omap4_ctrl_pad_readl(control_pbias_offset);
135 reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
136 OMAP4_MMC1_PWRDNZ_MASK |
137 OMAP4_MMC1_PBIASLITE_VMODE_MASK);
138 omap4_ctrl_pad_writel(reg, control_pbias_offset);
139}
140
141static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
142 int power_on, int vdd)
143{
144 u32 reg;
145 unsigned long timeout;
146
147 if (power_on) {
148 reg = omap4_ctrl_pad_readl(control_pbias_offset);
149 reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK;
150 if ((1 << vdd) <= MMC_VDD_165_195)
151 reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK;
152 else
153 reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK;
154 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
155 OMAP4_MMC1_PWRDNZ_MASK);
156 omap4_ctrl_pad_writel(reg, control_pbias_offset);
157
158 timeout = jiffies + msecs_to_jiffies(5);
159 do {
160 reg = omap4_ctrl_pad_readl(control_pbias_offset);
161 if (!(reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK))
162 break;
163 usleep_range(100, 200);
164 } while (!time_after(jiffies, timeout));
165
166 if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) {
167 pr_err("Pbias Voltage is not same as LDO\n");
168 /* Caution : On VMODE_ERROR Power Down MMC IO */
169 reg &= ~(OMAP4_MMC1_PWRDNZ_MASK);
170 omap4_ctrl_pad_writel(reg, control_pbias_offset);
171 }
172 }
173}
174
175static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc) 123static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc)
176{ 124{
177 u32 reg; 125 u32 reg;
@@ -317,11 +265,7 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
317 mmc->slots[0].pm_caps = c->pm_caps; 265 mmc->slots[0].pm_caps = c->pm_caps;
318 mmc->slots[0].internal_clock = !c->ext_clock; 266 mmc->slots[0].internal_clock = !c->ext_clock;
319 mmc->max_freq = c->max_freq; 267 mmc->max_freq = c->max_freq;
320 if (cpu_is_omap44xx()) 268 mmc->reg_offset = 0;
321 mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
322 else
323 mmc->reg_offset = 0;
324
325 mmc->get_context_loss_count = hsmmc_get_context_loss; 269 mmc->get_context_loss_count = hsmmc_get_context_loss;
326 270
327 mmc->slots[0].switch_pin = c->gpio_cd; 271 mmc->slots[0].switch_pin = c->gpio_cd;
@@ -368,24 +312,14 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
368 if (!soc_is_am35xx()) 312 if (!soc_is_am35xx())
369 mmc->slots[0].features |= HSMMC_HAS_PBIAS; 313 mmc->slots[0].features |= HSMMC_HAS_PBIAS;
370 314
371 if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
372 mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
373
374 switch (c->mmc) { 315 switch (c->mmc) {
375 case 1: 316 case 1:
376 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { 317 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
377 /* on-chip level shifting via PBIAS0/PBIAS1 */ 318 /* on-chip level shifting via PBIAS0/PBIAS1 */
378 if (cpu_is_omap44xx()) { 319 mmc->slots[0].before_set_reg =
379 mmc->slots[0].before_set_reg = 320 omap_hsmmc1_before_set_reg;
380 omap4_hsmmc1_before_set_reg; 321 mmc->slots[0].after_set_reg =
381 mmc->slots[0].after_set_reg = 322 omap_hsmmc1_after_set_reg;
382 omap4_hsmmc1_after_set_reg;
383 } else {
384 mmc->slots[0].before_set_reg =
385 omap_hsmmc1_before_set_reg;
386 mmc->slots[0].after_set_reg =
387 omap_hsmmc1_after_set_reg;
388 }
389 } 323 }
390 324
391 if (soc_is_am35xx()) 325 if (soc_is_am35xx())
@@ -563,34 +497,17 @@ free_mmc:
563 497
564void __init omap_hsmmc_init(struct omap2_hsmmc_info *controllers) 498void __init omap_hsmmc_init(struct omap2_hsmmc_info *controllers)
565{ 499{
566 u32 reg;
567
568 if (omap_hsmmc_done) 500 if (omap_hsmmc_done)
569 return; 501 return;
570 502
571 omap_hsmmc_done = 1; 503 omap_hsmmc_done = 1;
572 504
573 if (!cpu_is_omap44xx()) { 505 if (cpu_is_omap2430()) {
574 if (cpu_is_omap2430()) { 506 control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
575 control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; 507 control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
576 control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
577 } else {
578 control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
579 control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
580 }
581 } else { 508 } else {
582 control_pbias_offset = 509 control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
583 OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE; 510 control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
584 control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
585 reg = omap4_ctrl_pad_readl(control_mmc1);
586 reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
587 OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
588 reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
589 OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
590 reg |= (OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK |
591 OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
592 OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
593 omap4_ctrl_pad_writel(reg, control_mmc1);
594 } 511 }
595 512
596 for (; controllers->mmc; controllers++) 513 for (; controllers->mmc; controllers++)
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 1272c41d4749..2dc62a25f2c3 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -55,7 +55,7 @@ int omap_type(void)
55 55
56 if (cpu_is_omap24xx()) { 56 if (cpu_is_omap24xx()) {
57 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS); 57 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
58 } else if (soc_is_am33xx()) { 58 } else if (soc_is_am33xx() || soc_is_am43xx()) {
59 val = omap_ctrl_readl(AM33XX_CONTROL_STATUS); 59 val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
60 } else if (cpu_is_omap34xx()) { 60 } else if (cpu_is_omap34xx()) {
61 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); 61 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
@@ -209,6 +209,8 @@ static void __init omap3_cpuinfo(void)
209 cpu_name = "TI816X"; 209 cpu_name = "TI816X";
210 } else if (soc_is_am335x()) { 210 } else if (soc_is_am335x()) {
211 cpu_name = "AM335X"; 211 cpu_name = "AM335X";
212 } else if (soc_is_am437x()) {
213 cpu_name = "AM437x";
212 } else if (cpu_is_ti814x()) { 214 } else if (cpu_is_ti814x()) {
213 cpu_name = "TI814X"; 215 cpu_name = "TI814X";
214 } else if (omap3_has_iva() && omap3_has_sgx()) { 216 } else if (omap3_has_iva() && omap3_has_sgx()) {
@@ -302,6 +304,19 @@ void __init ti81xx_check_features(void)
302 omap3_cpuinfo(); 304 omap3_cpuinfo();
303} 305}
304 306
307void __init am33xx_check_features(void)
308{
309 u32 status;
310
311 omap_features = OMAP3_HAS_NEON;
312
313 status = omap_ctrl_readl(AM33XX_DEV_FEATURE);
314 if (status & AM33XX_SGX_MASK)
315 omap_features |= OMAP3_HAS_SGX;
316
317 omap3_cpuinfo();
318}
319
305void __init omap3xxx_check_revision(void) 320void __init omap3xxx_check_revision(void)
306{ 321{
307 const char *cpu_rev; 322 const char *cpu_rev;
@@ -405,11 +420,18 @@ void __init omap3xxx_check_revision(void)
405 cpu_rev = "1.0"; 420 cpu_rev = "1.0";
406 break; 421 break;
407 case 1: 422 case 1:
408 /* FALLTHROUGH */
409 default:
410 omap_revision = TI8168_REV_ES1_1; 423 omap_revision = TI8168_REV_ES1_1;
411 cpu_rev = "1.1"; 424 cpu_rev = "1.1";
412 break; 425 break;
426 case 2:
427 omap_revision = TI8168_REV_ES2_0;
428 cpu_rev = "2.0";
429 break;
430 case 3:
431 /* FALLTHROUGH */
432 default:
433 omap_revision = TI8168_REV_ES2_1;
434 cpu_rev = "2.1";
413 } 435 }
414 break; 436 break;
415 case 0xb944: 437 case 0xb944:
@@ -430,6 +452,10 @@ void __init omap3xxx_check_revision(void)
430 break; 452 break;
431 } 453 }
432 break; 454 break;
455 case 0xb98c:
456 omap_revision = AM437X_REV_ES1_0;
457 cpu_rev = "1.0";
458 break;
433 case 0xb8f2: 459 case 0xb8f2:
434 switch (rev) { 460 switch (rev) {
435 case 0: 461 case 0:
@@ -601,7 +627,7 @@ void __init omap2_set_globals_tap(u32 class, void __iomem *tap)
601 627
602#ifdef CONFIG_SOC_BUS 628#ifdef CONFIG_SOC_BUS
603 629
604static const char const *omap_types[] = { 630static const char * const omap_types[] = {
605 [OMAP2_DEVICE_TYPE_TEST] = "TST", 631 [OMAP2_DEVICE_TYPE_TEST] = "TST",
606 [OMAP2_DEVICE_TYPE_EMU] = "EMU", 632 [OMAP2_DEVICE_TYPE_EMU] = "EMU",
607 [OMAP2_DEVICE_TYPE_SEC] = "HS", 633 [OMAP2_DEVICE_TYPE_SEC] = "HS",
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 09abf99e9e57..4a3f06f02859 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -202,7 +202,7 @@ static struct map_desc omapti81xx_io_desc[] __initdata = {
202}; 202};
203#endif 203#endif
204 204
205#ifdef CONFIG_SOC_AM33XX 205#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
206static struct map_desc omapam33xx_io_desc[] __initdata = { 206static struct map_desc omapam33xx_io_desc[] __initdata = {
207 { 207 {
208 .virtual = L4_34XX_VIRT, 208 .virtual = L4_34XX_VIRT,
@@ -318,7 +318,7 @@ void __init ti81xx_map_io(void)
318} 318}
319#endif 319#endif
320 320
321#ifdef CONFIG_SOC_AM33XX 321#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
322void __init am33xx_map_io(void) 322void __init am33xx_map_io(void)
323{ 323{
324 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc)); 324 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
@@ -394,7 +394,7 @@ static void __init omap_hwmod_init_postsetup(void)
394 omap_pm_if_early_init(); 394 omap_pm_if_early_init();
395} 395}
396 396
397static void __init omap_common_late_init(void) 397static void __init __maybe_unused omap_common_late_init(void)
398{ 398{
399 omap_mux_late_init(); 399 omap_mux_late_init();
400 omap2_common_pm_late_init(); 400 omap2_common_pm_late_init();
@@ -576,8 +576,7 @@ void __init am33xx_init_early(void)
576 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE)); 576 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
577 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL); 577 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
578 omap3xxx_check_revision(); 578 omap3xxx_check_revision();
579 ti81xx_check_features(); 579 am33xx_check_features();
580 am33xx_voltagedomains_init();
581 am33xx_powerdomains_init(); 580 am33xx_powerdomains_init();
582 am33xx_clockdomains_init(); 581 am33xx_clockdomains_init();
583 am33xx_hwmod_init(); 582 am33xx_hwmod_init();
@@ -586,6 +585,19 @@ void __init am33xx_init_early(void)
586} 585}
587#endif 586#endif
588 587
588#ifdef CONFIG_SOC_AM43XX
589void __init am43xx_init_early(void)
590{
591 omap2_set_globals_tap(AM335X_CLASS,
592 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
593 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
594 NULL);
595 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE));
596 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL);
597 omap3xxx_check_revision();
598}
599#endif
600
589#ifdef CONFIG_ARCH_OMAP4 601#ifdef CONFIG_ARCH_OMAP4
590void __init omap4430_init_early(void) 602void __init omap4430_init_early(void)
591{ 603{
@@ -631,7 +643,13 @@ void __init omap5_init_early(void)
631 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); 643 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
632 omap_prm_base_init(); 644 omap_prm_base_init();
633 omap_cm_base_init(); 645 omap_cm_base_init();
646 omap44xx_prm_init();
634 omap5xxx_check_revision(); 647 omap5xxx_check_revision();
648 omap54xx_voltagedomains_init();
649 omap54xx_powerdomains_init();
650 omap54xx_clockdomains_init();
651 omap54xx_hwmod_init();
652 omap_hwmod_init_postsetup();
635} 653}
636#endif 654#endif
637 655
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
deleted file mode 100644
index 0b080267b7f6..000000000000
--- a/arch/arm/mach-omap2/mailbox.c
+++ /dev/null
@@ -1,430 +0,0 @@
1/*
2 * Mailbox reservation modules for OMAP2/3
3 *
4 * Copyright (C) 2006-2009 Nokia Corporation
5 * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
6 * and Paul Mundt
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12
13#include <linux/module.h>
14#include <linux/clk.h>
15#include <linux/err.h>
16#include <linux/platform_device.h>
17#include <linux/io.h>
18#include <linux/pm_runtime.h>
19
20#include <plat/mailbox.h>
21
22#include "soc.h"
23
24#define MAILBOX_REVISION 0x000
25#define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
26#define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
27#define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
28#define MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u))
29#define MAILBOX_IRQENABLE(u) (0x104 + 8 * (u))
30
31#define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 0x10 * (u))
32#define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 0x10 * (u))
33#define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 0x10 * (u))
34
35#define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m)))
36#define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1))
37
38#define MBOX_REG_SIZE 0x120
39
40#define OMAP4_MBOX_REG_SIZE 0x130
41
42#define MBOX_NR_REGS (MBOX_REG_SIZE / sizeof(u32))
43#define OMAP4_MBOX_NR_REGS (OMAP4_MBOX_REG_SIZE / sizeof(u32))
44
45static void __iomem *mbox_base;
46
47struct omap_mbox2_fifo {
48 unsigned long msg;
49 unsigned long fifo_stat;
50 unsigned long msg_stat;
51};
52
53struct omap_mbox2_priv {
54 struct omap_mbox2_fifo tx_fifo;
55 struct omap_mbox2_fifo rx_fifo;
56 unsigned long irqenable;
57 unsigned long irqstatus;
58 u32 newmsg_bit;
59 u32 notfull_bit;
60 u32 ctx[OMAP4_MBOX_NR_REGS];
61 unsigned long irqdisable;
62};
63
64static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
65 omap_mbox_type_t irq);
66
67static inline unsigned int mbox_read_reg(size_t ofs)
68{
69 return __raw_readl(mbox_base + ofs);
70}
71
72static inline void mbox_write_reg(u32 val, size_t ofs)
73{
74 __raw_writel(val, mbox_base + ofs);
75}
76
77/* Mailbox H/W preparations */
78static int omap2_mbox_startup(struct omap_mbox *mbox)
79{
80 u32 l;
81
82 pm_runtime_enable(mbox->dev->parent);
83 pm_runtime_get_sync(mbox->dev->parent);
84
85 l = mbox_read_reg(MAILBOX_REVISION);
86 pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
87
88 return 0;
89}
90
91static void omap2_mbox_shutdown(struct omap_mbox *mbox)
92{
93 pm_runtime_put_sync(mbox->dev->parent);
94 pm_runtime_disable(mbox->dev->parent);
95}
96
97/* Mailbox FIFO handle functions */
98static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
99{
100 struct omap_mbox2_fifo *fifo =
101 &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
102 return (mbox_msg_t) mbox_read_reg(fifo->msg);
103}
104
105static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
106{
107 struct omap_mbox2_fifo *fifo =
108 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
109 mbox_write_reg(msg, fifo->msg);
110}
111
112static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
113{
114 struct omap_mbox2_fifo *fifo =
115 &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
116 return (mbox_read_reg(fifo->msg_stat) == 0);
117}
118
119static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
120{
121 struct omap_mbox2_fifo *fifo =
122 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
123 return mbox_read_reg(fifo->fifo_stat);
124}
125
126/* Mailbox IRQ handle functions */
127static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
128 omap_mbox_type_t irq)
129{
130 struct omap_mbox2_priv *p = mbox->priv;
131 u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
132
133 l = mbox_read_reg(p->irqenable);
134 l |= bit;
135 mbox_write_reg(l, p->irqenable);
136}
137
138static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
139 omap_mbox_type_t irq)
140{
141 struct omap_mbox2_priv *p = mbox->priv;
142 u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
143
144 if (!cpu_is_omap44xx())
145 bit = mbox_read_reg(p->irqdisable) & ~bit;
146
147 mbox_write_reg(bit, p->irqdisable);
148}
149
150static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
151 omap_mbox_type_t irq)
152{
153 struct omap_mbox2_priv *p = mbox->priv;
154 u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
155
156 mbox_write_reg(bit, p->irqstatus);
157
158 /* Flush posted write for irq status to avoid spurious interrupts */
159 mbox_read_reg(p->irqstatus);
160}
161
162static int omap2_mbox_is_irq(struct omap_mbox *mbox,
163 omap_mbox_type_t irq)
164{
165 struct omap_mbox2_priv *p = mbox->priv;
166 u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
167 u32 enable = mbox_read_reg(p->irqenable);
168 u32 status = mbox_read_reg(p->irqstatus);
169
170 return (int)(enable & status & bit);
171}
172
173static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
174{
175 int i;
176 struct omap_mbox2_priv *p = mbox->priv;
177 int nr_regs;
178 if (cpu_is_omap44xx())
179 nr_regs = OMAP4_MBOX_NR_REGS;
180 else
181 nr_regs = MBOX_NR_REGS;
182 for (i = 0; i < nr_regs; i++) {
183 p->ctx[i] = mbox_read_reg(i * sizeof(u32));
184
185 dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
186 i, p->ctx[i]);
187 }
188}
189
190static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
191{
192 int i;
193 struct omap_mbox2_priv *p = mbox->priv;
194 int nr_regs;
195 if (cpu_is_omap44xx())
196 nr_regs = OMAP4_MBOX_NR_REGS;
197 else
198 nr_regs = MBOX_NR_REGS;
199 for (i = 0; i < nr_regs; i++) {
200 mbox_write_reg(p->ctx[i], i * sizeof(u32));
201
202 dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
203 i, p->ctx[i]);
204 }
205}
206
207static struct omap_mbox_ops omap2_mbox_ops = {
208 .type = OMAP_MBOX_TYPE2,
209 .startup = omap2_mbox_startup,
210 .shutdown = omap2_mbox_shutdown,
211 .fifo_read = omap2_mbox_fifo_read,
212 .fifo_write = omap2_mbox_fifo_write,
213 .fifo_empty = omap2_mbox_fifo_empty,
214 .fifo_full = omap2_mbox_fifo_full,
215 .enable_irq = omap2_mbox_enable_irq,
216 .disable_irq = omap2_mbox_disable_irq,
217 .ack_irq = omap2_mbox_ack_irq,
218 .is_irq = omap2_mbox_is_irq,
219 .save_ctx = omap2_mbox_save_ctx,
220 .restore_ctx = omap2_mbox_restore_ctx,
221};
222
223/*
224 * MAILBOX 0: ARM -> DSP,
225 * MAILBOX 1: ARM <- DSP.
226 * MAILBOX 2: ARM -> IVA,
227 * MAILBOX 3: ARM <- IVA.
228 */
229
230/* FIXME: the following structs should be filled automatically by the user id */
231
232#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP2)
233/* DSP */
234static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
235 .tx_fifo = {
236 .msg = MAILBOX_MESSAGE(0),
237 .fifo_stat = MAILBOX_FIFOSTATUS(0),
238 },
239 .rx_fifo = {
240 .msg = MAILBOX_MESSAGE(1),
241 .msg_stat = MAILBOX_MSGSTATUS(1),
242 },
243 .irqenable = MAILBOX_IRQENABLE(0),
244 .irqstatus = MAILBOX_IRQSTATUS(0),
245 .notfull_bit = MAILBOX_IRQ_NOTFULL(0),
246 .newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
247 .irqdisable = MAILBOX_IRQENABLE(0),
248};
249
250struct omap_mbox mbox_dsp_info = {
251 .name = "dsp",
252 .ops = &omap2_mbox_ops,
253 .priv = &omap2_mbox_dsp_priv,
254};
255#endif
256
257#if defined(CONFIG_ARCH_OMAP3)
258struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL };
259#endif
260
261#if defined(CONFIG_SOC_OMAP2420)
262/* IVA */
263static struct omap_mbox2_priv omap2_mbox_iva_priv = {
264 .tx_fifo = {
265 .msg = MAILBOX_MESSAGE(2),
266 .fifo_stat = MAILBOX_FIFOSTATUS(2),
267 },
268 .rx_fifo = {
269 .msg = MAILBOX_MESSAGE(3),
270 .msg_stat = MAILBOX_MSGSTATUS(3),
271 },
272 .irqenable = MAILBOX_IRQENABLE(3),
273 .irqstatus = MAILBOX_IRQSTATUS(3),
274 .notfull_bit = MAILBOX_IRQ_NOTFULL(2),
275 .newmsg_bit = MAILBOX_IRQ_NEWMSG(3),
276 .irqdisable = MAILBOX_IRQENABLE(3),
277};
278
279static struct omap_mbox mbox_iva_info = {
280 .name = "iva",
281 .ops = &omap2_mbox_ops,
282 .priv = &omap2_mbox_iva_priv,
283};
284#endif
285
286#ifdef CONFIG_ARCH_OMAP2
287struct omap_mbox *omap2_mboxes[] = {
288 &mbox_dsp_info,
289#ifdef CONFIG_SOC_OMAP2420
290 &mbox_iva_info,
291#endif
292 NULL
293};
294#endif
295
296#if defined(CONFIG_ARCH_OMAP4)
297/* OMAP4 */
298static struct omap_mbox2_priv omap2_mbox_1_priv = {
299 .tx_fifo = {
300 .msg = MAILBOX_MESSAGE(0),
301 .fifo_stat = MAILBOX_FIFOSTATUS(0),
302 },
303 .rx_fifo = {
304 .msg = MAILBOX_MESSAGE(1),
305 .msg_stat = MAILBOX_MSGSTATUS(1),
306 },
307 .irqenable = OMAP4_MAILBOX_IRQENABLE(0),
308 .irqstatus = OMAP4_MAILBOX_IRQSTATUS(0),
309 .notfull_bit = MAILBOX_IRQ_NOTFULL(0),
310 .newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
311 .irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(0),
312};
313
314struct omap_mbox mbox_1_info = {
315 .name = "mailbox-1",
316 .ops = &omap2_mbox_ops,
317 .priv = &omap2_mbox_1_priv,
318};
319
320static struct omap_mbox2_priv omap2_mbox_2_priv = {
321 .tx_fifo = {
322 .msg = MAILBOX_MESSAGE(3),
323 .fifo_stat = MAILBOX_FIFOSTATUS(3),
324 },
325 .rx_fifo = {
326 .msg = MAILBOX_MESSAGE(2),
327 .msg_stat = MAILBOX_MSGSTATUS(2),
328 },
329 .irqenable = OMAP4_MAILBOX_IRQENABLE(0),
330 .irqstatus = OMAP4_MAILBOX_IRQSTATUS(0),
331 .notfull_bit = MAILBOX_IRQ_NOTFULL(3),
332 .newmsg_bit = MAILBOX_IRQ_NEWMSG(2),
333 .irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(0),
334};
335
336struct omap_mbox mbox_2_info = {
337 .name = "mailbox-2",
338 .ops = &omap2_mbox_ops,
339 .priv = &omap2_mbox_2_priv,
340};
341
342struct omap_mbox *omap4_mboxes[] = { &mbox_1_info, &mbox_2_info, NULL };
343#endif
344
345static int omap2_mbox_probe(struct platform_device *pdev)
346{
347 struct resource *mem;
348 int ret;
349 struct omap_mbox **list;
350
351 if (false)
352 ;
353#if defined(CONFIG_ARCH_OMAP3)
354 else if (cpu_is_omap34xx()) {
355 list = omap3_mboxes;
356
357 list[0]->irq = platform_get_irq(pdev, 0);
358 }
359#endif
360#if defined(CONFIG_ARCH_OMAP2)
361 else if (cpu_is_omap2430()) {
362 list = omap2_mboxes;
363
364 list[0]->irq = platform_get_irq(pdev, 0);
365 } else if (cpu_is_omap2420()) {
366 list = omap2_mboxes;
367
368 list[0]->irq = platform_get_irq_byname(pdev, "dsp");
369 list[1]->irq = platform_get_irq_byname(pdev, "iva");
370 }
371#endif
372#if defined(CONFIG_ARCH_OMAP4)
373 else if (cpu_is_omap44xx()) {
374 list = omap4_mboxes;
375
376 list[0]->irq = list[1]->irq = platform_get_irq(pdev, 0);
377 }
378#endif
379 else {
380 pr_err("%s: platform not supported\n", __func__);
381 return -ENODEV;
382 }
383
384 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
385 mbox_base = ioremap(mem->start, resource_size(mem));
386 if (!mbox_base)
387 return -ENOMEM;
388
389 ret = omap_mbox_register(&pdev->dev, list);
390 if (ret) {
391 iounmap(mbox_base);
392 return ret;
393 }
394
395 return 0;
396}
397
398static int omap2_mbox_remove(struct platform_device *pdev)
399{
400 omap_mbox_unregister();
401 iounmap(mbox_base);
402 return 0;
403}
404
405static struct platform_driver omap2_mbox_driver = {
406 .probe = omap2_mbox_probe,
407 .remove = omap2_mbox_remove,
408 .driver = {
409 .name = "omap-mailbox",
410 },
411};
412
413static int __init omap2_mbox_init(void)
414{
415 return platform_driver_register(&omap2_mbox_driver);
416}
417
418static void __exit omap2_mbox_exit(void)
419{
420 platform_driver_unregister(&omap2_mbox_driver);
421}
422
423module_init(omap2_mbox_init);
424module_exit(omap2_mbox_exit);
425
426MODULE_LICENSE("GPL v2");
427MODULE_DESCRIPTION("omap mailbox: omap2/3/4 architecture specific functions");
428MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>");
429MODULE_AUTHOR("Paul Mundt");
430MODULE_ALIAS("platform:omap2-mailbox");
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index fdb22f14021f..5d2080ef7923 100644
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -10,7 +10,6 @@
10#include "mux2420.h" 10#include "mux2420.h"
11#include "mux2430.h" 11#include "mux2430.h"
12#include "mux34xx.h" 12#include "mux34xx.h"
13#include "mux44xx.h"
14 13
15#define OMAP_MUX_TERMINATOR 0xffff 14#define OMAP_MUX_TERMINATOR 0xffff
16 15
@@ -64,8 +63,6 @@
64 63
65/* Flags for omapX_mux_init */ 64/* Flags for omapX_mux_init */
66#define OMAP_PACKAGE_MASK 0xffff 65#define OMAP_PACKAGE_MASK 0xffff
67#define OMAP_PACKAGE_CBS 8 /* 547-pin 0.40 0.40 */
68#define OMAP_PACKAGE_CBL 7 /* 547-pin 0.40 0.40 */
69#define OMAP_PACKAGE_CBP 6 /* 515-pin 0.40 0.50 */ 66#define OMAP_PACKAGE_CBP 6 /* 515-pin 0.40 0.50 */
70#define OMAP_PACKAGE_CUS 5 /* 423-pin 0.65 */ 67#define OMAP_PACKAGE_CUS 5 /* 423-pin 0.65 */
71#define OMAP_PACKAGE_CBB 4 /* 515-pin 0.40 0.50 */ 68#define OMAP_PACKAGE_CBB 4 /* 515-pin 0.40 0.50 */
diff --git a/arch/arm/mach-omap2/mux44xx.c b/arch/arm/mach-omap2/mux44xx.c
deleted file mode 100644
index f5a74daab2ff..000000000000
--- a/arch/arm/mach-omap2/mux44xx.c
+++ /dev/null
@@ -1,1356 +0,0 @@
1/*
2 * OMAP44xx ES1.0 pin mux definition
3 *
4 * Copyright (C) 2010 Texas Instruments, Inc.
5 *
6 * Benoit Cousson (b-cousson@ti.com)
7 *
8 * - Based on mux34xx.c done by Tony Lindgren <tony@atomide.com>
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20#include <linux/module.h>
21#include <linux/init.h>
22
23#include "mux.h"
24
25#ifdef CONFIG_OMAP_MUX
26
27#define _OMAP4_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
28{ \
29 .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \
30 .gpio = (g), \
31 .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \
32}
33
34#else
35
36#define _OMAP4_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
37{ \
38 .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \
39 .gpio = (g), \
40}
41
42#endif
43
44#define _OMAP4_BALLENTRY(M0, bb, bt) \
45{ \
46 .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \
47 .balls = { bb, bt }, \
48}
49
50/*
51 * Superset of all mux modes for omap4 ES1.0
52 */
53static struct omap_mux __initdata omap4_core_muxmodes[] = {
54 _OMAP4_MUXENTRY(GPMC_AD0, 0, "gpmc_ad0", "sdmmc2_dat0", NULL, NULL,
55 NULL, NULL, NULL, NULL),
56 _OMAP4_MUXENTRY(GPMC_AD1, 0, "gpmc_ad1", "sdmmc2_dat1", NULL, NULL,
57 NULL, NULL, NULL, NULL),
58 _OMAP4_MUXENTRY(GPMC_AD2, 0, "gpmc_ad2", "sdmmc2_dat2", NULL, NULL,
59 NULL, NULL, NULL, NULL),
60 _OMAP4_MUXENTRY(GPMC_AD3, 0, "gpmc_ad3", "sdmmc2_dat3", NULL, NULL,
61 NULL, NULL, NULL, NULL),
62 _OMAP4_MUXENTRY(GPMC_AD4, 0, "gpmc_ad4", "sdmmc2_dat4",
63 "sdmmc2_dir_dat0", NULL, NULL, NULL, NULL, NULL),
64 _OMAP4_MUXENTRY(GPMC_AD5, 0, "gpmc_ad5", "sdmmc2_dat5",
65 "sdmmc2_dir_dat1", NULL, NULL, NULL, NULL, NULL),
66 _OMAP4_MUXENTRY(GPMC_AD6, 0, "gpmc_ad6", "sdmmc2_dat6",
67 "sdmmc2_dir_cmd", NULL, NULL, NULL, NULL, NULL),
68 _OMAP4_MUXENTRY(GPMC_AD7, 0, "gpmc_ad7", "sdmmc2_dat7",
69 "sdmmc2_clk_fdbk", NULL, NULL, NULL, NULL, NULL),
70 _OMAP4_MUXENTRY(GPMC_AD8, 32, "gpmc_ad8", "kpd_row0", "c2c_data15",
71 "gpio_32", NULL, NULL, NULL, NULL),
72 _OMAP4_MUXENTRY(GPMC_AD9, 33, "gpmc_ad9", "kpd_row1", "c2c_data14",
73 "gpio_33", NULL, NULL, NULL, NULL),
74 _OMAP4_MUXENTRY(GPMC_AD10, 34, "gpmc_ad10", "kpd_row2", "c2c_data13",
75 "gpio_34", NULL, NULL, NULL, NULL),
76 _OMAP4_MUXENTRY(GPMC_AD11, 35, "gpmc_ad11", "kpd_row3", "c2c_data12",
77 "gpio_35", NULL, NULL, NULL, NULL),
78 _OMAP4_MUXENTRY(GPMC_AD12, 36, "gpmc_ad12", "kpd_col0", "c2c_data11",
79 "gpio_36", NULL, NULL, NULL, NULL),
80 _OMAP4_MUXENTRY(GPMC_AD13, 37, "gpmc_ad13", "kpd_col1", "c2c_data10",
81 "gpio_37", NULL, NULL, NULL, NULL),
82 _OMAP4_MUXENTRY(GPMC_AD14, 38, "gpmc_ad14", "kpd_col2", "c2c_data9",
83 "gpio_38", NULL, NULL, NULL, NULL),
84 _OMAP4_MUXENTRY(GPMC_AD15, 39, "gpmc_ad15", "kpd_col3", "c2c_data8",
85 "gpio_39", NULL, NULL, NULL, NULL),
86 _OMAP4_MUXENTRY(GPMC_A16, 40, "gpmc_a16", "kpd_row4", "c2c_datain0",
87 "gpio_40", "venc_656_data0", NULL, NULL, NULL),
88 _OMAP4_MUXENTRY(GPMC_A17, 41, "gpmc_a17", "kpd_row5", "c2c_datain1",
89 "gpio_41", "venc_656_data1", NULL, NULL, "safe_mode"),
90 _OMAP4_MUXENTRY(GPMC_A18, 42, "gpmc_a18", "kpd_row6", "c2c_datain2",
91 "gpio_42", "venc_656_data2", NULL, NULL, "safe_mode"),
92 _OMAP4_MUXENTRY(GPMC_A19, 43, "gpmc_a19", "kpd_row7", "c2c_datain3",
93 "gpio_43", "venc_656_data3", NULL, NULL, "safe_mode"),
94 _OMAP4_MUXENTRY(GPMC_A20, 44, "gpmc_a20", "kpd_col4", "c2c_datain4",
95 "gpio_44", "venc_656_data4", NULL, NULL, "safe_mode"),
96 _OMAP4_MUXENTRY(GPMC_A21, 45, "gpmc_a21", "kpd_col5", "c2c_datain5",
97 "gpio_45", "venc_656_data5", NULL, NULL, "safe_mode"),
98 _OMAP4_MUXENTRY(GPMC_A22, 46, "gpmc_a22", "kpd_col6", "c2c_datain6",
99 "gpio_46", "venc_656_data6", NULL, NULL, "safe_mode"),
100 _OMAP4_MUXENTRY(GPMC_A23, 47, "gpmc_a23", "kpd_col7", "c2c_datain7",
101 "gpio_47", "venc_656_data7", NULL, NULL, "safe_mode"),
102 _OMAP4_MUXENTRY(GPMC_A24, 48, "gpmc_a24", NULL, "c2c_clkout0",
103 "gpio_48", NULL, NULL, NULL, "safe_mode"),
104 _OMAP4_MUXENTRY(GPMC_A25, 49, "gpmc_a25", NULL, "c2c_clkout1",
105 "gpio_49", NULL, NULL, NULL, "safe_mode"),
106 _OMAP4_MUXENTRY(GPMC_NCS0, 50, "gpmc_ncs0", NULL, NULL, "gpio_50",
107 "sys_ndmareq0", NULL, NULL, NULL),
108 _OMAP4_MUXENTRY(GPMC_NCS1, 51, "gpmc_ncs1", NULL, "c2c_dataout6",
109 "gpio_51", NULL, NULL, NULL, "safe_mode"),
110 _OMAP4_MUXENTRY(GPMC_NCS2, 52, "gpmc_ncs2", NULL, "c2c_dataout7",
111 "gpio_52", NULL, NULL, NULL, "safe_mode"),
112 _OMAP4_MUXENTRY(GPMC_NCS3, 53, "gpmc_ncs3", "gpmc_dir",
113 "c2c_dataout4", "gpio_53", NULL, NULL, NULL,
114 "safe_mode"),
115 _OMAP4_MUXENTRY(GPMC_NWP, 54, "gpmc_nwp", "dsi1_te0", NULL, "gpio_54",
116 "sys_ndmareq1", NULL, NULL, NULL),
117 _OMAP4_MUXENTRY(GPMC_CLK, 55, "gpmc_clk", NULL, NULL, "gpio_55",
118 "sys_ndmareq2", NULL, NULL, NULL),
119 _OMAP4_MUXENTRY(GPMC_NADV_ALE, 56, "gpmc_nadv_ale", "dsi1_te1", NULL,
120 "gpio_56", "sys_ndmareq3", NULL, NULL, NULL),
121 _OMAP4_MUXENTRY(GPMC_NOE, 0, "gpmc_noe", "sdmmc2_clk", NULL, NULL,
122 NULL, NULL, NULL, NULL),
123 _OMAP4_MUXENTRY(GPMC_NWE, 0, "gpmc_nwe", "sdmmc2_cmd", NULL, NULL,
124 NULL, NULL, NULL, NULL),
125 _OMAP4_MUXENTRY(GPMC_NBE0_CLE, 59, "gpmc_nbe0_cle", "dsi2_te0", NULL,
126 "gpio_59", NULL, NULL, NULL, NULL),
127 _OMAP4_MUXENTRY(GPMC_NBE1, 60, "gpmc_nbe1", NULL, "c2c_dataout5",
128 "gpio_60", NULL, NULL, NULL, "safe_mode"),
129 _OMAP4_MUXENTRY(GPMC_WAIT0, 61, "gpmc_wait0", "dsi2_te1", NULL,
130 "gpio_61", NULL, NULL, NULL, NULL),
131 _OMAP4_MUXENTRY(GPMC_WAIT1, 62, "gpmc_wait1", NULL, "c2c_dataout2",
132 "gpio_62", NULL, NULL, NULL, "safe_mode"),
133 _OMAP4_MUXENTRY(C2C_DATA11, 100, "c2c_data11", "usbc1_icusb_txen",
134 "c2c_dataout3", "gpio_100", "sys_ndmareq0", NULL,
135 NULL, "safe_mode"),
136 _OMAP4_MUXENTRY(C2C_DATA12, 101, "c2c_data12", "dsi1_te0",
137 "c2c_clkin0", "gpio_101", "sys_ndmareq1", NULL, NULL,
138 "safe_mode"),
139 _OMAP4_MUXENTRY(C2C_DATA13, 102, "c2c_data13", "dsi1_te1",
140 "c2c_clkin1", "gpio_102", "sys_ndmareq2", NULL, NULL,
141 "safe_mode"),
142 _OMAP4_MUXENTRY(C2C_DATA14, 103, "c2c_data14", "dsi2_te0",
143 "c2c_dataout0", "gpio_103", "sys_ndmareq3", NULL,
144 NULL, "safe_mode"),
145 _OMAP4_MUXENTRY(C2C_DATA15, 104, "c2c_data15", "dsi2_te1",
146 "c2c_dataout1", "gpio_104", NULL, NULL, NULL,
147 "safe_mode"),
148 _OMAP4_MUXENTRY(HDMI_HPD, 63, "hdmi_hpd", NULL, NULL, "gpio_63", NULL,
149 NULL, NULL, "safe_mode"),
150 _OMAP4_MUXENTRY(HDMI_CEC, 64, "hdmi_cec", NULL, NULL, "gpio_64", NULL,
151 NULL, NULL, "safe_mode"),
152 _OMAP4_MUXENTRY(HDMI_DDC_SCL, 65, "hdmi_ddc_scl", NULL, NULL,
153 "gpio_65", NULL, NULL, NULL, "safe_mode"),
154 _OMAP4_MUXENTRY(HDMI_DDC_SDA, 66, "hdmi_ddc_sda", NULL, NULL,
155 "gpio_66", NULL, NULL, NULL, "safe_mode"),
156 _OMAP4_MUXENTRY(CSI21_DX0, 0, "csi21_dx0", NULL, NULL, "gpi_67", NULL,
157 NULL, NULL, "safe_mode"),
158 _OMAP4_MUXENTRY(CSI21_DY0, 0, "csi21_dy0", NULL, NULL, "gpi_68", NULL,
159 NULL, NULL, "safe_mode"),
160 _OMAP4_MUXENTRY(CSI21_DX1, 0, "csi21_dx1", NULL, NULL, "gpi_69", NULL,
161 NULL, NULL, "safe_mode"),
162 _OMAP4_MUXENTRY(CSI21_DY1, 0, "csi21_dy1", NULL, NULL, "gpi_70", NULL,
163 NULL, NULL, "safe_mode"),
164 _OMAP4_MUXENTRY(CSI21_DX2, 0, "csi21_dx2", NULL, NULL, "gpi_71", NULL,
165 NULL, NULL, "safe_mode"),
166 _OMAP4_MUXENTRY(CSI21_DY2, 0, "csi21_dy2", NULL, NULL, "gpi_72", NULL,
167 NULL, NULL, "safe_mode"),
168 _OMAP4_MUXENTRY(CSI21_DX3, 0, "csi21_dx3", NULL, NULL, "gpi_73", NULL,
169 NULL, NULL, "safe_mode"),
170 _OMAP4_MUXENTRY(CSI21_DY3, 0, "csi21_dy3", NULL, NULL, "gpi_74", NULL,
171 NULL, NULL, "safe_mode"),
172 _OMAP4_MUXENTRY(CSI21_DX4, 0, "csi21_dx4", NULL, NULL, "gpi_75", NULL,
173 NULL, NULL, "safe_mode"),
174 _OMAP4_MUXENTRY(CSI21_DY4, 0, "csi21_dy4", NULL, NULL, "gpi_76", NULL,
175 NULL, NULL, "safe_mode"),
176 _OMAP4_MUXENTRY(CSI22_DX0, 0, "csi22_dx0", NULL, NULL, "gpi_77", NULL,
177 NULL, NULL, "safe_mode"),
178 _OMAP4_MUXENTRY(CSI22_DY0, 0, "csi22_dy0", NULL, NULL, "gpi_78", NULL,
179 NULL, NULL, "safe_mode"),
180 _OMAP4_MUXENTRY(CSI22_DX1, 0, "csi22_dx1", NULL, NULL, "gpi_79", NULL,
181 NULL, NULL, "safe_mode"),
182 _OMAP4_MUXENTRY(CSI22_DY1, 0, "csi22_dy1", NULL, NULL, "gpi_80", NULL,
183 NULL, NULL, "safe_mode"),
184 _OMAP4_MUXENTRY(CAM_SHUTTER, 81, "cam_shutter", NULL, NULL, "gpio_81",
185 NULL, NULL, NULL, "safe_mode"),
186 _OMAP4_MUXENTRY(CAM_STROBE, 82, "cam_strobe", NULL, NULL, "gpio_82",
187 NULL, NULL, NULL, "safe_mode"),
188 _OMAP4_MUXENTRY(CAM_GLOBALRESET, 83, "cam_globalreset", NULL, NULL,
189 "gpio_83", NULL, NULL, NULL, "safe_mode"),
190 _OMAP4_MUXENTRY(USBB1_ULPITLL_CLK, 84, "usbb1_ulpitll_clk",
191 "hsi1_cawake", NULL, "gpio_84", "usbb1_ulpiphy_clk",
192 NULL, "hw_dbg20", "safe_mode"),
193 _OMAP4_MUXENTRY(USBB1_ULPITLL_STP, 85, "usbb1_ulpitll_stp",
194 "hsi1_cadata", "mcbsp4_clkr", "gpio_85",
195 "usbb1_ulpiphy_stp", "usbb1_mm_rxdp", "hw_dbg21",
196 "safe_mode"),
197 _OMAP4_MUXENTRY(USBB1_ULPITLL_DIR, 86, "usbb1_ulpitll_dir",
198 "hsi1_caflag", "mcbsp4_fsr", "gpio_86",
199 "usbb1_ulpiphy_dir", NULL, "hw_dbg22", "safe_mode"),
200 _OMAP4_MUXENTRY(USBB1_ULPITLL_NXT, 87, "usbb1_ulpitll_nxt",
201 "hsi1_acready", "mcbsp4_fsx", "gpio_87",
202 "usbb1_ulpiphy_nxt", "usbb1_mm_rxdm", "hw_dbg23",
203 "safe_mode"),
204 _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT0, 88, "usbb1_ulpitll_dat0",
205 "hsi1_acwake", "mcbsp4_clkx", "gpio_88",
206 "usbb1_ulpiphy_dat0", "usbb1_mm_rxrcv", "hw_dbg24",
207 "safe_mode"),
208 _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT1, 89, "usbb1_ulpitll_dat1",
209 "hsi1_acdata", "mcbsp4_dx", "gpio_89",
210 "usbb1_ulpiphy_dat1", "usbb1_mm_txse0", "hw_dbg25",
211 "safe_mode"),
212 _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT2, 90, "usbb1_ulpitll_dat2",
213 "hsi1_acflag", "mcbsp4_dr", "gpio_90",
214 "usbb1_ulpiphy_dat2", "usbb1_mm_txdat", "hw_dbg26",
215 "safe_mode"),
216 _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT3, 91, "usbb1_ulpitll_dat3",
217 "hsi1_caready", NULL, "gpio_91", "usbb1_ulpiphy_dat3",
218 "usbb1_mm_txen", "hw_dbg27", "safe_mode"),
219 _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT4, 92, "usbb1_ulpitll_dat4",
220 "dmtimer8_pwm_evt", "abe_mcbsp3_dr", "gpio_92",
221 "usbb1_ulpiphy_dat4", NULL, "hw_dbg28", "safe_mode"),
222 _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT5, 93, "usbb1_ulpitll_dat5",
223 "dmtimer9_pwm_evt", "abe_mcbsp3_dx", "gpio_93",
224 "usbb1_ulpiphy_dat5", NULL, "hw_dbg29", "safe_mode"),
225 _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT6, 94, "usbb1_ulpitll_dat6",
226 "dmtimer10_pwm_evt", "abe_mcbsp3_clkx", "gpio_94",
227 "usbb1_ulpiphy_dat6", "abe_dmic_din3", "hw_dbg30",
228 "safe_mode"),
229 _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT7, 95, "usbb1_ulpitll_dat7",
230 "dmtimer11_pwm_evt", "abe_mcbsp3_fsx", "gpio_95",
231 "usbb1_ulpiphy_dat7", "abe_dmic_clk3", "hw_dbg31",
232 "safe_mode"),
233 _OMAP4_MUXENTRY(USBB1_HSIC_DATA, 96, "usbb1_hsic_data", NULL, NULL,
234 "gpio_96", NULL, NULL, NULL, "safe_mode"),
235 _OMAP4_MUXENTRY(USBB1_HSIC_STROBE, 97, "usbb1_hsic_strobe", NULL,
236 NULL, "gpio_97", NULL, NULL, NULL, "safe_mode"),
237 _OMAP4_MUXENTRY(USBC1_ICUSB_DP, 98, "usbc1_icusb_dp", NULL, NULL,
238 "gpio_98", NULL, NULL, NULL, "safe_mode"),
239 _OMAP4_MUXENTRY(USBC1_ICUSB_DM, 99, "usbc1_icusb_dm", NULL, NULL,
240 "gpio_99", NULL, NULL, NULL, "safe_mode"),
241 _OMAP4_MUXENTRY(SDMMC1_CLK, 100, "sdmmc1_clk", NULL, "dpm_emu19",
242 "gpio_100", NULL, NULL, NULL, "safe_mode"),
243 _OMAP4_MUXENTRY(SDMMC1_CMD, 101, "sdmmc1_cmd", NULL, "uart1_rx",
244 "gpio_101", NULL, NULL, NULL, "safe_mode"),
245 _OMAP4_MUXENTRY(SDMMC1_DAT0, 102, "sdmmc1_dat0", NULL, "dpm_emu18",
246 "gpio_102", NULL, NULL, NULL, "safe_mode"),
247 _OMAP4_MUXENTRY(SDMMC1_DAT1, 103, "sdmmc1_dat1", NULL, "dpm_emu17",
248 "gpio_103", NULL, NULL, NULL, "safe_mode"),
249 _OMAP4_MUXENTRY(SDMMC1_DAT2, 104, "sdmmc1_dat2", NULL, "dpm_emu16",
250 "gpio_104", "jtag_tms_tmsc", NULL, NULL, "safe_mode"),
251 _OMAP4_MUXENTRY(SDMMC1_DAT3, 105, "sdmmc1_dat3", NULL, "dpm_emu15",
252 "gpio_105", "jtag_tck", NULL, NULL, "safe_mode"),
253 _OMAP4_MUXENTRY(SDMMC1_DAT4, 106, "sdmmc1_dat4", NULL, NULL,
254 "gpio_106", NULL, NULL, NULL, "safe_mode"),
255 _OMAP4_MUXENTRY(SDMMC1_DAT5, 107, "sdmmc1_dat5", NULL, NULL,
256 "gpio_107", NULL, NULL, NULL, "safe_mode"),
257 _OMAP4_MUXENTRY(SDMMC1_DAT6, 108, "sdmmc1_dat6", NULL, NULL,
258 "gpio_108", NULL, NULL, NULL, "safe_mode"),
259 _OMAP4_MUXENTRY(SDMMC1_DAT7, 109, "sdmmc1_dat7", NULL, NULL,
260 "gpio_109", NULL, NULL, NULL, "safe_mode"),
261 _OMAP4_MUXENTRY(ABE_MCBSP2_CLKX, 110, "abe_mcbsp2_clkx", "mcspi2_clk",
262 "abe_mcasp_ahclkx", "gpio_110", "usbb2_mm_rxdm",
263 NULL, NULL, "safe_mode"),
264 _OMAP4_MUXENTRY(ABE_MCBSP2_DR, 111, "abe_mcbsp2_dr", "mcspi2_somi",
265 "abe_mcasp_axr", "gpio_111", "usbb2_mm_rxdp", NULL,
266 NULL, "safe_mode"),
267 _OMAP4_MUXENTRY(ABE_MCBSP2_DX, 112, "abe_mcbsp2_dx", "mcspi2_simo",
268 "abe_mcasp_amute", "gpio_112", "usbb2_mm_rxrcv", NULL,
269 NULL, "safe_mode"),
270 _OMAP4_MUXENTRY(ABE_MCBSP2_FSX, 113, "abe_mcbsp2_fsx", "mcspi2_cs0",
271 "abe_mcasp_afsx", "gpio_113", "usbb2_mm_txen", NULL,
272 NULL, "safe_mode"),
273 _OMAP4_MUXENTRY(ABE_MCBSP1_CLKX, 114, "abe_mcbsp1_clkx",
274 "abe_slimbus1_clock", NULL, "gpio_114", NULL, NULL,
275 NULL, "safe_mode"),
276 _OMAP4_MUXENTRY(ABE_MCBSP1_DR, 115, "abe_mcbsp1_dr",
277 "abe_slimbus1_data", NULL, "gpio_115", NULL, NULL,
278 NULL, "safe_mode"),
279 _OMAP4_MUXENTRY(ABE_MCBSP1_DX, 116, "abe_mcbsp1_dx", "sdmmc3_dat2",
280 "abe_mcasp_aclkx", "gpio_116", NULL, NULL, NULL,
281 "safe_mode"),
282 _OMAP4_MUXENTRY(ABE_MCBSP1_FSX, 117, "abe_mcbsp1_fsx", "sdmmc3_dat3",
283 "abe_mcasp_amutein", "gpio_117", NULL, NULL, NULL,
284 "safe_mode"),
285 _OMAP4_MUXENTRY(ABE_PDM_UL_DATA, 0, "abe_pdm_ul_data",
286 "abe_mcbsp3_dr", NULL, NULL, NULL, NULL, NULL,
287 "safe_mode"),
288 _OMAP4_MUXENTRY(ABE_PDM_DL_DATA, 0, "abe_pdm_dl_data",
289 "abe_mcbsp3_dx", NULL, NULL, NULL, NULL, NULL,
290 "safe_mode"),
291 _OMAP4_MUXENTRY(ABE_PDM_FRAME, 0, "abe_pdm_frame", "abe_mcbsp3_clkx",
292 NULL, NULL, NULL, NULL, NULL, "safe_mode"),
293 _OMAP4_MUXENTRY(ABE_PDM_LB_CLK, 0, "abe_pdm_lb_clk", "abe_mcbsp3_fsx",
294 NULL, NULL, NULL, NULL, NULL, "safe_mode"),
295 _OMAP4_MUXENTRY(ABE_CLKS, 118, "abe_clks", NULL, NULL, "gpio_118",
296 NULL, NULL, NULL, "safe_mode"),
297 _OMAP4_MUXENTRY(ABE_DMIC_CLK1, 119, "abe_dmic_clk1", NULL, NULL,
298 "gpio_119", "usbb2_mm_txse0", NULL, NULL,
299 "safe_mode"),
300 _OMAP4_MUXENTRY(ABE_DMIC_DIN1, 120, "abe_dmic_din1", NULL, NULL,
301 "gpio_120", "usbb2_mm_txdat", NULL, NULL,
302 "safe_mode"),
303 _OMAP4_MUXENTRY(ABE_DMIC_DIN2, 121, "abe_dmic_din2", "slimbus2_clock",
304 NULL, "gpio_121", NULL, NULL, NULL, "safe_mode"),
305 _OMAP4_MUXENTRY(ABE_DMIC_DIN3, 122, "abe_dmic_din3", "slimbus2_data",
306 "abe_dmic_clk2", "gpio_122", NULL, NULL, NULL,
307 "safe_mode"),
308 _OMAP4_MUXENTRY(UART2_CTS, 123, "uart2_cts", "sdmmc3_clk", NULL,
309 "gpio_123", NULL, NULL, NULL, "safe_mode"),
310 _OMAP4_MUXENTRY(UART2_RTS, 124, "uart2_rts", "sdmmc3_cmd", NULL,
311 "gpio_124", NULL, NULL, NULL, "safe_mode"),
312 _OMAP4_MUXENTRY(UART2_RX, 125, "uart2_rx", "sdmmc3_dat0", NULL,
313 "gpio_125", NULL, NULL, NULL, "safe_mode"),
314 _OMAP4_MUXENTRY(UART2_TX, 126, "uart2_tx", "sdmmc3_dat1", NULL,
315 "gpio_126", NULL, NULL, NULL, "safe_mode"),
316 _OMAP4_MUXENTRY(HDQ_SIO, 127, "hdq_sio", "i2c3_sccb", "i2c2_sccb",
317 "gpio_127", NULL, NULL, NULL, "safe_mode"),
318 _OMAP4_MUXENTRY(I2C1_SCL, 0, "i2c1_scl", NULL, NULL, NULL, NULL, NULL,
319 NULL, NULL),
320 _OMAP4_MUXENTRY(I2C1_SDA, 0, "i2c1_sda", NULL, NULL, NULL, NULL, NULL,
321 NULL, NULL),
322 _OMAP4_MUXENTRY(I2C2_SCL, 128, "i2c2_scl", "uart1_rx", NULL,
323 "gpio_128", NULL, NULL, NULL, "safe_mode"),
324 _OMAP4_MUXENTRY(I2C2_SDA, 129, "i2c2_sda", "uart1_tx", NULL,
325 "gpio_129", NULL, NULL, NULL, "safe_mode"),
326 _OMAP4_MUXENTRY(I2C3_SCL, 130, "i2c3_scl", NULL, NULL, "gpio_130",
327 NULL, NULL, NULL, "safe_mode"),
328 _OMAP4_MUXENTRY(I2C3_SDA, 131, "i2c3_sda", NULL, NULL, "gpio_131",
329 NULL, NULL, NULL, "safe_mode"),
330 _OMAP4_MUXENTRY(I2C4_SCL, 132, "i2c4_scl", NULL, NULL, "gpio_132",
331 NULL, NULL, NULL, "safe_mode"),
332 _OMAP4_MUXENTRY(I2C4_SDA, 133, "i2c4_sda", NULL, NULL, "gpio_133",
333 NULL, NULL, NULL, "safe_mode"),
334 _OMAP4_MUXENTRY(MCSPI1_CLK, 134, "mcspi1_clk", NULL, NULL, "gpio_134",
335 NULL, NULL, NULL, "safe_mode"),
336 _OMAP4_MUXENTRY(MCSPI1_SOMI, 135, "mcspi1_somi", NULL, NULL,
337 "gpio_135", NULL, NULL, NULL, "safe_mode"),
338 _OMAP4_MUXENTRY(MCSPI1_SIMO, 136, "mcspi1_simo", NULL, NULL,
339 "gpio_136", NULL, NULL, NULL, "safe_mode"),
340 _OMAP4_MUXENTRY(MCSPI1_CS0, 137, "mcspi1_cs0", NULL, NULL, "gpio_137",
341 NULL, NULL, NULL, "safe_mode"),
342 _OMAP4_MUXENTRY(MCSPI1_CS1, 138, "mcspi1_cs1", "uart1_rx", NULL,
343 "gpio_138", NULL, NULL, NULL, "safe_mode"),
344 _OMAP4_MUXENTRY(MCSPI1_CS2, 139, "mcspi1_cs2", "uart1_cts",
345 "slimbus2_clock", "gpio_139", NULL, NULL, NULL,
346 "safe_mode"),
347 _OMAP4_MUXENTRY(MCSPI1_CS3, 140, "mcspi1_cs3", "uart1_rts",
348 "slimbus2_data", "gpio_140", NULL, NULL, NULL,
349 "safe_mode"),
350 _OMAP4_MUXENTRY(UART3_CTS_RCTX, 141, "uart3_cts_rctx", "uart1_tx",
351 NULL, "gpio_141", NULL, NULL, NULL, "safe_mode"),
352 _OMAP4_MUXENTRY(UART3_RTS_SD, 142, "uart3_rts_sd", NULL, NULL,
353 "gpio_142", NULL, NULL, NULL, "safe_mode"),
354 _OMAP4_MUXENTRY(UART3_RX_IRRX, 143, "uart3_rx_irrx",
355 "dmtimer8_pwm_evt", NULL, "gpio_143", NULL, NULL,
356 NULL, "safe_mode"),
357 _OMAP4_MUXENTRY(UART3_TX_IRTX, 144, "uart3_tx_irtx",
358 "dmtimer9_pwm_evt", NULL, "gpio_144", NULL, NULL,
359 NULL, "safe_mode"),
360 _OMAP4_MUXENTRY(SDMMC5_CLK, 145, "sdmmc5_clk", "mcspi2_clk",
361 "usbc1_icusb_dp", "gpio_145", NULL, NULL, NULL,
362 "safe_mode"),
363 _OMAP4_MUXENTRY(SDMMC5_CMD, 146, "sdmmc5_cmd", "mcspi2_simo",
364 "usbc1_icusb_dm", "gpio_146", NULL, NULL, NULL,
365 "safe_mode"),
366 _OMAP4_MUXENTRY(SDMMC5_DAT0, 147, "sdmmc5_dat0", "mcspi2_somi",
367 "usbc1_icusb_rcv", "gpio_147", NULL, NULL, NULL,
368 "safe_mode"),
369 _OMAP4_MUXENTRY(SDMMC5_DAT1, 148, "sdmmc5_dat1", NULL,
370 "usbc1_icusb_txen", "gpio_148", NULL, NULL, NULL,
371 "safe_mode"),
372 _OMAP4_MUXENTRY(SDMMC5_DAT2, 149, "sdmmc5_dat2", "mcspi2_cs1", NULL,
373 "gpio_149", NULL, NULL, NULL, "safe_mode"),
374 _OMAP4_MUXENTRY(SDMMC5_DAT3, 150, "sdmmc5_dat3", "mcspi2_cs0", NULL,
375 "gpio_150", NULL, NULL, NULL, "safe_mode"),
376 _OMAP4_MUXENTRY(MCSPI4_CLK, 151, "mcspi4_clk", "sdmmc4_clk", NULL,
377 "gpio_151", NULL, NULL, NULL, "safe_mode"),
378 _OMAP4_MUXENTRY(MCSPI4_SIMO, 152, "mcspi4_simo", "sdmmc4_cmd", NULL,
379 "gpio_152", NULL, NULL, NULL, "safe_mode"),
380 _OMAP4_MUXENTRY(MCSPI4_SOMI, 153, "mcspi4_somi", "sdmmc4_dat0", NULL,
381 "gpio_153", NULL, NULL, NULL, "safe_mode"),
382 _OMAP4_MUXENTRY(MCSPI4_CS0, 154, "mcspi4_cs0", "sdmmc4_dat3", NULL,
383 "gpio_154", NULL, NULL, NULL, "safe_mode"),
384 _OMAP4_MUXENTRY(UART4_RX, 155, "uart4_rx", "sdmmc4_dat2", NULL,
385 "gpio_155", NULL, NULL, NULL, "safe_mode"),
386 _OMAP4_MUXENTRY(UART4_TX, 156, "uart4_tx", "sdmmc4_dat1", NULL,
387 "gpio_156", NULL, NULL, NULL, "safe_mode"),
388 _OMAP4_MUXENTRY(USBB2_ULPITLL_CLK, 157, "usbb2_ulpitll_clk",
389 "usbb2_ulpiphy_clk", "sdmmc4_cmd", "gpio_157",
390 "hsi2_cawake", NULL, NULL, "safe_mode"),
391 _OMAP4_MUXENTRY(USBB2_ULPITLL_STP, 158, "usbb2_ulpitll_stp",
392 "usbb2_ulpiphy_stp", "sdmmc4_clk", "gpio_158",
393 "hsi2_cadata", "dispc2_data23", NULL, "reserved"),
394 _OMAP4_MUXENTRY(USBB2_ULPITLL_DIR, 159, "usbb2_ulpitll_dir",
395 "usbb2_ulpiphy_dir", "sdmmc4_dat0", "gpio_159",
396 "hsi2_caflag", "dispc2_data22", NULL, "reserved"),
397 _OMAP4_MUXENTRY(USBB2_ULPITLL_NXT, 160, "usbb2_ulpitll_nxt",
398 "usbb2_ulpiphy_nxt", "sdmmc4_dat1", "gpio_160",
399 "hsi2_acready", "dispc2_data21", NULL, "reserved"),
400 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT0, 161, "usbb2_ulpitll_dat0",
401 "usbb2_ulpiphy_dat0", "sdmmc4_dat2", "gpio_161",
402 "hsi2_acwake", "dispc2_data20", NULL, "reserved"),
403 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT1, 162, "usbb2_ulpitll_dat1",
404 "usbb2_ulpiphy_dat1", "sdmmc4_dat3", "gpio_162",
405 "hsi2_acdata", "dispc2_data19", NULL, "reserved"),
406 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT2, 163, "usbb2_ulpitll_dat2",
407 "usbb2_ulpiphy_dat2", "sdmmc3_dat2", "gpio_163",
408 "hsi2_acflag", "dispc2_data18", NULL, "reserved"),
409 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT3, 164, "usbb2_ulpitll_dat3",
410 "usbb2_ulpiphy_dat3", "sdmmc3_dat1", "gpio_164",
411 "hsi2_caready", "dispc2_data15", NULL, "reserved"),
412 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT4, 165, "usbb2_ulpitll_dat4",
413 "usbb2_ulpiphy_dat4", "sdmmc3_dat0", "gpio_165",
414 "mcspi3_somi", "dispc2_data14", NULL, "reserved"),
415 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT5, 166, "usbb2_ulpitll_dat5",
416 "usbb2_ulpiphy_dat5", "sdmmc3_dat3", "gpio_166",
417 "mcspi3_cs0", "dispc2_data13", NULL, "reserved"),
418 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT6, 167, "usbb2_ulpitll_dat6",
419 "usbb2_ulpiphy_dat6", "sdmmc3_cmd", "gpio_167",
420 "mcspi3_simo", "dispc2_data12", NULL, "reserved"),
421 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT7, 168, "usbb2_ulpitll_dat7",
422 "usbb2_ulpiphy_dat7", "sdmmc3_clk", "gpio_168",
423 "mcspi3_clk", "dispc2_data11", NULL, "reserved"),
424 _OMAP4_MUXENTRY(USBB2_HSIC_DATA, 169, "usbb2_hsic_data", NULL, NULL,
425 "gpio_169", NULL, NULL, NULL, "safe_mode"),
426 _OMAP4_MUXENTRY(USBB2_HSIC_STROBE, 170, "usbb2_hsic_strobe", NULL,
427 NULL, "gpio_170", NULL, NULL, NULL, "safe_mode"),
428 _OMAP4_MUXENTRY(UNIPRO_TX0, 171, "unipro_tx0", "kpd_col0", NULL,
429 "gpio_171", NULL, NULL, NULL, "safe_mode"),
430 _OMAP4_MUXENTRY(UNIPRO_TY0, 172, "unipro_ty0", "kpd_col1", NULL,
431 "gpio_172", NULL, NULL, NULL, "safe_mode"),
432 _OMAP4_MUXENTRY(UNIPRO_TX1, 173, "unipro_tx1", "kpd_col2", NULL,
433 "gpio_173", NULL, NULL, NULL, "safe_mode"),
434 _OMAP4_MUXENTRY(UNIPRO_TY1, 174, "unipro_ty1", "kpd_col3", NULL,
435 "gpio_174", NULL, NULL, NULL, "safe_mode"),
436 _OMAP4_MUXENTRY(UNIPRO_TX2, 0, "unipro_tx2", "kpd_col4", NULL,
437 "gpio_0", NULL, NULL, NULL, "safe_mode"),
438 _OMAP4_MUXENTRY(UNIPRO_TY2, 1, "unipro_ty2", "kpd_col5", NULL,
439 "gpio_1", NULL, NULL, NULL, "safe_mode"),
440 _OMAP4_MUXENTRY(UNIPRO_RX0, 0, "unipro_rx0", "kpd_row0", NULL,
441 "gpi_175", NULL, NULL, NULL, "safe_mode"),
442 _OMAP4_MUXENTRY(UNIPRO_RY0, 0, "unipro_ry0", "kpd_row1", NULL,
443 "gpi_176", NULL, NULL, NULL, "safe_mode"),
444 _OMAP4_MUXENTRY(UNIPRO_RX1, 0, "unipro_rx1", "kpd_row2", NULL,
445 "gpi_177", NULL, NULL, NULL, "safe_mode"),
446 _OMAP4_MUXENTRY(UNIPRO_RY1, 0, "unipro_ry1", "kpd_row3", NULL,
447 "gpi_178", NULL, NULL, NULL, "safe_mode"),
448 _OMAP4_MUXENTRY(UNIPRO_RX2, 0, "unipro_rx2", "kpd_row4", NULL,
449 "gpi_2", NULL, NULL, NULL, "safe_mode"),
450 _OMAP4_MUXENTRY(UNIPRO_RY2, 0, "unipro_ry2", "kpd_row5", NULL,
451 "gpi_3", NULL, NULL, NULL, "safe_mode"),
452 _OMAP4_MUXENTRY(USBA0_OTG_CE, 0, "usba0_otg_ce", NULL, NULL, NULL,
453 NULL, NULL, NULL, NULL),
454 _OMAP4_MUXENTRY(USBA0_OTG_DP, 179, "usba0_otg_dp", "uart3_rx_irrx",
455 "uart2_rx", "gpio_179", NULL, NULL, NULL,
456 "safe_mode"),
457 _OMAP4_MUXENTRY(USBA0_OTG_DM, 180, "usba0_otg_dm", "uart3_tx_irtx",
458 "uart2_tx", "gpio_180", NULL, NULL, NULL,
459 "safe_mode"),
460 _OMAP4_MUXENTRY(FREF_CLK1_OUT, 181, "fref_clk1_out", NULL, NULL,
461 "gpio_181", NULL, NULL, NULL, "safe_mode"),
462 _OMAP4_MUXENTRY(FREF_CLK2_OUT, 182, "fref_clk2_out", NULL, NULL,
463 "gpio_182", NULL, NULL, NULL, "safe_mode"),
464 _OMAP4_MUXENTRY(SYS_NIRQ1, 0, "sys_nirq1", NULL, NULL, NULL, NULL,
465 NULL, NULL, "safe_mode"),
466 _OMAP4_MUXENTRY(SYS_NIRQ2, 183, "sys_nirq2", NULL, NULL, "gpio_183",
467 NULL, NULL, NULL, "safe_mode"),
468 _OMAP4_MUXENTRY(SYS_BOOT0, 184, "sys_boot0", NULL, NULL, "gpio_184",
469 NULL, NULL, NULL, "safe_mode"),
470 _OMAP4_MUXENTRY(SYS_BOOT1, 185, "sys_boot1", NULL, NULL, "gpio_185",
471 NULL, NULL, NULL, "safe_mode"),
472 _OMAP4_MUXENTRY(SYS_BOOT2, 186, "sys_boot2", NULL, NULL, "gpio_186",
473 NULL, NULL, NULL, "safe_mode"),
474 _OMAP4_MUXENTRY(SYS_BOOT3, 187, "sys_boot3", NULL, NULL, "gpio_187",
475 NULL, NULL, NULL, "safe_mode"),
476 _OMAP4_MUXENTRY(SYS_BOOT4, 188, "sys_boot4", NULL, NULL, "gpio_188",
477 NULL, NULL, NULL, "safe_mode"),
478 _OMAP4_MUXENTRY(SYS_BOOT5, 189, "sys_boot5", NULL, NULL, "gpio_189",
479 NULL, NULL, NULL, "safe_mode"),
480 _OMAP4_MUXENTRY(DPM_EMU0, 11, "dpm_emu0", NULL, NULL, "gpio_11", NULL,
481 NULL, "hw_dbg0", "safe_mode"),
482 _OMAP4_MUXENTRY(DPM_EMU1, 12, "dpm_emu1", NULL, NULL, "gpio_12", NULL,
483 NULL, "hw_dbg1", "safe_mode"),
484 _OMAP4_MUXENTRY(DPM_EMU2, 13, "dpm_emu2", "usba0_ulpiphy_clk", NULL,
485 "gpio_13", NULL, "dispc2_fid", "hw_dbg2", "reserved"),
486 _OMAP4_MUXENTRY(DPM_EMU3, 14, "dpm_emu3", "usba0_ulpiphy_stp", NULL,
487 "gpio_14", NULL, "dispc2_data10", "hw_dbg3",
488 "reserved"),
489 _OMAP4_MUXENTRY(DPM_EMU4, 15, "dpm_emu4", "usba0_ulpiphy_dir", NULL,
490 "gpio_15", NULL, "dispc2_data9", "hw_dbg4",
491 "reserved"),
492 _OMAP4_MUXENTRY(DPM_EMU5, 16, "dpm_emu5", "usba0_ulpiphy_nxt", NULL,
493 "gpio_16", "rfbi_te_vsync0", "dispc2_data16",
494 "hw_dbg5", "reserved"),
495 _OMAP4_MUXENTRY(DPM_EMU6, 17, "dpm_emu6", "usba0_ulpiphy_dat0",
496 "uart3_tx_irtx", "gpio_17", "rfbi_hsync0",
497 "dispc2_data17", "hw_dbg6", "reserved"),
498 _OMAP4_MUXENTRY(DPM_EMU7, 18, "dpm_emu7", "usba0_ulpiphy_dat1",
499 "uart3_rx_irrx", "gpio_18", "rfbi_cs0",
500 "dispc2_hsync", "hw_dbg7", "reserved"),
501 _OMAP4_MUXENTRY(DPM_EMU8, 19, "dpm_emu8", "usba0_ulpiphy_dat2",
502 "uart3_rts_sd", "gpio_19", "rfbi_re", "dispc2_pclk",
503 "hw_dbg8", "reserved"),
504 _OMAP4_MUXENTRY(DPM_EMU9, 20, "dpm_emu9", "usba0_ulpiphy_dat3",
505 "uart3_cts_rctx", "gpio_20", "rfbi_we",
506 "dispc2_vsync", "hw_dbg9", "reserved"),
507 _OMAP4_MUXENTRY(DPM_EMU10, 21, "dpm_emu10", "usba0_ulpiphy_dat4",
508 NULL, "gpio_21", "rfbi_a0", "dispc2_de", "hw_dbg10",
509 "reserved"),
510 _OMAP4_MUXENTRY(DPM_EMU11, 22, "dpm_emu11", "usba0_ulpiphy_dat5",
511 NULL, "gpio_22", "rfbi_data8", "dispc2_data8",
512 "hw_dbg11", "reserved"),
513 _OMAP4_MUXENTRY(DPM_EMU12, 23, "dpm_emu12", "usba0_ulpiphy_dat6",
514 NULL, "gpio_23", "rfbi_data7", "dispc2_data7",
515 "hw_dbg12", "reserved"),
516 _OMAP4_MUXENTRY(DPM_EMU13, 24, "dpm_emu13", "usba0_ulpiphy_dat7",
517 NULL, "gpio_24", "rfbi_data6", "dispc2_data6",
518 "hw_dbg13", "reserved"),
519 _OMAP4_MUXENTRY(DPM_EMU14, 25, "dpm_emu14", "sys_drm_msecure",
520 "uart1_rx", "gpio_25", "rfbi_data5", "dispc2_data5",
521 "hw_dbg14", "reserved"),
522 _OMAP4_MUXENTRY(DPM_EMU15, 26, "dpm_emu15", "sys_secure_indicator",
523 NULL, "gpio_26", "rfbi_data4", "dispc2_data4",
524 "hw_dbg15", "reserved"),
525 _OMAP4_MUXENTRY(DPM_EMU16, 27, "dpm_emu16", "dmtimer8_pwm_evt",
526 "dsi1_te0", "gpio_27", "rfbi_data3", "dispc2_data3",
527 "hw_dbg16", "reserved"),
528 _OMAP4_MUXENTRY(DPM_EMU17, 28, "dpm_emu17", "dmtimer9_pwm_evt",
529 "dsi1_te1", "gpio_28", "rfbi_data2", "dispc2_data2",
530 "hw_dbg17", "reserved"),
531 _OMAP4_MUXENTRY(DPM_EMU18, 190, "dpm_emu18", "dmtimer10_pwm_evt",
532 "dsi2_te0", "gpio_190", "rfbi_data1", "dispc2_data1",
533 "hw_dbg18", "reserved"),
534 _OMAP4_MUXENTRY(DPM_EMU19, 191, "dpm_emu19", "dmtimer11_pwm_evt",
535 "dsi2_te1", "gpio_191", "rfbi_data0", "dispc2_data0",
536 "hw_dbg19", "reserved"),
537 { .reg_offset = OMAP_MUX_TERMINATOR },
538};
539
540/*
541 * Balls for 44XX CBL package
542 * 547-pin CBL ES1.0 S-FPGA-N547, 0.40mm Ball Pitch (Top),
543 * 0.40mm Ball Pitch (Bottom)
544 */
545#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
546 && defined(CONFIG_OMAP_PACKAGE_CBL)
547static struct omap_ball __initdata omap4_core_cbl_ball[] = {
548 _OMAP4_BALLENTRY(GPMC_AD0, "c12", NULL),
549 _OMAP4_BALLENTRY(GPMC_AD1, "d12", NULL),
550 _OMAP4_BALLENTRY(GPMC_AD2, "c13", NULL),
551 _OMAP4_BALLENTRY(GPMC_AD3, "d13", NULL),
552 _OMAP4_BALLENTRY(GPMC_AD4, "c15", NULL),
553 _OMAP4_BALLENTRY(GPMC_AD5, "d15", NULL),
554 _OMAP4_BALLENTRY(GPMC_AD6, "a16", NULL),
555 _OMAP4_BALLENTRY(GPMC_AD7, "b16", NULL),
556 _OMAP4_BALLENTRY(GPMC_AD8, "c16", NULL),
557 _OMAP4_BALLENTRY(GPMC_AD9, "d16", NULL),
558 _OMAP4_BALLENTRY(GPMC_AD10, "c17", NULL),
559 _OMAP4_BALLENTRY(GPMC_AD11, "d17", NULL),
560 _OMAP4_BALLENTRY(GPMC_AD12, "c18", NULL),
561 _OMAP4_BALLENTRY(GPMC_AD13, "d18", NULL),
562 _OMAP4_BALLENTRY(GPMC_AD14, "c19", NULL),
563 _OMAP4_BALLENTRY(GPMC_AD15, "d19", NULL),
564 _OMAP4_BALLENTRY(GPMC_A16, "b17", NULL),
565 _OMAP4_BALLENTRY(GPMC_A17, "a18", NULL),
566 _OMAP4_BALLENTRY(GPMC_A18, "b18", NULL),
567 _OMAP4_BALLENTRY(GPMC_A19, "a19", NULL),
568 _OMAP4_BALLENTRY(GPMC_A20, "b19", NULL),
569 _OMAP4_BALLENTRY(GPMC_A21, "b20", NULL),
570 _OMAP4_BALLENTRY(GPMC_A22, "a21", NULL),
571 _OMAP4_BALLENTRY(GPMC_A23, "b21", NULL),
572 _OMAP4_BALLENTRY(GPMC_A24, "c20", NULL),
573 _OMAP4_BALLENTRY(GPMC_A25, "d20", NULL),
574 _OMAP4_BALLENTRY(GPMC_NCS0, "b25", NULL),
575 _OMAP4_BALLENTRY(GPMC_NCS1, "c21", NULL),
576 _OMAP4_BALLENTRY(GPMC_NCS2, "d21", NULL),
577 _OMAP4_BALLENTRY(GPMC_NCS3, "c22", NULL),
578 _OMAP4_BALLENTRY(GPMC_NWP, "c25", NULL),
579 _OMAP4_BALLENTRY(GPMC_CLK, "b22", NULL),
580 _OMAP4_BALLENTRY(GPMC_NADV_ALE, "d25", NULL),
581 _OMAP4_BALLENTRY(GPMC_NOE, "b11", NULL),
582 _OMAP4_BALLENTRY(GPMC_NWE, "b12", NULL),
583 _OMAP4_BALLENTRY(GPMC_NBE0_CLE, "c23", NULL),
584 _OMAP4_BALLENTRY(GPMC_NBE1, "d22", NULL),
585 _OMAP4_BALLENTRY(GPMC_WAIT0, "b26", NULL),
586 _OMAP4_BALLENTRY(GPMC_WAIT1, "b23", NULL),
587 _OMAP4_BALLENTRY(C2C_DATA11, "d23", NULL),
588 _OMAP4_BALLENTRY(C2C_DATA12, "a24", NULL),
589 _OMAP4_BALLENTRY(C2C_DATA13, "b24", NULL),
590 _OMAP4_BALLENTRY(C2C_DATA14, "c24", NULL),
591 _OMAP4_BALLENTRY(C2C_DATA15, "d24", NULL),
592 _OMAP4_BALLENTRY(HDMI_HPD, "b9", NULL),
593 _OMAP4_BALLENTRY(HDMI_CEC, "b10", NULL),
594 _OMAP4_BALLENTRY(HDMI_DDC_SCL, "a8", NULL),
595 _OMAP4_BALLENTRY(HDMI_DDC_SDA, "b8", NULL),
596 _OMAP4_BALLENTRY(CSI21_DX0, "r26", NULL),
597 _OMAP4_BALLENTRY(CSI21_DY0, "r25", NULL),
598 _OMAP4_BALLENTRY(CSI21_DX1, "t26", NULL),
599 _OMAP4_BALLENTRY(CSI21_DY1, "t25", NULL),
600 _OMAP4_BALLENTRY(CSI21_DX2, "u26", NULL),
601 _OMAP4_BALLENTRY(CSI21_DY2, "u25", NULL),
602 _OMAP4_BALLENTRY(CSI21_DX3, "v26", NULL),
603 _OMAP4_BALLENTRY(CSI21_DY3, "v25", NULL),
604 _OMAP4_BALLENTRY(CSI21_DX4, "w26", NULL),
605 _OMAP4_BALLENTRY(CSI21_DY4, "w25", NULL),
606 _OMAP4_BALLENTRY(CSI22_DX0, "m26", NULL),
607 _OMAP4_BALLENTRY(CSI22_DY0, "m25", NULL),
608 _OMAP4_BALLENTRY(CSI22_DX1, "n26", NULL),
609 _OMAP4_BALLENTRY(CSI22_DY1, "n25", NULL),
610 _OMAP4_BALLENTRY(CAM_SHUTTER, "t27", NULL),
611 _OMAP4_BALLENTRY(CAM_STROBE, "u27", NULL),
612 _OMAP4_BALLENTRY(CAM_GLOBALRESET, "v27", NULL),
613 _OMAP4_BALLENTRY(USBB1_ULPITLL_CLK, "ae18", NULL),
614 _OMAP4_BALLENTRY(USBB1_ULPITLL_STP, "ag19", NULL),
615 _OMAP4_BALLENTRY(USBB1_ULPITLL_DIR, "af19", NULL),
616 _OMAP4_BALLENTRY(USBB1_ULPITLL_NXT, "ae19", NULL),
617 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT0, "af18", NULL),
618 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT1, "ag18", NULL),
619 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT2, "ae17", NULL),
620 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT3, "af17", NULL),
621 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT4, "ah17", NULL),
622 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT5, "ae16", NULL),
623 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT6, "af16", NULL),
624 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT7, "ag16", NULL),
625 _OMAP4_BALLENTRY(USBB1_HSIC_DATA, "af14", NULL),
626 _OMAP4_BALLENTRY(USBB1_HSIC_STROBE, "ae14", NULL),
627 _OMAP4_BALLENTRY(USBC1_ICUSB_DP, "h2", NULL),
628 _OMAP4_BALLENTRY(USBC1_ICUSB_DM, "h3", NULL),
629 _OMAP4_BALLENTRY(SDMMC1_CLK, "d2", NULL),
630 _OMAP4_BALLENTRY(SDMMC1_CMD, "e3", NULL),
631 _OMAP4_BALLENTRY(SDMMC1_DAT0, "e4", NULL),
632 _OMAP4_BALLENTRY(SDMMC1_DAT1, "e2", NULL),
633 _OMAP4_BALLENTRY(SDMMC1_DAT2, "e1", NULL),
634 _OMAP4_BALLENTRY(SDMMC1_DAT3, "f4", NULL),
635 _OMAP4_BALLENTRY(SDMMC1_DAT4, "f3", NULL),
636 _OMAP4_BALLENTRY(SDMMC1_DAT5, "f1", NULL),
637 _OMAP4_BALLENTRY(SDMMC1_DAT6, "g4", NULL),
638 _OMAP4_BALLENTRY(SDMMC1_DAT7, "g3", NULL),
639 _OMAP4_BALLENTRY(ABE_MCBSP2_CLKX, "ad27", NULL),
640 _OMAP4_BALLENTRY(ABE_MCBSP2_DR, "ad26", NULL),
641 _OMAP4_BALLENTRY(ABE_MCBSP2_DX, "ad25", NULL),
642 _OMAP4_BALLENTRY(ABE_MCBSP2_FSX, "ac28", NULL),
643 _OMAP4_BALLENTRY(ABE_MCBSP1_CLKX, "ac26", NULL),
644 _OMAP4_BALLENTRY(ABE_MCBSP1_DR, "ac25", NULL),
645 _OMAP4_BALLENTRY(ABE_MCBSP1_DX, "ab25", NULL),
646 _OMAP4_BALLENTRY(ABE_MCBSP1_FSX, "ac27", NULL),
647 _OMAP4_BALLENTRY(ABE_PDM_UL_DATA, "ag25", NULL),
648 _OMAP4_BALLENTRY(ABE_PDM_DL_DATA, "af25", NULL),
649 _OMAP4_BALLENTRY(ABE_PDM_FRAME, "ae25", NULL),
650 _OMAP4_BALLENTRY(ABE_PDM_LB_CLK, "af26", NULL),
651 _OMAP4_BALLENTRY(ABE_CLKS, "ah26", NULL),
652 _OMAP4_BALLENTRY(ABE_DMIC_CLK1, "ae24", NULL),
653 _OMAP4_BALLENTRY(ABE_DMIC_DIN1, "af24", NULL),
654 _OMAP4_BALLENTRY(ABE_DMIC_DIN2, "ag24", NULL),
655 _OMAP4_BALLENTRY(ABE_DMIC_DIN3, "ah24", NULL),
656 _OMAP4_BALLENTRY(UART2_CTS, "ab26", NULL),
657 _OMAP4_BALLENTRY(UART2_RTS, "ab27", NULL),
658 _OMAP4_BALLENTRY(UART2_RX, "aa25", NULL),
659 _OMAP4_BALLENTRY(UART2_TX, "aa26", NULL),
660 _OMAP4_BALLENTRY(HDQ_SIO, "aa27", NULL),
661 _OMAP4_BALLENTRY(I2C1_SCL, "ae28", NULL),
662 _OMAP4_BALLENTRY(I2C1_SDA, "ae26", NULL),
663 _OMAP4_BALLENTRY(I2C2_SCL, "c26", NULL),
664 _OMAP4_BALLENTRY(I2C2_SDA, "d26", NULL),
665 _OMAP4_BALLENTRY(I2C3_SCL, "w27", NULL),
666 _OMAP4_BALLENTRY(I2C3_SDA, "y27", NULL),
667 _OMAP4_BALLENTRY(I2C4_SCL, "ag21", NULL),
668 _OMAP4_BALLENTRY(I2C4_SDA, "ah22", NULL),
669 _OMAP4_BALLENTRY(MCSPI1_CLK, "af22", NULL),
670 _OMAP4_BALLENTRY(MCSPI1_SOMI, "ae22", NULL),
671 _OMAP4_BALLENTRY(MCSPI1_SIMO, "ag22", NULL),
672 _OMAP4_BALLENTRY(MCSPI1_CS0, "ae23", NULL),
673 _OMAP4_BALLENTRY(MCSPI1_CS1, "af23", NULL),
674 _OMAP4_BALLENTRY(MCSPI1_CS2, "ag23", NULL),
675 _OMAP4_BALLENTRY(MCSPI1_CS3, "ah23", NULL),
676 _OMAP4_BALLENTRY(UART3_CTS_RCTX, "f27", NULL),
677 _OMAP4_BALLENTRY(UART3_RTS_SD, "f28", NULL),
678 _OMAP4_BALLENTRY(UART3_RX_IRRX, "g27", NULL),
679 _OMAP4_BALLENTRY(UART3_TX_IRTX, "g28", NULL),
680 _OMAP4_BALLENTRY(SDMMC5_CLK, "ae5", NULL),
681 _OMAP4_BALLENTRY(SDMMC5_CMD, "af5", NULL),
682 _OMAP4_BALLENTRY(SDMMC5_DAT0, "ae4", NULL),
683 _OMAP4_BALLENTRY(SDMMC5_DAT1, "af4", NULL),
684 _OMAP4_BALLENTRY(SDMMC5_DAT2, "ag3", NULL),
685 _OMAP4_BALLENTRY(SDMMC5_DAT3, "af3", NULL),
686 _OMAP4_BALLENTRY(MCSPI4_CLK, "ae21", NULL),
687 _OMAP4_BALLENTRY(MCSPI4_SIMO, "af20", NULL),
688 _OMAP4_BALLENTRY(MCSPI4_SOMI, "af21", NULL),
689 _OMAP4_BALLENTRY(MCSPI4_CS0, "ae20", NULL),
690 _OMAP4_BALLENTRY(UART4_RX, "ag20", NULL),
691 _OMAP4_BALLENTRY(UART4_TX, "ah19", NULL),
692 _OMAP4_BALLENTRY(USBB2_ULPITLL_CLK, "ag12", NULL),
693 _OMAP4_BALLENTRY(USBB2_ULPITLL_STP, "af12", NULL),
694 _OMAP4_BALLENTRY(USBB2_ULPITLL_DIR, "ae12", NULL),
695 _OMAP4_BALLENTRY(USBB2_ULPITLL_NXT, "ag13", NULL),
696 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT0, "ae11", NULL),
697 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT1, "af11", NULL),
698 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT2, "ag11", NULL),
699 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT3, "ah11", NULL),
700 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT4, "ae10", NULL),
701 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT5, "af10", NULL),
702 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT6, "ag10", NULL),
703 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT7, "ae9", NULL),
704 _OMAP4_BALLENTRY(USBB2_HSIC_DATA, "af13", NULL),
705 _OMAP4_BALLENTRY(USBB2_HSIC_STROBE, "ae13", NULL),
706 _OMAP4_BALLENTRY(UNIPRO_TX0, "g26", NULL),
707 _OMAP4_BALLENTRY(UNIPRO_TY0, "g25", NULL),
708 _OMAP4_BALLENTRY(UNIPRO_TX1, "h26", NULL),
709 _OMAP4_BALLENTRY(UNIPRO_TY1, "h25", NULL),
710 _OMAP4_BALLENTRY(UNIPRO_TX2, "j27", NULL),
711 _OMAP4_BALLENTRY(UNIPRO_TY2, "h27", NULL),
712 _OMAP4_BALLENTRY(UNIPRO_RX0, "j26", NULL),
713 _OMAP4_BALLENTRY(UNIPRO_RY0, "j25", NULL),
714 _OMAP4_BALLENTRY(UNIPRO_RX1, "k26", NULL),
715 _OMAP4_BALLENTRY(UNIPRO_RY1, "k25", NULL),
716 _OMAP4_BALLENTRY(UNIPRO_RX2, "l27", NULL),
717 _OMAP4_BALLENTRY(UNIPRO_RY2, "k27", NULL),
718 _OMAP4_BALLENTRY(USBA0_OTG_CE, "c3", NULL),
719 _OMAP4_BALLENTRY(USBA0_OTG_DP, "b5", NULL),
720 _OMAP4_BALLENTRY(USBA0_OTG_DM, "b4", NULL),
721 _OMAP4_BALLENTRY(FREF_CLK1_OUT, "aa28", NULL),
722 _OMAP4_BALLENTRY(FREF_CLK2_OUT, "y28", NULL),
723 _OMAP4_BALLENTRY(SYS_NIRQ1, "ae6", NULL),
724 _OMAP4_BALLENTRY(SYS_NIRQ2, "af6", NULL),
725 _OMAP4_BALLENTRY(SYS_BOOT0, "f26", NULL),
726 _OMAP4_BALLENTRY(SYS_BOOT1, "e27", NULL),
727 _OMAP4_BALLENTRY(SYS_BOOT2, "e26", NULL),
728 _OMAP4_BALLENTRY(SYS_BOOT3, "e25", NULL),
729 _OMAP4_BALLENTRY(SYS_BOOT4, "d28", NULL),
730 _OMAP4_BALLENTRY(SYS_BOOT5, "d27", NULL),
731 _OMAP4_BALLENTRY(DPM_EMU0, "m2", NULL),
732 _OMAP4_BALLENTRY(DPM_EMU1, "n2", NULL),
733 _OMAP4_BALLENTRY(DPM_EMU2, "p2", NULL),
734 _OMAP4_BALLENTRY(DPM_EMU3, "v1", NULL),
735 _OMAP4_BALLENTRY(DPM_EMU4, "v2", NULL),
736 _OMAP4_BALLENTRY(DPM_EMU5, "w1", NULL),
737 _OMAP4_BALLENTRY(DPM_EMU6, "w2", NULL),
738 _OMAP4_BALLENTRY(DPM_EMU7, "w3", NULL),
739 _OMAP4_BALLENTRY(DPM_EMU8, "w4", NULL),
740 _OMAP4_BALLENTRY(DPM_EMU9, "y2", NULL),
741 _OMAP4_BALLENTRY(DPM_EMU10, "y3", NULL),
742 _OMAP4_BALLENTRY(DPM_EMU11, "y4", NULL),
743 _OMAP4_BALLENTRY(DPM_EMU12, "aa1", NULL),
744 _OMAP4_BALLENTRY(DPM_EMU13, "aa2", NULL),
745 _OMAP4_BALLENTRY(DPM_EMU14, "aa3", NULL),
746 _OMAP4_BALLENTRY(DPM_EMU15, "aa4", NULL),
747 _OMAP4_BALLENTRY(DPM_EMU16, "ab2", NULL),
748 _OMAP4_BALLENTRY(DPM_EMU17, "ab3", NULL),
749 _OMAP4_BALLENTRY(DPM_EMU18, "ab4", NULL),
750 _OMAP4_BALLENTRY(DPM_EMU19, "ac4", NULL),
751 { .reg_offset = OMAP_MUX_TERMINATOR },
752};
753#else
754#define omap4_core_cbl_ball NULL
755#endif
756
757/*
758 * Signals different on ES2.0 compared to superset
759 */
760static struct omap_mux __initdata omap4_es2_core_subset[] = {
761 _OMAP4_MUXENTRY(GPMC_AD8, 32, "gpmc_ad8", "kpd_row0", "c2c_data15",
762 "gpio_32", NULL, "sdmmc1_dat0", NULL, NULL),
763 _OMAP4_MUXENTRY(GPMC_AD9, 33, "gpmc_ad9", "kpd_row1", "c2c_data14",
764 "gpio_33", NULL, "sdmmc1_dat1", NULL, NULL),
765 _OMAP4_MUXENTRY(GPMC_AD10, 34, "gpmc_ad10", "kpd_row2", "c2c_data13",
766 "gpio_34", NULL, "sdmmc1_dat2", NULL, NULL),
767 _OMAP4_MUXENTRY(GPMC_AD11, 35, "gpmc_ad11", "kpd_row3", "c2c_data12",
768 "gpio_35", NULL, "sdmmc1_dat3", NULL, NULL),
769 _OMAP4_MUXENTRY(GPMC_AD12, 36, "gpmc_ad12", "kpd_col0", "c2c_data11",
770 "gpio_36", NULL, "sdmmc1_dat4", NULL, NULL),
771 _OMAP4_MUXENTRY(GPMC_AD13, 37, "gpmc_ad13", "kpd_col1", "c2c_data10",
772 "gpio_37", NULL, "sdmmc1_dat5", NULL, NULL),
773 _OMAP4_MUXENTRY(GPMC_AD14, 38, "gpmc_ad14", "kpd_col2", "c2c_data9",
774 "gpio_38", NULL, "sdmmc1_dat6", NULL, NULL),
775 _OMAP4_MUXENTRY(GPMC_AD15, 39, "gpmc_ad15", "kpd_col3", "c2c_data8",
776 "gpio_39", NULL, "sdmmc1_dat7", NULL, NULL),
777 _OMAP4_MUXENTRY(GPMC_A16, 40, "gpmc_a16", "kpd_row4", "c2c_datain0",
778 "gpio_40", "venc_656_data0", NULL, NULL, "safe_mode"),
779 _OMAP4_MUXENTRY(GPMC_A24, 48, "gpmc_a24", "kpd_col8", "c2c_clkout0",
780 "gpio_48", NULL, NULL, NULL, "safe_mode"),
781 _OMAP4_MUXENTRY(GPMC_NCS2, 52, "gpmc_ncs2", "kpd_row8",
782 "c2c_dataout7", "gpio_52", NULL, NULL, NULL,
783 "safe_mode"),
784 _OMAP4_MUXENTRY(GPMC_CLK, 55, "gpmc_clk", NULL, NULL, "gpio_55",
785 "sys_ndmareq2", "sdmmc1_cmd", NULL, NULL),
786 _OMAP4_MUXENTRY(GPMC_NADV_ALE, 56, "gpmc_nadv_ale", "dsi1_te1", NULL,
787 "gpio_56", "sys_ndmareq3", "sdmmc1_clk", NULL, NULL),
788 _OMAP4_MUXENTRY(GPMC_WAIT2, 100, "gpmc_wait2", "usbc1_icusb_txen",
789 "c2c_dataout3", "gpio_100", "sys_ndmareq0", NULL,
790 NULL, "safe_mode"),
791 _OMAP4_MUXENTRY(GPMC_NCS4, 101, "gpmc_ncs4", "dsi1_te0", "c2c_clkin0",
792 "gpio_101", "sys_ndmareq1", NULL, NULL, "safe_mode"),
793 _OMAP4_MUXENTRY(GPMC_NCS5, 102, "gpmc_ncs5", "dsi1_te1", "c2c_clkin1",
794 "gpio_102", "sys_ndmareq2", NULL, NULL, "safe_mode"),
795 _OMAP4_MUXENTRY(GPMC_NCS6, 103, "gpmc_ncs6", "dsi2_te0",
796 "c2c_dataout0", "gpio_103", "sys_ndmareq3", NULL,
797 NULL, "safe_mode"),
798 _OMAP4_MUXENTRY(GPMC_NCS7, 104, "gpmc_ncs7", "dsi2_te1",
799 "c2c_dataout1", "gpio_104", NULL, NULL, NULL,
800 "safe_mode"),
801 _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT0, 88, "usbb1_ulpitll_dat0",
802 "hsi1_acwake", "mcbsp4_clkx", "gpio_88",
803 "usbb1_ulpiphy_dat0", "usbb1_mm_txen", "hw_dbg24",
804 "safe_mode"),
805 _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT1, 89, "usbb1_ulpitll_dat1",
806 "hsi1_acdata", "mcbsp4_dx", "gpio_89",
807 "usbb1_ulpiphy_dat1", "usbb1_mm_txdat", "hw_dbg25",
808 "safe_mode"),
809 _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT2, 90, "usbb1_ulpitll_dat2",
810 "hsi1_acflag", "mcbsp4_dr", "gpio_90",
811 "usbb1_ulpiphy_dat2", "usbb1_mm_txse0", "hw_dbg26",
812 "safe_mode"),
813 _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT3, 91, "usbb1_ulpitll_dat3",
814 "hsi1_caready", NULL, "gpio_91", "usbb1_ulpiphy_dat3",
815 "usbb1_mm_rxrcv", "hw_dbg27", "safe_mode"),
816 _OMAP4_MUXENTRY(ABE_DMIC_CLK1, 119, "abe_dmic_clk1", NULL, NULL,
817 "gpio_119", "usbb2_mm_txse0", "uart4_cts", NULL,
818 "safe_mode"),
819 _OMAP4_MUXENTRY(ABE_DMIC_DIN1, 120, "abe_dmic_din1", NULL, NULL,
820 "gpio_120", "usbb2_mm_txdat", "uart4_rts", NULL,
821 "safe_mode"),
822 _OMAP4_MUXENTRY(ABE_DMIC_DIN2, 121, "abe_dmic_din2", "slimbus2_clock",
823 "abe_mcasp_axr", "gpio_121", NULL,
824 "dmtimer11_pwm_evt", NULL, "safe_mode"),
825 _OMAP4_MUXENTRY(ABE_DMIC_DIN3, 122, "abe_dmic_din3", "slimbus2_data",
826 "abe_dmic_clk2", "gpio_122", NULL, "dmtimer9_pwm_evt",
827 NULL, "safe_mode"),
828 _OMAP4_MUXENTRY(SDMMC5_CLK, 145, "sdmmc5_clk", "mcspi2_clk",
829 "usbc1_icusb_dp", "gpio_145", NULL, "sdmmc2_clk",
830 NULL, "safe_mode"),
831 _OMAP4_MUXENTRY(SDMMC5_CMD, 146, "sdmmc5_cmd", "mcspi2_simo",
832 "usbc1_icusb_dm", "gpio_146", NULL, "sdmmc2_cmd",
833 NULL, "safe_mode"),
834 _OMAP4_MUXENTRY(SDMMC5_DAT0, 147, "sdmmc5_dat0", "mcspi2_somi",
835 "usbc1_icusb_rcv", "gpio_147", NULL, "sdmmc2_dat0",
836 NULL, "safe_mode"),
837 _OMAP4_MUXENTRY(SDMMC5_DAT1, 148, "sdmmc5_dat1", NULL,
838 "usbc1_icusb_txen", "gpio_148", NULL, "sdmmc2_dat1",
839 NULL, "safe_mode"),
840 _OMAP4_MUXENTRY(SDMMC5_DAT2, 149, "sdmmc5_dat2", "mcspi2_cs1", NULL,
841 "gpio_149", NULL, "sdmmc2_dat2", NULL, "safe_mode"),
842 _OMAP4_MUXENTRY(SDMMC5_DAT3, 150, "sdmmc5_dat3", "mcspi2_cs0", NULL,
843 "gpio_150", NULL, "sdmmc2_dat3", NULL, "safe_mode"),
844 _OMAP4_MUXENTRY(MCSPI4_CLK, 151, "mcspi4_clk", "sdmmc4_clk",
845 "kpd_col6", "gpio_151", NULL, NULL, NULL,
846 "safe_mode"),
847 _OMAP4_MUXENTRY(MCSPI4_SIMO, 152, "mcspi4_simo", "sdmmc4_cmd",
848 "kpd_col7", "gpio_152", NULL, NULL, NULL,
849 "safe_mode"),
850 _OMAP4_MUXENTRY(MCSPI4_SOMI, 153, "mcspi4_somi", "sdmmc4_dat0",
851 "kpd_row6", "gpio_153", NULL, NULL, NULL,
852 "safe_mode"),
853 _OMAP4_MUXENTRY(MCSPI4_CS0, 154, "mcspi4_cs0", "sdmmc4_dat3",
854 "kpd_row7", "gpio_154", NULL, NULL, NULL,
855 "safe_mode"),
856 _OMAP4_MUXENTRY(UART4_RX, 155, "uart4_rx", "sdmmc4_dat2", "kpd_row8",
857 "gpio_155", NULL, NULL, NULL, "safe_mode"),
858 _OMAP4_MUXENTRY(UART4_TX, 156, "uart4_tx", "sdmmc4_dat1", "kpd_col8",
859 "gpio_156", NULL, NULL, NULL, "safe_mode"),
860 _OMAP4_MUXENTRY(USBB2_ULPITLL_STP, 158, "usbb2_ulpitll_stp",
861 "usbb2_ulpiphy_stp", "sdmmc4_clk", "gpio_158",
862 "hsi2_cadata", "dispc2_data23", NULL, "safe_mode"),
863 _OMAP4_MUXENTRY(USBB2_ULPITLL_DIR, 159, "usbb2_ulpitll_dir",
864 "usbb2_ulpiphy_dir", "sdmmc4_dat0", "gpio_159",
865 "hsi2_caflag", "dispc2_data22", NULL, "safe_mode"),
866 _OMAP4_MUXENTRY(USBB2_ULPITLL_NXT, 160, "usbb2_ulpitll_nxt",
867 "usbb2_ulpiphy_nxt", "sdmmc4_dat1", "gpio_160",
868 "hsi2_acready", "dispc2_data21", NULL, "safe_mode"),
869 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT0, 161, "usbb2_ulpitll_dat0",
870 "usbb2_ulpiphy_dat0", "sdmmc4_dat2", "gpio_161",
871 "hsi2_acwake", "dispc2_data20", "usbb2_mm_txen",
872 "safe_mode"),
873 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT1, 162, "usbb2_ulpitll_dat1",
874 "usbb2_ulpiphy_dat1", "sdmmc4_dat3", "gpio_162",
875 "hsi2_acdata", "dispc2_data19", "usbb2_mm_txdat",
876 "safe_mode"),
877 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT2, 163, "usbb2_ulpitll_dat2",
878 "usbb2_ulpiphy_dat2", "sdmmc3_dat2", "gpio_163",
879 "hsi2_acflag", "dispc2_data18", "usbb2_mm_txse0",
880 "safe_mode"),
881 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT3, 164, "usbb2_ulpitll_dat3",
882 "usbb2_ulpiphy_dat3", "sdmmc3_dat1", "gpio_164",
883 "hsi2_caready", "dispc2_data15", "rfbi_data15",
884 "safe_mode"),
885 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT4, 165, "usbb2_ulpitll_dat4",
886 "usbb2_ulpiphy_dat4", "sdmmc3_dat0", "gpio_165",
887 "mcspi3_somi", "dispc2_data14", "rfbi_data14",
888 "safe_mode"),
889 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT5, 166, "usbb2_ulpitll_dat5",
890 "usbb2_ulpiphy_dat5", "sdmmc3_dat3", "gpio_166",
891 "mcspi3_cs0", "dispc2_data13", "rfbi_data13",
892 "safe_mode"),
893 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT6, 167, "usbb2_ulpitll_dat6",
894 "usbb2_ulpiphy_dat6", "sdmmc3_cmd", "gpio_167",
895 "mcspi3_simo", "dispc2_data12", "rfbi_data12",
896 "safe_mode"),
897 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT7, 168, "usbb2_ulpitll_dat7",
898 "usbb2_ulpiphy_dat7", "sdmmc3_clk", "gpio_168",
899 "mcspi3_clk", "dispc2_data11", "rfbi_data11",
900 "safe_mode"),
901 _OMAP4_MUXENTRY(KPD_COL3, 171, "kpd_col3", "kpd_col0", NULL,
902 "gpio_171", NULL, NULL, NULL, "safe_mode"),
903 _OMAP4_MUXENTRY(KPD_COL4, 172, "kpd_col4", "kpd_col1", NULL,
904 "gpio_172", NULL, NULL, NULL, "safe_mode"),
905 _OMAP4_MUXENTRY(KPD_COL5, 173, "kpd_col5", "kpd_col2", NULL,
906 "gpio_173", NULL, NULL, NULL, "safe_mode"),
907 _OMAP4_MUXENTRY(KPD_COL0, 174, "kpd_col0", "kpd_col3", NULL,
908 "gpio_174", NULL, NULL, NULL, "safe_mode"),
909 _OMAP4_MUXENTRY(KPD_COL1, 0, "kpd_col1", "kpd_col4", NULL, "gpio_0",
910 NULL, NULL, NULL, "safe_mode"),
911 _OMAP4_MUXENTRY(KPD_COL2, 1, "kpd_col2", "kpd_col5", NULL, "gpio_1",
912 NULL, NULL, NULL, "safe_mode"),
913 _OMAP4_MUXENTRY(KPD_ROW3, 175, "kpd_row3", "kpd_row0", NULL,
914 "gpio_175", NULL, NULL, NULL, "safe_mode"),
915 _OMAP4_MUXENTRY(KPD_ROW4, 176, "kpd_row4", "kpd_row1", NULL,
916 "gpio_176", NULL, NULL, NULL, "safe_mode"),
917 _OMAP4_MUXENTRY(KPD_ROW5, 177, "kpd_row5", "kpd_row2", NULL,
918 "gpio_177", NULL, NULL, NULL, "safe_mode"),
919 _OMAP4_MUXENTRY(KPD_ROW0, 178, "kpd_row0", "kpd_row3", NULL,
920 "gpio_178", NULL, NULL, NULL, "safe_mode"),
921 _OMAP4_MUXENTRY(KPD_ROW1, 2, "kpd_row1", "kpd_row4", NULL, "gpio_2",
922 NULL, NULL, NULL, "safe_mode"),
923 _OMAP4_MUXENTRY(KPD_ROW2, 3, "kpd_row2", "kpd_row5", NULL, "gpio_3",
924 NULL, NULL, NULL, "safe_mode"),
925 _OMAP4_MUXENTRY(USBA0_OTG_DP, 0, "usba0_otg_dp", "uart3_rx_irrx",
926 "uart2_rx", NULL, NULL, NULL, NULL, "safe_mode"),
927 _OMAP4_MUXENTRY(USBA0_OTG_DM, 0, "usba0_otg_dm", "uart3_tx_irtx",
928 "uart2_tx", NULL, NULL, NULL, NULL, "safe_mode"),
929 _OMAP4_MUXENTRY(DPM_EMU2, 13, "dpm_emu2", "usba0_ulpiphy_clk", NULL,
930 "gpio_13", NULL, "dispc2_fid", "hw_dbg2",
931 "safe_mode"),
932 _OMAP4_MUXENTRY(DPM_EMU3, 14, "dpm_emu3", "usba0_ulpiphy_stp", NULL,
933 "gpio_14", "rfbi_data10", "dispc2_data10", "hw_dbg3",
934 "safe_mode"),
935 _OMAP4_MUXENTRY(DPM_EMU4, 15, "dpm_emu4", "usba0_ulpiphy_dir", NULL,
936 "gpio_15", "rfbi_data9", "dispc2_data9", "hw_dbg4",
937 "safe_mode"),
938 _OMAP4_MUXENTRY(DPM_EMU5, 16, "dpm_emu5", "usba0_ulpiphy_nxt", NULL,
939 "gpio_16", "rfbi_te_vsync0", "dispc2_data16",
940 "hw_dbg5", "safe_mode"),
941 _OMAP4_MUXENTRY(DPM_EMU6, 17, "dpm_emu6", "usba0_ulpiphy_dat0",
942 "uart3_tx_irtx", "gpio_17", "rfbi_hsync0",
943 "dispc2_data17", "hw_dbg6", "safe_mode"),
944 _OMAP4_MUXENTRY(DPM_EMU7, 18, "dpm_emu7", "usba0_ulpiphy_dat1",
945 "uart3_rx_irrx", "gpio_18", "rfbi_cs0",
946 "dispc2_hsync", "hw_dbg7", "safe_mode"),
947 _OMAP4_MUXENTRY(DPM_EMU8, 19, "dpm_emu8", "usba0_ulpiphy_dat2",
948 "uart3_rts_sd", "gpio_19", "rfbi_re", "dispc2_pclk",
949 "hw_dbg8", "safe_mode"),
950 _OMAP4_MUXENTRY(DPM_EMU9, 20, "dpm_emu9", "usba0_ulpiphy_dat3",
951 "uart3_cts_rctx", "gpio_20", "rfbi_we",
952 "dispc2_vsync", "hw_dbg9", "safe_mode"),
953 _OMAP4_MUXENTRY(DPM_EMU10, 21, "dpm_emu10", "usba0_ulpiphy_dat4",
954 NULL, "gpio_21", "rfbi_a0", "dispc2_de", "hw_dbg10",
955 "safe_mode"),
956 _OMAP4_MUXENTRY(DPM_EMU11, 22, "dpm_emu11", "usba0_ulpiphy_dat5",
957 NULL, "gpio_22", "rfbi_data8", "dispc2_data8",
958 "hw_dbg11", "safe_mode"),
959 _OMAP4_MUXENTRY(DPM_EMU12, 23, "dpm_emu12", "usba0_ulpiphy_dat6",
960 NULL, "gpio_23", "rfbi_data7", "dispc2_data7",
961 "hw_dbg12", "safe_mode"),
962 _OMAP4_MUXENTRY(DPM_EMU13, 24, "dpm_emu13", "usba0_ulpiphy_dat7",
963 NULL, "gpio_24", "rfbi_data6", "dispc2_data6",
964 "hw_dbg13", "safe_mode"),
965 _OMAP4_MUXENTRY(DPM_EMU14, 25, "dpm_emu14", "sys_drm_msecure",
966 "uart1_rx", "gpio_25", "rfbi_data5", "dispc2_data5",
967 "hw_dbg14", "safe_mode"),
968 _OMAP4_MUXENTRY(DPM_EMU15, 26, "dpm_emu15", "sys_secure_indicator",
969 NULL, "gpio_26", "rfbi_data4", "dispc2_data4",
970 "hw_dbg15", "safe_mode"),
971 _OMAP4_MUXENTRY(DPM_EMU16, 27, "dpm_emu16", "dmtimer8_pwm_evt",
972 "dsi1_te0", "gpio_27", "rfbi_data3", "dispc2_data3",
973 "hw_dbg16", "safe_mode"),
974 _OMAP4_MUXENTRY(DPM_EMU17, 28, "dpm_emu17", "dmtimer9_pwm_evt",
975 "dsi1_te1", "gpio_28", "rfbi_data2", "dispc2_data2",
976 "hw_dbg17", "safe_mode"),
977 _OMAP4_MUXENTRY(DPM_EMU18, 190, "dpm_emu18", "dmtimer10_pwm_evt",
978 "dsi2_te0", "gpio_190", "rfbi_data1", "dispc2_data1",
979 "hw_dbg18", "safe_mode"),
980 _OMAP4_MUXENTRY(DPM_EMU19, 191, "dpm_emu19", "dmtimer11_pwm_evt",
981 "dsi2_te1", "gpio_191", "rfbi_data0", "dispc2_data0",
982 "hw_dbg19", "safe_mode"),
983 { .reg_offset = OMAP_MUX_TERMINATOR },
984};
985
986/*
987 * Balls for 44XX CBS package
988 * 547-pin CBL ES2.0 S-FPGA-N547, 0.40mm Ball Pitch (Top),
989 * 0.40mm Ball Pitch (Bottom)
990 */
991#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
992 && defined(CONFIG_OMAP_PACKAGE_CBS)
993static struct omap_ball __initdata omap4_core_cbs_ball[] = {
994 _OMAP4_BALLENTRY(GPMC_AD0, "c12", NULL),
995 _OMAP4_BALLENTRY(GPMC_AD1, "d12", NULL),
996 _OMAP4_BALLENTRY(GPMC_AD2, "c13", NULL),
997 _OMAP4_BALLENTRY(GPMC_AD3, "d13", NULL),
998 _OMAP4_BALLENTRY(GPMC_AD4, "c15", NULL),
999 _OMAP4_BALLENTRY(GPMC_AD5, "d15", NULL),
1000 _OMAP4_BALLENTRY(GPMC_AD6, "a16", NULL),
1001 _OMAP4_BALLENTRY(GPMC_AD7, "b16", NULL),
1002 _OMAP4_BALLENTRY(GPMC_AD8, "c16", NULL),
1003 _OMAP4_BALLENTRY(GPMC_AD9, "d16", NULL),
1004 _OMAP4_BALLENTRY(GPMC_AD10, "c17", NULL),
1005 _OMAP4_BALLENTRY(GPMC_AD11, "d17", NULL),
1006 _OMAP4_BALLENTRY(GPMC_AD12, "c18", NULL),
1007 _OMAP4_BALLENTRY(GPMC_AD13, "d18", NULL),
1008 _OMAP4_BALLENTRY(GPMC_AD14, "c19", NULL),
1009 _OMAP4_BALLENTRY(GPMC_AD15, "d19", NULL),
1010 _OMAP4_BALLENTRY(GPMC_A16, "b17", NULL),
1011 _OMAP4_BALLENTRY(GPMC_A17, "a18", NULL),
1012 _OMAP4_BALLENTRY(GPMC_A18, "b18", NULL),
1013 _OMAP4_BALLENTRY(GPMC_A19, "a19", NULL),
1014 _OMAP4_BALLENTRY(GPMC_A20, "b19", NULL),
1015 _OMAP4_BALLENTRY(GPMC_A21, "b20", NULL),
1016 _OMAP4_BALLENTRY(GPMC_A22, "a21", NULL),
1017 _OMAP4_BALLENTRY(GPMC_A23, "b21", NULL),
1018 _OMAP4_BALLENTRY(GPMC_A24, "c20", NULL),
1019 _OMAP4_BALLENTRY(GPMC_A25, "d20", NULL),
1020 _OMAP4_BALLENTRY(GPMC_NCS0, "b25", NULL),
1021 _OMAP4_BALLENTRY(GPMC_NCS1, "c21", NULL),
1022 _OMAP4_BALLENTRY(GPMC_NCS2, "d21", NULL),
1023 _OMAP4_BALLENTRY(GPMC_NCS3, "c22", NULL),
1024 _OMAP4_BALLENTRY(GPMC_NWP, "c25", NULL),
1025 _OMAP4_BALLENTRY(GPMC_CLK, "b22", NULL),
1026 _OMAP4_BALLENTRY(GPMC_NADV_ALE, "d25", NULL),
1027 _OMAP4_BALLENTRY(GPMC_NOE, "b11", NULL),
1028 _OMAP4_BALLENTRY(GPMC_NWE, "b12", NULL),
1029 _OMAP4_BALLENTRY(GPMC_NBE0_CLE, "c23", NULL),
1030 _OMAP4_BALLENTRY(GPMC_NBE1, "d22", NULL),
1031 _OMAP4_BALLENTRY(GPMC_WAIT0, "b26", NULL),
1032 _OMAP4_BALLENTRY(GPMC_WAIT1, "b23", NULL),
1033 _OMAP4_BALLENTRY(GPMC_WAIT2, "d23", NULL),
1034 _OMAP4_BALLENTRY(GPMC_NCS4, "a24", NULL),
1035 _OMAP4_BALLENTRY(GPMC_NCS5, "b24", NULL),
1036 _OMAP4_BALLENTRY(GPMC_NCS6, "c24", NULL),
1037 _OMAP4_BALLENTRY(GPMC_NCS7, "d24", NULL),
1038 _OMAP4_BALLENTRY(HDMI_HPD, "b9", NULL),
1039 _OMAP4_BALLENTRY(HDMI_CEC, "b10", NULL),
1040 _OMAP4_BALLENTRY(HDMI_DDC_SCL, "a8", NULL),
1041 _OMAP4_BALLENTRY(HDMI_DDC_SDA, "b8", NULL),
1042 _OMAP4_BALLENTRY(CSI21_DX0, "r26", NULL),
1043 _OMAP4_BALLENTRY(CSI21_DY0, "r25", NULL),
1044 _OMAP4_BALLENTRY(CSI21_DX1, "t26", NULL),
1045 _OMAP4_BALLENTRY(CSI21_DY1, "t25", NULL),
1046 _OMAP4_BALLENTRY(CSI21_DX2, "u26", NULL),
1047 _OMAP4_BALLENTRY(CSI21_DY2, "u25", NULL),
1048 _OMAP4_BALLENTRY(CSI21_DX3, "v26", NULL),
1049 _OMAP4_BALLENTRY(CSI21_DY3, "v25", NULL),
1050 _OMAP4_BALLENTRY(CSI21_DX4, "w26", NULL),
1051 _OMAP4_BALLENTRY(CSI21_DY4, "w25", NULL),
1052 _OMAP4_BALLENTRY(CSI22_DX0, "m26", NULL),
1053 _OMAP4_BALLENTRY(CSI22_DY0, "m25", NULL),
1054 _OMAP4_BALLENTRY(CSI22_DX1, "n26", NULL),
1055 _OMAP4_BALLENTRY(CSI22_DY1, "n25", NULL),
1056 _OMAP4_BALLENTRY(CAM_SHUTTER, "t27", NULL),
1057 _OMAP4_BALLENTRY(CAM_STROBE, "u27", NULL),
1058 _OMAP4_BALLENTRY(CAM_GLOBALRESET, "v27", NULL),
1059 _OMAP4_BALLENTRY(USBB1_ULPITLL_CLK, "ae18", NULL),
1060 _OMAP4_BALLENTRY(USBB1_ULPITLL_STP, "ag19", NULL),
1061 _OMAP4_BALLENTRY(USBB1_ULPITLL_DIR, "af19", NULL),
1062 _OMAP4_BALLENTRY(USBB1_ULPITLL_NXT, "ae19", NULL),
1063 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT0, "af18", NULL),
1064 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT1, "ag18", NULL),
1065 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT2, "ae17", NULL),
1066 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT3, "af17", NULL),
1067 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT4, "ah17", NULL),
1068 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT5, "ae16", NULL),
1069 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT6, "af16", NULL),
1070 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT7, "ag16", NULL),
1071 _OMAP4_BALLENTRY(USBB1_HSIC_DATA, "af14", NULL),
1072 _OMAP4_BALLENTRY(USBB1_HSIC_STROBE, "ae14", NULL),
1073 _OMAP4_BALLENTRY(USBC1_ICUSB_DP, "h2", NULL),
1074 _OMAP4_BALLENTRY(USBC1_ICUSB_DM, "h3", NULL),
1075 _OMAP4_BALLENTRY(SDMMC1_CLK, "d2", NULL),
1076 _OMAP4_BALLENTRY(SDMMC1_CMD, "e3", NULL),
1077 _OMAP4_BALLENTRY(SDMMC1_DAT0, "e4", NULL),
1078 _OMAP4_BALLENTRY(SDMMC1_DAT1, "e2", NULL),
1079 _OMAP4_BALLENTRY(SDMMC1_DAT2, "e1", NULL),
1080 _OMAP4_BALLENTRY(SDMMC1_DAT3, "f4", NULL),
1081 _OMAP4_BALLENTRY(SDMMC1_DAT4, "f3", NULL),
1082 _OMAP4_BALLENTRY(SDMMC1_DAT5, "f1", NULL),
1083 _OMAP4_BALLENTRY(SDMMC1_DAT6, "g4", NULL),
1084 _OMAP4_BALLENTRY(SDMMC1_DAT7, "g3", NULL),
1085 _OMAP4_BALLENTRY(ABE_MCBSP2_CLKX, "ad27", NULL),
1086 _OMAP4_BALLENTRY(ABE_MCBSP2_DR, "ad26", NULL),
1087 _OMAP4_BALLENTRY(ABE_MCBSP2_DX, "ad25", NULL),
1088 _OMAP4_BALLENTRY(ABE_MCBSP2_FSX, "ac28", NULL),
1089 _OMAP4_BALLENTRY(ABE_MCBSP1_CLKX, "ac26", NULL),
1090 _OMAP4_BALLENTRY(ABE_MCBSP1_DR, "ac25", NULL),
1091 _OMAP4_BALLENTRY(ABE_MCBSP1_DX, "ab25", NULL),
1092 _OMAP4_BALLENTRY(ABE_MCBSP1_FSX, "ac27", NULL),
1093 _OMAP4_BALLENTRY(ABE_PDM_UL_DATA, "ag25", NULL),
1094 _OMAP4_BALLENTRY(ABE_PDM_DL_DATA, "af25", NULL),
1095 _OMAP4_BALLENTRY(ABE_PDM_FRAME, "ae25", NULL),
1096 _OMAP4_BALLENTRY(ABE_PDM_LB_CLK, "af26", NULL),
1097 _OMAP4_BALLENTRY(ABE_CLKS, "ah26", NULL),
1098 _OMAP4_BALLENTRY(ABE_DMIC_CLK1, "ae24", NULL),
1099 _OMAP4_BALLENTRY(ABE_DMIC_DIN1, "af24", NULL),
1100 _OMAP4_BALLENTRY(ABE_DMIC_DIN2, "ag24", NULL),
1101 _OMAP4_BALLENTRY(ABE_DMIC_DIN3, "ah24", NULL),
1102 _OMAP4_BALLENTRY(UART2_CTS, "ab26", NULL),
1103 _OMAP4_BALLENTRY(UART2_RTS, "ab27", NULL),
1104 _OMAP4_BALLENTRY(UART2_RX, "aa25", NULL),
1105 _OMAP4_BALLENTRY(UART2_TX, "aa26", NULL),
1106 _OMAP4_BALLENTRY(HDQ_SIO, "aa27", NULL),
1107 _OMAP4_BALLENTRY(I2C1_SCL, "ae28", NULL),
1108 _OMAP4_BALLENTRY(I2C1_SDA, "ae26", NULL),
1109 _OMAP4_BALLENTRY(I2C2_SCL, "c26", NULL),
1110 _OMAP4_BALLENTRY(I2C2_SDA, "d26", NULL),
1111 _OMAP4_BALLENTRY(I2C3_SCL, "w27", NULL),
1112 _OMAP4_BALLENTRY(I2C3_SDA, "y27", NULL),
1113 _OMAP4_BALLENTRY(I2C4_SCL, "ag21", NULL),
1114 _OMAP4_BALLENTRY(I2C4_SDA, "ah22", NULL),
1115 _OMAP4_BALLENTRY(MCSPI1_CLK, "af22", NULL),
1116 _OMAP4_BALLENTRY(MCSPI1_SOMI, "ae22", NULL),
1117 _OMAP4_BALLENTRY(MCSPI1_SIMO, "ag22", NULL),
1118 _OMAP4_BALLENTRY(MCSPI1_CS0, "ae23", NULL),
1119 _OMAP4_BALLENTRY(MCSPI1_CS1, "af23", NULL),
1120 _OMAP4_BALLENTRY(MCSPI1_CS2, "ag23", NULL),
1121 _OMAP4_BALLENTRY(MCSPI1_CS3, "ah23", NULL),
1122 _OMAP4_BALLENTRY(UART3_CTS_RCTX, "f27", NULL),
1123 _OMAP4_BALLENTRY(UART3_RTS_SD, "f28", NULL),
1124 _OMAP4_BALLENTRY(UART3_RX_IRRX, "g27", NULL),
1125 _OMAP4_BALLENTRY(UART3_TX_IRTX, "g28", NULL),
1126 _OMAP4_BALLENTRY(SDMMC5_CLK, "ae5", NULL),
1127 _OMAP4_BALLENTRY(SDMMC5_CMD, "af5", NULL),
1128 _OMAP4_BALLENTRY(SDMMC5_DAT0, "ae4", NULL),
1129 _OMAP4_BALLENTRY(SDMMC5_DAT1, "af4", NULL),
1130 _OMAP4_BALLENTRY(SDMMC5_DAT2, "ag3", NULL),
1131 _OMAP4_BALLENTRY(SDMMC5_DAT3, "af3", NULL),
1132 _OMAP4_BALLENTRY(MCSPI4_CLK, "ae21", NULL),
1133 _OMAP4_BALLENTRY(MCSPI4_SIMO, "af20", NULL),
1134 _OMAP4_BALLENTRY(MCSPI4_SOMI, "af21", NULL),
1135 _OMAP4_BALLENTRY(MCSPI4_CS0, "ae20", NULL),
1136 _OMAP4_BALLENTRY(UART4_RX, "ag20", NULL),
1137 _OMAP4_BALLENTRY(UART4_TX, "ah19", NULL),
1138 _OMAP4_BALLENTRY(USBB2_ULPITLL_CLK, "ag12", NULL),
1139 _OMAP4_BALLENTRY(USBB2_ULPITLL_STP, "af12", NULL),
1140 _OMAP4_BALLENTRY(USBB2_ULPITLL_DIR, "ae12", NULL),
1141 _OMAP4_BALLENTRY(USBB2_ULPITLL_NXT, "ag13", NULL),
1142 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT0, "ae11", NULL),
1143 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT1, "af11", NULL),
1144 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT2, "ag11", NULL),
1145 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT3, "ah11", NULL),
1146 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT4, "ae10", NULL),
1147 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT5, "af10", NULL),
1148 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT6, "ag10", NULL),
1149 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT7, "ae9", NULL),
1150 _OMAP4_BALLENTRY(USBB2_HSIC_DATA, "af13", NULL),
1151 _OMAP4_BALLENTRY(USBB2_HSIC_STROBE, "ae13", NULL),
1152 _OMAP4_BALLENTRY(KPD_COL3, "g26", NULL),
1153 _OMAP4_BALLENTRY(KPD_COL4, "g25", NULL),
1154 _OMAP4_BALLENTRY(KPD_COL5, "h26", NULL),
1155 _OMAP4_BALLENTRY(KPD_COL0, "h25", NULL),
1156 _OMAP4_BALLENTRY(KPD_COL1, "j27", NULL),
1157 _OMAP4_BALLENTRY(KPD_COL2, "h27", NULL),
1158 _OMAP4_BALLENTRY(KPD_ROW3, "j26", NULL),
1159 _OMAP4_BALLENTRY(KPD_ROW4, "j25", NULL),
1160 _OMAP4_BALLENTRY(KPD_ROW5, "k26", NULL),
1161 _OMAP4_BALLENTRY(KPD_ROW0, "k25", NULL),
1162 _OMAP4_BALLENTRY(KPD_ROW1, "l27", NULL),
1163 _OMAP4_BALLENTRY(KPD_ROW2, "k27", NULL),
1164 _OMAP4_BALLENTRY(USBA0_OTG_CE, "c3", NULL),
1165 _OMAP4_BALLENTRY(USBA0_OTG_DP, "b5", NULL),
1166 _OMAP4_BALLENTRY(USBA0_OTG_DM, "b4", NULL),
1167 _OMAP4_BALLENTRY(FREF_CLK1_OUT, "aa28", NULL),
1168 _OMAP4_BALLENTRY(FREF_CLK2_OUT, "y28", NULL),
1169 _OMAP4_BALLENTRY(SYS_NIRQ1, "ae6", NULL),
1170 _OMAP4_BALLENTRY(SYS_NIRQ2, "af6", NULL),
1171 _OMAP4_BALLENTRY(SYS_BOOT0, "f26", NULL),
1172 _OMAP4_BALLENTRY(SYS_BOOT1, "e27", NULL),
1173 _OMAP4_BALLENTRY(SYS_BOOT2, "e26", NULL),
1174 _OMAP4_BALLENTRY(SYS_BOOT3, "e25", NULL),
1175 _OMAP4_BALLENTRY(SYS_BOOT4, "d28", NULL),
1176 _OMAP4_BALLENTRY(SYS_BOOT5, "d27", NULL),
1177 _OMAP4_BALLENTRY(DPM_EMU0, "m2", NULL),
1178 _OMAP4_BALLENTRY(DPM_EMU1, "n2", NULL),
1179 _OMAP4_BALLENTRY(DPM_EMU2, "p2", NULL),
1180 _OMAP4_BALLENTRY(DPM_EMU3, "v1", NULL),
1181 _OMAP4_BALLENTRY(DPM_EMU4, "v2", NULL),
1182 _OMAP4_BALLENTRY(DPM_EMU5, "w1", NULL),
1183 _OMAP4_BALLENTRY(DPM_EMU6, "w2", NULL),
1184 _OMAP4_BALLENTRY(DPM_EMU7, "w3", NULL),
1185 _OMAP4_BALLENTRY(DPM_EMU8, "w4", NULL),
1186 _OMAP4_BALLENTRY(DPM_EMU9, "y2", NULL),
1187 _OMAP4_BALLENTRY(DPM_EMU10, "y3", NULL),
1188 _OMAP4_BALLENTRY(DPM_EMU11, "y4", NULL),
1189 _OMAP4_BALLENTRY(DPM_EMU12, "aa1", NULL),
1190 _OMAP4_BALLENTRY(DPM_EMU13, "aa2", NULL),
1191 _OMAP4_BALLENTRY(DPM_EMU14, "aa3", NULL),
1192 _OMAP4_BALLENTRY(DPM_EMU15, "aa4", NULL),
1193 _OMAP4_BALLENTRY(DPM_EMU16, "ab2", NULL),
1194 _OMAP4_BALLENTRY(DPM_EMU17, "ab3", NULL),
1195 _OMAP4_BALLENTRY(DPM_EMU18, "ab4", NULL),
1196 _OMAP4_BALLENTRY(DPM_EMU19, "ac4", NULL),
1197 { .reg_offset = OMAP_MUX_TERMINATOR },
1198};
1199#else
1200#define omap4_core_cbs_ball NULL
1201#endif
1202
1203/*
1204 * Superset of all mux modes for omap4
1205 */
1206static struct omap_mux __initdata omap4_wkup_muxmodes[] = {
1207 _OMAP4_MUXENTRY(SIM_IO, 0, "sim_io", NULL, NULL, "gpio_wk0", NULL,
1208 NULL, NULL, "safe_mode"),
1209 _OMAP4_MUXENTRY(SIM_CLK, 1, "sim_clk", NULL, NULL, "gpio_wk1", NULL,
1210 NULL, NULL, "safe_mode"),
1211 _OMAP4_MUXENTRY(SIM_RESET, 2, "sim_reset", NULL, NULL, "gpio_wk2",
1212 NULL, NULL, NULL, "safe_mode"),
1213 _OMAP4_MUXENTRY(SIM_CD, 3, "sim_cd", NULL, NULL, "gpio_wk3", NULL,
1214 NULL, NULL, "safe_mode"),
1215 _OMAP4_MUXENTRY(SIM_PWRCTRL, 4, "sim_pwrctrl", NULL, NULL, "gpio_wk4",
1216 NULL, NULL, NULL, "safe_mode"),
1217 _OMAP4_MUXENTRY(SR_SCL, 0, "sr_scl", NULL, NULL, NULL, NULL, NULL,
1218 NULL, NULL),
1219 _OMAP4_MUXENTRY(SR_SDA, 0, "sr_sda", NULL, NULL, NULL, NULL, NULL,
1220 NULL, NULL),
1221 _OMAP4_MUXENTRY(FREF_XTAL_IN, 0, "fref_xtal_in", NULL, NULL, NULL,
1222 "c2c_wakereqin", NULL, NULL, NULL),
1223 _OMAP4_MUXENTRY(FREF_SLICER_IN, 0, "fref_slicer_in", NULL, NULL,
1224 "gpi_wk5", "c2c_wakereqin", NULL, NULL, "safe_mode"),
1225 _OMAP4_MUXENTRY(FREF_CLK_IOREQ, 0, "fref_clk_ioreq", NULL, NULL, NULL,
1226 NULL, NULL, NULL, NULL),
1227 _OMAP4_MUXENTRY(FREF_CLK0_OUT, 6, "fref_clk0_out", "fref_clk1_req",
1228 "sys_drm_msecure", "gpio_wk6", NULL, NULL, NULL,
1229 "safe_mode"),
1230 _OMAP4_MUXENTRY(FREF_CLK3_REQ, 30, "fref_clk3_req", "fref_clk1_req",
1231 "sys_drm_msecure", "gpio_wk30", "c2c_wakereqin", NULL,
1232 NULL, "safe_mode"),
1233 _OMAP4_MUXENTRY(FREF_CLK3_OUT, 31, "fref_clk3_out", "fref_clk2_req",
1234 "sys_secure_indicator", "gpio_wk31", "c2c_wakereqout",
1235 NULL, NULL, "safe_mode"),
1236 _OMAP4_MUXENTRY(FREF_CLK4_REQ, 7, "fref_clk4_req", "fref_clk5_out",
1237 NULL, "gpio_wk7", NULL, NULL, NULL, NULL),
1238 _OMAP4_MUXENTRY(FREF_CLK4_OUT, 8, "fref_clk4_out", NULL, NULL,
1239 "gpio_wk8", NULL, NULL, NULL, NULL),
1240 _OMAP4_MUXENTRY(SYS_32K, 0, "sys_32k", NULL, NULL, NULL, NULL, NULL,
1241 NULL, NULL),
1242 _OMAP4_MUXENTRY(SYS_NRESPWRON, 0, "sys_nrespwron", NULL, NULL, NULL,
1243 NULL, NULL, NULL, NULL),
1244 _OMAP4_MUXENTRY(SYS_NRESWARM, 0, "sys_nreswarm", NULL, NULL, NULL,
1245 NULL, NULL, NULL, NULL),
1246 _OMAP4_MUXENTRY(SYS_PWR_REQ, 0, "sys_pwr_req", NULL, NULL, NULL, NULL,
1247 NULL, NULL, NULL),
1248 _OMAP4_MUXENTRY(SYS_PWRON_RESET_OUT, 29, "sys_pwron_reset_out", NULL,
1249 NULL, "gpio_wk29", NULL, NULL, NULL, NULL),
1250 _OMAP4_MUXENTRY(SYS_BOOT6, 9, "sys_boot6", "dpm_emu18", NULL,
1251 "gpio_wk9", "c2c_wakereqout", NULL, NULL,
1252 "safe_mode"),
1253 _OMAP4_MUXENTRY(SYS_BOOT7, 10, "sys_boot7", "dpm_emu19", NULL,
1254 "gpio_wk10", NULL, NULL, NULL, "safe_mode"),
1255 _OMAP4_MUXENTRY(JTAG_NTRST, 0, "jtag_ntrst", NULL, NULL, NULL, NULL,
1256 NULL, NULL, NULL),
1257 _OMAP4_MUXENTRY(JTAG_TCK, 0, "jtag_tck", NULL, NULL, NULL, NULL, NULL,
1258 NULL, "safe_mode"),
1259 _OMAP4_MUXENTRY(JTAG_RTCK, 0, "jtag_rtck", NULL, NULL, NULL, NULL,
1260 NULL, NULL, NULL),
1261 _OMAP4_MUXENTRY(JTAG_TMS_TMSC, 0, "jtag_tms_tmsc", NULL, NULL, NULL,
1262 NULL, NULL, NULL, "safe_mode"),
1263 _OMAP4_MUXENTRY(JTAG_TDI, 0, "jtag_tdi", NULL, NULL, NULL, NULL, NULL,
1264 NULL, NULL),
1265 _OMAP4_MUXENTRY(JTAG_TDO, 0, "jtag_tdo", NULL, NULL, NULL, NULL, NULL,
1266 NULL, NULL),
1267 { .reg_offset = OMAP_MUX_TERMINATOR },
1268};
1269
1270/*
1271 * Balls for 44XX CBL & CBS package - wakeup partition
1272 * 547-pin CBL ES1.0 S-FPGA-N547, 0.40mm Ball Pitch (Top),
1273 * 0.40mm Ball Pitch (Bottom)
1274 */
1275#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
1276 && defined(CONFIG_OMAP_PACKAGE_CBL)
1277static struct omap_ball __initdata omap4_wkup_cbl_cbs_ball[] = {
1278 _OMAP4_BALLENTRY(SIM_IO, "h4", NULL),
1279 _OMAP4_BALLENTRY(SIM_CLK, "j2", NULL),
1280 _OMAP4_BALLENTRY(SIM_RESET, "g2", NULL),
1281 _OMAP4_BALLENTRY(SIM_CD, "j1", NULL),
1282 _OMAP4_BALLENTRY(SIM_PWRCTRL, "k1", NULL),
1283 _OMAP4_BALLENTRY(SR_SCL, "ag9", NULL),
1284 _OMAP4_BALLENTRY(SR_SDA, "af9", NULL),
1285 _OMAP4_BALLENTRY(FREF_XTAL_IN, "ah6", NULL),
1286 _OMAP4_BALLENTRY(FREF_SLICER_IN, "ag8", NULL),
1287 _OMAP4_BALLENTRY(FREF_CLK_IOREQ, "ad1", NULL),
1288 _OMAP4_BALLENTRY(FREF_CLK0_OUT, "ad2", NULL),
1289 _OMAP4_BALLENTRY(FREF_CLK3_REQ, "ad3", NULL),
1290 _OMAP4_BALLENTRY(FREF_CLK3_OUT, "ad4", NULL),
1291 _OMAP4_BALLENTRY(FREF_CLK4_REQ, "ac2", NULL),
1292 _OMAP4_BALLENTRY(FREF_CLK4_OUT, "ac3", NULL),
1293 _OMAP4_BALLENTRY(SYS_32K, "ag7", NULL),
1294 _OMAP4_BALLENTRY(SYS_NRESPWRON, "ae7", NULL),
1295 _OMAP4_BALLENTRY(SYS_NRESWARM, "af7", NULL),
1296 _OMAP4_BALLENTRY(SYS_PWR_REQ, "ah7", NULL),
1297 _OMAP4_BALLENTRY(SYS_PWRON_RESET_OUT, "ag6", NULL),
1298 _OMAP4_BALLENTRY(SYS_BOOT6, "af8", NULL),
1299 _OMAP4_BALLENTRY(SYS_BOOT7, "ae8", NULL),
1300 _OMAP4_BALLENTRY(JTAG_NTRST, "ah2", NULL),
1301 _OMAP4_BALLENTRY(JTAG_TCK, "ag1", NULL),
1302 _OMAP4_BALLENTRY(JTAG_RTCK, "ae3", NULL),
1303 _OMAP4_BALLENTRY(JTAG_TMS_TMSC, "ah1", NULL),
1304 _OMAP4_BALLENTRY(JTAG_TDI, "ae1", NULL),
1305 _OMAP4_BALLENTRY(JTAG_TDO, "ae2", NULL),
1306 { .reg_offset = OMAP_MUX_TERMINATOR },
1307};
1308#else
1309#define omap4_wkup_cbl_cbs_ball NULL
1310#endif
1311
1312int __init omap4_mux_init(struct omap_board_mux *board_subset,
1313 struct omap_board_mux *board_wkup_subset, int flags)
1314{
1315 struct omap_ball *package_balls_core;
1316 struct omap_ball *package_balls_wkup = omap4_wkup_cbl_cbs_ball;
1317 struct omap_mux *core_muxmodes;
1318 struct omap_mux *core_subset = NULL;
1319 int ret;
1320
1321 switch (flags & OMAP_PACKAGE_MASK) {
1322 case OMAP_PACKAGE_CBL:
1323 pr_debug("%s: OMAP4430 ES1.0 -> OMAP_PACKAGE_CBL\n", __func__);
1324 package_balls_core = omap4_core_cbl_ball;
1325 core_muxmodes = omap4_core_muxmodes;
1326 break;
1327 case OMAP_PACKAGE_CBS:
1328 pr_debug("%s: OMAP4430 ES2.X -> OMAP_PACKAGE_CBS\n", __func__);
1329 package_balls_core = omap4_core_cbs_ball;
1330 core_muxmodes = omap4_core_muxmodes;
1331 core_subset = omap4_es2_core_subset;
1332 break;
1333 default:
1334 pr_err("%s: Unknown omap package, mux disabled\n", __func__);
1335 return -EINVAL;
1336 }
1337
1338 ret = omap_mux_init("core",
1339 OMAP_MUX_GPIO_IN_MODE3,
1340 OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE,
1341 OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE,
1342 core_muxmodes, core_subset, board_subset,
1343 package_balls_core);
1344 if (ret)
1345 return ret;
1346
1347 ret = omap_mux_init("wkup",
1348 OMAP_MUX_GPIO_IN_MODE3,
1349 OMAP4_CTRL_MODULE_PAD_WKUP_MUX_PBASE,
1350 OMAP4_CTRL_MODULE_PAD_WKUP_MUX_SIZE,
1351 omap4_wkup_muxmodes, NULL, board_wkup_subset,
1352 package_balls_wkup);
1353
1354 return ret;
1355}
1356
diff --git a/arch/arm/mach-omap2/mux44xx.h b/arch/arm/mach-omap2/mux44xx.h
deleted file mode 100644
index c635026cd7e9..000000000000
--- a/arch/arm/mach-omap2/mux44xx.h
+++ /dev/null
@@ -1,298 +0,0 @@
1/*
2 * OMAP44xx MUX registers and bitfields
3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 *
6 * Benoit Cousson (b-cousson@ti.com)
7 *
8 * This file is automatically generated from the OMAP hardware databases.
9 * We respectfully ask that any modifications to this file be coordinated
10 * with the public linux-omap@vger.kernel.org mailing list and the
11 * authors above to ensure that the autogeneration scripts are kept
12 * up-to-date with the file contents.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#ifndef __ARCH_ARM_MACH_OMAP2_MUX_44XX_H
20#define __ARCH_ARM_MACH_OMAP2_MUX_44XX_H
21
22#define OMAP4_MUX(M0, mux_value) \
23{ \
24 .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \
25 .value = (mux_value), \
26}
27
28/* ctrl_module_pad_core base address */
29#define OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE 0x4a100000
30
31/* ctrl_module_pad_core registers offset */
32#define OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET 0x0040
33#define OMAP4_CTRL_MODULE_PAD_GPMC_AD1_OFFSET 0x0042
34#define OMAP4_CTRL_MODULE_PAD_GPMC_AD2_OFFSET 0x0044
35#define OMAP4_CTRL_MODULE_PAD_GPMC_AD3_OFFSET 0x0046
36#define OMAP4_CTRL_MODULE_PAD_GPMC_AD4_OFFSET 0x0048
37#define OMAP4_CTRL_MODULE_PAD_GPMC_AD5_OFFSET 0x004a
38#define OMAP4_CTRL_MODULE_PAD_GPMC_AD6_OFFSET 0x004c
39#define OMAP4_CTRL_MODULE_PAD_GPMC_AD7_OFFSET 0x004e
40#define OMAP4_CTRL_MODULE_PAD_GPMC_AD8_OFFSET 0x0050
41#define OMAP4_CTRL_MODULE_PAD_GPMC_AD9_OFFSET 0x0052
42#define OMAP4_CTRL_MODULE_PAD_GPMC_AD10_OFFSET 0x0054
43#define OMAP4_CTRL_MODULE_PAD_GPMC_AD11_OFFSET 0x0056
44#define OMAP4_CTRL_MODULE_PAD_GPMC_AD12_OFFSET 0x0058
45#define OMAP4_CTRL_MODULE_PAD_GPMC_AD13_OFFSET 0x005a
46#define OMAP4_CTRL_MODULE_PAD_GPMC_AD14_OFFSET 0x005c
47#define OMAP4_CTRL_MODULE_PAD_GPMC_AD15_OFFSET 0x005e
48#define OMAP4_CTRL_MODULE_PAD_GPMC_A16_OFFSET 0x0060
49#define OMAP4_CTRL_MODULE_PAD_GPMC_A17_OFFSET 0x0062
50#define OMAP4_CTRL_MODULE_PAD_GPMC_A18_OFFSET 0x0064
51#define OMAP4_CTRL_MODULE_PAD_GPMC_A19_OFFSET 0x0066
52#define OMAP4_CTRL_MODULE_PAD_GPMC_A20_OFFSET 0x0068
53#define OMAP4_CTRL_MODULE_PAD_GPMC_A21_OFFSET 0x006a
54#define OMAP4_CTRL_MODULE_PAD_GPMC_A22_OFFSET 0x006c
55#define OMAP4_CTRL_MODULE_PAD_GPMC_A23_OFFSET 0x006e
56#define OMAP4_CTRL_MODULE_PAD_GPMC_A24_OFFSET 0x0070
57#define OMAP4_CTRL_MODULE_PAD_GPMC_A25_OFFSET 0x0072
58#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS0_OFFSET 0x0074
59#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS1_OFFSET 0x0076
60#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS2_OFFSET 0x0078
61#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS3_OFFSET 0x007a
62#define OMAP4_CTRL_MODULE_PAD_GPMC_NWP_OFFSET 0x007c
63#define OMAP4_CTRL_MODULE_PAD_GPMC_CLK_OFFSET 0x007e
64#define OMAP4_CTRL_MODULE_PAD_GPMC_NADV_ALE_OFFSET 0x0080
65#define OMAP4_CTRL_MODULE_PAD_GPMC_NOE_OFFSET 0x0082
66#define OMAP4_CTRL_MODULE_PAD_GPMC_NWE_OFFSET 0x0084
67#define OMAP4_CTRL_MODULE_PAD_GPMC_NBE0_CLE_OFFSET 0x0086
68#define OMAP4_CTRL_MODULE_PAD_GPMC_NBE1_OFFSET 0x0088
69#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT0_OFFSET 0x008a
70#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT1_OFFSET 0x008c
71#define OMAP4_CTRL_MODULE_PAD_C2C_DATA11_OFFSET 0x008e
72#define OMAP4_CTRL_MODULE_PAD_C2C_DATA12_OFFSET 0x0090
73#define OMAP4_CTRL_MODULE_PAD_C2C_DATA13_OFFSET 0x0092
74#define OMAP4_CTRL_MODULE_PAD_C2C_DATA14_OFFSET 0x0094
75#define OMAP4_CTRL_MODULE_PAD_C2C_DATA15_OFFSET 0x0096
76#define OMAP4_CTRL_MODULE_PAD_HDMI_HPD_OFFSET 0x0098
77#define OMAP4_CTRL_MODULE_PAD_HDMI_CEC_OFFSET 0x009a
78#define OMAP4_CTRL_MODULE_PAD_HDMI_DDC_SCL_OFFSET 0x009c
79#define OMAP4_CTRL_MODULE_PAD_HDMI_DDC_SDA_OFFSET 0x009e
80#define OMAP4_CTRL_MODULE_PAD_CSI21_DX0_OFFSET 0x00a0
81#define OMAP4_CTRL_MODULE_PAD_CSI21_DY0_OFFSET 0x00a2
82#define OMAP4_CTRL_MODULE_PAD_CSI21_DX1_OFFSET 0x00a4
83#define OMAP4_CTRL_MODULE_PAD_CSI21_DY1_OFFSET 0x00a6
84#define OMAP4_CTRL_MODULE_PAD_CSI21_DX2_OFFSET 0x00a8
85#define OMAP4_CTRL_MODULE_PAD_CSI21_DY2_OFFSET 0x00aa
86#define OMAP4_CTRL_MODULE_PAD_CSI21_DX3_OFFSET 0x00ac
87#define OMAP4_CTRL_MODULE_PAD_CSI21_DY3_OFFSET 0x00ae
88#define OMAP4_CTRL_MODULE_PAD_CSI21_DX4_OFFSET 0x00b0
89#define OMAP4_CTRL_MODULE_PAD_CSI21_DY4_OFFSET 0x00b2
90#define OMAP4_CTRL_MODULE_PAD_CSI22_DX0_OFFSET 0x00b4
91#define OMAP4_CTRL_MODULE_PAD_CSI22_DY0_OFFSET 0x00b6
92#define OMAP4_CTRL_MODULE_PAD_CSI22_DX1_OFFSET 0x00b8
93#define OMAP4_CTRL_MODULE_PAD_CSI22_DY1_OFFSET 0x00ba
94#define OMAP4_CTRL_MODULE_PAD_CAM_SHUTTER_OFFSET 0x00bc
95#define OMAP4_CTRL_MODULE_PAD_CAM_STROBE_OFFSET 0x00be
96#define OMAP4_CTRL_MODULE_PAD_CAM_GLOBALRESET_OFFSET 0x00c0
97#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_CLK_OFFSET 0x00c2
98#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_STP_OFFSET 0x00c4
99#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DIR_OFFSET 0x00c6
100#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_NXT_OFFSET 0x00c8
101#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT0_OFFSET 0x00ca
102#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT1_OFFSET 0x00cc
103#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT2_OFFSET 0x00ce
104#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT3_OFFSET 0x00d0
105#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT4_OFFSET 0x00d2
106#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT5_OFFSET 0x00d4
107#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT6_OFFSET 0x00d6
108#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT7_OFFSET 0x00d8
109#define OMAP4_CTRL_MODULE_PAD_USBB1_HSIC_DATA_OFFSET 0x00da
110#define OMAP4_CTRL_MODULE_PAD_USBB1_HSIC_STROBE_OFFSET 0x00dc
111#define OMAP4_CTRL_MODULE_PAD_USBC1_ICUSB_DP_OFFSET 0x00de
112#define OMAP4_CTRL_MODULE_PAD_USBC1_ICUSB_DM_OFFSET 0x00e0
113#define OMAP4_CTRL_MODULE_PAD_SDMMC1_CLK_OFFSET 0x00e2
114#define OMAP4_CTRL_MODULE_PAD_SDMMC1_CMD_OFFSET 0x00e4
115#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT0_OFFSET 0x00e6
116#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT1_OFFSET 0x00e8
117#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT2_OFFSET 0x00ea
118#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT3_OFFSET 0x00ec
119#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT4_OFFSET 0x00ee
120#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT5_OFFSET 0x00f0
121#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT6_OFFSET 0x00f2
122#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT7_OFFSET 0x00f4
123#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_CLKX_OFFSET 0x00f6
124#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_DR_OFFSET 0x00f8
125#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_DX_OFFSET 0x00fa
126#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_FSX_OFFSET 0x00fc
127#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_CLKX_OFFSET 0x00fe
128#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_DR_OFFSET 0x0100
129#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_DX_OFFSET 0x0102
130#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_FSX_OFFSET 0x0104
131#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_UL_DATA_OFFSET 0x0106
132#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_DL_DATA_OFFSET 0x0108
133#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_FRAME_OFFSET 0x010a
134#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_LB_CLK_OFFSET 0x010c
135#define OMAP4_CTRL_MODULE_PAD_ABE_CLKS_OFFSET 0x010e
136#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_CLK1_OFFSET 0x0110
137#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN1_OFFSET 0x0112
138#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN2_OFFSET 0x0114
139#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN3_OFFSET 0x0116
140#define OMAP4_CTRL_MODULE_PAD_UART2_CTS_OFFSET 0x0118
141#define OMAP4_CTRL_MODULE_PAD_UART2_RTS_OFFSET 0x011a
142#define OMAP4_CTRL_MODULE_PAD_UART2_RX_OFFSET 0x011c
143#define OMAP4_CTRL_MODULE_PAD_UART2_TX_OFFSET 0x011e
144#define OMAP4_CTRL_MODULE_PAD_HDQ_SIO_OFFSET 0x0120
145#define OMAP4_CTRL_MODULE_PAD_I2C1_SCL_OFFSET 0x0122
146#define OMAP4_CTRL_MODULE_PAD_I2C1_SDA_OFFSET 0x0124
147#define OMAP4_CTRL_MODULE_PAD_I2C2_SCL_OFFSET 0x0126
148#define OMAP4_CTRL_MODULE_PAD_I2C2_SDA_OFFSET 0x0128
149#define OMAP4_CTRL_MODULE_PAD_I2C3_SCL_OFFSET 0x012a
150#define OMAP4_CTRL_MODULE_PAD_I2C3_SDA_OFFSET 0x012c
151#define OMAP4_CTRL_MODULE_PAD_I2C4_SCL_OFFSET 0x012e
152#define OMAP4_CTRL_MODULE_PAD_I2C4_SDA_OFFSET 0x0130
153#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CLK_OFFSET 0x0132
154#define OMAP4_CTRL_MODULE_PAD_MCSPI1_SOMI_OFFSET 0x0134
155#define OMAP4_CTRL_MODULE_PAD_MCSPI1_SIMO_OFFSET 0x0136
156#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS0_OFFSET 0x0138
157#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS1_OFFSET 0x013a
158#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS2_OFFSET 0x013c
159#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS3_OFFSET 0x013e
160#define OMAP4_CTRL_MODULE_PAD_UART3_CTS_RCTX_OFFSET 0x0140
161#define OMAP4_CTRL_MODULE_PAD_UART3_RTS_SD_OFFSET 0x0142
162#define OMAP4_CTRL_MODULE_PAD_UART3_RX_IRRX_OFFSET 0x0144
163#define OMAP4_CTRL_MODULE_PAD_UART3_TX_IRTX_OFFSET 0x0146
164#define OMAP4_CTRL_MODULE_PAD_SDMMC5_CLK_OFFSET 0x0148
165#define OMAP4_CTRL_MODULE_PAD_SDMMC5_CMD_OFFSET 0x014a
166#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT0_OFFSET 0x014c
167#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT1_OFFSET 0x014e
168#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT2_OFFSET 0x0150
169#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT3_OFFSET 0x0152
170#define OMAP4_CTRL_MODULE_PAD_MCSPI4_CLK_OFFSET 0x0154
171#define OMAP4_CTRL_MODULE_PAD_MCSPI4_SIMO_OFFSET 0x0156
172#define OMAP4_CTRL_MODULE_PAD_MCSPI4_SOMI_OFFSET 0x0158
173#define OMAP4_CTRL_MODULE_PAD_MCSPI4_CS0_OFFSET 0x015a
174#define OMAP4_CTRL_MODULE_PAD_UART4_RX_OFFSET 0x015c
175#define OMAP4_CTRL_MODULE_PAD_UART4_TX_OFFSET 0x015e
176#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_CLK_OFFSET 0x0160
177#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_STP_OFFSET 0x0162
178#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DIR_OFFSET 0x0164
179#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_NXT_OFFSET 0x0166
180#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT0_OFFSET 0x0168
181#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT1_OFFSET 0x016a
182#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT2_OFFSET 0x016c
183#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT3_OFFSET 0x016e
184#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT4_OFFSET 0x0170
185#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT5_OFFSET 0x0172
186#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT6_OFFSET 0x0174
187#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT7_OFFSET 0x0176
188#define OMAP4_CTRL_MODULE_PAD_USBB2_HSIC_DATA_OFFSET 0x0178
189#define OMAP4_CTRL_MODULE_PAD_USBB2_HSIC_STROBE_OFFSET 0x017a
190#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX0_OFFSET 0x017c
191#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY0_OFFSET 0x017e
192#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX1_OFFSET 0x0180
193#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY1_OFFSET 0x0182
194#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX2_OFFSET 0x0184
195#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY2_OFFSET 0x0186
196#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX0_OFFSET 0x0188
197#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY0_OFFSET 0x018a
198#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX1_OFFSET 0x018c
199#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY1_OFFSET 0x018e
200#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX2_OFFSET 0x0190
201#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY2_OFFSET 0x0192
202#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_CE_OFFSET 0x0194
203#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_DP_OFFSET 0x0196
204#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_DM_OFFSET 0x0198
205#define OMAP4_CTRL_MODULE_PAD_FREF_CLK1_OUT_OFFSET 0x019a
206#define OMAP4_CTRL_MODULE_PAD_FREF_CLK2_OUT_OFFSET 0x019c
207#define OMAP4_CTRL_MODULE_PAD_SYS_NIRQ1_OFFSET 0x019e
208#define OMAP4_CTRL_MODULE_PAD_SYS_NIRQ2_OFFSET 0x01a0
209#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT0_OFFSET 0x01a2
210#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT1_OFFSET 0x01a4
211#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT2_OFFSET 0x01a6
212#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT3_OFFSET 0x01a8
213#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT4_OFFSET 0x01aa
214#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT5_OFFSET 0x01ac
215#define OMAP4_CTRL_MODULE_PAD_DPM_EMU0_OFFSET 0x01ae
216#define OMAP4_CTRL_MODULE_PAD_DPM_EMU1_OFFSET 0x01b0
217#define OMAP4_CTRL_MODULE_PAD_DPM_EMU2_OFFSET 0x01b2
218#define OMAP4_CTRL_MODULE_PAD_DPM_EMU3_OFFSET 0x01b4
219#define OMAP4_CTRL_MODULE_PAD_DPM_EMU4_OFFSET 0x01b6
220#define OMAP4_CTRL_MODULE_PAD_DPM_EMU5_OFFSET 0x01b8
221#define OMAP4_CTRL_MODULE_PAD_DPM_EMU6_OFFSET 0x01ba
222#define OMAP4_CTRL_MODULE_PAD_DPM_EMU7_OFFSET 0x01bc
223#define OMAP4_CTRL_MODULE_PAD_DPM_EMU8_OFFSET 0x01be
224#define OMAP4_CTRL_MODULE_PAD_DPM_EMU9_OFFSET 0x01c0
225#define OMAP4_CTRL_MODULE_PAD_DPM_EMU10_OFFSET 0x01c2
226#define OMAP4_CTRL_MODULE_PAD_DPM_EMU11_OFFSET 0x01c4
227#define OMAP4_CTRL_MODULE_PAD_DPM_EMU12_OFFSET 0x01c6
228#define OMAP4_CTRL_MODULE_PAD_DPM_EMU13_OFFSET 0x01c8
229#define OMAP4_CTRL_MODULE_PAD_DPM_EMU14_OFFSET 0x01ca
230#define OMAP4_CTRL_MODULE_PAD_DPM_EMU15_OFFSET 0x01cc
231#define OMAP4_CTRL_MODULE_PAD_DPM_EMU16_OFFSET 0x01ce
232#define OMAP4_CTRL_MODULE_PAD_DPM_EMU17_OFFSET 0x01d0
233#define OMAP4_CTRL_MODULE_PAD_DPM_EMU18_OFFSET 0x01d2
234#define OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET 0x01d4
235
236/* ES2.0 only */
237#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT2_OFFSET 0x008e
238#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS4_OFFSET 0x0090
239#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS5_OFFSET 0x0092
240#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS6_OFFSET 0x0094
241#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS7_OFFSET 0x0096
242
243#define OMAP4_CTRL_MODULE_PAD_KPD_COL3_OFFSET 0x017c
244#define OMAP4_CTRL_MODULE_PAD_KPD_COL4_OFFSET 0x017e
245#define OMAP4_CTRL_MODULE_PAD_KPD_COL5_OFFSET 0x0180
246#define OMAP4_CTRL_MODULE_PAD_KPD_COL0_OFFSET 0x0182
247#define OMAP4_CTRL_MODULE_PAD_KPD_COL1_OFFSET 0x0184
248#define OMAP4_CTRL_MODULE_PAD_KPD_COL2_OFFSET 0x0186
249#define OMAP4_CTRL_MODULE_PAD_KPD_ROW3_OFFSET 0x0188
250#define OMAP4_CTRL_MODULE_PAD_KPD_ROW4_OFFSET 0x018a
251#define OMAP4_CTRL_MODULE_PAD_KPD_ROW5_OFFSET 0x018c
252#define OMAP4_CTRL_MODULE_PAD_KPD_ROW0_OFFSET 0x018e
253#define OMAP4_CTRL_MODULE_PAD_KPD_ROW1_OFFSET 0x0190
254#define OMAP4_CTRL_MODULE_PAD_KPD_ROW2_OFFSET 0x0192
255
256
257#define OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE \
258 (OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET \
259 - OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET + 2)
260
261/* ctrl_module_pad_wkup base address */
262#define OMAP4_CTRL_MODULE_PAD_WKUP_MUX_PBASE 0x4a31e000
263
264/* ctrl_module_pad_wkup registers offset */
265#define OMAP4_CTRL_MODULE_PAD_SIM_IO_OFFSET 0x0040
266#define OMAP4_CTRL_MODULE_PAD_SIM_CLK_OFFSET 0x0042
267#define OMAP4_CTRL_MODULE_PAD_SIM_RESET_OFFSET 0x0044
268#define OMAP4_CTRL_MODULE_PAD_SIM_CD_OFFSET 0x0046
269#define OMAP4_CTRL_MODULE_PAD_SIM_PWRCTRL_OFFSET 0x0048
270#define OMAP4_CTRL_MODULE_PAD_SR_SCL_OFFSET 0x004a
271#define OMAP4_CTRL_MODULE_PAD_SR_SDA_OFFSET 0x004c
272#define OMAP4_CTRL_MODULE_PAD_FREF_XTAL_IN_OFFSET 0x004e
273#define OMAP4_CTRL_MODULE_PAD_FREF_SLICER_IN_OFFSET 0x0050
274#define OMAP4_CTRL_MODULE_PAD_FREF_CLK_IOREQ_OFFSET 0x0052
275#define OMAP4_CTRL_MODULE_PAD_FREF_CLK0_OUT_OFFSET 0x0054
276#define OMAP4_CTRL_MODULE_PAD_FREF_CLK3_REQ_OFFSET 0x0056
277#define OMAP4_CTRL_MODULE_PAD_FREF_CLK3_OUT_OFFSET 0x0058
278#define OMAP4_CTRL_MODULE_PAD_FREF_CLK4_REQ_OFFSET 0x005a
279#define OMAP4_CTRL_MODULE_PAD_FREF_CLK4_OUT_OFFSET 0x005c
280#define OMAP4_CTRL_MODULE_PAD_SYS_32K_OFFSET 0x005e
281#define OMAP4_CTRL_MODULE_PAD_SYS_NRESPWRON_OFFSET 0x0060
282#define OMAP4_CTRL_MODULE_PAD_SYS_NRESWARM_OFFSET 0x0062
283#define OMAP4_CTRL_MODULE_PAD_SYS_PWR_REQ_OFFSET 0x0064
284#define OMAP4_CTRL_MODULE_PAD_SYS_PWRON_RESET_OUT_OFFSET 0x0066
285#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT6_OFFSET 0x0068
286#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT7_OFFSET 0x006a
287#define OMAP4_CTRL_MODULE_PAD_JTAG_NTRST_OFFSET 0x006c
288#define OMAP4_CTRL_MODULE_PAD_JTAG_TCK_OFFSET 0x006e
289#define OMAP4_CTRL_MODULE_PAD_JTAG_RTCK_OFFSET 0x0070
290#define OMAP4_CTRL_MODULE_PAD_JTAG_TMS_TMSC_OFFSET 0x0072
291#define OMAP4_CTRL_MODULE_PAD_JTAG_TDI_OFFSET 0x0074
292#define OMAP4_CTRL_MODULE_PAD_JTAG_TDO_OFFSET 0x0076
293
294#define OMAP4_CTRL_MODULE_PAD_WKUP_MUX_SIZE \
295 (OMAP4_CTRL_MODULE_PAD_JTAG_TDO_OFFSET \
296 - OMAP4_CTRL_MODULE_PAD_SIM_IO_OFFSET + 2)
297
298#endif
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index 0ea09faf327b..75e92952c18e 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -20,8 +20,6 @@
20 20
21#include "omap44xx.h" 21#include "omap44xx.h"
22 22
23 __CPUINIT
24
25/* Physical address needed since MMU not enabled yet on secondary core */ 23/* Physical address needed since MMU not enabled yet on secondary core */
26#define AUX_CORE_BOOT0_PA 0x48281800 24#define AUX_CORE_BOOT0_PA 0x48281800
27 25
@@ -49,7 +47,7 @@ END(omap5_secondary_startup)
49 * The primary core will update this flag using a hardware 47 * The primary core will update this flag using a hardware
50 * register AuxCoreBoot0. 48 * register AuxCoreBoot0.
51 */ 49 */
52ENTRY(omap_secondary_startup) 50ENTRY(omap4_secondary_startup)
53hold: ldr r12,=0x103 51hold: ldr r12,=0x103
54 dsb 52 dsb
55 smc #0 @ read from AuxCoreBoot0 53 smc #0 @ read from AuxCoreBoot0
@@ -64,9 +62,9 @@ hold: ldr r12,=0x103
64 * should now contain the SVC stack for this core 62 * should now contain the SVC stack for this core
65 */ 63 */
66 b secondary_startup 64 b secondary_startup
67ENDPROC(omap_secondary_startup) 65ENDPROC(omap4_secondary_startup)
68 66
69ENTRY(omap_secondary_startup_4460) 67ENTRY(omap4460_secondary_startup)
70hold_2: ldr r12,=0x103 68hold_2: ldr r12,=0x103
71 dsb 69 dsb
72 smc #0 @ read from AuxCoreBoot0 70 smc #0 @ read from AuxCoreBoot0
@@ -101,4 +99,4 @@ hold_2: ldr r12,=0x103
101 * should now contain the SVC stack for this core 99 * should now contain the SVC stack for this core
102 */ 100 */
103 b secondary_startup 101 b secondary_startup
104ENDPROC(omap_secondary_startup_4460) 102ENDPROC(omap4460_secondary_startup)
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index e80327b6c81f..f991016e2a6a 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -71,10 +71,43 @@ struct omap4_cpu_pm_info {
71 void (*secondary_startup)(void); 71 void (*secondary_startup)(void);
72}; 72};
73 73
74/**
75 * struct cpu_pm_ops - CPU pm operations
76 * @finish_suspend: CPU suspend finisher function pointer
77 * @resume: CPU resume function pointer
78 * @scu_prepare: CPU Snoop Control program function pointer
79 *
80 * Structure holds functions pointer for CPU low power operations like
81 * suspend, resume and scu programming.
82 */
83struct cpu_pm_ops {
84 int (*finish_suspend)(unsigned long cpu_state);
85 void (*resume)(void);
86 void (*scu_prepare)(unsigned int cpu_id, unsigned int cpu_state);
87};
88
74static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info); 89static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
75static struct powerdomain *mpuss_pd; 90static struct powerdomain *mpuss_pd;
76static void __iomem *sar_base; 91static void __iomem *sar_base;
77 92
93static int default_finish_suspend(unsigned long cpu_state)
94{
95 omap_do_wfi();
96 return 0;
97}
98
99static void dummy_cpu_resume(void)
100{}
101
102static void dummy_scu_prepare(unsigned int cpu_id, unsigned int cpu_state)
103{}
104
105struct cpu_pm_ops omap_pm_ops = {
106 .finish_suspend = default_finish_suspend,
107 .resume = dummy_cpu_resume,
108 .scu_prepare = dummy_scu_prepare,
109};
110
78/* 111/*
79 * Program the wakeup routine address for the CPU0 and CPU1 112 * Program the wakeup routine address for the CPU0 and CPU1
80 * used for OFF or DORMANT wakeup. 113 * used for OFF or DORMANT wakeup.
@@ -158,11 +191,12 @@ static void save_l2x0_context(void)
158{ 191{
159 u32 val; 192 u32 val;
160 void __iomem *l2x0_base = omap4_get_l2cache_base(); 193 void __iomem *l2x0_base = omap4_get_l2cache_base();
161 194 if (l2x0_base) {
162 val = __raw_readl(l2x0_base + L2X0_AUX_CTRL); 195 val = __raw_readl(l2x0_base + L2X0_AUX_CTRL);
163 __raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET); 196 __raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET);
164 val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL); 197 val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL);
165 __raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET); 198 __raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET);
199 }
166} 200}
167#else 201#else
168static void save_l2x0_context(void) 202static void save_l2x0_context(void)
@@ -225,14 +259,17 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
225 259
226 cpu_clear_prev_logic_pwrst(cpu); 260 cpu_clear_prev_logic_pwrst(cpu);
227 pwrdm_set_next_pwrst(pm_info->pwrdm, power_state); 261 pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
228 set_cpu_wakeup_addr(cpu, virt_to_phys(omap4_cpu_resume)); 262 set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.resume));
229 scu_pwrst_prepare(cpu, power_state); 263 omap_pm_ops.scu_prepare(cpu, power_state);
230 l2x0_pwrst_prepare(cpu, save_state); 264 l2x0_pwrst_prepare(cpu, save_state);
231 265
232 /* 266 /*
233 * Call low level function with targeted low power state. 267 * Call low level function with targeted low power state.
234 */ 268 */
235 cpu_suspend(save_state, omap4_finish_suspend); 269 if (save_state)
270 cpu_suspend(save_state, omap_pm_ops.finish_suspend);
271 else
272 omap_pm_ops.finish_suspend(save_state);
236 273
237 /* 274 /*
238 * Restore the CPUx power state to ON otherwise CPUx 275 * Restore the CPUx power state to ON otherwise CPUx
@@ -254,7 +291,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
254 * @cpu : CPU ID 291 * @cpu : CPU ID
255 * @power_state: CPU low power state. 292 * @power_state: CPU low power state.
256 */ 293 */
257int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state) 294int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
258{ 295{
259 struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu); 296 struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
260 unsigned int cpu_state = 0; 297 unsigned int cpu_state = 0;
@@ -268,14 +305,14 @@ int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
268 pwrdm_clear_all_prev_pwrst(pm_info->pwrdm); 305 pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
269 pwrdm_set_next_pwrst(pm_info->pwrdm, power_state); 306 pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
270 set_cpu_wakeup_addr(cpu, virt_to_phys(pm_info->secondary_startup)); 307 set_cpu_wakeup_addr(cpu, virt_to_phys(pm_info->secondary_startup));
271 scu_pwrst_prepare(cpu, power_state); 308 omap_pm_ops.scu_prepare(cpu, power_state);
272 309
273 /* 310 /*
274 * CPU never retuns back if targeted power state is OFF mode. 311 * CPU never retuns back if targeted power state is OFF mode.
275 * CPU ONLINE follows normal CPU ONLINE ptah via 312 * CPU ONLINE follows normal CPU ONLINE ptah via
276 * omap_secondary_startup(). 313 * omap4_secondary_startup().
277 */ 314 */
278 omap4_finish_suspend(cpu_state); 315 omap_pm_ops.finish_suspend(cpu_state);
279 316
280 pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON); 317 pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
281 return 0; 318 return 0;
@@ -319,9 +356,9 @@ int __init omap4_mpuss_init(void)
319 pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET; 356 pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
320 pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1; 357 pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
321 if (cpu_is_omap446x()) 358 if (cpu_is_omap446x())
322 pm_info->secondary_startup = omap_secondary_startup_4460; 359 pm_info->secondary_startup = omap4460_secondary_startup;
323 else 360 else
324 pm_info->secondary_startup = omap_secondary_startup; 361 pm_info->secondary_startup = omap4_secondary_startup;
325 362
326 pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm"); 363 pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
327 if (!pm_info->pwrdm) { 364 if (!pm_info->pwrdm) {
@@ -352,6 +389,12 @@ int __init omap4_mpuss_init(void)
352 389
353 save_l2x0_context(); 390 save_l2x0_context();
354 391
392 if (cpu_is_omap44xx()) {
393 omap_pm_ops.finish_suspend = omap4_finish_suspend;
394 omap_pm_ops.resume = omap4_cpu_resume;
395 omap_pm_ops.scu_prepare = scu_pwrst_prepare;
396 }
397
355 return 0; 398 return 0;
356} 399}
357 400
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 2a551f997aea..8708b2a9da45 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -51,7 +51,7 @@ void __iomem *omap4_get_scu_base(void)
51 return scu_base; 51 return scu_base;
52} 52}
53 53
54static void __cpuinit omap4_secondary_init(unsigned int cpu) 54static void omap4_secondary_init(unsigned int cpu)
55{ 55{
56 /* 56 /*
57 * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device. 57 * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
@@ -72,7 +72,7 @@ static void __cpuinit omap4_secondary_init(unsigned int cpu)
72 spin_unlock(&boot_lock); 72 spin_unlock(&boot_lock);
73} 73}
74 74
75static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *idle) 75static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
76{ 76{
77 static struct clockdomain *cpu1_clkdm; 77 static struct clockdomain *cpu1_clkdm;
78 static bool booted; 78 static bool booted;
@@ -87,7 +87,7 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
87 87
88 /* 88 /*
89 * Update the AuxCoreBoot0 with boot state for secondary core. 89 * Update the AuxCoreBoot0 with boot state for secondary core.
90 * omap_secondary_startup() routine will hold the secondary core till 90 * omap4_secondary_startup() routine will hold the secondary core till
91 * the AuxCoreBoot1 register is updated with cpu state 91 * the AuxCoreBoot1 register is updated with cpu state
92 * A barrier is added to ensure that write buffer is drained 92 * A barrier is added to ensure that write buffer is drained
93 */ 93 */
@@ -200,7 +200,7 @@ static void __init omap4_smp_init_cpus(void)
200 200
201static void __init omap4_smp_prepare_cpus(unsigned int max_cpus) 201static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
202{ 202{
203 void *startup_addr = omap_secondary_startup; 203 void *startup_addr = omap4_secondary_startup;
204 void __iomem *base = omap_get_wakeupgen_base(); 204 void __iomem *base = omap_get_wakeupgen_base();
205 205
206 /* 206 /*
@@ -211,7 +211,7 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
211 scu_enable(scu_base); 211 scu_enable(scu_base);
212 212
213 if (cpu_is_omap446x()) { 213 if (cpu_is_omap446x()) {
214 startup_addr = omap_secondary_startup_4460; 214 startup_addr = omap4460_secondary_startup;
215 pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD; 215 pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
216 } 216 }
217 217
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index f8bb3b9b6a76..813c61558a5f 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -323,8 +323,8 @@ static void irq_save_secure_context(void)
323#endif 323#endif
324 324
325#ifdef CONFIG_HOTPLUG_CPU 325#ifdef CONFIG_HOTPLUG_CPU
326static int __cpuinit irq_cpu_hotplug_notify(struct notifier_block *self, 326static int irq_cpu_hotplug_notify(struct notifier_block *self,
327 unsigned long action, void *hcpu) 327 unsigned long action, void *hcpu)
328{ 328{
329 unsigned int cpu = (unsigned int)hcpu; 329 unsigned int cpu = (unsigned int)hcpu;
330 330
diff --git a/arch/arm/mach-omap2/omap2-restart.c b/arch/arm/mach-omap2/omap2-restart.c
index 719b716a4494..68423e26399d 100644
--- a/arch/arm/mach-omap2/omap2-restart.c
+++ b/arch/arm/mach-omap2/omap2-restart.c
@@ -31,7 +31,7 @@ static struct clk *reset_virt_prcm_set_ck, *reset_sys_ck;
31 * Set the DPLL to bypass so that reboot completes successfully. No 31 * Set the DPLL to bypass so that reboot completes successfully. No
32 * return value. 32 * return value.
33 */ 33 */
34void omap2xxx_restart(char mode, const char *cmd) 34void omap2xxx_restart(enum reboot_mode mode, const char *cmd)
35{ 35{
36 u32 rate; 36 u32 rate;
37 37
diff --git a/arch/arm/mach-omap2/omap3-restart.c b/arch/arm/mach-omap2/omap3-restart.c
index 923c582189e5..5de2a0c2979d 100644
--- a/arch/arm/mach-omap2/omap3-restart.c
+++ b/arch/arm/mach-omap2/omap3-restart.c
@@ -12,6 +12,7 @@
12 */ 12 */
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/reboot.h>
15 16
16#include "iomap.h" 17#include "iomap.h"
17#include "common.h" 18#include "common.h"
@@ -28,7 +29,7 @@
28 * Resets the SoC. For @cmd, see the 'reboot' syscall in 29 * Resets the SoC. For @cmd, see the 'reboot' syscall in
29 * kernel/sys.c. No return value. 30 * kernel/sys.c. No return value.
30 */ 31 */
31void omap3xxx_restart(char mode, const char *cmd) 32void omap3xxx_restart(enum reboot_mode mode, const char *cmd)
32{ 33{
33 omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0)); 34 omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
34 omap3xxx_prm_dpll3_reset(); /* never returns */ 35 omap3xxx_prm_dpll3_reset(); /* never returns */
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 13b27ffaf45e..57911430324e 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -23,6 +23,7 @@
23#include <linux/export.h> 23#include <linux/export.h>
24#include <linux/irqchip/arm-gic.h> 24#include <linux/irqchip/arm-gic.h>
25#include <linux/of_address.h> 25#include <linux/of_address.h>
26#include <linux/reboot.h>
26 27
27#include <asm/hardware/cache-l2x0.h> 28#include <asm/hardware/cache-l2x0.h>
28#include <asm/mach/map.h> 29#include <asm/mach/map.h>
@@ -339,19 +340,3 @@ int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
339 return 0; 340 return 0;
340} 341}
341#endif 342#endif
342
343/**
344 * omap44xx_restart - trigger a software restart of the SoC
345 * @mode: the "reboot mode", see arch/arm/kernel/{setup,process}.c
346 * @cmd: passed from the userspace program rebooting the system (if provided)
347 *
348 * Resets the SoC. For @cmd, see the 'reboot' syscall in
349 * kernel/sys.c. No return value.
350 */
351void omap44xx_restart(char mode, const char *cmd)
352{
353 /* XXX Should save 'cmd' into scratchpad for use after reboot */
354 omap4_prminst_global_warm_sw_reset(); /* never returns */
355 while (1);
356}
357
diff --git a/arch/arm/mach-omap2/omap4-restart.c b/arch/arm/mach-omap2/omap4-restart.c
new file mode 100644
index 000000000000..41dfd7da8170
--- /dev/null
+++ b/arch/arm/mach-omap2/omap4-restart.c
@@ -0,0 +1,28 @@
1/*
2 * omap4-restart.c - Common to OMAP4 and OMAP5
3 *
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/types.h>
11#include <linux/reboot.h>
12#include "prminst44xx.h"
13
14/**
15 * omap44xx_restart - trigger a software restart of the SoC
16 * @mode: the "reboot mode", see arch/arm/kernel/{setup,process}.c
17 * @cmd: passed from the userspace program rebooting the system (if provided)
18 *
19 * Resets the SoC. For @cmd, see the 'reboot' syscall in
20 * kernel/sys.c. No return value.
21 */
22void omap44xx_restart(enum reboot_mode mode, const char *cmd)
23{
24 /* XXX Should save 'cmd' into scratchpad for use after reboot */
25 omap4_prminst_global_warm_sw_reset(); /* never returns */
26 while (1)
27 ;
28}
diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c
index e6d230700b2b..f99f68e1e85b 100644
--- a/arch/arm/mach-omap2/omap_device.c
+++ b/arch/arm/mach-omap2/omap_device.c
@@ -129,6 +129,7 @@ static int omap_device_build_from_dt(struct platform_device *pdev)
129 struct device_node *node = pdev->dev.of_node; 129 struct device_node *node = pdev->dev.of_node;
130 const char *oh_name; 130 const char *oh_name;
131 int oh_cnt, i, ret = 0; 131 int oh_cnt, i, ret = 0;
132 bool device_active = false;
132 133
133 oh_cnt = of_property_count_strings(node, "ti,hwmods"); 134 oh_cnt = of_property_count_strings(node, "ti,hwmods");
134 if (oh_cnt <= 0) { 135 if (oh_cnt <= 0) {
@@ -152,6 +153,8 @@ static int omap_device_build_from_dt(struct platform_device *pdev)
152 goto odbfd_exit1; 153 goto odbfd_exit1;
153 } 154 }
154 hwmods[i] = oh; 155 hwmods[i] = oh;
156 if (oh->flags & HWMOD_INIT_NO_IDLE)
157 device_active = true;
155 } 158 }
156 159
157 od = omap_device_alloc(pdev, hwmods, oh_cnt); 160 od = omap_device_alloc(pdev, hwmods, oh_cnt);
@@ -170,11 +173,13 @@ static int omap_device_build_from_dt(struct platform_device *pdev)
170 r->name = dev_name(&pdev->dev); 173 r->name = dev_name(&pdev->dev);
171 } 174 }
172 175
173 if (of_get_property(node, "ti,no_idle_on_suspend", NULL))
174 omap_device_disable_idle_on_suspend(pdev);
175
176 pdev->dev.pm_domain = &omap_device_pm_domain; 176 pdev->dev.pm_domain = &omap_device_pm_domain;
177 177
178 if (device_active) {
179 omap_device_enable(pdev);
180 pm_runtime_set_active(&pdev->dev);
181 }
182
178odbfd_exit1: 183odbfd_exit1:
179 kfree(hwmods); 184 kfree(hwmods);
180odbfd_exit: 185odbfd_exit:
@@ -591,11 +596,6 @@ static int _od_runtime_suspend(struct device *dev)
591 return ret; 596 return ret;
592} 597}
593 598
594static int _od_runtime_idle(struct device *dev)
595{
596 return pm_generic_runtime_idle(dev);
597}
598
599static int _od_runtime_resume(struct device *dev) 599static int _od_runtime_resume(struct device *dev)
600{ 600{
601 struct platform_device *pdev = to_platform_device(dev); 601 struct platform_device *pdev = to_platform_device(dev);
@@ -621,8 +621,7 @@ static int _od_suspend_noirq(struct device *dev)
621 621
622 if (!ret && !pm_runtime_status_suspended(dev)) { 622 if (!ret && !pm_runtime_status_suspended(dev)) {
623 if (pm_generic_runtime_suspend(dev) == 0) { 623 if (pm_generic_runtime_suspend(dev) == 0) {
624 if (!(od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND)) 624 omap_device_idle(pdev);
625 omap_device_idle(pdev);
626 od->flags |= OMAP_DEVICE_SUSPENDED; 625 od->flags |= OMAP_DEVICE_SUSPENDED;
627 } 626 }
628 } 627 }
@@ -638,8 +637,7 @@ static int _od_resume_noirq(struct device *dev)
638 if ((od->flags & OMAP_DEVICE_SUSPENDED) && 637 if ((od->flags & OMAP_DEVICE_SUSPENDED) &&
639 !pm_runtime_status_suspended(dev)) { 638 !pm_runtime_status_suspended(dev)) {
640 od->flags &= ~OMAP_DEVICE_SUSPENDED; 639 od->flags &= ~OMAP_DEVICE_SUSPENDED;
641 if (!(od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND)) 640 omap_device_enable(pdev);
642 omap_device_enable(pdev);
643 pm_generic_runtime_resume(dev); 641 pm_generic_runtime_resume(dev);
644 } 642 }
645 643
@@ -653,7 +651,7 @@ static int _od_resume_noirq(struct device *dev)
653struct dev_pm_domain omap_device_pm_domain = { 651struct dev_pm_domain omap_device_pm_domain = {
654 .ops = { 652 .ops = {
655 SET_RUNTIME_PM_OPS(_od_runtime_suspend, _od_runtime_resume, 653 SET_RUNTIME_PM_OPS(_od_runtime_suspend, _od_runtime_resume,
656 _od_runtime_idle) 654 NULL)
657 USE_PLATFORM_PM_SLEEP_OPS 655 USE_PLATFORM_PM_SLEEP_OPS
658 .suspend_noirq = _od_suspend_noirq, 656 .suspend_noirq = _od_suspend_noirq,
659 .resume_noirq = _od_resume_noirq, 657 .resume_noirq = _od_resume_noirq,
@@ -852,6 +850,7 @@ static int __init omap_device_late_idle(struct device *dev, void *data)
852{ 850{
853 struct platform_device *pdev = to_platform_device(dev); 851 struct platform_device *pdev = to_platform_device(dev);
854 struct omap_device *od = to_omap_device(pdev); 852 struct omap_device *od = to_omap_device(pdev);
853 int i;
855 854
856 if (!od) 855 if (!od)
857 return 0; 856 return 0;
@@ -860,6 +859,15 @@ static int __init omap_device_late_idle(struct device *dev, void *data)
860 * If omap_device state is enabled, but has no driver bound, 859 * If omap_device state is enabled, but has no driver bound,
861 * idle it. 860 * idle it.
862 */ 861 */
862
863 /*
864 * Some devices (like memory controllers) are always kept
865 * enabled, and should not be idled even with no drivers.
866 */
867 for (i = 0; i < od->hwmods_cnt; i++)
868 if (od->hwmods[i]->flags & HWMOD_INIT_NO_IDLE)
869 return 0;
870
863 if (od->_driver_status != BUS_NOTIFY_BOUND_DRIVER) { 871 if (od->_driver_status != BUS_NOTIFY_BOUND_DRIVER) {
864 if (od->_state == OMAP_DEVICE_STATE_ENABLED) { 872 if (od->_state == OMAP_DEVICE_STATE_ENABLED) {
865 dev_warn(dev, "%s: enabled but no driver. Idling\n", 873 dev_warn(dev, "%s: enabled but no driver. Idling\n",
diff --git a/arch/arm/mach-omap2/omap_device.h b/arch/arm/mach-omap2/omap_device.h
index 044c31d50e5b..17ca1aec2710 100644
--- a/arch/arm/mach-omap2/omap_device.h
+++ b/arch/arm/mach-omap2/omap_device.h
@@ -38,7 +38,6 @@ extern struct dev_pm_domain omap_device_pm_domain;
38 38
39/* omap_device.flags values */ 39/* omap_device.flags values */
40#define OMAP_DEVICE_SUSPENDED BIT(0) 40#define OMAP_DEVICE_SUSPENDED BIT(0)
41#define OMAP_DEVICE_NO_IDLE_ON_SUSPEND BIT(1)
42 41
43/** 42/**
44 * struct omap_device - omap_device wrapper for platform_devices 43 * struct omap_device - omap_device wrapper for platform_devices
@@ -101,13 +100,4 @@ static inline struct omap_device *to_omap_device(struct platform_device *pdev)
101{ 100{
102 return pdev ? pdev->archdata.od : NULL; 101 return pdev ? pdev->archdata.od : NULL;
103} 102}
104
105static inline
106void omap_device_disable_idle_on_suspend(struct platform_device *pdev)
107{
108 struct omap_device *od = to_omap_device(pdev);
109
110 od->flags |= OMAP_DEVICE_NO_IDLE_ON_SUSPEND;
111}
112
113#endif 103#endif
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 7341eff63f56..7f4db12b1459 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -2386,7 +2386,7 @@ static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data)
2386 2386
2387 np = of_dev_hwmod_lookup(of_find_node_by_name(NULL, "ocp"), oh); 2387 np = of_dev_hwmod_lookup(of_find_node_by_name(NULL, "ocp"), oh);
2388 if (np) 2388 if (np)
2389 va_start = of_iomap(np, 0); 2389 va_start = of_iomap(np, oh->mpu_rt_idx);
2390 } else { 2390 } else {
2391 va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start); 2391 va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
2392 } 2392 }
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index 0c898f58ac9b..e1482a9b3bc2 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -95,6 +95,54 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3;
95#define MODULEMODE_HWCTRL 1 95#define MODULEMODE_HWCTRL 1
96#define MODULEMODE_SWCTRL 2 96#define MODULEMODE_SWCTRL 2
97 97
98#define DEBUG_OMAP2UART1_FLAGS 0
99#define DEBUG_OMAP2UART2_FLAGS 0
100#define DEBUG_OMAP2UART3_FLAGS 0
101#define DEBUG_OMAP3UART3_FLAGS 0
102#define DEBUG_OMAP3UART4_FLAGS 0
103#define DEBUG_OMAP4UART3_FLAGS 0
104#define DEBUG_OMAP4UART4_FLAGS 0
105#define DEBUG_TI81XXUART1_FLAGS 0
106#define DEBUG_TI81XXUART2_FLAGS 0
107#define DEBUG_TI81XXUART3_FLAGS 0
108#define DEBUG_AM33XXUART1_FLAGS 0
109
110#define DEBUG_OMAPUART_FLAGS (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET)
111
112#if defined(CONFIG_DEBUG_OMAP2UART1)
113#undef DEBUG_OMAP2UART1_FLAGS
114#define DEBUG_OMAP2UART1_FLAGS DEBUG_OMAPUART_FLAGS
115#elif defined(CONFIG_DEBUG_OMAP2UART2)
116#undef DEBUG_OMAP2UART2_FLAGS
117#define DEBUG_OMAP2UART2_FLAGS DEBUG_OMAPUART_FLAGS
118#elif defined(CONFIG_DEBUG_OMAP2UART3)
119#undef DEBUG_OMAP2UART3_FLAGS
120#define DEBUG_OMAP2UART3_FLAGS DEBUG_OMAPUART_FLAGS
121#elif defined(CONFIG_DEBUG_OMAP3UART3)
122#undef DEBUG_OMAP3UART3_FLAGS
123#define DEBUG_OMAP3UART3_FLAGS DEBUG_OMAPUART_FLAGS
124#elif defined(CONFIG_DEBUG_OMAP3UART4)
125#undef DEBUG_OMAP3UART4_FLAGS
126#define DEBUG_OMAP3UART4_FLAGS DEBUG_OMAPUART_FLAGS
127#elif defined(CONFIG_DEBUG_OMAP4UART3)
128#undef DEBUG_OMAP4UART3_FLAGS
129#define DEBUG_OMAP4UART3_FLAGS DEBUG_OMAPUART_FLAGS
130#elif defined(CONFIG_DEBUG_OMAP4UART4)
131#undef DEBUG_OMAP4UART4_FLAGS
132#define DEBUG_OMAP4UART4_FLAGS DEBUG_OMAPUART_FLAGS
133#elif defined(CONFIG_DEBUG_TI81XXUART1)
134#undef DEBUG_TI81XXUART1_FLAGS
135#define DEBUG_TI81XXUART1_FLAGS DEBUG_OMAPUART_FLAGS
136#elif defined(CONFIG_DEBUG_TI81XXUART2)
137#undef DEBUG_TI81XXUART2_FLAGS
138#define DEBUG_TI81XXUART2_FLAGS DEBUG_OMAPUART_FLAGS
139#elif defined(CONFIG_DEBUG_TI81XXUART3)
140#undef DEBUG_TI81XXUART3_FLAGS
141#define DEBUG_TI81XXUART3_FLAGS DEBUG_OMAPUART_FLAGS
142#elif defined(CONFIG_DEBUG_AM33XXUART1)
143#undef DEBUG_AM33XXUART1_FLAGS
144#define DEBUG_AM33XXUART1_FLAGS DEBUG_OMAPUART_FLAGS
145#endif
98 146
99/** 147/**
100 * struct omap_hwmod_mux_info - hwmod specific mux configuration 148 * struct omap_hwmod_mux_info - hwmod specific mux configuration
@@ -568,6 +616,7 @@ struct omap_hwmod_link {
568 * @voltdm: pointer to voltage domain (filled in at runtime) 616 * @voltdm: pointer to voltage domain (filled in at runtime)
569 * @dev_attr: arbitrary device attributes that can be passed to the driver 617 * @dev_attr: arbitrary device attributes that can be passed to the driver
570 * @_sysc_cache: internal-use hwmod flags 618 * @_sysc_cache: internal-use hwmod flags
619 * @mpu_rt_idx: index of device address space for register target (for DT boot)
571 * @_mpu_rt_va: cached register target start address (internal use) 620 * @_mpu_rt_va: cached register target start address (internal use)
572 * @_mpu_port: cached MPU register target slave (internal use) 621 * @_mpu_port: cached MPU register target slave (internal use)
573 * @opt_clks_cnt: number of @opt_clks 622 * @opt_clks_cnt: number of @opt_clks
@@ -617,6 +666,7 @@ struct omap_hwmod {
617 struct list_head node; 666 struct list_head node;
618 struct omap_hwmod_ocp_if *_mpu_port; 667 struct omap_hwmod_ocp_if *_mpu_port;
619 u16 flags; 668 u16 flags;
669 u8 mpu_rt_idx;
620 u8 response_lat; 670 u8 response_lat;
621 u8 rst_lines_cnt; 671 u8 rst_lines_cnt;
622 u8 opt_clks_cnt; 672 u8 opt_clks_cnt;
@@ -699,6 +749,7 @@ extern int omap2420_hwmod_init(void);
699extern int omap2430_hwmod_init(void); 749extern int omap2430_hwmod_init(void);
700extern int omap3xxx_hwmod_init(void); 750extern int omap3xxx_hwmod_init(void);
701extern int omap44xx_hwmod_init(void); 751extern int omap44xx_hwmod_init(void);
752extern int omap54xx_hwmod_init(void);
702extern int am33xx_hwmod_init(void); 753extern int am33xx_hwmod_init(void);
703 754
704extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois); 755extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 5137cc84b504..d8b9d60f854f 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -16,6 +16,7 @@
16#include <linux/i2c-omap.h> 16#include <linux/i2c-omap.h>
17#include <linux/platform_data/spi-omap2-mcspi.h> 17#include <linux/platform_data/spi-omap2-mcspi.h>
18#include <linux/omap-dma.h> 18#include <linux/omap-dma.h>
19#include <linux/platform_data/mailbox-omap.h>
19#include <plat/dmtimer.h> 20#include <plat/dmtimer.h>
20 21
21#include "omap_hwmod.h" 22#include "omap_hwmod.h"
@@ -166,6 +167,18 @@ static struct omap_hwmod omap2420_dma_system_hwmod = {
166}; 167};
167 168
168/* mailbox */ 169/* mailbox */
170static struct omap_mbox_dev_info omap2420_mailbox_info[] = {
171 { .name = "dsp", .tx_id = 0, .rx_id = 1, .irq_id = 0, .usr_id = 0 },
172 { .name = "iva", .tx_id = 2, .rx_id = 3, .irq_id = 1, .usr_id = 3 },
173};
174
175static struct omap_mbox_pdata omap2420_mailbox_attrs = {
176 .num_users = 4,
177 .num_fifos = 6,
178 .info_cnt = ARRAY_SIZE(omap2420_mailbox_info),
179 .info = omap2420_mailbox_info,
180};
181
169static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = { 182static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
170 { .name = "dsp", .irq = 26 + OMAP_INTC_START, }, 183 { .name = "dsp", .irq = 26 + OMAP_INTC_START, },
171 { .name = "iva", .irq = 34 + OMAP_INTC_START, }, 184 { .name = "iva", .irq = 34 + OMAP_INTC_START, },
@@ -186,6 +199,7 @@ static struct omap_hwmod omap2420_mailbox_hwmod = {
186 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, 199 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
187 }, 200 },
188 }, 201 },
202 .dev_attr = &omap2420_mailbox_attrs,
189}; 203};
190 204
191/* 205/*
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 4ce999ee3ee9..5b9083461dc5 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -17,6 +17,7 @@
17#include <linux/platform_data/asoc-ti-mcbsp.h> 17#include <linux/platform_data/asoc-ti-mcbsp.h>
18#include <linux/platform_data/spi-omap2-mcspi.h> 18#include <linux/platform_data/spi-omap2-mcspi.h>
19#include <linux/omap-dma.h> 19#include <linux/omap-dma.h>
20#include <linux/platform_data/mailbox-omap.h>
20#include <plat/dmtimer.h> 21#include <plat/dmtimer.h>
21 22
22#include "omap_hwmod.h" 23#include "omap_hwmod.h"
@@ -170,6 +171,17 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
170}; 171};
171 172
172/* mailbox */ 173/* mailbox */
174static struct omap_mbox_dev_info omap2430_mailbox_info[] = {
175 { .name = "dsp", .tx_id = 0, .rx_id = 1 },
176};
177
178static struct omap_mbox_pdata omap2430_mailbox_attrs = {
179 .num_users = 4,
180 .num_fifos = 6,
181 .info_cnt = ARRAY_SIZE(omap2430_mailbox_info),
182 .info = omap2430_mailbox_info,
183};
184
173static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = { 185static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
174 { .irq = 26 + OMAP_INTC_START, }, 186 { .irq = 26 + OMAP_INTC_START, },
175 { .irq = -1 }, 187 { .irq = -1 },
@@ -189,6 +201,7 @@ static struct omap_hwmod omap2430_mailbox_hwmod = {
189 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, 201 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
190 }, 202 },
191 }, 203 },
204 .dev_attr = &omap2430_mailbox_attrs,
192}; 205};
193 206
194/* mcspi3 */ 207/* mcspi3 */
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
index 534974e08add..5da7a42a6d90 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
@@ -17,7 +17,6 @@
17#include "hdq1w.h" 17#include "hdq1w.h"
18 18
19#include "omap_hwmod_common_data.h" 19#include "omap_hwmod_common_data.h"
20#include "dma.h"
21 20
22/* UART */ 21/* UART */
23 22
@@ -89,32 +88,32 @@ struct omap_hwmod_class omap2_venc_hwmod_class = {
89 88
90/* Common DMA request line data */ 89/* Common DMA request line data */
91struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = { 90struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {
92 { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, 91 { .name = "rx", .dma_req = 50, },
93 { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, 92 { .name = "tx", .dma_req = 49, },
94 { .dma_req = -1 } 93 { .dma_req = -1 }
95}; 94};
96 95
97struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = { 96struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {
98 { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, 97 { .name = "rx", .dma_req = 52, },
99 { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, 98 { .name = "tx", .dma_req = 51, },
100 { .dma_req = -1 } 99 { .dma_req = -1 }
101}; 100};
102 101
103struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = { 102struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {
104 { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, 103 { .name = "rx", .dma_req = 54, },
105 { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, 104 { .name = "tx", .dma_req = 53, },
106 { .dma_req = -1 } 105 { .dma_req = -1 }
107}; 106};
108 107
109struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = { 108struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {
110 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX }, 109 { .name = "tx", .dma_req = 27 },
111 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX }, 110 { .name = "rx", .dma_req = 28 },
112 { .dma_req = -1 } 111 { .dma_req = -1 }
113}; 112};
114 113
115struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = { 114struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {
116 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX }, 115 { .name = "tx", .dma_req = 29 },
117 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX }, 116 { .name = "rx", .dma_req = 30 },
118 { .dma_req = -1 } 117 { .dma_req = -1 }
119}; 118};
120 119
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index d05fc7b54567..56cebb05509e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -512,7 +512,7 @@ struct omap_hwmod omap2xxx_uart1_hwmod = {
512 .mpu_irqs = omap2_uart1_mpu_irqs, 512 .mpu_irqs = omap2_uart1_mpu_irqs,
513 .sdma_reqs = omap2_uart1_sdma_reqs, 513 .sdma_reqs = omap2_uart1_sdma_reqs,
514 .main_clk = "uart1_fck", 514 .main_clk = "uart1_fck",
515 .flags = HWMOD_SWSUP_SIDLE_ACT, 515 .flags = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
516 .prcm = { 516 .prcm = {
517 .omap2 = { 517 .omap2 = {
518 .module_offs = CORE_MOD, 518 .module_offs = CORE_MOD,
@@ -532,7 +532,7 @@ struct omap_hwmod omap2xxx_uart2_hwmod = {
532 .mpu_irqs = omap2_uart2_mpu_irqs, 532 .mpu_irqs = omap2_uart2_mpu_irqs,
533 .sdma_reqs = omap2_uart2_sdma_reqs, 533 .sdma_reqs = omap2_uart2_sdma_reqs,
534 .main_clk = "uart2_fck", 534 .main_clk = "uart2_fck",
535 .flags = HWMOD_SWSUP_SIDLE_ACT, 535 .flags = DEBUG_OMAP2UART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
536 .prcm = { 536 .prcm = {
537 .omap2 = { 537 .omap2 = {
538 .module_offs = CORE_MOD, 538 .module_offs = CORE_MOD,
@@ -552,7 +552,7 @@ struct omap_hwmod omap2xxx_uart3_hwmod = {
552 .mpu_irqs = omap2_uart3_mpu_irqs, 552 .mpu_irqs = omap2_uart3_mpu_irqs,
553 .sdma_reqs = omap2_uart3_sdma_reqs, 553 .sdma_reqs = omap2_uart3_sdma_reqs,
554 .main_clk = "uart3_fck", 554 .main_clk = "uart3_fck",
555 .flags = HWMOD_SWSUP_SIDLE_ACT, 555 .flags = DEBUG_OMAP2UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
556 .prcm = { 556 .prcm = {
557 .omap2 = { 557 .omap2 = {
558 .module_offs = CORE_MOD, 558 .module_offs = CORE_MOD,
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 69337af748cc..eb2f3b93b51c 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -35,29 +35,6 @@
35 */ 35 */
36 36
37/* 37/*
38 * 'emif_fw' class
39 * instance(s): emif_fw
40 */
41static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
42 .name = "emif_fw",
43};
44
45/* emif_fw */
46static struct omap_hwmod am33xx_emif_fw_hwmod = {
47 .name = "emif_fw",
48 .class = &am33xx_emif_fw_hwmod_class,
49 .clkdm_name = "l4fw_clkdm",
50 .main_clk = "l4fw_gclk",
51 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
52 .prcm = {
53 .omap4 = {
54 .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
55 .modulemode = MODULEMODE_SWCTRL,
56 },
57 },
58};
59
60/*
61 * 'emif' class 38 * 'emif' class
62 * instance(s): emif 39 * instance(s): emif
63 */ 40 */
@@ -70,18 +47,12 @@ static struct omap_hwmod_class am33xx_emif_hwmod_class = {
70 .sysc = &am33xx_emif_sysc, 47 .sysc = &am33xx_emif_sysc,
71}; 48};
72 49
73static struct omap_hwmod_irq_info am33xx_emif_irqs[] = {
74 { .name = "ddrerr0", .irq = 101 + OMAP_INTC_START, },
75 { .irq = -1 },
76};
77
78/* emif */ 50/* emif */
79static struct omap_hwmod am33xx_emif_hwmod = { 51static struct omap_hwmod am33xx_emif_hwmod = {
80 .name = "emif", 52 .name = "emif",
81 .class = &am33xx_emif_hwmod_class, 53 .class = &am33xx_emif_hwmod_class,
82 .clkdm_name = "l3_clkdm", 54 .clkdm_name = "l3_clkdm",
83 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), 55 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
84 .mpu_irqs = am33xx_emif_irqs,
85 .main_clk = "dpll_ddr_m2_div2_ck", 56 .main_clk = "dpll_ddr_m2_div2_ck",
86 .prcm = { 57 .prcm = {
87 .omap4 = { 58 .omap4 = {
@@ -99,19 +70,11 @@ static struct omap_hwmod_class am33xx_l3_hwmod_class = {
99 .name = "l3", 70 .name = "l3",
100}; 71};
101 72
102/* l3_main (l3_fast) */
103static struct omap_hwmod_irq_info am33xx_l3_main_irqs[] = {
104 { .name = "l3debug", .irq = 9 + OMAP_INTC_START, },
105 { .name = "l3appint", .irq = 10 + OMAP_INTC_START, },
106 { .irq = -1 },
107};
108
109static struct omap_hwmod am33xx_l3_main_hwmod = { 73static struct omap_hwmod am33xx_l3_main_hwmod = {
110 .name = "l3_main", 74 .name = "l3_main",
111 .class = &am33xx_l3_hwmod_class, 75 .class = &am33xx_l3_hwmod_class,
112 .clkdm_name = "l3_clkdm", 76 .clkdm_name = "l3_clkdm",
113 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), 77 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
114 .mpu_irqs = am33xx_l3_main_irqs,
115 .main_clk = "l3_gclk", 78 .main_clk = "l3_gclk",
116 .prcm = { 79 .prcm = {
117 .omap4 = { 80 .omap4 = {
@@ -196,20 +159,6 @@ static struct omap_hwmod am33xx_l4_wkup_hwmod = {
196 }, 159 },
197}; 160};
198 161
199/* l4_fw */
200static struct omap_hwmod am33xx_l4_fw_hwmod = {
201 .name = "l4_fw",
202 .class = &am33xx_l4_hwmod_class,
203 .clkdm_name = "l4fw_clkdm",
204 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
205 .prcm = {
206 .omap4 = {
207 .clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
208 .modulemode = MODULEMODE_SWCTRL,
209 },
210 },
211};
212
213/* 162/*
214 * 'mpu' class 163 * 'mpu' class
215 */ 164 */
@@ -217,21 +166,11 @@ static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
217 .name = "mpu", 166 .name = "mpu",
218}; 167};
219 168
220/* mpu */
221static struct omap_hwmod_irq_info am33xx_mpu_irqs[] = {
222 { .name = "emuint", .irq = 0 + OMAP_INTC_START, },
223 { .name = "commtx", .irq = 1 + OMAP_INTC_START, },
224 { .name = "commrx", .irq = 2 + OMAP_INTC_START, },
225 { .name = "bench", .irq = 3 + OMAP_INTC_START, },
226 { .irq = -1 },
227};
228
229static struct omap_hwmod am33xx_mpu_hwmod = { 169static struct omap_hwmod am33xx_mpu_hwmod = {
230 .name = "mpu", 170 .name = "mpu",
231 .class = &am33xx_mpu_hwmod_class, 171 .class = &am33xx_mpu_hwmod_class,
232 .clkdm_name = "mpu_clkdm", 172 .clkdm_name = "mpu_clkdm",
233 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), 173 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
234 .mpu_irqs = am33xx_mpu_irqs,
235 .main_clk = "dpll_mpu_m2_ck", 174 .main_clk = "dpll_mpu_m2_ck",
236 .prcm = { 175 .prcm = {
237 .omap4 = { 176 .omap4 = {
@@ -253,11 +192,6 @@ static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
253 { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 }, 192 { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
254}; 193};
255 194
256static struct omap_hwmod_irq_info am33xx_wkup_m3_irqs[] = {
257 { .name = "txev", .irq = 78 + OMAP_INTC_START, },
258 { .irq = -1 },
259};
260
261/* wkup_m3 */ 195/* wkup_m3 */
262static struct omap_hwmod am33xx_wkup_m3_hwmod = { 196static struct omap_hwmod am33xx_wkup_m3_hwmod = {
263 .name = "wkup_m3", 197 .name = "wkup_m3",
@@ -265,7 +199,6 @@ static struct omap_hwmod am33xx_wkup_m3_hwmod = {
265 .clkdm_name = "l4_wkup_aon_clkdm", 199 .clkdm_name = "l4_wkup_aon_clkdm",
266 /* Keep hardreset asserted */ 200 /* Keep hardreset asserted */
267 .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST, 201 .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
268 .mpu_irqs = am33xx_wkup_m3_irqs,
269 .main_clk = "dpll_core_m4_div2_ck", 202 .main_clk = "dpll_core_m4_div2_ck",
270 .prcm = { 203 .prcm = {
271 .omap4 = { 204 .omap4 = {
@@ -291,25 +224,12 @@ static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
291 { .name = "pruss", .rst_shift = 1 }, 224 { .name = "pruss", .rst_shift = 1 },
292}; 225};
293 226
294static struct omap_hwmod_irq_info am33xx_pruss_irqs[] = {
295 { .name = "evtout0", .irq = 20 + OMAP_INTC_START, },
296 { .name = "evtout1", .irq = 21 + OMAP_INTC_START, },
297 { .name = "evtout2", .irq = 22 + OMAP_INTC_START, },
298 { .name = "evtout3", .irq = 23 + OMAP_INTC_START, },
299 { .name = "evtout4", .irq = 24 + OMAP_INTC_START, },
300 { .name = "evtout5", .irq = 25 + OMAP_INTC_START, },
301 { .name = "evtout6", .irq = 26 + OMAP_INTC_START, },
302 { .name = "evtout7", .irq = 27 + OMAP_INTC_START, },
303 { .irq = -1 },
304};
305
306/* pru-icss */ 227/* pru-icss */
307/* Pseudo hwmod for reset control purpose only */ 228/* Pseudo hwmod for reset control purpose only */
308static struct omap_hwmod am33xx_pruss_hwmod = { 229static struct omap_hwmod am33xx_pruss_hwmod = {
309 .name = "pruss", 230 .name = "pruss",
310 .class = &am33xx_pruss_hwmod_class, 231 .class = &am33xx_pruss_hwmod_class,
311 .clkdm_name = "pruss_ocp_clkdm", 232 .clkdm_name = "pruss_ocp_clkdm",
312 .mpu_irqs = am33xx_pruss_irqs,
313 .main_clk = "pruss_ocp_gclk", 233 .main_clk = "pruss_ocp_gclk",
314 .prcm = { 234 .prcm = {
315 .omap4 = { 235 .omap4 = {
@@ -329,24 +249,19 @@ static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
329}; 249};
330 250
331static struct omap_hwmod_rst_info am33xx_gfx_resets[] = { 251static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
332 { .name = "gfx", .rst_shift = 0 }, 252 { .name = "gfx", .rst_shift = 0, .st_shift = 0},
333};
334
335static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
336 { .name = "gfxint", .irq = 37 + OMAP_INTC_START, },
337 { .irq = -1 },
338}; 253};
339 254
340static struct omap_hwmod am33xx_gfx_hwmod = { 255static struct omap_hwmod am33xx_gfx_hwmod = {
341 .name = "gfx", 256 .name = "gfx",
342 .class = &am33xx_gfx_hwmod_class, 257 .class = &am33xx_gfx_hwmod_class,
343 .clkdm_name = "gfx_l3_clkdm", 258 .clkdm_name = "gfx_l3_clkdm",
344 .mpu_irqs = am33xx_gfx_irqs,
345 .main_clk = "gfx_fck_div_ck", 259 .main_clk = "gfx_fck_div_ck",
346 .prcm = { 260 .prcm = {
347 .omap4 = { 261 .omap4 = {
348 .clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET, 262 .clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
349 .rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET, 263 .rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET,
264 .rstst_offs = AM33XX_RM_GFX_RSTST_OFFSET,
350 .modulemode = MODULEMODE_SWCTRL, 265 .modulemode = MODULEMODE_SWCTRL,
351 }, 266 },
352 }, 267 },
@@ -387,16 +302,10 @@ static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
387 .sysc = &am33xx_adc_tsc_sysc, 302 .sysc = &am33xx_adc_tsc_sysc,
388}; 303};
389 304
390static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
391 { .irq = 16 + OMAP_INTC_START, },
392 { .irq = -1 },
393};
394
395static struct omap_hwmod am33xx_adc_tsc_hwmod = { 305static struct omap_hwmod am33xx_adc_tsc_hwmod = {
396 .name = "adc_tsc", 306 .name = "adc_tsc",
397 .class = &am33xx_adc_tsc_hwmod_class, 307 .class = &am33xx_adc_tsc_hwmod_class,
398 .clkdm_name = "l4_wkup_clkdm", 308 .clkdm_name = "l4_wkup_clkdm",
399 .mpu_irqs = am33xx_adc_tsc_irqs,
400 .main_clk = "adc_tsc_fck", 309 .main_clk = "adc_tsc_fck",
401 .prcm = { 310 .prcm = {
402 .omap4 = { 311 .omap4 = {
@@ -515,23 +424,10 @@ static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
515 .sysc = &am33xx_aes0_sysc, 424 .sysc = &am33xx_aes0_sysc,
516}; 425};
517 426
518static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
519 { .irq = 103 + OMAP_INTC_START, },
520 { .irq = -1 },
521};
522
523static struct omap_hwmod_dma_info am33xx_aes0_edma_reqs[] = {
524 { .name = "tx", .dma_req = 6, },
525 { .name = "rx", .dma_req = 5, },
526 { .dma_req = -1 }
527};
528
529static struct omap_hwmod am33xx_aes0_hwmod = { 427static struct omap_hwmod am33xx_aes0_hwmod = {
530 .name = "aes", 428 .name = "aes",
531 .class = &am33xx_aes0_hwmod_class, 429 .class = &am33xx_aes0_hwmod_class,
532 .clkdm_name = "l3_clkdm", 430 .clkdm_name = "l3_clkdm",
533 .mpu_irqs = am33xx_aes0_irqs,
534 .sdma_reqs = am33xx_aes0_edma_reqs,
535 .main_clk = "aes0_fck", 431 .main_clk = "aes0_fck",
536 .prcm = { 432 .prcm = {
537 .omap4 = { 433 .omap4 = {
@@ -554,22 +450,10 @@ static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
554 .sysc = &am33xx_sha0_sysc, 450 .sysc = &am33xx_sha0_sysc,
555}; 451};
556 452
557static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
558 { .irq = 109 + OMAP_INTC_START, },
559 { .irq = -1 },
560};
561
562static struct omap_hwmod_dma_info am33xx_sha0_edma_reqs[] = {
563 { .name = "rx", .dma_req = 36, },
564 { .dma_req = -1 }
565};
566
567static struct omap_hwmod am33xx_sha0_hwmod = { 453static struct omap_hwmod am33xx_sha0_hwmod = {
568 .name = "sham", 454 .name = "sham",
569 .class = &am33xx_sha0_hwmod_class, 455 .class = &am33xx_sha0_hwmod_class,
570 .clkdm_name = "l3_clkdm", 456 .clkdm_name = "l3_clkdm",
571 .mpu_irqs = am33xx_sha0_irqs,
572 .sdma_reqs = am33xx_sha0_edma_reqs,
573 .main_clk = "l3_gclk", 457 .main_clk = "l3_gclk",
574 .prcm = { 458 .prcm = {
575 .omap4 = { 459 .omap4 = {
@@ -604,16 +488,10 @@ static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
604}; 488};
605 489
606/* smartreflex0 */ 490/* smartreflex0 */
607static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
608 { .irq = 120 + OMAP_INTC_START, },
609 { .irq = -1 },
610};
611
612static struct omap_hwmod am33xx_smartreflex0_hwmod = { 491static struct omap_hwmod am33xx_smartreflex0_hwmod = {
613 .name = "smartreflex0", 492 .name = "smartreflex0",
614 .class = &am33xx_smartreflex_hwmod_class, 493 .class = &am33xx_smartreflex_hwmod_class,
615 .clkdm_name = "l4_wkup_clkdm", 494 .clkdm_name = "l4_wkup_clkdm",
616 .mpu_irqs = am33xx_smartreflex0_irqs,
617 .main_clk = "smartreflex0_fck", 495 .main_clk = "smartreflex0_fck",
618 .prcm = { 496 .prcm = {
619 .omap4 = { 497 .omap4 = {
@@ -624,16 +502,10 @@ static struct omap_hwmod am33xx_smartreflex0_hwmod = {
624}; 502};
625 503
626/* smartreflex1 */ 504/* smartreflex1 */
627static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
628 { .irq = 121 + OMAP_INTC_START, },
629 { .irq = -1 },
630};
631
632static struct omap_hwmod am33xx_smartreflex1_hwmod = { 505static struct omap_hwmod am33xx_smartreflex1_hwmod = {
633 .name = "smartreflex1", 506 .name = "smartreflex1",
634 .class = &am33xx_smartreflex_hwmod_class, 507 .class = &am33xx_smartreflex_hwmod_class,
635 .clkdm_name = "l4_wkup_clkdm", 508 .clkdm_name = "l4_wkup_clkdm",
636 .mpu_irqs = am33xx_smartreflex1_irqs,
637 .main_clk = "smartreflex1_fck", 509 .main_clk = "smartreflex1_fck",
638 .prcm = { 510 .prcm = {
639 .omap4 = { 511 .omap4 = {
@@ -650,17 +522,11 @@ static struct omap_hwmod_class am33xx_control_hwmod_class = {
650 .name = "control", 522 .name = "control",
651}; 523};
652 524
653static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
654 { .irq = 8 + OMAP_INTC_START, },
655 { .irq = -1 },
656};
657
658static struct omap_hwmod am33xx_control_hwmod = { 525static struct omap_hwmod am33xx_control_hwmod = {
659 .name = "control", 526 .name = "control",
660 .class = &am33xx_control_hwmod_class, 527 .class = &am33xx_control_hwmod_class,
661 .clkdm_name = "l4_wkup_clkdm", 528 .clkdm_name = "l4_wkup_clkdm",
662 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), 529 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
663 .mpu_irqs = am33xx_control_irqs,
664 .main_clk = "dpll_core_m4_div2_ck", 530 .main_clk = "dpll_core_m4_div2_ck",
665 .prcm = { 531 .prcm = {
666 .omap4 = { 532 .omap4 = {
@@ -690,21 +556,13 @@ static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
690 .sysc = &am33xx_cpgmac_sysc, 556 .sysc = &am33xx_cpgmac_sysc,
691}; 557};
692 558
693static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
694 { .name = "c0_rx_thresh_pend", .irq = 40 + OMAP_INTC_START, },
695 { .name = "c0_rx_pend", .irq = 41 + OMAP_INTC_START, },
696 { .name = "c0_tx_pend", .irq = 42 + OMAP_INTC_START, },
697 { .name = "c0_misc_pend", .irq = 43 + OMAP_INTC_START, },
698 { .irq = -1 },
699};
700
701static struct omap_hwmod am33xx_cpgmac0_hwmod = { 559static struct omap_hwmod am33xx_cpgmac0_hwmod = {
702 .name = "cpgmac0", 560 .name = "cpgmac0",
703 .class = &am33xx_cpgmac0_hwmod_class, 561 .class = &am33xx_cpgmac0_hwmod_class,
704 .clkdm_name = "cpsw_125mhz_clkdm", 562 .clkdm_name = "cpsw_125mhz_clkdm",
705 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), 563 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
706 .mpu_irqs = am33xx_cpgmac0_irqs,
707 .main_clk = "cpsw_125mhz_gclk", 564 .main_clk = "cpsw_125mhz_gclk",
565 .mpu_rt_idx = 1,
708 .prcm = { 566 .prcm = {
709 .omap4 = { 567 .omap4 = {
710 .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET, 568 .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
@@ -735,17 +593,10 @@ static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
735}; 593};
736 594
737/* dcan0 */ 595/* dcan0 */
738static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
739 { .name = "d_can_ms", .irq = 52 + OMAP_INTC_START, },
740 { .name = "d_can_mo", .irq = 53 + OMAP_INTC_START, },
741 { .irq = -1 },
742};
743
744static struct omap_hwmod am33xx_dcan0_hwmod = { 596static struct omap_hwmod am33xx_dcan0_hwmod = {
745 .name = "d_can0", 597 .name = "d_can0",
746 .class = &am33xx_dcan_hwmod_class, 598 .class = &am33xx_dcan_hwmod_class,
747 .clkdm_name = "l4ls_clkdm", 599 .clkdm_name = "l4ls_clkdm",
748 .mpu_irqs = am33xx_dcan0_irqs,
749 .main_clk = "dcan0_fck", 600 .main_clk = "dcan0_fck",
750 .prcm = { 601 .prcm = {
751 .omap4 = { 602 .omap4 = {
@@ -756,16 +607,10 @@ static struct omap_hwmod am33xx_dcan0_hwmod = {
756}; 607};
757 608
758/* dcan1 */ 609/* dcan1 */
759static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
760 { .name = "d_can_ms", .irq = 55 + OMAP_INTC_START, },
761 { .name = "d_can_mo", .irq = 56 + OMAP_INTC_START, },
762 { .irq = -1 },
763};
764static struct omap_hwmod am33xx_dcan1_hwmod = { 610static struct omap_hwmod am33xx_dcan1_hwmod = {
765 .name = "d_can1", 611 .name = "d_can1",
766 .class = &am33xx_dcan_hwmod_class, 612 .class = &am33xx_dcan_hwmod_class,
767 .clkdm_name = "l4ls_clkdm", 613 .clkdm_name = "l4ls_clkdm",
768 .mpu_irqs = am33xx_dcan1_irqs,
769 .main_clk = "dcan1_fck", 614 .main_clk = "dcan1_fck",
770 .prcm = { 615 .prcm = {
771 .omap4 = { 616 .omap4 = {
@@ -792,16 +637,10 @@ static struct omap_hwmod_class am33xx_elm_hwmod_class = {
792 .sysc = &am33xx_elm_sysc, 637 .sysc = &am33xx_elm_sysc,
793}; 638};
794 639
795static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
796 { .irq = 4 + OMAP_INTC_START, },
797 { .irq = -1 },
798};
799
800static struct omap_hwmod am33xx_elm_hwmod = { 640static struct omap_hwmod am33xx_elm_hwmod = {
801 .name = "elm", 641 .name = "elm",
802 .class = &am33xx_elm_hwmod_class, 642 .class = &am33xx_elm_hwmod_class,
803 .clkdm_name = "l4ls_clkdm", 643 .clkdm_name = "l4ls_clkdm",
804 .mpu_irqs = am33xx_elm_irqs,
805 .main_clk = "l4ls_gclk", 644 .main_clk = "l4ls_gclk",
806 .prcm = { 645 .prcm = {
807 .omap4 = { 646 .omap4 = {
@@ -854,45 +693,26 @@ static struct omap_hwmod am33xx_epwmss0_hwmod = {
854}; 693};
855 694
856/* ecap0 */ 695/* ecap0 */
857static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
858 { .irq = 31 + OMAP_INTC_START, },
859 { .irq = -1 },
860};
861
862static struct omap_hwmod am33xx_ecap0_hwmod = { 696static struct omap_hwmod am33xx_ecap0_hwmod = {
863 .name = "ecap0", 697 .name = "ecap0",
864 .class = &am33xx_ecap_hwmod_class, 698 .class = &am33xx_ecap_hwmod_class,
865 .clkdm_name = "l4ls_clkdm", 699 .clkdm_name = "l4ls_clkdm",
866 .mpu_irqs = am33xx_ecap0_irqs,
867 .main_clk = "l4ls_gclk", 700 .main_clk = "l4ls_gclk",
868}; 701};
869 702
870/* eqep0 */ 703/* eqep0 */
871static struct omap_hwmod_irq_info am33xx_eqep0_irqs[] = {
872 { .irq = 79 + OMAP_INTC_START, },
873 { .irq = -1 },
874};
875
876static struct omap_hwmod am33xx_eqep0_hwmod = { 704static struct omap_hwmod am33xx_eqep0_hwmod = {
877 .name = "eqep0", 705 .name = "eqep0",
878 .class = &am33xx_eqep_hwmod_class, 706 .class = &am33xx_eqep_hwmod_class,
879 .clkdm_name = "l4ls_clkdm", 707 .clkdm_name = "l4ls_clkdm",
880 .mpu_irqs = am33xx_eqep0_irqs,
881 .main_clk = "l4ls_gclk", 708 .main_clk = "l4ls_gclk",
882}; 709};
883 710
884/* ehrpwm0 */ 711/* ehrpwm0 */
885static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
886 { .name = "int", .irq = 86 + OMAP_INTC_START, },
887 { .name = "tzint", .irq = 58 + OMAP_INTC_START, },
888 { .irq = -1 },
889};
890
891static struct omap_hwmod am33xx_ehrpwm0_hwmod = { 712static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
892 .name = "ehrpwm0", 713 .name = "ehrpwm0",
893 .class = &am33xx_ehrpwm_hwmod_class, 714 .class = &am33xx_ehrpwm_hwmod_class,
894 .clkdm_name = "l4ls_clkdm", 715 .clkdm_name = "l4ls_clkdm",
895 .mpu_irqs = am33xx_ehrpwm0_irqs,
896 .main_clk = "l4ls_gclk", 716 .main_clk = "l4ls_gclk",
897}; 717};
898 718
@@ -911,45 +731,26 @@ static struct omap_hwmod am33xx_epwmss1_hwmod = {
911}; 731};
912 732
913/* ecap1 */ 733/* ecap1 */
914static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
915 { .irq = 47 + OMAP_INTC_START, },
916 { .irq = -1 },
917};
918
919static struct omap_hwmod am33xx_ecap1_hwmod = { 734static struct omap_hwmod am33xx_ecap1_hwmod = {
920 .name = "ecap1", 735 .name = "ecap1",
921 .class = &am33xx_ecap_hwmod_class, 736 .class = &am33xx_ecap_hwmod_class,
922 .clkdm_name = "l4ls_clkdm", 737 .clkdm_name = "l4ls_clkdm",
923 .mpu_irqs = am33xx_ecap1_irqs,
924 .main_clk = "l4ls_gclk", 738 .main_clk = "l4ls_gclk",
925}; 739};
926 740
927/* eqep1 */ 741/* eqep1 */
928static struct omap_hwmod_irq_info am33xx_eqep1_irqs[] = {
929 { .irq = 88 + OMAP_INTC_START, },
930 { .irq = -1 },
931};
932
933static struct omap_hwmod am33xx_eqep1_hwmod = { 742static struct omap_hwmod am33xx_eqep1_hwmod = {
934 .name = "eqep1", 743 .name = "eqep1",
935 .class = &am33xx_eqep_hwmod_class, 744 .class = &am33xx_eqep_hwmod_class,
936 .clkdm_name = "l4ls_clkdm", 745 .clkdm_name = "l4ls_clkdm",
937 .mpu_irqs = am33xx_eqep1_irqs,
938 .main_clk = "l4ls_gclk", 746 .main_clk = "l4ls_gclk",
939}; 747};
940 748
941/* ehrpwm1 */ 749/* ehrpwm1 */
942static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
943 { .name = "int", .irq = 87 + OMAP_INTC_START, },
944 { .name = "tzint", .irq = 59 + OMAP_INTC_START, },
945 { .irq = -1 },
946};
947
948static struct omap_hwmod am33xx_ehrpwm1_hwmod = { 750static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
949 .name = "ehrpwm1", 751 .name = "ehrpwm1",
950 .class = &am33xx_ehrpwm_hwmod_class, 752 .class = &am33xx_ehrpwm_hwmod_class,
951 .clkdm_name = "l4ls_clkdm", 753 .clkdm_name = "l4ls_clkdm",
952 .mpu_irqs = am33xx_ehrpwm1_irqs,
953 .main_clk = "l4ls_gclk", 754 .main_clk = "l4ls_gclk",
954}; 755};
955 756
@@ -968,45 +769,26 @@ static struct omap_hwmod am33xx_epwmss2_hwmod = {
968}; 769};
969 770
970/* ecap2 */ 771/* ecap2 */
971static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
972 { .irq = 61 + OMAP_INTC_START, },
973 { .irq = -1 },
974};
975
976static struct omap_hwmod am33xx_ecap2_hwmod = { 772static struct omap_hwmod am33xx_ecap2_hwmod = {
977 .name = "ecap2", 773 .name = "ecap2",
978 .class = &am33xx_ecap_hwmod_class, 774 .class = &am33xx_ecap_hwmod_class,
979 .clkdm_name = "l4ls_clkdm", 775 .clkdm_name = "l4ls_clkdm",
980 .mpu_irqs = am33xx_ecap2_irqs,
981 .main_clk = "l4ls_gclk", 776 .main_clk = "l4ls_gclk",
982}; 777};
983 778
984/* eqep2 */ 779/* eqep2 */
985static struct omap_hwmod_irq_info am33xx_eqep2_irqs[] = {
986 { .irq = 89 + OMAP_INTC_START, },
987 { .irq = -1 },
988};
989
990static struct omap_hwmod am33xx_eqep2_hwmod = { 780static struct omap_hwmod am33xx_eqep2_hwmod = {
991 .name = "eqep2", 781 .name = "eqep2",
992 .class = &am33xx_eqep_hwmod_class, 782 .class = &am33xx_eqep_hwmod_class,
993 .clkdm_name = "l4ls_clkdm", 783 .clkdm_name = "l4ls_clkdm",
994 .mpu_irqs = am33xx_eqep2_irqs,
995 .main_clk = "l4ls_gclk", 784 .main_clk = "l4ls_gclk",
996}; 785};
997 786
998/* ehrpwm2 */ 787/* ehrpwm2 */
999static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
1000 { .name = "int", .irq = 39 + OMAP_INTC_START, },
1001 { .name = "tzint", .irq = 60 + OMAP_INTC_START, },
1002 { .irq = -1 },
1003};
1004
1005static struct omap_hwmod am33xx_ehrpwm2_hwmod = { 788static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
1006 .name = "ehrpwm2", 789 .name = "ehrpwm2",
1007 .class = &am33xx_ehrpwm_hwmod_class, 790 .class = &am33xx_ehrpwm_hwmod_class,
1008 .clkdm_name = "l4ls_clkdm", 791 .clkdm_name = "l4ls_clkdm",
1009 .mpu_irqs = am33xx_ehrpwm2_irqs,
1010 .main_clk = "l4ls_gclk", 792 .main_clk = "l4ls_gclk",
1011}; 793};
1012 794
@@ -1041,17 +823,11 @@ static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
1041 { .role = "dbclk", .clk = "gpio0_dbclk" }, 823 { .role = "dbclk", .clk = "gpio0_dbclk" },
1042}; 824};
1043 825
1044static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
1045 { .irq = 96 + OMAP_INTC_START, },
1046 { .irq = -1 },
1047};
1048
1049static struct omap_hwmod am33xx_gpio0_hwmod = { 826static struct omap_hwmod am33xx_gpio0_hwmod = {
1050 .name = "gpio1", 827 .name = "gpio1",
1051 .class = &am33xx_gpio_hwmod_class, 828 .class = &am33xx_gpio_hwmod_class,
1052 .clkdm_name = "l4_wkup_clkdm", 829 .clkdm_name = "l4_wkup_clkdm",
1053 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 830 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1054 .mpu_irqs = am33xx_gpio0_irqs,
1055 .main_clk = "dpll_core_m4_div2_ck", 831 .main_clk = "dpll_core_m4_div2_ck",
1056 .prcm = { 832 .prcm = {
1057 .omap4 = { 833 .omap4 = {
@@ -1065,11 +841,6 @@ static struct omap_hwmod am33xx_gpio0_hwmod = {
1065}; 841};
1066 842
1067/* gpio1 */ 843/* gpio1 */
1068static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
1069 { .irq = 98 + OMAP_INTC_START, },
1070 { .irq = -1 },
1071};
1072
1073static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { 844static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1074 { .role = "dbclk", .clk = "gpio1_dbclk" }, 845 { .role = "dbclk", .clk = "gpio1_dbclk" },
1075}; 846};
@@ -1079,7 +850,6 @@ static struct omap_hwmod am33xx_gpio1_hwmod = {
1079 .class = &am33xx_gpio_hwmod_class, 850 .class = &am33xx_gpio_hwmod_class,
1080 .clkdm_name = "l4ls_clkdm", 851 .clkdm_name = "l4ls_clkdm",
1081 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 852 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1082 .mpu_irqs = am33xx_gpio1_irqs,
1083 .main_clk = "l4ls_gclk", 853 .main_clk = "l4ls_gclk",
1084 .prcm = { 854 .prcm = {
1085 .omap4 = { 855 .omap4 = {
@@ -1093,11 +863,6 @@ static struct omap_hwmod am33xx_gpio1_hwmod = {
1093}; 863};
1094 864
1095/* gpio2 */ 865/* gpio2 */
1096static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
1097 { .irq = 32 + OMAP_INTC_START, },
1098 { .irq = -1 },
1099};
1100
1101static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { 866static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1102 { .role = "dbclk", .clk = "gpio2_dbclk" }, 867 { .role = "dbclk", .clk = "gpio2_dbclk" },
1103}; 868};
@@ -1107,7 +872,6 @@ static struct omap_hwmod am33xx_gpio2_hwmod = {
1107 .class = &am33xx_gpio_hwmod_class, 872 .class = &am33xx_gpio_hwmod_class,
1108 .clkdm_name = "l4ls_clkdm", 873 .clkdm_name = "l4ls_clkdm",
1109 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 874 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1110 .mpu_irqs = am33xx_gpio2_irqs,
1111 .main_clk = "l4ls_gclk", 875 .main_clk = "l4ls_gclk",
1112 .prcm = { 876 .prcm = {
1113 .omap4 = { 877 .omap4 = {
@@ -1121,11 +885,6 @@ static struct omap_hwmod am33xx_gpio2_hwmod = {
1121}; 885};
1122 886
1123/* gpio3 */ 887/* gpio3 */
1124static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
1125 { .irq = 62 + OMAP_INTC_START, },
1126 { .irq = -1 },
1127};
1128
1129static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { 888static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1130 { .role = "dbclk", .clk = "gpio3_dbclk" }, 889 { .role = "dbclk", .clk = "gpio3_dbclk" },
1131}; 890};
@@ -1135,7 +894,6 @@ static struct omap_hwmod am33xx_gpio3_hwmod = {
1135 .class = &am33xx_gpio_hwmod_class, 894 .class = &am33xx_gpio_hwmod_class,
1136 .clkdm_name = "l4ls_clkdm", 895 .clkdm_name = "l4ls_clkdm",
1137 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 896 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1138 .mpu_irqs = am33xx_gpio3_irqs,
1139 .main_clk = "l4ls_gclk", 897 .main_clk = "l4ls_gclk",
1140 .prcm = { 898 .prcm = {
1141 .omap4 = { 899 .omap4 = {
@@ -1164,17 +922,11 @@ static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
1164 .sysc = &gpmc_sysc, 922 .sysc = &gpmc_sysc,
1165}; 923};
1166 924
1167static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = {
1168 { .irq = 100 + OMAP_INTC_START, },
1169 { .irq = -1 },
1170};
1171
1172static struct omap_hwmod am33xx_gpmc_hwmod = { 925static struct omap_hwmod am33xx_gpmc_hwmod = {
1173 .name = "gpmc", 926 .name = "gpmc",
1174 .class = &am33xx_gpmc_hwmod_class, 927 .class = &am33xx_gpmc_hwmod_class,
1175 .clkdm_name = "l3s_clkdm", 928 .clkdm_name = "l3s_clkdm",
1176 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), 929 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1177 .mpu_irqs = am33xx_gpmc_irqs,
1178 .main_clk = "l3s_gclk", 930 .main_clk = "l3s_gclk",
1179 .prcm = { 931 .prcm = {
1180 .omap4 = { 932 .omap4 = {
@@ -1208,23 +960,10 @@ static struct omap_i2c_dev_attr i2c_dev_attr = {
1208}; 960};
1209 961
1210/* i2c1 */ 962/* i2c1 */
1211static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1212 { .irq = 70 + OMAP_INTC_START, },
1213 { .irq = -1 },
1214};
1215
1216static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
1217 { .name = "tx", .dma_req = 0, },
1218 { .name = "rx", .dma_req = 0, },
1219 { .dma_req = -1 }
1220};
1221
1222static struct omap_hwmod am33xx_i2c1_hwmod = { 963static struct omap_hwmod am33xx_i2c1_hwmod = {
1223 .name = "i2c1", 964 .name = "i2c1",
1224 .class = &i2c_class, 965 .class = &i2c_class,
1225 .clkdm_name = "l4_wkup_clkdm", 966 .clkdm_name = "l4_wkup_clkdm",
1226 .mpu_irqs = i2c1_mpu_irqs,
1227 .sdma_reqs = i2c1_edma_reqs,
1228 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 967 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1229 .main_clk = "dpll_per_m2_div4_wkupdm_ck", 968 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
1230 .prcm = { 969 .prcm = {
@@ -1237,23 +976,10 @@ static struct omap_hwmod am33xx_i2c1_hwmod = {
1237}; 976};
1238 977
1239/* i2c1 */ 978/* i2c1 */
1240static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1241 { .irq = 71 + OMAP_INTC_START, },
1242 { .irq = -1 },
1243};
1244
1245static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
1246 { .name = "tx", .dma_req = 0, },
1247 { .name = "rx", .dma_req = 0, },
1248 { .dma_req = -1 }
1249};
1250
1251static struct omap_hwmod am33xx_i2c2_hwmod = { 979static struct omap_hwmod am33xx_i2c2_hwmod = {
1252 .name = "i2c2", 980 .name = "i2c2",
1253 .class = &i2c_class, 981 .class = &i2c_class,
1254 .clkdm_name = "l4ls_clkdm", 982 .clkdm_name = "l4ls_clkdm",
1255 .mpu_irqs = i2c2_mpu_irqs,
1256 .sdma_reqs = i2c2_edma_reqs,
1257 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 983 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1258 .main_clk = "dpll_per_m2_div4_ck", 984 .main_clk = "dpll_per_m2_div4_ck",
1259 .prcm = { 985 .prcm = {
@@ -1266,23 +992,10 @@ static struct omap_hwmod am33xx_i2c2_hwmod = {
1266}; 992};
1267 993
1268/* i2c3 */ 994/* i2c3 */
1269static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
1270 { .name = "tx", .dma_req = 0, },
1271 { .name = "rx", .dma_req = 0, },
1272 { .dma_req = -1 }
1273};
1274
1275static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1276 { .irq = 30 + OMAP_INTC_START, },
1277 { .irq = -1 },
1278};
1279
1280static struct omap_hwmod am33xx_i2c3_hwmod = { 995static struct omap_hwmod am33xx_i2c3_hwmod = {
1281 .name = "i2c3", 996 .name = "i2c3",
1282 .class = &i2c_class, 997 .class = &i2c_class,
1283 .clkdm_name = "l4ls_clkdm", 998 .clkdm_name = "l4ls_clkdm",
1284 .mpu_irqs = i2c3_mpu_irqs,
1285 .sdma_reqs = i2c3_edma_reqs,
1286 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 999 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1287 .main_clk = "dpll_per_m2_div4_ck", 1000 .main_clk = "dpll_per_m2_div4_ck",
1288 .prcm = { 1001 .prcm = {
@@ -1309,16 +1022,10 @@ static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
1309 .sysc = &lcdc_sysc, 1022 .sysc = &lcdc_sysc,
1310}; 1023};
1311 1024
1312static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
1313 { .irq = 36 + OMAP_INTC_START, },
1314 { .irq = -1 },
1315};
1316
1317static struct omap_hwmod am33xx_lcdc_hwmod = { 1025static struct omap_hwmod am33xx_lcdc_hwmod = {
1318 .name = "lcdc", 1026 .name = "lcdc",
1319 .class = &am33xx_lcdc_hwmod_class, 1027 .class = &am33xx_lcdc_hwmod_class,
1320 .clkdm_name = "lcdc_clkdm", 1028 .clkdm_name = "lcdc_clkdm",
1321 .mpu_irqs = am33xx_lcdc_irqs,
1322 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, 1029 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1323 .main_clk = "lcd_gclk", 1030 .main_clk = "lcd_gclk",
1324 .prcm = { 1031 .prcm = {
@@ -1348,16 +1055,10 @@ static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
1348 .sysc = &am33xx_mailbox_sysc, 1055 .sysc = &am33xx_mailbox_sysc,
1349}; 1056};
1350 1057
1351static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
1352 { .irq = 77 + OMAP_INTC_START, },
1353 { .irq = -1 },
1354};
1355
1356static struct omap_hwmod am33xx_mailbox_hwmod = { 1058static struct omap_hwmod am33xx_mailbox_hwmod = {
1357 .name = "mailbox", 1059 .name = "mailbox",
1358 .class = &am33xx_mailbox_hwmod_class, 1060 .class = &am33xx_mailbox_hwmod_class,
1359 .clkdm_name = "l4ls_clkdm", 1061 .clkdm_name = "l4ls_clkdm",
1360 .mpu_irqs = am33xx_mailbox_irqs,
1361 .main_clk = "l4ls_gclk", 1062 .main_clk = "l4ls_gclk",
1362 .prcm = { 1063 .prcm = {
1363 .omap4 = { 1064 .omap4 = {
@@ -1384,24 +1085,10 @@ static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
1384}; 1085};
1385 1086
1386/* mcasp0 */ 1087/* mcasp0 */
1387static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
1388 { .name = "ax", .irq = 80 + OMAP_INTC_START, },
1389 { .name = "ar", .irq = 81 + OMAP_INTC_START, },
1390 { .irq = -1 },
1391};
1392
1393static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = {
1394 { .name = "tx", .dma_req = 8, },
1395 { .name = "rx", .dma_req = 9, },
1396 { .dma_req = -1 }
1397};
1398
1399static struct omap_hwmod am33xx_mcasp0_hwmod = { 1088static struct omap_hwmod am33xx_mcasp0_hwmod = {
1400 .name = "mcasp0", 1089 .name = "mcasp0",
1401 .class = &am33xx_mcasp_hwmod_class, 1090 .class = &am33xx_mcasp_hwmod_class,
1402 .clkdm_name = "l3s_clkdm", 1091 .clkdm_name = "l3s_clkdm",
1403 .mpu_irqs = am33xx_mcasp0_irqs,
1404 .sdma_reqs = am33xx_mcasp0_edma_reqs,
1405 .main_clk = "mcasp0_fck", 1092 .main_clk = "mcasp0_fck",
1406 .prcm = { 1093 .prcm = {
1407 .omap4 = { 1094 .omap4 = {
@@ -1412,24 +1099,10 @@ static struct omap_hwmod am33xx_mcasp0_hwmod = {
1412}; 1099};
1413 1100
1414/* mcasp1 */ 1101/* mcasp1 */
1415static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
1416 { .name = "ax", .irq = 82 + OMAP_INTC_START, },
1417 { .name = "ar", .irq = 83 + OMAP_INTC_START, },
1418 { .irq = -1 },
1419};
1420
1421static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = {
1422 { .name = "tx", .dma_req = 10, },
1423 { .name = "rx", .dma_req = 11, },
1424 { .dma_req = -1 }
1425};
1426
1427static struct omap_hwmod am33xx_mcasp1_hwmod = { 1102static struct omap_hwmod am33xx_mcasp1_hwmod = {
1428 .name = "mcasp1", 1103 .name = "mcasp1",
1429 .class = &am33xx_mcasp_hwmod_class, 1104 .class = &am33xx_mcasp_hwmod_class,
1430 .clkdm_name = "l3s_clkdm", 1105 .clkdm_name = "l3s_clkdm",
1431 .mpu_irqs = am33xx_mcasp1_irqs,
1432 .sdma_reqs = am33xx_mcasp1_edma_reqs,
1433 .main_clk = "mcasp1_fck", 1106 .main_clk = "mcasp1_fck",
1434 .prcm = { 1107 .prcm = {
1435 .omap4 = { 1108 .omap4 = {
@@ -1457,17 +1130,6 @@ static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
1457}; 1130};
1458 1131
1459/* mmc0 */ 1132/* mmc0 */
1460static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
1461 { .irq = 64 + OMAP_INTC_START, },
1462 { .irq = -1 },
1463};
1464
1465static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
1466 { .name = "tx", .dma_req = 24, },
1467 { .name = "rx", .dma_req = 25, },
1468 { .dma_req = -1 }
1469};
1470
1471static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = { 1133static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
1472 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, 1134 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1473}; 1135};
@@ -1476,8 +1138,6 @@ static struct omap_hwmod am33xx_mmc0_hwmod = {
1476 .name = "mmc1", 1138 .name = "mmc1",
1477 .class = &am33xx_mmc_hwmod_class, 1139 .class = &am33xx_mmc_hwmod_class,
1478 .clkdm_name = "l4ls_clkdm", 1140 .clkdm_name = "l4ls_clkdm",
1479 .mpu_irqs = am33xx_mmc0_irqs,
1480 .sdma_reqs = am33xx_mmc0_edma_reqs,
1481 .main_clk = "mmc_clk", 1141 .main_clk = "mmc_clk",
1482 .prcm = { 1142 .prcm = {
1483 .omap4 = { 1143 .omap4 = {
@@ -1489,17 +1149,6 @@ static struct omap_hwmod am33xx_mmc0_hwmod = {
1489}; 1149};
1490 1150
1491/* mmc1 */ 1151/* mmc1 */
1492static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
1493 { .irq = 28 + OMAP_INTC_START, },
1494 { .irq = -1 },
1495};
1496
1497static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
1498 { .name = "tx", .dma_req = 2, },
1499 { .name = "rx", .dma_req = 3, },
1500 { .dma_req = -1 }
1501};
1502
1503static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = { 1152static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
1504 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, 1153 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1505}; 1154};
@@ -1508,8 +1157,6 @@ static struct omap_hwmod am33xx_mmc1_hwmod = {
1508 .name = "mmc2", 1157 .name = "mmc2",
1509 .class = &am33xx_mmc_hwmod_class, 1158 .class = &am33xx_mmc_hwmod_class,
1510 .clkdm_name = "l4ls_clkdm", 1159 .clkdm_name = "l4ls_clkdm",
1511 .mpu_irqs = am33xx_mmc1_irqs,
1512 .sdma_reqs = am33xx_mmc1_edma_reqs,
1513 .main_clk = "mmc_clk", 1160 .main_clk = "mmc_clk",
1514 .prcm = { 1161 .prcm = {
1515 .omap4 = { 1162 .omap4 = {
@@ -1521,17 +1168,6 @@ static struct omap_hwmod am33xx_mmc1_hwmod = {
1521}; 1168};
1522 1169
1523/* mmc2 */ 1170/* mmc2 */
1524static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
1525 { .irq = 29 + OMAP_INTC_START, },
1526 { .irq = -1 },
1527};
1528
1529static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
1530 { .name = "tx", .dma_req = 64, },
1531 { .name = "rx", .dma_req = 65, },
1532 { .dma_req = -1 }
1533};
1534
1535static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = { 1171static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
1536 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, 1172 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1537}; 1173};
@@ -1539,8 +1175,6 @@ static struct omap_hwmod am33xx_mmc2_hwmod = {
1539 .name = "mmc3", 1175 .name = "mmc3",
1540 .class = &am33xx_mmc_hwmod_class, 1176 .class = &am33xx_mmc_hwmod_class,
1541 .clkdm_name = "l3s_clkdm", 1177 .clkdm_name = "l3s_clkdm",
1542 .mpu_irqs = am33xx_mmc2_irqs,
1543 .sdma_reqs = am33xx_mmc2_edma_reqs,
1544 .main_clk = "mmc_clk", 1178 .main_clk = "mmc_clk",
1545 .prcm = { 1179 .prcm = {
1546 .omap4 = { 1180 .omap4 = {
@@ -1569,17 +1203,10 @@ static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
1569 .sysc = &am33xx_rtc_sysc, 1203 .sysc = &am33xx_rtc_sysc,
1570}; 1204};
1571 1205
1572static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
1573 { .name = "rtcint", .irq = 75 + OMAP_INTC_START, },
1574 { .name = "rtcalarmint", .irq = 76 + OMAP_INTC_START, },
1575 { .irq = -1 },
1576};
1577
1578static struct omap_hwmod am33xx_rtc_hwmod = { 1206static struct omap_hwmod am33xx_rtc_hwmod = {
1579 .name = "rtc", 1207 .name = "rtc",
1580 .class = &am33xx_rtc_hwmod_class, 1208 .class = &am33xx_rtc_hwmod_class,
1581 .clkdm_name = "l4_rtc_clkdm", 1209 .clkdm_name = "l4_rtc_clkdm",
1582 .mpu_irqs = am33xx_rtc_irqs,
1583 .main_clk = "clk_32768_ck", 1210 .main_clk = "clk_32768_ck",
1584 .prcm = { 1211 .prcm = {
1585 .omap4 = { 1212 .omap4 = {
@@ -1608,19 +1235,6 @@ static struct omap_hwmod_class am33xx_spi_hwmod_class = {
1608}; 1235};
1609 1236
1610/* spi0 */ 1237/* spi0 */
1611static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
1612 { .irq = 65 + OMAP_INTC_START, },
1613 { .irq = -1 },
1614};
1615
1616static struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = {
1617 { .name = "rx0", .dma_req = 17 },
1618 { .name = "tx0", .dma_req = 16 },
1619 { .name = "rx1", .dma_req = 19 },
1620 { .name = "tx1", .dma_req = 18 },
1621 { .dma_req = -1 }
1622};
1623
1624static struct omap2_mcspi_dev_attr mcspi_attrib = { 1238static struct omap2_mcspi_dev_attr mcspi_attrib = {
1625 .num_chipselect = 2, 1239 .num_chipselect = 2,
1626}; 1240};
@@ -1628,8 +1242,6 @@ static struct omap_hwmod am33xx_spi0_hwmod = {
1628 .name = "spi0", 1242 .name = "spi0",
1629 .class = &am33xx_spi_hwmod_class, 1243 .class = &am33xx_spi_hwmod_class,
1630 .clkdm_name = "l4ls_clkdm", 1244 .clkdm_name = "l4ls_clkdm",
1631 .mpu_irqs = am33xx_spi0_irqs,
1632 .sdma_reqs = am33xx_mcspi0_edma_reqs,
1633 .main_clk = "dpll_per_m2_div4_ck", 1245 .main_clk = "dpll_per_m2_div4_ck",
1634 .prcm = { 1246 .prcm = {
1635 .omap4 = { 1247 .omap4 = {
@@ -1641,25 +1253,10 @@ static struct omap_hwmod am33xx_spi0_hwmod = {
1641}; 1253};
1642 1254
1643/* spi1 */ 1255/* spi1 */
1644static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
1645 { .irq = 125 + OMAP_INTC_START, },
1646 { .irq = -1 },
1647};
1648
1649static struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = {
1650 { .name = "rx0", .dma_req = 43 },
1651 { .name = "tx0", .dma_req = 42 },
1652 { .name = "rx1", .dma_req = 45 },
1653 { .name = "tx1", .dma_req = 44 },
1654 { .dma_req = -1 }
1655};
1656
1657static struct omap_hwmod am33xx_spi1_hwmod = { 1256static struct omap_hwmod am33xx_spi1_hwmod = {
1658 .name = "spi1", 1257 .name = "spi1",
1659 .class = &am33xx_spi_hwmod_class, 1258 .class = &am33xx_spi_hwmod_class,
1660 .clkdm_name = "l4ls_clkdm", 1259 .clkdm_name = "l4ls_clkdm",
1661 .mpu_irqs = am33xx_spi1_irqs,
1662 .sdma_reqs = am33xx_mcspi1_edma_reqs,
1663 .main_clk = "dpll_per_m2_div4_ck", 1260 .main_clk = "dpll_per_m2_div4_ck",
1664 .prcm = { 1261 .prcm = {
1665 .omap4 = { 1262 .omap4 = {
@@ -1725,16 +1322,10 @@ static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
1725 .sysc = &am33xx_timer1ms_sysc, 1322 .sysc = &am33xx_timer1ms_sysc,
1726}; 1323};
1727 1324
1728static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
1729 { .irq = 67 + OMAP_INTC_START, },
1730 { .irq = -1 },
1731};
1732
1733static struct omap_hwmod am33xx_timer1_hwmod = { 1325static struct omap_hwmod am33xx_timer1_hwmod = {
1734 .name = "timer1", 1326 .name = "timer1",
1735 .class = &am33xx_timer1ms_hwmod_class, 1327 .class = &am33xx_timer1ms_hwmod_class,
1736 .clkdm_name = "l4_wkup_clkdm", 1328 .clkdm_name = "l4_wkup_clkdm",
1737 .mpu_irqs = am33xx_timer1_irqs,
1738 .main_clk = "timer1_fck", 1329 .main_clk = "timer1_fck",
1739 .prcm = { 1330 .prcm = {
1740 .omap4 = { 1331 .omap4 = {
@@ -1744,16 +1335,10 @@ static struct omap_hwmod am33xx_timer1_hwmod = {
1744 }, 1335 },
1745}; 1336};
1746 1337
1747static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
1748 { .irq = 68 + OMAP_INTC_START, },
1749 { .irq = -1 },
1750};
1751
1752static struct omap_hwmod am33xx_timer2_hwmod = { 1338static struct omap_hwmod am33xx_timer2_hwmod = {
1753 .name = "timer2", 1339 .name = "timer2",
1754 .class = &am33xx_timer_hwmod_class, 1340 .class = &am33xx_timer_hwmod_class,
1755 .clkdm_name = "l4ls_clkdm", 1341 .clkdm_name = "l4ls_clkdm",
1756 .mpu_irqs = am33xx_timer2_irqs,
1757 .main_clk = "timer2_fck", 1342 .main_clk = "timer2_fck",
1758 .prcm = { 1343 .prcm = {
1759 .omap4 = { 1344 .omap4 = {
@@ -1763,16 +1348,10 @@ static struct omap_hwmod am33xx_timer2_hwmod = {
1763 }, 1348 },
1764}; 1349};
1765 1350
1766static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
1767 { .irq = 69 + OMAP_INTC_START, },
1768 { .irq = -1 },
1769};
1770
1771static struct omap_hwmod am33xx_timer3_hwmod = { 1351static struct omap_hwmod am33xx_timer3_hwmod = {
1772 .name = "timer3", 1352 .name = "timer3",
1773 .class = &am33xx_timer_hwmod_class, 1353 .class = &am33xx_timer_hwmod_class,
1774 .clkdm_name = "l4ls_clkdm", 1354 .clkdm_name = "l4ls_clkdm",
1775 .mpu_irqs = am33xx_timer3_irqs,
1776 .main_clk = "timer3_fck", 1355 .main_clk = "timer3_fck",
1777 .prcm = { 1356 .prcm = {
1778 .omap4 = { 1357 .omap4 = {
@@ -1782,16 +1361,10 @@ static struct omap_hwmod am33xx_timer3_hwmod = {
1782 }, 1361 },
1783}; 1362};
1784 1363
1785static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
1786 { .irq = 92 + OMAP_INTC_START, },
1787 { .irq = -1 },
1788};
1789
1790static struct omap_hwmod am33xx_timer4_hwmod = { 1364static struct omap_hwmod am33xx_timer4_hwmod = {
1791 .name = "timer4", 1365 .name = "timer4",
1792 .class = &am33xx_timer_hwmod_class, 1366 .class = &am33xx_timer_hwmod_class,
1793 .clkdm_name = "l4ls_clkdm", 1367 .clkdm_name = "l4ls_clkdm",
1794 .mpu_irqs = am33xx_timer4_irqs,
1795 .main_clk = "timer4_fck", 1368 .main_clk = "timer4_fck",
1796 .prcm = { 1369 .prcm = {
1797 .omap4 = { 1370 .omap4 = {
@@ -1801,16 +1374,10 @@ static struct omap_hwmod am33xx_timer4_hwmod = {
1801 }, 1374 },
1802}; 1375};
1803 1376
1804static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
1805 { .irq = 93 + OMAP_INTC_START, },
1806 { .irq = -1 },
1807};
1808
1809static struct omap_hwmod am33xx_timer5_hwmod = { 1377static struct omap_hwmod am33xx_timer5_hwmod = {
1810 .name = "timer5", 1378 .name = "timer5",
1811 .class = &am33xx_timer_hwmod_class, 1379 .class = &am33xx_timer_hwmod_class,
1812 .clkdm_name = "l4ls_clkdm", 1380 .clkdm_name = "l4ls_clkdm",
1813 .mpu_irqs = am33xx_timer5_irqs,
1814 .main_clk = "timer5_fck", 1381 .main_clk = "timer5_fck",
1815 .prcm = { 1382 .prcm = {
1816 .omap4 = { 1383 .omap4 = {
@@ -1820,16 +1387,10 @@ static struct omap_hwmod am33xx_timer5_hwmod = {
1820 }, 1387 },
1821}; 1388};
1822 1389
1823static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
1824 { .irq = 94 + OMAP_INTC_START, },
1825 { .irq = -1 },
1826};
1827
1828static struct omap_hwmod am33xx_timer6_hwmod = { 1390static struct omap_hwmod am33xx_timer6_hwmod = {
1829 .name = "timer6", 1391 .name = "timer6",
1830 .class = &am33xx_timer_hwmod_class, 1392 .class = &am33xx_timer_hwmod_class,
1831 .clkdm_name = "l4ls_clkdm", 1393 .clkdm_name = "l4ls_clkdm",
1832 .mpu_irqs = am33xx_timer6_irqs,
1833 .main_clk = "timer6_fck", 1394 .main_clk = "timer6_fck",
1834 .prcm = { 1395 .prcm = {
1835 .omap4 = { 1396 .omap4 = {
@@ -1839,16 +1400,10 @@ static struct omap_hwmod am33xx_timer6_hwmod = {
1839 }, 1400 },
1840}; 1401};
1841 1402
1842static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
1843 { .irq = 95 + OMAP_INTC_START, },
1844 { .irq = -1 },
1845};
1846
1847static struct omap_hwmod am33xx_timer7_hwmod = { 1403static struct omap_hwmod am33xx_timer7_hwmod = {
1848 .name = "timer7", 1404 .name = "timer7",
1849 .class = &am33xx_timer_hwmod_class, 1405 .class = &am33xx_timer_hwmod_class,
1850 .clkdm_name = "l4ls_clkdm", 1406 .clkdm_name = "l4ls_clkdm",
1851 .mpu_irqs = am33xx_timer7_irqs,
1852 .main_clk = "timer7_fck", 1407 .main_clk = "timer7_fck",
1853 .prcm = { 1408 .prcm = {
1854 .omap4 = { 1409 .omap4 = {
@@ -1863,18 +1418,10 @@ static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1863 .name = "tpcc", 1418 .name = "tpcc",
1864}; 1419};
1865 1420
1866static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
1867 { .name = "edma0", .irq = 12 + OMAP_INTC_START, },
1868 { .name = "edma0_mperr", .irq = 13 + OMAP_INTC_START, },
1869 { .name = "edma0_err", .irq = 14 + OMAP_INTC_START, },
1870 { .irq = -1 },
1871};
1872
1873static struct omap_hwmod am33xx_tpcc_hwmod = { 1421static struct omap_hwmod am33xx_tpcc_hwmod = {
1874 .name = "tpcc", 1422 .name = "tpcc",
1875 .class = &am33xx_tpcc_hwmod_class, 1423 .class = &am33xx_tpcc_hwmod_class,
1876 .clkdm_name = "l3_clkdm", 1424 .clkdm_name = "l3_clkdm",
1877 .mpu_irqs = am33xx_tpcc_irqs,
1878 .main_clk = "l3_gclk", 1425 .main_clk = "l3_gclk",
1879 .prcm = { 1426 .prcm = {
1880 .omap4 = { 1427 .omap4 = {
@@ -1900,16 +1447,10 @@ static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
1900}; 1447};
1901 1448
1902/* tptc0 */ 1449/* tptc0 */
1903static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
1904 { .irq = 112 + OMAP_INTC_START, },
1905 { .irq = -1 },
1906};
1907
1908static struct omap_hwmod am33xx_tptc0_hwmod = { 1450static struct omap_hwmod am33xx_tptc0_hwmod = {
1909 .name = "tptc0", 1451 .name = "tptc0",
1910 .class = &am33xx_tptc_hwmod_class, 1452 .class = &am33xx_tptc_hwmod_class,
1911 .clkdm_name = "l3_clkdm", 1453 .clkdm_name = "l3_clkdm",
1912 .mpu_irqs = am33xx_tptc0_irqs,
1913 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, 1454 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1914 .main_clk = "l3_gclk", 1455 .main_clk = "l3_gclk",
1915 .prcm = { 1456 .prcm = {
@@ -1921,16 +1462,10 @@ static struct omap_hwmod am33xx_tptc0_hwmod = {
1921}; 1462};
1922 1463
1923/* tptc1 */ 1464/* tptc1 */
1924static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
1925 { .irq = 113 + OMAP_INTC_START, },
1926 { .irq = -1 },
1927};
1928
1929static struct omap_hwmod am33xx_tptc1_hwmod = { 1465static struct omap_hwmod am33xx_tptc1_hwmod = {
1930 .name = "tptc1", 1466 .name = "tptc1",
1931 .class = &am33xx_tptc_hwmod_class, 1467 .class = &am33xx_tptc_hwmod_class,
1932 .clkdm_name = "l3_clkdm", 1468 .clkdm_name = "l3_clkdm",
1933 .mpu_irqs = am33xx_tptc1_irqs,
1934 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), 1469 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1935 .main_clk = "l3_gclk", 1470 .main_clk = "l3_gclk",
1936 .prcm = { 1471 .prcm = {
@@ -1942,16 +1477,10 @@ static struct omap_hwmod am33xx_tptc1_hwmod = {
1942}; 1477};
1943 1478
1944/* tptc2 */ 1479/* tptc2 */
1945static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
1946 { .irq = 114 + OMAP_INTC_START, },
1947 { .irq = -1 },
1948};
1949
1950static struct omap_hwmod am33xx_tptc2_hwmod = { 1480static struct omap_hwmod am33xx_tptc2_hwmod = {
1951 .name = "tptc2", 1481 .name = "tptc2",
1952 .class = &am33xx_tptc_hwmod_class, 1482 .class = &am33xx_tptc_hwmod_class,
1953 .clkdm_name = "l3_clkdm", 1483 .clkdm_name = "l3_clkdm",
1954 .mpu_irqs = am33xx_tptc2_irqs,
1955 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), 1484 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1956 .main_clk = "l3_gclk", 1485 .main_clk = "l3_gclk",
1957 .prcm = { 1486 .prcm = {
@@ -1980,24 +1509,11 @@ static struct omap_hwmod_class uart_class = {
1980}; 1509};
1981 1510
1982/* uart1 */ 1511/* uart1 */
1983static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
1984 { .name = "tx", .dma_req = 26, },
1985 { .name = "rx", .dma_req = 27, },
1986 { .dma_req = -1 }
1987};
1988
1989static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
1990 { .irq = 72 + OMAP_INTC_START, },
1991 { .irq = -1 },
1992};
1993
1994static struct omap_hwmod am33xx_uart1_hwmod = { 1512static struct omap_hwmod am33xx_uart1_hwmod = {
1995 .name = "uart1", 1513 .name = "uart1",
1996 .class = &uart_class, 1514 .class = &uart_class,
1997 .clkdm_name = "l4_wkup_clkdm", 1515 .clkdm_name = "l4_wkup_clkdm",
1998 .flags = HWMOD_SWSUP_SIDLE_ACT, 1516 .flags = DEBUG_AM33XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
1999 .mpu_irqs = am33xx_uart1_irqs,
2000 .sdma_reqs = uart1_edma_reqs,
2001 .main_clk = "dpll_per_m2_div4_wkupdm_ck", 1517 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
2002 .prcm = { 1518 .prcm = {
2003 .omap4 = { 1519 .omap4 = {
@@ -2007,25 +1523,11 @@ static struct omap_hwmod am33xx_uart1_hwmod = {
2007 }, 1523 },
2008}; 1524};
2009 1525
2010/* uart2 */
2011static struct omap_hwmod_dma_info uart2_edma_reqs[] = {
2012 { .name = "tx", .dma_req = 28, },
2013 { .name = "rx", .dma_req = 29, },
2014 { .dma_req = -1 }
2015};
2016
2017static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
2018 { .irq = 73 + OMAP_INTC_START, },
2019 { .irq = -1 },
2020};
2021
2022static struct omap_hwmod am33xx_uart2_hwmod = { 1526static struct omap_hwmod am33xx_uart2_hwmod = {
2023 .name = "uart2", 1527 .name = "uart2",
2024 .class = &uart_class, 1528 .class = &uart_class,
2025 .clkdm_name = "l4ls_clkdm", 1529 .clkdm_name = "l4ls_clkdm",
2026 .flags = HWMOD_SWSUP_SIDLE_ACT, 1530 .flags = HWMOD_SWSUP_SIDLE_ACT,
2027 .mpu_irqs = am33xx_uart2_irqs,
2028 .sdma_reqs = uart2_edma_reqs,
2029 .main_clk = "dpll_per_m2_div4_ck", 1531 .main_clk = "dpll_per_m2_div4_ck",
2030 .prcm = { 1532 .prcm = {
2031 .omap4 = { 1533 .omap4 = {
@@ -2036,24 +1538,11 @@ static struct omap_hwmod am33xx_uart2_hwmod = {
2036}; 1538};
2037 1539
2038/* uart3 */ 1540/* uart3 */
2039static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
2040 { .name = "tx", .dma_req = 30, },
2041 { .name = "rx", .dma_req = 31, },
2042 { .dma_req = -1 }
2043};
2044
2045static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
2046 { .irq = 74 + OMAP_INTC_START, },
2047 { .irq = -1 },
2048};
2049
2050static struct omap_hwmod am33xx_uart3_hwmod = { 1541static struct omap_hwmod am33xx_uart3_hwmod = {
2051 .name = "uart3", 1542 .name = "uart3",
2052 .class = &uart_class, 1543 .class = &uart_class,
2053 .clkdm_name = "l4ls_clkdm", 1544 .clkdm_name = "l4ls_clkdm",
2054 .flags = HWMOD_SWSUP_SIDLE_ACT, 1545 .flags = HWMOD_SWSUP_SIDLE_ACT,
2055 .mpu_irqs = am33xx_uart3_irqs,
2056 .sdma_reqs = uart3_edma_reqs,
2057 .main_clk = "dpll_per_m2_div4_ck", 1546 .main_clk = "dpll_per_m2_div4_ck",
2058 .prcm = { 1547 .prcm = {
2059 .omap4 = { 1548 .omap4 = {
@@ -2063,18 +1552,11 @@ static struct omap_hwmod am33xx_uart3_hwmod = {
2063 }, 1552 },
2064}; 1553};
2065 1554
2066static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
2067 { .irq = 44 + OMAP_INTC_START, },
2068 { .irq = -1 },
2069};
2070
2071static struct omap_hwmod am33xx_uart4_hwmod = { 1555static struct omap_hwmod am33xx_uart4_hwmod = {
2072 .name = "uart4", 1556 .name = "uart4",
2073 .class = &uart_class, 1557 .class = &uart_class,
2074 .clkdm_name = "l4ls_clkdm", 1558 .clkdm_name = "l4ls_clkdm",
2075 .flags = HWMOD_SWSUP_SIDLE_ACT, 1559 .flags = HWMOD_SWSUP_SIDLE_ACT,
2076 .mpu_irqs = am33xx_uart4_irqs,
2077 .sdma_reqs = uart1_edma_reqs,
2078 .main_clk = "dpll_per_m2_div4_ck", 1560 .main_clk = "dpll_per_m2_div4_ck",
2079 .prcm = { 1561 .prcm = {
2080 .omap4 = { 1562 .omap4 = {
@@ -2084,18 +1566,11 @@ static struct omap_hwmod am33xx_uart4_hwmod = {
2084 }, 1566 },
2085}; 1567};
2086 1568
2087static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
2088 { .irq = 45 + OMAP_INTC_START, },
2089 { .irq = -1 },
2090};
2091
2092static struct omap_hwmod am33xx_uart5_hwmod = { 1569static struct omap_hwmod am33xx_uart5_hwmod = {
2093 .name = "uart5", 1570 .name = "uart5",
2094 .class = &uart_class, 1571 .class = &uart_class,
2095 .clkdm_name = "l4ls_clkdm", 1572 .clkdm_name = "l4ls_clkdm",
2096 .flags = HWMOD_SWSUP_SIDLE_ACT, 1573 .flags = HWMOD_SWSUP_SIDLE_ACT,
2097 .mpu_irqs = am33xx_uart5_irqs,
2098 .sdma_reqs = uart1_edma_reqs,
2099 .main_clk = "dpll_per_m2_div4_ck", 1574 .main_clk = "dpll_per_m2_div4_ck",
2100 .prcm = { 1575 .prcm = {
2101 .omap4 = { 1576 .omap4 = {
@@ -2105,18 +1580,11 @@ static struct omap_hwmod am33xx_uart5_hwmod = {
2105 }, 1580 },
2106}; 1581};
2107 1582
2108static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
2109 { .irq = 46 + OMAP_INTC_START, },
2110 { .irq = -1 },
2111};
2112
2113static struct omap_hwmod am33xx_uart6_hwmod = { 1583static struct omap_hwmod am33xx_uart6_hwmod = {
2114 .name = "uart6", 1584 .name = "uart6",
2115 .class = &uart_class, 1585 .class = &uart_class,
2116 .clkdm_name = "l4ls_clkdm", 1586 .clkdm_name = "l4ls_clkdm",
2117 .flags = HWMOD_SWSUP_SIDLE_ACT, 1587 .flags = HWMOD_SWSUP_SIDLE_ACT,
2118 .mpu_irqs = am33xx_uart6_irqs,
2119 .sdma_reqs = uart1_edma_reqs,
2120 .main_clk = "dpll_per_m2_div4_ck", 1588 .main_clk = "dpll_per_m2_div4_ck",
2121 .prcm = { 1589 .prcm = {
2122 .omap4 = { 1590 .omap4 = {
@@ -2180,18 +1648,10 @@ static struct omap_hwmod_class am33xx_usbotg_class = {
2180 .sysc = &am33xx_usbhsotg_sysc, 1648 .sysc = &am33xx_usbhsotg_sysc,
2181}; 1649};
2182 1650
2183static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
2184 { .name = "usbss-irq", .irq = 17 + OMAP_INTC_START, },
2185 { .name = "musb0-irq", .irq = 18 + OMAP_INTC_START, },
2186 { .name = "musb1-irq", .irq = 19 + OMAP_INTC_START, },
2187 { .irq = -1, },
2188};
2189
2190static struct omap_hwmod am33xx_usbss_hwmod = { 1651static struct omap_hwmod am33xx_usbss_hwmod = {
2191 .name = "usb_otg_hs", 1652 .name = "usb_otg_hs",
2192 .class = &am33xx_usbotg_class, 1653 .class = &am33xx_usbotg_class,
2193 .clkdm_name = "l3s_clkdm", 1654 .clkdm_name = "l3s_clkdm",
2194 .mpu_irqs = am33xx_usbss_mpu_irqs,
2195 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, 1655 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2196 .main_clk = "usbotg_fck", 1656 .main_clk = "usbotg_fck",
2197 .prcm = { 1657 .prcm = {
@@ -2207,14 +1667,6 @@ static struct omap_hwmod am33xx_usbss_hwmod = {
2207 * Interfaces 1667 * Interfaces
2208 */ 1668 */
2209 1669
2210/* l4 fw -> emif fw */
2211static struct omap_hwmod_ocp_if am33xx_l4_fw__emif_fw = {
2212 .master = &am33xx_l4_fw_hwmod,
2213 .slave = &am33xx_emif_fw_hwmod,
2214 .clk = "l4fw_gclk",
2215 .user = OCP_USER_MPU,
2216};
2217
2218static struct omap_hwmod_addr_space am33xx_emif_addrs[] = { 1670static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
2219 { 1671 {
2220 .pa_start = 0x4c000000, 1672 .pa_start = 0x4c000000,
@@ -2272,14 +1724,6 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
2272 .user = OCP_USER_MPU | OCP_USER_SDMA, 1724 .user = OCP_USER_MPU | OCP_USER_SDMA,
2273}; 1725};
2274 1726
2275/* l3 s -> l4 fw */
2276static struct omap_hwmod_ocp_if am33xx_l3_s__l4_fw = {
2277 .master = &am33xx_l3_s_hwmod,
2278 .slave = &am33xx_l4_fw_hwmod,
2279 .clk = "l3s_gclk",
2280 .user = OCP_USER_MPU | OCP_USER_SDMA,
2281};
2282
2283/* l3 main -> l3 instr */ 1727/* l3 main -> l3 instr */
2284static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = { 1728static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
2285 .master = &am33xx_l3_main_hwmod, 1729 .master = &am33xx_l3_main_hwmod,
@@ -2329,261 +1773,114 @@ static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
2329}; 1773};
2330 1774
2331/* l4 wkup -> wkup m3 */ 1775/* l4 wkup -> wkup m3 */
2332static struct omap_hwmod_addr_space am33xx_wkup_m3_addrs[] = {
2333 {
2334 .name = "umem",
2335 .pa_start = 0x44d00000,
2336 .pa_end = 0x44d00000 + SZ_16K - 1,
2337 .flags = ADDR_TYPE_RT
2338 },
2339 {
2340 .name = "dmem",
2341 .pa_start = 0x44d80000,
2342 .pa_end = 0x44d80000 + SZ_8K - 1,
2343 .flags = ADDR_TYPE_RT
2344 },
2345 { }
2346};
2347
2348static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = { 1776static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
2349 .master = &am33xx_l4_wkup_hwmod, 1777 .master = &am33xx_l4_wkup_hwmod,
2350 .slave = &am33xx_wkup_m3_hwmod, 1778 .slave = &am33xx_wkup_m3_hwmod,
2351 .clk = "dpll_core_m4_div2_ck", 1779 .clk = "dpll_core_m4_div2_ck",
2352 .addr = am33xx_wkup_m3_addrs,
2353 .user = OCP_USER_MPU | OCP_USER_SDMA, 1780 .user = OCP_USER_MPU | OCP_USER_SDMA,
2354}; 1781};
2355 1782
2356/* l4 hs -> pru-icss */ 1783/* l4 hs -> pru-icss */
2357static struct omap_hwmod_addr_space am33xx_pruss_addrs[] = {
2358 {
2359 .pa_start = 0x4a300000,
2360 .pa_end = 0x4a300000 + SZ_512K - 1,
2361 .flags = ADDR_TYPE_RT
2362 },
2363 { }
2364};
2365
2366static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = { 1784static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
2367 .master = &am33xx_l4_hs_hwmod, 1785 .master = &am33xx_l4_hs_hwmod,
2368 .slave = &am33xx_pruss_hwmod, 1786 .slave = &am33xx_pruss_hwmod,
2369 .clk = "dpll_core_m4_ck", 1787 .clk = "dpll_core_m4_ck",
2370 .addr = am33xx_pruss_addrs,
2371 .user = OCP_USER_MPU | OCP_USER_SDMA, 1788 .user = OCP_USER_MPU | OCP_USER_SDMA,
2372}; 1789};
2373 1790
2374/* l3 main -> gfx */ 1791/* l3 main -> gfx */
2375static struct omap_hwmod_addr_space am33xx_gfx_addrs[] = {
2376 {
2377 .pa_start = 0x56000000,
2378 .pa_end = 0x56000000 + SZ_16M - 1,
2379 .flags = ADDR_TYPE_RT
2380 },
2381 { }
2382};
2383
2384static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = { 1792static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
2385 .master = &am33xx_l3_main_hwmod, 1793 .master = &am33xx_l3_main_hwmod,
2386 .slave = &am33xx_gfx_hwmod, 1794 .slave = &am33xx_gfx_hwmod,
2387 .clk = "dpll_core_m4_ck", 1795 .clk = "dpll_core_m4_ck",
2388 .addr = am33xx_gfx_addrs,
2389 .user = OCP_USER_MPU | OCP_USER_SDMA, 1796 .user = OCP_USER_MPU | OCP_USER_SDMA,
2390}; 1797};
2391 1798
2392/* l4 wkup -> smartreflex0 */ 1799/* l4 wkup -> smartreflex0 */
2393static struct omap_hwmod_addr_space am33xx_smartreflex0_addrs[] = {
2394 {
2395 .pa_start = 0x44e37000,
2396 .pa_end = 0x44e37000 + SZ_4K - 1,
2397 .flags = ADDR_TYPE_RT
2398 },
2399 { }
2400};
2401
2402static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = { 1800static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
2403 .master = &am33xx_l4_wkup_hwmod, 1801 .master = &am33xx_l4_wkup_hwmod,
2404 .slave = &am33xx_smartreflex0_hwmod, 1802 .slave = &am33xx_smartreflex0_hwmod,
2405 .clk = "dpll_core_m4_div2_ck", 1803 .clk = "dpll_core_m4_div2_ck",
2406 .addr = am33xx_smartreflex0_addrs,
2407 .user = OCP_USER_MPU, 1804 .user = OCP_USER_MPU,
2408}; 1805};
2409 1806
2410/* l4 wkup -> smartreflex1 */ 1807/* l4 wkup -> smartreflex1 */
2411static struct omap_hwmod_addr_space am33xx_smartreflex1_addrs[] = {
2412 {
2413 .pa_start = 0x44e39000,
2414 .pa_end = 0x44e39000 + SZ_4K - 1,
2415 .flags = ADDR_TYPE_RT
2416 },
2417 { }
2418};
2419
2420static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = { 1808static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
2421 .master = &am33xx_l4_wkup_hwmod, 1809 .master = &am33xx_l4_wkup_hwmod,
2422 .slave = &am33xx_smartreflex1_hwmod, 1810 .slave = &am33xx_smartreflex1_hwmod,
2423 .clk = "dpll_core_m4_div2_ck", 1811 .clk = "dpll_core_m4_div2_ck",
2424 .addr = am33xx_smartreflex1_addrs,
2425 .user = OCP_USER_MPU, 1812 .user = OCP_USER_MPU,
2426}; 1813};
2427 1814
2428/* l4 wkup -> control */ 1815/* l4 wkup -> control */
2429static struct omap_hwmod_addr_space am33xx_control_addrs[] = {
2430 {
2431 .pa_start = 0x44e10000,
2432 .pa_end = 0x44e10000 + SZ_8K - 1,
2433 .flags = ADDR_TYPE_RT
2434 },
2435 { }
2436};
2437
2438static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = { 1816static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
2439 .master = &am33xx_l4_wkup_hwmod, 1817 .master = &am33xx_l4_wkup_hwmod,
2440 .slave = &am33xx_control_hwmod, 1818 .slave = &am33xx_control_hwmod,
2441 .clk = "dpll_core_m4_div2_ck", 1819 .clk = "dpll_core_m4_div2_ck",
2442 .addr = am33xx_control_addrs,
2443 .user = OCP_USER_MPU, 1820 .user = OCP_USER_MPU,
2444}; 1821};
2445 1822
2446/* l4 wkup -> rtc */ 1823/* l4 wkup -> rtc */
2447static struct omap_hwmod_addr_space am33xx_rtc_addrs[] = {
2448 {
2449 .pa_start = 0x44e3e000,
2450 .pa_end = 0x44e3e000 + SZ_4K - 1,
2451 .flags = ADDR_TYPE_RT
2452 },
2453 { }
2454};
2455
2456static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = { 1824static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
2457 .master = &am33xx_l4_wkup_hwmod, 1825 .master = &am33xx_l4_wkup_hwmod,
2458 .slave = &am33xx_rtc_hwmod, 1826 .slave = &am33xx_rtc_hwmod,
2459 .clk = "clkdiv32k_ick", 1827 .clk = "clkdiv32k_ick",
2460 .addr = am33xx_rtc_addrs,
2461 .user = OCP_USER_MPU, 1828 .user = OCP_USER_MPU,
2462}; 1829};
2463 1830
2464/* l4 per/ls -> DCAN0 */ 1831/* l4 per/ls -> DCAN0 */
2465static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = {
2466 {
2467 .pa_start = 0x481CC000,
2468 .pa_end = 0x481CC000 + SZ_4K - 1,
2469 .flags = ADDR_TYPE_RT
2470 },
2471 { }
2472};
2473
2474static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = { 1832static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
2475 .master = &am33xx_l4_ls_hwmod, 1833 .master = &am33xx_l4_ls_hwmod,
2476 .slave = &am33xx_dcan0_hwmod, 1834 .slave = &am33xx_dcan0_hwmod,
2477 .clk = "l4ls_gclk", 1835 .clk = "l4ls_gclk",
2478 .addr = am33xx_dcan0_addrs,
2479 .user = OCP_USER_MPU | OCP_USER_SDMA, 1836 .user = OCP_USER_MPU | OCP_USER_SDMA,
2480}; 1837};
2481 1838
2482/* l4 per/ls -> DCAN1 */ 1839/* l4 per/ls -> DCAN1 */
2483static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = {
2484 {
2485 .pa_start = 0x481D0000,
2486 .pa_end = 0x481D0000 + SZ_4K - 1,
2487 .flags = ADDR_TYPE_RT
2488 },
2489 { }
2490};
2491
2492static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = { 1840static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
2493 .master = &am33xx_l4_ls_hwmod, 1841 .master = &am33xx_l4_ls_hwmod,
2494 .slave = &am33xx_dcan1_hwmod, 1842 .slave = &am33xx_dcan1_hwmod,
2495 .clk = "l4ls_gclk", 1843 .clk = "l4ls_gclk",
2496 .addr = am33xx_dcan1_addrs,
2497 .user = OCP_USER_MPU | OCP_USER_SDMA, 1844 .user = OCP_USER_MPU | OCP_USER_SDMA,
2498}; 1845};
2499 1846
2500/* l4 per/ls -> GPIO2 */ 1847/* l4 per/ls -> GPIO2 */
2501static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
2502 {
2503 .pa_start = 0x4804C000,
2504 .pa_end = 0x4804C000 + SZ_4K - 1,
2505 .flags = ADDR_TYPE_RT,
2506 },
2507 { }
2508};
2509
2510static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = { 1848static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
2511 .master = &am33xx_l4_ls_hwmod, 1849 .master = &am33xx_l4_ls_hwmod,
2512 .slave = &am33xx_gpio1_hwmod, 1850 .slave = &am33xx_gpio1_hwmod,
2513 .clk = "l4ls_gclk", 1851 .clk = "l4ls_gclk",
2514 .addr = am33xx_gpio1_addrs,
2515 .user = OCP_USER_MPU | OCP_USER_SDMA, 1852 .user = OCP_USER_MPU | OCP_USER_SDMA,
2516}; 1853};
2517 1854
2518/* l4 per/ls -> gpio3 */ 1855/* l4 per/ls -> gpio3 */
2519static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
2520 {
2521 .pa_start = 0x481AC000,
2522 .pa_end = 0x481AC000 + SZ_4K - 1,
2523 .flags = ADDR_TYPE_RT,
2524 },
2525 { }
2526};
2527
2528static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = { 1856static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
2529 .master = &am33xx_l4_ls_hwmod, 1857 .master = &am33xx_l4_ls_hwmod,
2530 .slave = &am33xx_gpio2_hwmod, 1858 .slave = &am33xx_gpio2_hwmod,
2531 .clk = "l4ls_gclk", 1859 .clk = "l4ls_gclk",
2532 .addr = am33xx_gpio2_addrs,
2533 .user = OCP_USER_MPU | OCP_USER_SDMA, 1860 .user = OCP_USER_MPU | OCP_USER_SDMA,
2534}; 1861};
2535 1862
2536/* l4 per/ls -> gpio4 */ 1863/* l4 per/ls -> gpio4 */
2537static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
2538 {
2539 .pa_start = 0x481AE000,
2540 .pa_end = 0x481AE000 + SZ_4K - 1,
2541 .flags = ADDR_TYPE_RT,
2542 },
2543 { }
2544};
2545
2546static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = { 1864static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
2547 .master = &am33xx_l4_ls_hwmod, 1865 .master = &am33xx_l4_ls_hwmod,
2548 .slave = &am33xx_gpio3_hwmod, 1866 .slave = &am33xx_gpio3_hwmod,
2549 .clk = "l4ls_gclk", 1867 .clk = "l4ls_gclk",
2550 .addr = am33xx_gpio3_addrs,
2551 .user = OCP_USER_MPU | OCP_USER_SDMA, 1868 .user = OCP_USER_MPU | OCP_USER_SDMA,
2552}; 1869};
2553 1870
2554/* L4 WKUP -> I2C1 */ 1871/* L4 WKUP -> I2C1 */
2555static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
2556 {
2557 .pa_start = 0x44E0B000,
2558 .pa_end = 0x44E0B000 + SZ_4K - 1,
2559 .flags = ADDR_TYPE_RT,
2560 },
2561 { }
2562};
2563
2564static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = { 1872static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
2565 .master = &am33xx_l4_wkup_hwmod, 1873 .master = &am33xx_l4_wkup_hwmod,
2566 .slave = &am33xx_i2c1_hwmod, 1874 .slave = &am33xx_i2c1_hwmod,
2567 .clk = "dpll_core_m4_div2_ck", 1875 .clk = "dpll_core_m4_div2_ck",
2568 .addr = am33xx_i2c1_addr_space,
2569 .user = OCP_USER_MPU, 1876 .user = OCP_USER_MPU,
2570}; 1877};
2571 1878
2572/* L4 WKUP -> GPIO1 */ 1879/* L4 WKUP -> GPIO1 */
2573static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
2574 {
2575 .pa_start = 0x44E07000,
2576 .pa_end = 0x44E07000 + SZ_4K - 1,
2577 .flags = ADDR_TYPE_RT,
2578 },
2579 { }
2580};
2581
2582static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = { 1880static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
2583 .master = &am33xx_l4_wkup_hwmod, 1881 .master = &am33xx_l4_wkup_hwmod,
2584 .slave = &am33xx_gpio0_hwmod, 1882 .slave = &am33xx_gpio0_hwmod,
2585 .clk = "dpll_core_m4_div2_ck", 1883 .clk = "dpll_core_m4_div2_ck",
2586 .addr = am33xx_gpio0_addrs,
2587 .user = OCP_USER_MPU | OCP_USER_SDMA, 1884 .user = OCP_USER_MPU | OCP_USER_SDMA,
2588}; 1885};
2589 1886
@@ -2605,41 +1902,16 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
2605 .user = OCP_USER_MPU, 1902 .user = OCP_USER_MPU,
2606}; 1903};
2607 1904
2608static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
2609 /* cpsw ss */
2610 {
2611 .pa_start = 0x4a100000,
2612 .pa_end = 0x4a100000 + SZ_2K - 1,
2613 },
2614 /* cpsw wr */
2615 {
2616 .pa_start = 0x4a101200,
2617 .pa_end = 0x4a101200 + SZ_256 - 1,
2618 .flags = ADDR_TYPE_RT,
2619 },
2620 { }
2621};
2622
2623static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = { 1905static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
2624 .master = &am33xx_l4_hs_hwmod, 1906 .master = &am33xx_l4_hs_hwmod,
2625 .slave = &am33xx_cpgmac0_hwmod, 1907 .slave = &am33xx_cpgmac0_hwmod,
2626 .clk = "cpsw_125mhz_gclk", 1908 .clk = "cpsw_125mhz_gclk",
2627 .addr = am33xx_cpgmac0_addr_space,
2628 .user = OCP_USER_MPU, 1909 .user = OCP_USER_MPU,
2629}; 1910};
2630 1911
2631static struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
2632 {
2633 .pa_start = 0x4A101000,
2634 .pa_end = 0x4A101000 + SZ_256 - 1,
2635 },
2636 { }
2637};
2638
2639static struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = { 1912static struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
2640 .master = &am33xx_cpgmac0_hwmod, 1913 .master = &am33xx_cpgmac0_hwmod,
2641 .slave = &am33xx_mdio_hwmod, 1914 .slave = &am33xx_mdio_hwmod,
2642 .addr = am33xx_mdio_addr_space,
2643 .user = OCP_USER_MPU, 1915 .user = OCP_USER_MPU,
2644}; 1916};
2645 1917
@@ -2677,51 +1949,24 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = {
2677 .user = OCP_USER_MPU, 1949 .user = OCP_USER_MPU,
2678}; 1950};
2679 1951
2680static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
2681 {
2682 .pa_start = 0x48300100,
2683 .pa_end = 0x48300100 + SZ_128 - 1,
2684 },
2685 { }
2686};
2687
2688static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = { 1952static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = {
2689 .master = &am33xx_epwmss0_hwmod, 1953 .master = &am33xx_epwmss0_hwmod,
2690 .slave = &am33xx_ecap0_hwmod, 1954 .slave = &am33xx_ecap0_hwmod,
2691 .clk = "l4ls_gclk", 1955 .clk = "l4ls_gclk",
2692 .addr = am33xx_ecap0_addr_space,
2693 .user = OCP_USER_MPU, 1956 .user = OCP_USER_MPU,
2694}; 1957};
2695 1958
2696static struct omap_hwmod_addr_space am33xx_eqep0_addr_space[] = {
2697 {
2698 .pa_start = 0x48300180,
2699 .pa_end = 0x48300180 + SZ_128 - 1,
2700 },
2701 { }
2702};
2703
2704static struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = { 1959static struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = {
2705 .master = &am33xx_epwmss0_hwmod, 1960 .master = &am33xx_epwmss0_hwmod,
2706 .slave = &am33xx_eqep0_hwmod, 1961 .slave = &am33xx_eqep0_hwmod,
2707 .clk = "l4ls_gclk", 1962 .clk = "l4ls_gclk",
2708 .addr = am33xx_eqep0_addr_space,
2709 .user = OCP_USER_MPU, 1963 .user = OCP_USER_MPU,
2710}; 1964};
2711 1965
2712static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
2713 {
2714 .pa_start = 0x48300200,
2715 .pa_end = 0x48300200 + SZ_128 - 1,
2716 },
2717 { }
2718};
2719
2720static struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = { 1966static struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = {
2721 .master = &am33xx_epwmss0_hwmod, 1967 .master = &am33xx_epwmss0_hwmod,
2722 .slave = &am33xx_ehrpwm0_hwmod, 1968 .slave = &am33xx_ehrpwm0_hwmod,
2723 .clk = "l4ls_gclk", 1969 .clk = "l4ls_gclk",
2724 .addr = am33xx_ehrpwm0_addr_space,
2725 .user = OCP_USER_MPU, 1970 .user = OCP_USER_MPU,
2726}; 1971};
2727 1972
@@ -2743,51 +1988,24 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = {
2743 .user = OCP_USER_MPU, 1988 .user = OCP_USER_MPU,
2744}; 1989};
2745 1990
2746static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
2747 {
2748 .pa_start = 0x48302100,
2749 .pa_end = 0x48302100 + SZ_128 - 1,
2750 },
2751 { }
2752};
2753
2754static struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = { 1991static struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = {
2755 .master = &am33xx_epwmss1_hwmod, 1992 .master = &am33xx_epwmss1_hwmod,
2756 .slave = &am33xx_ecap1_hwmod, 1993 .slave = &am33xx_ecap1_hwmod,
2757 .clk = "l4ls_gclk", 1994 .clk = "l4ls_gclk",
2758 .addr = am33xx_ecap1_addr_space,
2759 .user = OCP_USER_MPU, 1995 .user = OCP_USER_MPU,
2760}; 1996};
2761 1997
2762static struct omap_hwmod_addr_space am33xx_eqep1_addr_space[] = {
2763 {
2764 .pa_start = 0x48302180,
2765 .pa_end = 0x48302180 + SZ_128 - 1,
2766 },
2767 { }
2768};
2769
2770static struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = { 1998static struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = {
2771 .master = &am33xx_epwmss1_hwmod, 1999 .master = &am33xx_epwmss1_hwmod,
2772 .slave = &am33xx_eqep1_hwmod, 2000 .slave = &am33xx_eqep1_hwmod,
2773 .clk = "l4ls_gclk", 2001 .clk = "l4ls_gclk",
2774 .addr = am33xx_eqep1_addr_space,
2775 .user = OCP_USER_MPU, 2002 .user = OCP_USER_MPU,
2776}; 2003};
2777 2004
2778static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
2779 {
2780 .pa_start = 0x48302200,
2781 .pa_end = 0x48302200 + SZ_128 - 1,
2782 },
2783 { }
2784};
2785
2786static struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = { 2005static struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = {
2787 .master = &am33xx_epwmss1_hwmod, 2006 .master = &am33xx_epwmss1_hwmod,
2788 .slave = &am33xx_ehrpwm1_hwmod, 2007 .slave = &am33xx_ehrpwm1_hwmod,
2789 .clk = "l4ls_gclk", 2008 .clk = "l4ls_gclk",
2790 .addr = am33xx_ehrpwm1_addr_space,
2791 .user = OCP_USER_MPU, 2009 .user = OCP_USER_MPU,
2792}; 2010};
2793 2011
@@ -2808,51 +2026,24 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = {
2808 .user = OCP_USER_MPU, 2026 .user = OCP_USER_MPU,
2809}; 2027};
2810 2028
2811static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
2812 {
2813 .pa_start = 0x48304100,
2814 .pa_end = 0x48304100 + SZ_128 - 1,
2815 },
2816 { }
2817};
2818
2819static struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = { 2029static struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = {
2820 .master = &am33xx_epwmss2_hwmod, 2030 .master = &am33xx_epwmss2_hwmod,
2821 .slave = &am33xx_ecap2_hwmod, 2031 .slave = &am33xx_ecap2_hwmod,
2822 .clk = "l4ls_gclk", 2032 .clk = "l4ls_gclk",
2823 .addr = am33xx_ecap2_addr_space,
2824 .user = OCP_USER_MPU, 2033 .user = OCP_USER_MPU,
2825}; 2034};
2826 2035
2827static struct omap_hwmod_addr_space am33xx_eqep2_addr_space[] = {
2828 {
2829 .pa_start = 0x48304180,
2830 .pa_end = 0x48304180 + SZ_128 - 1,
2831 },
2832 { }
2833};
2834
2835static struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = { 2036static struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = {
2836 .master = &am33xx_epwmss2_hwmod, 2037 .master = &am33xx_epwmss2_hwmod,
2837 .slave = &am33xx_eqep2_hwmod, 2038 .slave = &am33xx_eqep2_hwmod,
2838 .clk = "l4ls_gclk", 2039 .clk = "l4ls_gclk",
2839 .addr = am33xx_eqep2_addr_space,
2840 .user = OCP_USER_MPU, 2040 .user = OCP_USER_MPU,
2841}; 2041};
2842 2042
2843static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
2844 {
2845 .pa_start = 0x48304200,
2846 .pa_end = 0x48304200 + SZ_128 - 1,
2847 },
2848 { }
2849};
2850
2851static struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = { 2043static struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = {
2852 .master = &am33xx_epwmss2_hwmod, 2044 .master = &am33xx_epwmss2_hwmod,
2853 .slave = &am33xx_ehrpwm2_hwmod, 2045 .slave = &am33xx_ehrpwm2_hwmod,
2854 .clk = "l4ls_gclk", 2046 .clk = "l4ls_gclk",
2855 .addr = am33xx_ehrpwm2_addr_space,
2856 .user = OCP_USER_MPU, 2047 .user = OCP_USER_MPU,
2857}; 2048};
2858 2049
@@ -2875,37 +2066,17 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
2875}; 2066};
2876 2067
2877/* i2c2 */ 2068/* i2c2 */
2878static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
2879 {
2880 .pa_start = 0x4802A000,
2881 .pa_end = 0x4802A000 + SZ_4K - 1,
2882 .flags = ADDR_TYPE_RT,
2883 },
2884 { }
2885};
2886
2887static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = { 2069static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
2888 .master = &am33xx_l4_ls_hwmod, 2070 .master = &am33xx_l4_ls_hwmod,
2889 .slave = &am33xx_i2c2_hwmod, 2071 .slave = &am33xx_i2c2_hwmod,
2890 .clk = "l4ls_gclk", 2072 .clk = "l4ls_gclk",
2891 .addr = am33xx_i2c2_addr_space,
2892 .user = OCP_USER_MPU, 2073 .user = OCP_USER_MPU,
2893}; 2074};
2894 2075
2895static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
2896 {
2897 .pa_start = 0x4819C000,
2898 .pa_end = 0x4819C000 + SZ_4K - 1,
2899 .flags = ADDR_TYPE_RT
2900 },
2901 { }
2902};
2903
2904static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = { 2076static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
2905 .master = &am33xx_l4_ls_hwmod, 2077 .master = &am33xx_l4_ls_hwmod,
2906 .slave = &am33xx_i2c3_hwmod, 2078 .slave = &am33xx_i2c3_hwmod,
2907 .clk = "l4ls_gclk", 2079 .clk = "l4ls_gclk",
2908 .addr = am33xx_i2c3_addr_space,
2909 .user = OCP_USER_MPU, 2080 .user = OCP_USER_MPU,
2910}; 2081};
2911 2082
@@ -2945,20 +2116,10 @@ static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
2945}; 2116};
2946 2117
2947/* l4 ls -> spinlock */ 2118/* l4 ls -> spinlock */
2948static struct omap_hwmod_addr_space am33xx_spinlock_addrs[] = {
2949 {
2950 .pa_start = 0x480Ca000,
2951 .pa_end = 0x480Ca000 + SZ_4K - 1,
2952 .flags = ADDR_TYPE_RT
2953 },
2954 { }
2955};
2956
2957static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = { 2119static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
2958 .master = &am33xx_l4_ls_hwmod, 2120 .master = &am33xx_l4_ls_hwmod,
2959 .slave = &am33xx_spinlock_hwmod, 2121 .slave = &am33xx_spinlock_hwmod,
2960 .clk = "l4ls_gclk", 2122 .clk = "l4ls_gclk",
2961 .addr = am33xx_spinlock_addrs,
2962 .user = OCP_USER_MPU, 2123 .user = OCP_USER_MPU,
2963}; 2124};
2964 2125
@@ -2980,24 +2141,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
2980 .user = OCP_USER_MPU, 2141 .user = OCP_USER_MPU,
2981}; 2142};
2982 2143
2983/* l3 s -> mcasp0 data */
2984static struct omap_hwmod_addr_space am33xx_mcasp0_data_addr_space[] = {
2985 {
2986 .pa_start = 0x46000000,
2987 .pa_end = 0x46000000 + SZ_4M - 1,
2988 .flags = ADDR_TYPE_RT
2989 },
2990 { }
2991};
2992
2993static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp0_data = {
2994 .master = &am33xx_l3_s_hwmod,
2995 .slave = &am33xx_mcasp0_hwmod,
2996 .clk = "l3s_gclk",
2997 .addr = am33xx_mcasp0_data_addr_space,
2998 .user = OCP_USER_SDMA,
2999};
3000
3001/* l4 ls -> mcasp1 */ 2144/* l4 ls -> mcasp1 */
3002static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = { 2145static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
3003 { 2146 {
@@ -3016,24 +2159,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
3016 .user = OCP_USER_MPU, 2159 .user = OCP_USER_MPU,
3017}; 2160};
3018 2161
3019/* l3 s -> mcasp1 data */
3020static struct omap_hwmod_addr_space am33xx_mcasp1_data_addr_space[] = {
3021 {
3022 .pa_start = 0x46400000,
3023 .pa_end = 0x46400000 + SZ_4M - 1,
3024 .flags = ADDR_TYPE_RT
3025 },
3026 { }
3027};
3028
3029static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp1_data = {
3030 .master = &am33xx_l3_s_hwmod,
3031 .slave = &am33xx_mcasp1_hwmod,
3032 .clk = "l3s_gclk",
3033 .addr = am33xx_mcasp1_data_addr_space,
3034 .user = OCP_USER_SDMA,
3035};
3036
3037/* l4 ls -> mmc0 */ 2162/* l4 ls -> mmc0 */
3038static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = { 2163static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
3039 { 2164 {
@@ -3089,182 +2214,82 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
3089}; 2214};
3090 2215
3091/* l4 ls -> mcspi0 */ 2216/* l4 ls -> mcspi0 */
3092static struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
3093 {
3094 .pa_start = 0x48030000,
3095 .pa_end = 0x48030000 + SZ_1K - 1,
3096 .flags = ADDR_TYPE_RT,
3097 },
3098 { }
3099};
3100
3101static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = { 2217static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
3102 .master = &am33xx_l4_ls_hwmod, 2218 .master = &am33xx_l4_ls_hwmod,
3103 .slave = &am33xx_spi0_hwmod, 2219 .slave = &am33xx_spi0_hwmod,
3104 .clk = "l4ls_gclk", 2220 .clk = "l4ls_gclk",
3105 .addr = am33xx_mcspi0_addr_space,
3106 .user = OCP_USER_MPU, 2221 .user = OCP_USER_MPU,
3107}; 2222};
3108 2223
3109/* l4 ls -> mcspi1 */ 2224/* l4 ls -> mcspi1 */
3110static struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
3111 {
3112 .pa_start = 0x481A0000,
3113 .pa_end = 0x481A0000 + SZ_1K - 1,
3114 .flags = ADDR_TYPE_RT,
3115 },
3116 { }
3117};
3118
3119static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = { 2225static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
3120 .master = &am33xx_l4_ls_hwmod, 2226 .master = &am33xx_l4_ls_hwmod,
3121 .slave = &am33xx_spi1_hwmod, 2227 .slave = &am33xx_spi1_hwmod,
3122 .clk = "l4ls_gclk", 2228 .clk = "l4ls_gclk",
3123 .addr = am33xx_mcspi1_addr_space,
3124 .user = OCP_USER_MPU, 2229 .user = OCP_USER_MPU,
3125}; 2230};
3126 2231
3127/* l4 wkup -> timer1 */ 2232/* l4 wkup -> timer1 */
3128static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
3129 {
3130 .pa_start = 0x44E31000,
3131 .pa_end = 0x44E31000 + SZ_1K - 1,
3132 .flags = ADDR_TYPE_RT
3133 },
3134 { }
3135};
3136
3137static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = { 2233static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
3138 .master = &am33xx_l4_wkup_hwmod, 2234 .master = &am33xx_l4_wkup_hwmod,
3139 .slave = &am33xx_timer1_hwmod, 2235 .slave = &am33xx_timer1_hwmod,
3140 .clk = "dpll_core_m4_div2_ck", 2236 .clk = "dpll_core_m4_div2_ck",
3141 .addr = am33xx_timer1_addr_space,
3142 .user = OCP_USER_MPU, 2237 .user = OCP_USER_MPU,
3143}; 2238};
3144 2239
3145/* l4 per -> timer2 */ 2240/* l4 per -> timer2 */
3146static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
3147 {
3148 .pa_start = 0x48040000,
3149 .pa_end = 0x48040000 + SZ_1K - 1,
3150 .flags = ADDR_TYPE_RT
3151 },
3152 { }
3153};
3154
3155static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = { 2241static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
3156 .master = &am33xx_l4_ls_hwmod, 2242 .master = &am33xx_l4_ls_hwmod,
3157 .slave = &am33xx_timer2_hwmod, 2243 .slave = &am33xx_timer2_hwmod,
3158 .clk = "l4ls_gclk", 2244 .clk = "l4ls_gclk",
3159 .addr = am33xx_timer2_addr_space,
3160 .user = OCP_USER_MPU, 2245 .user = OCP_USER_MPU,
3161}; 2246};
3162 2247
3163/* l4 per -> timer3 */ 2248/* l4 per -> timer3 */
3164static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
3165 {
3166 .pa_start = 0x48042000,
3167 .pa_end = 0x48042000 + SZ_1K - 1,
3168 .flags = ADDR_TYPE_RT
3169 },
3170 { }
3171};
3172
3173static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = { 2249static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
3174 .master = &am33xx_l4_ls_hwmod, 2250 .master = &am33xx_l4_ls_hwmod,
3175 .slave = &am33xx_timer3_hwmod, 2251 .slave = &am33xx_timer3_hwmod,
3176 .clk = "l4ls_gclk", 2252 .clk = "l4ls_gclk",
3177 .addr = am33xx_timer3_addr_space,
3178 .user = OCP_USER_MPU, 2253 .user = OCP_USER_MPU,
3179}; 2254};
3180 2255
3181/* l4 per -> timer4 */ 2256/* l4 per -> timer4 */
3182static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
3183 {
3184 .pa_start = 0x48044000,
3185 .pa_end = 0x48044000 + SZ_1K - 1,
3186 .flags = ADDR_TYPE_RT
3187 },
3188 { }
3189};
3190
3191static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = { 2257static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
3192 .master = &am33xx_l4_ls_hwmod, 2258 .master = &am33xx_l4_ls_hwmod,
3193 .slave = &am33xx_timer4_hwmod, 2259 .slave = &am33xx_timer4_hwmod,
3194 .clk = "l4ls_gclk", 2260 .clk = "l4ls_gclk",
3195 .addr = am33xx_timer4_addr_space,
3196 .user = OCP_USER_MPU, 2261 .user = OCP_USER_MPU,
3197}; 2262};
3198 2263
3199/* l4 per -> timer5 */ 2264/* l4 per -> timer5 */
3200static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
3201 {
3202 .pa_start = 0x48046000,
3203 .pa_end = 0x48046000 + SZ_1K - 1,
3204 .flags = ADDR_TYPE_RT
3205 },
3206 { }
3207};
3208
3209static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = { 2265static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
3210 .master = &am33xx_l4_ls_hwmod, 2266 .master = &am33xx_l4_ls_hwmod,
3211 .slave = &am33xx_timer5_hwmod, 2267 .slave = &am33xx_timer5_hwmod,
3212 .clk = "l4ls_gclk", 2268 .clk = "l4ls_gclk",
3213 .addr = am33xx_timer5_addr_space,
3214 .user = OCP_USER_MPU, 2269 .user = OCP_USER_MPU,
3215}; 2270};
3216 2271
3217/* l4 per -> timer6 */ 2272/* l4 per -> timer6 */
3218static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
3219 {
3220 .pa_start = 0x48048000,
3221 .pa_end = 0x48048000 + SZ_1K - 1,
3222 .flags = ADDR_TYPE_RT
3223 },
3224 { }
3225};
3226
3227static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = { 2273static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
3228 .master = &am33xx_l4_ls_hwmod, 2274 .master = &am33xx_l4_ls_hwmod,
3229 .slave = &am33xx_timer6_hwmod, 2275 .slave = &am33xx_timer6_hwmod,
3230 .clk = "l4ls_gclk", 2276 .clk = "l4ls_gclk",
3231 .addr = am33xx_timer6_addr_space,
3232 .user = OCP_USER_MPU, 2277 .user = OCP_USER_MPU,
3233}; 2278};
3234 2279
3235/* l4 per -> timer7 */ 2280/* l4 per -> timer7 */
3236static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
3237 {
3238 .pa_start = 0x4804A000,
3239 .pa_end = 0x4804A000 + SZ_1K - 1,
3240 .flags = ADDR_TYPE_RT
3241 },
3242 { }
3243};
3244
3245static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = { 2281static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
3246 .master = &am33xx_l4_ls_hwmod, 2282 .master = &am33xx_l4_ls_hwmod,
3247 .slave = &am33xx_timer7_hwmod, 2283 .slave = &am33xx_timer7_hwmod,
3248 .clk = "l4ls_gclk", 2284 .clk = "l4ls_gclk",
3249 .addr = am33xx_timer7_addr_space,
3250 .user = OCP_USER_MPU, 2285 .user = OCP_USER_MPU,
3251}; 2286};
3252 2287
3253/* l3 main -> tpcc */ 2288/* l3 main -> tpcc */
3254static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
3255 {
3256 .pa_start = 0x49000000,
3257 .pa_end = 0x49000000 + SZ_32K - 1,
3258 .flags = ADDR_TYPE_RT
3259 },
3260 { }
3261};
3262
3263static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = { 2289static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
3264 .master = &am33xx_l3_main_hwmod, 2290 .master = &am33xx_l3_main_hwmod,
3265 .slave = &am33xx_tpcc_hwmod, 2291 .slave = &am33xx_tpcc_hwmod,
3266 .clk = "l3_gclk", 2292 .clk = "l3_gclk",
3267 .addr = am33xx_tpcc_addr_space,
3268 .user = OCP_USER_MPU, 2293 .user = OCP_USER_MPU,
3269}; 2294};
3270 2295
@@ -3323,160 +2348,67 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
3323}; 2348};
3324 2349
3325/* l4 wkup -> uart1 */ 2350/* l4 wkup -> uart1 */
3326static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
3327 {
3328 .pa_start = 0x44E09000,
3329 .pa_end = 0x44E09000 + SZ_8K - 1,
3330 .flags = ADDR_TYPE_RT,
3331 },
3332 { }
3333};
3334
3335static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = { 2351static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
3336 .master = &am33xx_l4_wkup_hwmod, 2352 .master = &am33xx_l4_wkup_hwmod,
3337 .slave = &am33xx_uart1_hwmod, 2353 .slave = &am33xx_uart1_hwmod,
3338 .clk = "dpll_core_m4_div2_ck", 2354 .clk = "dpll_core_m4_div2_ck",
3339 .addr = am33xx_uart1_addr_space,
3340 .user = OCP_USER_MPU, 2355 .user = OCP_USER_MPU,
3341}; 2356};
3342 2357
3343/* l4 ls -> uart2 */ 2358/* l4 ls -> uart2 */
3344static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
3345 {
3346 .pa_start = 0x48022000,
3347 .pa_end = 0x48022000 + SZ_8K - 1,
3348 .flags = ADDR_TYPE_RT,
3349 },
3350 { }
3351};
3352
3353static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = { 2359static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
3354 .master = &am33xx_l4_ls_hwmod, 2360 .master = &am33xx_l4_ls_hwmod,
3355 .slave = &am33xx_uart2_hwmod, 2361 .slave = &am33xx_uart2_hwmod,
3356 .clk = "l4ls_gclk", 2362 .clk = "l4ls_gclk",
3357 .addr = am33xx_uart2_addr_space,
3358 .user = OCP_USER_MPU, 2363 .user = OCP_USER_MPU,
3359}; 2364};
3360 2365
3361/* l4 ls -> uart3 */ 2366/* l4 ls -> uart3 */
3362static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
3363 {
3364 .pa_start = 0x48024000,
3365 .pa_end = 0x48024000 + SZ_8K - 1,
3366 .flags = ADDR_TYPE_RT,
3367 },
3368 { }
3369};
3370
3371static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = { 2367static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
3372 .master = &am33xx_l4_ls_hwmod, 2368 .master = &am33xx_l4_ls_hwmod,
3373 .slave = &am33xx_uart3_hwmod, 2369 .slave = &am33xx_uart3_hwmod,
3374 .clk = "l4ls_gclk", 2370 .clk = "l4ls_gclk",
3375 .addr = am33xx_uart3_addr_space,
3376 .user = OCP_USER_MPU, 2371 .user = OCP_USER_MPU,
3377}; 2372};
3378 2373
3379/* l4 ls -> uart4 */ 2374/* l4 ls -> uart4 */
3380static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
3381 {
3382 .pa_start = 0x481A6000,
3383 .pa_end = 0x481A6000 + SZ_8K - 1,
3384 .flags = ADDR_TYPE_RT,
3385 },
3386 { }
3387};
3388
3389static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = { 2375static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
3390 .master = &am33xx_l4_ls_hwmod, 2376 .master = &am33xx_l4_ls_hwmod,
3391 .slave = &am33xx_uart4_hwmod, 2377 .slave = &am33xx_uart4_hwmod,
3392 .clk = "l4ls_gclk", 2378 .clk = "l4ls_gclk",
3393 .addr = am33xx_uart4_addr_space,
3394 .user = OCP_USER_MPU, 2379 .user = OCP_USER_MPU,
3395}; 2380};
3396 2381
3397/* l4 ls -> uart5 */ 2382/* l4 ls -> uart5 */
3398static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
3399 {
3400 .pa_start = 0x481A8000,
3401 .pa_end = 0x481A8000 + SZ_8K - 1,
3402 .flags = ADDR_TYPE_RT,
3403 },
3404 { }
3405};
3406
3407static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = { 2383static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
3408 .master = &am33xx_l4_ls_hwmod, 2384 .master = &am33xx_l4_ls_hwmod,
3409 .slave = &am33xx_uart5_hwmod, 2385 .slave = &am33xx_uart5_hwmod,
3410 .clk = "l4ls_gclk", 2386 .clk = "l4ls_gclk",
3411 .addr = am33xx_uart5_addr_space,
3412 .user = OCP_USER_MPU, 2387 .user = OCP_USER_MPU,
3413}; 2388};
3414 2389
3415/* l4 ls -> uart6 */ 2390/* l4 ls -> uart6 */
3416static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
3417 {
3418 .pa_start = 0x481aa000,
3419 .pa_end = 0x481aa000 + SZ_8K - 1,
3420 .flags = ADDR_TYPE_RT,
3421 },
3422 { }
3423};
3424
3425static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = { 2391static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
3426 .master = &am33xx_l4_ls_hwmod, 2392 .master = &am33xx_l4_ls_hwmod,
3427 .slave = &am33xx_uart6_hwmod, 2393 .slave = &am33xx_uart6_hwmod,
3428 .clk = "l4ls_gclk", 2394 .clk = "l4ls_gclk",
3429 .addr = am33xx_uart6_addr_space,
3430 .user = OCP_USER_MPU, 2395 .user = OCP_USER_MPU,
3431}; 2396};
3432 2397
3433/* l4 wkup -> wd_timer1 */ 2398/* l4 wkup -> wd_timer1 */
3434static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
3435 {
3436 .pa_start = 0x44e35000,
3437 .pa_end = 0x44e35000 + SZ_4K - 1,
3438 .flags = ADDR_TYPE_RT
3439 },
3440 { }
3441};
3442
3443static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = { 2399static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
3444 .master = &am33xx_l4_wkup_hwmod, 2400 .master = &am33xx_l4_wkup_hwmod,
3445 .slave = &am33xx_wd_timer1_hwmod, 2401 .slave = &am33xx_wd_timer1_hwmod,
3446 .clk = "dpll_core_m4_div2_ck", 2402 .clk = "dpll_core_m4_div2_ck",
3447 .addr = am33xx_wd_timer1_addrs,
3448 .user = OCP_USER_MPU, 2403 .user = OCP_USER_MPU,
3449}; 2404};
3450 2405
3451/* usbss */ 2406/* usbss */
3452/* l3 s -> USBSS interface */ 2407/* l3 s -> USBSS interface */
3453static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
3454 {
3455 .name = "usbss",
3456 .pa_start = 0x47400000,
3457 .pa_end = 0x47400000 + SZ_4K - 1,
3458 .flags = ADDR_TYPE_RT
3459 },
3460 {
3461 .name = "musb0",
3462 .pa_start = 0x47401000,
3463 .pa_end = 0x47401000 + SZ_2K - 1,
3464 .flags = ADDR_TYPE_RT
3465 },
3466 {
3467 .name = "musb1",
3468 .pa_start = 0x47401800,
3469 .pa_end = 0x47401800 + SZ_2K - 1,
3470 .flags = ADDR_TYPE_RT
3471 },
3472 { }
3473};
3474
3475static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = { 2408static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
3476 .master = &am33xx_l3_s_hwmod, 2409 .master = &am33xx_l3_s_hwmod,
3477 .slave = &am33xx_usbss_hwmod, 2410 .slave = &am33xx_usbss_hwmod,
3478 .clk = "l3s_gclk", 2411 .clk = "l3s_gclk",
3479 .addr = am33xx_usbss_addr_space,
3480 .user = OCP_USER_MPU, 2412 .user = OCP_USER_MPU,
3481 .flags = OCPIF_SWSUP_IDLE, 2413 .flags = OCPIF_SWSUP_IDLE,
3482}; 2414};
@@ -3525,13 +2457,11 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
3525}; 2457};
3526 2458
3527static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { 2459static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
3528 &am33xx_l4_fw__emif_fw,
3529 &am33xx_l3_main__emif, 2460 &am33xx_l3_main__emif,
3530 &am33xx_mpu__l3_main, 2461 &am33xx_mpu__l3_main,
3531 &am33xx_mpu__prcm, 2462 &am33xx_mpu__prcm,
3532 &am33xx_l3_s__l4_ls, 2463 &am33xx_l3_s__l4_ls,
3533 &am33xx_l3_s__l4_wkup, 2464 &am33xx_l3_s__l4_wkup,
3534 &am33xx_l3_s__l4_fw,
3535 &am33xx_l3_main__l4_hs, 2465 &am33xx_l3_main__l4_hs,
3536 &am33xx_l3_main__l3_s, 2466 &am33xx_l3_main__l3_s,
3537 &am33xx_l3_main__l3_instr, 2467 &am33xx_l3_main__l3_instr,
@@ -3561,9 +2491,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
3561 &am33xx_l4_per__i2c3, 2491 &am33xx_l4_per__i2c3,
3562 &am33xx_l4_per__mailbox, 2492 &am33xx_l4_per__mailbox,
3563 &am33xx_l4_ls__mcasp0, 2493 &am33xx_l4_ls__mcasp0,
3564 &am33xx_l3_s__mcasp0_data,
3565 &am33xx_l4_ls__mcasp1, 2494 &am33xx_l4_ls__mcasp1,
3566 &am33xx_l3_s__mcasp1_data,
3567 &am33xx_l4_ls__mmc0, 2495 &am33xx_l4_ls__mmc0,
3568 &am33xx_l4_ls__mmc1, 2496 &am33xx_l4_ls__mmc1,
3569 &am33xx_l3_s__mmc2, 2497 &am33xx_l3_s__mmc2,
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 31c7126eb3bb..0c3a427da544 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -25,6 +25,7 @@
25#include <linux/platform_data/asoc-ti-mcbsp.h> 25#include <linux/platform_data/asoc-ti-mcbsp.h>
26#include <linux/platform_data/spi-omap2-mcspi.h> 26#include <linux/platform_data/spi-omap2-mcspi.h>
27#include <linux/platform_data/iommu-omap.h> 27#include <linux/platform_data/iommu-omap.h>
28#include <linux/platform_data/mailbox-omap.h>
28#include <plat/dmtimer.h> 29#include <plat/dmtimer.h>
29 30
30#include "am35xx.h" 31#include "am35xx.h"
@@ -35,7 +36,6 @@
35#include "prm-regbits-34xx.h" 36#include "prm-regbits-34xx.h"
36#include "cm-regbits-34xx.h" 37#include "cm-regbits-34xx.h"
37 38
38#include "dma.h"
39#include "i2c.h" 39#include "i2c.h"
40#include "mmc.h" 40#include "mmc.h"
41#include "wd_timer.h" 41#include "wd_timer.h"
@@ -490,7 +490,7 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = {
490 .mpu_irqs = omap2_uart1_mpu_irqs, 490 .mpu_irqs = omap2_uart1_mpu_irqs,
491 .sdma_reqs = omap2_uart1_sdma_reqs, 491 .sdma_reqs = omap2_uart1_sdma_reqs,
492 .main_clk = "uart1_fck", 492 .main_clk = "uart1_fck",
493 .flags = HWMOD_SWSUP_SIDLE_ACT, 493 .flags = DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
494 .prcm = { 494 .prcm = {
495 .omap2 = { 495 .omap2 = {
496 .module_offs = CORE_MOD, 496 .module_offs = CORE_MOD,
@@ -509,7 +509,7 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = {
509 .mpu_irqs = omap2_uart2_mpu_irqs, 509 .mpu_irqs = omap2_uart2_mpu_irqs,
510 .sdma_reqs = omap2_uart2_sdma_reqs, 510 .sdma_reqs = omap2_uart2_sdma_reqs,
511 .main_clk = "uart2_fck", 511 .main_clk = "uart2_fck",
512 .flags = HWMOD_SWSUP_SIDLE_ACT, 512 .flags = DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
513 .prcm = { 513 .prcm = {
514 .omap2 = { 514 .omap2 = {
515 .module_offs = CORE_MOD, 515 .module_offs = CORE_MOD,
@@ -528,7 +528,8 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
528 .mpu_irqs = omap2_uart3_mpu_irqs, 528 .mpu_irqs = omap2_uart3_mpu_irqs,
529 .sdma_reqs = omap2_uart3_sdma_reqs, 529 .sdma_reqs = omap2_uart3_sdma_reqs,
530 .main_clk = "uart3_fck", 530 .main_clk = "uart3_fck",
531 .flags = HWMOD_SWSUP_SIDLE_ACT, 531 .flags = DEBUG_OMAP3UART3_FLAGS | DEBUG_TI81XXUART3_FLAGS |
532 HWMOD_SWSUP_SIDLE_ACT,
532 .prcm = { 533 .prcm = {
533 .omap2 = { 534 .omap2 = {
534 .module_offs = OMAP3430_PER_MOD, 535 .module_offs = OMAP3430_PER_MOD,
@@ -548,8 +549,8 @@ static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
548}; 549};
549 550
550static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { 551static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
551 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, }, 552 { .name = "rx", .dma_req = 82, },
552 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, }, 553 { .name = "tx", .dma_req = 81, },
553 { .dma_req = -1 } 554 { .dma_req = -1 }
554}; 555};
555 556
@@ -558,7 +559,7 @@ static struct omap_hwmod omap36xx_uart4_hwmod = {
558 .mpu_irqs = uart4_mpu_irqs, 559 .mpu_irqs = uart4_mpu_irqs,
559 .sdma_reqs = uart4_sdma_reqs, 560 .sdma_reqs = uart4_sdma_reqs,
560 .main_clk = "uart4_fck", 561 .main_clk = "uart4_fck",
561 .flags = HWMOD_SWSUP_SIDLE_ACT, 562 .flags = DEBUG_OMAP3UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
562 .prcm = { 563 .prcm = {
563 .omap2 = { 564 .omap2 = {
564 .module_offs = OMAP3430_PER_MOD, 565 .module_offs = OMAP3430_PER_MOD,
@@ -577,8 +578,8 @@ static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
577}; 578};
578 579
579static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = { 580static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
580 { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, }, 581 { .name = "rx", .dma_req = 55, },
581 { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, }, 582 { .name = "tx", .dma_req = 54, },
582 { .dma_req = -1 } 583 { .dma_req = -1 }
583}; 584};
584 585
@@ -857,8 +858,8 @@ static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
857}; 858};
858 859
859static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = { 860static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
860 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX }, 861 { .name = "tx", .dma_req = 25 },
861 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX }, 862 { .name = "rx", .dma_req = 26 },
862 { .dma_req = -1 } 863 { .dma_req = -1 }
863}; 864};
864 865
@@ -1505,6 +1506,17 @@ static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1505 .sysc = &omap3xxx_mailbox_sysc, 1506 .sysc = &omap3xxx_mailbox_sysc,
1506}; 1507};
1507 1508
1509static struct omap_mbox_dev_info omap3xxx_mailbox_info[] = {
1510 { .name = "dsp", .tx_id = 0, .rx_id = 1 },
1511};
1512
1513static struct omap_mbox_pdata omap3xxx_mailbox_attrs = {
1514 .num_users = 2,
1515 .num_fifos = 2,
1516 .info_cnt = ARRAY_SIZE(omap3xxx_mailbox_info),
1517 .info = omap3xxx_mailbox_info,
1518};
1519
1508static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = { 1520static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
1509 { .irq = 26 + OMAP_INTC_START, }, 1521 { .irq = 26 + OMAP_INTC_START, },
1510 { .irq = -1 }, 1522 { .irq = -1 },
@@ -1524,6 +1536,7 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1524 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT, 1536 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1525 }, 1537 },
1526 }, 1538 },
1539 .dev_attr = &omap3xxx_mailbox_attrs,
1527}; 1540};
1528 1541
1529/* 1542/*
@@ -3581,7 +3594,7 @@ static struct omap_hwmod_irq_info omap3_sham_mpu_irqs[] = {
3581}; 3594};
3582 3595
3583static struct omap_hwmod_dma_info omap3_sham_sdma_reqs[] = { 3596static struct omap_hwmod_dma_info omap3_sham_sdma_reqs[] = {
3584 { .name = "rx", .dma_req = OMAP34XX_DMA_SHA1MD5_RX, }, 3597 { .name = "rx", .dma_req = 69, },
3585 { .dma_req = -1 } 3598 { .dma_req = -1 }
3586}; 3599};
3587 3600
@@ -3642,8 +3655,8 @@ static struct omap_hwmod_class omap3xxx_aes_class = {
3642}; 3655};
3643 3656
3644static struct omap_hwmod_dma_info omap3_aes_sdma_reqs[] = { 3657static struct omap_hwmod_dma_info omap3_aes_sdma_reqs[] = {
3645 { .name = "tx", .dma_req = OMAP34XX_DMA_AES2_TX, }, 3658 { .name = "tx", .dma_req = 65, },
3646 { .name = "rx", .dma_req = OMAP34XX_DMA_AES2_RX, }, 3659 { .name = "rx", .dma_req = 66, },
3647 { .dma_req = -1 } 3660 { .dma_req = -1 }
3648}; 3661};
3649 3662
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 848b6dc67590..9c3b504477d7 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -12,6 +12,8 @@
12 * with the public linux-omap@vger.kernel.org mailing list and the 12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept 13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents. 14 * up-to-date with the file contents.
15 * Note that this file is currently not in sync with autogeneration scripts.
16 * The above note to be removed, once it is synced up.
15 * 17 *
16 * This program is free software; you can redistribute it and/or modify 18 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as 19 * it under the terms of the GNU General Public License version 2 as
@@ -21,7 +23,6 @@
21#include <linux/io.h> 23#include <linux/io.h>
22#include <linux/platform_data/gpio-omap.h> 24#include <linux/platform_data/gpio-omap.h>
23#include <linux/power/smartreflex.h> 25#include <linux/power/smartreflex.h>
24#include <linux/platform_data/omap_ocp2scp.h>
25#include <linux/i2c-omap.h> 26#include <linux/i2c-omap.h>
26 27
27#include <linux/omap-dma.h> 28#include <linux/omap-dma.h>
@@ -52,27 +53,6 @@
52 */ 53 */
53 54
54/* 55/*
55 * 'c2c_target_fw' class
56 * instance(s): c2c_target_fw
57 */
58static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
59 .name = "c2c_target_fw",
60};
61
62/* c2c_target_fw */
63static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
64 .name = "c2c_target_fw",
65 .class = &omap44xx_c2c_target_fw_hwmod_class,
66 .clkdm_name = "d2d_clkdm",
67 .prcm = {
68 .omap4 = {
69 .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
70 .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
71 },
72 },
73};
74
75/*
76 * 'dmm' class 56 * 'dmm' class
77 * instance(s): dmm 57 * instance(s): dmm
78 */ 58 */
@@ -81,16 +61,10 @@ static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
81}; 61};
82 62
83/* dmm */ 63/* dmm */
84static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
85 { .irq = 113 + OMAP44XX_IRQ_GIC_START },
86 { .irq = -1 }
87};
88
89static struct omap_hwmod omap44xx_dmm_hwmod = { 64static struct omap_hwmod omap44xx_dmm_hwmod = {
90 .name = "dmm", 65 .name = "dmm",
91 .class = &omap44xx_dmm_hwmod_class, 66 .class = &omap44xx_dmm_hwmod_class,
92 .clkdm_name = "l3_emif_clkdm", 67 .clkdm_name = "l3_emif_clkdm",
93 .mpu_irqs = omap44xx_dmm_irqs,
94 .prcm = { 68 .prcm = {
95 .omap4 = { 69 .omap4 = {
96 .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET, 70 .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
@@ -100,27 +74,6 @@ static struct omap_hwmod omap44xx_dmm_hwmod = {
100}; 74};
101 75
102/* 76/*
103 * 'emif_fw' class
104 * instance(s): emif_fw
105 */
106static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
107 .name = "emif_fw",
108};
109
110/* emif_fw */
111static struct omap_hwmod omap44xx_emif_fw_hwmod = {
112 .name = "emif_fw",
113 .class = &omap44xx_emif_fw_hwmod_class,
114 .clkdm_name = "l3_emif_clkdm",
115 .prcm = {
116 .omap4 = {
117 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
118 .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
119 },
120 },
121};
122
123/*
124 * 'l3' class 77 * 'l3' class
125 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3 78 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
126 */ 79 */
@@ -143,17 +96,10 @@ static struct omap_hwmod omap44xx_l3_instr_hwmod = {
143}; 96};
144 97
145/* l3_main_1 */ 98/* l3_main_1 */
146static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
147 { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
148 { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
149 { .irq = -1 }
150};
151
152static struct omap_hwmod omap44xx_l3_main_1_hwmod = { 99static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
153 .name = "l3_main_1", 100 .name = "l3_main_1",
154 .class = &omap44xx_l3_hwmod_class, 101 .class = &omap44xx_l3_hwmod_class,
155 .clkdm_name = "l3_1_clkdm", 102 .clkdm_name = "l3_1_clkdm",
156 .mpu_irqs = omap44xx_l3_main_1_irqs,
157 .prcm = { 103 .prcm = {
158 .omap4 = { 104 .omap4 = {
159 .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET, 105 .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
@@ -326,29 +272,10 @@ static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
326}; 272};
327 273
328/* aess */ 274/* aess */
329static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
330 { .irq = 99 + OMAP44XX_IRQ_GIC_START },
331 { .irq = -1 }
332};
333
334static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
335 { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
336 { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
337 { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
338 { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
339 { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
340 { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
341 { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
342 { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
343 { .dma_req = -1 }
344};
345
346static struct omap_hwmod omap44xx_aess_hwmod = { 275static struct omap_hwmod omap44xx_aess_hwmod = {
347 .name = "aess", 276 .name = "aess",
348 .class = &omap44xx_aess_hwmod_class, 277 .class = &omap44xx_aess_hwmod_class,
349 .clkdm_name = "abe_clkdm", 278 .clkdm_name = "abe_clkdm",
350 .mpu_irqs = omap44xx_aess_irqs,
351 .sdma_reqs = omap44xx_aess_sdma_reqs,
352 .main_clk = "aess_fclk", 279 .main_clk = "aess_fclk",
353 .prcm = { 280 .prcm = {
354 .omap4 = { 281 .omap4 = {
@@ -371,22 +298,10 @@ static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
371}; 298};
372 299
373/* c2c */ 300/* c2c */
374static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
375 { .irq = 88 + OMAP44XX_IRQ_GIC_START },
376 { .irq = -1 }
377};
378
379static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
380 { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
381 { .dma_req = -1 }
382};
383
384static struct omap_hwmod omap44xx_c2c_hwmod = { 301static struct omap_hwmod omap44xx_c2c_hwmod = {
385 .name = "c2c", 302 .name = "c2c",
386 .class = &omap44xx_c2c_hwmod_class, 303 .class = &omap44xx_c2c_hwmod_class,
387 .clkdm_name = "d2d_clkdm", 304 .clkdm_name = "d2d_clkdm",
388 .mpu_irqs = omap44xx_c2c_irqs,
389 .sdma_reqs = omap44xx_c2c_sdma_reqs,
390 .prcm = { 305 .prcm = {
391 .omap4 = { 306 .omap4 = {
392 .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET, 307 .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
@@ -449,16 +364,10 @@ static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
449}; 364};
450 365
451/* ctrl_module_core */ 366/* ctrl_module_core */
452static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
453 { .irq = 8 + OMAP44XX_IRQ_GIC_START },
454 { .irq = -1 }
455};
456
457static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = { 367static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
458 .name = "ctrl_module_core", 368 .name = "ctrl_module_core",
459 .class = &omap44xx_ctrl_module_hwmod_class, 369 .class = &omap44xx_ctrl_module_hwmod_class,
460 .clkdm_name = "l4_cfg_clkdm", 370 .clkdm_name = "l4_cfg_clkdm",
461 .mpu_irqs = omap44xx_ctrl_module_core_irqs,
462 .prcm = { 371 .prcm = {
463 .omap4 = { 372 .omap4 = {
464 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, 373 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
@@ -601,22 +510,10 @@ static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
601}; 510};
602 511
603/* dmic */ 512/* dmic */
604static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
605 { .irq = 114 + OMAP44XX_IRQ_GIC_START },
606 { .irq = -1 }
607};
608
609static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
610 { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
611 { .dma_req = -1 }
612};
613
614static struct omap_hwmod omap44xx_dmic_hwmod = { 513static struct omap_hwmod omap44xx_dmic_hwmod = {
615 .name = "dmic", 514 .name = "dmic",
616 .class = &omap44xx_dmic_hwmod_class, 515 .class = &omap44xx_dmic_hwmod_class,
617 .clkdm_name = "abe_clkdm", 516 .clkdm_name = "abe_clkdm",
618 .mpu_irqs = omap44xx_dmic_irqs,
619 .sdma_reqs = omap44xx_dmic_sdma_reqs,
620 .main_clk = "func_dmic_abe_gfclk", 517 .main_clk = "func_dmic_abe_gfclk",
621 .prcm = { 518 .prcm = {
622 .omap4 = { 519 .omap4 = {
@@ -637,11 +534,6 @@ static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
637}; 534};
638 535
639/* dsp */ 536/* dsp */
640static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
641 { .irq = 28 + OMAP44XX_IRQ_GIC_START },
642 { .irq = -1 }
643};
644
645static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { 537static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
646 { .name = "dsp", .rst_shift = 0 }, 538 { .name = "dsp", .rst_shift = 0 },
647}; 539};
@@ -650,7 +542,6 @@ static struct omap_hwmod omap44xx_dsp_hwmod = {
650 .name = "dsp", 542 .name = "dsp",
651 .class = &omap44xx_dsp_hwmod_class, 543 .class = &omap44xx_dsp_hwmod_class,
652 .clkdm_name = "tesla_clkdm", 544 .clkdm_name = "tesla_clkdm",
653 .mpu_irqs = omap44xx_dsp_irqs,
654 .rst_lines = omap44xx_dsp_resets, 545 .rst_lines = omap44xx_dsp_resets,
655 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets), 546 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
656 .main_clk = "dpll_iva_m4x2_ck", 547 .main_clk = "dpll_iva_m4x2_ck",
@@ -992,16 +883,10 @@ static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
992}; 883};
993 884
994/* elm */ 885/* elm */
995static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
996 { .irq = 4 + OMAP44XX_IRQ_GIC_START },
997 { .irq = -1 }
998};
999
1000static struct omap_hwmod omap44xx_elm_hwmod = { 886static struct omap_hwmod omap44xx_elm_hwmod = {
1001 .name = "elm", 887 .name = "elm",
1002 .class = &omap44xx_elm_hwmod_class, 888 .class = &omap44xx_elm_hwmod_class,
1003 .clkdm_name = "l4_per_clkdm", 889 .clkdm_name = "l4_per_clkdm",
1004 .mpu_irqs = omap44xx_elm_irqs,
1005 .prcm = { 890 .prcm = {
1006 .omap4 = { 891 .omap4 = {
1007 .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET, 892 .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
@@ -1025,17 +910,11 @@ static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
1025}; 910};
1026 911
1027/* emif1 */ 912/* emif1 */
1028static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
1029 { .irq = 110 + OMAP44XX_IRQ_GIC_START },
1030 { .irq = -1 }
1031};
1032
1033static struct omap_hwmod omap44xx_emif1_hwmod = { 913static struct omap_hwmod omap44xx_emif1_hwmod = {
1034 .name = "emif1", 914 .name = "emif1",
1035 .class = &omap44xx_emif_hwmod_class, 915 .class = &omap44xx_emif_hwmod_class,
1036 .clkdm_name = "l3_emif_clkdm", 916 .clkdm_name = "l3_emif_clkdm",
1037 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, 917 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1038 .mpu_irqs = omap44xx_emif1_irqs,
1039 .main_clk = "ddrphy_ck", 918 .main_clk = "ddrphy_ck",
1040 .prcm = { 919 .prcm = {
1041 .omap4 = { 920 .omap4 = {
@@ -1047,17 +926,11 @@ static struct omap_hwmod omap44xx_emif1_hwmod = {
1047}; 926};
1048 927
1049/* emif2 */ 928/* emif2 */
1050static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
1051 { .irq = 111 + OMAP44XX_IRQ_GIC_START },
1052 { .irq = -1 }
1053};
1054
1055static struct omap_hwmod omap44xx_emif2_hwmod = { 929static struct omap_hwmod omap44xx_emif2_hwmod = {
1056 .name = "emif2", 930 .name = "emif2",
1057 .class = &omap44xx_emif_hwmod_class, 931 .class = &omap44xx_emif_hwmod_class,
1058 .clkdm_name = "l3_emif_clkdm", 932 .clkdm_name = "l3_emif_clkdm",
1059 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, 933 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1060 .mpu_irqs = omap44xx_emif2_irqs,
1061 .main_clk = "ddrphy_ck", 934 .main_clk = "ddrphy_ck",
1062 .prcm = { 935 .prcm = {
1063 .omap4 = { 936 .omap4 = {
@@ -1098,16 +971,10 @@ static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1098}; 971};
1099 972
1100/* fdif */ 973/* fdif */
1101static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
1102 { .irq = 69 + OMAP44XX_IRQ_GIC_START },
1103 { .irq = -1 }
1104};
1105
1106static struct omap_hwmod omap44xx_fdif_hwmod = { 974static struct omap_hwmod omap44xx_fdif_hwmod = {
1107 .name = "fdif", 975 .name = "fdif",
1108 .class = &omap44xx_fdif_hwmod_class, 976 .class = &omap44xx_fdif_hwmod_class,
1109 .clkdm_name = "iss_clkdm", 977 .clkdm_name = "iss_clkdm",
1110 .mpu_irqs = omap44xx_fdif_irqs,
1111 .main_clk = "fdif_fck", 978 .main_clk = "fdif_fck",
1112 .prcm = { 979 .prcm = {
1113 .omap4 = { 980 .omap4 = {
@@ -1148,11 +1015,6 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
1148}; 1015};
1149 1016
1150/* gpio1 */ 1017/* gpio1 */
1151static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1152 { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1153 { .irq = -1 }
1154};
1155
1156static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { 1018static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1157 { .role = "dbclk", .clk = "gpio1_dbclk" }, 1019 { .role = "dbclk", .clk = "gpio1_dbclk" },
1158}; 1020};
@@ -1161,7 +1023,6 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
1161 .name = "gpio1", 1023 .name = "gpio1",
1162 .class = &omap44xx_gpio_hwmod_class, 1024 .class = &omap44xx_gpio_hwmod_class,
1163 .clkdm_name = "l4_wkup_clkdm", 1025 .clkdm_name = "l4_wkup_clkdm",
1164 .mpu_irqs = omap44xx_gpio1_irqs,
1165 .main_clk = "l4_wkup_clk_mux_ck", 1026 .main_clk = "l4_wkup_clk_mux_ck",
1166 .prcm = { 1027 .prcm = {
1167 .omap4 = { 1028 .omap4 = {
@@ -1176,11 +1037,6 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
1176}; 1037};
1177 1038
1178/* gpio2 */ 1039/* gpio2 */
1179static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1180 { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1181 { .irq = -1 }
1182};
1183
1184static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { 1040static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1185 { .role = "dbclk", .clk = "gpio2_dbclk" }, 1041 { .role = "dbclk", .clk = "gpio2_dbclk" },
1186}; 1042};
@@ -1190,7 +1046,6 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
1190 .class = &omap44xx_gpio_hwmod_class, 1046 .class = &omap44xx_gpio_hwmod_class,
1191 .clkdm_name = "l4_per_clkdm", 1047 .clkdm_name = "l4_per_clkdm",
1192 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1048 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1193 .mpu_irqs = omap44xx_gpio2_irqs,
1194 .main_clk = "l4_div_ck", 1049 .main_clk = "l4_div_ck",
1195 .prcm = { 1050 .prcm = {
1196 .omap4 = { 1051 .omap4 = {
@@ -1205,11 +1060,6 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
1205}; 1060};
1206 1061
1207/* gpio3 */ 1062/* gpio3 */
1208static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1209 { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1210 { .irq = -1 }
1211};
1212
1213static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { 1063static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1214 { .role = "dbclk", .clk = "gpio3_dbclk" }, 1064 { .role = "dbclk", .clk = "gpio3_dbclk" },
1215}; 1065};
@@ -1219,7 +1069,6 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
1219 .class = &omap44xx_gpio_hwmod_class, 1069 .class = &omap44xx_gpio_hwmod_class,
1220 .clkdm_name = "l4_per_clkdm", 1070 .clkdm_name = "l4_per_clkdm",
1221 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1071 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1222 .mpu_irqs = omap44xx_gpio3_irqs,
1223 .main_clk = "l4_div_ck", 1072 .main_clk = "l4_div_ck",
1224 .prcm = { 1073 .prcm = {
1225 .omap4 = { 1074 .omap4 = {
@@ -1234,11 +1083,6 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
1234}; 1083};
1235 1084
1236/* gpio4 */ 1085/* gpio4 */
1237static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1238 { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1239 { .irq = -1 }
1240};
1241
1242static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { 1086static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1243 { .role = "dbclk", .clk = "gpio4_dbclk" }, 1087 { .role = "dbclk", .clk = "gpio4_dbclk" },
1244}; 1088};
@@ -1248,7 +1092,6 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
1248 .class = &omap44xx_gpio_hwmod_class, 1092 .class = &omap44xx_gpio_hwmod_class,
1249 .clkdm_name = "l4_per_clkdm", 1093 .clkdm_name = "l4_per_clkdm",
1250 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1094 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1251 .mpu_irqs = omap44xx_gpio4_irqs,
1252 .main_clk = "l4_div_ck", 1095 .main_clk = "l4_div_ck",
1253 .prcm = { 1096 .prcm = {
1254 .omap4 = { 1097 .omap4 = {
@@ -1263,11 +1106,6 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
1263}; 1106};
1264 1107
1265/* gpio5 */ 1108/* gpio5 */
1266static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1267 { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1268 { .irq = -1 }
1269};
1270
1271static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { 1109static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1272 { .role = "dbclk", .clk = "gpio5_dbclk" }, 1110 { .role = "dbclk", .clk = "gpio5_dbclk" },
1273}; 1111};
@@ -1277,7 +1115,6 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
1277 .class = &omap44xx_gpio_hwmod_class, 1115 .class = &omap44xx_gpio_hwmod_class,
1278 .clkdm_name = "l4_per_clkdm", 1116 .clkdm_name = "l4_per_clkdm",
1279 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1117 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1280 .mpu_irqs = omap44xx_gpio5_irqs,
1281 .main_clk = "l4_div_ck", 1118 .main_clk = "l4_div_ck",
1282 .prcm = { 1119 .prcm = {
1283 .omap4 = { 1120 .omap4 = {
@@ -1292,11 +1129,6 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
1292}; 1129};
1293 1130
1294/* gpio6 */ 1131/* gpio6 */
1295static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1296 { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1297 { .irq = -1 }
1298};
1299
1300static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { 1132static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1301 { .role = "dbclk", .clk = "gpio6_dbclk" }, 1133 { .role = "dbclk", .clk = "gpio6_dbclk" },
1302}; 1134};
@@ -1306,7 +1138,6 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
1306 .class = &omap44xx_gpio_hwmod_class, 1138 .class = &omap44xx_gpio_hwmod_class,
1307 .clkdm_name = "l4_per_clkdm", 1139 .clkdm_name = "l4_per_clkdm",
1308 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1140 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1309 .mpu_irqs = omap44xx_gpio6_irqs,
1310 .main_clk = "l4_div_ck", 1141 .main_clk = "l4_div_ck",
1311 .prcm = { 1142 .prcm = {
1312 .omap4 = { 1143 .omap4 = {
@@ -1341,16 +1172,6 @@ static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1341}; 1172};
1342 1173
1343/* gpmc */ 1174/* gpmc */
1344static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
1345 { .irq = 20 + OMAP44XX_IRQ_GIC_START },
1346 { .irq = -1 }
1347};
1348
1349static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
1350 { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
1351 { .dma_req = -1 }
1352};
1353
1354static struct omap_hwmod omap44xx_gpmc_hwmod = { 1175static struct omap_hwmod omap44xx_gpmc_hwmod = {
1355 .name = "gpmc", 1176 .name = "gpmc",
1356 .class = &omap44xx_gpmc_hwmod_class, 1177 .class = &omap44xx_gpmc_hwmod_class,
@@ -1364,8 +1185,6 @@ static struct omap_hwmod omap44xx_gpmc_hwmod = {
1364 * HWMOD_INIT_NO_RESET should be removed ASAP. 1185 * HWMOD_INIT_NO_RESET should be removed ASAP.
1365 */ 1186 */
1366 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, 1187 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1367 .mpu_irqs = omap44xx_gpmc_irqs,
1368 .sdma_reqs = omap44xx_gpmc_sdma_reqs,
1369 .prcm = { 1188 .prcm = {
1370 .omap4 = { 1189 .omap4 = {
1371 .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET, 1190 .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
@@ -1396,16 +1215,10 @@ static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1396}; 1215};
1397 1216
1398/* gpu */ 1217/* gpu */
1399static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
1400 { .irq = 21 + OMAP44XX_IRQ_GIC_START },
1401 { .irq = -1 }
1402};
1403
1404static struct omap_hwmod omap44xx_gpu_hwmod = { 1218static struct omap_hwmod omap44xx_gpu_hwmod = {
1405 .name = "gpu", 1219 .name = "gpu",
1406 .class = &omap44xx_gpu_hwmod_class, 1220 .class = &omap44xx_gpu_hwmod_class,
1407 .clkdm_name = "l3_gfx_clkdm", 1221 .clkdm_name = "l3_gfx_clkdm",
1408 .mpu_irqs = omap44xx_gpu_irqs,
1409 .main_clk = "sgx_clk_mux", 1222 .main_clk = "sgx_clk_mux",
1410 .prcm = { 1223 .prcm = {
1411 .omap4 = { 1224 .omap4 = {
@@ -1436,17 +1249,11 @@ static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1436}; 1249};
1437 1250
1438/* hdq1w */ 1251/* hdq1w */
1439static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
1440 { .irq = 58 + OMAP44XX_IRQ_GIC_START },
1441 { .irq = -1 }
1442};
1443
1444static struct omap_hwmod omap44xx_hdq1w_hwmod = { 1252static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1445 .name = "hdq1w", 1253 .name = "hdq1w",
1446 .class = &omap44xx_hdq1w_hwmod_class, 1254 .class = &omap44xx_hdq1w_hwmod_class,
1447 .clkdm_name = "l4_per_clkdm", 1255 .clkdm_name = "l4_per_clkdm",
1448 .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */ 1256 .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */
1449 .mpu_irqs = omap44xx_hdq1w_irqs,
1450 .main_clk = "func_12m_fclk", 1257 .main_clk = "func_12m_fclk",
1451 .prcm = { 1258 .prcm = {
1452 .omap4 = { 1259 .omap4 = {
@@ -1482,18 +1289,10 @@ static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1482}; 1289};
1483 1290
1484/* hsi */ 1291/* hsi */
1485static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
1486 { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
1487 { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
1488 { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
1489 { .irq = -1 }
1490};
1491
1492static struct omap_hwmod omap44xx_hsi_hwmod = { 1292static struct omap_hwmod omap44xx_hsi_hwmod = {
1493 .name = "hsi", 1293 .name = "hsi",
1494 .class = &omap44xx_hsi_hwmod_class, 1294 .class = &omap44xx_hsi_hwmod_class,
1495 .clkdm_name = "l3_init_clkdm", 1295 .clkdm_name = "l3_init_clkdm",
1496 .mpu_irqs = omap44xx_hsi_irqs,
1497 .main_clk = "hsi_fck", 1296 .main_clk = "hsi_fck",
1498 .prcm = { 1297 .prcm = {
1499 .omap4 = { 1298 .omap4 = {
@@ -1533,24 +1332,11 @@ static struct omap_i2c_dev_attr i2c_dev_attr = {
1533}; 1332};
1534 1333
1535/* i2c1 */ 1334/* i2c1 */
1536static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1537 { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1538 { .irq = -1 }
1539};
1540
1541static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1542 { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1543 { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1544 { .dma_req = -1 }
1545};
1546
1547static struct omap_hwmod omap44xx_i2c1_hwmod = { 1335static struct omap_hwmod omap44xx_i2c1_hwmod = {
1548 .name = "i2c1", 1336 .name = "i2c1",
1549 .class = &omap44xx_i2c_hwmod_class, 1337 .class = &omap44xx_i2c_hwmod_class,
1550 .clkdm_name = "l4_per_clkdm", 1338 .clkdm_name = "l4_per_clkdm",
1551 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 1339 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1552 .mpu_irqs = omap44xx_i2c1_irqs,
1553 .sdma_reqs = omap44xx_i2c1_sdma_reqs,
1554 .main_clk = "func_96m_fclk", 1340 .main_clk = "func_96m_fclk",
1555 .prcm = { 1341 .prcm = {
1556 .omap4 = { 1342 .omap4 = {
@@ -1563,24 +1349,11 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
1563}; 1349};
1564 1350
1565/* i2c2 */ 1351/* i2c2 */
1566static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1567 { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1568 { .irq = -1 }
1569};
1570
1571static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1572 { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1573 { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1574 { .dma_req = -1 }
1575};
1576
1577static struct omap_hwmod omap44xx_i2c2_hwmod = { 1352static struct omap_hwmod omap44xx_i2c2_hwmod = {
1578 .name = "i2c2", 1353 .name = "i2c2",
1579 .class = &omap44xx_i2c_hwmod_class, 1354 .class = &omap44xx_i2c_hwmod_class,
1580 .clkdm_name = "l4_per_clkdm", 1355 .clkdm_name = "l4_per_clkdm",
1581 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 1356 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1582 .mpu_irqs = omap44xx_i2c2_irqs,
1583 .sdma_reqs = omap44xx_i2c2_sdma_reqs,
1584 .main_clk = "func_96m_fclk", 1357 .main_clk = "func_96m_fclk",
1585 .prcm = { 1358 .prcm = {
1586 .omap4 = { 1359 .omap4 = {
@@ -1593,24 +1366,11 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
1593}; 1366};
1594 1367
1595/* i2c3 */ 1368/* i2c3 */
1596static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1597 { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1598 { .irq = -1 }
1599};
1600
1601static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1602 { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1603 { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1604 { .dma_req = -1 }
1605};
1606
1607static struct omap_hwmod omap44xx_i2c3_hwmod = { 1369static struct omap_hwmod omap44xx_i2c3_hwmod = {
1608 .name = "i2c3", 1370 .name = "i2c3",
1609 .class = &omap44xx_i2c_hwmod_class, 1371 .class = &omap44xx_i2c_hwmod_class,
1610 .clkdm_name = "l4_per_clkdm", 1372 .clkdm_name = "l4_per_clkdm",
1611 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 1373 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1612 .mpu_irqs = omap44xx_i2c3_irqs,
1613 .sdma_reqs = omap44xx_i2c3_sdma_reqs,
1614 .main_clk = "func_96m_fclk", 1374 .main_clk = "func_96m_fclk",
1615 .prcm = { 1375 .prcm = {
1616 .omap4 = { 1376 .omap4 = {
@@ -1623,24 +1383,11 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
1623}; 1383};
1624 1384
1625/* i2c4 */ 1385/* i2c4 */
1626static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1627 { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1628 { .irq = -1 }
1629};
1630
1631static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1632 { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1633 { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1634 { .dma_req = -1 }
1635};
1636
1637static struct omap_hwmod omap44xx_i2c4_hwmod = { 1386static struct omap_hwmod omap44xx_i2c4_hwmod = {
1638 .name = "i2c4", 1387 .name = "i2c4",
1639 .class = &omap44xx_i2c_hwmod_class, 1388 .class = &omap44xx_i2c_hwmod_class,
1640 .clkdm_name = "l4_per_clkdm", 1389 .clkdm_name = "l4_per_clkdm",
1641 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 1390 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1642 .mpu_irqs = omap44xx_i2c4_irqs,
1643 .sdma_reqs = omap44xx_i2c4_sdma_reqs,
1644 .main_clk = "func_96m_fclk", 1391 .main_clk = "func_96m_fclk",
1645 .prcm = { 1392 .prcm = {
1646 .omap4 = { 1393 .omap4 = {
@@ -1662,11 +1409,6 @@ static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1662}; 1409};
1663 1410
1664/* ipu */ 1411/* ipu */
1665static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
1666 { .irq = 100 + OMAP44XX_IRQ_GIC_START },
1667 { .irq = -1 }
1668};
1669
1670static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = { 1412static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1671 { .name = "cpu0", .rst_shift = 0 }, 1413 { .name = "cpu0", .rst_shift = 0 },
1672 { .name = "cpu1", .rst_shift = 1 }, 1414 { .name = "cpu1", .rst_shift = 1 },
@@ -1676,7 +1418,6 @@ static struct omap_hwmod omap44xx_ipu_hwmod = {
1676 .name = "ipu", 1418 .name = "ipu",
1677 .class = &omap44xx_ipu_hwmod_class, 1419 .class = &omap44xx_ipu_hwmod_class,
1678 .clkdm_name = "ducati_clkdm", 1420 .clkdm_name = "ducati_clkdm",
1679 .mpu_irqs = omap44xx_ipu_irqs,
1680 .rst_lines = omap44xx_ipu_resets, 1421 .rst_lines = omap44xx_ipu_resets,
1681 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets), 1422 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
1682 .main_clk = "ducati_clk_mux_ck", 1423 .main_clk = "ducati_clk_mux_ck",
@@ -1721,19 +1462,6 @@ static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1721}; 1462};
1722 1463
1723/* iss */ 1464/* iss */
1724static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
1725 { .irq = 24 + OMAP44XX_IRQ_GIC_START },
1726 { .irq = -1 }
1727};
1728
1729static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
1730 { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
1731 { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
1732 { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
1733 { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
1734 { .dma_req = -1 }
1735};
1736
1737static struct omap_hwmod_opt_clk iss_opt_clks[] = { 1465static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1738 { .role = "ctrlclk", .clk = "iss_ctrlclk" }, 1466 { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1739}; 1467};
@@ -1742,8 +1470,6 @@ static struct omap_hwmod omap44xx_iss_hwmod = {
1742 .name = "iss", 1470 .name = "iss",
1743 .class = &omap44xx_iss_hwmod_class, 1471 .class = &omap44xx_iss_hwmod_class,
1744 .clkdm_name = "iss_clkdm", 1472 .clkdm_name = "iss_clkdm",
1745 .mpu_irqs = omap44xx_iss_irqs,
1746 .sdma_reqs = omap44xx_iss_sdma_reqs,
1747 .main_clk = "ducati_clk_mux_ck", 1473 .main_clk = "ducati_clk_mux_ck",
1748 .prcm = { 1474 .prcm = {
1749 .omap4 = { 1475 .omap4 = {
@@ -1766,13 +1492,6 @@ static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1766}; 1492};
1767 1493
1768/* iva */ 1494/* iva */
1769static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1770 { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1771 { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1772 { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1773 { .irq = -1 }
1774};
1775
1776static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { 1495static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1777 { .name = "seq0", .rst_shift = 0 }, 1496 { .name = "seq0", .rst_shift = 0 },
1778 { .name = "seq1", .rst_shift = 1 }, 1497 { .name = "seq1", .rst_shift = 1 },
@@ -1783,7 +1502,6 @@ static struct omap_hwmod omap44xx_iva_hwmod = {
1783 .name = "iva", 1502 .name = "iva",
1784 .class = &omap44xx_iva_hwmod_class, 1503 .class = &omap44xx_iva_hwmod_class,
1785 .clkdm_name = "ivahd_clkdm", 1504 .clkdm_name = "ivahd_clkdm",
1786 .mpu_irqs = omap44xx_iva_irqs,
1787 .rst_lines = omap44xx_iva_resets, 1505 .rst_lines = omap44xx_iva_resets,
1788 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), 1506 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
1789 .main_clk = "dpll_iva_m5x2_ck", 1507 .main_clk = "dpll_iva_m5x2_ck",
@@ -1820,16 +1538,10 @@ static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1820}; 1538};
1821 1539
1822/* kbd */ 1540/* kbd */
1823static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
1824 { .irq = 120 + OMAP44XX_IRQ_GIC_START },
1825 { .irq = -1 }
1826};
1827
1828static struct omap_hwmod omap44xx_kbd_hwmod = { 1541static struct omap_hwmod omap44xx_kbd_hwmod = {
1829 .name = "kbd", 1542 .name = "kbd",
1830 .class = &omap44xx_kbd_hwmod_class, 1543 .class = &omap44xx_kbd_hwmod_class,
1831 .clkdm_name = "l4_wkup_clkdm", 1544 .clkdm_name = "l4_wkup_clkdm",
1832 .mpu_irqs = omap44xx_kbd_irqs,
1833 .main_clk = "sys_32k_ck", 1545 .main_clk = "sys_32k_ck",
1834 .prcm = { 1546 .prcm = {
1835 .omap4 = { 1547 .omap4 = {
@@ -1861,16 +1573,10 @@ static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1861}; 1573};
1862 1574
1863/* mailbox */ 1575/* mailbox */
1864static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
1865 { .irq = 26 + OMAP44XX_IRQ_GIC_START },
1866 { .irq = -1 }
1867};
1868
1869static struct omap_hwmod omap44xx_mailbox_hwmod = { 1576static struct omap_hwmod omap44xx_mailbox_hwmod = {
1870 .name = "mailbox", 1577 .name = "mailbox",
1871 .class = &omap44xx_mailbox_hwmod_class, 1578 .class = &omap44xx_mailbox_hwmod_class,
1872 .clkdm_name = "l4_cfg_clkdm", 1579 .clkdm_name = "l4_cfg_clkdm",
1873 .mpu_irqs = omap44xx_mailbox_irqs,
1874 .prcm = { 1580 .prcm = {
1875 .omap4 = { 1581 .omap4 = {
1876 .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET, 1582 .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
@@ -1903,24 +1609,10 @@ static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1903}; 1609};
1904 1610
1905/* mcasp */ 1611/* mcasp */
1906static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
1907 { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
1908 { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
1909 { .irq = -1 }
1910};
1911
1912static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
1913 { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
1914 { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
1915 { .dma_req = -1 }
1916};
1917
1918static struct omap_hwmod omap44xx_mcasp_hwmod = { 1612static struct omap_hwmod omap44xx_mcasp_hwmod = {
1919 .name = "mcasp", 1613 .name = "mcasp",
1920 .class = &omap44xx_mcasp_hwmod_class, 1614 .class = &omap44xx_mcasp_hwmod_class,
1921 .clkdm_name = "abe_clkdm", 1615 .clkdm_name = "abe_clkdm",
1922 .mpu_irqs = omap44xx_mcasp_irqs,
1923 .sdma_reqs = omap44xx_mcasp_sdma_reqs,
1924 .main_clk = "func_mcasp_abe_gfclk", 1616 .main_clk = "func_mcasp_abe_gfclk",
1925 .prcm = { 1617 .prcm = {
1926 .omap4 = { 1618 .omap4 = {
@@ -1951,17 +1643,6 @@ static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1951}; 1643};
1952 1644
1953/* mcbsp1 */ 1645/* mcbsp1 */
1954static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
1955 { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
1956 { .irq = -1 }
1957};
1958
1959static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
1960 { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
1961 { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
1962 { .dma_req = -1 }
1963};
1964
1965static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = { 1646static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1966 { .role = "pad_fck", .clk = "pad_clks_ck" }, 1647 { .role = "pad_fck", .clk = "pad_clks_ck" },
1967 { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" }, 1648 { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
@@ -1971,8 +1652,6 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1971 .name = "mcbsp1", 1652 .name = "mcbsp1",
1972 .class = &omap44xx_mcbsp_hwmod_class, 1653 .class = &omap44xx_mcbsp_hwmod_class,
1973 .clkdm_name = "abe_clkdm", 1654 .clkdm_name = "abe_clkdm",
1974 .mpu_irqs = omap44xx_mcbsp1_irqs,
1975 .sdma_reqs = omap44xx_mcbsp1_sdma_reqs,
1976 .main_clk = "func_mcbsp1_gfclk", 1655 .main_clk = "func_mcbsp1_gfclk",
1977 .prcm = { 1656 .prcm = {
1978 .omap4 = { 1657 .omap4 = {
@@ -1986,17 +1665,6 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1986}; 1665};
1987 1666
1988/* mcbsp2 */ 1667/* mcbsp2 */
1989static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
1990 { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
1991 { .irq = -1 }
1992};
1993
1994static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
1995 { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
1996 { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
1997 { .dma_req = -1 }
1998};
1999
2000static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = { 1668static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
2001 { .role = "pad_fck", .clk = "pad_clks_ck" }, 1669 { .role = "pad_fck", .clk = "pad_clks_ck" },
2002 { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" }, 1670 { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
@@ -2006,8 +1674,6 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2006 .name = "mcbsp2", 1674 .name = "mcbsp2",
2007 .class = &omap44xx_mcbsp_hwmod_class, 1675 .class = &omap44xx_mcbsp_hwmod_class,
2008 .clkdm_name = "abe_clkdm", 1676 .clkdm_name = "abe_clkdm",
2009 .mpu_irqs = omap44xx_mcbsp2_irqs,
2010 .sdma_reqs = omap44xx_mcbsp2_sdma_reqs,
2011 .main_clk = "func_mcbsp2_gfclk", 1677 .main_clk = "func_mcbsp2_gfclk",
2012 .prcm = { 1678 .prcm = {
2013 .omap4 = { 1679 .omap4 = {
@@ -2021,17 +1687,6 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2021}; 1687};
2022 1688
2023/* mcbsp3 */ 1689/* mcbsp3 */
2024static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2025 { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
2026 { .irq = -1 }
2027};
2028
2029static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2030 { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2031 { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2032 { .dma_req = -1 }
2033};
2034
2035static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = { 1690static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
2036 { .role = "pad_fck", .clk = "pad_clks_ck" }, 1691 { .role = "pad_fck", .clk = "pad_clks_ck" },
2037 { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" }, 1692 { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
@@ -2041,8 +1696,6 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2041 .name = "mcbsp3", 1696 .name = "mcbsp3",
2042 .class = &omap44xx_mcbsp_hwmod_class, 1697 .class = &omap44xx_mcbsp_hwmod_class,
2043 .clkdm_name = "abe_clkdm", 1698 .clkdm_name = "abe_clkdm",
2044 .mpu_irqs = omap44xx_mcbsp3_irqs,
2045 .sdma_reqs = omap44xx_mcbsp3_sdma_reqs,
2046 .main_clk = "func_mcbsp3_gfclk", 1699 .main_clk = "func_mcbsp3_gfclk",
2047 .prcm = { 1700 .prcm = {
2048 .omap4 = { 1701 .omap4 = {
@@ -2056,17 +1709,6 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2056}; 1709};
2057 1710
2058/* mcbsp4 */ 1711/* mcbsp4 */
2059static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2060 { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
2061 { .irq = -1 }
2062};
2063
2064static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2065 { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2066 { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2067 { .dma_req = -1 }
2068};
2069
2070static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = { 1712static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
2071 { .role = "pad_fck", .clk = "pad_clks_ck" }, 1713 { .role = "pad_fck", .clk = "pad_clks_ck" },
2072 { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" }, 1714 { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
@@ -2076,8 +1718,6 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2076 .name = "mcbsp4", 1718 .name = "mcbsp4",
2077 .class = &omap44xx_mcbsp_hwmod_class, 1719 .class = &omap44xx_mcbsp_hwmod_class,
2078 .clkdm_name = "l4_per_clkdm", 1720 .clkdm_name = "l4_per_clkdm",
2079 .mpu_irqs = omap44xx_mcbsp4_irqs,
2080 .sdma_reqs = omap44xx_mcbsp4_sdma_reqs,
2081 .main_clk = "per_mcbsp4_gfclk", 1721 .main_clk = "per_mcbsp4_gfclk",
2082 .prcm = { 1722 .prcm = {
2083 .omap4 = { 1723 .omap4 = {
@@ -2112,17 +1752,6 @@ static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
2112}; 1752};
2113 1753
2114/* mcpdm */ 1754/* mcpdm */
2115static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
2116 { .irq = 112 + OMAP44XX_IRQ_GIC_START },
2117 { .irq = -1 }
2118};
2119
2120static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
2121 { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
2122 { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
2123 { .dma_req = -1 }
2124};
2125
2126static struct omap_hwmod omap44xx_mcpdm_hwmod = { 1755static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2127 .name = "mcpdm", 1756 .name = "mcpdm",
2128 .class = &omap44xx_mcpdm_hwmod_class, 1757 .class = &omap44xx_mcpdm_hwmod_class,
@@ -2139,8 +1768,6 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2139 * results 'slow motion' audio playback. 1768 * results 'slow motion' audio playback.
2140 */ 1769 */
2141 .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE, 1770 .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
2142 .mpu_irqs = omap44xx_mcpdm_irqs,
2143 .sdma_reqs = omap44xx_mcpdm_sdma_reqs,
2144 .main_clk = "pad_clks_ck", 1771 .main_clk = "pad_clks_ck",
2145 .prcm = { 1772 .prcm = {
2146 .omap4 = { 1773 .omap4 = {
@@ -2174,11 +1801,6 @@ static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
2174}; 1801};
2175 1802
2176/* mcspi1 */ 1803/* mcspi1 */
2177static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
2178 { .irq = 65 + OMAP44XX_IRQ_GIC_START },
2179 { .irq = -1 }
2180};
2181
2182static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = { 1804static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
2183 { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START }, 1805 { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
2184 { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START }, 1806 { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
@@ -2200,7 +1822,6 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2200 .name = "mcspi1", 1822 .name = "mcspi1",
2201 .class = &omap44xx_mcspi_hwmod_class, 1823 .class = &omap44xx_mcspi_hwmod_class,
2202 .clkdm_name = "l4_per_clkdm", 1824 .clkdm_name = "l4_per_clkdm",
2203 .mpu_irqs = omap44xx_mcspi1_irqs,
2204 .sdma_reqs = omap44xx_mcspi1_sdma_reqs, 1825 .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
2205 .main_clk = "func_48m_fclk", 1826 .main_clk = "func_48m_fclk",
2206 .prcm = { 1827 .prcm = {
@@ -2214,11 +1835,6 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2214}; 1835};
2215 1836
2216/* mcspi2 */ 1837/* mcspi2 */
2217static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
2218 { .irq = 66 + OMAP44XX_IRQ_GIC_START },
2219 { .irq = -1 }
2220};
2221
2222static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = { 1838static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
2223 { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START }, 1839 { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
2224 { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START }, 1840 { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
@@ -2236,7 +1852,6 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2236 .name = "mcspi2", 1852 .name = "mcspi2",
2237 .class = &omap44xx_mcspi_hwmod_class, 1853 .class = &omap44xx_mcspi_hwmod_class,
2238 .clkdm_name = "l4_per_clkdm", 1854 .clkdm_name = "l4_per_clkdm",
2239 .mpu_irqs = omap44xx_mcspi2_irqs,
2240 .sdma_reqs = omap44xx_mcspi2_sdma_reqs, 1855 .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
2241 .main_clk = "func_48m_fclk", 1856 .main_clk = "func_48m_fclk",
2242 .prcm = { 1857 .prcm = {
@@ -2250,11 +1865,6 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2250}; 1865};
2251 1866
2252/* mcspi3 */ 1867/* mcspi3 */
2253static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
2254 { .irq = 91 + OMAP44XX_IRQ_GIC_START },
2255 { .irq = -1 }
2256};
2257
2258static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = { 1868static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2259 { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START }, 1869 { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2260 { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START }, 1870 { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
@@ -2272,7 +1882,6 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2272 .name = "mcspi3", 1882 .name = "mcspi3",
2273 .class = &omap44xx_mcspi_hwmod_class, 1883 .class = &omap44xx_mcspi_hwmod_class,
2274 .clkdm_name = "l4_per_clkdm", 1884 .clkdm_name = "l4_per_clkdm",
2275 .mpu_irqs = omap44xx_mcspi3_irqs,
2276 .sdma_reqs = omap44xx_mcspi3_sdma_reqs, 1885 .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
2277 .main_clk = "func_48m_fclk", 1886 .main_clk = "func_48m_fclk",
2278 .prcm = { 1887 .prcm = {
@@ -2286,11 +1895,6 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2286}; 1895};
2287 1896
2288/* mcspi4 */ 1897/* mcspi4 */
2289static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
2290 { .irq = 48 + OMAP44XX_IRQ_GIC_START },
2291 { .irq = -1 }
2292};
2293
2294static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = { 1898static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
2295 { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START }, 1899 { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
2296 { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START }, 1900 { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
@@ -2306,7 +1910,6 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2306 .name = "mcspi4", 1910 .name = "mcspi4",
2307 .class = &omap44xx_mcspi_hwmod_class, 1911 .class = &omap44xx_mcspi_hwmod_class,
2308 .clkdm_name = "l4_per_clkdm", 1912 .clkdm_name = "l4_per_clkdm",
2309 .mpu_irqs = omap44xx_mcspi4_irqs,
2310 .sdma_reqs = omap44xx_mcspi4_sdma_reqs, 1913 .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
2311 .main_clk = "func_48m_fclk", 1914 .main_clk = "func_48m_fclk",
2312 .prcm = { 1915 .prcm = {
@@ -2342,11 +1945,6 @@ static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
2342}; 1945};
2343 1946
2344/* mmc1 */ 1947/* mmc1 */
2345static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
2346 { .irq = 83 + OMAP44XX_IRQ_GIC_START },
2347 { .irq = -1 }
2348};
2349
2350static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = { 1948static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
2351 { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START }, 1949 { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
2352 { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START }, 1950 { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
@@ -2362,7 +1960,6 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
2362 .name = "mmc1", 1960 .name = "mmc1",
2363 .class = &omap44xx_mmc_hwmod_class, 1961 .class = &omap44xx_mmc_hwmod_class,
2364 .clkdm_name = "l3_init_clkdm", 1962 .clkdm_name = "l3_init_clkdm",
2365 .mpu_irqs = omap44xx_mmc1_irqs,
2366 .sdma_reqs = omap44xx_mmc1_sdma_reqs, 1963 .sdma_reqs = omap44xx_mmc1_sdma_reqs,
2367 .main_clk = "hsmmc1_fclk", 1964 .main_clk = "hsmmc1_fclk",
2368 .prcm = { 1965 .prcm = {
@@ -2376,11 +1973,6 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
2376}; 1973};
2377 1974
2378/* mmc2 */ 1975/* mmc2 */
2379static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
2380 { .irq = 86 + OMAP44XX_IRQ_GIC_START },
2381 { .irq = -1 }
2382};
2383
2384static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = { 1976static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
2385 { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START }, 1977 { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
2386 { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START }, 1978 { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
@@ -2391,7 +1983,6 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
2391 .name = "mmc2", 1983 .name = "mmc2",
2392 .class = &omap44xx_mmc_hwmod_class, 1984 .class = &omap44xx_mmc_hwmod_class,
2393 .clkdm_name = "l3_init_clkdm", 1985 .clkdm_name = "l3_init_clkdm",
2394 .mpu_irqs = omap44xx_mmc2_irqs,
2395 .sdma_reqs = omap44xx_mmc2_sdma_reqs, 1986 .sdma_reqs = omap44xx_mmc2_sdma_reqs,
2396 .main_clk = "hsmmc2_fclk", 1987 .main_clk = "hsmmc2_fclk",
2397 .prcm = { 1988 .prcm = {
@@ -2404,11 +1995,6 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
2404}; 1995};
2405 1996
2406/* mmc3 */ 1997/* mmc3 */
2407static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
2408 { .irq = 94 + OMAP44XX_IRQ_GIC_START },
2409 { .irq = -1 }
2410};
2411
2412static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = { 1998static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2413 { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START }, 1999 { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2414 { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START }, 2000 { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
@@ -2419,7 +2005,6 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
2419 .name = "mmc3", 2005 .name = "mmc3",
2420 .class = &omap44xx_mmc_hwmod_class, 2006 .class = &omap44xx_mmc_hwmod_class,
2421 .clkdm_name = "l4_per_clkdm", 2007 .clkdm_name = "l4_per_clkdm",
2422 .mpu_irqs = omap44xx_mmc3_irqs,
2423 .sdma_reqs = omap44xx_mmc3_sdma_reqs, 2008 .sdma_reqs = omap44xx_mmc3_sdma_reqs,
2424 .main_clk = "func_48m_fclk", 2009 .main_clk = "func_48m_fclk",
2425 .prcm = { 2010 .prcm = {
@@ -2432,11 +2017,6 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
2432}; 2017};
2433 2018
2434/* mmc4 */ 2019/* mmc4 */
2435static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
2436 { .irq = 96 + OMAP44XX_IRQ_GIC_START },
2437 { .irq = -1 }
2438};
2439
2440static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = { 2020static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2441 { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START }, 2021 { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2442 { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START }, 2022 { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
@@ -2447,7 +2027,6 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
2447 .name = "mmc4", 2027 .name = "mmc4",
2448 .class = &omap44xx_mmc_hwmod_class, 2028 .class = &omap44xx_mmc_hwmod_class,
2449 .clkdm_name = "l4_per_clkdm", 2029 .clkdm_name = "l4_per_clkdm",
2450 .mpu_irqs = omap44xx_mmc4_irqs,
2451 .sdma_reqs = omap44xx_mmc4_sdma_reqs, 2030 .sdma_reqs = omap44xx_mmc4_sdma_reqs,
2452 .main_clk = "func_48m_fclk", 2031 .main_clk = "func_48m_fclk",
2453 .prcm = { 2032 .prcm = {
@@ -2460,11 +2039,6 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
2460}; 2039};
2461 2040
2462/* mmc5 */ 2041/* mmc5 */
2463static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
2464 { .irq = 59 + OMAP44XX_IRQ_GIC_START },
2465 { .irq = -1 }
2466};
2467
2468static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = { 2042static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2469 { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START }, 2043 { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2470 { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START }, 2044 { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
@@ -2475,7 +2049,6 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = {
2475 .name = "mmc5", 2049 .name = "mmc5",
2476 .class = &omap44xx_mmc_hwmod_class, 2050 .class = &omap44xx_mmc_hwmod_class,
2477 .clkdm_name = "l4_per_clkdm", 2051 .clkdm_name = "l4_per_clkdm",
2478 .mpu_irqs = omap44xx_mmc5_irqs,
2479 .sdma_reqs = omap44xx_mmc5_sdma_reqs, 2052 .sdma_reqs = omap44xx_mmc5_sdma_reqs,
2480 .main_clk = "func_48m_fclk", 2053 .main_clk = "func_48m_fclk",
2481 .prcm = { 2054 .prcm = {
@@ -2517,11 +2090,6 @@ static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
2517}; 2090};
2518 2091
2519static struct omap_hwmod omap44xx_mmu_ipu_hwmod; 2092static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
2520static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = {
2521 { .irq = 100 + OMAP44XX_IRQ_GIC_START, },
2522 { .irq = -1 }
2523};
2524
2525static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = { 2093static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
2526 { .name = "mmu_cache", .rst_shift = 2 }, 2094 { .name = "mmu_cache", .rst_shift = 2 },
2527}; 2095};
@@ -2548,7 +2116,6 @@ static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
2548 .name = "mmu_ipu", 2116 .name = "mmu_ipu",
2549 .class = &omap44xx_mmu_hwmod_class, 2117 .class = &omap44xx_mmu_hwmod_class,
2550 .clkdm_name = "ducati_clkdm", 2118 .clkdm_name = "ducati_clkdm",
2551 .mpu_irqs = omap44xx_mmu_ipu_irqs,
2552 .rst_lines = omap44xx_mmu_ipu_resets, 2119 .rst_lines = omap44xx_mmu_ipu_resets,
2553 .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_ipu_resets), 2120 .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
2554 .main_clk = "ducati_clk_mux_ck", 2121 .main_clk = "ducati_clk_mux_ck",
@@ -2572,11 +2139,6 @@ static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
2572}; 2139};
2573 2140
2574static struct omap_hwmod omap44xx_mmu_dsp_hwmod; 2141static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
2575static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = {
2576 { .irq = 28 + OMAP44XX_IRQ_GIC_START },
2577 { .irq = -1 }
2578};
2579
2580static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = { 2142static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
2581 { .name = "mmu_cache", .rst_shift = 1 }, 2143 { .name = "mmu_cache", .rst_shift = 1 },
2582}; 2144};
@@ -2603,7 +2165,6 @@ static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
2603 .name = "mmu_dsp", 2165 .name = "mmu_dsp",
2604 .class = &omap44xx_mmu_hwmod_class, 2166 .class = &omap44xx_mmu_hwmod_class,
2605 .clkdm_name = "tesla_clkdm", 2167 .clkdm_name = "tesla_clkdm",
2606 .mpu_irqs = omap44xx_mmu_dsp_irqs,
2607 .rst_lines = omap44xx_mmu_dsp_resets, 2168 .rst_lines = omap44xx_mmu_dsp_resets,
2608 .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_dsp_resets), 2169 .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
2609 .main_clk = "dpll_iva_m4x2_ck", 2170 .main_clk = "dpll_iva_m4x2_ck",
@@ -2628,21 +2189,11 @@ static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2628}; 2189};
2629 2190
2630/* mpu */ 2191/* mpu */
2631static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
2632 { .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START },
2633 { .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START },
2634 { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
2635 { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
2636 { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
2637 { .irq = -1 }
2638};
2639
2640static struct omap_hwmod omap44xx_mpu_hwmod = { 2192static struct omap_hwmod omap44xx_mpu_hwmod = {
2641 .name = "mpu", 2193 .name = "mpu",
2642 .class = &omap44xx_mpu_hwmod_class, 2194 .class = &omap44xx_mpu_hwmod_class,
2643 .clkdm_name = "mpuss_clkdm", 2195 .clkdm_name = "mpuss_clkdm",
2644 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, 2196 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2645 .mpu_irqs = omap44xx_mpu_irqs,
2646 .main_clk = "dpll_mpu_m2_ck", 2197 .main_clk = "dpll_mpu_m2_ck",
2647 .prcm = { 2198 .prcm = {
2648 .omap4 = { 2199 .omap4 = {
@@ -2695,25 +2246,6 @@ static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2695 .sysc = &omap44xx_ocp2scp_sysc, 2246 .sysc = &omap44xx_ocp2scp_sysc,
2696}; 2247};
2697 2248
2698/* ocp2scp dev_attr */
2699static struct resource omap44xx_usb_phy_and_pll_addrs[] = {
2700 {
2701 .name = "usb_phy",
2702 .start = 0x4a0ad080,
2703 .end = 0x4a0ae000,
2704 .flags = IORESOURCE_MEM,
2705 },
2706 { }
2707};
2708
2709static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = {
2710 {
2711 .drv_name = "omap-usb2",
2712 .res = omap44xx_usb_phy_and_pll_addrs,
2713 },
2714 { }
2715};
2716
2717/* ocp2scp_usb_phy */ 2249/* ocp2scp_usb_phy */
2718static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { 2250static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2719 .name = "ocp2scp_usb_phy", 2251 .name = "ocp2scp_usb_phy",
@@ -2737,7 +2269,6 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2737 .modulemode = MODULEMODE_HWCTRL, 2269 .modulemode = MODULEMODE_HWCTRL,
2738 }, 2270 },
2739 }, 2271 },
2740 .dev_attr = ocp2scp_dev_attr,
2741}; 2272};
2742 2273
2743/* 2274/*
@@ -2788,11 +2319,6 @@ static struct omap_hwmod omap44xx_cm_core_hwmod = {
2788}; 2319};
2789 2320
2790/* prm */ 2321/* prm */
2791static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
2792 { .irq = 11 + OMAP44XX_IRQ_GIC_START },
2793 { .irq = -1 }
2794};
2795
2796static struct omap_hwmod_rst_info omap44xx_prm_resets[] = { 2322static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2797 { .name = "rst_global_warm_sw", .rst_shift = 0 }, 2323 { .name = "rst_global_warm_sw", .rst_shift = 0 },
2798 { .name = "rst_global_cold_sw", .rst_shift = 1 }, 2324 { .name = "rst_global_cold_sw", .rst_shift = 1 },
@@ -2801,7 +2327,6 @@ static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2801static struct omap_hwmod omap44xx_prm_hwmod = { 2327static struct omap_hwmod omap44xx_prm_hwmod = {
2802 .name = "prm", 2328 .name = "prm",
2803 .class = &omap44xx_prcm_hwmod_class, 2329 .class = &omap44xx_prcm_hwmod_class,
2804 .mpu_irqs = omap44xx_prm_irqs,
2805 .rst_lines = omap44xx_prm_resets, 2330 .rst_lines = omap44xx_prm_resets,
2806 .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets), 2331 .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets),
2807}; 2332};
@@ -2872,23 +2397,6 @@ static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2872}; 2397};
2873 2398
2874/* slimbus1 */ 2399/* slimbus1 */
2875static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
2876 { .irq = 97 + OMAP44XX_IRQ_GIC_START },
2877 { .irq = -1 }
2878};
2879
2880static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
2881 { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
2882 { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
2883 { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
2884 { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
2885 { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
2886 { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
2887 { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
2888 { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
2889 { .dma_req = -1 }
2890};
2891
2892static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = { 2400static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2893 { .role = "fclk_1", .clk = "slimbus1_fclk_1" }, 2401 { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2894 { .role = "fclk_0", .clk = "slimbus1_fclk_0" }, 2402 { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
@@ -2900,8 +2408,6 @@ static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2900 .name = "slimbus1", 2408 .name = "slimbus1",
2901 .class = &omap44xx_slimbus_hwmod_class, 2409 .class = &omap44xx_slimbus_hwmod_class,
2902 .clkdm_name = "abe_clkdm", 2410 .clkdm_name = "abe_clkdm",
2903 .mpu_irqs = omap44xx_slimbus1_irqs,
2904 .sdma_reqs = omap44xx_slimbus1_sdma_reqs,
2905 .prcm = { 2411 .prcm = {
2906 .omap4 = { 2412 .omap4 = {
2907 .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET, 2413 .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
@@ -2914,23 +2420,6 @@ static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2914}; 2420};
2915 2421
2916/* slimbus2 */ 2422/* slimbus2 */
2917static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
2918 { .irq = 98 + OMAP44XX_IRQ_GIC_START },
2919 { .irq = -1 }
2920};
2921
2922static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
2923 { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
2924 { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
2925 { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
2926 { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
2927 { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
2928 { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
2929 { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
2930 { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
2931 { .dma_req = -1 }
2932};
2933
2934static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = { 2423static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2935 { .role = "fclk_1", .clk = "slimbus2_fclk_1" }, 2424 { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2936 { .role = "fclk_0", .clk = "slimbus2_fclk_0" }, 2425 { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
@@ -2941,8 +2430,6 @@ static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2941 .name = "slimbus2", 2430 .name = "slimbus2",
2942 .class = &omap44xx_slimbus_hwmod_class, 2431 .class = &omap44xx_slimbus_hwmod_class,
2943 .clkdm_name = "l4_per_clkdm", 2432 .clkdm_name = "l4_per_clkdm",
2944 .mpu_irqs = omap44xx_slimbus2_irqs,
2945 .sdma_reqs = omap44xx_slimbus2_sdma_reqs,
2946 .prcm = { 2433 .prcm = {
2947 .omap4 = { 2434 .omap4 = {
2948 .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET, 2435 .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
@@ -2985,16 +2472,10 @@ static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2985 .sensor_voltdm_name = "core", 2472 .sensor_voltdm_name = "core",
2986}; 2473};
2987 2474
2988static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
2989 { .irq = 19 + OMAP44XX_IRQ_GIC_START },
2990 { .irq = -1 }
2991};
2992
2993static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { 2475static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2994 .name = "smartreflex_core", 2476 .name = "smartreflex_core",
2995 .class = &omap44xx_smartreflex_hwmod_class, 2477 .class = &omap44xx_smartreflex_hwmod_class,
2996 .clkdm_name = "l4_ao_clkdm", 2478 .clkdm_name = "l4_ao_clkdm",
2997 .mpu_irqs = omap44xx_smartreflex_core_irqs,
2998 2479
2999 .main_clk = "smartreflex_core_fck", 2480 .main_clk = "smartreflex_core_fck",
3000 .prcm = { 2481 .prcm = {
@@ -3012,16 +2493,10 @@ static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
3012 .sensor_voltdm_name = "iva", 2493 .sensor_voltdm_name = "iva",
3013}; 2494};
3014 2495
3015static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
3016 { .irq = 102 + OMAP44XX_IRQ_GIC_START },
3017 { .irq = -1 }
3018};
3019
3020static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { 2496static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
3021 .name = "smartreflex_iva", 2497 .name = "smartreflex_iva",
3022 .class = &omap44xx_smartreflex_hwmod_class, 2498 .class = &omap44xx_smartreflex_hwmod_class,
3023 .clkdm_name = "l4_ao_clkdm", 2499 .clkdm_name = "l4_ao_clkdm",
3024 .mpu_irqs = omap44xx_smartreflex_iva_irqs,
3025 .main_clk = "smartreflex_iva_fck", 2500 .main_clk = "smartreflex_iva_fck",
3026 .prcm = { 2501 .prcm = {
3027 .omap4 = { 2502 .omap4 = {
@@ -3038,16 +2513,10 @@ static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
3038 .sensor_voltdm_name = "mpu", 2513 .sensor_voltdm_name = "mpu",
3039}; 2514};
3040 2515
3041static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
3042 { .irq = 18 + OMAP44XX_IRQ_GIC_START },
3043 { .irq = -1 }
3044};
3045
3046static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { 2516static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3047 .name = "smartreflex_mpu", 2517 .name = "smartreflex_mpu",
3048 .class = &omap44xx_smartreflex_hwmod_class, 2518 .class = &omap44xx_smartreflex_hwmod_class,
3049 .clkdm_name = "l4_ao_clkdm", 2519 .clkdm_name = "l4_ao_clkdm",
3050 .mpu_irqs = omap44xx_smartreflex_mpu_irqs,
3051 .main_clk = "smartreflex_mpu_fck", 2520 .main_clk = "smartreflex_mpu_fck",
3052 .prcm = { 2521 .prcm = {
3053 .omap4 = { 2522 .omap4 = {
@@ -3155,17 +2624,11 @@ static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
3155}; 2624};
3156 2625
3157/* timer1 */ 2626/* timer1 */
3158static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
3159 { .irq = 37 + OMAP44XX_IRQ_GIC_START },
3160 { .irq = -1 }
3161};
3162
3163static struct omap_hwmod omap44xx_timer1_hwmod = { 2627static struct omap_hwmod omap44xx_timer1_hwmod = {
3164 .name = "timer1", 2628 .name = "timer1",
3165 .class = &omap44xx_timer_1ms_hwmod_class, 2629 .class = &omap44xx_timer_1ms_hwmod_class,
3166 .clkdm_name = "l4_wkup_clkdm", 2630 .clkdm_name = "l4_wkup_clkdm",
3167 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 2631 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
3168 .mpu_irqs = omap44xx_timer1_irqs,
3169 .main_clk = "dmt1_clk_mux", 2632 .main_clk = "dmt1_clk_mux",
3170 .prcm = { 2633 .prcm = {
3171 .omap4 = { 2634 .omap4 = {
@@ -3178,17 +2641,11 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
3178}; 2641};
3179 2642
3180/* timer2 */ 2643/* timer2 */
3181static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
3182 { .irq = 38 + OMAP44XX_IRQ_GIC_START },
3183 { .irq = -1 }
3184};
3185
3186static struct omap_hwmod omap44xx_timer2_hwmod = { 2644static struct omap_hwmod omap44xx_timer2_hwmod = {
3187 .name = "timer2", 2645 .name = "timer2",
3188 .class = &omap44xx_timer_1ms_hwmod_class, 2646 .class = &omap44xx_timer_1ms_hwmod_class,
3189 .clkdm_name = "l4_per_clkdm", 2647 .clkdm_name = "l4_per_clkdm",
3190 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 2648 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
3191 .mpu_irqs = omap44xx_timer2_irqs,
3192 .main_clk = "cm2_dm2_mux", 2649 .main_clk = "cm2_dm2_mux",
3193 .prcm = { 2650 .prcm = {
3194 .omap4 = { 2651 .omap4 = {
@@ -3200,16 +2657,10 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
3200}; 2657};
3201 2658
3202/* timer3 */ 2659/* timer3 */
3203static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
3204 { .irq = 39 + OMAP44XX_IRQ_GIC_START },
3205 { .irq = -1 }
3206};
3207
3208static struct omap_hwmod omap44xx_timer3_hwmod = { 2660static struct omap_hwmod omap44xx_timer3_hwmod = {
3209 .name = "timer3", 2661 .name = "timer3",
3210 .class = &omap44xx_timer_hwmod_class, 2662 .class = &omap44xx_timer_hwmod_class,
3211 .clkdm_name = "l4_per_clkdm", 2663 .clkdm_name = "l4_per_clkdm",
3212 .mpu_irqs = omap44xx_timer3_irqs,
3213 .main_clk = "cm2_dm3_mux", 2664 .main_clk = "cm2_dm3_mux",
3214 .prcm = { 2665 .prcm = {
3215 .omap4 = { 2666 .omap4 = {
@@ -3221,16 +2672,10 @@ static struct omap_hwmod omap44xx_timer3_hwmod = {
3221}; 2672};
3222 2673
3223/* timer4 */ 2674/* timer4 */
3224static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
3225 { .irq = 40 + OMAP44XX_IRQ_GIC_START },
3226 { .irq = -1 }
3227};
3228
3229static struct omap_hwmod omap44xx_timer4_hwmod = { 2675static struct omap_hwmod omap44xx_timer4_hwmod = {
3230 .name = "timer4", 2676 .name = "timer4",
3231 .class = &omap44xx_timer_hwmod_class, 2677 .class = &omap44xx_timer_hwmod_class,
3232 .clkdm_name = "l4_per_clkdm", 2678 .clkdm_name = "l4_per_clkdm",
3233 .mpu_irqs = omap44xx_timer4_irqs,
3234 .main_clk = "cm2_dm4_mux", 2679 .main_clk = "cm2_dm4_mux",
3235 .prcm = { 2680 .prcm = {
3236 .omap4 = { 2681 .omap4 = {
@@ -3242,16 +2687,10 @@ static struct omap_hwmod omap44xx_timer4_hwmod = {
3242}; 2687};
3243 2688
3244/* timer5 */ 2689/* timer5 */
3245static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
3246 { .irq = 41 + OMAP44XX_IRQ_GIC_START },
3247 { .irq = -1 }
3248};
3249
3250static struct omap_hwmod omap44xx_timer5_hwmod = { 2690static struct omap_hwmod omap44xx_timer5_hwmod = {
3251 .name = "timer5", 2691 .name = "timer5",
3252 .class = &omap44xx_timer_hwmod_class, 2692 .class = &omap44xx_timer_hwmod_class,
3253 .clkdm_name = "abe_clkdm", 2693 .clkdm_name = "abe_clkdm",
3254 .mpu_irqs = omap44xx_timer5_irqs,
3255 .main_clk = "timer5_sync_mux", 2694 .main_clk = "timer5_sync_mux",
3256 .prcm = { 2695 .prcm = {
3257 .omap4 = { 2696 .omap4 = {
@@ -3264,16 +2703,10 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
3264}; 2703};
3265 2704
3266/* timer6 */ 2705/* timer6 */
3267static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
3268 { .irq = 42 + OMAP44XX_IRQ_GIC_START },
3269 { .irq = -1 }
3270};
3271
3272static struct omap_hwmod omap44xx_timer6_hwmod = { 2706static struct omap_hwmod omap44xx_timer6_hwmod = {
3273 .name = "timer6", 2707 .name = "timer6",
3274 .class = &omap44xx_timer_hwmod_class, 2708 .class = &omap44xx_timer_hwmod_class,
3275 .clkdm_name = "abe_clkdm", 2709 .clkdm_name = "abe_clkdm",
3276 .mpu_irqs = omap44xx_timer6_irqs,
3277 .main_clk = "timer6_sync_mux", 2710 .main_clk = "timer6_sync_mux",
3278 .prcm = { 2711 .prcm = {
3279 .omap4 = { 2712 .omap4 = {
@@ -3286,16 +2719,10 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
3286}; 2719};
3287 2720
3288/* timer7 */ 2721/* timer7 */
3289static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
3290 { .irq = 43 + OMAP44XX_IRQ_GIC_START },
3291 { .irq = -1 }
3292};
3293
3294static struct omap_hwmod omap44xx_timer7_hwmod = { 2722static struct omap_hwmod omap44xx_timer7_hwmod = {
3295 .name = "timer7", 2723 .name = "timer7",
3296 .class = &omap44xx_timer_hwmod_class, 2724 .class = &omap44xx_timer_hwmod_class,
3297 .clkdm_name = "abe_clkdm", 2725 .clkdm_name = "abe_clkdm",
3298 .mpu_irqs = omap44xx_timer7_irqs,
3299 .main_clk = "timer7_sync_mux", 2726 .main_clk = "timer7_sync_mux",
3300 .prcm = { 2727 .prcm = {
3301 .omap4 = { 2728 .omap4 = {
@@ -3308,16 +2735,10 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
3308}; 2735};
3309 2736
3310/* timer8 */ 2737/* timer8 */
3311static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
3312 { .irq = 44 + OMAP44XX_IRQ_GIC_START },
3313 { .irq = -1 }
3314};
3315
3316static struct omap_hwmod omap44xx_timer8_hwmod = { 2738static struct omap_hwmod omap44xx_timer8_hwmod = {
3317 .name = "timer8", 2739 .name = "timer8",
3318 .class = &omap44xx_timer_hwmod_class, 2740 .class = &omap44xx_timer_hwmod_class,
3319 .clkdm_name = "abe_clkdm", 2741 .clkdm_name = "abe_clkdm",
3320 .mpu_irqs = omap44xx_timer8_irqs,
3321 .main_clk = "timer8_sync_mux", 2742 .main_clk = "timer8_sync_mux",
3322 .prcm = { 2743 .prcm = {
3323 .omap4 = { 2744 .omap4 = {
@@ -3330,16 +2751,10 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
3330}; 2751};
3331 2752
3332/* timer9 */ 2753/* timer9 */
3333static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
3334 { .irq = 45 + OMAP44XX_IRQ_GIC_START },
3335 { .irq = -1 }
3336};
3337
3338static struct omap_hwmod omap44xx_timer9_hwmod = { 2754static struct omap_hwmod omap44xx_timer9_hwmod = {
3339 .name = "timer9", 2755 .name = "timer9",
3340 .class = &omap44xx_timer_hwmod_class, 2756 .class = &omap44xx_timer_hwmod_class,
3341 .clkdm_name = "l4_per_clkdm", 2757 .clkdm_name = "l4_per_clkdm",
3342 .mpu_irqs = omap44xx_timer9_irqs,
3343 .main_clk = "cm2_dm9_mux", 2758 .main_clk = "cm2_dm9_mux",
3344 .prcm = { 2759 .prcm = {
3345 .omap4 = { 2760 .omap4 = {
@@ -3352,17 +2767,11 @@ static struct omap_hwmod omap44xx_timer9_hwmod = {
3352}; 2767};
3353 2768
3354/* timer10 */ 2769/* timer10 */
3355static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
3356 { .irq = 46 + OMAP44XX_IRQ_GIC_START },
3357 { .irq = -1 }
3358};
3359
3360static struct omap_hwmod omap44xx_timer10_hwmod = { 2770static struct omap_hwmod omap44xx_timer10_hwmod = {
3361 .name = "timer10", 2771 .name = "timer10",
3362 .class = &omap44xx_timer_1ms_hwmod_class, 2772 .class = &omap44xx_timer_1ms_hwmod_class,
3363 .clkdm_name = "l4_per_clkdm", 2773 .clkdm_name = "l4_per_clkdm",
3364 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 2774 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
3365 .mpu_irqs = omap44xx_timer10_irqs,
3366 .main_clk = "cm2_dm10_mux", 2775 .main_clk = "cm2_dm10_mux",
3367 .prcm = { 2776 .prcm = {
3368 .omap4 = { 2777 .omap4 = {
@@ -3375,16 +2784,10 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
3375}; 2784};
3376 2785
3377/* timer11 */ 2786/* timer11 */
3378static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
3379 { .irq = 47 + OMAP44XX_IRQ_GIC_START },
3380 { .irq = -1 }
3381};
3382
3383static struct omap_hwmod omap44xx_timer11_hwmod = { 2787static struct omap_hwmod omap44xx_timer11_hwmod = {
3384 .name = "timer11", 2788 .name = "timer11",
3385 .class = &omap44xx_timer_hwmod_class, 2789 .class = &omap44xx_timer_hwmod_class,
3386 .clkdm_name = "l4_per_clkdm", 2790 .clkdm_name = "l4_per_clkdm",
3387 .mpu_irqs = omap44xx_timer11_irqs,
3388 .main_clk = "cm2_dm11_mux", 2791 .main_clk = "cm2_dm11_mux",
3389 .prcm = { 2792 .prcm = {
3390 .omap4 = { 2793 .omap4 = {
@@ -3419,24 +2822,11 @@ static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
3419}; 2822};
3420 2823
3421/* uart1 */ 2824/* uart1 */
3422static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
3423 { .irq = 72 + OMAP44XX_IRQ_GIC_START },
3424 { .irq = -1 }
3425};
3426
3427static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
3428 { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
3429 { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
3430 { .dma_req = -1 }
3431};
3432
3433static struct omap_hwmod omap44xx_uart1_hwmod = { 2825static struct omap_hwmod omap44xx_uart1_hwmod = {
3434 .name = "uart1", 2826 .name = "uart1",
3435 .class = &omap44xx_uart_hwmod_class, 2827 .class = &omap44xx_uart_hwmod_class,
3436 .clkdm_name = "l4_per_clkdm", 2828 .clkdm_name = "l4_per_clkdm",
3437 .flags = HWMOD_SWSUP_SIDLE_ACT, 2829 .flags = HWMOD_SWSUP_SIDLE_ACT,
3438 .mpu_irqs = omap44xx_uart1_irqs,
3439 .sdma_reqs = omap44xx_uart1_sdma_reqs,
3440 .main_clk = "func_48m_fclk", 2830 .main_clk = "func_48m_fclk",
3441 .prcm = { 2831 .prcm = {
3442 .omap4 = { 2832 .omap4 = {
@@ -3448,24 +2838,11 @@ static struct omap_hwmod omap44xx_uart1_hwmod = {
3448}; 2838};
3449 2839
3450/* uart2 */ 2840/* uart2 */
3451static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
3452 { .irq = 73 + OMAP44XX_IRQ_GIC_START },
3453 { .irq = -1 }
3454};
3455
3456static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
3457 { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
3458 { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
3459 { .dma_req = -1 }
3460};
3461
3462static struct omap_hwmod omap44xx_uart2_hwmod = { 2841static struct omap_hwmod omap44xx_uart2_hwmod = {
3463 .name = "uart2", 2842 .name = "uart2",
3464 .class = &omap44xx_uart_hwmod_class, 2843 .class = &omap44xx_uart_hwmod_class,
3465 .clkdm_name = "l4_per_clkdm", 2844 .clkdm_name = "l4_per_clkdm",
3466 .flags = HWMOD_SWSUP_SIDLE_ACT, 2845 .flags = HWMOD_SWSUP_SIDLE_ACT,
3467 .mpu_irqs = omap44xx_uart2_irqs,
3468 .sdma_reqs = omap44xx_uart2_sdma_reqs,
3469 .main_clk = "func_48m_fclk", 2846 .main_clk = "func_48m_fclk",
3470 .prcm = { 2847 .prcm = {
3471 .omap4 = { 2848 .omap4 = {
@@ -3477,25 +2854,11 @@ static struct omap_hwmod omap44xx_uart2_hwmod = {
3477}; 2854};
3478 2855
3479/* uart3 */ 2856/* uart3 */
3480static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
3481 { .irq = 74 + OMAP44XX_IRQ_GIC_START },
3482 { .irq = -1 }
3483};
3484
3485static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
3486 { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
3487 { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
3488 { .dma_req = -1 }
3489};
3490
3491static struct omap_hwmod omap44xx_uart3_hwmod = { 2857static struct omap_hwmod omap44xx_uart3_hwmod = {
3492 .name = "uart3", 2858 .name = "uart3",
3493 .class = &omap44xx_uart_hwmod_class, 2859 .class = &omap44xx_uart_hwmod_class,
3494 .clkdm_name = "l4_per_clkdm", 2860 .clkdm_name = "l4_per_clkdm",
3495 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET | 2861 .flags = DEBUG_OMAP4UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
3496 HWMOD_SWSUP_SIDLE_ACT,
3497 .mpu_irqs = omap44xx_uart3_irqs,
3498 .sdma_reqs = omap44xx_uart3_sdma_reqs,
3499 .main_clk = "func_48m_fclk", 2862 .main_clk = "func_48m_fclk",
3500 .prcm = { 2863 .prcm = {
3501 .omap4 = { 2864 .omap4 = {
@@ -3507,24 +2870,11 @@ static struct omap_hwmod omap44xx_uart3_hwmod = {
3507}; 2870};
3508 2871
3509/* uart4 */ 2872/* uart4 */
3510static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
3511 { .irq = 70 + OMAP44XX_IRQ_GIC_START },
3512 { .irq = -1 }
3513};
3514
3515static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
3516 { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
3517 { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
3518 { .dma_req = -1 }
3519};
3520
3521static struct omap_hwmod omap44xx_uart4_hwmod = { 2873static struct omap_hwmod omap44xx_uart4_hwmod = {
3522 .name = "uart4", 2874 .name = "uart4",
3523 .class = &omap44xx_uart_hwmod_class, 2875 .class = &omap44xx_uart_hwmod_class,
3524 .clkdm_name = "l4_per_clkdm", 2876 .clkdm_name = "l4_per_clkdm",
3525 .flags = HWMOD_SWSUP_SIDLE_ACT, 2877 .flags = DEBUG_OMAP4UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
3526 .mpu_irqs = omap44xx_uart4_irqs,
3527 .sdma_reqs = omap44xx_uart4_sdma_reqs,
3528 .main_clk = "func_48m_fclk", 2878 .main_clk = "func_48m_fclk",
3529 .prcm = { 2879 .prcm = {
3530 .omap4 = { 2880 .omap4 = {
@@ -3563,17 +2913,10 @@ static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
3563}; 2913};
3564 2914
3565/* usb_host_fs */ 2915/* usb_host_fs */
3566static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
3567 { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
3568 { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
3569 { .irq = -1 }
3570};
3571
3572static struct omap_hwmod omap44xx_usb_host_fs_hwmod = { 2916static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
3573 .name = "usb_host_fs", 2917 .name = "usb_host_fs",
3574 .class = &omap44xx_usb_host_fs_hwmod_class, 2918 .class = &omap44xx_usb_host_fs_hwmod_class,
3575 .clkdm_name = "l3_init_clkdm", 2919 .clkdm_name = "l3_init_clkdm",
3576 .mpu_irqs = omap44xx_usb_host_fs_irqs,
3577 .main_clk = "usb_host_fs_fck", 2920 .main_clk = "usb_host_fs_fck",
3578 .prcm = { 2921 .prcm = {
3579 .omap4 = { 2922 .omap4 = {
@@ -3607,12 +2950,6 @@ static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
3607}; 2950};
3608 2951
3609/* usb_host_hs */ 2952/* usb_host_hs */
3610static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
3611 { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
3612 { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
3613 { .irq = -1 }
3614};
3615
3616static struct omap_hwmod omap44xx_usb_host_hs_hwmod = { 2953static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
3617 .name = "usb_host_hs", 2954 .name = "usb_host_hs",
3618 .class = &omap44xx_usb_host_hs_hwmod_class, 2955 .class = &omap44xx_usb_host_hs_hwmod_class,
@@ -3625,7 +2962,6 @@ static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
3625 .modulemode = MODULEMODE_SWCTRL, 2962 .modulemode = MODULEMODE_SWCTRL,
3626 }, 2963 },
3627 }, 2964 },
3628 .mpu_irqs = omap44xx_usb_host_hs_irqs,
3629 2965
3630 /* 2966 /*
3631 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock 2967 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
@@ -3700,12 +3036,6 @@ static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3700}; 3036};
3701 3037
3702/* usb_otg_hs */ 3038/* usb_otg_hs */
3703static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
3704 { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
3705 { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
3706 { .irq = -1 }
3707};
3708
3709static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = { 3039static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3710 { .role = "xclk", .clk = "usb_otg_hs_xclk" }, 3040 { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3711}; 3041};
@@ -3715,7 +3045,6 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3715 .class = &omap44xx_usb_otg_hs_hwmod_class, 3045 .class = &omap44xx_usb_otg_hs_hwmod_class,
3716 .clkdm_name = "l3_init_clkdm", 3046 .clkdm_name = "l3_init_clkdm",
3717 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, 3047 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3718 .mpu_irqs = omap44xx_usb_otg_hs_irqs,
3719 .main_clk = "usb_otg_hs_ick", 3048 .main_clk = "usb_otg_hs_ick",
3720 .prcm = { 3049 .prcm = {
3721 .omap4 = { 3050 .omap4 = {
@@ -3749,16 +3078,10 @@ static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3749 .sysc = &omap44xx_usb_tll_hs_sysc, 3078 .sysc = &omap44xx_usb_tll_hs_sysc,
3750}; 3079};
3751 3080
3752static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
3753 { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
3754 { .irq = -1 }
3755};
3756
3757static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = { 3081static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3758 .name = "usb_tll_hs", 3082 .name = "usb_tll_hs",
3759 .class = &omap44xx_usb_tll_hs_hwmod_class, 3083 .class = &omap44xx_usb_tll_hs_hwmod_class,
3760 .clkdm_name = "l3_init_clkdm", 3084 .clkdm_name = "l3_init_clkdm",
3761 .mpu_irqs = omap44xx_usb_tll_hs_irqs,
3762 .main_clk = "usb_tll_hs_ick", 3085 .main_clk = "usb_tll_hs_ick",
3763 .prcm = { 3086 .prcm = {
3764 .omap4 = { 3087 .omap4 = {
@@ -3794,16 +3117,10 @@ static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3794}; 3117};
3795 3118
3796/* wd_timer2 */ 3119/* wd_timer2 */
3797static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
3798 { .irq = 80 + OMAP44XX_IRQ_GIC_START },
3799 { .irq = -1 }
3800};
3801
3802static struct omap_hwmod omap44xx_wd_timer2_hwmod = { 3120static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3803 .name = "wd_timer2", 3121 .name = "wd_timer2",
3804 .class = &omap44xx_wd_timer_hwmod_class, 3122 .class = &omap44xx_wd_timer_hwmod_class,
3805 .clkdm_name = "l4_wkup_clkdm", 3123 .clkdm_name = "l4_wkup_clkdm",
3806 .mpu_irqs = omap44xx_wd_timer2_irqs,
3807 .main_clk = "sys_32k_ck", 3124 .main_clk = "sys_32k_ck",
3808 .prcm = { 3125 .prcm = {
3809 .omap4 = { 3126 .omap4 = {
@@ -3815,16 +3132,10 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3815}; 3132};
3816 3133
3817/* wd_timer3 */ 3134/* wd_timer3 */
3818static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
3819 { .irq = 36 + OMAP44XX_IRQ_GIC_START },
3820 { .irq = -1 }
3821};
3822
3823static struct omap_hwmod omap44xx_wd_timer3_hwmod = { 3135static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3824 .name = "wd_timer3", 3136 .name = "wd_timer3",
3825 .class = &omap44xx_wd_timer_hwmod_class, 3137 .class = &omap44xx_wd_timer_hwmod_class,
3826 .clkdm_name = "abe_clkdm", 3138 .clkdm_name = "abe_clkdm",
3827 .mpu_irqs = omap44xx_wd_timer3_irqs,
3828 .main_clk = "sys_32k_ck", 3139 .main_clk = "sys_32k_ck",
3829 .prcm = { 3140 .prcm = {
3830 .omap4 = { 3141 .omap4 = {
@@ -3840,32 +3151,6 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3840 * interfaces 3151 * interfaces
3841 */ 3152 */
3842 3153
3843static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
3844 {
3845 .pa_start = 0x4a204000,
3846 .pa_end = 0x4a2040ff,
3847 .flags = ADDR_TYPE_RT
3848 },
3849 { }
3850};
3851
3852/* c2c -> c2c_target_fw */
3853static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
3854 .master = &omap44xx_c2c_hwmod,
3855 .slave = &omap44xx_c2c_target_fw_hwmod,
3856 .clk = "div_core_ck",
3857 .addr = omap44xx_c2c_target_fw_addrs,
3858 .user = OCP_USER_MPU,
3859};
3860
3861/* l4_cfg -> c2c_target_fw */
3862static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
3863 .master = &omap44xx_l4_cfg_hwmod,
3864 .slave = &omap44xx_c2c_target_fw_hwmod,
3865 .clk = "l4_div_ck",
3866 .user = OCP_USER_MPU | OCP_USER_SDMA,
3867};
3868
3869/* l3_main_1 -> dmm */ 3154/* l3_main_1 -> dmm */
3870static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { 3155static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3871 .master = &omap44xx_l3_main_1_hwmod, 3156 .master = &omap44xx_l3_main_1_hwmod,
@@ -3874,55 +3159,11 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3874 .user = OCP_USER_SDMA, 3159 .user = OCP_USER_SDMA,
3875}; 3160};
3876 3161
3877static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
3878 {
3879 .pa_start = 0x4e000000,
3880 .pa_end = 0x4e0007ff,
3881 .flags = ADDR_TYPE_RT
3882 },
3883 { }
3884};
3885
3886/* mpu -> dmm */ 3162/* mpu -> dmm */
3887static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { 3163static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3888 .master = &omap44xx_mpu_hwmod, 3164 .master = &omap44xx_mpu_hwmod,
3889 .slave = &omap44xx_dmm_hwmod, 3165 .slave = &omap44xx_dmm_hwmod,
3890 .clk = "l3_div_ck", 3166 .clk = "l3_div_ck",
3891 .addr = omap44xx_dmm_addrs,
3892 .user = OCP_USER_MPU,
3893};
3894
3895/* c2c -> emif_fw */
3896static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
3897 .master = &omap44xx_c2c_hwmod,
3898 .slave = &omap44xx_emif_fw_hwmod,
3899 .clk = "div_core_ck",
3900 .user = OCP_USER_MPU | OCP_USER_SDMA,
3901};
3902
3903/* dmm -> emif_fw */
3904static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
3905 .master = &omap44xx_dmm_hwmod,
3906 .slave = &omap44xx_emif_fw_hwmod,
3907 .clk = "l3_div_ck",
3908 .user = OCP_USER_MPU | OCP_USER_SDMA,
3909};
3910
3911static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
3912 {
3913 .pa_start = 0x4a20c000,
3914 .pa_end = 0x4a20c0ff,
3915 .flags = ADDR_TYPE_RT
3916 },
3917 { }
3918};
3919
3920/* l4_cfg -> emif_fw */
3921static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
3922 .master = &omap44xx_l4_cfg_hwmod,
3923 .slave = &omap44xx_emif_fw_hwmod,
3924 .clk = "l4_div_ck",
3925 .addr = omap44xx_emif_fw_addrs,
3926 .user = OCP_USER_MPU, 3167 .user = OCP_USER_MPU,
3927}; 3168};
3928 3169
@@ -3998,32 +3239,14 @@ static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3998 .user = OCP_USER_MPU | OCP_USER_SDMA, 3239 .user = OCP_USER_MPU | OCP_USER_SDMA,
3999}; 3240};
4000 3241
4001static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
4002 {
4003 .pa_start = 0x44000000,
4004 .pa_end = 0x44000fff,
4005 .flags = ADDR_TYPE_RT
4006 },
4007 { }
4008};
4009
4010/* mpu -> l3_main_1 */ 3242/* mpu -> l3_main_1 */
4011static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { 3243static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
4012 .master = &omap44xx_mpu_hwmod, 3244 .master = &omap44xx_mpu_hwmod,
4013 .slave = &omap44xx_l3_main_1_hwmod, 3245 .slave = &omap44xx_l3_main_1_hwmod,
4014 .clk = "l3_div_ck", 3246 .clk = "l3_div_ck",
4015 .addr = omap44xx_l3_main_1_addrs,
4016 .user = OCP_USER_MPU, 3247 .user = OCP_USER_MPU,
4017}; 3248};
4018 3249
4019/* c2c_target_fw -> l3_main_2 */
4020static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
4021 .master = &omap44xx_c2c_target_fw_hwmod,
4022 .slave = &omap44xx_l3_main_2_hwmod,
4023 .clk = "l3_div_ck",
4024 .user = OCP_USER_MPU | OCP_USER_SDMA,
4025};
4026
4027/* debugss -> l3_main_2 */ 3250/* debugss -> l3_main_2 */
4028static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = { 3251static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
4029 .master = &omap44xx_debugss_hwmod, 3252 .master = &omap44xx_debugss_hwmod,
@@ -4088,21 +3311,11 @@ static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
4088 .user = OCP_USER_MPU | OCP_USER_SDMA, 3311 .user = OCP_USER_MPU | OCP_USER_SDMA,
4089}; 3312};
4090 3313
4091static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
4092 {
4093 .pa_start = 0x44800000,
4094 .pa_end = 0x44801fff,
4095 .flags = ADDR_TYPE_RT
4096 },
4097 { }
4098};
4099
4100/* l3_main_1 -> l3_main_2 */ 3314/* l3_main_1 -> l3_main_2 */
4101static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { 3315static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
4102 .master = &omap44xx_l3_main_1_hwmod, 3316 .master = &omap44xx_l3_main_1_hwmod,
4103 .slave = &omap44xx_l3_main_2_hwmod, 3317 .slave = &omap44xx_l3_main_2_hwmod,
4104 .clk = "l3_div_ck", 3318 .clk = "l3_div_ck",
4105 .addr = omap44xx_l3_main_2_addrs,
4106 .user = OCP_USER_MPU, 3319 .user = OCP_USER_MPU,
4107}; 3320};
4108 3321
@@ -4138,21 +3351,11 @@ static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
4138 .user = OCP_USER_MPU | OCP_USER_SDMA, 3351 .user = OCP_USER_MPU | OCP_USER_SDMA,
4139}; 3352};
4140 3353
4141static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
4142 {
4143 .pa_start = 0x45000000,
4144 .pa_end = 0x45000fff,
4145 .flags = ADDR_TYPE_RT
4146 },
4147 { }
4148};
4149
4150/* l3_main_1 -> l3_main_3 */ 3354/* l3_main_1 -> l3_main_3 */
4151static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { 3355static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
4152 .master = &omap44xx_l3_main_1_hwmod, 3356 .master = &omap44xx_l3_main_1_hwmod,
4153 .slave = &omap44xx_l3_main_3_hwmod, 3357 .slave = &omap44xx_l3_main_3_hwmod,
4154 .clk = "l3_div_ck", 3358 .clk = "l3_div_ck",
4155 .addr = omap44xx_l3_main_3_addrs,
4156 .user = OCP_USER_MPU, 3359 .user = OCP_USER_MPU,
4157}; 3360};
4158 3361
@@ -4236,21 +3439,11 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
4236 .user = OCP_USER_MPU | OCP_USER_SDMA, 3439 .user = OCP_USER_MPU | OCP_USER_SDMA,
4237}; 3440};
4238 3441
4239static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
4240 {
4241 .pa_start = 0x4a102000,
4242 .pa_end = 0x4a10207f,
4243 .flags = ADDR_TYPE_RT
4244 },
4245 { }
4246};
4247
4248/* l4_cfg -> ocp_wp_noc */ 3442/* l4_cfg -> ocp_wp_noc */
4249static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = { 3443static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
4250 .master = &omap44xx_l4_cfg_hwmod, 3444 .master = &omap44xx_l4_cfg_hwmod,
4251 .slave = &omap44xx_ocp_wp_noc_hwmod, 3445 .slave = &omap44xx_ocp_wp_noc_hwmod,
4252 .clk = "l4_div_ck", 3446 .clk = "l4_div_ck",
4253 .addr = omap44xx_ocp_wp_noc_addrs,
4254 .user = OCP_USER_MPU | OCP_USER_SDMA, 3447 .user = OCP_USER_MPU | OCP_USER_SDMA,
4255}; 3448};
4256 3449
@@ -4340,21 +3533,11 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
4340 .user = OCP_USER_MPU | OCP_USER_SDMA, 3533 .user = OCP_USER_MPU | OCP_USER_SDMA,
4341}; 3534};
4342 3535
4343static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
4344 {
4345 .pa_start = 0x4a304000,
4346 .pa_end = 0x4a30401f,
4347 .flags = ADDR_TYPE_RT
4348 },
4349 { }
4350};
4351
4352/* l4_wkup -> counter_32k */ 3536/* l4_wkup -> counter_32k */
4353static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { 3537static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
4354 .master = &omap44xx_l4_wkup_hwmod, 3538 .master = &omap44xx_l4_wkup_hwmod,
4355 .slave = &omap44xx_counter_32k_hwmod, 3539 .slave = &omap44xx_counter_32k_hwmod,
4356 .clk = "l4_wkup_clk_mux_ck", 3540 .clk = "l4_wkup_clk_mux_ck",
4357 .addr = omap44xx_counter_32k_addrs,
4358 .user = OCP_USER_MPU | OCP_USER_SDMA, 3541 .user = OCP_USER_MPU | OCP_USER_SDMA,
4359}; 3542};
4360 3543
@@ -4430,21 +3613,11 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
4430 .user = OCP_USER_MPU | OCP_USER_SDMA, 3613 .user = OCP_USER_MPU | OCP_USER_SDMA,
4431}; 3614};
4432 3615
4433static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
4434 {
4435 .pa_start = 0x54160000,
4436 .pa_end = 0x54167fff,
4437 .flags = ADDR_TYPE_RT
4438 },
4439 { }
4440};
4441
4442/* l3_instr -> debugss */ 3616/* l3_instr -> debugss */
4443static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = { 3617static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
4444 .master = &omap44xx_l3_instr_hwmod, 3618 .master = &omap44xx_l3_instr_hwmod,
4445 .slave = &omap44xx_debugss_hwmod, 3619 .slave = &omap44xx_debugss_hwmod,
4446 .clk = "l3_div_ck", 3620 .clk = "l3_div_ck",
4447 .addr = omap44xx_debugss_addrs,
4448 .user = OCP_USER_MPU | OCP_USER_SDMA, 3621 .user = OCP_USER_MPU | OCP_USER_SDMA,
4449}; 3622};
4450 3623
@@ -4466,41 +3639,19 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
4466 .user = OCP_USER_MPU | OCP_USER_SDMA, 3639 .user = OCP_USER_MPU | OCP_USER_SDMA,
4467}; 3640};
4468 3641
4469static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
4470 {
4471 .name = "mpu",
4472 .pa_start = 0x4012e000,
4473 .pa_end = 0x4012e07f,
4474 .flags = ADDR_TYPE_RT
4475 },
4476 { }
4477};
4478
4479/* l4_abe -> dmic */ 3642/* l4_abe -> dmic */
4480static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = { 3643static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
4481 .master = &omap44xx_l4_abe_hwmod, 3644 .master = &omap44xx_l4_abe_hwmod,
4482 .slave = &omap44xx_dmic_hwmod, 3645 .slave = &omap44xx_dmic_hwmod,
4483 .clk = "ocp_abe_iclk", 3646 .clk = "ocp_abe_iclk",
4484 .addr = omap44xx_dmic_addrs,
4485 .user = OCP_USER_MPU, 3647 .user = OCP_USER_MPU,
4486}; 3648};
4487 3649
4488static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
4489 {
4490 .name = "dma",
4491 .pa_start = 0x4902e000,
4492 .pa_end = 0x4902e07f,
4493 .flags = ADDR_TYPE_RT
4494 },
4495 { }
4496};
4497
4498/* l4_abe -> dmic (dma) */ 3650/* l4_abe -> dmic (dma) */
4499static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = { 3651static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
4500 .master = &omap44xx_l4_abe_hwmod, 3652 .master = &omap44xx_l4_abe_hwmod,
4501 .slave = &omap44xx_dmic_hwmod, 3653 .slave = &omap44xx_dmic_hwmod,
4502 .clk = "ocp_abe_iclk", 3654 .clk = "ocp_abe_iclk",
4503 .addr = omap44xx_dmic_dma_addrs,
4504 .user = OCP_USER_SDMA, 3655 .user = OCP_USER_SDMA,
4505}; 3656};
4506 3657
@@ -4798,42 +3949,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
4798 .user = OCP_USER_MPU | OCP_USER_SDMA, 3949 .user = OCP_USER_MPU | OCP_USER_SDMA,
4799}; 3950};
4800 3951
4801static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
4802 {
4803 .pa_start = 0x4c000000,
4804 .pa_end = 0x4c0000ff,
4805 .flags = ADDR_TYPE_RT
4806 },
4807 { }
4808};
4809
4810/* emif_fw -> emif1 */
4811static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
4812 .master = &omap44xx_emif_fw_hwmod,
4813 .slave = &omap44xx_emif1_hwmod,
4814 .clk = "l3_div_ck",
4815 .addr = omap44xx_emif1_addrs,
4816 .user = OCP_USER_MPU | OCP_USER_SDMA,
4817};
4818
4819static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
4820 {
4821 .pa_start = 0x4d000000,
4822 .pa_end = 0x4d0000ff,
4823 .flags = ADDR_TYPE_RT
4824 },
4825 { }
4826};
4827
4828/* emif_fw -> emif2 */
4829static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
4830 .master = &omap44xx_emif_fw_hwmod,
4831 .slave = &omap44xx_emif2_hwmod,
4832 .clk = "l3_div_ck",
4833 .addr = omap44xx_emif2_addrs,
4834 .user = OCP_USER_MPU | OCP_USER_SDMA,
4835};
4836
4837static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = { 3952static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
4838 { 3953 {
4839 .pa_start = 0x4a10a000, 3954 .pa_start = 0x4a10a000,
@@ -4852,129 +3967,59 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
4852 .user = OCP_USER_MPU | OCP_USER_SDMA, 3967 .user = OCP_USER_MPU | OCP_USER_SDMA,
4853}; 3968};
4854 3969
4855static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
4856 {
4857 .pa_start = 0x4a310000,
4858 .pa_end = 0x4a3101ff,
4859 .flags = ADDR_TYPE_RT
4860 },
4861 { }
4862};
4863
4864/* l4_wkup -> gpio1 */ 3970/* l4_wkup -> gpio1 */
4865static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { 3971static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
4866 .master = &omap44xx_l4_wkup_hwmod, 3972 .master = &omap44xx_l4_wkup_hwmod,
4867 .slave = &omap44xx_gpio1_hwmod, 3973 .slave = &omap44xx_gpio1_hwmod,
4868 .clk = "l4_wkup_clk_mux_ck", 3974 .clk = "l4_wkup_clk_mux_ck",
4869 .addr = omap44xx_gpio1_addrs,
4870 .user = OCP_USER_MPU | OCP_USER_SDMA, 3975 .user = OCP_USER_MPU | OCP_USER_SDMA,
4871}; 3976};
4872 3977
4873static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
4874 {
4875 .pa_start = 0x48055000,
4876 .pa_end = 0x480551ff,
4877 .flags = ADDR_TYPE_RT
4878 },
4879 { }
4880};
4881
4882/* l4_per -> gpio2 */ 3978/* l4_per -> gpio2 */
4883static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { 3979static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
4884 .master = &omap44xx_l4_per_hwmod, 3980 .master = &omap44xx_l4_per_hwmod,
4885 .slave = &omap44xx_gpio2_hwmod, 3981 .slave = &omap44xx_gpio2_hwmod,
4886 .clk = "l4_div_ck", 3982 .clk = "l4_div_ck",
4887 .addr = omap44xx_gpio2_addrs,
4888 .user = OCP_USER_MPU | OCP_USER_SDMA, 3983 .user = OCP_USER_MPU | OCP_USER_SDMA,
4889}; 3984};
4890 3985
4891static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
4892 {
4893 .pa_start = 0x48057000,
4894 .pa_end = 0x480571ff,
4895 .flags = ADDR_TYPE_RT
4896 },
4897 { }
4898};
4899
4900/* l4_per -> gpio3 */ 3986/* l4_per -> gpio3 */
4901static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { 3987static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
4902 .master = &omap44xx_l4_per_hwmod, 3988 .master = &omap44xx_l4_per_hwmod,
4903 .slave = &omap44xx_gpio3_hwmod, 3989 .slave = &omap44xx_gpio3_hwmod,
4904 .clk = "l4_div_ck", 3990 .clk = "l4_div_ck",
4905 .addr = omap44xx_gpio3_addrs,
4906 .user = OCP_USER_MPU | OCP_USER_SDMA, 3991 .user = OCP_USER_MPU | OCP_USER_SDMA,
4907}; 3992};
4908 3993
4909static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
4910 {
4911 .pa_start = 0x48059000,
4912 .pa_end = 0x480591ff,
4913 .flags = ADDR_TYPE_RT
4914 },
4915 { }
4916};
4917
4918/* l4_per -> gpio4 */ 3994/* l4_per -> gpio4 */
4919static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { 3995static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
4920 .master = &omap44xx_l4_per_hwmod, 3996 .master = &omap44xx_l4_per_hwmod,
4921 .slave = &omap44xx_gpio4_hwmod, 3997 .slave = &omap44xx_gpio4_hwmod,
4922 .clk = "l4_div_ck", 3998 .clk = "l4_div_ck",
4923 .addr = omap44xx_gpio4_addrs,
4924 .user = OCP_USER_MPU | OCP_USER_SDMA, 3999 .user = OCP_USER_MPU | OCP_USER_SDMA,
4925}; 4000};
4926 4001
4927static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
4928 {
4929 .pa_start = 0x4805b000,
4930 .pa_end = 0x4805b1ff,
4931 .flags = ADDR_TYPE_RT
4932 },
4933 { }
4934};
4935
4936/* l4_per -> gpio5 */ 4002/* l4_per -> gpio5 */
4937static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { 4003static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
4938 .master = &omap44xx_l4_per_hwmod, 4004 .master = &omap44xx_l4_per_hwmod,
4939 .slave = &omap44xx_gpio5_hwmod, 4005 .slave = &omap44xx_gpio5_hwmod,
4940 .clk = "l4_div_ck", 4006 .clk = "l4_div_ck",
4941 .addr = omap44xx_gpio5_addrs,
4942 .user = OCP_USER_MPU | OCP_USER_SDMA, 4007 .user = OCP_USER_MPU | OCP_USER_SDMA,
4943}; 4008};
4944 4009
4945static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
4946 {
4947 .pa_start = 0x4805d000,
4948 .pa_end = 0x4805d1ff,
4949 .flags = ADDR_TYPE_RT
4950 },
4951 { }
4952};
4953
4954/* l4_per -> gpio6 */ 4010/* l4_per -> gpio6 */
4955static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { 4011static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4956 .master = &omap44xx_l4_per_hwmod, 4012 .master = &omap44xx_l4_per_hwmod,
4957 .slave = &omap44xx_gpio6_hwmod, 4013 .slave = &omap44xx_gpio6_hwmod,
4958 .clk = "l4_div_ck", 4014 .clk = "l4_div_ck",
4959 .addr = omap44xx_gpio6_addrs,
4960 .user = OCP_USER_MPU | OCP_USER_SDMA, 4015 .user = OCP_USER_MPU | OCP_USER_SDMA,
4961}; 4016};
4962 4017
4963static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
4964 {
4965 .pa_start = 0x50000000,
4966 .pa_end = 0x500003ff,
4967 .flags = ADDR_TYPE_RT
4968 },
4969 { }
4970};
4971
4972/* l3_main_2 -> gpmc */ 4018/* l3_main_2 -> gpmc */
4973static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = { 4019static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4974 .master = &omap44xx_l3_main_2_hwmod, 4020 .master = &omap44xx_l3_main_2_hwmod,
4975 .slave = &omap44xx_gpmc_hwmod, 4021 .slave = &omap44xx_gpmc_hwmod,
4976 .clk = "l3_div_ck", 4022 .clk = "l3_div_ck",
4977 .addr = omap44xx_gpmc_addrs,
4978 .user = OCP_USER_MPU | OCP_USER_SDMA, 4023 .user = OCP_USER_MPU | OCP_USER_SDMA,
4979}; 4024};
4980 4025
@@ -5032,75 +4077,35 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
5032 .user = OCP_USER_MPU | OCP_USER_SDMA, 4077 .user = OCP_USER_MPU | OCP_USER_SDMA,
5033}; 4078};
5034 4079
5035static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
5036 {
5037 .pa_start = 0x48070000,
5038 .pa_end = 0x480700ff,
5039 .flags = ADDR_TYPE_RT
5040 },
5041 { }
5042};
5043
5044/* l4_per -> i2c1 */ 4080/* l4_per -> i2c1 */
5045static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { 4081static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
5046 .master = &omap44xx_l4_per_hwmod, 4082 .master = &omap44xx_l4_per_hwmod,
5047 .slave = &omap44xx_i2c1_hwmod, 4083 .slave = &omap44xx_i2c1_hwmod,
5048 .clk = "l4_div_ck", 4084 .clk = "l4_div_ck",
5049 .addr = omap44xx_i2c1_addrs,
5050 .user = OCP_USER_MPU | OCP_USER_SDMA, 4085 .user = OCP_USER_MPU | OCP_USER_SDMA,
5051}; 4086};
5052 4087
5053static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
5054 {
5055 .pa_start = 0x48072000,
5056 .pa_end = 0x480720ff,
5057 .flags = ADDR_TYPE_RT
5058 },
5059 { }
5060};
5061
5062/* l4_per -> i2c2 */ 4088/* l4_per -> i2c2 */
5063static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { 4089static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
5064 .master = &omap44xx_l4_per_hwmod, 4090 .master = &omap44xx_l4_per_hwmod,
5065 .slave = &omap44xx_i2c2_hwmod, 4091 .slave = &omap44xx_i2c2_hwmod,
5066 .clk = "l4_div_ck", 4092 .clk = "l4_div_ck",
5067 .addr = omap44xx_i2c2_addrs,
5068 .user = OCP_USER_MPU | OCP_USER_SDMA, 4093 .user = OCP_USER_MPU | OCP_USER_SDMA,
5069}; 4094};
5070 4095
5071static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
5072 {
5073 .pa_start = 0x48060000,
5074 .pa_end = 0x480600ff,
5075 .flags = ADDR_TYPE_RT
5076 },
5077 { }
5078};
5079
5080/* l4_per -> i2c3 */ 4096/* l4_per -> i2c3 */
5081static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { 4097static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
5082 .master = &omap44xx_l4_per_hwmod, 4098 .master = &omap44xx_l4_per_hwmod,
5083 .slave = &omap44xx_i2c3_hwmod, 4099 .slave = &omap44xx_i2c3_hwmod,
5084 .clk = "l4_div_ck", 4100 .clk = "l4_div_ck",
5085 .addr = omap44xx_i2c3_addrs,
5086 .user = OCP_USER_MPU | OCP_USER_SDMA, 4101 .user = OCP_USER_MPU | OCP_USER_SDMA,
5087}; 4102};
5088 4103
5089static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
5090 {
5091 .pa_start = 0x48350000,
5092 .pa_end = 0x483500ff,
5093 .flags = ADDR_TYPE_RT
5094 },
5095 { }
5096};
5097
5098/* l4_per -> i2c4 */ 4104/* l4_per -> i2c4 */
5099static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { 4105static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
5100 .master = &omap44xx_l4_per_hwmod, 4106 .master = &omap44xx_l4_per_hwmod,
5101 .slave = &omap44xx_i2c4_hwmod, 4107 .slave = &omap44xx_i2c4_hwmod,
5102 .clk = "l4_div_ck", 4108 .clk = "l4_div_ck",
5103 .addr = omap44xx_i2c4_addrs,
5104 .user = OCP_USER_MPU | OCP_USER_SDMA, 4109 .user = OCP_USER_MPU | OCP_USER_SDMA,
5105}; 4110};
5106 4111
@@ -5138,39 +4143,19 @@ static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
5138 .user = OCP_USER_IVA, 4143 .user = OCP_USER_IVA,
5139}; 4144};
5140 4145
5141static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
5142 {
5143 .pa_start = 0x5a000000,
5144 .pa_end = 0x5a07ffff,
5145 .flags = ADDR_TYPE_RT
5146 },
5147 { }
5148};
5149
5150/* l3_main_2 -> iva */ 4146/* l3_main_2 -> iva */
5151static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { 4147static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
5152 .master = &omap44xx_l3_main_2_hwmod, 4148 .master = &omap44xx_l3_main_2_hwmod,
5153 .slave = &omap44xx_iva_hwmod, 4149 .slave = &omap44xx_iva_hwmod,
5154 .clk = "l3_div_ck", 4150 .clk = "l3_div_ck",
5155 .addr = omap44xx_iva_addrs,
5156 .user = OCP_USER_MPU, 4151 .user = OCP_USER_MPU,
5157}; 4152};
5158 4153
5159static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
5160 {
5161 .pa_start = 0x4a31c000,
5162 .pa_end = 0x4a31c07f,
5163 .flags = ADDR_TYPE_RT
5164 },
5165 { }
5166};
5167
5168/* l4_wkup -> kbd */ 4154/* l4_wkup -> kbd */
5169static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = { 4155static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
5170 .master = &omap44xx_l4_wkup_hwmod, 4156 .master = &omap44xx_l4_wkup_hwmod,
5171 .slave = &omap44xx_kbd_hwmod, 4157 .slave = &omap44xx_kbd_hwmod,
5172 .clk = "l4_wkup_clk_mux_ck", 4158 .clk = "l4_wkup_clk_mux_ck",
5173 .addr = omap44xx_kbd_addrs,
5174 .user = OCP_USER_MPU | OCP_USER_SDMA, 4159 .user = OCP_USER_MPU | OCP_USER_SDMA,
5175}; 4160};
5176 4161
@@ -5228,335 +4213,147 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
5228 .user = OCP_USER_SDMA, 4213 .user = OCP_USER_SDMA,
5229}; 4214};
5230 4215
5231static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
5232 {
5233 .name = "mpu",
5234 .pa_start = 0x40122000,
5235 .pa_end = 0x401220ff,
5236 .flags = ADDR_TYPE_RT
5237 },
5238 { }
5239};
5240
5241/* l4_abe -> mcbsp1 */ 4216/* l4_abe -> mcbsp1 */
5242static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = { 4217static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
5243 .master = &omap44xx_l4_abe_hwmod, 4218 .master = &omap44xx_l4_abe_hwmod,
5244 .slave = &omap44xx_mcbsp1_hwmod, 4219 .slave = &omap44xx_mcbsp1_hwmod,
5245 .clk = "ocp_abe_iclk", 4220 .clk = "ocp_abe_iclk",
5246 .addr = omap44xx_mcbsp1_addrs,
5247 .user = OCP_USER_MPU, 4221 .user = OCP_USER_MPU,
5248}; 4222};
5249 4223
5250static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
5251 {
5252 .name = "dma",
5253 .pa_start = 0x49022000,
5254 .pa_end = 0x490220ff,
5255 .flags = ADDR_TYPE_RT
5256 },
5257 { }
5258};
5259
5260/* l4_abe -> mcbsp1 (dma) */ 4224/* l4_abe -> mcbsp1 (dma) */
5261static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = { 4225static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
5262 .master = &omap44xx_l4_abe_hwmod, 4226 .master = &omap44xx_l4_abe_hwmod,
5263 .slave = &omap44xx_mcbsp1_hwmod, 4227 .slave = &omap44xx_mcbsp1_hwmod,
5264 .clk = "ocp_abe_iclk", 4228 .clk = "ocp_abe_iclk",
5265 .addr = omap44xx_mcbsp1_dma_addrs,
5266 .user = OCP_USER_SDMA, 4229 .user = OCP_USER_SDMA,
5267}; 4230};
5268 4231
5269static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
5270 {
5271 .name = "mpu",
5272 .pa_start = 0x40124000,
5273 .pa_end = 0x401240ff,
5274 .flags = ADDR_TYPE_RT
5275 },
5276 { }
5277};
5278
5279/* l4_abe -> mcbsp2 */ 4232/* l4_abe -> mcbsp2 */
5280static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = { 4233static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
5281 .master = &omap44xx_l4_abe_hwmod, 4234 .master = &omap44xx_l4_abe_hwmod,
5282 .slave = &omap44xx_mcbsp2_hwmod, 4235 .slave = &omap44xx_mcbsp2_hwmod,
5283 .clk = "ocp_abe_iclk", 4236 .clk = "ocp_abe_iclk",
5284 .addr = omap44xx_mcbsp2_addrs,
5285 .user = OCP_USER_MPU, 4237 .user = OCP_USER_MPU,
5286}; 4238};
5287 4239
5288static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
5289 {
5290 .name = "dma",
5291 .pa_start = 0x49024000,
5292 .pa_end = 0x490240ff,
5293 .flags = ADDR_TYPE_RT
5294 },
5295 { }
5296};
5297
5298/* l4_abe -> mcbsp2 (dma) */ 4240/* l4_abe -> mcbsp2 (dma) */
5299static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = { 4241static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
5300 .master = &omap44xx_l4_abe_hwmod, 4242 .master = &omap44xx_l4_abe_hwmod,
5301 .slave = &omap44xx_mcbsp2_hwmod, 4243 .slave = &omap44xx_mcbsp2_hwmod,
5302 .clk = "ocp_abe_iclk", 4244 .clk = "ocp_abe_iclk",
5303 .addr = omap44xx_mcbsp2_dma_addrs,
5304 .user = OCP_USER_SDMA, 4245 .user = OCP_USER_SDMA,
5305}; 4246};
5306 4247
5307static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
5308 {
5309 .name = "mpu",
5310 .pa_start = 0x40126000,
5311 .pa_end = 0x401260ff,
5312 .flags = ADDR_TYPE_RT
5313 },
5314 { }
5315};
5316
5317/* l4_abe -> mcbsp3 */ 4248/* l4_abe -> mcbsp3 */
5318static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = { 4249static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
5319 .master = &omap44xx_l4_abe_hwmod, 4250 .master = &omap44xx_l4_abe_hwmod,
5320 .slave = &omap44xx_mcbsp3_hwmod, 4251 .slave = &omap44xx_mcbsp3_hwmod,
5321 .clk = "ocp_abe_iclk", 4252 .clk = "ocp_abe_iclk",
5322 .addr = omap44xx_mcbsp3_addrs,
5323 .user = OCP_USER_MPU, 4253 .user = OCP_USER_MPU,
5324}; 4254};
5325 4255
5326static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
5327 {
5328 .name = "dma",
5329 .pa_start = 0x49026000,
5330 .pa_end = 0x490260ff,
5331 .flags = ADDR_TYPE_RT
5332 },
5333 { }
5334};
5335
5336/* l4_abe -> mcbsp3 (dma) */ 4256/* l4_abe -> mcbsp3 (dma) */
5337static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = { 4257static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
5338 .master = &omap44xx_l4_abe_hwmod, 4258 .master = &omap44xx_l4_abe_hwmod,
5339 .slave = &omap44xx_mcbsp3_hwmod, 4259 .slave = &omap44xx_mcbsp3_hwmod,
5340 .clk = "ocp_abe_iclk", 4260 .clk = "ocp_abe_iclk",
5341 .addr = omap44xx_mcbsp3_dma_addrs,
5342 .user = OCP_USER_SDMA, 4261 .user = OCP_USER_SDMA,
5343}; 4262};
5344 4263
5345static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
5346 {
5347 .pa_start = 0x48096000,
5348 .pa_end = 0x480960ff,
5349 .flags = ADDR_TYPE_RT
5350 },
5351 { }
5352};
5353
5354/* l4_per -> mcbsp4 */ 4264/* l4_per -> mcbsp4 */
5355static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = { 4265static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
5356 .master = &omap44xx_l4_per_hwmod, 4266 .master = &omap44xx_l4_per_hwmod,
5357 .slave = &omap44xx_mcbsp4_hwmod, 4267 .slave = &omap44xx_mcbsp4_hwmod,
5358 .clk = "l4_div_ck", 4268 .clk = "l4_div_ck",
5359 .addr = omap44xx_mcbsp4_addrs,
5360 .user = OCP_USER_MPU | OCP_USER_SDMA, 4269 .user = OCP_USER_MPU | OCP_USER_SDMA,
5361}; 4270};
5362 4271
5363static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
5364 {
5365 .name = "mpu",
5366 .pa_start = 0x40132000,
5367 .pa_end = 0x4013207f,
5368 .flags = ADDR_TYPE_RT
5369 },
5370 { }
5371};
5372
5373/* l4_abe -> mcpdm */ 4272/* l4_abe -> mcpdm */
5374static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = { 4273static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
5375 .master = &omap44xx_l4_abe_hwmod, 4274 .master = &omap44xx_l4_abe_hwmod,
5376 .slave = &omap44xx_mcpdm_hwmod, 4275 .slave = &omap44xx_mcpdm_hwmod,
5377 .clk = "ocp_abe_iclk", 4276 .clk = "ocp_abe_iclk",
5378 .addr = omap44xx_mcpdm_addrs,
5379 .user = OCP_USER_MPU, 4277 .user = OCP_USER_MPU,
5380}; 4278};
5381 4279
5382static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
5383 {
5384 .name = "dma",
5385 .pa_start = 0x49032000,
5386 .pa_end = 0x4903207f,
5387 .flags = ADDR_TYPE_RT
5388 },
5389 { }
5390};
5391
5392/* l4_abe -> mcpdm (dma) */ 4280/* l4_abe -> mcpdm (dma) */
5393static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = { 4281static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
5394 .master = &omap44xx_l4_abe_hwmod, 4282 .master = &omap44xx_l4_abe_hwmod,
5395 .slave = &omap44xx_mcpdm_hwmod, 4283 .slave = &omap44xx_mcpdm_hwmod,
5396 .clk = "ocp_abe_iclk", 4284 .clk = "ocp_abe_iclk",
5397 .addr = omap44xx_mcpdm_dma_addrs,
5398 .user = OCP_USER_SDMA, 4285 .user = OCP_USER_SDMA,
5399}; 4286};
5400 4287
5401static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
5402 {
5403 .pa_start = 0x48098000,
5404 .pa_end = 0x480981ff,
5405 .flags = ADDR_TYPE_RT
5406 },
5407 { }
5408};
5409
5410/* l4_per -> mcspi1 */ 4288/* l4_per -> mcspi1 */
5411static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = { 4289static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
5412 .master = &omap44xx_l4_per_hwmod, 4290 .master = &omap44xx_l4_per_hwmod,
5413 .slave = &omap44xx_mcspi1_hwmod, 4291 .slave = &omap44xx_mcspi1_hwmod,
5414 .clk = "l4_div_ck", 4292 .clk = "l4_div_ck",
5415 .addr = omap44xx_mcspi1_addrs,
5416 .user = OCP_USER_MPU | OCP_USER_SDMA, 4293 .user = OCP_USER_MPU | OCP_USER_SDMA,
5417}; 4294};
5418 4295
5419static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
5420 {
5421 .pa_start = 0x4809a000,
5422 .pa_end = 0x4809a1ff,
5423 .flags = ADDR_TYPE_RT
5424 },
5425 { }
5426};
5427
5428/* l4_per -> mcspi2 */ 4296/* l4_per -> mcspi2 */
5429static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = { 4297static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
5430 .master = &omap44xx_l4_per_hwmod, 4298 .master = &omap44xx_l4_per_hwmod,
5431 .slave = &omap44xx_mcspi2_hwmod, 4299 .slave = &omap44xx_mcspi2_hwmod,
5432 .clk = "l4_div_ck", 4300 .clk = "l4_div_ck",
5433 .addr = omap44xx_mcspi2_addrs,
5434 .user = OCP_USER_MPU | OCP_USER_SDMA, 4301 .user = OCP_USER_MPU | OCP_USER_SDMA,
5435}; 4302};
5436 4303
5437static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
5438 {
5439 .pa_start = 0x480b8000,
5440 .pa_end = 0x480b81ff,
5441 .flags = ADDR_TYPE_RT
5442 },
5443 { }
5444};
5445
5446/* l4_per -> mcspi3 */ 4304/* l4_per -> mcspi3 */
5447static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = { 4305static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
5448 .master = &omap44xx_l4_per_hwmod, 4306 .master = &omap44xx_l4_per_hwmod,
5449 .slave = &omap44xx_mcspi3_hwmod, 4307 .slave = &omap44xx_mcspi3_hwmod,
5450 .clk = "l4_div_ck", 4308 .clk = "l4_div_ck",
5451 .addr = omap44xx_mcspi3_addrs,
5452 .user = OCP_USER_MPU | OCP_USER_SDMA, 4309 .user = OCP_USER_MPU | OCP_USER_SDMA,
5453}; 4310};
5454 4311
5455static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
5456 {
5457 .pa_start = 0x480ba000,
5458 .pa_end = 0x480ba1ff,
5459 .flags = ADDR_TYPE_RT
5460 },
5461 { }
5462};
5463
5464/* l4_per -> mcspi4 */ 4312/* l4_per -> mcspi4 */
5465static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = { 4313static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
5466 .master = &omap44xx_l4_per_hwmod, 4314 .master = &omap44xx_l4_per_hwmod,
5467 .slave = &omap44xx_mcspi4_hwmod, 4315 .slave = &omap44xx_mcspi4_hwmod,
5468 .clk = "l4_div_ck", 4316 .clk = "l4_div_ck",
5469 .addr = omap44xx_mcspi4_addrs,
5470 .user = OCP_USER_MPU | OCP_USER_SDMA, 4317 .user = OCP_USER_MPU | OCP_USER_SDMA,
5471}; 4318};
5472 4319
5473static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
5474 {
5475 .pa_start = 0x4809c000,
5476 .pa_end = 0x4809c3ff,
5477 .flags = ADDR_TYPE_RT
5478 },
5479 { }
5480};
5481
5482/* l4_per -> mmc1 */ 4320/* l4_per -> mmc1 */
5483static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = { 4321static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
5484 .master = &omap44xx_l4_per_hwmod, 4322 .master = &omap44xx_l4_per_hwmod,
5485 .slave = &omap44xx_mmc1_hwmod, 4323 .slave = &omap44xx_mmc1_hwmod,
5486 .clk = "l4_div_ck", 4324 .clk = "l4_div_ck",
5487 .addr = omap44xx_mmc1_addrs,
5488 .user = OCP_USER_MPU | OCP_USER_SDMA, 4325 .user = OCP_USER_MPU | OCP_USER_SDMA,
5489}; 4326};
5490 4327
5491static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
5492 {
5493 .pa_start = 0x480b4000,
5494 .pa_end = 0x480b43ff,
5495 .flags = ADDR_TYPE_RT
5496 },
5497 { }
5498};
5499
5500/* l4_per -> mmc2 */ 4328/* l4_per -> mmc2 */
5501static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = { 4329static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
5502 .master = &omap44xx_l4_per_hwmod, 4330 .master = &omap44xx_l4_per_hwmod,
5503 .slave = &omap44xx_mmc2_hwmod, 4331 .slave = &omap44xx_mmc2_hwmod,
5504 .clk = "l4_div_ck", 4332 .clk = "l4_div_ck",
5505 .addr = omap44xx_mmc2_addrs,
5506 .user = OCP_USER_MPU | OCP_USER_SDMA, 4333 .user = OCP_USER_MPU | OCP_USER_SDMA,
5507}; 4334};
5508 4335
5509static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
5510 {
5511 .pa_start = 0x480ad000,
5512 .pa_end = 0x480ad3ff,
5513 .flags = ADDR_TYPE_RT
5514 },
5515 { }
5516};
5517
5518/* l4_per -> mmc3 */ 4336/* l4_per -> mmc3 */
5519static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = { 4337static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
5520 .master = &omap44xx_l4_per_hwmod, 4338 .master = &omap44xx_l4_per_hwmod,
5521 .slave = &omap44xx_mmc3_hwmod, 4339 .slave = &omap44xx_mmc3_hwmod,
5522 .clk = "l4_div_ck", 4340 .clk = "l4_div_ck",
5523 .addr = omap44xx_mmc3_addrs,
5524 .user = OCP_USER_MPU | OCP_USER_SDMA, 4341 .user = OCP_USER_MPU | OCP_USER_SDMA,
5525}; 4342};
5526 4343
5527static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
5528 {
5529 .pa_start = 0x480d1000,
5530 .pa_end = 0x480d13ff,
5531 .flags = ADDR_TYPE_RT
5532 },
5533 { }
5534};
5535
5536/* l4_per -> mmc4 */ 4344/* l4_per -> mmc4 */
5537static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = { 4345static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
5538 .master = &omap44xx_l4_per_hwmod, 4346 .master = &omap44xx_l4_per_hwmod,
5539 .slave = &omap44xx_mmc4_hwmod, 4347 .slave = &omap44xx_mmc4_hwmod,
5540 .clk = "l4_div_ck", 4348 .clk = "l4_div_ck",
5541 .addr = omap44xx_mmc4_addrs,
5542 .user = OCP_USER_MPU | OCP_USER_SDMA, 4349 .user = OCP_USER_MPU | OCP_USER_SDMA,
5543}; 4350};
5544 4351
5545static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
5546 {
5547 .pa_start = 0x480d5000,
5548 .pa_end = 0x480d53ff,
5549 .flags = ADDR_TYPE_RT
5550 },
5551 { }
5552};
5553
5554/* l4_per -> mmc5 */ 4352/* l4_per -> mmc5 */
5555static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = { 4353static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
5556 .master = &omap44xx_l4_per_hwmod, 4354 .master = &omap44xx_l4_per_hwmod,
5557 .slave = &omap44xx_mmc5_hwmod, 4355 .slave = &omap44xx_mmc5_hwmod,
5558 .clk = "l4_div_ck", 4356 .clk = "l4_div_ck",
5559 .addr = omap44xx_mmc5_addrs,
5560 .user = OCP_USER_MPU | OCP_USER_SDMA, 4357 .user = OCP_USER_MPU | OCP_USER_SDMA,
5561}; 4358};
5562 4359
@@ -5568,111 +4365,51 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
5568 .user = OCP_USER_MPU | OCP_USER_SDMA, 4365 .user = OCP_USER_MPU | OCP_USER_SDMA,
5569}; 4366};
5570 4367
5571static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = {
5572 {
5573 .pa_start = 0x4a0ad000,
5574 .pa_end = 0x4a0ad01f,
5575 .flags = ADDR_TYPE_RT
5576 },
5577 { }
5578};
5579
5580/* l4_cfg -> ocp2scp_usb_phy */ 4368/* l4_cfg -> ocp2scp_usb_phy */
5581static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = { 4369static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
5582 .master = &omap44xx_l4_cfg_hwmod, 4370 .master = &omap44xx_l4_cfg_hwmod,
5583 .slave = &omap44xx_ocp2scp_usb_phy_hwmod, 4371 .slave = &omap44xx_ocp2scp_usb_phy_hwmod,
5584 .clk = "l4_div_ck", 4372 .clk = "l4_div_ck",
5585 .addr = omap44xx_ocp2scp_usb_phy_addrs,
5586 .user = OCP_USER_MPU | OCP_USER_SDMA, 4373 .user = OCP_USER_MPU | OCP_USER_SDMA,
5587}; 4374};
5588 4375
5589static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
5590 {
5591 .pa_start = 0x48243000,
5592 .pa_end = 0x48243fff,
5593 .flags = ADDR_TYPE_RT
5594 },
5595 { }
5596};
5597
5598/* mpu_private -> prcm_mpu */ 4376/* mpu_private -> prcm_mpu */
5599static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = { 4377static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
5600 .master = &omap44xx_mpu_private_hwmod, 4378 .master = &omap44xx_mpu_private_hwmod,
5601 .slave = &omap44xx_prcm_mpu_hwmod, 4379 .slave = &omap44xx_prcm_mpu_hwmod,
5602 .clk = "l3_div_ck", 4380 .clk = "l3_div_ck",
5603 .addr = omap44xx_prcm_mpu_addrs,
5604 .user = OCP_USER_MPU | OCP_USER_SDMA, 4381 .user = OCP_USER_MPU | OCP_USER_SDMA,
5605}; 4382};
5606 4383
5607static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
5608 {
5609 .pa_start = 0x4a004000,
5610 .pa_end = 0x4a004fff,
5611 .flags = ADDR_TYPE_RT
5612 },
5613 { }
5614};
5615
5616/* l4_wkup -> cm_core_aon */ 4384/* l4_wkup -> cm_core_aon */
5617static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = { 4385static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
5618 .master = &omap44xx_l4_wkup_hwmod, 4386 .master = &omap44xx_l4_wkup_hwmod,
5619 .slave = &omap44xx_cm_core_aon_hwmod, 4387 .slave = &omap44xx_cm_core_aon_hwmod,
5620 .clk = "l4_wkup_clk_mux_ck", 4388 .clk = "l4_wkup_clk_mux_ck",
5621 .addr = omap44xx_cm_core_aon_addrs,
5622 .user = OCP_USER_MPU | OCP_USER_SDMA, 4389 .user = OCP_USER_MPU | OCP_USER_SDMA,
5623}; 4390};
5624 4391
5625static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
5626 {
5627 .pa_start = 0x4a008000,
5628 .pa_end = 0x4a009fff,
5629 .flags = ADDR_TYPE_RT
5630 },
5631 { }
5632};
5633
5634/* l4_cfg -> cm_core */ 4392/* l4_cfg -> cm_core */
5635static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = { 4393static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
5636 .master = &omap44xx_l4_cfg_hwmod, 4394 .master = &omap44xx_l4_cfg_hwmod,
5637 .slave = &omap44xx_cm_core_hwmod, 4395 .slave = &omap44xx_cm_core_hwmod,
5638 .clk = "l4_div_ck", 4396 .clk = "l4_div_ck",
5639 .addr = omap44xx_cm_core_addrs,
5640 .user = OCP_USER_MPU | OCP_USER_SDMA, 4397 .user = OCP_USER_MPU | OCP_USER_SDMA,
5641}; 4398};
5642 4399
5643static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
5644 {
5645 .pa_start = 0x4a306000,
5646 .pa_end = 0x4a307fff,
5647 .flags = ADDR_TYPE_RT
5648 },
5649 { }
5650};
5651
5652/* l4_wkup -> prm */ 4400/* l4_wkup -> prm */
5653static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = { 4401static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
5654 .master = &omap44xx_l4_wkup_hwmod, 4402 .master = &omap44xx_l4_wkup_hwmod,
5655 .slave = &omap44xx_prm_hwmod, 4403 .slave = &omap44xx_prm_hwmod,
5656 .clk = "l4_wkup_clk_mux_ck", 4404 .clk = "l4_wkup_clk_mux_ck",
5657 .addr = omap44xx_prm_addrs,
5658 .user = OCP_USER_MPU | OCP_USER_SDMA, 4405 .user = OCP_USER_MPU | OCP_USER_SDMA,
5659}; 4406};
5660 4407
5661static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
5662 {
5663 .pa_start = 0x4a30a000,
5664 .pa_end = 0x4a30a7ff,
5665 .flags = ADDR_TYPE_RT
5666 },
5667 { }
5668};
5669
5670/* l4_wkup -> scrm */ 4408/* l4_wkup -> scrm */
5671static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = { 4409static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
5672 .master = &omap44xx_l4_wkup_hwmod, 4410 .master = &omap44xx_l4_wkup_hwmod,
5673 .slave = &omap44xx_scrm_hwmod, 4411 .slave = &omap44xx_scrm_hwmod,
5674 .clk = "l4_wkup_clk_mux_ck", 4412 .clk = "l4_wkup_clk_mux_ck",
5675 .addr = omap44xx_scrm_addrs,
5676 .user = OCP_USER_MPU | OCP_USER_SDMA, 4413 .user = OCP_USER_MPU | OCP_USER_SDMA,
5677}; 4414};
5678 4415
@@ -5810,447 +4547,195 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
5810 .user = OCP_USER_MPU | OCP_USER_SDMA, 4547 .user = OCP_USER_MPU | OCP_USER_SDMA,
5811}; 4548};
5812 4549
5813static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
5814 {
5815 .pa_start = 0x4a318000,
5816 .pa_end = 0x4a31807f,
5817 .flags = ADDR_TYPE_RT
5818 },
5819 { }
5820};
5821
5822/* l4_wkup -> timer1 */ 4550/* l4_wkup -> timer1 */
5823static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = { 4551static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
5824 .master = &omap44xx_l4_wkup_hwmod, 4552 .master = &omap44xx_l4_wkup_hwmod,
5825 .slave = &omap44xx_timer1_hwmod, 4553 .slave = &omap44xx_timer1_hwmod,
5826 .clk = "l4_wkup_clk_mux_ck", 4554 .clk = "l4_wkup_clk_mux_ck",
5827 .addr = omap44xx_timer1_addrs,
5828 .user = OCP_USER_MPU | OCP_USER_SDMA, 4555 .user = OCP_USER_MPU | OCP_USER_SDMA,
5829}; 4556};
5830 4557
5831static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
5832 {
5833 .pa_start = 0x48032000,
5834 .pa_end = 0x4803207f,
5835 .flags = ADDR_TYPE_RT
5836 },
5837 { }
5838};
5839
5840/* l4_per -> timer2 */ 4558/* l4_per -> timer2 */
5841static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = { 4559static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
5842 .master = &omap44xx_l4_per_hwmod, 4560 .master = &omap44xx_l4_per_hwmod,
5843 .slave = &omap44xx_timer2_hwmod, 4561 .slave = &omap44xx_timer2_hwmod,
5844 .clk = "l4_div_ck", 4562 .clk = "l4_div_ck",
5845 .addr = omap44xx_timer2_addrs,
5846 .user = OCP_USER_MPU | OCP_USER_SDMA, 4563 .user = OCP_USER_MPU | OCP_USER_SDMA,
5847}; 4564};
5848 4565
5849static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
5850 {
5851 .pa_start = 0x48034000,
5852 .pa_end = 0x4803407f,
5853 .flags = ADDR_TYPE_RT
5854 },
5855 { }
5856};
5857
5858/* l4_per -> timer3 */ 4566/* l4_per -> timer3 */
5859static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = { 4567static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
5860 .master = &omap44xx_l4_per_hwmod, 4568 .master = &omap44xx_l4_per_hwmod,
5861 .slave = &omap44xx_timer3_hwmod, 4569 .slave = &omap44xx_timer3_hwmod,
5862 .clk = "l4_div_ck", 4570 .clk = "l4_div_ck",
5863 .addr = omap44xx_timer3_addrs,
5864 .user = OCP_USER_MPU | OCP_USER_SDMA, 4571 .user = OCP_USER_MPU | OCP_USER_SDMA,
5865}; 4572};
5866 4573
5867static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
5868 {
5869 .pa_start = 0x48036000,
5870 .pa_end = 0x4803607f,
5871 .flags = ADDR_TYPE_RT
5872 },
5873 { }
5874};
5875
5876/* l4_per -> timer4 */ 4574/* l4_per -> timer4 */
5877static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = { 4575static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
5878 .master = &omap44xx_l4_per_hwmod, 4576 .master = &omap44xx_l4_per_hwmod,
5879 .slave = &omap44xx_timer4_hwmod, 4577 .slave = &omap44xx_timer4_hwmod,
5880 .clk = "l4_div_ck", 4578 .clk = "l4_div_ck",
5881 .addr = omap44xx_timer4_addrs,
5882 .user = OCP_USER_MPU | OCP_USER_SDMA, 4579 .user = OCP_USER_MPU | OCP_USER_SDMA,
5883}; 4580};
5884 4581
5885static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
5886 {
5887 .pa_start = 0x40138000,
5888 .pa_end = 0x4013807f,
5889 .flags = ADDR_TYPE_RT
5890 },
5891 { }
5892};
5893
5894/* l4_abe -> timer5 */ 4582/* l4_abe -> timer5 */
5895static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = { 4583static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
5896 .master = &omap44xx_l4_abe_hwmod, 4584 .master = &omap44xx_l4_abe_hwmod,
5897 .slave = &omap44xx_timer5_hwmod, 4585 .slave = &omap44xx_timer5_hwmod,
5898 .clk = "ocp_abe_iclk", 4586 .clk = "ocp_abe_iclk",
5899 .addr = omap44xx_timer5_addrs,
5900 .user = OCP_USER_MPU, 4587 .user = OCP_USER_MPU,
5901}; 4588};
5902 4589
5903static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
5904 {
5905 .pa_start = 0x49038000,
5906 .pa_end = 0x4903807f,
5907 .flags = ADDR_TYPE_RT
5908 },
5909 { }
5910};
5911
5912/* l4_abe -> timer5 (dma) */ 4590/* l4_abe -> timer5 (dma) */
5913static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = { 4591static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
5914 .master = &omap44xx_l4_abe_hwmod, 4592 .master = &omap44xx_l4_abe_hwmod,
5915 .slave = &omap44xx_timer5_hwmod, 4593 .slave = &omap44xx_timer5_hwmod,
5916 .clk = "ocp_abe_iclk", 4594 .clk = "ocp_abe_iclk",
5917 .addr = omap44xx_timer5_dma_addrs,
5918 .user = OCP_USER_SDMA, 4595 .user = OCP_USER_SDMA,
5919}; 4596};
5920 4597
5921static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
5922 {
5923 .pa_start = 0x4013a000,
5924 .pa_end = 0x4013a07f,
5925 .flags = ADDR_TYPE_RT
5926 },
5927 { }
5928};
5929
5930/* l4_abe -> timer6 */ 4598/* l4_abe -> timer6 */
5931static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = { 4599static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
5932 .master = &omap44xx_l4_abe_hwmod, 4600 .master = &omap44xx_l4_abe_hwmod,
5933 .slave = &omap44xx_timer6_hwmod, 4601 .slave = &omap44xx_timer6_hwmod,
5934 .clk = "ocp_abe_iclk", 4602 .clk = "ocp_abe_iclk",
5935 .addr = omap44xx_timer6_addrs,
5936 .user = OCP_USER_MPU, 4603 .user = OCP_USER_MPU,
5937}; 4604};
5938 4605
5939static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
5940 {
5941 .pa_start = 0x4903a000,
5942 .pa_end = 0x4903a07f,
5943 .flags = ADDR_TYPE_RT
5944 },
5945 { }
5946};
5947
5948/* l4_abe -> timer6 (dma) */ 4606/* l4_abe -> timer6 (dma) */
5949static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = { 4607static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
5950 .master = &omap44xx_l4_abe_hwmod, 4608 .master = &omap44xx_l4_abe_hwmod,
5951 .slave = &omap44xx_timer6_hwmod, 4609 .slave = &omap44xx_timer6_hwmod,
5952 .clk = "ocp_abe_iclk", 4610 .clk = "ocp_abe_iclk",
5953 .addr = omap44xx_timer6_dma_addrs,
5954 .user = OCP_USER_SDMA, 4611 .user = OCP_USER_SDMA,
5955}; 4612};
5956 4613
5957static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
5958 {
5959 .pa_start = 0x4013c000,
5960 .pa_end = 0x4013c07f,
5961 .flags = ADDR_TYPE_RT
5962 },
5963 { }
5964};
5965
5966/* l4_abe -> timer7 */ 4614/* l4_abe -> timer7 */
5967static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = { 4615static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
5968 .master = &omap44xx_l4_abe_hwmod, 4616 .master = &omap44xx_l4_abe_hwmod,
5969 .slave = &omap44xx_timer7_hwmod, 4617 .slave = &omap44xx_timer7_hwmod,
5970 .clk = "ocp_abe_iclk", 4618 .clk = "ocp_abe_iclk",
5971 .addr = omap44xx_timer7_addrs,
5972 .user = OCP_USER_MPU, 4619 .user = OCP_USER_MPU,
5973}; 4620};
5974 4621
5975static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
5976 {
5977 .pa_start = 0x4903c000,
5978 .pa_end = 0x4903c07f,
5979 .flags = ADDR_TYPE_RT
5980 },
5981 { }
5982};
5983
5984/* l4_abe -> timer7 (dma) */ 4622/* l4_abe -> timer7 (dma) */
5985static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = { 4623static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
5986 .master = &omap44xx_l4_abe_hwmod, 4624 .master = &omap44xx_l4_abe_hwmod,
5987 .slave = &omap44xx_timer7_hwmod, 4625 .slave = &omap44xx_timer7_hwmod,
5988 .clk = "ocp_abe_iclk", 4626 .clk = "ocp_abe_iclk",
5989 .addr = omap44xx_timer7_dma_addrs,
5990 .user = OCP_USER_SDMA, 4627 .user = OCP_USER_SDMA,
5991}; 4628};
5992 4629
5993static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
5994 {
5995 .pa_start = 0x4013e000,
5996 .pa_end = 0x4013e07f,
5997 .flags = ADDR_TYPE_RT
5998 },
5999 { }
6000};
6001
6002/* l4_abe -> timer8 */ 4630/* l4_abe -> timer8 */
6003static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = { 4631static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
6004 .master = &omap44xx_l4_abe_hwmod, 4632 .master = &omap44xx_l4_abe_hwmod,
6005 .slave = &omap44xx_timer8_hwmod, 4633 .slave = &omap44xx_timer8_hwmod,
6006 .clk = "ocp_abe_iclk", 4634 .clk = "ocp_abe_iclk",
6007 .addr = omap44xx_timer8_addrs,
6008 .user = OCP_USER_MPU, 4635 .user = OCP_USER_MPU,
6009}; 4636};
6010 4637
6011static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
6012 {
6013 .pa_start = 0x4903e000,
6014 .pa_end = 0x4903e07f,
6015 .flags = ADDR_TYPE_RT
6016 },
6017 { }
6018};
6019
6020/* l4_abe -> timer8 (dma) */ 4638/* l4_abe -> timer8 (dma) */
6021static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = { 4639static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
6022 .master = &omap44xx_l4_abe_hwmod, 4640 .master = &omap44xx_l4_abe_hwmod,
6023 .slave = &omap44xx_timer8_hwmod, 4641 .slave = &omap44xx_timer8_hwmod,
6024 .clk = "ocp_abe_iclk", 4642 .clk = "ocp_abe_iclk",
6025 .addr = omap44xx_timer8_dma_addrs,
6026 .user = OCP_USER_SDMA, 4643 .user = OCP_USER_SDMA,
6027}; 4644};
6028 4645
6029static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
6030 {
6031 .pa_start = 0x4803e000,
6032 .pa_end = 0x4803e07f,
6033 .flags = ADDR_TYPE_RT
6034 },
6035 { }
6036};
6037
6038/* l4_per -> timer9 */ 4646/* l4_per -> timer9 */
6039static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = { 4647static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
6040 .master = &omap44xx_l4_per_hwmod, 4648 .master = &omap44xx_l4_per_hwmod,
6041 .slave = &omap44xx_timer9_hwmod, 4649 .slave = &omap44xx_timer9_hwmod,
6042 .clk = "l4_div_ck", 4650 .clk = "l4_div_ck",
6043 .addr = omap44xx_timer9_addrs,
6044 .user = OCP_USER_MPU | OCP_USER_SDMA, 4651 .user = OCP_USER_MPU | OCP_USER_SDMA,
6045}; 4652};
6046 4653
6047static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
6048 {
6049 .pa_start = 0x48086000,
6050 .pa_end = 0x4808607f,
6051 .flags = ADDR_TYPE_RT
6052 },
6053 { }
6054};
6055
6056/* l4_per -> timer10 */ 4654/* l4_per -> timer10 */
6057static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = { 4655static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
6058 .master = &omap44xx_l4_per_hwmod, 4656 .master = &omap44xx_l4_per_hwmod,
6059 .slave = &omap44xx_timer10_hwmod, 4657 .slave = &omap44xx_timer10_hwmod,
6060 .clk = "l4_div_ck", 4658 .clk = "l4_div_ck",
6061 .addr = omap44xx_timer10_addrs,
6062 .user = OCP_USER_MPU | OCP_USER_SDMA, 4659 .user = OCP_USER_MPU | OCP_USER_SDMA,
6063}; 4660};
6064 4661
6065static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
6066 {
6067 .pa_start = 0x48088000,
6068 .pa_end = 0x4808807f,
6069 .flags = ADDR_TYPE_RT
6070 },
6071 { }
6072};
6073
6074/* l4_per -> timer11 */ 4662/* l4_per -> timer11 */
6075static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = { 4663static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
6076 .master = &omap44xx_l4_per_hwmod, 4664 .master = &omap44xx_l4_per_hwmod,
6077 .slave = &omap44xx_timer11_hwmod, 4665 .slave = &omap44xx_timer11_hwmod,
6078 .clk = "l4_div_ck", 4666 .clk = "l4_div_ck",
6079 .addr = omap44xx_timer11_addrs,
6080 .user = OCP_USER_MPU | OCP_USER_SDMA, 4667 .user = OCP_USER_MPU | OCP_USER_SDMA,
6081}; 4668};
6082 4669
6083static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
6084 {
6085 .pa_start = 0x4806a000,
6086 .pa_end = 0x4806a0ff,
6087 .flags = ADDR_TYPE_RT
6088 },
6089 { }
6090};
6091
6092/* l4_per -> uart1 */ 4670/* l4_per -> uart1 */
6093static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { 4671static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
6094 .master = &omap44xx_l4_per_hwmod, 4672 .master = &omap44xx_l4_per_hwmod,
6095 .slave = &omap44xx_uart1_hwmod, 4673 .slave = &omap44xx_uart1_hwmod,
6096 .clk = "l4_div_ck", 4674 .clk = "l4_div_ck",
6097 .addr = omap44xx_uart1_addrs,
6098 .user = OCP_USER_MPU | OCP_USER_SDMA, 4675 .user = OCP_USER_MPU | OCP_USER_SDMA,
6099}; 4676};
6100 4677
6101static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
6102 {
6103 .pa_start = 0x4806c000,
6104 .pa_end = 0x4806c0ff,
6105 .flags = ADDR_TYPE_RT
6106 },
6107 { }
6108};
6109
6110/* l4_per -> uart2 */ 4678/* l4_per -> uart2 */
6111static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { 4679static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
6112 .master = &omap44xx_l4_per_hwmod, 4680 .master = &omap44xx_l4_per_hwmod,
6113 .slave = &omap44xx_uart2_hwmod, 4681 .slave = &omap44xx_uart2_hwmod,
6114 .clk = "l4_div_ck", 4682 .clk = "l4_div_ck",
6115 .addr = omap44xx_uart2_addrs,
6116 .user = OCP_USER_MPU | OCP_USER_SDMA, 4683 .user = OCP_USER_MPU | OCP_USER_SDMA,
6117}; 4684};
6118 4685
6119static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
6120 {
6121 .pa_start = 0x48020000,
6122 .pa_end = 0x480200ff,
6123 .flags = ADDR_TYPE_RT
6124 },
6125 { }
6126};
6127
6128/* l4_per -> uart3 */ 4686/* l4_per -> uart3 */
6129static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { 4687static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
6130 .master = &omap44xx_l4_per_hwmod, 4688 .master = &omap44xx_l4_per_hwmod,
6131 .slave = &omap44xx_uart3_hwmod, 4689 .slave = &omap44xx_uart3_hwmod,
6132 .clk = "l4_div_ck", 4690 .clk = "l4_div_ck",
6133 .addr = omap44xx_uart3_addrs,
6134 .user = OCP_USER_MPU | OCP_USER_SDMA, 4691 .user = OCP_USER_MPU | OCP_USER_SDMA,
6135}; 4692};
6136 4693
6137static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
6138 {
6139 .pa_start = 0x4806e000,
6140 .pa_end = 0x4806e0ff,
6141 .flags = ADDR_TYPE_RT
6142 },
6143 { }
6144};
6145
6146/* l4_per -> uart4 */ 4694/* l4_per -> uart4 */
6147static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { 4695static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
6148 .master = &omap44xx_l4_per_hwmod, 4696 .master = &omap44xx_l4_per_hwmod,
6149 .slave = &omap44xx_uart4_hwmod, 4697 .slave = &omap44xx_uart4_hwmod,
6150 .clk = "l4_div_ck", 4698 .clk = "l4_div_ck",
6151 .addr = omap44xx_uart4_addrs,
6152 .user = OCP_USER_MPU | OCP_USER_SDMA, 4699 .user = OCP_USER_MPU | OCP_USER_SDMA,
6153}; 4700};
6154 4701
6155static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
6156 {
6157 .pa_start = 0x4a0a9000,
6158 .pa_end = 0x4a0a93ff,
6159 .flags = ADDR_TYPE_RT
6160 },
6161 { }
6162};
6163
6164/* l4_cfg -> usb_host_fs */ 4702/* l4_cfg -> usb_host_fs */
6165static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = { 4703static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
6166 .master = &omap44xx_l4_cfg_hwmod, 4704 .master = &omap44xx_l4_cfg_hwmod,
6167 .slave = &omap44xx_usb_host_fs_hwmod, 4705 .slave = &omap44xx_usb_host_fs_hwmod,
6168 .clk = "l4_div_ck", 4706 .clk = "l4_div_ck",
6169 .addr = omap44xx_usb_host_fs_addrs,
6170 .user = OCP_USER_MPU | OCP_USER_SDMA, 4707 .user = OCP_USER_MPU | OCP_USER_SDMA,
6171}; 4708};
6172 4709
6173static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
6174 {
6175 .name = "uhh",
6176 .pa_start = 0x4a064000,
6177 .pa_end = 0x4a0647ff,
6178 .flags = ADDR_TYPE_RT
6179 },
6180 {
6181 .name = "ohci",
6182 .pa_start = 0x4a064800,
6183 .pa_end = 0x4a064bff,
6184 },
6185 {
6186 .name = "ehci",
6187 .pa_start = 0x4a064c00,
6188 .pa_end = 0x4a064fff,
6189 },
6190 {}
6191};
6192
6193/* l4_cfg -> usb_host_hs */ 4710/* l4_cfg -> usb_host_hs */
6194static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = { 4711static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
6195 .master = &omap44xx_l4_cfg_hwmod, 4712 .master = &omap44xx_l4_cfg_hwmod,
6196 .slave = &omap44xx_usb_host_hs_hwmod, 4713 .slave = &omap44xx_usb_host_hs_hwmod,
6197 .clk = "l4_div_ck", 4714 .clk = "l4_div_ck",
6198 .addr = omap44xx_usb_host_hs_addrs,
6199 .user = OCP_USER_MPU | OCP_USER_SDMA, 4715 .user = OCP_USER_MPU | OCP_USER_SDMA,
6200}; 4716};
6201 4717
6202static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
6203 {
6204 .pa_start = 0x4a0ab000,
6205 .pa_end = 0x4a0ab7ff,
6206 .flags = ADDR_TYPE_RT
6207 },
6208 { }
6209};
6210
6211/* l4_cfg -> usb_otg_hs */ 4718/* l4_cfg -> usb_otg_hs */
6212static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = { 4719static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
6213 .master = &omap44xx_l4_cfg_hwmod, 4720 .master = &omap44xx_l4_cfg_hwmod,
6214 .slave = &omap44xx_usb_otg_hs_hwmod, 4721 .slave = &omap44xx_usb_otg_hs_hwmod,
6215 .clk = "l4_div_ck", 4722 .clk = "l4_div_ck",
6216 .addr = omap44xx_usb_otg_hs_addrs,
6217 .user = OCP_USER_MPU | OCP_USER_SDMA, 4723 .user = OCP_USER_MPU | OCP_USER_SDMA,
6218}; 4724};
6219 4725
6220static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
6221 {
6222 .name = "tll",
6223 .pa_start = 0x4a062000,
6224 .pa_end = 0x4a063fff,
6225 .flags = ADDR_TYPE_RT
6226 },
6227 {}
6228};
6229
6230/* l4_cfg -> usb_tll_hs */ 4726/* l4_cfg -> usb_tll_hs */
6231static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = { 4727static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
6232 .master = &omap44xx_l4_cfg_hwmod, 4728 .master = &omap44xx_l4_cfg_hwmod,
6233 .slave = &omap44xx_usb_tll_hs_hwmod, 4729 .slave = &omap44xx_usb_tll_hs_hwmod,
6234 .clk = "l4_div_ck", 4730 .clk = "l4_div_ck",
6235 .addr = omap44xx_usb_tll_hs_addrs,
6236 .user = OCP_USER_MPU | OCP_USER_SDMA, 4731 .user = OCP_USER_MPU | OCP_USER_SDMA,
6237}; 4732};
6238 4733
6239static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
6240 {
6241 .pa_start = 0x4a314000,
6242 .pa_end = 0x4a31407f,
6243 .flags = ADDR_TYPE_RT
6244 },
6245 { }
6246};
6247
6248/* l4_wkup -> wd_timer2 */ 4734/* l4_wkup -> wd_timer2 */
6249static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { 4735static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
6250 .master = &omap44xx_l4_wkup_hwmod, 4736 .master = &omap44xx_l4_wkup_hwmod,
6251 .slave = &omap44xx_wd_timer2_hwmod, 4737 .slave = &omap44xx_wd_timer2_hwmod,
6252 .clk = "l4_wkup_clk_mux_ck", 4738 .clk = "l4_wkup_clk_mux_ck",
6253 .addr = omap44xx_wd_timer2_addrs,
6254 .user = OCP_USER_MPU | OCP_USER_SDMA, 4739 .user = OCP_USER_MPU | OCP_USER_SDMA,
6255}; 4740};
6256 4741
@@ -6290,14 +4775,25 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
6290 .user = OCP_USER_SDMA, 4775 .user = OCP_USER_SDMA,
6291}; 4776};
6292 4777
4778/* mpu -> emif1 */
4779static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
4780 .master = &omap44xx_mpu_hwmod,
4781 .slave = &omap44xx_emif1_hwmod,
4782 .clk = "l3_div_ck",
4783 .user = OCP_USER_MPU | OCP_USER_SDMA,
4784};
4785
4786/* mpu -> emif2 */
4787static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
4788 .master = &omap44xx_mpu_hwmod,
4789 .slave = &omap44xx_emif2_hwmod,
4790 .clk = "l3_div_ck",
4791 .user = OCP_USER_MPU | OCP_USER_SDMA,
4792};
4793
6293static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { 4794static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
6294 &omap44xx_c2c__c2c_target_fw,
6295 &omap44xx_l4_cfg__c2c_target_fw,
6296 &omap44xx_l3_main_1__dmm, 4795 &omap44xx_l3_main_1__dmm,
6297 &omap44xx_mpu__dmm, 4796 &omap44xx_mpu__dmm,
6298 &omap44xx_c2c__emif_fw,
6299 &omap44xx_dmm__emif_fw,
6300 &omap44xx_l4_cfg__emif_fw,
6301 &omap44xx_iva__l3_instr, 4797 &omap44xx_iva__l3_instr,
6302 &omap44xx_l3_main_3__l3_instr, 4798 &omap44xx_l3_main_3__l3_instr,
6303 &omap44xx_ocp_wp_noc__l3_instr, 4799 &omap44xx_ocp_wp_noc__l3_instr,
@@ -6308,7 +4804,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
6308 &omap44xx_mmc1__l3_main_1, 4804 &omap44xx_mmc1__l3_main_1,
6309 &omap44xx_mmc2__l3_main_1, 4805 &omap44xx_mmc2__l3_main_1,
6310 &omap44xx_mpu__l3_main_1, 4806 &omap44xx_mpu__l3_main_1,
6311 &omap44xx_c2c_target_fw__l3_main_2,
6312 &omap44xx_debugss__l3_main_2, 4807 &omap44xx_debugss__l3_main_2,
6313 &omap44xx_dma_system__l3_main_2, 4808 &omap44xx_dma_system__l3_main_2,
6314 &omap44xx_fdif__l3_main_2, 4809 &omap44xx_fdif__l3_main_2,
@@ -6364,8 +4859,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
6364 &omap44xx_l3_main_2__dss_venc, 4859 &omap44xx_l3_main_2__dss_venc,
6365 &omap44xx_l4_per__dss_venc, 4860 &omap44xx_l4_per__dss_venc,
6366 &omap44xx_l4_per__elm, 4861 &omap44xx_l4_per__elm,
6367 &omap44xx_emif_fw__emif1,
6368 &omap44xx_emif_fw__emif2,
6369 &omap44xx_l4_cfg__fdif, 4862 &omap44xx_l4_cfg__fdif,
6370 &omap44xx_l4_wkup__gpio1, 4863 &omap44xx_l4_wkup__gpio1,
6371 &omap44xx_l4_per__gpio2, 4864 &omap44xx_l4_per__gpio2,
@@ -6450,6 +4943,8 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
6450 &omap44xx_l4_wkup__wd_timer2, 4943 &omap44xx_l4_wkup__wd_timer2,
6451 &omap44xx_l4_abe__wd_timer3, 4944 &omap44xx_l4_abe__wd_timer3,
6452 &omap44xx_l4_abe__wd_timer3_dma, 4945 &omap44xx_l4_abe__wd_timer3_dma,
4946 &omap44xx_mpu__emif1,
4947 &omap44xx_mpu__emif2,
6453 NULL, 4948 NULL,
6454}; 4949};
6455 4950
diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
new file mode 100644
index 000000000000..3c70f5c1860f
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
@@ -0,0 +1,2151 @@
1/*
2 * Hardware modules present on the OMAP54xx chips
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley
7 * Benoit Cousson
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#include <linux/io.h>
21#include <linux/platform_data/gpio-omap.h>
22#include <linux/power/smartreflex.h>
23#include <linux/i2c-omap.h>
24
25#include <linux/omap-dma.h>
26#include <linux/platform_data/spi-omap2-mcspi.h>
27#include <linux/platform_data/asoc-ti-mcbsp.h>
28#include <plat/dmtimer.h>
29
30#include "omap_hwmod.h"
31#include "omap_hwmod_common_data.h"
32#include "cm1_54xx.h"
33#include "cm2_54xx.h"
34#include "prm54xx.h"
35#include "prm-regbits-54xx.h"
36#include "i2c.h"
37#include "mmc.h"
38#include "wd_timer.h"
39
40/* Base offset for all OMAP5 interrupts external to MPUSS */
41#define OMAP54XX_IRQ_GIC_START 32
42
43/* Base offset for all OMAP5 dma requests */
44#define OMAP54XX_DMA_REQ_START 1
45
46
47/*
48 * IP blocks
49 */
50
51/*
52 * 'dmm' class
53 * instance(s): dmm
54 */
55static struct omap_hwmod_class omap54xx_dmm_hwmod_class = {
56 .name = "dmm",
57};
58
59/* dmm */
60static struct omap_hwmod omap54xx_dmm_hwmod = {
61 .name = "dmm",
62 .class = &omap54xx_dmm_hwmod_class,
63 .clkdm_name = "emif_clkdm",
64 .prcm = {
65 .omap4 = {
66 .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
67 .context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET,
68 },
69 },
70};
71
72/*
73 * 'l3' class
74 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
75 */
76static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
77 .name = "l3",
78};
79
80/* l3_instr */
81static struct omap_hwmod omap54xx_l3_instr_hwmod = {
82 .name = "l3_instr",
83 .class = &omap54xx_l3_hwmod_class,
84 .clkdm_name = "l3instr_clkdm",
85 .prcm = {
86 .omap4 = {
87 .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
88 .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
89 .modulemode = MODULEMODE_HWCTRL,
90 },
91 },
92};
93
94/* l3_main_1 */
95static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
96 .name = "l3_main_1",
97 .class = &omap54xx_l3_hwmod_class,
98 .clkdm_name = "l3main1_clkdm",
99 .prcm = {
100 .omap4 = {
101 .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
102 .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
103 },
104 },
105};
106
107/* l3_main_2 */
108static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
109 .name = "l3_main_2",
110 .class = &omap54xx_l3_hwmod_class,
111 .clkdm_name = "l3main2_clkdm",
112 .prcm = {
113 .omap4 = {
114 .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
115 .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
116 },
117 },
118};
119
120/* l3_main_3 */
121static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
122 .name = "l3_main_3",
123 .class = &omap54xx_l3_hwmod_class,
124 .clkdm_name = "l3instr_clkdm",
125 .prcm = {
126 .omap4 = {
127 .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
128 .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
129 .modulemode = MODULEMODE_HWCTRL,
130 },
131 },
132};
133
134/*
135 * 'l4' class
136 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
137 */
138static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
139 .name = "l4",
140};
141
142/* l4_abe */
143static struct omap_hwmod omap54xx_l4_abe_hwmod = {
144 .name = "l4_abe",
145 .class = &omap54xx_l4_hwmod_class,
146 .clkdm_name = "abe_clkdm",
147 .prcm = {
148 .omap4 = {
149 .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET,
150 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
151 },
152 },
153};
154
155/* l4_cfg */
156static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
157 .name = "l4_cfg",
158 .class = &omap54xx_l4_hwmod_class,
159 .clkdm_name = "l4cfg_clkdm",
160 .prcm = {
161 .omap4 = {
162 .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
163 .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
164 },
165 },
166};
167
168/* l4_per */
169static struct omap_hwmod omap54xx_l4_per_hwmod = {
170 .name = "l4_per",
171 .class = &omap54xx_l4_hwmod_class,
172 .clkdm_name = "l4per_clkdm",
173 .prcm = {
174 .omap4 = {
175 .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
176 .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
177 },
178 },
179};
180
181/* l4_wkup */
182static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
183 .name = "l4_wkup",
184 .class = &omap54xx_l4_hwmod_class,
185 .clkdm_name = "wkupaon_clkdm",
186 .prcm = {
187 .omap4 = {
188 .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
189 .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
190 },
191 },
192};
193
194/*
195 * 'mpu_bus' class
196 * instance(s): mpu_private
197 */
198static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
199 .name = "mpu_bus",
200};
201
202/* mpu_private */
203static struct omap_hwmod omap54xx_mpu_private_hwmod = {
204 .name = "mpu_private",
205 .class = &omap54xx_mpu_bus_hwmod_class,
206 .clkdm_name = "mpu_clkdm",
207 .prcm = {
208 .omap4 = {
209 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
210 },
211 },
212};
213
214/*
215 * 'counter' class
216 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
217 */
218
219static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = {
220 .rev_offs = 0x0000,
221 .sysc_offs = 0x0010,
222 .sysc_flags = SYSC_HAS_SIDLEMODE,
223 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
224 .sysc_fields = &omap_hwmod_sysc_type1,
225};
226
227static struct omap_hwmod_class omap54xx_counter_hwmod_class = {
228 .name = "counter",
229 .sysc = &omap54xx_counter_sysc,
230};
231
232/* counter_32k */
233static struct omap_hwmod omap54xx_counter_32k_hwmod = {
234 .name = "counter_32k",
235 .class = &omap54xx_counter_hwmod_class,
236 .clkdm_name = "wkupaon_clkdm",
237 .flags = HWMOD_SWSUP_SIDLE,
238 .main_clk = "wkupaon_iclk_mux",
239 .prcm = {
240 .omap4 = {
241 .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
242 .context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
243 },
244 },
245};
246
247/*
248 * 'dma' class
249 * dma controller for data exchange between memory to memory (i.e. internal or
250 * external memory) and gp peripherals to memory or memory to gp peripherals
251 */
252
253static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc = {
254 .rev_offs = 0x0000,
255 .sysc_offs = 0x002c,
256 .syss_offs = 0x0028,
257 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
258 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
259 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
260 SYSS_HAS_RESET_STATUS),
261 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
262 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
263 .sysc_fields = &omap_hwmod_sysc_type1,
264};
265
266static struct omap_hwmod_class omap54xx_dma_hwmod_class = {
267 .name = "dma",
268 .sysc = &omap54xx_dma_sysc,
269};
270
271/* dma dev_attr */
272static struct omap_dma_dev_attr dma_dev_attr = {
273 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
274 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
275 .lch_count = 32,
276};
277
278/* dma_system */
279static struct omap_hwmod_irq_info omap54xx_dma_system_irqs[] = {
280 { .name = "0", .irq = 12 + OMAP54XX_IRQ_GIC_START },
281 { .name = "1", .irq = 13 + OMAP54XX_IRQ_GIC_START },
282 { .name = "2", .irq = 14 + OMAP54XX_IRQ_GIC_START },
283 { .name = "3", .irq = 15 + OMAP54XX_IRQ_GIC_START },
284 { .irq = -1 }
285};
286
287static struct omap_hwmod omap54xx_dma_system_hwmod = {
288 .name = "dma_system",
289 .class = &omap54xx_dma_hwmod_class,
290 .clkdm_name = "dma_clkdm",
291 .mpu_irqs = omap54xx_dma_system_irqs,
292 .main_clk = "l3_iclk_div",
293 .prcm = {
294 .omap4 = {
295 .clkctrl_offs = OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
296 .context_offs = OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
297 },
298 },
299 .dev_attr = &dma_dev_attr,
300};
301
302/*
303 * 'dmic' class
304 * digital microphone controller
305 */
306
307static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc = {
308 .rev_offs = 0x0000,
309 .sysc_offs = 0x0010,
310 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
311 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
312 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
313 SIDLE_SMART_WKUP),
314 .sysc_fields = &omap_hwmod_sysc_type2,
315};
316
317static struct omap_hwmod_class omap54xx_dmic_hwmod_class = {
318 .name = "dmic",
319 .sysc = &omap54xx_dmic_sysc,
320};
321
322/* dmic */
323static struct omap_hwmod omap54xx_dmic_hwmod = {
324 .name = "dmic",
325 .class = &omap54xx_dmic_hwmod_class,
326 .clkdm_name = "abe_clkdm",
327 .main_clk = "dmic_gfclk",
328 .prcm = {
329 .omap4 = {
330 .clkctrl_offs = OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET,
331 .context_offs = OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET,
332 .modulemode = MODULEMODE_SWCTRL,
333 },
334 },
335};
336
337/*
338 * 'emif' class
339 * external memory interface no1 (wrapper)
340 */
341
342static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
343 .rev_offs = 0x0000,
344};
345
346static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
347 .name = "emif",
348 .sysc = &omap54xx_emif_sysc,
349};
350
351/* emif1 */
352static struct omap_hwmod omap54xx_emif1_hwmod = {
353 .name = "emif1",
354 .class = &omap54xx_emif_hwmod_class,
355 .clkdm_name = "emif_clkdm",
356 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
357 .main_clk = "dpll_core_h11x2_ck",
358 .prcm = {
359 .omap4 = {
360 .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
361 .context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
362 .modulemode = MODULEMODE_HWCTRL,
363 },
364 },
365};
366
367/* emif2 */
368static struct omap_hwmod omap54xx_emif2_hwmod = {
369 .name = "emif2",
370 .class = &omap54xx_emif_hwmod_class,
371 .clkdm_name = "emif_clkdm",
372 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
373 .main_clk = "dpll_core_h11x2_ck",
374 .prcm = {
375 .omap4 = {
376 .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
377 .context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
378 .modulemode = MODULEMODE_HWCTRL,
379 },
380 },
381};
382
383/*
384 * 'gpio' class
385 * general purpose io module
386 */
387
388static struct omap_hwmod_class_sysconfig omap54xx_gpio_sysc = {
389 .rev_offs = 0x0000,
390 .sysc_offs = 0x0010,
391 .syss_offs = 0x0114,
392 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
393 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
394 SYSS_HAS_RESET_STATUS),
395 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
396 SIDLE_SMART_WKUP),
397 .sysc_fields = &omap_hwmod_sysc_type1,
398};
399
400static struct omap_hwmod_class omap54xx_gpio_hwmod_class = {
401 .name = "gpio",
402 .sysc = &omap54xx_gpio_sysc,
403 .rev = 2,
404};
405
406/* gpio dev_attr */
407static struct omap_gpio_dev_attr gpio_dev_attr = {
408 .bank_width = 32,
409 .dbck_flag = true,
410};
411
412/* gpio1 */
413static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
414 { .role = "dbclk", .clk = "gpio1_dbclk" },
415};
416
417static struct omap_hwmod omap54xx_gpio1_hwmod = {
418 .name = "gpio1",
419 .class = &omap54xx_gpio_hwmod_class,
420 .clkdm_name = "wkupaon_clkdm",
421 .main_clk = "wkupaon_iclk_mux",
422 .prcm = {
423 .omap4 = {
424 .clkctrl_offs = OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
425 .context_offs = OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
426 .modulemode = MODULEMODE_HWCTRL,
427 },
428 },
429 .opt_clks = gpio1_opt_clks,
430 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
431 .dev_attr = &gpio_dev_attr,
432};
433
434/* gpio2 */
435static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
436 { .role = "dbclk", .clk = "gpio2_dbclk" },
437};
438
439static struct omap_hwmod omap54xx_gpio2_hwmod = {
440 .name = "gpio2",
441 .class = &omap54xx_gpio_hwmod_class,
442 .clkdm_name = "l4per_clkdm",
443 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
444 .main_clk = "l4_root_clk_div",
445 .prcm = {
446 .omap4 = {
447 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
448 .context_offs = OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
449 .modulemode = MODULEMODE_HWCTRL,
450 },
451 },
452 .opt_clks = gpio2_opt_clks,
453 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
454 .dev_attr = &gpio_dev_attr,
455};
456
457/* gpio3 */
458static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
459 { .role = "dbclk", .clk = "gpio3_dbclk" },
460};
461
462static struct omap_hwmod omap54xx_gpio3_hwmod = {
463 .name = "gpio3",
464 .class = &omap54xx_gpio_hwmod_class,
465 .clkdm_name = "l4per_clkdm",
466 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
467 .main_clk = "l4_root_clk_div",
468 .prcm = {
469 .omap4 = {
470 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
471 .context_offs = OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
472 .modulemode = MODULEMODE_HWCTRL,
473 },
474 },
475 .opt_clks = gpio3_opt_clks,
476 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
477 .dev_attr = &gpio_dev_attr,
478};
479
480/* gpio4 */
481static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
482 { .role = "dbclk", .clk = "gpio4_dbclk" },
483};
484
485static struct omap_hwmod omap54xx_gpio4_hwmod = {
486 .name = "gpio4",
487 .class = &omap54xx_gpio_hwmod_class,
488 .clkdm_name = "l4per_clkdm",
489 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
490 .main_clk = "l4_root_clk_div",
491 .prcm = {
492 .omap4 = {
493 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
494 .context_offs = OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
495 .modulemode = MODULEMODE_HWCTRL,
496 },
497 },
498 .opt_clks = gpio4_opt_clks,
499 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
500 .dev_attr = &gpio_dev_attr,
501};
502
503/* gpio5 */
504static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
505 { .role = "dbclk", .clk = "gpio5_dbclk" },
506};
507
508static struct omap_hwmod omap54xx_gpio5_hwmod = {
509 .name = "gpio5",
510 .class = &omap54xx_gpio_hwmod_class,
511 .clkdm_name = "l4per_clkdm",
512 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
513 .main_clk = "l4_root_clk_div",
514 .prcm = {
515 .omap4 = {
516 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
517 .context_offs = OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
518 .modulemode = MODULEMODE_HWCTRL,
519 },
520 },
521 .opt_clks = gpio5_opt_clks,
522 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
523 .dev_attr = &gpio_dev_attr,
524};
525
526/* gpio6 */
527static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
528 { .role = "dbclk", .clk = "gpio6_dbclk" },
529};
530
531static struct omap_hwmod omap54xx_gpio6_hwmod = {
532 .name = "gpio6",
533 .class = &omap54xx_gpio_hwmod_class,
534 .clkdm_name = "l4per_clkdm",
535 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
536 .main_clk = "l4_root_clk_div",
537 .prcm = {
538 .omap4 = {
539 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
540 .context_offs = OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
541 .modulemode = MODULEMODE_HWCTRL,
542 },
543 },
544 .opt_clks = gpio6_opt_clks,
545 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
546 .dev_attr = &gpio_dev_attr,
547};
548
549/* gpio7 */
550static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
551 { .role = "dbclk", .clk = "gpio7_dbclk" },
552};
553
554static struct omap_hwmod omap54xx_gpio7_hwmod = {
555 .name = "gpio7",
556 .class = &omap54xx_gpio_hwmod_class,
557 .clkdm_name = "l4per_clkdm",
558 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
559 .main_clk = "l4_root_clk_div",
560 .prcm = {
561 .omap4 = {
562 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
563 .context_offs = OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
564 .modulemode = MODULEMODE_HWCTRL,
565 },
566 },
567 .opt_clks = gpio7_opt_clks,
568 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
569 .dev_attr = &gpio_dev_attr,
570};
571
572/* gpio8 */
573static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
574 { .role = "dbclk", .clk = "gpio8_dbclk" },
575};
576
577static struct omap_hwmod omap54xx_gpio8_hwmod = {
578 .name = "gpio8",
579 .class = &omap54xx_gpio_hwmod_class,
580 .clkdm_name = "l4per_clkdm",
581 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
582 .main_clk = "l4_root_clk_div",
583 .prcm = {
584 .omap4 = {
585 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
586 .context_offs = OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
587 .modulemode = MODULEMODE_HWCTRL,
588 },
589 },
590 .opt_clks = gpio8_opt_clks,
591 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
592 .dev_attr = &gpio_dev_attr,
593};
594
595/*
596 * 'i2c' class
597 * multimaster high-speed i2c controller
598 */
599
600static struct omap_hwmod_class_sysconfig omap54xx_i2c_sysc = {
601 .sysc_offs = 0x0010,
602 .syss_offs = 0x0090,
603 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
604 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
605 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
606 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
607 SIDLE_SMART_WKUP),
608 .clockact = CLOCKACT_TEST_ICLK,
609 .sysc_fields = &omap_hwmod_sysc_type1,
610};
611
612static struct omap_hwmod_class omap54xx_i2c_hwmod_class = {
613 .name = "i2c",
614 .sysc = &omap54xx_i2c_sysc,
615 .reset = &omap_i2c_reset,
616 .rev = OMAP_I2C_IP_VERSION_2,
617};
618
619/* i2c dev_attr */
620static struct omap_i2c_dev_attr i2c_dev_attr = {
621 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
622};
623
624/* i2c1 */
625static struct omap_hwmod omap54xx_i2c1_hwmod = {
626 .name = "i2c1",
627 .class = &omap54xx_i2c_hwmod_class,
628 .clkdm_name = "l4per_clkdm",
629 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
630 .main_clk = "func_96m_fclk",
631 .prcm = {
632 .omap4 = {
633 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
634 .context_offs = OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
635 .modulemode = MODULEMODE_SWCTRL,
636 },
637 },
638 .dev_attr = &i2c_dev_attr,
639};
640
641/* i2c2 */
642static struct omap_hwmod omap54xx_i2c2_hwmod = {
643 .name = "i2c2",
644 .class = &omap54xx_i2c_hwmod_class,
645 .clkdm_name = "l4per_clkdm",
646 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
647 .main_clk = "func_96m_fclk",
648 .prcm = {
649 .omap4 = {
650 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
651 .context_offs = OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
652 .modulemode = MODULEMODE_SWCTRL,
653 },
654 },
655 .dev_attr = &i2c_dev_attr,
656};
657
658/* i2c3 */
659static struct omap_hwmod omap54xx_i2c3_hwmod = {
660 .name = "i2c3",
661 .class = &omap54xx_i2c_hwmod_class,
662 .clkdm_name = "l4per_clkdm",
663 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
664 .main_clk = "func_96m_fclk",
665 .prcm = {
666 .omap4 = {
667 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
668 .context_offs = OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
669 .modulemode = MODULEMODE_SWCTRL,
670 },
671 },
672 .dev_attr = &i2c_dev_attr,
673};
674
675/* i2c4 */
676static struct omap_hwmod omap54xx_i2c4_hwmod = {
677 .name = "i2c4",
678 .class = &omap54xx_i2c_hwmod_class,
679 .clkdm_name = "l4per_clkdm",
680 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
681 .main_clk = "func_96m_fclk",
682 .prcm = {
683 .omap4 = {
684 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
685 .context_offs = OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
686 .modulemode = MODULEMODE_SWCTRL,
687 },
688 },
689 .dev_attr = &i2c_dev_attr,
690};
691
692/* i2c5 */
693static struct omap_hwmod omap54xx_i2c5_hwmod = {
694 .name = "i2c5",
695 .class = &omap54xx_i2c_hwmod_class,
696 .clkdm_name = "l4per_clkdm",
697 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
698 .main_clk = "func_96m_fclk",
699 .prcm = {
700 .omap4 = {
701 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET,
702 .context_offs = OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET,
703 .modulemode = MODULEMODE_SWCTRL,
704 },
705 },
706 .dev_attr = &i2c_dev_attr,
707};
708
709/*
710 * 'kbd' class
711 * keyboard controller
712 */
713
714static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc = {
715 .rev_offs = 0x0000,
716 .sysc_offs = 0x0010,
717 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
718 SYSC_HAS_SOFTRESET),
719 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
720 .sysc_fields = &omap_hwmod_sysc_type1,
721};
722
723static struct omap_hwmod_class omap54xx_kbd_hwmod_class = {
724 .name = "kbd",
725 .sysc = &omap54xx_kbd_sysc,
726};
727
728/* kbd */
729static struct omap_hwmod omap54xx_kbd_hwmod = {
730 .name = "kbd",
731 .class = &omap54xx_kbd_hwmod_class,
732 .clkdm_name = "wkupaon_clkdm",
733 .main_clk = "sys_32k_ck",
734 .prcm = {
735 .omap4 = {
736 .clkctrl_offs = OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET,
737 .context_offs = OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET,
738 .modulemode = MODULEMODE_SWCTRL,
739 },
740 },
741};
742
743/*
744 * 'mcbsp' class
745 * multi channel buffered serial port controller
746 */
747
748static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc = {
749 .sysc_offs = 0x008c,
750 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
751 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
752 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
753 .sysc_fields = &omap_hwmod_sysc_type1,
754};
755
756static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = {
757 .name = "mcbsp",
758 .sysc = &omap54xx_mcbsp_sysc,
759 .rev = MCBSP_CONFIG_TYPE4,
760};
761
762/* mcbsp1 */
763static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
764 { .role = "pad_fck", .clk = "pad_clks_ck" },
765 { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
766};
767
768static struct omap_hwmod omap54xx_mcbsp1_hwmod = {
769 .name = "mcbsp1",
770 .class = &omap54xx_mcbsp_hwmod_class,
771 .clkdm_name = "abe_clkdm",
772 .main_clk = "mcbsp1_gfclk",
773 .prcm = {
774 .omap4 = {
775 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET,
776 .context_offs = OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET,
777 .modulemode = MODULEMODE_SWCTRL,
778 },
779 },
780 .opt_clks = mcbsp1_opt_clks,
781 .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
782};
783
784/* mcbsp2 */
785static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
786 { .role = "pad_fck", .clk = "pad_clks_ck" },
787 { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
788};
789
790static struct omap_hwmod omap54xx_mcbsp2_hwmod = {
791 .name = "mcbsp2",
792 .class = &omap54xx_mcbsp_hwmod_class,
793 .clkdm_name = "abe_clkdm",
794 .main_clk = "mcbsp2_gfclk",
795 .prcm = {
796 .omap4 = {
797 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET,
798 .context_offs = OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET,
799 .modulemode = MODULEMODE_SWCTRL,
800 },
801 },
802 .opt_clks = mcbsp2_opt_clks,
803 .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
804};
805
806/* mcbsp3 */
807static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
808 { .role = "pad_fck", .clk = "pad_clks_ck" },
809 { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
810};
811
812static struct omap_hwmod omap54xx_mcbsp3_hwmod = {
813 .name = "mcbsp3",
814 .class = &omap54xx_mcbsp_hwmod_class,
815 .clkdm_name = "abe_clkdm",
816 .main_clk = "mcbsp3_gfclk",
817 .prcm = {
818 .omap4 = {
819 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET,
820 .context_offs = OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET,
821 .modulemode = MODULEMODE_SWCTRL,
822 },
823 },
824 .opt_clks = mcbsp3_opt_clks,
825 .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
826};
827
828/*
829 * 'mcpdm' class
830 * multi channel pdm controller (proprietary interface with phoenix power
831 * ic)
832 */
833
834static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc = {
835 .rev_offs = 0x0000,
836 .sysc_offs = 0x0010,
837 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
838 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
839 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
840 SIDLE_SMART_WKUP),
841 .sysc_fields = &omap_hwmod_sysc_type2,
842};
843
844static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class = {
845 .name = "mcpdm",
846 .sysc = &omap54xx_mcpdm_sysc,
847};
848
849/* mcpdm */
850static struct omap_hwmod omap54xx_mcpdm_hwmod = {
851 .name = "mcpdm",
852 .class = &omap54xx_mcpdm_hwmod_class,
853 .clkdm_name = "abe_clkdm",
854 /*
855 * It's suspected that the McPDM requires an off-chip main
856 * functional clock, controlled via I2C. This IP block is
857 * currently reset very early during boot, before I2C is
858 * available, so it doesn't seem that we have any choice in
859 * the kernel other than to avoid resetting it. XXX This is
860 * really a hardware issue workaround: every IP block should
861 * be able to source its main functional clock from either
862 * on-chip or off-chip sources. McPDM seems to be the only
863 * current exception.
864 */
865
866 .flags = HWMOD_EXT_OPT_MAIN_CLK,
867 .main_clk = "pad_clks_ck",
868 .prcm = {
869 .omap4 = {
870 .clkctrl_offs = OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET,
871 .context_offs = OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET,
872 .modulemode = MODULEMODE_SWCTRL,
873 },
874 },
875};
876
877/*
878 * 'mcspi' class
879 * multichannel serial port interface (mcspi) / master/slave synchronous serial
880 * bus
881 */
882
883static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc = {
884 .rev_offs = 0x0000,
885 .sysc_offs = 0x0010,
886 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
887 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
888 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
889 SIDLE_SMART_WKUP),
890 .sysc_fields = &omap_hwmod_sysc_type2,
891};
892
893static struct omap_hwmod_class omap54xx_mcspi_hwmod_class = {
894 .name = "mcspi",
895 .sysc = &omap54xx_mcspi_sysc,
896 .rev = OMAP4_MCSPI_REV,
897};
898
899/* mcspi1 */
900/* mcspi1 dev_attr */
901static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
902 .num_chipselect = 4,
903};
904
905static struct omap_hwmod omap54xx_mcspi1_hwmod = {
906 .name = "mcspi1",
907 .class = &omap54xx_mcspi_hwmod_class,
908 .clkdm_name = "l4per_clkdm",
909 .main_clk = "func_48m_fclk",
910 .prcm = {
911 .omap4 = {
912 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
913 .context_offs = OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
914 .modulemode = MODULEMODE_SWCTRL,
915 },
916 },
917 .dev_attr = &mcspi1_dev_attr,
918};
919
920/* mcspi2 */
921/* mcspi2 dev_attr */
922static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
923 .num_chipselect = 2,
924};
925
926static struct omap_hwmod omap54xx_mcspi2_hwmod = {
927 .name = "mcspi2",
928 .class = &omap54xx_mcspi_hwmod_class,
929 .clkdm_name = "l4per_clkdm",
930 .main_clk = "func_48m_fclk",
931 .prcm = {
932 .omap4 = {
933 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
934 .context_offs = OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
935 .modulemode = MODULEMODE_SWCTRL,
936 },
937 },
938 .dev_attr = &mcspi2_dev_attr,
939};
940
941/* mcspi3 */
942/* mcspi3 dev_attr */
943static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
944 .num_chipselect = 2,
945};
946
947static struct omap_hwmod omap54xx_mcspi3_hwmod = {
948 .name = "mcspi3",
949 .class = &omap54xx_mcspi_hwmod_class,
950 .clkdm_name = "l4per_clkdm",
951 .main_clk = "func_48m_fclk",
952 .prcm = {
953 .omap4 = {
954 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
955 .context_offs = OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
956 .modulemode = MODULEMODE_SWCTRL,
957 },
958 },
959 .dev_attr = &mcspi3_dev_attr,
960};
961
962/* mcspi4 */
963/* mcspi4 dev_attr */
964static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
965 .num_chipselect = 1,
966};
967
968static struct omap_hwmod omap54xx_mcspi4_hwmod = {
969 .name = "mcspi4",
970 .class = &omap54xx_mcspi_hwmod_class,
971 .clkdm_name = "l4per_clkdm",
972 .main_clk = "func_48m_fclk",
973 .prcm = {
974 .omap4 = {
975 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
976 .context_offs = OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
977 .modulemode = MODULEMODE_SWCTRL,
978 },
979 },
980 .dev_attr = &mcspi4_dev_attr,
981};
982
983/*
984 * 'mmc' class
985 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
986 */
987
988static struct omap_hwmod_class_sysconfig omap54xx_mmc_sysc = {
989 .rev_offs = 0x0000,
990 .sysc_offs = 0x0010,
991 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
992 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
993 SYSC_HAS_SOFTRESET),
994 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
995 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
996 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
997 .sysc_fields = &omap_hwmod_sysc_type2,
998};
999
1000static struct omap_hwmod_class omap54xx_mmc_hwmod_class = {
1001 .name = "mmc",
1002 .sysc = &omap54xx_mmc_sysc,
1003};
1004
1005/* mmc1 */
1006static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1007 { .role = "32khz_clk", .clk = "mmc1_32khz_clk" },
1008};
1009
1010/* mmc1 dev_attr */
1011static struct omap_mmc_dev_attr mmc1_dev_attr = {
1012 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1013};
1014
1015static struct omap_hwmod omap54xx_mmc1_hwmod = {
1016 .name = "mmc1",
1017 .class = &omap54xx_mmc_hwmod_class,
1018 .clkdm_name = "l3init_clkdm",
1019 .main_clk = "mmc1_fclk",
1020 .prcm = {
1021 .omap4 = {
1022 .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1023 .context_offs = OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1024 .modulemode = MODULEMODE_SWCTRL,
1025 },
1026 },
1027 .opt_clks = mmc1_opt_clks,
1028 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1029 .dev_attr = &mmc1_dev_attr,
1030};
1031
1032/* mmc2 */
1033static struct omap_hwmod omap54xx_mmc2_hwmod = {
1034 .name = "mmc2",
1035 .class = &omap54xx_mmc_hwmod_class,
1036 .clkdm_name = "l3init_clkdm",
1037 .main_clk = "mmc2_fclk",
1038 .prcm = {
1039 .omap4 = {
1040 .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1041 .context_offs = OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1042 .modulemode = MODULEMODE_SWCTRL,
1043 },
1044 },
1045};
1046
1047/* mmc3 */
1048static struct omap_hwmod omap54xx_mmc3_hwmod = {
1049 .name = "mmc3",
1050 .class = &omap54xx_mmc_hwmod_class,
1051 .clkdm_name = "l4per_clkdm",
1052 .main_clk = "func_48m_fclk",
1053 .prcm = {
1054 .omap4 = {
1055 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1056 .context_offs = OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1057 .modulemode = MODULEMODE_SWCTRL,
1058 },
1059 },
1060};
1061
1062/* mmc4 */
1063static struct omap_hwmod omap54xx_mmc4_hwmod = {
1064 .name = "mmc4",
1065 .class = &omap54xx_mmc_hwmod_class,
1066 .clkdm_name = "l4per_clkdm",
1067 .main_clk = "func_48m_fclk",
1068 .prcm = {
1069 .omap4 = {
1070 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1071 .context_offs = OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1072 .modulemode = MODULEMODE_SWCTRL,
1073 },
1074 },
1075};
1076
1077/* mmc5 */
1078static struct omap_hwmod omap54xx_mmc5_hwmod = {
1079 .name = "mmc5",
1080 .class = &omap54xx_mmc_hwmod_class,
1081 .clkdm_name = "l4per_clkdm",
1082 .main_clk = "func_96m_fclk",
1083 .prcm = {
1084 .omap4 = {
1085 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET,
1086 .context_offs = OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET,
1087 .modulemode = MODULEMODE_SWCTRL,
1088 },
1089 },
1090};
1091
1092/*
1093 * 'mpu' class
1094 * mpu sub-system
1095 */
1096
1097static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
1098 .name = "mpu",
1099};
1100
1101/* mpu */
1102static struct omap_hwmod omap54xx_mpu_hwmod = {
1103 .name = "mpu",
1104 .class = &omap54xx_mpu_hwmod_class,
1105 .clkdm_name = "mpu_clkdm",
1106 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1107 .main_clk = "dpll_mpu_m2_ck",
1108 .prcm = {
1109 .omap4 = {
1110 .clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1111 .context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
1112 },
1113 },
1114};
1115
1116/*
1117 * 'timer' class
1118 * general purpose timer module with accurate 1ms tick
1119 * This class contains several variants: ['timer_1ms', 'timer']
1120 */
1121
1122static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = {
1123 .rev_offs = 0x0000,
1124 .sysc_offs = 0x0010,
1125 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1126 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1127 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1128 SIDLE_SMART_WKUP),
1129 .sysc_fields = &omap_hwmod_sysc_type2,
1130 .clockact = CLOCKACT_TEST_ICLK,
1131};
1132
1133static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = {
1134 .name = "timer",
1135 .sysc = &omap54xx_timer_1ms_sysc,
1136};
1137
1138static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc = {
1139 .rev_offs = 0x0000,
1140 .sysc_offs = 0x0010,
1141 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1142 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1143 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1144 SIDLE_SMART_WKUP),
1145 .sysc_fields = &omap_hwmod_sysc_type2,
1146};
1147
1148static struct omap_hwmod_class omap54xx_timer_hwmod_class = {
1149 .name = "timer",
1150 .sysc = &omap54xx_timer_sysc,
1151};
1152
1153/* timer1 */
1154static struct omap_hwmod omap54xx_timer1_hwmod = {
1155 .name = "timer1",
1156 .class = &omap54xx_timer_1ms_hwmod_class,
1157 .clkdm_name = "wkupaon_clkdm",
1158 .main_clk = "timer1_gfclk_mux",
1159 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1160 .prcm = {
1161 .omap4 = {
1162 .clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1163 .context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1164 .modulemode = MODULEMODE_SWCTRL,
1165 },
1166 },
1167};
1168
1169/* timer2 */
1170static struct omap_hwmod omap54xx_timer2_hwmod = {
1171 .name = "timer2",
1172 .class = &omap54xx_timer_1ms_hwmod_class,
1173 .clkdm_name = "l4per_clkdm",
1174 .main_clk = "timer2_gfclk_mux",
1175 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1176 .prcm = {
1177 .omap4 = {
1178 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1179 .context_offs = OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1180 .modulemode = MODULEMODE_SWCTRL,
1181 },
1182 },
1183};
1184
1185/* timer3 */
1186static struct omap_hwmod omap54xx_timer3_hwmod = {
1187 .name = "timer3",
1188 .class = &omap54xx_timer_hwmod_class,
1189 .clkdm_name = "l4per_clkdm",
1190 .main_clk = "timer3_gfclk_mux",
1191 .prcm = {
1192 .omap4 = {
1193 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1194 .context_offs = OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1195 .modulemode = MODULEMODE_SWCTRL,
1196 },
1197 },
1198};
1199
1200/* timer4 */
1201static struct omap_hwmod omap54xx_timer4_hwmod = {
1202 .name = "timer4",
1203 .class = &omap54xx_timer_hwmod_class,
1204 .clkdm_name = "l4per_clkdm",
1205 .main_clk = "timer4_gfclk_mux",
1206 .prcm = {
1207 .omap4 = {
1208 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1209 .context_offs = OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1210 .modulemode = MODULEMODE_SWCTRL,
1211 },
1212 },
1213};
1214
1215/* timer5 */
1216static struct omap_hwmod omap54xx_timer5_hwmod = {
1217 .name = "timer5",
1218 .class = &omap54xx_timer_hwmod_class,
1219 .clkdm_name = "abe_clkdm",
1220 .main_clk = "timer5_gfclk_mux",
1221 .prcm = {
1222 .omap4 = {
1223 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET,
1224 .context_offs = OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET,
1225 .modulemode = MODULEMODE_SWCTRL,
1226 },
1227 },
1228};
1229
1230/* timer6 */
1231static struct omap_hwmod omap54xx_timer6_hwmod = {
1232 .name = "timer6",
1233 .class = &omap54xx_timer_hwmod_class,
1234 .clkdm_name = "abe_clkdm",
1235 .main_clk = "timer6_gfclk_mux",
1236 .prcm = {
1237 .omap4 = {
1238 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET,
1239 .context_offs = OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET,
1240 .modulemode = MODULEMODE_SWCTRL,
1241 },
1242 },
1243};
1244
1245/* timer7 */
1246static struct omap_hwmod omap54xx_timer7_hwmod = {
1247 .name = "timer7",
1248 .class = &omap54xx_timer_hwmod_class,
1249 .clkdm_name = "abe_clkdm",
1250 .main_clk = "timer7_gfclk_mux",
1251 .prcm = {
1252 .omap4 = {
1253 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET,
1254 .context_offs = OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET,
1255 .modulemode = MODULEMODE_SWCTRL,
1256 },
1257 },
1258};
1259
1260/* timer8 */
1261static struct omap_hwmod omap54xx_timer8_hwmod = {
1262 .name = "timer8",
1263 .class = &omap54xx_timer_hwmod_class,
1264 .clkdm_name = "abe_clkdm",
1265 .main_clk = "timer8_gfclk_mux",
1266 .prcm = {
1267 .omap4 = {
1268 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET,
1269 .context_offs = OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET,
1270 .modulemode = MODULEMODE_SWCTRL,
1271 },
1272 },
1273};
1274
1275/* timer9 */
1276static struct omap_hwmod omap54xx_timer9_hwmod = {
1277 .name = "timer9",
1278 .class = &omap54xx_timer_hwmod_class,
1279 .clkdm_name = "l4per_clkdm",
1280 .main_clk = "timer9_gfclk_mux",
1281 .prcm = {
1282 .omap4 = {
1283 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1284 .context_offs = OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1285 .modulemode = MODULEMODE_SWCTRL,
1286 },
1287 },
1288};
1289
1290/* timer10 */
1291static struct omap_hwmod omap54xx_timer10_hwmod = {
1292 .name = "timer10",
1293 .class = &omap54xx_timer_1ms_hwmod_class,
1294 .clkdm_name = "l4per_clkdm",
1295 .main_clk = "timer10_gfclk_mux",
1296 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1297 .prcm = {
1298 .omap4 = {
1299 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1300 .context_offs = OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1301 .modulemode = MODULEMODE_SWCTRL,
1302 },
1303 },
1304};
1305
1306/* timer11 */
1307static struct omap_hwmod omap54xx_timer11_hwmod = {
1308 .name = "timer11",
1309 .class = &omap54xx_timer_hwmod_class,
1310 .clkdm_name = "l4per_clkdm",
1311 .main_clk = "timer11_gfclk_mux",
1312 .prcm = {
1313 .omap4 = {
1314 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1315 .context_offs = OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1316 .modulemode = MODULEMODE_SWCTRL,
1317 },
1318 },
1319};
1320
1321/*
1322 * 'uart' class
1323 * universal asynchronous receiver/transmitter (uart)
1324 */
1325
1326static struct omap_hwmod_class_sysconfig omap54xx_uart_sysc = {
1327 .rev_offs = 0x0050,
1328 .sysc_offs = 0x0054,
1329 .syss_offs = 0x0058,
1330 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1331 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1332 SYSS_HAS_RESET_STATUS),
1333 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1334 SIDLE_SMART_WKUP),
1335 .sysc_fields = &omap_hwmod_sysc_type1,
1336};
1337
1338static struct omap_hwmod_class omap54xx_uart_hwmod_class = {
1339 .name = "uart",
1340 .sysc = &omap54xx_uart_sysc,
1341};
1342
1343/* uart1 */
1344static struct omap_hwmod omap54xx_uart1_hwmod = {
1345 .name = "uart1",
1346 .class = &omap54xx_uart_hwmod_class,
1347 .clkdm_name = "l4per_clkdm",
1348 .main_clk = "func_48m_fclk",
1349 .prcm = {
1350 .omap4 = {
1351 .clkctrl_offs = OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
1352 .context_offs = OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET,
1353 .modulemode = MODULEMODE_SWCTRL,
1354 },
1355 },
1356};
1357
1358/* uart2 */
1359static struct omap_hwmod omap54xx_uart2_hwmod = {
1360 .name = "uart2",
1361 .class = &omap54xx_uart_hwmod_class,
1362 .clkdm_name = "l4per_clkdm",
1363 .main_clk = "func_48m_fclk",
1364 .prcm = {
1365 .omap4 = {
1366 .clkctrl_offs = OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
1367 .context_offs = OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET,
1368 .modulemode = MODULEMODE_SWCTRL,
1369 },
1370 },
1371};
1372
1373/* uart3 */
1374static struct omap_hwmod omap54xx_uart3_hwmod = {
1375 .name = "uart3",
1376 .class = &omap54xx_uart_hwmod_class,
1377 .clkdm_name = "l4per_clkdm",
1378 .flags = DEBUG_OMAP4UART3_FLAGS,
1379 .main_clk = "func_48m_fclk",
1380 .prcm = {
1381 .omap4 = {
1382 .clkctrl_offs = OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
1383 .context_offs = OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET,
1384 .modulemode = MODULEMODE_SWCTRL,
1385 },
1386 },
1387};
1388
1389/* uart4 */
1390static struct omap_hwmod omap54xx_uart4_hwmod = {
1391 .name = "uart4",
1392 .class = &omap54xx_uart_hwmod_class,
1393 .clkdm_name = "l4per_clkdm",
1394 .flags = DEBUG_OMAP4UART4_FLAGS,
1395 .main_clk = "func_48m_fclk",
1396 .prcm = {
1397 .omap4 = {
1398 .clkctrl_offs = OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
1399 .context_offs = OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET,
1400 .modulemode = MODULEMODE_SWCTRL,
1401 },
1402 },
1403};
1404
1405/* uart5 */
1406static struct omap_hwmod omap54xx_uart5_hwmod = {
1407 .name = "uart5",
1408 .class = &omap54xx_uart_hwmod_class,
1409 .clkdm_name = "l4per_clkdm",
1410 .main_clk = "func_48m_fclk",
1411 .prcm = {
1412 .omap4 = {
1413 .clkctrl_offs = OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
1414 .context_offs = OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET,
1415 .modulemode = MODULEMODE_SWCTRL,
1416 },
1417 },
1418};
1419
1420/* uart6 */
1421static struct omap_hwmod omap54xx_uart6_hwmod = {
1422 .name = "uart6",
1423 .class = &omap54xx_uart_hwmod_class,
1424 .clkdm_name = "l4per_clkdm",
1425 .main_clk = "func_48m_fclk",
1426 .prcm = {
1427 .omap4 = {
1428 .clkctrl_offs = OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET,
1429 .context_offs = OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET,
1430 .modulemode = MODULEMODE_SWCTRL,
1431 },
1432 },
1433};
1434
1435/*
1436 * 'usb_otg_ss' class
1437 * 2.0 super speed (usb_otg_ss) controller
1438 */
1439
1440static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = {
1441 .rev_offs = 0x0000,
1442 .sysc_offs = 0x0010,
1443 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
1444 SYSC_HAS_SIDLEMODE),
1445 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1446 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1447 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1448 .sysc_fields = &omap_hwmod_sysc_type2,
1449};
1450
1451static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = {
1452 .name = "usb_otg_ss",
1453 .sysc = &omap54xx_usb_otg_ss_sysc,
1454};
1455
1456/* usb_otg_ss */
1457static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = {
1458 { .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" },
1459};
1460
1461static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = {
1462 .name = "usb_otg_ss",
1463 .class = &omap54xx_usb_otg_ss_hwmod_class,
1464 .clkdm_name = "l3init_clkdm",
1465 .flags = HWMOD_SWSUP_SIDLE,
1466 .main_clk = "dpll_core_h13x2_ck",
1467 .prcm = {
1468 .omap4 = {
1469 .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET,
1470 .context_offs = OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET,
1471 .modulemode = MODULEMODE_HWCTRL,
1472 },
1473 },
1474 .opt_clks = usb_otg_ss_opt_clks,
1475 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss_opt_clks),
1476};
1477
1478/*
1479 * 'wd_timer' class
1480 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1481 * overflow condition
1482 */
1483
1484static struct omap_hwmod_class_sysconfig omap54xx_wd_timer_sysc = {
1485 .rev_offs = 0x0000,
1486 .sysc_offs = 0x0010,
1487 .syss_offs = 0x0014,
1488 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1489 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1490 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1491 SIDLE_SMART_WKUP),
1492 .sysc_fields = &omap_hwmod_sysc_type1,
1493};
1494
1495static struct omap_hwmod_class omap54xx_wd_timer_hwmod_class = {
1496 .name = "wd_timer",
1497 .sysc = &omap54xx_wd_timer_sysc,
1498 .pre_shutdown = &omap2_wd_timer_disable,
1499};
1500
1501/* wd_timer2 */
1502static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
1503 .name = "wd_timer2",
1504 .class = &omap54xx_wd_timer_hwmod_class,
1505 .clkdm_name = "wkupaon_clkdm",
1506 .main_clk = "sys_32k_ck",
1507 .prcm = {
1508 .omap4 = {
1509 .clkctrl_offs = OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
1510 .context_offs = OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
1511 .modulemode = MODULEMODE_SWCTRL,
1512 },
1513 },
1514};
1515
1516
1517/*
1518 * Interfaces
1519 */
1520
1521/* l3_main_1 -> dmm */
1522static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = {
1523 .master = &omap54xx_l3_main_1_hwmod,
1524 .slave = &omap54xx_dmm_hwmod,
1525 .clk = "l3_iclk_div",
1526 .user = OCP_USER_SDMA,
1527};
1528
1529/* l3_main_3 -> l3_instr */
1530static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
1531 .master = &omap54xx_l3_main_3_hwmod,
1532 .slave = &omap54xx_l3_instr_hwmod,
1533 .clk = "l3_iclk_div",
1534 .user = OCP_USER_MPU | OCP_USER_SDMA,
1535};
1536
1537/* l3_main_2 -> l3_main_1 */
1538static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
1539 .master = &omap54xx_l3_main_2_hwmod,
1540 .slave = &omap54xx_l3_main_1_hwmod,
1541 .clk = "l3_iclk_div",
1542 .user = OCP_USER_MPU | OCP_USER_SDMA,
1543};
1544
1545/* l4_cfg -> l3_main_1 */
1546static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
1547 .master = &omap54xx_l4_cfg_hwmod,
1548 .slave = &omap54xx_l3_main_1_hwmod,
1549 .clk = "l3_iclk_div",
1550 .user = OCP_USER_MPU | OCP_USER_SDMA,
1551};
1552
1553/* mpu -> l3_main_1 */
1554static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
1555 .master = &omap54xx_mpu_hwmod,
1556 .slave = &omap54xx_l3_main_1_hwmod,
1557 .clk = "l3_iclk_div",
1558 .user = OCP_USER_MPU,
1559};
1560
1561/* l3_main_1 -> l3_main_2 */
1562static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
1563 .master = &omap54xx_l3_main_1_hwmod,
1564 .slave = &omap54xx_l3_main_2_hwmod,
1565 .clk = "l3_iclk_div",
1566 .user = OCP_USER_MPU,
1567};
1568
1569/* l4_cfg -> l3_main_2 */
1570static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
1571 .master = &omap54xx_l4_cfg_hwmod,
1572 .slave = &omap54xx_l3_main_2_hwmod,
1573 .clk = "l3_iclk_div",
1574 .user = OCP_USER_MPU | OCP_USER_SDMA,
1575};
1576
1577/* l3_main_1 -> l3_main_3 */
1578static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
1579 .master = &omap54xx_l3_main_1_hwmod,
1580 .slave = &omap54xx_l3_main_3_hwmod,
1581 .clk = "l3_iclk_div",
1582 .user = OCP_USER_MPU,
1583};
1584
1585/* l3_main_2 -> l3_main_3 */
1586static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
1587 .master = &omap54xx_l3_main_2_hwmod,
1588 .slave = &omap54xx_l3_main_3_hwmod,
1589 .clk = "l3_iclk_div",
1590 .user = OCP_USER_MPU | OCP_USER_SDMA,
1591};
1592
1593/* l4_cfg -> l3_main_3 */
1594static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
1595 .master = &omap54xx_l4_cfg_hwmod,
1596 .slave = &omap54xx_l3_main_3_hwmod,
1597 .clk = "l3_iclk_div",
1598 .user = OCP_USER_MPU | OCP_USER_SDMA,
1599};
1600
1601/* l3_main_1 -> l4_abe */
1602static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = {
1603 .master = &omap54xx_l3_main_1_hwmod,
1604 .slave = &omap54xx_l4_abe_hwmod,
1605 .clk = "abe_iclk",
1606 .user = OCP_USER_MPU | OCP_USER_SDMA,
1607};
1608
1609/* mpu -> l4_abe */
1610static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = {
1611 .master = &omap54xx_mpu_hwmod,
1612 .slave = &omap54xx_l4_abe_hwmod,
1613 .clk = "abe_iclk",
1614 .user = OCP_USER_MPU | OCP_USER_SDMA,
1615};
1616
1617/* l3_main_1 -> l4_cfg */
1618static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
1619 .master = &omap54xx_l3_main_1_hwmod,
1620 .slave = &omap54xx_l4_cfg_hwmod,
1621 .clk = "l4_root_clk_div",
1622 .user = OCP_USER_MPU | OCP_USER_SDMA,
1623};
1624
1625/* l3_main_2 -> l4_per */
1626static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
1627 .master = &omap54xx_l3_main_2_hwmod,
1628 .slave = &omap54xx_l4_per_hwmod,
1629 .clk = "l4_root_clk_div",
1630 .user = OCP_USER_MPU | OCP_USER_SDMA,
1631};
1632
1633/* l3_main_1 -> l4_wkup */
1634static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
1635 .master = &omap54xx_l3_main_1_hwmod,
1636 .slave = &omap54xx_l4_wkup_hwmod,
1637 .clk = "wkupaon_iclk_mux",
1638 .user = OCP_USER_MPU | OCP_USER_SDMA,
1639};
1640
1641/* mpu -> mpu_private */
1642static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
1643 .master = &omap54xx_mpu_hwmod,
1644 .slave = &omap54xx_mpu_private_hwmod,
1645 .clk = "l3_iclk_div",
1646 .user = OCP_USER_MPU | OCP_USER_SDMA,
1647};
1648
1649/* l4_wkup -> counter_32k */
1650static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = {
1651 .master = &omap54xx_l4_wkup_hwmod,
1652 .slave = &omap54xx_counter_32k_hwmod,
1653 .clk = "wkupaon_iclk_mux",
1654 .user = OCP_USER_MPU | OCP_USER_SDMA,
1655};
1656
1657static struct omap_hwmod_addr_space omap54xx_dma_system_addrs[] = {
1658 {
1659 .pa_start = 0x4a056000,
1660 .pa_end = 0x4a056fff,
1661 .flags = ADDR_TYPE_RT
1662 },
1663 { }
1664};
1665
1666/* l4_cfg -> dma_system */
1667static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system = {
1668 .master = &omap54xx_l4_cfg_hwmod,
1669 .slave = &omap54xx_dma_system_hwmod,
1670 .clk = "l4_root_clk_div",
1671 .addr = omap54xx_dma_system_addrs,
1672 .user = OCP_USER_MPU | OCP_USER_SDMA,
1673};
1674
1675/* l4_abe -> dmic */
1676static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic = {
1677 .master = &omap54xx_l4_abe_hwmod,
1678 .slave = &omap54xx_dmic_hwmod,
1679 .clk = "abe_iclk",
1680 .user = OCP_USER_MPU,
1681};
1682
1683/* mpu -> emif1 */
1684static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
1685 .master = &omap54xx_mpu_hwmod,
1686 .slave = &omap54xx_emif1_hwmod,
1687 .clk = "dpll_core_h11x2_ck",
1688 .user = OCP_USER_MPU | OCP_USER_SDMA,
1689};
1690
1691/* mpu -> emif2 */
1692static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
1693 .master = &omap54xx_mpu_hwmod,
1694 .slave = &omap54xx_emif2_hwmod,
1695 .clk = "dpll_core_h11x2_ck",
1696 .user = OCP_USER_MPU | OCP_USER_SDMA,
1697};
1698
1699/* l4_wkup -> gpio1 */
1700static struct omap_hwmod_ocp_if omap54xx_l4_wkup__gpio1 = {
1701 .master = &omap54xx_l4_wkup_hwmod,
1702 .slave = &omap54xx_gpio1_hwmod,
1703 .clk = "wkupaon_iclk_mux",
1704 .user = OCP_USER_MPU | OCP_USER_SDMA,
1705};
1706
1707/* l4_per -> gpio2 */
1708static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio2 = {
1709 .master = &omap54xx_l4_per_hwmod,
1710 .slave = &omap54xx_gpio2_hwmod,
1711 .clk = "l4_root_clk_div",
1712 .user = OCP_USER_MPU | OCP_USER_SDMA,
1713};
1714
1715/* l4_per -> gpio3 */
1716static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio3 = {
1717 .master = &omap54xx_l4_per_hwmod,
1718 .slave = &omap54xx_gpio3_hwmod,
1719 .clk = "l4_root_clk_div",
1720 .user = OCP_USER_MPU | OCP_USER_SDMA,
1721};
1722
1723/* l4_per -> gpio4 */
1724static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio4 = {
1725 .master = &omap54xx_l4_per_hwmod,
1726 .slave = &omap54xx_gpio4_hwmod,
1727 .clk = "l4_root_clk_div",
1728 .user = OCP_USER_MPU | OCP_USER_SDMA,
1729};
1730
1731/* l4_per -> gpio5 */
1732static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio5 = {
1733 .master = &omap54xx_l4_per_hwmod,
1734 .slave = &omap54xx_gpio5_hwmod,
1735 .clk = "l4_root_clk_div",
1736 .user = OCP_USER_MPU | OCP_USER_SDMA,
1737};
1738
1739/* l4_per -> gpio6 */
1740static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio6 = {
1741 .master = &omap54xx_l4_per_hwmod,
1742 .slave = &omap54xx_gpio6_hwmod,
1743 .clk = "l4_root_clk_div",
1744 .user = OCP_USER_MPU | OCP_USER_SDMA,
1745};
1746
1747/* l4_per -> gpio7 */
1748static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio7 = {
1749 .master = &omap54xx_l4_per_hwmod,
1750 .slave = &omap54xx_gpio7_hwmod,
1751 .clk = "l4_root_clk_div",
1752 .user = OCP_USER_MPU | OCP_USER_SDMA,
1753};
1754
1755/* l4_per -> gpio8 */
1756static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio8 = {
1757 .master = &omap54xx_l4_per_hwmod,
1758 .slave = &omap54xx_gpio8_hwmod,
1759 .clk = "l4_root_clk_div",
1760 .user = OCP_USER_MPU | OCP_USER_SDMA,
1761};
1762
1763/* l4_per -> i2c1 */
1764static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c1 = {
1765 .master = &omap54xx_l4_per_hwmod,
1766 .slave = &omap54xx_i2c1_hwmod,
1767 .clk = "l4_root_clk_div",
1768 .user = OCP_USER_MPU | OCP_USER_SDMA,
1769};
1770
1771/* l4_per -> i2c2 */
1772static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c2 = {
1773 .master = &omap54xx_l4_per_hwmod,
1774 .slave = &omap54xx_i2c2_hwmod,
1775 .clk = "l4_root_clk_div",
1776 .user = OCP_USER_MPU | OCP_USER_SDMA,
1777};
1778
1779/* l4_per -> i2c3 */
1780static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c3 = {
1781 .master = &omap54xx_l4_per_hwmod,
1782 .slave = &omap54xx_i2c3_hwmod,
1783 .clk = "l4_root_clk_div",
1784 .user = OCP_USER_MPU | OCP_USER_SDMA,
1785};
1786
1787/* l4_per -> i2c4 */
1788static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c4 = {
1789 .master = &omap54xx_l4_per_hwmod,
1790 .slave = &omap54xx_i2c4_hwmod,
1791 .clk = "l4_root_clk_div",
1792 .user = OCP_USER_MPU | OCP_USER_SDMA,
1793};
1794
1795/* l4_per -> i2c5 */
1796static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c5 = {
1797 .master = &omap54xx_l4_per_hwmod,
1798 .slave = &omap54xx_i2c5_hwmod,
1799 .clk = "l4_root_clk_div",
1800 .user = OCP_USER_MPU | OCP_USER_SDMA,
1801};
1802
1803/* l4_wkup -> kbd */
1804static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = {
1805 .master = &omap54xx_l4_wkup_hwmod,
1806 .slave = &omap54xx_kbd_hwmod,
1807 .clk = "wkupaon_iclk_mux",
1808 .user = OCP_USER_MPU | OCP_USER_SDMA,
1809};
1810
1811/* l4_abe -> mcbsp1 */
1812static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = {
1813 .master = &omap54xx_l4_abe_hwmod,
1814 .slave = &omap54xx_mcbsp1_hwmod,
1815 .clk = "abe_iclk",
1816 .user = OCP_USER_MPU,
1817};
1818
1819/* l4_abe -> mcbsp2 */
1820static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp2 = {
1821 .master = &omap54xx_l4_abe_hwmod,
1822 .slave = &omap54xx_mcbsp2_hwmod,
1823 .clk = "abe_iclk",
1824 .user = OCP_USER_MPU,
1825};
1826
1827/* l4_abe -> mcbsp3 */
1828static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp3 = {
1829 .master = &omap54xx_l4_abe_hwmod,
1830 .slave = &omap54xx_mcbsp3_hwmod,
1831 .clk = "abe_iclk",
1832 .user = OCP_USER_MPU,
1833};
1834
1835/* l4_abe -> mcpdm */
1836static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm = {
1837 .master = &omap54xx_l4_abe_hwmod,
1838 .slave = &omap54xx_mcpdm_hwmod,
1839 .clk = "abe_iclk",
1840 .user = OCP_USER_MPU,
1841};
1842
1843/* l4_per -> mcspi1 */
1844static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi1 = {
1845 .master = &omap54xx_l4_per_hwmod,
1846 .slave = &omap54xx_mcspi1_hwmod,
1847 .clk = "l4_root_clk_div",
1848 .user = OCP_USER_MPU | OCP_USER_SDMA,
1849};
1850
1851/* l4_per -> mcspi2 */
1852static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi2 = {
1853 .master = &omap54xx_l4_per_hwmod,
1854 .slave = &omap54xx_mcspi2_hwmod,
1855 .clk = "l4_root_clk_div",
1856 .user = OCP_USER_MPU | OCP_USER_SDMA,
1857};
1858
1859/* l4_per -> mcspi3 */
1860static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi3 = {
1861 .master = &omap54xx_l4_per_hwmod,
1862 .slave = &omap54xx_mcspi3_hwmod,
1863 .clk = "l4_root_clk_div",
1864 .user = OCP_USER_MPU | OCP_USER_SDMA,
1865};
1866
1867/* l4_per -> mcspi4 */
1868static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi4 = {
1869 .master = &omap54xx_l4_per_hwmod,
1870 .slave = &omap54xx_mcspi4_hwmod,
1871 .clk = "l4_root_clk_div",
1872 .user = OCP_USER_MPU | OCP_USER_SDMA,
1873};
1874
1875/* l4_per -> mmc1 */
1876static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc1 = {
1877 .master = &omap54xx_l4_per_hwmod,
1878 .slave = &omap54xx_mmc1_hwmod,
1879 .clk = "l3_iclk_div",
1880 .user = OCP_USER_MPU | OCP_USER_SDMA,
1881};
1882
1883/* l4_per -> mmc2 */
1884static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc2 = {
1885 .master = &omap54xx_l4_per_hwmod,
1886 .slave = &omap54xx_mmc2_hwmod,
1887 .clk = "l3_iclk_div",
1888 .user = OCP_USER_MPU | OCP_USER_SDMA,
1889};
1890
1891/* l4_per -> mmc3 */
1892static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc3 = {
1893 .master = &omap54xx_l4_per_hwmod,
1894 .slave = &omap54xx_mmc3_hwmod,
1895 .clk = "l4_root_clk_div",
1896 .user = OCP_USER_MPU | OCP_USER_SDMA,
1897};
1898
1899/* l4_per -> mmc4 */
1900static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc4 = {
1901 .master = &omap54xx_l4_per_hwmod,
1902 .slave = &omap54xx_mmc4_hwmod,
1903 .clk = "l4_root_clk_div",
1904 .user = OCP_USER_MPU | OCP_USER_SDMA,
1905};
1906
1907/* l4_per -> mmc5 */
1908static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc5 = {
1909 .master = &omap54xx_l4_per_hwmod,
1910 .slave = &omap54xx_mmc5_hwmod,
1911 .clk = "l4_root_clk_div",
1912 .user = OCP_USER_MPU | OCP_USER_SDMA,
1913};
1914
1915/* l4_cfg -> mpu */
1916static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
1917 .master = &omap54xx_l4_cfg_hwmod,
1918 .slave = &omap54xx_mpu_hwmod,
1919 .clk = "l4_root_clk_div",
1920 .user = OCP_USER_MPU | OCP_USER_SDMA,
1921};
1922
1923/* l4_wkup -> timer1 */
1924static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
1925 .master = &omap54xx_l4_wkup_hwmod,
1926 .slave = &omap54xx_timer1_hwmod,
1927 .clk = "wkupaon_iclk_mux",
1928 .user = OCP_USER_MPU | OCP_USER_SDMA,
1929};
1930
1931/* l4_per -> timer2 */
1932static struct omap_hwmod_ocp_if omap54xx_l4_per__timer2 = {
1933 .master = &omap54xx_l4_per_hwmod,
1934 .slave = &omap54xx_timer2_hwmod,
1935 .clk = "l4_root_clk_div",
1936 .user = OCP_USER_MPU | OCP_USER_SDMA,
1937};
1938
1939/* l4_per -> timer3 */
1940static struct omap_hwmod_ocp_if omap54xx_l4_per__timer3 = {
1941 .master = &omap54xx_l4_per_hwmod,
1942 .slave = &omap54xx_timer3_hwmod,
1943 .clk = "l4_root_clk_div",
1944 .user = OCP_USER_MPU | OCP_USER_SDMA,
1945};
1946
1947/* l4_per -> timer4 */
1948static struct omap_hwmod_ocp_if omap54xx_l4_per__timer4 = {
1949 .master = &omap54xx_l4_per_hwmod,
1950 .slave = &omap54xx_timer4_hwmod,
1951 .clk = "l4_root_clk_div",
1952 .user = OCP_USER_MPU | OCP_USER_SDMA,
1953};
1954
1955/* l4_abe -> timer5 */
1956static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5 = {
1957 .master = &omap54xx_l4_abe_hwmod,
1958 .slave = &omap54xx_timer5_hwmod,
1959 .clk = "abe_iclk",
1960 .user = OCP_USER_MPU,
1961};
1962
1963/* l4_abe -> timer6 */
1964static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6 = {
1965 .master = &omap54xx_l4_abe_hwmod,
1966 .slave = &omap54xx_timer6_hwmod,
1967 .clk = "abe_iclk",
1968 .user = OCP_USER_MPU,
1969};
1970
1971/* l4_abe -> timer7 */
1972static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7 = {
1973 .master = &omap54xx_l4_abe_hwmod,
1974 .slave = &omap54xx_timer7_hwmod,
1975 .clk = "abe_iclk",
1976 .user = OCP_USER_MPU,
1977};
1978
1979/* l4_abe -> timer8 */
1980static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8 = {
1981 .master = &omap54xx_l4_abe_hwmod,
1982 .slave = &omap54xx_timer8_hwmod,
1983 .clk = "abe_iclk",
1984 .user = OCP_USER_MPU,
1985};
1986
1987/* l4_per -> timer9 */
1988static struct omap_hwmod_ocp_if omap54xx_l4_per__timer9 = {
1989 .master = &omap54xx_l4_per_hwmod,
1990 .slave = &omap54xx_timer9_hwmod,
1991 .clk = "l4_root_clk_div",
1992 .user = OCP_USER_MPU | OCP_USER_SDMA,
1993};
1994
1995/* l4_per -> timer10 */
1996static struct omap_hwmod_ocp_if omap54xx_l4_per__timer10 = {
1997 .master = &omap54xx_l4_per_hwmod,
1998 .slave = &omap54xx_timer10_hwmod,
1999 .clk = "l4_root_clk_div",
2000 .user = OCP_USER_MPU | OCP_USER_SDMA,
2001};
2002
2003/* l4_per -> timer11 */
2004static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11 = {
2005 .master = &omap54xx_l4_per_hwmod,
2006 .slave = &omap54xx_timer11_hwmod,
2007 .clk = "l4_root_clk_div",
2008 .user = OCP_USER_MPU | OCP_USER_SDMA,
2009};
2010
2011/* l4_per -> uart1 */
2012static struct omap_hwmod_ocp_if omap54xx_l4_per__uart1 = {
2013 .master = &omap54xx_l4_per_hwmod,
2014 .slave = &omap54xx_uart1_hwmod,
2015 .clk = "l4_root_clk_div",
2016 .user = OCP_USER_MPU | OCP_USER_SDMA,
2017};
2018
2019/* l4_per -> uart2 */
2020static struct omap_hwmod_ocp_if omap54xx_l4_per__uart2 = {
2021 .master = &omap54xx_l4_per_hwmod,
2022 .slave = &omap54xx_uart2_hwmod,
2023 .clk = "l4_root_clk_div",
2024 .user = OCP_USER_MPU | OCP_USER_SDMA,
2025};
2026
2027/* l4_per -> uart3 */
2028static struct omap_hwmod_ocp_if omap54xx_l4_per__uart3 = {
2029 .master = &omap54xx_l4_per_hwmod,
2030 .slave = &omap54xx_uart3_hwmod,
2031 .clk = "l4_root_clk_div",
2032 .user = OCP_USER_MPU | OCP_USER_SDMA,
2033};
2034
2035/* l4_per -> uart4 */
2036static struct omap_hwmod_ocp_if omap54xx_l4_per__uart4 = {
2037 .master = &omap54xx_l4_per_hwmod,
2038 .slave = &omap54xx_uart4_hwmod,
2039 .clk = "l4_root_clk_div",
2040 .user = OCP_USER_MPU | OCP_USER_SDMA,
2041};
2042
2043/* l4_per -> uart5 */
2044static struct omap_hwmod_ocp_if omap54xx_l4_per__uart5 = {
2045 .master = &omap54xx_l4_per_hwmod,
2046 .slave = &omap54xx_uart5_hwmod,
2047 .clk = "l4_root_clk_div",
2048 .user = OCP_USER_MPU | OCP_USER_SDMA,
2049};
2050
2051/* l4_per -> uart6 */
2052static struct omap_hwmod_ocp_if omap54xx_l4_per__uart6 = {
2053 .master = &omap54xx_l4_per_hwmod,
2054 .slave = &omap54xx_uart6_hwmod,
2055 .clk = "l4_root_clk_div",
2056 .user = OCP_USER_MPU | OCP_USER_SDMA,
2057};
2058
2059/* l4_cfg -> usb_otg_ss */
2060static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = {
2061 .master = &omap54xx_l4_cfg_hwmod,
2062 .slave = &omap54xx_usb_otg_ss_hwmod,
2063 .clk = "dpll_core_h13x2_ck",
2064 .user = OCP_USER_MPU | OCP_USER_SDMA,
2065};
2066
2067/* l4_wkup -> wd_timer2 */
2068static struct omap_hwmod_ocp_if omap54xx_l4_wkup__wd_timer2 = {
2069 .master = &omap54xx_l4_wkup_hwmod,
2070 .slave = &omap54xx_wd_timer2_hwmod,
2071 .clk = "wkupaon_iclk_mux",
2072 .user = OCP_USER_MPU | OCP_USER_SDMA,
2073};
2074
2075static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
2076 &omap54xx_l3_main_1__dmm,
2077 &omap54xx_l3_main_3__l3_instr,
2078 &omap54xx_l3_main_2__l3_main_1,
2079 &omap54xx_l4_cfg__l3_main_1,
2080 &omap54xx_mpu__l3_main_1,
2081 &omap54xx_l3_main_1__l3_main_2,
2082 &omap54xx_l4_cfg__l3_main_2,
2083 &omap54xx_l3_main_1__l3_main_3,
2084 &omap54xx_l3_main_2__l3_main_3,
2085 &omap54xx_l4_cfg__l3_main_3,
2086 &omap54xx_l3_main_1__l4_abe,
2087 &omap54xx_mpu__l4_abe,
2088 &omap54xx_l3_main_1__l4_cfg,
2089 &omap54xx_l3_main_2__l4_per,
2090 &omap54xx_l3_main_1__l4_wkup,
2091 &omap54xx_mpu__mpu_private,
2092 &omap54xx_l4_wkup__counter_32k,
2093 &omap54xx_l4_cfg__dma_system,
2094 &omap54xx_l4_abe__dmic,
2095 &omap54xx_mpu__emif1,
2096 &omap54xx_mpu__emif2,
2097 &omap54xx_l4_wkup__gpio1,
2098 &omap54xx_l4_per__gpio2,
2099 &omap54xx_l4_per__gpio3,
2100 &omap54xx_l4_per__gpio4,
2101 &omap54xx_l4_per__gpio5,
2102 &omap54xx_l4_per__gpio6,
2103 &omap54xx_l4_per__gpio7,
2104 &omap54xx_l4_per__gpio8,
2105 &omap54xx_l4_per__i2c1,
2106 &omap54xx_l4_per__i2c2,
2107 &omap54xx_l4_per__i2c3,
2108 &omap54xx_l4_per__i2c4,
2109 &omap54xx_l4_per__i2c5,
2110 &omap54xx_l4_wkup__kbd,
2111 &omap54xx_l4_abe__mcbsp1,
2112 &omap54xx_l4_abe__mcbsp2,
2113 &omap54xx_l4_abe__mcbsp3,
2114 &omap54xx_l4_abe__mcpdm,
2115 &omap54xx_l4_per__mcspi1,
2116 &omap54xx_l4_per__mcspi2,
2117 &omap54xx_l4_per__mcspi3,
2118 &omap54xx_l4_per__mcspi4,
2119 &omap54xx_l4_per__mmc1,
2120 &omap54xx_l4_per__mmc2,
2121 &omap54xx_l4_per__mmc3,
2122 &omap54xx_l4_per__mmc4,
2123 &omap54xx_l4_per__mmc5,
2124 &omap54xx_l4_cfg__mpu,
2125 &omap54xx_l4_wkup__timer1,
2126 &omap54xx_l4_per__timer2,
2127 &omap54xx_l4_per__timer3,
2128 &omap54xx_l4_per__timer4,
2129 &omap54xx_l4_abe__timer5,
2130 &omap54xx_l4_abe__timer6,
2131 &omap54xx_l4_abe__timer7,
2132 &omap54xx_l4_abe__timer8,
2133 &omap54xx_l4_per__timer9,
2134 &omap54xx_l4_per__timer10,
2135 &omap54xx_l4_per__timer11,
2136 &omap54xx_l4_per__uart1,
2137 &omap54xx_l4_per__uart2,
2138 &omap54xx_l4_per__uart3,
2139 &omap54xx_l4_per__uart4,
2140 &omap54xx_l4_per__uart5,
2141 &omap54xx_l4_per__uart6,
2142 &omap54xx_l4_cfg__usb_otg_ss,
2143 &omap54xx_l4_wkup__wd_timer2,
2144 NULL,
2145};
2146
2147int __init omap54xx_hwmod_init(void)
2148{
2149 omap_hwmod_init();
2150 return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);
2151}
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index a251f87fa2a2..82f0698933d8 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * OMAP4 Power Management Routines 2 * OMAP4+ Power Management Routines
3 * 3 *
4 * Copyright (C) 2010-2011 Texas Instruments, Inc. 4 * Copyright (C) 2010-2013 Texas Instruments, Inc.
5 * Rajendra Nayak <rnayak@ti.com> 5 * Rajendra Nayak <rnayak@ti.com>
6 * Santosh Shilimkar <santosh.shilimkar@ti.com> 6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
7 * 7 *
@@ -135,16 +135,16 @@ static void omap_default_idle(void)
135} 135}
136 136
137/** 137/**
138 * omap4_pm_init - Init routine for OMAP4 PM 138 * omap4_init_static_deps - Add OMAP4 static dependencies
139 * 139 *
140 * Initializes all powerdomain and clockdomain target states 140 * Add needed static clockdomain dependencies on OMAP4 devices.
141 * and all PRCM settings. 141 * Return: 0 on success or 'err' on failures
142 */ 142 */
143int __init omap4_pm_init(void) 143static inline int omap4_init_static_deps(void)
144{ 144{
145 int ret;
146 struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm; 145 struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm;
147 struct clockdomain *ducati_clkdm, *l3_2_clkdm; 146 struct clockdomain *ducati_clkdm, *l3_2_clkdm;
147 int ret = 0;
148 148
149 if (omap_rev() == OMAP4430_REV_ES1_0) { 149 if (omap_rev() == OMAP4430_REV_ES1_0) {
150 WARN(1, "Power Management not supported on OMAP4430 ES1.0\n"); 150 WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
@@ -163,7 +163,7 @@ int __init omap4_pm_init(void)
163 ret = pwrdm_for_each(pwrdms_setup, NULL); 163 ret = pwrdm_for_each(pwrdms_setup, NULL);
164 if (ret) { 164 if (ret) {
165 pr_err("Failed to setup powerdomains\n"); 165 pr_err("Failed to setup powerdomains\n");
166 goto err2; 166 return ret;
167 } 167 }
168 168
169 /* 169 /*
@@ -171,6 +171,10 @@ int __init omap4_pm_init(void)
171 * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as 171 * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
172 * expected. The hardware recommendation is to enable static 172 * expected. The hardware recommendation is to enable static
173 * dependencies for these to avoid system lock ups or random crashes. 173 * dependencies for these to avoid system lock ups or random crashes.
174 * The L4 wakeup depedency is added to workaround the OCP sync hardware
175 * BUG with 32K synctimer which lead to incorrect timer value read
176 * from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which
177 * are part of L4 wakeup clockdomain.
174 */ 178 */
175 mpuss_clkdm = clkdm_lookup("mpuss_clkdm"); 179 mpuss_clkdm = clkdm_lookup("mpuss_clkdm");
176 emif_clkdm = clkdm_lookup("l3_emif_clkdm"); 180 emif_clkdm = clkdm_lookup("l3_emif_clkdm");
@@ -179,7 +183,7 @@ int __init omap4_pm_init(void)
179 ducati_clkdm = clkdm_lookup("ducati_clkdm"); 183 ducati_clkdm = clkdm_lookup("ducati_clkdm");
180 if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) || 184 if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) ||
181 (!l3_2_clkdm) || (!ducati_clkdm)) 185 (!l3_2_clkdm) || (!ducati_clkdm))
182 goto err2; 186 return -EINVAL;
183 187
184 ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm); 188 ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
185 ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm); 189 ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm);
@@ -188,9 +192,42 @@ int __init omap4_pm_init(void)
188 ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm); 192 ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
189 if (ret) { 193 if (ret) {
190 pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 wakeup dependency\n"); 194 pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 wakeup dependency\n");
195 return -EINVAL;
196 }
197
198 return ret;
199}
200
201/**
202 * omap4_pm_init - Init routine for OMAP4+ devices
203 *
204 * Initializes all powerdomain and clockdomain target states
205 * and all PRCM settings.
206 * Return: Returns the error code returned by called functions.
207 */
208int __init omap4_pm_init(void)
209{
210 int ret = 0;
211
212 if (omap_rev() == OMAP4430_REV_ES1_0) {
213 WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
214 return -ENODEV;
215 }
216
217 pr_info("Power Management for TI OMAP4+ devices.\n");
218
219 ret = pwrdm_for_each(pwrdms_setup, NULL);
220 if (ret) {
221 pr_err("Failed to setup powerdomains.\n");
191 goto err2; 222 goto err2;
192 } 223 }
193 224
225 if (cpu_is_omap44xx()) {
226 ret = omap4_init_static_deps();
227 if (ret)
228 goto err2;
229 }
230
194 ret = omap4_mpuss_init(); 231 ret = omap4_mpuss_init();
195 if (ret) { 232 if (ret) {
196 pr_err("Failed to initialise OMAP4 MPUSS\n"); 233 pr_err("Failed to initialise OMAP4 MPUSS\n");
@@ -206,7 +243,8 @@ int __init omap4_pm_init(void)
206 /* Overwrite the default cpu_do_idle() */ 243 /* Overwrite the default cpu_do_idle() */
207 arm_pm_idle = omap_default_idle; 244 arm_pm_idle = omap_default_idle;
208 245
209 omap4_idle_init(); 246 if (cpu_is_omap44xx())
247 omap4_idle_init();
210 248
211err2: 249err2:
212 return ret; 250 return ret;
diff --git a/arch/arm/mach-omap2/pmu.c b/arch/arm/mach-omap2/pmu.c
index 9ace8eae7ee8..33c8846b4193 100644
--- a/arch/arm/mach-omap2/pmu.c
+++ b/arch/arm/mach-omap2/pmu.c
@@ -54,10 +54,7 @@ static int __init omap2_init_pmu(unsigned oh_num, char *oh_names[])
54 WARN(IS_ERR(omap_pmu_dev), "Can't build omap_device for %s.\n", 54 WARN(IS_ERR(omap_pmu_dev), "Can't build omap_device for %s.\n",
55 dev_name); 55 dev_name);
56 56
57 if (IS_ERR(omap_pmu_dev)) 57 return PTR_RET(omap_pmu_dev);
58 return PTR_ERR(omap_pmu_dev);
59
60 return 0;
61} 58}
62 59
63static int __init omap_init_pmu(void) 60static int __init omap_init_pmu(void)
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 86babd740d41..e233dfcbc186 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -102,6 +102,10 @@ static int _pwrdm_register(struct powerdomain *pwrdm)
102 if (_pwrdm_lookup(pwrdm->name)) 102 if (_pwrdm_lookup(pwrdm->name))
103 return -EEXIST; 103 return -EEXIST;
104 104
105 if (arch_pwrdm && arch_pwrdm->pwrdm_has_voltdm)
106 if (!arch_pwrdm->pwrdm_has_voltdm())
107 goto skip_voltdm;
108
105 voltdm = voltdm_lookup(pwrdm->voltdm.name); 109 voltdm = voltdm_lookup(pwrdm->voltdm.name);
106 if (!voltdm) { 110 if (!voltdm) {
107 pr_err("powerdomain: %s: voltagedomain %s does not exist\n", 111 pr_err("powerdomain: %s: voltagedomain %s does not exist\n",
@@ -111,6 +115,7 @@ static int _pwrdm_register(struct powerdomain *pwrdm)
111 pwrdm->voltdm.ptr = voltdm; 115 pwrdm->voltdm.ptr = voltdm;
112 INIT_LIST_HEAD(&pwrdm->voltdm_node); 116 INIT_LIST_HEAD(&pwrdm->voltdm_node);
113 voltdm_add_pwrdm(voltdm, pwrdm); 117 voltdm_add_pwrdm(voltdm, pwrdm);
118skip_voltdm:
114 spin_lock_init(&pwrdm->_lock); 119 spin_lock_init(&pwrdm->_lock);
115 120
116 list_add(&pwrdm->node, &pwrdm_list); 121 list_add(&pwrdm->node, &pwrdm_list);
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index 140c36074fed..e4d7bd6f94b8 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -166,6 +166,7 @@ struct powerdomain {
166 * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd 166 * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd
167 * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep 167 * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep
168 * @pwrdm_wait_transition: Wait for a pd state transition to complete 168 * @pwrdm_wait_transition: Wait for a pd state transition to complete
169 * @pwrdm_has_voltdm: Check if a voltdm association is needed
169 * 170 *
170 * Regarding @pwrdm_set_lowpwrstchange: On the OMAP2 and 3-family 171 * Regarding @pwrdm_set_lowpwrstchange: On the OMAP2 and 3-family
171 * chips, a powerdomain's power state is not allowed to directly 172 * chips, a powerdomain's power state is not allowed to directly
@@ -196,6 +197,7 @@ struct pwrdm_ops {
196 int (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm); 197 int (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm);
197 int (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm); 198 int (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm);
198 int (*pwrdm_wait_transition)(struct powerdomain *pwrdm); 199 int (*pwrdm_wait_transition)(struct powerdomain *pwrdm);
200 int (*pwrdm_has_voltdm)(void);
199}; 201};
200 202
201int pwrdm_register_platform_funcs(struct pwrdm_ops *custom_funcs); 203int pwrdm_register_platform_funcs(struct pwrdm_ops *custom_funcs);
@@ -253,6 +255,7 @@ extern void omap243x_powerdomains_init(void);
253extern void omap3xxx_powerdomains_init(void); 255extern void omap3xxx_powerdomains_init(void);
254extern void am33xx_powerdomains_init(void); 256extern void am33xx_powerdomains_init(void);
255extern void omap44xx_powerdomains_init(void); 257extern void omap44xx_powerdomains_init(void);
258extern void omap54xx_powerdomains_init(void);
256 259
257extern struct pwrdm_ops omap2_pwrdm_operations; 260extern struct pwrdm_ops omap2_pwrdm_operations;
258extern struct pwrdm_ops omap3_pwrdm_operations; 261extern struct pwrdm_ops omap3_pwrdm_operations;
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index f0e14e9efe5a..e2d4bd804523 100644
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -336,6 +336,54 @@ static struct powerdomain dpll5_pwrdm = {
336 .voltdm = { .name = "core" }, 336 .voltdm = { .name = "core" },
337}; 337};
338 338
339static struct powerdomain device_81xx_pwrdm = {
340 .name = "device_pwrdm",
341 .prcm_offs = TI81XX_PRM_DEVICE_MOD,
342 .voltdm = { .name = "core" },
343};
344
345static struct powerdomain active_816x_pwrdm = {
346 .name = "active_pwrdm",
347 .prcm_offs = TI816X_PRM_ACTIVE_MOD,
348 .pwrsts = PWRSTS_OFF_ON,
349 .voltdm = { .name = "core" },
350};
351
352static struct powerdomain default_816x_pwrdm = {
353 .name = "default_pwrdm",
354 .prcm_offs = TI81XX_PRM_DEFAULT_MOD,
355 .pwrsts = PWRSTS_OFF_ON,
356 .voltdm = { .name = "core" },
357};
358
359static struct powerdomain ivahd0_816x_pwrdm = {
360 .name = "ivahd0_pwrdm",
361 .prcm_offs = TI816X_PRM_IVAHD0_MOD,
362 .pwrsts = PWRSTS_OFF_ON,
363 .voltdm = { .name = "mpu_iva" },
364};
365
366static struct powerdomain ivahd1_816x_pwrdm = {
367 .name = "ivahd1_pwrdm",
368 .prcm_offs = TI816X_PRM_IVAHD1_MOD,
369 .pwrsts = PWRSTS_OFF_ON,
370 .voltdm = { .name = "mpu_iva" },
371};
372
373static struct powerdomain ivahd2_816x_pwrdm = {
374 .name = "ivahd2_pwrdm",
375 .prcm_offs = TI816X_PRM_IVAHD2_MOD,
376 .pwrsts = PWRSTS_OFF_ON,
377 .voltdm = { .name = "mpu_iva" },
378};
379
380static struct powerdomain sgx_816x_pwrdm = {
381 .name = "sgx_pwrdm",
382 .prcm_offs = TI816X_PRM_SGX_MOD,
383 .pwrsts = PWRSTS_OFF_ON,
384 .voltdm = { .name = "core" },
385};
386
339/* As powerdomains are added or removed above, this list must also be changed */ 387/* As powerdomains are added or removed above, this list must also be changed */
340static struct powerdomain *powerdomains_omap3430_common[] __initdata = { 388static struct powerdomain *powerdomains_omap3430_common[] __initdata = {
341 &wkup_omap2_pwrdm, 389 &wkup_omap2_pwrdm,
@@ -393,6 +441,17 @@ static struct powerdomain *powerdomains_am35x[] __initdata = {
393 NULL 441 NULL
394}; 442};
395 443
444static struct powerdomain *powerdomains_ti81xx[] __initdata = {
445 &device_81xx_pwrdm,
446 &active_816x_pwrdm,
447 &default_816x_pwrdm,
448 &ivahd0_816x_pwrdm,
449 &ivahd1_816x_pwrdm,
450 &ivahd2_816x_pwrdm,
451 &sgx_816x_pwrdm,
452 NULL
453};
454
396void __init omap3xxx_powerdomains_init(void) 455void __init omap3xxx_powerdomains_init(void)
397{ 456{
398 unsigned int rev; 457 unsigned int rev;
@@ -406,6 +465,9 @@ void __init omap3xxx_powerdomains_init(void)
406 465
407 if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) { 466 if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
408 pwrdm_register_pwrdms(powerdomains_am35x); 467 pwrdm_register_pwrdms(powerdomains_am35x);
468 } else if (rev == TI8168_REV_ES1_0 || rev == TI8168_REV_ES1_1
469 || rev == TI8168_REV_ES2_0 || rev == TI8168_REV_ES2_1) {
470 pwrdm_register_pwrdms(powerdomains_ti81xx);
409 } else { 471 } else {
410 pwrdm_register_pwrdms(powerdomains_omap3430_common); 472 pwrdm_register_pwrdms(powerdomains_omap3430_common);
411 473
diff --git a/arch/arm/mach-omap2/powerdomains54xx_data.c b/arch/arm/mach-omap2/powerdomains54xx_data.c
new file mode 100644
index 000000000000..81f8a7cc26ee
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomains54xx_data.c
@@ -0,0 +1,331 @@
1/*
2 * OMAP54XX Power domains framework
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * Abhijit Pagare (abhijitpagare@ti.com)
7 * Benoit Cousson (b-cousson@ti.com)
8 * Paul Walmsley (paul@pwsan.com)
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#include <linux/kernel.h>
22#include <linux/init.h>
23
24#include "powerdomain.h"
25
26#include "prcm-common.h"
27#include "prcm44xx.h"
28#include "prm-regbits-54xx.h"
29#include "prm54xx.h"
30#include "prcm_mpu54xx.h"
31
32/* core_54xx_pwrdm: CORE power domain */
33static struct powerdomain core_54xx_pwrdm = {
34 .name = "core_pwrdm",
35 .voltdm = { .name = "core" },
36 .prcm_offs = OMAP54XX_PRM_CORE_INST,
37 .prcm_partition = OMAP54XX_PRM_PARTITION,
38 .pwrsts = PWRSTS_RET_ON,
39 .pwrsts_logic_ret = PWRSTS_OFF_RET,
40 .banks = 5,
41 .pwrsts_mem_ret = {
42 [0] = PWRSTS_OFF_RET, /* core_nret_bank */
43 [1] = PWRSTS_OFF_RET, /* core_ocmram */
44 [2] = PWRSTS_OFF_RET, /* core_other_bank */
45 [3] = PWRSTS_OFF_RET, /* ipu_l2ram */
46 [4] = PWRSTS_OFF_RET, /* ipu_unicache */
47 },
48 .pwrsts_mem_on = {
49 [0] = PWRSTS_OFF_RET, /* core_nret_bank */
50 [1] = PWRSTS_OFF_RET, /* core_ocmram */
51 [2] = PWRSTS_OFF_RET, /* core_other_bank */
52 [3] = PWRSTS_OFF_RET, /* ipu_l2ram */
53 [4] = PWRSTS_OFF_RET, /* ipu_unicache */
54 },
55 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
56};
57
58/* abe_54xx_pwrdm: Audio back end power domain */
59static struct powerdomain abe_54xx_pwrdm = {
60 .name = "abe_pwrdm",
61 .voltdm = { .name = "core" },
62 .prcm_offs = OMAP54XX_PRM_ABE_INST,
63 .prcm_partition = OMAP54XX_PRM_PARTITION,
64 .pwrsts = PWRSTS_OFF_RET_ON,
65 .pwrsts_logic_ret = PWRSTS_OFF,
66 .banks = 2,
67 .pwrsts_mem_ret = {
68 [0] = PWRSTS_OFF_RET, /* aessmem */
69 [1] = PWRSTS_OFF_RET, /* periphmem */
70 },
71 .pwrsts_mem_on = {
72 [0] = PWRSTS_OFF_RET, /* aessmem */
73 [1] = PWRSTS_OFF_RET, /* periphmem */
74 },
75 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
76};
77
78/* coreaon_54xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
79static struct powerdomain coreaon_54xx_pwrdm = {
80 .name = "coreaon_pwrdm",
81 .voltdm = { .name = "core" },
82 .prcm_offs = OMAP54XX_PRM_COREAON_INST,
83 .prcm_partition = OMAP54XX_PRM_PARTITION,
84 .pwrsts = PWRSTS_ON,
85};
86
87/* dss_54xx_pwrdm: Display subsystem power domain */
88static struct powerdomain dss_54xx_pwrdm = {
89 .name = "dss_pwrdm",
90 .voltdm = { .name = "core" },
91 .prcm_offs = OMAP54XX_PRM_DSS_INST,
92 .prcm_partition = OMAP54XX_PRM_PARTITION,
93 .pwrsts = PWRSTS_OFF_RET_ON,
94 .pwrsts_logic_ret = PWRSTS_OFF,
95 .banks = 1,
96 .pwrsts_mem_ret = {
97 [0] = PWRSTS_OFF_RET, /* dss_mem */
98 },
99 .pwrsts_mem_on = {
100 [0] = PWRSTS_OFF_RET, /* dss_mem */
101 },
102 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
103};
104
105/* cpu0_54xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
106static struct powerdomain cpu0_54xx_pwrdm = {
107 .name = "cpu0_pwrdm",
108 .voltdm = { .name = "mpu" },
109 .prcm_offs = OMAP54XX_PRCM_MPU_PRM_C0_INST,
110 .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION,
111 .pwrsts = PWRSTS_OFF_RET_ON,
112 .pwrsts_logic_ret = PWRSTS_OFF_RET,
113 .banks = 1,
114 .pwrsts_mem_ret = {
115 [0] = PWRSTS_OFF_RET, /* cpu0_l1 */
116 },
117 .pwrsts_mem_on = {
118 [0] = PWRSTS_ON, /* cpu0_l1 */
119 },
120};
121
122/* cpu1_54xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
123static struct powerdomain cpu1_54xx_pwrdm = {
124 .name = "cpu1_pwrdm",
125 .voltdm = { .name = "mpu" },
126 .prcm_offs = OMAP54XX_PRCM_MPU_PRM_C1_INST,
127 .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION,
128 .pwrsts = PWRSTS_OFF_RET_ON,
129 .pwrsts_logic_ret = PWRSTS_OFF_RET,
130 .banks = 1,
131 .pwrsts_mem_ret = {
132 [0] = PWRSTS_OFF_RET, /* cpu1_l1 */
133 },
134 .pwrsts_mem_on = {
135 [0] = PWRSTS_ON, /* cpu1_l1 */
136 },
137};
138
139/* emu_54xx_pwrdm: Emulation power domain */
140static struct powerdomain emu_54xx_pwrdm = {
141 .name = "emu_pwrdm",
142 .voltdm = { .name = "wkup" },
143 .prcm_offs = OMAP54XX_PRM_EMU_INST,
144 .prcm_partition = OMAP54XX_PRM_PARTITION,
145 .pwrsts = PWRSTS_OFF_ON,
146 .banks = 1,
147 .pwrsts_mem_ret = {
148 [0] = PWRSTS_OFF_RET, /* emu_bank */
149 },
150 .pwrsts_mem_on = {
151 [0] = PWRSTS_OFF_RET, /* emu_bank */
152 },
153};
154
155/* mpu_54xx_pwrdm: Modena processor and the Neon coprocessor power domain */
156static struct powerdomain mpu_54xx_pwrdm = {
157 .name = "mpu_pwrdm",
158 .voltdm = { .name = "mpu" },
159 .prcm_offs = OMAP54XX_PRM_MPU_INST,
160 .prcm_partition = OMAP54XX_PRM_PARTITION,
161 .pwrsts = PWRSTS_RET_ON,
162 .pwrsts_logic_ret = PWRSTS_OFF_RET,
163 .banks = 2,
164 .pwrsts_mem_ret = {
165 [0] = PWRSTS_OFF_RET, /* mpu_l2 */
166 [1] = PWRSTS_RET, /* mpu_ram */
167 },
168 .pwrsts_mem_on = {
169 [0] = PWRSTS_OFF_RET, /* mpu_l2 */
170 [1] = PWRSTS_OFF_RET, /* mpu_ram */
171 },
172};
173
174/* custefuse_54xx_pwrdm: Customer efuse controller power domain */
175static struct powerdomain custefuse_54xx_pwrdm = {
176 .name = "custefuse_pwrdm",
177 .voltdm = { .name = "core" },
178 .prcm_offs = OMAP54XX_PRM_CUSTEFUSE_INST,
179 .prcm_partition = OMAP54XX_PRM_PARTITION,
180 .pwrsts = PWRSTS_OFF_ON,
181 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
182};
183
184/* dsp_54xx_pwrdm: Tesla processor power domain */
185static struct powerdomain dsp_54xx_pwrdm = {
186 .name = "dsp_pwrdm",
187 .voltdm = { .name = "mm" },
188 .prcm_offs = OMAP54XX_PRM_DSP_INST,
189 .prcm_partition = OMAP54XX_PRM_PARTITION,
190 .pwrsts = PWRSTS_OFF_RET_ON,
191 .pwrsts_logic_ret = PWRSTS_OFF_RET,
192 .banks = 3,
193 .pwrsts_mem_ret = {
194 [0] = PWRSTS_OFF_RET, /* dsp_edma */
195 [1] = PWRSTS_OFF_RET, /* dsp_l1 */
196 [2] = PWRSTS_OFF_RET, /* dsp_l2 */
197 },
198 .pwrsts_mem_on = {
199 [0] = PWRSTS_OFF_RET, /* dsp_edma */
200 [1] = PWRSTS_OFF_RET, /* dsp_l1 */
201 [2] = PWRSTS_OFF_RET, /* dsp_l2 */
202 },
203 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
204};
205
206/* cam_54xx_pwrdm: Camera subsystem power domain */
207static struct powerdomain cam_54xx_pwrdm = {
208 .name = "cam_pwrdm",
209 .voltdm = { .name = "core" },
210 .prcm_offs = OMAP54XX_PRM_CAM_INST,
211 .prcm_partition = OMAP54XX_PRM_PARTITION,
212 .pwrsts = PWRSTS_OFF_ON,
213 .banks = 1,
214 .pwrsts_mem_ret = {
215 [0] = PWRSTS_OFF_RET, /* cam_mem */
216 },
217 .pwrsts_mem_on = {
218 [0] = PWRSTS_OFF_RET, /* cam_mem */
219 },
220 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
221};
222
223/* l3init_54xx_pwrdm: L3 initators pheripherals power domain */
224static struct powerdomain l3init_54xx_pwrdm = {
225 .name = "l3init_pwrdm",
226 .voltdm = { .name = "core" },
227 .prcm_offs = OMAP54XX_PRM_L3INIT_INST,
228 .prcm_partition = OMAP54XX_PRM_PARTITION,
229 .pwrsts = PWRSTS_RET_ON,
230 .pwrsts_logic_ret = PWRSTS_OFF_RET,
231 .banks = 2,
232 .pwrsts_mem_ret = {
233 [0] = PWRSTS_OFF_RET, /* l3init_bank1 */
234 [1] = PWRSTS_OFF_RET, /* l3init_bank2 */
235 },
236 .pwrsts_mem_on = {
237 [0] = PWRSTS_OFF_RET, /* l3init_bank1 */
238 [1] = PWRSTS_OFF_RET, /* l3init_bank2 */
239 },
240 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
241};
242
243/* gpu_54xx_pwrdm: 3D accelerator power domain */
244static struct powerdomain gpu_54xx_pwrdm = {
245 .name = "gpu_pwrdm",
246 .voltdm = { .name = "mm" },
247 .prcm_offs = OMAP54XX_PRM_GPU_INST,
248 .prcm_partition = OMAP54XX_PRM_PARTITION,
249 .pwrsts = PWRSTS_OFF_ON,
250 .banks = 1,
251 .pwrsts_mem_ret = {
252 [0] = PWRSTS_OFF_RET, /* gpu_mem */
253 },
254 .pwrsts_mem_on = {
255 [0] = PWRSTS_OFF_RET, /* gpu_mem */
256 },
257 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
258};
259
260/* wkupaon_54xx_pwrdm: Wake-up power domain */
261static struct powerdomain wkupaon_54xx_pwrdm = {
262 .name = "wkupaon_pwrdm",
263 .voltdm = { .name = "wkup" },
264 .prcm_offs = OMAP54XX_PRM_WKUPAON_INST,
265 .prcm_partition = OMAP54XX_PRM_PARTITION,
266 .pwrsts = PWRSTS_ON,
267 .banks = 1,
268 .pwrsts_mem_ret = {
269 },
270 .pwrsts_mem_on = {
271 [0] = PWRSTS_ON, /* wkup_bank */
272 },
273};
274
275/* iva_54xx_pwrdm: IVA-HD power domain */
276static struct powerdomain iva_54xx_pwrdm = {
277 .name = "iva_pwrdm",
278 .voltdm = { .name = "mm" },
279 .prcm_offs = OMAP54XX_PRM_IVA_INST,
280 .prcm_partition = OMAP54XX_PRM_PARTITION,
281 .pwrsts = PWRSTS_OFF_RET_ON,
282 .pwrsts_logic_ret = PWRSTS_OFF,
283 .banks = 4,
284 .pwrsts_mem_ret = {
285 [0] = PWRSTS_OFF_RET, /* hwa_mem */
286 [1] = PWRSTS_OFF_RET, /* sl2_mem */
287 [2] = PWRSTS_OFF_RET, /* tcm1_mem */
288 [3] = PWRSTS_OFF_RET, /* tcm2_mem */
289 },
290 .pwrsts_mem_on = {
291 [0] = PWRSTS_OFF_RET, /* hwa_mem */
292 [1] = PWRSTS_OFF_RET, /* sl2_mem */
293 [2] = PWRSTS_OFF_RET, /* tcm1_mem */
294 [3] = PWRSTS_OFF_RET, /* tcm2_mem */
295 },
296 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
297};
298
299/*
300 * The following power domains are not under SW control
301 *
302 * mpuaon
303 * mmaon
304 */
305
306/* As powerdomains are added or removed above, this list must also be changed */
307static struct powerdomain *powerdomains_omap54xx[] __initdata = {
308 &core_54xx_pwrdm,
309 &abe_54xx_pwrdm,
310 &coreaon_54xx_pwrdm,
311 &dss_54xx_pwrdm,
312 &cpu0_54xx_pwrdm,
313 &cpu1_54xx_pwrdm,
314 &emu_54xx_pwrdm,
315 &mpu_54xx_pwrdm,
316 &custefuse_54xx_pwrdm,
317 &dsp_54xx_pwrdm,
318 &cam_54xx_pwrdm,
319 &l3init_54xx_pwrdm,
320 &gpu_54xx_pwrdm,
321 &wkupaon_54xx_pwrdm,
322 &iva_54xx_pwrdm,
323 NULL
324};
325
326void __init omap54xx_powerdomains_init(void)
327{
328 pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
329 pwrdm_register_pwrdms(powerdomains_omap54xx);
330 pwrdm_complete_init();
331}
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index c7d355fafd24..ff1ac4a82a04 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -48,6 +48,17 @@
48#define OMAP3430_NEON_MOD 0xb00 48#define OMAP3430_NEON_MOD 0xb00
49#define OMAP3430ES2_USBHOST_MOD 0xc00 49#define OMAP3430ES2_USBHOST_MOD 0xc00
50 50
51/*
52 * TI81XX PRM module offsets
53 */
54#define TI81XX_PRM_DEVICE_MOD 0x0000
55#define TI816X_PRM_ACTIVE_MOD 0x0a00
56#define TI81XX_PRM_DEFAULT_MOD 0x0b00
57#define TI816X_PRM_IVAHD0_MOD 0x0c00
58#define TI816X_PRM_IVAHD1_MOD 0x0d00
59#define TI816X_PRM_IVAHD2_MOD 0x0e00
60#define TI816X_PRM_SGX_MOD 0x0f00
61
51/* 24XX register bits shared between CM & PRM registers */ 62/* 24XX register bits shared between CM & PRM registers */
52 63
53/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ 64/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
diff --git a/arch/arm/mach-omap2/prcm44xx.h b/arch/arm/mach-omap2/prcm44xx.h
index 7334ffb9d2c1..f429cdd5a118 100644
--- a/arch/arm/mach-omap2/prcm44xx.h
+++ b/arch/arm/mach-omap2/prcm44xx.h
@@ -32,6 +32,12 @@
32#define OMAP4430_SCRM_PARTITION 4 32#define OMAP4430_SCRM_PARTITION 4
33#define OMAP4430_PRCM_MPU_PARTITION 5 33#define OMAP4430_PRCM_MPU_PARTITION 5
34 34
35#define OMAP54XX_PRM_PARTITION 1
36#define OMAP54XX_CM_CORE_AON_PARTITION 2
37#define OMAP54XX_CM_CORE_PARTITION 3
38#define OMAP54XX_SCRM_PARTITION 4
39#define OMAP54XX_PRCM_MPU_PARTITION 5
40
35/* 41/*
36 * OMAP4_MAX_PRCM_PARTITIONS: set to the highest value of the PRCM partition 42 * OMAP4_MAX_PRCM_PARTITIONS: set to the highest value of the PRCM partition
37 * IDs, plus one 43 * IDs, plus one
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h
index 884af7bb4afd..059bd4f49035 100644
--- a/arch/arm/mach-omap2/prcm_mpu44xx.h
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.h
@@ -25,12 +25,9 @@
25#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H 25#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
26#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H 26#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
27 27
28#include "prcm_mpu_44xx_54xx.h"
28#include "common.h" 29#include "common.h"
29 30
30# ifndef __ASSEMBLER__
31extern void __iomem *prcm_mpu_base;
32# endif
33
34#define OMAP4430_PRCM_MPU_BASE 0x48243000 31#define OMAP4430_PRCM_MPU_BASE 0x48243000
35 32
36#define OMAP44XX_PRCM_MPU_REGADDR(inst, reg) \ 33#define OMAP44XX_PRCM_MPU_REGADDR(inst, reg) \
@@ -98,13 +95,4 @@ extern void __iomem *prcm_mpu_base;
98#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018 95#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018
99#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018) 96#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)
100 97
101/* Function prototypes */
102# ifndef __ASSEMBLER__
103extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx);
104extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx);
105extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst,
106 s16 idx);
107extern void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu);
108# endif
109
110#endif 98#endif
diff --git a/arch/arm/mach-omap2/prcm_mpu54xx.h b/arch/arm/mach-omap2/prcm_mpu54xx.h
new file mode 100644
index 000000000000..bc2ce3288315
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm_mpu54xx.h
@@ -0,0 +1,87 @@
1/*
2 * OMAP54xx PRCM MPU instance offset macros
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley (paul@pwsan.com)
7 * Rajendra Nayak (rnayak@ti.com)
8 * Benoit Cousson (b-cousson@ti.com)
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU54XX_H
22#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU54XX_H
23
24#include "prcm_mpu_44xx_54xx.h"
25#include "common.h"
26
27#define OMAP54XX_PRCM_MPU_BASE 0x48243000
28
29#define OMAP54XX_PRCM_MPU_REGADDR(inst, reg) \
30 OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE + (inst) + (reg))
31
32/* PRCM_MPU instances */
33#define OMAP54XX_PRCM_MPU_OCP_SOCKET_INST 0x0000
34#define OMAP54XX_PRCM_MPU_DEVICE_INST 0x0200
35#define OMAP54XX_PRCM_MPU_PRM_C0_INST 0x0400
36#define OMAP54XX_PRCM_MPU_CM_C0_INST 0x0600
37#define OMAP54XX_PRCM_MPU_PRM_C1_INST 0x0800
38#define OMAP54XX_PRCM_MPU_CM_C1_INST 0x0a00
39
40/* PRCM_MPU clockdomain register offsets (from instance start) */
41#define OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS 0x0000
42#define OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS 0x0000
43
44
45/*
46 * PRCM_MPU
47 *
48 * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global)
49 * point of view the PRCM_MPU is a single entity. It shares the same
50 * programming model as the global PRCM and thus can be assimilate as two new
51 * MOD inside the PRCM
52 */
53
54/* PRCM_MPU.PRCM_MPU_OCP_SOCKET register offsets */
55#define OMAP54XX_REVISION_PRCM_MPU_OFFSET 0x0000
56
57/* PRCM_MPU.PRCM_MPU_DEVICE register offsets */
58#define OMAP54XX_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
59#define OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004
60#define OMAP54XX_PRM_FRAC_INCREMENTER_NUMERATOR_OFFSET 0x0010
61#define OMAP54XX_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x0014
62
63/* PRCM_MPU.PRCM_MPU_PRM_C0 register offsets */
64#define OMAP54XX_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
65#define OMAP54XX_PM_CPU0_PWRSTST_OFFSET 0x0004
66#define OMAP54XX_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x0010
67#define OMAP54XX_RM_CPU0_CPU0_RSTST_OFFSET 0x0014
68#define OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0024
69
70/* PRCM_MPU.PRCM_MPU_CM_C0 register offsets */
71#define OMAP54XX_CM_CPU0_CLKSTCTRL_OFFSET 0x0000
72#define OMAP54XX_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0020
73#define OMAP54XX_CM_CPU0_CPU0_CLKCTRL OMAP54XX_PRCM_MPU_REGADDR(OMAP54XX_PRCM_MPU_CM_C0_INST, 0x0020)
74
75/* PRCM_MPU.PRCM_MPU_PRM_C1 register offsets */
76#define OMAP54XX_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
77#define OMAP54XX_PM_CPU1_PWRSTST_OFFSET 0x0004
78#define OMAP54XX_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x0010
79#define OMAP54XX_RM_CPU1_CPU1_RSTST_OFFSET 0x0014
80#define OMAP54XX_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0024
81
82/* PRCM_MPU.PRCM_MPU_CM_C1 register offsets */
83#define OMAP54XX_CM_CPU1_CLKSTCTRL_OFFSET 0x0000
84#define OMAP54XX_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0020
85#define OMAP54XX_CM_CPU1_CPU1_CLKCTRL OMAP54XX_PRCM_MPU_REGADDR(OMAP54XX_PRCM_MPU_CM_C1_INST, 0x0020)
86
87#endif
diff --git a/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h b/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h
new file mode 100644
index 000000000000..ca149e70bed0
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h
@@ -0,0 +1,36 @@
1/*
2 * OMAP44xx and OMAP54xx PRCM MPU function prototypes
3 *
4 * Copyright (C) 2010, 2013 Texas Instruments, Inc.
5 * Copyright (C) 2010 Nokia Corporation
6 *
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 *
21 */
22
23#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU_44XX_54XX_H
24#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU_44XX_54XX_H
25
26#ifndef __ASSEMBLER__
27extern void __iomem *prcm_mpu_base;
28
29extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx);
30extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx);
31extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst,
32 s16 idx);
33extern void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu);
34#endif
35
36#endif
diff --git a/arch/arm/mach-omap2/prm-regbits-54xx.h b/arch/arm/mach-omap2/prm-regbits-54xx.h
new file mode 100644
index 000000000000..be31b21aa9c6
--- /dev/null
+++ b/arch/arm/mach-omap2/prm-regbits-54xx.h
@@ -0,0 +1,2701 @@
1/*
2 * OMAP54xx Power Management register bits
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley (paul@pwsan.com)
7 * Rajendra Nayak (rnayak@ti.com)
8 * Benoit Cousson (b-cousson@ti.com)
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_54XX_H
22#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_54XX_H
23
24/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
25#define OMAP54XX_ABBOFF_ACT_SHIFT 1
26#define OMAP54XX_ABBOFF_ACT_WIDTH 0x1
27#define OMAP54XX_ABBOFF_ACT_MASK (1 << 1)
28
29/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
30#define OMAP54XX_ABBOFF_SLEEP_SHIFT 2
31#define OMAP54XX_ABBOFF_SLEEP_WIDTH 0x1
32#define OMAP54XX_ABBOFF_SLEEP_MASK (1 << 2)
33
34/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
35#define OMAP54XX_ABB_MM_DONE_EN_SHIFT 31
36#define OMAP54XX_ABB_MM_DONE_EN_WIDTH 0x1
37#define OMAP54XX_ABB_MM_DONE_EN_MASK (1 << 31)
38
39/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
40#define OMAP54XX_ABB_MM_DONE_ST_SHIFT 31
41#define OMAP54XX_ABB_MM_DONE_ST_WIDTH 0x1
42#define OMAP54XX_ABB_MM_DONE_ST_MASK (1 << 31)
43
44/* Used by PRM_IRQENABLE_MPU_2 */
45#define OMAP54XX_ABB_MPU_DONE_EN_SHIFT 7
46#define OMAP54XX_ABB_MPU_DONE_EN_WIDTH 0x1
47#define OMAP54XX_ABB_MPU_DONE_EN_MASK (1 << 7)
48
49/* Used by PRM_IRQSTATUS_MPU_2 */
50#define OMAP54XX_ABB_MPU_DONE_ST_SHIFT 7
51#define OMAP54XX_ABB_MPU_DONE_ST_WIDTH 0x1
52#define OMAP54XX_ABB_MPU_DONE_ST_MASK (1 << 7)
53
54/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */
55#define OMAP54XX_ACTIVE_FBB_SEL_SHIFT 2
56#define OMAP54XX_ACTIVE_FBB_SEL_WIDTH 0x1
57#define OMAP54XX_ACTIVE_FBB_SEL_MASK (1 << 2)
58
59/* Used by PM_ABE_PWRSTCTRL */
60#define OMAP54XX_AESSMEM_ONSTATE_SHIFT 16
61#define OMAP54XX_AESSMEM_ONSTATE_WIDTH 0x2
62#define OMAP54XX_AESSMEM_ONSTATE_MASK (0x3 << 16)
63
64/* Used by PM_ABE_PWRSTCTRL */
65#define OMAP54XX_AESSMEM_RETSTATE_SHIFT 8
66#define OMAP54XX_AESSMEM_RETSTATE_WIDTH 0x1
67#define OMAP54XX_AESSMEM_RETSTATE_MASK (1 << 8)
68
69/* Used by PM_ABE_PWRSTST */
70#define OMAP54XX_AESSMEM_STATEST_SHIFT 4
71#define OMAP54XX_AESSMEM_STATEST_WIDTH 0x2
72#define OMAP54XX_AESSMEM_STATEST_MASK (0x3 << 4)
73
74/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
75#define OMAP54XX_AIPOFF_SHIFT 8
76#define OMAP54XX_AIPOFF_WIDTH 0x1
77#define OMAP54XX_AIPOFF_MASK (1 << 8)
78
79/* Used by PRM_VOLTCTRL */
80#define OMAP54XX_AUTO_CTRL_VDD_CORE_L_SHIFT 0
81#define OMAP54XX_AUTO_CTRL_VDD_CORE_L_WIDTH 0x2
82#define OMAP54XX_AUTO_CTRL_VDD_CORE_L_MASK (0x3 << 0)
83
84/* Used by PRM_VOLTCTRL */
85#define OMAP54XX_AUTO_CTRL_VDD_MM_L_SHIFT 4
86#define OMAP54XX_AUTO_CTRL_VDD_MM_L_WIDTH 0x2
87#define OMAP54XX_AUTO_CTRL_VDD_MM_L_MASK (0x3 << 4)
88
89/* Used by PRM_VOLTCTRL */
90#define OMAP54XX_AUTO_CTRL_VDD_MPU_L_SHIFT 2
91#define OMAP54XX_AUTO_CTRL_VDD_MPU_L_WIDTH 0x2
92#define OMAP54XX_AUTO_CTRL_VDD_MPU_L_MASK (0x3 << 2)
93
94/* Used by PRM_VC_BYPASS_ERRST */
95#define OMAP54XX_BYPS_RA_ERR_SHIFT 1
96#define OMAP54XX_BYPS_RA_ERR_WIDTH 0x1
97#define OMAP54XX_BYPS_RA_ERR_MASK (1 << 1)
98
99/* Used by PRM_VC_BYPASS_ERRST */
100#define OMAP54XX_BYPS_SA_ERR_SHIFT 0
101#define OMAP54XX_BYPS_SA_ERR_WIDTH 0x1
102#define OMAP54XX_BYPS_SA_ERR_MASK (1 << 0)
103
104/* Used by PRM_VC_BYPASS_ERRST */
105#define OMAP54XX_BYPS_TIMEOUT_ERR_SHIFT 2
106#define OMAP54XX_BYPS_TIMEOUT_ERR_WIDTH 0x1
107#define OMAP54XX_BYPS_TIMEOUT_ERR_MASK (1 << 2)
108
109/* Used by PRM_RSTST */
110#define OMAP54XX_C2C_RST_SHIFT 10
111#define OMAP54XX_C2C_RST_WIDTH 0x1
112#define OMAP54XX_C2C_RST_MASK (1 << 10)
113
114/* Used by PM_CAM_PWRSTCTRL */
115#define OMAP54XX_CAM_MEM_ONSTATE_SHIFT 16
116#define OMAP54XX_CAM_MEM_ONSTATE_WIDTH 0x2
117#define OMAP54XX_CAM_MEM_ONSTATE_MASK (0x3 << 16)
118
119/* Used by PM_CAM_PWRSTST */
120#define OMAP54XX_CAM_MEM_STATEST_SHIFT 4
121#define OMAP54XX_CAM_MEM_STATEST_WIDTH 0x2
122#define OMAP54XX_CAM_MEM_STATEST_MASK (0x3 << 4)
123
124/* Used by PRM_CLKREQCTRL */
125#define OMAP54XX_CLKREQ_COND_SHIFT 0
126#define OMAP54XX_CLKREQ_COND_WIDTH 0x3
127#define OMAP54XX_CLKREQ_COND_MASK (0x7 << 0)
128
129/* Used by PRM_VC_SMPS_CORE_CONFIG */
130#define OMAP54XX_CMDRA_VDD_CORE_L_SHIFT 16
131#define OMAP54XX_CMDRA_VDD_CORE_L_WIDTH 0x8
132#define OMAP54XX_CMDRA_VDD_CORE_L_MASK (0xff << 16)
133
134/* Used by PRM_VC_SMPS_MM_CONFIG */
135#define OMAP54XX_CMDRA_VDD_MM_L_SHIFT 16
136#define OMAP54XX_CMDRA_VDD_MM_L_WIDTH 0x8
137#define OMAP54XX_CMDRA_VDD_MM_L_MASK (0xff << 16)
138
139/* Used by PRM_VC_SMPS_MPU_CONFIG */
140#define OMAP54XX_CMDRA_VDD_MPU_L_SHIFT 16
141#define OMAP54XX_CMDRA_VDD_MPU_L_WIDTH 0x8
142#define OMAP54XX_CMDRA_VDD_MPU_L_MASK (0xff << 16)
143
144/* Used by PRM_VC_SMPS_CORE_CONFIG */
145#define OMAP54XX_CMD_VDD_CORE_L_SHIFT 28
146#define OMAP54XX_CMD_VDD_CORE_L_WIDTH 0x1
147#define OMAP54XX_CMD_VDD_CORE_L_MASK (1 << 28)
148
149/* Used by PRM_VC_SMPS_MM_CONFIG */
150#define OMAP54XX_CMD_VDD_MM_L_SHIFT 28
151#define OMAP54XX_CMD_VDD_MM_L_WIDTH 0x1
152#define OMAP54XX_CMD_VDD_MM_L_MASK (1 << 28)
153
154/* Used by PRM_VC_SMPS_MPU_CONFIG */
155#define OMAP54XX_CMD_VDD_MPU_L_SHIFT 28
156#define OMAP54XX_CMD_VDD_MPU_L_WIDTH 0x1
157#define OMAP54XX_CMD_VDD_MPU_L_MASK (1 << 28)
158
159/* Used by PM_CORE_PWRSTCTRL */
160#define OMAP54XX_CORE_OCMRAM_ONSTATE_SHIFT 18
161#define OMAP54XX_CORE_OCMRAM_ONSTATE_WIDTH 0x2
162#define OMAP54XX_CORE_OCMRAM_ONSTATE_MASK (0x3 << 18)
163
164/* Used by PM_CORE_PWRSTCTRL */
165#define OMAP54XX_CORE_OCMRAM_RETSTATE_SHIFT 9
166#define OMAP54XX_CORE_OCMRAM_RETSTATE_WIDTH 0x1
167#define OMAP54XX_CORE_OCMRAM_RETSTATE_MASK (1 << 9)
168
169/* Used by PM_CORE_PWRSTST */
170#define OMAP54XX_CORE_OCMRAM_STATEST_SHIFT 6
171#define OMAP54XX_CORE_OCMRAM_STATEST_WIDTH 0x2
172#define OMAP54XX_CORE_OCMRAM_STATEST_MASK (0x3 << 6)
173
174/* Used by PM_CORE_PWRSTCTRL */
175#define OMAP54XX_CORE_OTHER_BANK_ONSTATE_SHIFT 16
176#define OMAP54XX_CORE_OTHER_BANK_ONSTATE_WIDTH 0x2
177#define OMAP54XX_CORE_OTHER_BANK_ONSTATE_MASK (0x3 << 16)
178
179/* Used by PM_CORE_PWRSTCTRL */
180#define OMAP54XX_CORE_OTHER_BANK_RETSTATE_SHIFT 8
181#define OMAP54XX_CORE_OTHER_BANK_RETSTATE_WIDTH 0x1
182#define OMAP54XX_CORE_OTHER_BANK_RETSTATE_MASK (1 << 8)
183
184/* Used by PM_CORE_PWRSTST */
185#define OMAP54XX_CORE_OTHER_BANK_STATEST_SHIFT 4
186#define OMAP54XX_CORE_OTHER_BANK_STATEST_WIDTH 0x2
187#define OMAP54XX_CORE_OTHER_BANK_STATEST_MASK (0x3 << 4)
188
189/* Used by REVISION_PRM */
190#define OMAP54XX_CUSTOM_SHIFT 6
191#define OMAP54XX_CUSTOM_WIDTH 0x2
192#define OMAP54XX_CUSTOM_MASK (0x3 << 6)
193
194/* Used by PRM_VC_VAL_BYPASS */
195#define OMAP54XX_DATA_SHIFT 16
196#define OMAP54XX_DATA_WIDTH 0x8
197#define OMAP54XX_DATA_MASK (0xff << 16)
198
199/* Used by PRM_DEBUG_CORE_RET_TRANS */
200#define OMAP54XX_PRM_DEBUG_OUT_SHIFT 0
201#define OMAP54XX_PRM_DEBUG_OUT_WIDTH 0x1c
202#define OMAP54XX_PRM_DEBUG_OUT_MASK (0xfffffff << 0)
203
204/* Renamed from DEBUG_OUT Used by PRM_DEBUG_MM_RET_TRANS */
205#define OMAP54XX_DEBUG_OUT_0_9_SHIFT 0
206#define OMAP54XX_DEBUG_OUT_0_9_WIDTH 0xa
207#define OMAP54XX_DEBUG_OUT_0_9_MASK (0x3ff << 0)
208
209/* Renamed from DEBUG_OUT Used by PRM_DEBUG_MPU_RET_TRANS */
210#define OMAP54XX_DEBUG_OUT_0_6_SHIFT 0
211#define OMAP54XX_DEBUG_OUT_0_6_WIDTH 0x7
212#define OMAP54XX_DEBUG_OUT_0_6_MASK (0x7f << 0)
213
214/* Renamed from DEBUG_OUT Used by PRM_DEBUG_OFF_TRANS */
215#define OMAP54XX_DEBUG_OUT_0_31_SHIFT 0
216#define OMAP54XX_DEBUG_OUT_0_31_WIDTH 0x20
217#define OMAP54XX_DEBUG_OUT_0_31_MASK (0xffffffff << 0)
218
219/* Renamed from DEBUG_OUT Used by PRM_DEBUG_WKUPAON_FD_TRANS */
220#define OMAP54XX_DEBUG_OUT_0_11_SHIFT 0
221#define OMAP54XX_DEBUG_OUT_0_11_WIDTH 0xc
222#define OMAP54XX_DEBUG_OUT_0_11_MASK (0xfff << 0)
223
224/* Used by PRM_DEVICE_OFF_CTRL */
225#define OMAP54XX_DEVICE_OFF_ENABLE_SHIFT 0
226#define OMAP54XX_DEVICE_OFF_ENABLE_WIDTH 0x1
227#define OMAP54XX_DEVICE_OFF_ENABLE_MASK (1 << 0)
228
229/* Used by PRM_VC_CFG_I2C_MODE */
230#define OMAP54XX_DFILTEREN_SHIFT 6
231#define OMAP54XX_DFILTEREN_WIDTH 0x1
232#define OMAP54XX_DFILTEREN_MASK (1 << 6)
233
234/* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
235#define OMAP54XX_DPLL_ABE_RECAL_EN_SHIFT 4
236#define OMAP54XX_DPLL_ABE_RECAL_EN_WIDTH 0x1
237#define OMAP54XX_DPLL_ABE_RECAL_EN_MASK (1 << 4)
238
239/* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
240#define OMAP54XX_DPLL_ABE_RECAL_ST_SHIFT 4
241#define OMAP54XX_DPLL_ABE_RECAL_ST_WIDTH 0x1
242#define OMAP54XX_DPLL_ABE_RECAL_ST_MASK (1 << 4)
243
244/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
245#define OMAP54XX_DPLL_CORE_RECAL_EN_SHIFT 0
246#define OMAP54XX_DPLL_CORE_RECAL_EN_WIDTH 0x1
247#define OMAP54XX_DPLL_CORE_RECAL_EN_MASK (1 << 0)
248
249/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
250#define OMAP54XX_DPLL_CORE_RECAL_ST_SHIFT 0
251#define OMAP54XX_DPLL_CORE_RECAL_ST_WIDTH 0x1
252#define OMAP54XX_DPLL_CORE_RECAL_ST_MASK (1 << 0)
253
254/* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
255#define OMAP54XX_DPLL_IVA_RECAL_EN_SHIFT 2
256#define OMAP54XX_DPLL_IVA_RECAL_EN_WIDTH 0x1
257#define OMAP54XX_DPLL_IVA_RECAL_EN_MASK (1 << 2)
258
259/* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
260#define OMAP54XX_DPLL_IVA_RECAL_ST_SHIFT 2
261#define OMAP54XX_DPLL_IVA_RECAL_ST_WIDTH 0x1
262#define OMAP54XX_DPLL_IVA_RECAL_ST_MASK (1 << 2)
263
264/* Used by PRM_IRQENABLE_MPU */
265#define OMAP54XX_DPLL_MPU_RECAL_EN_SHIFT 1
266#define OMAP54XX_DPLL_MPU_RECAL_EN_WIDTH 0x1
267#define OMAP54XX_DPLL_MPU_RECAL_EN_MASK (1 << 1)
268
269/* Used by PRM_IRQSTATUS_MPU */
270#define OMAP54XX_DPLL_MPU_RECAL_ST_SHIFT 1
271#define OMAP54XX_DPLL_MPU_RECAL_ST_WIDTH 0x1
272#define OMAP54XX_DPLL_MPU_RECAL_ST_MASK (1 << 1)
273
274/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
275#define OMAP54XX_DPLL_PER_RECAL_EN_SHIFT 3
276#define OMAP54XX_DPLL_PER_RECAL_EN_WIDTH 0x1
277#define OMAP54XX_DPLL_PER_RECAL_EN_MASK (1 << 3)
278
279/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
280#define OMAP54XX_DPLL_PER_RECAL_ST_SHIFT 3
281#define OMAP54XX_DPLL_PER_RECAL_ST_WIDTH 0x1
282#define OMAP54XX_DPLL_PER_RECAL_ST_MASK (1 << 3)
283
284/* Used by PM_DSP_PWRSTCTRL */
285#define OMAP54XX_DSP_EDMA_ONSTATE_SHIFT 20
286#define OMAP54XX_DSP_EDMA_ONSTATE_WIDTH 0x2
287#define OMAP54XX_DSP_EDMA_ONSTATE_MASK (0x3 << 20)
288
289/* Used by PM_DSP_PWRSTCTRL */
290#define OMAP54XX_DSP_EDMA_RETSTATE_SHIFT 10
291#define OMAP54XX_DSP_EDMA_RETSTATE_WIDTH 0x1
292#define OMAP54XX_DSP_EDMA_RETSTATE_MASK (1 << 10)
293
294/* Used by PM_DSP_PWRSTST */
295#define OMAP54XX_DSP_EDMA_STATEST_SHIFT 8
296#define OMAP54XX_DSP_EDMA_STATEST_WIDTH 0x2
297#define OMAP54XX_DSP_EDMA_STATEST_MASK (0x3 << 8)
298
299/* Used by PM_DSP_PWRSTCTRL */
300#define OMAP54XX_DSP_L1_ONSTATE_SHIFT 16
301#define OMAP54XX_DSP_L1_ONSTATE_WIDTH 0x2
302#define OMAP54XX_DSP_L1_ONSTATE_MASK (0x3 << 16)
303
304/* Used by PM_DSP_PWRSTCTRL */
305#define OMAP54XX_DSP_L1_RETSTATE_SHIFT 8
306#define OMAP54XX_DSP_L1_RETSTATE_WIDTH 0x1
307#define OMAP54XX_DSP_L1_RETSTATE_MASK (1 << 8)
308
309/* Used by PM_DSP_PWRSTST */
310#define OMAP54XX_DSP_L1_STATEST_SHIFT 4
311#define OMAP54XX_DSP_L1_STATEST_WIDTH 0x2
312#define OMAP54XX_DSP_L1_STATEST_MASK (0x3 << 4)
313
314/* Used by PM_DSP_PWRSTCTRL */
315#define OMAP54XX_DSP_L2_ONSTATE_SHIFT 18
316#define OMAP54XX_DSP_L2_ONSTATE_WIDTH 0x2
317#define OMAP54XX_DSP_L2_ONSTATE_MASK (0x3 << 18)
318
319/* Used by PM_DSP_PWRSTCTRL */
320#define OMAP54XX_DSP_L2_RETSTATE_SHIFT 9
321#define OMAP54XX_DSP_L2_RETSTATE_WIDTH 0x1
322#define OMAP54XX_DSP_L2_RETSTATE_MASK (1 << 9)
323
324/* Used by PM_DSP_PWRSTST */
325#define OMAP54XX_DSP_L2_STATEST_SHIFT 6
326#define OMAP54XX_DSP_L2_STATEST_WIDTH 0x2
327#define OMAP54XX_DSP_L2_STATEST_MASK (0x3 << 6)
328
329/* Used by PM_DSS_PWRSTCTRL */
330#define OMAP54XX_DSS_MEM_ONSTATE_SHIFT 16
331#define OMAP54XX_DSS_MEM_ONSTATE_WIDTH 0x2
332#define OMAP54XX_DSS_MEM_ONSTATE_MASK (0x3 << 16)
333
334/* Used by PM_DSS_PWRSTCTRL */
335#define OMAP54XX_DSS_MEM_RETSTATE_SHIFT 8
336#define OMAP54XX_DSS_MEM_RETSTATE_WIDTH 0x1
337#define OMAP54XX_DSS_MEM_RETSTATE_MASK (1 << 8)
338
339/* Used by PM_DSS_PWRSTST */
340#define OMAP54XX_DSS_MEM_STATEST_SHIFT 4
341#define OMAP54XX_DSS_MEM_STATEST_WIDTH 0x2
342#define OMAP54XX_DSS_MEM_STATEST_MASK (0x3 << 4)
343
344/* Used by PRM_DEVICE_OFF_CTRL */
345#define OMAP54XX_EMIF1_OFFWKUP_DISABLE_SHIFT 8
346#define OMAP54XX_EMIF1_OFFWKUP_DISABLE_WIDTH 0x1
347#define OMAP54XX_EMIF1_OFFWKUP_DISABLE_MASK (1 << 8)
348
349/* Used by PRM_DEVICE_OFF_CTRL */
350#define OMAP54XX_EMIF2_OFFWKUP_DISABLE_SHIFT 9
351#define OMAP54XX_EMIF2_OFFWKUP_DISABLE_WIDTH 0x1
352#define OMAP54XX_EMIF2_OFFWKUP_DISABLE_MASK (1 << 9)
353
354/* Used by PM_EMU_PWRSTCTRL */
355#define OMAP54XX_EMU_BANK_ONSTATE_SHIFT 16
356#define OMAP54XX_EMU_BANK_ONSTATE_WIDTH 0x2
357#define OMAP54XX_EMU_BANK_ONSTATE_MASK (0x3 << 16)
358
359/* Used by PM_EMU_PWRSTST */
360#define OMAP54XX_EMU_BANK_STATEST_SHIFT 4
361#define OMAP54XX_EMU_BANK_STATEST_WIDTH 0x2
362#define OMAP54XX_EMU_BANK_STATEST_MASK (0x3 << 4)
363
364/*
365 * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP,
366 * PRM_SRAM_WKUP_SETUP
367 */
368#define OMAP54XX_ENABLE_RTA_SHIFT 0
369#define OMAP54XX_ENABLE_RTA_WIDTH 0x1
370#define OMAP54XX_ENABLE_RTA_MASK (1 << 0)
371
372/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
373#define OMAP54XX_ENFUNC1_SHIFT 3
374#define OMAP54XX_ENFUNC1_WIDTH 0x1
375#define OMAP54XX_ENFUNC1_MASK (1 << 3)
376
377/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
378#define OMAP54XX_ENFUNC2_SHIFT 4
379#define OMAP54XX_ENFUNC2_WIDTH 0x1
380#define OMAP54XX_ENFUNC2_MASK (1 << 4)
381
382/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
383#define OMAP54XX_ENFUNC3_SHIFT 5
384#define OMAP54XX_ENFUNC3_WIDTH 0x1
385#define OMAP54XX_ENFUNC3_MASK (1 << 5)
386
387/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
388#define OMAP54XX_ENFUNC4_SHIFT 6
389#define OMAP54XX_ENFUNC4_WIDTH 0x1
390#define OMAP54XX_ENFUNC4_MASK (1 << 6)
391
392/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
393#define OMAP54XX_ENFUNC5_SHIFT 7
394#define OMAP54XX_ENFUNC5_WIDTH 0x1
395#define OMAP54XX_ENFUNC5_MASK (1 << 7)
396
397/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
398#define OMAP54XX_ERRORGAIN_SHIFT 16
399#define OMAP54XX_ERRORGAIN_WIDTH 0x8
400#define OMAP54XX_ERRORGAIN_MASK (0xff << 16)
401
402/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
403#define OMAP54XX_ERROROFFSET_SHIFT 24
404#define OMAP54XX_ERROROFFSET_WIDTH 0x8
405#define OMAP54XX_ERROROFFSET_MASK (0xff << 24)
406
407/* Used by PRM_RSTST */
408#define OMAP54XX_EXTERNAL_WARM_RST_SHIFT 5
409#define OMAP54XX_EXTERNAL_WARM_RST_WIDTH 0x1
410#define OMAP54XX_EXTERNAL_WARM_RST_MASK (1 << 5)
411
412/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
413#define OMAP54XX_FORCEUPDATE_SHIFT 1
414#define OMAP54XX_FORCEUPDATE_WIDTH 0x1
415#define OMAP54XX_FORCEUPDATE_MASK (1 << 1)
416
417/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_MM_VOLTAGE, PRM_VP_MPU_VOLTAGE */
418#define OMAP54XX_FORCEUPDATEWAIT_SHIFT 8
419#define OMAP54XX_FORCEUPDATEWAIT_WIDTH 0x18
420#define OMAP54XX_FORCEUPDATEWAIT_MASK (0xffffff << 8)
421
422/* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU */
423#define OMAP54XX_FORCEWKUP_EN_SHIFT 10
424#define OMAP54XX_FORCEWKUP_EN_WIDTH 0x1
425#define OMAP54XX_FORCEWKUP_EN_MASK (1 << 10)
426
427/* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU */
428#define OMAP54XX_FORCEWKUP_ST_SHIFT 10
429#define OMAP54XX_FORCEWKUP_ST_WIDTH 0x1
430#define OMAP54XX_FORCEWKUP_ST_MASK (1 << 10)
431
432/* Used by REVISION_PRM */
433#define OMAP54XX_FUNC_SHIFT 16
434#define OMAP54XX_FUNC_WIDTH 0xc
435#define OMAP54XX_FUNC_MASK (0xfff << 16)
436
437/* Used by PRM_RSTST */
438#define OMAP54XX_GLOBAL_COLD_RST_SHIFT 0
439#define OMAP54XX_GLOBAL_COLD_RST_WIDTH 0x1
440#define OMAP54XX_GLOBAL_COLD_RST_MASK (1 << 0)
441
442/* Used by PRM_RSTST */
443#define OMAP54XX_GLOBAL_WARM_SW_RST_SHIFT 1
444#define OMAP54XX_GLOBAL_WARM_SW_RST_WIDTH 0x1
445#define OMAP54XX_GLOBAL_WARM_SW_RST_MASK (1 << 1)
446
447/* Used by PRM_IO_PMCTRL */
448#define OMAP54XX_GLOBAL_WUEN_SHIFT 16
449#define OMAP54XX_GLOBAL_WUEN_WIDTH 0x1
450#define OMAP54XX_GLOBAL_WUEN_MASK (1 << 16)
451
452/* Used by PM_GPU_PWRSTCTRL */
453#define OMAP54XX_GPU_MEM_ONSTATE_SHIFT 16
454#define OMAP54XX_GPU_MEM_ONSTATE_WIDTH 0x2
455#define OMAP54XX_GPU_MEM_ONSTATE_MASK (0x3 << 16)
456
457/* Used by PM_GPU_PWRSTST */
458#define OMAP54XX_GPU_MEM_STATEST_SHIFT 4
459#define OMAP54XX_GPU_MEM_STATEST_WIDTH 0x2
460#define OMAP54XX_GPU_MEM_STATEST_MASK (0x3 << 4)
461
462/* Used by PRM_VC_CFG_I2C_MODE */
463#define OMAP54XX_HSMCODE_SHIFT 0
464#define OMAP54XX_HSMCODE_WIDTH 0x3
465#define OMAP54XX_HSMCODE_MASK (0x7 << 0)
466
467/* Used by PRM_VC_CFG_I2C_MODE */
468#define OMAP54XX_HSMODEEN_SHIFT 3
469#define OMAP54XX_HSMODEEN_WIDTH 0x1
470#define OMAP54XX_HSMODEEN_MASK (1 << 3)
471
472/* Used by PRM_VC_CFG_I2C_CLK */
473#define OMAP54XX_HSSCLH_SHIFT 16
474#define OMAP54XX_HSSCLH_WIDTH 0x8
475#define OMAP54XX_HSSCLH_MASK (0xff << 16)
476
477/* Used by PRM_VC_CFG_I2C_CLK */
478#define OMAP54XX_HSSCLL_SHIFT 24
479#define OMAP54XX_HSSCLL_WIDTH 0x8
480#define OMAP54XX_HSSCLL_MASK (0xff << 24)
481
482/* Used by PM_IVA_PWRSTCTRL */
483#define OMAP54XX_HWA_MEM_ONSTATE_SHIFT 16
484#define OMAP54XX_HWA_MEM_ONSTATE_WIDTH 0x2
485#define OMAP54XX_HWA_MEM_ONSTATE_MASK (0x3 << 16)
486
487/* Used by PM_IVA_PWRSTCTRL */
488#define OMAP54XX_HWA_MEM_RETSTATE_SHIFT 8
489#define OMAP54XX_HWA_MEM_RETSTATE_WIDTH 0x1
490#define OMAP54XX_HWA_MEM_RETSTATE_MASK (1 << 8)
491
492/* Used by PM_IVA_PWRSTST */
493#define OMAP54XX_HWA_MEM_STATEST_SHIFT 4
494#define OMAP54XX_HWA_MEM_STATEST_WIDTH 0x2
495#define OMAP54XX_HWA_MEM_STATEST_MASK (0x3 << 4)
496
497/* Used by PRM_RSTST */
498#define OMAP54XX_ICEPICK_RST_SHIFT 9
499#define OMAP54XX_ICEPICK_RST_WIDTH 0x1
500#define OMAP54XX_ICEPICK_RST_MASK (1 << 9)
501
502/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
503#define OMAP54XX_INITVDD_SHIFT 2
504#define OMAP54XX_INITVDD_WIDTH 0x1
505#define OMAP54XX_INITVDD_MASK (1 << 2)
506
507/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
508#define OMAP54XX_INITVOLTAGE_SHIFT 8
509#define OMAP54XX_INITVOLTAGE_WIDTH 0x8
510#define OMAP54XX_INITVOLTAGE_MASK (0xff << 8)
511
512/*
513 * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST,
514 * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
515 * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST,
516 * PRM_VOLTST_MM, PRM_VOLTST_MPU
517 */
518#define OMAP54XX_INTRANSITION_SHIFT 20
519#define OMAP54XX_INTRANSITION_WIDTH 0x1
520#define OMAP54XX_INTRANSITION_MASK (1 << 20)
521
522/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
523#define OMAP54XX_IO_EN_SHIFT 9
524#define OMAP54XX_IO_EN_WIDTH 0x1
525#define OMAP54XX_IO_EN_MASK (1 << 9)
526
527/* Used by PRM_IO_PMCTRL */
528#define OMAP54XX_IO_ON_STATUS_SHIFT 5
529#define OMAP54XX_IO_ON_STATUS_WIDTH 0x1
530#define OMAP54XX_IO_ON_STATUS_MASK (1 << 5)
531
532/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
533#define OMAP54XX_IO_ST_SHIFT 9
534#define OMAP54XX_IO_ST_WIDTH 0x1
535#define OMAP54XX_IO_ST_MASK (1 << 9)
536
537/* Used by PM_CORE_PWRSTCTRL */
538#define OMAP54XX_IPU_L2RAM_ONSTATE_SHIFT 20
539#define OMAP54XX_IPU_L2RAM_ONSTATE_WIDTH 0x2
540#define OMAP54XX_IPU_L2RAM_ONSTATE_MASK (0x3 << 20)
541
542/* Used by PM_CORE_PWRSTCTRL */
543#define OMAP54XX_IPU_L2RAM_RETSTATE_SHIFT 10
544#define OMAP54XX_IPU_L2RAM_RETSTATE_WIDTH 0x1
545#define OMAP54XX_IPU_L2RAM_RETSTATE_MASK (1 << 10)
546
547/* Used by PM_CORE_PWRSTST */
548#define OMAP54XX_IPU_L2RAM_STATEST_SHIFT 8
549#define OMAP54XX_IPU_L2RAM_STATEST_WIDTH 0x2
550#define OMAP54XX_IPU_L2RAM_STATEST_MASK (0x3 << 8)
551
552/* Used by PM_CORE_PWRSTCTRL */
553#define OMAP54XX_IPU_UNICACHE_ONSTATE_SHIFT 22
554#define OMAP54XX_IPU_UNICACHE_ONSTATE_WIDTH 0x2
555#define OMAP54XX_IPU_UNICACHE_ONSTATE_MASK (0x3 << 22)
556
557/* Used by PM_CORE_PWRSTCTRL */
558#define OMAP54XX_IPU_UNICACHE_RETSTATE_SHIFT 11
559#define OMAP54XX_IPU_UNICACHE_RETSTATE_WIDTH 0x1
560#define OMAP54XX_IPU_UNICACHE_RETSTATE_MASK (1 << 11)
561
562/* Used by PM_CORE_PWRSTST */
563#define OMAP54XX_IPU_UNICACHE_STATEST_SHIFT 10
564#define OMAP54XX_IPU_UNICACHE_STATEST_WIDTH 0x2
565#define OMAP54XX_IPU_UNICACHE_STATEST_MASK (0x3 << 10)
566
567/* Used by PRM_IO_PMCTRL */
568#define OMAP54XX_ISOCLK_OVERRIDE_SHIFT 0
569#define OMAP54XX_ISOCLK_OVERRIDE_WIDTH 0x1
570#define OMAP54XX_ISOCLK_OVERRIDE_MASK (1 << 0)
571
572/* Used by PRM_IO_PMCTRL */
573#define OMAP54XX_ISOCLK_STATUS_SHIFT 1
574#define OMAP54XX_ISOCLK_STATUS_WIDTH 0x1
575#define OMAP54XX_ISOCLK_STATUS_MASK (1 << 1)
576
577/* Used by PRM_IO_PMCTRL */
578#define OMAP54XX_ISOOVR_EXTEND_SHIFT 4
579#define OMAP54XX_ISOOVR_EXTEND_WIDTH 0x1
580#define OMAP54XX_ISOOVR_EXTEND_MASK (1 << 4)
581
582/* Used by PRM_IO_COUNT */
583#define OMAP54XX_ISO_2_ON_TIME_SHIFT 0
584#define OMAP54XX_ISO_2_ON_TIME_WIDTH 0x8
585#define OMAP54XX_ISO_2_ON_TIME_MASK (0xff << 0)
586
587/* Used by PM_L3INIT_PWRSTCTRL */
588#define OMAP54XX_L3INIT_BANK1_ONSTATE_SHIFT 16
589#define OMAP54XX_L3INIT_BANK1_ONSTATE_WIDTH 0x2
590#define OMAP54XX_L3INIT_BANK1_ONSTATE_MASK (0x3 << 16)
591
592/* Used by PM_L3INIT_PWRSTCTRL */
593#define OMAP54XX_L3INIT_BANK1_RETSTATE_SHIFT 8
594#define OMAP54XX_L3INIT_BANK1_RETSTATE_WIDTH 0x1
595#define OMAP54XX_L3INIT_BANK1_RETSTATE_MASK (1 << 8)
596
597/* Used by PM_L3INIT_PWRSTST */
598#define OMAP54XX_L3INIT_BANK1_STATEST_SHIFT 4
599#define OMAP54XX_L3INIT_BANK1_STATEST_WIDTH 0x2
600#define OMAP54XX_L3INIT_BANK1_STATEST_MASK (0x3 << 4)
601
602/* Used by PM_L3INIT_PWRSTCTRL */
603#define OMAP54XX_L3INIT_BANK2_ONSTATE_SHIFT 18
604#define OMAP54XX_L3INIT_BANK2_ONSTATE_WIDTH 0x2
605#define OMAP54XX_L3INIT_BANK2_ONSTATE_MASK (0x3 << 18)
606
607/* Used by PM_L3INIT_PWRSTCTRL */
608#define OMAP54XX_L3INIT_BANK2_RETSTATE_SHIFT 9
609#define OMAP54XX_L3INIT_BANK2_RETSTATE_WIDTH 0x1
610#define OMAP54XX_L3INIT_BANK2_RETSTATE_MASK (1 << 9)
611
612/* Used by PM_L3INIT_PWRSTST */
613#define OMAP54XX_L3INIT_BANK2_STATEST_SHIFT 6
614#define OMAP54XX_L3INIT_BANK2_STATEST_WIDTH 0x2
615#define OMAP54XX_L3INIT_BANK2_STATEST_MASK (0x3 << 6)
616
617/*
618 * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST,
619 * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
620 * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST
621 */
622#define OMAP54XX_LASTPOWERSTATEENTERED_SHIFT 24
623#define OMAP54XX_LASTPOWERSTATEENTERED_WIDTH 0x2
624#define OMAP54XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24)
625
626/* Used by PRM_RSTST */
627#define OMAP54XX_LLI_RST_SHIFT 14
628#define OMAP54XX_LLI_RST_WIDTH 0x1
629#define OMAP54XX_LLI_RST_MASK (1 << 14)
630
631/*
632 * Used by PM_ABE_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_DSP_PWRSTCTRL,
633 * PM_DSS_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_MPU_PWRSTCTRL
634 */
635#define OMAP54XX_LOGICRETSTATE_SHIFT 2
636#define OMAP54XX_LOGICRETSTATE_WIDTH 0x1
637#define OMAP54XX_LOGICRETSTATE_MASK (1 << 2)
638
639/*
640 * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST,
641 * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
642 * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST
643 */
644#define OMAP54XX_LOGICSTATEST_SHIFT 2
645#define OMAP54XX_LOGICSTATEST_WIDTH 0x1
646#define OMAP54XX_LOGICSTATEST_MASK (1 << 2)
647
648/*
649 * Used by RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT,
650 * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT,
651 * RM_ABE_MCPDM_CONTEXT, RM_ABE_SLIMBUS1_CONTEXT, RM_ABE_TIMER5_CONTEXT,
652 * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT,
653 * RM_ABE_WD_TIMER3_CONTEXT, RM_C2C_C2C_CONTEXT, RM_C2C_C2C_OCP_FW_CONTEXT,
654 * RM_CAM_CAL_CONTEXT, RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT,
655 * RM_COREAON_SMARTREFLEX_CORE_CONTEXT, RM_COREAON_SMARTREFLEX_MM_CONTEXT,
656 * RM_COREAON_SMARTREFLEX_MPU_CONTEXT, RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT,
657 * RM_DSP_DSP_CONTEXT, RM_DSS_BB2D_CONTEXT, RM_DSS_DSS_CONTEXT,
658 * RM_EMIF_DMM_CONTEXT, RM_EMIF_EMIF1_CONTEXT, RM_EMIF_EMIF2_CONTEXT,
659 * RM_EMIF_EMIF_DLL_CONTEXT, RM_EMIF_EMIF_OCP_FW_CONTEXT,
660 * RM_EMU_DEBUGSS_CONTEXT, RM_GPU_GPU_CONTEXT, RM_IPU_IPU_CONTEXT,
661 * RM_IVA_IVA_CONTEXT, RM_IVA_SL2_CONTEXT, RM_L3INIT_IEEE1500_2_OCP_CONTEXT,
662 * RM_L3INIT_OCP2SCP1_CONTEXT, RM_L3INIT_OCP2SCP3_CONTEXT,
663 * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_UNIPRO2_CONTEXT,
664 * RM_L3INSTR_L3_INSTR_CONTEXT, RM_L3INSTR_L3_MAIN_3_CONTEXT,
665 * RM_L3INSTR_OCP_WP_NOC_CONTEXT, RM_L3MAIN1_L3_MAIN_1_CONTEXT,
666 * RM_L3MAIN2_L3_MAIN_2_CONTEXT, RM_L3MAIN2_OCMC_RAM_CONTEXT,
667 * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_OCP2SCP2_CONTEXT,
668 * RM_L4CFG_SAR_ROM_CONTEXT, RM_L4PER_ELM_CONTEXT, RM_L4PER_HDQ1W_CONTEXT,
669 * RM_L4PER_I2C2_CONTEXT, RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT,
670 * RM_L4PER_I2C5_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCSPI1_CONTEXT,
671 * RM_L4PER_MCSPI2_CONTEXT, RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT,
672 * RM_L4PER_MMC3_CONTEXT, RM_L4PER_MMC4_CONTEXT, RM_L4PER_MMC5_CONTEXT,
673 * RM_L4PER_TIMER10_CONTEXT, RM_L4PER_TIMER11_CONTEXT, RM_L4PER_TIMER2_CONTEXT,
674 * RM_L4PER_TIMER3_CONTEXT, RM_L4PER_TIMER4_CONTEXT, RM_L4PER_TIMER9_CONTEXT,
675 * RM_L4SEC_FPKA_CONTEXT, RM_MIPIEXT_LLI_CONTEXT,
676 * RM_MIPIEXT_LLI_OCP_FW_CONTEXT, RM_MIPIEXT_MPHY_CONTEXT, RM_MPU_MPU_CONTEXT,
677 * RM_WKUPAON_COUNTER_32K_CONTEXT, RM_WKUPAON_GPIO1_CONTEXT,
678 * RM_WKUPAON_KBD_CONTEXT, RM_WKUPAON_L4_WKUP_CONTEXT,
679 * RM_WKUPAON_SAR_RAM_CONTEXT, RM_WKUPAON_TIMER12_CONTEXT,
680 * RM_WKUPAON_TIMER1_CONTEXT, RM_WKUPAON_WD_TIMER1_CONTEXT,
681 * RM_WKUPAON_WD_TIMER2_CONTEXT
682 */
683#define OMAP54XX_LOSTCONTEXT_DFF_SHIFT 0
684#define OMAP54XX_LOSTCONTEXT_DFF_WIDTH 0x1
685#define OMAP54XX_LOSTCONTEXT_DFF_MASK (1 << 0)
686
687/*
688 * Used by RM_C2C_C2C_CONTEXT, RM_C2C_C2C_OCP_FW_CONTEXT,
689 * RM_C2C_MODEM_ICR_CONTEXT, RM_DMA_DMA_SYSTEM_CONTEXT, RM_DSP_DSP_CONTEXT,
690 * RM_DSS_DSS_CONTEXT, RM_EMIF_DMM_CONTEXT, RM_EMIF_EMIF1_CONTEXT,
691 * RM_EMIF_EMIF2_CONTEXT, RM_EMIF_EMIF_OCP_FW_CONTEXT, RM_IPU_IPU_CONTEXT,
692 * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT,
693 * RM_L3INIT_USB_HOST_HS_CONTEXT, RM_L3INIT_USB_OTG_SS_CONTEXT,
694 * RM_L3INIT_USB_TLL_HS_CONTEXT, RM_L3INSTR_L3_MAIN_3_CONTEXT,
695 * RM_L3INSTR_OCP_WP_NOC_CONTEXT, RM_L3MAIN1_L3_MAIN_1_CONTEXT,
696 * RM_L3MAIN2_GPMC_CONTEXT, RM_L3MAIN2_L3_MAIN_2_CONTEXT,
697 * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_MAILBOX_CONTEXT,
698 * RM_L4CFG_SPINLOCK_CONTEXT, RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT,
699 * RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT,
700 * RM_L4PER_GPIO7_CONTEXT, RM_L4PER_GPIO8_CONTEXT, RM_L4PER_I2C1_CONTEXT,
701 * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT,
702 * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4PER_UART5_CONTEXT,
703 * RM_L4PER_UART6_CONTEXT, RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT,
704 * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_DMA_CRYPTO_CONTEXT, RM_L4SEC_RNG_CONTEXT,
705 * RM_L4SEC_SHA2MD5_CONTEXT, RM_MIPIEXT_LLI_CONTEXT,
706 * RM_MIPIEXT_LLI_OCP_FW_CONTEXT, RM_MIPIEXT_MPHY_CONTEXT, RM_MPU_MPU_CONTEXT
707 */
708#define OMAP54XX_LOSTCONTEXT_RFF_SHIFT 1
709#define OMAP54XX_LOSTCONTEXT_RFF_WIDTH 0x1
710#define OMAP54XX_LOSTCONTEXT_RFF_MASK (1 << 1)
711
712/* Used by RM_ABE_AESS_CONTEXT */
713#define OMAP54XX_LOSTMEM_AESSMEM_SHIFT 8
714#define OMAP54XX_LOSTMEM_AESSMEM_WIDTH 0x1
715#define OMAP54XX_LOSTMEM_AESSMEM_MASK (1 << 8)
716
717/* Used by RM_CAM_CAL_CONTEXT */
718#define OMAP54XX_LOSTMEM_CAL_MEM_SHIFT 8
719#define OMAP54XX_LOSTMEM_CAL_MEM_WIDTH 0x1
720#define OMAP54XX_LOSTMEM_CAL_MEM_MASK (1 << 8)
721
722/* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */
723#define OMAP54XX_LOSTMEM_CAM_MEM_SHIFT 8
724#define OMAP54XX_LOSTMEM_CAM_MEM_WIDTH 0x1
725#define OMAP54XX_LOSTMEM_CAM_MEM_MASK (1 << 8)
726
727/* Used by RM_EMIF_DMM_CONTEXT */
728#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_SHIFT 9
729#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_WIDTH 0x1
730#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_MASK (1 << 9)
731
732/* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_L3INSTR_OCP_WP_NOC_CONTEXT */
733#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_SHIFT 8
734#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_WIDTH 0x1
735#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_MASK (1 << 8)
736
737/* Used by RM_L3MAIN2_OCMC_RAM_CONTEXT */
738#define OMAP54XX_LOSTMEM_CORE_OCMRAM_SHIFT 8
739#define OMAP54XX_LOSTMEM_CORE_OCMRAM_WIDTH 0x1
740#define OMAP54XX_LOSTMEM_CORE_OCMRAM_MASK (1 << 8)
741
742/* Used by RM_DMA_DMA_SYSTEM_CONTEXT, RM_EMIF_DMM_CONTEXT */
743#define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_SHIFT 8
744#define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_WIDTH 0x1
745#define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_MASK (1 << 8)
746
747/* Used by RM_DSP_DSP_CONTEXT */
748#define OMAP54XX_LOSTMEM_DSP_EDMA_SHIFT 10
749#define OMAP54XX_LOSTMEM_DSP_EDMA_WIDTH 0x1
750#define OMAP54XX_LOSTMEM_DSP_EDMA_MASK (1 << 10)
751
752/* Used by RM_DSP_DSP_CONTEXT */
753#define OMAP54XX_LOSTMEM_DSP_L1_SHIFT 8
754#define OMAP54XX_LOSTMEM_DSP_L1_WIDTH 0x1
755#define OMAP54XX_LOSTMEM_DSP_L1_MASK (1 << 8)
756
757/* Used by RM_DSP_DSP_CONTEXT */
758#define OMAP54XX_LOSTMEM_DSP_L2_SHIFT 9
759#define OMAP54XX_LOSTMEM_DSP_L2_WIDTH 0x1
760#define OMAP54XX_LOSTMEM_DSP_L2_MASK (1 << 9)
761
762/* Used by RM_DSS_BB2D_CONTEXT, RM_DSS_DSS_CONTEXT */
763#define OMAP54XX_LOSTMEM_DSS_MEM_SHIFT 8
764#define OMAP54XX_LOSTMEM_DSS_MEM_WIDTH 0x1
765#define OMAP54XX_LOSTMEM_DSS_MEM_MASK (1 << 8)
766
767/* Used by RM_EMU_DEBUGSS_CONTEXT */
768#define OMAP54XX_LOSTMEM_EMU_BANK_SHIFT 8
769#define OMAP54XX_LOSTMEM_EMU_BANK_WIDTH 0x1
770#define OMAP54XX_LOSTMEM_EMU_BANK_MASK (1 << 8)
771
772/* Used by RM_GPU_GPU_CONTEXT */
773#define OMAP54XX_LOSTMEM_GPU_MEM_SHIFT 8
774#define OMAP54XX_LOSTMEM_GPU_MEM_WIDTH 0x1
775#define OMAP54XX_LOSTMEM_GPU_MEM_MASK (1 << 8)
776
777/* Used by RM_IVA_IVA_CONTEXT */
778#define OMAP54XX_LOSTMEM_HWA_MEM_SHIFT 10
779#define OMAP54XX_LOSTMEM_HWA_MEM_WIDTH 0x1
780#define OMAP54XX_LOSTMEM_HWA_MEM_MASK (1 << 10)
781
782/* Used by RM_IPU_IPU_CONTEXT */
783#define OMAP54XX_LOSTMEM_IPU_L2RAM_SHIFT 9
784#define OMAP54XX_LOSTMEM_IPU_L2RAM_WIDTH 0x1
785#define OMAP54XX_LOSTMEM_IPU_L2RAM_MASK (1 << 9)
786
787/* Used by RM_IPU_IPU_CONTEXT */
788#define OMAP54XX_LOSTMEM_IPU_UNICACHE_SHIFT 8
789#define OMAP54XX_LOSTMEM_IPU_UNICACHE_WIDTH 0x1
790#define OMAP54XX_LOSTMEM_IPU_UNICACHE_MASK (1 << 8)
791
792/*
793 * Used by RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT,
794 * RM_L3INIT_MMC2_CONTEXT, RM_L3INIT_SATA_CONTEXT, RM_L3INIT_UNIPRO2_CONTEXT,
795 * RM_L3INIT_USB_OTG_SS_CONTEXT
796 */
797#define OMAP54XX_LOSTMEM_L3INIT_BANK1_SHIFT 8
798#define OMAP54XX_LOSTMEM_L3INIT_BANK1_WIDTH 0x1
799#define OMAP54XX_LOSTMEM_L3INIT_BANK1_MASK (1 << 8)
800
801/* Used by RM_MPU_MPU_CONTEXT */
802#define OMAP54XX_LOSTMEM_MPU_L2_SHIFT 9
803#define OMAP54XX_LOSTMEM_MPU_L2_WIDTH 0x1
804#define OMAP54XX_LOSTMEM_MPU_L2_MASK (1 << 9)
805
806/* Used by RM_MPU_MPU_CONTEXT */
807#define OMAP54XX_LOSTMEM_MPU_RAM_SHIFT 10
808#define OMAP54XX_LOSTMEM_MPU_RAM_WIDTH 0x1
809#define OMAP54XX_LOSTMEM_MPU_RAM_MASK (1 << 10)
810
811/*
812 * Used by RM_L4PER_MMC3_CONTEXT, RM_L4PER_MMC4_CONTEXT, RM_L4PER_MMC5_CONTEXT,
813 * RM_L4SEC_FPKA_CONTEXT
814 */
815#define OMAP54XX_LOSTMEM_NONRETAINED_BANK_SHIFT 8
816#define OMAP54XX_LOSTMEM_NONRETAINED_BANK_WIDTH 0x1
817#define OMAP54XX_LOSTMEM_NONRETAINED_BANK_MASK (1 << 8)
818
819/*
820 * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT,
821 * RM_ABE_MCBSP3_CONTEXT, RM_ABE_MCPDM_CONTEXT, RM_ABE_SLIMBUS1_CONTEXT
822 */
823#define OMAP54XX_LOSTMEM_PERIHPMEM_SHIFT 8
824#define OMAP54XX_LOSTMEM_PERIHPMEM_WIDTH 0x1
825#define OMAP54XX_LOSTMEM_PERIHPMEM_MASK (1 << 8)
826
827/*
828 * Used by RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT,
829 * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4PER_UART5_CONTEXT,
830 * RM_L4PER_UART6_CONTEXT, RM_L4SEC_DMA_CRYPTO_CONTEXT
831 */
832#define OMAP54XX_LOSTMEM_RETAINED_BANK_SHIFT 8
833#define OMAP54XX_LOSTMEM_RETAINED_BANK_WIDTH 0x1
834#define OMAP54XX_LOSTMEM_RETAINED_BANK_MASK (1 << 8)
835
836/* Used by RM_IVA_SL2_CONTEXT */
837#define OMAP54XX_LOSTMEM_SL2_MEM_SHIFT 8
838#define OMAP54XX_LOSTMEM_SL2_MEM_WIDTH 0x1
839#define OMAP54XX_LOSTMEM_SL2_MEM_MASK (1 << 8)
840
841/* Used by RM_IVA_IVA_CONTEXT */
842#define OMAP54XX_LOSTMEM_TCM1_MEM_SHIFT 8
843#define OMAP54XX_LOSTMEM_TCM1_MEM_WIDTH 0x1
844#define OMAP54XX_LOSTMEM_TCM1_MEM_MASK (1 << 8)
845
846/* Used by RM_IVA_IVA_CONTEXT */
847#define OMAP54XX_LOSTMEM_TCM2_MEM_SHIFT 9
848#define OMAP54XX_LOSTMEM_TCM2_MEM_WIDTH 0x1
849#define OMAP54XX_LOSTMEM_TCM2_MEM_MASK (1 << 9)
850
851/* Used by RM_WKUPAON_SAR_RAM_CONTEXT */
852#define OMAP54XX_LOSTMEM_WKUP_BANK_SHIFT 8
853#define OMAP54XX_LOSTMEM_WKUP_BANK_WIDTH 0x1
854#define OMAP54XX_LOSTMEM_WKUP_BANK_MASK (1 << 8)
855
856/*
857 * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CORE_PWRSTCTRL,
858 * PM_CUSTEFUSE_PWRSTCTRL, PM_DSP_PWRSTCTRL, PM_DSS_PWRSTCTRL,
859 * PM_GPU_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_MPU_PWRSTCTRL
860 */
861#define OMAP54XX_LOWPOWERSTATECHANGE_SHIFT 4
862#define OMAP54XX_LOWPOWERSTATECHANGE_WIDTH 0x1
863#define OMAP54XX_LOWPOWERSTATECHANGE_MASK (1 << 4)
864
865/* Used by PRM_DEBUG_TRANS_CFG */
866#define OMAP54XX_MODE_SHIFT 0
867#define OMAP54XX_MODE_WIDTH 0x2
868#define OMAP54XX_MODE_MASK (0x3 << 0)
869
870/* Used by PRM_MODEM_IF_CTRL */
871#define OMAP54XX_MODEM_SHUTDOWN_IRQ_SHIFT 9
872#define OMAP54XX_MODEM_SHUTDOWN_IRQ_WIDTH 0x1
873#define OMAP54XX_MODEM_SHUTDOWN_IRQ_MASK (1 << 9)
874
875/* Used by PRM_MODEM_IF_CTRL */
876#define OMAP54XX_MODEM_WAKE_IRQ_SHIFT 8
877#define OMAP54XX_MODEM_WAKE_IRQ_WIDTH 0x1
878#define OMAP54XX_MODEM_WAKE_IRQ_MASK (1 << 8)
879
880/* Used by PM_MPU_PWRSTCTRL */
881#define OMAP54XX_MPU_L2_ONSTATE_SHIFT 18
882#define OMAP54XX_MPU_L2_ONSTATE_WIDTH 0x2
883#define OMAP54XX_MPU_L2_ONSTATE_MASK (0x3 << 18)
884
885/* Used by PM_MPU_PWRSTCTRL */
886#define OMAP54XX_MPU_L2_RETSTATE_SHIFT 9
887#define OMAP54XX_MPU_L2_RETSTATE_WIDTH 0x1
888#define OMAP54XX_MPU_L2_RETSTATE_MASK (1 << 9)
889
890/* Used by PM_MPU_PWRSTST */
891#define OMAP54XX_MPU_L2_STATEST_SHIFT 6
892#define OMAP54XX_MPU_L2_STATEST_WIDTH 0x2
893#define OMAP54XX_MPU_L2_STATEST_MASK (0x3 << 6)
894
895/* Used by PM_MPU_PWRSTCTRL */
896#define OMAP54XX_MPU_RAM_ONSTATE_SHIFT 20
897#define OMAP54XX_MPU_RAM_ONSTATE_WIDTH 0x2
898#define OMAP54XX_MPU_RAM_ONSTATE_MASK (0x3 << 20)
899
900/* Used by PM_MPU_PWRSTCTRL */
901#define OMAP54XX_MPU_RAM_RETSTATE_SHIFT 10
902#define OMAP54XX_MPU_RAM_RETSTATE_WIDTH 0x1
903#define OMAP54XX_MPU_RAM_RETSTATE_MASK (1 << 10)
904
905/* Used by PM_MPU_PWRSTST */
906#define OMAP54XX_MPU_RAM_STATEST_SHIFT 8
907#define OMAP54XX_MPU_RAM_STATEST_WIDTH 0x2
908#define OMAP54XX_MPU_RAM_STATEST_MASK (0x3 << 8)
909
910/* Used by PRM_RSTST */
911#define OMAP54XX_MPU_SECURITY_VIOL_RST_SHIFT 2
912#define OMAP54XX_MPU_SECURITY_VIOL_RST_WIDTH 0x1
913#define OMAP54XX_MPU_SECURITY_VIOL_RST_MASK (1 << 2)
914
915/* Used by PRM_RSTST */
916#define OMAP54XX_MPU_WDT_RST_SHIFT 3
917#define OMAP54XX_MPU_WDT_RST_WIDTH 0x1
918#define OMAP54XX_MPU_WDT_RST_MASK (1 << 3)
919
920/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */
921#define OMAP54XX_NOCAP_SHIFT 4
922#define OMAP54XX_NOCAP_WIDTH 0x1
923#define OMAP54XX_NOCAP_MASK (1 << 4)
924
925/* Used by PM_CORE_PWRSTCTRL */
926#define OMAP54XX_OCP_NRET_BANK_ONSTATE_SHIFT 24
927#define OMAP54XX_OCP_NRET_BANK_ONSTATE_WIDTH 0x2
928#define OMAP54XX_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24)
929
930/* Used by PM_CORE_PWRSTCTRL */
931#define OMAP54XX_OCP_NRET_BANK_RETSTATE_SHIFT 12
932#define OMAP54XX_OCP_NRET_BANK_RETSTATE_WIDTH 0x1
933#define OMAP54XX_OCP_NRET_BANK_RETSTATE_MASK (1 << 12)
934
935/* Used by PM_CORE_PWRSTST */
936#define OMAP54XX_OCP_NRET_BANK_STATEST_SHIFT 12
937#define OMAP54XX_OCP_NRET_BANK_STATEST_WIDTH 0x2
938#define OMAP54XX_OCP_NRET_BANK_STATEST_MASK (0x3 << 12)
939
940/*
941 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L,
942 * PRM_VC_VAL_CMD_VDD_MPU_L
943 */
944#define OMAP54XX_OFF_SHIFT 0
945#define OMAP54XX_OFF_WIDTH 0x8
946#define OMAP54XX_OFF_MASK (0xff << 0)
947
948/*
949 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L,
950 * PRM_VC_VAL_CMD_VDD_MPU_L
951 */
952#define OMAP54XX_ON_SHIFT 24
953#define OMAP54XX_ON_WIDTH 0x8
954#define OMAP54XX_ON_MASK (0xff << 24)
955
956/*
957 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L,
958 * PRM_VC_VAL_CMD_VDD_MPU_L
959 */
960#define OMAP54XX_ONLP_SHIFT 16
961#define OMAP54XX_ONLP_WIDTH 0x8
962#define OMAP54XX_ONLP_MASK (0xff << 16)
963
964/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */
965#define OMAP54XX_OPP_CHANGE_SHIFT 2
966#define OMAP54XX_OPP_CHANGE_WIDTH 0x1
967#define OMAP54XX_OPP_CHANGE_MASK (1 << 2)
968
969/* Used by PRM_VC_VAL_BYPASS */
970#define OMAP54XX_OPP_CHANGE_EMIF_LVL_SHIFT 25
971#define OMAP54XX_OPP_CHANGE_EMIF_LVL_WIDTH 0x1
972#define OMAP54XX_OPP_CHANGE_EMIF_LVL_MASK (1 << 25)
973
974/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */
975#define OMAP54XX_OPP_SEL_SHIFT 0
976#define OMAP54XX_OPP_SEL_WIDTH 0x2
977#define OMAP54XX_OPP_SEL_MASK (0x3 << 0)
978
979/* Used by PRM_DEBUG_OUT */
980#define OMAP54XX_OUTPUT_SHIFT 0
981#define OMAP54XX_OUTPUT_WIDTH 0x20
982#define OMAP54XX_OUTPUT_MASK (0xffffffff << 0)
983
984/* Used by PRM_SRAM_COUNT */
985#define OMAP54XX_PCHARGECNT_VALUE_SHIFT 0
986#define OMAP54XX_PCHARGECNT_VALUE_WIDTH 0x6
987#define OMAP54XX_PCHARGECNT_VALUE_MASK (0x3f << 0)
988
989/* Used by PRM_PSCON_COUNT */
990#define OMAP54XX_PCHARGE_TIME_SHIFT 0
991#define OMAP54XX_PCHARGE_TIME_WIDTH 0x8
992#define OMAP54XX_PCHARGE_TIME_MASK (0xff << 0)
993
994/* Used by PM_ABE_PWRSTCTRL */
995#define OMAP54XX_PERIPHMEM_ONSTATE_SHIFT 20
996#define OMAP54XX_PERIPHMEM_ONSTATE_WIDTH 0x2
997#define OMAP54XX_PERIPHMEM_ONSTATE_MASK (0x3 << 20)
998
999/* Used by PM_ABE_PWRSTCTRL */
1000#define OMAP54XX_PERIPHMEM_RETSTATE_SHIFT 10
1001#define OMAP54XX_PERIPHMEM_RETSTATE_WIDTH 0x1
1002#define OMAP54XX_PERIPHMEM_RETSTATE_MASK (1 << 10)
1003
1004/* Used by PM_ABE_PWRSTST */
1005#define OMAP54XX_PERIPHMEM_STATEST_SHIFT 8
1006#define OMAP54XX_PERIPHMEM_STATEST_WIDTH 0x2
1007#define OMAP54XX_PERIPHMEM_STATEST_MASK (0x3 << 8)
1008
1009/* Used by PRM_PHASE1_CNDP */
1010#define OMAP54XX_PHASE1_CNDP_SHIFT 0
1011#define OMAP54XX_PHASE1_CNDP_WIDTH 0x20
1012#define OMAP54XX_PHASE1_CNDP_MASK (0xffffffff << 0)
1013
1014/* Used by PRM_PHASE2A_CNDP */
1015#define OMAP54XX_PHASE2A_CNDP_SHIFT 0
1016#define OMAP54XX_PHASE2A_CNDP_WIDTH 0x20
1017#define OMAP54XX_PHASE2A_CNDP_MASK (0xffffffff << 0)
1018
1019/* Used by PRM_PHASE2B_CNDP */
1020#define OMAP54XX_PHASE2B_CNDP_SHIFT 0
1021#define OMAP54XX_PHASE2B_CNDP_WIDTH 0x20
1022#define OMAP54XX_PHASE2B_CNDP_MASK (0xffffffff << 0)
1023
1024/* Used by PRM_PSCON_COUNT */
1025#define OMAP54XX_PONOUT_2_PGOODIN_TIME_SHIFT 8
1026#define OMAP54XX_PONOUT_2_PGOODIN_TIME_WIDTH 0x8
1027#define OMAP54XX_PONOUT_2_PGOODIN_TIME_MASK (0xff << 8)
1028
1029/*
1030 * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CORE_PWRSTCTRL,
1031 * PM_CUSTEFUSE_PWRSTCTRL, PM_DSP_PWRSTCTRL, PM_DSS_PWRSTCTRL,
1032 * PM_EMU_PWRSTCTRL, PM_GPU_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL,
1033 * PM_MPU_PWRSTCTRL
1034 */
1035#define OMAP54XX_POWERSTATE_SHIFT 0
1036#define OMAP54XX_POWERSTATE_WIDTH 0x2
1037#define OMAP54XX_POWERSTATE_MASK (0x3 << 0)
1038
1039/*
1040 * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST,
1041 * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
1042 * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST
1043 */
1044#define OMAP54XX_POWERSTATEST_SHIFT 0
1045#define OMAP54XX_POWERSTATEST_WIDTH 0x2
1046#define OMAP54XX_POWERSTATEST_MASK (0x3 << 0)
1047
1048/* Used by PRM_PWRREQCTRL */
1049#define OMAP54XX_PWRREQ_COND_SHIFT 0
1050#define OMAP54XX_PWRREQ_COND_WIDTH 0x2
1051#define OMAP54XX_PWRREQ_COND_MASK (0x3 << 0)
1052
1053/* Used by PRM_VC_SMPS_CORE_CONFIG */
1054#define OMAP54XX_RACEN_VDD_CORE_L_SHIFT 27
1055#define OMAP54XX_RACEN_VDD_CORE_L_WIDTH 0x1
1056#define OMAP54XX_RACEN_VDD_CORE_L_MASK (1 << 27)
1057
1058/* Used by PRM_VC_SMPS_MM_CONFIG */
1059#define OMAP54XX_RACEN_VDD_MM_L_SHIFT 27
1060#define OMAP54XX_RACEN_VDD_MM_L_WIDTH 0x1
1061#define OMAP54XX_RACEN_VDD_MM_L_MASK (1 << 27)
1062
1063/* Used by PRM_VC_SMPS_MPU_CONFIG */
1064#define OMAP54XX_RACEN_VDD_MPU_L_SHIFT 27
1065#define OMAP54XX_RACEN_VDD_MPU_L_WIDTH 0x1
1066#define OMAP54XX_RACEN_VDD_MPU_L_MASK (1 << 27)
1067
1068/* Used by PRM_VC_SMPS_CORE_CONFIG */
1069#define OMAP54XX_RAC_VDD_CORE_L_SHIFT 26
1070#define OMAP54XX_RAC_VDD_CORE_L_WIDTH 0x1
1071#define OMAP54XX_RAC_VDD_CORE_L_MASK (1 << 26)
1072
1073/* Used by PRM_VC_SMPS_MM_CONFIG */
1074#define OMAP54XX_RAC_VDD_MM_L_SHIFT 26
1075#define OMAP54XX_RAC_VDD_MM_L_WIDTH 0x1
1076#define OMAP54XX_RAC_VDD_MM_L_MASK (1 << 26)
1077
1078/* Used by PRM_VC_SMPS_MPU_CONFIG */
1079#define OMAP54XX_RAC_VDD_MPU_L_SHIFT 26
1080#define OMAP54XX_RAC_VDD_MPU_L_WIDTH 0x1
1081#define OMAP54XX_RAC_VDD_MPU_L_MASK (1 << 26)
1082
1083/*
1084 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
1085 * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
1086 * PRM_VOLTSETUP_MPU_RET_SLEEP
1087 */
1088#define OMAP54XX_RAMP_DOWN_COUNT_SHIFT 16
1089#define OMAP54XX_RAMP_DOWN_COUNT_WIDTH 0x6
1090#define OMAP54XX_RAMP_DOWN_COUNT_MASK (0x3f << 16)
1091
1092/*
1093 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
1094 * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
1095 * PRM_VOLTSETUP_MPU_RET_SLEEP
1096 */
1097#define OMAP54XX_RAMP_DOWN_PRESCAL_SHIFT 24
1098#define OMAP54XX_RAMP_DOWN_PRESCAL_WIDTH 0x2
1099#define OMAP54XX_RAMP_DOWN_PRESCAL_MASK (0x3 << 24)
1100
1101/*
1102 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
1103 * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
1104 * PRM_VOLTSETUP_MPU_RET_SLEEP
1105 */
1106#define OMAP54XX_RAMP_UP_COUNT_SHIFT 0
1107#define OMAP54XX_RAMP_UP_COUNT_WIDTH 0x6
1108#define OMAP54XX_RAMP_UP_COUNT_MASK (0x3f << 0)
1109
1110/*
1111 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
1112 * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
1113 * PRM_VOLTSETUP_MPU_RET_SLEEP
1114 */
1115#define OMAP54XX_RAMP_UP_PRESCAL_SHIFT 8
1116#define OMAP54XX_RAMP_UP_PRESCAL_WIDTH 0x2
1117#define OMAP54XX_RAMP_UP_PRESCAL_MASK (0x3 << 8)
1118
1119/* Used by PRM_VC_SMPS_CORE_CONFIG */
1120#define OMAP54XX_RAV_VDD_CORE_L_SHIFT 25
1121#define OMAP54XX_RAV_VDD_CORE_L_WIDTH 0x1
1122#define OMAP54XX_RAV_VDD_CORE_L_MASK (1 << 25)
1123
1124/* Used by PRM_VC_SMPS_MM_CONFIG */
1125#define OMAP54XX_RAV_VDD_MM_L_SHIFT 25
1126#define OMAP54XX_RAV_VDD_MM_L_WIDTH 0x1
1127#define OMAP54XX_RAV_VDD_MM_L_MASK (1 << 25)
1128
1129/* Used by PRM_VC_SMPS_MPU_CONFIG */
1130#define OMAP54XX_RAV_VDD_MPU_L_SHIFT 25
1131#define OMAP54XX_RAV_VDD_MPU_L_WIDTH 0x1
1132#define OMAP54XX_RAV_VDD_MPU_L_MASK (1 << 25)
1133
1134/* Used by PRM_VC_VAL_BYPASS */
1135#define OMAP54XX_REGADDR_SHIFT 8
1136#define OMAP54XX_REGADDR_WIDTH 0x8
1137#define OMAP54XX_REGADDR_MASK (0xff << 8)
1138
1139/*
1140 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L,
1141 * PRM_VC_VAL_CMD_VDD_MPU_L
1142 */
1143#define OMAP54XX_RET_SHIFT 8
1144#define OMAP54XX_RET_WIDTH 0x8
1145#define OMAP54XX_RET_MASK (0xff << 8)
1146
1147/* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */
1148#define OMAP54XX_RETMODE_ENABLE_SHIFT 0
1149#define OMAP54XX_RETMODE_ENABLE_WIDTH 0x1
1150#define OMAP54XX_RETMODE_ENABLE_MASK (1 << 0)
1151
1152/* Used by PRM_RSTTIME */
1153#define OMAP54XX_RSTTIME1_SHIFT 0
1154#define OMAP54XX_RSTTIME1_WIDTH 0xa
1155#define OMAP54XX_RSTTIME1_MASK (0x3ff << 0)
1156
1157/* Used by PRM_RSTTIME */
1158#define OMAP54XX_RSTTIME2_SHIFT 10
1159#define OMAP54XX_RSTTIME2_WIDTH 0x5
1160#define OMAP54XX_RSTTIME2_MASK (0x1f << 10)
1161
1162/* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */
1163#define OMAP54XX_RST_CPU0_SHIFT 0
1164#define OMAP54XX_RST_CPU0_WIDTH 0x1
1165#define OMAP54XX_RST_CPU0_MASK (1 << 0)
1166
1167/* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */
1168#define OMAP54XX_RST_CPU1_SHIFT 1
1169#define OMAP54XX_RST_CPU1_WIDTH 0x1
1170#define OMAP54XX_RST_CPU1_MASK (1 << 1)
1171
1172/* Used by RM_DSP_RSTCTRL, RM_DSP_RSTST */
1173#define OMAP54XX_RST_DSP_SHIFT 0
1174#define OMAP54XX_RST_DSP_WIDTH 0x1
1175#define OMAP54XX_RST_DSP_MASK (1 << 0)
1176
1177/* Used by RM_DSP_RSTST */
1178#define OMAP54XX_RST_DSP_EMU_SHIFT 2
1179#define OMAP54XX_RST_DSP_EMU_WIDTH 0x1
1180#define OMAP54XX_RST_DSP_EMU_MASK (1 << 2)
1181
1182/* Used by RM_DSP_RSTST */
1183#define OMAP54XX_RST_DSP_EMU_REQ_SHIFT 3
1184#define OMAP54XX_RST_DSP_EMU_REQ_WIDTH 0x1
1185#define OMAP54XX_RST_DSP_EMU_REQ_MASK (1 << 3)
1186
1187/* Used by RM_DSP_RSTCTRL, RM_DSP_RSTST */
1188#define OMAP54XX_RST_DSP_MMU_CACHE_SHIFT 1
1189#define OMAP54XX_RST_DSP_MMU_CACHE_WIDTH 0x1
1190#define OMAP54XX_RST_DSP_MMU_CACHE_MASK (1 << 1)
1191
1192/* Used by RM_IPU_RSTST */
1193#define OMAP54XX_RST_EMULATION_CPU0_SHIFT 3
1194#define OMAP54XX_RST_EMULATION_CPU0_WIDTH 0x1
1195#define OMAP54XX_RST_EMULATION_CPU0_MASK (1 << 3)
1196
1197/* Used by RM_IPU_RSTST */
1198#define OMAP54XX_RST_EMULATION_CPU1_SHIFT 4
1199#define OMAP54XX_RST_EMULATION_CPU1_WIDTH 0x1
1200#define OMAP54XX_RST_EMULATION_CPU1_MASK (1 << 4)
1201
1202/* Used by RM_IVA_RSTST */
1203#define OMAP54XX_RST_EMULATION_SEQ1_SHIFT 3
1204#define OMAP54XX_RST_EMULATION_SEQ1_WIDTH 0x1
1205#define OMAP54XX_RST_EMULATION_SEQ1_MASK (1 << 3)
1206
1207/* Used by RM_IVA_RSTST */
1208#define OMAP54XX_RST_EMULATION_SEQ2_SHIFT 4
1209#define OMAP54XX_RST_EMULATION_SEQ2_WIDTH 0x1
1210#define OMAP54XX_RST_EMULATION_SEQ2_MASK (1 << 4)
1211
1212/* Used by PRM_RSTCTRL */
1213#define OMAP54XX_RST_GLOBAL_COLD_SW_SHIFT 1
1214#define OMAP54XX_RST_GLOBAL_COLD_SW_WIDTH 0x1
1215#define OMAP54XX_RST_GLOBAL_COLD_SW_MASK (1 << 1)
1216
1217/* Used by PRM_RSTCTRL */
1218#define OMAP54XX_RST_GLOBAL_WARM_SW_SHIFT 0
1219#define OMAP54XX_RST_GLOBAL_WARM_SW_WIDTH 0x1
1220#define OMAP54XX_RST_GLOBAL_WARM_SW_MASK (1 << 0)
1221
1222/* Used by RM_IPU_RSTST */
1223#define OMAP54XX_RST_ICECRUSHER_CPU0_SHIFT 5
1224#define OMAP54XX_RST_ICECRUSHER_CPU0_WIDTH 0x1
1225#define OMAP54XX_RST_ICECRUSHER_CPU0_MASK (1 << 5)
1226
1227/* Used by RM_IPU_RSTST */
1228#define OMAP54XX_RST_ICECRUSHER_CPU1_SHIFT 6
1229#define OMAP54XX_RST_ICECRUSHER_CPU1_WIDTH 0x1
1230#define OMAP54XX_RST_ICECRUSHER_CPU1_MASK (1 << 6)
1231
1232/* Used by RM_IVA_RSTST */
1233#define OMAP54XX_RST_ICECRUSHER_SEQ1_SHIFT 5
1234#define OMAP54XX_RST_ICECRUSHER_SEQ1_WIDTH 0x1
1235#define OMAP54XX_RST_ICECRUSHER_SEQ1_MASK (1 << 5)
1236
1237/* Used by RM_IVA_RSTST */
1238#define OMAP54XX_RST_ICECRUSHER_SEQ2_SHIFT 6
1239#define OMAP54XX_RST_ICECRUSHER_SEQ2_WIDTH 0x1
1240#define OMAP54XX_RST_ICECRUSHER_SEQ2_MASK (1 << 6)
1241
1242/* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */
1243#define OMAP54XX_RST_IPU_MMU_CACHE_SHIFT 2
1244#define OMAP54XX_RST_IPU_MMU_CACHE_WIDTH 0x1
1245#define OMAP54XX_RST_IPU_MMU_CACHE_MASK (1 << 2)
1246
1247/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */
1248#define OMAP54XX_RST_LOGIC_SHIFT 2
1249#define OMAP54XX_RST_LOGIC_WIDTH 0x1
1250#define OMAP54XX_RST_LOGIC_MASK (1 << 2)
1251
1252/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */
1253#define OMAP54XX_RST_SEQ1_SHIFT 0
1254#define OMAP54XX_RST_SEQ1_WIDTH 0x1
1255#define OMAP54XX_RST_SEQ1_MASK (1 << 0)
1256
1257/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */
1258#define OMAP54XX_RST_SEQ2_SHIFT 1
1259#define OMAP54XX_RST_SEQ2_WIDTH 0x1
1260#define OMAP54XX_RST_SEQ2_MASK (1 << 1)
1261
1262/* Used by REVISION_PRM */
1263#define OMAP54XX_R_RTL_SHIFT 11
1264#define OMAP54XX_R_RTL_WIDTH 0x5
1265#define OMAP54XX_R_RTL_MASK (0x1f << 11)
1266
1267/* Used by PRM_VC_SMPS_CORE_CONFIG */
1268#define OMAP54XX_SA_VDD_CORE_L_SHIFT 0
1269#define OMAP54XX_SA_VDD_CORE_L_WIDTH 0x7
1270#define OMAP54XX_SA_VDD_CORE_L_MASK (0x7f << 0)
1271
1272/* Used by PRM_VC_SMPS_MM_CONFIG */
1273#define OMAP54XX_SA_VDD_MM_L_SHIFT 0
1274#define OMAP54XX_SA_VDD_MM_L_WIDTH 0x7
1275#define OMAP54XX_SA_VDD_MM_L_MASK (0x7f << 0)
1276
1277/* Used by PRM_VC_SMPS_MPU_CONFIG */
1278#define OMAP54XX_SA_VDD_MPU_L_SHIFT 0
1279#define OMAP54XX_SA_VDD_MPU_L_WIDTH 0x7
1280#define OMAP54XX_SA_VDD_MPU_L_MASK (0x7f << 0)
1281
1282/* Used by REVISION_PRM */
1283#define OMAP54XX_SCHEME_SHIFT 30
1284#define OMAP54XX_SCHEME_WIDTH 0x2
1285#define OMAP54XX_SCHEME_MASK (0x3 << 30)
1286
1287/* Used by PRM_VC_CFG_I2C_CLK */
1288#define OMAP54XX_SCLH_SHIFT 0
1289#define OMAP54XX_SCLH_WIDTH 0x8
1290#define OMAP54XX_SCLH_MASK (0xff << 0)
1291
1292/* Used by PRM_VC_CFG_I2C_CLK */
1293#define OMAP54XX_SCLL_SHIFT 8
1294#define OMAP54XX_SCLL_WIDTH 0x8
1295#define OMAP54XX_SCLL_MASK (0xff << 8)
1296
1297/* Used by PRM_RSTST */
1298#define OMAP54XX_SECURE_WDT_RST_SHIFT 4
1299#define OMAP54XX_SECURE_WDT_RST_WIDTH 0x1
1300#define OMAP54XX_SECURE_WDT_RST_MASK (1 << 4)
1301
1302/* Used by PRM_VC_SMPS_CORE_CONFIG */
1303#define OMAP54XX_SEL_SA_VDD_CORE_L_SHIFT 24
1304#define OMAP54XX_SEL_SA_VDD_CORE_L_WIDTH 0x1
1305#define OMAP54XX_SEL_SA_VDD_CORE_L_MASK (1 << 24)
1306
1307/* Used by PRM_VC_SMPS_MM_CONFIG */
1308#define OMAP54XX_SEL_SA_VDD_MM_L_SHIFT 24
1309#define OMAP54XX_SEL_SA_VDD_MM_L_WIDTH 0x1
1310#define OMAP54XX_SEL_SA_VDD_MM_L_MASK (1 << 24)
1311
1312/* Used by PRM_VC_SMPS_MPU_CONFIG */
1313#define OMAP54XX_SEL_SA_VDD_MPU_L_SHIFT 24
1314#define OMAP54XX_SEL_SA_VDD_MPU_L_WIDTH 0x1
1315#define OMAP54XX_SEL_SA_VDD_MPU_L_MASK (1 << 24)
1316
1317/* Used by PM_IVA_PWRSTCTRL */
1318#define OMAP54XX_SL2_MEM_ONSTATE_SHIFT 18
1319#define OMAP54XX_SL2_MEM_ONSTATE_WIDTH 0x2
1320#define OMAP54XX_SL2_MEM_ONSTATE_MASK (0x3 << 18)
1321
1322/* Used by PM_IVA_PWRSTCTRL */
1323#define OMAP54XX_SL2_MEM_RETSTATE_SHIFT 9
1324#define OMAP54XX_SL2_MEM_RETSTATE_WIDTH 0x1
1325#define OMAP54XX_SL2_MEM_RETSTATE_MASK (1 << 9)
1326
1327/* Used by PM_IVA_PWRSTST */
1328#define OMAP54XX_SL2_MEM_STATEST_SHIFT 6
1329#define OMAP54XX_SL2_MEM_STATEST_WIDTH 0x2
1330#define OMAP54XX_SL2_MEM_STATEST_MASK (0x3 << 6)
1331
1332/* Used by PRM_VC_VAL_BYPASS */
1333#define OMAP54XX_SLAVEADDR_SHIFT 0
1334#define OMAP54XX_SLAVEADDR_WIDTH 0x7
1335#define OMAP54XX_SLAVEADDR_MASK (0x7f << 0)
1336
1337/* Used by PRM_SRAM_COUNT */
1338#define OMAP54XX_SLPCNT_VALUE_SHIFT 16
1339#define OMAP54XX_SLPCNT_VALUE_WIDTH 0x8
1340#define OMAP54XX_SLPCNT_VALUE_MASK (0xff << 16)
1341
1342/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_MM_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
1343#define OMAP54XX_SMPSWAITTIMEMAX_SHIFT 8
1344#define OMAP54XX_SMPSWAITTIMEMAX_WIDTH 0x10
1345#define OMAP54XX_SMPSWAITTIMEMAX_MASK (0xffff << 8)
1346
1347/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_MM_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
1348#define OMAP54XX_SMPSWAITTIMEMIN_SHIFT 8
1349#define OMAP54XX_SMPSWAITTIMEMIN_WIDTH 0x10
1350#define OMAP54XX_SMPSWAITTIMEMIN_MASK (0xffff << 8)
1351
1352/* Used by PRM_VC_CORE_ERRST */
1353#define OMAP54XX_SMPS_RA_ERR_CORE_SHIFT 1
1354#define OMAP54XX_SMPS_RA_ERR_CORE_WIDTH 0x1
1355#define OMAP54XX_SMPS_RA_ERR_CORE_MASK (1 << 1)
1356
1357/* Used by PRM_VC_MM_ERRST */
1358#define OMAP54XX_SMPS_RA_ERR_MM_SHIFT 1
1359#define OMAP54XX_SMPS_RA_ERR_MM_WIDTH 0x1
1360#define OMAP54XX_SMPS_RA_ERR_MM_MASK (1 << 1)
1361
1362/* Used by PRM_VC_MPU_ERRST */
1363#define OMAP54XX_SMPS_RA_ERR_MPU_SHIFT 1
1364#define OMAP54XX_SMPS_RA_ERR_MPU_WIDTH 0x1
1365#define OMAP54XX_SMPS_RA_ERR_MPU_MASK (1 << 1)
1366
1367/* Used by PRM_VC_CORE_ERRST */
1368#define OMAP54XX_SMPS_SA_ERR_CORE_SHIFT 0
1369#define OMAP54XX_SMPS_SA_ERR_CORE_WIDTH 0x1
1370#define OMAP54XX_SMPS_SA_ERR_CORE_MASK (1 << 0)
1371
1372/* Used by PRM_VC_MM_ERRST */
1373#define OMAP54XX_SMPS_SA_ERR_MM_SHIFT 0
1374#define OMAP54XX_SMPS_SA_ERR_MM_WIDTH 0x1
1375#define OMAP54XX_SMPS_SA_ERR_MM_MASK (1 << 0)
1376
1377/* Used by PRM_VC_MPU_ERRST */
1378#define OMAP54XX_SMPS_SA_ERR_MPU_SHIFT 0
1379#define OMAP54XX_SMPS_SA_ERR_MPU_WIDTH 0x1
1380#define OMAP54XX_SMPS_SA_ERR_MPU_MASK (1 << 0)
1381
1382/* Used by PRM_VC_CORE_ERRST */
1383#define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_SHIFT 2
1384#define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_WIDTH 0x1
1385#define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_MASK (1 << 2)
1386
1387/* Used by PRM_VC_MM_ERRST */
1388#define OMAP54XX_SMPS_TIMEOUT_ERR_MM_SHIFT 2
1389#define OMAP54XX_SMPS_TIMEOUT_ERR_MM_WIDTH 0x1
1390#define OMAP54XX_SMPS_TIMEOUT_ERR_MM_MASK (1 << 2)
1391
1392/* Used by PRM_VC_MPU_ERRST */
1393#define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_SHIFT 2
1394#define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_WIDTH 0x1
1395#define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_MASK (1 << 2)
1396
1397/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */
1398#define OMAP54XX_SR2EN_SHIFT 0
1399#define OMAP54XX_SR2EN_WIDTH 0x1
1400#define OMAP54XX_SR2EN_MASK (1 << 0)
1401
1402/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */
1403#define OMAP54XX_SR2_IN_TRANSITION_SHIFT 6
1404#define OMAP54XX_SR2_IN_TRANSITION_WIDTH 0x1
1405#define OMAP54XX_SR2_IN_TRANSITION_MASK (1 << 6)
1406
1407/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */
1408#define OMAP54XX_SR2_STATUS_SHIFT 3
1409#define OMAP54XX_SR2_STATUS_WIDTH 0x2
1410#define OMAP54XX_SR2_STATUS_MASK (0x3 << 3)
1411
1412/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */
1413#define OMAP54XX_SR2_WTCNT_VALUE_SHIFT 8
1414#define OMAP54XX_SR2_WTCNT_VALUE_WIDTH 0x8
1415#define OMAP54XX_SR2_WTCNT_VALUE_MASK (0xff << 8)
1416
1417/* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */
1418#define OMAP54XX_SRAMLDO_STATUS_SHIFT 8
1419#define OMAP54XX_SRAMLDO_STATUS_WIDTH 0x1
1420#define OMAP54XX_SRAMLDO_STATUS_MASK (1 << 8)
1421
1422/* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */
1423#define OMAP54XX_SRAM_IN_TRANSITION_SHIFT 9
1424#define OMAP54XX_SRAM_IN_TRANSITION_WIDTH 0x1
1425#define OMAP54XX_SRAM_IN_TRANSITION_MASK (1 << 9)
1426
1427/* Used by PRM_VC_CFG_I2C_MODE */
1428#define OMAP54XX_SRMODEEN_SHIFT 4
1429#define OMAP54XX_SRMODEEN_WIDTH 0x1
1430#define OMAP54XX_SRMODEEN_MASK (1 << 4)
1431
1432/* Used by PRM_VOLTSETUP_WARMRESET */
1433#define OMAP54XX_STABLE_COUNT_SHIFT 0
1434#define OMAP54XX_STABLE_COUNT_WIDTH 0x6
1435#define OMAP54XX_STABLE_COUNT_MASK (0x3f << 0)
1436
1437/* Used by PRM_VOLTSETUP_WARMRESET */
1438#define OMAP54XX_STABLE_PRESCAL_SHIFT 8
1439#define OMAP54XX_STABLE_PRESCAL_WIDTH 0x2
1440#define OMAP54XX_STABLE_PRESCAL_MASK (0x3 << 8)
1441
1442/* Used by PRM_BANDGAP_SETUP */
1443#define OMAP54XX_STARTUP_COUNT_SHIFT 0
1444#define OMAP54XX_STARTUP_COUNT_WIDTH 0x8
1445#define OMAP54XX_STARTUP_COUNT_MASK (0xff << 0)
1446
1447/* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */
1448#define OMAP54XX_STARTUP_COUNT_24_31_SHIFT 24
1449#define OMAP54XX_STARTUP_COUNT_24_31_WIDTH 0x8
1450#define OMAP54XX_STARTUP_COUNT_24_31_MASK (0xff << 24)
1451
1452/* Used by PM_IVA_PWRSTCTRL */
1453#define OMAP54XX_TCM1_MEM_ONSTATE_SHIFT 20
1454#define OMAP54XX_TCM1_MEM_ONSTATE_WIDTH 0x2
1455#define OMAP54XX_TCM1_MEM_ONSTATE_MASK (0x3 << 20)
1456
1457/* Used by PM_IVA_PWRSTCTRL */
1458#define OMAP54XX_TCM1_MEM_RETSTATE_SHIFT 10
1459#define OMAP54XX_TCM1_MEM_RETSTATE_WIDTH 0x1
1460#define OMAP54XX_TCM1_MEM_RETSTATE_MASK (1 << 10)
1461
1462/* Used by PM_IVA_PWRSTST */
1463#define OMAP54XX_TCM1_MEM_STATEST_SHIFT 8
1464#define OMAP54XX_TCM1_MEM_STATEST_WIDTH 0x2
1465#define OMAP54XX_TCM1_MEM_STATEST_MASK (0x3 << 8)
1466
1467/* Used by PM_IVA_PWRSTCTRL */
1468#define OMAP54XX_TCM2_MEM_ONSTATE_SHIFT 22
1469#define OMAP54XX_TCM2_MEM_ONSTATE_WIDTH 0x2
1470#define OMAP54XX_TCM2_MEM_ONSTATE_MASK (0x3 << 22)
1471
1472/* Used by PM_IVA_PWRSTCTRL */
1473#define OMAP54XX_TCM2_MEM_RETSTATE_SHIFT 11
1474#define OMAP54XX_TCM2_MEM_RETSTATE_WIDTH 0x1
1475#define OMAP54XX_TCM2_MEM_RETSTATE_MASK (1 << 11)
1476
1477/* Used by PM_IVA_PWRSTST */
1478#define OMAP54XX_TCM2_MEM_STATEST_SHIFT 10
1479#define OMAP54XX_TCM2_MEM_STATEST_WIDTH 0x2
1480#define OMAP54XX_TCM2_MEM_STATEST_MASK (0x3 << 10)
1481
1482/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */
1483#define OMAP54XX_TIMEOUT_SHIFT 0
1484#define OMAP54XX_TIMEOUT_WIDTH 0x10
1485#define OMAP54XX_TIMEOUT_MASK (0xffff << 0)
1486
1487/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
1488#define OMAP54XX_TIMEOUTEN_SHIFT 3
1489#define OMAP54XX_TIMEOUTEN_WIDTH 0x1
1490#define OMAP54XX_TIMEOUTEN_MASK (1 << 3)
1491
1492/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1493#define OMAP54XX_TRANSITION_EN_SHIFT 8
1494#define OMAP54XX_TRANSITION_EN_WIDTH 0x1
1495#define OMAP54XX_TRANSITION_EN_MASK (1 << 8)
1496
1497/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1498#define OMAP54XX_TRANSITION_ST_SHIFT 8
1499#define OMAP54XX_TRANSITION_ST_WIDTH 0x1
1500#define OMAP54XX_TRANSITION_ST_MASK (1 << 8)
1501
1502/* Used by PRM_DEBUG_TRANS_CFG */
1503#define OMAP54XX_TRIGGER_CLEAR_SHIFT 2
1504#define OMAP54XX_TRIGGER_CLEAR_WIDTH 0x1
1505#define OMAP54XX_TRIGGER_CLEAR_MASK (1 << 2)
1506
1507/* Used by PRM_RSTST */
1508#define OMAP54XX_TSHUT_CORE_RST_SHIFT 13
1509#define OMAP54XX_TSHUT_CORE_RST_WIDTH 0x1
1510#define OMAP54XX_TSHUT_CORE_RST_MASK (1 << 13)
1511
1512/* Used by PRM_RSTST */
1513#define OMAP54XX_TSHUT_MM_RST_SHIFT 12
1514#define OMAP54XX_TSHUT_MM_RST_WIDTH 0x1
1515#define OMAP54XX_TSHUT_MM_RST_MASK (1 << 12)
1516
1517/* Used by PRM_RSTST */
1518#define OMAP54XX_TSHUT_MPU_RST_SHIFT 11
1519#define OMAP54XX_TSHUT_MPU_RST_WIDTH 0x1
1520#define OMAP54XX_TSHUT_MPU_RST_MASK (1 << 11)
1521
1522/* Used by PRM_VC_VAL_BYPASS */
1523#define OMAP54XX_VALID_SHIFT 24
1524#define OMAP54XX_VALID_WIDTH 0x1
1525#define OMAP54XX_VALID_MASK (1 << 24)
1526
1527/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1528#define OMAP54XX_VC_BYPASSACK_EN_SHIFT 14
1529#define OMAP54XX_VC_BYPASSACK_EN_WIDTH 0x1
1530#define OMAP54XX_VC_BYPASSACK_EN_MASK (1 << 14)
1531
1532/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1533#define OMAP54XX_VC_BYPASSACK_ST_SHIFT 14
1534#define OMAP54XX_VC_BYPASSACK_ST_WIDTH 0x1
1535#define OMAP54XX_VC_BYPASSACK_ST_MASK (1 << 14)
1536
1537/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1538#define OMAP54XX_VC_CORE_VPACK_EN_SHIFT 22
1539#define OMAP54XX_VC_CORE_VPACK_EN_WIDTH 0x1
1540#define OMAP54XX_VC_CORE_VPACK_EN_MASK (1 << 22)
1541
1542/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1543#define OMAP54XX_VC_CORE_VPACK_ST_SHIFT 22
1544#define OMAP54XX_VC_CORE_VPACK_ST_WIDTH 0x1
1545#define OMAP54XX_VC_CORE_VPACK_ST_MASK (1 << 22)
1546
1547/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1548#define OMAP54XX_VC_MM_VPACK_EN_SHIFT 30
1549#define OMAP54XX_VC_MM_VPACK_EN_WIDTH 0x1
1550#define OMAP54XX_VC_MM_VPACK_EN_MASK (1 << 30)
1551
1552/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1553#define OMAP54XX_VC_MM_VPACK_ST_SHIFT 30
1554#define OMAP54XX_VC_MM_VPACK_ST_WIDTH 0x1
1555#define OMAP54XX_VC_MM_VPACK_ST_MASK (1 << 30)
1556
1557/* Used by PRM_IRQENABLE_MPU_2 */
1558#define OMAP54XX_VC_MPU_VPACK_EN_SHIFT 6
1559#define OMAP54XX_VC_MPU_VPACK_EN_WIDTH 0x1
1560#define OMAP54XX_VC_MPU_VPACK_EN_MASK (1 << 6)
1561
1562/* Used by PRM_IRQSTATUS_MPU_2 */
1563#define OMAP54XX_VC_MPU_VPACK_ST_SHIFT 6
1564#define OMAP54XX_VC_MPU_VPACK_ST_WIDTH 0x1
1565#define OMAP54XX_VC_MPU_VPACK_ST_MASK (1 << 6)
1566
1567/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1568#define OMAP54XX_VC_RAERR_EN_SHIFT 12
1569#define OMAP54XX_VC_RAERR_EN_WIDTH 0x1
1570#define OMAP54XX_VC_RAERR_EN_MASK (1 << 12)
1571
1572/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1573#define OMAP54XX_VC_RAERR_ST_SHIFT 12
1574#define OMAP54XX_VC_RAERR_ST_WIDTH 0x1
1575#define OMAP54XX_VC_RAERR_ST_MASK (1 << 12)
1576
1577/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1578#define OMAP54XX_VC_SAERR_EN_SHIFT 11
1579#define OMAP54XX_VC_SAERR_EN_WIDTH 0x1
1580#define OMAP54XX_VC_SAERR_EN_MASK (1 << 11)
1581
1582/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1583#define OMAP54XX_VC_SAERR_ST_SHIFT 11
1584#define OMAP54XX_VC_SAERR_ST_WIDTH 0x1
1585#define OMAP54XX_VC_SAERR_ST_MASK (1 << 11)
1586
1587/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1588#define OMAP54XX_VC_TOERR_EN_SHIFT 13
1589#define OMAP54XX_VC_TOERR_EN_WIDTH 0x1
1590#define OMAP54XX_VC_TOERR_EN_MASK (1 << 13)
1591
1592/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1593#define OMAP54XX_VC_TOERR_ST_SHIFT 13
1594#define OMAP54XX_VC_TOERR_ST_WIDTH 0x1
1595#define OMAP54XX_VC_TOERR_ST_MASK (1 << 13)
1596
1597/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */
1598#define OMAP54XX_VDDMAX_SHIFT 24
1599#define OMAP54XX_VDDMAX_WIDTH 0x8
1600#define OMAP54XX_VDDMAX_MASK (0xff << 24)
1601
1602/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */
1603#define OMAP54XX_VDDMIN_SHIFT 16
1604#define OMAP54XX_VDDMIN_WIDTH 0x8
1605#define OMAP54XX_VDDMIN_MASK (0xff << 16)
1606
1607/* Used by PRM_VOLTCTRL */
1608#define OMAP54XX_VDD_CORE_I2C_DISABLE_SHIFT 12
1609#define OMAP54XX_VDD_CORE_I2C_DISABLE_WIDTH 0x1
1610#define OMAP54XX_VDD_CORE_I2C_DISABLE_MASK (1 << 12)
1611
1612/* Used by PRM_RSTST */
1613#define OMAP54XX_VDD_CORE_VOLT_MGR_RST_SHIFT 8
1614#define OMAP54XX_VDD_CORE_VOLT_MGR_RST_WIDTH 0x1
1615#define OMAP54XX_VDD_CORE_VOLT_MGR_RST_MASK (1 << 8)
1616
1617/* Used by PRM_VOLTCTRL */
1618#define OMAP54XX_VDD_MM_I2C_DISABLE_SHIFT 14
1619#define OMAP54XX_VDD_MM_I2C_DISABLE_WIDTH 0x1
1620#define OMAP54XX_VDD_MM_I2C_DISABLE_MASK (1 << 14)
1621
1622/* Used by PRM_VOLTCTRL */
1623#define OMAP54XX_VDD_MM_PRESENCE_SHIFT 9
1624#define OMAP54XX_VDD_MM_PRESENCE_WIDTH 0x1
1625#define OMAP54XX_VDD_MM_PRESENCE_MASK (1 << 9)
1626
1627/* Used by PRM_RSTST */
1628#define OMAP54XX_VDD_MM_VOLT_MGR_RST_SHIFT 7
1629#define OMAP54XX_VDD_MM_VOLT_MGR_RST_WIDTH 0x1
1630#define OMAP54XX_VDD_MM_VOLT_MGR_RST_MASK (1 << 7)
1631
1632/* Used by PRM_VOLTCTRL */
1633#define OMAP54XX_VDD_MPU_I2C_DISABLE_SHIFT 13
1634#define OMAP54XX_VDD_MPU_I2C_DISABLE_WIDTH 0x1
1635#define OMAP54XX_VDD_MPU_I2C_DISABLE_MASK (1 << 13)
1636
1637/* Used by PRM_VOLTCTRL */
1638#define OMAP54XX_VDD_MPU_PRESENCE_SHIFT 8
1639#define OMAP54XX_VDD_MPU_PRESENCE_WIDTH 0x1
1640#define OMAP54XX_VDD_MPU_PRESENCE_MASK (1 << 8)
1641
1642/* Used by PRM_RSTST */
1643#define OMAP54XX_VDD_MPU_VOLT_MGR_RST_SHIFT 6
1644#define OMAP54XX_VDD_MPU_VOLT_MGR_RST_WIDTH 0x1
1645#define OMAP54XX_VDD_MPU_VOLT_MGR_RST_MASK (1 << 6)
1646
1647/* Used by PRM_VC_CORE_ERRST */
1648#define OMAP54XX_VFSM_RA_ERR_CORE_SHIFT 4
1649#define OMAP54XX_VFSM_RA_ERR_CORE_WIDTH 0x1
1650#define OMAP54XX_VFSM_RA_ERR_CORE_MASK (1 << 4)
1651
1652/* Used by PRM_VC_MM_ERRST */
1653#define OMAP54XX_VFSM_RA_ERR_MM_SHIFT 4
1654#define OMAP54XX_VFSM_RA_ERR_MM_WIDTH 0x1
1655#define OMAP54XX_VFSM_RA_ERR_MM_MASK (1 << 4)
1656
1657/* Used by PRM_VC_MPU_ERRST */
1658#define OMAP54XX_VFSM_RA_ERR_MPU_SHIFT 4
1659#define OMAP54XX_VFSM_RA_ERR_MPU_WIDTH 0x1
1660#define OMAP54XX_VFSM_RA_ERR_MPU_MASK (1 << 4)
1661
1662/* Used by PRM_VC_CORE_ERRST */
1663#define OMAP54XX_VFSM_SA_ERR_CORE_SHIFT 3
1664#define OMAP54XX_VFSM_SA_ERR_CORE_WIDTH 0x1
1665#define OMAP54XX_VFSM_SA_ERR_CORE_MASK (1 << 3)
1666
1667/* Used by PRM_VC_MM_ERRST */
1668#define OMAP54XX_VFSM_SA_ERR_MM_SHIFT 3
1669#define OMAP54XX_VFSM_SA_ERR_MM_WIDTH 0x1
1670#define OMAP54XX_VFSM_SA_ERR_MM_MASK (1 << 3)
1671
1672/* Used by PRM_VC_MPU_ERRST */
1673#define OMAP54XX_VFSM_SA_ERR_MPU_SHIFT 3
1674#define OMAP54XX_VFSM_SA_ERR_MPU_WIDTH 0x1
1675#define OMAP54XX_VFSM_SA_ERR_MPU_MASK (1 << 3)
1676
1677/* Used by PRM_VC_CORE_ERRST */
1678#define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_SHIFT 5
1679#define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_WIDTH 0x1
1680#define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_MASK (1 << 5)
1681
1682/* Used by PRM_VC_MM_ERRST */
1683#define OMAP54XX_VFSM_TIMEOUT_ERR_MM_SHIFT 5
1684#define OMAP54XX_VFSM_TIMEOUT_ERR_MM_WIDTH 0x1
1685#define OMAP54XX_VFSM_TIMEOUT_ERR_MM_MASK (1 << 5)
1686
1687/* Used by PRM_VC_MPU_ERRST */
1688#define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_SHIFT 5
1689#define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_WIDTH 0x1
1690#define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_MASK (1 << 5)
1691
1692/* Used by PRM_VC_SMPS_CORE_CONFIG */
1693#define OMAP54XX_VOLRA_VDD_CORE_L_SHIFT 8
1694#define OMAP54XX_VOLRA_VDD_CORE_L_WIDTH 0x8
1695#define OMAP54XX_VOLRA_VDD_CORE_L_MASK (0xff << 8)
1696
1697/* Used by PRM_VC_SMPS_MM_CONFIG */
1698#define OMAP54XX_VOLRA_VDD_MM_L_SHIFT 8
1699#define OMAP54XX_VOLRA_VDD_MM_L_WIDTH 0x8
1700#define OMAP54XX_VOLRA_VDD_MM_L_MASK (0xff << 8)
1701
1702/* Used by PRM_VC_SMPS_MPU_CONFIG */
1703#define OMAP54XX_VOLRA_VDD_MPU_L_SHIFT 8
1704#define OMAP54XX_VOLRA_VDD_MPU_L_WIDTH 0x8
1705#define OMAP54XX_VOLRA_VDD_MPU_L_MASK (0xff << 8)
1706
1707/* Used by PRM_VOLTST_MM, PRM_VOLTST_MPU */
1708#define OMAP54XX_VOLTSTATEST_SHIFT 0
1709#define OMAP54XX_VOLTSTATEST_WIDTH 0x2
1710#define OMAP54XX_VOLTSTATEST_MASK (0x3 << 0)
1711
1712/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
1713#define OMAP54XX_VPENABLE_SHIFT 0
1714#define OMAP54XX_VPENABLE_WIDTH 0x1
1715#define OMAP54XX_VPENABLE_MASK (1 << 0)
1716
1717/* Used by PRM_VP_CORE_STATUS, PRM_VP_MM_STATUS, PRM_VP_MPU_STATUS */
1718#define OMAP54XX_VPINIDLE_SHIFT 0
1719#define OMAP54XX_VPINIDLE_WIDTH 0x1
1720#define OMAP54XX_VPINIDLE_MASK (1 << 0)
1721
1722/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_MM_VOLTAGE, PRM_VP_MPU_VOLTAGE */
1723#define OMAP54XX_VPVOLTAGE_SHIFT 0
1724#define OMAP54XX_VPVOLTAGE_WIDTH 0x8
1725#define OMAP54XX_VPVOLTAGE_MASK (0xff << 0)
1726
1727/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1728#define OMAP54XX_VP_CORE_EQVALUE_EN_SHIFT 20
1729#define OMAP54XX_VP_CORE_EQVALUE_EN_WIDTH 0x1
1730#define OMAP54XX_VP_CORE_EQVALUE_EN_MASK (1 << 20)
1731
1732/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1733#define OMAP54XX_VP_CORE_EQVALUE_ST_SHIFT 20
1734#define OMAP54XX_VP_CORE_EQVALUE_ST_WIDTH 0x1
1735#define OMAP54XX_VP_CORE_EQVALUE_ST_MASK (1 << 20)
1736
1737/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1738#define OMAP54XX_VP_CORE_MAXVDD_EN_SHIFT 18
1739#define OMAP54XX_VP_CORE_MAXVDD_EN_WIDTH 0x1
1740#define OMAP54XX_VP_CORE_MAXVDD_EN_MASK (1 << 18)
1741
1742/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1743#define OMAP54XX_VP_CORE_MAXVDD_ST_SHIFT 18
1744#define OMAP54XX_VP_CORE_MAXVDD_ST_WIDTH 0x1
1745#define OMAP54XX_VP_CORE_MAXVDD_ST_MASK (1 << 18)
1746
1747/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1748#define OMAP54XX_VP_CORE_MINVDD_EN_SHIFT 17
1749#define OMAP54XX_VP_CORE_MINVDD_EN_WIDTH 0x1
1750#define OMAP54XX_VP_CORE_MINVDD_EN_MASK (1 << 17)
1751
1752/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1753#define OMAP54XX_VP_CORE_MINVDD_ST_SHIFT 17
1754#define OMAP54XX_VP_CORE_MINVDD_ST_WIDTH 0x1
1755#define OMAP54XX_VP_CORE_MINVDD_ST_MASK (1 << 17)
1756
1757/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1758#define OMAP54XX_VP_CORE_NOSMPSACK_EN_SHIFT 19
1759#define OMAP54XX_VP_CORE_NOSMPSACK_EN_WIDTH 0x1
1760#define OMAP54XX_VP_CORE_NOSMPSACK_EN_MASK (1 << 19)
1761
1762/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1763#define OMAP54XX_VP_CORE_NOSMPSACK_ST_SHIFT 19
1764#define OMAP54XX_VP_CORE_NOSMPSACK_ST_WIDTH 0x1
1765#define OMAP54XX_VP_CORE_NOSMPSACK_ST_MASK (1 << 19)
1766
1767/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1768#define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_SHIFT 16
1769#define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_WIDTH 0x1
1770#define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_MASK (1 << 16)
1771
1772/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1773#define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_SHIFT 16
1774#define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_WIDTH 0x1
1775#define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_MASK (1 << 16)
1776
1777/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1778#define OMAP54XX_VP_CORE_TRANXDONE_EN_SHIFT 21
1779#define OMAP54XX_VP_CORE_TRANXDONE_EN_WIDTH 0x1
1780#define OMAP54XX_VP_CORE_TRANXDONE_EN_MASK (1 << 21)
1781
1782/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1783#define OMAP54XX_VP_CORE_TRANXDONE_ST_SHIFT 21
1784#define OMAP54XX_VP_CORE_TRANXDONE_ST_WIDTH 0x1
1785#define OMAP54XX_VP_CORE_TRANXDONE_ST_MASK (1 << 21)
1786
1787/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1788#define OMAP54XX_VP_MM_EQVALUE_EN_SHIFT 28
1789#define OMAP54XX_VP_MM_EQVALUE_EN_WIDTH 0x1
1790#define OMAP54XX_VP_MM_EQVALUE_EN_MASK (1 << 28)
1791
1792/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1793#define OMAP54XX_VP_MM_EQVALUE_ST_SHIFT 28
1794#define OMAP54XX_VP_MM_EQVALUE_ST_WIDTH 0x1
1795#define OMAP54XX_VP_MM_EQVALUE_ST_MASK (1 << 28)
1796
1797/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1798#define OMAP54XX_VP_MM_MAXVDD_EN_SHIFT 26
1799#define OMAP54XX_VP_MM_MAXVDD_EN_WIDTH 0x1
1800#define OMAP54XX_VP_MM_MAXVDD_EN_MASK (1 << 26)
1801
1802/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1803#define OMAP54XX_VP_MM_MAXVDD_ST_SHIFT 26
1804#define OMAP54XX_VP_MM_MAXVDD_ST_WIDTH 0x1
1805#define OMAP54XX_VP_MM_MAXVDD_ST_MASK (1 << 26)
1806
1807/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1808#define OMAP54XX_VP_MM_MINVDD_EN_SHIFT 25
1809#define OMAP54XX_VP_MM_MINVDD_EN_WIDTH 0x1
1810#define OMAP54XX_VP_MM_MINVDD_EN_MASK (1 << 25)
1811
1812/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1813#define OMAP54XX_VP_MM_MINVDD_ST_SHIFT 25
1814#define OMAP54XX_VP_MM_MINVDD_ST_WIDTH 0x1
1815#define OMAP54XX_VP_MM_MINVDD_ST_MASK (1 << 25)
1816
1817/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1818#define OMAP54XX_VP_MM_NOSMPSACK_EN_SHIFT 27
1819#define OMAP54XX_VP_MM_NOSMPSACK_EN_WIDTH 0x1
1820#define OMAP54XX_VP_MM_NOSMPSACK_EN_MASK (1 << 27)
1821
1822/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1823#define OMAP54XX_VP_MM_NOSMPSACK_ST_SHIFT 27
1824#define OMAP54XX_VP_MM_NOSMPSACK_ST_WIDTH 0x1
1825#define OMAP54XX_VP_MM_NOSMPSACK_ST_MASK (1 << 27)
1826
1827/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1828#define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_SHIFT 24
1829#define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_WIDTH 0x1
1830#define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_MASK (1 << 24)
1831
1832/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1833#define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_SHIFT 24
1834#define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_WIDTH 0x1
1835#define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_MASK (1 << 24)
1836
1837/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1838#define OMAP54XX_VP_MM_TRANXDONE_EN_SHIFT 29
1839#define OMAP54XX_VP_MM_TRANXDONE_EN_WIDTH 0x1
1840#define OMAP54XX_VP_MM_TRANXDONE_EN_MASK (1 << 29)
1841
1842/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1843#define OMAP54XX_VP_MM_TRANXDONE_ST_SHIFT 29
1844#define OMAP54XX_VP_MM_TRANXDONE_ST_WIDTH 0x1
1845#define OMAP54XX_VP_MM_TRANXDONE_ST_MASK (1 << 29)
1846
1847/* Used by PRM_IRQENABLE_MPU_2 */
1848#define OMAP54XX_VP_MPU_EQVALUE_EN_SHIFT 4
1849#define OMAP54XX_VP_MPU_EQVALUE_EN_WIDTH 0x1
1850#define OMAP54XX_VP_MPU_EQVALUE_EN_MASK (1 << 4)
1851
1852/* Used by PRM_IRQSTATUS_MPU_2 */
1853#define OMAP54XX_VP_MPU_EQVALUE_ST_SHIFT 4
1854#define OMAP54XX_VP_MPU_EQVALUE_ST_WIDTH 0x1
1855#define OMAP54XX_VP_MPU_EQVALUE_ST_MASK (1 << 4)
1856
1857/* Used by PRM_IRQENABLE_MPU_2 */
1858#define OMAP54XX_VP_MPU_MAXVDD_EN_SHIFT 2
1859#define OMAP54XX_VP_MPU_MAXVDD_EN_WIDTH 0x1
1860#define OMAP54XX_VP_MPU_MAXVDD_EN_MASK (1 << 2)
1861
1862/* Used by PRM_IRQSTATUS_MPU_2 */
1863#define OMAP54XX_VP_MPU_MAXVDD_ST_SHIFT 2
1864#define OMAP54XX_VP_MPU_MAXVDD_ST_WIDTH 0x1
1865#define OMAP54XX_VP_MPU_MAXVDD_ST_MASK (1 << 2)
1866
1867/* Used by PRM_IRQENABLE_MPU_2 */
1868#define OMAP54XX_VP_MPU_MINVDD_EN_SHIFT 1
1869#define OMAP54XX_VP_MPU_MINVDD_EN_WIDTH 0x1
1870#define OMAP54XX_VP_MPU_MINVDD_EN_MASK (1 << 1)
1871
1872/* Used by PRM_IRQSTATUS_MPU_2 */
1873#define OMAP54XX_VP_MPU_MINVDD_ST_SHIFT 1
1874#define OMAP54XX_VP_MPU_MINVDD_ST_WIDTH 0x1
1875#define OMAP54XX_VP_MPU_MINVDD_ST_MASK (1 << 1)
1876
1877/* Used by PRM_IRQENABLE_MPU_2 */
1878#define OMAP54XX_VP_MPU_NOSMPSACK_EN_SHIFT 3
1879#define OMAP54XX_VP_MPU_NOSMPSACK_EN_WIDTH 0x1
1880#define OMAP54XX_VP_MPU_NOSMPSACK_EN_MASK (1 << 3)
1881
1882/* Used by PRM_IRQSTATUS_MPU_2 */
1883#define OMAP54XX_VP_MPU_NOSMPSACK_ST_SHIFT 3
1884#define OMAP54XX_VP_MPU_NOSMPSACK_ST_WIDTH 0x1
1885#define OMAP54XX_VP_MPU_NOSMPSACK_ST_MASK (1 << 3)
1886
1887/* Used by PRM_IRQENABLE_MPU_2 */
1888#define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_SHIFT 0
1889#define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_WIDTH 0x1
1890#define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_MASK (1 << 0)
1891
1892/* Used by PRM_IRQSTATUS_MPU_2 */
1893#define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_SHIFT 0
1894#define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_WIDTH 0x1
1895#define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_MASK (1 << 0)
1896
1897/* Used by PRM_IRQENABLE_MPU_2 */
1898#define OMAP54XX_VP_MPU_TRANXDONE_EN_SHIFT 5
1899#define OMAP54XX_VP_MPU_TRANXDONE_EN_WIDTH 0x1
1900#define OMAP54XX_VP_MPU_TRANXDONE_EN_MASK (1 << 5)
1901
1902/* Used by PRM_IRQSTATUS_MPU_2 */
1903#define OMAP54XX_VP_MPU_TRANXDONE_ST_SHIFT 5
1904#define OMAP54XX_VP_MPU_TRANXDONE_ST_WIDTH 0x1
1905#define OMAP54XX_VP_MPU_TRANXDONE_ST_MASK (1 << 5)
1906
1907/* Used by PRM_SRAM_COUNT */
1908#define OMAP54XX_VSETUPCNT_VALUE_SHIFT 8
1909#define OMAP54XX_VSETUPCNT_VALUE_WIDTH 0x8
1910#define OMAP54XX_VSETUPCNT_VALUE_MASK (0xff << 8)
1911
1912/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_MM_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
1913#define OMAP54XX_VSTEPMAX_SHIFT 0
1914#define OMAP54XX_VSTEPMAX_WIDTH 0x8
1915#define OMAP54XX_VSTEPMAX_MASK (0xff << 0)
1916
1917/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_MM_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
1918#define OMAP54XX_VSTEPMIN_SHIFT 0
1919#define OMAP54XX_VSTEPMIN_WIDTH 0x8
1920#define OMAP54XX_VSTEPMIN_MASK (0xff << 0)
1921
1922/* Used by PM_DSS_DSS_WKDEP */
1923#define OMAP54XX_WKUPDEP_DISPC_DSP_SHIFT 2
1924#define OMAP54XX_WKUPDEP_DISPC_DSP_WIDTH 0x1
1925#define OMAP54XX_WKUPDEP_DISPC_DSP_MASK (1 << 2)
1926
1927/* Used by PM_DSS_DSS_WKDEP */
1928#define OMAP54XX_WKUPDEP_DISPC_IPU_SHIFT 1
1929#define OMAP54XX_WKUPDEP_DISPC_IPU_WIDTH 0x1
1930#define OMAP54XX_WKUPDEP_DISPC_IPU_MASK (1 << 1)
1931
1932/* Used by PM_DSS_DSS_WKDEP */
1933#define OMAP54XX_WKUPDEP_DISPC_MPU_SHIFT 0
1934#define OMAP54XX_WKUPDEP_DISPC_MPU_WIDTH 0x1
1935#define OMAP54XX_WKUPDEP_DISPC_MPU_MASK (1 << 0)
1936
1937/* Used by PM_DSS_DSS_WKDEP */
1938#define OMAP54XX_WKUPDEP_DISPC_SDMA_SHIFT 3
1939#define OMAP54XX_WKUPDEP_DISPC_SDMA_WIDTH 0x1
1940#define OMAP54XX_WKUPDEP_DISPC_SDMA_MASK (1 << 3)
1941
1942/* Used by PM_ABE_DMIC_WKDEP */
1943#define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_SHIFT 6
1944#define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_WIDTH 0x1
1945#define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_MASK (1 << 6)
1946
1947/* Used by PM_ABE_DMIC_WKDEP */
1948#define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_SHIFT 7
1949#define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_WIDTH 0x1
1950#define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_MASK (1 << 7)
1951
1952/* Used by PM_ABE_DMIC_WKDEP */
1953#define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_SHIFT 2
1954#define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_WIDTH 0x1
1955#define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_MASK (1 << 2)
1956
1957/* Used by PM_ABE_DMIC_WKDEP */
1958#define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_SHIFT 0
1959#define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_WIDTH 0x1
1960#define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_MASK (1 << 0)
1961
1962/* Used by PM_DSS_DSS_WKDEP */
1963#define OMAP54XX_WKUPDEP_DSI1_A_DSP_SHIFT 6
1964#define OMAP54XX_WKUPDEP_DSI1_A_DSP_WIDTH 0x1
1965#define OMAP54XX_WKUPDEP_DSI1_A_DSP_MASK (1 << 6)
1966
1967/* Used by PM_DSS_DSS_WKDEP */
1968#define OMAP54XX_WKUPDEP_DSI1_A_IPU_SHIFT 5
1969#define OMAP54XX_WKUPDEP_DSI1_A_IPU_WIDTH 0x1
1970#define OMAP54XX_WKUPDEP_DSI1_A_IPU_MASK (1 << 5)
1971
1972/* Used by PM_DSS_DSS_WKDEP */
1973#define OMAP54XX_WKUPDEP_DSI1_A_MPU_SHIFT 4
1974#define OMAP54XX_WKUPDEP_DSI1_A_MPU_WIDTH 0x1
1975#define OMAP54XX_WKUPDEP_DSI1_A_MPU_MASK (1 << 4)
1976
1977/* Used by PM_DSS_DSS_WKDEP */
1978#define OMAP54XX_WKUPDEP_DSI1_A_SDMA_SHIFT 7
1979#define OMAP54XX_WKUPDEP_DSI1_A_SDMA_WIDTH 0x1
1980#define OMAP54XX_WKUPDEP_DSI1_A_SDMA_MASK (1 << 7)
1981
1982/* Used by PM_DSS_DSS_WKDEP */
1983#define OMAP54XX_WKUPDEP_DSI1_B_DSP_SHIFT 10
1984#define OMAP54XX_WKUPDEP_DSI1_B_DSP_WIDTH 0x1
1985#define OMAP54XX_WKUPDEP_DSI1_B_DSP_MASK (1 << 10)
1986
1987/* Used by PM_DSS_DSS_WKDEP */
1988#define OMAP54XX_WKUPDEP_DSI1_B_IPU_SHIFT 9
1989#define OMAP54XX_WKUPDEP_DSI1_B_IPU_WIDTH 0x1
1990#define OMAP54XX_WKUPDEP_DSI1_B_IPU_MASK (1 << 9)
1991
1992/* Used by PM_DSS_DSS_WKDEP */
1993#define OMAP54XX_WKUPDEP_DSI1_B_MPU_SHIFT 8
1994#define OMAP54XX_WKUPDEP_DSI1_B_MPU_WIDTH 0x1
1995#define OMAP54XX_WKUPDEP_DSI1_B_MPU_MASK (1 << 8)
1996
1997/* Used by PM_DSS_DSS_WKDEP */
1998#define OMAP54XX_WKUPDEP_DSI1_B_SDMA_SHIFT 11
1999#define OMAP54XX_WKUPDEP_DSI1_B_SDMA_WIDTH 0x1
2000#define OMAP54XX_WKUPDEP_DSI1_B_SDMA_MASK (1 << 11)
2001
2002/* Used by PM_DSS_DSS_WKDEP */
2003#define OMAP54XX_WKUPDEP_DSI1_C_DSP_SHIFT 17
2004#define OMAP54XX_WKUPDEP_DSI1_C_DSP_WIDTH 0x1
2005#define OMAP54XX_WKUPDEP_DSI1_C_DSP_MASK (1 << 17)
2006
2007/* Used by PM_DSS_DSS_WKDEP */
2008#define OMAP54XX_WKUPDEP_DSI1_C_IPU_SHIFT 16
2009#define OMAP54XX_WKUPDEP_DSI1_C_IPU_WIDTH 0x1
2010#define OMAP54XX_WKUPDEP_DSI1_C_IPU_MASK (1 << 16)
2011
2012/* Used by PM_DSS_DSS_WKDEP */
2013#define OMAP54XX_WKUPDEP_DSI1_C_MPU_SHIFT 15
2014#define OMAP54XX_WKUPDEP_DSI1_C_MPU_WIDTH 0x1
2015#define OMAP54XX_WKUPDEP_DSI1_C_MPU_MASK (1 << 15)
2016
2017/* Used by PM_DSS_DSS_WKDEP */
2018#define OMAP54XX_WKUPDEP_DSI1_C_SDMA_SHIFT 18
2019#define OMAP54XX_WKUPDEP_DSI1_C_SDMA_WIDTH 0x1
2020#define OMAP54XX_WKUPDEP_DSI1_C_SDMA_MASK (1 << 18)
2021
2022/* Used by PM_WKUPAON_GPIO1_WKDEP */
2023#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_SHIFT 1
2024#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_WIDTH 0x1
2025#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_MASK (1 << 1)
2026
2027/* Used by PM_WKUPAON_GPIO1_WKDEP */
2028#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT 0
2029#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_WIDTH 0x1
2030#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_MASK (1 << 0)
2031
2032/* Used by PM_WKUPAON_GPIO1_WKDEP */
2033#define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_SHIFT 6
2034#define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_WIDTH 0x1
2035#define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_MASK (1 << 6)
2036
2037/* Used by PM_L4PER_GPIO2_WKDEP */
2038#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_SHIFT 1
2039#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_WIDTH 0x1
2040#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_MASK (1 << 1)
2041
2042/* Used by PM_L4PER_GPIO2_WKDEP */
2043#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT 0
2044#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_WIDTH 0x1
2045#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_MASK (1 << 0)
2046
2047/* Used by PM_L4PER_GPIO2_WKDEP */
2048#define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_SHIFT 6
2049#define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_WIDTH 0x1
2050#define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_MASK (1 << 6)
2051
2052/* Used by PM_L4PER_GPIO3_WKDEP */
2053#define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT 0
2054#define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_WIDTH 0x1
2055#define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_MASK (1 << 0)
2056
2057/* Used by PM_L4PER_GPIO3_WKDEP */
2058#define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_SHIFT 6
2059#define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_WIDTH 0x1
2060#define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_MASK (1 << 6)
2061
2062/* Used by PM_L4PER_GPIO4_WKDEP */
2063#define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT 0
2064#define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_WIDTH 0x1
2065#define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_MASK (1 << 0)
2066
2067/* Used by PM_L4PER_GPIO4_WKDEP */
2068#define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_SHIFT 6
2069#define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_WIDTH 0x1
2070#define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_MASK (1 << 6)
2071
2072/* Used by PM_L4PER_GPIO5_WKDEP */
2073#define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT 0
2074#define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_WIDTH 0x1
2075#define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_MASK (1 << 0)
2076
2077/* Used by PM_L4PER_GPIO5_WKDEP */
2078#define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_SHIFT 6
2079#define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_WIDTH 0x1
2080#define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_MASK (1 << 6)
2081
2082/* Used by PM_L4PER_GPIO6_WKDEP */
2083#define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT 0
2084#define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_WIDTH 0x1
2085#define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_MASK (1 << 0)
2086
2087/* Used by PM_L4PER_GPIO6_WKDEP */
2088#define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_SHIFT 6
2089#define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_WIDTH 0x1
2090#define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_MASK (1 << 6)
2091
2092/* Used by PM_L4PER_GPIO7_WKDEP */
2093#define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_SHIFT 0
2094#define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_WIDTH 0x1
2095#define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_MASK (1 << 0)
2096
2097/* Used by PM_L4PER_GPIO8_WKDEP */
2098#define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_SHIFT 0
2099#define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_WIDTH 0x1
2100#define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_MASK (1 << 0)
2101
2102/* Used by PM_DSS_DSS_WKDEP */
2103#define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_SHIFT 19
2104#define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_WIDTH 0x1
2105#define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_MASK (1 << 19)
2106
2107/* Used by PM_DSS_DSS_WKDEP */
2108#define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_SHIFT 14
2109#define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_WIDTH 0x1
2110#define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_MASK (1 << 14)
2111
2112/* Used by PM_DSS_DSS_WKDEP */
2113#define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_SHIFT 13
2114#define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_WIDTH 0x1
2115#define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_MASK (1 << 13)
2116
2117/* Used by PM_DSS_DSS_WKDEP */
2118#define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_SHIFT 12
2119#define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_WIDTH 0x1
2120#define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_MASK (1 << 12)
2121
2122/* Used by PM_L3INIT_HSI_WKDEP */
2123#define OMAP54XX_WKUPDEP_HSI_DSP_DSP_SHIFT 6
2124#define OMAP54XX_WKUPDEP_HSI_DSP_DSP_WIDTH 0x1
2125#define OMAP54XX_WKUPDEP_HSI_DSP_DSP_MASK (1 << 6)
2126
2127/* Used by PM_L3INIT_HSI_WKDEP */
2128#define OMAP54XX_WKUPDEP_HSI_MCU_IPU_SHIFT 1
2129#define OMAP54XX_WKUPDEP_HSI_MCU_IPU_WIDTH 0x1
2130#define OMAP54XX_WKUPDEP_HSI_MCU_IPU_MASK (1 << 1)
2131
2132/* Used by PM_L3INIT_HSI_WKDEP */
2133#define OMAP54XX_WKUPDEP_HSI_MCU_MPU_SHIFT 0
2134#define OMAP54XX_WKUPDEP_HSI_MCU_MPU_WIDTH 0x1
2135#define OMAP54XX_WKUPDEP_HSI_MCU_MPU_MASK (1 << 0)
2136
2137/* Used by PM_L4PER_I2C1_WKDEP */
2138#define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_SHIFT 7
2139#define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_WIDTH 0x1
2140#define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_MASK (1 << 7)
2141
2142/* Used by PM_L4PER_I2C1_WKDEP */
2143#define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_SHIFT 1
2144#define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_WIDTH 0x1
2145#define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_MASK (1 << 1)
2146
2147/* Used by PM_L4PER_I2C1_WKDEP */
2148#define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_SHIFT 0
2149#define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_WIDTH 0x1
2150#define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_MASK (1 << 0)
2151
2152/* Used by PM_L4PER_I2C2_WKDEP */
2153#define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_SHIFT 7
2154#define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_WIDTH 0x1
2155#define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_MASK (1 << 7)
2156
2157/* Used by PM_L4PER_I2C2_WKDEP */
2158#define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_SHIFT 1
2159#define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_WIDTH 0x1
2160#define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_MASK (1 << 1)
2161
2162/* Used by PM_L4PER_I2C2_WKDEP */
2163#define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_SHIFT 0
2164#define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_WIDTH 0x1
2165#define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_MASK (1 << 0)
2166
2167/* Used by PM_L4PER_I2C3_WKDEP */
2168#define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_SHIFT 7
2169#define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_WIDTH 0x1
2170#define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_MASK (1 << 7)
2171
2172/* Used by PM_L4PER_I2C3_WKDEP */
2173#define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_SHIFT 1
2174#define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_WIDTH 0x1
2175#define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_MASK (1 << 1)
2176
2177/* Used by PM_L4PER_I2C3_WKDEP */
2178#define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_SHIFT 0
2179#define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_WIDTH 0x1
2180#define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_MASK (1 << 0)
2181
2182/* Used by PM_L4PER_I2C4_WKDEP */
2183#define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_SHIFT 7
2184#define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_WIDTH 0x1
2185#define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_MASK (1 << 7)
2186
2187/* Used by PM_L4PER_I2C4_WKDEP */
2188#define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_SHIFT 1
2189#define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_WIDTH 0x1
2190#define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_MASK (1 << 1)
2191
2192/* Used by PM_L4PER_I2C4_WKDEP */
2193#define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_SHIFT 0
2194#define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_WIDTH 0x1
2195#define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_MASK (1 << 0)
2196
2197/* Used by PM_L4PER_I2C5_WKDEP */
2198#define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_SHIFT 0
2199#define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_WIDTH 0x1
2200#define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_MASK (1 << 0)
2201
2202/* Used by PM_WKUPAON_KBD_WKDEP */
2203#define OMAP54XX_WKUPDEP_KBD_MPU_SHIFT 0
2204#define OMAP54XX_WKUPDEP_KBD_MPU_WIDTH 0x1
2205#define OMAP54XX_WKUPDEP_KBD_MPU_MASK (1 << 0)
2206
2207/* Used by PM_ABE_MCASP_WKDEP */
2208#define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_SHIFT 6
2209#define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_WIDTH 0x1
2210#define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_MASK (1 << 6)
2211
2212/* Used by PM_ABE_MCASP_WKDEP */
2213#define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_SHIFT 7
2214#define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_WIDTH 0x1
2215#define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_MASK (1 << 7)
2216
2217/* Used by PM_ABE_MCASP_WKDEP */
2218#define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_SHIFT 2
2219#define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_WIDTH 0x1
2220#define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_MASK (1 << 2)
2221
2222/* Used by PM_ABE_MCASP_WKDEP */
2223#define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_SHIFT 0
2224#define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_WIDTH 0x1
2225#define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_MASK (1 << 0)
2226
2227/* Used by PM_ABE_MCBSP1_WKDEP */
2228#define OMAP54XX_WKUPDEP_MCBSP1_DSP_SHIFT 2
2229#define OMAP54XX_WKUPDEP_MCBSP1_DSP_WIDTH 0x1
2230#define OMAP54XX_WKUPDEP_MCBSP1_DSP_MASK (1 << 2)
2231
2232/* Used by PM_ABE_MCBSP1_WKDEP */
2233#define OMAP54XX_WKUPDEP_MCBSP1_MPU_SHIFT 0
2234#define OMAP54XX_WKUPDEP_MCBSP1_MPU_WIDTH 0x1
2235#define OMAP54XX_WKUPDEP_MCBSP1_MPU_MASK (1 << 0)
2236
2237/* Used by PM_ABE_MCBSP1_WKDEP */
2238#define OMAP54XX_WKUPDEP_MCBSP1_SDMA_SHIFT 3
2239#define OMAP54XX_WKUPDEP_MCBSP1_SDMA_WIDTH 0x1
2240#define OMAP54XX_WKUPDEP_MCBSP1_SDMA_MASK (1 << 3)
2241
2242/* Used by PM_ABE_MCBSP2_WKDEP */
2243#define OMAP54XX_WKUPDEP_MCBSP2_DSP_SHIFT 2
2244#define OMAP54XX_WKUPDEP_MCBSP2_DSP_WIDTH 0x1
2245#define OMAP54XX_WKUPDEP_MCBSP2_DSP_MASK (1 << 2)
2246
2247/* Used by PM_ABE_MCBSP2_WKDEP */
2248#define OMAP54XX_WKUPDEP_MCBSP2_MPU_SHIFT 0
2249#define OMAP54XX_WKUPDEP_MCBSP2_MPU_WIDTH 0x1
2250#define OMAP54XX_WKUPDEP_MCBSP2_MPU_MASK (1 << 0)
2251
2252/* Used by PM_ABE_MCBSP2_WKDEP */
2253#define OMAP54XX_WKUPDEP_MCBSP2_SDMA_SHIFT 3
2254#define OMAP54XX_WKUPDEP_MCBSP2_SDMA_WIDTH 0x1
2255#define OMAP54XX_WKUPDEP_MCBSP2_SDMA_MASK (1 << 3)
2256
2257/* Used by PM_ABE_MCBSP3_WKDEP */
2258#define OMAP54XX_WKUPDEP_MCBSP3_DSP_SHIFT 2
2259#define OMAP54XX_WKUPDEP_MCBSP3_DSP_WIDTH 0x1
2260#define OMAP54XX_WKUPDEP_MCBSP3_DSP_MASK (1 << 2)
2261
2262/* Used by PM_ABE_MCBSP3_WKDEP */
2263#define OMAP54XX_WKUPDEP_MCBSP3_MPU_SHIFT 0
2264#define OMAP54XX_WKUPDEP_MCBSP3_MPU_WIDTH 0x1
2265#define OMAP54XX_WKUPDEP_MCBSP3_MPU_MASK (1 << 0)
2266
2267/* Used by PM_ABE_MCBSP3_WKDEP */
2268#define OMAP54XX_WKUPDEP_MCBSP3_SDMA_SHIFT 3
2269#define OMAP54XX_WKUPDEP_MCBSP3_SDMA_WIDTH 0x1
2270#define OMAP54XX_WKUPDEP_MCBSP3_SDMA_MASK (1 << 3)
2271
2272/* Used by PM_ABE_MCPDM_WKDEP */
2273#define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_SHIFT 6
2274#define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_WIDTH 0x1
2275#define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_MASK (1 << 6)
2276
2277/* Used by PM_ABE_MCPDM_WKDEP */
2278#define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_SHIFT 7
2279#define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_WIDTH 0x1
2280#define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_MASK (1 << 7)
2281
2282/* Used by PM_ABE_MCPDM_WKDEP */
2283#define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_SHIFT 2
2284#define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_WIDTH 0x1
2285#define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_MASK (1 << 2)
2286
2287/* Used by PM_ABE_MCPDM_WKDEP */
2288#define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_SHIFT 0
2289#define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_WIDTH 0x1
2290#define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_MASK (1 << 0)
2291
2292/* Used by PM_L4PER_MCSPI1_WKDEP */
2293#define OMAP54XX_WKUPDEP_MCSPI1_DSP_SHIFT 2
2294#define OMAP54XX_WKUPDEP_MCSPI1_DSP_WIDTH 0x1
2295#define OMAP54XX_WKUPDEP_MCSPI1_DSP_MASK (1 << 2)
2296
2297/* Used by PM_L4PER_MCSPI1_WKDEP */
2298#define OMAP54XX_WKUPDEP_MCSPI1_IPU_SHIFT 1
2299#define OMAP54XX_WKUPDEP_MCSPI1_IPU_WIDTH 0x1
2300#define OMAP54XX_WKUPDEP_MCSPI1_IPU_MASK (1 << 1)
2301
2302/* Used by PM_L4PER_MCSPI1_WKDEP */
2303#define OMAP54XX_WKUPDEP_MCSPI1_MPU_SHIFT 0
2304#define OMAP54XX_WKUPDEP_MCSPI1_MPU_WIDTH 0x1
2305#define OMAP54XX_WKUPDEP_MCSPI1_MPU_MASK (1 << 0)
2306
2307/* Used by PM_L4PER_MCSPI1_WKDEP */
2308#define OMAP54XX_WKUPDEP_MCSPI1_SDMA_SHIFT 3
2309#define OMAP54XX_WKUPDEP_MCSPI1_SDMA_WIDTH 0x1
2310#define OMAP54XX_WKUPDEP_MCSPI1_SDMA_MASK (1 << 3)
2311
2312/* Used by PM_L4PER_MCSPI2_WKDEP */
2313#define OMAP54XX_WKUPDEP_MCSPI2_IPU_SHIFT 1
2314#define OMAP54XX_WKUPDEP_MCSPI2_IPU_WIDTH 0x1
2315#define OMAP54XX_WKUPDEP_MCSPI2_IPU_MASK (1 << 1)
2316
2317/* Used by PM_L4PER_MCSPI2_WKDEP */
2318#define OMAP54XX_WKUPDEP_MCSPI2_MPU_SHIFT 0
2319#define OMAP54XX_WKUPDEP_MCSPI2_MPU_WIDTH 0x1
2320#define OMAP54XX_WKUPDEP_MCSPI2_MPU_MASK (1 << 0)
2321
2322/* Used by PM_L4PER_MCSPI2_WKDEP */
2323#define OMAP54XX_WKUPDEP_MCSPI2_SDMA_SHIFT 3
2324#define OMAP54XX_WKUPDEP_MCSPI2_SDMA_WIDTH 0x1
2325#define OMAP54XX_WKUPDEP_MCSPI2_SDMA_MASK (1 << 3)
2326
2327/* Used by PM_L4PER_MCSPI3_WKDEP */
2328#define OMAP54XX_WKUPDEP_MCSPI3_MPU_SHIFT 0
2329#define OMAP54XX_WKUPDEP_MCSPI3_MPU_WIDTH 0x1
2330#define OMAP54XX_WKUPDEP_MCSPI3_MPU_MASK (1 << 0)
2331
2332/* Used by PM_L4PER_MCSPI3_WKDEP */
2333#define OMAP54XX_WKUPDEP_MCSPI3_SDMA_SHIFT 3
2334#define OMAP54XX_WKUPDEP_MCSPI3_SDMA_WIDTH 0x1
2335#define OMAP54XX_WKUPDEP_MCSPI3_SDMA_MASK (1 << 3)
2336
2337/* Used by PM_L4PER_MCSPI4_WKDEP */
2338#define OMAP54XX_WKUPDEP_MCSPI4_MPU_SHIFT 0
2339#define OMAP54XX_WKUPDEP_MCSPI4_MPU_WIDTH 0x1
2340#define OMAP54XX_WKUPDEP_MCSPI4_MPU_MASK (1 << 0)
2341
2342/* Used by PM_L4PER_MCSPI4_WKDEP */
2343#define OMAP54XX_WKUPDEP_MCSPI4_SDMA_SHIFT 3
2344#define OMAP54XX_WKUPDEP_MCSPI4_SDMA_WIDTH 0x1
2345#define OMAP54XX_WKUPDEP_MCSPI4_SDMA_MASK (1 << 3)
2346
2347/* Used by PM_L3INIT_MMC1_WKDEP */
2348#define OMAP54XX_WKUPDEP_MMC1_DSP_SHIFT 2
2349#define OMAP54XX_WKUPDEP_MMC1_DSP_WIDTH 0x1
2350#define OMAP54XX_WKUPDEP_MMC1_DSP_MASK (1 << 2)
2351
2352/* Used by PM_L3INIT_MMC1_WKDEP */
2353#define OMAP54XX_WKUPDEP_MMC1_IPU_SHIFT 1
2354#define OMAP54XX_WKUPDEP_MMC1_IPU_WIDTH 0x1
2355#define OMAP54XX_WKUPDEP_MMC1_IPU_MASK (1 << 1)
2356
2357/* Used by PM_L3INIT_MMC1_WKDEP */
2358#define OMAP54XX_WKUPDEP_MMC1_MPU_SHIFT 0
2359#define OMAP54XX_WKUPDEP_MMC1_MPU_WIDTH 0x1
2360#define OMAP54XX_WKUPDEP_MMC1_MPU_MASK (1 << 0)
2361
2362/* Used by PM_L3INIT_MMC1_WKDEP */
2363#define OMAP54XX_WKUPDEP_MMC1_SDMA_SHIFT 3
2364#define OMAP54XX_WKUPDEP_MMC1_SDMA_WIDTH 0x1
2365#define OMAP54XX_WKUPDEP_MMC1_SDMA_MASK (1 << 3)
2366
2367/* Used by PM_L3INIT_MMC2_WKDEP */
2368#define OMAP54XX_WKUPDEP_MMC2_DSP_SHIFT 2
2369#define OMAP54XX_WKUPDEP_MMC2_DSP_WIDTH 0x1
2370#define OMAP54XX_WKUPDEP_MMC2_DSP_MASK (1 << 2)
2371
2372/* Used by PM_L3INIT_MMC2_WKDEP */
2373#define OMAP54XX_WKUPDEP_MMC2_IPU_SHIFT 1
2374#define OMAP54XX_WKUPDEP_MMC2_IPU_WIDTH 0x1
2375#define OMAP54XX_WKUPDEP_MMC2_IPU_MASK (1 << 1)
2376
2377/* Used by PM_L3INIT_MMC2_WKDEP */
2378#define OMAP54XX_WKUPDEP_MMC2_MPU_SHIFT 0
2379#define OMAP54XX_WKUPDEP_MMC2_MPU_WIDTH 0x1
2380#define OMAP54XX_WKUPDEP_MMC2_MPU_MASK (1 << 0)
2381
2382/* Used by PM_L3INIT_MMC2_WKDEP */
2383#define OMAP54XX_WKUPDEP_MMC2_SDMA_SHIFT 3
2384#define OMAP54XX_WKUPDEP_MMC2_SDMA_WIDTH 0x1
2385#define OMAP54XX_WKUPDEP_MMC2_SDMA_MASK (1 << 3)
2386
2387/* Used by PM_L4PER_MMC3_WKDEP */
2388#define OMAP54XX_WKUPDEP_MMC3_IPU_SHIFT 1
2389#define OMAP54XX_WKUPDEP_MMC3_IPU_WIDTH 0x1
2390#define OMAP54XX_WKUPDEP_MMC3_IPU_MASK (1 << 1)
2391
2392/* Used by PM_L4PER_MMC3_WKDEP */
2393#define OMAP54XX_WKUPDEP_MMC3_MPU_SHIFT 0
2394#define OMAP54XX_WKUPDEP_MMC3_MPU_WIDTH 0x1
2395#define OMAP54XX_WKUPDEP_MMC3_MPU_MASK (1 << 0)
2396
2397/* Used by PM_L4PER_MMC3_WKDEP */
2398#define OMAP54XX_WKUPDEP_MMC3_SDMA_SHIFT 3
2399#define OMAP54XX_WKUPDEP_MMC3_SDMA_WIDTH 0x1
2400#define OMAP54XX_WKUPDEP_MMC3_SDMA_MASK (1 << 3)
2401
2402/* Used by PM_L4PER_MMC4_WKDEP */
2403#define OMAP54XX_WKUPDEP_MMC4_MPU_SHIFT 0
2404#define OMAP54XX_WKUPDEP_MMC4_MPU_WIDTH 0x1
2405#define OMAP54XX_WKUPDEP_MMC4_MPU_MASK (1 << 0)
2406
2407/* Used by PM_L4PER_MMC4_WKDEP */
2408#define OMAP54XX_WKUPDEP_MMC4_SDMA_SHIFT 3
2409#define OMAP54XX_WKUPDEP_MMC4_SDMA_WIDTH 0x1
2410#define OMAP54XX_WKUPDEP_MMC4_SDMA_MASK (1 << 3)
2411
2412/* Used by PM_L4PER_MMC5_WKDEP */
2413#define OMAP54XX_WKUPDEP_MMC5_MPU_SHIFT 0
2414#define OMAP54XX_WKUPDEP_MMC5_MPU_WIDTH 0x1
2415#define OMAP54XX_WKUPDEP_MMC5_MPU_MASK (1 << 0)
2416
2417/* Used by PM_L4PER_MMC5_WKDEP */
2418#define OMAP54XX_WKUPDEP_MMC5_SDMA_SHIFT 3
2419#define OMAP54XX_WKUPDEP_MMC5_SDMA_WIDTH 0x1
2420#define OMAP54XX_WKUPDEP_MMC5_SDMA_MASK (1 << 3)
2421
2422/* Used by PM_L3INIT_SATA_WKDEP */
2423#define OMAP54XX_WKUPDEP_SATA_MPU_SHIFT 0
2424#define OMAP54XX_WKUPDEP_SATA_MPU_WIDTH 0x1
2425#define OMAP54XX_WKUPDEP_SATA_MPU_MASK (1 << 0)
2426
2427/* Used by PM_ABE_SLIMBUS1_WKDEP */
2428#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_SHIFT 6
2429#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_WIDTH 0x1
2430#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_MASK (1 << 6)
2431
2432/* Used by PM_ABE_SLIMBUS1_WKDEP */
2433#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT 7
2434#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_WIDTH 0x1
2435#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK (1 << 7)
2436
2437/* Used by PM_ABE_SLIMBUS1_WKDEP */
2438#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_SHIFT 2
2439#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_WIDTH 0x1
2440#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_MASK (1 << 2)
2441
2442/* Used by PM_ABE_SLIMBUS1_WKDEP */
2443#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT 0
2444#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_WIDTH 0x1
2445#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK (1 << 0)
2446
2447/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
2448#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_SHIFT 1
2449#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_WIDTH 0x1
2450#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_MASK (1 << 1)
2451
2452/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
2453#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_SHIFT 0
2454#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_WIDTH 0x1
2455#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_MASK (1 << 0)
2456
2457/* Used by PM_COREAON_SMARTREFLEX_MM_WKDEP */
2458#define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_SHIFT 0
2459#define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_WIDTH 0x1
2460#define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_MASK (1 << 0)
2461
2462/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */
2463#define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_SHIFT 0
2464#define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_WIDTH 0x1
2465#define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_MASK (1 << 0)
2466
2467/* Used by PM_L4PER_TIMER10_WKDEP */
2468#define OMAP54XX_WKUPDEP_TIMER10_MPU_SHIFT 0
2469#define OMAP54XX_WKUPDEP_TIMER10_MPU_WIDTH 0x1
2470#define OMAP54XX_WKUPDEP_TIMER10_MPU_MASK (1 << 0)
2471
2472/* Used by PM_L4PER_TIMER11_WKDEP */
2473#define OMAP54XX_WKUPDEP_TIMER11_IPU_SHIFT 1
2474#define OMAP54XX_WKUPDEP_TIMER11_IPU_WIDTH 0x1
2475#define OMAP54XX_WKUPDEP_TIMER11_IPU_MASK (1 << 1)
2476
2477/* Used by PM_L4PER_TIMER11_WKDEP */
2478#define OMAP54XX_WKUPDEP_TIMER11_MPU_SHIFT 0
2479#define OMAP54XX_WKUPDEP_TIMER11_MPU_WIDTH 0x1
2480#define OMAP54XX_WKUPDEP_TIMER11_MPU_MASK (1 << 0)
2481
2482/* Used by PM_WKUPAON_TIMER12_WKDEP */
2483#define OMAP54XX_WKUPDEP_TIMER12_MPU_SHIFT 0
2484#define OMAP54XX_WKUPDEP_TIMER12_MPU_WIDTH 0x1
2485#define OMAP54XX_WKUPDEP_TIMER12_MPU_MASK (1 << 0)
2486
2487/* Used by PM_WKUPAON_TIMER1_WKDEP */
2488#define OMAP54XX_WKUPDEP_TIMER1_MPU_SHIFT 0
2489#define OMAP54XX_WKUPDEP_TIMER1_MPU_WIDTH 0x1
2490#define OMAP54XX_WKUPDEP_TIMER1_MPU_MASK (1 << 0)
2491
2492/* Used by PM_L4PER_TIMER2_WKDEP */
2493#define OMAP54XX_WKUPDEP_TIMER2_MPU_SHIFT 0
2494#define OMAP54XX_WKUPDEP_TIMER2_MPU_WIDTH 0x1
2495#define OMAP54XX_WKUPDEP_TIMER2_MPU_MASK (1 << 0)
2496
2497/* Used by PM_L4PER_TIMER3_WKDEP */
2498#define OMAP54XX_WKUPDEP_TIMER3_IPU_SHIFT 1
2499#define OMAP54XX_WKUPDEP_TIMER3_IPU_WIDTH 0x1
2500#define OMAP54XX_WKUPDEP_TIMER3_IPU_MASK (1 << 1)
2501
2502/* Used by PM_L4PER_TIMER3_WKDEP */
2503#define OMAP54XX_WKUPDEP_TIMER3_MPU_SHIFT 0
2504#define OMAP54XX_WKUPDEP_TIMER3_MPU_WIDTH 0x1
2505#define OMAP54XX_WKUPDEP_TIMER3_MPU_MASK (1 << 0)
2506
2507/* Used by PM_L4PER_TIMER4_WKDEP */
2508#define OMAP54XX_WKUPDEP_TIMER4_IPU_SHIFT 1
2509#define OMAP54XX_WKUPDEP_TIMER4_IPU_WIDTH 0x1
2510#define OMAP54XX_WKUPDEP_TIMER4_IPU_MASK (1 << 1)
2511
2512/* Used by PM_L4PER_TIMER4_WKDEP */
2513#define OMAP54XX_WKUPDEP_TIMER4_MPU_SHIFT 0
2514#define OMAP54XX_WKUPDEP_TIMER4_MPU_WIDTH 0x1
2515#define OMAP54XX_WKUPDEP_TIMER4_MPU_MASK (1 << 0)
2516
2517/* Used by PM_ABE_TIMER5_WKDEP */
2518#define OMAP54XX_WKUPDEP_TIMER5_DSP_SHIFT 2
2519#define OMAP54XX_WKUPDEP_TIMER5_DSP_WIDTH 0x1
2520#define OMAP54XX_WKUPDEP_TIMER5_DSP_MASK (1 << 2)
2521
2522/* Used by PM_ABE_TIMER5_WKDEP */
2523#define OMAP54XX_WKUPDEP_TIMER5_MPU_SHIFT 0
2524#define OMAP54XX_WKUPDEP_TIMER5_MPU_WIDTH 0x1
2525#define OMAP54XX_WKUPDEP_TIMER5_MPU_MASK (1 << 0)
2526
2527/* Used by PM_ABE_TIMER6_WKDEP */
2528#define OMAP54XX_WKUPDEP_TIMER6_DSP_SHIFT 2
2529#define OMAP54XX_WKUPDEP_TIMER6_DSP_WIDTH 0x1
2530#define OMAP54XX_WKUPDEP_TIMER6_DSP_MASK (1 << 2)
2531
2532/* Used by PM_ABE_TIMER6_WKDEP */
2533#define OMAP54XX_WKUPDEP_TIMER6_MPU_SHIFT 0
2534#define OMAP54XX_WKUPDEP_TIMER6_MPU_WIDTH 0x1
2535#define OMAP54XX_WKUPDEP_TIMER6_MPU_MASK (1 << 0)
2536
2537/* Used by PM_ABE_TIMER7_WKDEP */
2538#define OMAP54XX_WKUPDEP_TIMER7_DSP_SHIFT 2
2539#define OMAP54XX_WKUPDEP_TIMER7_DSP_WIDTH 0x1
2540#define OMAP54XX_WKUPDEP_TIMER7_DSP_MASK (1 << 2)
2541
2542/* Used by PM_ABE_TIMER7_WKDEP */
2543#define OMAP54XX_WKUPDEP_TIMER7_MPU_SHIFT 0
2544#define OMAP54XX_WKUPDEP_TIMER7_MPU_WIDTH 0x1
2545#define OMAP54XX_WKUPDEP_TIMER7_MPU_MASK (1 << 0)
2546
2547/* Used by PM_ABE_TIMER8_WKDEP */
2548#define OMAP54XX_WKUPDEP_TIMER8_DSP_SHIFT 2
2549#define OMAP54XX_WKUPDEP_TIMER8_DSP_WIDTH 0x1
2550#define OMAP54XX_WKUPDEP_TIMER8_DSP_MASK (1 << 2)
2551
2552/* Used by PM_ABE_TIMER8_WKDEP */
2553#define OMAP54XX_WKUPDEP_TIMER8_MPU_SHIFT 0
2554#define OMAP54XX_WKUPDEP_TIMER8_MPU_WIDTH 0x1
2555#define OMAP54XX_WKUPDEP_TIMER8_MPU_MASK (1 << 0)
2556
2557/* Used by PM_L4PER_TIMER9_WKDEP */
2558#define OMAP54XX_WKUPDEP_TIMER9_IPU_SHIFT 1
2559#define OMAP54XX_WKUPDEP_TIMER9_IPU_WIDTH 0x1
2560#define OMAP54XX_WKUPDEP_TIMER9_IPU_MASK (1 << 1)
2561
2562/* Used by PM_L4PER_TIMER9_WKDEP */
2563#define OMAP54XX_WKUPDEP_TIMER9_MPU_SHIFT 0
2564#define OMAP54XX_WKUPDEP_TIMER9_MPU_WIDTH 0x1
2565#define OMAP54XX_WKUPDEP_TIMER9_MPU_MASK (1 << 0)
2566
2567/* Used by PM_L4PER_UART1_WKDEP */
2568#define OMAP54XX_WKUPDEP_UART1_MPU_SHIFT 0
2569#define OMAP54XX_WKUPDEP_UART1_MPU_WIDTH 0x1
2570#define OMAP54XX_WKUPDEP_UART1_MPU_MASK (1 << 0)
2571
2572/* Used by PM_L4PER_UART1_WKDEP */
2573#define OMAP54XX_WKUPDEP_UART1_SDMA_SHIFT 3
2574#define OMAP54XX_WKUPDEP_UART1_SDMA_WIDTH 0x1
2575#define OMAP54XX_WKUPDEP_UART1_SDMA_MASK (1 << 3)
2576
2577/* Used by PM_L4PER_UART2_WKDEP */
2578#define OMAP54XX_WKUPDEP_UART2_MPU_SHIFT 0
2579#define OMAP54XX_WKUPDEP_UART2_MPU_WIDTH 0x1
2580#define OMAP54XX_WKUPDEP_UART2_MPU_MASK (1 << 0)
2581
2582/* Used by PM_L4PER_UART2_WKDEP */
2583#define OMAP54XX_WKUPDEP_UART2_SDMA_SHIFT 3
2584#define OMAP54XX_WKUPDEP_UART2_SDMA_WIDTH 0x1
2585#define OMAP54XX_WKUPDEP_UART2_SDMA_MASK (1 << 3)
2586
2587/* Used by PM_L4PER_UART3_WKDEP */
2588#define OMAP54XX_WKUPDEP_UART3_DSP_SHIFT 2
2589#define OMAP54XX_WKUPDEP_UART3_DSP_WIDTH 0x1
2590#define OMAP54XX_WKUPDEP_UART3_DSP_MASK (1 << 2)
2591
2592/* Used by PM_L4PER_UART3_WKDEP */
2593#define OMAP54XX_WKUPDEP_UART3_IPU_SHIFT 1
2594#define OMAP54XX_WKUPDEP_UART3_IPU_WIDTH 0x1
2595#define OMAP54XX_WKUPDEP_UART3_IPU_MASK (1 << 1)
2596
2597/* Used by PM_L4PER_UART3_WKDEP */
2598#define OMAP54XX_WKUPDEP_UART3_MPU_SHIFT 0
2599#define OMAP54XX_WKUPDEP_UART3_MPU_WIDTH 0x1
2600#define OMAP54XX_WKUPDEP_UART3_MPU_MASK (1 << 0)
2601
2602/* Used by PM_L4PER_UART3_WKDEP */
2603#define OMAP54XX_WKUPDEP_UART3_SDMA_SHIFT 3
2604#define OMAP54XX_WKUPDEP_UART3_SDMA_WIDTH 0x1
2605#define OMAP54XX_WKUPDEP_UART3_SDMA_MASK (1 << 3)
2606
2607/* Used by PM_L4PER_UART4_WKDEP */
2608#define OMAP54XX_WKUPDEP_UART4_MPU_SHIFT 0
2609#define OMAP54XX_WKUPDEP_UART4_MPU_WIDTH 0x1
2610#define OMAP54XX_WKUPDEP_UART4_MPU_MASK (1 << 0)
2611
2612/* Used by PM_L4PER_UART4_WKDEP */
2613#define OMAP54XX_WKUPDEP_UART4_SDMA_SHIFT 3
2614#define OMAP54XX_WKUPDEP_UART4_SDMA_WIDTH 0x1
2615#define OMAP54XX_WKUPDEP_UART4_SDMA_MASK (1 << 3)
2616
2617/* Used by PM_L4PER_UART5_WKDEP */
2618#define OMAP54XX_WKUPDEP_UART5_MPU_SHIFT 0
2619#define OMAP54XX_WKUPDEP_UART5_MPU_WIDTH 0x1
2620#define OMAP54XX_WKUPDEP_UART5_MPU_MASK (1 << 0)
2621
2622/* Used by PM_L4PER_UART5_WKDEP */
2623#define OMAP54XX_WKUPDEP_UART5_SDMA_SHIFT 3
2624#define OMAP54XX_WKUPDEP_UART5_SDMA_WIDTH 0x1
2625#define OMAP54XX_WKUPDEP_UART5_SDMA_MASK (1 << 3)
2626
2627/* Used by PM_L4PER_UART6_WKDEP */
2628#define OMAP54XX_WKUPDEP_UART6_MPU_SHIFT 0
2629#define OMAP54XX_WKUPDEP_UART6_MPU_WIDTH 0x1
2630#define OMAP54XX_WKUPDEP_UART6_MPU_MASK (1 << 0)
2631
2632/* Used by PM_L4PER_UART6_WKDEP */
2633#define OMAP54XX_WKUPDEP_UART6_SDMA_SHIFT 3
2634#define OMAP54XX_WKUPDEP_UART6_SDMA_WIDTH 0x1
2635#define OMAP54XX_WKUPDEP_UART6_SDMA_MASK (1 << 3)
2636
2637/* Used by PM_L3INIT_UNIPRO2_WKDEP */
2638#define OMAP54XX_WKUPDEP_UNIPRO2_MPU_SHIFT 0
2639#define OMAP54XX_WKUPDEP_UNIPRO2_MPU_WIDTH 0x1
2640#define OMAP54XX_WKUPDEP_UNIPRO2_MPU_MASK (1 << 0)
2641
2642/* Used by PM_L3INIT_USB_HOST_HS_WKDEP */
2643#define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_SHIFT 1
2644#define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_WIDTH 0x1
2645#define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_MASK (1 << 1)
2646
2647/* Used by PM_L3INIT_USB_HOST_HS_WKDEP */
2648#define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_SHIFT 0
2649#define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_WIDTH 0x1
2650#define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_MASK (1 << 0)
2651
2652/* Used by PM_L3INIT_USB_OTG_SS_WKDEP */
2653#define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_SHIFT 1
2654#define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_WIDTH 0x1
2655#define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_MASK (1 << 1)
2656
2657/* Used by PM_L3INIT_USB_OTG_SS_WKDEP */
2658#define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_SHIFT 0
2659#define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_WIDTH 0x1
2660#define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_MASK (1 << 0)
2661
2662/* Used by PM_L3INIT_USB_TLL_HS_WKDEP */
2663#define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_SHIFT 1
2664#define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_WIDTH 0x1
2665#define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_MASK (1 << 1)
2666
2667/* Used by PM_L3INIT_USB_TLL_HS_WKDEP */
2668#define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_SHIFT 0
2669#define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_WIDTH 0x1
2670#define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_MASK (1 << 0)
2671
2672/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */
2673#define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_SHIFT 0
2674#define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_WIDTH 0x1
2675#define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_MASK (1 << 0)
2676
2677/* Used by PM_ABE_WD_TIMER3_WKDEP */
2678#define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_SHIFT 0
2679#define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_WIDTH 0x1
2680#define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_MASK (1 << 0)
2681
2682/* Used by PRM_IO_PMCTRL */
2683#define OMAP54XX_WUCLK_CTRL_SHIFT 8
2684#define OMAP54XX_WUCLK_CTRL_WIDTH 0x1
2685#define OMAP54XX_WUCLK_CTRL_MASK (1 << 8)
2686
2687/* Used by PRM_IO_PMCTRL */
2688#define OMAP54XX_WUCLK_STATUS_SHIFT 9
2689#define OMAP54XX_WUCLK_STATUS_WIDTH 0x1
2690#define OMAP54XX_WUCLK_STATUS_MASK (1 << 9)
2691
2692/* Used by REVISION_PRM */
2693#define OMAP54XX_X_MAJOR_SHIFT 8
2694#define OMAP54XX_X_MAJOR_WIDTH 0x3
2695#define OMAP54XX_X_MAJOR_MASK (0x7 << 8)
2696
2697/* Used by REVISION_PRM */
2698#define OMAP54XX_Y_MINOR_SHIFT 0
2699#define OMAP54XX_Y_MINOR_WIDTH 0x6
2700#define OMAP54XX_Y_MINOR_MASK (0x3f << 0)
2701#endif
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
index 44c0d7216aa7..720440737744 100644
--- a/arch/arm/mach-omap2/prm33xx.c
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -320,6 +320,12 @@ static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm)
320 return 0; 320 return 0;
321} 321}
322 322
323static int am33xx_check_vcvp(void)
324{
325 /* No VC/VP on am33xx devices */
326 return 0;
327}
328
323struct pwrdm_ops am33xx_pwrdm_operations = { 329struct pwrdm_ops am33xx_pwrdm_operations = {
324 .pwrdm_set_next_pwrst = am33xx_pwrdm_set_next_pwrst, 330 .pwrdm_set_next_pwrst = am33xx_pwrdm_set_next_pwrst,
325 .pwrdm_read_next_pwrst = am33xx_pwrdm_read_next_pwrst, 331 .pwrdm_read_next_pwrst = am33xx_pwrdm_read_next_pwrst,
@@ -335,4 +341,5 @@ struct pwrdm_ops am33xx_pwrdm_operations = {
335 .pwrdm_set_mem_onst = am33xx_pwrdm_set_mem_onst, 341 .pwrdm_set_mem_onst = am33xx_pwrdm_set_mem_onst,
336 .pwrdm_set_mem_retst = am33xx_pwrdm_set_mem_retst, 342 .pwrdm_set_mem_retst = am33xx_pwrdm_set_mem_retst,
337 .pwrdm_wait_transition = am33xx_pwrdm_wait_transition, 343 .pwrdm_wait_transition = am33xx_pwrdm_wait_transition,
344 .pwrdm_has_voltdm = am33xx_check_vcvp,
338}; 345};
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 8ee1fbdec561..7db2422faa16 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -25,6 +25,7 @@
25#ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H 25#ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H
26#define __ARCH_ARM_MACH_OMAP2_PRM44XX_H 26#define __ARCH_ARM_MACH_OMAP2_PRM44XX_H
27 27
28#include "prm44xx_54xx.h"
28#include "prcm-common.h" 29#include "prcm-common.h"
29#include "prm.h" 30#include "prm.h"
30 31
@@ -744,36 +745,4 @@
744#define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8 745#define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8
745#define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8) 746#define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8)
746 747
747/* Function prototypes */
748# ifndef __ASSEMBLER__
749
750extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx);
751extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx);
752extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
753
754/* OMAP4-specific VP functions */
755u32 omap4_prm_vp_check_txdone(u8 vp_id);
756void omap4_prm_vp_clear_txdone(u8 vp_id);
757
758/*
759 * OMAP4 access functions for voltage controller (VC) and
760 * voltage proccessor (VP) in the PRM.
761 */
762extern u32 omap4_prm_vcvp_read(u8 offset);
763extern void omap4_prm_vcvp_write(u32 val, u8 offset);
764extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
765
766extern void omap44xx_prm_reconfigure_io_chain(void);
767
768/* PRM interrupt-related functions */
769extern void omap44xx_prm_read_pending_irqs(unsigned long *events);
770extern void omap44xx_prm_ocp_barrier(void);
771extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
772extern void omap44xx_prm_restore_irqen(u32 *saved_mask);
773
774extern int __init omap44xx_prm_init(void);
775extern u32 omap44xx_prm_get_reset_sources(void);
776
777# endif
778
779#endif 748#endif
diff --git a/arch/arm/mach-omap2/prm44xx_54xx.h b/arch/arm/mach-omap2/prm44xx_54xx.h
new file mode 100644
index 000000000000..7cd22abb8f15
--- /dev/null
+++ b/arch/arm/mach-omap2/prm44xx_54xx.h
@@ -0,0 +1,58 @@
1/*
2 * OMAP44xx and 54xx PRM common functions
3 *
4 * Copyright (C) 2009-2013 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 *
21 */
22
23#ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H
24#define __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H
25
26/* Function prototypes */
27#ifndef __ASSEMBLER__
28
29extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx);
30extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx);
31extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
32
33/* OMAP4/OMAP5-specific VP functions */
34u32 omap4_prm_vp_check_txdone(u8 vp_id);
35void omap4_prm_vp_clear_txdone(u8 vp_id);
36
37/*
38 * OMAP4/OMAP5 access functions for voltage controller (VC) and
39 * voltage proccessor (VP) in the PRM.
40 */
41extern u32 omap4_prm_vcvp_read(u8 offset);
42extern void omap4_prm_vcvp_write(u32 val, u8 offset);
43extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
44
45extern void omap44xx_prm_reconfigure_io_chain(void);
46
47/* PRM interrupt-related functions */
48extern void omap44xx_prm_read_pending_irqs(unsigned long *events);
49extern void omap44xx_prm_ocp_barrier(void);
50extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
51extern void omap44xx_prm_restore_irqen(u32 *saved_mask);
52
53extern int __init omap44xx_prm_init(void);
54extern u32 omap44xx_prm_get_reset_sources(void);
55
56#endif
57
58#endif
diff --git a/arch/arm/mach-omap2/prm54xx.h b/arch/arm/mach-omap2/prm54xx.h
new file mode 100644
index 000000000000..e4411010309c
--- /dev/null
+++ b/arch/arm/mach-omap2/prm54xx.h
@@ -0,0 +1,421 @@
1/*
2 * OMAP54xx PRM instance offset macros
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley (paul@pwsan.com)
7 * Rajendra Nayak (rnayak@ti.com)
8 * Benoit Cousson (b-cousson@ti.com)
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#ifndef __ARCH_ARM_MACH_OMAP2_PRM54XX_H
22#define __ARCH_ARM_MACH_OMAP2_PRM54XX_H
23
24#include "prm44xx_54xx.h"
25#include "prcm-common.h"
26#include "prm.h"
27
28#define OMAP54XX_PRM_BASE 0x4ae06000
29
30#define OMAP54XX_PRM_REGADDR(inst, reg) \
31 OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE + (inst) + (reg))
32
33
34/* PRM instances */
35#define OMAP54XX_PRM_OCP_SOCKET_INST 0x0000
36#define OMAP54XX_PRM_CKGEN_INST 0x0100
37#define OMAP54XX_PRM_MPU_INST 0x0300
38#define OMAP54XX_PRM_DSP_INST 0x0400
39#define OMAP54XX_PRM_ABE_INST 0x0500
40#define OMAP54XX_PRM_COREAON_INST 0x0600
41#define OMAP54XX_PRM_CORE_INST 0x0700
42#define OMAP54XX_PRM_IVA_INST 0x1200
43#define OMAP54XX_PRM_CAM_INST 0x1300
44#define OMAP54XX_PRM_DSS_INST 0x1400
45#define OMAP54XX_PRM_GPU_INST 0x1500
46#define OMAP54XX_PRM_L3INIT_INST 0x1600
47#define OMAP54XX_PRM_CUSTEFUSE_INST 0x1700
48#define OMAP54XX_PRM_WKUPAON_INST 0x1800
49#define OMAP54XX_PRM_WKUPAON_CM_INST 0x1900
50#define OMAP54XX_PRM_EMU_INST 0x1a00
51#define OMAP54XX_PRM_EMU_CM_INST 0x1b00
52#define OMAP54XX_PRM_DEVICE_INST 0x1c00
53#define OMAP54XX_PRM_INSTR_INST 0x1f00
54
55/* PRM clockdomain register offsets (from instance start) */
56#define OMAP54XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS 0x0000
57#define OMAP54XX_PRM_EMU_CM_EMU_CDOFFS 0x0000
58
59/* PRM */
60
61/* PRM.OCP_SOCKET_PRM register offsets */
62#define OMAP54XX_REVISION_PRM_OFFSET 0x0000
63#define OMAP54XX_PRM_IRQSTATUS_MPU_OFFSET 0x0010
64#define OMAP54XX_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014
65#define OMAP54XX_PRM_IRQENABLE_MPU_OFFSET 0x0018
66#define OMAP54XX_PRM_IRQENABLE_MPU_2_OFFSET 0x001c
67#define OMAP54XX_PRM_IRQSTATUS_IPU_OFFSET 0x0020
68#define OMAP54XX_PRM_IRQENABLE_IPU_OFFSET 0x0028
69#define OMAP54XX_PRM_IRQSTATUS_DSP_OFFSET 0x0030
70#define OMAP54XX_PRM_IRQENABLE_DSP_OFFSET 0x0038
71#define OMAP54XX_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040
72#define OMAP54XX_CM_PRM_PROFILING_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_OCP_SOCKET_INST, 0x0040)
73#define OMAP54XX_PRM_DEBUG_OUT_OFFSET 0x0084
74#define OMAP54XX_PRM_DEBUG_TRANS_CFG_OFFSET 0x0090
75#define OMAP54XX_PRM_DEBUG_OFF_TRANS_OFFSET 0x0094
76#define OMAP54XX_PRM_DEBUG_CORE_RET_TRANS_OFFSET 0x0098
77#define OMAP54XX_PRM_DEBUG_MPU_RET_TRANS_OFFSET 0x009c
78#define OMAP54XX_PRM_DEBUG_MM_RET_TRANS_OFFSET 0x00a0
79#define OMAP54XX_PRM_DEBUG_WKUPAON_FD_TRANS_OFFSET 0x00a4
80
81/* PRM.CKGEN_PRM register offsets */
82#define OMAP54XX_CM_CLKSEL_ABE_DSS_SYS_OFFSET 0x0000
83#define OMAP54XX_CM_CLKSEL_ABE_DSS_SYS OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0000)
84#define OMAP54XX_CM_CLKSEL_WKUPAON_OFFSET 0x0008
85#define OMAP54XX_CM_CLKSEL_WKUPAON OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0008)
86#define OMAP54XX_CM_CLKSEL_ABE_PLL_REF_OFFSET 0x000c
87#define OMAP54XX_CM_CLKSEL_ABE_PLL_REF OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x000c)
88#define OMAP54XX_CM_CLKSEL_SYS_OFFSET 0x0010
89#define OMAP54XX_CM_CLKSEL_SYS OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0010)
90
91/* PRM.MPU_PRM register offsets */
92#define OMAP54XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000
93#define OMAP54XX_PM_MPU_PWRSTST_OFFSET 0x0004
94#define OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET 0x0024
95
96/* PRM.DSP_PRM register offsets */
97#define OMAP54XX_PM_DSP_PWRSTCTRL_OFFSET 0x0000
98#define OMAP54XX_PM_DSP_PWRSTST_OFFSET 0x0004
99#define OMAP54XX_RM_DSP_RSTCTRL_OFFSET 0x0010
100#define OMAP54XX_RM_DSP_RSTST_OFFSET 0x0014
101#define OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET 0x0024
102
103/* PRM.ABE_PRM register offsets */
104#define OMAP54XX_PM_ABE_PWRSTCTRL_OFFSET 0x0000
105#define OMAP54XX_PM_ABE_PWRSTST_OFFSET 0x0004
106#define OMAP54XX_RM_ABE_AESS_CONTEXT_OFFSET 0x002c
107#define OMAP54XX_PM_ABE_MCPDM_WKDEP_OFFSET 0x0030
108#define OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET 0x0034
109#define OMAP54XX_PM_ABE_DMIC_WKDEP_OFFSET 0x0038
110#define OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET 0x003c
111#define OMAP54XX_PM_ABE_MCASP_WKDEP_OFFSET 0x0040
112#define OMAP54XX_RM_ABE_MCASP_CONTEXT_OFFSET 0x0044
113#define OMAP54XX_PM_ABE_MCBSP1_WKDEP_OFFSET 0x0048
114#define OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET 0x004c
115#define OMAP54XX_PM_ABE_MCBSP2_WKDEP_OFFSET 0x0050
116#define OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET 0x0054
117#define OMAP54XX_PM_ABE_MCBSP3_WKDEP_OFFSET 0x0058
118#define OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET 0x005c
119#define OMAP54XX_PM_ABE_SLIMBUS1_WKDEP_OFFSET 0x0060
120#define OMAP54XX_RM_ABE_SLIMBUS1_CONTEXT_OFFSET 0x0064
121#define OMAP54XX_PM_ABE_TIMER5_WKDEP_OFFSET 0x0068
122#define OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET 0x006c
123#define OMAP54XX_PM_ABE_TIMER6_WKDEP_OFFSET 0x0070
124#define OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET 0x0074
125#define OMAP54XX_PM_ABE_TIMER7_WKDEP_OFFSET 0x0078
126#define OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET 0x007c
127#define OMAP54XX_PM_ABE_TIMER8_WKDEP_OFFSET 0x0080
128#define OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET 0x0084
129#define OMAP54XX_PM_ABE_WD_TIMER3_WKDEP_OFFSET 0x0088
130#define OMAP54XX_RM_ABE_WD_TIMER3_CONTEXT_OFFSET 0x008c
131
132/* PRM.COREAON_PRM register offsets */
133#define OMAP54XX_PM_COREAON_SMARTREFLEX_MPU_WKDEP_OFFSET 0x0028
134#define OMAP54XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET 0x002c
135#define OMAP54XX_PM_COREAON_SMARTREFLEX_MM_WKDEP_OFFSET 0x0030
136#define OMAP54XX_RM_COREAON_SMARTREFLEX_MM_CONTEXT_OFFSET 0x0034
137#define OMAP54XX_PM_COREAON_SMARTREFLEX_CORE_WKDEP_OFFSET 0x0038
138#define OMAP54XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET 0x003c
139
140/* PRM.CORE_PRM register offsets */
141#define OMAP54XX_PM_CORE_PWRSTCTRL_OFFSET 0x0000
142#define OMAP54XX_PM_CORE_PWRSTST_OFFSET 0x0004
143#define OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET 0x0024
144#define OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET 0x0124
145#define OMAP54XX_RM_L3MAIN2_GPMC_CONTEXT_OFFSET 0x012c
146#define OMAP54XX_RM_L3MAIN2_OCMC_RAM_CONTEXT_OFFSET 0x0134
147#define OMAP54XX_RM_IPU_RSTCTRL_OFFSET 0x0210
148#define OMAP54XX_RM_IPU_RSTST_OFFSET 0x0214
149#define OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET 0x0224
150#define OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET 0x0324
151#define OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET 0x0424
152#define OMAP54XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET 0x042c
153#define OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET 0x0434
154#define OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET 0x043c
155#define OMAP54XX_RM_EMIF_EMIF_DLL_CONTEXT_OFFSET 0x0444
156#define OMAP54XX_RM_C2C_C2C_CONTEXT_OFFSET 0x0524
157#define OMAP54XX_RM_C2C_MODEM_ICR_CONTEXT_OFFSET 0x052c
158#define OMAP54XX_RM_C2C_C2C_OCP_FW_CONTEXT_OFFSET 0x0534
159#define OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624
160#define OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET 0x062c
161#define OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET 0x0634
162#define OMAP54XX_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET 0x063c
163#define OMAP54XX_RM_L4CFG_OCP2SCP2_CONTEXT_OFFSET 0x0644
164#define OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET 0x0724
165#define OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET 0x072c
166#define OMAP54XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET 0x0744
167#define OMAP54XX_RM_MIPIEXT_LLI_CONTEXT_OFFSET 0x0824
168#define OMAP54XX_RM_MIPIEXT_LLI_OCP_FW_CONTEXT_OFFSET 0x082c
169#define OMAP54XX_RM_MIPIEXT_MPHY_CONTEXT_OFFSET 0x0834
170#define OMAP54XX_PM_L4PER_TIMER10_WKDEP_OFFSET 0x0928
171#define OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET 0x092c
172#define OMAP54XX_PM_L4PER_TIMER11_WKDEP_OFFSET 0x0930
173#define OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET 0x0934
174#define OMAP54XX_PM_L4PER_TIMER2_WKDEP_OFFSET 0x0938
175#define OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET 0x093c
176#define OMAP54XX_PM_L4PER_TIMER3_WKDEP_OFFSET 0x0940
177#define OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET 0x0944
178#define OMAP54XX_PM_L4PER_TIMER4_WKDEP_OFFSET 0x0948
179#define OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET 0x094c
180#define OMAP54XX_PM_L4PER_TIMER9_WKDEP_OFFSET 0x0950
181#define OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET 0x0954
182#define OMAP54XX_RM_L4PER_ELM_CONTEXT_OFFSET 0x095c
183#define OMAP54XX_PM_L4PER_GPIO2_WKDEP_OFFSET 0x0960
184#define OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET 0x0964
185#define OMAP54XX_PM_L4PER_GPIO3_WKDEP_OFFSET 0x0968
186#define OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET 0x096c
187#define OMAP54XX_PM_L4PER_GPIO4_WKDEP_OFFSET 0x0970
188#define OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET 0x0974
189#define OMAP54XX_PM_L4PER_GPIO5_WKDEP_OFFSET 0x0978
190#define OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET 0x097c
191#define OMAP54XX_PM_L4PER_GPIO6_WKDEP_OFFSET 0x0980
192#define OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET 0x0984
193#define OMAP54XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET 0x098c
194#define OMAP54XX_PM_L4PER_I2C1_WKDEP_OFFSET 0x09a0
195#define OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET 0x09a4
196#define OMAP54XX_PM_L4PER_I2C2_WKDEP_OFFSET 0x09a8
197#define OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET 0x09ac
198#define OMAP54XX_PM_L4PER_I2C3_WKDEP_OFFSET 0x09b0
199#define OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET 0x09b4
200#define OMAP54XX_PM_L4PER_I2C4_WKDEP_OFFSET 0x09b8
201#define OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET 0x09bc
202#define OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET 0x09c0
203#define OMAP54XX_PM_L4PER_MCSPI1_WKDEP_OFFSET 0x09f0
204#define OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET 0x09f4
205#define OMAP54XX_PM_L4PER_MCSPI2_WKDEP_OFFSET 0x09f8
206#define OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET 0x09fc
207#define OMAP54XX_PM_L4PER_MCSPI3_WKDEP_OFFSET 0x0a00
208#define OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET 0x0a04
209#define OMAP54XX_PM_L4PER_MCSPI4_WKDEP_OFFSET 0x0a08
210#define OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET 0x0a0c
211#define OMAP54XX_PM_L4PER_GPIO7_WKDEP_OFFSET 0x0a10
212#define OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET 0x0a14
213#define OMAP54XX_PM_L4PER_GPIO8_WKDEP_OFFSET 0x0a18
214#define OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET 0x0a1c
215#define OMAP54XX_PM_L4PER_MMC3_WKDEP_OFFSET 0x0a20
216#define OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET 0x0a24
217#define OMAP54XX_PM_L4PER_MMC4_WKDEP_OFFSET 0x0a28
218#define OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET 0x0a2c
219#define OMAP54XX_PM_L4PER_UART1_WKDEP_OFFSET 0x0a40
220#define OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET 0x0a44
221#define OMAP54XX_PM_L4PER_UART2_WKDEP_OFFSET 0x0a48
222#define OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET 0x0a4c
223#define OMAP54XX_PM_L4PER_UART3_WKDEP_OFFSET 0x0a50
224#define OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET 0x0a54
225#define OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET 0x0a58
226#define OMAP54XX_PM_L4PER_UART4_WKDEP_OFFSET 0x0a5c
227#define OMAP54XX_PM_L4PER_MMC5_WKDEP_OFFSET 0x0a60
228#define OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET 0x0a64
229#define OMAP54XX_PM_L4PER_I2C5_WKDEP_OFFSET 0x0a68
230#define OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET 0x0a6c
231#define OMAP54XX_PM_L4PER_UART5_WKDEP_OFFSET 0x0a70
232#define OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET 0x0a74
233#define OMAP54XX_PM_L4PER_UART6_WKDEP_OFFSET 0x0a78
234#define OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET 0x0a7c
235#define OMAP54XX_RM_L4SEC_AES1_CONTEXT_OFFSET 0x0aa4
236#define OMAP54XX_RM_L4SEC_AES2_CONTEXT_OFFSET 0x0aac
237#define OMAP54XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET 0x0ab4
238#define OMAP54XX_RM_L4SEC_FPKA_CONTEXT_OFFSET 0x0abc
239#define OMAP54XX_RM_L4SEC_RNG_CONTEXT_OFFSET 0x0ac4
240#define OMAP54XX_RM_L4SEC_SHA2MD5_CONTEXT_OFFSET 0x0acc
241#define OMAP54XX_RM_L4SEC_DMA_CRYPTO_CONTEXT_OFFSET 0x0adc
242
243/* PRM.IVA_PRM register offsets */
244#define OMAP54XX_PM_IVA_PWRSTCTRL_OFFSET 0x0000
245#define OMAP54XX_PM_IVA_PWRSTST_OFFSET 0x0004
246#define OMAP54XX_RM_IVA_RSTCTRL_OFFSET 0x0010
247#define OMAP54XX_RM_IVA_RSTST_OFFSET 0x0014
248#define OMAP54XX_RM_IVA_IVA_CONTEXT_OFFSET 0x0024
249#define OMAP54XX_RM_IVA_SL2_CONTEXT_OFFSET 0x002c
250
251/* PRM.CAM_PRM register offsets */
252#define OMAP54XX_PM_CAM_PWRSTCTRL_OFFSET 0x0000
253#define OMAP54XX_PM_CAM_PWRSTST_OFFSET 0x0004
254#define OMAP54XX_RM_CAM_ISS_CONTEXT_OFFSET 0x0024
255#define OMAP54XX_RM_CAM_FDIF_CONTEXT_OFFSET 0x002c
256#define OMAP54XX_RM_CAM_CAL_CONTEXT_OFFSET 0x0034
257
258/* PRM.DSS_PRM register offsets */
259#define OMAP54XX_PM_DSS_PWRSTCTRL_OFFSET 0x0000
260#define OMAP54XX_PM_DSS_PWRSTST_OFFSET 0x0004
261#define OMAP54XX_PM_DSS_DSS_WKDEP_OFFSET 0x0020
262#define OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET 0x0024
263#define OMAP54XX_RM_DSS_BB2D_CONTEXT_OFFSET 0x0034
264
265/* PRM.GPU_PRM register offsets */
266#define OMAP54XX_PM_GPU_PWRSTCTRL_OFFSET 0x0000
267#define OMAP54XX_PM_GPU_PWRSTST_OFFSET 0x0004
268#define OMAP54XX_RM_GPU_GPU_CONTEXT_OFFSET 0x0024
269
270/* PRM.L3INIT_PRM register offsets */
271#define OMAP54XX_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000
272#define OMAP54XX_PM_L3INIT_PWRSTST_OFFSET 0x0004
273#define OMAP54XX_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028
274#define OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c
275#define OMAP54XX_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030
276#define OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET 0x0034
277#define OMAP54XX_PM_L3INIT_HSI_WKDEP_OFFSET 0x0038
278#define OMAP54XX_RM_L3INIT_HSI_CONTEXT_OFFSET 0x003c
279#define OMAP54XX_PM_L3INIT_UNIPRO2_WKDEP_OFFSET 0x0040
280#define OMAP54XX_RM_L3INIT_UNIPRO2_CONTEXT_OFFSET 0x0044
281#define OMAP54XX_PM_L3INIT_USB_HOST_HS_WKDEP_OFFSET 0x0058
282#define OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET 0x005c
283#define OMAP54XX_PM_L3INIT_USB_TLL_HS_WKDEP_OFFSET 0x0068
284#define OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET 0x006c
285#define OMAP54XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c
286#define OMAP54XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088
287#define OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c
288#define OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET 0x00e4
289#define OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET 0x00ec
290#define OMAP54XX_PM_L3INIT_USB_OTG_SS_WKDEP_OFFSET 0x00f0
291#define OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET 0x00f4
292
293/* PRM.CUSTEFUSE_PRM register offsets */
294#define OMAP54XX_PM_CUSTEFUSE_PWRSTCTRL_OFFSET 0x0000
295#define OMAP54XX_PM_CUSTEFUSE_PWRSTST_OFFSET 0x0004
296#define OMAP54XX_RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT_OFFSET 0x0024
297
298/* PRM.WKUPAON_PRM register offsets */
299#define OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET 0x0024
300#define OMAP54XX_RM_WKUPAON_WD_TIMER1_CONTEXT_OFFSET 0x002c
301#define OMAP54XX_PM_WKUPAON_WD_TIMER2_WKDEP_OFFSET 0x0030
302#define OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET 0x0034
303#define OMAP54XX_PM_WKUPAON_GPIO1_WKDEP_OFFSET 0x0038
304#define OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET 0x003c
305#define OMAP54XX_PM_WKUPAON_TIMER1_WKDEP_OFFSET 0x0040
306#define OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET 0x0044
307#define OMAP54XX_PM_WKUPAON_TIMER12_WKDEP_OFFSET 0x0048
308#define OMAP54XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET 0x004c
309#define OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET 0x0054
310#define OMAP54XX_RM_WKUPAON_SAR_RAM_CONTEXT_OFFSET 0x0064
311#define OMAP54XX_PM_WKUPAON_KBD_WKDEP_OFFSET 0x0078
312#define OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET 0x007c
313
314/* PRM.WKUPAON_CM register offsets */
315#define OMAP54XX_CM_WKUPAON_CLKSTCTRL_OFFSET 0x0000
316#define OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET 0x0020
317#define OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0020)
318#define OMAP54XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET 0x0028
319#define OMAP54XX_CM_WKUPAON_WD_TIMER1_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0028)
320#define OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET 0x0030
321#define OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0030)
322#define OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET 0x0038
323#define OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0038)
324#define OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET 0x0040
325#define OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0040)
326#define OMAP54XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET 0x0048
327#define OMAP54XX_CM_WKUPAON_TIMER12_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0048)
328#define OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET 0x0050
329#define OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0050)
330#define OMAP54XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET 0x0060
331#define OMAP54XX_CM_WKUPAON_SAR_RAM_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0060)
332#define OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET 0x0078
333#define OMAP54XX_CM_WKUPAON_KBD_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0078)
334#define OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET 0x0090
335#define OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0090)
336#define OMAP54XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0098
337#define OMAP54XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0098)
338
339/* PRM.EMU_PRM register offsets */
340#define OMAP54XX_PM_EMU_PWRSTCTRL_OFFSET 0x0000
341#define OMAP54XX_PM_EMU_PWRSTST_OFFSET 0x0004
342#define OMAP54XX_RM_EMU_DEBUGSS_CONTEXT_OFFSET 0x0024
343
344/* PRM.EMU_CM register offsets */
345#define OMAP54XX_CM_EMU_CLKSTCTRL_OFFSET 0x0000
346#define OMAP54XX_CM_EMU_DYNAMICDEP_OFFSET 0x0008
347#define OMAP54XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0020
348#define OMAP54XX_CM_EMU_DEBUGSS_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_EMU_CM_INST, 0x0020)
349#define OMAP54XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET 0x0028
350#define OMAP54XX_CM_EMU_MPU_EMU_DBG_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_EMU_CM_INST, 0x0028)
351
352/* PRM.DEVICE_PRM register offsets */
353#define OMAP54XX_PRM_RSTCTRL_OFFSET 0x0000
354#define OMAP54XX_PRM_RSTST_OFFSET 0x0004
355#define OMAP54XX_PRM_RSTTIME_OFFSET 0x0008
356#define OMAP54XX_PRM_CLKREQCTRL_OFFSET 0x000c
357#define OMAP54XX_PRM_VOLTCTRL_OFFSET 0x0010
358#define OMAP54XX_PRM_PWRREQCTRL_OFFSET 0x0014
359#define OMAP54XX_PRM_PSCON_COUNT_OFFSET 0x0018
360#define OMAP54XX_PRM_IO_COUNT_OFFSET 0x001c
361#define OMAP54XX_PRM_IO_PMCTRL_OFFSET 0x0020
362#define OMAP54XX_PRM_VOLTSETUP_WARMRESET_OFFSET 0x0024
363#define OMAP54XX_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028
364#define OMAP54XX_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c
365#define OMAP54XX_PRM_VOLTSETUP_MM_OFF_OFFSET 0x0030
366#define OMAP54XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034
367#define OMAP54XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038
368#define OMAP54XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET 0x003c
369#define OMAP54XX_PRM_VP_CORE_CONFIG_OFFSET 0x0040
370#define OMAP54XX_PRM_VP_CORE_STATUS_OFFSET 0x0044
371#define OMAP54XX_PRM_VP_CORE_VLIMITTO_OFFSET 0x0048
372#define OMAP54XX_PRM_VP_CORE_VOLTAGE_OFFSET 0x004c
373#define OMAP54XX_PRM_VP_CORE_VSTEPMAX_OFFSET 0x0050
374#define OMAP54XX_PRM_VP_CORE_VSTEPMIN_OFFSET 0x0054
375#define OMAP54XX_PRM_VP_MPU_CONFIG_OFFSET 0x0058
376#define OMAP54XX_PRM_VP_MPU_STATUS_OFFSET 0x005c
377#define OMAP54XX_PRM_VP_MPU_VLIMITTO_OFFSET 0x0060
378#define OMAP54XX_PRM_VP_MPU_VOLTAGE_OFFSET 0x0064
379#define OMAP54XX_PRM_VP_MPU_VSTEPMAX_OFFSET 0x0068
380#define OMAP54XX_PRM_VP_MPU_VSTEPMIN_OFFSET 0x006c
381#define OMAP54XX_PRM_VP_MM_CONFIG_OFFSET 0x0070
382#define OMAP54XX_PRM_VP_MM_STATUS_OFFSET 0x0074
383#define OMAP54XX_PRM_VP_MM_VLIMITTO_OFFSET 0x0078
384#define OMAP54XX_PRM_VP_MM_VOLTAGE_OFFSET 0x007c
385#define OMAP54XX_PRM_VP_MM_VSTEPMAX_OFFSET 0x0080
386#define OMAP54XX_PRM_VP_MM_VSTEPMIN_OFFSET 0x0084
387#define OMAP54XX_PRM_VC_SMPS_CORE_CONFIG_OFFSET 0x0088
388#define OMAP54XX_PRM_VC_SMPS_MM_CONFIG_OFFSET 0x008c
389#define OMAP54XX_PRM_VC_SMPS_MPU_CONFIG_OFFSET 0x0090
390#define OMAP54XX_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET 0x0094
391#define OMAP54XX_PRM_VC_VAL_CMD_VDD_MM_L_OFFSET 0x0098
392#define OMAP54XX_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET 0x009c
393#define OMAP54XX_PRM_VC_VAL_BYPASS_OFFSET 0x00a0
394#define OMAP54XX_PRM_VC_CORE_ERRST_OFFSET 0x00a4
395#define OMAP54XX_PRM_VC_MM_ERRST_OFFSET 0x00a8
396#define OMAP54XX_PRM_VC_MPU_ERRST_OFFSET 0x00ac
397#define OMAP54XX_PRM_VC_BYPASS_ERRST_OFFSET 0x00b0
398#define OMAP54XX_PRM_VC_CFG_I2C_MODE_OFFSET 0x00b4
399#define OMAP54XX_PRM_VC_CFG_I2C_CLK_OFFSET 0x00b8
400#define OMAP54XX_PRM_SRAM_COUNT_OFFSET 0x00bc
401#define OMAP54XX_PRM_SRAM_WKUP_SETUP_OFFSET 0x00c0
402#define OMAP54XX_PRM_SLDO_CORE_SETUP_OFFSET 0x00c4
403#define OMAP54XX_PRM_SLDO_CORE_CTRL_OFFSET 0x00c8
404#define OMAP54XX_PRM_SLDO_MPU_SETUP_OFFSET 0x00cc
405#define OMAP54XX_PRM_SLDO_MPU_CTRL_OFFSET 0x00d0
406#define OMAP54XX_PRM_SLDO_MM_SETUP_OFFSET 0x00d4
407#define OMAP54XX_PRM_SLDO_MM_CTRL_OFFSET 0x00d8
408#define OMAP54XX_PRM_ABBLDO_MPU_SETUP_OFFSET 0x00dc
409#define OMAP54XX_PRM_ABBLDO_MPU_CTRL_OFFSET 0x00e0
410#define OMAP54XX_PRM_ABBLDO_MM_SETUP_OFFSET 0x00e4
411#define OMAP54XX_PRM_ABBLDO_MM_CTRL_OFFSET 0x00e8
412#define OMAP54XX_PRM_BANDGAP_SETUP_OFFSET 0x00ec
413#define OMAP54XX_PRM_DEVICE_OFF_CTRL_OFFSET 0x00f0
414#define OMAP54XX_PRM_PHASE1_CNDP_OFFSET 0x00f4
415#define OMAP54XX_PRM_PHASE2A_CNDP_OFFSET 0x00f8
416#define OMAP54XX_PRM_PHASE2B_CNDP_OFFSET 0x00fc
417#define OMAP54XX_PRM_MODEM_IF_CTRL_OFFSET 0x0100
418#define OMAP54XX_PRM_VOLTST_MPU_OFFSET 0x0110
419#define OMAP54XX_PRM_VOLTST_MM_OFFSET 0x0114
420
421#endif
diff --git a/arch/arm/mach-omap2/scrm54xx.h b/arch/arm/mach-omap2/scrm54xx.h
new file mode 100644
index 000000000000..57e86c8f8239
--- /dev/null
+++ b/arch/arm/mach-omap2/scrm54xx.h
@@ -0,0 +1,231 @@
1/*
2 * OMAP54XX SCRM registers and bitfields
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Benoit Cousson (b-cousson@ti.com)
7 *
8 * This file is automatically generated from the OMAP hardware databases.
9 * We respectfully ask that any modifications to this file be coordinated
10 * with the public linux-omap@vger.kernel.org mailing list and the
11 * authors above to ensure that the autogeneration scripts are kept
12 * up-to-date with the file contents.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#ifndef __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H
20#define __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H
21
22#define OMAP5_SCRM_BASE 0x4ae0a000
23
24#define OMAP54XX_SCRM_REGADDR(reg) \
25 OMAP2_L4_IO_ADDRESS(OMAP5_SCRM_BASE + (reg))
26
27/* SCRM */
28
29/* SCRM.SCRM register offsets */
30#define OMAP5_SCRM_REVISION_SCRM_OFFSET 0x0000
31#define OMAP5_SCRM_REVISION_SCRM OMAP54XX_SCRM_REGADDR(0x0000)
32#define OMAP5_SCRM_CLKSETUPTIME_OFFSET 0x0100
33#define OMAP5_SCRM_CLKSETUPTIME OMAP54XX_SCRM_REGADDR(0x0100)
34#define OMAP5_SCRM_PMICSETUPTIME_OFFSET 0x0104
35#define OMAP5_SCRM_PMICSETUPTIME OMAP54XX_SCRM_REGADDR(0x0104)
36#define OMAP5_SCRM_ALTCLKSRC_OFFSET 0x0110
37#define OMAP5_SCRM_ALTCLKSRC OMAP54XX_SCRM_REGADDR(0x0110)
38#define OMAP5_SCRM_MODEMCLKM_OFFSET 0x0118
39#define OMAP5_SCRM_MODEMCLKM OMAP54XX_SCRM_REGADDR(0x0118)
40#define OMAP5_SCRM_D2DCLKM_OFFSET 0x011c
41#define OMAP5_SCRM_D2DCLKM OMAP54XX_SCRM_REGADDR(0x011c)
42#define OMAP5_SCRM_EXTCLKREQ_OFFSET 0x0200
43#define OMAP5_SCRM_EXTCLKREQ OMAP54XX_SCRM_REGADDR(0x0200)
44#define OMAP5_SCRM_ACCCLKREQ_OFFSET 0x0204
45#define OMAP5_SCRM_ACCCLKREQ OMAP54XX_SCRM_REGADDR(0x0204)
46#define OMAP5_SCRM_PWRREQ_OFFSET 0x0208
47#define OMAP5_SCRM_PWRREQ OMAP54XX_SCRM_REGADDR(0x0208)
48#define OMAP5_SCRM_AUXCLKREQ0_OFFSET 0x0210
49#define OMAP5_SCRM_AUXCLKREQ0 OMAP54XX_SCRM_REGADDR(0x0210)
50#define OMAP5_SCRM_AUXCLKREQ1_OFFSET 0x0214
51#define OMAP5_SCRM_AUXCLKREQ1 OMAP54XX_SCRM_REGADDR(0x0214)
52#define OMAP5_SCRM_AUXCLKREQ2_OFFSET 0x0218
53#define OMAP5_SCRM_AUXCLKREQ2 OMAP54XX_SCRM_REGADDR(0x0218)
54#define OMAP5_SCRM_AUXCLKREQ3_OFFSET 0x021c
55#define OMAP5_SCRM_AUXCLKREQ3 OMAP54XX_SCRM_REGADDR(0x021c)
56#define OMAP5_SCRM_AUXCLKREQ4_OFFSET 0x0220
57#define OMAP5_SCRM_AUXCLKREQ4 OMAP54XX_SCRM_REGADDR(0x0220)
58#define OMAP5_SCRM_AUXCLKREQ5_OFFSET 0x0224
59#define OMAP5_SCRM_AUXCLKREQ5 OMAP54XX_SCRM_REGADDR(0x0224)
60#define OMAP5_SCRM_D2DCLKREQ_OFFSET 0x0234
61#define OMAP5_SCRM_D2DCLKREQ OMAP54XX_SCRM_REGADDR(0x0234)
62#define OMAP5_SCRM_AUXCLK0_OFFSET 0x0310
63#define OMAP5_SCRM_AUXCLK0 OMAP54XX_SCRM_REGADDR(0x0310)
64#define OMAP5_SCRM_AUXCLK1_OFFSET 0x0314
65#define OMAP5_SCRM_AUXCLK1 OMAP54XX_SCRM_REGADDR(0x0314)
66#define OMAP5_SCRM_AUXCLK2_OFFSET 0x0318
67#define OMAP5_SCRM_AUXCLK2 OMAP54XX_SCRM_REGADDR(0x0318)
68#define OMAP5_SCRM_AUXCLK3_OFFSET 0x031c
69#define OMAP5_SCRM_AUXCLK3 OMAP54XX_SCRM_REGADDR(0x031c)
70#define OMAP5_SCRM_AUXCLK4_OFFSET 0x0320
71#define OMAP5_SCRM_AUXCLK4 OMAP54XX_SCRM_REGADDR(0x0320)
72#define OMAP5_SCRM_AUXCLK5_OFFSET 0x0324
73#define OMAP5_SCRM_AUXCLK5 OMAP54XX_SCRM_REGADDR(0x0324)
74#define OMAP5_SCRM_RSTTIME_OFFSET 0x0400
75#define OMAP5_SCRM_RSTTIME OMAP54XX_SCRM_REGADDR(0x0400)
76#define OMAP5_SCRM_MODEMRSTCTRL_OFFSET 0x0418
77#define OMAP5_SCRM_MODEMRSTCTRL OMAP54XX_SCRM_REGADDR(0x0418)
78#define OMAP5_SCRM_D2DRSTCTRL_OFFSET 0x041c
79#define OMAP5_SCRM_D2DRSTCTRL OMAP54XX_SCRM_REGADDR(0x041c)
80#define OMAP5_SCRM_EXTPWRONRSTCTRL_OFFSET 0x0420
81#define OMAP5_SCRM_EXTPWRONRSTCTRL OMAP54XX_SCRM_REGADDR(0x0420)
82#define OMAP5_SCRM_EXTWARMRSTST_OFFSET 0x0510
83#define OMAP5_SCRM_EXTWARMRSTST OMAP54XX_SCRM_REGADDR(0x0510)
84#define OMAP5_SCRM_APEWARMRSTST_OFFSET 0x0514
85#define OMAP5_SCRM_APEWARMRSTST OMAP54XX_SCRM_REGADDR(0x0514)
86#define OMAP5_SCRM_MODEMWARMRSTST_OFFSET 0x0518
87#define OMAP5_SCRM_MODEMWARMRSTST OMAP54XX_SCRM_REGADDR(0x0518)
88#define OMAP5_SCRM_D2DWARMRSTST_OFFSET 0x051c
89#define OMAP5_SCRM_D2DWARMRSTST OMAP54XX_SCRM_REGADDR(0x051c)
90
91/*
92 * Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4,
93 * AUXCLKREQ5, D2DCLKREQ
94 */
95#define OMAP5_ACCURACY_SHIFT 1
96#define OMAP5_ACCURACY_WIDTH 0x1
97#define OMAP5_ACCURACY_MASK (1 << 1)
98
99/* Used by APEWARMRSTST */
100#define OMAP5_APEWARMRSTST_SHIFT 1
101#define OMAP5_APEWARMRSTST_WIDTH 0x1
102#define OMAP5_APEWARMRSTST_MASK (1 << 1)
103
104/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
105#define OMAP5_CLKDIV_SHIFT 16
106#define OMAP5_CLKDIV_WIDTH 0x4
107#define OMAP5_CLKDIV_MASK (0xf << 16)
108
109/* Used by D2DCLKM, MODEMCLKM */
110#define OMAP5_CLK_32KHZ_SHIFT 0
111#define OMAP5_CLK_32KHZ_WIDTH 0x1
112#define OMAP5_CLK_32KHZ_MASK (1 << 0)
113
114/* Used by D2DRSTCTRL, MODEMRSTCTRL */
115#define OMAP5_COLDRST_SHIFT 0
116#define OMAP5_COLDRST_WIDTH 0x1
117#define OMAP5_COLDRST_MASK (1 << 0)
118
119/* Used by D2DWARMRSTST */
120#define OMAP5_D2DWARMRSTST_SHIFT 3
121#define OMAP5_D2DWARMRSTST_WIDTH 0x1
122#define OMAP5_D2DWARMRSTST_MASK (1 << 3)
123
124/* Used by AUXCLK0 */
125#define OMAP5_DISABLECLK_SHIFT 9
126#define OMAP5_DISABLECLK_WIDTH 0x1
127#define OMAP5_DISABLECLK_MASK (1 << 9)
128
129/* Used by CLKSETUPTIME */
130#define OMAP5_DOWNTIME_SHIFT 16
131#define OMAP5_DOWNTIME_WIDTH 0x6
132#define OMAP5_DOWNTIME_MASK (0x3f << 16)
133
134/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
135#define OMAP5_ENABLE_SHIFT 8
136#define OMAP5_ENABLE_WIDTH 0x1
137#define OMAP5_ENABLE_MASK (1 << 8)
138
139/* Renamed from ENABLE Used by EXTPWRONRSTCTRL */
140#define OMAP5_ENABLE_0_0_SHIFT 0
141#define OMAP5_ENABLE_0_0_WIDTH 0x1
142#define OMAP5_ENABLE_0_0_MASK (1 << 0)
143
144/* Used by ALTCLKSRC */
145#define OMAP5_ENABLE_EXT_SHIFT 3
146#define OMAP5_ENABLE_EXT_WIDTH 0x1
147#define OMAP5_ENABLE_EXT_MASK (1 << 3)
148
149/* Used by ALTCLKSRC */
150#define OMAP5_ENABLE_INT_SHIFT 2
151#define OMAP5_ENABLE_INT_WIDTH 0x1
152#define OMAP5_ENABLE_INT_MASK (1 << 2)
153
154/* Used by EXTWARMRSTST */
155#define OMAP5_EXTWARMRSTST_SHIFT 0
156#define OMAP5_EXTWARMRSTST_WIDTH 0x1
157#define OMAP5_EXTWARMRSTST_MASK (1 << 0)
158
159/*
160 * Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4,
161 * AUXCLKREQ5
162 */
163#define OMAP5_MAPPING_SHIFT 2
164#define OMAP5_MAPPING_WIDTH 0x3
165#define OMAP5_MAPPING_MASK (0x7 << 2)
166
167/* Used by ALTCLKSRC */
168#define OMAP5_MODE_SHIFT 0
169#define OMAP5_MODE_WIDTH 0x2
170#define OMAP5_MODE_MASK (0x3 << 0)
171
172/* Used by MODEMWARMRSTST */
173#define OMAP5_MODEMWARMRSTST_SHIFT 2
174#define OMAP5_MODEMWARMRSTST_WIDTH 0x1
175#define OMAP5_MODEMWARMRSTST_MASK (1 << 2)
176
177/*
178 * Used by ACCCLKREQ, AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5,
179 * AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4, AUXCLKREQ5,
180 * D2DCLKREQ, EXTCLKREQ, PWRREQ
181 */
182#define OMAP5_POLARITY_SHIFT 0
183#define OMAP5_POLARITY_WIDTH 0x1
184#define OMAP5_POLARITY_MASK (1 << 0)
185
186/* Used by EXTPWRONRSTCTRL */
187#define OMAP5_PWRONRST_SHIFT 1
188#define OMAP5_PWRONRST_WIDTH 0x1
189#define OMAP5_PWRONRST_MASK (1 << 1)
190
191/* Used by REVISION_SCRM */
192#define OMAP5_REV_SHIFT 0
193#define OMAP5_REV_WIDTH 0x8
194#define OMAP5_REV_MASK (0xff << 0)
195
196/* Used by RSTTIME */
197#define OMAP5_RSTTIME_SHIFT 0
198#define OMAP5_RSTTIME_WIDTH 0x4
199#define OMAP5_RSTTIME_MASK (0xf << 0)
200
201/* Used by CLKSETUPTIME */
202#define OMAP5_SETUPTIME_SHIFT 0
203#define OMAP5_SETUPTIME_WIDTH 0xc
204#define OMAP5_SETUPTIME_MASK (0xfff << 0)
205
206/* Used by PMICSETUPTIME */
207#define OMAP5_SLEEPTIME_SHIFT 0
208#define OMAP5_SLEEPTIME_WIDTH 0x6
209#define OMAP5_SLEEPTIME_MASK (0x3f << 0)
210
211/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
212#define OMAP5_SRCSELECT_SHIFT 1
213#define OMAP5_SRCSELECT_WIDTH 0x2
214#define OMAP5_SRCSELECT_MASK (0x3 << 1)
215
216/* Used by D2DCLKM */
217#define OMAP5_SYSCLK_SHIFT 1
218#define OMAP5_SYSCLK_WIDTH 0x1
219#define OMAP5_SYSCLK_MASK (1 << 1)
220
221/* Used by PMICSETUPTIME */
222#define OMAP5_WAKEUPTIME_SHIFT 16
223#define OMAP5_WAKEUPTIME_WIDTH 0x6
224#define OMAP5_WAKEUPTIME_MASK (0x3f << 16)
225
226/* Used by D2DRSTCTRL, MODEMRSTCTRL */
227#define OMAP5_WARMRST_SHIFT 1
228#define OMAP5_WARMRST_WIDTH 0x1
229#define OMAP5_WARMRST_MASK (1 << 1)
230
231#endif
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index f6601563aa69..a388f8c1bcb3 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -63,7 +63,6 @@ struct omap_uart_state {
63static LIST_HEAD(uart_list); 63static LIST_HEAD(uart_list);
64static u8 num_uarts; 64static u8 num_uarts;
65static u8 console_uart_id = -1; 65static u8 console_uart_id = -1;
66static u8 no_console_suspend;
67static u8 uart_debug; 66static u8 uart_debug;
68 67
69#define DEFAULT_RXDMA_POLLRATE 1 /* RX DMA polling rate (us) */ 68#define DEFAULT_RXDMA_POLLRATE 1 /* RX DMA polling rate (us) */
@@ -176,6 +175,9 @@ static char *cmdline_find_option(char *str)
176 175
177static int __init omap_serial_early_init(void) 176static int __init omap_serial_early_init(void)
178{ 177{
178 if (of_have_populated_dt())
179 return -ENODEV;
180
179 do { 181 do {
180 char oh_name[MAX_UART_HWMOD_NAME_LEN]; 182 char oh_name[MAX_UART_HWMOD_NAME_LEN];
181 struct omap_hwmod *oh; 183 struct omap_hwmod *oh;
@@ -206,20 +208,6 @@ static int __init omap_serial_early_init(void)
206 pr_info("%s used as console in debug mode: uart%d clocks will not be gated", 208 pr_info("%s used as console in debug mode: uart%d clocks will not be gated",
207 uart_name, uart->num); 209 uart_name, uart->num);
208 } 210 }
209
210 if (cmdline_find_option("no_console_suspend"))
211 no_console_suspend = true;
212
213 /*
214 * omap-uart can be used for earlyprintk logs
215 * So if omap-uart is used as console then prevent
216 * uart reset and idle to get logs from omap-uart
217 * until uart console driver is available to take
218 * care for console messages.
219 * Idling or resetting omap-uart while printing logs
220 * early boot logs can stall the boot-up.
221 */
222 oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET;
223 } 211 }
224 } while (1); 212 } while (1);
225 213
@@ -292,9 +280,6 @@ void __init omap_serial_init_port(struct omap_board_data *bdata,
292 return; 280 return;
293 } 281 }
294 282
295 if ((console_uart_id == bdata->id) && no_console_suspend)
296 omap_device_disable_idle_on_suspend(pdev);
297
298 oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt); 283 oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
299 284
300 if (console_uart_id == bdata->id) { 285 if (console_uart_id == bdata->id) {
diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S
index 88ff83a0942e..9086ce03ae12 100644
--- a/arch/arm/mach-omap2/sleep44xx.S
+++ b/arch/arm/mach-omap2/sleep44xx.S
@@ -34,6 +34,8 @@ ppa_zero_params:
34ppa_por_params: 34ppa_por_params:
35 .word 1, 0 35 .word 1, 0
36 36
37#ifdef CONFIG_ARCH_OMAP4
38
37/* 39/*
38 * ============================= 40 * =============================
39 * == CPU suspend finisher == 41 * == CPU suspend finisher ==
@@ -326,7 +328,9 @@ skip_l2en:
326 328
327 b cpu_resume @ Jump to generic resume 329 b cpu_resume @ Jump to generic resume
328ENDPROC(omap4_cpu_resume) 330ENDPROC(omap4_cpu_resume)
329#endif 331#endif /* CONFIG_ARCH_OMAP4 */
332
333#endif /* defined(CONFIG_SMP) && defined(CONFIG_PM) */
330 334
331#ifndef CONFIG_OMAP4_ERRATA_I688 335#ifndef CONFIG_OMAP4_ERRATA_I688
332ENTRY(omap_bus_sync) 336ENTRY(omap_bus_sync)
diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c
index aee3c8940a30..7a42e1960c3b 100644
--- a/arch/arm/mach-omap2/smartreflex-class3.c
+++ b/arch/arm/mach-omap2/smartreflex-class3.c
@@ -26,14 +26,14 @@ static int sr_class3_enable(struct omap_sr *sr)
26 } 26 }
27 27
28 omap_vp_enable(sr->voltdm); 28 omap_vp_enable(sr->voltdm);
29 return sr_enable(sr->voltdm, volt); 29 return sr_enable(sr, volt);
30} 30}
31 31
32static int sr_class3_disable(struct omap_sr *sr, int is_volt_reset) 32static int sr_class3_disable(struct omap_sr *sr, int is_volt_reset)
33{ 33{
34 sr_disable_errgen(sr->voltdm); 34 sr_disable_errgen(sr);
35 omap_vp_disable(sr->voltdm); 35 omap_vp_disable(sr->voltdm);
36 sr_disable(sr->voltdm); 36 sr_disable(sr);
37 if (is_volt_reset) 37 if (is_volt_reset)
38 voltdm_reset(sr->voltdm); 38 voltdm_reset(sr->voltdm);
39 39
@@ -42,7 +42,7 @@ static int sr_class3_disable(struct omap_sr *sr, int is_volt_reset)
42 42
43static int sr_class3_configure(struct omap_sr *sr) 43static int sr_class3_configure(struct omap_sr *sr)
44{ 44{
45 return sr_configure_errgen(sr->voltdm); 45 return sr_configure_errgen(sr);
46} 46}
47 47
48/* SR class3 structure */ 48/* SR class3 structure */
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index 197cc16870d9..8c616e436bc7 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -96,6 +96,15 @@
96# endif 96# endif
97#endif 97#endif
98 98
99#ifdef CONFIG_SOC_AM43XX
100# ifdef OMAP_NAME
101# undef MULTI_OMAP2
102# define MULTI_OMAP2
103# else
104# define OMAP_NAME am43xx
105# endif
106#endif
107
99/* 108/*
100 * Omap device type i.e. EMU/HS/TST/GP/BAD 109 * Omap device type i.e. EMU/HS/TST/GP/BAD
101 */ 110 */
@@ -187,6 +196,7 @@ IS_OMAP_CLASS(44xx, 0x44)
187IS_AM_CLASS(35xx, 0x35) 196IS_AM_CLASS(35xx, 0x35)
188IS_OMAP_CLASS(54xx, 0x54) 197IS_OMAP_CLASS(54xx, 0x54)
189IS_AM_CLASS(33xx, 0x33) 198IS_AM_CLASS(33xx, 0x33)
199IS_AM_CLASS(43xx, 0x43)
190 200
191IS_TI_CLASS(81xx, 0x81) 201IS_TI_CLASS(81xx, 0x81)
192 202
@@ -202,6 +212,7 @@ IS_OMAP_SUBCLASS(543x, 0x543)
202IS_TI_SUBCLASS(816x, 0x816) 212IS_TI_SUBCLASS(816x, 0x816)
203IS_TI_SUBCLASS(814x, 0x814) 213IS_TI_SUBCLASS(814x, 0x814)
204IS_AM_SUBCLASS(335x, 0x335) 214IS_AM_SUBCLASS(335x, 0x335)
215IS_AM_SUBCLASS(437x, 0x437)
205 216
206#define cpu_is_omap24xx() 0 217#define cpu_is_omap24xx() 0
207#define cpu_is_omap242x() 0 218#define cpu_is_omap242x() 0
@@ -214,6 +225,8 @@ IS_AM_SUBCLASS(335x, 0x335)
214#define soc_is_am35xx() 0 225#define soc_is_am35xx() 0
215#define soc_is_am33xx() 0 226#define soc_is_am33xx() 0
216#define soc_is_am335x() 0 227#define soc_is_am335x() 0
228#define soc_is_am43xx() 0
229#define soc_is_am437x() 0
217#define cpu_is_omap44xx() 0 230#define cpu_is_omap44xx() 0
218#define cpu_is_omap443x() 0 231#define cpu_is_omap443x() 0
219#define cpu_is_omap446x() 0 232#define cpu_is_omap446x() 0
@@ -341,6 +354,13 @@ IS_OMAP_TYPE(3430, 0x3430)
341# define soc_is_am335x() is_am335x() 354# define soc_is_am335x() is_am335x()
342#endif 355#endif
343 356
357#ifdef CONFIG_SOC_AM43XX
358# undef soc_is_am43xx
359# undef soc_is_am437x
360# define soc_is_am43xx() is_am43xx()
361# define soc_is_am437x() is_am437x()
362#endif
363
344# if defined(CONFIG_ARCH_OMAP4) 364# if defined(CONFIG_ARCH_OMAP4)
345# undef cpu_is_omap44xx 365# undef cpu_is_omap44xx
346# undef cpu_is_omap443x 366# undef cpu_is_omap443x
@@ -383,6 +403,8 @@ IS_OMAP_TYPE(3430, 0x3430)
383#define TI816X_CLASS 0x81600034 403#define TI816X_CLASS 0x81600034
384#define TI8168_REV_ES1_0 TI816X_CLASS 404#define TI8168_REV_ES1_0 TI816X_CLASS
385#define TI8168_REV_ES1_1 (TI816X_CLASS | (0x1 << 8)) 405#define TI8168_REV_ES1_1 (TI816X_CLASS | (0x1 << 8))
406#define TI8168_REV_ES2_0 (TI816X_CLASS | (0x2 << 8))
407#define TI8168_REV_ES2_1 (TI816X_CLASS | (0x3 << 8))
386 408
387#define TI814X_CLASS 0x81400034 409#define TI814X_CLASS 0x81400034
388#define TI8148_REV_ES1_0 TI814X_CLASS 410#define TI8148_REV_ES1_0 TI814X_CLASS
@@ -398,6 +420,9 @@ IS_OMAP_TYPE(3430, 0x3430)
398#define AM335X_REV_ES2_0 (AM335X_CLASS | (0x1 << 8)) 420#define AM335X_REV_ES2_0 (AM335X_CLASS | (0x1 << 8))
399#define AM335X_REV_ES2_1 (AM335X_CLASS | (0x2 << 8)) 421#define AM335X_REV_ES2_1 (AM335X_CLASS | (0x2 << 8))
400 422
423#define AM437X_CLASS 0x43700000
424#define AM437X_REV_ES1_0 AM437X_CLASS
425
401#define OMAP443X_CLASS 0x44300044 426#define OMAP443X_CLASS 0x44300044
402#define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8)) 427#define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8))
403#define OMAP4430_REV_ES2_0 (OMAP443X_CLASS | (0x20 << 8)) 428#define OMAP4430_REV_ES2_0 (OMAP443X_CLASS | (0x20 << 8))
@@ -424,6 +449,7 @@ void omap4xxx_check_revision(void);
424void omap5xxx_check_revision(void); 449void omap5xxx_check_revision(void);
425void omap3xxx_check_features(void); 450void omap3xxx_check_features(void);
426void ti81xx_check_features(void); 451void ti81xx_check_features(void);
452void am33xx_check_features(void);
427void omap4xxx_check_features(void); 453void omap4xxx_check_features(void);
428 454
429/* 455/*
diff --git a/arch/arm/mach-omap2/sram.c b/arch/arm/mach-omap2/sram.c
index 0ff0f068bea8..4bd096836235 100644
--- a/arch/arm/mach-omap2/sram.c
+++ b/arch/arm/mach-omap2/sram.c
@@ -119,6 +119,9 @@ static void __init omap_detect_sram(void)
119 if (soc_is_am33xx()) { 119 if (soc_is_am33xx()) {
120 omap_sram_start = AM33XX_SRAM_PA; 120 omap_sram_start = AM33XX_SRAM_PA;
121 omap_sram_size = 0x10000; /* 64K */ 121 omap_sram_size = 0x10000; /* 64K */
122 } else if (soc_is_am43xx()) {
123 omap_sram_start = AM33XX_SRAM_PA;
124 omap_sram_size = SZ_256K;
122 } else if (cpu_is_omap34xx()) { 125 } else if (cpu_is_omap34xx()) {
123 omap_sram_start = OMAP3_SRAM_PA; 126 omap_sram_start = OMAP3_SRAM_PA;
124 omap_sram_size = 0x10000; /* 64K */ 127 omap_sram_size = 0x10000; /* 64K */
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index f8b23b8040d9..b37e1fcbad56 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -41,10 +41,10 @@
41#include <linux/of_irq.h> 41#include <linux/of_irq.h>
42#include <linux/platform_device.h> 42#include <linux/platform_device.h>
43#include <linux/platform_data/dmtimer-omap.h> 43#include <linux/platform_data/dmtimer-omap.h>
44#include <linux/sched_clock.h>
44 45
45#include <asm/mach/time.h> 46#include <asm/mach/time.h>
46#include <asm/smp_twd.h> 47#include <asm/smp_twd.h>
47#include <asm/sched_clock.h>
48 48
49#include "omap_hwmod.h" 49#include "omap_hwmod.h"
50#include "omap_device.h" 50#include "omap_device.h"
@@ -220,7 +220,7 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
220 int posted) 220 int posted)
221{ 221{
222 char name[10]; /* 10 = sizeof("gptXX_Xck0") */ 222 char name[10]; /* 10 = sizeof("gptXX_Xck0") */
223 const char *oh_name; 223 const char *oh_name = NULL;
224 struct device_node *np; 224 struct device_node *np;
225 struct omap_hwmod *oh; 225 struct omap_hwmod *oh;
226 struct resource irq, mem; 226 struct resource irq, mem;
@@ -582,7 +582,7 @@ OMAP_SYS_32K_TIMER_INIT(2, 1, "timer_32k_ck", "ti,timer-alwon",
582 2, "timer_sys_ck", NULL); 582 2, "timer_sys_ck", NULL);
583#endif /* CONFIG_ARCH_OMAP2 */ 583#endif /* CONFIG_ARCH_OMAP2 */
584 584
585#ifdef CONFIG_ARCH_OMAP3 585#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
586OMAP_SYS_32K_TIMER_INIT(3, 1, "timer_32k_ck", "ti,timer-alwon", 586OMAP_SYS_32K_TIMER_INIT(3, 1, "timer_32k_ck", "ti,timer-alwon",
587 2, "timer_sys_ck", NULL); 587 2, "timer_sys_ck", NULL);
588OMAP_SYS_32K_TIMER_INIT(3_secure, 12, "secure_32k_fck", "ti,timer-secure", 588OMAP_SYS_32K_TIMER_INIT(3_secure, 12, "secure_32k_fck", "ti,timer-secure",
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index 51e138cc5398..c05898fbd634 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -140,6 +140,7 @@ static struct regulator_init_data omap3_vdac_idata = {
140 140
141static struct regulator_consumer_supply omap3_vpll2_supplies[] = { 141static struct regulator_consumer_supply omap3_vpll2_supplies[] = {
142 REGULATOR_SUPPLY("vdds_dsi", "omapdss"), 142 REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
143 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dpi.0"),
143 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"), 144 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"),
144}; 145};
145 146
diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
index aa27d7f5cbb7..2eb19d4d0aa1 100644
--- a/arch/arm/mach-omap2/usb-host.c
+++ b/arch/arm/mach-omap2/usb-host.c
@@ -28,6 +28,7 @@
28#include <linux/io.h> 28#include <linux/io.h>
29#include <linux/gpio.h> 29#include <linux/gpio.h>
30#include <linux/usb/phy.h> 30#include <linux/usb/phy.h>
31#include <linux/usb/nop-usb-xceiv.h>
31 32
32#include "soc.h" 33#include "soc.h"
33#include "omap_device.h" 34#include "omap_device.h"
@@ -188,125 +189,6 @@ static void __init setup_ehci_io_mux(const enum usbhs_omap_port_mode *port_mode)
188 return; 189 return;
189} 190}
190 191
191static
192void __init setup_4430ehci_io_mux(const enum usbhs_omap_port_mode *port_mode)
193{
194 switch (port_mode[0]) {
195 case OMAP_EHCI_PORT_MODE_PHY:
196 omap_mux_init_signal("usbb1_ulpiphy_stp",
197 OMAP_PIN_OUTPUT);
198 omap_mux_init_signal("usbb1_ulpiphy_clk",
199 OMAP_PIN_INPUT_PULLDOWN);
200 omap_mux_init_signal("usbb1_ulpiphy_dir",
201 OMAP_PIN_INPUT_PULLDOWN);
202 omap_mux_init_signal("usbb1_ulpiphy_nxt",
203 OMAP_PIN_INPUT_PULLDOWN);
204 omap_mux_init_signal("usbb1_ulpiphy_dat0",
205 OMAP_PIN_INPUT_PULLDOWN);
206 omap_mux_init_signal("usbb1_ulpiphy_dat1",
207 OMAP_PIN_INPUT_PULLDOWN);
208 omap_mux_init_signal("usbb1_ulpiphy_dat2",
209 OMAP_PIN_INPUT_PULLDOWN);
210 omap_mux_init_signal("usbb1_ulpiphy_dat3",
211 OMAP_PIN_INPUT_PULLDOWN);
212 omap_mux_init_signal("usbb1_ulpiphy_dat4",
213 OMAP_PIN_INPUT_PULLDOWN);
214 omap_mux_init_signal("usbb1_ulpiphy_dat5",
215 OMAP_PIN_INPUT_PULLDOWN);
216 omap_mux_init_signal("usbb1_ulpiphy_dat6",
217 OMAP_PIN_INPUT_PULLDOWN);
218 omap_mux_init_signal("usbb1_ulpiphy_dat7",
219 OMAP_PIN_INPUT_PULLDOWN);
220 break;
221 case OMAP_EHCI_PORT_MODE_TLL:
222 omap_mux_init_signal("usbb1_ulpitll_stp",
223 OMAP_PIN_INPUT_PULLUP);
224 omap_mux_init_signal("usbb1_ulpitll_clk",
225 OMAP_PIN_INPUT_PULLDOWN);
226 omap_mux_init_signal("usbb1_ulpitll_dir",
227 OMAP_PIN_INPUT_PULLDOWN);
228 omap_mux_init_signal("usbb1_ulpitll_nxt",
229 OMAP_PIN_INPUT_PULLDOWN);
230 omap_mux_init_signal("usbb1_ulpitll_dat0",
231 OMAP_PIN_INPUT_PULLDOWN);
232 omap_mux_init_signal("usbb1_ulpitll_dat1",
233 OMAP_PIN_INPUT_PULLDOWN);
234 omap_mux_init_signal("usbb1_ulpitll_dat2",
235 OMAP_PIN_INPUT_PULLDOWN);
236 omap_mux_init_signal("usbb1_ulpitll_dat3",
237 OMAP_PIN_INPUT_PULLDOWN);
238 omap_mux_init_signal("usbb1_ulpitll_dat4",
239 OMAP_PIN_INPUT_PULLDOWN);
240 omap_mux_init_signal("usbb1_ulpitll_dat5",
241 OMAP_PIN_INPUT_PULLDOWN);
242 omap_mux_init_signal("usbb1_ulpitll_dat6",
243 OMAP_PIN_INPUT_PULLDOWN);
244 omap_mux_init_signal("usbb1_ulpitll_dat7",
245 OMAP_PIN_INPUT_PULLDOWN);
246 break;
247 case OMAP_USBHS_PORT_MODE_UNUSED:
248 default:
249 break;
250 }
251 switch (port_mode[1]) {
252 case OMAP_EHCI_PORT_MODE_PHY:
253 omap_mux_init_signal("usbb2_ulpiphy_stp",
254 OMAP_PIN_OUTPUT);
255 omap_mux_init_signal("usbb2_ulpiphy_clk",
256 OMAP_PIN_INPUT_PULLDOWN);
257 omap_mux_init_signal("usbb2_ulpiphy_dir",
258 OMAP_PIN_INPUT_PULLDOWN);
259 omap_mux_init_signal("usbb2_ulpiphy_nxt",
260 OMAP_PIN_INPUT_PULLDOWN);
261 omap_mux_init_signal("usbb2_ulpiphy_dat0",
262 OMAP_PIN_INPUT_PULLDOWN);
263 omap_mux_init_signal("usbb2_ulpiphy_dat1",
264 OMAP_PIN_INPUT_PULLDOWN);
265 omap_mux_init_signal("usbb2_ulpiphy_dat2",
266 OMAP_PIN_INPUT_PULLDOWN);
267 omap_mux_init_signal("usbb2_ulpiphy_dat3",
268 OMAP_PIN_INPUT_PULLDOWN);
269 omap_mux_init_signal("usbb2_ulpiphy_dat4",
270 OMAP_PIN_INPUT_PULLDOWN);
271 omap_mux_init_signal("usbb2_ulpiphy_dat5",
272 OMAP_PIN_INPUT_PULLDOWN);
273 omap_mux_init_signal("usbb2_ulpiphy_dat6",
274 OMAP_PIN_INPUT_PULLDOWN);
275 omap_mux_init_signal("usbb2_ulpiphy_dat7",
276 OMAP_PIN_INPUT_PULLDOWN);
277 break;
278 case OMAP_EHCI_PORT_MODE_TLL:
279 omap_mux_init_signal("usbb2_ulpitll_stp",
280 OMAP_PIN_INPUT_PULLUP);
281 omap_mux_init_signal("usbb2_ulpitll_clk",
282 OMAP_PIN_INPUT_PULLDOWN);
283 omap_mux_init_signal("usbb2_ulpitll_dir",
284 OMAP_PIN_INPUT_PULLDOWN);
285 omap_mux_init_signal("usbb2_ulpitll_nxt",
286 OMAP_PIN_INPUT_PULLDOWN);
287 omap_mux_init_signal("usbb2_ulpitll_dat0",
288 OMAP_PIN_INPUT_PULLDOWN);
289 omap_mux_init_signal("usbb2_ulpitll_dat1",
290 OMAP_PIN_INPUT_PULLDOWN);
291 omap_mux_init_signal("usbb2_ulpitll_dat2",
292 OMAP_PIN_INPUT_PULLDOWN);
293 omap_mux_init_signal("usbb2_ulpitll_dat3",
294 OMAP_PIN_INPUT_PULLDOWN);
295 omap_mux_init_signal("usbb2_ulpitll_dat4",
296 OMAP_PIN_INPUT_PULLDOWN);
297 omap_mux_init_signal("usbb2_ulpitll_dat5",
298 OMAP_PIN_INPUT_PULLDOWN);
299 omap_mux_init_signal("usbb2_ulpitll_dat6",
300 OMAP_PIN_INPUT_PULLDOWN);
301 omap_mux_init_signal("usbb2_ulpitll_dat7",
302 OMAP_PIN_INPUT_PULLDOWN);
303 break;
304 case OMAP_USBHS_PORT_MODE_UNUSED:
305 default:
306 break;
307 }
308}
309
310static void __init setup_ohci_io_mux(const enum usbhs_omap_port_mode *port_mode) 192static void __init setup_ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
311{ 193{
312 switch (port_mode[0]) { 194 switch (port_mode[0]) {
@@ -404,78 +286,6 @@ static void __init setup_ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
404 } 286 }
405} 287}
406 288
407static
408void __init setup_4430ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
409{
410 switch (port_mode[0]) {
411 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
412 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
413 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
414 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
415 omap_mux_init_signal("usbb1_mm_rxdp",
416 OMAP_PIN_INPUT_PULLDOWN);
417 omap_mux_init_signal("usbb1_mm_rxdm",
418 OMAP_PIN_INPUT_PULLDOWN);
419
420 case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
421 case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
422 omap_mux_init_signal("usbb1_mm_rxrcv",
423 OMAP_PIN_INPUT_PULLDOWN);
424
425 case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
426 case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
427 omap_mux_init_signal("usbb1_mm_txen",
428 OMAP_PIN_INPUT_PULLDOWN);
429
430
431 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
432 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
433 omap_mux_init_signal("usbb1_mm_txdat",
434 OMAP_PIN_INPUT_PULLDOWN);
435 omap_mux_init_signal("usbb1_mm_txse0",
436 OMAP_PIN_INPUT_PULLDOWN);
437 break;
438
439 case OMAP_USBHS_PORT_MODE_UNUSED:
440 default:
441 break;
442 }
443
444 switch (port_mode[1]) {
445 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
446 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
447 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
448 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
449 omap_mux_init_signal("usbb2_mm_rxdp",
450 OMAP_PIN_INPUT_PULLDOWN);
451 omap_mux_init_signal("usbb2_mm_rxdm",
452 OMAP_PIN_INPUT_PULLDOWN);
453
454 case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
455 case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
456 omap_mux_init_signal("usbb2_mm_rxrcv",
457 OMAP_PIN_INPUT_PULLDOWN);
458
459 case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
460 case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
461 omap_mux_init_signal("usbb2_mm_txen",
462 OMAP_PIN_INPUT_PULLDOWN);
463
464
465 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
466 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
467 omap_mux_init_signal("usbb2_mm_txdat",
468 OMAP_PIN_INPUT_PULLDOWN);
469 omap_mux_init_signal("usbb2_mm_txse0",
470 OMAP_PIN_INPUT_PULLDOWN);
471 break;
472
473 case OMAP_USBHS_PORT_MODE_UNUSED:
474 default:
475 break;
476 }
477}
478
479void __init usbhs_init(struct usbhs_omap_platform_data *pdata) 289void __init usbhs_init(struct usbhs_omap_platform_data *pdata)
480{ 290{
481 struct omap_hwmod *uhh_hwm, *tll_hwm; 291 struct omap_hwmod *uhh_hwm, *tll_hwm;
@@ -489,9 +299,6 @@ void __init usbhs_init(struct usbhs_omap_platform_data *pdata)
489 if (omap_rev() <= OMAP3430_REV_ES2_1) 299 if (omap_rev() <= OMAP3430_REV_ES2_1)
490 pdata->single_ulpi_bypass = true; 300 pdata->single_ulpi_bypass = true;
491 301
492 } else if (cpu_is_omap44xx()) {
493 setup_4430ehci_io_mux(pdata->port_mode);
494 setup_4430ohci_io_mux(pdata->port_mode);
495 } 302 }
496 303
497 uhh_hwm = omap_hwmod_lookup(USBHS_UHH_HWMODNAME); 304 uhh_hwm = omap_hwmod_lookup(USBHS_UHH_HWMODNAME);
@@ -560,7 +367,8 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
560 struct regulator_init_data *reg_data; 367 struct regulator_init_data *reg_data;
561 struct fixed_voltage_config *config; 368 struct fixed_voltage_config *config;
562 struct platform_device *pdev; 369 struct platform_device *pdev;
563 int ret; 370 struct platform_device_info pdevinfo;
371 int ret = -ENOMEM;
564 372
565 supplies = kzalloc(sizeof(*supplies), GFP_KERNEL); 373 supplies = kzalloc(sizeof(*supplies), GFP_KERNEL);
566 if (!supplies) 374 if (!supplies)
@@ -571,7 +379,7 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
571 379
572 reg_data = kzalloc(sizeof(*reg_data), GFP_KERNEL); 380 reg_data = kzalloc(sizeof(*reg_data), GFP_KERNEL);
573 if (!reg_data) 381 if (!reg_data)
574 return -ENOMEM; 382 goto err_data;
575 383
576 reg_data->constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS; 384 reg_data->constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS;
577 reg_data->consumer_supplies = supplies; 385 reg_data->consumer_supplies = supplies;
@@ -580,39 +388,53 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
580 config = kmemdup(&hsusb_reg_config, sizeof(hsusb_reg_config), 388 config = kmemdup(&hsusb_reg_config, sizeof(hsusb_reg_config),
581 GFP_KERNEL); 389 GFP_KERNEL);
582 if (!config) 390 if (!config)
583 return -ENOMEM; 391 goto err_config;
392
393 config->supply_name = kstrdup(name, GFP_KERNEL);
394 if (!config->supply_name)
395 goto err_supplyname;
584 396
585 config->supply_name = name;
586 config->gpio = gpio; 397 config->gpio = gpio;
587 config->enable_high = polarity; 398 config->enable_high = polarity;
588 config->init_data = reg_data; 399 config->init_data = reg_data;
589 400
590 /* create a regulator device */ 401 /* create a regulator device */
591 pdev = kzalloc(sizeof(*pdev), GFP_KERNEL); 402 memset(&pdevinfo, 0, sizeof(pdevinfo));
592 if (!pdev) 403 pdevinfo.name = reg_name;
593 return -ENOMEM; 404 pdevinfo.id = PLATFORM_DEVID_AUTO;
405 pdevinfo.data = config;
406 pdevinfo.size_data = sizeof(*config);
594 407
595 pdev->id = PLATFORM_DEVID_AUTO; 408 pdev = platform_device_register_full(&pdevinfo);
596 pdev->name = reg_name; 409 if (IS_ERR(pdev)) {
597 pdev->dev.platform_data = config; 410 ret = PTR_ERR(pdev);
411 pr_err("%s: Failed registering regulator %s for %s : %d\n",
412 __func__, name, dev_id, ret);
413 goto err_register;
414 }
598 415
599 ret = platform_device_register(pdev); 416 return 0;
600 if (ret)
601 pr_err("%s: Failed registering regulator %s for %s\n",
602 __func__, name, dev_id);
603 417
418err_register:
419 kfree(config->supply_name);
420err_supplyname:
421 kfree(config);
422err_config:
423 kfree(reg_data);
424err_data:
425 kfree(supplies);
604 return ret; 426 return ret;
605} 427}
606 428
429#define MAX_STR 20
430
607int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys) 431int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys)
608{ 432{
609 char *rail_name; 433 char rail_name[MAX_STR];
610 int i, len; 434 int i;
611 struct platform_device *pdev; 435 struct platform_device *pdev;
612 char *phy_id; 436 char *phy_id;
613 437 struct platform_device_info pdevinfo;
614 /* the phy_id will be something like "nop_usb_xceiv.1" */
615 len = strlen(nop_name) + 3; /* 3 -> ".1" and NULL terminator */
616 438
617 for (i = 0; i < num_phys; i++) { 439 for (i = 0; i < num_phys; i++) {
618 440
@@ -627,25 +449,26 @@ int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys)
627 !gpio_is_valid(phy->vcc_gpio)) 449 !gpio_is_valid(phy->vcc_gpio))
628 continue; 450 continue;
629 451
630 /* create a NOP PHY device */ 452 phy_id = kmalloc(MAX_STR, GFP_KERNEL);
631 pdev = kzalloc(sizeof(*pdev), GFP_KERNEL); 453 if (!phy_id) {
632 if (!pdev) 454 pr_err("%s: kmalloc() failed\n", __func__);
633 return -ENOMEM; 455 return -ENOMEM;
456 }
634 457
635 pdev->id = phy->port; 458 /* create a NOP PHY device */
636 pdev->name = nop_name; 459 memset(&pdevinfo, 0, sizeof(pdevinfo));
637 pdev->dev.platform_data = phy->platform_data; 460 pdevinfo.name = nop_name;
638 461 pdevinfo.id = phy->port;
639 phy_id = kmalloc(len, GFP_KERNEL); 462 pdevinfo.data = phy->platform_data;
640 if (!phy_id) 463 pdevinfo.size_data = sizeof(struct nop_usb_xceiv_platform_data);
641 return -ENOMEM; 464
642 465 scnprintf(phy_id, MAX_STR, "nop_usb_xceiv.%d",
643 scnprintf(phy_id, len, "nop_usb_xceiv.%d\n", 466 phy->port);
644 pdev->id); 467 pdev = platform_device_register_full(&pdevinfo);
645 468 if (IS_ERR(pdev)) {
646 if (platform_device_register(pdev)) { 469 pr_err("%s: Failed to register device %s : %ld\n",
647 pr_err("%s: Failed to register device %s\n", 470 __func__, phy_id, PTR_ERR(pdev));
648 __func__, phy_id); 471 kfree(phy_id);
649 continue; 472 continue;
650 } 473 }
651 474
@@ -653,26 +476,15 @@ int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys)
653 476
654 /* Do we need RESET regulator ? */ 477 /* Do we need RESET regulator ? */
655 if (gpio_is_valid(phy->reset_gpio)) { 478 if (gpio_is_valid(phy->reset_gpio)) {
656 479 scnprintf(rail_name, MAX_STR,
657 rail_name = kmalloc(13, GFP_KERNEL); 480 "hsusb%d_reset", phy->port);
658 if (!rail_name)
659 return -ENOMEM;
660
661 scnprintf(rail_name, 13, "hsusb%d_reset", phy->port);
662
663 usbhs_add_regulator(rail_name, phy_id, "reset", 481 usbhs_add_regulator(rail_name, phy_id, "reset",
664 phy->reset_gpio, 1); 482 phy->reset_gpio, 1);
665 } 483 }
666 484
667 /* Do we need VCC regulator ? */ 485 /* Do we need VCC regulator ? */
668 if (gpio_is_valid(phy->vcc_gpio)) { 486 if (gpio_is_valid(phy->vcc_gpio)) {
669 487 scnprintf(rail_name, MAX_STR, "hsusb%d_vcc", phy->port);
670 rail_name = kmalloc(13, GFP_KERNEL);
671 if (!rail_name)
672 return -ENOMEM;
673
674 scnprintf(rail_name, 13, "hsusb%d_vcc", phy->port);
675
676 usbhs_add_regulator(rail_name, phy_id, "vcc", 488 usbhs_add_regulator(rail_name, phy_id, "vcc",
677 phy->vcc_gpio, phy->vcc_polarity); 489 phy->vcc_gpio, phy->vcc_polarity);
678 } 490 }
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index 3242a554ad6b..8c4de2708cf2 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -85,9 +85,6 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
85 musb_plat.mode = board_data->mode; 85 musb_plat.mode = board_data->mode;
86 musb_plat.extvbus = board_data->extvbus; 86 musb_plat.extvbus = board_data->extvbus;
87 87
88 if (cpu_is_omap44xx())
89 musb_plat.has_mailbox = true;
90
91 if (soc_is_am35xx()) { 88 if (soc_is_am35xx()) {
92 oh_name = "am35x_otg_hs"; 89 oh_name = "am35x_otg_hs";
93 name = "musb-am35x"; 90 name = "musb-am35x";
diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
index a0ce4f10ff13..f7f2879b31b0 100644
--- a/arch/arm/mach-omap2/voltage.h
+++ b/arch/arm/mach-omap2/voltage.h
@@ -169,8 +169,8 @@ int omap_voltage_late_init(void);
169 169
170extern void omap2xxx_voltagedomains_init(void); 170extern void omap2xxx_voltagedomains_init(void);
171extern void omap3xxx_voltagedomains_init(void); 171extern void omap3xxx_voltagedomains_init(void);
172extern void am33xx_voltagedomains_init(void);
173extern void omap44xx_voltagedomains_init(void); 172extern void omap44xx_voltagedomains_init(void);
173extern void omap54xx_voltagedomains_init(void);
174 174
175struct voltagedomain *voltdm_lookup(const char *name); 175struct voltagedomain *voltdm_lookup(const char *name);
176void voltdm_init(struct voltagedomain **voltdm_list); 176void voltdm_init(struct voltagedomain **voltdm_list);
diff --git a/arch/arm/mach-omap2/voltagedomains33xx_data.c b/arch/arm/mach-omap2/voltagedomains33xx_data.c
deleted file mode 100644
index 965458dc0cb9..000000000000
--- a/arch/arm/mach-omap2/voltagedomains33xx_data.c
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * AM33XX voltage domain data
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include "voltage.h"
20
21static struct voltagedomain am33xx_voltdm_mpu = {
22 .name = "mpu",
23};
24
25static struct voltagedomain am33xx_voltdm_core = {
26 .name = "core",
27};
28
29static struct voltagedomain am33xx_voltdm_rtc = {
30 .name = "rtc",
31};
32
33static struct voltagedomain *voltagedomains_am33xx[] __initdata = {
34 &am33xx_voltdm_mpu,
35 &am33xx_voltdm_core,
36 &am33xx_voltdm_rtc,
37 NULL,
38};
39
40void __init am33xx_voltagedomains_init(void)
41{
42 voltdm_init(voltagedomains_am33xx);
43}
diff --git a/arch/arm/mach-omap2/voltagedomains54xx_data.c b/arch/arm/mach-omap2/voltagedomains54xx_data.c
new file mode 100644
index 000000000000..33d22b87252d
--- /dev/null
+++ b/arch/arm/mach-omap2/voltagedomains54xx_data.c
@@ -0,0 +1,92 @@
1/*
2 * OMAP5 Voltage Management Routines
3 *
4 * Based on voltagedomains44xx_data.c
5 *
6 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12#include <linux/kernel.h>
13#include <linux/err.h>
14#include <linux/init.h>
15
16#include "common.h"
17
18#include "prm54xx.h"
19#include "voltage.h"
20#include "omap_opp_data.h"
21#include "vc.h"
22#include "vp.h"
23
24static const struct omap_vfsm_instance omap5_vdd_mpu_vfsm = {
25 .voltsetup_reg = OMAP54XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET,
26};
27
28static const struct omap_vfsm_instance omap5_vdd_mm_vfsm = {
29 .voltsetup_reg = OMAP54XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET,
30};
31
32static const struct omap_vfsm_instance omap5_vdd_core_vfsm = {
33 .voltsetup_reg = OMAP54XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET,
34};
35
36static struct voltagedomain omap5_voltdm_mpu = {
37 .name = "mpu",
38 .scalable = true,
39 .read = omap4_prm_vcvp_read,
40 .write = omap4_prm_vcvp_write,
41 .rmw = omap4_prm_vcvp_rmw,
42 .vc = &omap4_vc_mpu,
43 .vfsm = &omap5_vdd_mpu_vfsm,
44 .vp = &omap4_vp_mpu,
45};
46
47static struct voltagedomain omap5_voltdm_mm = {
48 .name = "mm",
49 .scalable = true,
50 .read = omap4_prm_vcvp_read,
51 .write = omap4_prm_vcvp_write,
52 .rmw = omap4_prm_vcvp_rmw,
53 .vc = &omap4_vc_iva,
54 .vfsm = &omap5_vdd_mm_vfsm,
55 .vp = &omap4_vp_iva,
56};
57
58static struct voltagedomain omap5_voltdm_core = {
59 .name = "core",
60 .scalable = true,
61 .read = omap4_prm_vcvp_read,
62 .write = omap4_prm_vcvp_write,
63 .rmw = omap4_prm_vcvp_rmw,
64 .vc = &omap4_vc_core,
65 .vfsm = &omap5_vdd_core_vfsm,
66 .vp = &omap4_vp_core,
67};
68
69static struct voltagedomain omap5_voltdm_wkup = {
70 .name = "wkup",
71};
72
73static struct voltagedomain *voltagedomains_omap5[] __initdata = {
74 &omap5_voltdm_mpu,
75 &omap5_voltdm_mm,
76 &omap5_voltdm_core,
77 &omap5_voltdm_wkup,
78 NULL,
79};
80
81static const char *sys_clk_name __initdata = "sys_clkin";
82
83void __init omap54xx_voltagedomains_init(void)
84{
85 struct voltagedomain *voltdm;
86 int i;
87
88 for (i = 0; voltdm = voltagedomains_omap5[i], voltdm; i++)
89 voltdm->sys_clk.name = sys_clk_name;
90
91 voltdm_init(voltagedomains_omap5);
92};
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-13 10:22:37 -0400