Merge remote-tracking branch 'linus/master' into testing

author: Sage Weil <sage@inktank.com> 2013-08-15 14:11:45 -0400
committer: Sage Weil <sage@inktank.com> 2013-08-15 14:11:45 -0400
commit: ee3e542fec6e69bc9fb668698889a37d93950ddf (patch)
tree: e74ee766a4764769ef1d3d45d266b4dea64101d3 /arch/arm
parent: fe2a801b50c0bb8039d627e5ae1fec249d10ff39 (diff)
parent: f1d6e17f540af37bb1891480143669ba7636c4cf (diff)
1189 files changed, 41724 insertions, 35968 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 136f263ed47b..43594d5116ef 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -9,17 +9,17 @@ config ARM
        select BUILDTIME_EXTABLE_SORT if MMU
        select CPU_PM if (SUSPEND || CPU_IDLE)
        select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
-        select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
+        select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
        select GENERIC_CLOCKEVENTS_BROADCAST if SMP
        select GENERIC_IRQ_PROBE
        select GENERIC_IRQ_SHOW
        select GENERIC_PCI_IOMAP
+        select GENERIC_SCHED_CLOCK
        select GENERIC_SMP_IDLE_THREAD
        select GENERIC_IDLE_POLL_SETUP
        select GENERIC_STRNCPY_FROM_USER
        select GENERIC_STRNLEN_USER
        select HARDIRQS_SW_RESEND
-        select HAVE_AOUT
        select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
        select HAVE_ARCH_KGDB
        select HAVE_ARCH_SECCOMP_FILTER
@@ -40,6 +40,7 @@ config ARM
        select HAVE_IDE if PCI || ISA || PCMCIA
        select HAVE_IRQ_TIME_ACCOUNTING
        select HAVE_KERNEL_GZIP
+        select HAVE_KERNEL_LZ4
        select HAVE_KERNEL_LZMA
        select HAVE_KERNEL_LZO
        select HAVE_KERNEL_XZ
@@ -175,6 +176,9 @@ config ARCH_HAS_CPUFREQ
          and that the relevant menu configurations are displayed for
          it.
+config ARCH_HAS_BANDGAP
+        bool
 config GENERIC_HWEIGHT
        bool
        default y
@@ -213,7 +217,8 @@ config VECTORS_BASE
        default DRAM_BASE if REMAP_VECTORS_TO_RAM
        default 0x00000000
        help
-          The base address of exception vectors.
+          The base address of exception vectors.  This must be two pages
+          in size.
 config ARM_PATCH_PHYS_VIRT
        bool "Patch physical to virtual translations at runtime" if EMBEDDED
@@ -366,11 +371,12 @@ config ARCH_CLPS711X
        select ARCH_REQUIRE_GPIOLIB
        select AUTO_ZRELADDR
        select CLKDEV_LOOKUP
+        select CLKSRC_MMIO
        select COMMON_CLK
        select CPU_ARM720T
        select GENERIC_CLOCKEVENTS
+        select MFD_SYSCON
        select MULTI_IRQ_HANDLER
-        select NEED_MACH_MEMORY_H
        select SPARSE_IRQ
        help
          Support for Cirrus Logic 711x/721x/731x based boards.
@@ -502,6 +508,7 @@ config ARCH_DOVE
 config ARCH_KIRKWOOD
        bool "Marvell Kirkwood"
+        select ARCH_HAS_CPUFREQ
        select ARCH_REQUIRE_GPIOLIB
        select CPU_FEROCEON
        select GENERIC_CLOCKEVENTS
@@ -623,8 +630,8 @@ config ARCH_MSM
        bool "Qualcomm MSM"
        select ARCH_REQUIRE_GPIOLIB
        select CLKDEV_LOOKUP
+        select COMMON_CLK
        select GENERIC_CLOCKEVENTS
-        select HAVE_CLK
        help
          Support for Qualcomm MSM/QSD based systems.  This runs on the
          apps processor of the MSM/QSD and depends on a shared memory
@@ -634,6 +641,7 @@ config ARCH_MSM
 config ARCH_SHMOBILE
        bool "Renesas SH-Mobile / R-Mobile"
+        select ARM_PATCH_PHYS_VIRT
        select CLKDEV_LOOKUP
        select GENERIC_CLOCKEVENTS
        select HAVE_ARM_SCU if SMP
@@ -643,9 +651,8 @@ config ARCH_SHMOBILE
        select HAVE_SMP
        select MIGHT_HAVE_CACHE_L2X0
        select MULTI_IRQ_HANDLER
-        select NEED_MACH_MEMORY_H
        select NO_IOPORT
-        select PINCTRL if ARCH_WANT_OPTIONAL_GPIOLIB
+        select PINCTRL
        select PM_GENERIC_DOMAINS if PM
        select SPARSE_IRQ
        help
@@ -695,6 +702,7 @@ config ARCH_S3C24XX
        select CLKDEV_LOOKUP
        select CLKSRC_MMIO
        select GENERIC_CLOCKEVENTS
+        select GPIO_SAMSUNG
        select HAVE_CLK
        select HAVE_S3C2410_I2C if I2C
        select HAVE_S3C2410_WATCHDOG if WATCHDOG
@@ -702,6 +710,7 @@ config ARCH_S3C24XX
        select MULTI_IRQ_HANDLER
        select NEED_MACH_GPIO_H
        select NEED_MACH_IO_H
+        select SAMSUNG_ATAGS
        help
          Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
          and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
@@ -717,6 +726,7 @@ config ARCH_S3C64XX
        select CLKSRC_MMIO
        select CPU_V6
        select GENERIC_CLOCKEVENTS
+        select GPIO_SAMSUNG
        select HAVE_CLK
        select HAVE_S3C2410_I2C if I2C
        select HAVE_S3C2410_WATCHDOG if WATCHDOG
@@ -726,9 +736,11 @@ config ARCH_S3C64XX
        select PLAT_SAMSUNG
        select S3C_DEV_NAND
        select S3C_GPIO_TRACK
+        select SAMSUNG_ATAGS
        select SAMSUNG_CLKSRC
        select SAMSUNG_GPIOLIB_4BIT
        select SAMSUNG_IRQ_VIC_TIMER
+        select SAMSUNG_WDT_RESET
        select USB_ARCH_HAS_OHCI
        help
          Samsung S3C64XX series based systems
@@ -739,11 +751,14 @@ config ARCH_S5P64X0
        select CLKSRC_MMIO
        select CPU_V6
        select GENERIC_CLOCKEVENTS
+        select GPIO_SAMSUNG
        select HAVE_CLK
        select HAVE_S3C2410_I2C if I2C
        select HAVE_S3C2410_WATCHDOG if WATCHDOG
        select HAVE_S3C_RTC if RTC_CLASS
        select NEED_MACH_GPIO_H
+        select SAMSUNG_WDT_RESET
+        select SAMSUNG_ATAGS
        help
          Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
          SMDK6450.
@@ -755,11 +770,14 @@ config ARCH_S5PC100
        select CLKSRC_MMIO
        select CPU_V7
        select GENERIC_CLOCKEVENTS
+        select GPIO_SAMSUNG
        select HAVE_CLK
        select HAVE_S3C2410_I2C if I2C
        select HAVE_S3C2410_WATCHDOG if WATCHDOG
        select HAVE_S3C_RTC if RTC_CLASS
        select NEED_MACH_GPIO_H
+        select SAMSUNG_WDT_RESET
+        select SAMSUNG_ATAGS
        help
          Samsung S5PC100 series based systems
@@ -772,12 +790,14 @@ config ARCH_S5PV210
        select CLKSRC_MMIO
        select CPU_V7
        select GENERIC_CLOCKEVENTS
+        select GPIO_SAMSUNG
        select HAVE_CLK
        select HAVE_S3C2410_I2C if I2C
        select HAVE_S3C2410_WATCHDOG if WATCHDOG
        select HAVE_S3C_RTC if RTC_CLASS
        select NEED_MACH_GPIO_H
        select NEED_MACH_MEMORY_H
+        select SAMSUNG_ATAGS
        help
          Samsung S5PV210/S5PC110 series based systems
@@ -785,7 +805,9 @@ config ARCH_EXYNOS
        bool "Samsung EXYNOS"
        select ARCH_HAS_CPUFREQ
        select ARCH_HAS_HOLES_MEMORYMODEL
+        select ARCH_REQUIRE_GPIOLIB
        select ARCH_SPARSEMEM_ENABLE
+        select ARM_GIC
        select CLKDEV_LOOKUP
        select COMMON_CLK
        select CPU_V7
@@ -794,8 +816,9 @@ config ARCH_EXYNOS
        select HAVE_S3C2410_I2C if I2C
        select HAVE_S3C2410_WATCHDOG if WATCHDOG
        select HAVE_S3C_RTC if RTC_CLASS
-        select NEED_MACH_GPIO_H
        select NEED_MACH_MEMORY_H
+        select SPARSE_IRQ
+        select USE_OF
        help
          Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
@@ -813,23 +836,6 @@ config ARCH_SHARK
          Support for the StrongARM based Digital DNARD machine, also known
          as "Shark" (<http://www.shark-linux.de/shark.html>).
-config ARCH_U300
-        bool "ST-Ericsson U300 Series"
-        depends on MMU
-        select ARCH_REQUIRE_GPIOLIB
-        select ARM_AMBA
-        select ARM_PATCH_PHYS_VIRT
-        select ARM_VIC
-        select CLKDEV_LOOKUP
-        select CLKSRC_MMIO
-        select COMMON_CLK
-        select CPU_ARM926T
-        select GENERIC_CLOCKEVENTS
-        select HAVE_TCM
-        select SPARSE_IRQ
-        help
-          Support for ST-Ericsson U300 series mobile platforms.
 config ARCH_DAVINCI
        bool "TI DaVinci"
        select ARCH_HAS_HOLES_MEMORYMODEL
@@ -840,6 +846,7 @@ config ARCH_DAVINCI
        select GENERIC_IRQ_CHIP
        select HAVE_IDE
        select NEED_MACH_GPIO_H
+        select TI_PRIV_EDMA
        select USE_OF
        select ZONE_DMA
        help
@@ -871,20 +878,21 @@ menu "Multiple platform selection"
 comment "CPU Core family selection"
-config ARCH_MULTI_V4
-        bool "ARMv4 based platforms (FA526, StrongARM)"
-        depends on !ARCH_MULTI_V6_V7
-        select ARCH_MULTI_V4_V5
 config ARCH_MULTI_V4T
        bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
        depends on !ARCH_MULTI_V6_V7
        select ARCH_MULTI_V4_V5
+        select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
+                CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
+                CPU_ARM925T || CPU_ARM940T)
 config ARCH_MULTI_V5
        bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
        depends on !ARCH_MULTI_V6_V7
        select ARCH_MULTI_V4_V5
+        select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
+                CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
+                CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 config ARCH_MULTI_V4_V5
        bool
@@ -948,6 +956,8 @@ source "arch/arm/mach-iop13xx/Kconfig"
 source "arch/arm/mach-ixp4xx/Kconfig"
+source "arch/arm/mach-keystone/Kconfig"
 source "arch/arm/mach-kirkwood/Kconfig"
 source "arch/arm/mach-ks8695/Kconfig"
@@ -964,6 +974,8 @@ source "arch/arm/mach-netx/Kconfig"
 source "arch/arm/mach-nomadik/Kconfig"
+source "arch/arm/mach-nspire/Kconfig"
 source "arch/arm/plat-omap/Kconfig"
 source "arch/arm/mach-omap1/Kconfig"
@@ -981,6 +993,8 @@ source "arch/arm/mach-mmp/Kconfig"
 source "arch/arm/mach-realview/Kconfig"
+source "arch/arm/mach-rockchip/Kconfig"
 source "arch/arm/mach-sa1100/Kconfig"
 source "arch/arm/plat-samsung/Kconfig"
@@ -989,6 +1003,8 @@ source "arch/arm/mach-socfpga/Kconfig"
 source "arch/arm/mach-spear/Kconfig"
+source "arch/arm/mach-sti/Kconfig"
 source "arch/arm/mach-s3c24xx/Kconfig"
 if ARCH_S3C64XX
@@ -1300,7 +1316,7 @@ config ARM_ERRATA_754327
 config ARM_ERRATA_364296
        bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
-        depends on CPU_V6 && !SMP
+        depends on CPU_V6
        help
          This options enables the workaround for the 364296 ARM1136
          r0p2 erratum (possible cache data corruption with
@@ -1417,6 +1433,7 @@ config PCI_HOST_ITE8152
        select DMABOUNCE
 source "drivers/pci/Kconfig"
+source "drivers/pci/pcie/Kconfig"
 source "drivers/pcmcia/Kconfig"
@@ -1438,7 +1455,7 @@ config SMP
        depends on CPU_V6K || CPU_V7
        depends on GENERIC_CLOCKEVENTS
        depends on HAVE_SMP
-        depends on MMU
+        depends on MMU || ARM_MPU
        select USE_GENERIC_SMP_HELPERS
        help
          This enables support for systems with more than one CPU. If you have
@@ -1459,7 +1476,7 @@ config SMP
 config SMP_ON_UP
        bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
-        depends on SMP && !XIP_KERNEL
+        depends on SMP && !XIP_KERNEL && MMU
        default y
        help
          SMP kernels contain instructions which fail on non-SMP processors.
@@ -1552,7 +1569,7 @@ config NR_CPUS
 config HOTPLUG_CPU
        bool "Support for hot-pluggable CPUs"
-        depends on SMP && HOTPLUG
+        depends on SMP
        help
          Say Y here to experiment with turning CPUs off and on.  CPUs
          can be controlled through /sys/devices/system/cpu.
@@ -1583,7 +1600,7 @@ config LOCAL_TIMERS
 config ARCH_NR_GPIO
        int
        default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
-        default 512 if SOC_OMAP5
+        default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5
        default 392 if ARCH_U8500
        default 352 if ARCH_VT8500
        default 288 if ARCH_SUNXI
@@ -1609,7 +1626,7 @@ config SCHED_HRTICK
 config THUMB2_KERNEL
        bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
-        depends on CPU_V7 && !CPU_V6 && !CPU_V6K
+        depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
        default y if CPU_THUMBONLY
        select AEABI
        select ARM_ASM_UNIFIED
@@ -1731,6 +1748,14 @@ config HW_PERF_EVENTS
          Enable hardware performance counter support for perf events. If
          disabled, perf events will use software events only.
+config SYS_SUPPORTS_HUGETLBFS
+       def_bool y
+       depends on ARM_LPAE
+config HAVE_ARCH_TRANSPARENT_HUGEPAGE
+       def_bool y
+       depends on ARM_LPAE
 source "mm/Kconfig"
 config FORCE_MAX_ZONEORDER
@@ -2064,7 +2089,7 @@ config CRASH_DUMP
 config AUTO_ZRELADDR
        bool "Auto calculation of the decompressed kernel image address"
-        depends on !ZBOOT_ROM && !ARCH_U300
+        depends on !ZBOOT_ROM
        help
          ZRELADDR is the physical address where the decompressed kernel
          image will be placed. If AUTO_ZRELADDR is selected, the address
@@ -2078,53 +2103,6 @@ menu "CPU Power Management"
 if ARCH_HAS_CPUFREQ
 source "drivers/cpufreq/Kconfig"
-config CPU_FREQ_S3C
-        bool
-        help
-          Internal configuration node for common cpufreq on Samsung SoC
-config CPU_FREQ_S3C24XX
-        bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
-        depends on ARCH_S3C24XX && CPU_FREQ
-        select CPU_FREQ_S3C
-        help
-          This enables the CPUfreq driver for the Samsung S3C24XX family
-          of CPUs.
-          For details, take a look at <file:Documentation/cpu-freq>.
-          If in doubt, say N.
-config CPU_FREQ_S3C24XX_PLL
-        bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
-        depends on CPU_FREQ_S3C24XX
-        help
-          Compile in support for changing the PLL frequency from the
-          S3C24XX series CPUfreq driver. The PLL takes time to settle
-          after a frequency change, so by default it is not enabled.
-          This also means that the PLL tables for the selected CPU(s) will
-          be built which may increase the size of the kernel image.
-config CPU_FREQ_S3C24XX_DEBUG
-        bool "Debug CPUfreq Samsung driver core"
-        depends on CPU_FREQ_S3C24XX
-        help
-          Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
-config CPU_FREQ_S3C24XX_IODEBUG
-        bool "Debug CPUfreq Samsung driver IO timing"
-        depends on CPU_FREQ_S3C24XX
-        help
-          Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
-config CPU_FREQ_S3C24XX_DEBUGFS
-        bool "Export debugfs for CPUFreq"
-        depends on CPU_FREQ_S3C24XX && DEBUG_FS
-        help
-          Export status information via debugfs.
 endif
 source "drivers/cpuidle/Kconfig"
diff --git a/arch/arm/Kconfig-nommu b/arch/arm/Kconfig-nommu
index 2cef8e13f9f8..aed66d5df7f1 100644
--- a/arch/arm/Kconfig-nommu
+++ b/arch/arm/Kconfig-nommu
@@ -28,7 +28,7 @@ config FLASH_SIZE
 config PROCESSOR_ID
        hex 'Hard wire the processor ID'
        default 0x00007700
-        depends on !CPU_CP15
+        depends on !(CPU_CP15 || CPU_V7M)
        help
          If processor has no CP15 register, this processor ID is
          used instead of the auto-probing which utilizes the register.
@@ -50,3 +50,15 @@ config REMAP_VECTORS_TO_RAM
          Otherwise, say 'y' here.  In this case, the kernel will require
          external support to redirect the hardware exception vectors to
          the writable versions located at DRAM_BASE.
+config ARM_MPU
+       bool 'Use the ARM v7 PMSA Compliant MPU'
+       depends on CPU_V7
+       default y
+       help
+         Some ARM systems without an MMU have instead a Memory Protection
+         Unit (MPU) that defines the type and permissions for regions of
+         memory.
+         If your CPU has an MPU then you should choose 'y' here unless you
+         know that you do not want to use the MPU.
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 1d41908d5cda..583f4a00ec32 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -251,6 +251,27 @@ choice
                  Say Y here if you want kernel low-level debugging support
                  on i.MX6Q/DL.
+        config DEBUG_IMX6SL_UART
+                bool "i.MX6SL Debug UART"
+                depends on SOC_IMX6SL
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on i.MX6SL.
+        config DEBUG_KEYSTONE_UART0
+                bool "Kernel low-level debugging on KEYSTONE2 using UART0"
+                depends on ARCH_KEYSTONE
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to UART0 serial port on KEYSTONE2 devices.
+        config DEBUG_KEYSTONE_UART1
+                bool "Kernel low-level debugging on KEYSTONE2 using UART1"
+                depends on ARCH_KEYSTONE
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to UART1 serial port on KEYSTONE2 devices.
        config DEBUG_MMP_UART2
                bool "Kernel low-level debugging message via MMP UART2"
                depends on ARCH_MMP
@@ -303,12 +324,37 @@ choice
                  their output to the serial port on MSM 8960 devices.
        config DEBUG_MVEBU_UART
-                bool "Kernel low-level debugging messages via MVEBU UART"
+                bool "Kernel low-level debugging messages via MVEBU UART (old bootloaders)"
+                depends on ARCH_MVEBU
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on MVEBU based platforms.
+                  This option should be used with the old bootloaders
+                  that left the internal registers mapped at
+                  0xd0000000. As of today, this is the case on
+                  platforms such as the Globalscale Mirabox or the
+                  Plathome OpenBlocks AX3, when using the original
+                  bootloader.
+                  If the wrong DEBUG_MVEBU_UART* option is selected,
+                  when u-boot hands over to the kernel, the system
+                  silently crashes, with no serial output at all.
+        config DEBUG_MVEBU_UART_ALTERNATE
+                bool "Kernel low-level debugging messages via MVEBU UART (new bootloaders)"
                depends on ARCH_MVEBU
                help
                  Say Y here if you want kernel low-level debugging support
                  on MVEBU based platforms.
+                  This option should be used with the new bootloaders
+                  that remap the internal registers at 0xf1000000.
+                  If the wrong DEBUG_MVEBU_UART* option is selected,
+                  when u-boot hands over to the kernel, the system
+                  silently crashes, with no serial output at all.
        config DEBUG_NOMADIK_UART
                bool "Kernel low-level debugging messages via NOMADIK UART"
                depends on ARCH_NOMADIK
@@ -316,6 +362,20 @@ choice
                  Say Y here if you want kernel low-level debugging support
                  on NOMADIK based platforms.
+        config DEBUG_NSPIRE_CLASSIC_UART
+                bool "Kernel low-level debugging via TI-NSPIRE 8250 UART"
+                depends on ARCH_NSPIRE
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on TI-NSPIRE classic models.
+        config DEBUG_NSPIRE_CX_UART
+                bool "Kernel low-level debugging via TI-NSPIRE PL011 UART"
+                depends on ARCH_NSPIRE
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on TI-NSPIRE CX models.
        config DEBUG_OMAP2PLUS_UART
                bool "Kernel low-level debugging messages via OMAP2PLUS UART"
                depends on ARCH_OMAP2PLUS
@@ -353,6 +413,13 @@ choice
                  their output to the standard serial port on the RealView
                  PB1176 platform.
+        config DEBUG_ROCKCHIP_UART
+                bool "Kernel low-level debugging messages via Rockchip UART"
+                depends on ARCH_ROCKCHIP
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on Rockchip based platforms.
        config DEBUG_S3C_UART0
                depends on PLAT_SAMSUNG
                select DEBUG_EXYNOS_UART if ARCH_EXYNOS
@@ -443,6 +510,23 @@ choice
                  Say Y here if you want the debug print routines to direct
                  their output to the uart1 port on SiRFmarco devices.
+        config DEBUG_STI_UART
+                depends on ARCH_STI
+                bool "Use StiH415/416 ASC for low-level debug"
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on StiH415/416 based platforms like B2000, B2020.
+                  It support UART2 and SBC_UART1.
+                  If unsure, say N.
+        config DEBUG_U300_UART
+                bool "Kernel low-level debugging messages via U300 UART0"
+                depends on ARCH_U300
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to the uart port on U300 devices.
        config DEBUG_UX500_UART
                depends on ARCH_U8500
                bool "Use Ux500 UART for low-level debug"
@@ -476,6 +560,13 @@ choice
                  of the tiles using the RS1 memory map, including all new A-class
                  core tiles, FPGA-based SMMs and software models.
+        config DEBUG_VEXPRESS_UART0_CRX
+                bool "Use PL011 UART0 at 0xb0090000 (Cortex-R compliant tiles)"
+                depends on ARCH_VEXPRESS && !MMU
+                help
+                  This option selects UART0 at 0xb0090000. This is appropriate for
+                  Cortex-R series tiles and SMMs, such as Cortex-R5 and Cortex-R7
        config DEBUG_VT8500_UART0
                bool "Use UART0 on VIA/Wondermedia SoCs"
                depends on ARCH_VT8500
@@ -532,7 +623,8 @@ config DEBUG_IMX_UART_PORT
                                                DEBUG_IMX35_UART || \
                                                DEBUG_IMX51_UART || \
                                                DEBUG_IMX53_UART || \
-                                                DEBUG_IMX6Q_UART
+                                                DEBUG_IMX6Q_UART || \
+                                                DEBUG_IMX6SL_UART
        default 1
        depends on ARCH_MXC
        help
@@ -589,6 +681,32 @@ endchoice
 choice
        prompt "Low-level debug console UART"
+        depends on DEBUG_ROCKCHIP_UART
+        config DEBUG_RK29_UART0
+                bool "RK29 UART0"
+        config DEBUG_RK29_UART1
+                bool "RK29 UART1"
+        config DEBUG_RK29_UART2
+                bool "RK29 UART2"
+        config DEBUG_RK3X_UART0
+                bool "RK3X UART0"
+        config DEBUG_RK3X_UART1
+                bool "RK3X UART1"
+        config DEBUG_RK3X_UART2
+                bool "RK3X UART2"
+        config DEBUG_RK3X_UART3
+                bool "RK3X UART3"
+endchoice
+choice
+        prompt "Low-level debug console UART"
        depends on DEBUG_LL && DEBUG_TEGRA_UART
        config TEGRA_DEBUG_UART_AUTO_ODMDATA
@@ -617,6 +735,30 @@ choice
 endchoice
+choice
+        prompt "Low-level debug console UART"
+        depends on DEBUG_LL && DEBUG_STI_UART
+        config STIH41X_DEBUG_ASC2
+                bool "ASC2 UART"
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on STiH415/416 based platforms like b2000, which has
+                  default UART wired up to ASC2.
+                  If unsure, say N.
+        config STIH41X_DEBUG_SBC_ASC1
+                bool "SBC ASC1 UART"
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on STiH415/416 based platforms like b2020. which has
+                  default UART wired up to SBC ASC1.
+                  If unsure, say N.
+endchoice
 config DEBUG_LL_INCLUDE
        string
        default "debug/bcm2835.S" if DEBUG_BCM2835
@@ -631,30 +773,50 @@ config DEBUG_LL_INCLUDE
                                 DEBUG_IMX35_UART || \
                                 DEBUG_IMX51_UART || \
                                 DEBUG_IMX53_UART ||\
-                                 DEBUG_IMX6Q_UART
+                                 DEBUG_IMX6Q_UART || \
-        default "debug/mvebu.S" if DEBUG_MVEBU_UART
+                                 DEBUG_IMX6SL_UART
+        default "debug/keystone.S" if DEBUG_KEYSTONE_UART0 || \
+                                      DEBUG_KEYSTONE_UART1
+        default "debug/mvebu.S" if DEBUG_MVEBU_UART || \
+                                   DEBUG_MVEBU_UART_ALTERNATE
        default "debug/mxs.S" if DEBUG_IMX23_UART || DEBUG_IMX28_UART
        default "debug/nomadik.S" if DEBUG_NOMADIK_UART
+        default "debug/nspire.S" if     DEBUG_NSPIRE_CX_UART || \
+                                        DEBUG_NSPIRE_CLASSIC_UART
        default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
        default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART
        default "debug/pxa.S" if DEBUG_PXA_UART1 || DEBUG_MMP_UART2 || \
                                 DEBUG_MMP_UART3
+        default "debug/rockchip.S" if DEBUG_ROCKCHIP_UART
        default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1
        default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
+        default "debug/sti.S" if DEBUG_STI_UART
        default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1
        default "debug/tegra.S" if DEBUG_TEGRA_UART
+        default "debug/u300.S" if DEBUG_U300_UART
        default "debug/ux500.S" if DEBUG_UX500_UART
        default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
-                DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1
+                DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1 || \
+                DEBUG_VEXPRESS_UART0_CRX
        default "debug/vt8500.S" if DEBUG_VT8500_UART0
        default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1
        default "mach/debug-macro.S"
 config DEBUG_UNCOMPRESS
        bool
-        default y if ARCH_MULTIPLATFORM && DEBUG_LL && \
+        depends on ARCH_MULTIPLATFORM
-                     !DEBUG_OMAP2PLUS_UART && \
+        default y if DEBUG_LL && !DEBUG_OMAP2PLUS_UART && \
                     !DEBUG_TEGRA_UART
+        help
+          This option influences the normal decompressor output for
+          multiplatform kernels.  Normally, multiplatform kernels disable
+          decompressor output because it is not possible to know where to
+          send the decompressor output.
+          When this option is set, the selected DEBUG_LL output method
+          will be re-used for normal decompressor output on multiplatform
+          kernels.
+          
 config UNCOMPRESS_INCLUDE
        string
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 1ba358ba16b8..6fd2ceae305a 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -59,37 +59,44 @@ comma = ,
 # Note that GCC does not numerically define an architecture version
 # macro, but instead defines a whole series of macros which makes
 # testing for a specific architecture or later rather impossible.
-arch-$(CONFIG_CPU_32v7)         :=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a)
+arch-$(CONFIG_CPU_32v7M)        =-D__LINUX_ARM_ARCH__=7 -march=armv7-m -Wa,-march=armv7-m
-arch-$(CONFIG_CPU_32v6)         :=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6)
+arch-$(CONFIG_CPU_32v7)         =-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a)
+arch-$(CONFIG_CPU_32v6)         =-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6)
 # Only override the compiler option if ARMv6. The ARMv6K extensions are
 # always available in ARMv7
 ifeq ($(CONFIG_CPU_32v6),y)
-arch-$(CONFIG_CPU_32v6K)        :=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6k,-march=armv5t -Wa$(comma)-march=armv6k)
+arch-$(CONFIG_CPU_32v6K)        =-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6k,-march=armv5t -Wa$(comma)-march=armv6k)
 endif
-arch-$(CONFIG_CPU_32v5)         :=-D__LINUX_ARM_ARCH__=5 $(call cc-option,-march=armv5te,-march=armv4t)
+arch-$(CONFIG_CPU_32v5)         =-D__LINUX_ARM_ARCH__=5 $(call cc-option,-march=armv5te,-march=armv4t)
-arch-$(CONFIG_CPU_32v4T)        :=-D__LINUX_ARM_ARCH__=4 -march=armv4t
+arch-$(CONFIG_CPU_32v4T)        =-D__LINUX_ARM_ARCH__=4 -march=armv4t
-arch-$(CONFIG_CPU_32v4)         :=-D__LINUX_ARM_ARCH__=4 -march=armv4
+arch-$(CONFIG_CPU_32v4)         =-D__LINUX_ARM_ARCH__=4 -march=armv4
-arch-$(CONFIG_CPU_32v3)         :=-D__LINUX_ARM_ARCH__=3 -march=armv3
+arch-$(CONFIG_CPU_32v3)         =-D__LINUX_ARM_ARCH__=3 -march=armv3
+# Evaluate arch cc-option calls now
+arch-y := $(arch-y)
 # This selects how we optimise for the processor.
-tune-$(CONFIG_CPU_ARM7TDMI)     :=-mtune=arm7tdmi
+tune-$(CONFIG_CPU_ARM7TDMI)     =-mtune=arm7tdmi
-tune-$(CONFIG_CPU_ARM720T)      :=-mtune=arm7tdmi
+tune-$(CONFIG_CPU_ARM720T)      =-mtune=arm7tdmi
-tune-$(CONFIG_CPU_ARM740T)      :=-mtune=arm7tdmi
+tune-$(CONFIG_CPU_ARM740T)      =-mtune=arm7tdmi
-tune-$(CONFIG_CPU_ARM9TDMI)     :=-mtune=arm9tdmi
+tune-$(CONFIG_CPU_ARM9TDMI)     =-mtune=arm9tdmi
-tune-$(CONFIG_CPU_ARM940T)      :=-mtune=arm9tdmi
+tune-$(CONFIG_CPU_ARM940T)      =-mtune=arm9tdmi
-tune-$(CONFIG_CPU_ARM946E)      :=$(call cc-option,-mtune=arm9e,-mtune=arm9tdmi)
+tune-$(CONFIG_CPU_ARM946E)      =$(call cc-option,-mtune=arm9e,-mtune=arm9tdmi)
-tune-$(CONFIG_CPU_ARM920T)      :=-mtune=arm9tdmi
+tune-$(CONFIG_CPU_ARM920T)      =-mtune=arm9tdmi
-tune-$(CONFIG_CPU_ARM922T)      :=-mtune=arm9tdmi
+tune-$(CONFIG_CPU_ARM922T)      =-mtune=arm9tdmi
-tune-$(CONFIG_CPU_ARM925T)      :=-mtune=arm9tdmi
+tune-$(CONFIG_CPU_ARM925T)      =-mtune=arm9tdmi
-tune-$(CONFIG_CPU_ARM926T)      :=-mtune=arm9tdmi
+tune-$(CONFIG_CPU_ARM926T)      =-mtune=arm9tdmi
-tune-$(CONFIG_CPU_FA526)        :=-mtune=arm9tdmi
+tune-$(CONFIG_CPU_FA526)        =-mtune=arm9tdmi
-tune-$(CONFIG_CPU_SA110)        :=-mtune=strongarm110
+tune-$(CONFIG_CPU_SA110)        =-mtune=strongarm110
-tune-$(CONFIG_CPU_SA1100)       :=-mtune=strongarm1100
+tune-$(CONFIG_CPU_SA1100)       =-mtune=strongarm1100
-tune-$(CONFIG_CPU_XSCALE)       :=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale
+tune-$(CONFIG_CPU_XSCALE)       =$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale
-tune-$(CONFIG_CPU_XSC3)         :=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale
+tune-$(CONFIG_CPU_XSC3)         =$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale
-tune-$(CONFIG_CPU_FEROCEON)     :=$(call cc-option,-mtune=marvell-f,-mtune=xscale)
+tune-$(CONFIG_CPU_FEROCEON)     =$(call cc-option,-mtune=marvell-f,-mtune=xscale)
-tune-$(CONFIG_CPU_V6)           :=$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm)
+tune-$(CONFIG_CPU_V6)           =$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm)
-tune-$(CONFIG_CPU_V6K)          :=$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm)
+tune-$(CONFIG_CPU_V6K)          =$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm)
+# Evaluate tune cc-option calls now
+tune-y := $(tune-y)
 ifeq ($(CONFIG_AEABI),y)
 CFLAGS_ABI      :=-mabi=aapcs-linux -mno-thumb-interwork
@@ -146,6 +153,7 @@ machine-$(CONFIG_ARCH_DAVINCI)		+= davinci
 machine-$(CONFIG_ARCH_DOVE)             += dove
 machine-$(CONFIG_ARCH_EBSA110)          += ebsa110
 machine-$(CONFIG_ARCH_EP93XX)           += ep93xx
+machine-$(CONFIG_ARCH_EXYNOS)           += exynos
 machine-$(CONFIG_ARCH_GEMINI)           += gemini
 machine-$(CONFIG_ARCH_HIGHBANK)         += highbank
 machine-$(CONFIG_ARCH_INTEGRATOR)       += integrator
@@ -153,50 +161,54 @@ machine-$(CONFIG_ARCH_IOP13XX)		+= iop13xx
 machine-$(CONFIG_ARCH_IOP32X)           += iop32x
 machine-$(CONFIG_ARCH_IOP33X)           += iop33x
 machine-$(CONFIG_ARCH_IXP4XX)           += ixp4xx
+machine-$(CONFIG_ARCH_KEYSTONE)         += keystone
 machine-$(CONFIG_ARCH_KIRKWOOD)         += kirkwood
 machine-$(CONFIG_ARCH_KS8695)           += ks8695
 machine-$(CONFIG_ARCH_LPC32XX)          += lpc32xx
 machine-$(CONFIG_ARCH_MMP)              += mmp
 machine-$(CONFIG_ARCH_MSM)              += msm
 machine-$(CONFIG_ARCH_MV78XX0)          += mv78xx0
+machine-$(CONFIG_ARCH_MVEBU)            += mvebu
 machine-$(CONFIG_ARCH_MXC)              += imx
 machine-$(CONFIG_ARCH_MXS)              += mxs
-machine-$(CONFIG_ARCH_MVEBU)            += mvebu
 machine-$(CONFIG_ARCH_NETX)             += netx
 machine-$(CONFIG_ARCH_NOMADIK)          += nomadik
+machine-$(CONFIG_ARCH_NSPIRE)           += nspire
 machine-$(CONFIG_ARCH_OMAP1)            += omap1
 machine-$(CONFIG_ARCH_OMAP2PLUS)        += omap2
 machine-$(CONFIG_ARCH_ORION5X)          += orion5x
 machine-$(CONFIG_ARCH_PICOXCELL)        += picoxcell
-machine-$(CONFIG_ARCH_PRIMA2)           += prima2
 machine-$(CONFIG_ARCH_PXA)              += pxa
 machine-$(CONFIG_ARCH_REALVIEW)         += realview
+machine-$(CONFIG_ARCH_ROCKCHIP)         += rockchip
 machine-$(CONFIG_ARCH_RPC)              += rpc
 machine-$(CONFIG_ARCH_S3C24XX)          += s3c24xx
 machine-$(CONFIG_ARCH_S3C64XX)          += s3c64xx
 machine-$(CONFIG_ARCH_S5P64X0)          += s5p64x0
 machine-$(CONFIG_ARCH_S5PC100)          += s5pc100
 machine-$(CONFIG_ARCH_S5PV210)          += s5pv210
-machine-$(CONFIG_ARCH_EXYNOS)           += exynos
 machine-$(CONFIG_ARCH_SA1100)           += sa1100
 machine-$(CONFIG_ARCH_SHARK)            += shark
 machine-$(CONFIG_ARCH_SHMOBILE)         += shmobile
+machine-$(CONFIG_ARCH_SIRF)             += prima2
+machine-$(CONFIG_ARCH_SOCFPGA)          += socfpga
+machine-$(CONFIG_ARCH_STI)              += sti
+machine-$(CONFIG_ARCH_SUNXI)            += sunxi
 machine-$(CONFIG_ARCH_TEGRA)            += tegra
 machine-$(CONFIG_ARCH_U300)             += u300
 machine-$(CONFIG_ARCH_U8500)            += ux500
 machine-$(CONFIG_ARCH_VERSATILE)        += versatile
 machine-$(CONFIG_ARCH_VEXPRESS)         += vexpress
+machine-$(CONFIG_ARCH_VIRT)             += virt
 machine-$(CONFIG_ARCH_VT8500)           += vt8500
 machine-$(CONFIG_ARCH_W90X900)          += w90x900
+machine-$(CONFIG_ARCH_ZYNQ)             += zynq
 machine-$(CONFIG_FOOTBRIDGE)            += footbridge
-machine-$(CONFIG_ARCH_SOCFPGA)          += socfpga
 machine-$(CONFIG_PLAT_SPEAR)            += spear
-machine-$(CONFIG_ARCH_VIRT)             += virt
-machine-$(CONFIG_ARCH_ZYNQ)             += zynq
-machine-$(CONFIG_ARCH_SUNXI)            += sunxi
 # Platform directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
+plat-$(CONFIG_ARCH_EXYNOS)      += samsung
 plat-$(CONFIG_ARCH_OMAP)        += omap
 plat-$(CONFIG_ARCH_S3C64XX)     += samsung
 plat-$(CONFIG_PLAT_IOP)         += iop
@@ -289,9 +301,10 @@ zImage Image xipImage bootpImage uImage: vmlinux
 zinstall uinstall install: vmlinux
        $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $@
-%.dtb: scripts
+%.dtb: | scripts
        $(Q)$(MAKE) $(build)=$(boot)/dts MACHINE=$(MACHINE) $(boot)/dts/$@
+PHONY += dtbs
 dtbs: scripts
        $(Q)$(MAKE) $(build)=$(boot)/dts MACHINE=$(MACHINE) dtbs
diff --git a/arch/arm/boot/compressed/.gitignore b/arch/arm/boot/compressed/.gitignore
index f79a08efe000..47279aa96a6a 100644
--- a/arch/arm/boot/compressed/.gitignore
+++ b/arch/arm/boot/compressed/.gitignore
@@ -6,6 +6,7 @@ piggy.gzip
 piggy.lzo
 piggy.lzma
 piggy.xzkern
+piggy.lz4
 vmlinux
 vmlinux.lds
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 120b83bfde20..7ac1610252ba 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -27,7 +27,7 @@ OBJS	+= misc.o decompress.o
 ifeq ($(CONFIG_DEBUG_UNCOMPRESS),y)
 OBJS    += debug.o
 endif
-FONTC   = $(srctree)/drivers/video/console/font_acorn_8x8.c
+FONTC   = $(srctree)/lib/fonts/font_acorn_8x8.c
 # string library code (-Os is enforced to keep it much smaller)
 OBJS            += string.o
@@ -91,6 +91,7 @@ suffix_$(CONFIG_KERNEL_GZIP) = gzip
 suffix_$(CONFIG_KERNEL_LZO)  = lzo
 suffix_$(CONFIG_KERNEL_LZMA) = lzma
 suffix_$(CONFIG_KERNEL_XZ)   = xzkern
+suffix_$(CONFIG_KERNEL_LZ4)  = lz4
 # Borrowed libfdt files for the ATAG compatibility mode
@@ -115,7 +116,7 @@ targets       := vmlinux vmlinux.lds \
                 font.o font.c head.o misc.o $(OBJS)
 # Make sure files are removed during clean
-extra-y       += piggy.gzip piggy.lzo piggy.lzma piggy.xzkern \
+extra-y       += piggy.gzip piggy.lzo piggy.lzma piggy.xzkern piggy.lz4 \
                 lib1funcs.S ashldi3.S $(libfdt) $(libfdt_hdrs) \
                 hyp-stub.S
diff --git a/arch/arm/boot/compressed/atags_to_fdt.c b/arch/arm/boot/compressed/atags_to_fdt.c
index aabc02a68482..d1153c8a765a 100644
--- a/arch/arm/boot/compressed/atags_to_fdt.c
+++ b/arch/arm/boot/compressed/atags_to_fdt.c
@@ -53,6 +53,17 @@ static const void *getprop(const void *fdt, const char *node_path,
        return fdt_getprop(fdt, offset, property, len);
 }
+static uint32_t get_cell_size(const void *fdt)
+{
+        int len;
+        uint32_t cell_size = 1;
+        const uint32_t *size_len =  getprop(fdt, "/", "#size-cells", &len);
+        if (size_len)
+                cell_size = fdt32_to_cpu(*size_len);
+        return cell_size;
+}
 static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
 {
        char cmdline[COMMAND_LINE_SIZE];
@@ -95,9 +106,11 @@ static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
 int atags_to_fdt(void *atag_list, void *fdt, int total_space)
 {
        struct tag *atag = atag_list;
-        uint32_t mem_reg_property[2 * NR_BANKS];
+        /* In the case of 64 bits memory size, need to reserve 2 cells for
+         * address and size for each bank */
+        uint32_t mem_reg_property[2 * 2 * NR_BANKS];
        int memcount = 0;
-        int ret;
+        int ret, memsize;
        /* make sure we've got an aligned pointer */
        if ((u32)atag_list & 0x3)
@@ -137,8 +150,25 @@ int atags_to_fdt(void *atag_list, void *fdt, int total_space)
                                continue;
                        if (!atag->u.mem.size)
                                continue;
-                        mem_reg_property[memcount++] = cpu_to_fdt32(atag->u.mem.start);
+                        memsize = get_cell_size(fdt);
-                        mem_reg_property[memcount++] = cpu_to_fdt32(atag->u.mem.size);
+                        if (memsize == 2) {
+                                /* if memsize is 2, that means that
+                                 * each data needs 2 cells of 32 bits,
+                                 * so the data are 64 bits */
+                                uint64_t *mem_reg_prop64 =
+                                        (uint64_t *)mem_reg_property;
+                                mem_reg_prop64[memcount++] =
+                                        cpu_to_fdt64(atag->u.mem.start);
+                                mem_reg_prop64[memcount++] =
+                                        cpu_to_fdt64(atag->u.mem.size);
+                        } else {
+                                mem_reg_property[memcount++] =
+                                        cpu_to_fdt32(atag->u.mem.start);
+                                mem_reg_property[memcount++] =
+                                        cpu_to_fdt32(atag->u.mem.size);
+                        }
                } else if (atag->hdr.tag == ATAG_INITRD2) {
                        uint32_t initrd_start, initrd_size;
                        initrd_start = atag->u.initrd.start;
@@ -150,8 +180,10 @@ int atags_to_fdt(void *atag_list, void *fdt, int total_space)
                }
        }
-        if (memcount)
+        if (memcount) {
-                setprop(fdt, "/memory", "reg", mem_reg_property, 4*memcount);
+                setprop(fdt, "/memory", "reg", mem_reg_property,
+                        4 * memcount * memsize);
+        }
        return fdt_pack(fdt);
 }
diff --git a/arch/arm/boot/compressed/decompress.c b/arch/arm/boot/compressed/decompress.c
index 24b0475cb8bf..bd245d34952d 100644
--- a/arch/arm/boot/compressed/decompress.c
+++ b/arch/arm/boot/compressed/decompress.c
@@ -51,6 +51,10 @@ extern char * strstr(const char * s1, const char *s2);
 #include "../../../../lib/decompress_unxz.c"
 #endif
+#ifdef CONFIG_KERNEL_LZ4
+#include "../../../../lib/decompress_unlz4.c"
+#endif
 int do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x))
 {
        return decompress(input, len, NULL, NULL, output, NULL, error);
diff --git a/arch/arm/boot/compressed/head-shmobile.S b/arch/arm/boot/compressed/head-shmobile.S
index fe3719b516fd..e2d636336b7c 100644
--- a/arch/arm/boot/compressed/head-shmobile.S
+++ b/arch/arm/boot/compressed/head-shmobile.S
@@ -46,7 +46,7 @@ __image_start:
 __image_end:
        .long   _got_end
 __load_base:
-        .long   CONFIG_MEMORY_START + 0x02000000 @ Load at 32Mb into SDRAM
+        .long   MEMORY_START + 0x02000000 @ Load at 32Mb into SDRAM
 __loaded:
        .long   __continue
        .align
@@ -55,26 +55,9 @@ __tmp_stack:
 __continue:
 #endif /* CONFIG_ZBOOT_ROM_MMC || CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI */
-        b       1f
-__atags:@ tag #1
-        .long   12                      @ tag->hdr.size = tag_size(tag_core);
-        .long   0x54410001              @ tag->hdr.tag = ATAG_CORE;
-        .long   0                       @ tag->u.core.flags = 0;
-        .long   0                       @ tag->u.core.pagesize = 0;
-        .long   0                       @ tag->u.core.rootdev = 0;
-        @ tag #2
-        .long   8                       @ tag->hdr.size = tag_size(tag_mem32);
-        .long   0x54410002              @ tag->hdr.tag = ATAG_MEM;
-        .long   CONFIG_MEMORY_SIZE      @ tag->u.mem.size = CONFIG_MEMORY_SIZE;
-        .long   CONFIG_MEMORY_START     @ @ tag->u.mem.start = CONFIG_MEMORY_START;
-        @ tag #3
-        .long   0                       @ tag->hdr.size = 0
-        .long   0                       @ tag->hdr.tag = ATAG_NONE;
-1:
        /* Set board ID necessary for boot */
        ldr     r7, 1f                          @ Set machine type register
-        adr     r8, __atags                     @ Set atag register
+        mov     r8, #0                          @ pass null pointer as atag
        b       2f
 1 :     .long MACH_TYPE
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 032a8d987148..75189f13cf54 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -142,7 +142,6 @@ start:
                mov     r7, r1                  @ save architecture ID
                mov     r8, r2                  @ save atags pointer
-#ifndef __ARM_ARCH_2__
                /*
                 * Booting from Angel - need to enter SVC mode and disable
                 * FIQs/IRQs (numeric definitions from angel arm.h source).
@@ -158,10 +157,6 @@ not_angel:
                safe_svcmode_maskall r0
                msr     spsr_cxsf, r9           @ Save the CPU boot mode in
                                                @ SPSR
-#else
-                teqp    pc, #0x0c000003         @ turn off interrupts
-#endif
                /*
                 * Note that some cache flushing and other stuff may
                 * be needed here - is there an Angel SWI call for this?
@@ -183,7 +178,19 @@ not_angel:
                ldr     r4, =zreladdr
 #endif
-                bl      cache_on
+                /*
+                 * Set up a page table only if it won't overwrite ourself.
+                 * That means r4 < pc && r4 - 16k page directory > &_end.
+                 * Given that r4 > &_end is most unfrequent, we add a rough
+                 * additional 1MB of room for a possible appended DTB.
+                 */
+                mov     r0, pc
+                cmp     r0, r4
+                ldrcc   r0, LC0+32
+                addcc   r0, r0, pc
+                cmpcc   r4, r0
+                orrcc   r4, r4, #1              @ remember we skipped cache_on
+                blcs    cache_on
 restart:        adr     r0, LC0
                ldmia   r0, {r1, r2, r3, r6, r10, r11, r12}
@@ -229,7 +236,7 @@ restart:	adr	r0, LC0
 *   r0  = delta
 *   r2  = BSS start
 *   r3  = BSS end
- *   r4  = final kernel address
+ *   r4  = final kernel address (possibly with LSB set)
 *   r5  = appended dtb size (still unknown)
 *   r6  = _edata
 *   r7  = architecture ID
@@ -277,6 +284,7 @@ restart:	adr	r0, LC0
                 */
                cmp     r0, #1
                sub     r0, r4, #TEXT_OFFSET
+                bic     r0, r0, #1
                add     r0, r0, #0x100
                mov     r1, r6
                sub     r2, sp, r6
@@ -323,12 +331,13 @@ dtb_check_done:
 /*
 * Check to see if we will overwrite ourselves.
- *   r4  = final kernel address
+ *   r4  = final kernel address (possibly with LSB set)
 *   r9  = size of decompressed image
 *   r10 = end of this image, including  bss/stack/malloc space if non XIP
 * We basically want:
 *   r4 - 16k page directory >= r10 -> OK
 *   r4 + image length <= address of wont_overwrite -> OK
+ * Note: the possible LSB in r4 is harmless here.
 */
                add     r10, r10, #16384
                cmp     r4, r10
@@ -390,7 +399,8 @@ dtb_check_done:
                add     sp, sp, r6
 #endif
-                bl      cache_clean_flush
+                tst     r4, #1
+                bleq    cache_clean_flush
                adr     r0, BSYM(restart)
                add     r0, r0, r6
@@ -402,7 +412,7 @@ wont_overwrite:
 *   r0  = delta
 *   r2  = BSS start
 *   r3  = BSS end
- *   r4  = kernel execution address
+ *   r4  = kernel execution address (possibly with LSB set)
 *   r5  = appended dtb size (0 if not present)
 *   r7  = architecture ID
 *   r8  = atags pointer
@@ -465,6 +475,15 @@ not_relocated:	mov	r0, #0
                cmp     r2, r3
                blo     1b
+                /*
+                 * Did we skip the cache setup earlier?
+                 * That is indicated by the LSB in r4.
+                 * Do it now if so.
+                 */
+                tst     r4, #1
+                bic     r4, r4, #1
+                blne    cache_on
 /*
 * The C runtime environment should now be setup sufficiently.
 * Set up some pointers, and start decompressing.
@@ -513,6 +532,7 @@ LC0:		.word	LC0			@ r1
                .word   _got_start              @ r11
                .word   _got_end                @ ip
                .word   .L_user_stack_end       @ sp
+                .word   _end - restart + 16384 + 1024*1024
                .size   LC0, . - LC0
 #ifdef CONFIG_ARCH_RPC
diff --git a/arch/arm/boot/compressed/piggy.lz4.S b/arch/arm/boot/compressed/piggy.lz4.S
new file mode 100644
index 000000000000..3d9a575618a3
--- /dev/null
+++ b/arch/arm/boot/compressed/piggy.lz4.S
@@ -0,0 +1,6 @@
+        .section .piggydata,#alloc
+        .globl  input_data
+input_data:
+        .incbin "arch/arm/boot/compressed/piggy.lz4"
+        .globl  input_data_end
+input_data_end:
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f0895c581a89..641b3c9a7028 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -16,11 +16,13 @@ dtb-$(CONFIG_ARCH_AT91) += at91sam9263ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += tny_a9263.dtb
 dtb-$(CONFIG_ARCH_AT91) += usb_a9263.dtb
 # sam9g20
+dtb-$(CONFIG_ARCH_AT91) += at91-foxg20.dtb
 dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek_2mmc.dtb
 dtb-$(CONFIG_ARCH_AT91) += kizbox.dtb
 dtb-$(CONFIG_ARCH_AT91) += tny_a9g20.dtb
 dtb-$(CONFIG_ARCH_AT91) += usb_a9g20.dtb
+dtb-$(CONFIG_ARCH_AT91) += usb_a9g20_lpw.dtb
 # sam9g45
 dtb-$(CONFIG_ARCH_AT91) += at91sam9m10g45ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += pm9g45.dtb
@@ -57,6 +59,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
        exynos5440-sd5v1.dtb \
        exynos5250-smdk5250.dtb \
        exynos5250-snow.dtb \
+        exynos5420-smdk5420.dtb \
        exynos5440-ssdk5440.dtb
 dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
        ecx-2000.dtb
@@ -64,6 +67,8 @@ dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
        integratorcp.dtb
 dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
 dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
+        kirkwood-db-88f6281.dtb \
+        kirkwood-db-88f6282.dtb \
        kirkwood-dns320.dtb \
        kirkwood-dns325.dtb \
        kirkwood-dockstar.dtb \
@@ -84,6 +89,8 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
        kirkwood-ns2max.dtb \
        kirkwood-ns2mini.dtb \
        kirkwood-nsa310.dtb \
+        kirkwood-sheevaplug.dtb \
+        kirkwood-sheevaplug-esata.dtb \
        kirkwood-topkick.dtb \
        kirkwood-ts219-6281.dtb \
        kirkwood-ts219-6282.dtb \
@@ -103,13 +110,15 @@ dtb-$(CONFIG_ARCH_MXC) += \
        imx27-apf27.dtb \
        imx27-apf27dev.dtb \
        imx27-pdk.dtb \
-        imx27-phytec-phycore.dtb \
+        imx27-phytec-phycore-som.dtb \
+        imx27-phytec-phycore-rdk.dtb \
        imx31-bug.dtb \
        imx51-apf51.dtb \
        imx51-apf51dev.dtb \
        imx51-babbage.dtb \
        imx53-ard.dtb \
        imx53-evk.dtb \
+        imx53-m53evk.dtb \
        imx53-mba53.dtb \
        imx53-qsb.dtb \
        imx53-smd.dtb \
@@ -117,10 +126,13 @@ dtb-$(CONFIG_ARCH_MXC) += \
        imx6dl-sabresd.dtb \
        imx6dl-wandboard.dtb \
        imx6q-arm2.dtb \
+        imx6q-phytec-pbab01.dtb \
        imx6q-sabreauto.dtb \
        imx6q-sabrelite.dtb \
        imx6q-sabresd.dtb \
-        imx6q-sbc6x.dtb
+        imx6q-sbc6x.dtb \
+        imx6sl-evk.dtb \
+        vf610-twr.dtb
 dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
        imx23-olinuxino.dtb \
        imx23-stmp378x_devb.dtb \
@@ -130,11 +142,16 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
        imx28-cfa10036.dtb \
        imx28-cfa10037.dtb \
        imx28-cfa10049.dtb \
+        imx28-cfa10055.dtb \
+        imx28-cfa10057.dtb \
        imx28-evk.dtb \
        imx28-m28evk.dtb \
        imx28-sps1.dtb \
        imx28-tx28.dtb
 dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb
+dtb-$(CONFIG_ARCH_NSPIRE) += nspire-cx.dtb \
+        nspire-tp.dtb \
+        nspire-clp.dtb
 dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
        omap3430-sdp.dtb \
        omap3-beagle.dtb \
@@ -149,19 +166,26 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
        omap4-panda-es.dtb \
        omap4-var-som.dtb \
        omap4-sdp.dtb \
-        omap5-evm.dtb \
+        omap4-sdp-es23plus.dtb \
+        omap5-uevm.dtb \
        am335x-evm.dtb \
        am335x-evmsk.dtb \
-        am335x-bone.dtb
+        am335x-bone.dtb \
+        am3517-evm.dtb \
+        am3517_mt_ventoux.dtb \
+        am43x-epos-evm.dtb
 dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
 dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
 dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \
        hrefprev60.dtb \
        hrefv60plus.dtb \
+        ccu8540.dtb \
        ccu9540.dtb
+dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb
 dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
        r8a7740-armadillo800eva.dtb \
        r8a7778-bockw.dtb \
+        r8a7740-armadillo800eva-reference.dtb \
        r8a7779-marzen-reference.dtb \
        r8a7790-lager.dtb \
        sh73a0-kzm9g.dtb \
@@ -177,10 +201,15 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
        spear320-evb.dtb \
        spear320-hmi.dtb
 dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
+dtb-$(CONFIG_ARCH_STI)+= stih415-b2000.dtb \
+        stih416-b2000.dtb \
+        stih415-b2020.dtb \
+        stih416-b2020.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += \
        sun4i-a10-cubieboard.dtb \
        sun4i-a10-mini-xplus.dtb \
        sun4i-a10-hackberry.dtb \
+        sun5i-a10s-olinuxino-micro.dtb \
        sun5i-a13-olinuxino.dtb
 dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
        tegra20-iris-512.dtb \
@@ -199,6 +228,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
        tegra114-pluto.dtb
 dtb-$(CONFIG_ARCH_VERSATILE) += versatile-ab.dtb \
        versatile-pb.dtb
+dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
        vexpress-v2p-ca9.dtb \
        vexpress-v2p-ca15-tc1.dtb \
@@ -207,8 +237,11 @@ dtb-$(CONFIG_ARCH_VIRT) += xenvm-4.2.dtb
 dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \
        wm8505-ref.dtb \
        wm8650-mid.dtb \
+        wm8750-apc8750.dtb \
        wm8850-w70v2.dtb
-dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb
+dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
+        zynq-zc706.dtb \
+        zynq-zed.dtb
 targets += dtbs
 targets += $(dtb-y)
diff --git a/arch/arm/boot/dts/aks-cdu.dts b/arch/arm/boot/dts/aks-cdu.dts
index 29b9f15e7599..54cb5cf8604a 100644
--- a/arch/arm/boot/dts/aks-cdu.dts
+++ b/arch/arm/boot/dts/aks-cdu.dts
@@ -9,7 +9,7 @@
 /dts-v1/;
-/include/ "ge863-pro3.dtsi"
+#include "ge863-pro3.dtsi"
 / {
        chosen {
@@ -46,7 +46,7 @@
                        };
                        usb1: gadget@fffa4000 {
-                                atmel,vbus-gpio = <&pioC 15 0>;
+                                atmel,vbus-gpio = <&pioC 15 GPIO_ACTIVE_HIGH>;
                                status = "okay";
                        };
                };
@@ -90,23 +90,23 @@
                compatible = "gpio-leds";
                red {
-                        gpios = <&pioC 10 0>;
+                        gpios = <&pioC 10 GPIO_ACTIVE_HIGH>;
                        linux,default-trigger = "none";
                };
                green {
-                        gpios = <&pioA 5 1>;
+                        gpios = <&pioA 5 GPIO_ACTIVE_LOW>;
                        linux,default-trigger = "none";
                        default-state = "on";
                };
                yellow {
-                        gpios = <&pioB 20 1>;
+                        gpios = <&pioB 20 GPIO_ACTIVE_LOW>;
                        linux,default-trigger = "none";
                };
                blue {
-                        gpios = <&pioB 21 1>;
+                        gpios = <&pioB 21 GPIO_ACTIVE_LOW>;
                        linux,default-trigger = "none";
                };
        };
diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index 5302f79c05b7..444b4ede0d60 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -7,7 +7,7 @@
 */
 /dts-v1/;
-/include/ "am33xx.dtsi"
+#include "am33xx.dtsi"
 / {
        model = "TI AM335x BeagleBone";
@@ -26,24 +26,104 @@
        am33xx_pinmux: pinmux@44e10800 {
                pinctrl-names = "default";
-                pinctrl-0 = <&user_leds_s0>;
+                pinctrl-0 = <&clkout2_pin>;
                user_leds_s0: user_leds_s0 {
                        pinctrl-single,pins = <
-                                0x54 0x7        /* gpmc_a5.gpio1_21, OUTPUT | MODE7 */
+                                0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a5.gpio1_21 */
-                                0x58 0x17       /* gpmc_a6.gpio1_22, OUTPUT_PULLUP | MODE7 */
+                                0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7)    /* gpmc_a6.gpio1_22 */
-                                0x5c 0x7        /* gpmc_a7.gpio1_23, OUTPUT | MODE7 */
+                                0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a7.gpio1_23 */
-                                0x60 0x17       /* gpmc_a8.gpio1_24, OUTPUT_PULLUP | MODE7 */
+                                0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7)    /* gpmc_a8.gpio1_24 */
+                        >;
+                };
+                i2c0_pins: pinmux_i2c0_pins {
+                        pinctrl-single,pins = <
+                                0x188 (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_sda.i2c0_sda */
+                                0x18c (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_scl.i2c0_scl */
+                        >;
+                };
+                uart0_pins: pinmux_uart0_pins {
+                        pinctrl-single,pins = <
+                                0x170 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart0_rxd.uart0_rxd */
+                                0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
+                        >;
+                };
+                clkout2_pin: pinmux_clkout2_pin {
+                        pinctrl-single,pins = <
+                                0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
+                        >;
+                };
+                cpsw_default: cpsw_default {
+                        pinctrl-single,pins = <
+                                /* Slave 1 */
+                                0x110 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxerr.mii1_rxerr */
+                                0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */
+                                0x118 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxdv.mii1_rxdv */
+                                0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
+                                0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
+                                0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
+                                0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
+                                0x12c (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_txclk.mii1_txclk */
+                                0x130 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxclk.mii1_rxclk */
+                                0x134 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxd3.mii1_rxd3 */
+                                0x138 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxd2.mii1_rxd2 */
+                                0x13c (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxd1.mii1_rxd1 */
+                                0x140 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxd0.mii1_rxd0 */
+                        >;
+                };
+                cpsw_sleep: cpsw_sleep {
+                        pinctrl-single,pins = <
+                                /* Slave 1 reset value */
+                                0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        >;
+                };
+                davinci_mdio_default: davinci_mdio_default {
+                        pinctrl-single,pins = <
+                                /* MDIO */
+                                0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* mdio_data.mdio_data */
+                                0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)                   /* mdio_clk.mdio_clk */
+                        >;
+                };
+                davinci_mdio_sleep: davinci_mdio_sleep {
+                        pinctrl-single,pins = <
+                                /* MDIO reset value */
+                                0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
                        >;
                };
        };
        ocp {
-                uart1: serial@44e09000 {
+                uart0: serial@44e09000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins>;
                        status = "okay";
                };
                i2c0: i2c@44e0b000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_pins>;
                        status = "okay";
                        clock-frequency = <400000>;
@@ -55,31 +135,34 @@
        };
        leds {
+                pinctrl-names = "default";
+                pinctrl-0 = <&user_leds_s0>;
                compatible = "gpio-leds";
                led@2 {
                        label = "beaglebone:green:heartbeat";
-                        gpios = <&gpio1 21 0>;
+                        gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
                        linux,default-trigger = "heartbeat";
                        default-state = "off";
                };
                led@3 {
                        label = "beaglebone:green:mmc0";
-                        gpios = <&gpio1 22 0>;
+                        gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
                        linux,default-trigger = "mmc0";
                        default-state = "off";
                };
                led@4 {
                        label = "beaglebone:green:usr2";
-                        gpios = <&gpio1 23 0>;
+                        gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
                        default-state = "off";
                };
                led@5 {
                        label = "beaglebone:green:usr3";
-                        gpios = <&gpio1 24 0>;
+                        gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
                        default-state = "off";
                };
        };
@@ -131,8 +214,23 @@
 &cpsw_emac0 {
        phy_id = <&davinci_mdio>, <0>;
+        phy-mode = "mii";
 };
 &cpsw_emac1 {
        phy_id = <&davinci_mdio>, <1>;
+        phy-mode = "mii";
+};
+&mac {
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&cpsw_default>;
+        pinctrl-1 = <&cpsw_sleep>;
+};
+&davinci_mdio {
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&davinci_mdio_default>;
+        pinctrl-1 = <&davinci_mdio_sleep>;
 };
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 0423298a26fe..3aee1a43782d 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -7,7 +7,7 @@
 */
 /dts-v1/;
-/include/ "am33xx.dtsi"
+#include "am33xx.dtsi"
 / {
        model = "TI AM335x EVM";
@@ -26,32 +26,143 @@
        am33xx_pinmux: pinmux@44e10800 {
                pinctrl-names = "default";
-                pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0>;
+                pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;
                matrix_keypad_s0: matrix_keypad_s0 {
                        pinctrl-single,pins = <
-                                0x54 0x7        /* gpmc_a5.gpio1_21, OUTPUT | MODE7 */
+                                0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a5.gpio1_21 */
-                                0x58 0x7        /* gpmc_a6.gpio1_22, OUTPUT | MODE7 */
+                                0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a6.gpio1_22 */
-                                0x64 0x27       /* gpmc_a9.gpio1_25, INPUT | MODE7 */
+                                0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a9.gpio1_25 */
-                                0x68 0x27       /* gpmc_a10.gpio1_26, INPUT | MODE7 */
+                                0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a10.gpio1_26 */
-                                0x6c 0x27       /* gpmc_a11.gpio1_27, INPUT | MODE7 */
+                                0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a11.gpio1_27 */
                        >;
                };
                volume_keys_s0: volume_keys_s0 {
                        pinctrl-single,pins = <
-                                0x150 0x27      /* spi0_sclk.gpio0_2, INPUT | MODE7 */
+                                0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* spi0_sclk.gpio0_2 */
-                                0x154 0x27      /* spi0_d0.gpio0_3, INPUT | MODE7 */
+                                0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* spi0_d0.gpio0_3 */
+                        >;
+                };
+                i2c0_pins: pinmux_i2c0_pins {
+                        pinctrl-single,pins = <
+                                0x188 (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_sda.i2c0_sda */
+                                0x18c (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_scl.i2c0_scl */
+                        >;
+                };
+                i2c1_pins: pinmux_i2c1_pins {
+                        pinctrl-single,pins = <
+                                0x158 (PIN_INPUT_PULLUP | MUX_MODE2)    /* spi0_d1.i2c1_sda */
+                                0x15c (PIN_INPUT_PULLUP | MUX_MODE2)    /* spi0_cs0.i2c1_scl */
+                        >;
+                };
+                uart0_pins: pinmux_uart0_pins {
+                        pinctrl-single,pins = <
+                                0x170 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart0_rxd.uart0_rxd */
+                                0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
+                        >;
+                };
+                clkout2_pin: pinmux_clkout2_pin {
+                        pinctrl-single,pins = <
+                                0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
+                        >;
+                };
+                nandflash_pins_s0: nandflash_pins_s0 {
+                        pinctrl-single,pins = <
+                                0x0 (PIN_INPUT_PULLUP | MUX_MODE0)      /* gpmc_ad0.gpmc_ad0 */
+                                0x4 (PIN_INPUT_PULLUP | MUX_MODE0)      /* gpmc_ad1.gpmc_ad1 */
+                                0x8 (PIN_INPUT_PULLUP | MUX_MODE0)      /* gpmc_ad2.gpmc_ad2 */
+                                0xc (PIN_INPUT_PULLUP | MUX_MODE0)      /* gpmc_ad3.gpmc_ad3 */
+                                0x10 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_ad4.gpmc_ad4 */
+                                0x14 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_ad5.gpmc_ad5 */
+                                0x18 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_ad6.gpmc_ad6 */
+                                0x1c (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_ad7.gpmc_ad7 */
+                                0x70 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_wait0.gpmc_wait0 */
+                                0x74 (PIN_INPUT_PULLUP | MUX_MODE7)     /* gpmc_wpn.gpio0_30 */
+                                0x7c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_csn0.gpmc_csn0  */
+                                0x90 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_advn_ale.gpmc_advn_ale */
+                                0x94 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_oen_ren.gpmc_oen_ren */
+                                0x98 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_wen.gpmc_wen */
+                                0x9c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_be0n_cle.gpmc_be0n_cle */
+                        >;
+                };
+                ecap0_pins: backlight_pins {
+                        pinctrl-single,pins = <
+                                0x164 0x0       /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
+                        >;
+                };
+                cpsw_default: cpsw_default {
+                        pinctrl-single,pins = <
+                                /* Slave 1 */
+                                0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
+                                0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxdv.rgmii1_rctl */
+                                0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
+                                0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
+                                0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
+                                0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
+                                0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
+                                0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxclk.rgmii1_rclk */
+                                0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd3.rgmii1_rd3 */
+                                0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd2.rgmii1_rd2 */
+                                0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd1.rgmii1_rd1 */
+                                0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd0.rgmii1_rd0 */
+                        >;
+                };
+                cpsw_sleep: cpsw_sleep {
+                        pinctrl-single,pins = <
+                                /* Slave 1 reset value */
+                                0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        >;
+                };
+                davinci_mdio_default: davinci_mdio_default {
+                        pinctrl-single,pins = <
+                                /* MDIO */
+                                0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* mdio_data.mdio_data */
+                                0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)                   /* mdio_clk.mdio_clk */
+                        >;
+                };
+                davinci_mdio_sleep: davinci_mdio_sleep {
+                        pinctrl-single,pins = <
+                                /* MDIO reset value */
+                                0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
                        >;
                };
        };
        ocp {
-                uart1: serial@44e09000 {
+                uart0: serial@44e09000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins>;
                        status = "okay";
                };
                i2c0: i2c@44e0b000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_pins>;
                        status = "okay";
                        clock-frequency = <400000>;
@@ -61,6 +172,9 @@
                };
                i2c1: i2c@4802a000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c1_pins>;
                        status = "okay";
                        clock-frequency = <100000>;
@@ -102,6 +216,101 @@
                                reg = <0x48>;
                        };
                };
+                elm: elm@48080000 {
+                        status = "okay";
+                };
+                epwmss0: epwmss@48300000 {
+                        status = "okay";
+                        ecap0: ecap@48300100 {
+                                status = "okay";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&ecap0_pins>;
+                        };
+                };
+                gpmc: gpmc@50000000 {
+                        status = "okay";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&nandflash_pins_s0>;
+                        ranges = <0 0 0x08000000 0x10000000>;   /* CS0: NAND */
+                        nand@0,0 {
+                                reg = <0 0 0>; /* CS0, offset 0 */
+                                nand-bus-width = <8>;
+                                ti,nand-ecc-opt = "bch8";
+                                gpmc,device-nand = "true";
+                                gpmc,device-width = <1>;
+                                gpmc,sync-clk-ps = <0>;
+                                gpmc,cs-on-ns = <0>;
+                                gpmc,cs-rd-off-ns = <44>;
+                                gpmc,cs-wr-off-ns = <44>;
+                                gpmc,adv-on-ns = <6>;
+                                gpmc,adv-rd-off-ns = <34>;
+                                gpmc,adv-wr-off-ns = <44>;
+                                gpmc,we-on-ns = <0>;
+                                gpmc,we-off-ns = <40>;
+                                gpmc,oe-on-ns = <0>;
+                                gpmc,oe-off-ns = <54>;
+                                gpmc,access-ns = <64>;
+                                gpmc,rd-cycle-ns = <82>;
+                                gpmc,wr-cycle-ns = <82>;
+                                gpmc,wait-on-read = "true";
+                                gpmc,wait-on-write = "true";
+                                gpmc,bus-turnaround-ns = <0>;
+                                gpmc,cycle2cycle-delay-ns = <0>;
+                                gpmc,clk-activation-ns = <0>;
+                                gpmc,wait-monitoring-ns = <0>;
+                                gpmc,wr-access-ns = <40>;
+                                gpmc,wr-data-mux-bus-ns = <0>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                elm_id = <&elm>;
+                                /* MTD partition table */
+                                partition@0 {
+                                        label = "SPL1";
+                                        reg = <0x00000000 0x000020000>;
+                                };
+                                partition@1 {
+                                        label = "SPL2";
+                                        reg = <0x00020000 0x00020000>;
+                                };
+                                partition@2 {
+                                        label = "SPL3";
+                                        reg = <0x00040000 0x00020000>;
+                                };
+                                partition@3 {
+                                        label = "SPL4";
+                                        reg = <0x00060000 0x00020000>;
+                                };
+                                partition@4 {
+                                        label = "U-boot";
+                                        reg = <0x00080000 0x001e0000>;
+                                };
+                                partition@5 {
+                                        label = "environment";
+                                        reg = <0x00260000 0x00020000>;
+                                };
+                                partition@6 {
+                                        label = "Kernel";
+                                        reg = <0x00280000 0x00500000>;
+                                };
+                                partition@7 {
+                                        label = "File-System";
+                                        reg = <0x00780000 0x0F880000>;
+                                };
+                        };
+                };
        };
        vbat: fixedregulator@0 {
@@ -123,12 +332,12 @@
                debounce-delay-ms = <5>;
                col-scan-delay-us = <2>;
-                row-gpios = <&gpio1 25 0        /* Bank1, pin25 */
+                row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH         /* Bank1, pin25 */
-                             &gpio1 26 0        /* Bank1, pin26 */
+                             &gpio1 26 GPIO_ACTIVE_HIGH         /* Bank1, pin26 */
-                             &gpio1 27 0>;      /* Bank1, pin27 */
+                             &gpio1 27 GPIO_ACTIVE_HIGH>;       /* Bank1, pin27 */
-                col-gpios = <&gpio1 21 0        /* Bank1, pin21 */
+                col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH         /* Bank1, pin21 */
-                             &gpio1 22 0>;      /* Bank1, pin22 */
+                             &gpio1 22 GPIO_ACTIVE_HIGH>;       /* Bank1, pin22 */
                linux,keymap = <0x0000008b      /* MENU */
                                0x0100009e      /* BACK */
@@ -147,20 +356,27 @@
                switch@9 {
                        label = "volume-up";
                        linux,code = <115>;
-                        gpios = <&gpio0 2 1>;
+                        gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
                        gpio-key,wakeup;
                };
                switch@10 {
                        label = "volume-down";
                        linux,code = <114>;
-                        gpios = <&gpio0 3 1>;
+                        gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
                        gpio-key,wakeup;
                };
        };
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&ecap0 0 50000 0>;
+                brightness-levels = <0 51 53 56 62 75 101 152 255>;
+                default-brightness-level = <8>;
+        };
 };
-/include/ "tps65910.dtsi"
+#include "tps65910.dtsi"
 &tps {
        vcc1-supply = <&vbat>;
@@ -237,10 +453,38 @@
        };
 };
+&mac {
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&cpsw_default>;
+        pinctrl-1 = <&cpsw_sleep>;
+};
+&davinci_mdio {
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&davinci_mdio_default>;
+        pinctrl-1 = <&davinci_mdio_sleep>;
+};
 &cpsw_emac0 {
        phy_id = <&davinci_mdio>, <0>;
+        phy-mode = "rgmii-txid";
 };
 &cpsw_emac1 {
        phy_id = <&davinci_mdio>, <1>;
+        phy-mode = "rgmii-txid";
+};
+&tscadc {
+        status = "okay";
+        tsc {
+                ti,wires = <4>;
+                ti,x-plate-resistance = <200>;
+                ti,coordiante-readouts = <5>;
+                ti,wire-config = <0x00 0x11 0x22 0x33>;
+        };
+        adc {
+                ti,adc-channels = <4 5 6 7>;
+        };
 };
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index f67c360844f4..0c8ad173d2b0 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -13,7 +13,7 @@
 /dts-v1/;
-/include/ "am33xx.dtsi"
+#include "am33xx.dtsi"
 / {
        model = "TI AM335x EVM-SK";
@@ -32,33 +32,145 @@
        am33xx_pinmux: pinmux@44e10800 {
                pinctrl-names = "default";
-                pinctrl-0 = <&user_leds_s0 &gpio_keys_s0>;
+                pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>;
                user_leds_s0: user_leds_s0 {
                        pinctrl-single,pins = <
-                                0x10 0x7        /* gpmc_ad4.gpio1_4, OUTPUT | MODE7 */
+                                0x10 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_ad4.gpio1_4 */
-                                0x14 0x7        /* gpmc_ad5.gpio1_5, OUTPUT | MODE7 */
+                                0x14 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_ad5.gpio1_5 */
-                                0x18 0x7        /* gpmc_ad6.gpio1_6, OUTPUT | MODE7 */
+                                0x18 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_ad6.gpio1_6 */
-                                0x1c 0x7        /* gpmc_ad7.gpio1_7, OUTPUT | MODE7 */
+                                0x1c (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_ad7.gpio1_7 */
                        >;
                };
                gpio_keys_s0: gpio_keys_s0 {
                        pinctrl-single,pins = <
-                                0x94 0x27       /* gpmc_oen_ren.gpio2_3, INPUT | MODE7 */
+                                0x94 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_oen_ren.gpio2_3 */
-                                0x90 0x27       /* gpmc_advn_ale.gpio2_2, INPUT | MODE7 */
+                                0x90 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_advn_ale.gpio2_2 */
-                                0x70 0x27       /* gpmc_wait0.gpio0_30, INPUT | MODE7 */
+                                0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_wait0.gpio0_30 */
-                                0x9c 0x27       /* gpmc_ben0_cle.gpio2_5, INPUT | MODE7 */
+                                0x9c (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_ben0_cle.gpio2_5 */
+                        >;
+                };
+                i2c0_pins: pinmux_i2c0_pins {
+                        pinctrl-single,pins = <
+                                0x188 (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_sda.i2c0_sda */
+                                0x18c (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_scl.i2c0_scl */
+                        >;
+                };
+                uart0_pins: pinmux_uart0_pins {
+                        pinctrl-single,pins = <
+                                0x170 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart0_rxd.uart0_rxd */
+                                0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)         /* uart0_txd.uart0_txd */
+                        >;
+                };
+                clkout2_pin: pinmux_clkout2_pin {
+                        pinctrl-single,pins = <
+                                0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)         /* xdma_event_intr1.clkout2 */
+                        >;
+                };
+                ecap2_pins: backlight_pins {
+                        pinctrl-single,pins = <
+                                0x19c 0x4       /* mcasp0_ahclkr.ecap2_in_pwm2_out MODE4 */
+                        >;
+                };
+                cpsw_default: cpsw_default {
+                        pinctrl-single,pins = <
+                                /* Slave 1 */
+                                0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
+                                0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxdv.rgmii1_rctl */
+                                0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
+                                0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
+                                0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
+                                0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
+                                0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
+                                0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxclk.rgmii1_rclk */
+                                0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd3.rgmii1_rd3 */
+                                0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd2.rgmii1_rd2 */
+                                0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd1.rgmii1_rd1 */
+                                0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd0.rgmii1_rd0 */
+                                /* Slave 2 */
+                                0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)  /* gpmc_a0.rgmii2_tctl */
+                                0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2)   /* gpmc_a1.rgmii2_rctl */
+                                0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)  /* gpmc_a2.rgmii2_td3 */
+                                0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2)  /* gpmc_a3.rgmii2_td2 */
+                                0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)  /* gpmc_a4.rgmii2_td1 */
+                                0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)  /* gpmc_a5.rgmii2_td0 */
+                                0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)  /* gpmc_a6.rgmii2_tclk */
+                                0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2)   /* gpmc_a7.rgmii2_rclk */
+                                0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2)   /* gpmc_a8.rgmii2_rd3 */
+                                0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2)   /* gpmc_a9.rgmii2_rd2 */
+                                0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2)   /* gpmc_a10.rgmii2_rd1 */
+                                0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2)   /* gpmc_a11.rgmii2_rd0 */
+                        >;
+                };
+                cpsw_sleep: cpsw_sleep {
+                        pinctrl-single,pins = <
+                                /* Slave 1 reset value */
+                                0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                /* Slave 2 reset value*/
+                                0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        >;
+                };
+                davinci_mdio_default: davinci_mdio_default {
+                        pinctrl-single,pins = <
+                                /* MDIO */
+                                0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* mdio_data.mdio_data */
+                                0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)                   /* mdio_clk.mdio_clk */
+                        >;
+                };
+                davinci_mdio_sleep: davinci_mdio_sleep {
+                        pinctrl-single,pins = <
+                                /* MDIO reset value */
+                                0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
                        >;
                };
        };
        ocp {
-                uart1: serial@44e09000 {
+                uart0: serial@44e09000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins>;
                        status = "okay";
                };
                i2c0: i2c@44e0b000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_pins>;
                        status = "okay";
                        clock-frequency = <400000>;
@@ -94,6 +206,16 @@
                                st,max-limit-z = <750>;
                        };
                };
+                epwmss2: epwmss@48304000 {
+                        status = "okay";
+                        ecap2: ecap@48304100 {
+                                status = "okay";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&ecap2_pins>;
+                        };
+                };
        };
        vbat: fixedregulator@0 {
@@ -111,30 +233,33 @@
        };
        leds {
+                pinctrl-names = "default";
+                pinctrl-0 = <&user_leds_s0>;
                compatible = "gpio-leds";
                led@1 {
                        label = "evmsk:green:usr0";
-                        gpios = <&gpio1 4 0>;
+                        gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
                        default-state = "off";
                };
                led@2 {
                        label = "evmsk:green:usr1";
-                        gpios = <&gpio1 5 0>;
+                        gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
                        default-state = "off";
                };
                led@3 {
                        label = "evmsk:green:mmc0";
-                        gpios = <&gpio1 6 0>;
+                        gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
                        linux,default-trigger = "mmc0";
                        default-state = "off";
                };
                led@4 {
                        label = "evmsk:green:heartbeat";
-                        gpios = <&gpio1 7 0>;
+                        gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
                        linux,default-trigger = "heartbeat";
                        default-state = "off";
                };
@@ -148,31 +273,38 @@
                switch@1 {
                        label = "button0";
                        linux,code = <0x100>;
-                        gpios = <&gpio2 3 0>;
+                        gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
                };
                switch@2 {
                        label = "button1";
                        linux,code = <0x101>;
-                        gpios = <&gpio2 2 0>;
+                        gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
                };
                switch@3 {
                        label = "button2";
                        linux,code = <0x102>;
-                        gpios = <&gpio0 30 0>;
+                        gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>;
                        gpio-key,wakeup;
                };
                switch@4 {
                        label = "button3";
                        linux,code = <0x103>;
-                        gpios = <&gpio2 5 0>;
+                        gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
                };
        };
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&ecap2 0 50000 1>;
+                brightness-levels = <0 58 61 66 75 90 125 170 255>;
+                default-brightness-level = <8>;
+        };
 };
-/include/ "tps65910.dtsi"
+#include "tps65910.dtsi"
 &tps {
        vcc1-supply = <&vbat>;
@@ -248,3 +380,25 @@
                };
        };
 };
+&mac {
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&cpsw_default>;
+        pinctrl-1 = <&cpsw_sleep>;
+};
+&davinci_mdio {
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&davinci_mdio_default>;
+        pinctrl-1 = <&davinci_mdio_sleep>;
+};
+&cpsw_emac0 {
+        phy_id = <&davinci_mdio>, <0>;
+        phy-mode = "rgmii-txid";
+};
+&cpsw_emac1 {
+        phy_id = <&davinci_mdio>, <1>;
+        phy-mode = "rgmii-txid";
+};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 8e1248f01fab..38b446ba1ce1 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -8,26 +8,33 @@
 * kind, whether express or implied.
 */
-/include/ "skeleton.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/am33xx.h>
+#include "skeleton.dtsi"
 / {
        compatible = "ti,am33xx";
        interrupt-parent = <&intc>;
        aliases {
-                serial0 = &uart1;
+                serial0 = &uart0;
-                serial1 = &uart2;
+                serial1 = &uart1;
-                serial2 = &uart3;
+                serial2 = &uart2;
-                serial3 = &uart4;
+                serial3 = &uart3;
-                serial4 = &uart5;
+                serial4 = &uart4;
-                serial5 = &uart6;
+                serial5 = &uart5;
                d_can0 = &dcan0;
                d_can1 = &dcan1;
        };
        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
                cpu@0 {
                        compatible = "arm,cortex-a8";
+                        device_type = "cpu";
+                        reg = <0>;
                        /*
                         * To consider voltage drop between PMIC and SoC,
@@ -133,7 +140,7 @@
                        interrupts = <62>;
                };
-                uart1: serial@44e09000 {
+                uart0: serial@44e09000 {
                        compatible = "ti,omap3-uart";
                        ti,hwmods = "uart1";
                        clock-frequency = <48000000>;
@@ -142,7 +149,7 @@
                        status = "disabled";
                };
-                uart2: serial@48022000 {
+                uart1: serial@48022000 {
                        compatible = "ti,omap3-uart";
                        ti,hwmods = "uart2";
                        clock-frequency = <48000000>;
@@ -151,7 +158,7 @@
                        status = "disabled";
                };
-                uart3: serial@48024000 {
+                uart2: serial@48024000 {
                        compatible = "ti,omap3-uart";
                        ti,hwmods = "uart3";
                        clock-frequency = <48000000>;
@@ -160,7 +167,7 @@
                        status = "disabled";
                };
-                uart4: serial@481a6000 {
+                uart3: serial@481a6000 {
                        compatible = "ti,omap3-uart";
                        ti,hwmods = "uart4";
                        clock-frequency = <48000000>;
@@ -169,7 +176,7 @@
                        status = "disabled";
                };
-                uart5: serial@481a8000 {
+                uart4: serial@481a8000 {
                        compatible = "ti,omap3-uart";
                        ti,hwmods = "uart5";
                        clock-frequency = <48000000>;
@@ -178,7 +185,7 @@
                        status = "disabled";
                };
-                uart6: serial@481aa000 {
+                uart5: serial@481aa000 {
                        compatible = "ti,omap3-uart";
                        ti,hwmods = "uart6";
                        clock-frequency = <48000000>;
@@ -343,6 +350,90 @@
                        ti,hwmods = "usb_otg_hs";
                };
+                epwmss0: epwmss@48300000 {
+                        compatible = "ti,am33xx-pwmss";
+                        reg = <0x48300000 0x10>;
+                        ti,hwmods = "epwmss0";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        status = "disabled";
+                        ranges = <0x48300100 0x48300100 0x80   /* ECAP */
+                                  0x48300180 0x48300180 0x80   /* EQEP */
+                                  0x48300200 0x48300200 0x80>; /* EHRPWM */
+                        ecap0: ecap@48300100 {
+                                compatible = "ti,am33xx-ecap";
+                                #pwm-cells = <3>;
+                                reg = <0x48300100 0x80>;
+                                ti,hwmods = "ecap0";
+                                status = "disabled";
+                        };
+                        ehrpwm0: ehrpwm@48300200 {
+                                compatible = "ti,am33xx-ehrpwm";
+                                #pwm-cells = <3>;
+                                reg = <0x48300200 0x80>;
+                                ti,hwmods = "ehrpwm0";
+                                status = "disabled";
+                        };
+                };
+                epwmss1: epwmss@48302000 {
+                        compatible = "ti,am33xx-pwmss";
+                        reg = <0x48302000 0x10>;
+                        ti,hwmods = "epwmss1";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        status = "disabled";
+                        ranges = <0x48302100 0x48302100 0x80   /* ECAP */
+                                  0x48302180 0x48302180 0x80   /* EQEP */
+                                  0x48302200 0x48302200 0x80>; /* EHRPWM */
+                        ecap1: ecap@48302100 {
+                                compatible = "ti,am33xx-ecap";
+                                #pwm-cells = <3>;
+                                reg = <0x48302100 0x80>;
+                                ti,hwmods = "ecap1";
+                                status = "disabled";
+                        };
+                        ehrpwm1: ehrpwm@48302200 {
+                                compatible = "ti,am33xx-ehrpwm";
+                                #pwm-cells = <3>;
+                                reg = <0x48302200 0x80>;
+                                ti,hwmods = "ehrpwm1";
+                                status = "disabled";
+                        };
+                };
+                epwmss2: epwmss@48304000 {
+                        compatible = "ti,am33xx-pwmss";
+                        reg = <0x48304000 0x10>;
+                        ti,hwmods = "epwmss2";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        status = "disabled";
+                        ranges = <0x48304100 0x48304100 0x80   /* ECAP */
+                                  0x48304180 0x48304180 0x80   /* EQEP */
+                                  0x48304200 0x48304200 0x80>; /* EHRPWM */
+                        ecap2: ecap@48304100 {
+                                compatible = "ti,am33xx-ecap";
+                                #pwm-cells = <3>;
+                                reg = <0x48304100 0x80>;
+                                ti,hwmods = "ecap2";
+                                status = "disabled";
+                        };
+                        ehrpwm2: ehrpwm@48304200 {
+                                compatible = "ti,am33xx-ehrpwm";
+                                #pwm-cells = <3>;
+                                reg = <0x48304200 0x80>;
+                                ti,hwmods = "ehrpwm2";
+                                status = "disabled";
+                        };
+                };
                mac: ethernet@4a100000 {
                        compatible = "ti,cpsw";
                        ti,hwmods = "cpgmac0";
@@ -394,7 +485,6 @@
                        compatible = "ti,am3352-ocmcram";
                        reg = <0x40300000 0x10000>;
                        ti,hwmods = "ocmcram";
-                        ti,no_idle_on_suspend;
                };
                wkup_m3: wkup_m3@44d00000 {
@@ -404,6 +494,31 @@
                        ti,hwmods = "wkup_m3";
                };
+                elm: elm@48080000 {
+                        compatible = "ti,am3352-elm";
+                        reg = <0x48080000 0x2000>;
+                        interrupts = <4>;
+                        ti,hwmods = "elm";
+                        status = "disabled";
+                };
+                tscadc: tscadc@44e0d000 {
+                        compatible = "ti,am3359-tscadc";
+                        reg = <0x44e0d000 0x1000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <16>;
+                        ti,hwmods = "adc_tsc";
+                        status = "disabled";
+                        tsc {
+                                compatible = "ti,am3359-tsc";
+                        };
+                        am335x_adc: adc {
+                                #io-channel-cells = <1>;
+                                compatible = "ti,am3359-adc";
+                        };
+                };
                gpmc: gpmc@50000000 {
                        compatible = "ti,am3352-gpmc";
                        ti,hwmods = "gpmc";
diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts
index e9b5bdae4908..e99dfaf70052 100644
--- a/arch/arm/boot/dts/am3517-evm.dts
+++ b/arch/arm/boot/dts/am3517-evm.dts
@@ -7,7 +7,7 @@
 */
 /dts-v1/;
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 / {
        model = "TI AM3517 EVM (AM3517/05)";
diff --git a/arch/arm/boot/dts/am3517_mt_ventoux.dts b/arch/arm/boot/dts/am3517_mt_ventoux.dts
index 556868388a23..fdf5ce63c8e6 100644
--- a/arch/arm/boot/dts/am3517_mt_ventoux.dts
+++ b/arch/arm/boot/dts/am3517_mt_ventoux.dts
@@ -7,7 +7,7 @@
 */
 /dts-v1/;
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 / {
        model = "TeeJet Mt.Ventoux";
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
new file mode 100644
index 000000000000..ddc1df77ac52
--- /dev/null
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -0,0 +1,68 @@
+/*
+ * Device Tree Source for AM4372 SoC
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "skeleton.dtsi"
+/ {
+        compatible = "ti,am4372", "ti,am43";
+        interrupt-parent = <&gic>;
+        aliases {
+                serial0 = &uart0;
+        };
+        cpus {
+                cpu@0 {
+                        compatible = "arm,cortex-a9";
+                };
+        };
+        gic: interrupt-controller@48241000 {
+                compatible = "arm,cortex-a9-gic";
+                interrupt-controller;
+                #interrupt-cells = <3>;
+                reg = <0x48241000 0x1000>,
+                      <0x48240100 0x0100>;
+        };
+        ocp {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                uart0: serial@44e09000 {
+                        compatible = "ti,am4372-uart","ti,omap2-uart";
+                        reg = <0x44e09000 0x2000>;
+                        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+                };
+                timer1: timer@44e31000 {
+                        compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
+                        reg = <0x44e31000 0x400>;
+                        interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+                        ti,timer-alwon;
+                };
+                timer2: timer@48040000  {
+                        compatible = "ti,am4372-timer","ti,am335x-timer";
+                        reg = <0x48040000  0x400>;
+                        interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+                };
+                counter32k: counter@44e86000 {
+                        compatible = "ti,am4372-counter32k","ti,omap-counter32k";
+                        reg = <0x44e86000 0x40>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
new file mode 100644
index 000000000000..74174d48f476
--- /dev/null
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/* AM43x EPOS EVM */
+/dts-v1/;
+#include "am4372.dtsi"
+/ {
+        model = "TI AM43x EPOS EVM";
+        compatible = "ti,am43x-epos-evm","ti,am4372","ti,am43";
+};
diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts
index 5160210f74da..3a1de9eb5111 100644
--- a/arch/arm/boot/dts/animeo_ip.dts
+++ b/arch/arm/boot/dts/animeo_ip.dts
@@ -7,7 +7,7 @@
 */
 /dts-v1/;
-/include/ "at91sam9260.dtsi"
+#include "at91sam9260.dtsi"
 / {
        model = "Somfy Animeo IP";
@@ -123,7 +123,7 @@
                usb0: ohci@00500000 {
                        num-ports = <2>;
-                        atmel,vbus-gpio = <&pioB 15 1>;
+                        atmel,vbus-gpio = <&pioB 15 GPIO_ACTIVE_LOW>;
                        status = "okay";
                };
        };
@@ -133,23 +133,23 @@
                power_green {
                        label = "power_green";
-                        gpios = <&pioC 17 0>;
+                        gpios = <&pioC 17 GPIO_ACTIVE_HIGH>;
                        linux,default-trigger = "heartbeat";
                };
                power_red {
                        label = "power_red";
-                        gpios = <&pioA 2 0>;
+                        gpios = <&pioA 2 GPIO_ACTIVE_HIGH>;
                };
                tx_green {
                        label = "tx_green";
-                        gpios = <&pioC 19 0>;
+                        gpios = <&pioC 19 GPIO_ACTIVE_HIGH>;
                };
                tx_red {
                        label = "tx_red";
-                        gpios = <&pioC 18 0>;
+                        gpios = <&pioC 18 GPIO_ACTIVE_HIGH>;
                };
        };
@@ -160,21 +160,21 @@
                keyswitch_in {
                        label = "keyswitch_in";
-                        gpios = <&pioB 1 0>;
+                        gpios = <&pioB 1 GPIO_ACTIVE_HIGH>;
                        linux,code = <28>;
                        gpio-key,wakeup;
                };
                error_in {
                        label = "error_in";
-                        gpios = <&pioB 2 0>;
+                        gpios = <&pioB 2 GPIO_ACTIVE_HIGH>;
                        linux,code = <29>;
                        gpio-key,wakeup;
                };
                btn {
                        label = "btn";
-                        gpios = <&pioC 23 0>;
+                        gpios = <&pioC 23 GPIO_ACTIVE_HIGH>;
                        linux,code = <31>;
                        gpio-key,wakeup;
                };
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index 2353b1f13704..beee1699d49e 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -74,6 +74,7 @@
                                 */
                                status = "disabled";
                                /* No CD or WP GPIOs */
+                                broken-cd;
                        };
                        usb@50000 {
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index 14e36e19d515..45b107763e3b 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -99,6 +99,7 @@
                                 * No CD or WP GPIOs: SDIO interface used for
                                 * Wifi/Bluetooth chip
                                 */
+                                 broken-cd;
                        };
                        usb@50000 {
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index 130f8390a7e4..a3a2fedb8726 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -64,6 +64,7 @@
                                pinctrl-names = "default";
                                status = "okay";
                                /* No CD or WP GPIOs */
+                                broken-cd;
                        };
                        usb@50000 {
@@ -84,6 +85,22 @@
                                        gpios = <&gpio0 6 1>;
                                };
                        };
+                        pcie-controller {
+                                status = "okay";
+                                /* Internal mini-PCIe connector */
+                                pcie@1,0 {
+                                        /* Port 0, Lane 0 */
+                                        status = "okay";
+                                };
+                                /* Internal mini-PCIe connector */
+                                pcie@2,0 {
+                                        /* Port 1, Lane 0 */
+                                        status = "okay";
+                                };
+                        };
                };
        };
 };
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 550eb772c30e..90b117624abb 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -22,9 +22,18 @@
        model = "Marvell Armada 370 and XP SoC";
        compatible = "marvell,armada-370-xp";
+        aliases {
+                eth0 = &eth0;
+                eth1 = &eth1;
+        };
        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
                cpu@0 {
                        compatible = "marvell,sheeva-v7";
+                        device_type = "cpu";
+                        reg = <0>;
                };
        };
@@ -80,7 +89,7 @@
                        sata@a0000 {
                                compatible = "marvell,orion-sata";
-                                reg = <0xa0000 0x2400>;
+                                reg = <0xa0000 0x5000>;
                                interrupts = <55>;
                                clocks = <&gateclk 15>, <&gateclk 30>;
                                clock-names = "0", "1";
@@ -94,17 +103,17 @@
                                reg = <0x72004 0x4>;
                        };
-                        ethernet@70000 {
+                        eth0: ethernet@70000 {
                                compatible = "marvell,armada-370-neta";
-                                reg = <0x70000 0x2500>;
+                                reg = <0x70000 0x4000>;
                                interrupts = <8>;
                                clocks = <&gateclk 4>;
                                status = "disabled";
                        };
-                        ethernet@74000 {
+                        eth1: ethernet@74000 {
                                compatible = "marvell,armada-370-neta";
-                                reg = <0x74000 0x2500>;
+                                reg = <0x74000 0x4000>;
                                interrupts = <10>;
                                clocks = <&gateclk 3>;
                                status = "disabled";
@@ -143,6 +152,10 @@
                                reg = <0xd4000 0x200>;
                                interrupts = <54>;
                                clocks = <&gateclk 17>;
+                                bus-width = <4>;
+                                cap-sdio-irq;
+                                cap-sd-highspeed;
+                                cap-mmc-highspeed;
                                status = "disabled";
                        };
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index aee2b1866ce2..fa3dfc6b4c6a 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -180,10 +180,6 @@
                                bus-range = <0x00 0xff>;
-                                reg = <0x40000 0x2000>, <0x80000 0x2000>;
-                                reg-names = "pcie0.0", "pcie1.0";
                                ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000   /* Port 0.0 registers */
                                        0x82000000 0 0x80000 0x80000 0 0x00002000   /* Port 1.0 registers */
                                        0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index d6cc8bf8272e..e28e68ff864d 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -30,6 +30,10 @@
        };
        soc {
+                ranges = <0          0 0xd0000000 0x100000      /* Internal registers 1MiB */
+                          0xe0000000 0 0xe0000000 0x8100000     /* PCIe */
+                          0xf0000000 0 0xf0000000 0x1000000>;   /* Device Bus, NOR 16MiB   */
                internal-regs {
                        serial@12000 {
                                clock-frequency = <250000000>;
@@ -97,6 +101,7 @@
                                pinctrl-names = "default";
                                status = "okay";
                                /* No CD or WP GPIOs */
+                                broken-cd;
                        };
                        usb@50000 {
@@ -155,6 +160,35 @@
                                        status = "okay";
                                };
                        };
+                        devbus-bootcs@10400 {
+                                status = "okay";
+                                ranges = <0 0xf0000000 0x1000000>;
+                                /* Device Bus parameters are required */
+                                /* Read parameters */
+                                devbus,bus-width    = <8>;
+                                devbus,turn-off-ps  = <60000>;
+                                devbus,badr-skew-ps = <0>;
+                                devbus,acc-first-ps = <124000>;
+                                devbus,acc-next-ps  = <248000>;
+                                devbus,rd-setup-ps  = <0>;
+                                devbus,rd-hold-ps   = <0>;
+                                /* Write parameters */
+                                devbus,sync-enable = <0>;
+                                devbus,wr-high-ps  = <60000>;
+                                devbus,wr-low-ps   = <60000>;
+                                devbus,ale-wr-ps   = <60000>;
+                                /* NOR 16 MiB */
+                                nor@0 {
+                                        compatible = "cfi-flash";
+                                        reg = <0 0x1000000>;
+                                        bank-width = <2>;
+                                };
+                        };
                };
        };
 };
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 76db557adbe7..c87b2de29c30 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -105,6 +105,16 @@
                                phy-mode = "rgmii-id";
                        };
+                        /* Front-side USB slot */
+                        usb@50000 {
+                                status = "okay";
+                        };
+                        /* Back-side USB slot */
+                        usb@51000 {
+                                status = "okay";
+                        };
                        spi0: spi@10600 {
                                status = "okay";
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index f4029f015aff..2d9335da210c 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -92,7 +92,7 @@
                        ethernet@34000 {
                                compatible = "marvell,armada-370-neta";
-                                reg = <0x34000 0x2500>;
+                                reg = <0x34000 0x4000>;
                                interrupts = <14>;
                                clocks = <&gateclk 1>;
                                status = "disabled";
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index 6ab56bd35de9..c7b1f4d5c1c7 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -23,6 +23,7 @@
                gpio0 = &gpio0;
                gpio1 = &gpio1;
                gpio2 = &gpio2;
+                eth3 = &eth3;
        };
@@ -105,9 +106,9 @@
                                interrupts = <91>;
                        };
-                        ethernet@34000 {
+                        eth3: ethernet@34000 {
                                compatible = "marvell,armada-370-neta";
-                                reg = <0x34000 0x2500>;
+                                reg = <0x34000 0x4000>;
                                interrupts = <14>;
                                clocks = <&gateclk 1>;
                                status = "disabled";
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index fdea75c73411..8f510458ea86 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -138,13 +138,22 @@
                                nr-ports = <2>;
                                status = "okay";
                        };
+                        /* Front side USB 0 */
                        usb@50000 {
                                status = "okay";
                        };
+                        /* Front side USB 1 */
                        usb@51000 {
                                status = "okay";
                        };
+                        /* USB interface in the mini-PCIe connector */
+                        usb@52000 {
+                                status = "okay";
+                        };
                        devbus-bootcs@10400 {
                                status = "okay";
                                ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 5b902f9a3af2..416eb9481844 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -22,6 +22,10 @@
        model = "Marvell Armada XP family SoC";
        compatible = "marvell,armadaxp", "marvell,armada-370-xp";
+        aliases {
+                eth2 = &eth2;
+        };
        soc {
                internal-regs {
                        L2: l2-cache {
@@ -86,9 +90,9 @@
                                reg = <0x18200 0x500>;
                        };
-                        ethernet@30000 {
+                        eth2: ethernet@30000 {
                                compatible = "marvell,armada-370-neta";
-                                reg = <0x30000 0x2500>;
+                                reg = <0x30000 0x4000>;
                                interrupts = <12>;
                                clocks = <&gateclk 2>;
                                status = "disabled";
diff --git a/arch/arm/boot/dts/at91-ariag25.dts b/arch/arm/boot/dts/at91-ariag25.dts
index c7aebba4e8e7..cce45f5177f9 100644
--- a/arch/arm/boot/dts/at91-ariag25.dts
+++ b/arch/arm/boot/dts/at91-ariag25.dts
@@ -7,7 +7,7 @@
 * Licensed under GPLv2 or later.
 */
 /dts-v1/;
-/include/ "at91sam9g25.dtsi"
+#include "at91sam9g25.dtsi"
 / {
        model = "Acme Systems Aria G25";
@@ -21,6 +21,7 @@
                serial3 = &usart2;
                serial4 = &usart3;
                serial5 = &uart0;
+                serial6 = &uart1;
        };
        chosen {
@@ -112,13 +113,17 @@
                                status = "okay";
                        };
+                        /*
+                         * UART0/1 pins are marked as GPIO on
+                         * Aria documentation.
+                         * Change to "okay" if you need additional serial ports
+                         */
                        uart0: serial@f8040000 {
-                                compatible = "atmel,at91sam9260-usart";
+                                status = "disabled";
-                                reg = <0xf8040000 0x200>;
+                        };
-                                interrupts = <15 4 5>;
-                                pinctrl-names = "default";
+                        uart1: serial@f8044000 {
-                                pinctrl-0 = <&pinctrl_uart0>;
+                                status = "disabled";
-                                status = "okay";
                        };
                        adc0: adc@f804c000 {
@@ -138,6 +143,10 @@
                                        };
                                };
                        };
+                        rtc@fffffeb0 {
+                                status = "okay";
+                        };
                };
                usb0: ohci@00600000 {
@@ -156,7 +165,7 @@
                /* little green LED in middle of Aria G25 module */
                aria_led {
                        label = "aria_led";
-                        gpios = <&pioB 8 0>; /* PB8 */
+                        gpios = <&pioB 8 GPIO_ACTIVE_HIGH>; /* PB8 */
                        linux,default-trigger = "heartbeat";
                };
@@ -164,7 +173,7 @@
        onewire@0 {
                compatible = "w1-gpio";
-                gpios = <&pioA 21 1>;
+                gpios = <&pioA 21 GPIO_ACTIVE_LOW>;
                pinctrl-names = "default";
                pinctrl-0 = <&pinctrl_w1_0>;
        };
diff --git a/arch/arm/boot/dts/at91-foxg20.dts b/arch/arm/boot/dts/at91-foxg20.dts
new file mode 100644
index 000000000000..cbe967343997
--- /dev/null
+++ b/arch/arm/boot/dts/at91-foxg20.dts
@@ -0,0 +1,157 @@
+/*
+ * at91-foxg20.dts - Device Tree file for Acme Systems FoxG20 board
+ *
+ * Based on DT files for at91sam9g20ek evaluation board (AT91SAM9G20 SoC)
+ *
+ * Copyright (C) 2013 Douglas Gilbert <dgilbert@interlog.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+#include "at91sam9g20.dtsi"
+/ {
+        model = "Acme Systems FoxG20";
+        compatible = "acme,foxg20", "atmel,at91sam9g20", "atmel,at91sam9";
+        chosen {
+                bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait";
+        };
+        memory {
+                reg = <0x20000000 0x4000000>;
+        };
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <18432000>;
+                };
+        };
+        ahb {
+                apb {
+                        usb1: gadget@fffa4000 {
+                                atmel,vbus-gpio = <&pioC 6 GPIO_ACTIVE_HIGH>;
+                                status = "okay";
+                        };
+                        mmc0: mmc@fffa8000 {
+                                pinctrl-0 = <
+                                        &pinctrl_mmc0_clk
+                                        &pinctrl_mmc0_slot1_cmd_dat0
+                                        &pinctrl_mmc0_slot1_dat1_3>;
+                                status = "okay";
+                                slot@1 {
+                                        reg = <1>;
+                                        bus-width = <4>;
+                                };
+                        };
+                        usart0: serial@fffb0000 {
+                                pinctrl-0 =
+                                        <&pinctrl_usart0
+                                         &pinctrl_usart0_rts
+                                         &pinctrl_usart0_cts
+                                        >;
+                                status = "okay";
+                        };
+                        usart1: serial@fffb4000 {
+                                status = "okay";
+                        };
+                        usart2: serial@fffb8000 {
+                                status = "okay";
+                        };
+                        macb0: ethernet@fffc4000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+                        usart3: serial@fffd0000 {
+                                status = "okay";
+                        };
+                        uart0: serial@fffd4000 {
+                                status = "okay";
+                        };
+                        uart1: serial@fffd8000 {
+                                status = "okay";
+                        };
+                        dbgu: serial@fffff200 {
+                                status = "okay";
+                        };
+                        pinctrl@fffff400 {
+                                board {
+                                        pinctrl_pck0_as_mck: pck0_as_mck {
+                                                atmel,pins =
+                                                        <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                };
+                                mmc0_slot1 {
+                                        pinctrl_board_mmc0_slot1: mmc0_slot1-board {
+                                                atmel,pins =
+                                                        <AT91_PIOC 9 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;   /* CD pin */
+                                        };
+                                };
+                                i2c0 {
+                                        pinctrl_i2c0: i2c0-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE    /* TWD (SDA), open drain */
+                                                         AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE>;  /* TWCK (SCL), open drain */
+                                        };
+                                };
+                        };
+                        watchdog@fffffd40 {
+                                status = "okay";
+                        };
+                };
+                usb0: ohci@00500000 {
+                        num-ports = <2>;
+                        status = "okay";
+                };
+        };
+        i2c@0 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_i2c0>;
+                i2c-gpio,delay-us = <5>;        /* ~85 kHz */
+                status = "okay";
+        };
+        leds {
+                compatible = "gpio-leds";
+                /* red LED marked "PC7" near mini USB (device) receptacle */
+                user_led {
+                        label = "user_led";
+                        gpios = <&pioC 7 GPIO_ACTIVE_HIGH>;     /* PC7 */
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+        gpio_keys {
+                compatible = "gpio-keys";
+                btn {
+                        label = "Button";
+                        gpios = <&pioC 4 GPIO_ACTIVE_LOW>;
+                        linux,code = <0x103>;
+                        gpio-key,wakeup;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index 5d3ed5aafc69..92b9e21389db 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -10,7 +10,10 @@
 * Licensed under GPLv2 or later.
 */
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
 / {
        model = "Atmel AT91RM9200 family SoC";
@@ -35,8 +38,12 @@
                ssc2 = &ssc2;
        };
        cpus {
-                cpu@0 {
+                #address-cells = <0>;
+                #size-cells = <0>;
+                cpu {
                        compatible = "arm,arm920t";
+                        device_type = "cpu";
                };
        };
@@ -77,25 +84,29 @@
                        st: timer@fffffd00 {
                                compatible = "atmel,at91rm9200-st";
                                reg = <0xfffffd00 0x100>;
-                                interrupts = <1 4 7>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                        };
                        tcb0: timer@fffa0000 {
                                compatible = "atmel,at91rm9200-tcb";
                                reg = <0xfffa0000 0x100>;
-                                interrupts = <17 4 0 18 4 0 19 4 0>;
+                                interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
+                                              18 IRQ_TYPE_LEVEL_HIGH 0
+                                              19 IRQ_TYPE_LEVEL_HIGH 0>;
                        };
                        tcb1: timer@fffa4000 {
                                compatible = "atmel,at91rm9200-tcb";
                                reg = <0xfffa4000 0x100>;
-                                interrupts = <20 4 0 21 4 0 22 4 0>;
+                                interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0
+                                              21 IRQ_TYPE_LEVEL_HIGH 0
+                                              22 IRQ_TYPE_LEVEL_HIGH 0>;
                        };
                        i2c0: i2c@fffb8000 {
                                compatible = "atmel,at91rm9200-i2c";
                                reg = <0xfffb8000 0x4000>;
-                                interrupts = <12 4 6>;
+                                interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_twi>;
                                #address-cells = <1>;
@@ -106,7 +117,7 @@
                        mmc0: mmc@fffb4000 {
                                compatible = "atmel,hsmci";
                                reg = <0xfffb4000 0x4000>;
-                                interrupts = <10 4 0>;
+                                interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
                                #address-cells = <1>;
                                #size-cells = <0>;
                                status = "disabled";
@@ -115,7 +126,7 @@
                        ssc0: ssc@fffd0000 {
                                compatible = "atmel,at91rm9200-ssc";
                                reg = <0xfffd0000 0x4000>;
-                                interrupts = <14 4 5>;
+                                interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
                                status = "disable";
@@ -124,7 +135,7 @@
                        ssc1: ssc@fffd4000 {
                                compatible = "atmel,at91rm9200-ssc";
                                reg = <0xfffd4000 0x4000>;
-                                interrupts = <15 4 5>;
+                                interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
                                status = "disable";
@@ -133,7 +144,7 @@
                        ssc2: ssc@fffd8000 {
                                compatible = "atmel,at91rm9200-ssc";
                                reg = <0xfffd8000 0x4000>;
-                                interrupts = <16 4 5>;
+                                interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
                                status = "disable";
@@ -142,7 +153,7 @@
                        macb0: ethernet@fffbc000 {
                                compatible = "cdns,at91rm9200-emac", "cdns,emac";
                                reg = <0xfffbc000 0x4000>;
-                                interrupts = <24 4 3>;
+                                interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
                                phy-mode = "rmii";
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_macb_rmii>;
@@ -167,234 +178,319 @@
                                dbgu {
                                        pinctrl_dbgu: dbgu-0 {
                                                atmel,pins =
-                                                        <0 30 0x1 0x0   /* PA30 periph A */
+                                                        <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA30 periph A */
-                                                         0 31 0x1 0x1>; /* PA31 periph with pullup */
+                                                         AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA31 periph with pullup */
                                        };
                                };
                                uart0 {
                                        pinctrl_uart0: uart0-0 {
                                                atmel,pins =
-                                                        <0 17 0x1 0x0   /* PA17 periph A */
+                                                        <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA17 periph A */
-                                                         0 18 0x1 0x0>; /* PA18 periph A */
+                                                         AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA18 periph A */
                                        };
                                        pinctrl_uart0_rts: uart0_rts-0 {
                                                atmel,pins =
-                                                        <0 20 0x1 0x0>; /* PA20 periph A */
+                                                        <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A */
                                        };
                                        pinctrl_uart0_cts: uart0_cts-0 {
                                                atmel,pins =
-                                                        <0 21 0x1 0x0>; /* PA21 periph A */
+                                                        <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */
                                        };
                                };
                                uart1 {
                                        pinctrl_uart1: uart1-0 {
                                                atmel,pins =
-                                                        <1 20 0x1 0x1   /* PB20 periph A with pullup */
+                                                        <AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PB20 periph A with pullup */
-                                                         1 21 0x1 0x0>; /* PB21 periph A */
+                                                         AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB21 periph A */
                                        };
                                        pinctrl_uart1_rts: uart1_rts-0 {
                                                atmel,pins =
-                                                        <1 24 0x1 0x0>; /* PB24 periph A */
+                                                        <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB24 periph A */
                                        };
                                        pinctrl_uart1_cts: uart1_cts-0 {
                                                atmel,pins =
-                                                        <1 26 0x1 0x0>; /* PB26 periph A */
+                                                        <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB26 periph A */
                                        };
                                        pinctrl_uart1_dtr_dsr: uart1_dtr_dsr-0 {
                                                atmel,pins =
-                                                        <1 19 0x1 0x0   /* PB19 periph A */
+                                                        <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB19 periph A */
-                                                         1 25 0x1 0x0>; /* PB25 periph A */
+                                                         AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB25 periph A */
                                        };
                                        pinctrl_uart1_dcd: uart1_dcd-0 {
                                                atmel,pins =
-                                                        <1 23 0x1 0x0>; /* PB23 periph A */
+                                                        <AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB23 periph A */
                                        };
                                        pinctrl_uart1_ri: uart1_ri-0 {
                                                atmel,pins =
-                                                        <1 18 0x1 0x0>; /* PB18 periph A */
+                                                        <AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */
                                        };
                                };
                                uart2 {
                                        pinctrl_uart2: uart2-0 {
                                                atmel,pins =
-                                                        <0 22 0x1 0x0   /* PA22 periph A */
+                                                        <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA22 periph A */
-                                                         0 23 0x1 0x1>; /* PA23 periph A with pullup */
+                                                         AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA23 periph A with pullup */
                                        };
                                        pinctrl_uart2_rts: uart2_rts-0 {
                                                atmel,pins =
-                                                        <0 30 0x2 0x0>; /* PA30 periph B */
+                                                        <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */
                                        };
                                        pinctrl_uart2_cts: uart2_cts-0 {
                                                atmel,pins =
-                                                        <0 31 0x2 0x0>; /* PA31 periph B */
+                                                        <AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA31 periph B */
                                        };
                                };
                                uart3 {
                                        pinctrl_uart3: uart3-0 {
                                                atmel,pins =
-                                                        <0 5 0x2 0x1    /* PA5 periph B with pullup */
+                                                        <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA5 periph B with pullup */
-                                                         0 6 0x2 0x0>;  /* PA6 periph B */
+                                                         AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PA6 periph B */
                                        };
                                        pinctrl_uart3_rts: uart3_rts-0 {
                                                atmel,pins =
-                                                        <1 0 0x2 0x0>;  /* PB0 periph B */
+                                                        <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PB0 periph B */
                                        };
                                        pinctrl_uart3_cts: uart3_cts-0 {
                                                atmel,pins =
-                                                        <1 1 0x2 0x0>;  /* PB1 periph B */
+                                                        <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PB1 periph B */
                                        };
                                };
                                nand {
                                        pinctrl_nand: nand-0 {
                                                atmel,pins =
-                                                        <2 2 0x0 0x1    /* PC2 gpio RDY pin pull_up */
+                                                        <AT91_PIOC 2 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP      /* PC2 gpio RDY pin pull_up */
-                                                         1 1 0x0 0x1>;  /* PB1 gpio CD pin pull_up */
+                                                         AT91_PIOB 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;    /* PB1 gpio CD pin pull_up */
                                        };
                                };
                                macb {
                                        pinctrl_macb_rmii: macb_rmii-0 {
                                                atmel,pins =
-                                                        <0 7 0x1 0x0    /* PA7 periph A */
+                                                        <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA7 periph A */
-                                                         0 8 0x1 0x0    /* PA8 periph A */
+                                                         AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA8 periph A */
-                                                         0 9 0x1 0x0    /* PA9 periph A */
+                                                         AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA9 periph A */
-                                                         0 10 0x1 0x0   /* PA10 periph A */
+                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA10 periph A */
-                                                         0 11 0x1 0x0   /* PA11 periph A */
+                                                         AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA11 periph A */
-                                                         0 12 0x1 0x0   /* PA12 periph A */
+                                                         AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA12 periph A */
-                                                         0 13 0x1 0x0   /* PA13 periph A */
+                                                         AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA13 periph A */
-                                                         0 14 0x1 0x0   /* PA14 periph A */
+                                                         AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA14 periph A */
-                                                         0 15 0x1 0x0   /* PA15 periph A */
+                                                         AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA15 periph A */
-                                                         0 16 0x1 0x0>; /* PA16 periph A */
+                                                         AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA16 periph A */
                                        };
                                        pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
                                                atmel,pins =
-                                                        <1 12 0x2 0x0   /* PB12 periph B */
+                                                        <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB12 periph B */
-                                                         1 13 0x2 0x0   /* PB13 periph B */
+                                                         AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB13 periph B */
-                                                         1 14 0x2 0x0   /* PB14 periph B */
+                                                         AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB14 periph B */
-                                                         1 15 0x2 0x0   /* PB15 periph B */
+                                                         AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB15 periph B */
-                                                         1 16 0x2 0x0   /* PB16 periph B */
+                                                         AT91_PIOB 16 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB16 periph B */
-                                                         1 17 0x2 0x0   /* PB17 periph B */
+                                                         AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB17 periph B */
-                                                         1 18 0x2 0x0   /* PB18 periph B */
+                                                         AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB18 periph B */
-                                                         1 19 0x2 0x0>; /* PB19 periph B */
+                                                         AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB19 periph B */
                                        };
                                };
                                mmc0 {
                                        pinctrl_mmc0_clk: mmc0_clk-0 {
                                                atmel,pins =
-                                                        <0 27 0x1 0x0>; /* PA27 periph A */
+                                                        <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA27 periph A */
                                        };
                                        pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
                                                atmel,pins =
-                                                        <0 28 0x1 0x1   /* PA28 periph A with pullup */
+                                                        <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA28 periph A with pullup */
-                                                         0 29 0x1 0x1>; /* PA29 periph A with pullup */
+                                                         AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA29 periph A with pullup */
                                        };
                                        pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
                                                atmel,pins =
-                                                        <1 3 0x2 0x1    /* PB3 periph B with pullup */
+                                                        <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PB3 periph B with pullup */
-                                                         1 4 0x2 0x1    /* PB4 periph B with pullup */
+                                                         AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PB4 periph B with pullup */
-                                                         1 5 0x2 0x1>;  /* PB5 periph B with pullup */
+                                                         AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;       /* PB5 periph B with pullup */
                                        };
                                        pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
                                                atmel,pins =
-                                                        <0 8 0x2 0x1    /* PA8 periph B with pullup */
+                                                        <AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA8 periph B with pullup */
-                                                         0 9 0x2 0x1>;  /* PA9 periph B with pullup */
+                                                         AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;       /* PA9 periph B with pullup */
                                        };
                                        pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
                                                atmel,pins =
-                                                        <0 10 0x2 0x1   /* PA10 periph B with pullup */
+                                                        <AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* PA10 periph B with pullup */
-                                                         0 11 0x2 0x1   /* PA11 periph B with pullup */
+                                                         AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* PA11 periph B with pullup */
-                                                         0 12 0x2 0x1>; /* PA12 periph B with pullup */
+                                                         AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;      /* PA12 periph B with pullup */
                                        };
                                };
                                ssc0 {
                                        pinctrl_ssc0_tx: ssc0_tx-0 {
                                                atmel,pins =
-                                                        <1 0 0x1 0x0    /* PB0 periph A */
+                                                        <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB0 periph A */
-                                                         1 1 0x1 0x0    /* PB1 periph A */
+                                                         AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB1 periph A */
-                                                         1 2 0x1 0x0>;  /* PB2 periph A */
+                                                         AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB2 periph A */
                                        };
                                        pinctrl_ssc0_rx: ssc0_rx-0 {
                                                atmel,pins =
-                                                        <1 3 0x1 0x0    /* PB3 periph A */
+                                                        <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB3 periph A */
-                                                         1 4 0x1 0x0    /* PB4 periph A */
+                                                         AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB4 periph A */
-                                                         1 5 0x1 0x0>;  /* PB5 periph A */
+                                                         AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB5 periph A */
                                        };
                                };
                                ssc1 {
                                        pinctrl_ssc1_tx: ssc1_tx-0 {
                                                atmel,pins =
-                                                        <1 6 0x1 0x0    /* PB6 periph A */
+                                                        <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB6 periph A */
-                                                         1 7 0x1 0x0    /* PB7 periph A */
+                                                         AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB7 periph A */
-                                                         1 8 0x1 0x0>;  /* PB8 periph A */
+                                                         AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB8 periph A */
                                        };
                                        pinctrl_ssc1_rx: ssc1_rx-0 {
                                                atmel,pins =
-                                                        <1 9 0x1 0x0    /* PB9 periph A */
+                                                        <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB9 periph A */
-                                                         1 10 0x1 0x0   /* PB10 periph A */
+                                                         AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB10 periph A */
-                                                         1 11 0x1 0x0>; /* PB11 periph A */
+                                                         AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */
                                        };
                                };
                                ssc2 {
                                        pinctrl_ssc2_tx: ssc2_tx-0 {
                                                atmel,pins =
-                                                        <1 12 0x1 0x0   /* PB12 periph A */
+                                                        <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB12 periph A */
-                                                         1 13 0x1 0x0   /* PB13 periph A */
+                                                         AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB13 periph A */
-                                                         1 14 0x1 0x0>; /* PB14 periph A */
+                                                         AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A */
                                        };
                                        pinctrl_ssc2_rx: ssc2_rx-0 {
                                                atmel,pins =
-                                                        <1 15 0x1 0x0   /* PB15 periph A */
+                                                        <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB15 periph A */
-                                                         1 16 0x1 0x0   /* PB16 periph A */
+                                                         AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB16 periph A */
-                                                         1 17 0x1 0x0>; /* PB17 periph A */
+                                                         AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */
                                        };
                                };
                                twi {
                                        pinctrl_twi: twi-0 {
                                                atmel,pins =
-                                                        <0 25 0x1 0x2   /* PA25 periph A with multi drive */
+                                                        <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE    /* PA25 periph A with multi drive */
-                                                         0 26 0x1 0x2>; /* PA26 periph A with multi drive */
+                                                         AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE>;  /* PA26 periph A with multi drive */
                                        };
                                        pinctrl_twi_gpio: twi_gpio-0 {
                                                atmel,pins =
-                                                        <0 25 0x0 0x2   /* PA25 GPIO with multi drive */
+                                                        <AT91_PIOA 25 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PA25 GPIO with multi drive */
-                                                         0 26 0x0 0x2>; /* PA26 GPIO with multi drive */
+                                                         AT91_PIOA 26 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;       /* PA26 GPIO with multi drive */
+                                        };
+                                };
+                                tcb0 {
+                                        pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+                                                atmel,pins = <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+                                                atmel,pins = <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+                                                atmel,pins = <AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+                                                atmel,pins = <AT91_PIOA 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+                                                atmel,pins = <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+                                                atmel,pins = <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+                                                atmel,pins = <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+                                                atmel,pins = <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+                                                atmel,pins = <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                };
+                                tcb1 {
+                                        pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
+                                                atmel,pins = <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
+                                                atmel,pins = <AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
+                                                atmel,pins = <AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
+                                                atmel,pins = <AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
+                                                atmel,pins = <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
+                                                atmel,pins = <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
+                                                atmel,pins = <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
+                                                atmel,pins = <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
+                                                atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                };
+                                spi0 {
+                                        pinctrl_spi0: spi0-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA0 periph A SPI0_MISO pin */
+                                                         AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA1 periph A SPI0_MOSI pin */
+                                                         AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA2 periph A SPI0_SPCK pin */
                                        };
                                };
                                pioA: gpio@fffff400 {
                                        compatible = "atmel,at91rm9200-gpio";
                                        reg = <0xfffff400 0x200>;
-                                        interrupts = <2 4 1>;
+                                        interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
                                        #gpio-cells = <2>;
                                        gpio-controller;
                                        interrupt-controller;
@@ -404,7 +500,7 @@
                                pioB: gpio@fffff600 {
                                        compatible = "atmel,at91rm9200-gpio";
                                        reg = <0xfffff600 0x200>;
-                                        interrupts = <3 4 1>;
+                                        interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
                                        #gpio-cells = <2>;
                                        gpio-controller;
                                        interrupt-controller;
@@ -414,7 +510,7 @@
                                pioC: gpio@fffff800 {
                                        compatible = "atmel,at91rm9200-gpio";
                                        reg = <0xfffff800 0x200>;
-                                        interrupts = <4 4 1>;
+                                        interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
                                        #gpio-cells = <2>;
                                        gpio-controller;
                                        interrupt-controller;
@@ -424,7 +520,7 @@
                                pioD: gpio@fffffa00 {
                                        compatible = "atmel,at91rm9200-gpio";
                                        reg = <0xfffffa00 0x200>;
-                                        interrupts = <5 4 1>;
+                                        interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
                                        #gpio-cells = <2>;
                                        gpio-controller;
                                        interrupt-controller;
@@ -435,7 +531,7 @@
                        dbgu: serial@fffff200 {
                                compatible = "atmel,at91rm9200-usart";
                                reg = <0xfffff200 0x200>;
-                                interrupts = <1 4 7>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_dbgu>;
                                status = "disabled";
@@ -444,7 +540,7 @@
                        usart0: serial@fffc0000 {
                                compatible = "atmel,at91rm9200-usart";
                                reg = <0xfffc0000 0x200>;
-                                interrupts = <6 4 5>;
+                                interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
                                pinctrl-names = "default";
@@ -455,7 +551,7 @@
                        usart1: serial@fffc4000 {
                                compatible = "atmel,at91rm9200-usart";
                                reg = <0xfffc4000 0x200>;
-                                interrupts = <7 4 5>;
+                                interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
                                pinctrl-names = "default";
@@ -466,7 +562,7 @@
                        usart2: serial@fffc8000 {
                                compatible = "atmel,at91rm9200-usart";
                                reg = <0xfffc8000 0x200>;
-                                interrupts = <8 4 5>;
+                                interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
                                pinctrl-names = "default";
@@ -477,7 +573,7 @@
                        usart3: serial@fffcc000 {
                                compatible = "atmel,at91rm9200-usart";
                                reg = <0xfffcc000 0x200>;
-                                interrupts = <23 4 5>;
+                                interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
                                pinctrl-names = "default";
@@ -488,7 +584,18 @@
                        usb1: gadget@fffb0000 {
                                compatible = "atmel,at91rm9200-udc";
                                reg = <0xfffb0000 0x4000>;
-                                interrupts = <11 4 2>;
+                                interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>;
+                                status = "disabled";
+                        };
+                        spi0: spi@fffe0000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "atmel,at91rm9200-spi";
+                                reg = <0xfffe0000 0x200>;
+                                interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_spi0>;
                                status = "disabled";
                        };
                };
@@ -503,9 +610,9 @@
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_nand>;
                        nand-ecc-mode = "soft";
-                        gpios = <&pioC 2 0
+                        gpios = <&pioC 2 GPIO_ACTIVE_HIGH
                                 0
-                                 &pioB 1 0
+                                 &pioB 1 GPIO_ACTIVE_HIGH
                                >;
                        status = "disabled";
                };
@@ -513,15 +620,15 @@
                usb0: ohci@00300000 {
                        compatible = "atmel,at91rm9200-ohci", "usb-ohci";
                        reg = <0x00300000 0x100000>;
-                        interrupts = <23 4 2>;
+                        interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
                        status = "disabled";
                };
        };
        i2c@0 {
                compatible = "i2c-gpio";
-                gpios = <&pioA 25 0 /* sda */
+                gpios = <&pioA 25 GPIO_ACTIVE_HIGH /* sda */
-                         &pioA 26 0 /* scl */
+                         &pioA 26 GPIO_ACTIVE_HIGH /* scl */
                        >;
                i2c-gpio,sda-open-drain;
                i2c-gpio,scl-open-drain;
diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts
index e586d85f8e23..d2d72c3b44c4 100644
--- a/arch/arm/boot/dts/at91rm9200ek.dts
+++ b/arch/arm/boot/dts/at91rm9200ek.dts
@@ -6,7 +6,7 @@
 * Licensed under GPLv2 only
 */
 /dts-v1/;
-/include/ "at91rm9200.dtsi"
+#include "at91rm9200.dtsi"
 / {
        model = "Atmel AT91RM9200 evaluation kit";
@@ -50,9 +50,19 @@
                        };
                        usb1: gadget@fffb0000 {
-                                atmel,vbus-gpio = <&pioD 4 0>;
+                                atmel,vbus-gpio = <&pioD 4 GPIO_ACTIVE_HIGH>;
                                status = "okay";
                        };
+                        spi0: spi@fffe0000 {
+                                status = "okay";
+                                cs-gpios = <&pioA 3 0>, <0>, <0>, <0>;
+                                mtd_dataflash@0 {
+                                        compatible = "atmel,at45", "atmel,dataflash";
+                                        spi-max-frequency = <15000000>;
+                                        reg = <0>;
+                                };
+                        };
                };
                usb0: ohci@00300000 {
@@ -66,19 +76,19 @@
                ds2 {
                        label = "green";
-                        gpios = <&pioB 0 0x1>;
+                        gpios = <&pioB 0 GPIO_ACTIVE_LOW>;
                        linux,default-trigger = "mmc0";
                };
                ds4 {
                        label = "yellow";
-                        gpios = <&pioB 1 0x1>;
+                        gpios = <&pioB 1 GPIO_ACTIVE_LOW>;
                        linux,default-trigger = "heartbeat";
                };
                ds6 {
                        label = "red";
-                        gpios = <&pioB 2 0x1>;
+                        gpios = <&pioB 2 GPIO_ACTIVE_LOW>;
                };
        };
 };
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 84c4bef2d726..c7ccbcbffb3e 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -8,7 +8,10 @@
 * Licensed under GPLv2 or later.
 */
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
 / {
        model = "Atmel AT91SAM9260 family SoC";
@@ -32,8 +35,12 @@
                ssc0 = &ssc0;
        };
        cpus {
-                cpu@0 {
+                #address-cells = <0>;
-                        compatible = "arm,arm926ejs";
+                #size-cells = <0>;
+                cpu {
+                        compatible = "arm,arm926ej-s";
+                        device_type = "cpu";
                };
        };
@@ -84,19 +91,23 @@
                        pit: timer@fffffd30 {
                                compatible = "atmel,at91sam9260-pit";
                                reg = <0xfffffd30 0xf>;
-                                interrupts = <1 4 7>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                        };
                        tcb0: timer@fffa0000 {
                                compatible = "atmel,at91rm9200-tcb";
                                reg = <0xfffa0000 0x100>;
-                                interrupts = <17 4 0 18 4 0 19 4 0>;
+                                interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
+                                              18 IRQ_TYPE_LEVEL_HIGH 0
+                                              19 IRQ_TYPE_LEVEL_HIGH 0>;
                        };
                        tcb1: timer@fffdc000 {
                                compatible = "atmel,at91rm9200-tcb";
                                reg = <0xfffdc000 0x100>;
-                                interrupts = <26 4 0 27 4 0 28 4 0>;
+                                interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0
+                                              27 IRQ_TYPE_LEVEL_HIGH 0
+                                              28 IRQ_TYPE_LEVEL_HIGH 0>;
                        };
                        pinctrl@fffff400 {
@@ -116,234 +127,318 @@
                                dbgu {
                                        pinctrl_dbgu: dbgu-0 {
                                                atmel,pins =
-                                                        <1 14 0x1 0x0   /* PB14 periph A */
+                                                        <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB14 periph A */
-                                                         1 15 0x1 0x1>; /* PB15 periph with pullup */
+                                                         AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PB15 periph with pullup */
                                        };
                                };
                                usart0 {
                                        pinctrl_usart0: usart0-0 {
                                                atmel,pins =
-                                                        <1 4 0x1 0x0    /* PB4 periph A */
+                                                        <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB4 periph A */
-                                                         1 5 0x1 0x0>;  /* PB5 periph A */
+                                                         AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB5 periph A */
                                        };
                                        pinctrl_usart0_rts: usart0_rts-0 {
                                                atmel,pins =
-                                                        <1 26 0x1 0x0>; /* PB26 periph A */
+                                                        <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB26 periph A */
                                        };
                                        pinctrl_usart0_cts: usart0_cts-0 {
                                                atmel,pins =
-                                                        <1 27 0x1 0x0>; /* PB27 periph A */
+                                                        <AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A */
                                        };
                                        pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 {
                                                atmel,pins =
-                                                        <1 24 0x1 0x0   /* PB24 periph A */
+                                                        <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB24 periph A */
-                                                         1 22 0x1 0x0>; /* PB22 periph A */
+                                                         AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB22 periph A */
                                        };
                                        pinctrl_usart0_dcd: usart0_dcd-0 {
                                                atmel,pins =
-                                                        <1 23 0x1 0x0>; /* PB23 periph A */
+                                                        <AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB23 periph A */
                                        };
                                        pinctrl_usart0_ri: usart0_ri-0 {
                                                atmel,pins =
-                                                        <1 25 0x1 0x0>; /* PB25 periph A */
+                                                        <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB25 periph A */
                                        };
                                };
                                usart1 {
                                        pinctrl_usart1: usart1-0 {
                                                atmel,pins =
-                                                        <1 6 0x1 0x1    /* PB6 periph A with pullup */
+                                                        <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */
-                                                         1 7 0x1 0x0>;  /* PB7 periph A */
+                                                         AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB7 periph A */
                                        };
                                        pinctrl_usart1_rts: usart1_rts-0 {
                                                atmel,pins =
-                                                        <1 28 0x1 0x0>; /* PB28 periph A */
+                                                        <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB28 periph A */
                                        };
                                        pinctrl_usart1_cts: usart1_cts-0 {
                                                atmel,pins =
-                                                        <1 29 0x1 0x0>; /* PB29 periph A */
+                                                        <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB29 periph A */
                                        };
                                };
                                usart2 {
                                        pinctrl_usart2: usart2-0 {
                                                atmel,pins =
-                                                        <1 8 0x1 0x1    /* PB8 periph A with pullup */
+                                                        <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB8 periph A with pullup */
-                                                         1 9 0x1 0x0>;  /* PB9 periph A */
+                                                         AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB9 periph A */
                                        };
                                        pinctrl_usart2_rts: usart2_rts-0 {
                                                atmel,pins =
-                                                        <0 4 0x1 0x0>;  /* PA4 periph A */
+                                                        <AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA4 periph A */
                                        };
                                        pinctrl_usart2_cts: usart2_cts-0 {
                                                atmel,pins =
-                                                        <0 5 0x1 0x0>;  /* PA5 periph A */
+                                                        <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA5 periph A */
                                        };
                                };
                                usart3 {
                                        pinctrl_usart3: usart3-0 {
                                                atmel,pins =
-                                                        <1 10 0x1 0x1   /* PB10 periph A with pullup */
+                                                        <AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PB10 periph A with pullup */
-                                                         1 11 0x1 0x0>; /* PB11 periph A */
+                                                         AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */
                                        };
                                        pinctrl_usart3_rts: usart3_rts-0 {
                                                atmel,pins =
-                                                        <2 8 0x2 0x0>;  /* PC8 periph B */
+                                                        <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PC8 periph B */
                                        };
                                        pinctrl_usart3_cts: usart3_cts-0 {
                                                atmel,pins =
-                                                        <2 10 0x2 0x0>; /* PC10 periph B */
+                                                        <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC10 periph B */
                                        };
                                };
                                uart0 {
                                        pinctrl_uart0: uart0-0 {
                                                atmel,pins =
-                                                        <0 31 0x2 0x1   /* PA31 periph B with pullup */
+                                                        <AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* PA31 periph B with pullup */
-                                                         0 30 0x2 0x0>; /* PA30 periph B */
+                                                         AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */
                                        };
                                };
                                uart1 {
                                        pinctrl_uart1: uart1-0 {
                                                atmel,pins =
-                                                        <1 12 0x1 0x1   /* PB12 periph A with pullup */
+                                                        <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PB12 periph A with pullup */
-                                                         1 13 0x1 0x0>; /* PB13 periph A */
+                                                         AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */
                                        };
                                };
                                nand {
                                        pinctrl_nand: nand-0 {
                                                atmel,pins =
-                                                        <2 13 0x0 0x1   /* PC13 gpio RDY pin pull_up */
+                                                        <AT91_PIOC 13 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP     /* PC13 gpio RDY pin pull_up */
-                                                         2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
+                                                         AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;   /* PC14 gpio enable pin pull_up */
                                        };
                                };
                                macb {
                                        pinctrl_macb_rmii: macb_rmii-0 {
                                                atmel,pins =
-                                                        <0 12 0x1 0x0   /* PA12 periph A */
+                                                        <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA12 periph A */
-                                                         0 13 0x1 0x0   /* PA13 periph A */
+                                                         AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA13 periph A */
-                                                         0 14 0x1 0x0   /* PA14 periph A */
+                                                         AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA14 periph A */
-                                                         0 15 0x1 0x0   /* PA15 periph A */
+                                                         AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA15 periph A */
-                                                         0 16 0x1 0x0   /* PA16 periph A */
+                                                         AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA16 periph A */
-                                                         0 17 0x1 0x0   /* PA17 periph A */
+                                                         AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA17 periph A */
-                                                         0 18 0x1 0x0   /* PA18 periph A */
+                                                         AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA18 periph A */
-                                                         0 19 0x1 0x0   /* PA19 periph A */
+                                                         AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA19 periph A */
-                                                         0 20 0x1 0x0   /* PA20 periph A */
+                                                         AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA20 periph A */
-                                                         0 21 0x1 0x0>; /* PA21 periph A */
+                                                         AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */
                                        };
                                        pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
                                                atmel,pins =
-                                                        <0 22 0x2 0x0   /* PA22 periph B */
+                                                        <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA22 periph B */
-                                                         0 23 0x2 0x0   /* PA23 periph B */
+                                                         AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA23 periph B */
-                                                         0 24 0x2 0x0   /* PA24 periph B */
+                                                         AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA24 periph B */
-                                                         0 25 0x2 0x0   /* PA25 periph B */
+                                                         AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA25 periph B */
-                                                         0 26 0x2 0x0   /* PA26 periph B */
+                                                         AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA26 periph B */
-                                                         0 27 0x2 0x0   /* PA27 periph B */
+                                                         AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA27 periph B */
-                                                         0 28 0x2 0x0   /* PA28 periph B */
+                                                         AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA28 periph B */
-                                                         0 29 0x2 0x0>; /* PA29 periph B */
+                                                         AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */
                                        };
                                        pinctrl_macb_rmii_mii_alt: macb_rmii_mii-1 {
                                                atmel,pins =
-                                                        <0 10 0x2 0x0   /* PA10 periph B */
+                                                        <AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA10 periph B */
-                                                         0 11 0x2 0x0   /* PA11 periph B */
+                                                         AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA11 periph B */
-                                                         0 22 0x2 0x0   /* PA22 periph B */
+                                                         AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA22 periph B */
-                                                         0 25 0x2 0x0   /* PA25 periph B */
+                                                         AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA25 periph B */
-                                                         0 26 0x2 0x0   /* PA26 periph B */
+                                                         AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA26 periph B */
-                                                         0 27 0x2 0x0   /* PA27 periph B */
+                                                         AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA27 periph B */
-                                                         0 28 0x2 0x0   /* PA28 periph B */
+                                                         AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA28 periph B */
-                                                         0 29 0x2 0x0>; /* PA29 periph B */
+                                                         AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */
                                        };
                                };
                                mmc0 {
                                        pinctrl_mmc0_clk: mmc0_clk-0 {
                                                atmel,pins =
-                                                        <0 8 0x1 0x0>;  /* PA8 periph A */
+                                                        <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA8 periph A */
                                        };
                                        pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
                                                atmel,pins =
-                                                        <0 7 0x1 0x1    /* PA7 periph A with pullup */
+                                                        <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
-                                                         0 6 0x1 0x1>;  /* PA6 periph A with pullup */
+                                                         AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;       /* PA6 periph A with pullup */
                                        };
                                        pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
                                                atmel,pins =
-                                                        <0 9 0x1 0x1    /* PA9 periph A with pullup */
+                                                        <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA9 periph A with pullup */
-                                                         0 10 0x1 0x1   /* PA10 periph A with pullup */
+                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA10 periph A with pullup */
-                                                         0 11 0x1 0x1>; /* PA11 periph A with pullup */
+                                                         AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA11 periph A with pullup */
                                        };
                                        pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
                                                atmel,pins =
-                                                        <0 1 0x2 0x1    /* PA1 periph B with pullup */
+                                                        <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA1 periph B with pullup */
-                                                         0 0 0x2 0x1>;  /* PA0 periph B with pullup */
+                                                         AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;       /* PA0 periph B with pullup */
                                        };
                                        pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
                                                atmel,pins =
-                                                        <0 5 0x2 0x1    /* PA5 periph B with pullup */
+                                                        <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA5 periph B with pullup */
-                                                         0 4 0x2 0x1    /* PA4 periph B with pullup */
+                                                         AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA4 periph B with pullup */
-                                                         0 3 0x2 0x1>;  /* PA3 periph B with pullup */
+                                                         AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;       /* PA3 periph B with pullup */
                                        };
                                };
                                ssc0 {
                                        pinctrl_ssc0_tx: ssc0_tx-0 {
                                                atmel,pins =
-                                                        <1 16 0x1 0x0   /* PB16 periph A */
+                                                        <AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB16 periph A */
-                                                         1 17 0x1 0x0   /* PB17 periph A */
+                                                         AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB17 periph A */
-                                                         1 18 0x1 0x0>; /* PB18 periph A */
+                                                         AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */
                                        };
                                        pinctrl_ssc0_rx: ssc0_rx-0 {
                                                atmel,pins =
-                                                        <1 19 0x1 0x0   /* PB19 periph A */
+                                                        <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB19 periph A */
-                                                         1 20 0x1 0x0   /* PB20 periph A */
+                                                         AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB20 periph A */
-                                                         1 21 0x1 0x0>; /* PB21 periph A */
+                                                         AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB21 periph A */
                                        };
                                };
                                spi0 {
                                        pinctrl_spi0: spi0-0 {
                                                atmel,pins =
-                                                        <0 0 0x1 0x0    /* PA0 periph A SPI0_MISO pin */
+                                                        <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA0 periph A SPI0_MISO pin */
-                                                         0 1 0x1 0x0    /* PA1 periph A SPI0_MOSI pin */
+                                                         AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA1 periph A SPI0_MOSI pin */
-                                                         0 2 0x1 0x0>;  /* PA2 periph A SPI0_SPCK pin */
+                                                         AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA2 periph A SPI0_SPCK pin */
                                        };
                                };
                                spi1 {
                                        pinctrl_spi1: spi1-0 {
                                                atmel,pins =
-                                                        <1 0 0x1 0x0    /* PB0 periph A SPI1_MISO pin */
+                                                        <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB0 periph A SPI1_MISO pin */
-                                                         1 1 0x1 0x0    /* PB1 periph A SPI1_MOSI pin */
+                                                         AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB1 periph A SPI1_MOSI pin */
-                                                         1 2 0x1 0x0>;  /* PB2 periph A SPI1_SPCK pin */
+                                                         AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB2 periph A SPI1_SPCK pin */
+                                        };
+                                };
+                                i2c_gpio0 {
+                                        pinctrl_i2c_gpio0: i2c_gpio0-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 23 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE
+                                                         AT91_PIOA 24 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;
+                                        };
+                                };
+                                tcb0 {
+                                        pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+                                                atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+                                                atmel,pins = <AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+                                                atmel,pins = <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+                                                atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+                                                atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+                                                atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+                                                atmel,pins = <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+                                                atmel,pins = <AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+                                                atmel,pins = <AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                };
+                                tcb1 {
+                                        pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
+                                                atmel,pins = <AT91_PIOB 16 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
+                                                atmel,pins = <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
+                                                atmel,pins = <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
+                                                atmel,pins = <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
+                                                atmel,pins = <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
+                                                atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
+                                                atmel,pins = <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
+                                                atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
+                                                atmel,pins = <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
                                        };
                                };
                                pioA: gpio@fffff400 {
                                        compatible = "atmel,at91rm9200-gpio";
                                        reg = <0xfffff400 0x200>;
-                                        interrupts = <2 4 1>;
+                                        interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
                                        #gpio-cells = <2>;
                                        gpio-controller;
                                        interrupt-controller;
@@ -353,7 +448,7 @@
                                pioB: gpio@fffff600 {
                                        compatible = "atmel,at91rm9200-gpio";
                                        reg = <0xfffff600 0x200>;
-                                        interrupts = <3 4 1>;
+                                        interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
                                        #gpio-cells = <2>;
                                        gpio-controller;
                                        interrupt-controller;
@@ -363,7 +458,7 @@
                                pioC: gpio@fffff800 {
                                        compatible = "atmel,at91rm9200-gpio";
                                        reg = <0xfffff800 0x200>;
-                                        interrupts = <4 4 1>;
+                                        interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
                                        #gpio-cells = <2>;
                                        gpio-controller;
                                        interrupt-controller;
@@ -374,7 +469,7 @@
                        dbgu: serial@fffff200 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xfffff200 0x200>;
-                                interrupts = <1 4 7>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_dbgu>;
                                status = "disabled";
@@ -383,7 +478,7 @@
                        usart0: serial@fffb0000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xfffb0000 0x200>;
-                                interrupts = <6 4 5>;
+                                interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
                                pinctrl-names = "default";
@@ -394,7 +489,7 @@
                        usart1: serial@fffb4000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xfffb4000 0x200>;
-                                interrupts = <7 4 5>;
+                                interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
                                pinctrl-names = "default";
@@ -405,7 +500,7 @@
                        usart2: serial@fffb8000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xfffb8000 0x200>;
-                                interrupts = <8 4 5>;
+                                interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
                                pinctrl-names = "default";
@@ -416,7 +511,7 @@
                        usart3: serial@fffd0000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xfffd0000 0x200>;
-                                interrupts = <23 4 5>;
+                                interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
                                pinctrl-names = "default";
@@ -427,7 +522,7 @@
                        uart0: serial@fffd4000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xfffd4000 0x200>;
-                                interrupts = <24 4 5>;
+                                interrupts = <24 IRQ_TYPE_LEVEL_HIGH 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
                                pinctrl-names = "default";
@@ -438,7 +533,7 @@
                        uart1: serial@fffd8000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xfffd8000 0x200>;
-                                interrupts = <25 4 5>;
+                                interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
                                pinctrl-names = "default";
@@ -449,7 +544,7 @@
                        macb0: ethernet@fffc4000 {
                                compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                reg = <0xfffc4000 0x100>;
-                                interrupts = <21 4 3>;
+                                interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_macb_rmii>;
                                status = "disabled";
@@ -458,14 +553,14 @@
                        usb1: gadget@fffa4000 {
                                compatible = "atmel,at91rm9200-udc";
                                reg = <0xfffa4000 0x4000>;
-                                interrupts = <10 4 2>;
+                                interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
                                status = "disabled";
                        };
                        i2c0: i2c@fffac000 {
                                compatible = "atmel,at91sam9260-i2c";
                                reg = <0xfffac000 0x100>;
-                                interrupts = <11 4 6>;
+                                interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
                                #address-cells = <1>;
                                #size-cells = <0>;
                                status = "disabled";
@@ -474,7 +569,7 @@
                        mmc0: mmc@fffa8000 {
                                compatible = "atmel,hsmci";
                                reg = <0xfffa8000 0x600>;
-                                interrupts = <9 4 0>;
+                                interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
                                #address-cells = <1>;
                                #size-cells = <0>;
                                status = "disabled";
@@ -483,7 +578,7 @@
                        ssc0: ssc@fffbc000 {
                                compatible = "atmel,at91rm9200-ssc";
                                reg = <0xfffbc000 0x4000>;
-                                interrupts = <14 4 5>;
+                                interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
                                status = "disabled";
@@ -494,7 +589,7 @@
                                #size-cells = <0>;
                                compatible = "atmel,at91rm9200-spi";
                                reg = <0xfffc8000 0x200>;
-                                interrupts = <12 4 3>;
+                                interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_spi0>;
                                status = "disabled";
@@ -505,7 +600,7 @@
                                #size-cells = <0>;
                                compatible = "atmel,at91rm9200-spi";
                                reg = <0xfffcc000 0x200>;
-                                interrupts = <13 4 3>;
+                                interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_spi1>;
                                status = "disabled";
@@ -514,7 +609,7 @@
                        adc0: adc@fffe0000 {
                                compatible = "atmel,at91sam9260-adc";
                                reg = <0xfffe0000 0x100>;
-                                interrupts = <5 4 0>;
+                                interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>;
                                atmel,adc-use-external-triggers;
                                atmel,adc-channels-used = <0xf>;
                                atmel,adc-vref = <3300>;
@@ -567,8 +662,8 @@
                        atmel,nand-cmd-offset = <22>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_nand>;
-                        gpios = <&pioC 13 0
+                        gpios = <&pioC 13 GPIO_ACTIVE_HIGH
-                                 &pioC 14 0
+                                 &pioC 14 GPIO_ACTIVE_HIGH
                                 0
                                >;
                        status = "disabled";
@@ -577,21 +672,23 @@
                usb0: ohci@00500000 {
                        compatible = "atmel,at91rm9200-ohci", "usb-ohci";
                        reg = <0x00500000 0x100000>;
-                        interrupts = <20 4 2>;
+                        interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>;
                        status = "disabled";
                };
        };
        i2c@0 {
                compatible = "i2c-gpio";
-                gpios = <&pioA 23 0 /* sda */
+                gpios = <&pioA 23 GPIO_ACTIVE_HIGH /* sda */
-                         &pioA 24 0 /* scl */
+                         &pioA 24 GPIO_ACTIVE_HIGH /* scl */
                        >;
                i2c-gpio,sda-open-drain;
                i2c-gpio,scl-open-drain;
                i2c-gpio,delay-us = <2>;        /* ~100 kHz */
                #address-cells = <1>;
                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_i2c_gpio0>;
                status = "disabled";
        };
 };
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 94b58ab2cc08..d5bd65f74602 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -6,7 +6,10 @@
 * Licensed under GPLv2 only.
 */
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
 / {
        model = "Atmel AT91SAM9263 family SoC";
@@ -29,8 +32,12 @@
                ssc1 = &ssc1;
        };
        cpus {
-                cpu@0 {
+                #address-cells = <0>;
-                        compatible = "arm,arm926ejs";
+                #size-cells = <0>;
+                cpu {
+                        compatible = "arm,arm926ej-s";
+                        device_type = "cpu";
                };
        };
@@ -72,13 +79,13 @@
                        pit: timer@fffffd30 {
                                compatible = "atmel,at91sam9260-pit";
                                reg = <0xfffffd30 0xf>;
-                                interrupts = <1 4 7>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                        };
                        tcb0: timer@fff7c000 {
                                compatible = "atmel,at91rm9200-tcb";
                                reg = <0xfff7c000 0x100>;
-                                interrupts = <19 4 0>;
+                                interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
                        };
                        rstc@fffffd00 {
@@ -110,221 +117,259 @@
                                dbgu {
                                        pinctrl_dbgu: dbgu-0 {
                                                atmel,pins =
-                                                        <2 30 0x1 0x0   /* PC30 periph A */
+                                                        <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC30 periph A */
-                                                         2 31 0x1 0x1>; /* PC31 periph with pullup */
+                                                         AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PC31 periph with pullup */
                                        };
                                };
                                usart0 {
                                        pinctrl_usart0: usart0-0 {
                                                atmel,pins =
-                                                        <0 26 0x1 0x1   /* PA26 periph A with pullup */
+                                                        <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA26 periph A with pullup */
-                                                         0 27 0x1 0x0>; /* PA27 periph A */
+                                                         AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA27 periph A */
                                        };
                                        pinctrl_usart0_rts: usart0_rts-0 {
                                                atmel,pins =
-                                                        <0 28 0x1 0x0>; /* PA28 periph A */
+                                                        <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA28 periph A */
                                        };
                                        pinctrl_usart0_cts: usart0_cts-0 {
                                                atmel,pins =
-                                                        <0 29 0x1 0x0>; /* PA29 periph A */
+                                                        <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA29 periph A */
                                        };
                                };
                                usart1 {
                                        pinctrl_usart1: usart1-0 {
                                                atmel,pins =
-                                                        <3 0 0x1 0x1    /* PD0 periph A with pullup */
+                                                        <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A with pullup */
-                                                         3 1 0x1 0x0>;  /* PD1 periph A */
+                                                         AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PD1 periph A */
                                        };
                                        pinctrl_usart1_rts: usart1_rts-0 {
                                                atmel,pins =
-                                                        <3 7 0x2 0x0>;  /* PD7 periph B */
+                                                        <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PD7 periph B */
                                        };
                                        pinctrl_usart1_cts: usart1_cts-0 {
                                                atmel,pins =
-                                                        <3 8 0x2 0x0>;  /* PD8 periph B */
+                                                        <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PD8 periph B */
                                        };
                                };
                                usart2 {
                                        pinctrl_usart2: usart2-0 {
                                                atmel,pins =
-                                                        <3 2 0x1 0x1    /* PD2 periph A with pullup */
+                                                        <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A with pullup */
-                                                         3 3 0x1 0x0>;  /* PD3 periph A */
+                                                         AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PD3 periph A */
                                        };
                                        pinctrl_usart2_rts: usart2_rts-0 {
                                                atmel,pins =
-                                                        <3 5 0x2 0x0>;  /* PD5 periph B */
+                                                        <AT91_PIOD 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PD5 periph B */
                                        };
                                        pinctrl_usart2_cts: usart2_cts-0 {
                                                atmel,pins =
-                                                        <4 6 0x2 0x0>;  /* PD6 periph B */
+                                                        <AT91_PIOD 6 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PD6 periph B */
                                        };
                                };
                                nand {
                                        pinctrl_nand: nand-0 {
                                                atmel,pins =
-                                                        <0 22 0x0 0x1   /* PA22 gpio RDY pin pull_up*/
+                                                        <AT91_PIOA 22 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP     /* PA22 gpio RDY pin pull_up*/
-                                                         3 15 0x0 0x1>; /* PD15 gpio enable pin pull_up */
+                                                         AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;   /* PD15 gpio enable pin pull_up */
                                        };
                                };
                                macb {
                                        pinctrl_macb_rmii: macb_rmii-0 {
                                                atmel,pins =
-                                                        <2 25 0x2 0x0   /* PC25 periph B */
+                                                        <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC25 periph B */
-                                                         4 21 0x1 0x0   /* PE21 periph A */
+                                                         AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE21 periph A */
-                                                         4 23 0x1 0x0   /* PE23 periph A */
+                                                         AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE23 periph A */
-                                                         4 24 0x1 0x0   /* PE24 periph A */
+                                                         AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE24 periph A */
-                                                         4 25 0x1 0x0   /* PE25 periph A */
+                                                         AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE25 periph A */
-                                                         4 26 0x1 0x0   /* PE26 periph A */
+                                                         AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE26 periph A */
-                                                         4 27 0x1 0x0   /* PE27 periph A */
+                                                         AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE27 periph A */
-                                                         4 28 0x1 0x0   /* PE28 periph A */
+                                                         AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE28 periph A */
-                                                         4 29 0x1 0x0   /* PE29 periph A */
+                                                         AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE29 periph A */
-                                                         4 30 0x1 0x0>; /* PE30 periph A */
+                                                         AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */
                                        };
                                        pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
                                                atmel,pins =
-                                                        <2 20 0x2 0x0   /* PC20 periph B */
+                                                        <AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC20 periph B */
-                                                         2 21 0x2 0x0   /* PC21 periph B */
+                                                         AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC21 periph B */
-                                                         2 22 0x2 0x0   /* PC22 periph B */
+                                                         AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC22 periph B */
-                                                         2 23 0x2 0x0   /* PC23 periph B */
+                                                         AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC23 periph B */
-                                                         2 24 0x2 0x0   /* PC24 periph B */
+                                                         AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC24 periph B */
-                                                         2 25 0x2 0x0   /* PC25 periph B */
+                                                         AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC25 periph B */
-                                                         2 27 0x2 0x0   /* PC27 periph B */
+                                                         AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC27 periph B */
-                                                         4 22 0x2 0x0>; /* PE22 periph B */
+                                                         AT91_PIOE 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE22 periph B */
                                        };
                                };
                                mmc0 {
                                        pinctrl_mmc0_clk: mmc0_clk-0 {
                                                atmel,pins =
-                                                        <0 12 0x1 0x0>; /* PA12 periph A */
+                                                        <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA12 periph A */
                                        };
                                        pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
                                                atmel,pins =
-                                                        <0 1 0x1 0x1    /* PA1 periph A with pullup */
+                                                        <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
-                                                         0 0 0x1 0x1>;  /* PA0 periph A with pullup */
+                                                         AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;       /* PA0 periph A with pullup */
                                        };
                                        pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
                                                atmel,pins =
-                                                        <0 3 0x1 0x1    /* PA3 periph A with pullup */
+                                                        <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */
-                                                         0 4 0x1 0x1    /* PA4 periph A with pullup */
+                                                         AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */
-                                                         0 5 0x1 0x1>;  /* PA5 periph A with pullup */
+                                                         AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;       /* PA5 periph A with pullup */
                                        };
                                        pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
                                                atmel,pins =
-                                                        <0 16 0x1 0x1   /* PA16 periph A with pullup */
+                                                        <AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA16 periph A with pullup */
-                                                         0 17 0x1 0x1>; /* PA17 periph A with pullup */
+                                                         AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA17 periph A with pullup */
                                        };
                                        pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
                                                atmel,pins =
-                                                        <0 18 0x1 0x1   /* PA18 periph A with pullup */
+                                                        <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA18 periph A with pullup */
-                                                         0 19 0x1 0x1   /* PA19 periph A with pullup */
+                                                         AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA19 periph A with pullup */
-                                                         0 20 0x1 0x1>; /* PA20 periph A with pullup */
+                                                         AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA20 periph A with pullup */
                                        };
                                };
                                mmc1 {
                                        pinctrl_mmc1_clk: mmc1_clk-0 {
                                                atmel,pins =
-                                                        <0 6 0x1 0x0>;  /* PA6 periph A */
+                                                        <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA6 periph A */
                                        };
                                        pinctrl_mmc1_slot0_cmd_dat0: mmc1_slot0_cmd_dat0-0 {
                                                atmel,pins =
-                                                        <0 7 0x1 0x1    /* PA7 periph A with pullup */
+                                                        <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
-                                                         0 8 0x1 0x1>;  /* PA8 periph A with pullup */
+                                                         AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;       /* PA8 periph A with pullup */
                                        };
                                        pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
                                                atmel,pins =
-                                                        <0 9 0x1 0x1    /* PA9 periph A with pullup */
+                                                        <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA9 periph A with pullup */
-                                                         0 10 0x1 0x1   /* PA10 periph A with pullup */
+                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA10 periph A with pullup */
-                                                         0 11 0x1 0x1>; /* PA11 periph A with pullup */
+                                                         AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA11 periph A with pullup */
                                        };
                                        pinctrl_mmc1_slot1_cmd_dat0: mmc1_slot1_cmd_dat0-0 {
                                                atmel,pins =
-                                                        <0 21 0x1 0x1   /* PA21 periph A with pullup */
+                                                        <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA21 periph A with pullup */
-                                                         0 22 0x1 0x1>; /* PA22 periph A with pullup */
+                                                         AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA22 periph A with pullup */
                                        };
                                        pinctrl_mmc1_slot1_dat1_3: mmc1_slot1_dat1_3-0 {
                                                atmel,pins =
-                                                        <0 23 0x1 0x1   /* PA23 periph A with pullup */
+                                                        <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA23 periph A with pullup */
-                                                         0 24 0x1 0x1   /* PA24 periph A with pullup */
+                                                         AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA24 periph A with pullup */
-                                                         0 25 0x1 0x1>; /* PA25 periph A with pullup */
+                                                         AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA25 periph A with pullup */
                                        };
                                };
                                ssc0 {
                                        pinctrl_ssc0_tx: ssc0_tx-0 {
                                                atmel,pins =
-                                                        <1 0 0x2 0x0    /* PB0 periph B */
+                                                        <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE    /* PB0 periph B */
-                                                         1 1 0x2 0x0    /* PB1 periph B */
+                                                         AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE    /* PB1 periph B */
-                                                         1 2 0x2 0x0>;  /* PB2 periph B */
+                                                         AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PB2 periph B */
                                        };
                                        pinctrl_ssc0_rx: ssc0_rx-0 {
                                                atmel,pins =
-                                                        <1 3 0x2 0x0    /* PB3 periph B */
+                                                        <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE    /* PB3 periph B */
-                                                         1 4 0x2 0x0    /* PB4 periph B */
+                                                         AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE    /* PB4 periph B */
-                                                         1 5 0x2 0x0>;  /* PB5 periph B */
+                                                         AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PB5 periph B */
                                        };
                                };
                                ssc1 {
                                        pinctrl_ssc1_tx: ssc1_tx-0 {
                                                atmel,pins =
-                                                        <1 6 0x1 0x0    /* PB6 periph A */
+                                                        <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB6 periph A */
-                                                         1 7 0x1 0x0    /* PB7 periph A */
+                                                         AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB7 periph A */
-                                                         1 8 0x1 0x0>;  /* PB8 periph A */
+                                                         AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB8 periph A */
                                        };
                                        pinctrl_ssc1_rx: ssc1_rx-0 {
                                                atmel,pins =
-                                                        <1 9 0x1 0x0    /* PB9 periph A */
+                                                        <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB9 periph A */
-                                                         1 10 0x1 0x0   /* PB10 periph A */
+                                                         AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB10 periph A */
-                                                         1 11 0x1 0x0>; /* PB11 periph A */
+                                                         AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */
                                        };
                                };
                                spi0 {
                                        pinctrl_spi0: spi0-0 {
                                                atmel,pins =
-                                                        <0 0 0x2 0x0    /* PA0 periph B SPI0_MISO pin */
+                                                        <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE    /* PA0 periph B SPI0_MISO pin */
-                                                         0 1 0x2 0x0    /* PA1 periph B SPI0_MOSI pin */
+                                                         AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE    /* PA1 periph B SPI0_MOSI pin */
-                                                         0 2 0x2 0x0>;  /* PA2 periph B SPI0_SPCK pin */
+                                                         AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PA2 periph B SPI0_SPCK pin */
                                        };
                                };
                                spi1 {
                                        pinctrl_spi1: spi1-0 {
                                                atmel,pins =
-                                                        <1 12 0x1 0x0   /* PB12 periph A SPI1_MISO pin */
+                                                        <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB12 periph A SPI1_MISO pin */
-                                                         1 13 0x1 0x0   /* PB13 periph A SPI1_MOSI pin */
+                                                         AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB13 periph A SPI1_MOSI pin */
-                                                         1 14 0x1 0x0>; /* PB14 periph A SPI1_SPCK pin */
+                                                         AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A SPI1_SPCK pin */
+                                        };
+                                };
+                                tcb0 {
+                                        pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+                                                atmel,pins = <AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+                                                atmel,pins = <AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+                                                atmel,pins = <AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+                                                atmel,pins = <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+                                                atmel,pins = <AT91_PIOE 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+                                                atmel,pins = <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+                                                atmel,pins = <AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+                                                atmel,pins = <AT91_PIOE 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+                                                atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
                                        };
                                };
                                pioA: gpio@fffff200 {
                                        compatible = "atmel,at91rm9200-gpio";
                                        reg = <0xfffff200 0x200>;
-                                        interrupts = <2 4 1>;
+                                        interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
                                        #gpio-cells = <2>;
                                        gpio-controller;
                                        interrupt-controller;
@@ -334,7 +379,7 @@
                                pioB: gpio@fffff400 {
                                        compatible = "atmel,at91rm9200-gpio";
                                        reg = <0xfffff400 0x200>;
-                                        interrupts = <3 4 1>;
+                                        interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
                                        #gpio-cells = <2>;
                                        gpio-controller;
                                        interrupt-controller;
@@ -344,7 +389,7 @@
                                pioC: gpio@fffff600 {
                                        compatible = "atmel,at91rm9200-gpio";
                                        reg = <0xfffff600 0x200>;
-                                        interrupts = <4 4 1>;
+                                        interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
                                        #gpio-cells = <2>;
                                        gpio-controller;
                                        interrupt-controller;
@@ -354,7 +399,7 @@
                                pioD: gpio@fffff800 {
                                        compatible = "atmel,at91rm9200-gpio";
                                        reg = <0xfffff800 0x200>;
-                                        interrupts = <4 4 1>;
+                                        interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
                                        #gpio-cells = <2>;
                                        gpio-controller;
                                        interrupt-controller;
@@ -364,7 +409,7 @@
                                pioE: gpio@fffffa00 {
                                        compatible = "atmel,at91rm9200-gpio";
                                        reg = <0xfffffa00 0x200>;
-                                        interrupts = <4 4 1>;
+                                        interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
                                        #gpio-cells = <2>;
                                        gpio-controller;
                                        interrupt-controller;
@@ -375,7 +420,7 @@
                        dbgu: serial@ffffee00 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xffffee00 0x200>;
-                                interrupts = <1 4 7>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_dbgu>;
                                status = "disabled";
@@ -384,7 +429,7 @@
                        usart0: serial@fff8c000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xfff8c000 0x200>;
-                                interrupts = <7 4 5>;
+                                interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
                                pinctrl-names = "default";
@@ -395,7 +440,7 @@
                        usart1: serial@fff90000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xfff90000 0x200>;
-                                interrupts = <8 4 5>;
+                                interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
                                pinctrl-names = "default";
@@ -406,7 +451,7 @@
                        usart2: serial@fff94000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xfff94000 0x200>;
-                                interrupts = <9 4 5>;
+                                interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
                                pinctrl-names = "default";
@@ -417,7 +462,7 @@
                        ssc0: ssc@fff98000 {
                                compatible = "atmel,at91rm9200-ssc";
                                reg = <0xfff98000 0x4000>;
-                                interrupts = <16 4 5>;
+                                interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
                                status = "disabled";
@@ -426,7 +471,7 @@
                        ssc1: ssc@fff9c000 {
                                compatible = "atmel,at91rm9200-ssc";
                                reg = <0xfff9c000 0x4000>;
-                                interrupts = <17 4 5>;
+                                interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
                                status = "disabled";
@@ -435,7 +480,7 @@
                        macb0: ethernet@fffbc000 {
                                compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                reg = <0xfffbc000 0x100>;
-                                interrupts = <21 4 3>;
+                                interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_macb_rmii>;
                                status = "disabled";
@@ -444,14 +489,14 @@
                        usb1: gadget@fff78000 {
                                compatible = "atmel,at91rm9200-udc";
                                reg = <0xfff78000 0x4000>;
-                                interrupts = <24 4 2>;
+                                interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>;
                                status = "disabled";
                        };
                        i2c0: i2c@fff88000 {
                                compatible = "atmel,at91sam9263-i2c";
                                reg = <0xfff88000 0x100>;
-                                interrupts = <13 4 6>;
+                                interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
                                #address-cells = <1>;
                                #size-cells = <0>;
                                status = "disabled";
@@ -460,7 +505,7 @@
                        mmc0: mmc@fff80000 {
                                compatible = "atmel,hsmci";
                                reg = <0xfff80000 0x600>;
-                                interrupts = <10 4 0>;
+                                interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
                                #address-cells = <1>;
                                #size-cells = <0>;
                                status = "disabled";
@@ -469,7 +514,7 @@
                        mmc1: mmc@fff84000 {
                                compatible = "atmel,hsmci";
                                reg = <0xfff84000 0x600>;
-                                interrupts = <11 4 0>;
+                                interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
                                #address-cells = <1>;
                                #size-cells = <0>;
                                status = "disabled";
@@ -486,7 +531,7 @@
                                #size-cells = <0>;
                                compatible = "atmel,at91rm9200-spi";
                                reg = <0xfffa4000 0x200>;
-                                interrupts = <14 4 3>;
+                                interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_spi0>;
                                status = "disabled";
@@ -497,7 +542,7 @@
                                #size-cells = <0>;
                                compatible = "atmel,at91rm9200-spi";
                                reg = <0xfffa8000 0x200>;
-                                interrupts = <15 4 3>;
+                                interrupts = <15 IRQ_TYPE_LEVEL_HIGH 3>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_spi1>;
                                status = "disabled";
@@ -515,8 +560,8 @@
                        atmel,nand-cmd-offset = <22>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_nand>;
-                        gpios = <&pioA 22 0
+                        gpios = <&pioA 22 GPIO_ACTIVE_HIGH
-                                 &pioD 15 0
+                                 &pioD 15 GPIO_ACTIVE_HIGH
                                 0
                                >;
                        status = "disabled";
@@ -525,15 +570,15 @@
                usb0: ohci@00a00000 {
                        compatible = "atmel,at91rm9200-ohci", "usb-ohci";
                        reg = <0x00a00000 0x100000>;
-                        interrupts = <29 4 2>;
+                        interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>;
                        status = "disabled";
                };
        };
        i2c@0 {
                compatible = "i2c-gpio";
-                gpios = <&pioB 4 0 /* sda */
+                gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */
-                         &pioB 5 0 /* scl */
+                         &pioB 5 GPIO_ACTIVE_HIGH /* scl */
                        >;
                i2c-gpio,sda-open-drain;
                i2c-gpio,scl-open-drain;
diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
index 3b82d91e7fcc..70f835b55c0b 100644
--- a/arch/arm/boot/dts/at91sam9263ek.dts
+++ b/arch/arm/boot/dts/at91sam9263ek.dts
@@ -6,7 +6,7 @@
 * Licensed under GPLv2 only
 */
 /dts-v1/;
-/include/ "at91sam9263.dtsi"
+#include "at91sam9263.dtsi"
 / {
        model = "Atmel at91sam9263ek";
@@ -51,7 +51,7 @@
                        };
                        usb1: gadget@fff78000 {
-                                atmel,vbus-gpio = <&pioA 25 0>;
+                                atmel,vbus-gpio = <&pioA 25 GPIO_ACTIVE_HIGH>;
                                status = "okay";
                        };
@@ -65,8 +65,8 @@
                                slot@0 {
                                        reg = <0>;
                                        bus-width = <4>;
-                                        cd-gpios = <&pioE 18 0>;
+                                        cd-gpios = <&pioE 18 GPIO_ACTIVE_HIGH>;
-                                        wp-gpios = <&pioE 19 0>;
+                                        wp-gpios = <&pioE 19 GPIO_ACTIVE_HIGH>;
                                };
                        };
@@ -74,8 +74,8 @@
                                mmc0 {
                                        pinctrl_board_mmc0: mmc0-board {
                                                atmel,pins =
-                                                        <5 18 0x0 0x5   /* PE18 gpio CD pin pull up and deglitch */
+                                                        <AT91_PIOE 18 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH    /* PE18 gpio CD pin pull up and deglitch */
-                                                         5 19 0x0 0x1>; /* PE19 gpio WP pin pull up */
+                                                         AT91_PIOE 19 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;   /* PE19 gpio WP pin pull up */
                                        };
                                };
                        };
@@ -89,6 +89,10 @@
                                        reg = <0>;
                                };
                        };
+                        watchdog@fffffd40 {
+                                status = "okay";
+                        };
                };
                nand0: nand@40000000 {
@@ -141,8 +145,8 @@
                usb0: ohci@00a00000 {
                        num-ports = <2>;
                        status = "okay";
-                        atmel,vbus-gpio = <&pioA 24 0
+                        atmel,vbus-gpio = <&pioA 24 GPIO_ACTIVE_HIGH
-                                           &pioA 21 0
+                                           &pioA 21 GPIO_ACTIVE_HIGH
                                          >;
                };
        };
@@ -152,13 +156,13 @@
                d3 {
                        label = "d3";
-                        gpios = <&pioB 7 0>;
+                        gpios = <&pioB 7 GPIO_ACTIVE_HIGH>;
                        linux,default-trigger = "heartbeat";
                };
                d2 {
                        label = "d2";
-                        gpios = <&pioC 29 1>;
+                        gpios = <&pioC 29 GPIO_ACTIVE_LOW>;
                        linux,default-trigger = "nand-disk";
                };
        };
@@ -168,14 +172,14 @@
                left_click {
                        label = "left_click";
-                        gpios = <&pioC 5 1>;
+                        gpios = <&pioC 5 GPIO_ACTIVE_LOW>;
                        linux,code = <272>;
                        gpio-key,wakeup;
                };
                right_click {
                        label = "right_click";
-                        gpios = <&pioC 4 1>;
+                        gpios = <&pioC 4 GPIO_ACTIVE_LOW>;
                        linux,code = <273>;
                        gpio-key,wakeup;
                };
diff --git a/arch/arm/boot/dts/at91sam9g15.dtsi b/arch/arm/boot/dts/at91sam9g15.dtsi
index 28467fd6bf96..cfd7044616d7 100644
--- a/arch/arm/boot/dts/at91sam9g15.dtsi
+++ b/arch/arm/boot/dts/at91sam9g15.dtsi
@@ -6,7 +6,7 @@
 * Licensed under GPLv2.
 */
-/include/ "at91sam9x5.dtsi"
+#include "at91sam9x5.dtsi"
 / {
        model = "Atmel AT91SAM9G15 SoC";
diff --git a/arch/arm/boot/dts/at91sam9g15ek.dts b/arch/arm/boot/dts/at91sam9g15ek.dts
index 5427b2dba87e..26b0444b0f96 100644
--- a/arch/arm/boot/dts/at91sam9g15ek.dts
+++ b/arch/arm/boot/dts/at91sam9g15ek.dts
@@ -7,8 +7,8 @@
 * Licensed under GPLv2 or later.
 */
 /dts-v1/;
-/include/ "at91sam9g15.dtsi"
+#include "at91sam9g15.dtsi"
-/include/ "at91sam9x5ek.dtsi"
+#include "at91sam9x5ek.dtsi"
 / {
        model = "Atmel AT91SAM9G15-EK";
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index 75ce6e760016..b8e79466014f 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -6,7 +6,7 @@
 * Licensed under GPLv2.
 */
-/include/ "at91sam9260.dtsi"
+#include "at91sam9260.dtsi"
 / {
        model = "Atmel AT91SAM9G20 family SoC";
diff --git a/arch/arm/boot/dts/at91sam9g20ek.dts b/arch/arm/boot/dts/at91sam9g20ek.dts
index e5324bf9d529..bbfd753112c9 100644
--- a/arch/arm/boot/dts/at91sam9g20ek.dts
+++ b/arch/arm/boot/dts/at91sam9g20ek.dts
@@ -6,7 +6,7 @@
 * Licensed under GPLv2.
 */
 /dts-v1/;
-/include/ "at91sam9g20ek_common.dtsi"
+#include "at91sam9g20ek_common.dtsi"
 / {
        model = "Atmel at91sam9g20ek";
@@ -17,13 +17,13 @@
                ds1 {
                        label = "ds1";
-                        gpios = <&pioA 9 0>;
+                        gpios = <&pioA 9 GPIO_ACTIVE_HIGH>;
                        linux,default-trigger = "heartbeat";
                };
                ds5 {
                        label = "ds5";
-                        gpios = <&pioA 6 1>;
+                        gpios = <&pioA 6 GPIO_ACTIVE_LOW>;
                };
        };
 };
diff --git a/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts b/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts
index 66467b113126..bdb799bad179 100644
--- a/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts
+++ b/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts
@@ -6,7 +6,7 @@
 * Licensed under GPLv2.
 */
 /dts-v1/;
-/include/ "at91sam9g20ek_common.dtsi"
+#include "at91sam9g20ek_common.dtsi"
 / {
        model = "Atmel at91sam9g20ek 2 mmc";
@@ -23,7 +23,7 @@
                                slot@0 {
                                        reg = <0>;
                                        bus-width = <4>;
-                                        cd-gpios = <&pioC 2 0>;
+                                        cd-gpios = <&pioC 2 GPIO_ACTIVE_HIGH>;
                                };
                        };
@@ -31,7 +31,7 @@
                                mmc0_slot0 {
                                        pinctrl_board_mmc0_slot0: mmc0_slot0-board {
                                                atmel,pins =
-                                                        <2 2 0x0 0x5>;  /* PC2 gpio CD pin pull up and deglitch */
+                                                        <AT91_PIOC 2 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;   /* PC2 gpio CD pin pull up and deglitch */
                                        };
                                };
                        };
@@ -43,13 +43,13 @@
                ds1 {
                        label = "ds1";
-                        gpios = <&pioB 9 0>;
+                        gpios = <&pioB 9 GPIO_ACTIVE_HIGH>;
                        linux,default-trigger = "heartbeat";
                };
                ds5 {
                        label = "ds5";
-                        gpios = <&pioB 8 1>;
+                        gpios = <&pioB 8 GPIO_ACTIVE_LOW>;
                };
        };
 };
diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
index 6a92c5baef8c..137354689ad0 100644
--- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
@@ -5,7 +5,7 @@
 *
 * Licensed under GPLv2.
 */
-/include/ "at91sam9g20.dtsi"
+#include "at91sam9g20.dtsi"
 / {
@@ -34,10 +34,17 @@
                                board {
                                        pinctrl_pck0_as_mck: pck0_as_mck {
                                                atmel,pins =
-                                                        <2 1 0x2 0x0>;  /* PC1 periph B */
+                                                        <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PC1 periph B */
                                        };
                                };
+                                mmc0_slot1 {
+                                        pinctrl_board_mmc0_slot1: mmc0_slot1-board {
+                                                atmel,pins =
+                                                        <AT91_PIOC 9 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;   /* PC9 gpio CD pin pull up and deglitch */
+                                        };
+                                };
                        };
                        dbgu: serial@fffff200 {
@@ -65,7 +72,7 @@
                        };
                        usb1: gadget@fffa4000 {
-                                atmel,vbus-gpio = <&pioC 5 0>;
+                                atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
                                status = "okay";
                        };
@@ -79,16 +86,7 @@
                                slot@1 {
                                        reg = <1>;
                                        bus-width = <4>;
-                                        cd-gpios = <&pioC 9 0>;
+                                        cd-gpios = <&pioC 9 GPIO_ACTIVE_HIGH>;
-                                };
-                        };
-                        pinctrl@fffff400 {
-                                mmc0_slot1 {
-                                        pinctrl_board_mmc0_slot1: mmc0_slot1-board {
-                                                atmel,pins =
-                                                        <2 9 0x0 0x5>;  /* PC9 gpio CD pin pull up and deglitch */
-                                        };
                                };
                        };
@@ -106,6 +104,10 @@
                                        reg = <1>;
                                };
                        };
+                        watchdog@fffffd40 {
+                                status = "okay";
+                        };
                };
                nand0: nand@40000000 {
@@ -180,14 +182,14 @@
                btn3 {
                        label = "Button 3";
-                        gpios = <&pioA 30 1>;
+                        gpios = <&pioA 30 GPIO_ACTIVE_LOW>;
                        linux,code = <0x103>;
                        gpio-key,wakeup;
                };
                btn4 {
                        label = "Button 4";
-                        gpios = <&pioA 31 1>;
+                        gpios = <&pioA 31 GPIO_ACTIVE_LOW>;
                        linux,code = <0x104>;
                        gpio-key,wakeup;
                };
diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi b/arch/arm/boot/dts/at91sam9g25.dtsi
index 5fd32df03f25..b4ec6fe53fc7 100644
--- a/arch/arm/boot/dts/at91sam9g25.dtsi
+++ b/arch/arm/boot/dts/at91sam9g25.dtsi
@@ -6,7 +6,7 @@
 * Licensed under GPLv2.
 */
-/include/ "at91sam9x5.dtsi"
+#include "at91sam9x5.dtsi"
 / {
        model = "Atmel AT91SAM9G25 SoC";
diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
index a1c511fecdc1..1e4c49c584d3 100644
--- a/arch/arm/boot/dts/at91sam9g25ek.dts
+++ b/arch/arm/boot/dts/at91sam9g25ek.dts
@@ -7,8 +7,8 @@
 * Licensed under GPLv2 or later.
 */
 /dts-v1/;
-/include/ "at91sam9g25.dtsi"
+#include "at91sam9g25.dtsi"
-/include/ "at91sam9x5ek.dtsi"
+#include "at91sam9x5ek.dtsi"
 / {
        model = "Atmel AT91SAM9G25-EK";
diff --git a/arch/arm/boot/dts/at91sam9g35.dtsi b/arch/arm/boot/dts/at91sam9g35.dtsi
index d6fa8af50724..bebf9f55614b 100644
--- a/arch/arm/boot/dts/at91sam9g35.dtsi
+++ b/arch/arm/boot/dts/at91sam9g35.dtsi
@@ -6,7 +6,7 @@
 * Licensed under GPLv2.
 */
-/include/ "at91sam9x5.dtsi"
+#include "at91sam9x5.dtsi"
 / {
        model = "Atmel AT91SAM9G35 SoC";
diff --git a/arch/arm/boot/dts/at91sam9g35ek.dts b/arch/arm/boot/dts/at91sam9g35ek.dts
index 6f58ab8d21f5..641a9bf89ed1 100644
--- a/arch/arm/boot/dts/at91sam9g35ek.dts
+++ b/arch/arm/boot/dts/at91sam9g35ek.dts
@@ -7,8 +7,8 @@
 * Licensed under GPLv2 or later.
 */
 /dts-v1/;
-/include/ "at91sam9g35.dtsi"
+#include "at91sam9g35.dtsi"
-/include/ "at91sam9x5ek.dtsi"
+#include "at91sam9x5ek.dtsi"
 / {
        model = "Atmel AT91SAM9G35-EK";
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index bf18a735c37d..c3e514837074 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -9,7 +9,11 @@
 * Licensed under GPLv2 or later.
 */
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
+#include <dt-bindings/dma/at91.h>
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
 / {
        model = "Atmel AT91SAM9G45 family SoC";
@@ -35,8 +39,12 @@
                ssc1 = &ssc1;
        };
        cpus {
-                cpu@0 {
+                #address-cells = <0>;
-                        compatible = "arm,arm926ejs";
+                #size-cells = <0>;
+                cpu {
+                        compatible = "arm,arm926ej-s";
+                        device_type = "cpu";
                };
        };
@@ -83,7 +91,7 @@
                        pit: timer@fffffd30 {
                                compatible = "atmel,at91sam9260-pit";
                                reg = <0xfffffd30 0xf>;
-                                interrupts = <1 4 7>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                        };
@@ -95,19 +103,19 @@
                        tcb0: timer@fff7c000 {
                                compatible = "atmel,at91rm9200-tcb";
                                reg = <0xfff7c000 0x100>;
-                                interrupts = <18 4 0>;
+                                interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
                        };
                        tcb1: timer@fffd4000 {
                                compatible = "atmel,at91rm9200-tcb";
                                reg = <0xfffd4000 0x100>;
-                                interrupts = <18 4 0>;
+                                interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
                        };
                        dma: dma-controller@ffffec00 {
                                compatible = "atmel,at91sam9g45-dma";
                                reg = <0xffffec00 0x200>;
-                                interrupts = <21 4 0>;
+                                interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
                                #dma-cells = <2>;
                        };
@@ -130,221 +138,297 @@
                                dbgu {
                                        pinctrl_dbgu: dbgu-0 {
                                                atmel,pins =
-                                                        <1 12 0x1 0x0   /* PB12 periph A */
+                                                        <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB12 periph A */
-                                                         1 13 0x1 0x0>; /* PB13 periph A */
+                                                         AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */
                                        };
                                };
                                usart0 {
                                        pinctrl_usart0: usart0-0 {
                                                atmel,pins =
-                                                        <1 19 0x1 0x1   /* PB19 periph A with pullup */
+                                                        <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PB19 periph A with pullup */
-                                                         1 18 0x1 0x0>; /* PB18 periph A */
+                                                         AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */
                                        };
                                        pinctrl_usart0_rts: usart0_rts-0 {
                                                atmel,pins =
-                                                        <1 17 0x2 0x0>; /* PB17 periph B */
+                                                        <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB17 periph B */
                                        };
                                        pinctrl_usart0_cts: usart0_cts-0 {
                                                atmel,pins =
-                                                        <1 15 0x2 0x0>; /* PB15 periph B */
+                                                        <AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B */
                                        };
                                };
                                uart1 {
                                        pinctrl_usart1: usart1-0 {
                                                atmel,pins =
-                                                        <1 4 0x1 0x1    /* PB4 periph A with pullup */
+                                                        <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB4 periph A with pullup */
-                                                         1 5 0x1 0x0>;  /* PB5 periph A */
+                                                         AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB5 periph A */
                                        };
                                        pinctrl_usart1_rts: usart1_rts-0 {
                                                atmel,pins =
-                                                        <3 16 0x1 0x0>; /* PD16 periph A */
+                                                        <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A */
                                        };
                                        pinctrl_usart1_cts: usart1_cts-0 {
                                                atmel,pins =
-                                                        <3 17 0x1 0x0>; /* PD17 periph A */
+                                                        <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD17 periph A */
                                        };
                                };
                                usart2 {
                                        pinctrl_usart2: usart2-0 {
                                                atmel,pins =
-                                                        <1 6 0x1 0x1    /* PB6 periph A with pullup */
+                                                        <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */
-                                                         1 7 0x1 0x0>;  /* PB7 periph A */
+                                                         AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB7 periph A */
                                        };
                                        pinctrl_usart2_rts: usart2_rts-0 {
                                                atmel,pins =
-                                                        <2 9 0x2 0x0>;  /* PC9 periph B */
+                                                        <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PC9 periph B */
                                        };
                                        pinctrl_usart2_cts: usart2_cts-0 {
                                                atmel,pins =
-                                                        <2 11 0x2 0x0>; /* PC11 periph B */
+                                                        <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC11 periph B */
                                        };
                                };
                                usart3 {
                                        pinctrl_usart3: usart3-0 {
                                                atmel,pins =
-                                                        <1 8 0x1 0x1    /* PB9 periph A with pullup */
+                                                        <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB9 periph A with pullup */
-                                                         1 9 0x1 0x0>;  /* PB8 periph A */
+                                                         AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB8 periph A */
                                        };
                                        pinctrl_usart3_rts: usart3_rts-0 {
                                                atmel,pins =
-                                                        <0 23 0x2 0x0>; /* PA23 periph B */
+                                                        <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B */
                                        };
                                        pinctrl_usart3_cts: usart3_cts-0 {
                                                atmel,pins =
-                                                        <0 24 0x2 0x0>; /* PA24 periph B */
+                                                        <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA24 periph B */
                                        };
                                };
                                nand {
                                        pinctrl_nand: nand-0 {
                                                atmel,pins =
-                                                        <2 8 0x0 0x1    /* PC8 gpio RDY pin pull_up*/
+                                                        <AT91_PIOC 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP      /* PC8 gpio RDY pin pull_up*/
-                                                         2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
+                                                         AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;   /* PC14 gpio enable pin pull_up */
                                        };
                                };
                                macb {
                                        pinctrl_macb_rmii: macb_rmii-0 {
                                                atmel,pins =
-                                                        <0 10 0x1 0x0   /* PA10 periph A */
+                                                        <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA10 periph A */
-                                                         0 11 0x1 0x0   /* PA11 periph A */
+                                                         AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA11 periph A */
-                                                         0 12 0x1 0x0   /* PA12 periph A */
+                                                         AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA12 periph A */
-                                                         0 13 0x1 0x0   /* PA13 periph A */
+                                                         AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA13 periph A */
-                                                         0 14 0x1 0x0   /* PA14 periph A */
+                                                         AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA14 periph A */
-                                                         0 15 0x1 0x0   /* PA15 periph A */
+                                                         AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA15 periph A */
-                                                         0 16 0x1 0x0   /* PA16 periph A */
+                                                         AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA16 periph A */
-                                                         0 17 0x1 0x0   /* PA17 periph A */
+                                                         AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA17 periph A */
-                                                         0 18 0x1 0x0   /* PA18 periph A */
+                                                         AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA18 periph A */
-                                                         0 19 0x1 0x0>; /* PA19 periph A */
+                                                         AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA19 periph A */
                                        };
                                        pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
                                                atmel,pins =
-                                                        <0 6 0x2 0x0    /* PA6 periph B */
+                                                        <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE    /* PA6 periph B */
-                                                         0 7 0x2 0x0    /* PA7 periph B */
+                                                         AT91_PIOA 7 AT91_PERIPH_B AT91_PINCTRL_NONE    /* PA7 periph B */
-                                                         0 8 0x2 0x0    /* PA8 periph B */
+                                                         AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE    /* PA8 periph B */
-                                                         0 9 0x2 0x0    /* PA9 periph B */
+                                                         AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE    /* PA9 periph B */
-                                                         0 27 0x2 0x0   /* PA27 periph B */
+                                                         AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA27 periph B */
-                                                         0 28 0x2 0x0   /* PA28 periph B */
+                                                         AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA28 periph B */
-                                                         0 29 0x2 0x0   /* PA29 periph B */
+                                                         AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA29 periph B */
-                                                         0 30 0x2 0x0>; /* PA30 periph B */
+                                                         AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */
                                        };
                                };
                                mmc0 {
                                        pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
                                                atmel,pins =
-                                                        <0 0 0x1 0x0    /* PA0 periph A */
+                                                        <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA0 periph A */
-                                                         0 1 0x1 0x1    /* PA1 periph A with pullup */
+                                                         AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
-                                                         0 2 0x1 0x1>;  /* PA2 periph A with pullup */
+                                                         AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;       /* PA2 periph A with pullup */
                                        };
                                        pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
                                                atmel,pins =
-                                                        <0 3 0x1 0x1    /* PA3 periph A with pullup */
+                                                        <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */
-                                                         0 4 0x1 0x1    /* PA4 periph A with pullup */
+                                                         AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */
-                                                         0 5 0x1 0x1>;  /* PA5 periph A with pullup */
+                                                         AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;       /* PA5 periph A with pullup */
                                        };
                                        pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
                                                atmel,pins =
-                                                        <0 6 0x1 0x1    /* PA6 periph A with pullup */
+                                                        <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */
-                                                         0 7 0x1 0x1    /* PA7 periph A with pullup */
+                                                         AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
-                                                         0 8 0x1 0x1    /* PA8 periph A with pullup */
+                                                         AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */
-                                                         0 9 0x1 0x1>;  /* PA9 periph A with pullup */
+                                                         AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;       /* PA9 periph A with pullup */
                                        };
                                };
                                mmc1 {
                                        pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
                                                atmel,pins =
-                                                        <0 31 0x1 0x0   /* PA31 periph A */
+                                                        <AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA31 periph A */
-                                                         0 22 0x1 0x1   /* PA22 periph A with pullup */
+                                                         AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA22 periph A with pullup */
-                                                         0 23 0x1 0x1>; /* PA23 periph A with pullup */
+                                                         AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA23 periph A with pullup */
                                        };
                                        pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
                                                atmel,pins =
-                                                        <0 24 0x1 0x1   /* PA24 periph A with pullup */
+                                                        <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA24 periph A with pullup */
-                                                         0 25 0x1 0x1   /* PA25 periph A with pullup */
+                                                         AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA25 periph A with pullup */
-                                                         0 26 0x1 0x1>; /* PA26 periph A with pullup */
+                                                         AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA26 periph A with pullup */
                                        };
                                        pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 {
                                                atmel,pins =
-                                                        <0 27 0x1 0x1   /* PA27 periph A with pullup */
+                                                        <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA27 periph A with pullup */
-                                                         0 28 0x1 0x1   /* PA28 periph A with pullup */
+                                                         AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA28 periph A with pullup */
-                                                         0 29 0x1 0x1   /* PA29 periph A with pullup */
+                                                         AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA29 periph A with pullup */
-                                                         0 20 0x1 0x1>; /* PA30 periph A with pullup */
+                                                         AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA30 periph A with pullup */
                                        };
                                };
                                ssc0 {
                                        pinctrl_ssc0_tx: ssc0_tx-0 {
                                                atmel,pins =
-                                                        <3 0 0x1 0x0    /* PD0 periph A */
+                                                        <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PD0 periph A */
-                                                         3 1 0x1 0x0    /* PD1 periph A */
+                                                         AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PD1 periph A */
-                                                         3 2 0x1 0x0>;  /* PD2 periph A */
+                                                         AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PD2 periph A */
                                        };
                                        pinctrl_ssc0_rx: ssc0_rx-0 {
                                                atmel,pins =
-                                                        <3 3 0x1 0x0    /* PD3 periph A */
+                                                        <AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PD3 periph A */
-                                                         3 4 0x1 0x0    /* PD4 periph A */
+                                                         AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PD4 periph A */
-                                                         3 5 0x1 0x0>;  /* PD5 periph A */
+                                                         AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PD5 periph A */
                                        };
                                };
                                ssc1 {
                                        pinctrl_ssc1_tx: ssc1_tx-0 {
                                                atmel,pins =
-                                                        <3 10 0x1 0x0   /* PD10 periph A */
+                                                        <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD10 periph A */
-                                                         3 11 0x1 0x0   /* PD11 periph A */
+                                                         AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD11 periph A */
-                                                         3 12 0x1 0x0>; /* PD12 periph A */
+                                                         AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A */
                                        };
                                        pinctrl_ssc1_rx: ssc1_rx-0 {
                                                atmel,pins =
-                                                        <3 13 0x1 0x0   /* PD13 periph A */
+                                                        <AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD13 periph A */
-                                                         3 14 0x1 0x0   /* PD14 periph A */
+                                                         AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD14 periph A */
-                                                         3 15 0x1 0x0>; /* PD15 periph A */
+                                                         AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD15 periph A */
                                        };
                                };
                                spi0 {
                                        pinctrl_spi0: spi0-0 {
                                                atmel,pins =
-                                                        <1 0 0x1 0x0    /* PB0 periph A SPI0_MISO pin */
+                                                        <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB0 periph A SPI0_MISO pin */
-                                                         1 1 0x1 0x0    /* PB1 periph A SPI0_MOSI pin */
+                                                         AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB1 periph A SPI0_MOSI pin */
-                                                         1 2 0x1 0x0>;  /* PB2 periph A SPI0_SPCK pin */
+                                                         AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB2 periph A SPI0_SPCK pin */
                                        };
                                };
                                spi1 {
                                        pinctrl_spi1: spi1-0 {
                                                atmel,pins =
-                                                        <1 14 0x1 0x0   /* PB14 periph A SPI1_MISO pin */
+                                                        <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB14 periph A SPI1_MISO pin */
-                                                         1 15 0x1 0x0   /* PB15 periph A SPI1_MOSI pin */
+                                                         AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB15 periph A SPI1_MOSI pin */
-                                                         1 16 0x1 0x0>; /* PB16 periph A SPI1_SPCK pin */
+                                                         AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB16 periph A SPI1_SPCK pin */
+                                        };
+                                };
+                                tcb0 {
+                                        pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+                                                atmel,pins = <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+                                                atmel,pins = <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+                                                atmel,pins = <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+                                                atmel,pins = <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+                                                atmel,pins = <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+                                                atmel,pins = <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+                                                atmel,pins = <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+                                                atmel,pins = <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+                                                atmel,pins = <AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                };
+                                tcb1 {
+                                        pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
+                                                atmel,pins = <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
+                                                atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
+                                                atmel,pins = <AT91_PIOD 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
+                                                atmel,pins = <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
+                                                atmel,pins = <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
+                                                atmel,pins = <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
+                                                atmel,pins = <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
+                                                atmel,pins = <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
+                                                atmel,pins = <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
                                        };
                                };
                                pioA: gpio@fffff200 {
                                        compatible = "atmel,at91rm9200-gpio";
                                        reg = <0xfffff200 0x200>;
-                                        interrupts = <2 4 1>;
+                                        interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
                                        #gpio-cells = <2>;
                                        gpio-controller;
                                        interrupt-controller;
@@ -354,7 +438,7 @@
                                pioB: gpio@fffff400 {
                                        compatible = "atmel,at91rm9200-gpio";
                                        reg = <0xfffff400 0x200>;
-                                        interrupts = <3 4 1>;
+                                        interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
                                        #gpio-cells = <2>;
                                        gpio-controller;
                                        interrupt-controller;
@@ -364,7 +448,7 @@
                                pioC: gpio@fffff600 {
                                        compatible = "atmel,at91rm9200-gpio";
                                        reg = <0xfffff600 0x200>;
-                                        interrupts = <4 4 1>;
+                                        interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
                                        #gpio-cells = <2>;
                                        gpio-controller;
                                        interrupt-controller;
@@ -374,7 +458,7 @@
                                pioD: gpio@fffff800 {
                                        compatible = "atmel,at91rm9200-gpio";
                                        reg = <0xfffff800 0x200>;
-                                        interrupts = <5 4 1>;
+                                        interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
                                        #gpio-cells = <2>;
                                        gpio-controller;
                                        interrupt-controller;
@@ -384,7 +468,7 @@
                                pioE: gpio@fffffa00 {
                                        compatible = "atmel,at91rm9200-gpio";
                                        reg = <0xfffffa00 0x200>;
-                                        interrupts = <5 4 1>;
+                                        interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
                                        #gpio-cells = <2>;
                                        gpio-controller;
                                        interrupt-controller;
@@ -395,7 +479,7 @@
                        dbgu: serial@ffffee00 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xffffee00 0x200>;
-                                interrupts = <1 4 7>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_dbgu>;
                                status = "disabled";
@@ -404,7 +488,7 @@
                        usart0: serial@fff8c000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xfff8c000 0x200>;
-                                interrupts = <7 4 5>;
+                                interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
                                pinctrl-names = "default";
@@ -415,7 +499,7 @@
                        usart1: serial@fff90000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xfff90000 0x200>;
-                                interrupts = <8 4 5>;
+                                interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
                                pinctrl-names = "default";
@@ -426,7 +510,7 @@
                        usart2: serial@fff94000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xfff94000 0x200>;
-                                interrupts = <9 4 5>;
+                                interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
                                pinctrl-names = "default";
@@ -437,7 +521,7 @@
                        usart3: serial@fff98000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xfff98000 0x200>;
-                                interrupts = <10 4 5>;
+                                interrupts = <10 IRQ_TYPE_LEVEL_HIGH 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
                                pinctrl-names = "default";
@@ -448,7 +532,7 @@
                        macb0: ethernet@fffbc000 {
                                compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                reg = <0xfffbc000 0x100>;
-                                interrupts = <25 4 3>;
+                                interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_macb_rmii>;
                                status = "disabled";
@@ -457,7 +541,7 @@
                        i2c0: i2c@fff84000 {
                                compatible = "atmel,at91sam9g10-i2c";
                                reg = <0xfff84000 0x100>;
-                                interrupts = <12 4 6>;
+                                interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
                                #address-cells = <1>;
                                #size-cells = <0>;
                                status = "disabled";
@@ -466,7 +550,7 @@
                        i2c1: i2c@fff88000 {
                                compatible = "atmel,at91sam9g10-i2c";
                                reg = <0xfff88000 0x100>;
-                                interrupts = <13 4 6>;
+                                interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
                                #address-cells = <1>;
                                #size-cells = <0>;
                                status = "disabled";
@@ -475,7 +559,7 @@
                        ssc0: ssc@fff9c000 {
                                compatible = "atmel,at91sam9g45-ssc";
                                reg = <0xfff9c000 0x4000>;
-                                interrupts = <16 4 5>;
+                                interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
                                status = "disabled";
@@ -484,7 +568,7 @@
                        ssc1: ssc@fffa0000 {
                                compatible = "atmel,at91sam9g45-ssc";
                                reg = <0xfffa0000 0x4000>;
-                                interrupts = <17 4 5>;
+                                interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
                                status = "disabled";
@@ -493,7 +577,7 @@
                        adc0: adc@fffb0000 {
                                compatible = "atmel,at91sam9260-adc";
                                reg = <0xfffb0000 0x100>;
-                                interrupts = <20 4 0>;
+                                interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
                                atmel,adc-use-external-triggers;
                                atmel,adc-channels-used = <0xff>;
                                atmel,adc-vref = <3300>;
@@ -533,8 +617,8 @@
                        mmc0: mmc@fff80000 {
                                compatible = "atmel,hsmci";
                                reg = <0xfff80000 0x600>;
-                                interrupts = <11 4 0>;
+                                interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
-                                dmas = <&dma 1 0>;
+                                dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
                                dma-names = "rxtx";
                                #address-cells = <1>;
                                #size-cells = <0>;
@@ -544,8 +628,8 @@
                        mmc1: mmc@fffd0000 {
                                compatible = "atmel,hsmci";
                                reg = <0xfffd0000 0x600>;
-                                interrupts = <29 4 0>;
+                                interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>;
-                                dmas = <&dma 1 13>;
+                                dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>;
                                dma-names = "rxtx";
                                #address-cells = <1>;
                                #size-cells = <0>;
@@ -579,6 +663,68 @@
                                pinctrl-0 = <&pinctrl_spi1>;
                                status = "disabled";
                        };
+                        usb2: gadget@fff78000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "atmel,at91sam9rl-udc";
+                                reg = <0x00600000 0x80000
+                                       0xfff78000 0x400>;
+                                interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
+                                status = "disabled";
+                                ep0 {
+                                        reg = <0>;
+                                        atmel,fifo-size = <64>;
+                                        atmel,nb-banks = <1>;
+                                };
+                                ep1 {
+                                        reg = <1>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <2>;
+                                        atmel,can-dma;
+                                        atmel,can-isoc;
+                                };
+                                ep2 {
+                                        reg = <2>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <2>;
+                                        atmel,can-dma;
+                                        atmel,can-isoc;
+                                };
+                                ep3 {
+                                        reg = <3>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <3>;
+                                        atmel,can-dma;
+                                };
+                                ep4 {
+                                        reg = <4>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <3>;
+                                        atmel,can-dma;
+                                };
+                                ep5 {
+                                        reg = <5>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <3>;
+                                        atmel,can-dma;
+                                        atmel,can-isoc;
+                                };
+                                ep6 {
+                                        reg = <6>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <3>;
+                                        atmel,can-dma;
+                                        atmel,can-isoc;
+                                };
+                        };
                };
                nand0: nand@40000000 {
@@ -592,8 +738,8 @@
                        atmel,nand-cmd-offset = <22>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_nand>;
-                        gpios = <&pioC 8 0
+                        gpios = <&pioC 8 GPIO_ACTIVE_HIGH
-                                 &pioC 14 0
+                                 &pioC 14 GPIO_ACTIVE_HIGH
                                 0
                                >;
                        status = "disabled";
@@ -602,22 +748,22 @@
                usb0: ohci@00700000 {
                        compatible = "atmel,at91rm9200-ohci", "usb-ohci";
                        reg = <0x00700000 0x100000>;
-                        interrupts = <22 4 2>;
+                        interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
                        status = "disabled";
                };
                usb1: ehci@00800000 {
                        compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
                        reg = <0x00800000 0x100000>;
-                        interrupts = <22 4 2>;
+                        interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
                        status = "disabled";
                };
        };
        i2c@0 {
                compatible = "i2c-gpio";
-                gpios = <&pioA 20 0 /* sda */
+                gpios = <&pioA 20 GPIO_ACTIVE_HIGH /* sda */
-                         &pioA 21 0 /* scl */
+                         &pioA 21 GPIO_ACTIVE_HIGH /* scl */
                        >;
                i2c-gpio,sda-open-drain;
                i2c-gpio,scl-open-drain;
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index 51d9251b5bbe..a4b00e5c61c0 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -7,7 +7,7 @@
 * Licensed under GPLv2 or later.
 */
 /dts-v1/;
-/include/ "at91sam9g45.dtsi"
+#include "at91sam9g45.dtsi"
 / {
        model = "Atmel AT91SAM9M10G45-EK";
@@ -59,6 +59,10 @@
                                status = "okay";
                        };
+                        watchdog@fffffd40 {
+                                status = "okay";
+                        };
                        mmc0: mmc@fff80000 {
                                pinctrl-0 = <
                                        &pinctrl_board_mmc0
@@ -68,7 +72,7 @@
                                slot@0 {
                                        reg = <0>;
                                        bus-width = <4>;
-                                        cd-gpios = <&pioD 10 0>;
+                                        cd-gpios = <&pioD 10 GPIO_ACTIVE_HIGH>;
                                };
                        };
@@ -81,8 +85,8 @@
                                slot@0 {
                                        reg = <0>;
                                        bus-width = <4>;
-                                        cd-gpios = <&pioD 11 0>;
+                                        cd-gpios = <&pioD 11 GPIO_ACTIVE_HIGH>;
-                                        wp-gpios = <&pioD 29 0>;
+                                        wp-gpios = <&pioD 29 GPIO_ACTIVE_HIGH>;
                                };
                        };
@@ -90,15 +94,15 @@
                                mmc0 {
                                        pinctrl_board_mmc0: mmc0-board {
                                                atmel,pins =
-                                                        <3 10 0x0 0x5>; /* PD10 gpio CD pin pull up and deglitch */
+                                                        <AT91_PIOD 10 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;  /* PD10 gpio CD pin pull up and deglitch */
                                        };
                                };
                                mmc1 {
                                        pinctrl_board_mmc1: mmc1-board {
                                                atmel,pins =
-                                                        <3 11 0x0 0x5   /* PD11 gpio CD pin pull up and deglitch */
+                                                        <AT91_PIOD 11 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH    /* PD11 gpio CD pin pull up and deglitch */
-                                                         3 29 0x0 0x1>; /* PD29 gpio WP pin pull up */
+                                                         AT91_PIOD 29 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;   /* PD29 gpio WP pin pull up */
                                        };
                                };
                        };
@@ -112,6 +116,11 @@
                                        reg = <0>;
                                };
                        };
+                        usb2: gadget@fff78000 {
+                                atmel,vbus-gpio = <&pioB 19 GPIO_ACTIVE_HIGH>;
+                                status = "okay";
+                        };
                };
                nand0: nand@40000000 {
@@ -139,8 +148,8 @@
                usb0: ohci@00700000 {
                        status = "okay";
                        num-ports = <2>;
-                        atmel,vbus-gpio = <&pioD 1 1
+                        atmel,vbus-gpio = <&pioD 1 GPIO_ACTIVE_LOW
-                                           &pioD 3 1>;
+                                           &pioD 3 GPIO_ACTIVE_LOW>;
                };
                usb1: ehci@00800000 {
@@ -153,19 +162,19 @@
                d8 {
                        label = "d8";
-                        gpios = <&pioD 30 0>;
+                        gpios = <&pioD 30 GPIO_ACTIVE_HIGH>;
                        linux,default-trigger = "heartbeat";
                };
                d6 {
                        label = "d6";
-                        gpios = <&pioD 0 1>;
+                        gpios = <&pioD 0 GPIO_ACTIVE_LOW>;
                        linux,default-trigger = "nand-disk";
                };
                d7 {
                        label = "d7";
-                        gpios = <&pioD 31 1>;
+                        gpios = <&pioD 31 GPIO_ACTIVE_LOW>;
                        linux,default-trigger = "mmc0";
                };
        };
@@ -175,45 +184,45 @@
                left_click {
                        label = "left_click";
-                        gpios = <&pioB 6 1>;
+                        gpios = <&pioB 6 GPIO_ACTIVE_LOW>;
                        linux,code = <272>;
                        gpio-key,wakeup;
                };
                right_click {
                        label = "right_click";
-                        gpios = <&pioB 7 1>;
+                        gpios = <&pioB 7 GPIO_ACTIVE_LOW>;
                        linux,code = <273>;
                        gpio-key,wakeup;
                };
                left {
                        label = "Joystick Left";
-                        gpios = <&pioB 14 1>;
+                        gpios = <&pioB 14 GPIO_ACTIVE_LOW>;
                        linux,code = <105>;
                };
                right {
                        label = "Joystick Right";
-                        gpios = <&pioB 15 1>;
+                        gpios = <&pioB 15 GPIO_ACTIVE_LOW>;
                        linux,code = <106>;
                };
                up {
                        label = "Joystick Up";
-                        gpios = <&pioB 16 1>;
+                        gpios = <&pioB 16 GPIO_ACTIVE_LOW>;
                        linux,code = <103>;
                };
                down {
                        label = "Joystick Down";
-                        gpios = <&pioB 17 1>;
+                        gpios = <&pioB 17 GPIO_ACTIVE_LOW>;
                        linux,code = <108>;
                };
                enter {
                        label = "Joystick Press";
-                        gpios = <&pioB 18 1>;
+                        gpios = <&pioB 18 GPIO_ACTIVE_LOW>;
                        linux,code = <28>;
                };
        };
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 8d25f889928e..bb7f564b3a55 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -7,7 +7,11 @@
 * Licensed under GPLv2 or later.
 */
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
+#include <dt-bindings/dma/at91.h>
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
 / {
        model = "Atmel AT91SAM9N12 SoC";
@@ -31,8 +35,12 @@
                ssc0 = &ssc0;
        };
        cpus {
-                cpu@0 {
+                #address-cells = <0>;
-                        compatible = "arm,arm926ejs";
+                #size-cells = <0>;
+                cpu {
+                        compatible = "arm,arm926ej-s";
+                        device_type = "cpu";
                };
        };
@@ -78,7 +86,7 @@
                        pit: timer@fffffe30 {
                                compatible = "atmel,at91sam9260-pit";
                                reg = <0xfffffe30 0xf>;
-                                interrupts = <1 4 7>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                        };
                        shdwc@fffffe10 {
@@ -89,8 +97,8 @@
                        mmc0: mmc@f0008000 {
                                compatible = "atmel,hsmci";
                                reg = <0xf0008000 0x600>;
-                                interrupts = <12 4 0>;
+                                interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
-                                dmas = <&dma 1 0>;
+                                dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
                                dma-names = "rxtx";
                                #address-cells = <1>;
                                #size-cells = <0>;
@@ -100,19 +108,19 @@
                        tcb0: timer@f8008000 {
                                compatible = "atmel,at91sam9x5-tcb";
                                reg = <0xf8008000 0x100>;
-                                interrupts = <17 4 0>;
+                                interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
                        };
                        tcb1: timer@f800c000 {
                                compatible = "atmel,at91sam9x5-tcb";
                                reg = <0xf800c000 0x100>;
-                                interrupts = <17 4 0>;
+                                interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
                        };
                        dma: dma-controller@ffffec00 {
                                compatible = "atmel,at91sam9g45-dma";
                                reg = <0xffffec00 0x200>;
-                                interrupts = <20 4 0>;
+                                interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
                                #dma-cells = <2>;
                        };
@@ -134,159 +142,235 @@
                                dbgu {
                                        pinctrl_dbgu: dbgu-0 {
                                                atmel,pins =
-                                                        <0 9 0x1 0x0    /* PA9 periph A */
+                                                        <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA9 periph A */
-                                                         0 10 0x1 0x1>; /* PA10 periph with pullup */
+                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA10 periph with pullup */
                                        };
                                };
                                usart0 {
                                        pinctrl_usart0: usart0-0 {
                                                atmel,pins =
-                                                        <0 1 0x1 0x1    /* PA1 periph A with pullup */
+                                                        <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
-                                                         0 0 0x1 0x0>;  /* PA0 periph A */
+                                                         AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA0 periph A */
                                        };
                                        pinctrl_usart0_rts: usart0_rts-0 {
                                                atmel,pins =
-                                                        <0 2 0x1 0x0>;  /* PA2 periph A */
+                                                        <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA2 periph A */
                                        };
                                        pinctrl_usart0_cts: usart0_cts-0 {
                                                atmel,pins =
-                                                        <0 3 0x1 0x0>;  /* PA3 periph A */
+                                                        <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA3 periph A */
                                        };
                                };
                                usart1 {
                                        pinctrl_usart1: usart1-0 {
                                                atmel,pins =
-                                                        <0 6 0x1 0x1    /* PA6 periph A with pullup */
+                                                        <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */
-                                                         0 5 0x1 0x0>;  /* PA5 periph A */
+                                                         AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA5 periph A */
                                        };
                                };
                                usart2 {
                                        pinctrl_usart2: usart2-0 {
                                                atmel,pins =
-                                                        <0 8 0x1 0x1    /* PA8 periph A with pullup */
+                                                        <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */
-                                                         0 7 0x1 0x0>;  /* PA7 periph A */
+                                                         AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA7 periph A */
                                        };
                                        pinctrl_usart2_rts: usart2_rts-0 {
                                                atmel,pins =
-                                                        <1 0 0x2 0x0>;  /* PB0 periph B */
+                                                        <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PB0 periph B */
                                        };
                                        pinctrl_usart2_cts: usart2_cts-0 {
                                                atmel,pins =
-                                                        <1 1 0x2 0x0>;  /* PB1 periph B */
+                                                        <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PB1 periph B */
                                        };
                                };
                                usart3 {
                                        pinctrl_usart3: usart3-0 {
                                                atmel,pins =
-                                                        <2 23 0x2 0x1   /* PC23 periph B with pullup */
+                                                        <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* PC23 periph B with pullup */
-                                                         2 22 0x2 0x0>; /* PC22 periph B */
+                                                         AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC22 periph B */
                                        };
                                        pinctrl_usart3_rts: usart3_rts-0 {
                                                atmel,pins =
-                                                        <2 24 0x2 0x0>; /* PC24 periph B */
+                                                        <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */
                                        };
                                        pinctrl_usart3_cts: usart3_cts-0 {
                                                atmel,pins =
-                                                        <2 25 0x2 0x0>; /* PC25 periph B */
+                                                        <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */
                                        };
                                };
                                uart0 {
                                        pinctrl_uart0: uart0-0 {
                                                atmel,pins =
-                                                        <2 9 0x3 0x1    /* PC9 periph C with pullup */
+                                                        <AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC9 periph C with pullup */
-                                                         2 8 0x3 0x0>;  /* PC8 periph C */
+                                                         AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE>;  /* PC8 periph C */
                                        };
                                };
                                uart1 {
                                        pinctrl_uart1: uart1-0 {
                                                atmel,pins =
-                                                        <2 16 0x3 0x1   /* PC17 periph C with pullup */
+                                                        <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_PULL_UP        /* PC17 periph C with pullup */
-                                                         2 17 0x3 0x0>; /* PC16 periph C */
+                                                         AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC16 periph C */
                                        };
                                };
                                nand {
                                        pinctrl_nand: nand-0 {
                                                atmel,pins =
-                                                        <3 5 0x0 0x1    /* PD5 gpio RDY pin pull_up*/
+                                                        <AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP      /* PD5 gpio RDY pin pull_up*/
-                                                         3 4 0x0 0x1>;  /* PD4 gpio enable pin pull_up */
+                                                         AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;    /* PD4 gpio enable pin pull_up */
                                        };
                                };
                                mmc0 {
                                        pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
                                                atmel,pins =
-                                                        <0 17 0x1 0x0   /* PA17 periph A */
+                                                        <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA17 periph A */
-                                                         0 16 0x1 0x1   /* PA16 periph A with pullup */
+                                                         AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA16 periph A with pullup */
-                                                         0 15 0x1 0x1>; /* PA15 periph A with pullup */
+                                                         AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA15 periph A with pullup */
                                        };
                                        pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
                                                atmel,pins =
-                                                        <0 18 0x1 0x1   /* PA18 periph A with pullup */
+                                                        <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA18 periph A with pullup */
-                                                         0 19 0x1 0x1   /* PA19 periph A with pullup */
+                                                         AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA19 periph A with pullup */
-                                                         0 20 0x1 0x1>; /* PA20 periph A with pullup */
+                                                         AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA20 periph A with pullup */
                                        };
                                        pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
                                                atmel,pins =
-                                                        <0 11 0x2 0x1   /* PA11 periph B with pullup */
+                                                        <AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* PA11 periph B with pullup */
-                                                         0 12 0x2 0x1   /* PA12 periph B with pullup */
+                                                         AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* PA12 periph B with pullup */
-                                                         0 13 0x2 0x1   /* PA13 periph B with pullup */
+                                                         AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* PA13 periph B with pullup */
-                                                         0 14 0x2 0x1>; /* PA14 periph B with pullup */
+                                                         AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;      /* PA14 periph B with pullup */
                                        };
                                };
                                ssc0 {
                                        pinctrl_ssc0_tx: ssc0_tx-0 {
                                                atmel,pins =
-                                                        <0 24 0x2 0x0   /* PA24 periph B */
+                                                        <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA24 periph B */
-                                                         0 25 0x2 0x0   /* PA25 periph B */
+                                                         AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA25 periph B */
-                                                         0 26 0x2 0x0>; /* PA26 periph B */
+                                                         AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */
                                        };
                                        pinctrl_ssc0_rx: ssc0_rx-0 {
                                                atmel,pins =
-                                                        <0 27 0x2 0x0   /* PA27 periph B */
+                                                        <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA27 periph B */
-                                                         0 28 0x2 0x0   /* PA28 periph B */
+                                                         AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA28 periph B */
-                                                         0 29 0x2 0x0>; /* PA29 periph B */
+                                                         AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */
                                        };
                                };
                                spi0 {
                                        pinctrl_spi0: spi0-0 {
                                                atmel,pins =
-                                                        <0 11 0x1 0x0   /* PA11 periph A SPI0_MISO pin */
+                                                        <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA11 periph A SPI0_MISO pin */
-                                                         0 12 0x1 0x0   /* PA12 periph A SPI0_MOSI pin */
+                                                         AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA12 periph A SPI0_MOSI pin */
-                                                         0 13 0x1 0x0>; /* PA13 periph A SPI0_SPCK pin */
+                                                         AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */
                                        };
                                };
                                spi1 {
                                        pinctrl_spi1: spi1-0 {
                                                atmel,pins =
-                                                        <0 21 0x2 0x0   /* PA21 periph B SPI1_MISO pin */
+                                                        <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA21 periph B SPI1_MISO pin */
-                                                         0 22 0x2 0x0   /* PA22 periph B SPI1_MOSI pin */
+                                                         AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA22 periph B SPI1_MOSI pin */
-                                                         0 23 0x2 0x0>; /* PA23 periph B SPI1_SPCK pin */
+                                                         AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */
+                                        };
+                                };
+                                tcb0 {
+                                        pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+                                                atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+                                                atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+                                                atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+                                                atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+                                                atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+                                                atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+                                                atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+                                                atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+                                                atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                };
+                                tcb1 {
+                                        pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
+                                                atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
+                                                atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
+                                                atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
+                                                atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
+                                                atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
+                                                atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
+                                                atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
+                                                atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
+                                                atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
                                        };
                                };
                                pioA: gpio@fffff400 {
                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                        reg = <0xfffff400 0x200>;
-                                        interrupts = <2 4 1>;
+                                        interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
                                        #gpio-cells = <2>;
                                        gpio-controller;
                                        interrupt-controller;
@@ -296,7 +380,7 @@
                                pioB: gpio@fffff600 {
                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                        reg = <0xfffff600 0x200>;
-                                        interrupts = <2 4 1>;
+                                        interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
                                        #gpio-cells = <2>;
                                        gpio-controller;
                                        interrupt-controller;
@@ -306,7 +390,7 @@
                                pioC: gpio@fffff800 {
                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                        reg = <0xfffff800 0x200>;
-                                        interrupts = <3 4 1>;
+                                        interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
                                        #gpio-cells = <2>;
                                        gpio-controller;
                                        interrupt-controller;
@@ -316,7 +400,7 @@
                                pioD: gpio@fffffa00 {
                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                        reg = <0xfffffa00 0x200>;
-                                        interrupts = <3 4 1>;
+                                        interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
                                        #gpio-cells = <2>;
                                        gpio-controller;
                                        interrupt-controller;
@@ -327,7 +411,7 @@
                        dbgu: serial@fffff200 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xfffff200 0x200>;
-                                interrupts = <1 4 7>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_dbgu>;
                                status = "disabled";
@@ -336,7 +420,7 @@
                        ssc0: ssc@f0010000 {
                                compatible = "atmel,at91sam9g45-ssc";
                                reg = <0xf0010000 0x4000>;
-                                interrupts = <28 4 5>;
+                                interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
                                status = "disabled";
@@ -345,7 +429,7 @@
                        usart0: serial@f801c000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xf801c000 0x4000>;
-                                interrupts = <5 4 5>;
+                                interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_usart0>;
                                status = "disabled";
@@ -354,7 +438,7 @@
                        usart1: serial@f8020000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xf8020000 0x4000>;
-                                interrupts = <6 4 5>;
+                                interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_usart1>;
                                status = "disabled";
@@ -363,7 +447,7 @@
                        usart2: serial@f8024000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xf8024000 0x4000>;
-                                interrupts = <7 4 5>;
+                                interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_usart2>;
                                status = "disabled";
@@ -372,7 +456,7 @@
                        usart3: serial@f8028000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xf8028000 0x4000>;
-                                interrupts = <8 4 5>;
+                                interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_usart3>;
                                status = "disabled";
@@ -381,9 +465,9 @@
                        i2c0: i2c@f8010000 {
                                compatible = "atmel,at91sam9x5-i2c";
                                reg = <0xf8010000 0x100>;
-                                interrupts = <9 4 6>;
+                                interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>;
-                                dmas = <&dma 1 13>,
+                                dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>,
-                                       <&dma 1 14>;
+                                       <&dma 1 AT91_DMA_CFG_PER_ID(14)>;
                                dma-names = "tx", "rx";
                                #address-cells = <1>;
                                #size-cells = <0>;
@@ -393,9 +477,9 @@
                        i2c1: i2c@f8014000 {
                                compatible = "atmel,at91sam9x5-i2c";
                                reg = <0xf8014000 0x100>;
-                                interrupts = <10 4 6>;
+                                interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>;
-                                dmas = <&dma 1 15>,
+                                dmas = <&dma 1 AT91_DMA_CFG_PER_ID(15)>,
-                                       <&dma 1 16>;
+                                       <&dma 1 AT91_DMA_CFG_PER_ID(16)>;
                                dma-names = "tx", "rx";
                                #address-cells = <1>;
                                #size-cells = <0>;
@@ -407,7 +491,10 @@
                                #size-cells = <0>;
                                compatible = "atmel,at91rm9200-spi";
                                reg = <0xf0000000 0x100>;
-                                interrupts = <13 4 3>;
+                                interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
+                                dmas = <&dma 1 AT91_DMA_CFG_PER_ID(1)>,
+                                       <&dma 1 AT91_DMA_CFG_PER_ID(2)>;
+                                dma-names = "tx", "rx";
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_spi0>;
                                status = "disabled";
@@ -418,11 +505,20 @@
                                #size-cells = <0>;
                                compatible = "atmel,at91rm9200-spi";
                                reg = <0xf0004000 0x100>;
-                                interrupts = <14 4 3>;
+                                interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
+                                dmas = <&dma 1 AT91_DMA_CFG_PER_ID(3)>,
+                                       <&dma 1 AT91_DMA_CFG_PER_ID(4)>;
+                                dma-names = "tx", "rx";
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_spi1>;
                                status = "disabled";
                        };
+                        watchdog@fffffe40 {
+                                compatible = "atmel,at91sam9260-wdt";
+                                reg = <0xfffffe40 0x10>;
+                                status = "disabled";
+                        };
                };
                nand0: nand@40000000 {
@@ -439,8 +535,8 @@
                        atmel,nand-cmd-offset = <22>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_nand>;
-                        gpios = <&pioD 5 0
+                        gpios = <&pioD 5 GPIO_ACTIVE_HIGH
-                                 &pioD 4 0
+                                 &pioD 4 GPIO_ACTIVE_HIGH
                                 0
                                >;
                        status = "disabled";
@@ -449,15 +545,15 @@
                usb0: ohci@00500000 {
                        compatible = "atmel,at91rm9200-ohci", "usb-ohci";
                        reg = <0x00500000 0x00100000>;
-                        interrupts = <22 4 2>;
+                        interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
                        status = "disabled";
                };
        };
        i2c@0 {
                compatible = "i2c-gpio";
-                gpios = <&pioA 30 0 /* sda */
+                gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */
-                         &pioA 31 0 /* scl */
+                         &pioA 31 GPIO_ACTIVE_HIGH /* scl */
                        >;
                i2c-gpio,sda-open-drain;
                i2c-gpio,scl-open-drain;
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index d30e48bd1e9d..d59b70c6a6a0 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -7,7 +7,7 @@
 * Licensed under GPLv2 or later.
 */
 /dts-v1/;
-/include/ "at91sam9n12.dtsi"
+#include "at91sam9n12.dtsi"
 / {
        model = "Atmel AT91SAM9N12-EK";
@@ -55,7 +55,7 @@
                                slot@0 {
                                        reg = <0>;
                                        bus-width = <4>;
-                                        cd-gpios = <&pioA 7 0>;
+                                        cd-gpios = <&pioA 7 GPIO_ACTIVE_HIGH>;
                                };
                        };
@@ -63,7 +63,7 @@
                                mmc0 {
                                        pinctrl_board_mmc0: mmc0-board {
                                                atmel,pins =
-                                                        <0 7 0x0 0x5>;  /* PA7 gpio CD pin pull up and deglitch */
+                                                        <AT91_PIOA 7 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;   /* PA7 gpio CD pin pull up and deglitch */
                                        };
                                };
                        };
@@ -77,6 +77,10 @@
                                        reg = <0>;
                                };
                        };
+                        watchdog@fffffe40 {
+                                status = "okay";
+                        };
                };
                nand0: nand@40000000 {
@@ -95,19 +99,19 @@
                d8 {
                        label = "d8";
-                        gpios = <&pioB 4 1>;
+                        gpios = <&pioB 4 GPIO_ACTIVE_LOW>;
                        linux,default-trigger = "mmc0";
                };
                d9 {
                        label = "d6";
-                        gpios = <&pioB 5 1>;
+                        gpios = <&pioB 5 GPIO_ACTIVE_LOW>;
                        linux,default-trigger = "nand-disk";
                };
                d10 {
                        label = "d7";
-                        gpios = <&pioB 6 0>;
+                        gpios = <&pioB 6 GPIO_ACTIVE_HIGH>;
                        linux,default-trigger = "heartbeat";
                };
        };
@@ -117,7 +121,7 @@
                enter {
                        label = "Enter";
-                        gpios = <&pioB 4 1>;
+                        gpios = <&pioB 4 GPIO_ACTIVE_LOW>;
                        linux,code = <28>;
                        gpio-key,wakeup;
                };
diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi b/arch/arm/boot/dts/at91sam9x25.dtsi
index 9ac2bc2b4f07..49e94aba938f 100644
--- a/arch/arm/boot/dts/at91sam9x25.dtsi
+++ b/arch/arm/boot/dts/at91sam9x25.dtsi
@@ -6,7 +6,7 @@
 * Licensed under GPLv2.
 */
-/include/ "at91sam9x5.dtsi"
+#include "at91sam9x5.dtsi"
 / {
        model = "Atmel AT91SAM9X25 SoC";
@@ -26,16 +26,16 @@
                                macb1 {
                                        pinctrl_macb1_rmii: macb1_rmii-0 {
                                                atmel,pins =
-                                                        <2 16 0x2 0x0   /* PC16 periph B */
+                                                        <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC16 periph B */
-                                                         2 18 0x2 0x0   /* PC18 periph B */
+                                                         AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC18 periph B */
-                                                         2 19 0x2 0x0   /* PC19 periph B */
+                                                         AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC19 periph B */
-                                                         2 20 0x2 0x0   /* PC20 periph B */
+                                                         AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC20 periph B */
-                                                         2 21 0x2 0x0   /* PC21 periph B */
+                                                         AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC21 periph B */
-                                                         2 27 0x2 0x0   /* PC27 periph B */
+                                                         AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC27 periph B */
-                                                         2 28 0x2 0x0   /* PC28 periph B */
+                                                         AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC28 periph B */
-                                                         2 29 0x2 0x0   /* PC29 periph B */
+                                                         AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC29 periph B */
-                                                         2 30 0x2 0x0   /* PC30 periph B */
+                                                         AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC30 periph B */
-                                                         2 31 0x2 0x0>; /* PC31 periph B */
+                                                         AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC31 periph B */
                                        };
                                };
                        };
diff --git a/arch/arm/boot/dts/at91sam9x25ek.dts b/arch/arm/boot/dts/at91sam9x25ek.dts
index 315250b4995e..494864836e83 100644
--- a/arch/arm/boot/dts/at91sam9x25ek.dts
+++ b/arch/arm/boot/dts/at91sam9x25ek.dts
@@ -7,8 +7,8 @@
 * Licensed under GPLv2 or later.
 */
 /dts-v1/;
-/include/ "at91sam9x25.dtsi"
+#include "at91sam9x25.dtsi"
-/include/ "at91sam9x5ek.dtsi"
+#include "at91sam9x5ek.dtsi"
 / {
        model = "Atmel AT91SAM9X25-EK";
diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/at91sam9x35.dtsi
index ba67d83d17ac..1a3d525a1f5d 100644
--- a/arch/arm/boot/dts/at91sam9x35.dtsi
+++ b/arch/arm/boot/dts/at91sam9x35.dtsi
@@ -6,7 +6,7 @@
 * Licensed under GPLv2.
 */
-/include/ "at91sam9x5.dtsi"
+#include "at91sam9x5.dtsi"
 / {
        model = "Atmel AT91SAM9X35 SoC";
diff --git a/arch/arm/boot/dts/at91sam9x35ek.dts b/arch/arm/boot/dts/at91sam9x35ek.dts
index 6ad19a0d5424..343d32818ca3 100644
--- a/arch/arm/boot/dts/at91sam9x35ek.dts
+++ b/arch/arm/boot/dts/at91sam9x35ek.dts
@@ -7,8 +7,8 @@
 * Licensed under GPLv2 or later.
 */
 /dts-v1/;
-/include/ "at91sam9x35.dtsi"
+#include "at91sam9x35.dtsi"
-/include/ "at91sam9x5ek.dtsi"
+#include "at91sam9x5ek.dtsi"
 / {
        model = "Atmel AT91SAM9X35-EK";
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 1145ac330fb7..57d45f5bea09 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -9,7 +9,11 @@
 * Licensed under GPLv2 or later.
 */
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
+#include <dt-bindings/dma/at91.h>
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
 / {
        model = "Atmel AT91SAM9x5 family SoC";
@@ -33,8 +37,12 @@
                ssc0 = &ssc0;
        };
        cpus {
-                cpu@0 {
+                #address-cells = <0>;
-                        compatible = "arm,arm926ejs";
+                #size-cells = <0>;
+                cpu {
+                        compatible = "arm,arm926ej-s";
+                        device_type = "cpu";
                };
        };
@@ -85,32 +93,32 @@
                        pit: timer@fffffe30 {
                                compatible = "atmel,at91sam9260-pit";
                                reg = <0xfffffe30 0xf>;
-                                interrupts = <1 4 7>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                        };
                        tcb0: timer@f8008000 {
                                compatible = "atmel,at91sam9x5-tcb";
                                reg = <0xf8008000 0x100>;
-                                interrupts = <17 4 0>;
+                                interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
                        };
                        tcb1: timer@f800c000 {
                                compatible = "atmel,at91sam9x5-tcb";
                                reg = <0xf800c000 0x100>;
-                                interrupts = <17 4 0>;
+                                interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
                        };
                        dma0: dma-controller@ffffec00 {
                                compatible = "atmel,at91sam9g45-dma";
                                reg = <0xffffec00 0x200>;
-                                interrupts = <20 4 0>;
+                                interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
                                #dma-cells = <2>;
                        };
                        dma1: dma-controller@ffffee00 {
                                compatible = "atmel,at91sam9g45-dma";
                                reg = <0xffffee00 0x200>;
-                                interrupts = <21 4 0>;
+                                interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
                                #dma-cells = <2>;
                        };
@@ -124,297 +132,373 @@
                                dbgu {
                                        pinctrl_dbgu: dbgu-0 {
                                                atmel,pins =
-                                                        <0 9 0x1 0x0    /* PA9 periph A */
+                                                        <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA9 periph A */
-                                                         0 10 0x1 0x1>; /* PA10 periph A with pullup */
+                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA10 periph A with pullup */
                                        };
                                };
                                usart0 {
                                        pinctrl_usart0: usart0-0 {
                                                atmel,pins =
-                                                        <0 0 0x1 0x1    /* PA0 periph A with pullup */
+                                                        <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA0 periph A with pullup */
-                                                         0 1 0x1 0x0>;  /* PA1 periph A */
+                                                         AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA1 periph A */
                                        };
                                        pinctrl_usart0_rts: usart0_rts-0 {
                                                atmel,pins =
-                                                        <0 2 0x1 0x0>;  /* PA2 periph A */
+                                                        <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA2 periph A */
                                        };
                                        pinctrl_usart0_cts: usart0_cts-0 {
                                                atmel,pins =
-                                                        <0 3 0x1 0x0>;  /* PA3 periph A */
+                                                        <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA3 periph A */
                                        };
                                        pinctrl_usart0_sck: usart0_sck-0 {
                                                atmel,pins =
-                                                        <0 4 0x1 0x0>;  /* PA4 periph A */
+                                                        <AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA4 periph A */
                                        };
                                };
                                usart1 {
                                        pinctrl_usart1: usart1-0 {
                                                atmel,pins =
-                                                        <0 5 0x1 0x1    /* PA5 periph A with pullup */
+                                                        <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA5 periph A with pullup */
-                                                         0 6 0x1 0x0>;  /* PA6 periph A */
+                                                         AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA6 periph A */
                                        };
                                        pinctrl_usart1_rts: usart1_rts-0 {
                                                atmel,pins =
-                                                        <2 27 0x3 0x0>; /* PC27 periph C */
+                                                        <AT91_PIOC 27 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC27 periph C */
                                        };
                                        pinctrl_usart1_cts: usart1_cts-0 {
                                                atmel,pins =
-                                                        <2 28 0x3 0x0>; /* PC28 periph C */
+                                                        <AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C */
                                        };
                                        pinctrl_usart1_sck: usart1_sck-0 {
                                                atmel,pins =
-                                                        <2 28 0x3 0x0>; /* PC29 periph C */
+                                                        <AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC29 periph C */
                                        };
                                };
                                usart2 {
                                        pinctrl_usart2: usart2-0 {
                                                atmel,pins =
-                                                        <0 7 0x1 0x1    /* PA7 periph A with pullup */
+                                                        <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
-                                                         0 8 0x1 0x0>;  /* PA8 periph A */
+                                                         AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA8 periph A */
                                        };
                                        pinctrl_uart2_rts: uart2_rts-0 {
                                                atmel,pins =
-                                                        <1 0 0x2 0x0>;  /* PB0 periph B */
+                                                        <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PB0 periph B */
                                        };
                                        pinctrl_uart2_cts: uart2_cts-0 {
                                                atmel,pins =
-                                                        <1 1 0x2 0x0>;  /* PB1 periph B */
+                                                        <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PB1 periph B */
                                        };
                                        pinctrl_usart2_sck: usart2_sck-0 {
                                                atmel,pins =
-                                                        <1 2 0x2 0x0>;  /* PB2 periph B */
+                                                        <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PB2 periph B */
                                        };
                                };
                                usart3 {
                                        pinctrl_usart3: usart3-0 {
                                                atmel,pins =
-                                                        <2 22 0x2 0x1   /* PC22 periph B with pullup */
+                                                        <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* PC22 periph B with pullup */
-                                                         2 23 0x2 0x0>; /* PC23 periph B */
+                                                         AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC23 periph B */
                                        };
                                        pinctrl_usart3_rts: usart3_rts-0 {
                                                atmel,pins =
-                                                        <2 24 0x2 0x0>; /* PC24 periph B */
+                                                        <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */
                                        };
                                        pinctrl_usart3_cts: usart3_cts-0 {
                                                atmel,pins =
-                                                        <2 25 0x2 0x0>; /* PC25 periph B */
+                                                        <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */
                                        };
                                        pinctrl_usart3_sck: usart3_sck-0 {
                                                atmel,pins =
-                                                        <2 26 0x2 0x0>; /* PC26 periph B */
+                                                        <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC26 periph B */
                                        };
                                };
                                uart0 {
                                        pinctrl_uart0: uart0-0 {
                                                atmel,pins =
-                                                        <2 8 0x3 0x0    /* PC8 periph C */
+                                                        <AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE    /* PC8 periph C */
-                                                         2 9 0x3 0x1>;  /* PC9 periph C with pullup */
+                                                         AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>;       /* PC9 periph C with pullup */
                                        };
                                };
                                uart1 {
                                        pinctrl_uart1: uart1-0 {
                                                atmel,pins =
-                                                        <2 16 0x3 0x0   /* PC16 periph C */
+                                                        <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PC16 periph C */
-                                                         2 17 0x3 0x1>; /* PC17 periph C with pullup */
+                                                         AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>;      /* PC17 periph C with pullup */
                                        };
                                };
                                nand {
                                        pinctrl_nand: nand-0 {
                                                atmel,pins =
-                                                        <3 0 0x1 0x0    /* PD0 periph A Read Enable */
+                                                        <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PD0 periph A Read Enable */
-                                                         3 1 0x1 0x0    /* PD1 periph A Write Enable */
+                                                         AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PD1 periph A Write Enable */
-                                                         3 2 0x1 0x0    /* PD2 periph A Address Latch Enable */
+                                                         AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PD2 periph A Address Latch Enable */
-                                                         3 3 0x1 0x0    /* PD3 periph A Command Latch Enable */
+                                                         AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PD3 periph A Command Latch Enable */
-                                                         3 4 0x0 0x1    /* PD4 gpio Chip Enable pin pull_up */
+                                                         AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP      /* PD4 gpio Chip Enable pin pull_up */
-                                                         3 5 0x0 0x1    /* PD5 gpio RDY/BUSY pin pull_up */
+                                                         AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP      /* PD5 gpio RDY/BUSY pin pull_up */
-                                                         3 6 0x1 0x0    /* PD6 periph A Data bit 0 */
+                                                         AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PD6 periph A Data bit 0 */
-                                                         3 7 0x1 0x0    /* PD7 periph A Data bit 1 */
+                                                         AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PD7 periph A Data bit 1 */
-                                                         3 8 0x1 0x0    /* PD8 periph A Data bit 2 */
+                                                         AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PD8 periph A Data bit 2 */
-                                                         3 9 0x1 0x0    /* PD9 periph A Data bit 3 */
+                                                         AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PD9 periph A Data bit 3 */
-                                                         3 10 0x1 0x0   /* PD10 periph A Data bit 4 */
+                                                         AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD10 periph A Data bit 4 */
-                                                         3 11 0x1 0x0   /* PD11 periph A Data bit 5 */
+                                                         AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD11 periph A Data bit 5 */
-                                                         3 12 0x1 0x0   /* PD12 periph A Data bit 6 */
+                                                         AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD12 periph A Data bit 6 */
-                                                         3 13 0x1 0x0>; /* PD13 periph A Data bit 7 */
+                                                         AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD13 periph A Data bit 7 */
                                        };
                                        pinctrl_nand_16bits: nand_16bits-0 {
                                                atmel,pins =
-                                                        <3 14 0x1 0x0   /* PD14 periph A Data bit 8 */
+                                                        <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD14 periph A Data bit 8 */
-                                                         3 15 0x1 0x0   /* PD15 periph A Data bit 9 */
+                                                         AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD15 periph A Data bit 9 */
-                                                         3 16 0x1 0x0   /* PD16 periph A Data bit 10 */
+                                                         AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD16 periph A Data bit 10 */
-                                                         3 17 0x1 0x0   /* PD17 periph A Data bit 11 */
+                                                         AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD17 periph A Data bit 11 */
-                                                         3 18 0x1 0x0   /* PD18 periph A Data bit 12 */
+                                                         AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD18 periph A Data bit 12 */
-                                                         3 19 0x1 0x0   /* PD19 periph A Data bit 13 */
+                                                         AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD19 periph A Data bit 13 */
-                                                         3 20 0x1 0x0   /* PD20 periph A Data bit 14 */
+                                                         AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD20 periph A Data bit 14 */
-                                                         3 21 0x1 0x0>; /* PD21 periph A Data bit 15 */
+                                                         AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A Data bit 15 */
                                        };
                                };
                                macb0 {
                                        pinctrl_macb0_rmii: macb0_rmii-0 {
                                                atmel,pins =
-                                                        <1 0 0x1 0x0    /* PB0 periph A */
+                                                        <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB0 periph A */
-                                                         1 1 0x1 0x0    /* PB1 periph A */
+                                                         AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB1 periph A */
-                                                         1 2 0x1 0x0    /* PB2 periph A */
+                                                         AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB2 periph A */
-                                                         1 3 0x1 0x0    /* PB3 periph A */
+                                                         AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB3 periph A */
-                                                         1 4 0x1 0x0    /* PB4 periph A */
+                                                         AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB4 periph A */
-                                                         1 5 0x1 0x0    /* PB5 periph A */
+                                                         AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB5 periph A */
-                                                         1 6 0x1 0x0    /* PB6 periph A */
+                                                         AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB6 periph A */
-                                                         1 7 0x1 0x0    /* PB7 periph A */
+                                                         AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB7 periph A */
-                                                         1 9 0x1 0x0    /* PB9 periph A */
+                                                         AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB9 periph A */
-                                                         1 10 0x1 0x0>; /* PB10 periph A */
+                                                         AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
                                        };
                                        pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
                                                atmel,pins =
-                                                        <1 8 0x1 0x0    /* PB8 periph A */
+                                                        <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB8 periph A */
-                                                         1 11 0x1 0x0   /* PB11 periph A */
+                                                         AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB11 periph A */
-                                                         1 12 0x1 0x0   /* PB12 periph A */
+                                                         AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB12 periph A */
-                                                         1 13 0x1 0x0   /* PB13 periph A */
+                                                         AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB13 periph A */
-                                                         1 14 0x1 0x0   /* PB14 periph A */
+                                                         AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB14 periph A */
-                                                         1 15 0x1 0x0   /* PB15 periph A */
+                                                         AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB15 periph A */
-                                                         1 16 0x1 0x0   /* PB16 periph A */
+                                                         AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB16 periph A */
-                                                         1 17 0x1 0x0>; /* PB17 periph A */
+                                                         AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */
                                        };
                                };
                                mmc0 {
                                        pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
                                                atmel,pins =
-                                                        <0 17 0x1 0x0   /* PA17 periph A */
+                                                        <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA17 periph A */
-                                                         0 16 0x1 0x1   /* PA16 periph A with pullup */
+                                                         AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA16 periph A with pullup */
-                                                         0 15 0x1 0x1>; /* PA15 periph A with pullup */
+                                                         AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA15 periph A with pullup */
                                        };
                                        pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
                                                atmel,pins =
-                                                        <0 18 0x1 0x1   /* PA18 periph A with pullup */
+                                                        <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA18 periph A with pullup */
-                                                         0 19 0x1 0x1   /* PA19 periph A with pullup */
+                                                         AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA19 periph A with pullup */
-                                                         0 20 0x1 0x1>; /* PA20 periph A with pullup */
+                                                         AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA20 periph A with pullup */
                                        };
                                };
                                mmc1 {
                                        pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
                                                atmel,pins =
-                                                        <0 13 0x2 0x0   /* PA13 periph B */
+                                                        <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA13 periph B */
-                                                         0 12 0x2 0x1   /* PA12 periph B with pullup */
+                                                         AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* PA12 periph B with pullup */
-                                                         0 11 0x2 0x1>; /* PA11 periph B with pullup */
+                                                         AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;      /* PA11 periph B with pullup */
                                        };
                                        pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
                                                atmel,pins =
-                                                        <0 2 0x2 0x1    /* PA2 periph B with pullup */
+                                                        <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA2 periph B with pullup */
-                                                         0 3 0x2 0x1    /* PA3 periph B with pullup */
+                                                         AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA3 periph B with pullup */
-                                                         0 4 0x2 0x1>;  /* PA4 periph B with pullup */
+                                                         AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;       /* PA4 periph B with pullup */
                                        };
                                };
                                ssc0 {
                                        pinctrl_ssc0_tx: ssc0_tx-0 {
                                                atmel,pins =
-                                                        <0 24 0x2 0x0   /* PA24 periph B */
+                                                        <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA24 periph B */
-                                                         0 25 0x2 0x0   /* PA25 periph B */
+                                                         AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA25 periph B */
-                                                         0 26 0x2 0x0>; /* PA26 periph B */
+                                                         AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */
                                        };
                                        pinctrl_ssc0_rx: ssc0_rx-0 {
                                                atmel,pins =
-                                                        <0 27 0x2 0x0   /* PA27 periph B */
+                                                        <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA27 periph B */
-                                                         0 28 0x2 0x0   /* PA28 periph B */
+                                                         AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA28 periph B */
-                                                         0 29 0x2 0x0>; /* PA29 periph B */
+                                                         AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */
                                        };
                                };
                                spi0 {
                                        pinctrl_spi0: spi0-0 {
                                                atmel,pins =
-                                                        <0 11 0x1 0x0   /* PA11 periph A SPI0_MISO pin */
+                                                        <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA11 periph A SPI0_MISO pin */
-                                                         0 12 0x1 0x0   /* PA12 periph A SPI0_MOSI pin */
+                                                         AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA12 periph A SPI0_MOSI pin */
-                                                         0 13 0x1 0x0>; /* PA13 periph A SPI0_SPCK pin */
+                                                         AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */
                                        };
                                };
                                spi1 {
                                        pinctrl_spi1: spi1-0 {
                                                atmel,pins =
-                                                        <0 21 0x2 0x0   /* PA21 periph B SPI1_MISO pin */
+                                                        <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA21 periph B SPI1_MISO pin */
-                                                         0 22 0x2 0x0   /* PA22 periph B SPI1_MOSI pin */
+                                                         AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA22 periph B SPI1_MOSI pin */
-                                                         0 23 0x2 0x0>; /* PA23 periph B SPI1_SPCK pin */
+                                                         AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */
                                        };
                                };
                                i2c0 {
                                        pinctrl_i2c0: i2c0-0 {
                                                atmel,pins =
-                                                        <0 30 0x1 0x0   /* PA30 periph A I2C0 data */
+                                                        <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA30 periph A I2C0 data */
-                                                         0 31 0x1 0x0>; /* PA31 periph A I2C0 clock */
+                                                         AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A I2C0 clock */
                                        };
                                };
                                i2c1 {
                                        pinctrl_i2c1: i2c1-0 {
                                                atmel,pins =
-                                                        <2 0 0x3 0x0    /* PC0 periph C I2C1 data */
+                                                        <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE    /* PC0 periph C I2C1 data */
-                                                         2 1 0x3 0x0>;  /* PC1 periph C I2C1 clock */
+                                                         AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>;  /* PC1 periph C I2C1 clock */
                                        };
                                };
                                i2c2 {
                                        pinctrl_i2c2: i2c2-0 {
                                                atmel,pins =
-                                                        <1 4 0x2 0x0    /* PB4 periph B I2C2 data */
+                                                        <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE    /* PB4 periph B I2C2 data */
-                                                         1 5 0x2 0x0>;  /* PB5 periph B I2C2 clock */
+                                                         AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PB5 periph B I2C2 clock */
                                        };
                                };
                                i2c_gpio0 {
                                        pinctrl_i2c_gpio0: i2c_gpio0-0 {
                                                atmel,pins =
-                                                        <0 30 0x0 0x2   /* PA30 gpio multidrive I2C0 data */
+                                                        <AT91_PIOA 30 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PA30 gpio multidrive I2C0 data */
-                                                         0 31 0x0 0x2>; /* PA31 gpio multidrive I2C0 clock */
+                                                         AT91_PIOA 31 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;       /* PA31 gpio multidrive I2C0 clock */
                                        };
                                };
                                i2c_gpio1 {
                                        pinctrl_i2c_gpio1: i2c_gpio1-0 {
                                                atmel,pins =
-                                                        <2 0 0x0 0x2    /* PC0 gpio multidrive I2C1 data */
+                                                        <AT91_PIOC 0 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE  /* PC0 gpio multidrive I2C1 data */
-                                                         2 1 0x0 0x2>;  /* PC1 gpio multidrive I2C1 clock */
+                                                         AT91_PIOC 1 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;        /* PC1 gpio multidrive I2C1 clock */
                                        };
                                };
                                i2c_gpio2 {
                                        pinctrl_i2c_gpio2: i2c_gpio2-0 {
                                                atmel,pins =
-                                                        <1 4 0x0 0x2    /* PB4 gpio multidrive I2C2 data */
+                                                        <AT91_PIOB 4 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE  /* PB4 gpio multidrive I2C2 data */
-                                                         1 5 0x0 0x2>;  /* PB5 gpio multidrive I2C2 clock */
+                                                         AT91_PIOB 5 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;        /* PB5 gpio multidrive I2C2 clock */
+                                        };
+                                };
+                                tcb0 {
+                                        pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+                                                atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+                                                atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+                                                atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+                                                atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+                                                atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+                                                atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+                                                atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+                                                atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+                                                atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                };
+                                tcb1 {
+                                        pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
+                                                atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
+                                                atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
+                                                atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
+                                                atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
+                                                atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
+                                                atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
+                                                atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
+                                                atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
+                                                atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
                                        };
                                };
                                pioA: gpio@fffff400 {
                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                        reg = <0xfffff400 0x200>;
-                                        interrupts = <2 4 1>;
+                                        interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
                                        #gpio-cells = <2>;
                                        gpio-controller;
                                        interrupt-controller;
@@ -424,7 +508,7 @@
                                pioB: gpio@fffff600 {
                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                        reg = <0xfffff600 0x200>;
-                                        interrupts = <2 4 1>;
+                                        interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
                                        #gpio-cells = <2>;
                                        gpio-controller;
                                        #gpio-lines = <19>;
@@ -435,7 +519,7 @@
                                pioC: gpio@fffff800 {
                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                        reg = <0xfffff800 0x200>;
-                                        interrupts = <3 4 1>;
+                                        interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
                                        #gpio-cells = <2>;
                                        gpio-controller;
                                        interrupt-controller;
@@ -445,7 +529,7 @@
                                pioD: gpio@fffffa00 {
                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                        reg = <0xfffffa00 0x200>;
-                                        interrupts = <3 4 1>;
+                                        interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
                                        #gpio-cells = <2>;
                                        gpio-controller;
                                        #gpio-lines = <22>;
@@ -457,7 +541,7 @@
                        ssc0: ssc@f0010000 {
                                compatible = "atmel,at91sam9g45-ssc";
                                reg = <0xf0010000 0x4000>;
-                                interrupts = <28 4 5>;
+                                interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
                                status = "disabled";
@@ -466,8 +550,8 @@
                        mmc0: mmc@f0008000 {
                                compatible = "atmel,hsmci";
                                reg = <0xf0008000 0x600>;
-                                interrupts = <12 4 0>;
+                                interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
-                                dmas = <&dma0 1 0>;
+                                dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>;
                                dma-names = "rxtx";
                                #address-cells = <1>;
                                #size-cells = <0>;
@@ -477,8 +561,8 @@
                        mmc1: mmc@f000c000 {
                                compatible = "atmel,hsmci";
                                reg = <0xf000c000 0x600>;
-                                interrupts = <26 4 0>;
+                                interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
-                                dmas = <&dma1 1 0>;
+                                dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>;
                                dma-names = "rxtx";
                                #address-cells = <1>;
                                #size-cells = <0>;
@@ -488,7 +572,7 @@
                        dbgu: serial@fffff200 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xfffff200 0x200>;
-                                interrupts = <1 4 7>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_dbgu>;
                                status = "disabled";
@@ -497,7 +581,7 @@
                        usart0: serial@f801c000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xf801c000 0x200>;
-                                interrupts = <5 4 5>;
+                                interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_usart0>;
                                status = "disabled";
@@ -506,7 +590,7 @@
                        usart1: serial@f8020000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xf8020000 0x200>;
-                                interrupts = <6 4 5>;
+                                interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_usart1>;
                                status = "disabled";
@@ -515,7 +599,7 @@
                        usart2: serial@f8024000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xf8024000 0x200>;
-                                interrupts = <7 4 5>;
+                                interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_usart2>;
                                status = "disabled";
@@ -524,7 +608,7 @@
                        macb0: ethernet@f802c000 {
                                compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                reg = <0xf802c000 0x100>;
-                                interrupts = <24 4 3>;
+                                interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_macb0_rmii>;
                                status = "disabled";
@@ -533,16 +617,16 @@
                        macb1: ethernet@f8030000 {
                                compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                reg = <0xf8030000 0x100>;
-                                interrupts = <27 4 3>;
+                                interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
                                status = "disabled";
                        };
                        i2c0: i2c@f8010000 {
                                compatible = "atmel,at91sam9x5-i2c";
                                reg = <0xf8010000 0x100>;
-                                interrupts = <9 4 6>;
+                                interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>;
-                                dmas = <&dma0 1 7>,
+                                dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(7)>,
-                                       <&dma0 1 8>;
+                                       <&dma0 1 AT91_DMA_CFG_PER_ID(8)>;
                                dma-names = "tx", "rx";
                                #address-cells = <1>;
                                #size-cells = <0>;
@@ -554,9 +638,9 @@
                        i2c1: i2c@f8014000 {
                                compatible = "atmel,at91sam9x5-i2c";
                                reg = <0xf8014000 0x100>;
-                                interrupts = <10 4 6>;
+                                interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>;
-                                dmas = <&dma1 1 5>,
+                                dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(5)>,
-                                       <&dma1 1 6>;
+                                       <&dma1 1 AT91_DMA_CFG_PER_ID(6)>;
                                dma-names = "tx", "rx";
                                #address-cells = <1>;
                                #size-cells = <0>;
@@ -568,9 +652,9 @@
                        i2c2: i2c@f8018000 {
                                compatible = "atmel,at91sam9x5-i2c";
                                reg = <0xf8018000 0x100>;
-                                interrupts = <11 4 6>;
+                                interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
-                                dmas = <&dma0 1 9>,
+                                dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(9)>,
-                                       <&dma0 1 10>;
+                                       <&dma0 1 AT91_DMA_CFG_PER_ID(10)>;
                                dma-names = "tx", "rx";
                                #address-cells = <1>;
                                #size-cells = <0>;
@@ -579,10 +663,28 @@
                                status = "disabled";
                        };
+                        uart0: serial@f8040000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xf8040000 0x200>;
+                                interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart0>;
+                                status = "disabled";
+                        };
+                        uart1: serial@f8044000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xf8044000 0x200>;
+                                interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart1>;
+                                status = "disabled";
+                        };
                        adc0: adc@f804c000 {
                                compatible = "atmel,at91sam9260-adc";
                                reg = <0xf804c000 0x100>;
-                                interrupts = <19 4 0>;
+                                interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
                                atmel,adc-use-external;
                                atmel,adc-channels-used = <0xffff>;
                                atmel,adc-vref = <3300>;
@@ -625,7 +727,10 @@
                                #size-cells = <0>;
                                compatible = "atmel,at91rm9200-spi";
                                reg = <0xf0000000 0x100>;
-                                interrupts = <13 4 3>;
+                                interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
+                                dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(1)>,
+                                       <&dma0 1 AT91_DMA_CFG_PER_ID(2)>;
+                                dma-names = "tx", "rx";
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_spi0>;
                                status = "disabled";
@@ -636,16 +741,87 @@
                                #size-cells = <0>;
                                compatible = "atmel,at91rm9200-spi";
                                reg = <0xf0004000 0x100>;
-                                interrupts = <14 4 3>;
+                                interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
+                                dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(1)>,
+                                       <&dma1 1 AT91_DMA_CFG_PER_ID(2)>;
+                                dma-names = "tx", "rx";
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_spi1>;
                                status = "disabled";
                        };
+                        usb2: gadget@f803c000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "atmel,at91sam9rl-udc";
+                                reg = <0x00500000 0x80000
+                                       0xf803c000 0x400>;
+                                interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
+                                status = "disabled";
+                                ep0 {
+                                        reg = <0>;
+                                        atmel,fifo-size = <64>;
+                                        atmel,nb-banks = <1>;
+                                };
+                                ep1 {
+                                        reg = <1>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <2>;
+                                        atmel,can-dma;
+                                        atmel,can-isoc;
+                                };
+                                ep2 {
+                                        reg = <2>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <2>;
+                                        atmel,can-dma;
+                                        atmel,can-isoc;
+                                };
+                                ep3 {
+                                        reg = <3>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <3>;
+                                        atmel,can-dma;
+                                };
+                                ep4 {
+                                        reg = <4>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <3>;
+                                        atmel,can-dma;
+                                };
+                                ep5 {
+                                        reg = <5>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <3>;
+                                        atmel,can-dma;
+                                        atmel,can-isoc;
+                                };
+                                ep6 {
+                                        reg = <6>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <3>;
+                                        atmel,can-dma;
+                                        atmel,can-isoc;
+                                };
+                        };
+                        watchdog@fffffe40 {
+                                compatible = "atmel,at91sam9260-wdt";
+                                reg = <0xfffffe40 0x10>;
+                                status = "disabled";
+                        };
                        rtc@fffffeb0 {
-                                compatible = "atmel,at91rm9200-rtc";
+                                compatible = "atmel,at91sam9x5-rtc";
                                reg = <0xfffffeb0 0x40>;
-                                interrupts = <1 4 7>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                                status = "disabled";
                        };
                };
@@ -664,8 +840,8 @@
                        atmel,nand-cmd-offset = <22>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_nand>;
-                        gpios = <&pioD 5 0
+                        gpios = <&pioD 5 GPIO_ACTIVE_HIGH
-                                 &pioD 4 0
+                                 &pioD 4 GPIO_ACTIVE_HIGH
                                 0
                                >;
                        status = "disabled";
@@ -674,22 +850,22 @@
                usb0: ohci@00600000 {
                        compatible = "atmel,at91rm9200-ohci", "usb-ohci";
                        reg = <0x00600000 0x100000>;
-                        interrupts = <22 4 2>;
+                        interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
                        status = "disabled";
                };
                usb1: ehci@00700000 {
                        compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
                        reg = <0x00700000 0x100000>;
-                        interrupts = <22 4 2>;
+                        interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
                        status = "disabled";
                };
        };
        i2c@0 {
                compatible = "i2c-gpio";
-                gpios = <&pioA 30 0 /* sda */
+                gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */
-                         &pioA 31 0 /* scl */
+                         &pioA 31 GPIO_ACTIVE_HIGH /* scl */
                        >;
                i2c-gpio,sda-open-drain;
                i2c-gpio,scl-open-drain;
@@ -703,8 +879,8 @@
        i2c@1 {
                compatible = "i2c-gpio";
-                gpios = <&pioC 0 0 /* sda */
+                gpios = <&pioC 0 GPIO_ACTIVE_HIGH /* sda */
-                         &pioC 1 0 /* scl */
+                         &pioC 1 GPIO_ACTIVE_HIGH /* scl */
                        >;
                i2c-gpio,sda-open-drain;
                i2c-gpio,scl-open-drain;
@@ -718,8 +894,8 @@
        i2c@2 {
                compatible = "i2c-gpio";
-                gpios = <&pioB 4 0 /* sda */
+                gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */
-                         &pioB 5 0 /* scl */
+                         &pioB 5 GPIO_ACTIVE_HIGH /* scl */
                        >;
                i2c-gpio,sda-open-drain;
                i2c-gpio,scl-open-drain;
diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi
index 347a74a857f6..4a5ee5cc115a 100644
--- a/arch/arm/boot/dts/at91sam9x5cm.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5cm.dtsi
@@ -28,7 +28,7 @@
                        pinctrl@fffff400 {
                                1wire_cm {
                                        pinctrl_1wire_cm: 1wire_cm-0 {
-                                                atmel,pins = <1 18 0x0 0x2>; /* PB18 multidrive, conflicts with led */
+                                                atmel,pins = <AT91_PIOB 18 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PB18 multidrive, conflicts with led */
                                        };
                                };
                        };
@@ -75,19 +75,19 @@
                pb18 {
                        label = "pb18";
-                        gpios = <&pioB 18 1>;
+                        gpios = <&pioB 18 GPIO_ACTIVE_LOW>;
                        linux,default-trigger = "heartbeat";
                };
                pd21 {
                        label = "pd21";
-                        gpios = <&pioD 21 0>;
+                        gpios = <&pioD 21 GPIO_ACTIVE_HIGH>;
                };
        };
        1wire_cm {
                compatible = "w1-gpio";
-                gpios = <&pioB 18 0>;
+                gpios = <&pioB 18 GPIO_ACTIVE_HIGH>;
                linux,open-drain;
                pinctrl-names = "default";
                pinctrl-0 = <&pinctrl_1wire_cm>;
diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi
index 1fa48d2bfd80..b753855b2058 100644
--- a/arch/arm/boot/dts/at91sam9x5ek.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi
@@ -6,7 +6,7 @@
 *
 * Licensed under GPLv2 or later.
 */
-/include/ "at91sam9x5cm.dtsi"
+#include "at91sam9x5cm.dtsi"
 / {
        model = "Atmel AT91SAM9X5-EK";
@@ -27,7 +27,7 @@
                                slot@0 {
                                        reg = <0>;
                                        bus-width = <4>;
-                                        cd-gpios = <&pioD 15 0>;
+                                        cd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>;
                                };
                        };
@@ -40,7 +40,7 @@
                                slot@0 {
                                        reg = <0>;
                                        bus-width = <4>;
-                                        cd-gpios = <&pioD 14 0>;
+                                        cd-gpios = <&pioD 14 GPIO_ACTIVE_HIGH>;
                                };
                        };
@@ -52,6 +52,11 @@
                                status = "okay";
                        };
+                        usb2: gadget@f803c000 {
+                                atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>;
+                                status = "okay";
+                        };
                        i2c0: i2c@f8010000 {
                                status = "okay";
                        };
@@ -60,14 +65,14 @@
                                mmc0 {
                                        pinctrl_board_mmc0: mmc0-board {
                                                atmel,pins =
-                                                        <3 15 0x0 0x5>; /* PD15 gpio CD pin pull up and deglitch */
+                                                        <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;  /* PD15 gpio CD pin pull up and deglitch */
                                        };
                                };
                                mmc1 {
                                        pinctrl_board_mmc1: mmc1-board {
                                                atmel,pins =
-                                                        <3 14 0x0 0x5>; /* PD14 gpio CD pin pull up and deglitch */
+                                                        <AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;  /* PD14 gpio CD pin pull up and deglitch */
                                        };
                                };
                        };
@@ -81,13 +86,17 @@
                                        reg = <0>;
                                };
                        };
+                        watchdog@fffffe40 {
+                                status = "okay";
+                        };
                };
                usb0: ohci@00600000 {
                        status = "okay";
                        num-ports = <2>;
-                        atmel,vbus-gpio = <&pioD 19 1
+                        atmel,vbus-gpio = <&pioD 19 GPIO_ACTIVE_LOW
-                                           &pioD 20 1
+                                           &pioD 20 GPIO_ACTIVE_LOW
                                          >;
                };
diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi
index 7d1a27949c13..a0f2721ea583 100644
--- a/arch/arm/boot/dts/atlas6.dtsi
+++ b/arch/arm/boot/dts/atlas6.dtsi
@@ -485,6 +485,12 @@
                                                sirf,function = "usp0";
                                        };
                                };
+                                usp0_uart_nostreamctrl_pins_a: usp0@1 {
+                                        usp0 {
+                                                sirf,pins = "usp0_uart_nostreamctrl_grp";
+                                                sirf,function = "usp0_uart_nostreamctrl";
+                                        };
+                                };
                                usp1_pins_a: usp1@0 {
                                        usp1 {
                                                sirf,pins = "usp1grp";
@@ -515,16 +521,16 @@
                                                sirf,function = "pulse_count";
                                        };
                                };
-                                cko0_rst_pins_a: cko0_rst@0 {
+                                cko0_pins_a: cko0@0 {
-                                        cko0_rst {
+                                        cko0 {
-                                                sirf,pins = "cko0_rstgrp";
+                                                sirf,pins = "cko0grp";
-                                                sirf,function = "cko0_rst";
+                                                sirf,function = "cko0";
                                        };
                                };
-                                cko1_rst_pins_a: cko1_rst@0 {
+                                cko1_pins_a: cko1@0 {
-                                        cko1_rst {
+                                        cko1 {
-                                                sirf,pins = "cko1_rstgrp";
+                                                sirf,pins = "cko1grp";
-                                                sirf,function = "cko1_rst";
+                                                sirf,function = "cko1";
                                        };
                                };
                        };
@@ -613,7 +619,7 @@
                };
                rtc-iobg {
-                        compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus";
+                        compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus";
                        #address-cells = <1>;
                        #size-cells = <1>;
                        reg = <0x80030000 0x10000>;
diff --git a/arch/arm/boot/dts/bcm11351-brt.dts b/arch/arm/boot/dts/bcm11351-brt.dts
index 248067cf7069..67ec524098b5 100644
--- a/arch/arm/boot/dts/bcm11351-brt.dts
+++ b/arch/arm/boot/dts/bcm11351-brt.dts
@@ -13,7 +13,7 @@
 /dts-v1/;
-/include/ "bcm11351.dtsi"
+#include "bcm11351.dtsi"
 / {
        model = "BCM11351 BRT board";
@@ -27,4 +27,21 @@
                status = "okay";
        };
+        sdio0: sdio@0x3f180000 {
+                max-frequency = <48000000>;
+                status = "okay";
+        };
+        sdio1: sdio@0x3f190000 {
+                non-removable;
+                max-frequency = <48000000>;
+                status = "okay";
+        };
+        sdio3: sdio@0x3f1b0000 {
+                max-frequency = <48000000>;
+                status = "okay";
+        };
 };
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
index 41b2c6c33f09..c0cdf66f8964 100644
--- a/arch/arm/boot/dts/bcm11351.dtsi
+++ b/arch/arm/boot/dts/bcm11351.dtsi
@@ -11,7 +11,10 @@
 * GNU General Public License for more details.
 */
-/include/ "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "skeleton.dtsi"
 / {
        model = "BCM11351 SoC";
@@ -33,7 +36,7 @@
        smc@0x3404c000 {
                compatible = "bcm,bcm11351-smc", "bcm,kona-smc";
-                reg = <0x3404c000 0x400>; //1 KiB in SRAM
+                reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */
        };
        uart@3e000000 {
@@ -41,23 +44,51 @@
                status = "disabled";
                reg = <0x3e000000 0x1000>;
                clock-frequency = <13000000>;
-                interrupts = <0x0 67 0x4>;
+                interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
                reg-shift = <2>;
                reg-io-width = <4>;
        };
        L2: l2-cache {
-                    compatible = "arm,pl310-cache";
+                compatible = "bcm,bcm11351-a2-pl310-cache";
-                    reg = <0x3ff20000 0x1000>;
+                reg = <0x3ff20000 0x1000>;
-                    cache-unified;
+                cache-unified;
-                    cache-level = <2>;
+                cache-level = <2>;
        };
        timer@35006000 {
                compatible = "bcm,kona-timer";
                reg = <0x35006000 0x1000>;
-                interrupts = <0x0 7 0x4>;
+                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
                clock-frequency = <32768>;
        };
+        sdio0: sdio@0x3f180000 {
+                compatible = "bcm,kona-sdhci";
+                reg = <0x3f180000 0x10000>;
+                interrupts = <0x0 77 0x4>;
+                status = "disabled";
+        };
+        sdio1: sdio@0x3f190000 {
+                compatible = "bcm,kona-sdhci";
+                reg = <0x3f190000 0x10000>;
+                interrupts = <0x0 76 0x4>;
+                status = "disabled";
+        };
+        sdio2: sdio@0x3f1a0000 {
+                compatible = "bcm,kona-sdhci";
+                reg = <0x3f1a0000 0x10000>;
+                interrupts = <0x0 74 0x4>;
+                status = "disabled";
+        };
+        sdio3: sdio@0x3f1b0000 {
+                compatible = "bcm,kona-sdhci";
+                reg = <0x3f1b0000 0x10000>;
+                interrupts = <0x0 73 0x4>;
+                status = "disabled";
+        };
 };
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts
index aafda174a605..6e9deb786a7d 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts
@@ -8,6 +8,17 @@
        memory {
                reg = <0 0x10000000>;
        };
+        leds {
+                compatible = "gpio-leds";
+                act {
+                        label = "ACT";
+                        gpios = <&gpio 16 1>;
+                        default-state = "keep";
+                        linux,default-trigger = "heartbeat";
+                };
+        };
 };
 &gpio {
diff --git a/arch/arm/boot/dts/ccu8540.dts b/arch/arm/boot/dts/ccu8540.dts
new file mode 100644
index 000000000000..48ff03441f5a
--- /dev/null
+++ b/arch/arm/boot/dts/ccu8540.dts
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2013 ST-Ericsson AB
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+#include "dbx5x0.dtsi"
+/ {
+        model = "ST-Ericsson U8540 platform with Device Tree";
+        compatible = "st-ericsson,ccu8540", "st-ericsson,u8540";
+        memory@0 {
+                reg = <0x20000000 0x1f000000>, <0xc0000000 0x3f000000>;
+        };
+        soc {
+                prcmu@80157000 {
+                        reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x3000>;
+                        reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
+                };
+                uart@80120000 {
+                        status = "okay";
+                };
+                uart@80121000 {
+                        status = "okay";
+                };
+                uart@80007000 {
+                        status = "okay";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/ccu9540.dts b/arch/arm/boot/dts/ccu9540.dts
index 04305463f00d..ed29ec7288e4 100644
--- a/arch/arm/boot/dts/ccu9540.dts
+++ b/arch/arm/boot/dts/ccu9540.dts
@@ -10,7 +10,7 @@
 */
 /dts-v1/;
-/include/ "dbx5x0.dtsi"
+#include "dbx5x0.dtsi"
 / {
        model = "ST-Ericsson CCU9540 platform with Device Tree";
@@ -20,7 +20,7 @@
                reg = <0x00000000 0x20000000>;
        };
-        soc-u9500 {
+        soc {
                uart@80120000 {
                        status = "okay";
                };
@@ -52,7 +52,7 @@
                // WLAN SDIO channel
                sdi1_per2@80118000 {
                        arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <50000000>;
+                        max-frequency = <100000000>;
                        bus-width = <4>;
                        status = "okay";
diff --git a/arch/arm/boot/dts/cros5250-common.dtsi b/arch/arm/boot/dts/cros5250-common.dtsi
index 3f0239ec1bc5..dc259e8b8a73 100644
--- a/arch/arm/boot/dts/cros5250-common.dtsi
+++ b/arch/arm/boot/dts/cros5250-common.dtsi
@@ -190,7 +190,7 @@
                samsung,i2c-max-bus-freq = <66000>;
                hdmiddc@50 {
-                        compatible = "samsung,exynos5-hdmiddc";
+                        compatible = "samsung,exynos4210-hdmiddc";
                        reg = <0x50>;
                };
        };
@@ -224,7 +224,7 @@
                samsung,i2c-max-bus-freq = <378000>;
                hdmiphy@38 {
-                        compatible = "samsung,exynos5-hdmiphy";
+                        compatible = "samsung,exynos4212-hdmiphy";
                        reg = <0x38>;
                };
        };
diff --git a/arch/arm/boot/dts/da850-enbw-cmc.dts b/arch/arm/boot/dts/da850-enbw-cmc.dts
index 422fdb3fcfc1..e750ab9086d5 100644
--- a/arch/arm/boot/dts/da850-enbw-cmc.dts
+++ b/arch/arm/boot/dts/da850-enbw-cmc.dts
@@ -10,7 +10,7 @@
 * option) any later version.
 */
 /dts-v1/;
-/include/ "da850.dtsi"
+#include "da850.dtsi"
 / {
        compatible = "enbw,cmc", "ti,da850";
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index c914357c0d89..5bce7cc55cf3 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -8,7 +8,7 @@
 * Free Software Foundation, version 2.
 */
 /dts-v1/;
-/include/ "da850.dtsi"
+#include "da850.dtsi"
 / {
        compatible = "ti,da850-evm", "ti,da850";
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 2c88313d2c7a..d70ba5504481 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -7,7 +7,7 @@
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 / {
        arm {
@@ -37,7 +37,7 @@
                        #size-cells = <0>;
                        pinctrl-single,bit-per-mux;
                        pinctrl-single,register-width = <32>;
-                        pinctrl-single,function-mask = <0xffffffff>;
+                        pinctrl-single,function-mask = <0xf>;
                        status = "disabled";
                        nand_cs3_pins: pinmux_nand_pins {
diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index b6bc4ff17f26..a1529455f081 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -9,10 +9,11 @@
 * http://www.gnu.org/copyleft/gpl.html
 */
-/include/ "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "skeleton.dtsi"
 / {
-        soc-u9500 {
+        soc {
                #address-cells = <1>;
                #size-cells = <1>;
                compatible = "stericsson,db8500";
@@ -31,33 +32,33 @@
                L2: l2-cache {
                        compatible = "arm,pl310-cache";
                        reg = <0xa0412000 0x1000>;
-                        interrupts = <0 13 4>;
+                        interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
                        cache-unified;
                        cache-level = <2>;
                };
                pmu {
                        compatible = "arm,cortex-a9-pmu";
-                        interrupts = <0 7 0x4>;
+                        interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
                };
                timer@a0410600 {
                        compatible = "arm,cortex-a9-twd-timer";
                        reg = <0xa0410600 0x20>;
-                        interrupts = <1 13 0x304>;
+                        interrupts = <1 13 0x304>; /* IRQ level high per-CPU */
                };
                rtc@80154000 {
                        compatible = "arm,rtc-pl031", "arm,primecell";
                        reg = <0x80154000 0x1000>;
-                        interrupts = <0 18 0x4>;
+                        interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
                };
                gpio0: gpio@8012e000 {
                        compatible = "stericsson,db8500-gpio",
                                "st,nomadik-gpio";
                        reg =  <0x8012e000 0x80>;
-                        interrupts = <0 119 0x4>;
+                        interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-controller;
                        #interrupt-cells = <2>;
                        st,supports-sleepmode;
@@ -70,7 +71,7 @@
                        compatible = "stericsson,db8500-gpio",
                                "st,nomadik-gpio";
                        reg =  <0x8012e080 0x80>;
-                        interrupts = <0 120 0x4>;
+                        interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-controller;
                        #interrupt-cells = <2>;
                        st,supports-sleepmode;
@@ -83,7 +84,7 @@
                        compatible = "stericsson,db8500-gpio",
                                "st,nomadik-gpio";
                        reg =  <0x8000e000 0x80>;
-                        interrupts = <0 121 0x4>;
+                        interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-controller;
                        #interrupt-cells = <2>;
                        st,supports-sleepmode;
@@ -96,7 +97,7 @@
                        compatible = "stericsson,db8500-gpio",
                                "st,nomadik-gpio";
                        reg =  <0x8000e080 0x80>;
-                        interrupts = <0 122 0x4>;
+                        interrupts = <0 122 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-controller;
                        #interrupt-cells = <2>;
                        st,supports-sleepmode;
@@ -109,7 +110,7 @@
                        compatible = "stericsson,db8500-gpio",
                                "st,nomadik-gpio";
                        reg =  <0x8000e100 0x80>;
-                        interrupts = <0 123 0x4>;
+                        interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-controller;
                        #interrupt-cells = <2>;
                        st,supports-sleepmode;
@@ -122,7 +123,7 @@
                        compatible = "stericsson,db8500-gpio",
                                "st,nomadik-gpio";
                        reg =  <0x8000e180 0x80>;
-                        interrupts = <0 124 0x4>;
+                        interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-controller;
                        #interrupt-cells = <2>;
                        st,supports-sleepmode;
@@ -135,7 +136,7 @@
                        compatible = "stericsson,db8500-gpio",
                                "st,nomadik-gpio";
                        reg =  <0x8011e000 0x80>;
-                        interrupts = <0 125 0x4>;
+                        interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-controller;
                        #interrupt-cells = <2>;
                        st,supports-sleepmode;
@@ -148,7 +149,7 @@
                        compatible = "stericsson,db8500-gpio",
                                "st,nomadik-gpio";
                        reg =  <0x8011e080 0x80>;
-                        interrupts = <0 126 0x4>;
+                        interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-controller;
                        #interrupt-cells = <2>;
                        st,supports-sleepmode;
@@ -161,7 +162,7 @@
                        compatible = "stericsson,db8500-gpio",
                                "st,nomadik-gpio";
                        reg =  <0xa03fe000 0x80>;
-                        interrupts = <0 127 0x4>;
+                        interrupts = <0 127 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-controller;
                        #interrupt-cells = <2>;
                        st,supports-sleepmode;
@@ -171,29 +172,61 @@
                };
                pinctrl {
-                        compatible = "stericsson,nmk-pinctrl";
+                        compatible = "stericsson,db8500-pinctrl";
                        prcm = <&prcmu>;
                };
-                usb@a03e0000 {
+                usb_per5@a03e0000 {
                        compatible = "stericsson,db8500-musb",
                                "mentor,musb";
                        reg = <0xa03e0000 0x10000>;
-                        interrupts = <0 23 0x4>;
+                        interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
-                };
+                        interrupt-names = "mc";
-                dma-controller@801C0000 {
+                        dr_mode = "otg";
-                        compatible = "stericsson,db8500-dma40",
-                                        "stericsson,dma40";
+                        dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
+                               <&dma 38 0 0x0>, /* Logical - MemToDev */
+                               <&dma 37 0 0x2>, /* Logical - DevToMem */
+                               <&dma 37 0 0x0>, /* Logical - MemToDev */
+                               <&dma 36 0 0x2>, /* Logical - DevToMem */
+                               <&dma 36 0 0x0>, /* Logical - MemToDev */
+                               <&dma 19 0 0x2>, /* Logical - DevToMem */
+                               <&dma 19 0 0x0>, /* Logical - MemToDev */
+                               <&dma 18 0 0x2>, /* Logical - DevToMem */
+                               <&dma 18 0 0x0>, /* Logical - MemToDev */
+                               <&dma 17 0 0x2>, /* Logical - DevToMem */
+                               <&dma 17 0 0x0>, /* Logical - MemToDev */
+                               <&dma 16 0 0x2>, /* Logical - DevToMem */
+                               <&dma 16 0 0x0>, /* Logical - MemToDev */
+                               <&dma 39 0 0x2>, /* Logical - DevToMem */
+                               <&dma 39 0 0x0>; /* Logical - MemToDev */
+                        dma-names = "iep_1_9",  "oep_1_9",
+                                    "iep_2_10", "oep_2_10",
+                                    "iep_3_11", "oep_3_11",
+                                    "iep_4_12", "oep_4_12",
+                                    "iep_5_13", "oep_5_13",
+                                    "iep_6_14", "oep_6_14",
+                                    "iep_7_15", "oep_7_15",
+                                    "iep_8",    "oep_8";
+                };
+                dma: dma-controller@801C0000 {
+                        compatible = "stericsson,db8500-dma40", "stericsson,dma40";
                        reg = <0x801C0000 0x1000 0x40010000 0x800>;
-                        interrupts = <0 25 0x4>;
+                        reg-names = "base", "lcpa";
+                        interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
+                        #dma-cells = <3>;
+                        memcpy-channels = <56 57 58 59 60>;
                };
                prcmu: prcmu@80157000 {
                        compatible = "stericsson,db8500-prcmu";
                        reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
                        reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
-                        interrupts = <0 47 0x4>;
+                        interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
                        #address-cells = <1>;
                        #size-cells = <1>;
                        interrupt-controller;
@@ -208,7 +241,8 @@
                        thermal@801573c0 {
                                compatible = "stericsson,db8500-thermal";
                                reg = <0x801573c0 0x40>;
-                                interrupts = <21 0x4>, <22 0x4>;
+                                interrupts = <21 IRQ_TYPE_LEVEL_HIGH>,
+                                             <22 IRQ_TYPE_LEVEL_HIGH>;
                                interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
                                status = "disabled";
                         };
@@ -322,21 +356,26 @@
                        ab8500 {
                                compatible = "stericsson,ab8500";
                                interrupt-parent = <&intc>;
-                                interrupts = <0 40 0x4>;
+                                interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
                                interrupt-controller;
                                #interrupt-cells = <2>;
+                                ab8500_gpio: ab8500-gpio {
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                };
                                ab8500-rtc {
                                        compatible = "stericsson,ab8500-rtc";
-                                        interrupts = <17 0x4
+                                        interrupts = <17 IRQ_TYPE_LEVEL_HIGH
-                                                      18 0x4>;
+                                                      18 IRQ_TYPE_LEVEL_HIGH>;
                                        interrupt-names = "60S", "ALARM";
                                };
                                ab8500-gpadc {
                                        compatible = "stericsson,ab8500-gpadc";
-                                        interrupts = <32 0x4
+                                        interrupts = <32 IRQ_TYPE_LEVEL_HIGH
-                                                      39 0x4>;
+                                                      39 IRQ_TYPE_LEVEL_HIGH>;
                                        interrupt-names = "HW_CONV_END", "SW_CONV_END";
                                        vddadc-supply = <&ab8500_ldo_tvout_reg>;
                                };
@@ -369,13 +408,13 @@
                                ab8500_usb {
                                        compatible = "stericsson,ab8500-usb";
-                                        interrupts = < 90 0x4
+                                        interrupts = < 90 IRQ_TYPE_LEVEL_HIGH
-                                                       96 0x4
+                                                       96 IRQ_TYPE_LEVEL_HIGH
-                                                       14 0x4
+                                                       14 IRQ_TYPE_LEVEL_HIGH
-                                                       15 0x4
+                                                       15 IRQ_TYPE_LEVEL_HIGH
-                                                       79 0x4
+                                                       79 IRQ_TYPE_LEVEL_HIGH
-                                                       74 0x4
+                                                       74 IRQ_TYPE_LEVEL_HIGH
-                                                       75 0x4>;
+                                                       75 IRQ_TYPE_LEVEL_HIGH>;
                                        interrupt-names = "ID_WAKEUP_R",
                                                          "ID_WAKEUP_F",
                                                          "VBUS_DET_F",
@@ -383,15 +422,15 @@
                                                          "USB_LINK_STATUS",
                                                          "USB_ADP_PROBE_PLUG",
                                                          "USB_ADP_PROBE_UNPLUG";
-                                        vddulpivio18-supply = <&ab8500_ldo_initcore_reg>;
+                                        vddulpivio18-supply = <&ab8500_ldo_intcore_reg>;
                                        v-ape-supply = <&db8500_vape_reg>;
                                        musb_1v8-supply = <&db8500_vsmps2_reg>;
                                };
                                ab8500-ponkey {
                                        compatible = "stericsson,ab8500-poweron-key";
-                                        interrupts = <6 0x4
+                                        interrupts = <6 IRQ_TYPE_LEVEL_HIGH
-                                                      7 0x4>;
+                                                      7 IRQ_TYPE_LEVEL_HIGH>;
                                        interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
                                };
@@ -410,6 +449,11 @@
                                codec: ab8500-codec {
                                        compatible = "stericsson,ab8500-codec";
+                                        V-AUD-supply = <&ab8500_ldo_audio_reg>;
+                                        V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>;
+                                        V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>;
+                                        V-DMIC-supply = <&ab8500_ldo_dmic_reg>;
                                        stericsson,earpeice-cmv = <950>; /* Units in mV. */
                                };
@@ -441,8 +485,8 @@
                                        };
                                        // supply for v-intcore12; VINTCORE12 LDO
-                                        ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
+                                        ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
-                                                regulator-compatible = "ab8500_ldo_initcore";
+                                                regulator-compatible = "ab8500_ldo_intcore";
                                        };
                                        // supply for tvout; gpadc; TVOUT LDO
@@ -460,14 +504,14 @@
                                                regulator-compatible = "ab8500_ldo_audio";
                                        };
-                                        // supply for v-anamic1 VAMic1-LDO
+                                        // supply for v-anamic1 VAMIC1 LDO
                                        ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
                                                regulator-compatible = "ab8500_ldo_anamic1";
                                        };
                                        // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1
-                                        ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
+                                        ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
-                                                regulator-compatible = "ab8500_ldo_amamic2";
+                                                regulator-compatible = "ab8500_ldo_anamic2";
                                        };
                                        // supply for v-dmic; VDMIC LDO
@@ -486,7 +530,7 @@
                i2c@80004000 {
                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
                        reg = <0x80004000 0x1000>;
-                        interrupts = <0 21 0x4>;
+                        interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
                        arm,primecell-periphid = <0x180024>;
                        #address-cells = <1>;
@@ -499,7 +543,7 @@
                i2c@80122000 {
                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
                        reg = <0x80122000 0x1000>;
-                        interrupts = <0 22 0x4>;
+                        interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
                        arm,primecell-periphid = <0x180024>;
                        #address-cells = <1>;
@@ -512,7 +556,7 @@
                i2c@80128000 {
                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
                        reg = <0x80128000 0x1000>;
-                        interrupts = <0 55 0x4>;
+                        interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
                        arm,primecell-periphid = <0x180024>;
                        #address-cells = <1>;
@@ -525,7 +569,7 @@
                i2c@80110000 {
                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
                        reg = <0x80110000 0x1000>;
-                        interrupts = <0 12 0x4>;
+                        interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>;
                        arm,primecell-periphid = <0x180024>;
                        #address-cells = <1>;
@@ -538,7 +582,7 @@
                i2c@8012a000 {
                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
                        reg = <0x8012a000 0x1000>;
-                        interrupts = <0 51 0x4>;
+                        interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
                        arm,primecell-periphid = <0x180024>;
                        #address-cells = <1>;
@@ -551,82 +595,114 @@
                ssp@80002000 {
                        compatible = "arm,pl022", "arm,primecell";
                        reg = <0x80002000 0x1000>;
-                        interrupts = <0 14 0x4>;
+                        interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        status = "disabled";
-                        // Add one of these for each child device
-                        cs-gpios = <&gpio0 31 0x4 &gpio4 14 0x4 &gpio4 16 0x4
-                                    &gpio6 22 0x4 &gpio7 0 0x4>;
                };
                uart@80120000 {
                        compatible = "arm,pl011", "arm,primecell";
                        reg = <0x80120000 0x1000>;
-                        interrupts = <0 11 0x4>;
+                        interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
+                        dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
+                               <&dma 13 0 0x0>; /* Logical - MemToDev */
+                        dma-names = "rx", "tx";
                        status = "disabled";
                };
                uart@80121000 {
                        compatible = "arm,pl011", "arm,primecell";
                        reg = <0x80121000 0x1000>;
-                        interrupts = <0 19 0x4>;
+                        interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
+                        dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */
+                               <&dma 12 0 0x0>; /* Logical - MemToDev */
+                        dma-names = "rx", "tx";
                        status = "disabled";
                };
                uart@80007000 {
                        compatible = "arm,pl011", "arm,primecell";
                        reg = <0x80007000 0x1000>;
-                        interrupts = <0 26 0x4>;
+                        interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
+                        dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */
+                               <&dma 11 0 0x0>; /* Logical - MemToDev */
+                        dma-names = "rx", "tx";
                        status = "disabled";
                };
                sdi0_per1@80126000 {
                        compatible = "arm,pl18x", "arm,primecell";
                        reg = <0x80126000 0x1000>;
-                        interrupts = <0 60 0x4>;
+                        interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
+                        dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
+                               <&dma 29 0 0x0>; /* Logical - MemToDev */
+                        dma-names = "rx", "tx";
                        status = "disabled";
                };
                sdi1_per2@80118000 {
                        compatible = "arm,pl18x", "arm,primecell";
                        reg = <0x80118000 0x1000>;
-                        interrupts = <0 50 0x4>;
+                        interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
+                        dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */
+                               <&dma 32 0 0x0>; /* Logical - MemToDev */
+                        dma-names = "rx", "tx";
                        status = "disabled";
                };
                sdi2_per3@80005000 {
                        compatible = "arm,pl18x", "arm,primecell";
                        reg = <0x80005000 0x1000>;
-                        interrupts = <0 41 0x4>;
+                        interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
+                        dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */
+                               <&dma 28 0 0x0>; /* Logical - MemToDev */
+                        dma-names = "rx", "tx";
                        status = "disabled";
                };
                sdi3_per2@80119000 {
                        compatible = "arm,pl18x", "arm,primecell";
                        reg = <0x80119000 0x1000>;
-                        interrupts = <0 59 0x4>;
+                        interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
                        status = "disabled";
                };
                sdi4_per2@80114000 {
                        compatible = "arm,pl18x", "arm,primecell";
                        reg = <0x80114000 0x1000>;
-                        interrupts = <0 99 0x4>;
+                        interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
+                        dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */
+                               <&dma 42 0 0x0>; /* Logical - MemToDev */
+                        dma-names = "rx", "tx";
                        status = "disabled";
                };
                sdi5_per3@80008000 {
                        compatible = "arm,pl18x", "arm,primecell";
                        reg = <0x80008000 0x1000>;
-                        interrupts = <0 100 0x4>;
+                        interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
                        status = "disabled";
                };
                msp0: msp@80123000 {
                        compatible = "stericsson,ux500-msp-i2s";
                        reg = <0x80123000 0x1000>;
-                        interrupts = <0 31 0x4>;
+                        interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
                        v-ape-supply = <&db8500_vape_reg>;
                        status = "disabled";
                };
@@ -634,7 +710,7 @@
                msp1: msp@80124000 {
                        compatible = "stericsson,ux500-msp-i2s";
                        reg = <0x80124000 0x1000>;
-                        interrupts = <0 62 0x4>;
+                        interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
                        v-ape-supply = <&db8500_vape_reg>;
                        status = "disabled";
                };
@@ -643,7 +719,7 @@
                msp2: msp@80117000 {
                        compatible = "stericsson,ux500-msp-i2s";
                        reg = <0x80117000 0x1000>;
-                        interrupts = <0 98 0x4>;
+                        interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
                        v-ape-supply = <&db8500_vape_reg>;
                        status = "disabled";
                };
@@ -651,7 +727,7 @@
                msp3: msp@80125000 {
                        compatible = "stericsson,ux500-msp-i2s";
                        reg = <0x80125000 0x1000>;
-                        interrupts = <0 62 0x4>;
+                        interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
                        v-ape-supply = <&db8500_vape_reg>;
                        status = "disabled";
                };
@@ -686,5 +762,20 @@
                        status = "disabled";
                };
+                cryp@a03cb000 {
+                        compatible = "stericsson,ux500-cryp";
+                        reg = <0xa03cb000 0x1000>;
+                        interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
+                        v-ape-supply = <&db8500_vape_reg>;
+                };
+                hash@a03c2000 {
+                        compatible = "stericsson,ux500-hash";
+                        reg = <0xa03c2000 0x1000>;
+                        v-ape-supply = <&db8500_vape_reg>;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts
index 7e3065abd751..5cae2ab69762 100644
--- a/arch/arm/boot/dts/dove-cubox.dts
+++ b/arch/arm/boot/dts/dove-cubox.dts
@@ -44,11 +44,60 @@
                        gpio = <&gpio0 1 0>;
                };
        };
+        clocks {
+                /* 25MHz reference crystal */
+                ref25: oscillator {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <25000000>;
+                };
+        };
 };
 &uart0 { status = "okay"; };
 &sata0 { status = "okay"; };
-&i2c0 { status = "okay"; };
+&i2c0 {
+        status = "okay";
+        clock-frequency = <100000>;
+        si5351: clock-generator {
+                compatible = "silabs,si5351a-msop";
+                reg = <0x60>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                #clock-cells = <1>;
+                /* connect xtal input to 25MHz reference */
+                clocks = <&ref25>;
+                /* connect xtal input as source of pll0 and pll1 */
+                silabs,pll-source = <0 0>, <1 0>;
+                clkout0 {
+                        reg = <0>;
+                        silabs,drive-strength = <8>;
+                        silabs,multisynth-source = <0>;
+                        silabs,clock-source = <0>;
+                        silabs,pll-master;
+                };
+                clkout1 {
+                        reg = <1>;
+                        silabs,drive-strength = <8>;
+                        silabs,multisynth-source = <1>;
+                        silabs,clock-source = <0>;
+                        silabs,pll-master;
+                };
+                clkout2 {
+                        reg = <2>;
+                        silabs,multisynth-source = <1>;
+                        silabs,clock-source = <0>;
+                };
+        };
+};
 &sdio0 {
        status = "okay";
diff --git a/arch/arm/boot/dts/ecx-common.dtsi b/arch/arm/boot/dts/ecx-common.dtsi
index d61b535f682a..e8559b753c9d 100644
--- a/arch/arm/boot/dts/ecx-common.dtsi
+++ b/arch/arm/boot/dts/ecx-common.dtsi
@@ -33,6 +33,8 @@
                        calxeda,port-phys = <&combophy5 0 &combophy0 0
                                             &combophy0 1 &combophy0 2
                                             &combophy0 3>;
+                        calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>;
+                        calxeda,led-order = <4 0 1 2 3>;
                };
                sdhci@ffe0e000 {
diff --git a/arch/arm/boot/dts/ethernut5.dts b/arch/arm/boot/dts/ethernut5.dts
index 1ea9d34460a4..143b6d25bc80 100644
--- a/arch/arm/boot/dts/ethernut5.dts
+++ b/arch/arm/boot/dts/ethernut5.dts
@@ -6,7 +6,7 @@
 * Licensed under GPLv2.
 */
 /dts-v1/;
-/include/ "at91sam9260.dtsi"
+#include "at91sam9260.dtsi"
 / {
        model = "Ethernut 5";
@@ -40,7 +40,7 @@
                        };
                        usb1: gadget@fffa4000 {
-                                atmel,vbus-gpio = <&pioC 5 0>;
+                                atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
                                status = "okay";
                        };
                };
@@ -52,7 +52,7 @@
                        status = "okay";
                        gpios = <0
-                                 &pioC 14 0
+                                 &pioC 14 GPIO_ACTIVE_HIGH
                                 0
                                >;
diff --git a/arch/arm/boot/dts/evk-pro3.dts b/arch/arm/boot/dts/evk-pro3.dts
index 96e50f569433..4d829685fdfb 100644
--- a/arch/arm/boot/dts/evk-pro3.dts
+++ b/arch/arm/boot/dts/evk-pro3.dts
@@ -9,7 +9,7 @@
 /dts-v1/;
-/include/ "ge863-pro3.dtsi"
+#include "ge863-pro3.dtsi"
 / {
        model = "Telit EVK-PRO3 for Telit GE863-PRO3";
@@ -31,7 +31,7 @@
                        };
                        usb1: gadget@fffa4000 {
-                                atmel,vbus-gpio = <&pioC 5 0>;
+                                atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
                                status = "okay";
                        };
@@ -50,4 +50,4 @@
                status = "okay";
        };
-};
-\ No newline at end of file
+};
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 359694c78918..3f94fe8e3706 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -19,7 +19,7 @@
 * published by the Free Software Foundation.
 */
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 / {
        interrupt-parent = <&gic>;
@@ -160,6 +160,8 @@
                reg = <0x13400000 0x10000>;
                interrupts = <0 94 0>;
                samsung,power-domain = <&pd_mfc>;
+                clocks = <&clock 170>, <&clock 273>;
+                clock-names = "sclk_mfc", "mfc";
                status = "disabled";
        };
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index 524b90846df5..382d8c7e2906 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -15,7 +15,7 @@
 */
 /dts-v1/;
-/include/ "exynos4210.dtsi"
+#include "exynos4210.dtsi"
 / {
        model = "Insignal Origen evaluation board based on Exynos4210";
@@ -41,6 +41,10 @@
                enable-active-high;
        };
+        tmu@100C0000 {
+                status = "okay";
+        };
        sdhci@12530000 {
                bus-width = <4>;
                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
@@ -83,6 +87,150 @@
                status = "okay";
        };
+        i2c@13860000 {
+                status = "okay";
+                samsung,i2c-sda-delay = <100>;
+                samsung,i2c-max-bus-freq = <20000>;
+                pinctrl-0 = <&i2c0_bus>;
+                pinctrl-names = "default";
+                max8997_pmic@66 {
+                        compatible = "maxim,max8997-pmic";
+                        reg = <0x66>;
+                        interrupt-parent = <&gpx0>;
+                        interrupts = <4 0>, <3 0>;
+                        max8997,pmic-buck1-dvs-voltage = <1350000>;
+                        max8997,pmic-buck2-dvs-voltage = <1100000>;
+                        max8997,pmic-buck5-dvs-voltage = <1200000>;
+                        regulators {
+                                ldo1_reg: LDO1 {
+                                        regulator-name = "VDD_ABB_3.3V";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+                                ldo2_reg: LDO2 {
+                                        regulator-name = "VDD_ALIVE_1.1V";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                };
+                                ldo3_reg: LDO3 {
+                                        regulator-name = "VMIPI_1.1V";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                };
+                                ldo4_reg: LDO4 {
+                                        regulator-name = "VDD_RTC_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+                                ldo6_reg: LDO6 {
+                                        regulator-name = "VMIPI_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+                                ldo7_reg: LDO7 {
+                                        regulator-name = "VDD_AUD_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                                ldo8_reg: LDO8 {
+                                        regulator-name = "VADC_3.3V";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+                                ldo9_reg: LDO9 {
+                                        regulator-name = "DVDD_SWB_2.8V";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                };
+                                ldo10_reg: LDO10 {
+                                        regulator-name = "VDD_PLL_1.1V";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                };
+                                ldo11_reg: LDO11 {
+                                        regulator-name = "VDD_AUD_3V";
+                                        regulator-min-microvolt = <3000000>;
+                                        regulator-max-microvolt = <3000000>;
+                                };
+                                ldo14_reg: LDO14 {
+                                        regulator-name = "AVDD18_SWB_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+                                ldo17_reg: LDO17 {
+                                        regulator-name = "VDD_SWB_3.3V";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+                                ldo21_reg: LDO21 {
+                                        regulator-name = "VDD_MIF_1.2V";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+                                buck1_reg: BUCK1 {
+                                        regulator-name = "VDD_ARM_1.2V";
+                                        regulator-min-microvolt = <950000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                buck2_reg: BUCK2 {
+                                        regulator-name = "VDD_INT_1.1V";
+                                        regulator-min-microvolt = <900000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                buck3_reg: BUCK3 {
+                                        regulator-name = "VDD_G3D_1.1V";
+                                        regulator-min-microvolt = <900000>;
+                                        regulator-max-microvolt = <1100000>;
+                                };
+                                buck5_reg: BUCK5 {
+                                        regulator-name = "VDDQ_M1M2_1.2V";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+                                buck7_reg: BUCK7 {
+                                        regulator-name = "VDD_LCD_3.3V";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                };
+                        };
+                };
+        };
        gpio_keys {
                compatible = "gpio-keys";
                #address-cells = <1>;
@@ -143,4 +291,25 @@
                        clock-frequency = <24000000>;
                };
        };
+        fimd@11c00000 {
+                pinctrl-0 = <&lcd_en &lcd_clk &lcd_data24 &pwm0_out>;
+                pinctrl-names = "default";
+                status = "okay";
+        };
+        display-timings {
+                native-mode = <&timing0>;
+                timing0: timing {
+                        clock-frequency = <50000>;
+                        hactive = <1024>;
+                        vactive = <600>;
+                        hfront-porch = <64>;
+                        hback-porch = <16>;
+                        hsync-len = <48>;
+                        vback-porch = <64>;
+                        vfront-porch = <16>;
+                        vsync-len = <3>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
index 55a2efb763d1..553bceae8967 100644
--- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
@@ -330,6 +330,95 @@
                        samsung,pin-pud = <3>;
                        samsung,pin-drv = <0>;
                };
+                pwm0_out: pwm0-out {
+                        samsung,pins = "gpd0-0";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                pwm1_out: pwm1-out {
+                        samsung,pins = "gpd0-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                pwm2_out: pwm2-out {
+                        samsung,pins = "gpd0-2";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                pwm3_out: pwm3-out {
+                        samsung,pins = "gpd0-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                lcd_ctrl: lcd-ctrl {
+                        samsung,pins = "gpd0-0", "gpd0-1";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                lcd_sync: lcd-sync {
+                        samsung,pins = "gpf0-0", "gpf0-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                lcd_en: lcd-en {
+                        samsung,pins = "gpe3-4";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                lcd_clk: lcd-clk {
+                        samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                lcd_data16: lcd-data-width16 {
+                        samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2",
+                                        "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0",
+                                        "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7",
+                                        "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                lcd_data18: lcd-data-width18 {
+                        samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1",
+                                        "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7",
+                                        "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
+                                        "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1",
+                                        "gpf3-2", "gpf3-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                lcd_data24: lcd-data-width24 {
+                        samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7",
+                                        "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3",
+                                        "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7",
+                                        "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
+                                        "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7",
+                                        "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
        };
        pinctrl@11000000 {
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 91332b72acf5..9c01b718d29d 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -15,7 +15,7 @@
 */
 /dts-v1/;
-/include/ "exynos4210.dtsi"
+#include "exynos4210.dtsi"
 / {
        model = "Samsung smdkv310 evaluation board based on Exynos4210";
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index 9a14484c7bb1..94eebffe3044 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -13,7 +13,7 @@
 */
 /dts-v1/;
-/include/ "exynos4210.dtsi"
+#include "exynos4210.dtsi"
 / {
        model = "Samsung Trats based on Exynos4210";
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index 345cdb51dcb7..889cdada1ce9 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -13,7 +13,7 @@
 */
 /dts-v1/;
-/include/ "exynos4210.dtsi"
+#include "exynos4210.dtsi"
 / {
        model = "Samsung Universal C210 based on Exynos4210 rev0";
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 54710de82908..b7f358a93bcb 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -19,8 +19,8 @@
 * published by the Free Software Foundation.
 */
-/include/ "exynos4.dtsi"
+#include "exynos4.dtsi"
-/include/ "exynos4210-pinctrl.dtsi"
+#include "exynos4210-pinctrl.dtsi"
 / {
        compatible = "samsung,exynos4210";
@@ -112,12 +112,17 @@
                interrupt-parent = <&combiner>;
                reg = <0x100C0000 0x100>;
                interrupts = <2 4>;
+                clocks = <&clock 383>;
+                clock-names = "tmu_apbif";
+                status = "disabled";
        };
        g2d@12800000 {
                compatible = "samsung,s5pv210-g2d";
                reg = <0x12800000 0x1000>;
                interrupts = <0 89 0>;
+                clocks = <&clock 177>, <&clock 277>;
+                clock-names = "sclk_fimg2d", "fimg2d";
                status = "disabled";
        };
 };
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
index c0f60f49cea6..6f34d7f6ba7e 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -17,7 +17,7 @@
 * published by the Free Software Foundation.
 */
-/include/ "exynos4x12.dtsi"
+#include "exynos4x12.dtsi"
 / {
        compatible = "samsung,exynos4212";
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 53bc8bf77984..46c678ee119c 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -12,7 +12,7 @@
 */
 /dts-v1/;
-/include/ "exynos4412.dtsi"
+#include "exynos4412.dtsi"
 / {
        model = "Hardkernel ODROID-X board based on Exynos4412";
@@ -43,6 +43,7 @@
                #size-cells = <0>;
                pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
                pinctrl-names = "default";
+                vmmc-supply = <&ldo20_reg &buck8_reg>;
                status = "okay";
                num-slots = <1>;
@@ -78,6 +79,7 @@
                bus-width = <4>;
                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
                pinctrl-names = "default";
+                vmmc-supply = <&ldo4_reg &ldo21_reg>;
                status = "okay";
        };
@@ -108,4 +110,199 @@
                        clock-frequency = <24000000>;
                };
        };
+        i2c@13860000 {
+                pinctrl-0 = <&i2c0_bus>;
+                pinctrl-names = "default";
+                status = "okay";
+                max77686: pmic@09 {
+                        compatible = "maxim,max77686";
+                        reg = <0x09>;
+                        voltage-regulators {
+                                ldo1_reg: LDO1 {
+                                        regulator-name = "VDD_ALIVE_1.0V";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+                                ldo2_reg: LDO2 {
+                                        regulator-name = "VDDQ_M1_2_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+                                ldo3_reg: LDO3 {
+                                        regulator-name = "VDDQ_EXT_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+                                ldo4_reg: LDO4 {
+                                        regulator-name = "VDDQ_MMC2_2.8V";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                ldo5_reg: LDO5 {
+                                        regulator-name = "VDDQ_MMC1_3_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                ldo6_reg: LDO6 {
+                                        regulator-name = "VDD10_MPLL_1.0V";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+                                ldo7_reg: LDO7 {
+                                        regulator-name = "VDD10_XPLL_1.0V";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+                                ldo11_reg: LDO11 {
+                                        regulator-name = "VDD18_ABB1_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+                                ldo12_reg: LDO12 {
+                                        regulator-name = "VDD33_USB_3.3V";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                ldo13_reg: LDO13 {
+                                        regulator-name = "VDDQ_C2C_W_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                ldo14_reg: LDO14 {
+                                        regulator-name = "VDD18_ABB0_2_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                ldo15_reg: LDO15 {
+                                        regulator-name = "VDD10_HSIC_1.0V";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                ldo16_reg: LDO16 {
+                                        regulator-name = "VDD18_HSIC_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                ldo20_reg: LDO20 {
+                                        regulator-name = "LDO20_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-boot-on;
+                                };
+                                ldo21_reg: LDO21 {
+                                        regulator-name = "LDO21_3.3V";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                ldo25_reg: LDO25 {
+                                        regulator-name = "VDDQ_LCD_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                buck1_reg: BUCK1 {
+                                        regulator-name = "vdd_mif";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                buck2_reg: BUCK2 {
+                                        regulator-name = "vdd_arm";
+                                        regulator-min-microvolt = <900000>;
+                                        regulator-max-microvolt = <1300000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                buck3_reg: BUCK3 {
+                                        regulator-name = "vdd_int";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                buck4_reg: BUCK4 {
+                                        regulator-name = "vdd_g3d";
+                                        regulator-min-microvolt = <900000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-microvolt-offset = <50000>;
+                                };
+                                buck5_reg: BUCK5 {
+                                        regulator-name = "VDDQ_CKEM1_2_1.2V";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                buck6_reg: BUCK6 {
+                                        regulator-name = "BUCK6_1.35V";
+                                        regulator-min-microvolt = <1350000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                buck7_reg: BUCK7 {
+                                        regulator-name = "BUCK7_2.0V";
+                                        regulator-min-microvolt = <2000000>;
+                                        regulator-max-microvolt = <2000000>;
+                                        regulator-always-on;
+                                };
+                                buck8_reg: BUCK8 {
+                                        regulator-name = "BUCK8_2.8V";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                };
+                        };
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
index 1c21bad32ca9..7993641cb32a 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -13,7 +13,7 @@
 */
 /dts-v1/;
-/include/ "exynos4412.dtsi"
+#include "exynos4412.dtsi"
 / {
        model = "Insignal Origen evaluation board based on Exynos4412";
@@ -36,6 +36,72 @@
                enable-active-high;
        };
+        pinctrl@11000000 {
+                keypad_rows: keypad-rows {
+                        samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                keypad_cols: keypad-cols {
+                        samsung,pins = "gpx1-0", "gpx1-1";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+        };
+        keypad@100A0000 {
+                samsung,keypad-num-rows = <3>;
+                samsung,keypad-num-columns = <2>;
+                linux,keypad-no-autorepeat;
+                linux,keypad-wakeup;
+                pinctrl-0 = <&keypad_rows &keypad_cols>;
+                pinctrl-names = "default";
+                status = "okay";
+                key_home {
+                        keypad,row = <0>;
+                        keypad,column = <0>;
+                        linux,code = <102>;
+                };
+                key_down {
+                        keypad,row = <0>;
+                        keypad,column = <1>;
+                        linux,code = <108>;
+                };
+                key_up {
+                        keypad,row = <1>;
+                        keypad,column = <0>;
+                        linux,code = <103>;
+                };
+                key_menu {
+                        keypad,row = <1>;
+                        keypad,column = <1>;
+                        linux,code = <139>;
+                };
+                key_back {
+                        keypad,row = <2>;
+                        keypad,column = <0>;
+                        linux,code = <158>;
+                };
+                key_enter {
+                        keypad,row = <2>;
+                        keypad,column = <1>;
+                        linux,code = <28>;
+                };
+        };
+        g2d@10800000 {
+                status = "okay";
+        };
        sdhci@12530000 {
                bus-width = <4>;
                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts
index dd564310d4a5..ad316a1ee9e0 100644
--- a/arch/arm/boot/dts/exynos4412-smdk4412.dts
+++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts
@@ -13,7 +13,7 @@
 */
 /dts-v1/;
-/include/ "exynos4412.dtsi"
+#include "exynos4412.dtsi"
 / {
        model = "Samsung SMDK evaluation board based on Exynos4412";
@@ -31,8 +31,91 @@
                status = "okay";
        };
-        g2d@10800000 {
+        pinctrl@11000000 {
+                keypad_rows: keypad-rows {
+                        samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                keypad_cols: keypad-cols {
+                        samsung,pins = "gpx1-0", "gpx1-1", "gpx1-2", "gpx1-3",
+                                       "gpx1-4", "gpx1-5", "gpx1-6", "gpx1-7";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+        };
+        keypad@100A0000 {
+                samsung,keypad-num-rows = <3>;
+                samsung,keypad-num-columns = <8>;
+                linux,keypad-no-autorepeat;
+                linux,keypad-wakeup;
+                pinctrl-0 = <&keypad_rows &keypad_cols>;
+                pinctrl-names = "default";
                status = "okay";
+                key_1 {
+                        keypad,row = <1>;
+                        keypad,column = <3>;
+                        linux,code = <2>;
+                };
+                key_2 {
+                        keypad,row = <1>;
+                        keypad,column = <4>;
+                        linux,code = <3>;
+                };
+                key_3 {
+                        keypad,row = <1>;
+                        keypad,column = <5>;
+                        linux,code = <4>;
+                };
+                key_4 {
+                        keypad,row = <1>;
+                        keypad,column = <6>;
+                        linux,code = <5>;
+                };
+                key_5 {
+                        keypad,row = <1>;
+                        keypad,column = <7>;
+                        linux,code = <6>;
+                };
+                key_A {
+                        keypad,row = <2>;
+                        keypad,column = <6>;
+                        linux,code = <30>;
+                };
+                key_B {
+                        keypad,row = <2>;
+                        keypad,column = <7>;
+                        linux,code = <48>;
+                };
+                key_C {
+                        keypad,row = <0>;
+                        keypad,column = <5>;
+                        linux,code = <46>;
+                };
+                key_D {
+                        keypad,row = <2>;
+                        keypad,column = <5>;
+                        linux,code = <32>;
+                };
+                key_E {
+                        keypad,row = <0>;
+                        keypad,column = <7>;
+                        linux,code = <18>;
+                };
        };
        sdhci@12530000 {
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index 270b389e0a1b..e743e677a9e2 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -17,7 +17,7 @@
 * published by the Free Software Foundation.
 */
-/include/ "exynos4x12.dtsi"
+#include "exynos4x12.dtsi"
 / {
        compatible = "samsung,exynos4412";
diff --git a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
index 099cec79e2ae..704290f7c5c0 100644
--- a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
@@ -778,62 +778,6 @@
                        samsung,pin-drv = <3>;
                };
-                keypad_col0: keypad-col0 {
-                        samsung,pins = "gpl2-0";
-                        samsung,pin-function = <3>;
-                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
-                };
-                keypad_col1: keypad-col1 {
-                        samsung,pins = "gpl2-1";
-                        samsung,pin-function = <3>;
-                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
-                };
-                keypad_col2: keypad-col2 {
-                        samsung,pins = "gpl2-2";
-                        samsung,pin-function = <3>;
-                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
-                };
-                keypad_col3: keypad-col3 {
-                        samsung,pins = "gpl2-3";
-                        samsung,pin-function = <3>;
-                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
-                };
-                keypad_col4: keypad-col4 {
-                        samsung,pins = "gpl2-4";
-                        samsung,pin-function = <3>;
-                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
-                };
-                keypad_col5: keypad-col5 {
-                        samsung,pins = "gpl2-5";
-                        samsung,pin-function = <3>;
-                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
-                };
-                keypad_col6: keypad-col6 {
-                        samsung,pins = "gpl2-6";
-                        samsung,pin-function = <3>;
-                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
-                };
-                keypad_col7: keypad-col7 {
-                        samsung,pins = "gpl2-7";
-                        samsung,pin-function = <3>;
-                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
-                };
                cam_port_b: cam-port-b {
                        samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3",
                                        "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7",
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index e3380a7a285c..01da194ba329 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -17,8 +17,8 @@
 * published by the Free Software Foundation.
 */
-/include/ "exynos4.dtsi"
+#include "exynos4.dtsi"
-/include/ "exynos4x12-pinctrl.dtsi"
+#include "exynos4x12-pinctrl.dtsi"
 / {
        aliases {
@@ -28,14 +28,6 @@
                pinctrl3 = &pinctrl_3;
        };
-        combiner:interrupt-controller@10440000 {
-                interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
-                             <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
-                             <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
-                             <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
-                             <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>;
-        };
        clock: clock-controller@0x10030000 {
                compatible = "samsung,exynos4412-clock";
                reg = <0x10030000 0x20000>;
@@ -77,6 +69,8 @@
                compatible = "samsung,exynos4212-g2d";
                reg = <0x10800000 0x1000>;
                interrupts = <0 89 0>;
+                clocks = <&clock 177>, <&clock 277>;
+                clock-names = "sclk_fimg2d", "fimg2d";
                status = "disabled";
        };
 };
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
new file mode 100644
index 000000000000..f65e124c04a6
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -0,0 +1,111 @@
+/*
+ * Samsung's Exynos5 SoC series common device tree source
+ *
+ * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Samsung's Exynos5 SoC series device nodes are listed in this file. Particular
+ * SoCs from Exynos5 series can include this file and provide values for SoCs
+ * specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include "skeleton.dtsi"
+/ {
+        interrupt-parent = <&gic>;
+        chipid@10000000 {
+                compatible = "samsung,exynos4210-chipid";
+                reg = <0x10000000 0x100>;
+        };
+        combiner:interrupt-controller@10440000 {
+                compatible = "samsung,exynos4210-combiner";
+                #interrupt-cells = <2>;
+                interrupt-controller;
+                samsung,combiner-nr = <32>;
+                reg = <0x10440000 0x1000>;
+                interrupts =    <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+                                <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+                                <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+                                <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
+                                <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
+                                <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
+                                <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
+                                <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
+        };
+        gic:interrupt-controller@10481000 {
+                compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                interrupt-controller;
+                reg =   <0x10481000 0x1000>,
+                        <0x10482000 0x1000>,
+                        <0x10484000 0x2000>,
+                        <0x10486000 0x2000>;
+                interrupts = <1 9 0xf04>;
+        };
+        dwmmc_0: dwmmc0@12200000 {
+                compatible = "samsung,exynos5250-dw-mshc";
+                interrupts = <0 75 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+        dwmmc_1: dwmmc1@12210000 {
+                compatible = "samsung,exynos5250-dw-mshc";
+                interrupts = <0 76 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+        dwmmc_2: dwmmc2@12220000 {
+                compatible = "samsung,exynos5250-dw-mshc";
+                interrupts = <0 77 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+        serial@12C00000 {
+                compatible = "samsung,exynos4210-uart";
+                reg = <0x12C00000 0x100>;
+                interrupts = <0 51 0>;
+        };
+        serial@12C10000 {
+                compatible = "samsung,exynos4210-uart";
+                reg = <0x12C10000 0x100>;
+                interrupts = <0 52 0>;
+        };
+        serial@12C20000 {
+                compatible = "samsung,exynos4210-uart";
+                reg = <0x12C20000 0x100>;
+                interrupts = <0 53 0>;
+        };
+        serial@12C30000 {
+                compatible = "samsung,exynos4210-uart";
+                reg = <0x12C30000 0x100>;
+                interrupts = <0 54 0>;
+        };
+        rtc {
+                compatible = "samsung,s3c6410-rtc";
+                reg = <0x101E0000 0x100>;
+                interrupts = <0 43 0>, <0 44 0>;
+                status = "disabled";
+        };
+        watchdog {
+                compatible = "samsung,s3c2410-wdt";
+                reg = <0x101D0000 0x100>;
+                interrupts = <0 42 0>;
+                status = "disabled";
+        };
+};
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index 02cfc76d002f..abc7272c7afd 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -10,7 +10,7 @@
 */
 /dts-v1/;
-/include/ "exynos5250.dtsi"
+#include "exynos5250.dtsi"
 / {
        model = "Insignal Arndale evaluation board based on EXYNOS5250";
@@ -449,4 +449,35 @@
                        clock-frequency = <24000000>;
                };
        };
+        dp-controller {
+                samsung,color-space = <0>;
+                samsung,dynamic-range = <0>;
+                samsung,ycbcr-coeff = <0>;
+                samsung,color-depth = <1>;
+                samsung,link-rate = <0x0a>;
+                samsung,lane-count = <4>;
+        };
+        fimd: fimd@14400000 {
+                display-timings {
+                        native-mode = <&timing0>;
+                        timing0: timing@0 {
+                                /* 2560x1600 DP panel */
+                                clock-frequency = <50000>;
+                                hactive = <2560>;
+                                vactive = <1600>;
+                                hfront-porch = <48>;
+                                hback-porch = <80>;
+                                hsync-len = <32>;
+                                vback-porch = <16>;
+                                vfront-porch = <8>;
+                                vsync-len = <6>;
+                        };
+                };
+        };
+        rtc {
+                status = "okay";
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
index ded558bb0f3b..724a22f9b1c8 100644
--- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
@@ -553,6 +553,13 @@
                        samsung,pin-pud = <0>;
                        samaung,pin-drv = <0>;
                };
+                dp_hpd: dp_hpd {
+                        samsung,pins = "gpx0-7";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samaung,pin-drv = <0>;
+                };
        };
        pinctrl@13400000 {
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 3e0c792e2767..49f18c24a576 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -10,7 +10,7 @@
 */
 /dts-v1/;
-/include/ "exynos5250.dtsi"
+#include "exynos5250.dtsi"
 / {
        model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
@@ -37,6 +37,30 @@
                };
        };
+        vdd:fixed-regulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "vdd-supply";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                regulator-always-on;
+        };
+        dbvdd:fixed-regulator@1 {
+                compatible = "regulator-fixed";
+                regulator-name = "dbvdd-supply";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+        };
+        spkvdd:fixed-regulator@2 {
+                compatible = "regulator-fixed";
+                regulator-name = "spkvdd-supply";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-always-on;
+        };
        i2c@12C70000 {
                samsung,i2c-sda-delay = <100>;
                samsung,i2c-max-bus-freq = <20000>;
@@ -47,8 +71,17 @@
                };
                wm8994: wm8994@1a {
-                         compatible = "wlf,wm8994";
+                        compatible = "wlf,wm8994";
-                         reg = <0x1a>;
+                        reg = <0x1a>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        AVDD2-supply = <&vdd>;
+                        CPVDD-supply = <&vdd>;
+                        DBVDD-supply = <&dbvdd>;
+                        SPKVDD1-supply = <&spkvdd>;
+                        SPKVDD2-supply = <&spkvdd>;
                };
        };
@@ -72,7 +105,7 @@
                samsung,i2c-max-bus-freq = <66000>;
                hdmiddc@50 {
-                        compatible = "samsung,exynos5-hdmiddc";
+                        compatible = "samsung,exynos4210-hdmiddc";
                        reg = <0x50>;
                };
        };
@@ -102,7 +135,7 @@
                samsung,i2c-max-bus-freq = <66000>;
                hdmiphy@38 {
-                        compatible = "samsung,exynos5-hdmiphy";
+                        compatible = "samsung,exynos4212-hdmiphy";
                        reg = <0x38>;
                };
        };
@@ -224,6 +257,9 @@
                samsung,color-depth = <1>;
                samsung,link-rate = <0x0a>;
                samsung,lane-count = <4>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&dp_hpd>;
        };
        display-timings {
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index d449feb7e143..e79331dba12d 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -9,8 +9,8 @@
 */
 /dts-v1/;
-/include/ "exynos5250.dtsi"
+#include "exynos5250.dtsi"
-/include/ "cros5250-common.dtsi"
+#include "cros5250-common.dtsi"
 / {
        model = "Google Snow";
@@ -171,6 +171,10 @@
                };
        };
+        rtc {
+                status = "okay";
+        };
        /*
         * On Snow we've got SIP WiFi and so can keep drive strengths low to
         * reduce EMI.
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index fc9fb3d526e2..ef57277fc38f 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -17,12 +17,13 @@
 * published by the Free Software Foundation.
 */
-/include/ "skeleton.dtsi"
+#include "exynos5.dtsi"
-/include/ "exynos5250-pinctrl.dtsi"
+#include "exynos5250-pinctrl.dtsi"
+#include <dt-bindings/clk/exynos-audss-clk.h>
 / {
        compatible = "samsung,exynos5250";
-        interrupt-parent = <&gic>;
        aliases {
                spi0 = &spi_0;
@@ -51,9 +52,20 @@
                pinctrl3 = &pinctrl_3;
        };
-        chipid@10000000 {
+        cpus {
-                compatible = "samsung,exynos4210-chipid";
+                #address-cells = <1>;
-                reg = <0x10000000 0x100>;
+                #size-cells = <0>;
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0>;
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <1>;
+                };
        };
        pd_gsc: gsc-power-domain@0x10044000 {
@@ -72,15 +84,10 @@
                #clock-cells = <1>;
        };
-        gic:interrupt-controller@10481000 {
+        clock_audss: audss-clock-controller@3810000 {
-                compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+                compatible = "samsung,exynos5250-audss-clock";
-                #interrupt-cells = <3>;
+                reg = <0x03810000 0x0C>;
-                interrupt-controller;
+                #clock-cells = <1>;
-                reg = <0x10481000 0x1000>,
-                      <0x10482000 0x1000>,
-                      <0x10484000 0x2000>,
-                      <0x10486000 0x2000>;
-                interrupts = <1 9 0xf04>;
        };
        timer {
@@ -91,22 +98,6 @@
                             <1 10 0xf08>;
        };
-        combiner:interrupt-controller@10440000 {
-                compatible = "samsung,exynos4210-combiner";
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                samsung,combiner-nr = <32>;
-                reg = <0x10440000 0x1000>;
-                interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
-                             <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
-                             <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
-                             <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
-                             <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
-                             <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
-                             <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
-                             <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
-        };
        mct@101C0000 {
                compatible = "samsung,exynos4210-mct";
                reg = <0x101C0000 0x800>;
@@ -168,9 +159,6 @@
        };
        watchdog {
-                compatible = "samsung,s3c2410-wdt";
-                reg = <0x101D0000 0x100>;
-                interrupts = <0 42 0>;
                clocks = <&clock 336>;
                clock-names = "watchdog";
        };
@@ -183,12 +171,8 @@
        };
        rtc {
-                compatible = "samsung,s3c6410-rtc";
-                reg = <0x101E0000 0x100>;
-                interrupts = <0 43 0>, <0 44 0>;
                clocks = <&clock 337>;
                clock-names = "rtc";
-                status = "disabled";
        };
        tmu@10060000 {
@@ -200,33 +184,21 @@
        };
        serial@12C00000 {
-                compatible = "samsung,exynos4210-uart";
-                reg = <0x12C00000 0x100>;
-                interrupts = <0 51 0>;
                clocks = <&clock 289>, <&clock 146>;
                clock-names = "uart", "clk_uart_baud0";
        };
        serial@12C10000 {
-                compatible = "samsung,exynos4210-uart";
-                reg = <0x12C10000 0x100>;
-                interrupts = <0 52 0>;
                clocks = <&clock 290>, <&clock 147>;
                clock-names = "uart", "clk_uart_baud0";
        };
        serial@12C20000 {
-                compatible = "samsung,exynos4210-uart";
-                reg = <0x12C20000 0x100>;
-                interrupts = <0 53 0>;
                clocks = <&clock 291>, <&clock 148>;
                clock-names = "uart", "clk_uart_baud0";
        };
        serial@12C30000 {
-                compatible = "samsung,exynos4210-uart";
-                reg = <0x12C30000 0x100>;
-                interrupts = <0 54 0>;
                clocks = <&clock 292>, <&clock 149>;
                clock-names = "uart", "clk_uart_baud0";
        };
@@ -405,31 +377,19 @@
        };
        dwmmc_0: dwmmc0@12200000 {
-                compatible = "samsung,exynos5250-dw-mshc";
                reg = <0x12200000 0x1000>;
-                interrupts = <0 75 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
                clocks = <&clock 280>, <&clock 139>;
                clock-names = "biu", "ciu";
        };
        dwmmc_1: dwmmc1@12210000 {
-                compatible = "samsung,exynos5250-dw-mshc";
                reg = <0x12210000 0x1000>;
-                interrupts = <0 76 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
                clocks = <&clock 281>, <&clock 140>;
                clock-names = "biu", "ciu";
        };
        dwmmc_2: dwmmc2@12220000 {
-                compatible = "samsung,exynos5250-dw-mshc";
                reg = <0x12220000 0x1000>;
-                interrupts = <0 77 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
                clocks = <&clock 282>, <&clock 141>;
                clock-names = "biu", "ciu";
        };
@@ -451,6 +411,10 @@
                        &pdma0 9
                        &pdma0 8>;
                dma-names = "tx", "rx", "tx-sec";
+                clocks = <&clock_audss EXYNOS_I2S_BUS>,
+                        <&clock_audss EXYNOS_I2S_BUS>,
+                        <&clock_audss EXYNOS_SCLK_I2S>;
+                clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
                samsung,supports-6ch;
                samsung,supports-rstclr;
                samsung,supports-secdai;
@@ -465,6 +429,8 @@
                dmas = <&pdma1 12
                        &pdma1 11>;
                dma-names = "tx", "rx";
+                clocks = <&clock 307>, <&clock 157>;
+                clock-names = "iis", "i2s_opclk0";
                pinctrl-names = "default";
                pinctrl-0 = <&i2s1_bus>;
        };
@@ -475,10 +441,42 @@
                dmas = <&pdma0 12
                        &pdma0 11>;
                dma-names = "tx", "rx";
+                clocks = <&clock 308>, <&clock 158>;
+                clock-names = "iis", "i2s_opclk0";
                pinctrl-names = "default";
                pinctrl-0 = <&i2s2_bus>;
        };
+        usb@12000000 {
+                compatible = "samsung,exynos5250-dwusb3";
+                clocks = <&clock 286>;
+                clock-names = "usbdrd30";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                dwc3 {
+                        compatible = "synopsys,dwc3";
+                        reg = <0x12000000 0x10000>;
+                        interrupts = <0 72 0>;
+                        usb-phy = <&usb2_phy &usb3_phy>;
+                };
+        };
+        usb3_phy: usbphy@12100000 {
+                compatible = "samsung,exynos5250-usb3phy";
+                reg = <0x12100000 0x100>;
+                clocks = <&clock 1>, <&clock 286>;
+                clock-names = "ext_xtal", "usbdrd30";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                usbphy-sys {
+                        reg = <0x10040704 0x8>;
+                };
+        };
        usb@12110000 {
                compatible = "samsung,exynos4210-ehci";
                reg = <0x12110000 0x100>;
@@ -497,7 +495,7 @@
                clock-names = "usbhost";
        };
-        usbphy@12130000 {
+        usb2_phy: usbphy@12130000 {
                compatible = "samsung,exynos5250-usb2phy";
                reg = <0x12130000 0x100>;
                clocks = <&clock 1>, <&clock 285>;
@@ -601,7 +599,7 @@
        };
        hdmi {
-                compatible = "samsung,exynos5-hdmi";
+                compatible = "samsung,exynos4212-hdmi";
                reg = <0x14530000 0x70000>;
                interrupts = <0 95 0>;
                clocks = <&clock 333>, <&clock 136>, <&clock 137>,
@@ -611,7 +609,7 @@
        };
        mixer {
-                compatible = "samsung,exynos5-mixer";
+                compatible = "samsung,exynos5250-mixer";
                reg = <0x14450000 0x10000>;
                interrupts = <0 94 0>;
        };
@@ -621,6 +619,8 @@
                reg = <0x145b0000 0x1000>;
                interrupts = <10 3>;
                interrupt-parent = <&combiner>;
+                clocks = <&clock 342>;
+                clock-names = "dp";
                #address-cells = <1>;
                #size-cells = <0>;
diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
new file mode 100644
index 000000000000..5848c425ae4d
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
@@ -0,0 +1,680 @@
+/*
+ * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+/ {
+        pinctrl@13400000 {
+                gpy7: gpy7 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpx0: gpx0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        interrupt-parent = <&combiner>;
+                        #interrupt-cells = <2>;
+                        interrupts = <23 0>, <24 0>, <25 0>, <25 1>,
+                                     <26 0>, <26 1>, <27 0>, <27 1>;
+                };
+                gpx1: gpx1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        interrupt-parent = <&combiner>;
+                        #interrupt-cells = <2>;
+                        interrupts = <28 0>, <28 1>, <29 0>, <29 1>,
+                                     <30 0>, <30 1>, <31 0>, <31 1>;
+                };
+                gpx2: gpx2 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpx3: gpx3 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+        };
+        pinctrl@13410000 {
+                gpc0: gpc0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpc1: gpc1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpc2: gpc2 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpc3: gpc3 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpc4: gpc4 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpd1: gpd1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpy0: gpy0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+                gpy1: gpy1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+                gpy2: gpy2 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+                gpy3: gpy3 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+                gpy4: gpy4 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+                gpy5: gpy5 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+                gpy6: gpy6 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+                sd0_clk: sd0-clk {
+                        samsung,pins = "gpc0-0";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <3>;
+                };
+                sd0_cmd: sd0-cmd {
+                        samsung,pins = "gpc0-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <3>;
+                };
+                sd0_cd: sd0-cd {
+                        samsung,pins = "gpc0-2";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+                sd0_bus1: sd0-bus-width1 {
+                        samsung,pins = "gpc0-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+                sd0_bus4: sd0-bus-width4 {
+                        samsung,pins = "gpc0-4", "gpc0-5", "gpc0-6";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+                sd0_bus8: sd0-bus-width8 {
+                        samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+                sd1_clk: sd1-clk {
+                        samsung,pins = "gpc1-0";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <3>;
+                };
+                sd1_cmd: sd1-cmd {
+                        samsung,pins = "gpc1-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <3>;
+                };
+                sd1_cd: sd1-cd {
+                        samsung,pins = "gpc1-2";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+                sd1_int: sd1-int {
+                        samsung,pins = "gpd1-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                sd1_bus1: sd1-bus-width1 {
+                        samsung,pins = "gpc1-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+                sd1_bus4: sd1-bus-width4 {
+                        samsung,pins = "gpc1-4", "gpc1-5", "gpc1-6";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+                sd1_bus8: sd1-bus-width8 {
+                        samsung,pins = "gpd1-4", "gpd1-5", "gpd1-6", "gpd1-7";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+                sd2_clk: sd2-clk {
+                        samsung,pins = "gpc2-0";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <3>;
+                };
+                sd2_cmd: sd2-cmd {
+                        samsung,pins = "gpc2-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <3>;
+                };
+                sd2_cd: sd2-cd {
+                        samsung,pins = "gpc2-2";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+                sd2_bus1: sd2-bus-width1 {
+                        samsung,pins = "gpc2-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+                sd2_bus4: sd2-bus-width4 {
+                        samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+        };
+        pinctrl@14000000 {
+                gpe0: gpe0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpe1: gpe1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpf0: gpf0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpf1: gpf1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpg0: gpg0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpg1: gpg1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpg2: gpg2 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpj4: gpj4 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                cam_gpio_a: cam-gpio-a {
+                        samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3",
+                                       "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7",
+                                       "gpe1-0", "gpe1-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                cam_gpio_b: cam-gpio-b {
+                        samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3",
+                                       "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                cam_i2c2_bus: cam-i2c2-bus {
+                        samsung,pins = "gpf0-4", "gpf0-5";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                cam_spi1_bus: cam-spi1-bus {
+                        samsung,pins = "gpe0-4", "gpe0-5", "gpf0-2", "gpf0-3";
+                        samsung,pin-function = <4>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                cam_i2c1_bus: cam-i2c1-bus {
+                        samsung,pins = "gpf0-2", "gpf0-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                cam_i2c0_bus: cam-i2c0-bus {
+                        samsung,pins = "gpf0-0", "gpf0-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                cam_spi0_bus: cam-spi0-bus {
+                        samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                cam_bayrgb_bus: cam-bayrgb-bus {
+                        samsung,pins = "gpg0-0", "gpg0-1", "gpg0-2", "gpg0-3",
+                                       "gpg0-4", "gpg0-5", "gpg0-6", "gpg0-7",
+                                       "gpg1-0", "gpg1-1", "gpg1-2", "gpg1-3",
+                                       "gpg1-4", "gpg1-5", "gpg1-6", "gpg1-7",
+                                       "gpg2-0";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+        };
+        pinctrl@14010000 {
+                gpa0: gpa0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpa1: gpa1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpa2: gpa2 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpb0: gpb0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpb1: gpb1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpb2: gpb2 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpb3: gpb3 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpb4: gpb4 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gph0: gph0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                uart0_data: uart0-data {
+                        samsung,pins = "gpa0-0", "gpa0-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                uart0_fctl: uart0-fctl {
+                        samsung,pins = "gpa0-2", "gpa0-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                uart1_data: uart1-data {
+                        samsung,pins = "gpa0-4", "gpa0-5";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                uart1_fctl: uart1-fctl {
+                        samsung,pins = "gpa0-6", "gpa0-7";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                i2c2_bus: i2c2-bus {
+                        samsung,pins = "gpa0-6", "gpa0-7";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                uart2_data: uart2-data {
+                        samsung,pins = "gpa1-0", "gpa1-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                uart2_fctl: uart2-fctl {
+                        samsung,pins = "gpa1-2", "gpa1-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                i2c3_bus: i2c3-bus {
+                        samsung,pins = "gpa1-2", "gpa1-3";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                uart3_data: uart3-data {
+                        samsung,pins = "gpa1-4", "gpa1-5";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                spi0_bus: spi0-bus {
+                        samsung,pins = "gpa2-0", "gpa2-1", "gpa2-2", "gpa2-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                spi1_bus: spi1-bus {
+                        samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                i2c4_hs_bus: i2c4-hs-bus {
+                        samsung,pins = "gpa2-0", "gpa2-1";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                i2c5_hs_bus: i2c5-hs-bus {
+                        samsung,pins = "gpa2-2", "gpa2-3";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                i2s1_bus: i2s1-bus {
+                        samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3",
+                                        "gpb0-4";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                pcm1_bus: pcm1-bus {
+                        samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3",
+                                        "gpb0-4";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                i2s2_bus: i2s2-bus {
+                        samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3",
+                                        "gpb1-4";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                pcm2_bus: pcm2-bus {
+                        samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3",
+                                        "gpb1-4";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                spdif_bus: spdif-bus {
+                        samsung,pins = "gpb1-0", "gpb1-1";
+                        samsung,pin-function = <4>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                spi2_bus: spi2-bus {
+                        samsung,pins = "gpb1-1", "gpb1-3", "gpb1-4";
+                        samsung,pin-function = <5>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                i2c6_hs_bus: i2c6-hs-bus {
+                        samsung,pins = "gpb1-3", "gpb1-4";
+                        samsung,pin-function = <4>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                i2c7_hs_bus: i2c7-hs-bus {
+                        samsung,pins = "gpb2-2", "gpb2-3";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                i2c0_bus: i2c0-bus {
+                        samsung,pins = "gpb3-0", "gpb3-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                i2c1_bus: i2c1-bus {
+                        samsung,pins = "gpb3-2", "gpb3-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                i2c8_hs_bus: i2c8-hs-bus {
+                        samsung,pins = "gpb3-4", "gpb3-5";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                i2c9_hs_bus: i2c9-hs-bus {
+                        samsung,pins = "gpb3-6", "gpb3-7";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                i2c10_hs_bus: i2c10-hs-bus {
+                        samsung,pins = "gpb4-0", "gpb4-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+        };
+        pinctrl@03860000 {
+                gpz: gpz {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                i2s0_bus: i2s0-bus {
+                        samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
+                                        "gpz-4", "gpz-5", "gpz-6";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
new file mode 100644
index 000000000000..08607df6a180
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -0,0 +1,33 @@
+/*
+ * SAMSUNG SMDK5420 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+/dts-v1/;
+#include "exynos5420.dtsi"
+/ {
+        model = "Samsung SMDK5420 board based on EXYNOS5420";
+        compatible = "samsung,smdk5420", "samsung,exynos5420";
+        memory {
+                reg = <0x20000000 0x80000000>;
+        };
+        chosen {
+                bootargs = "console=ttySAC2,115200 init=/linuxrc";
+        };
+        fixed-rate-clocks {
+                oscclk {
+                        compatible = "samsung,exynos5420-oscclk";
+                        clock-frequency = <24000000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
new file mode 100644
index 000000000000..8c54c4b74f0e
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -0,0 +1,148 @@
+/*
+ * SAMSUNG EXYNOS5420 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
+ * EXYNOS5420 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include "exynos5.dtsi"
+/include/ "exynos5420-pinctrl.dtsi"
+/ {
+        compatible = "samsung,exynos5420";
+        aliases {
+                pinctrl0 = &pinctrl_0;
+                pinctrl1 = &pinctrl_1;
+                pinctrl2 = &pinctrl_2;
+                pinctrl3 = &pinctrl_3;
+                pinctrl4 = &pinctrl_4;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu0: cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x0>;
+                        clock-frequency = <1800000000>;
+                };
+                cpu1: cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x1>;
+                        clock-frequency = <1800000000>;
+                };
+                cpu2: cpu@2 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x2>;
+                        clock-frequency = <1800000000>;
+                };
+                cpu3: cpu@3 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x3>;
+                        clock-frequency = <1800000000>;
+                };
+        };
+        clock: clock-controller@0x10010000 {
+                compatible = "samsung,exynos5420-clock";
+                reg = <0x10010000 0x30000>;
+                #clock-cells = <1>;
+        };
+        mct@101C0000 {
+                compatible = "samsung,exynos4210-mct";
+                reg = <0x101C0000 0x800>;
+                interrupt-controller;
+                #interrups-cells = <1>;
+                interrupt-parent = <&mct_map>;
+                interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>;
+                clocks = <&clock 1>, <&clock 315>;
+                clock-names = "fin_pll", "mct";
+                mct_map: mct-map {
+                        #interrupt-cells = <1>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = <0 &combiner 23 3>,
+                                        <1 &combiner 23 4>,
+                                        <2 &combiner 25 2>,
+                                        <3 &combiner 25 3>,
+                                        <4 &gic 0 120 0>,
+                                        <5 &gic 0 121 0>,
+                                        <6 &gic 0 122 0>,
+                                        <7 &gic 0 123 0>;
+                };
+        };
+        pinctrl_0: pinctrl@13400000 {
+                compatible = "samsung,exynos5420-pinctrl";
+                reg = <0x13400000 0x1000>;
+                interrupts = <0 45 0>;
+                wakeup-interrupt-controller {
+                        compatible = "samsung,exynos4210-wakeup-eint";
+                        interrupt-parent = <&gic>;
+                        interrupts = <0 32 0>;
+                };
+        };
+        pinctrl_1: pinctrl@13410000 {
+                compatible = "samsung,exynos5420-pinctrl";
+                reg = <0x13410000 0x1000>;
+                interrupts = <0 78 0>;
+        };
+        pinctrl_2: pinctrl@14000000 {
+                compatible = "samsung,exynos5420-pinctrl";
+                reg = <0x14000000 0x1000>;
+                interrupts = <0 46 0>;
+        };
+        pinctrl_3: pinctrl@14010000 {
+                compatible = "samsung,exynos5420-pinctrl";
+                reg = <0x14010000 0x1000>;
+                interrupts = <0 50 0>;
+        };
+        pinctrl_4: pinctrl@03860000 {
+                compatible = "samsung,exynos5420-pinctrl";
+                reg = <0x03860000 0x1000>;
+                interrupts = <0 47 0>;
+        };
+        serial@12C00000 {
+                clocks = <&clock 257>, <&clock 128>;
+                clock-names = "uart", "clk_uart_baud0";
+        };
+        serial@12C10000 {
+                clocks = <&clock 258>, <&clock 129>;
+                clock-names = "uart", "clk_uart_baud0";
+        };
+        serial@12C20000 {
+                clocks = <&clock 259>, <&clock 130>;
+                clock-names = "uart", "clk_uart_baud0";
+        };
+        serial@12C30000 {
+                clocks = <&clock 260>, <&clock 131>;
+                clock-names = "uart", "clk_uart_baud0";
+        };
+};
diff --git a/arch/arm/boot/dts/exynos5440-sd5v1.dts b/arch/arm/boot/dts/exynos5440-sd5v1.dts
index ef747b52b674..5b22508050da 100644
--- a/arch/arm/boot/dts/exynos5440-sd5v1.dts
+++ b/arch/arm/boot/dts/exynos5440-sd5v1.dts
@@ -10,14 +10,14 @@
 */
 /dts-v1/;
-/include/ "exynos5440.dtsi"
+#include "exynos5440.dtsi"
 / {
        model = "SAMSUNG SD5v1 board based on EXYNOS5440";
        compatible = "samsung,sd5v1", "samsung,exynos5440";
        chosen {
-                bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 console=ttySAC0,115200";
+                bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200";
        };
        fixed-rate-clocks {
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
index d55042beb5c5..ede772741f81 100644
--- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
+++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
@@ -10,18 +10,53 @@
 */
 /dts-v1/;
-/include/ "exynos5440.dtsi"
+#include "exynos5440.dtsi"
 / {
        model = "SAMSUNG SSDK5440 board based on EXYNOS5440";
        compatible = "samsung,ssdk5440", "samsung,exynos5440";
        chosen {
-                bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 console=ttySAC0,115200";
+                bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200";
        };
-        spi {
+        spi_0: spi@D0000 {
-                status = "disabled";
+                flash: w25q128@0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "winbond,w25q128";
+                        spi-max-frequency = <15625000>;
+                        reg = <0>;
+                        controller-data {
+                                samsung,spi-feedback-delay = <0>;
+                        };
+                        partition@00000 {
+                                label = "BootLoader";
+                                reg = <0x60000 0x80000>;
+                                read-only;
+                        };
+                        partition@e0000 {
+                                label = "Recovery-Kernel";
+                                reg = <0xe0000 0x300000>;
+                                read-only;
+                        };
+                        partition@3e0000 {
+                                label = "CRAM-FS";
+                                reg = <0x3e0000 0x700000>;
+                                read-only;
+                        };
+                        partition@ae0000 {
+                                label = "User-Data";
+                                reg = <0xae0000 0x520000>;
+                        };
+                };
        };
        fixed-rate-clocks {
@@ -30,4 +65,12 @@
                        clock-frequency = <50000000>;
                };
        };
+        pcie@290000 {
+                reset-gpio = <&pin_ctrl 5 0>;
+        };
+        pcie@2a0000 {
+                reset-gpio = <&pin_ctrl 22 0>;
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index f6b1c8973845..ff7f5d855845 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -9,13 +9,17 @@
 * published by the Free Software Foundation.
 */
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 / {
        compatible = "samsung,exynos5440";
        interrupt-parent = <&gic>;
+        aliases {
+                spi0 = &spi_0;
+        };
        clock: clock-controller@0x160000 {
                compatible = "samsung,exynos5440-clock";
                reg = <0x160000 0x1000>;
@@ -38,18 +42,22 @@
                #size-cells = <0>;
                cpu@0 {
+                        device_type = "cpu";
                        compatible = "arm,cortex-a15";
                        reg = <0>;
                };
                cpu@1 {
+                        device_type = "cpu";
                        compatible = "arm,cortex-a15";
                        reg = <1>;
                };
                cpu@2 {
+                        device_type = "cpu";
                        compatible = "arm,cortex-a15";
                        reg = <2>;
                };
                cpu@3 {
+                        device_type = "cpu";
                        compatible = "arm,cortex-a15";
                        reg = <3>;
                };
@@ -79,8 +87,13 @@
                interrupts = <0 57 0>;
                operating-points = <
                                /* KHz    uV */
+                                1500000 1100000
+                                1400000 1075000
+                                1300000 1050000
                                1200000 1025000
+                                1100000 1000000
                                1000000 975000
+                                900000  950000
                                800000  925000
                >;
        };
@@ -101,19 +114,19 @@
                clock-names = "uart", "clk_uart_baud0";
        };
-        spi {
+        spi_0: spi@D0000 {
-                compatible = "samsung,exynos4210-spi";
+                compatible = "samsung,exynos5440-spi";
-                reg = <0xD0000 0x1000>;
+                reg = <0xD0000 0x100>;
                interrupts = <0 4 0>;
-                tx-dma-channel = <&pdma0 5>; /* preliminary */
-                rx-dma-channel = <&pdma0 4>; /* preliminary */
                #address-cells = <1>;
                #size-cells = <0>;
+                samsung,spi-src-clk = <0>;
+                num-cs = <1>;
                clocks = <&clock 21>, <&clock 16>;
                clock-names = "spi", "spi_busclk0";
        };
-        pinctrl {
+        pin_ctrl: pinctrl {
                compatible = "samsung,exynos5440-pinctrl";
                reg = <0xE0000 0x1000>;
                interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>,
@@ -184,28 +197,6 @@
                compatible = "arm,amba-bus";
                interrupt-parent = <&gic>;
                ranges;
-                pdma0: pdma@00121000 {
-                        compatible = "arm,pl330", "arm,primecell";
-                        reg = <0x121000 0x1000>;
-                        interrupts = <0 46 0>;
-                        clocks = <&clock 8>;
-                        clock-names = "apb_pclk";
-                        #dma-cells = <1>;
-                        #dma-channels = <8>;
-                        #dma-requests = <32>;
-                };
-                pdma1: pdma@00120000 {
-                        compatible = "arm,pl330", "arm,primecell";
-                        reg = <0x120000 0x1000>;
-                        interrupts = <0 47 0>;
-                        clocks = <&clock 8>;
-                        clock-names = "apb_pclk";
-                        #dma-cells = <1>;
-                        #dma-channels = <8>;
-                        #dma-requests = <32>;
-                };
        };
        rtc {
@@ -214,6 +205,67 @@
                interrupts = <0 17 0>, <0 16 0>;
                clocks = <&clock 21>;
                clock-names = "rtc";
-                status = "disabled";
+        };
+        sata@210000 {
+                compatible = "snps,exynos5440-ahci";
+                reg = <0x210000 0x10000>;
+                interrupts = <0 30 0>;
+                clocks = <&clock 23>;
+                clock-names = "sata";
+        };
+        ohci@220000 {
+                compatible = "samsung,exynos5440-ohci";
+                reg = <0x220000 0x1000>;
+                interrupts = <0 29 0>;
+                clocks = <&clock 24>;
+                clock-names = "usbhost";
+        };
+        ehci@221000 {
+                compatible = "samsung,exynos5440-ehci";
+                reg = <0x221000 0x1000>;
+                interrupts = <0 29 0>;
+                clocks = <&clock 24>;
+                clock-names = "usbhost";
+        };
+        pcie@290000 {
+                compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
+                reg = <0x290000 0x1000
+                        0x270000 0x1000
+                        0x271000 0x40>;
+                interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
+                clocks = <&clock 28>, <&clock 27>;
+                clock-names = "pcie", "pcie_bus";
+                #address-cells = <3>;
+                #size-cells = <2>;
+                device_type = "pci";
+                ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000   /* configuration space */
+                          0x81000000 0 0          0x40001000 0 0x00010000   /* downstream I/O */
+                          0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
+                #interrupt-cells = <1>;
+                interrupt-map-mask = <0 0 0 0>;
+                interrupt-map = <0x0 0 &gic 53>;
+        };
+        pcie@2a0000 {
+                compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
+                reg = <0x2a0000 0x1000
+                        0x272000 0x1000
+                        0x271040 0x40>;
+                interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
+                clocks = <&clock 29>, <&clock 27>;
+                clock-names = "pcie", "pcie_bus";
+                #address-cells = <3>;
+                #size-cells = <2>;
+                device_type = "pci";
+                ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000   /* configuration space */
+                          0x81000000 0 0          0x60001000 0 0x00010000   /* downstream I/O */
+                          0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
+                #interrupt-cells = <1>;
+                interrupt-map-mask = <0 0 0 0>;
+                interrupt-map = <0x0 0 &gic 56>;
        };
 };
diff --git a/arch/arm/boot/dts/ge863-pro3.dtsi b/arch/arm/boot/dts/ge863-pro3.dtsi
index 17136fc7a516..230099bb31c8 100644
--- a/arch/arm/boot/dts/ge863-pro3.dtsi
+++ b/arch/arm/boot/dts/ge863-pro3.dtsi
@@ -7,7 +7,7 @@
 * Licensed under GPLv2 or later.
 */
-/include/ "at91sam9260.dtsi"
+#include "at91sam9260.dtsi"
 / {
        clocks {
diff --git a/arch/arm/boot/dts/href.dtsi b/arch/arm/boot/dts/href.dtsi
index c0bc426952ea..9db41b9d8358 100644
--- a/arch/arm/boot/dts/href.dtsi
+++ b/arch/arm/boot/dts/href.dtsi
@@ -9,7 +9,8 @@
 * http://www.gnu.org/copyleft/gpl.html
 */
-/include/ "dbx5x0.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "dbx5x0.dtsi"
 / {
        memory {
@@ -27,7 +28,7 @@
                };
        };
-        soc-u9500 {
+        soc {
                uart@80120000 {
                        status = "okay";
                };
@@ -45,14 +46,14 @@
                                compatible = "tc3589x";
                                reg = <0x42>;
                                interrupt-parent = <&gpio6>;
-                                interrupts = <25 0x1>;
+                                interrupts = <25 IRQ_TYPE_EDGE_RISING>;
                                interrupt-controller;
                                #interrupt-cells = <2>;
                                tc3589x_gpio: tc3589x_gpio {
                                        compatible = "tc3589x-gpio";
-                                        interrupts = <0 0x1>;
+                                        interrupts = <0 IRQ_TYPE_EDGE_RISING>;
                                        interrupt-controller;
                                        #interrupt-cells = <2>;
@@ -63,17 +64,43 @@
                };
                i2c@80128000 {
-                        lp5521@0x33 {
+                        lp5521@33 {
-                                compatible = "lp5521";
+                                compatible = "national,lp5521";
                                reg = <0x33>;
+                                label = "lp5521_pri";
+                                clock-mode = /bits/ 8 <2>;
+                                chan0 {
+                                        led-cur = /bits/ 8 <0x2f>;
+                                        max-cur = /bits/ 8 <0x5f>;
+                                };
+                                chan1 {
+                                        led-cur = /bits/ 8 <0x2f>;
+                                        max-cur = /bits/ 8 <0x5f>;
+                                };
+                                chan2 {
+                                        led-cur = /bits/ 8 <0x2f>;
+                                        max-cur = /bits/ 8 <0x5f>;
+                                };
                        };
+                        lp5521@34 {
-                        lp5521@0x34 {
+                                compatible = "national,lp5521";
-                                compatible = "lp5521";
                                reg = <0x34>;
+                                label = "lp5521_sec";
+                                clock-mode = /bits/ 8 <2>;
+                                chan0 {
+                                        led-cur = /bits/ 8 <0x2f>;
+                                        max-cur = /bits/ 8 <0x5f>;
+                                };
+                                chan1 {
+                                        led-cur = /bits/ 8 <0x2f>;
+                                        max-cur = /bits/ 8 <0x5f>;
+                                };
+                                chan2 {
+                                        led-cur = /bits/ 8 <0x2f>;
+                                        max-cur = /bits/ 8 <0x5f>;
+                                };
                        };
+                        bh1780@29 {
-                        bh1780@0x29 {
                                compatible = "rohm,bh1780gli";
                                reg = <0x33>;
                        };
@@ -82,7 +109,7 @@
                // External Micro SD slot
                sdi0_per1@80126000 {
                        arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <50000000>;
+                        max-frequency = <100000000>;
                        bus-width = <4>;
                        mmc-cap-sd-highspeed;
                        mmc-cap-mmc-highspeed;
@@ -97,7 +124,7 @@
                // WLAN SDIO channel
                sdi1_per2@80118000 {
                        arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <50000000>;
+                        max-frequency = <100000000>;
                        bus-width = <4>;
                        status = "okay";
@@ -106,7 +133,7 @@
                // PoP:ed eMMC
                sdi2_per3@80005000 {
                        arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <50000000>;
+                        max-frequency = <100000000>;
                        bus-width = <8>;
                        mmc-cap-mmc-highspeed;
@@ -116,7 +143,7 @@
                // On-board eMMC
                sdi4_per2@80114000 {
                        arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <50000000>;
+                        max-frequency = <100000000>;
                        bus-width = <8>;
                        mmc-cap-mmc-highspeed;
                        vmmc-supply = <&ab8500_ldo_aux2_reg>;
@@ -236,7 +263,7 @@
                                                regulator-name = "V-MMC-SD";
                                        };
-                                        ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
+                                        ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
                                                regulator-name = "V-INTCORE";
                                        };
@@ -256,7 +283,7 @@
                                                regulator-name = "V-AMIC1";
                                        };
-                                        ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
+                                        ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
                                                regulator-name = "V-AMIC2";
                                        };
diff --git a/arch/arm/boot/dts/hrefprev60.dts b/arch/arm/boot/dts/hrefprev60.dts
index c2d274815923..c6bb07df2d1d 100644
--- a/arch/arm/boot/dts/hrefprev60.dts
+++ b/arch/arm/boot/dts/hrefprev60.dts
@@ -10,9 +10,9 @@
 */
 /dts-v1/;
-/include/ "dbx5x0.dtsi"
+#include "dbx5x0.dtsi"
-/include/ "href.dtsi"
+#include "href.dtsi"
-/include/ "stuib.dtsi"
+#include "stuib.dtsi"
 / {
        model = "ST-Ericsson HREF (pre-v60) platform with Device Tree";
@@ -24,7 +24,7 @@
                };
        };
-        soc-u9500 {
+        soc {
                prcmu@80157000 {
                        ab8500@5 {
                                ab8500-gpio {
@@ -41,7 +41,7 @@
                };
                i2c@80110000 {
-                        bu21013_tp@0x5c {
+                        bu21013_tp@5c {
                                reset-gpio = <&tc3589x_gpio 13 0x4>;
                        };
                };
diff --git a/arch/arm/boot/dts/hrefv60plus.dts b/arch/arm/boot/dts/hrefv60plus.dts
index 2b587a74b813..3d580d6447f9 100644
--- a/arch/arm/boot/dts/hrefv60plus.dts
+++ b/arch/arm/boot/dts/hrefv60plus.dts
@@ -10,9 +10,9 @@
 */
 /dts-v1/;
-/include/ "dbx5x0.dtsi"
+#include "dbx5x0.dtsi"
-/include/ "href.dtsi"
+#include "href.dtsi"
-/include/ "stuib.dtsi"
+#include "stuib.dtsi"
 / {
        model = "ST-Ericsson HREF (v60+) platform with Device Tree";
@@ -24,7 +24,7 @@
                };
        };
-        soc-u9500 {
+        soc {
                i2c@80110000 {
                        bu21013_tp@0x5c {
                                reset-gpio = <&gpio4 15 0x4>;
@@ -34,7 +34,7 @@
                // External Micro SD slot
                sdi0_per1@80126000 {
                        arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <50000000>;
+                        max-frequency = <100000000>;
                        bus-width = <4>;
                        mmc-cap-sd-highspeed;
                        mmc-cap-mmc-highspeed;
@@ -48,7 +48,7 @@
                // WLAN SDIO channel
                sdi1_per2@80118000 {
                        arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <50000000>;
+                        max-frequency = <100000000>;
                        bus-width = <4>;
                        status = "okay";
@@ -57,7 +57,7 @@
                // PoP:ed eMMC
                sdi2_per3@80005000 {
                        arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <50000000>;
+                        max-frequency = <100000000>;
                        bus-width = <8>;
                        mmc-cap-mmc-highspeed;
@@ -67,7 +67,7 @@
                // On-board eMMC
                sdi4_per2@80114000 {
                        arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <50000000>;
+                        max-frequency = <100000000>;
                        bus-width = <8>;
                        mmc-cap-mmc-highspeed;
                        vmmc-supply = <&ab8500_ldo_aux2_reg>;
@@ -172,7 +172,7 @@
                                                regulator-name = "V-MMC-SD";
                                        };
-                                        ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
+                                        ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
                                                regulator-name = "V-INTCORE";
                                        };
@@ -192,7 +192,7 @@
                                                regulator-name = "V-AMIC1";
                                        };
-                                        ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
+                                        ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
                                                regulator-name = "V-AMIC2";
                                        };
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 73fd7d0887b5..587ceef81e45 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -23,8 +23,12 @@
        };
        cpus {
-                cpu@0 {
+                #address-cells = <0>;
-                        compatible = "arm,arm926ejs";
+                #size-cells = <0>;
+                cpu {
+                        compatible = "arm,arm926ej-s";
+                        device_type = "cpu";
                };
        };
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
new file mode 100644
index 000000000000..e7ed9786920a
--- /dev/null
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
@@ -0,0 +1,37 @@
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include "imx27-phytec-phycore-som.dts"
+/ {
+        model = "Phytec pcm970";
+        compatible = "phytec,imx27-pcm970", "phytec,imx27-pcm038", "fsl,imx27";
+};
+&cspi1 {
+        fsl,spi-num-chipselects = <2>;
+        cs-gpios = <&gpio4 28 0>, <&gpio4 27 0>;
+};
+&sdhci2 {
+        bus-width = <4>;
+        cd-gpios = <&gpio3 29 0>;
+        wp-gpios = <&gpio3 28 0>;
+        vmmc-supply = <&vmmc1_reg>;
+        status = "okay";
+};
+&uart1 {
+        fsl,uart-has-rtscts;
+};
+&uart2 {
+        fsl,uart-has-rtscts;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dts b/arch/arm/boot/dts/imx27-phytec-phycore-som.dts
new file mode 100644
index 000000000000..f0105651869d
--- /dev/null
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dts
@@ -0,0 +1,179 @@
+/*
+ * Copyright 2012 Sascha Hauer, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+#include "imx27.dtsi"
+/ {
+        model = "Phytec pcm038";
+        compatible = "phytec,imx27-pcm038", "fsl,imx27";
+        memory {
+                reg = <0x0 0x0>;
+        };
+        soc {
+                aipi@10000000 { /* aipi1 */
+                        serial@1000a000 {
+                                status = "okay";
+                        };
+                        i2c@1001d000 {
+                                clock-frequency = <400000>;
+                                status = "okay";
+                                at24@52 {
+                                        compatible = "at,24c32";
+                                        pagesize = <32>;
+                                        reg = <0x52>;
+                                };
+                                pcf8563@51 {
+                                        compatible = "nxp,pcf8563";
+                                        reg = <0x51>;
+                                };
+                                lm75@4a {
+                                        compatible = "national,lm75";
+                                        reg = <0x4a>;
+                                };
+                        };
+                };
+                aipi@10020000 { /* aipi2 */
+                        ethernet@1002b000 {
+                                phy-reset-gpios = <&gpio3 30 0>;
+                                status = "okay";
+                        };
+                };
+        };
+        nor_flash@c0000000 {
+                compatible = "cfi-flash";
+                bank-width = <2>;
+                reg = <0xc0000000 0x02000000>;
+                linux,mtd-name = "physmap-flash.0";
+                #address-cells = <1>;
+                #size-cells = <1>;
+        };
+};
+&cspi1 {
+        fsl,spi-num-chipselects = <1>;
+        cs-gpios = <&gpio4 28 0>;
+        status = "okay";
+        pmic: mc13783@0 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "fsl,mc13783";
+                spi-max-frequency = <20000000>;
+                reg = <0>;
+                interrupt-parent = <&gpio2>;
+                interrupts = <23 0x4>;
+                fsl,mc13xxx-uses-adc;
+                fsl,mc13xxx-uses-rtc;
+                regulators {
+                        sw1a_reg: sw1a {
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        sw1b_reg: sw1b {
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        sw2a_reg: sw2a {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        sw2b_reg: sw2b {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        sw3_reg: sw3 {
+                                regulator-min-microvolt = <5000000>;
+                                regulator-max-microvolt = <5000000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        vaudio_reg: vaudio {
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        violo_reg: violo {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        viohi_reg: viohi {
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        vgen_reg: vgen {
+                                regulator-min-microvolt = <1500000>;
+                                regulator-max-microvolt = <1500000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        vcam_reg: vcam {
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                        };
+                        vrf1_reg: vrf1 {
+                                regulator-min-microvolt = <2775000>;
+                                regulator-max-microvolt = <2775000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        vrf2_reg: vrf2 {
+                                regulator-min-microvolt = <2775000>;
+                                regulator-max-microvolt = <2775000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        vmmc1_reg: vmmc1 {
+                                regulator-min-microvolt = <1600000>;
+                                regulator-max-microvolt = <3000000>;
+                        };
+                        gpo1_reg: gpo1 { };
+                        pwgt1spi_reg: pwgt1spi {
+                                regulator-always-on;
+                        };
+                };
+        };
+};
+&nfc {
+        nand-bus-width = <8>;
+        nand-ecc-mode = "hw";
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore.dts b/arch/arm/boot/dts/imx27-phytec-phycore.dts
deleted file mode 100644
index fe64e3a91df0..000000000000
--- a/arch/arm/boot/dts/imx27-phytec-phycore.dts
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Copyright 2012 Sascha Hauer, Pengutronix
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-/dts-v1/;
-#include "imx27.dtsi"
-/ {
-        model = "Phytec pcm038";
-        compatible = "phytec,imx27-pcm038", "fsl,imx27";
-        memory {
-                reg = <0x0 0x0>;
-        };
-        soc {
-                aipi@10000000 { /* aipi1 */
-                        serial@1000a000 {
-                                fsl,uart-has-rtscts;
-                                status = "okay";
-                        };
-                        serial@1000b000 {
-                                fsl,uart-has-rtscts;
-                                status = "okay";
-                        };
-                        serial@1000c000 {
-                                fsl,uart-has-rtscts;
-                                status = "okay";
-                        };
-                        i2c@1001d000 {
-                                clock-frequency = <400000>;
-                                status = "okay";
-                                at24@52 {
-                                        compatible = "at,24c32";
-                                        pagesize = <32>;
-                                        reg = <0x52>;
-                                };
-                                pcf8563@51 {
-                                        compatible = "nxp,pcf8563";
-                                        reg = <0x51>;
-                                };
-                                lm75@4a {
-                                        compatible = "national,lm75";
-                                        reg = <0x4a>;
-                                };
-                        };
-                };
-                aipi@10020000 { /* aipi2 */
-                        ethernet@1002b000 {
-                                status = "okay";
-                        };
-                };
-        };
-        nor_flash@c0000000 {
-                compatible = "cfi-flash";
-                bank-width = <2>;
-                reg = <0xc0000000 0x02000000>;
-                #address-cells = <1>;
-                #size-cells = <1>;
-        };
-};
-&nfc {
-        nand-bus-width = <8>;
-        nand-ecc-mode = "hw";
-        status = "okay";
-};
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 75bd11386516..0695264ddf1b 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -25,6 +25,9 @@
                gpio3 = &gpio4;
                gpio4 = &gpio5;
                gpio5 = &gpio6;
+                spi0 = &cspi1;
+                spi1 = &cspi2;
+                spi2 = &cspi3;
        };
        avic: avic-interrupt-controller@e0000000 {
@@ -58,6 +61,16 @@
                        reg = <0x10000000 0x20000>;
                        ranges;
+                        dma: dma@10001000 {
+                                compatible = "fsl,imx27-dma";
+                                reg = <0x10001000 0x1000>;
+                                interrupts = <32>;
+                                clocks = <&clks 50>, <&clks 70>;
+                                clock-names = "ipg", "ahb";
+                                #dma-cells = <1>;
+                                #dma-channels = <16>;
+                        };
                        wdog: wdog@10002000 {
                                compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
                                reg = <0x10002000 0x1000>;
@@ -89,6 +102,14 @@
                                clock-names = "ipg", "per";
                        };
+                        pwm0: pwm@10006000 {
+                                compatible = "fsl,imx27-pwm";
+                                reg = <0x10006000 0x1000>;
+                                interrupts = <23>;
+                                clocks = <&clks 34>, <&clks 61>;
+                                clock-names = "ipg", "per";
+                        };
                        uart1: serial@1000a000 {
                                compatible = "fsl,imx27-uart", "fsl,imx21-uart";
                                reg = <0x1000a000 0x1000>;
@@ -157,6 +178,28 @@
                                status = "disabled";
                        };
+                        sdhci1: sdhci@10013000 {
+                                compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
+                                reg = <0x10013000 0x1000>;
+                                interrupts = <11>;
+                                clocks = <&clks 30>, <&clks 60>;
+                                clock-names = "ipg", "per";
+                                dmas = <&dma 7>;
+                                dma-names = "rx-tx";
+                                status = "disabled";
+                        };
+                        sdhci2: sdhci@10014000 {
+                                compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
+                                reg = <0x10014000 0x1000>;
+                                interrupts = <10>;
+                                clocks = <&clks 29>, <&clks 60>;
+                                clock-names = "ipg", "per";
+                                dmas = <&dma 6>;
+                                dma-names = "rx-tx";
+                                status = "disabled";
+                        };
                        gpio1: gpio@10015000 {
                                compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
                                reg = <0x10015000 0x100>;
@@ -272,6 +315,17 @@
                                status = "disabled";
                        };
+                        sdhci3: sdhci@1001e000 {
+                                compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
+                                reg = <0x1001e000 0x1000>;
+                                interrupts = <9>;
+                                clocks = <&clks 28>, <&clks 60>;
+                                clock-names = "ipg", "per";
+                                dmas = <&dma 36>;
+                                dma-names = "rx-tx";
+                                status = "disabled";
+                        };
                        gpt6: timer@1001f000 {
                                compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
                                reg = <0x1001f000 0x1000>;
@@ -288,6 +342,21 @@
                        reg = <0x10020000 0x20000>;
                        ranges;
+                        coda: coda@10023000 {
+                                compatible = "fsl,imx27-vpu";
+                                reg = <0x10023000 0x0200>;
+                                interrupts = <53>;
+                                clocks = <&clks 57>, <&clks 66>;
+                                clock-names = "per", "ahb";
+                                iram = <&iram>;
+                        };
+                        clks: ccm@10027000{
+                                compatible = "fsl,imx27-ccm";
+                                reg = <0x10027000 0x1000>;
+                                #clock-cells = <1>;
+                        };
                        fec: ethernet@1002b000 {
                                compatible = "fsl,imx27-fec";
                                reg = <0x1002b000 0x4000>;
@@ -296,19 +365,16 @@
                                clock-names = "ipg", "ahb", "ptp";
                                status = "disabled";
                        };
-                        clks: ccm@10027000{
-                                compatible = "fsl,imx27-ccm";
-                                reg = <0x10027000 0x1000>;
-                                #clock-cells = <1>;
-                        };
                };
+                iram: iram@ffff4c00 {
+                        compatible = "mmio-sram";
+                        reg = <0xffff4c00 0xb400>;
+                };
                nfc: nand@d8000000 {
                        #address-cells = <1>;
                        #size-cells = <1>;
                        compatible = "fsl,imx27-nand";
                        reg = <0xd8000000 0x1000>;
                        interrupts = <29>;
diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts
index 3d905d16cbec..b602494c152b 100644
--- a/arch/arm/boot/dts/imx28-apf28dev.dts
+++ b/arch/arm/boot/dts/imx28-apf28dev.dts
@@ -103,6 +103,7 @@
                apbx@80040000 {
                        lradc@80050000 {
+                                fsl,lradc-touchscreen-wires = <4>;
                                status = "okay";
                        };
diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts
index 43bf3c796cba..0e7fed47bd8d 100644
--- a/arch/arm/boot/dts/imx28-apx4devkit.dts
+++ b/arch/arm/boot/dts/imx28-apx4devkit.dts
@@ -147,7 +147,7 @@
                                        reg = <0x0a>;
                                        VDDA-supply = <&reg_3p3v>;
                                        VDDIO-supply = <&reg_3p3v>;
+                                        clocks = <&saif0>;
                                };
                                pcf8563: rtc@51 {
diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts
index 1594694532b9..94c4476972c3 100644
--- a/arch/arm/boot/dts/imx28-cfa10036.dts
+++ b/arch/arm/boot/dts/imx28-cfa10036.dts
@@ -45,6 +45,17 @@
                                        fsl,voltage = <1>;
                                        fsl,pull-up = <0>;
                                };
+                                usb0_otg_cfa10036: otg-10036@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x0142 /* MX28_PAD_GPMI_READY0__USB0_ID */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
                        };
                        ssp0: ssp@80010000 {
@@ -58,12 +69,6 @@
                };
                apbx@80040000 {
-                        pwm: pwm@80064000 {
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pwm4_pins_a>;
-                                status = "okay";
-                        };
                        duart: serial@80074000 {
                                pinctrl-names = "default";
                                pinctrl-0 = <&duart_pins_b>;
@@ -73,15 +78,30 @@
                        i2c0: i2c@80058000 {
                                pinctrl-names = "default";
                                pinctrl-0 = <&i2c0_pins_b>;
+                                clock-frequency = <400000>;
                                status = "okay";
-                                ssd1307: oled@3c {
+                                ssd1306: oled@3c {
-                                        compatible = "solomon,ssd1307fb-i2c";
+                                        compatible = "solomon,ssd1306fb-i2c";
                                        reg = <0x3c>;
-                                        pwms = <&pwm 4 3000>;
                                        reset-gpios = <&gpio2 7 0>;
+                                        solomon,height = <32>;
+                                        solomon,width = <128>;
+                                        solomon,page-offset = <0>;
                                };
                        };
+                        usbphy0: usbphy@8007c000 {
+                                status = "okay";
+                        };
+                };
+        };
+        ahb@80080000 {
+                usb0: usb@80080000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&usb0_otg_cfa10036>;
+                        status = "okay";
                };
        };
diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts
index 063e62059890..04b2f769ffbd 100644
--- a/arch/arm/boot/dts/imx28-cfa10049.dts
+++ b/arch/arm/boot/dts/imx28-cfa10049.dts
@@ -33,7 +33,7 @@
                                                0x1163 /* MX28_PAD_LCD_D22__GPIO_1_22 */
                                                0x1173 /* MX28_PAD_LCD_D22__GPIO_1_23 */
                                                0x2153 /* MX28_PAD_SSP2_D5__GPIO_2_21 */
-                                                0x3173 /* MX28_PAD_LCD_RESET__GPIO_3_23 */
+                                                0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */
                                        >;
                                        fsl,drive-strength = <0>;
                                        fsl,voltage = <1>;
@@ -166,8 +166,8 @@
                apbx@80040000 {
                        pwm: pwm@80064000 {
-                                pinctrl-names = "default", "default";
+                                pinctrl-names = "default";
-                                pinctrl-1 = <&pwm3_pins_b>;
+                                pinctrl-0 = <&pwm3_pins_b>;
                                status = "okay";
                        };
@@ -265,7 +265,7 @@
                gpio-sck = <&gpio2 16 0>;
                gpio-mosi = <&gpio2 17 0>;
                gpio-miso = <&gpio2 18 0>;
-                cs-gpios = <&gpio3 23 0>;
+                cs-gpios = <&gpio3 5 0>;
                num-chipselects = <1>;
                #address-cells = <1>;
                #size-cells = <0>;
diff --git a/arch/arm/boot/dts/imx28-cfa10055.dts b/arch/arm/boot/dts/imx28-cfa10055.dts
new file mode 100644
index 000000000000..158111244122
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-cfa10055.dts
@@ -0,0 +1,179 @@
+/*
+ * Copyright 2013 Crystalfontz America, Inc.
+ *                                Free Electrons
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/*
+ * The CFA-10055 is an expansion board for the CFA-10036 module and
+ * CFA-10037, thus we need to include the CFA-10037 DTS.
+ */
+/include/ "imx28-cfa10037.dts"
+/ {
+        model = "Crystalfontz CFA-10055 Board";
+        compatible = "crystalfontz,cfa10055", "crystalfontz,cfa10037", "crystalfontz,cfa10036", "fsl,imx28";
+        apb@80000000 {
+                apbh@80000000 {
+                        pinctrl@80018000 {
+                                pinctrl-names = "default", "default";
+                                pinctrl-1 = <&hog_pins_cfa10055
+                                        &hog_pins_cfa10055_pullup>;
+                                hog_pins_cfa10055: hog-10055@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+                                hog_pins_cfa10055_pullup: hog-10055-pullup@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <1>;
+                                };
+                                spi2_pins_cfa10055: spi2-cfa10055@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x2103 /* MX28_PAD_SSP2_SCK__GPIO_2_16 */
+                                                0x2113 /* MX28_PAD_SSP2_CMD__GPIO_2_17 */
+                                                0x2123 /* MX28_PAD_SSP2_D0__GPIO_2_18 */
+                                        >;
+                                        fsl,drive-strength = <1>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <1>;
+                                };
+                                lcdif_18bit_pins_cfa10055: lcdif-18bit@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
+                                                0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
+                                                0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
+                                                0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
+                                                0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
+                                                0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
+                                                0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
+                                                0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
+                                                0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
+                                                0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
+                                                0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
+                                                0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
+                                                0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
+                                                0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
+                                                0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
+                                                0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
+                                                0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */
+                                                0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+                                lcdif_pins_cfa10055: lcdif-evk@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */
+                                                0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */
+                                                0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */
+                                                0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+                        };
+                        lcdif@80030000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&lcdif_18bit_pins_cfa10055
+                                             &lcdif_pins_cfa10055>;
+                                display = <&display>;
+                                status = "okay";
+                                display: display {
+                                        bits-per-pixel = <32>;
+                                        bus-width = <18>;
+                                        display-timings {
+                                                native-mode = <&timing0>;
+                                                timing0: timing0 {
+                                                        clock-frequency = <9216000>;
+                                                        hactive = <320>;
+                                                        vactive = <480>;
+                                                        hback-porch = <2>;
+                                                        hfront-porch = <2>;
+                                                        vback-porch = <2>;
+                                                        vfront-porch = <2>;
+                                                        hsync-len = <15>;
+                                                        vsync-len = <15>;
+                                                        hsync-active = <0>;
+                                                        vsync-active = <0>;
+                                                        de-active = <1>;
+                                                        pixelclk-active = <1>;
+                                                };
+                                        };
+                                };
+                        };
+                };
+                apbx@80040000 {
+                        lradc@80050000 {
+                                fsl,lradc-touchscreen-wires = <4>;
+                                status = "okay";
+                        };
+                        pwm: pwm@80064000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pwm3_pins_b>;
+                                status = "okay";
+                        };
+                };
+        };
+        spi2 {
+                compatible = "spi-gpio";
+                pinctrl-names = "default";
+                pinctrl-0 = <&spi2_pins_cfa10055>;
+                status = "okay";
+                gpio-sck = <&gpio2 16 0>;
+                gpio-mosi = <&gpio2 17 0>;
+                gpio-miso = <&gpio2 18 0>;
+                cs-gpios = <&gpio3 5 0>;
+                num-chipselects = <1>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                hx8357: hx8357@0 {
+                        compatible = "himax,hx8357b", "himax,hx8357";
+                        reg = <0>;
+                        spi-max-frequency = <100000>;
+                        spi-cpol;
+                        spi-cpha;
+                        gpios-reset = <&gpio3 30 0>;
+                };
+        };
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm 3 5000000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+        };
+};
diff --git a/arch/arm/boot/dts/imx28-cfa10057.dts b/arch/arm/boot/dts/imx28-cfa10057.dts
new file mode 100644
index 000000000000..2da713cdb42a
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-cfa10057.dts
@@ -0,0 +1,191 @@
+/*
+ * Copyright 2013 Crystalfontz America, Inc.
+ * Copyright 2012 Free Electrons
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/*
+ * The CFA-10057 is an expansion board for the CFA-10036 module, thus we
+ * need to include the CFA-10036 DTS.
+ */
+/include/ "imx28-cfa10036.dts"
+/ {
+        model = "Crystalfontz CFA-10057 Board";
+        compatible = "crystalfontz,cfa10057", "crystalfontz,cfa10036", "fsl,imx28";
+        apb@80000000 {
+                apbh@80000000 {
+                        pinctrl@80018000 {
+                                pinctrl-names = "default", "default";
+                                pinctrl-1 = <&hog_pins_cfa10057
+                                        &hog_pins_cfa10057_pullup>;
+                                hog_pins_cfa10057: hog-10057@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */
+                                                0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+                                hog_pins_cfa10057_pullup: hog-10057-pullup@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x2133 /* MX28_PAD_SSP2_D3__GPIO_2_19 */
+                                                0x3183 /* MX28_PAD_I2C0_SCL__GPIO_3_24 */
+                                                0x3193 /* MX28_PAD_I2C0_SDA__GPIO_3_25 */
+                                                0x31a3 /* MX28_PAD_SAIF_SDATA0__GPIO_3_26 */
+                                                0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <1>;
+                                };
+                                lcdif_18bit_pins_cfa10057: lcdif-18bit@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
+                                                0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
+                                                0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
+                                                0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
+                                                0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
+                                                0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
+                                                0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
+                                                0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
+                                                0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
+                                                0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
+                                                0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
+                                                0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
+                                                0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
+                                                0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
+                                                0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
+                                                0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
+                                                0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */
+                                                0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+                                lcdif_pins_cfa10057: lcdif-evk@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */
+                                                0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */
+                                                0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */
+                                                0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+                        };
+                        lcdif@80030000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&lcdif_18bit_pins_cfa10057
+                                             &lcdif_pins_cfa10057>;
+                                display = <&display>;
+                                status = "okay";
+                                display: display {
+                                        bits-per-pixel = <32>;
+                                        bus-width = <18>;
+                                        display-timings {
+                                                native-mode = <&timing0>;
+                                                timing0: timing0 {
+                                                        clock-frequency = <30000000>;
+                                                        hactive = <480>;
+                                                        vactive = <800>;
+                                                        hfront-porch = <12>;
+                                                        hback-porch = <2>;
+                                                        vfront-porch = <5>;
+                                                        vback-porch = <3>;
+                                                        hsync-len = <2>;
+                                                        vsync-len = <2>;
+                                                        hsync-active = <0>;
+                                                        vsync-active = <0>;
+                                                        de-active = <1>;
+                                                        pixelclk-active = <1>;
+                                                };
+                                        };
+                                };
+                        };
+                };
+                apbx@80040000 {
+                        lradc@80050000 {
+                                fsl,lradc-touchscreen-wires = <4>;
+                                status = "okay";
+                        };
+                        pwm: pwm@80064000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pwm3_pins_b>;
+                                status = "okay";
+                        };
+                        i2c1: i2c@8005a000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&i2c1_pins_a>;
+                                status = "okay";
+                        };
+                        usbphy1: usbphy@8007e000 {
+                                status = "okay";
+                        };
+                };
+        };
+        ahb@80080000 {
+                usb1: usb@80090000 {
+                        vbus-supply = <&reg_usb1_vbus>;
+                        pinctrl-0 = <&usbphy1_pins_a>;
+                        pinctrl-names = "default";
+                        status = "okay";
+                };
+        };
+        regulators {
+                compatible = "simple-bus";
+                reg_usb1_vbus: usb1_vbus {
+                        compatible = "regulator-fixed";
+                        regulator-name = "usb1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio0 7 1>;
+                };
+        };
+        ahb@80080000 {
+                mac0: ethernet@800f0000 {
+                        phy-mode = "rmii";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mac0_pins_a>;
+                        phy-reset-gpios = <&gpio2 21 0>;
+                        phy-reset-duration = <100>;
+                        status = "okay";
+                };
+        };
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm 3 5000000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <7>;
+        };
+};
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index 3637bf3b1d59..e035f4664b97 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -155,12 +155,14 @@
                        can0: can@80032000 {
                                pinctrl-names = "default";
                                pinctrl-0 = <&can0_pins_a>;
+                                xceiver-supply = <&reg_can_3v3>;
                                status = "okay";
                        };
                        can1: can@80034000 {
                                pinctrl-names = "default";
                                pinctrl-0 = <&can1_pins_a>;
+                                xceiver-supply = <&reg_can_3v3>;
                                status = "okay";
                        };
                };
@@ -193,7 +195,7 @@
                                        reg = <0x0a>;
                                        VDDA-supply = <&reg_3p3v>;
                                        VDDIO-supply = <&reg_3p3v>;
+                                        clocks = <&saif0>;
                                };
                                at24@51 {
@@ -319,6 +321,16 @@
                        gpio = <&gpio3 30 0>;
                        enable-active-high;
                };
+                reg_can_3v3: can-3v3 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "can-3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpio = <&gpio2 13 0>;
+                        enable-active-high;
+                };
        };
        sound {
diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts
index 5aa44e05c9f5..44d9da57736e 100644
--- a/arch/arm/boot/dts/imx28-m28evk.dts
+++ b/arch/arm/boot/dts/imx28-m28evk.dts
@@ -184,7 +184,7 @@
                                        reg = <0x0a>;
                                        VDDA-supply = <&reg_3p3v>;
                                        VDDIO-supply = <&reg_3p3v>;
+                                        clocks = <&saif0>;
                                };
                                eeprom: eeprom@51 {
@@ -220,7 +220,19 @@
                        auart0: serial@8006a000 {
                                pinctrl-names = "default";
-                                pinctrl-0 = <&auart0_2pins_a>;
+                                pinctrl-0 = <&auart0_pins_a>;
+                                status = "okay";
+                        };
+                        auart1: serial@8006c000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&auart1_pins_a>;
+                                status = "okay";
+                        };
+                        auart2: serial@8006e000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&auart2_2pins_b>;
                                status = "okay";
                        };
                };
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 600f7cb51f3e..9524a0571281 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -32,8 +32,12 @@
        };
        cpus {
-                cpu@0 {
+                #address-cells = <0>;
-                        compatible = "arm,arm926ejs";
+                #size-cells = <0>;
+                cpu {
+                        compatible = "arm,arm926ej-s";
+                        device_type = "cpu";
                };
        };
@@ -330,6 +334,17 @@
                                        fsl,pull-up = <0>;
                                };
+                                auart2_2pins_b: auart2-2pins@1 {
+                                        reg = <1>;
+                                        fsl,pinmux-ids = <
+                                                0x3080 /* MX28_PAD_AUART2_RX__AUART2_RX */
+                                                0x3090 /* MX28_PAD_AUART2_TX__AUART2_TX */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
                                auart3_pins_a: auart3@0 {
                                        reg = <0>;
                                        fsl,pinmux-ids = <
@@ -354,6 +369,28 @@
                                        fsl,pull-up = <0>;
                                };
+                                auart3_2pins_b: auart3-2pins@1 {
+                                        reg = <1>;
+                                        fsl,pinmux-ids = <
+                                                0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */
+                                                0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+                                auart4_2pins_a: auart4@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x2181 /* MX28_PAD_SSP3_SCK__AUART4_TX */
+                                                0x2191 /* MX28_PAD_SSP3_MOSI__AUART4_RX */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
                                mac0_pins_a: mac0@0 {
                                        reg = <0>;
                                        fsl,pinmux-ids = <
@@ -669,7 +706,7 @@
                        };
                        digctl@8001c000 {
-                                compatible = "fsl,imx28-digctl";
+                                compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
                                reg = <0x8001c000 0x2000>;
                                interrupts = <89>;
                                status = "disabled";
@@ -699,7 +736,7 @@
                        dcp@80028000 {
                                reg = <0x80028000 0x2000>;
                                interrupts = <52 53 54>;
-                                status = "disabled";
+                                compatible = "fsl-dcp";
                        };
                        pxp@8002a000 {
@@ -800,6 +837,7 @@
                                compatible = "fsl,imx28-saif";
                                reg = <0x80042000 0x2000>;
                                interrupts = <59 80>;
+                                #clock-cells = <0>;
                                clocks = <&clks 53>;
                                dmas = <&dma_apbx 4>;
                                dma-names = "rx-tx";
diff --git a/arch/arm/boot/dts/imx51-apf51.dts b/arch/arm/boot/dts/imx51-apf51.dts
index 2bcf6981d490..8f7f9ac0b989 100644
--- a/arch/arm/boot/dts/imx51-apf51.dts
+++ b/arch/arm/boot/dts/imx51-apf51.dts
@@ -45,6 +45,13 @@
        status = "okay";
 };
+&nfc {
+        nand-bus-width = <8>;
+        nand-ecc-mode = "hw";
+        nand-on-flash-bbt;
+        status = "okay";
+};
 &uart3 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_uart3_2>;
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index 6dd9486c755b..ad3471ca17c7 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -61,6 +61,16 @@
                mux-int-port = <2>;
                mux-ext-port = <3>;
        };
+        clocks {
+                clk_26M: codec_clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <26000000>;
+                        gpios = <&gpio4 26 1>;
+                };
+        };
 };
 &esdhc1 {
@@ -229,6 +239,7 @@
                                MX51_PAD_EIM_A27__GPIO2_21   0x5
                                MX51_PAD_CSPI1_SS0__GPIO4_24 0x85
                                MX51_PAD_CSPI1_SS1__GPIO4_25 0x85
+                                MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000
                        >;
                };
        };
@@ -255,7 +266,7 @@
        sgtl5000: codec@0a {
                compatible = "fsl,sgtl5000";
                reg = <0x0a>;
-                clock-frequency = <26000000>;
+                clocks = <&clk_26M>;
                VDDA-supply = <&vdig_reg>;
                VDDIO-supply = <&vvideo_reg>;
        };
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 53fdde69bbf4..25764b505a61 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -175,10 +175,20 @@
                                };
                        };
+                        usbphy0: usbphy@0 {
+                                compatible = "usb-nop-xceiv";
+                                clocks = <&clks 124>;
+                                clock-names = "main_clk";
+                                status = "okay";
+                        };
                        usbotg: usb@73f80000 {
                                compatible = "fsl,imx51-usb", "fsl,imx27-usb";
                                reg = <0x73f80000 0x0200>;
                                interrupts = <18>;
+                                clocks = <&clks 108>;
+                                fsl,usbmisc = <&usbmisc 0>;
+                                fsl,usbphy = <&usbphy0>;
                                status = "disabled";
                        };
@@ -186,6 +196,8 @@
                                compatible = "fsl,imx51-usb", "fsl,imx27-usb";
                                reg = <0x73f80200 0x0200>;
                                interrupts = <14>;
+                                clocks = <&clks 108>;
+                                fsl,usbmisc = <&usbmisc 1>;
                                status = "disabled";
                        };
@@ -193,6 +205,8 @@
                                compatible = "fsl,imx51-usb", "fsl,imx27-usb";
                                reg = <0x73f80400 0x0200>;
                                interrupts = <16>;
+                                clocks = <&clks 108>;
+                                fsl,usbmisc = <&usbmisc 2>;
                                status = "disabled";
                        };
@@ -200,9 +214,18 @@
                                compatible = "fsl,imx51-usb", "fsl,imx27-usb";
                                reg = <0x73f80600 0x0200>;
                                interrupts = <17>;
+                                clocks = <&clks 108>;
+                                fsl,usbmisc = <&usbmisc 3>;
                                status = "disabled";
                        };
+                        usbmisc: usbmisc@73f80800 {
+                                #index-cells = <1>;
+                                compatible = "fsl,imx51-usbmisc";
+                                reg = <0x73f80800 0x200>;
+                                clocks = <&clks 108>;
+                        };
                        gpio1: gpio@73f84000 {
                                compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
                                reg = <0x73f84000 0x4000>;
diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts
new file mode 100644
index 000000000000..7d304d02ed38
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-m53evk.dts
@@ -0,0 +1,259 @@
+/*
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+#include "imx53.dtsi"
+/ {
+        model = "DENX M53EVK";
+        compatible = "denx,imx53-m53evk", "fsl,imx53";
+        memory {
+                reg = <0x70000000 0x20000000>;
+        };
+        soc {
+                display@di1 {
+                        compatible = "fsl,imx-parallel-display";
+                        crtcs = <&ipu 1>;
+                        interface-pix-fmt = "bgr666";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_ipu_disp2_1>;
+                        display-timings {
+                                800x480p60 {
+                                        native-mode;
+                                        clock-frequency = <31500000>;
+                                        hactive = <800>;
+                                        vactive = <480>;
+                                        hfront-porch = <40>;
+                                        hback-porch = <88>;
+                                        hsync-len = <128>;
+                                        vback-porch = <33>;
+                                        vfront-porch = <9>;
+                                        vsync-len = <3>;
+                                        vsync-active = <1>;
+                                };
+                        };
+                };
+        };
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm1 0 3000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+        };
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pin_gpio>;
+                user1 {
+                        label = "user1";
+                        gpios = <&gpio2 8 0>;
+                        linux,default-trigger = "heartbeat";
+                };
+                user2 {
+                        label = "user2";
+                        gpios = <&gpio2 9 0>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+        regulators {
+                compatible = "simple-bus";
+                reg_3p2v: 3p2v {
+                        compatible = "regulator-fixed";
+                        regulator-name = "3P2V";
+                        regulator-min-microvolt = <3200000>;
+                        regulator-max-microvolt = <3200000>;
+                        regulator-always-on;
+                };
+        };
+        sound {
+                compatible = "fsl,imx53-m53evk-sgtl5000",
+                             "fsl,imx-audio-sgtl5000";
+                model = "imx53-m53evk-sgtl5000";
+                ssi-controller = <&ssi2>;
+                audio-codec = <&sgtl5000>;
+                audio-routing =
+                        "MIC_IN", "Mic Jack",
+                        "Mic Jack", "Mic Bias",
+                        "LINE_IN", "Line In Jack",
+                        "Headphone Jack", "HP_OUT",
+                        "Ext Spk", "LINE_OUT";
+                mux-int-port = <2>;
+                mux-ext-port = <4>;
+        };
+};
+&audmux {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux_2>;
+        status = "okay";
+};
+&can1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_can1_3>;
+        status = "okay";
+};
+&can2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_can2_1>;
+        status = "okay";
+};
+&esdhc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc1_1>;
+        cd-gpios = <&gpio1 1 0>;
+        wp-gpios = <&gpio1 9 0>;
+        status = "okay";
+};
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec_1>;
+        phy-mode = "rmii";
+        status = "okay";
+};
+&i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1_2>;
+        status = "okay";
+        sgtl5000: codec@0a {
+                compatible = "fsl,sgtl5000";
+                reg = <0x0a>;
+                VDDA-supply = <&reg_3p2v>;
+                VDDIO-supply = <&reg_3p2v>;
+                clocks = <&clks 150>;
+        };
+};
+&i2c2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2_2>;
+        clock-frequency = <400000>;
+        status = "okay";
+        stmpe610@41 {
+                compatible = "st,stmpe610";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0x41>;
+                id = <0>;
+                blocks = <0x5>;
+                interrupts = <6 0x0>;
+                interrupt-parent = <&gpio7>;
+                irq-trigger = <0x1>;
+                stmpe_touchscreen {
+                        compatible = "stmpe,ts";
+                        reg = <0>;
+                        ts,sample-time = <4>;
+                        ts,mod-12b = <1>;
+                        ts,ref-sel = <0>;
+                        ts,adc-freq = <1>;
+                        ts,ave-ctrl = <3>;
+                        ts,touch-det-delay = <3>;
+                        ts,settling = <4>;
+                        ts,fraction-z = <7>;
+                        ts,i-drive = <1>;
+                };
+        };
+        eeprom: eeprom@50 {
+                compatible = "atmel,24c128";
+                reg = <0x50>;
+                pagesize = <32>;
+        };
+        rtc: rtc@68 {
+                compatible = "stm,m41t62";
+                reg = <0x68>;
+        };
+};
+&i2c3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c3_1>;
+        status = "okay";
+};
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+        hog {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK       0x80000000
+                                MX53_PAD_EIM_EB3__GPIO2_31              0x80000000
+                                MX53_PAD_PATA_DA_0__GPIO7_6             0x80000000
+                                MX53_PAD_DISP0_DAT8__PWM1_PWMO          0x5
+                        >;
+                };
+                led_pin_gpio: led_gpio@0 {
+                        fsl,pins = <
+                                MX53_PAD_PATA_DATA8__GPIO2_8            0x80000000
+                                MX53_PAD_PATA_DATA9__GPIO2_9            0x80000000
+                        >;
+                };
+        };
+};
+&nfc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_nand_1>;
+        nand-bus-width = <8>;
+        nand-ecc-mode = "hw";
+        status = "okay";
+};
+&pwm1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm1_1>;
+        status = "okay";
+};
+&ssi2 {
+        fsl,mode = "i2s-slave";
+        status = "okay";
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1_2>;
+        status = "okay";
+};
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2_1>;
+        status = "okay";
+};
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart3_1>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx53-mba53.dts b/arch/arm/boot/dts/imx53-mba53.dts
index 445a01119cc5..a63090267941 100644
--- a/arch/arm/boot/dts/imx53-mba53.dts
+++ b/arch/arm/boot/dts/imx53-mba53.dts
@@ -16,27 +16,81 @@
 / {
        model = "TQ MBa53 starter kit";
        compatible = "tq,mba53", "tq,tqma53", "fsl,imx53";
+        reg_backlight: fixed@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "lcd-supply";
+                gpio = <&gpio2 5 0>;
+                startup-delay-us = <5000>;
+                enable-active-low;
+        };
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm2 0 50000>;
+                brightness-levels = <0 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100>;
+                default-brightness-level = <10>;
+                enable-gpios = <&gpio7 7 0>;
+                power-supply = <&reg_backlight>;
+        };
+        disp1: display@disp1 {
+                compatible = "fsl,imx-parallel-display";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_disp1_1>;
+                crtcs = <&ipu 1>;
+                interface-pix-fmt = "rgb24";
+                status = "disabled";
+        };
+        reg_3p2v: 3p2v {
+                compatible = "regulator-fixed";
+                regulator-name = "3P2V";
+                regulator-min-microvolt = <3200000>;
+                regulator-max-microvolt = <3200000>;
+                regulator-always-on;
+        };
+        sound {
+                compatible = "tq,imx53-mba53-sgtl5000",
+                             "fsl,imx-audio-sgtl5000";
+                model = "imx53-mba53-sgtl5000";
+                ssi-controller = <&ssi2>;
+                audio-codec = <&codec>;
+                audio-routing =
+                        "MIC_IN", "Mic Jack",
+                        "Mic Jack", "Mic Bias",
+                        "Headphone Jack", "HP_OUT";
+                mux-int-port = <2>;
+                mux-ext-port = <5>;
+        };
+};
+&ldb {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_lvds1_1>;
+        status = "disabled";
 };
 &iomuxc {
        lvds1 {
                pinctrl_lvds1_1: lvds1-grp1 {
                        fsl,pins = <
-                                MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x10000
+                                MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
-                                MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x10000
+                                MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
-                                MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x10000
+                                MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
-                                MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x10000
+                                MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
-                                MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x10000
+                                MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
                        >;
                };
                pinctrl_lvds1_2: lvds1-grp2 {
                        fsl,pins = <
-                                MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x10000
+                                MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
-                                MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x10000
+                                MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
-                                MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x10000
+                                MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
-                                MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x10000
+                                MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
-                                MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x10000
+                                MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
                        >;
                };
        };
@@ -44,33 +98,44 @@
        disp1 {
                pinctrl_disp1_1: disp1-grp1 {
                        fsl,pins = <
-                                MX53_PAD_EIM_DA10__IPU_DI1_PIN15   0x10000 /* DISP1_DRDY */
+                                MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x80000000 /* DISP1_CLK */
-                                MX53_PAD_EIM_D23__IPU_DI1_PIN2     0x10000 /* DISP1_HSYNC */
+                                MX53_PAD_EIM_DA10__IPU_DI1_PIN15   0x80000000 /* DISP1_DRDY */
-                                MX53_PAD_EIM_EB3__IPU_DI1_PIN3     0x10000 /* DISP1_VSYNC */
+                                MX53_PAD_EIM_D23__IPU_DI1_PIN2     0x80000000 /* DISP1_HSYNC */
-                                MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x10000
+                                MX53_PAD_EIM_EB3__IPU_DI1_PIN3     0x80000000 /* DISP1_VSYNC */
-                                MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x10000
+                                MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x80000000
-                                MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x10000
+                                MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x80000000
-                                MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x10000
+                                MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x80000000
-                                MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x10000
+                                MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x80000000
-                                MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x10000
+                                MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x80000000
-                                MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x10000
+                                MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x80000000
-                                MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x10000
+                                MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x80000000
-                                MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x10000
+                                MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x80000000
-                                MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x10000
+                                MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x80000000
-                                MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x10000
+                                MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x80000000
-                                MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x10000
+                                MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x80000000
-                                MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x10000
+                                MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x80000000
-                                MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x10000
+                                MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x80000000
-                                MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9  0x10000
+                                MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x80000000
-                                MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8  0x10000
+                                MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9  0x80000000
-                                MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7  0x10000
+                                MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8  0x80000000
-                                MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6  0x10000
+                                MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7  0x80000000
-                                MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5  0x10000
+                                MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6  0x80000000
-                                MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4  0x10000
+                                MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5  0x80000000
-                                MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3  0x10000
+                                MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4  0x80000000
-                                MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2  0x10000
+                                MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3  0x80000000
-                                MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1  0x10000
+                                MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2  0x80000000
-                                MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0  0x10000
+                                MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1  0x80000000
+                                MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0  0x80000000
+                        >;
+                };
+        };
+        tve {
+                pinctrl_vga_sync_1: vgasync-grp1 {
+                        fsl,pins = <
+                                /* VGA_VSYNC, HSYNC with max drive strength */
+                                MX53_PAD_EIM_CS1__IPU_DI1_PIN6     0xe6
+                                MX53_PAD_EIM_DA15__IPU_DI1_PIN4    0xe6
                        >;
                };
        };
@@ -80,16 +145,27 @@
        status = "okay";
 };
+&audmux {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux_1>;
+};
 &i2c2 {
        codec: sgtl5000@a {
                compatible = "fsl,sgtl5000";
                reg = <0x0a>;
+                clocks = <&clks 150>;
+                VDDA-supply = <&reg_3p2v>;
+                VDDIO-supply = <&reg_3p2v>;
        };
        expander: pca9554@20 {
                compatible = "pca9554";
                reg = <0x20>;
                interrupts = <109>;
+                #gpio-cells = <2>;
+                gpio-controller;
        };
        sensor2: lm75@49 {
@@ -99,6 +175,7 @@
 };
 &fec {
+        phy-reset-gpios = <&gpio7 6 0>;
        status = "okay";
 };
@@ -114,10 +191,24 @@
        status = "okay";
 };
+&usbotg {
+        dr_mode = "host";
+        status = "okay";
+};
+&usbh1 {
+        status = "okay";
+};
 &uart1 {
        status = "okay";
 };
+&ssi2 {
+        fsl,mode = "i2s-slave";
+        status = "okay";
+};
 &uart2 {
        status = "okay";
 };
@@ -133,3 +224,13 @@
 &i2c3 {
        status = "okay";
 };
+&tve {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_vga_sync_1>;
+        ddc = <&i2c3>;
+        fsl,tve-mode = "vga";
+        fsl,hsync-pin = <4>;
+        fsl,vsync-pin = <6>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
index 8f0e9ae0e3e6..512a1f608253 100644
--- a/arch/arm/boot/dts/imx53-qsb.dts
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -21,6 +21,33 @@
                reg = <0x70000000 0x40000000>;
        };
+        display@di0 {
+                compatible = "fsl,imx-parallel-display";
+                crtcs = <&ipu 0>;
+                interface-pix-fmt = "rgb565";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_ipu_disp0_1>;
+                status = "disabled";
+                display-timings {
+                        claawvga {
+                                native-mode;
+                                clock-frequency = <27000000>;
+                                hactive = <800>;
+                                vactive = <480>;
+                                hback-porch = <40>;
+                                hfront-porch = <60>;
+                                vback-porch = <10>;
+                                vfront-porch = <10>;
+                                hsync-len = <20>;
+                                vsync-len = <10>;
+                                hsync-active = <0>;
+                                vsync-active = <0>;
+                                de-active = <1>;
+                                pixelclk-active = <0>;
+                        };
+                };
+        };
        gpio-keys {
                compatible = "gpio-keys";
@@ -147,6 +174,7 @@
                reg = <0x0a>;
                VDDA-supply = <&reg_3p2v>;
                VDDIO-supply = <&reg_3p2v>;
+                clocks = <&clks 150>;
        };
 };
@@ -268,3 +296,11 @@
        phy-reset-gpios = <&gpio7 6 0>;
        status = "okay";
 };
+&usbh1 {
+       status = "okay";
+};
+&usbotg {
+       status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx53-tqma53.dtsi b/arch/arm/boot/dts/imx53-tqma53.dtsi
index 38bed3ed7c1a..abd72af545bf 100644
--- a/arch/arm/boot/dts/imx53-tqma53.dtsi
+++ b/arch/arm/boot/dts/imx53-tqma53.dtsi
@@ -35,7 +35,9 @@
 &esdhc2 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_esdhc2_1>;
+        pinctrl-0 = <&pinctrl_esdhc2_1>,
+                    <&pinctrl_tqma53_esdhc2_2>;
+        vmmc-supply = <&reg_3p3v>;
        wp-gpios = <&gpio1 2 0>;
        cd-gpios = <&gpio1 4 0>;
        status = "disabled";
@@ -69,14 +71,22 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_hog>;
+        esdhc2_2 {
+                pinctrl_tqma53_esdhc2_2: esdhc2-tqma53-grp2 {
+                        fsl,pins = <
+                                MX53_PAD_GPIO_4__GPIO1_4        0x80000000 /* SD2_CD */
+                                MX53_PAD_GPIO_2__GPIO1_2        0x80000000 /* SD2_WP */
+                        >;
+                };
+        };
        i2s {
                pinctrl_i2s_1: i2s-grp1 {
                        fsl,pins = <
-                                 MX53_PAD_GPIO_19__GPIO4_5           0x10000 /* I2S_MCLK */
+                                 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC  0x80000000 /* I2S_SCLK */
-                                 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC  0x10000 /* I2S_SCLK */
+                                 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD  0x80000000 /* I2S_DOUT */
-                                 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD  0x10000 /* I2S_DOUT */
+                                 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 /* I2S_LRCLK */
-                                 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x10000 /* I2S_LRCLK */
+                                 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD  0x80000000 /* I2S_DIN */
-                                 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD  0x10000 /* I2S_DIN */
                        >;
                };
        };
@@ -84,16 +94,17 @@
        hog {
                pinctrl_hog: hoggrp {
                        fsl,pins = <
-                                 MX53_PAD_EIM_CS1__IPU_DI1_PIN6  0x10000 /* VSYNC */
+                                 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 /* SSI_MCLK */
-                                 MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0x10000 /* HSYNC */
+                                 MX53_PAD_PATA_DA_1__GPIO7_7     0x80000000 /* LCD_BLT_EN */
-                                 MX53_PAD_PATA_DA_1__GPIO7_7     0x10000 /* LCD_BLT_EN */
+                                 MX53_PAD_PATA_DA_2__GPIO7_8     0x80000000 /* LCD_RESET */
-                                 MX53_PAD_PATA_DA_2__GPIO7_8     0x10000 /* LCD_RESET */
+                                 MX53_PAD_PATA_DATA5__GPIO2_5    0x80000000 /* LCD_POWER */
-                                 MX53_PAD_PATA_DATA5__GPIO2_5    0x10000 /* LCD_POWER */
+                                 MX53_PAD_PATA_DATA6__GPIO2_6    0x80000000 /* PMIC_INT */
-                                 MX53_PAD_PATA_DATA6__GPIO2_6    0x10000 /* PMIC_INT */
+                                 MX53_PAD_PATA_DATA14__GPIO2_14  0x80000000 /* CSI_RST */
-                                 MX53_PAD_PATA_DATA14__GPIO2_14  0x10000 /* CSI_RST */
+                                 MX53_PAD_PATA_DATA15__GPIO2_15  0x80000000 /* CSI_PWDN */
-                                 MX53_PAD_PATA_DATA15__GPIO2_15  0x10000 /* CSI_PWDN */
+                                 MX53_PAD_GPIO_19__GPIO4_5       0x80000000 /* #SYSTEM_DOWN */
-                                 MX53_PAD_GPIO_0__GPIO1_0        0x10000 /* SYSTEM_DOWN */
+                                 MX53_PAD_GPIO_3__GPIO1_3        0x80000000
-                                 MX53_PAD_GPIO_3__GPIO1_3        0x10000
+                                 MX53_PAD_PATA_DA_0__GPIO7_6     0x80000000 /* #PHY_RESET */
+                                 MX53_PAD_GPIO_1__PWM2_PWMO      0x80000000 /* LCD_CONTRAST */
                        >;
                };
        };
@@ -149,7 +160,7 @@
                reg = <0x8>;
                fsl,mc13xxx-uses-rtc;
                interrupt-parent = <&gpio2>;
-                interrupts = <6 8>; /* PDATA_DATA6, low active */
+                interrupts = <6 4>; /* PATA_DATA6, active high */
        };
        sensor1: lm75@48 {
diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi b/arch/arm/boot/dts/imx53-tx53.dtsi
new file mode 100644
index 000000000000..f494766700a3
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-tx53.dtsi
@@ -0,0 +1,122 @@
+/*
+ * Copyright 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/include/ "imx53.dtsi"
+/ {
+        model = "Ka-Ro TX53";
+        compatible = "karo,tx53", "fsl,imx53";
+        memory {
+                reg = <0x70000000 0x40000000>; /* Up to 1GiB */
+        };
+        regulators {
+                compatible = "simple-bus";
+                reg_3p3v: 3p3v {
+                        compatible = "regulator-fixed";
+                        regulator-name = "3P3V";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+        };
+};
+&can1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_can1_2>;
+        status = "disabled";
+};
+&can2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_can2_1>;
+        status = "disabled";
+};
+&ecspi1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ecspi1_2>;
+        status = "disabled";
+};
+&esdhc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc1_2>;
+        status = "disabled";
+};
+&esdhc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc2_1>;
+        status = "disabled";
+};
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec_1>;
+        phy-mode = "rmii";
+        status = "disabled";
+};
+&i2c3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c3_2>;
+        status = "disabled";
+};
+&owire {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_owire_1>;
+        status = "disabled";
+};
+&pwm2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm2_1>;
+        status = "disabled";
+};
+&ssi1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux_1>;
+        status = "disabled";
+};
+&ssi2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux_2>;
+        status = "disabled";
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1_2>,
+                    <&pinctrl_uart1_3>;
+        fsl,uart-has-rtscts;
+        status = "disabled";
+};
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2_2>;
+        fsl,uart-has-rtscts;
+        status = "disabled";
+};
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart3_1>;
+        fsl,uart-has-rtscts;
+        status = "disabled";
+};
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index eb83aa039b8b..569aa9f2c4ed 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -27,6 +27,9 @@
                gpio4 = &gpio5;
                gpio5 = &gpio6;
                gpio6 = &gpio7;
+                i2c0 = &i2c1;
+                i2c1 = &i2c2;
+                i2c2 = &i2c3;
        };
        tzic: tz-interrupt-controller@0fffc000 {
@@ -163,10 +166,27 @@
                                };
                        };
+                        usbphy0: usbphy@0 {
+                                compatible = "usb-nop-xceiv";
+                                clocks = <&clks 124>;
+                                clock-names = "main_clk";
+                                status = "okay";
+                        };
+                        usbphy1: usbphy@1 {
+                                compatible = "usb-nop-xceiv";
+                                clocks = <&clks 125>;
+                                clock-names = "main_clk";
+                                status = "okay";
+                        };
                        usbotg: usb@53f80000 {
                                compatible = "fsl,imx53-usb", "fsl,imx27-usb";
                                reg = <0x53f80000 0x0200>;
                                interrupts = <18>;
+                                clocks = <&clks 108>;
+                                fsl,usbmisc = <&usbmisc 0>;
+                                fsl,usbphy = <&usbphy0>;
                                status = "disabled";
                        };
@@ -174,6 +194,9 @@
                                compatible = "fsl,imx53-usb", "fsl,imx27-usb";
                                reg = <0x53f80200 0x0200>;
                                interrupts = <14>;
+                                clocks = <&clks 108>;
+                                fsl,usbmisc = <&usbmisc 1>;
+                                fsl,usbphy = <&usbphy1>;
                                status = "disabled";
                        };
@@ -181,6 +204,8 @@
                                compatible = "fsl,imx53-usb", "fsl,imx27-usb";
                                reg = <0x53f80400 0x0200>;
                                interrupts = <16>;
+                                clocks = <&clks 108>;
+                                fsl,usbmisc = <&usbmisc 2>;
                                status = "disabled";
                        };
@@ -188,9 +213,18 @@
                                compatible = "fsl,imx53-usb", "fsl,imx27-usb";
                                reg = <0x53f80600 0x0200>;
                                interrupts = <17>;
+                                clocks = <&clks 108>;
+                                fsl,usbmisc = <&usbmisc 3>;
                                status = "disabled";
                        };
+                        usbmisc: usbmisc@53f80800 {
+                                #index-cells = <1>;
+                                compatible = "fsl,imx53-usbmisc";
+                                reg = <0x53f80800 0x200>;
+                                clocks = <&clks 108>;
+                        };
                        gpio1: gpio@53f84000 {
                                compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
                                reg = <0x53f84000 0x4000>;
@@ -267,6 +301,24 @@
                                                        MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD  0x80000000
                                                >;
                                        };
+                                        pinctrl_audmux_2: audmuxgrp-2 {
+                                                fsl,pins = <
+                                                        MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC     0x80000000
+                                                        MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD     0x80000000
+                                                        MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS    0x80000000
+                                                        MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD     0x80000000
+                                                >;
+                                        };
+                                        pinctrl_audmux_3: audmuxgrp-3 {
+                                                fsl,pins = <
+                                                        MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC     0x80000000
+                                                        MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD     0x80000000
+                                                        MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS    0x80000000
+                                                        MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD     0x80000000
+                                                >;
+                                        };
                                };
                                fec {
@@ -284,6 +336,29 @@
                                                        MX53_PAD_FEC_TXD0__FEC_TDATA_0   0x80000000
                                                >;
                                        };
+                                        pinctrl_fec_2: fecgrp-2 {
+                                                fsl,pins = <
+                                                        MX53_PAD_FEC_MDC__FEC_MDC        0x80000000
+                                                        MX53_PAD_FEC_MDIO__FEC_MDIO      0x80000000
+                                                        MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
+                                                        MX53_PAD_FEC_RX_ER__FEC_RX_ER    0x80000000
+                                                        MX53_PAD_FEC_CRS_DV__FEC_RX_DV   0x80000000
+                                                        MX53_PAD_FEC_RXD1__FEC_RDATA_1   0x80000000
+                                                        MX53_PAD_FEC_RXD0__FEC_RDATA_0   0x80000000
+                                                        MX53_PAD_FEC_TX_EN__FEC_TX_EN    0x80000000
+                                                        MX53_PAD_FEC_TXD1__FEC_TDATA_1   0x80000000
+                                                        MX53_PAD_FEC_TXD0__FEC_TDATA_0   0x80000000
+                                                        MX53_PAD_KEY_ROW1__FEC_COL       0x80000000
+                                                        MX53_PAD_KEY_COL3__FEC_CRS       0x80000000
+                                                        MX53_PAD_KEY_COL2__FEC_RDATA_2   0x80000000
+                                                        MX53_PAD_KEY_COL0__FEC_RDATA_3   0x80000000
+                                                        MX53_PAD_KEY_COL1__FEC_RX_CLK    0x80000000
+                                                        MX53_PAD_KEY_ROW2__FEC_TDATA_2   0x80000000
+                                                        MX53_PAD_GPIO_19__FEC_TDATA_3    0x80000000
+                                                        MX53_PAD_KEY_ROW0__FEC_TX_ER     0x80000000
+                                                >;
+                                        };
                                };
                                csi {
@@ -312,6 +387,22 @@
                                                        MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK   0x1d5
                                                >;
                                        };
+                                        pinctrl_csi_2: csigrp-2 {
+                                                fsl,pins = <
+                                                        MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC     0x1d5
+                                                        MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC      0x1d5
+                                                        MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK   0x1d5
+                                                        MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19      0x1d5
+                                                        MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18      0x1d5
+                                                        MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17      0x1d5
+                                                        MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16      0x1d5
+                                                        MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15      0x1d5
+                                                        MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14      0x1d5
+                                                        MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13      0x1d5
+                                                        MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12      0x1d5
+                                                >;
+                                        };
                                };
                                cspi {
@@ -322,6 +413,14 @@
                                                        MX53_PAD_SD1_CLK__CSPI_SCLK   0x1d5
                                                >;
                                        };
+                                        pinctrl_cspi_2: cspigrp-2 {
+                                                fsl,pins = <
+                                                        MX53_PAD_EIM_D22__CSPI_MISO 0x1d5
+                                                        MX53_PAD_EIM_D28__CSPI_MOSI 0x1d5
+                                                        MX53_PAD_EIM_D21__CSPI_SCLK 0x1d5
+                                                >;
+                                        };
                                };
                                ecspi1 {
@@ -332,6 +431,27 @@
                                                        MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
                                                >;
                                        };
+                                        pinctrl_ecspi1_2: ecspi1grp-2 {
+                                                fsl,pins = <
+                                                        MX53_PAD_GPIO_19__ECSPI1_RDY    0x80000000
+                                                        MX53_PAD_EIM_EB2__ECSPI1_SS0    0x80000000
+                                                        MX53_PAD_EIM_D16__ECSPI1_SCLK   0x80000000
+                                                        MX53_PAD_EIM_D17__ECSPI1_MISO   0x80000000
+                                                        MX53_PAD_EIM_D18__ECSPI1_MOSI   0x80000000
+                                                        MX53_PAD_EIM_D19__ECSPI1_SS1    0x80000000
+                                                >;
+                                        };
+                                };
+                                ecspi2 {
+                                        pinctrl_ecspi2_1: ecspi2grp-1 {
+                                                fsl,pins = <
+                                                        MX53_PAD_EIM_OE__ECSPI2_MISO  0x80000000
+                                                        MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x80000000
+                                                        MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x80000000
+                                                >;
+                                        };
                                };
                                esdhc1 {
@@ -406,6 +526,13 @@
                                                        MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
                                                >;
                                        };
+                                        pinctrl_can1_3: can1grp-3 {
+                                                fsl,pins = <
+                                                        MX53_PAD_GPIO_7__CAN1_TXCAN     0x80000000
+                                                        MX53_PAD_GPIO_8__CAN1_RXCAN     0x80000000
+                                                >;
+                                        };
                                };
                                can2 {
@@ -424,6 +551,13 @@
                                                        MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
                                                >;
                                        };
+                                        pinctrl_i2c1_2: i2c1grp-2 {
+                                                fsl,pins = <
+                                                        MX53_PAD_EIM_D21__I2C1_SCL      0xc0000000
+                                                        MX53_PAD_EIM_D28__I2C1_SDA      0xc0000000
+                                                >;
+                                        };
                                };
                                i2c2 {
@@ -433,6 +567,13 @@
                                                        MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
                                                >;
                                        };
+                                        pinctrl_i2c2_2: i2c2grp-2 {
+                                                fsl,pins = <
+                                                        MX53_PAD_EIM_D16__I2C2_SDA      0xc0000000
+                                                        MX53_PAD_EIM_EB2__I2C2_SCL      0xc0000000
+                                                >;
+                                        };
                                };
                                i2c3 {
@@ -444,6 +585,119 @@
                                        };
                                };
+                                ipu_disp0 {
+                                        pinctrl_ipu_disp0_1: ipudisp0grp-1 {
+                                                fsl,pins = <
+                                                MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
+                                                MX53_PAD_DI0_PIN15__IPU_DI0_PIN15               0x5
+                                                MX53_PAD_DI0_PIN2__IPU_DI0_PIN2         0x5
+                                                MX53_PAD_DI0_PIN3__IPU_DI0_PIN3                 0x5
+                                                MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0            0x5
+                                                MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1            0x5
+                                                MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2            0x5
+                                                MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3            0x5
+                                                MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4            0x5
+                                                MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5            0x5
+                                                MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6            0x5
+                                                MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7            0x5
+                                                MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8            0x5
+                                                MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9            0x5
+                                                MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10          0x5
+                                                MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11          0x5
+                                                MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12          0x5
+                                                MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13          0x5
+                                                MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14          0x5
+                                                MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15          0x5
+                                                MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16          0x5
+                                                MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17          0x5
+                                                MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18          0x5
+                                                MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19          0x5
+                                                MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20          0x5
+                                                MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21          0x5
+                                                MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22          0x5
+                                                MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23          0x5
+                                                >;
+                                        };
+                                };
+                                ipu_disp1 {
+                                        pinctrl_ipu_disp1_1: ipudisp1grp-1 {
+                                                fsl,pins = <
+                                                        MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0       0x5
+                                                        MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1       0x5
+                                                        MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2       0x5
+                                                        MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3       0x5
+                                                        MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4       0x5
+                                                        MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5       0x5
+                                                        MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6       0x5
+                                                        MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7       0x5
+                                                        MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8       0x5
+                                                        MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9       0x5
+                                                        MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10      0x5
+                                                        MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11      0x5
+                                                        MX53_PAD_EIM_A17__IPU_DISP1_DAT_12      0x5
+                                                        MX53_PAD_EIM_A18__IPU_DISP1_DAT_13      0x5
+                                                        MX53_PAD_EIM_A19__IPU_DISP1_DAT_14      0x5
+                                                        MX53_PAD_EIM_A20__IPU_DISP1_DAT_15      0x5
+                                                        MX53_PAD_EIM_A21__IPU_DISP1_DAT_16      0x5
+                                                        MX53_PAD_EIM_A22__IPU_DISP1_DAT_17      0x5
+                                                        MX53_PAD_EIM_A23__IPU_DISP1_DAT_18      0x5
+                                                        MX53_PAD_EIM_A24__IPU_DISP1_DAT_19      0x5
+                                                        MX53_PAD_EIM_D31__IPU_DISP1_DAT_20      0x5
+                                                        MX53_PAD_EIM_D30__IPU_DISP1_DAT_21      0x5
+                                                        MX53_PAD_EIM_D26__IPU_DISP1_DAT_22      0x5
+                                                        MX53_PAD_EIM_D27__IPU_DISP1_DAT_23      0x5
+                                                        MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK      0x5
+                                                        MX53_PAD_EIM_DA13__IPU_DI1_D0_CS        0x5
+                                                        MX53_PAD_EIM_DA14__IPU_DI1_D1_CS        0x5
+                                                        MX53_PAD_EIM_DA15__IPU_DI1_PIN1         0x5
+                                                        MX53_PAD_EIM_DA11__IPU_DI1_PIN2         0x5
+                                                        MX53_PAD_EIM_DA12__IPU_DI1_PIN3         0x5
+                                                        MX53_PAD_EIM_A25__IPU_DI1_PIN12         0x5
+                                                        MX53_PAD_EIM_DA10__IPU_DI1_PIN15        0x5
+                                                >;
+                                        };
+                                };
+                                ipu_disp2 {
+                                        pinctrl_ipu_disp2_1: ipudisp2grp-1 {
+                                                fsl,pins = <
+                                                        MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0     0x80000000
+                                                        MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1     0x80000000
+                                                        MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2     0x80000000
+                                                        MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3     0x80000000
+                                                        MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK     0x80000000
+                                                        MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0     0x80000000
+                                                        MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1     0x80000000
+                                                        MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2     0x80000000
+                                                        MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3     0x80000000
+                                                        MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK     0x80000000
+                                                >;
+                                        };
+                                };
+                                nand {
+                                        pinctrl_nand_1: nandgrp-1 {
+                                                fsl,pins = <
+                                                        MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B     0x4
+                                                        MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B     0x4
+                                                        MX53_PAD_NANDF_CLE__EMI_NANDF_CLE       0x4
+                                                        MX53_PAD_NANDF_ALE__EMI_NANDF_ALE       0x4
+                                                        MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B     0xe0
+                                                        MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0      0xe0
+                                                        MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0      0x4
+                                                        MX53_PAD_PATA_DATA0__EMI_NANDF_D_0      0xa4
+                                                        MX53_PAD_PATA_DATA1__EMI_NANDF_D_1      0xa4
+                                                        MX53_PAD_PATA_DATA2__EMI_NANDF_D_2      0xa4
+                                                        MX53_PAD_PATA_DATA3__EMI_NANDF_D_3      0xa4
+                                                        MX53_PAD_PATA_DATA4__EMI_NANDF_D_4      0xa4
+                                                        MX53_PAD_PATA_DATA5__EMI_NANDF_D_5      0xa4
+                                                        MX53_PAD_PATA_DATA6__EMI_NANDF_D_6      0xa4
+                                                        MX53_PAD_PATA_DATA7__EMI_NANDF_D_7      0xa4
+                                                >;
+                                        };
+                                };
                                owire {
                                        pinctrl_owire_1: owiregrp-1 {
                                                fsl,pins = <
@@ -452,18 +706,41 @@
                                        };
                                };
+                                pwm1 {
+                                        pinctrl_pwm1_1: pwm1grp-1 {
+                                                fsl,pins = <
+                                                        MX53_PAD_DISP0_DAT8__PWM1_PWMO  0x5
+                                                >;
+                                        };
+                                };
+                                pwm2 {
+                                        pinctrl_pwm2_1: pwm2grp-1 {
+                                                fsl,pins = <
+                                                        MX53_PAD_GPIO_1__PWM2_PWMO      0x80000000
+                                                >;
+                                        };
+                                };
                                uart1 {
                                        pinctrl_uart1_1: uart1grp-1 {
                                                fsl,pins = <
-                                                        MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1c5
+                                                        MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
-                                                        MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1c5
+                                                        MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
                                                >;
                                        };
                                        pinctrl_uart1_2: uart1grp-2 {
                                                fsl,pins = <
-                                                        MX53_PAD_PATA_DIOW__UART1_TXD_MUX  0x1c5
+                                                        MX53_PAD_PATA_DIOW__UART1_TXD_MUX  0x1e4
-                                                        MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1c5
+                                                        MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
+                                                >;
+                                        };
+                                        pinctrl_uart1_3: uart1grp-3 {
+                                                fsl,pins = <
+                                                        MX53_PAD_PATA_RESET_B__UART1_CTS 0x1c5
+                                                        MX53_PAD_PATA_IORDY__UART1_RTS   0x1c5
                                                >;
                                        };
                                };
@@ -471,8 +748,17 @@
                                uart2 {
                                        pinctrl_uart2_1: uart2grp-1 {
                                                fsl,pins = <
-                                                        MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5
+                                                        MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
-                                                        MX53_PAD_PATA_DMARQ__UART2_TXD_MUX     0x1c5
+                                                        MX53_PAD_PATA_DMARQ__UART2_TXD_MUX     0x1e4
+                                                >;
+                                        };
+                                        pinctrl_uart2_2: uart2grp-2 {
+                                                fsl,pins = <
+                                                        MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX  0x1c5
+                                                        MX53_PAD_PATA_DMARQ__UART2_TXD_MUX      0x1c5
+                                                        MX53_PAD_PATA_DIOR__UART2_RTS           0x1c5
+                                                        MX53_PAD_PATA_INTRQ__UART2_CTS          0x1c5
                                                >;
                                        };
                                };
@@ -480,17 +766,17 @@
                                uart3 {
                                        pinctrl_uart3_1: uart3grp-1 {
                                                fsl,pins = <
-                                                        MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
+                                                        MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
-                                                        MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
+                                                        MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
-                                                        MX53_PAD_PATA_DA_1__UART3_CTS     0x1c5
+                                                        MX53_PAD_PATA_DA_1__UART3_CTS     0x1e4
-                                                        MX53_PAD_PATA_DA_2__UART3_RTS     0x1c5
+                                                        MX53_PAD_PATA_DA_2__UART3_RTS     0x1e4
                                                >;
                                        };
                                        pinctrl_uart3_2: uart3grp-2 {
                                                fsl,pins = <
-                                                        MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
+                                                        MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
-                                                        MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
+                                                        MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
                                                >;
                                        };
@@ -499,8 +785,8 @@
                                uart4 {
                                        pinctrl_uart4_1: uart4grp-1 {
                                                fsl,pins = <
-                                                        MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1c5
+                                                        MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1e4
-                                                        MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1c5
+                                                        MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1e4
                                                >;
                                        };
                                };
@@ -508,12 +794,11 @@
                                uart5 {
                                        pinctrl_uart5_1: uart5grp-1 {
                                                fsl,pins = <
-                                                        MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1c5
+                                                        MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1e4
-                                                        MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1c5
+                                                        MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1e4
                                                >;
                                        };
                                };
                        };
                        gpr: iomuxc-gpr@53fa8000 {
@@ -781,6 +1066,16 @@
                                clock-names = "ipg", "ahb", "ptp";
                                status = "disabled";
                        };
+                        tve: tve@63ff0000 {
+                                compatible = "fsl,imx53-tve";
+                                reg = <0x63ff0000 0x1000>;
+                                interrupts = <92>;
+                                clocks = <&clks 69>, <&clks 116>;
+                                clock-names = "tve", "di_sel";
+                                crtcs = <&ipu 1>;
+                                status = "disabled";
+                        };
                };
        };
 };
diff --git a/arch/arm/boot/dts/imx6dl-sabreauto.dts b/arch/arm/boot/dts/imx6dl-sabreauto.dts
index 7adcec360213..95da71185a4a 100644
--- a/arch/arm/boot/dts/imx6dl-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6dl-sabreauto.dts
@@ -28,4 +28,12 @@
                        >;
                };
        };
+        ecspi1 {
+                pinctrl_ecspi1_sabreauto: ecspi1-sabreauto {
+                        fsl,pins = <
+                                MX6DL_PAD_EIM_D19__GPIO3_IO19  0x80000000
+                        >;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/imx6dl-sabresd.dts b/arch/arm/boot/dts/imx6dl-sabresd.dts
index 7efb05db4783..8989df2b89e5 100644
--- a/arch/arm/boot/dts/imx6dl-sabresd.dts
+++ b/arch/arm/boot/dts/imx6dl-sabresd.dts
@@ -29,6 +29,7 @@
                                MX6DL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
                                MX6DL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
                                MX6DL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
+                                MX6DL_PAD_GPIO_0__CCM_CLKO1    0x130b0
                        >;
                };
        };
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 5bcdf3a90bb3..2b3ecd679350 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -18,12 +18,14 @@
                cpu@0 {
                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
                        reg = <0>;
                        next-level-cache = <&L2>;
                };
                cpu@1 {
                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
                        reg = <1>;
                        next-level-cache = <&L2>;
                };
@@ -35,6 +37,27 @@
                                compatible = "fsl,imx6dl-iomuxc";
                                reg = <0x020e0000 0x4000>;
+                                audmux {
+                                        pinctrl_audmux_2: audmux-2 {
+                                                fsl,pins = <
+                                                        MX6DL_PAD_CSI0_DAT7__AUD3_RXD  0x80000000
+                                                        MX6DL_PAD_CSI0_DAT4__AUD3_TXC  0x80000000
+                                                        MX6DL_PAD_CSI0_DAT5__AUD3_TXD  0x80000000
+                                                        MX6DL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
+                                                >;
+                                        };
+                                };
+                                ecspi1 {
+                                        pinctrl_ecspi1_1: ecspi1grp-1 {
+                                                fsl,pins = <
+                                                        MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+                                                        MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+                                                        MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+                                                >;
+                                        };
+                                };
                                enet {
                                        pinctrl_enet_1: enetgrp-1 {
                                                fsl,pins = <
@@ -78,6 +101,39 @@
                                        };
                                };
+                                gpmi-nand {
+                                        pinctrl_gpmi_nand_1: gpmi-nand-1 {
+                                                fsl,pins = <
+                                                        MX6DL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
+                                                        MX6DL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
+                                                        MX6DL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
+                                                        MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000
+                                                        MX6DL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
+                                                        MX6DL_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
+                                                        MX6DL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
+                                                        MX6DL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
+                                                        MX6DL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
+                                                        MX6DL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
+                                                        MX6DL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
+                                                        MX6DL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
+                                                        MX6DL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
+                                                        MX6DL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
+                                                        MX6DL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
+                                                        MX6DL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
+                                                        MX6DL_PAD_SD4_DAT0__NAND_DQS      0x00b1
+                                                >;
+                                        };
+                                };
+                                i2c1 {
+                                        pinctrl_i2c1_2: i2c1grp-2 {
+                                                fsl,pins = <
+                                                        MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
+                                                        MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
+                                                >;
+                                        };
+                                };
                                uart1 {
                                        pinctrl_uart1_1: uart1grp-1 {
                                                fsl,pins = <
@@ -149,6 +205,64 @@
                                        };
                                };
+                                weim {
+                                        pinctrl_weim_cs0_1: weim_cs0grp-1 {
+                                                fsl,pins = <
+                                                        MX6DL_PAD_EIM_CS0__EIM_CS0_B   0xb0b1
+                                                >;
+                                        };
+                                        pinctrl_weim_nor_1: weim_norgrp-1 {
+                                                fsl,pins = <
+                                                        MX6DL_PAD_EIM_OE__EIM_OE_B     0xb0b1
+                                                        MX6DL_PAD_EIM_RW__EIM_RW       0xb0b1
+                                                        MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
+                                                        /* data */
+                                                        MX6DL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
+                                                        MX6DL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
+                                                        MX6DL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
+                                                        MX6DL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
+                                                        MX6DL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
+                                                        MX6DL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
+                                                        MX6DL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
+                                                        MX6DL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
+                                                        MX6DL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
+                                                        MX6DL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
+                                                        MX6DL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
+                                                        MX6DL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
+                                                        MX6DL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
+                                                        MX6DL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
+                                                        MX6DL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
+                                                        MX6DL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
+                                                        /* address */
+                                                        MX6DL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
+                                                        MX6DL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
+                                                        MX6DL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
+                                                        MX6DL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
+                                                        MX6DL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
+                                                        MX6DL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
+                                                        MX6DL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
+                                                        MX6DL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
+                                                        MX6DL_PAD_EIM_DA15__EIM_AD15  0xb0b1
+                                                        MX6DL_PAD_EIM_DA14__EIM_AD14  0xb0b1
+                                                        MX6DL_PAD_EIM_DA13__EIM_AD13  0xb0b1
+                                                        MX6DL_PAD_EIM_DA12__EIM_AD12  0xb0b1
+                                                        MX6DL_PAD_EIM_DA11__EIM_AD11  0xb0b1
+                                                        MX6DL_PAD_EIM_DA10__EIM_AD10  0xb0b1
+                                                        MX6DL_PAD_EIM_DA9__EIM_AD09   0xb0b1
+                                                        MX6DL_PAD_EIM_DA8__EIM_AD08   0xb0b1
+                                                        MX6DL_PAD_EIM_DA7__EIM_AD07   0xb0b1
+                                                        MX6DL_PAD_EIM_DA6__EIM_AD06   0xb0b1
+                                                        MX6DL_PAD_EIM_DA5__EIM_AD05   0xb0b1
+                                                        MX6DL_PAD_EIM_DA4__EIM_AD04   0xb0b1
+                                                        MX6DL_PAD_EIM_DA3__EIM_AD03   0xb0b1
+                                                        MX6DL_PAD_EIM_DA2__EIM_AD02   0xb0b1
+                                                        MX6DL_PAD_EIM_DA1__EIM_AD01   0xb0b1
+                                                        MX6DL_PAD_EIM_DA0__EIM_AD00   0xb0b1
+                                                >;
+                                        };
+                                };
                        };
diff --git a/arch/arm/boot/dts/imx6q-phytec-pbab01.dts b/arch/arm/boot/dts/imx6q-phytec-pbab01.dts
new file mode 100644
index 000000000000..7d37ec60d58d
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-phytec-pbab01.dts
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+#include "imx6q-phytec-pfla02.dtsi"
+/ {
+        model = "Phytec phyFLEX-i.MX6 Quad Carrier-Board";
+        compatible = "phytec,imx6q-pbab01", "phytec,imx6q-pfla02", "fsl,imx6q";
+};
+&fec {
+        status = "okay";
+};
+&uart4 {
+        status = "okay";
+};
+&usdhc2 {
+        status = "okay";
+};
+&usdhc3 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
new file mode 100644
index 000000000000..f5e1981025ed
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
@@ -0,0 +1,74 @@
+/*
+ * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include "imx6q.dtsi"
+/ {
+        model = "Phytec phyFLEX-i.MX6 Ouad";
+        compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
+        memory {
+                reg = <0x10000000 0x80000000>;
+        };
+};
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+        hog {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                MX6Q_PAD_EIM_D23__GPIO3_IO23    0x80000000
+                        >;
+                };
+        };
+        pfla02 {
+                pinctrl_usdhc3_pfla02: usdhc3grp-pfla02 {
+                        fsl,pins = <
+                                MX6Q_PAD_ENET_RXD0__GPIO1_IO27  0x80000000
+                                MX6Q_PAD_ENET_TXD1__GPIO1_IO29  0x80000000
+                        >;
+                };
+        };
+};
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet_3>;
+        phy-mode = "rgmii";
+        phy-reset-gpios = <&gpio3 23 0>;
+        status = "disabled";
+};
+&uart4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart4_1>;
+        status = "disabled";
+};
+&usdhc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc2_2>;
+        cd-gpios = <&gpio1 4 0>;
+        wp-gpios = <&gpio1 2 0>;
+        status = "disabled";
+};
+&usdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc3_2
+                     &pinctrl_usdhc3_pfla02>;
+        cd-gpios = <&gpio1 27 0>;
+        wp-gpios = <&gpio1 29 0>;
+        status = "disabled";
+};
diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts
index 49d6f2831ec9..09a75807bc6d 100644
--- a/arch/arm/boot/dts/imx6q-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6q-sabreauto.dts
@@ -32,4 +32,12 @@
                        >;
                };
        };
+        ecspi1 {
+                pinctrl_ecspi1_sabreauto: ecspi1-sabreauto {
+                        fsl,pins = <
+                                MX6Q_PAD_EIM_D19__GPIO3_IO19  0x80000000
+                        >;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts
index 442051350225..0038228c508c 100644
--- a/arch/arm/boot/dts/imx6q-sabresd.dts
+++ b/arch/arm/boot/dts/imx6q-sabresd.dts
@@ -33,6 +33,7 @@
                                MX6Q_PAD_NANDF_D1__GPIO2_IO01 0x80000000
                                MX6Q_PAD_NANDF_D2__GPIO2_IO02 0x80000000
                                MX6Q_PAD_NANDF_D3__GPIO2_IO03 0x80000000
+                                MX6Q_PAD_GPIO_0__CCM_CLKO1    0x130b0
                        >;
                };
        };
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 21e675848bd1..ba09dc32324e 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -18,6 +18,7 @@
                cpu@0 {
                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
                        reg = <0>;
                        next-level-cache = <&L2>;
                        operating-points = <
@@ -39,18 +40,21 @@
                cpu@1 {
                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
                        reg = <1>;
                        next-level-cache = <&L2>;
                };
                cpu@2 {
                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
                        reg = <2>;
                        next-level-cache = <&L2>;
                };
                cpu@3 {
                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
                        reg = <3>;
                        next-level-cache = <&L2>;
                };
@@ -157,6 +161,27 @@
                                                        MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
                                                >;
                                        };
+                                        pinctrl_enet_3: enetgrp-3 {
+                                                fsl,pins = <
+                                                        MX6Q_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
+                                                        MX6Q_PAD_ENET_MDC__ENET_MDC         0x1b0b0
+                                                        MX6Q_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
+                                                        MX6Q_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
+                                                        MX6Q_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
+                                                        MX6Q_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
+                                                        MX6Q_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
+                                                        MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+                                                        MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
+                                                        MX6Q_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
+                                                        MX6Q_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
+                                                        MX6Q_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
+                                                        MX6Q_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
+                                                        MX6Q_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
+                                                        MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+                                                        MX6Q_PAD_ENET_TX_EN__ENET_TX_EN     0x1b0b0
+                                                >;
+                                        };
                                };
                                gpmi-nand {
@@ -168,8 +193,6 @@
                                                        MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000
                                                        MX6Q_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
                                                        MX6Q_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
-                                                        MX6Q_PAD_NANDF_CS2__NAND_CE2_B   0xb0b1
-                                                        MX6Q_PAD_NANDF_CS3__NAND_CE3_B   0xb0b1
                                                        MX6Q_PAD_SD4_CMD__NAND_RE_B      0xb0b1
                                                        MX6Q_PAD_SD4_CLK__NAND_WE_B      0xb0b1
                                                        MX6Q_PAD_NANDF_D0__NAND_DATA00   0xb0b1
@@ -192,6 +215,13 @@
                                                        MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
                                                >;
                                        };
+                                        pinctrl_i2c1_2: i2c1grp-2 {
+                                                fsl,pins = <
+                                                        MX6Q_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
+                                                        MX6Q_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
+                                                >;
+                                        };
                                };
                                i2c2 {
@@ -268,6 +298,17 @@
                                                        MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059
                                                >;
                                        };
+                                        pinctrl_usdhc2_2: usdhc2grp-2 {
+                                                fsl,pins = <
+                                                        MX6Q_PAD_SD2_CMD__SD2_CMD    0x17059
+                                                        MX6Q_PAD_SD2_CLK__SD2_CLK    0x10059
+                                                        MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
+                                                        MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
+                                                        MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
+                                                        MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
+                                                >;
+                                        };
                                };
                                usdhc3 {
@@ -325,6 +366,65 @@
                                                >;
                                        };
                                };
+                                weim {
+                                        pinctrl_weim_cs0_1: weim_cs0grp-1 {
+                                                fsl,pins = <
+                                                        MX6Q_PAD_EIM_CS0__EIM_CS0_B   0xb0b1
+                                                >;
+                                        };
+                                        pinctrl_weim_nor_1: weimnorgrp-1 {
+                                                fsl,pins = <
+                                                        MX6Q_PAD_EIM_OE__EIM_OE_B     0xb0b1
+                                                        MX6Q_PAD_EIM_RW__EIM_RW       0xb0b1
+                                                        MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
+                                                        /* data */
+                                                        MX6Q_PAD_EIM_D16__EIM_DATA16 0x1b0b0
+                                                        MX6Q_PAD_EIM_D17__EIM_DATA17 0x1b0b0
+                                                        MX6Q_PAD_EIM_D18__EIM_DATA18 0x1b0b0
+                                                        MX6Q_PAD_EIM_D19__EIM_DATA19 0x1b0b0
+                                                        MX6Q_PAD_EIM_D20__EIM_DATA20 0x1b0b0
+                                                        MX6Q_PAD_EIM_D21__EIM_DATA21 0x1b0b0
+                                                        MX6Q_PAD_EIM_D22__EIM_DATA22 0x1b0b0
+                                                        MX6Q_PAD_EIM_D23__EIM_DATA23 0x1b0b0
+                                                        MX6Q_PAD_EIM_D24__EIM_DATA24 0x1b0b0
+                                                        MX6Q_PAD_EIM_D25__EIM_DATA25 0x1b0b0
+                                                        MX6Q_PAD_EIM_D26__EIM_DATA26 0x1b0b0
+                                                        MX6Q_PAD_EIM_D27__EIM_DATA27 0x1b0b0
+                                                        MX6Q_PAD_EIM_D28__EIM_DATA28 0x1b0b0
+                                                        MX6Q_PAD_EIM_D29__EIM_DATA29 0x1b0b0
+                                                        MX6Q_PAD_EIM_D30__EIM_DATA30 0x1b0b0
+                                                        MX6Q_PAD_EIM_D31__EIM_DATA31 0x1b0b0
+                                                        /* address */
+                                                        MX6Q_PAD_EIM_A23__EIM_ADDR23 0xb0b1
+                                                        MX6Q_PAD_EIM_A22__EIM_ADDR22 0xb0b1
+                                                        MX6Q_PAD_EIM_A21__EIM_ADDR21 0xb0b1
+                                                        MX6Q_PAD_EIM_A20__EIM_ADDR20 0xb0b1
+                                                        MX6Q_PAD_EIM_A19__EIM_ADDR19 0xb0b1
+                                                        MX6Q_PAD_EIM_A18__EIM_ADDR18 0xb0b1
+                                                        MX6Q_PAD_EIM_A17__EIM_ADDR17 0xb0b1
+                                                        MX6Q_PAD_EIM_A16__EIM_ADDR16 0xb0b1
+                                                        MX6Q_PAD_EIM_DA15__EIM_AD15  0xb0b1
+                                                        MX6Q_PAD_EIM_DA14__EIM_AD14  0xb0b1
+                                                        MX6Q_PAD_EIM_DA13__EIM_AD13  0xb0b1
+                                                        MX6Q_PAD_EIM_DA12__EIM_AD12  0xb0b1
+                                                        MX6Q_PAD_EIM_DA11__EIM_AD11  0xb0b1
+                                                        MX6Q_PAD_EIM_DA10__EIM_AD10  0xb0b1
+                                                        MX6Q_PAD_EIM_DA9__EIM_AD09   0xb0b1
+                                                        MX6Q_PAD_EIM_DA8__EIM_AD08   0xb0b1
+                                                        MX6Q_PAD_EIM_DA7__EIM_AD07   0xb0b1
+                                                        MX6Q_PAD_EIM_DA6__EIM_AD06   0xb0b1
+                                                        MX6Q_PAD_EIM_DA5__EIM_AD05   0xb0b1
+                                                        MX6Q_PAD_EIM_DA4__EIM_AD04   0xb0b1
+                                                        MX6Q_PAD_EIM_DA3__EIM_AD03   0xb0b1
+                                                        MX6Q_PAD_EIM_DA2__EIM_AD02   0xb0b1
+                                                        MX6Q_PAD_EIM_DA1__EIM_AD01   0xb0b1
+                                                        MX6Q_PAD_EIM_DA0__EIM_AD00   0xb0b1
+                                                >;
+                                        };
+                                };
                        };
                };
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 4d237cffcc41..e994011220e7 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -16,6 +16,22 @@
        };
 };
+&ecspi1 {
+        fsl,spi-num-chipselects = <1>;
+        cs-gpios = <&gpio3 19 0>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_sabreauto>;
+        status = "disabled"; /* pin conflict with WEIM NOR */
+        flash: m25p80@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "st,m25p32";
+                spi-max-frequency = <20000000>;
+                reg = <0>;
+        };
+};
 &fec {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet_2>;
@@ -23,6 +39,12 @@
        status = "okay";
 };
+&gpmi {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_gpmi_nand_1>;
+        status = "okay";
+};
 &uart4 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_uart4_1>;
@@ -36,3 +58,22 @@
        wp-gpios = <&gpio1 13 0>;
        status = "okay";
 };
+&weim {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs0_1>;
+        #address-cells = <2>;
+        #size-cells = <1>;
+        ranges = <0 0 0x08000000 0x08000000>;
+        status = "disabled"; /* pin conflict with SPI NOR */
+        nor@0,0 {
+                compatible = "cfi-flash";
+                reg = <0 0 0x02000000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                bank-width = <2>;
+                fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
+                                0x0000c000 0x1404a38e 0x00000000>;
+        };
+};
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index e21f6a89cf0f..6e5dfdb32416 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -26,6 +26,13 @@
                        gpio = <&gpio3 22 0>;
                        enable-active-high;
                };
+                reg_audio: wm8962_supply {
+                        compatible = "regulator-fixed";
+                        regulator-name = "wm8962-supply";
+                        gpio = <&gpio4 10 0>;
+                        enable-active-high;
+                };
        };
        gpio-keys {
@@ -43,6 +50,31 @@
                        linux,code = <114>; /* KEY_VOLUMEDOWN */
                };
        };
+        sound {
+                compatible = "fsl,imx6q-sabresd-wm8962",
+                           "fsl,imx-audio-wm8962";
+                model = "wm8962-audio";
+                ssi-controller = <&ssi2>;
+                audio-codec = <&codec>;
+                audio-routing =
+                        "Headphone Jack", "HPOUTL",
+                        "Headphone Jack", "HPOUTR",
+                        "Ext Spk", "SPKOUTL",
+                        "Ext Spk", "SPKOUTR",
+                        "MICBIAS", "AMIC",
+                        "IN3R", "MICBIAS",
+                        "DMIC", "MICBIAS",
+                        "DMICDAT", "DMIC";
+                mux-int-port = <2>;
+                mux-ext-port = <3>;
+        };
+};
+&audmux {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux_2>;
+        status = "okay";
 };
 &fec {
@@ -52,6 +84,40 @@
        status = "okay";
 };
+&i2c1 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1_2>;
+        status = "okay";
+        codec: wm8962@1a {
+                compatible = "wlf,wm8962";
+                reg = <0x1a>;
+                clocks = <&clks 169>;
+                DCVDD-supply = <&reg_audio>;
+                DBVDD-supply = <&reg_audio>;
+                AVDD-supply = <&reg_audio>;
+                CPVDD-supply = <&reg_audio>;
+                MICVDD-supply = <&reg_audio>;
+                PLLVDD-supply = <&reg_audio>;
+                SPKVDD1-supply = <&reg_audio>;
+                SPKVDD2-supply = <&reg_audio>;
+                gpio-cfg = <
+                        0x0000 /* 0:Default */
+                        0x0000 /* 1:Default */
+                        0x0013 /* 2:FN_DMICCLK */
+                        0x0000 /* 3:Default */
+                        0x8014 /* 4:FN_DMICCDAT */
+                        0x0000 /* 5:Default */
+                >;
+       };
+};
+&ssi2 {
+        fsl,mode = "i2s-slave";
+        status = "okay";
+};
 &uart1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_uart1_1>;
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 9e8296e4c343..f21d259080fd 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -106,6 +106,8 @@
                        interrupts = <0 92 0x04>;
                        cache-unified;
                        cache-level = <2>;
+                        arm,tag-latency = <4 2 3>;
+                        arm,data-latency = <4 2 3>;
                };
                pmu {
@@ -638,7 +640,7 @@
                                status = "disabled";
                        };
-                        usbmisc: usbmisc: usbmisc@02184800 {
+                        usbmisc: usbmisc@02184800 {
                                #index-cells = <1>;
                                compatible = "fsl,imx6q-usbmisc";
                                reg = <0x02184800 0x200>;
@@ -742,9 +744,11 @@
                                reg = <0x021b4000 0x4000>;
                        };
-                        weim@021b8000 {
+                        weim: weim@021b8000 {
+                                compatible = "fsl,imx6q-weim";
                                reg = <0x021b8000 0x4000>;
                                interrupts = <0 14 0x04>;
+                                clocks = <&clks 196>;
                        };
                        ocotp@021bc000 {
@@ -752,11 +756,6 @@
                                reg = <0x021bc000 0x4000>;
                        };
-                        ocotp@021c0000 {
-                                reg = <0x021c0000 0x4000>;
-                                interrupts = <0 21 0x04>;
-                        };
                        tzasc@021d0000 { /* TZASC1 */
                                reg = <0x021d0000 0x4000>;
                                interrupts = <0 108 0x04>;
diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
new file mode 100644
index 000000000000..2886a590823d
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sl-evk.dts
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "imx6sl.dtsi"
+/ {
+        model = "Freescale i.MX6 SoloLite EVK Board";
+        compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
+        memory {
+                reg = <0x80000000 0x40000000>;
+        };
+};
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec_1>;
+        phy-mode = "rmii";
+        status = "okay";
+};
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+        hog {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                MX6SL_PAD_KEY_ROW7__GPIO4_IO07    0x17059
+                                MX6SL_PAD_KEY_COL7__GPIO4_IO06    0x17059
+                                MX6SL_PAD_SD2_DAT7__GPIO5_IO00    0x17059
+                                MX6SL_PAD_SD2_DAT6__GPIO4_IO29    0x17059
+                                MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059
+                        >;
+                };
+        };
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1_1>;
+        status = "okay";
+};
+&usdhc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc1_1>;
+        bus-width = <8>;
+        cd-gpios = <&gpio4 7 0>;
+        wp-gpios = <&gpio4 6 0>;
+        status = "okay";
+};
+&usdhc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc2_1>;
+        cd-gpios = <&gpio5 0 0>;
+        wp-gpios = <&gpio4 29 0>;
+        status = "okay";
+};
+&usdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc3_1>;
+        cd-gpios = <&gpio3 22 0>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
new file mode 100644
index 000000000000..c5e5da02d7e3
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -0,0 +1,779 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include "skeleton.dtsi"
+#include "imx6sl-pinfunc.h"
+#include <dt-bindings/clock/imx6sl-clock.h>
+/ {
+        aliases {
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                serial3 = &uart4;
+                serial4 = &uart5;
+                gpio0 = &gpio1;
+                gpio1 = &gpio2;
+                gpio2 = &gpio3;
+                gpio3 = &gpio4;
+                gpio4 = &gpio5;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
+                        reg = <0x0>;
+                        next-level-cache = <&L2>;
+                };
+        };
+        intc: interrupt-controller@00a01000 {
+                compatible = "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                interrupt-controller;
+                reg = <0x00a01000 0x1000>,
+                      <0x00a00100 0x100>;
+        };
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                ckil {
+                        compatible = "fixed-clock";
+                        clock-frequency = <32768>;
+                };
+                osc {
+                        compatible = "fixed-clock";
+                        clock-frequency = <24000000>;
+                };
+        };
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                interrupt-parent = <&intc>;
+                ranges;
+                L2: l2-cache@00a02000 {
+                        compatible = "arm,pl310-cache";
+                        reg = <0x00a02000 0x1000>;
+                        interrupts = <0 92 0x04>;
+                        cache-unified;
+                        cache-level = <2>;
+                        arm,tag-latency = <4 2 3>;
+                        arm,data-latency = <4 2 3>;
+                };
+                pmu {
+                        compatible = "arm,cortex-a9-pmu";
+                        interrupts = <0 94 0x04>;
+                };
+                aips1: aips-bus@02000000 {
+                        compatible = "fsl,aips-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x02000000 0x100000>;
+                        ranges;
+                        spba: spba-bus@02000000 {
+                                compatible = "fsl,spba-bus", "simple-bus";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <0x02000000 0x40000>;
+                                ranges;
+                                spdif: spdif@02004000 {
+                                        reg = <0x02004000 0x4000>;
+                                        interrupts = <0 52 0x04>;
+                                };
+                                ecspi1: ecspi@02008000 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
+                                        reg = <0x02008000 0x4000>;
+                                        interrupts = <0 31 0x04>;
+                                        clocks = <&clks IMX6SL_CLK_ECSPI1>,
+                                                 <&clks IMX6SL_CLK_ECSPI1>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
+                                ecspi2: ecspi@0200c000 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
+                                        reg = <0x0200c000 0x4000>;
+                                        interrupts = <0 32 0x04>;
+                                        clocks = <&clks IMX6SL_CLK_ECSPI2>,
+                                                 <&clks IMX6SL_CLK_ECSPI2>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
+                                ecspi3: ecspi@02010000 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
+                                        reg = <0x02010000 0x4000>;
+                                        interrupts = <0 33 0x04>;
+                                        clocks = <&clks IMX6SL_CLK_ECSPI3>,
+                                                 <&clks IMX6SL_CLK_ECSPI3>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
+                                ecspi4: ecspi@02014000 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
+                                        reg = <0x02014000 0x4000>;
+                                        interrupts = <0 34 0x04>;
+                                        clocks = <&clks IMX6SL_CLK_ECSPI4>,
+                                                 <&clks IMX6SL_CLK_ECSPI4>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
+                                uart5: serial@02018000 {
+                                        compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
+                                        reg = <0x02018000 0x4000>;
+                                        interrupts = <0 30 0x04>;
+                                        clocks = <&clks IMX6SL_CLK_UART>,
+                                                 <&clks IMX6SL_CLK_UART_SERIAL>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
+                                uart1: serial@02020000 {
+                                        compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
+                                        reg = <0x02020000 0x4000>;
+                                        interrupts = <0 26 0x04>;
+                                        clocks = <&clks IMX6SL_CLK_UART>,
+                                                 <&clks IMX6SL_CLK_UART_SERIAL>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
+                                uart2: serial@02024000 {
+                                        compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
+                                        reg = <0x02024000 0x4000>;
+                                        interrupts = <0 27 0x04>;
+                                        clocks = <&clks IMX6SL_CLK_UART>,
+                                                 <&clks IMX6SL_CLK_UART_SERIAL>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
+                                ssi1: ssi@02028000 {
+                                        compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
+                                        reg = <0x02028000 0x4000>;
+                                        interrupts = <0 46 0x04>;
+                                        clocks = <&clks IMX6SL_CLK_SSI1>;
+                                        fsl,fifo-depth = <15>;
+                                        status = "disabled";
+                                };
+                                ssi2: ssi@0202c000 {
+                                        compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
+                                        reg = <0x0202c000 0x4000>;
+                                        interrupts = <0 47 0x04>;
+                                        clocks = <&clks IMX6SL_CLK_SSI2>;
+                                        fsl,fifo-depth = <15>;
+                                        status = "disabled";
+                                };
+                                ssi3: ssi@02030000 {
+                                        compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
+                                        reg = <0x02030000 0x4000>;
+                                        interrupts = <0 48 0x04>;
+                                        clocks = <&clks IMX6SL_CLK_SSI3>;
+                                        fsl,fifo-depth = <15>;
+                                        status = "disabled";
+                                };
+                                uart3: serial@02034000 {
+                                        compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
+                                        reg = <0x02034000 0x4000>;
+                                        interrupts = <0 28 0x04>;
+                                        clocks = <&clks IMX6SL_CLK_UART>,
+                                                 <&clks IMX6SL_CLK_UART_SERIAL>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
+                                uart4: serial@02038000 {
+                                        compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
+                                        reg = <0x02038000 0x4000>;
+                                        interrupts = <0 29 0x04>;
+                                        clocks = <&clks IMX6SL_CLK_UART>,
+                                                 <&clks IMX6SL_CLK_UART_SERIAL>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
+                        };
+                        pwm1: pwm@02080000 {
+                                #pwm-cells = <2>;
+                                compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
+                                reg = <0x02080000 0x4000>;
+                                interrupts = <0 83 0x04>;
+                                clocks = <&clks IMX6SL_CLK_PWM1>,
+                                         <&clks IMX6SL_CLK_PWM1>;
+                                clock-names = "ipg", "per";
+                        };
+                        pwm2: pwm@02084000 {
+                                #pwm-cells = <2>;
+                                compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
+                                reg = <0x02084000 0x4000>;
+                                interrupts = <0 84 0x04>;
+                                clocks = <&clks IMX6SL_CLK_PWM2>,
+                                         <&clks IMX6SL_CLK_PWM2>;
+                                clock-names = "ipg", "per";
+                        };
+                        pwm3: pwm@02088000 {
+                                #pwm-cells = <2>;
+                                compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
+                                reg = <0x02088000 0x4000>;
+                                interrupts = <0 85 0x04>;
+                                clocks = <&clks IMX6SL_CLK_PWM3>,
+                                         <&clks IMX6SL_CLK_PWM3>;
+                                clock-names = "ipg", "per";
+                        };
+                        pwm4: pwm@0208c000 {
+                                #pwm-cells = <2>;
+                                compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
+                                reg = <0x0208c000 0x4000>;
+                                interrupts = <0 86 0x04>;
+                                clocks = <&clks IMX6SL_CLK_PWM4>,
+                                         <&clks IMX6SL_CLK_PWM4>;
+                                clock-names = "ipg", "per";
+                        };
+                        gpt: gpt@02098000 {
+                                compatible = "fsl,imx6sl-gpt";
+                                reg = <0x02098000 0x4000>;
+                                interrupts = <0 55 0x04>;
+                                clocks = <&clks IMX6SL_CLK_GPT>,
+                                         <&clks IMX6SL_CLK_GPT_SERIAL>;
+                                clock-names = "ipg", "per";
+                        };
+                        gpio1: gpio@0209c000 {
+                                compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
+                                reg = <0x0209c000 0x4000>;
+                                interrupts = <0 66 0x04 0 67 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+                        gpio2: gpio@020a0000 {
+                                compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
+                                reg = <0x020a0000 0x4000>;
+                                interrupts = <0 68 0x04 0 69 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+                        gpio3: gpio@020a4000 {
+                                compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
+                                reg = <0x020a4000 0x4000>;
+                                interrupts = <0 70 0x04 0 71 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+                        gpio4: gpio@020a8000 {
+                                compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
+                                reg = <0x020a8000 0x4000>;
+                                interrupts = <0 72 0x04 0 73 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+                        gpio5: gpio@020ac000 {
+                                compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
+                                reg = <0x020ac000 0x4000>;
+                                interrupts = <0 74 0x04 0 75 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+                        kpp: kpp@020b8000 {
+                                reg = <0x020b8000 0x4000>;
+                                interrupts = <0 82 0x04>;
+                        };
+                        wdog1: wdog@020bc000 {
+                                compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
+                                reg = <0x020bc000 0x4000>;
+                                interrupts = <0 80 0x04>;
+                                clocks = <&clks IMX6SL_CLK_DUMMY>;
+                        };
+                        wdog2: wdog@020c0000 {
+                                compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
+                                reg = <0x020c0000 0x4000>;
+                                interrupts = <0 81 0x04>;
+                                clocks = <&clks IMX6SL_CLK_DUMMY>;
+                                status = "disabled";
+                        };
+                        clks: ccm@020c4000 {
+                                compatible = "fsl,imx6sl-ccm";
+                                reg = <0x020c4000 0x4000>;
+                                interrupts = <0 87 0x04 0 88 0x04>;
+                                #clock-cells = <1>;
+                        };
+                        anatop: anatop@020c8000 {
+                                compatible = "fsl,imx6sl-anatop", "syscon", "simple-bus";
+                                reg = <0x020c8000 0x1000>;
+                                interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
+                                regulator-1p1@110 {
+                                        compatible = "fsl,anatop-regulator";
+                                        regulator-name = "vdd1p1";
+                                        regulator-min-microvolt = <800000>;
+                                        regulator-max-microvolt = <1375000>;
+                                        regulator-always-on;
+                                        anatop-reg-offset = <0x110>;
+                                        anatop-vol-bit-shift = <8>;
+                                        anatop-vol-bit-width = <5>;
+                                        anatop-min-bit-val = <4>;
+                                        anatop-min-voltage = <800000>;
+                                        anatop-max-voltage = <1375000>;
+                                };
+                                regulator-3p0@120 {
+                                        compatible = "fsl,anatop-regulator";
+                                        regulator-name = "vdd3p0";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <3150000>;
+                                        regulator-always-on;
+                                        anatop-reg-offset = <0x120>;
+                                        anatop-vol-bit-shift = <8>;
+                                        anatop-vol-bit-width = <5>;
+                                        anatop-min-bit-val = <0>;
+                                        anatop-min-voltage = <2625000>;
+                                        anatop-max-voltage = <3400000>;
+                                };
+                                regulator-2p5@130 {
+                                        compatible = "fsl,anatop-regulator";
+                                        regulator-name = "vdd2p5";
+                                        regulator-min-microvolt = <2100000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        regulator-always-on;
+                                        anatop-reg-offset = <0x130>;
+                                        anatop-vol-bit-shift = <8>;
+                                        anatop-vol-bit-width = <5>;
+                                        anatop-min-bit-val = <0>;
+                                        anatop-min-voltage = <2100000>;
+                                        anatop-max-voltage = <2850000>;
+                                };
+                                reg_arm: regulator-vddcore@140 {
+                                        compatible = "fsl,anatop-regulator";
+                                        regulator-name = "cpu";
+                                        regulator-min-microvolt = <725000>;
+                                        regulator-max-microvolt = <1450000>;
+                                        regulator-always-on;
+                                        anatop-reg-offset = <0x140>;
+                                        anatop-vol-bit-shift = <0>;
+                                        anatop-vol-bit-width = <5>;
+                                        anatop-delay-reg-offset = <0x170>;
+                                        anatop-delay-bit-shift = <24>;
+                                        anatop-delay-bit-width = <2>;
+                                        anatop-min-bit-val = <1>;
+                                        anatop-min-voltage = <725000>;
+                                        anatop-max-voltage = <1450000>;
+                                };
+                                reg_pu: regulator-vddpu@140 {
+                                        compatible = "fsl,anatop-regulator";
+                                        regulator-name = "vddpu";
+                                        regulator-min-microvolt = <725000>;
+                                        regulator-max-microvolt = <1450000>;
+                                        regulator-always-on;
+                                        anatop-reg-offset = <0x140>;
+                                        anatop-vol-bit-shift = <9>;
+                                        anatop-vol-bit-width = <5>;
+                                        anatop-delay-reg-offset = <0x170>;
+                                        anatop-delay-bit-shift = <26>;
+                                        anatop-delay-bit-width = <2>;
+                                        anatop-min-bit-val = <1>;
+                                        anatop-min-voltage = <725000>;
+                                        anatop-max-voltage = <1450000>;
+                                };
+                                reg_soc: regulator-vddsoc@140 {
+                                        compatible = "fsl,anatop-regulator";
+                                        regulator-name = "vddsoc";
+                                        regulator-min-microvolt = <725000>;
+                                        regulator-max-microvolt = <1450000>;
+                                        regulator-always-on;
+                                        anatop-reg-offset = <0x140>;
+                                        anatop-vol-bit-shift = <18>;
+                                        anatop-vol-bit-width = <5>;
+                                        anatop-delay-reg-offset = <0x170>;
+                                        anatop-delay-bit-shift = <28>;
+                                        anatop-delay-bit-width = <2>;
+                                        anatop-min-bit-val = <1>;
+                                        anatop-min-voltage = <725000>;
+                                        anatop-max-voltage = <1450000>;
+                                };
+                        };
+                        usbphy1: usbphy@020c9000 {
+                                compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
+                                reg = <0x020c9000 0x1000>;
+                                interrupts = <0 44 0x04>;
+                                clocks = <&clks IMX6SL_CLK_USBPHY1>;
+                        };
+                        usbphy2: usbphy@020ca000 {
+                                compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
+                                reg = <0x020ca000 0x1000>;
+                                interrupts = <0 45 0x04>;
+                                clocks = <&clks IMX6SL_CLK_USBPHY2>;
+                        };
+                        snvs@020cc000 {
+                                compatible = "fsl,sec-v4.0-mon", "simple-bus";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0 0x020cc000 0x4000>;
+                                snvs-rtc-lp@34 {
+                                        compatible = "fsl,sec-v4.0-mon-rtc-lp";
+                                        reg = <0x34 0x58>;
+                                        interrupts = <0 19 0x04 0 20 0x04>;
+                                };
+                        };
+                        epit1: epit@020d0000 {
+                                reg = <0x020d0000 0x4000>;
+                                interrupts = <0 56 0x04>;
+                        };
+                        epit2: epit@020d4000 {
+                                reg = <0x020d4000 0x4000>;
+                                interrupts = <0 57 0x04>;
+                        };
+                        src: src@020d8000 {
+                                compatible = "fsl,imx6sl-src", "fsl,imx51-src";
+                                reg = <0x020d8000 0x4000>;
+                                interrupts = <0 91 0x04 0 96 0x04>;
+                                #reset-cells = <1>;
+                        };
+                        gpc: gpc@020dc000 {
+                                compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
+                                reg = <0x020dc000 0x4000>;
+                                interrupts = <0 89 0x04>;
+                        };
+                        iomuxc: iomuxc@020e0000 {
+                                compatible = "fsl,imx6sl-iomuxc";
+                                reg = <0x020e0000 0x4000>;
+                                fec {
+                                        pinctrl_fec_1: fecgrp-1 {
+                                                fsl,pins = <
+                                                        MX6SL_PAD_FEC_MDC__FEC_MDC         0x1b0b0
+                                                        MX6SL_PAD_FEC_MDIO__FEC_MDIO       0x1b0b0
+                                                        MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV    0x1b0b0
+                                                        MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0   0x1b0b0
+                                                        MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1   0x1b0b0
+                                                        MX6SL_PAD_FEC_TX_EN__FEC_TX_EN     0x1b0b0
+                                                        MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0   0x1b0b0
+                                                        MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1   0x1b0b0
+                                                        MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
+                                                >;
+                                        };
+                                };
+                                uart1 {
+                                        pinctrl_uart1_1: uart1grp-1 {
+                                                fsl,pins = <
+                                                        MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
+                                                        MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
+                                                >;
+                                        };
+                                };
+                                usdhc1 {
+                                        pinctrl_usdhc1_1: usdhc1grp-1 {
+                                                fsl,pins = <
+                                                        MX6SL_PAD_SD1_CMD__SD1_CMD    0x17059
+                                                        MX6SL_PAD_SD1_CLK__SD1_CLK    0x10059
+                                                        MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
+                                                        MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
+                                                        MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
+                                                        MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
+                                                        MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059
+                                                        MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059
+                                                        MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059
+                                                        MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
+                                                >;
+                                        };
+                                };
+                                usdhc2 {
+                                        pinctrl_usdhc2_1: usdhc2grp-1 {
+                                                fsl,pins = <
+                                                        MX6SL_PAD_SD2_CMD__SD2_CMD    0x17059
+                                                        MX6SL_PAD_SD2_CLK__SD2_CLK    0x10059
+                                                        MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+                                                        MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+                                                        MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+                                                        MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+                                                >;
+                                        };
+                                };
+                                usdhc3 {
+                                        pinctrl_usdhc3_1: usdhc3grp-1 {
+                                                fsl,pins = <
+                                                        MX6SL_PAD_SD3_CMD__SD3_CMD    0x17059
+                                                        MX6SL_PAD_SD3_CLK__SD3_CLK    0x10059
+                                                        MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+                                                        MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+                                                        MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+                                                        MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+                                                >;
+                                        };
+                                };
+                        };
+                        csi: csi@020e4000 {
+                                reg = <0x020e4000 0x4000>;
+                                interrupts = <0 7 0x04>;
+                        };
+                        spdc: spdc@020e8000 {
+                                reg = <0x020e8000 0x4000>;
+                                interrupts = <0 6 0x04>;
+                        };
+                        sdma: sdma@020ec000 {
+                                compatible = "fsl,imx6sl-sdma", "fsl,imx35-sdma";
+                                reg = <0x020ec000 0x4000>;
+                                interrupts = <0 2 0x04>;
+                                clocks = <&clks IMX6SL_CLK_SDMA>,
+                                         <&clks IMX6SL_CLK_SDMA>;
+                                clock-names = "ipg", "ahb";
+                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6sl.bin";
+                        };
+                        pxp: pxp@020f0000 {
+                                reg = <0x020f0000 0x4000>;
+                                interrupts = <0 98 0x04>;
+                        };
+                        epdc: epdc@020f4000 {
+                                reg = <0x020f4000 0x4000>;
+                                interrupts = <0 97 0x04>;
+                        };
+                        lcdif: lcdif@020f8000 {
+                                reg = <0x020f8000 0x4000>;
+                                interrupts = <0 39 0x04>;
+                        };
+                        dcp: dcp@020fc000 {
+                                reg = <0x020fc000 0x4000>;
+                                interrupts = <0 99 0x04>;
+                        };
+                };
+                aips2: aips-bus@02100000 {
+                        compatible = "fsl,aips-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x02100000 0x100000>;
+                        ranges;
+                        usbotg1: usb@02184000 {
+                                compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
+                                reg = <0x02184000 0x200>;
+                                interrupts = <0 43 0x04>;
+                                clocks = <&clks IMX6SL_CLK_USBOH3>;
+                                fsl,usbphy = <&usbphy1>;
+                                fsl,usbmisc = <&usbmisc 0>;
+                                status = "disabled";
+                        };
+                        usbotg2: usb@02184200 {
+                                compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
+                                reg = <0x02184200 0x200>;
+                                interrupts = <0 40 0x04>;
+                                clocks = <&clks IMX6SL_CLK_USBOH3>;
+                                fsl,usbphy = <&usbphy2>;
+                                fsl,usbmisc = <&usbmisc 1>;
+                                status = "disabled";
+                        };
+                        usbh: usb@02184400 {
+                                compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
+                                reg = <0x02184400 0x200>;
+                                interrupts = <0 42 0x04>;
+                                clocks = <&clks IMX6SL_CLK_USBOH3>;
+                                fsl,usbmisc = <&usbmisc 2>;
+                                status = "disabled";
+                        };
+                        usbmisc: usbmisc@02184800 {
+                                #index-cells = <1>;
+                                compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
+                                reg = <0x02184800 0x200>;
+                                clocks = <&clks IMX6SL_CLK_USBOH3>;
+                        };
+                        fec: ethernet@02188000 {
+                                compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
+                                reg = <0x02188000 0x4000>;
+                                interrupts = <0 114 0x04>;
+                                clocks = <&clks IMX6SL_CLK_ENET_REF>,
+                                         <&clks IMX6SL_CLK_ENET_REF>;
+                                clock-names = "ipg", "ahb";
+                                status = "disabled";
+                        };
+                        usdhc1: usdhc@02190000 {
+                                compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
+                                reg = <0x02190000 0x4000>;
+                                interrupts = <0 22 0x04>;
+                                clocks = <&clks IMX6SL_CLK_USDHC1>,
+                                         <&clks IMX6SL_CLK_USDHC1>,
+                                         <&clks IMX6SL_CLK_USDHC1>;
+                                clock-names = "ipg", "ahb", "per";
+                                bus-width = <4>;
+                                status = "disabled";
+                        };
+                        usdhc2: usdhc@02194000 {
+                                compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
+                                reg = <0x02194000 0x4000>;
+                                interrupts = <0 23 0x04>;
+                                clocks = <&clks IMX6SL_CLK_USDHC2>,
+                                         <&clks IMX6SL_CLK_USDHC2>,
+                                         <&clks IMX6SL_CLK_USDHC2>;
+                                clock-names = "ipg", "ahb", "per";
+                                bus-width = <4>;
+                                status = "disabled";
+                        };
+                        usdhc3: usdhc@02198000 {
+                                compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
+                                reg = <0x02198000 0x4000>;
+                                interrupts = <0 24 0x04>;
+                                clocks = <&clks IMX6SL_CLK_USDHC3>,
+                                         <&clks IMX6SL_CLK_USDHC3>,
+                                         <&clks IMX6SL_CLK_USDHC3>;
+                                clock-names = "ipg", "ahb", "per";
+                                bus-width = <4>;
+                                status = "disabled";
+                        };
+                        usdhc4: usdhc@0219c000 {
+                                compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
+                                reg = <0x0219c000 0x4000>;
+                                interrupts = <0 25 0x04>;
+                                clocks = <&clks IMX6SL_CLK_USDHC4>,
+                                         <&clks IMX6SL_CLK_USDHC4>,
+                                         <&clks IMX6SL_CLK_USDHC4>;
+                                clock-names = "ipg", "ahb", "per";
+                                bus-width = <4>;
+                                status = "disabled";
+                        };
+                        i2c1: i2c@021a0000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
+                                reg = <0x021a0000 0x4000>;
+                                interrupts = <0 36 0x04>;
+                                clocks = <&clks IMX6SL_CLK_I2C1>;
+                                status = "disabled";
+                        };
+                        i2c2: i2c@021a4000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
+                                reg = <0x021a4000 0x4000>;
+                                interrupts = <0 37 0x04>;
+                                clocks = <&clks IMX6SL_CLK_I2C2>;
+                                status = "disabled";
+                        };
+                        i2c3: i2c@021a8000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
+                                reg = <0x021a8000 0x4000>;
+                                interrupts = <0 38 0x04>;
+                                clocks = <&clks IMX6SL_CLK_I2C3>;
+                                status = "disabled";
+                        };
+                        mmdc: mmdc@021b0000 {
+                                compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
+                                reg = <0x021b0000 0x4000>;
+                        };
+                        rngb: rngb@021b4000 {
+                                reg = <0x021b4000 0x4000>;
+                                interrupts = <0 5 0x04>;
+                        };
+                        weim: weim@021b8000 {
+                                reg = <0x021b8000 0x4000>;
+                                interrupts = <0 14 0x04>;
+                        };
+                        ocotp: ocotp@021bc000 {
+                                compatible = "fsl,imx6sl-ocotp";
+                                reg = <0x021bc000 0x4000>;
+                        };
+                        audmux: audmux@021d8000 {
+                                compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
+                                reg = <0x021d8000 0x4000>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts
index c9c3fa344647..b6b82eca8d1e 100644
--- a/arch/arm/boot/dts/integratorap.dts
+++ b/arch/arm/boot/dts/integratorap.dts
@@ -39,6 +39,47 @@
                valid-mask = <0x003fffff>;
        };
+        pci: pciv3@62000000 {
+                compatible = "v3,v360epc-pci";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0x62000000 0x10000>;
+                interrupt-parent = <&pic>;
+                interrupts = <17>; /* Bus error IRQ */
+                ranges = <0x00000000 0 0x61000000 /* config space */
+                        0x61000000 0 0x00100000 /* 16 MiB @ 61000000 */
+                        0x01000000 0 0x0 /* I/O space */
+                        0x60000000 0 0x00100000 /* 16 MiB @ 60000000 */
+                        0x02000000 0 0x00000000 /* non-prefectable memory */
+                        0x40000000 0 0x10000000 /* 256 MiB @ 40000000 */
+                        0x42000000 0 0x10000000 /* prefetchable memory */
+                        0x50000000 0 0x10000000>; /* 256 MiB @ 50000000 */
+                interrupt-map-mask = <0xf800 0 0 0x7>;
+                interrupt-map = <
+                /* IDSEL 9 */
+                0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
+                0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
+                0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
+                0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
+                /* IDSEL 10 */
+                0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
+                0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
+                0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
+                0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
+                /* IDSEL 11 */
+                0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
+                0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
+                0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */
+                0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */
+                /* IDSEL 12 */
+                0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
+                0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */
+                0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */
+                0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */
+                >;
+        };
        fpga {
                /*
                 * The Integator/AP predates the idea to have magic numbers
diff --git a/arch/arm/boot/dts/keystone.dts b/arch/arm/boot/dts/keystone.dts
new file mode 100644
index 000000000000..1334b42c6b77
--- /dev/null
+++ b/arch/arm/boot/dts/keystone.dts
@@ -0,0 +1,117 @@
+/*
+ * Copyright 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+/include/ "skeleton.dtsi"
+/ {
+        model = "Texas Instruments Keystone 2 SoC";
+        compatible =  "ti,keystone-evm";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&gic>;
+        aliases {
+                serial0 = &uart0;
+        };
+        memory {
+                reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                interrupt-parent = <&gic>;
+                cpu@0 {
+                        compatible = "arm,cortex-a15";
+                        device_type = "cpu";
+                        reg = <0>;
+                };
+                cpu@1 {
+                        compatible = "arm,cortex-a15";
+                        device_type = "cpu";
+                        reg = <1>;
+                };
+                cpu@2 {
+                        compatible = "arm,cortex-a15";
+                        device_type = "cpu";
+                        reg = <2>;
+                };
+                cpu@3 {
+                        compatible = "arm,cortex-a15";
+                        device_type = "cpu";
+                        reg = <3>;
+                };
+        };
+        gic: interrupt-controller {
+                compatible = "arm,cortex-a15-gic";
+                #interrupt-cells = <3>;
+                #size-cells = <0>;
+                #address-cells = <1>;
+                interrupt-controller;
+                reg = <0x0 0x02561000 0x0 0x1000>,
+                      <0x0 0x02562000 0x0 0x2000>;
+        };
+        timer {
+                compatible = "arm,armv7-timer";
+                interrupts = <1 13 0xf08>,
+                             <1 14 0xf08>,
+                             <1 11 0xf08>,
+                             <1 10 0x308>;
+        };
+        pmu {
+                compatible = "arm,cortex-a15-pmu";
+                interrupts = <0 20 0xf01>,
+                             <0 21 0xf01>,
+                             <0 22 0xf01>,
+                             <0 23 0xf01>;
+        };
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "ti,keystone","simple-bus";
+                interrupt-parent = <&gic>;
+                ranges = <0x0 0x0 0x0 0xc0000000>;
+                rstctrl: reset-controller {
+                        compatible = "ti,keystone-reset";
+                        reg = <0x023100e8 4>;   /* pll reset control reg */
+                };
+                uart0: serial@02530c00 {
+                        compatible = "ns16550a";
+                        current-speed = <115200>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        reg = <0x02530c00 0x100>;
+                        clock-frequency = <133120000>;
+                        interrupts = <0 277 0xf01>;
+                };
+                uart1:  serial@02531000 {
+                        compatible = "ns16550a";
+                        current-speed = <115200>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        reg = <0x02531000 0x100>;
+                        clock-frequency = <133120000>;
+                        interrupts = <0 280 0xf01>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi
index d6c9d65cbaeb..1e5bef0bead7 100644
--- a/arch/arm/boot/dts/kirkwood-6281.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6281.dtsi
@@ -40,5 +40,64 @@
                                marvell,function = "sdio";
                        };
                };
+                pcie-controller {
+                        compatible = "marvell,kirkwood-pcie";
+                        status = "disabled";
+                        device_type = "pci";
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        bus-range = <0x00 0xff>;
+                        ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000   /* Port 0.0 registers */
+                                  0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
+                                  0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
+                        pcie@1,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
+                                reg = <0x0800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &intc 9>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gate_clk 2>;
+                                status = "disabled";
+                        };
+                };
+                rtc@10300 {
+                        compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
+                        reg = <0x10300 0x20>;
+                        interrupts = <53>;
+                        clocks = <&gate_clk 7>;
+                };
+                sata@80000 {
+                        compatible = "marvell,orion-sata";
+                        reg = <0x80000 0x5000>;
+                        interrupts = <21>;
+                        clocks = <&gate_clk 14>, <&gate_clk 15>;
+                        clock-names = "0", "1";
+                        status = "disabled";
+                };
+                mvsdio@90000 {
+                        compatible = "marvell,orion-sdio";
+                        reg = <0x90000 0x200>;
+                        interrupts = <28>;
+                        clocks = <&gate_clk 4>;
+                        bus-width = <4>;
+                        cap-sdio-irq;
+                        cap-sd-highspeed;
+                        cap-mmc-highspeed;
+                        status = "disabled";
+                };
        };
 };
diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi
index 23991e45bc55..a63a11137262 100644
--- a/arch/arm/boot/dts/kirkwood-6282.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6282.dtsi
@@ -49,6 +49,34 @@
                        };
                };
+                rtc@10300 {
+                        compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
+                        reg = <0x10300 0x20>;
+                        interrupts = <53>;
+                        clocks = <&gate_clk 7>;
+                };
+                sata@80000 {
+                        compatible = "marvell,orion-sata";
+                        reg = <0x80000 0x5000>;
+                        interrupts = <21>;
+                        clocks = <&gate_clk 14>, <&gate_clk 15>;
+                        clock-names = "0", "1";
+                        status = "disabled";
+                };
+                mvsdio@90000 {
+                        compatible = "marvell,orion-sdio";
+                        reg = <0x90000 0x200>;
+                        interrupts = <28>;
+                        clocks = <&gate_clk 4>;
+                        bus-width = <4>;
+                        cap-sdio-irq;
+                        cap-sd-highspeed;
+                        cap-mmc-highspeed;
+                        status = "disabled";
+                };
                thermal@10078 {
                        compatible = "marvell,kirkwood-thermal";
                        reg = <0x10078 0x4>;
@@ -65,5 +93,53 @@
                        clocks = <&gate_clk 7>;
                        status = "disabled";
                };
+                pcie-controller {
+                        compatible = "marvell,kirkwood-pcie";
+                        status = "disabled";
+                        device_type = "pci";
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        bus-range = <0x00 0xff>;
+                        ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000   /* Port 0.0 registers */
+                                  0x82000000 0 0x00044000 0x00044000 0 0x00002000   /* Port 1.0 registers */
+                                  0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
+                                  0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
+                        pcie@1,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
+                                reg = <0x0800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &intc 9>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gate_clk 2>;
+                                status = "disabled";
+                        };
+                        pcie@2,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;
+                                reg = <0x1000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &intc 10>;
+                                marvell,pcie-port = <1>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gate_clk 18>;
+                                status = "disabled";
+                        };
+                };
        };
 };
diff --git a/arch/arm/boot/dts/kirkwood-cloudbox.dts b/arch/arm/boot/dts/kirkwood-cloudbox.dts
index 5f21d4e427b0..00c48d26de68 100644
--- a/arch/arm/boot/dts/kirkwood-cloudbox.dts
+++ b/arch/arm/boot/dts/kirkwood-cloudbox.dts
@@ -18,10 +18,6 @@
        ocp@f1000000 {
                pinctrl: pinctrl@10000 {
-                        pinctrl-0 = < &pmx_spi &pmx_uart0
-                                        &pmx_cloudbox_sata0 >;
-                        pinctrl-names = "default";
                        pmx_cloudbox_sata0: pmx-cloudbox-sata0 {
                                marvell,pins = "mpp15";
                                marvell,function = "sata0";
@@ -29,16 +25,22 @@
                };
                serial@12000 {
+                        pinctrl-0 = <&pmx_uart0>;
+                        pinctrl-names = "default";
                        clock-frequency = <166666667>;
                        status = "okay";
                };
                sata@80000 {
+                        pinctrl-0 = <&pmx_cloudbox_sata0>;
+                        pinctrl-names = "default";
                        status = "okay";
                        nr-ports = <1>;
                };
                spi@10600 {
+                        pinctrl-0 = <&pmx_spi>;
+                        pinctrl-names = "default";
                        status = "okay";
                        flash@0 {
diff --git a/arch/arm/boot/dts/kirkwood-db-88f6281.dts b/arch/arm/boot/dts/kirkwood-db-88f6281.dts
new file mode 100644
index 000000000000..9d777edd1f36
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-db-88f6281.dts
@@ -0,0 +1,30 @@
+/*
+ * Marvell DB-88F6281-BP Development Board Setup
+ *
+ * Saeed Bishara <saeed@marvell.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+/dts-v1/;
+/include/ "kirkwood-db.dtsi"
+/include/ "kirkwood-6281.dtsi"
+/ {
+        model = "Marvell DB-88F6281-BP Development Board";
+        compatible = "marvell,db-88f6281-bp", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+        ocp@f1000000 {
+                pcie-controller {
+                        status = "okay";
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-db-88f6282.dts b/arch/arm/boot/dts/kirkwood-db-88f6282.dts
new file mode 100644
index 000000000000..f4c852886d23
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-db-88f6282.dts
@@ -0,0 +1,34 @@
+/*
+ * Marvell DB-88F6282-BP Development Board Setup
+ *
+ * Saeed Bishara <saeed@marvell.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+/dts-v1/;
+/include/ "kirkwood-db.dtsi"
+/include/ "kirkwood-6282.dtsi"
+/ {
+        model = "Marvell DB-88F6282-BP Development Board";
+        compatible = "marvell,db-88f6282-bp", "marvell,kirkwood-88f6282", "marvell,kirkwood";
+        ocp@f1000000 {
+                pcie-controller {
+                        status = "okay";
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                        pcie@2,0 {
+                                status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-db.dtsi b/arch/arm/boot/dts/kirkwood-db.dtsi
new file mode 100644
index 000000000000..c87cfb816120
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-db.dtsi
@@ -0,0 +1,89 @@
+/*
+ * Marvell DB-{88F6281,88F6282}-BP Development Board Setup
+ *
+ * Saeed Bishara <saeed@marvell.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * This file contains the definitions that are common between the 6281
+ * and 6282 variants of the Marvell Kirkwood Development Board.
+ */
+/include/ "kirkwood.dtsi"
+/ {
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x20000000>; /* 512 MB */
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+        ocp@f1000000 {
+                pinctrl@10000 {
+                        pmx_sdio_gpios: pmx-sdio-gpios {
+                                marvell,pins = "mpp37", "mpp38";
+                                marvell,function = "gpio";
+                        };
+                };
+                serial@12000 {
+                        pinctrl-0 = <&pmx_uart0>;
+                        pinctrl-names = "default";
+                        clock-frequency = <200000000>;
+                        status = "ok";
+                };
+                nand@3000000 {
+                        pinctrl-0 = <&pmx_nand>;
+                        pinctrl-names = "default";
+                        chip-delay = <25>;
+                        status = "okay";
+                        partition@0 {
+                                label = "uboot";
+                                reg = <0x0 0x100000>;
+                        };
+                        partition@100000 {
+                                label = "uImage";
+                                reg = <0x100000 0x400000>;
+                        };
+                        partition@500000 {
+                                label = "root";
+                                reg = <0x500000 0x1fb00000>;
+                        };
+                };
+                sata@80000 {
+                        nr-ports = <2>;
+                        status = "okay";
+                };
+                ehci@50000 {
+                        status = "okay";
+                };
+                mvsdio@90000 {
+                        pinctrl-0 = <&pmx_sdio_gpios>;
+                        pinctrl-names = "default";
+                        wp-gpios = <&gpio1 5 0>;
+                        cd-gpios = <&gpio1 6 0>;
+                        status = "okay";
+                };
+                pcie-controller {
+                        status = "okay";
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts
index c9c44b2f62d7..14d4ceea3057 100644
--- a/arch/arm/boot/dts/kirkwood-dns320.dts
+++ b/arch/arm/boot/dts/kirkwood-dns320.dts
@@ -17,6 +17,11 @@
        gpio-leds {
                compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_led_power &pmx_led_red_usb_320
+                             &pmx_led_red_left_hdd &pmx_led_red_right_hdd
+                             &pmx_led_white_usb>;
+                pinctrl-names = "default";
                blue-power {
                        label = "dns320:blue:power";
                        gpios = <&gpio0 26 1>; /* GPIO 26 Active Low */
@@ -46,6 +51,8 @@
                };
                serial@12100 {
+                        pinctrl-0 = <&pmx_uart1>;
+                        pinctrl-names = "default";
                        status = "okay";
                };
        };
diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts b/arch/arm/boot/dts/kirkwood-dns325.dts
index e4e4930dc5cf..63872570e6ce 100644
--- a/arch/arm/boot/dts/kirkwood-dns325.dts
+++ b/arch/arm/boot/dts/kirkwood-dns325.dts
@@ -17,6 +17,11 @@
        gpio-leds {
                compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_led_power &pmx_led_red_usb_325
+                             &pmx_led_red_left_hdd &pmx_led_red_right_hdd
+                             &pmx_led_white_usb>;
+                pinctrl-names = "default";
                white-power {
                        label = "dns325:white:power";
                        gpios = <&gpio0 26 1>; /* GPIO 26 Active Low */
diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
index 6875ac00c174..0afe1d07c803 100644
--- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi
+++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
@@ -9,6 +9,10 @@
                compatible = "gpio-keys";
                #address-cells = <1>;
                #size-cells = <0>;
+                pinctrl-0 = <&pmx_button_power &pmx_button_unmount
+                             &pmx_button_reset>;
+                pinctrl-names = "default";
                button@1 {
                        label = "Power button";
                        linux,code = <116>;
@@ -29,6 +33,8 @@
        gpio_fan {
                /* Fan: ADDA AD045HB-G73 40mm 6000rpm@5v */
                compatible = "gpio-fan";
+                pinctrl-0 = <&pmx_fan_high_speed &pmx_fan_low_speed>;
+                pinctrl-names = "default";
                gpios = <&gpio1 14 1
                         &gpio1 13 1>;
                gpio-fan,speed-map = <0    0
@@ -38,27 +44,17 @@
        gpio_poweroff {
                compatible = "gpio-poweroff";
+                pinctrl-0 = <&pmx_power_off>;
+                pinctrl-names = "default";
                gpios = <&gpio1 4 0>;
        };
        ocp@f1000000 {
                pinctrl: pinctrl@10000 {
-                        pinctrl-0 = < &pmx_nand &pmx_uart1
+                        pinctrl-0 = <&pmx_power_back_on &pmx_present_sata0
-                                      &pmx_sata0 &pmx_sata1
+                                     &pmx_present_sata1 &pmx_fan_tacho
-                                      &pmx_led_power
+                                     &pmx_temp_alarm>;
-                                      &pmx_led_red_right_hdd
-                                      &pmx_led_red_left_hdd
-                                      &pmx_led_red_usb_325
-                                      &pmx_button_power
-                                      &pmx_led_red_usb_320
-                                      &pmx_power_off &pmx_power_back_on
-                                      &pmx_power_sata0 &pmx_power_sata1
-                                      &pmx_present_sata0 &pmx_present_sata1
-                                      &pmx_led_white_usb &pmx_fan_tacho
-                                      &pmx_fan_high_speed &pmx_fan_low_speed
-                                      &pmx_button_unmount &pmx_button_reset
-                                      &pmx_temp_alarm >;
                        pinctrl-names = "default";
                        pmx_sata0: pmx-sata0 {
@@ -147,11 +143,15 @@
                        };
                };
                sata@80000 {
+                        pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
+                        pinctrl-names = "default";
                        status = "okay";
                        nr-ports = <2>;
                };
                nand@3000000 {
+                        pinctrl-0 = <&pmx_nand>;
+                        pinctrl-names = "default";
                        status = "okay";
                        chip-delay = <35>;
@@ -192,6 +192,8 @@
                compatible = "simple-bus";
                #address-cells = <1>;
                #size-cells = <0>;
+                pinctrl-0 = <&pmx_power_sata0 &pmx_power_sata1>;
+                pinctrl-names = "default";
                sata0_power: regulator@1 {
                        compatible = "regulator-fixed";
diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts
index 0196cf6b0ef2..7714742bb8d8 100644
--- a/arch/arm/boot/dts/kirkwood-dockstar.dts
+++ b/arch/arm/boot/dts/kirkwood-dockstar.dts
@@ -18,11 +18,6 @@
        ocp@f1000000 {
                pinctrl: pinctrl@10000 {
-                        pinctrl-0 = < &pmx_usb_power_enable
-                                      &pmx_led_green &pmx_led_orange >;
-                        pinctrl-names = "default";
                        pmx_usb_power_enable: pmx-usb-power-enable {
                                marvell,pins = "mpp29";
                                marvell,function = "gpio";
@@ -62,6 +57,8 @@
        };
        gpio-leds {
                compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_led_green &pmx_led_orange>;
+                pinctrl-names = "default";
                health {
                        label = "status:green:health";
@@ -77,6 +74,8 @@
                compatible = "simple-bus";
                #address-cells = <1>;
                #size-cells = <0>;
+                pinctrl-0 = <&pmx_usb_power_enable>;
+                pinctrl-names = "default";
                usb_power: regulator@1 {
                        compatible = "regulator-fixed";
diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
index 289e51d86372..36c7ba38d500 100644
--- a/arch/arm/boot/dts/kirkwood-dreamplug.dts
+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
@@ -18,12 +18,6 @@
        ocp@f1000000 {
                pinctrl: pinctrl@10000 {
-                        pinctrl-0 = < &pmx_spi
-                                      &pmx_led_bluetooth &pmx_led_wifi
-                                      &pmx_led_wifi_ap >;
-                        pinctrl-names = "default";
                        pmx_led_bluetooth: pmx-led-bluetooth {
                                marvell,pins = "mpp47";
                                marvell,function = "gpio";
@@ -43,6 +37,8 @@
                spi@10600 {
                        status = "okay";
+                        pinctrl-0 = <&pmx_spi>;
+                        pinctrl-names = "default";
                        m25p40@0 {
                                #address-cells = <1>;
@@ -79,11 +75,15 @@
                        pinctrl-names = "default";
                        status = "okay";
                        /* No CD or WP GPIOs */
+                        broken-cd;
                };
        };
        gpio-leds {
                compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_led_bluetooth &pmx_led_wifi
+                             &pmx_led_wifi_ap >;
+                pinctrl-names = "default";
                bluetooth {
                        label = "dreamplug:blue:bluetooth";
diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts
index c3573be7b92c..31caa6405065 100644
--- a/arch/arm/boot/dts/kirkwood-goflexnet.dts
+++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts
@@ -18,15 +18,6 @@
        ocp@f1000000 {
                pinctrl: pinctrl@10000 {
-                        pinctrl-0 = < &pmx_usb_power_enable &pmx_led_orange
-                                      &pmx_led_left_cap_0 &pmx_led_left_cap_1
-                                      &pmx_led_left_cap_2 &pmx_led_left_cap_3
-                                      &pmx_led_right_cap_0 &pmx_led_right_cap_1
-                                      &pmx_led_right_cap_2 &pmx_led_right_cap_3
-                                    >;
-                        pinctrl-names = "default";
                        pmx_usb_power_enable: pmx-usb-power-enable {
                                marvell,pins = "mpp29";
                                marvell,function = "gpio";
@@ -109,6 +100,13 @@
        };
        gpio-leds {
                compatible = "gpio-leds";
+                pinctrl-0 = < &pmx_led_orange
+                              &pmx_led_left_cap_0 &pmx_led_left_cap_1
+                              &pmx_led_left_cap_2 &pmx_led_left_cap_3
+                              &pmx_led_right_cap_0 &pmx_led_right_cap_1
+                              &pmx_led_right_cap_2 &pmx_led_right_cap_3
+                            >;
+                pinctrl-names = "default";
                health {
                        label = "status:green:health";
@@ -156,6 +154,8 @@
                compatible = "simple-bus";
                #address-cells = <1>;
                #size-cells = <0>;
+                pinctrl-0 = <&pmx_usb_power_enable>;
+                pinctrl-names = "default";
                usb_power: regulator@1 {
                        compatible = "regulator-fixed";
diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
index 44fd97dfc1f3..1e642f39b154 100644
--- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
+++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
@@ -18,11 +18,6 @@
        ocp@f1000000 {
                pinctrl: pinctrl@10000 {
-                        pinctrl-0 = < &pmx_led_health_r &pmx_led_health_g
-                                      &pmx_led_wmode_r &pmx_led_wmode_g >;
-                        pinctrl-names = "default";
                        pmx_led_health_r: pmx-led-health-r {
                                marvell,pins = "mpp46";
                                marvell,function = "gpio";
@@ -72,11 +67,16 @@
                mvsdio@90000 {
                        status = "okay";
+                        /* No CD or WP GPIOs */
+                        broken-cd;
                };
        };
        gpio-leds {
                compatible = "gpio-leds";
+                pinctrl-0 = < &pmx_led_health_r &pmx_led_health_g
+                              &pmx_led_wmode_r &pmx_led_wmode_g >;
+                pinctrl-names = "default";
                health-r {
                        label = "guruplug:red:health";
diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts
index 5335b1aa8601..20c4b081f420 100644
--- a/arch/arm/boot/dts/kirkwood-ib62x0.dts
+++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts
@@ -18,13 +18,6 @@
        ocp@f1000000 {
                pinctrl: pinctrl@10000 {
-                        pinctrl-0 = < &pmx_nand
-                                      &pmx_led_os_red &pmx_power_off
-                                      &pmx_led_os_green &pmx_led_usb_transfer
-                                      &pmx_button_reset &pmx_button_usb_copy >;
-                        pinctrl-names = "default";
                        pmx_led_os_red: pmx-led-os-red {
                                marvell,pins = "mpp22";
                                marvell,function = "gpio";
@@ -61,6 +54,8 @@
                nand@3000000 {
                        status = "okay";
+                        pinctrl-0 = <&pmx_nand>;
+                        pinctrl-names = "default";
                        partition@0 {
                                label = "u-boot";
@@ -84,6 +79,9 @@
                compatible = "gpio-keys";
                #address-cells = <1>;
                #size-cells = <0>;
+                pinctrl-0 = <&pmx_button_reset &pmx_button_usb_copy>;
+                pinctrl-names = "default";
                button@1 {
                        label = "USB Copy";
                        linux,code = <133>;
@@ -97,6 +95,9 @@
        };
        gpio-leds {
                compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_led_os_red &pmx_led_os_green
+                             &pmx_led_usb_transfer>;
+                pinctrl-names = "default";
                green-os {
                        label = "ib62x0:green:os";
@@ -114,6 +115,8 @@
        };
        gpio_poweroff {
                compatible = "gpio-poweroff";
+                pinctrl-0 = <&pmx_power_off>;
+                pinctrl-names = "default";
                gpios = <&gpio0 24 0>;
        };
diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts
index 12ccf74ac3c4..441204e8abc6 100644
--- a/arch/arm/boot/dts/kirkwood-iconnect.dts
+++ b/arch/arm/boot/dts/kirkwood-iconnect.dts
@@ -20,51 +20,43 @@
        ocp@f1000000 {
                pinctrl: pinctrl@10000 {
+                        pmx_button_reset: pmx-button-reset {
-                        pinctrl-0 = < &pmx_gpio_12 &pmx_gpio_35
-                                      &pmx_gpio_41 &pmx_gpio_42
-                                      &pmx_gpio_43 &pmx_gpio_44
-                                      &pmx_gpio_45 &pmx_gpio_46
-                                      &pmx_gpio_47 &pmx_gpio_48 >;
-                        pinctrl-names = "default";
-                        pmx_gpio_12: pmx-gpio-12 {
                                marvell,pins = "mpp12";
                                marvell,function = "gpio";
                        };
-                        pmx_gpio_35: pmx-gpio-35 {
+                        pmx_button_otb: pmx-button-otb {
                                marvell,pins = "mpp35";
                                marvell,function = "gpio";
                        };
-                        pmx_gpio_41: pmx-gpio-41 {
+                        pmx_led_level: pmx-led-level {
                                marvell,pins = "mpp41";
                                marvell,function = "gpio";
                        };
-                        pmx_gpio_42: pmx-gpio-42 {
+                        pmx_led_power_blue: pmx-led-power-blue {
                                marvell,pins = "mpp42";
                                marvell,function = "gpio";
                        };
-                        pmx_gpio_43: pmx-gpio-43 {
+                        pmx_led_power_red: pmx-power-red {
                                marvell,pins = "mpp43";
                                marvell,function = "gpio";
                        };
-                        pmx_gpio_44: pmx-gpio-44 {
+                        pmx_led_usb1: pmx-led-usb1 {
                                marvell,pins = "mpp44";
                                marvell,function = "gpio";
                        };
-                        pmx_gpio_45: pmx-gpio-45 {
+                        pmx_led_usb2: pmx-led-usb2 {
                                marvell,pins = "mpp45";
                                marvell,function = "gpio";
                        };
-                        pmx_gpio_46: pmx-gpio-46 {
+                        pmx_led_usb3: pmx-led-usb3 {
                                marvell,pins = "mpp46";
                                marvell,function = "gpio";
                        };
-                        pmx_gpio_47: pmx-gpio-47 {
+                        pmx_led_usb4: pmx-led-usb4 {
                                marvell,pins = "mpp47";
                                marvell,function = "gpio";
                        };
-                        pmx_gpio_48: pmx-gpio-48 {
+                        pmx_led_otb: pmx-led-otb {
                                marvell,pins = "mpp48";
                                marvell,function = "gpio";
                        };
@@ -109,10 +101,23 @@
                                reg = <0x980000 0x1f400000>;
                        };
                };
+                pcie-controller {
+                        status = "okay";
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
        };
        gpio-leds {
                compatible = "gpio-leds";
+                pinctrl-0 = < &pmx_led_level &pmx_led_power_blue
+                              &pmx_led_power_red &pmx_led_usb1
+                              &pmx_led_usb2 &pmx_led_usb3
+                              &pmx_led_usb4 &pmx_led_otb >;
+                pinctrl-names = "default";
                led-level {
                        label = "led_level";
@@ -154,6 +159,9 @@
                compatible = "gpio-keys";
                #address-cells = <1>;
                #size-cells = <0>;
+                pinctrl-0 = < &pmx_button_reset &pmx_button_otb >;
+                pinctrl-names = "default";
                button@1 {
                        label = "OTB Button";
                        linux,code = <133>;
diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
index 3694e94f6e99..00a7bfe5e83b 100644
--- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
+++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
@@ -18,12 +18,7 @@
        ocp@f1000000 {
                pinctrl: pinctrl@10000 {
+                        pinctrl-0 = < &pmx_led_sata_brt_ctrl_1
-                        pinctrl-0 = < &pmx_button_reset &pmx_button_power
-                                      &pmx_led_backup &pmx_led_power
-                                      &pmx_button_otb &pmx_led_rebuild
-                                      &pmx_led_health
-                                      &pmx_led_sata_brt_ctrl_1
                                      &pmx_led_sata_brt_ctrl_2
                                      &pmx_led_backup_brt_ctrl_1
                                      &pmx_led_backup_brt_ctrl_2
@@ -151,6 +146,9 @@
        };
        gpio-leds {
                compatible = "gpio-leds";
+                pinctrl-0 = < &pmx_led_backup &pmx_led_power
+                              &pmx_led_rebuild &pmx_led_health >;
+                pinctrl-names = "default";
                power_led {
                        label = "status:white:power_led";
@@ -174,6 +172,11 @@
                compatible = "gpio-keys";
                #address-cells = <1>;
                #size-cells = <0>;
+                pinctrl-0 = <&pmx_button_reset &pmx_button_power
+                             &pmx_button_otb>;
+                pinctrl-names = "default";
                Power {
                        label = "Power Button";
                        linux,code = <116>;
diff --git a/arch/arm/boot/dts/kirkwood-is2.dts b/arch/arm/boot/dts/kirkwood-is2.dts
index 0bdce0ad7277..c3f036b86cca 100644
--- a/arch/arm/boot/dts/kirkwood-is2.dts
+++ b/arch/arm/boot/dts/kirkwood-is2.dts
@@ -13,6 +13,8 @@
        ocp@f1000000 {
                sata@80000 {
+                        pinctrl-0 = <&pmx_ns2_sata0>;
+                        pinctrl-names = "default";
                        status = "okay";
                        nr-ports = <1>;
                };
diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
index 5bbd0542cdd3..5d9f5ea78700 100644
--- a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
+++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
@@ -18,9 +18,7 @@
        ocp@f1000000 {
                pinctrl: pinctrl@10000 {
+                        pinctrl-0 = < &pmx_i2c_gpio_sda &pmx_i2c_gpio_scl >;
-                        pinctrl-0 = < &pmx_nand &pmx_i2c_gpio_sda
-                                &pmx_i2c_gpio_scl >;
                        pinctrl-names = "default";
                        pmx_i2c_gpio_sda: pmx-gpio-sda {
@@ -38,8 +36,17 @@
                };
                nand@3000000 {
+                        pinctrl-0 = <&pmx_nand>;
+                        pinctrl-names = "default";
                        status = "ok";
                        chip-delay = <25>;
                };
        };
+        i2c@0 {
+                compatible = "i2c-gpio";
+                gpios = < &gpio0 8 0            /* sda */
+                        &gpio0 9 0 >;           /* scl */
+                i2c-gpio,delay-us = <2>;        /* ~100 kHz */
+        };
 };
diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
index 37d45c4f88fb..31b17f5b9d28 100644
--- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi
+++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
@@ -8,16 +8,6 @@
        ocp@f1000000 {
                pinctrl: pinctrl@10000 {
-                        pinctrl-0 = < &pmx_power_hdd &pmx_usb_vbus
-                                      &pmx_fan_low &pmx_fan_high
-                                      &pmx_led_function_red &pmx_led_alarm
-                                      &pmx_led_info &pmx_led_power
-                                      &pmx_fan_lock &pmx_button_function
-                                      &pmx_power_switch &pmx_power_auto_switch
-                                      &pmx_led_function_blue >;
-                        pinctrl-names = "default";
                        pmx_power_hdd: pmx-power-hdd {
                                marvell,pins = "mpp10";
                                marvell,function = "gpo";
@@ -112,6 +102,10 @@
                compatible = "gpio-keys";
                #address-cells = <1>;
                #size-cells = <0>;
+                pinctrl-0 = <&pmx_button_function &pmx_power_switch
+                             &pmx_power_auto_switch>;
+                pinctrl-names = "default";
                button@1 {
                        label = "Function Button";
                        linux,code = <357>;
@@ -133,6 +127,10 @@
        gpio_leds {
                compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm
+                             &pmx_led_info &pmx_led_power
+                             &pmx_led_function_blue>;
+                pinctrl-names = "default";
                led@1 {
                        label = "lsxl:blue:func";
@@ -163,6 +161,8 @@
        gpio_fan {
                compatible = "gpio-fan";
+                pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>;
+                pinctrl-names = "default";
                gpios = <&gpio0 19 1
                         &gpio0 18 1>;
                gpio-fan,speed-map = <0    3
@@ -172,10 +172,16 @@
                alarm-gpios = <&gpio1 8 0>;
        };
+        restart_poweroff {
+                compatible = "restart-poweroff";
+        };
        regulators {
                compatible = "simple-bus";
                #address-cells = <1>;
                #size-cells = <0>;
+                pinctrl-0 = <&pmx_power_hdd &pmx_usb_vbus>;
+                pinctrl-names = "default";
                usb_power: regulator@1 {
                        compatible = "regulator-fixed";
diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts
index 758824118a9a..6179333fd71f 100644
--- a/arch/arm/boot/dts/kirkwood-mplcec4.dts
+++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts
@@ -18,16 +18,6 @@
        ocp@f1000000 {
                pinctrl: pinctrl@10000 {
-                        pinctrl-0 = < &pmx_nand &pmx_uart0
-                                      &pmx_led_health
-                                      &pmx_sata0 &pmx_sata1
-                                      &pmx_led_user1o
-                                      &pmx_led_user1g &pmx_led_user0o
-                                      &pmx_led_user0g &pmx_led_misc
-                                    >;
-                        pinctrl-names = "default";
                        pmx_led_health: pmx-led-health {
                                marvell,pins = "mpp7";
                                marvell,function = "gpo";
@@ -91,9 +81,13 @@
                serial@12000 {
                        status = "ok";
+                        pinctrl-0 = <&pmx_uart0>;
+                        pinctrl-names = "default";
                };
                nand@3000000 {
+                        pinctrl-0 = <&pmx_nand>;
+                        pinctrl-names = "default";
                        status = "okay";
                        partition@0 {
@@ -127,22 +121,37 @@
                };
                sata@80000 {
+                        pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
+                        pinctrl-names = "default";
                        nr-ports = <2>;
                        status = "okay";
                };
                mvsdio@90000 {
                        pinctrl-0 = <&pmx_sdio &pmx_sdio_cd>;
                        pinctrl-names = "default";
                        status = "okay";
-                        cd-gpios = <&gpio1 15 0>;
+                        cd-gpios = <&gpio1 15 1>;
                        /* No WP GPIO */
                };
+                pcie-controller {
+                        status = "okay";
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
        };
        gpio-leds {
                compatible = "gpio-leds";
+                pinctrl-0 = < &pmx_led_health
+                              &pmx_led_user1o
+                              &pmx_led_user1g &pmx_led_user0o
+                              &pmx_led_user0g &pmx_led_misc
+                            >;
+                pinctrl-names = "default";
                health {
                        label = "status:green:health";
diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
index 1ca66ab83ad6..ad6ade7d9191 100644
--- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
+++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
@@ -18,18 +18,6 @@
        ocp@f1000000 {
                pinctrl: pinctrl@10000 {
-                        pinctrl-0 = < &pmx_uart0
-                                      &pmx_button_power
-                                      &pmx_button_backup
-                                      &pmx_button_reset
-                                      &pmx_led_blue_power
-                                      &pmx_led_blue_activity
-                                      &pmx_led_blue_disk1
-                                      &pmx_led_blue_disk2
-                                      &pmx_led_blue_backup >;
-                        pinctrl-names = "default";
                        pmx_button_power: pmx-button-power {
                                marvell,pins = "mpp47";
                                marvell,function = "gpio";
@@ -74,6 +62,8 @@
                };
                serial@12000 {
+                        pinctrl-0 = <&pmx_uart0>;
+                        pinctrl-names = "default";
                        status = "okay";
                };
@@ -111,10 +101,22 @@
                        status = "okay";
                        nr-ports = <2>;
                };
+                pcie-controller {
+                        status = "okay";
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
        };
        gpio-leds {
                compatible = "gpio-leds";
+                pinctrl-0 = < &pmx_led_blue_power &pmx_led_blue_activity
+                              &pmx_led_blue_disk1 &pmx_led_blue_disk2
+                              &pmx_led_blue_backup >;
+                pinctrl-names = "default";
                power_led {
                        label = "status:blue:power_led";
@@ -143,6 +145,10 @@
                compatible = "gpio-keys";
                #address-cells = <1>;
                #size-cells = <0>;
+                pinctrl-0 = <&pmx_button_power &pmx_button_backup
+                             &pmx_button_reset>;
+                pinctrl-names = "default";
                button@1 {
                        label = "Power Button";
                        linux,code = <116>;     /* KEY_POWER */
diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
index 6affd924fe11..2afac0405816 100644
--- a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
+++ b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
@@ -8,10 +8,6 @@
        ocp@f1000000 {
                pinctrl: pinctrl@10000 {
-                        pinctrl-0 = < &pmx_spi &pmx_twsi0 &pmx_uart0
-                                        &pmx_ns2_sata0 &pmx_ns2_sata1>;
-                        pinctrl-names = "default";
                        pmx_ns2_sata0: pmx-ns2-sata0 {
                                marvell,pins = "mpp21";
                                marvell,function = "sata0";
@@ -23,10 +19,14 @@
                };
                serial@12000 {
+                        pinctrl-0 = <&pmx_uart0>;
+                        pinctrl-names = "default";
                        status = "okay";
                };
                spi@10600 {
+                        pinctrl-0 = <&pmx_spi>;
+                        pinctrl-names = "default";
                        status = "okay";
                        flash@0 {
@@ -45,6 +45,8 @@
                };
                i2c@11000 {
+                        pinctrl-0 = <&pmx_twsi0>;
+                        pinctrl-names = "default";
                        status = "okay";
                        eeprom@50 {
diff --git a/arch/arm/boot/dts/kirkwood-ns2.dts b/arch/arm/boot/dts/kirkwood-ns2.dts
index f2d36ecf36d8..b50e93d7796c 100644
--- a/arch/arm/boot/dts/kirkwood-ns2.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2.dts
@@ -13,6 +13,8 @@
        ocp@f1000000 {
                sata@80000 {
+                        pinctrl-0 = <&pmx_ns2_sata0>;
+                        pinctrl-names = "default";
                        status = "okay";
                        nr-ports = <1>;
                };
diff --git a/arch/arm/boot/dts/kirkwood-ns2lite.dts b/arch/arm/boot/dts/kirkwood-ns2lite.dts
index b02eb4ea1bb4..af8259fe8955 100644
--- a/arch/arm/boot/dts/kirkwood-ns2lite.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2lite.dts
@@ -13,6 +13,8 @@
        ocp@f1000000 {
                sata@80000 {
+                        pinctrl-0 = <&pmx_ns2_sata0>;
+                        pinctrl-names = "default";
                        status = "okay";
                        nr-ports = <1>;
                };
diff --git a/arch/arm/boot/dts/kirkwood-ns2max.dts b/arch/arm/boot/dts/kirkwood-ns2max.dts
index bcec4d6cada7..85f24d227e17 100644
--- a/arch/arm/boot/dts/kirkwood-ns2max.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2max.dts
@@ -13,6 +13,8 @@
        ocp@f1000000 {
                sata@80000 {
+                        pinctrl-0 = <&pmx_ns2_sata0 &pmx_ns2_sata1>;
+                        pinctrl-names = "default";
                        status = "okay";
                        nr-ports = <2>;
                };
diff --git a/arch/arm/boot/dts/kirkwood-ns2mini.dts b/arch/arm/boot/dts/kirkwood-ns2mini.dts
index adab1ab25733..329e530bffe7 100644
--- a/arch/arm/boot/dts/kirkwood-ns2mini.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2mini.dts
@@ -14,6 +14,8 @@
        ocp@f1000000 {
                sata@80000 {
+                        pinctrl-0 = <&pmx_ns2_sata0>;
+                        pinctrl-names = "default";
                        status = "okay";
                        nr-ports = <1>;
                };
diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts
index a7412b937a8a..69003598f5fa 100644
--- a/arch/arm/boot/dts/kirkwood-nsa310.dts
+++ b/arch/arm/boot/dts/kirkwood-nsa310.dts
@@ -1,6 +1,7 @@
 /dts-v1/;
 /include/ "kirkwood.dtsi"
+/include/ "kirkwood-6281.dtsi"
 / {
        model = "ZyXEL NSA310";
@@ -17,22 +18,7 @@
        ocp@f1000000 {
                pinctrl: pinctrl@10000 {
-                        pinctrl-0 = < &pmx_led_esata_green
+                        pinctrl-0 = <&pmx_unknown>;
-                                      &pmx_led_esata_red
-                                      &pmx_led_usb_green
-                                      &pmx_led_usb_red
-                                      &pmx_usb_power_off
-                                      &pmx_led_sys_green
-                                      &pmx_led_sys_red
-                                      &pmx_btn_reset
-                                      &pmx_btn_copy
-                                      &pmx_led_copy_green
-                                      &pmx_led_copy_red
-                                      &pmx_led_hdd_green
-                                      &pmx_led_hdd_red
-                                      &pmx_unknown
-                                      &pmx_btn_power
-                                      &pmx_pwr_off >;
                        pinctrl-names = "default";
                        pmx_led_esata_green: pmx-led-esata-green {
@@ -176,12 +162,22 @@
                                reg = <0x5040000 0x2fc0000>;
                        };
                };
+                pcie-controller {
+                        status = "okay";
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
        };
        gpio_keys {
                compatible = "gpio-keys";
                #address-cells = <1>;
                #size-cells = <0>;
+                pinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>;
+                pinctrl-names = "default";
                button@1 {
                        label = "Power Button";
@@ -202,6 +198,12 @@
        gpio-leds {
                compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_led_esata_green &pmx_led_esata_red
+                             &pmx_led_usb_green &pmx_led_usb_red
+                             &pmx_led_sys_green &pmx_led_sys_red
+                             &pmx_led_copy_green &pmx_led_copy_red
+                             &pmx_led_hdd_green &pmx_led_hdd_red>;
+                pinctrl-names = "default";
                green-sys {
                        label = "nsa310:green:sys";
@@ -247,6 +249,8 @@
        gpio_poweroff {
                compatible = "gpio-poweroff";
+                pinctrl-0 = <&pmx_pwr_off>;
+                pinctrl-names = "default";
                gpios = <&gpio1 16 0>;
        };
@@ -254,6 +258,8 @@
                compatible = "simple-bus";
                #address-cells = <1>;
                #size-cells = <0>;
+                pinctrl-0 = <&pmx_usb_power_off>;
+                pinctrl-names = "default";
                usb0_power_off: regulator@1 {
                        compatible = "regulator-fixed";
diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
index d27f7245f8e7..38dc8517d777 100644
--- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
+++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
@@ -19,15 +19,21 @@
        ocp@f1000000 {
                serial@12000 {
                        status = "ok";
+                        pinctrl-0 = <&pmx_uart0>;
+                        pinctrl-names = "default";
                };
                serial@12100 {
                        status = "ok";
+                        pinctrl-0 = <&pmx_uart1>;
+                        pinctrl-names = "default";
                };
                nand@3000000 {
                        chip-delay = <25>;
                        status = "okay";
+                        pinctrl-0 = <&pmx_nand>;
+                        pinctrl-names = "default";
                        partition@0 {
                                label = "uboot";
@@ -67,6 +73,8 @@
                i2c@11100 {
                        status = "okay";
+                        pinctrl-0 = <&pmx_twsi1>;
+                        pinctrl-names = "default";
                        s35390a: s35390a@30 {
                                compatible = "s35390a";
@@ -75,16 +83,7 @@
                };
                pinctrl: pinctrl@10000 {
-                        pinctrl-0 = < &pmx_nand &pmx_uart0
+                        pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header>;
-                                &pmx_uart1 &pmx_twsi1
-                                &pmx_dip_sw0 &pmx_dip_sw1
-                                &pmx_dip_sw2 &pmx_dip_sw3
-                                &pmx_gpio_0 &pmx_gpio_1
-                                &pmx_gpio_2 &pmx_gpio_3
-                                &pmx_gpio_4 &pmx_gpio_5
-                                &pmx_gpio_6 &pmx_gpio_7
-                                &pmx_led_red &pmx_led_green
-                                &pmx_led_yellow >;
                        pinctrl-names = "default";
                        pmx_uart0: pmx-uart0 {
@@ -104,63 +103,14 @@
                                marvell,function = "sysrst";
                        };
-                        pmx_dip_sw0: pmx-dip-sw0 {
+                        pmx_dip_switches: pmx-dip-switches {
-                                marvell,pins = "mpp20";
+                                marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23";
-                                marvell,function = "gpio";
-                        };
-                        pmx_dip_sw1: pmx-dip-sw1 {
-                                marvell,pins = "mpp21";
-                                marvell,function = "gpio";
-                        };
-                        pmx_dip_sw2: pmx-dip-sw2 {
-                                marvell,pins = "mpp22";
-                                marvell,function = "gpio";
-                        };
-                        pmx_dip_sw3: pmx-dip-sw3 {
-                                marvell,pins = "mpp23";
-                                marvell,function = "gpio";
-                        };
-                        pmx_gpio_0: pmx-gpio-0 {
-                                marvell,pins = "mpp24";
-                                marvell,function = "gpio";
-                        };
-                        pmx_gpio_1: pmx-gpio-1 {
-                                marvell,pins = "mpp25";
-                                marvell,function = "gpio";
-                        };
-                        pmx_gpio_2: pmx-gpio-2 {
-                                marvell,pins = "mpp26";
                                marvell,function = "gpio";
                        };
-                        pmx_gpio_3: pmx-gpio-3 {
+                        pmx_gpio_header: pmx-gpio-header {
-                                marvell,pins = "mpp27";
+                                marvell,pins = "mpp24", "mpp25", "mpp26", "mpp27",
-                                marvell,function = "gpio";
+                                               "mpp28", "mpp29", "mpp30", "mpp31";
-                        };
-                        pmx_gpio_4: pmx-gpio-4 {
-                                marvell,pins = "mpp28";
-                                marvell,function = "gpio";
-                        };
-                        pmx_gpio_5: pmx-gpio-5 {
-                                marvell,pins = "mpp29";
-                                marvell,function = "gpio";
-                        };
-                        pmx_gpio_6: pmx-gpio-6 {
-                                marvell,pins = "mpp30";
-                                marvell,function = "gpio";
-                        };
-                        pmx_gpio_7: pmx-gpio-7 {
-                                marvell,pins = "mpp31";
                                marvell,function = "gpio";
                        };
@@ -174,18 +124,8 @@
                                marvell,function = "gpio";
                        };
-                        pmx_led_red: pmx-led-red {
+                        pmx_leds: pmx-leds {
-                                marvell,pins = "mpp41";
+                                marvell,pins = "mpp41", "mpp42", "mpp43";
-                                marvell,function = "gpio";
-                        };
-                        pmx_led_green: pmx-led-green {
-                                marvell,pins = "mpp42";
-                                marvell,function = "gpio";
-                        };
-                        pmx_led_yellow: pmx-led-yellow {
-                                marvell,pins = "mpp43";
                                marvell,function = "gpio";
                        };
                };
@@ -193,6 +133,8 @@
        gpio-leds {
                compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_leds>;
+                pinctrl-names = "default";
                led-red {
                        label = "obsa6:red:stat";
@@ -209,4 +151,18 @@
                        gpios = <&gpio1 11 1>;
                };
        };
+        gpio_keys {
+                compatible = "gpio-keys";
+                pinctrl-0 = <&pmx_gpio_init>;
+                pinctrl-names = "default";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                button@1 {
+                        label = "Init Button";
+                        linux,code = <116>;
+                        gpios = <&gpio1 6 0>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
new file mode 100644
index 000000000000..f7143f128504
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
@@ -0,0 +1,93 @@
+/*
+ * kirkwood-sheevaplug-common.dts - Common parts for Sheevaplugs
+ *
+ * Copyright (C) 2013 Simon Baatz <gmbnomis@gmail.com>
+ *
+ * Licensed under GPLv2
+ */
+/include/ "kirkwood.dtsi"
+/include/ "kirkwood-6281.dtsi"
+/ {
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x20000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+        ocp@f1000000 {
+                pinctrl: pinctrl@10000 {
+                        pmx_usb_power_enable: pmx-usb-power-enable {
+                                marvell,pins = "mpp29";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_red: pmx-led-red {
+                                marvell,pins = "mpp46";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_blue: pmx-led-blue {
+                                marvell,pins = "mpp49";
+                                marvell,function = "gpio";
+                        };
+                        pmx_sdio_cd: pmx-sdio-cd {
+                                marvell,pins = "mpp44";
+                                marvell,function = "gpio";
+                        };
+                        pmx_sdio_wp: pmx-sdio-wp {
+                                marvell,pins = "mpp47";
+                                marvell,function = "gpio";
+                        };
+                };
+                serial@12000 {
+                        pinctrl-0 = <&pmx_uart0>;
+                        pinctrl-names = "default";
+                        status = "okay";
+                };
+                nand@3000000 {
+                        pinctrl-0 = <&pmx_nand>;
+                        pinctrl-names = "default";
+                        status = "okay";
+                        partition@0 {
+                                label = "u-boot";
+                                reg = <0x0000000 0x100000>;
+                        };
+                        partition@100000 {
+                                label = "uImage";
+                                reg = <0x0100000 0x400000>;
+                        };
+                        partition@500000 {
+                                label = "root";
+                                reg = <0x0500000 0x1fb00000>;
+                        };
+                };
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-0 = <&pmx_usb_power_enable>;
+                pinctrl-names = "default";
+                usb_power: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "USB Power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio0 29 0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
new file mode 100644
index 000000000000..f620ce48de97
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
@@ -0,0 +1,43 @@
+/*
+ * kirkwood-sheevaplug-esata.dts - Device tree file for eSATA Sheevaplug
+ *
+ * Copyright (C) 2013 Simon Baatz <gmbnomis@gmail.com>
+ *
+ * Licensed under GPLv2
+ */
+/dts-v1/;
+/include/ "kirkwood-sheevaplug-common.dtsi"
+/ {
+        model = "Globalscale Technologies eSATA SheevaPlug";
+        compatible = "globalscale,sheevaplug-esata-rev13", "globalscale,sheevaplug-esata", "globalscale,sheevaplug", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+        ocp@f1000000 {
+                sata@80000 {
+                        status = "okay";
+                        nr-ports = <2>;
+                };
+                mvsdio@90000 {
+                        pinctrl-0 = <&pmx_sdio &pmx_sdio_cd &pmx_sdio_wp>;
+                        pinctrl-names = "default";
+                        status = "okay";
+                        cd-gpios = <&gpio1 12 1>;
+                        wp-gpios = <&gpio1 15 0>;
+                };
+        };
+        gpio-leds {
+                compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_led_blue>;
+                pinctrl-names = "default";
+                health {
+                        label = "sheevaplug:blue:health";
+                        gpios = <&gpio1 17 1>;
+                        linux,default-trigger = "default-on";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug.dts b/arch/arm/boot/dts/kirkwood-sheevaplug.dts
new file mode 100644
index 000000000000..bf1dff251432
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-sheevaplug.dts
@@ -0,0 +1,43 @@
+/*
+ * kirkwood-sheevaplug-esata.dts - Device tree file for Sheevaplug
+ *
+ * Copyright (C) 2013 Simon Baatz <gmbnomis@gmail.com>
+ *
+ * Licensed under GPLv2
+ */
+/dts-v1/;
+/include/ "kirkwood-sheevaplug-common.dtsi"
+/ {
+        model = "Globalscale Technologies SheevaPlug";
+        compatible = "globalscale,sheevaplug", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+        ocp@f1000000 {
+                mvsdio@90000 {
+                        pinctrl-0 = <&pmx_sdio>;
+                        pinctrl-names = "default";
+                        status = "okay";
+                        /* No CD or WP GPIOs */
+                        broken-cd;
+                };
+        };
+        gpio-leds {
+                compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_led_blue &pmx_led_red>;
+                pinctrl-names = "default";
+                health {
+                        label = "sheevaplug:blue:health";
+                        gpios = <&gpio1 17 1>;
+                        linux,default-trigger = "default-on";
+                };
+                misc {
+                        label = "sheevaplug:red:misc";
+                        gpios = <&gpio1 14 1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts
index 66eb45b00b25..f2052d7bc10f 100644
--- a/arch/arm/boot/dts/kirkwood-topkick.dts
+++ b/arch/arm/boot/dts/kirkwood-topkick.dts
@@ -19,18 +19,6 @@
        ocp@f1000000 {
                pinctrl: pinctrl@10000 {
                        /*
-                         * GPIO LED layout
-                         *
-                         *       /-SYS_LED(2)
-                         *       |
-                         *       |   /-DISK_LED
-                         *       |   |
-                         *       |   |   /-WLAN_LED(2)
-                         *       |   |   |
-                         * [SW] [*] [*] [*]
-                         */
-                        /*
                         * Switch positions
                         *
                         *     /-SW_LEFT(2)
@@ -41,19 +29,8 @@
                         *     |   |   |
                         * PS [L] [I] [R] LEDS
                         */
-                        pinctrl-0 = < &pmx_led_disk_yellow
+                        pinctrl-0 = <&pmx_sw_left &pmx_sw_right
-                                      &pmx_sata0_pwr_enable
+                                     &pmx_sw_idle &pmx_sw_left2>;
-                                      &pmx_led_sys_red
-                                      &pmx_led_sys_blue
-                                      &pmx_led_wifi_green
-                                      &pmx_sw_left
-                                      &pmx_sw_right
-                                      &pmx_sw_idle
-                                      &pmx_sw_left2
-                                      &pmx_led_wifi_yellow
-                                      &pmx_uart0
-                                      &pmx_nand
-                                      &pmx_twsi0 >;
                        pinctrl-names = "default";
                        pmx_led_disk_yellow: pmx-led-disk-yellow {
@@ -109,10 +86,14 @@
                serial@12000 {
                        status = "ok";
+                        pinctrl-0 = <&pmx_uart0>;
+                        pinctrl-names = "default";
                };
                nand@3000000 {
                        status = "okay";
+                        pinctrl-0 = <&pmx_nand>;
+                        pinctrl-names = "default";
                        partition@0 {
                                label = "u-boot";
@@ -147,6 +128,8 @@
                i2c@11000 {
                        status = "ok";
+                        pinctrl-0 = <&pmx_twsi0>;
+                        pinctrl-names = "default";
                };
                mvsdio@90000 {
@@ -154,11 +137,28 @@
                        pinctrl-names = "default";
                        status = "okay";
                        /* No CD or WP GPIOs */
+                        broken-cd;
                };
        };
        gpio-leds {
+                /*
+                 * GPIO LED layout
+                 *
+                 *       /-SYS_LED(2)
+                 *       |
+                 *       |   /-DISK_LED
+                 *       |   |
+                 *       |   |   /-WLAN_LED(2)
+                 *       |   |   |
+                 * [SW] [*] [*] [*]
+                 */
                compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_led_disk_yellow &pmx_led_sys_red
+                             &pmx_led_sys_blue &pmx_led_wifi_green
+                             &pmx_led_wifi_yellow>;
+                pinctrl-names = "default";
                disk {
                        label = "topkick:yellow:disk";
@@ -187,6 +187,8 @@
                compatible = "simple-bus";
                #address-cells = <1>;
                #size-cells = <0>;
+                pinctrl-0 = <&pmx_sata0_pwr_enable>;
+                pinctrl-names = "default";
                sata0_power: regulator@1 {
                        compatible = "regulator-fixed";
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
index 8295c833887f..6dd1038e4de4 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
@@ -1,16 +1,14 @@
 /dts-v1/;
-/include/ "kirkwood-ts219.dtsi"
+/include/ "kirkwood.dtsi"
 /include/ "kirkwood-6281.dtsi"
+/include/ "kirkwood-ts219.dtsi"
 / {
        ocp@f1000000 {
                pinctrl: pinctrl@10000 {
-                        pinctrl-0 = < &pmx_uart0 &pmx_uart1 &pmx_spi
+                        pinctrl-0 = <&pmx_ram_size &pmx_board_id>;
-                                      &pmx_twsi0 &pmx_sata0 &pmx_sata1
-                                      &pmx_ram_size &pmx_reset_button
-                                      &pmx_USB_copy_button &pmx_board_id>;
                        pinctrl-names = "default";
                        pmx_ram_size: pmx-ram-size {
@@ -38,6 +36,9 @@
                compatible = "gpio-keys";
                #address-cells = <1>;
                #size-cells = <0>;
+                pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>;
+                pinctrl-names = "default";
                button@1 {
                        label = "USB Copy";
                        linux,code = <133>;
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
index df3f95dfba33..6fdc5ffcaae5 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
@@ -1,16 +1,14 @@
 /dts-v1/;
-/include/ "kirkwood-ts219.dtsi"
+/include/ "kirkwood.dtsi"
 /include/ "kirkwood-6282.dtsi"
+/include/ "kirkwood-ts219.dtsi"
 / {
        ocp@f1000000 {
                pinctrl: pinctrl@10000 {
-                        pinctrl-0 = < &pmx_uart0 &pmx_uart1 &pmx_spi
+                        pinctrl-0 = <&pmx_ram_size &pmx_board_id>;
-                                      &pmx_twsi0 &pmx_sata0 &pmx_sata1
-                                      &pmx_ram_size &pmx_reset_button
-                                      &pmx_USB_copy_button &pmx_board_id>;
                        pinctrl-names = "default";
                        pmx_ram_size: pmx-ram-size {
@@ -32,12 +30,23 @@
                                marvell,function = "gpio";
                        };
                };
+                pcie-controller {
+                        status = "okay";
+                        pcie@2,0 {
+                                status = "okay";
+                        };
+                };
        };
        gpio_keys {
                compatible = "gpio-keys";
                #address-cells = <1>;
                #size-cells = <0>;
+                pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>;
+                pinctrl-names = "default";
                button@1 {
                        label = "USB Copy";
                        linux,code = <133>;
diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi
index 64ea27cb3298..0c9a94cd666c 100644
--- a/arch/arm/boot/dts/kirkwood-ts219.dtsi
+++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi
@@ -1,5 +1,3 @@
-/include/ "kirkwood.dtsi"
 / {
        model = "QNAP TS219 family";
        compatible = "qnap,ts219", "marvell,kirkwood";
@@ -17,6 +15,8 @@
                i2c@11000 {
                        status = "okay";
                        clock-frequency = <400000>;
+                        pinctrl-0 = <&pmx_twsi0>;
+                        pinctrl-names = "default";
                        s35390a: s35390a@30 {
                                compatible = "s35390a";
@@ -26,13 +26,24 @@
                serial@12000 {
                        clock-frequency = <200000000>;
                        status = "okay";
+                        pinctrl-0 = <&pmx_uart0>;
+                        pinctrl-names = "default";
                };
                serial@12100 {
                        clock-frequency = <200000000>;
                        status = "okay";
+                        pinctrl-0 = <&pmx_uart1>;
+                        pinctrl-names = "default";
+                };
+                poweroff@12100 {
+                        compatible = "qnap,power-off";
+                        reg = <0x12000 0x100>;
+                        clocks = <&gate_clk 7>;
                };
                spi@10600 {
                        status = "okay";
+                        pinctrl-0 = <&pmx_spi>;
+                        pinctrl-names = "default";
                        m25p128@0 {
                                #address-cells = <1>;
@@ -71,8 +82,17 @@
                        };
                };
                sata@80000 {
+                        pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
+                        pinctrl-names = "default";
                        status = "okay";
                        nr-ports = <2>;
                };
+                pcie-controller {
+                        status = "okay";
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
        };
 };
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index fada7e6d24d8..9809fc1f105c 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -4,6 +4,18 @@
        compatible = "marvell,kirkwood";
        interrupt-parent = <&intc>;
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "marvell,feroceon";
+                        clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
+                        clock-names = "cpu_clk", "ddrclk", "powersave";
+                };
+        };
        aliases {
               gpio0 = &gpio0;
               gpio1 = &gpio1;
@@ -18,7 +30,9 @@
        ocp@f1000000 {
                compatible = "simple-bus";
-                ranges = <0x00000000 0xf1000000 0x4000000
+                ranges = <0x00000000 0xf1000000 0x0100000
+                          0xe0000000 0xe0000000 0x8100000 /* PCIE */
+                          0xf4000000 0xf4000000 0x0000400
                          0xf5000000 0xf5000000 0x0000400>;
                #address-cells = <1>;
                #size-cells = <1>;
@@ -71,13 +85,6 @@
                        status = "disabled";
                };
-                rtc@10300 {
-                        compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
-                        reg = <0x10300 0x20>;
-                        interrupts = <53>;
-                        clocks = <&gate_clk 7>;
-                };
                spi@10600 {
                        compatible = "marvell,orion-spi";
                        #address-cells = <1>;
@@ -151,15 +158,6 @@
                        status = "okay";
                };
-                sata@80000 {
-                        compatible = "marvell,orion-sata";
-                        reg = <0x80000 0x5000>;
-                        interrupts = <21>;
-                        clocks = <&gate_clk 14>, <&gate_clk 15>;
-                        clock-names = "0", "1";
-                        status = "disabled";
-                };
                nand@3000000 {
                        #address-cells = <1>;
                        #size-cells = <1>;
@@ -167,7 +165,7 @@
                        ale = <1>;
                        bank-width = <1>;
                        compatible = "marvell,orion-nand";
-                        reg = <0x3000000 0x400>;
+                        reg = <0xf4000000 0x400>;
                        chip-delay = <25>;
                        /* set partition map and/or chip-delay in board dts */
                        clocks = <&gate_clk 7>;
@@ -194,13 +192,5 @@
                        clocks = <&gate_clk 17>;
                        status = "okay";
                };
-                mvsdio@90000 {
-                        compatible = "marvell,orion-sdio";
-                        reg = <0x90000 0x200>;
-                        interrupts = <28>;
-                        clocks = <&gate_clk 4>;
-                        status = "disabled";
-                };
        };
 };
diff --git a/arch/arm/boot/dts/kizbox.dts b/arch/arm/boot/dts/kizbox.dts
index b4dc3ed9a3ec..02df1914a47c 100644
--- a/arch/arm/boot/dts/kizbox.dts
+++ b/arch/arm/boot/dts/kizbox.dts
@@ -6,7 +6,7 @@
 * Licensed under GPLv2.
 */
 /dts-v1/;
-/include/ "at91sam9g20.dtsi"
+#include "at91sam9g20.dtsi"
 / {
@@ -94,26 +94,26 @@
                led1g {
                        label = "led1:green";
-                        gpios = <&pioB 0 1>;
+                        gpios = <&pioB 0 GPIO_ACTIVE_LOW>;
                        linux,default-trigger = "none";
                };
                led1r {
                        label = "led1:red";
-                        gpios = <&pioB 1 1>;
+                        gpios = <&pioB 1 GPIO_ACTIVE_LOW>;
                        linux,default-trigger = "none";
                };
                led2g {
                        label = "led2:green";
-                        gpios = <&pioB 2 1>;
+                        gpios = <&pioB 2 GPIO_ACTIVE_LOW>;
                        linux,default-trigger = "none";
                        default-state = "on";
                };
                led2r {
                        label = "led2:red";
-                        gpios = <&pioB 3 1>;
+                        gpios = <&pioB 3 GPIO_ACTIVE_LOW>;
                        linux,default-trigger = "none";
                };
        };
@@ -125,16 +125,16 @@
                reset {
                        label = "reset";
-                        gpios = <&pioB 30 1>;
+                        gpios = <&pioB 30 GPIO_ACTIVE_LOW>;
                        linux,code = <0x100>;
                        gpio-key,wakeup;
                };
                mode {
                        label = "mode";
-                        gpios = <&pioB 31 1>;
+                        gpios = <&pioB 31 GPIO_ACTIVE_LOW>;
                        linux,code = <0x101>;
                        gpio-key,wakeup;
                };
        };
-};
-\ No newline at end of file
+};
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index 1582f484a867..3abebb75fc57 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -18,8 +18,12 @@
        interrupt-parent = <&mic>;
        cpus {
-                cpu@0 {
+                #address-cells = <0>;
-                        compatible = "arm,arm926ejs";
+                #size-cells = <0>;
+                cpu {
+                        compatible = "arm,arm926ej-s";
+                        device_type = "cpu";
                };
        };
diff --git a/arch/arm/boot/dts/mpa1600.dts b/arch/arm/boot/dts/mpa1600.dts
index 317300875f34..ccf9ea242f72 100644
--- a/arch/arm/boot/dts/mpa1600.dts
+++ b/arch/arm/boot/dts/mpa1600.dts
@@ -6,7 +6,7 @@
 * Licensed under GPLv2 only
 */
 /dts-v1/;
-/include/ "at91rm9200.dtsi"
+#include "at91rm9200.dtsi"
 / {
        model = "Phontech MPA 1600";
@@ -62,7 +62,7 @@
                monitor_mute {
                        label = "Monitor mute";
-                        gpios = <&pioC 1 1>;
+                        gpios = <&pioC 1 GPIO_ACTIVE_LOW>;
                        linux,code = <113>;
                };
        };
diff --git a/arch/arm/boot/dts/msm8660-surf.dts b/arch/arm/boot/dts/msm8660-surf.dts
index 9bf49b3826ea..cdc010e0f93e 100644
--- a/arch/arm/boot/dts/msm8660-surf.dts
+++ b/arch/arm/boot/dts/msm8660-surf.dts
@@ -15,7 +15,7 @@
                      < 0x02081000 0x1000 >;
        };
-        timer@2000004 {
+        timer@2000000 {
                compatible = "qcom,scss-timer", "qcom,msm-timer";
                interrupts = <1 0 0x301>,
                             <1 1 0x301>,
@@ -26,7 +26,18 @@
                cpu-offset = <0x40000>;
        };
-        serial@19c400000 {
+        msmgpio: gpio@800000 {
+                compatible = "qcom,msm-gpio";
+                reg = <0x00800000 0x1000>;
+                gpio-controller;
+                #gpio-cells = <2>;
+                ngpio = <173>;
+                interrupts = <0 32 0x4>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        serial@19c40000 {
                compatible = "qcom,msm-hsuart", "qcom,msm-uart";
                reg = <0x19c40000 0x1000>,
                      <0x19c00000 0x1000>;
diff --git a/arch/arm/boot/dts/msm8960-cdp.dts b/arch/arm/boot/dts/msm8960-cdp.dts
index 2e4d87a125d6..9c1167b0459b 100644
--- a/arch/arm/boot/dts/msm8960-cdp.dts
+++ b/arch/arm/boot/dts/msm8960-cdp.dts
@@ -26,7 +26,18 @@
                cpu-offset = <0x80000>;
        };
-        serial@19c400000 {
+        msmgpio: gpio@800000 {
+                compatible = "qcom,msm-gpio";
+                gpio-controller;
+                #gpio-cells = <2>;
+                ngpio = <150>;
+                interrupts = <0 32 0x4>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                reg = <0x800000 0x4000>;
+        };
+        serial@16440000 {
                compatible = "qcom,msm-hsuart", "qcom,msm-uart";
                reg = <0x16440000 0x1000>,
                      <0x16400000 0x1000>;
diff --git a/arch/arm/boot/dts/nspire-classic.dtsi b/arch/arm/boot/dts/nspire-classic.dtsi
new file mode 100644
index 000000000000..9565199bce7a
--- /dev/null
+++ b/arch/arm/boot/dts/nspire-classic.dtsi
@@ -0,0 +1,74 @@
+/*
+ *  linux/arch/arm/boot/nspire-classic.dts
+ *
+ *  Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+/include/ "nspire.dtsi"
+&lcd {
+        lcd-type = "classic";
+};
+&fast_timer {
+        /* compatible = "lsi,zevio-timer"; */
+        reg = <0x90010000 0x1000>, <0x900A0010 0x8>;
+};
+&uart {
+        compatible = "ns16550";
+        reg-shift = <2>;
+        reg-io-width = <4>;
+        clocks = <&apb_pclk>;
+        no-loopback-test;
+};
+&timer0 {
+        /* compatible = "lsi,zevio-timer"; */
+        reg = <0x900C0000 0x1000>, <0x900A0018 0x8>;
+};
+&timer1 {
+        compatible = "lsi,zevio-timer";
+        reg = <0x900D0000 0x1000>, <0x900A0020 0x8>;
+};
+&keypad {
+        active-low;
+};
+&base_clk {
+        compatible = "lsi,nspire-classic-clock";
+};
+&ahb_clk {
+        compatible = "lsi,nspire-classic-ahb-divider";
+};
+/ {
+        memory {
+                device_type = "memory";
+                reg = <0x10000000 0x2000000>; /* 32 MB */
+        };
+        ahb {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                intc: interrupt-controller@DC000000 {
+                        compatible = "lsi,zevio-intc";
+                        interrupt-controller;
+                        reg = <0xDC000000 0x1000>;
+                        #interrupt-cells = <1>;
+                };
+        };
+        chosen {
+                bootargs = "debug earlyprintk console=tty0 console=ttyS0,115200n8 root=/dev/ram0";
+        };
+};
diff --git a/arch/arm/boot/dts/nspire-clp.dts b/arch/arm/boot/dts/nspire-clp.dts
new file mode 100644
index 000000000000..fa5a044656de
--- /dev/null
+++ b/arch/arm/boot/dts/nspire-clp.dts
@@ -0,0 +1,45 @@
+/*
+ *  linux/arch/arm/boot/nspire-clp.dts
+ *
+ *  Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+/dts-v1/;
+/include/ "nspire-classic.dtsi"
+&keypad {
+        linux,keymap = <
+        0x0000001c      0x0001001c      0x00020039
+        0x0004002c      0x00050034      0x00060015
+        0x0007000b      0x0008002d      0x01000033
+        0x0101004e      0x01020011      0x01030004
+        0x0104002f      0x01050003      0x01060016
+        0x01070002      0x01080014      0x02000062
+        0x0201000c      0x0202001f      0x02030007
+        0x02040013      0x02050006      0x02060010
+        0x02070005      0x02080019      0x03000027
+        0x03010037      0x03020018      0x0303000a
+        0x03040031      0x03050009      0x03060032
+        0x03070008      0x03080026      0x04000028
+        0x04010035      0x04020025      0x04040024
+        0x04060017      0x04080023      0x05000028
+        0x05020022      0x0503001b      0x05040021
+        0x0505001a      0x05060012      0x0507006f
+        0x05080020      0x0509002a      0x0601001c
+        0x0602002e      0x06030068      0x06040030
+        0x0605006d      0x0606001e      0x06070001
+        0x0608002b      0x0609000f      0x07000067
+        0x0702006a      0x0704006c      0x07060069
+        0x0707000e      0x0708001d      0x070a000d
+        >;
+};
+/ {
+        model = "TI-NSPIRE Clickpad";
+        compatible = "ti,nspire-clp";
+};
diff --git a/arch/arm/boot/dts/nspire-cx.dts b/arch/arm/boot/dts/nspire-cx.dts
new file mode 100644
index 000000000000..375b924f60d8
--- /dev/null
+++ b/arch/arm/boot/dts/nspire-cx.dts
@@ -0,0 +1,112 @@
+/*
+ *  linux/arch/arm/boot/nspire-cx.dts
+ *
+ *  Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+/dts-v1/;
+/include/ "nspire.dtsi"
+&lcd {
+        lcd-type = "cx";
+};
+&fast_timer {
+        /* compatible = "arm,sp804", "arm,primecell"; */
+};
+&uart {
+        compatible = "arm,pl011", "arm,primecell";
+        clocks = <&uart_clk>, <&apb_pclk>;
+        clock-names = "uart_clk", "apb_pclk";
+};
+&timer0 {
+        compatible = "arm,sp804", "arm,primecell";
+};
+&timer1 {
+        compatible = "arm,sp804", "arm,primecell";
+};
+&base_clk {
+        compatible = "lsi,nspire-cx-clock";
+};
+&ahb_clk {
+        compatible = "lsi,nspire-cx-ahb-divider";
+};
+&keypad {
+        linux,keymap = <
+        0x0000001c      0x0001001c      0x00040039
+        0x0005002c      0x00060015      0x0007000b
+        0x0008000f      0x0100002d      0x01010011
+        0x0102002f      0x01030004      0x01040016
+        0x01050014      0x0106001f      0x01070002
+        0x010a006a      0x02000013      0x02010010
+        0x02020019      0x02030007      0x02040018
+        0x02050031      0x02060032      0x02070005
+        0x02080028      0x0209006c      0x03000026
+        0x03010025      0x03020024      0x0303000a
+        0x03040017      0x03050023      0x03060022
+        0x03070008      0x03080035      0x03090069
+        0x04000021      0x04010012      0x04020020
+        0x0404002e      0x04050030      0x0406001e
+        0x0407000d      0x04080037      0x04090067
+        0x05010038      0x0502000c      0x0503001b
+        0x05040034      0x0505001a      0x05060006
+        0x05080027      0x0509000e      0x050a006f
+        0x0600002b      0x0602004e      0x06030068
+        0x06040003      0x0605006d      0x06060009
+        0x06070001      0x0609000f      0x0708002a
+        0x0709001d      0x070a0033      >;
+};
+/ {
+        model = "TI-NSPIRE CX";
+        compatible = "ti,nspire-cx";
+        memory {
+                device_type = "memory";
+                reg = <0x10000000 0x4000000>; /* 64 MB */
+        };
+        uart_clk: uart_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <12000000>;
+        };
+        ahb {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                intc: interrupt-controller@DC000000 {
+                        compatible = "arm,pl190-vic";
+                        interrupt-controller;
+                        reg = <0xDC000000 0x1000>;
+                        #interrupt-cells = <1>;
+                };
+                apb@90000000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        i2c@90050000 {
+                                compatible = "snps,designware-i2c";
+                                reg = <0x90050000 0x1000>;
+                                interrupts = <20>;
+                        };
+                };
+        };
+        chosen {
+                bootargs = "debug earlyprintk console=tty0 console=ttyAMA0,115200n8 root=/dev/ram0";
+        };
+};
diff --git a/arch/arm/boot/dts/nspire-tp.dts b/arch/arm/boot/dts/nspire-tp.dts
new file mode 100644
index 000000000000..621391ce6ed6
--- /dev/null
+++ b/arch/arm/boot/dts/nspire-tp.dts
@@ -0,0 +1,44 @@
+/*
+ *  linux/arch/arm/boot/nspire-tp.dts
+ *
+ *  Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+/dts-v1/;
+/include/ "nspire-classic.dtsi"
+&keypad {
+        linux,keymap = <
+        0x0000001c      0x0001001c      0x00040039
+        0x0005002c      0x00060015      0x0007000b
+        0x0008000f      0x0100002d      0x01010011
+        0x0102002f      0x01030004      0x01040016
+        0x01050014      0x0106001f      0x01070002
+        0x010a006a      0x02000013      0x02010010
+        0x02020019      0x02030007      0x02040018
+        0x02050031      0x02060032      0x02070005
+        0x02080028      0x0209006c      0x03000026
+        0x03010025      0x03020024      0x0303000a
+        0x03040017      0x03050023      0x03060022
+        0x03070008      0x03080035      0x03090069
+        0x04000021      0x04010012      0x04020020
+        0x0404002e      0x04050030      0x0406001e
+        0x0407000d      0x04080037      0x04090067
+        0x05010038      0x0502000c      0x0503001b
+        0x05040034      0x0505001a      0x05060006
+        0x05080027      0x0509000e      0x050a006f
+        0x0600002b      0x0602004e      0x06030068
+        0x06040003      0x0605006d      0x06060009
+        0x06070001      0x0609000f      0x0708002a
+        0x0709001d      0x070a0033      >;
+};
+/ {
+        model = "TI-NSPIRE Touchpad";
+        compatible = "ti,nspire-tp";
+};
diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire.dtsi
new file mode 100644
index 000000000000..a22ffe633b49
--- /dev/null
+++ b/arch/arm/boot/dts/nspire.dtsi
@@ -0,0 +1,175 @@
+/*
+ *  linux/arch/arm/boot/nspire.dtsi
+ *
+ *  Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+/include/ "skeleton.dtsi"
+/ {
+        interrupt-parent = <&intc>;
+        cpus {
+                cpu@0 {
+                        compatible = "arm,arm926ejs";
+                };
+        };
+        bootrom: bootrom@00000000 {
+                reg = <0x00000000 0x80000>;
+        };
+        sram: sram@A4000000 {
+                device = "memory";
+                reg = <0xA4000000 0x20000>;
+        };
+        timer_clk: timer_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+        base_clk: base_clk {
+                #clock-cells = <0>;
+                reg = <0x900B0024 0x4>;
+        };
+        ahb_clk: ahb_clk {
+                #clock-cells = <0>;
+                reg = <0x900B0024 0x4>;
+                clocks = <&base_clk>;
+        };
+        apb_pclk: apb_pclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clock-div = <2>;
+                clock-mult = <1>;
+                clocks = <&ahb_clk>;
+        };
+        ahb {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                spi: spi@A9000000 {
+                        reg = <0xA9000000 0x1000>;
+                };
+                usb0: usb@B0000000 {
+                        reg = <0xB0000000 0x1000>;
+                        interrupts = <8>;
+                };
+                usb1: usb@B4000000 {
+                        reg = <0xB4000000 0x1000>;
+                        interrupts = <9>;
+                        status = "disabled";
+                };
+                lcd: lcd@C0000000 {
+                        compatible = "arm,pl111", "arm,primecell";
+                        reg = <0xC0000000 0x1000>;
+                        interrupts = <21>;
+                        clocks = <&apb_pclk>;
+                        clock-names = "apb_pclk";
+                };
+                adc: adc@C4000000 {
+                        reg = <0xC4000000 0x1000>;
+                        interrupts = <11>;
+                };
+                tdes: crypto@C8010000 {
+                        reg = <0xC8010000 0x1000>;
+                };
+                sha256: crypto@CC000000 {
+                        reg = <0xCC000000 0x1000>;
+                };
+                apb@90000000 {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        clock-ranges;
+                        ranges;
+                        gpio: gpio@90000000 {
+                                reg = <0x90000000 0x1000>;
+                                interrupts = <7>;
+                        };
+                        fast_timer: timer@90010000 {
+                                reg = <0x90010000 0x1000>;
+                                interrupts = <17>;
+                        };
+                        uart: serial@90020000 {
+                                reg = <0x90020000 0x1000>;
+                                interrupts = <1>;
+                        };
+                        timer0: timer@900C0000 {
+                                reg = <0x900C0000 0x1000>;
+                                clocks = <&timer_clk>;
+                        };
+                        timer1: timer@900D0000 {
+                                reg = <0x900D0000 0x1000>;
+                                interrupts = <19>;
+                                clocks = <&timer_clk>;
+                        };
+                        watchdog: watchdog@90060000 {
+                                compatible = "arm,amba-primecell";
+                                reg = <0x90060000 0x1000>;
+                                interrupts = <3>;
+                        };
+                        rtc: rtc@90090000 {
+                                reg = <0x90090000 0x1000>;
+                                interrupts = <4>;
+                        };
+                        misc: misc@900A0000 {
+                                reg = <0x900A0000 0x1000>;
+                        };
+                        pwr: pwr@900B0000 {
+                                reg = <0x900B0000 0x1000>;
+                                interrupts = <15>;
+                        };
+                        keypad: input@900E0000 {
+                                compatible = "ti,nspire-keypad";
+                                reg = <0x900E0000 0x1000>;
+                                interrupts = <16>;
+                                scan-interval = <1000>;
+                                row-delay = <200>;
+                                clocks = <&apb_pclk>;
+                        };
+                        contrast: contrast@900F0000 {
+                                reg = <0x900F0000 0x1000>;
+                        };
+                        led: led@90110000 {
+                                reg = <0x90110000 0x1000>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index 37aa7487d4d8..a2bfcde858a6 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -8,7 +8,10 @@
 * kind, whether express or implied.
 */
-/include/ "skeleton.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/omap.h>
+#include "skeleton.dtsi"
 / {
        compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
@@ -21,8 +24,12 @@
        };
        cpus {
-                cpu@0 {
+                #address-cells = <0>;
+                #size-cells = <0>;
+                cpu {
                        compatible = "arm,arm1136jf-s";
+                        device_type = "cpu";
                };
        };
diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts
index 68282ee13e26..224c08f472f4 100644
--- a/arch/arm/boot/dts/omap2420-h4.dts
+++ b/arch/arm/boot/dts/omap2420-h4.dts
@@ -7,7 +7,7 @@
 */
 /dts-v1/;
-/include/ "omap2420.dtsi"
+#include "omap2420.dtsi"
 / {
        model = "TI OMAP2420 H4 board";
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index da5b285b73be..c8f9c55169ea 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -8,7 +8,7 @@
 * kind, whether express or implied.
 */
-/include/ "omap2.dtsi"
+#include "omap2.dtsi"
 / {
        compatible = "ti,omap2420", "ti,omap2";
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index 054bc4439568..c535a5a2b27f 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -8,7 +8,7 @@
 * kind, whether express or implied.
 */
-/include/ "omap2.dtsi"
+#include "omap2.dtsi"
 / {
        compatible = "ti,omap2430", "ti,omap2";
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index 3046d1f81be0..afdb16417d4e 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -7,7 +7,7 @@
 */
 /dts-v1/;
-/include/ "omap36xx.dtsi"
+#include "omap36xx.dtsi"
 / {
        model = "TI OMAP3 BeagleBoard xM";
@@ -29,13 +29,13 @@
                heartbeat {
                        label = "beagleboard::usr0";
-                        gpios = <&gpio5 22 0>; /* 150 -> D6 LED */
+                        gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */
                        linux,default-trigger = "heartbeat";
                };
                mmc {
                        label = "beagleboard::usr1";
-                        gpios = <&gpio5 21 0>; /* 149 -> D7 LED */
+                        gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */
                        linux,default-trigger = "mmc0";
                };
        };
@@ -57,6 +57,26 @@
                ti,mcbsp = <&mcbsp2>;
                ti,codec = <&twl_audio>;
        };
+        gpio_keys {
+                compatible = "gpio-keys";
+                user {
+                        label = "user";
+                        gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+                        linux,code = <0x114>;
+                        gpio-key,wakeup;
+                };
+        };
+};
+&omap3_pmx_wkup {
+        gpio1_pins: pinmux_gpio1_pins {
+                pinctrl-single,pins = <
+                        0x0e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot2.gpio_4 */
+                >;
+        };
 };
 &i2c1 {
@@ -75,7 +95,8 @@
        };
 };
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
 &i2c2 {
        clock-frequency = <400000>;
@@ -126,3 +147,22 @@
        mode = <3>;
        power = <50>;
 };
+&omap3_pmx_core {
+        uart3_pins: pinmux_uart3_pins {
+                pinctrl-single,pins = <
+                        0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
+                        0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */
+                >;
+        };
+};
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart3_pins>;
+};
+&gpio1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&gpio1_pins>;
+};
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index 6eec69997607..dfd83103657a 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -7,7 +7,7 @@
 */
 /dts-v1/;
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 / {
        model = "TI OMAP3 BeagleBoard";
@@ -28,18 +28,18 @@
                compatible = "gpio-leds";
                pmu_stat {
                        label = "beagleboard::pmu_stat";
-                        gpios = <&twl_gpio 19 0>; /* LEDB */
+                        gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */
                };
                heartbeat {
                        label = "beagleboard::usr0";
-                        gpios = <&gpio5 22 0>; /* 150 -> D6 LED */
+                        gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */
                        linux,default-trigger = "heartbeat";
                };
                mmc {
                        label = "beagleboard::usr1";
-                        gpios = <&gpio5 21 0>; /* 149 -> D7 LED */
+                        gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */
                        linux,default-trigger = "mmc0";
                };
        };
@@ -71,6 +71,26 @@
                reset-supply = <&hsusb2_reset>;
                vcc-supply = <&hsusb2_power>;
        };
+        gpio_keys {
+                compatible = "gpio-keys";
+                user {
+                        label = "user";
+                        gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+                        linux,code = <0x114>;
+                        gpio-key,wakeup;
+                };
+        };
+};
+&omap3_pmx_wkup {
+        gpio1_pins: pinmux_gpio1_pins {
+                pinctrl-single,pins = <
+                        0x14 (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot5.gpio_7 */
+                >;
+        };
 };
 &omap3_pmx_core {
@@ -81,18 +101,25 @@
        hsusbb2_pins: pinmux_hsusbb2_pins {
                pinctrl-single,pins = <
-                        0x5c0 0x3  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_clk OUTPUT */
+                        0x5c0 (PIN_OUTPUT | MUX_MODE3)          /* usbb2_ulpitll_clk.usbb1_ulpiphy_clk */
-                        0x5c2 0x3  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_stp OUTPUT */
+                        0x5c2 (PIN_OUTPUT | MUX_MODE3)          /* usbb2_ulpitll_clk.usbb1_ulpiphy_stp */
-                        0x5c4 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dir INPUT | PULLDOWN */
+                        0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* usbb2_ulpitll_clk.usbb1_ulpiphy_dir */
-                        0x5c6 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_nxt INPUT | PULLDOWN */
+                        0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* usbb2_ulpitll_clk.usbb1_ulpiphy_nxt */
-                        0x5c8 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat0 INPUT | PULLDOWN */
+                        0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat0 */
-                        0x5cA 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat1 INPUT | PULLDOWN */
+                        0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat1 */
-                        0x1a4 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat2 INPUT | PULLDOWN */
+                        0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat2 */
-                        0x1a6 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat3 INPUT | PULLDOWN */
+                        0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat3 */
-                        0x1a8 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat4 INPUT | PULLDOWN */
+                        0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat4 */
-                        0x1aa 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat5 INPUT | PULLDOWN */
+                        0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat5 */
-                        0x1ac 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat6 INPUT | PULLDOWN */
+                        0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat6 */
-                        0x1ae 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat7 INPUT | PULLDOWN */
+                        0x1ae (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat7 */
+                >;
+        };
+        uart3_pins: pinmux_uart3_pins {
+                pinctrl-single,pins = <
+                        0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
+                        0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
                >;
        };
 };
@@ -107,7 +134,8 @@
        };
 };
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
 &mmc1 {
        vmmc-supply = <&vmmc1>;
@@ -142,3 +170,13 @@
         */
        ti,pulldowns = <0x03a1c4>;
 };
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart3_pins>;
+};
+&gpio1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&gpio1_pins>;
+};
diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts
index 8a5cdcc6debd..7ef282795dd4 100644
--- a/arch/arm/boot/dts/omap3-devkit8000.dts
+++ b/arch/arm/boot/dts/omap3-devkit8000.dts
@@ -7,7 +7,7 @@
 */
 /dts-v1/;
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 / {
        model = "TimLL OMAP3 Devkit8000";
        compatible = "timll,omap3-devkit8000", "ti,omap3";
@@ -22,21 +22,21 @@
                heartbeat {
                        label = "devkit8000::led1";
-                        gpios = <&gpio6 26 0>;  /* 186 -> LED1 */
+                        gpios = <&gpio6 26 GPIO_ACTIVE_HIGH>;   /* 186 -> LED1 */
                        default-state = "on";
                        linux,default-trigger = "heartbeat";
                };
                mmc {
                        label = "devkit8000::led2";
-                        gpios = <&gpio6 3 0>;   /* 163 -> LED2 */
+                        gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>;    /* 163 -> LED2 */
                        default-state = "on";
                        linux,default-trigger = "none";
                };
                usr {
                        label = "devkit8000::led3";
-                        gpios = <&gpio6 4 0>;   /* 164 -> LED3 */
+                        gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>;    /* 164 -> LED3 */
                        default-state = "on";
                        linux,default-trigger = "usr";
                };
@@ -80,7 +80,8 @@
        status = "disabled";
 };
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
 &mmc1 {
        vmmc-supply = <&vmmc1>;
@@ -123,20 +124,21 @@
                reg = <0 0 0>; /* CS0, offset 0 */
                nand-bus-width = <16>;
-                gpmc,sync-clk = <0>;
+                gpmc,device-nand;
-                gpmc,cs-on = <0>;
+                gpmc,sync-clki-ps = <0>;
-                gpmc,cs-rd-off = <44>;
+                gpmc,cs-on-ns = <0>;
-                gpmc,cs-wr-off = <44>;
+                gpmc,cs-rd-off-ns = <44>;
-                gpmc,adv-on = <6>;
+                gpmc,cs-wr-off-ns = <44>;
-                gpmc,adv-rd-off = <34>;
+                gpmc,adv-on-ns = <6>;
-                gpmc,adv-wr-off = <44>;
+                gpmc,adv-rd-off-ns = <34>;
-                gpmc,we-off = <40>;
+                gpmc,adv-wr-off-ns = <44>;
-                gpmc,oe-off = <54>;
+                gpmc,we-off-ns = <40>;
-                gpmc,access = <64>;
+                gpmc,oe-off-ns = <54>;
-                gpmc,rd-cycle = <82>;
+                gpmc,access-ns = <64>;
-                gpmc,wr-cycle = <82>;
+                gpmc,rd-cycle-ns = <82>;
-                gpmc,wr-access = <40>;
+                gpmc,wr-cycle-ns = <82>;
-                gpmc,wr-data-mux-bus = <0>;
+                gpmc,wr-access-ns = <40>;
+                gpmc,wr-data-mux-bus-ns = <0>;
                #address-cells = <1>;
                #size-cells = <1>;
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
index 96d1c206a57b..7d4329d179c4 100644
--- a/arch/arm/boot/dts/omap3-evm.dts
+++ b/arch/arm/boot/dts/omap3-evm.dts
@@ -7,7 +7,7 @@
 */
 /dts-v1/;
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 / {
        model = "TI OMAP3 EVM (OMAP3530, AM/DM37x)";
@@ -28,7 +28,7 @@
                compatible = "gpio-leds";
                ledb {
                        label = "omap3evm::ledb";
-                        gpios = <&twl_gpio 19 0>; /* LEDB */
+                        gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */
                        linux,default-trigger = "default-on";
                };
        };
@@ -44,7 +44,8 @@
        };
 };
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
 &i2c2 {
        clock-frequency = <400000>;
diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi
index f8fe3b748c3e..bc48b114eae6 100644
--- a/arch/arm/boot/dts/omap3-igep.dtsi
+++ b/arch/arm/boot/dts/omap3-igep.dtsi
@@ -10,7 +10,7 @@
 */
 /dts-v1/;
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 / {
        memory {
@@ -29,37 +29,43 @@
 &omap3_pmx_core {
        uart1_pins: pinmux_uart1_pins {
                pinctrl-single,pins = <
-                        0x152 0x100     /* uart1_rx.uart1_rx INPUT | MODE0 */
+                        0x152 (PIN_INPUT | MUX_MODE0)           /* uart1_rx.uart1_rx */
-                        0x14c 0         /* uart1_tx.uart1_tx OUTPUT | MODE0 */
+                        0x14c (PIN_OUTPUT |MUX_MODE0)           /* uart1_tx.uart1_tx */
                >;
        };
        uart2_pins: pinmux_uart2_pins {
                pinctrl-single,pins = <
-                        0x14a 0x100     /* uart2_rx.uart2_rx INPUT | MODE0 */
+                        0x14a (PIN_INPUT | MUX_MODE0)           /* uart2_rx.uart2_rx */
-                        0x148 0         /* uart2_tx.uart2_tx OUTPUT | MODE0 */
+                        0x148 (PIN_OUTPUT | MUX_MODE0)          /* uart2_tx.uart2_tx */
                >;
        };
        uart3_pins: pinmux_uart3_pins {
                pinctrl-single,pins = <
-                        0x16e 0x100     /* uart3_rx.uart3_rx INPUT | MODE0 */
+                        0x16e (PIN_INPUT | MUX_MODE0)           /* uart3_rx.uart3_rx */
-                        0x170 0         /* uart3_tx.uart3_tx OUTPUT | MODE0 */
+                        0x170 (PIN_OUTPUT | MUX_MODE0)          /* uart3_tx.uart3_tx */
                >;
        };
        mmc1_pins: pinmux_mmc1_pins {
                pinctrl-single,pins = <
-                        0x114 0x0118    /* sdmmc1_clk.sdmmc1_clk INPUT PULLUP | MODE 0 */
+                        0x114 (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_clk.sdmmc1_clk */
-                        0x116 0x0118    /* sdmmc1_cmd.sdmmc1_cmd INPUT PULLUP | MODE 0 */
+                        0x116 (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_cmd.sdmmc1_cmd */
-                        0x118 0x0118    /* sdmmc1_dat0.sdmmc1_dat0 INPUT PULLUP | MODE 0 */
+                        0x118 (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_dat0.sdmmc1_dat0 */
-                        0x11a 0x0118    /* sdmmc1_dat1.sdmmc1_dat1 INPUT PULLUP | MODE 0 */
+                        0x11a (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_dat1.sdmmc1_dat1 */
-                        0x11c 0x0118    /* sdmmc1_dat2.sdmmc1_dat2 INPUT PULLUP | MODE 0 */
+                        0x11c (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_dat2.sdmmc1_dat2 */
-                        0x11e 0x0118    /* sdmmc1_dat3.sdmmc1_dat3 INPUT PULLUP | MODE 0 */
+                        0x11e (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_dat3.sdmmc1_dat3 */
-                        0x120 0x0100    /* sdmmc1_dat4.sdmmc1_dat4 INPUT | MODE 0 */
+                        0x120 (PIN_INPUT | MUX_MODE0)           /* sdmmc1_dat4.sdmmc1_dat4 */
-                        0x122 0x0100    /* sdmmc1_dat5.sdmmc1_dat5 INPUT | MODE 0 */
+                        0x122 (PIN_INPUT | MUX_MODE0)           /* sdmmc1_dat5.sdmmc1_dat5 */
-                        0x124 0x0100    /* sdmmc1_dat6.sdmmc1_dat6 INPUT | MODE 0 */
+                        0x124 (PIN_INPUT | MUX_MODE0)           /* sdmmc1_dat6.sdmmc1_dat6 */
-                        0x126 0x0100    /* sdmmc1_dat7.sdmmc1_dat7 INPUT | MODE 0 */
+                        0x126 (PIN_INPUT | MUX_MODE0)           /* sdmmc1_dat7.sdmmc1_dat7 */
+                >;
+        };
+        smsc911x_pins: pinmux_smsc911x_pins {
+                pinctrl-single,pins = <
+                        0x1a2 (PIN_INPUT | MUX_MODE4)           /* mcspi1_cs2.gpio_176 */
                >;
        };
 };
@@ -80,7 +86,8 @@
        };
 };
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
 &i2c2 {
        clock-frequency = <400000>;
diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts
index e2b98490cc9a..e8c48284587c 100644
--- a/arch/arm/boot/dts/omap3-igep0020.dts
+++ b/arch/arm/boot/dts/omap3-igep0020.dts
@@ -9,7 +9,7 @@
 * published by the Free Software Foundation.
 */
-/include/ "omap3-igep.dtsi"
+#include "omap3-igep.dtsi"
 / {
        model = "IGEPv2";
@@ -19,27 +19,39 @@
                compatible = "gpio-leds";
                boot {
                         label = "omap3:green:boot";
-                         gpios = <&gpio1 26 0>;
+                         gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
                         default-state = "on";
                };
                user0 {
                         label = "omap3:red:user0";
-                         gpios = <&gpio1 27 0>;
+                         gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
                         default-state = "off";
                };
                user1 {
                         label = "omap3:red:user1";
-                         gpios = <&gpio1 28 0>;
+                         gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
                         default-state = "off";
                };
                user2 {
                        label = "omap3:green:user1";
-                        gpios = <&twl_gpio 19 1>;
+                        gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>;
                };
        };
+        vddvario: regulator-vddvario {
+                  compatible = "regulator-fixed";
+                  regulator-name = "vddvario";
+                  regulator-always-on;
+        };
+        vdd33a: regulator-vdd33a {
+                compatible = "regulator-fixed";
+                regulator-name = "vdd33a";
+                regulator-always-on;
+        };
 };
 &i2c3 {
@@ -54,3 +66,92 @@
                reg = <0x50>;
        };
 };
+&gpmc {
+        ranges = <0 0 0x00000000 0x20000000>,
+                 <5 0 0x2c000000 0x01000000>;
+        nand@0,0 {
+                linux,mtd-name= "micron,mt29c4g96maz";
+                reg = <0 0 0>;
+                nand-bus-width = <16>;
+                ti,nand-ecc-opt = "bch8";
+                gpmc,sync-clk-ps = <0>;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <44>;
+                gpmc,cs-wr-off-ns = <44>;
+                gpmc,adv-on-ns = <6>;
+                gpmc,adv-rd-off-ns = <34>;
+                gpmc,adv-wr-off-ns = <44>;
+                gpmc,we-off-ns = <40>;
+                gpmc,oe-off-ns = <54>;
+                gpmc,access-ns = <64>;
+                gpmc,rd-cycle-ns = <82>;
+                gpmc,wr-cycle-ns = <82>;
+                gpmc,wr-access-ns = <40>;
+                gpmc,wr-data-mux-bus-ns = <0>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                partition@0 {
+                        label = "SPL";
+                        reg = <0 0x100000>;
+                };
+                partition@0x80000 {
+                        label = "U-Boot";
+                        reg = <0x100000 0x180000>;
+                };
+                partition@0x1c0000 {
+                        label = "Environment";
+                        reg = <0x280000 0x100000>;
+                };
+                partition@0x280000 {
+                        label = "Kernel";
+                        reg = <0x380000 0x300000>;
+                };
+                partition@0x780000 {
+                        label = "Filesystem";
+                        reg = <0x680000 0x1f980000>;
+                };
+        };
+        ethernet@5,0 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&smsc911x_pins>;
+                compatible = "smsc,lan9221", "smsc,lan9115";
+                reg = <5 0 0xff>;
+                bank-width = <2>;
+                gpmc,mux-add-data;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <186>;
+                gpmc,cs-wr-off-ns = <186>;
+                gpmc,adv-on-ns = <12>;
+                gpmc,adv-rd-off-ns = <48>;
+                gpmc,adv-wr-off-ns = <48>;
+                gpmc,oe-on-ns = <54>;
+                gpmc,oe-off-ns = <168>;
+                gpmc,we-on-ns = <54>;
+                gpmc,we-off-ns = <168>;
+                gpmc,rd-cycle-ns = <186>;
+                gpmc,wr-cycle-ns = <186>;
+                gpmc,access-ns = <114>;
+                gpmc,page-burst-access-ns = <6>;
+                gpmc,bus-turnaround-ns = <12>;
+                gpmc,cycle2cycle-delay-ns = <18>;
+                gpmc,wr-data-mux-bus-ns = <90>;
+                gpmc,wr-access-ns = <186>;
+                gpmc,cycle2cycle-samecsen;
+                gpmc,cycle2cycle-diffcsen;
+                interrupt-parent = <&gpio6>;
+                interrupts = <16 8>;
+                vmmc-supply = <&vddvario>;
+                vmmc_aux-supply = <&vdd33a>;
+                reg-io-width = <4>;
+                smsc,save-mac-address;
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-igep0030.dts b/arch/arm/boot/dts/omap3-igep0030.dts
index 9dc48d262ffb..644d05383836 100644
--- a/arch/arm/boot/dts/omap3-igep0030.dts
+++ b/arch/arm/boot/dts/omap3-igep0030.dts
@@ -9,7 +9,7 @@
 * published by the Free Software Foundation.
 */
-/include/ "omap3-igep.dtsi"
+#include "omap3-igep.dtsi"
 / {
        model = "IGEP COM Module";
@@ -19,26 +19,76 @@
                compatible = "gpio-leds";
                boot {
                         label = "omap3:green:boot";
-                         gpios = <&twl_gpio 13 1>;
+                         gpios = <&twl_gpio 13 GPIO_ACTIVE_LOW>;
                         default-state = "on";
                };
                user0 {
                         label = "omap3:red:user0";
-                         gpios = <&twl_gpio 18 1>; /* LEDA */
+                         gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */
                         default-state = "off";
                };
                user1 {
                         label = "omap3:green:user1";
-                         gpios = <&twl_gpio 19 1>; /* LEDB */
+                         gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; /* LEDB */
                         default-state = "off";
                };
                user2 {
                         label = "omap3:red:user1";
-                         gpios = <&gpio1 16 1>;
+                         gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
                         default-state = "off";
                };
        };
 };
+&gpmc {
+        ranges = <0 0 0x00000000 0x20000000>;
+        nand@0,0 {
+                linux,mtd-name= "micron,mt29c4g96maz";
+                reg = <0 0 0>;
+                nand-bus-width = <16>;
+                ti,nand-ecc-opt = "bch8";
+                gpmc,sync-clk-ps = <0>;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <44>;
+                gpmc,cs-wr-off-ns = <44>;
+                gpmc,adv-on-ns = <6>;
+                gpmc,adv-rd-off-ns = <34>;
+                gpmc,adv-wr-off-ns = <44>;
+                gpmc,we-off-ns = <40>;
+                gpmc,oe-off-ns = <54>;
+                gpmc,access-ns = <64>;
+                gpmc,rd-cycle-ns = <82>;
+                gpmc,wr-cycle-ns = <82>;
+                gpmc,wr-access-ns = <40>;
+                gpmc,wr-data-mux-bus-ns = <0>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                partition@0 {
+                        label = "SPL";
+                        reg = <0 0x100000>;
+                };
+                partition@0x80000 {
+                        label = "U-Boot";
+                        reg = <0x100000 0x180000>;
+                };
+                partition@0x1c0000 {
+                        label = "Environment";
+                        reg = <0x280000 0x100000>;
+                };
+                partition@0x280000 {
+                        label = "Kernel";
+                        reg = <0x380000 0x300000>;
+                };
+                partition@0x780000 {
+                        label = "Filesystem";
+                        reg = <0x680000 0x1f980000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-overo.dtsi b/arch/arm/boot/dts/omap3-overo.dtsi
index a626c50041f6..8f1abec78275 100644
--- a/arch/arm/boot/dts/omap3-overo.dtsi
+++ b/arch/arm/boot/dts/omap3-overo.dtsi
@@ -11,7 +11,7 @@
 */
 /dts-v1/;
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 / {
        pwmleds {
@@ -21,6 +21,7 @@
                        label = "overo:blue:COM";
                        pwms = <&twl_pwmled 1 7812500>;
                        max-brightness = <127>;
+                        linux,default-trigger = "mmc0";
                };
        };
@@ -49,7 +50,8 @@
        };
 };
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
 /* i2c2 pins are used for gpio */
 &i2c2 {
@@ -77,3 +79,17 @@
        mode = <3>;
        power = <50>;
 };
+&omap3_pmx_core {
+        uart3_pins: pinmux_uart3_pins {
+                pinctrl-single,pins = <
+                        0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
+                        0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
+                >;
+        };
+};
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart3_pins>;
+};
diff --git a/arch/arm/boot/dts/omap3-tobi.dts b/arch/arm/boot/dts/omap3-tobi.dts
index a13d12de77ff..7e4ad2aec37a 100644
--- a/arch/arm/boot/dts/omap3-tobi.dts
+++ b/arch/arm/boot/dts/omap3-tobi.dts
@@ -10,7 +10,7 @@
 * Tobi expansion board is manufactured by Gumstix Inc.
 */
-/include/ "omap3-overo.dtsi"
+#include "omap3-overo.dtsi"
 / {
        model = "TI OMAP3 Gumstix Overo on Tobi";
@@ -20,10 +20,58 @@
                compatible = "gpio-leds";
                heartbeat {
                        label = "overo:red:gpio21";
-                        gpios = <&gpio1 21 0>;
+                        gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
                        linux,default-trigger = "heartbeat";
                };
        };
+        vddvario: regulator-vddvario {
+                  compatible = "regulator-fixed";
+                  regulator-name = "vddvario";
+                  regulator-always-on;
+        };
+        vdd33a: regulator-vdd33a {
+                compatible = "regulator-fixed";
+                regulator-name = "vdd33a";
+                regulator-always-on;
+        };
+};
+&gpmc {
+        ranges = <5 0 0x2c000000 0x1000000>;    /* CS5 */
+        ethernet@5,0 {
+                compatible = "smsc,lan9221", "smsc,lan9115";
+                reg = <5 0 0xff>;
+                bank-width = <2>;
+                gpmc,mux-add-data;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <42>;
+                gpmc,cs-wr-off-ns = <36>;
+                gpmc,adv-on-ns = <6>;
+                gpmc,adv-rd-off-ns = <12>;
+                gpmc,adv-wr-off-ns = <12>;
+                gpmc,oe-on-ns = <0>;
+                gpmc,oe-off-ns = <42>;
+                gpmc,we-on-ns = <0>;
+                gpmc,we-off-ns = <36>;
+                gpmc,rd-cycle-ns = <60>;
+                gpmc,wr-cycle-ns = <54>;
+                gpmc,access-ns = <36>;
+                gpmc,page-burst-access-ns = <0>;
+                gpmc,bus-turnaround-ns = <0>;
+                gpmc,cycle2cycle-delay-ns = <0>;
+                gpmc,wr-data-mux-bus-ns = <18>;
+                gpmc,wr-access-ns = <42>;
+                gpmc,cycle2cycle-samecsen;
+                gpmc,cycle2cycle-diffcsen;
+                interrupt-parent = <&gpio6>;
+                interrupts = <16 IRQ_TYPE_LEVEL_LOW>;   /* GPIO 176 */
+                reg-io-width = <4>;
+        };
 };
 &i2c3 {
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 99ba6e14ebf3..7d95cda1fae4 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -8,7 +8,11 @@
 * kind, whether express or implied.
 */
-/include/ "skeleton.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/omap.h>
+#include "skeleton.dtsi"
 / {
        compatible = "ti,omap3430", "ti,omap3";
@@ -21,8 +25,13 @@
        };
        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
                cpu@0 {
                        compatible = "arm,cortex-a8";
+                        device_type = "cpu";
+                        reg = <0x0>;
                };
        };
diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts
index 144ae43453c4..e2249bcc3e63 100644
--- a/arch/arm/boot/dts/omap3430-sdp.dts
+++ b/arch/arm/boot/dts/omap3430-sdp.dts
@@ -7,7 +7,7 @@
 */
 /dts-v1/;
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 / {
        model = "TI OMAP3430 SDP";
@@ -28,7 +28,8 @@
        };
 };
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
 &mmc1 {
        vmmc-supply = <&vmmc1>;
@@ -105,7 +106,6 @@
                nand-bus-width = <8>;
                ti,nand-ecc-opt = "sw";
-                gpmc,device-nand;
                gpmc,cs-on-ns = <0>;
                gpmc,cs-rd-off-ns = <36>;
                gpmc,cs-wr-off-ns = <36>;
diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
index 75ed4ae2e631..5355d6173748 100644
--- a/arch/arm/boot/dts/omap34xx.dtsi
+++ b/arch/arm/boot/dts/omap34xx.dtsi
@@ -8,7 +8,7 @@
 * kind, whether express or implied.
 */
-/include/ "omap3.dtsi"
+#include "omap3.dtsi"
 / {
        cpus {
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index f3447bc1b032..f8b3765eb9be 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -8,7 +8,7 @@
 * kind, whether express or implied.
 */
-/include/ "omap3.dtsi"
+#include "omap3.dtsi"
 / {
        aliases {
diff --git a/arch/arm/boot/dts/omap4-panda-a4.dts b/arch/arm/boot/dts/omap4-panda-a4.dts
index e30cdf0f5ac1..133f1b74e8ae 100644
--- a/arch/arm/boot/dts/omap4-panda-a4.dts
+++ b/arch/arm/boot/dts/omap4-panda-a4.dts
@@ -7,14 +7,14 @@
 */
 /dts-v1/;
-/include/ "omap443x.dtsi"
+#include "omap443x.dtsi"
-/include/ "omap4-panda-common.dtsi"
+#include "omap4-panda-common.dtsi"
 /* Pandaboard Rev A4+ have external pullups on SCL & SDA */
 &dss_hdmi_pins {
        pinctrl-single,pins = <
-                0x5a 0x118      /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
+                0x5a (PIN_INPUT_PULLUP | MUX_MODE0)     /* hdmi_cec.hdmi_cec */
-                0x5c 0x100      /* hdmi_scl.hdmi_scl INPUT | MODE 0 */
+                0x5c (PIN_INPUT | MUX_MODE0)            /* hdmi_scl.hdmi_scl */
-                0x5e 0x100      /* hdmi_sda.hdmi_sda INPUT | MODE 0 */
+                0x5e (PIN_INPUT | MUX_MODE0)            /* hdmi_sda.hdmi_sda */
                >;
 };
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index eeb734e25709..faa95b5b242e 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -5,7 +5,7 @@
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
-/include/ "elpida_ecb240abacn.dtsi"
+#include "elpida_ecb240abacn.dtsi"
 / {
        model = "TI OMAP4 PandaBoard";
@@ -16,17 +16,22 @@
                reg = <0x80000000 0x40000000>; /* 1 GB */
        };
-        leds {
+        leds: leds {
                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <
+                        &led_wkgpio_pins
+                >;
                heartbeat {
                        label = "pandaboard::status1";
-                        gpios = <&gpio1 7 0>;
+                        gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
                        linux,default-trigger = "heartbeat";
                };
                mmc {
                        label = "pandaboard::status2";
-                        gpios = <&gpio1 8 0>;
+                        gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
                        linux,default-trigger = "mmc0";
                };
        };
@@ -54,6 +59,54 @@
                        "AFML", "Line In",
                        "AFMR", "Line In";
        };
+        /*
+         * Temp hack: Need to be replaced with the proper gpio-controlled
+         * reset driver as soon it will be merged.
+         * http://thread.gmane.org/gmane.linux.drivers.devicetree/36830
+         */
+        /* HS USB Port 1 RESET */
+        hsusb1_reset: hsusb1_reset_reg {
+                compatible = "regulator-fixed";
+                regulator-name = "hsusb1_reset";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio2 30 0>;   /* gpio_62 */
+                startup-delay-us = <70000>;
+                enable-active-high;
+        };
+        /* HS USB Port 1 Power */
+        hsusb1_power: hsusb1_power_reg {
+                compatible = "regulator-fixed";
+                regulator-name = "hsusb1_vbus";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio1 1 0>;    /* gpio_1 */
+                startup-delay-us = <70000>;
+                enable-active-high;
+                /*
+                 * boot-on is required along with always-on as the
+                 * regulator framework doesn't enable the regulator
+                 * if boot-on is not there.
+                 */
+                regulator-always-on;
+                regulator-boot-on;
+        };
+        /* HS USB Host PHY on PORT 1 */
+        hsusb1_phy: hsusb1_phy {
+                compatible = "usb-nop-xceiv";
+                reset-supply = <&hsusb1_reset>;
+                vcc-supply = <&hsusb1_power>;
+        /**
+         * FIXME:
+         * put the right clock phandle here when available
+         *      clocks = <&auxclk3>;
+         *      clock-names = "main_clk";
+         */
+                clock-frequency = <19200000>;
+        };
 };
 &omap4_pmx_wkup {
@@ -64,7 +117,7 @@
        twl6030_wkup_pins: pinmux_twl6030_wkup_pins {
                pinctrl-single,pins = <
-                        0x14 0x2        /* fref_clk0_out.sys_drm_msecure OUTPUT | MODE2 */
+                        0x14 (PIN_OUTPUT | MUX_MODE2)           /* fref_clk0_out.sys_drm_msecure */
                >;
        };
 };
@@ -78,81 +131,108 @@
                        &mcbsp1_pins
                        &dss_hdmi_pins
                        &tpd12s015_pins
+                        &hsusbb1_pins
        >;
        twl6030_pins: pinmux_twl6030_pins {
                pinctrl-single,pins = <
-                        0x15e 0x4118    /* sys_nirq1.sys_nirq1 OMAP_WAKEUP_EN | INPUT_PULLUP | MODE0 */
+                        0x15e (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0)        /* sys_nirq1.sys_nirq1 */
                >;
        };
        twl6040_pins: pinmux_twl6040_pins {
                pinctrl-single,pins = <
-                        0xe0 0x3        /* hdq_sio.gpio_127 OUTPUT | MODE3 */
+                        0xe0 (PIN_OUTPUT | MUX_MODE3)   /* hdq_sio.gpio_127 */
-                        0x160 0x100     /* sys_nirq2.sys_nirq2 INPUT | MODE0 */
+                        0x160 (PIN_INPUT | MUX_MODE0)   /* sys_nirq2.sys_nirq2 */
                >;
        };
        mcpdm_pins: pinmux_mcpdm_pins {
                pinctrl-single,pins = <
-                        0xc6 0x108      /* abe_pdm_ul_data.abe_pdm_ul_data INPUT PULLDOWN | MODE0 */
+                        0xc6 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_pdm_ul_data.abe_pdm_ul_data */
-                        0xc8 0x108      /* abe_pdm_dl_data.abe_pdm_dl_data INPUT PULLDOWN | MODE0 */
+                        0xc8 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_pdm_dl_data.abe_pdm_dl_data */
-                        0xca 0x118      /* abe_pdm_frame.abe_pdm_frame INPUT PULLUP | MODE0 */
+                        0xca (PIN_INPUT_PULLUP   | MUX_MODE0)   /* abe_pdm_frame.abe_pdm_frame */
-                        0xcc 0x108      /* abe_pdm_lb_clk.abe_pdm_lb_clk INPUT PULLDOWN | MODE0 */
+                        0xcc (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_pdm_lb_clk.abe_pdm_lb_clk */
-                        0xce 0x108      /* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */
+                        0xce (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_clks.abe_clks */
                >;
        };
        mcbsp1_pins: pinmux_mcbsp1_pins {
                pinctrl-single,pins = <
-                        0xbe 0x100      /* abe_mcbsp1_clkx.abe_mcbsp1_clkx INPUT | MODE0 */
+                        0xbe (PIN_INPUT | MUX_MODE0)            /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */
-                        0xc0 0x108      /* abe_mcbsp1_dr.abe_mcbsp1_dr INPUT PULLDOWN | MODE0 */
+                        0xc0 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_mcbsp1_dr.abe_mcbsp1_dr */
-                        0xc2 0x8                /* abe_mcbsp1_dx.abe_mcbsp1_dx OUTPUT PULLDOWN | MODE0 */
+                        0xc2 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)  /* abe_mcbsp1_dx.abe_mcbsp1_dx */
-                        0xc4 0x100      /* abe_mcbsp1_fsx.abe_mcbsp1_fsx INPUT | MODE0 */
+                        0xc4 (PIN_INPUT | MUX_MODE0)            /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */
                >;
        };
        dss_hdmi_pins: pinmux_dss_hdmi_pins {
                pinctrl-single,pins = <
-                        0x5a 0x118      /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
+                        0x5a (PIN_INPUT_PULLUP | MUX_MODE0)     /* hdmi_cec.hdmi_cec */
-                        0x5c 0x118      /* hdmi_scl.hdmi_scl INPUT PULLUP | MODE 0 */
+                        0x5c (PIN_INPUT_PULLUP | MUX_MODE0)     /* hdmi_scl.hdmi_scl */
-                        0x5e 0x118      /* hdmi_sda.hdmi_sda INPUT PULLUP | MODE 0 */
+                        0x5e (PIN_INPUT_PULLUP | MUX_MODE0)     /* hdmi_sda.hdmi_sda */
                >;
        };
        tpd12s015_pins: pinmux_tpd12s015_pins {
                pinctrl-single,pins = <
-                        0x22 0x3        /* gpmc_a17.gpio_41 OUTPUT | MODE3 */
+                        0x22 (PIN_OUTPUT | MUX_MODE3)           /* gpmc_a17.gpio_41 */
-                        0x48 0x3        /* gpmc_nbe1.gpio_60 OUTPUT | MODE3 */
+                        0x48 (PIN_OUTPUT | MUX_MODE3)           /* gpmc_nbe1.gpio_60 */
-                        0x58 0x10b      /* hdmi_hpd.gpio_63 INPUT PULLDOWN | MODE3 */
+                        0x58 (PIN_INPUT_PULLDOWN | MUX_MODE3)   /* hdmi_hpd.gpio_63 */
+                >;
+        };
+        hsusbb1_pins: pinmux_hsusbb1_pins {
+                pinctrl-single,pins = <
+                        0x82 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */
+                        0x84 (PIN_OUTPUT | MUX_MODE4)           /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */
+                        0x86 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dir.usbb1_ulpiphy_dir */
+                        0x88 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_nxt.usbb1_ulpiphy_nxt */
+                        0x8a (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat0.usbb1_ulpiphy_dat0 */
+                        0x8c (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat1.usbb1_ulpiphy_dat1 */
+                        0x8e (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat2.usbb1_ulpiphy_dat2 */
+                        0x90 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat3.usbb1_ulpiphy_dat3 */
+                        0x92 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat4.usbb1_ulpiphy_dat4 */
+                        0x94 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat5.usbb1_ulpiphy_dat5 */
+                        0x96 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat6.usbb1_ulpiphy_dat6 */
+                        0x98 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat7.usbb1_ulpiphy_dat7 */
                >;
        };
        i2c1_pins: pinmux_i2c1_pins {
                pinctrl-single,pins = <
-                        0xe2 0x118        /* i2c1_scl PULLUP | INPUTENABLE | MODE0 */
+                        0xe2 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c1_scl */
-                        0xe4 0x118        /* i2c1_sda PULLUP | INPUTENABLE | MODE0 */
+                        0xe4 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c1_sda */
                >;
        };
        i2c2_pins: pinmux_i2c2_pins {
                pinctrl-single,pins = <
-                        0xe6 0x118        /* i2c2_scl PULLUP | INPUTENABLE | MODE0 */
+                        0xe6 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c2_scl */
-                        0xe8 0x118        /* i2c2_sda PULLUP | INPUTENABLE | MODE0 */
+                        0xe8 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c2_sda */
                >;
        };
        i2c3_pins: pinmux_i2c3_pins {
                pinctrl-single,pins = <
-                        0xea 0x118        /* i2c3_scl PULLUP | INPUTENABLE | MODE0 */
+                        0xea (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c3_scl */
-                        0xec 0x118     /* i2c3_sda PULLUP | INPUTENABLE | MODE0 */
+                        0xec (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c3_sda */
                >;
        };
        i2c4_pins: pinmux_i2c4_pins {
                pinctrl-single,pins = <
-                        0xee 0x118        /* i2c4_scl PULLUP | INPUTENABLE | MODE0 */
+                        0xee (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c4_scl */
-                        0xf0 0x118     /* i2c4_sda PULLUP | INPUTENABLE | MODE0 */
+                        0xf0 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c4_sda */
+                >;
+        };
+};
+&omap4_pmx_wkup {
+        led_wkgpio_pins: pinmux_leds_wkpins {
+                pinctrl-single,pins = <
+                        0x1a (PIN_OUTPUT | MUX_MODE3)   /* gpio_wk7 */
+                        0x1c (PIN_OUTPUT | MUX_MODE3)   /* gpio_wk8 */
                >;
        };
 };
@@ -165,18 +245,18 @@
        twl: twl@48 {
                reg = <0x48>;
-                /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
+                /* IRQ# = 7 */
-                interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
+                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
                interrupt-parent = <&gic>;
        };
        twl6040: twl@4b {
                compatible = "ti,twl6040";
                reg = <0x4b>;
-                /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
+                /* IRQ# = 119 */
-                interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */
+                interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
                interrupt-parent = <&gic>;
-                ti,audpwron-gpio = <&gpio4 31 0>;  /* gpio line 127 */
+                ti,audpwron-gpio = <&gpio4 31 GPIO_ACTIVE_HIGH>;  /* gpio line 127 */
                vio-supply = <&v1v8>;
                v2v1-supply = <&v2v1>;
@@ -184,7 +264,7 @@
        };
 };
-/include/ "twl6030.dtsi"
+#include "twl6030.dtsi"
 &i2c2 {
        pinctrl-names = "default";
@@ -269,3 +349,11 @@
        mode = <3>;
        power = <50>;
 };
+&usbhshost {
+        port1-mode = "ehci-phy";
+};
+&usbhsehci {
+        phys = <&hsusb1_phy>;
+};
diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
index f1d8c217ce12..56c435468e94 100644
--- a/arch/arm/boot/dts/omap4-panda-es.dts
+++ b/arch/arm/boot/dts/omap4-panda-es.dts
@@ -7,8 +7,8 @@
 */
 /dts-v1/;
-/include/ "omap4460.dtsi"
+#include "omap4460.dtsi"
-/include/ "omap4-panda-common.dtsi"
+#include "omap4-panda-common.dtsi"
 /* Audio routing is differnet between PandaBoard4430 and PandaBoardES */
 &sound {
@@ -29,8 +29,36 @@
 /* PandaboardES has external pullups on SCL & SDA */
 &dss_hdmi_pins {
        pinctrl-single,pins = <
-                0x5a 0x118      /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
+                0x5a (PIN_INPUT_PULLUP | MUX_MODE0)     /* hdmi_cec.hdmi_cec */
-                0x5c 0x100      /* hdmi_scl.hdmi_scl INPUT | MODE 0 */
+                0x5c (PIN_INPUT | MUX_MODE0)            /* hdmi_scl.hdmi_scl */
-                0x5e 0x100      /* hdmi_sda.hdmi_sda INPUT | MODE 0 */
+                0x5e (PIN_INPUT | MUX_MODE0)            /* hdmi_sda.hdmi_sda */
                >;
 };
+&omap4_pmx_core {
+        led_gpio_pins: gpio_led_pmx {
+                pinctrl-single,pins = <
+                        0xb6 (PIN_OUTPUT | MUX_MODE3)   /* gpio_110 */
+                >;
+        };
+};
+&led_wkgpio_pins {
+        pinctrl-single,pins = <
+                0x1c (PIN_OUTPUT | MUX_MODE3)   /* gpio_wk8 */
+        >;
+};
+&leds {
+        pinctrl-0 = <
+                &led_gpio_pins
+                &led_wkgpio_pins
+        >;
+        heartbeat {
+                gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>;
+        };
+        mmc {
+                gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index f8b221f0168e..6189a8b77d7f 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -7,5 +7,5 @@
 */
 /dts-v1/;
-/include/ "omap443x.dtsi"
+#include "omap443x.dtsi"
-/include/ "omap4-panda-common.dtsi"
+#include "omap4-panda-common.dtsi"
diff --git a/arch/arm/boot/dts/omap4-sdp-es23plus.dts b/arch/arm/boot/dts/omap4-sdp-es23plus.dts
index b4a40ffbce31..aad5dda0f469 100644
--- a/arch/arm/boot/dts/omap4-sdp-es23plus.dts
+++ b/arch/arm/boot/dts/omap4-sdp-es23plus.dts
@@ -5,13 +5,13 @@
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
-/include/ "omap4-sdp.dts"
+#include "omap4-sdp.dts"
 /* SDP boards with 4430 ES2.3+ or 4460 have external pullups on SCL & SDA */
 &dss_hdmi_pins {
        pinctrl-single,pins = <
-                0x5a 0x118      /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
+                0x5a (PIN_INPUT_PULLUP | MUX_MODE0)     /* hdmi_cec.hdmi_cec */
-                0x5c 0x100      /* hdmi_scl.hdmi_scl INPUT | MODE 0 */
+                0x5c (PIN_INPUT | MUX_MODE0)            /* hdmi_scl.hdmi_scl */
-                0x5e 0x100      /* hdmi_sda.hdmi_sda INPUT | MODE 0 */
+                0x5e (PIN_INPUT | MUX_MODE0)            /* hdmi_sda.hdmi_sda */
                >;
 };
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 98505a2ef162..7951b4ea500a 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -7,8 +7,8 @@
 */
 /dts-v1/;
-/include/ "omap443x.dtsi"
+#include "omap443x.dtsi"
-/include/ "elpida_ecb240abacn.dtsi"
+#include "elpida_ecb240abacn.dtsi"
 / {
        model = "TI OMAP4 SDP board";
@@ -41,42 +41,42 @@
                compatible = "gpio-leds";
                debug0 {
                        label = "omap4:green:debug0";
-                        gpios = <&gpio2 29 0>; /* 61 */
+                        gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; /* 61 */
                };
                debug1 {
                        label = "omap4:green:debug1";
-                        gpios = <&gpio1 30 0>; /* 30 */
+                        gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; /* 30 */
                };
                debug2 {
                        label = "omap4:green:debug2";
-                        gpios = <&gpio1 7 0>; /* 7 */
+                        gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; /* 7 */
                };
                debug3 {
                        label = "omap4:green:debug3";
-                        gpios = <&gpio1 8 0>; /* 8 */
+                        gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; /* 8 */
                };
                debug4 {
                        label = "omap4:green:debug4";
-                        gpios = <&gpio2 18 0>; /* 50 */
+                        gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; /* 50 */
                };
                user1 {
                        label = "omap4:blue:user";
-                        gpios = <&gpio6 9 0>; /* 169 */
+                        gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* 169 */
                };
                user2 {
                        label = "omap4:red:user";
-                        gpios = <&gpio6 10 0>; /* 170 */
+                        gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; /* 170 */
                };
                user3 {
                        label = "omap4:green:user";
-                        gpios = <&gpio5 11 0>; /* 139 */
+                        gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* 139 */
                };
        };
@@ -150,7 +150,7 @@
        twl6030_wkup_pins: pinmux_twl6030_wkup_pins {
                pinctrl-single,pins = <
-                        0x14 0x2        /* fref_clk0_out.sys_drm_msecure OUTPUT | MODE2 */
+                        0x14 (PIN_OUTPUT | MUX_MODE2)           /* fref_clk0_out.sys_drm_msecure */
                >;
        };
 };
@@ -170,129 +170,129 @@
        uart2_pins: pinmux_uart2_pins {
                pinctrl-single,pins = <
-                        0xd8 0x118      /* uart2_cts.uart2_cts INPUT_PULLUP | MODE0 */
+                        0xd8 (PIN_INPUT_PULLUP | MUX_MODE0)     /* uart2_cts.uart2_cts */
-                        0xda 0          /* uart2_rts.uart2_rts OUTPUT | MODE0 */
+                        0xda (PIN_OUTPUT | MUX_MODE0)           /* uart2_rts.uart2_rts */
-                        0xdc 0x118      /* uart2_rx.uart2_rx INPUT_PULLUP | MODE0 */
+                        0xdc (PIN_INPUT_PULLUP | MUX_MODE0)     /* uart2_rx.uart2_rx */
-                        0xde 0          /* uart2_tx.uart2_tx OUTPUT | MODE0 */
+                        0xde (PIN_OUTPUT | MUX_MODE0)           /* uart2_tx.uart2_tx */
                >;
        };
        uart3_pins: pinmux_uart3_pins {
                pinctrl-single,pins = <
-                        0x100 0x118     /* uart3_cts_rctx.uart3_cts_rctx INPUT_PULLUP | MODE0 */
+                        0x100 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart3_cts_rctx.uart3_cts_rctx */
-                        0x102 0         /* uart3_rts_sd.uart3_rts_sd OUTPUT | MODE0 */
+                        0x102 (PIN_OUTPUT | MUX_MODE0)          /* uart3_rts_sd.uart3_rts_sd */
-                        0x104 0x100     /* uart3_rx_irrx.uart3_rx_irrx INPUT | MODE0 */
+                        0x104 (PIN_INPUT | MUX_MODE0)           /* uart3_rx_irrx.uart3_rx_irrx */
-                        0x106 0         /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */
+                        0x106 (PIN_OUTPUT | MUX_MODE0)          /* uart3_tx_irtx.uart3_tx_irtx */
                >;
        };
        uart4_pins: pinmux_uart4_pins {
                pinctrl-single,pins = <
-                        0x11c 0x100     /* uart4_rx.uart4_rx INPUT | MODE0 */
+                        0x11c (PIN_INPUT | MUX_MODE0)           /* uart4_rx.uart4_rx */
-                        0x11e 0         /* uart4_tx.uart4_tx OUTPUT | MODE0 */
+                        0x11e (PIN_OUTPUT | MUX_MODE0)          /* uart4_tx.uart4_tx */
                >;
        };
        twl6030_pins: pinmux_twl6030_pins {
                pinctrl-single,pins = <
-                        0x15e 0x4118    /* sys_nirq1.sys_nirq1 OMAP_WAKEUP_EN | INPUT_PULLUP | MODE0 */
+                        0x15e (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0)        /* sys_nirq1.sys_nirq1 */
                >;
        };
        twl6040_pins: pinmux_twl6040_pins {
                pinctrl-single,pins = <
-                        0xe0 0x3        /* hdq_sio.gpio_127 OUTPUT | MODE3 */
+                        0xe0 (PIN_OUTPUT | MUX_MODE3)           /* hdq_sio.gpio_127 */
-                        0x160 0x100     /* sys_nirq2.sys_nirq2 INPUT | MODE0 */
+                        0x160 (PIN_INPUT | MUX_MODE0)           /* sys_nirq2.sys_nirq2 */
                >;
        };
        mcpdm_pins: pinmux_mcpdm_pins {
                pinctrl-single,pins = <
-                        0xc6 0x108      /* abe_pdm_ul_data.abe_pdm_ul_data INPUT PULLDOWN | MODE0 */
+                        0xc6 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_pdm_ul_data.abe_pdm_ul_data */
-                        0xc8 0x108      /* abe_pdm_dl_data.abe_pdm_dl_data INPUT PULLDOWN | MODE0 */
+                        0xc8 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_pdm_dl_data.abe_pdm_dl_data */
-                        0xca 0x118      /* abe_pdm_frame.abe_pdm_frame INPUT PULLUP | MODE0 */
+                        0xca (PIN_INPUT_PULLUP | MUX_MODE0)     /* abe_pdm_frame.abe_pdm_frame */
-                        0xcc 0x108      /* abe_pdm_lb_clk.abe_pdm_lb_clk INPUT PULLDOWN | MODE0 */
+                        0xcc (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_pdm_lb_clk.abe_pdm_lb_clk */
-                        0xce 0x108      /* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */
+                        0xce (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_clks.abe_clks */
                >;
        };
        dmic_pins: pinmux_dmic_pins {
                pinctrl-single,pins = <
-                        0xd0 0          /* abe_dmic_clk1.abe_dmic_clk1 OUTPUT | MODE0 */
+                        0xd0 (PIN_OUTPUT | MUX_MODE0)           /* abe_dmic_clk1.abe_dmic_clk1 */
-                        0xd2 0x100      /* abe_dmic_din1.abe_dmic_din1 INPUT | MODE0 */
+                        0xd2 (PIN_INPUT | MUX_MODE0)            /* abe_dmic_din1.abe_dmic_din1 */
-                        0xd4 0x100      /* abe_dmic_din2.abe_dmic_din2 INPUT | MODE0 */
+                        0xd4 (PIN_INPUT | MUX_MODE0)            /* abe_dmic_din2.abe_dmic_din2 */
-                        0xd6 0x100      /* abe_dmic_din3.abe_dmic_din3 INPUT | MODE0 */
+                        0xd6 (PIN_INPUT | MUX_MODE0)            /* abe_dmic_din3.abe_dmic_din3 */
                >;
        };
        mcbsp1_pins: pinmux_mcbsp1_pins {
                pinctrl-single,pins = <
-                        0xbe 0x100      /* abe_mcbsp1_clkx.abe_mcbsp1_clkx INPUT | MODE0 */
+                        0xbe (PIN_INPUT | MUX_MODE0)            /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */
-                        0xc0 0x108      /* abe_mcbsp1_dr.abe_mcbsp1_dr INPUT PULLDOWN | MODE0 */
+                        0xc0 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_mcbsp1_dr.abe_mcbsp1_dr */
-                        0xc2 0x8        /* abe_mcbsp1_dx.abe_mcbsp1_dx OUTPUT PULLDOWN | MODE0 */
+                        0xc2 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)  /* abe_mcbsp1_dx.abe_mcbsp1_dx */
-                        0xc4 0x100      /* abe_mcbsp1_fsx.abe_mcbsp1_fsx INPUT | MODE0 */
+                        0xc4 (PIN_INPUT | MUX_MODE0)            /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */
                >;
        };
        mcbsp2_pins: pinmux_mcbsp2_pins {
                pinctrl-single,pins = <
-                        0xb6 0x100      /* abe_mcbsp2_clkx.abe_mcbsp2_clkx INPUT | MODE0 */
+                        0xb6 (PIN_INPUT | MUX_MODE0)            /* abe_mcbsp2_clkx.abe_mcbsp2_clkx */
-                        0xb8 0x108      /* abe_mcbsp2_dr.abe_mcbsp2_dr INPUT PULLDOWN | MODE0 */
+                        0xb8 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_mcbsp2_dr.abe_mcbsp2_dr */
-                        0xba 0x8        /* abe_mcbsp2_dx.abe_mcbsp2_dx OUTPUT PULLDOWN | MODE0 */
+                        0xba (PIN_OUTPUT_PULLDOWN | MUX_MODE0)  /* abe_mcbsp2_dx.abe_mcbsp2_dx */
-                        0xbc 0x100      /* abe_mcbsp2_fsx.abe_mcbsp2_fsx INPUT | MODE0 */
+                        0xbc (PIN_INPUT | MUX_MODE0)            /* abe_mcbsp2_fsx.abe_mcbsp2_fsx */
                >;
        };
        mcspi1_pins: pinmux_mcspi1_pins {
                pinctrl-single,pins = <
-                        0xf2 0x100      /*  mcspi1_clk.mcspi1_clk INPUT | MODE0 */
+                        0xf2 (PIN_INPUT | MUX_MODE0)            /*  mcspi1_clk.mcspi1_clk */
-                        0xf4 0x100      /*  mcspi1_somi.mcspi1_somi INPUT | MODE0 */
+                        0xf4 (PIN_INPUT | MUX_MODE0)            /*  mcspi1_somi.mcspi1_somi */
-                        0xf6 0x100      /*  mcspi1_simo.mcspi1_simo INPUT | MODE0 */
+                        0xf6 (PIN_INPUT | MUX_MODE0)            /*  mcspi1_simo.mcspi1_simo */
-                        0xf8 0x100      /*  mcspi1_cs0.mcspi1_cs0 INPUT | MODE0*/
+                        0xf8 (PIN_INPUT | MUX_MODE0)            /*  mcspi1_cs0.mcspi1_cs0 */
                >;
        };
        dss_hdmi_pins: pinmux_dss_hdmi_pins {
                pinctrl-single,pins = <
-                        0x5a 0x118      /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
+                        0x5a (PIN_INPUT_PULLUP | MUX_MODE0)     /* hdmi_cec.hdmi_cec */
-                        0x5c 0x118      /* hdmi_scl.hdmi_scl INPUT PULLUP | MODE 0 */
+                        0x5c (PIN_INPUT_PULLUP | MUX_MODE0)     /* hdmi_scl.hdmi_scl */
-                        0x5e 0x118      /* hdmi_sda.hdmi_sda INPUT PULLUP | MODE 0 */
+                        0x5e (PIN_INPUT_PULLUP | MUX_MODE0)     /* hdmi_sda.hdmi_sda */
                >;
        };
        tpd12s015_pins: pinmux_tpd12s015_pins {
                pinctrl-single,pins = <
-                        0x22 0x3        /* gpmc_a17.gpio_41 OUTPUT | MODE3 */
+                        0x22 (PIN_OUTPUT | MUX_MODE3)           /* gpmc_a17.gpio_41 */
-                        0x48 0x3        /* gpmc_nbe1.gpio_60 OUTPUT | MODE3 */
+                        0x48 (PIN_OUTPUT | MUX_MODE3)           /* gpmc_nbe1.gpio_60 */
-                        0x58 0x10b      /* hdmi_hpd.gpio_63 INPUT PULLDOWN | MODE3 */
+                        0x58 (PIN_INPUT_PULLDOWN | MUX_MODE3)   /* hdmi_hpd.gpio_63 */
                >;
        };
        i2c1_pins: pinmux_i2c1_pins {
                pinctrl-single,pins = <
-                        0xe2 0x118        /* i2c1_scl PULLUP | INPUTENABLE | MODE0 */
+                        0xe2 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c1_scl */
-                        0xe4 0x118       /* i2c1_sda PULLUP | INPUTENABLE | MODE0 */
+                        0xe4 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c1_sda */
                >;
        };
        i2c2_pins: pinmux_i2c2_pins {
                pinctrl-single,pins = <
-                        0xe6 0x118        /* i2c2_scl PULLUP | INPUTENABLE | MODE0 */
+                        0xe6 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c2_scl */
-                        0xe8 0x118        /* i2c2_sda PULLUP | INPUTENABLE | MODE0 */
+                        0xe8 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c2_sda */
                >;
        };
        i2c3_pins: pinmux_i2c3_pins {
                pinctrl-single,pins = <
-                        0xea 0x118        /* i2c3_scl PULLUP | INPUTENABLE | MODE0 */
+                        0xea (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c3_scl */
-                        0xec 0x118     /* i2c3_sda PULLUP | INPUTENABLE | MODE0 */
+                        0xec (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c3_sda */
                >;
        };
        i2c4_pins: pinmux_i2c4_pins {
                pinctrl-single,pins = <
-                        0xee 0x118        /* i2c4_scl PULLUP | INPUTENABLE | MODE0 */
+                        0xee (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c4_scl */
-                        0xf0 0x118     /* i2c4_sda PULLUP | INPUTENABLE | MODE0 */
+                        0xf0 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c4_sda */
                >;
        };
 };
@@ -306,7 +306,7 @@
        twl: twl@48 {
                reg = <0x48>;
                /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
-                interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
+                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
                interrupt-parent = <&gic>;
        };
@@ -314,7 +314,7 @@
                compatible = "ti,twl6040";
                reg = <0x4b>;
                /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
-                interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */
+                interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
                interrupt-parent = <&gic>;
                ti,audpwron-gpio = <&gpio4 31 0>;  /* gpio line 127 */
@@ -336,7 +336,7 @@
        };
 };
-/include/ "twl6030.dtsi"
+#include "twl6030.dtsi"
 &i2c2 {
        pinctrl-names = "default";
@@ -395,7 +395,7 @@
                spi-max-frequency = <24000000>;
                reg = <0>;
                interrupt-parent = <&gpio2>;
-                interrupts = <2 8>; /* gpio line 34, low triggered */
+                interrupts = <2 IRQ_TYPE_LEVEL_LOW>; /* gpio line 34 */
                vdd-supply = <&vdd_eth>;
        };
 };
diff --git a/arch/arm/boot/dts/omap4-var-som.dts b/arch/arm/boot/dts/omap4-var-som.dts
index 7e04103779c4..b41269e871dd 100644
--- a/arch/arm/boot/dts/omap4-var-som.dts
+++ b/arch/arm/boot/dts/omap4-var-som.dts
@@ -7,7 +7,7 @@
 */
 /dts-v1/;
-/include/ "omap443x.dtsi"
+#include "omap443x.dtsi"
 / {
        model = "Variscite OMAP4 SOM";
@@ -34,12 +34,12 @@
        twl: twl@48 {
                reg = <0x48>;
                /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
-                interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
+                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
                interrupt-parent = <&gic>;
        };
 };
-/include/ "twl6030.dtsi"
+#include "twl6030.dtsi"
 &i2c2 {
        clock-frequency = <400000>;
@@ -68,7 +68,7 @@
                spi-max-frequency = <24000000>;
                reg = <0>;
                interrupt-parent = <&gpio6>;
-                interrupts = <11 8>; /* gpio line 171, low triggered */
+                interrupts = <11 IRQ_TYPE_LEVEL_LOW>; /* gpio line 171 */
                vdd-supply = <&vdd_eth>;
        };
 };
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 2a5642882c8a..22d9f2b593d4 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -6,15 +6,11 @@
 * published by the Free Software Foundation.
 */
-/*
+#include <dt-bindings/gpio/gpio.h>
- * Carveout for multimedia usecases
+#include <dt-bindings/interrupt-controller/arm-gic.h>
- * It should be the last 48MB of the first 512MB memory part
+#include <dt-bindings/pinctrl/omap.h>
- * In theory, it should not even exist. That zone should be reserved
- * dynamically during the .reserve callback.
- */
-/memreserve/ 0x9d000000 0x03000000;
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 / {
        compatible = "ti,omap4430", "ti,omap4";
@@ -28,13 +24,20 @@
        };
        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
                cpu@0 {
                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
                        next-level-cache = <&L2>;
+                        reg = <0x0>;
                };
                cpu@1 {
                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
                        next-level-cache = <&L2>;
+                        reg = <0x1>;
                };
        };
@@ -56,7 +59,7 @@
        local-timer@0x48240600 {
                compatible = "arm,cortex-a9-twd-timer";
                reg = <0x48240600 0x20>;
-                interrupts = <1 13 0x304>;
+                interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
        };
        /*
@@ -97,8 +100,8 @@
                reg = <0x44000000 0x1000>,
                      <0x44800000 0x2000>,
                      <0x45000000 0x1000>;
-                interrupts = <0 9 0x4>,
+                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
-                             <0 10 0x4>;
+                             <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
                counter32k: counter@4a304000 {
                        compatible = "ti,omap-counter32k";
@@ -126,10 +129,10 @@
                sdma: dma-controller@4a056000 {
                        compatible = "ti,omap4430-sdma";
                        reg = <0x4a056000 0x1000>;
-                        interrupts = <0 12 0x4>,
+                        interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
-                                     <0 13 0x4>,
+                                     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
-                                     <0 14 0x4>,
+                                     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
-                                     <0 15 0x4>;
+                                     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
                        #dma-cells = <1>;
                        #dma-channels = <32>;
                        #dma-requests = <127>;
@@ -138,7 +141,7 @@
                gpio1: gpio@4a310000 {
                        compatible = "ti,omap4-gpio";
                        reg = <0x4a310000 0x200>;
-                        interrupts = <0 29 0x4>;
+                        interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "gpio1";
                        ti,gpio-always-on;
                        gpio-controller;
@@ -150,7 +153,7 @@
                gpio2: gpio@48055000 {
                        compatible = "ti,omap4-gpio";
                        reg = <0x48055000 0x200>;
-                        interrupts = <0 30 0x4>;
+                        interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "gpio2";
                        gpio-controller;
                        #gpio-cells = <2>;
@@ -161,7 +164,7 @@
                gpio3: gpio@48057000 {
                        compatible = "ti,omap4-gpio";
                        reg = <0x48057000 0x200>;
-                        interrupts = <0 31 0x4>;
+                        interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "gpio3";
                        gpio-controller;
                        #gpio-cells = <2>;
@@ -172,7 +175,7 @@
                gpio4: gpio@48059000 {
                        compatible = "ti,omap4-gpio";
                        reg = <0x48059000 0x200>;
-                        interrupts = <0 32 0x4>;
+                        interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "gpio4";
                        gpio-controller;
                        #gpio-cells = <2>;
@@ -183,7 +186,7 @@
                gpio5: gpio@4805b000 {
                        compatible = "ti,omap4-gpio";
                        reg = <0x4805b000 0x200>;
-                        interrupts = <0 33 0x4>;
+                        interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "gpio5";
                        gpio-controller;
                        #gpio-cells = <2>;
@@ -194,7 +197,7 @@
                gpio6: gpio@4805d000 {
                        compatible = "ti,omap4-gpio";
                        reg = <0x4805d000 0x200>;
-                        interrupts = <0 34 0x4>;
+                        interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "gpio6";
                        gpio-controller;
                        #gpio-cells = <2>;
@@ -207,7 +210,7 @@
                        reg = <0x50000000 0x1000>;
                        #address-cells = <2>;
                        #size-cells = <1>;
-                        interrupts = <0 20 0x4>;
+                        interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
                        gpmc,num-cs = <8>;
                        gpmc,num-waitpins = <4>;
                        ti,hwmods = "gpmc";
@@ -216,7 +219,7 @@
                uart1: serial@4806a000 {
                        compatible = "ti,omap4-uart";
                        reg = <0x4806a000 0x100>;
-                        interrupts = <0 72 0x4>;
+                        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "uart1";
                        clock-frequency = <48000000>;
                };
@@ -224,7 +227,7 @@
                uart2: serial@4806c000 {
                        compatible = "ti,omap4-uart";
                        reg = <0x4806c000 0x100>;
-                        interrupts = <0 73 0x4>;
+                        interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "uart2";
                        clock-frequency = <48000000>;
                };
@@ -232,7 +235,7 @@
                uart3: serial@48020000 {
                        compatible = "ti,omap4-uart";
                        reg = <0x48020000 0x100>;
-                        interrupts = <0 74 0x4>;
+                        interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "uart3";
                        clock-frequency = <48000000>;
                };
@@ -240,7 +243,7 @@
                uart4: serial@4806e000 {
                        compatible = "ti,omap4-uart";
                        reg = <0x4806e000 0x100>;
-                        interrupts = <0 70 0x4>;
+                        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "uart4";
                        clock-frequency = <48000000>;
                };
@@ -248,7 +251,7 @@
                i2c1: i2c@48070000 {
                        compatible = "ti,omap4-i2c";
                        reg = <0x48070000 0x100>;
-                        interrupts = <0 56 0x4>;
+                        interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        ti,hwmods = "i2c1";
@@ -257,7 +260,7 @@
                i2c2: i2c@48072000 {
                        compatible = "ti,omap4-i2c";
                        reg = <0x48072000 0x100>;
-                        interrupts = <0 57 0x4>;
+                        interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        ti,hwmods = "i2c2";
@@ -266,7 +269,7 @@
                i2c3: i2c@48060000 {
                        compatible = "ti,omap4-i2c";
                        reg = <0x48060000 0x100>;
-                        interrupts = <0 61 0x4>;
+                        interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        ti,hwmods = "i2c3";
@@ -275,7 +278,7 @@
                i2c4: i2c@48350000 {
                        compatible = "ti,omap4-i2c";
                        reg = <0x48350000 0x100>;
-                        interrupts = <0 62 0x4>;
+                        interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        ti,hwmods = "i2c4";
@@ -284,7 +287,7 @@
                mcspi1: spi@48098000 {
                        compatible = "ti,omap4-mcspi";
                        reg = <0x48098000 0x200>;
-                        interrupts = <0 65 0x4>;
+                        interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        ti,hwmods = "mcspi1";
@@ -304,7 +307,7 @@
                mcspi2: spi@4809a000 {
                        compatible = "ti,omap4-mcspi";
                        reg = <0x4809a000 0x200>;
-                        interrupts = <0 66 0x4>;
+                        interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        ti,hwmods = "mcspi2";
@@ -319,7 +322,7 @@
                mcspi3: spi@480b8000 {
                        compatible = "ti,omap4-mcspi";
                        reg = <0x480b8000 0x200>;
-                        interrupts = <0 91 0x4>;
+                        interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        ti,hwmods = "mcspi3";
@@ -331,7 +334,7 @@
                mcspi4: spi@480ba000 {
                        compatible = "ti,omap4-mcspi";
                        reg = <0x480ba000 0x200>;
-                        interrupts = <0 48 0x4>;
+                        interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        ti,hwmods = "mcspi4";
@@ -343,7 +346,7 @@
                mmc1: mmc@4809c000 {
                        compatible = "ti,omap4-hsmmc";
                        reg = <0x4809c000 0x400>;
-                        interrupts = <0 83 0x4>;
+                        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "mmc1";
                        ti,dual-volt;
                        ti,needs-special-reset;
@@ -354,7 +357,7 @@
                mmc2: mmc@480b4000 {
                        compatible = "ti,omap4-hsmmc";
                        reg = <0x480b4000 0x400>;
-                        interrupts = <0 86 0x4>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "mmc2";
                        ti,needs-special-reset;
                        dmas = <&sdma 47>, <&sdma 48>;
@@ -364,7 +367,7 @@
                mmc3: mmc@480ad000 {
                        compatible = "ti,omap4-hsmmc";
                        reg = <0x480ad000 0x400>;
-                        interrupts = <0 94 0x4>;
+                        interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "mmc3";
                        ti,needs-special-reset;
                        dmas = <&sdma 77>, <&sdma 78>;
@@ -374,7 +377,7 @@
                mmc4: mmc@480d1000 {
                        compatible = "ti,omap4-hsmmc";
                        reg = <0x480d1000 0x400>;
-                        interrupts = <0 96 0x4>;
+                        interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "mmc4";
                        ti,needs-special-reset;
                        dmas = <&sdma 57>, <&sdma 58>;
@@ -384,7 +387,7 @@
                mmc5: mmc@480d5000 {
                        compatible = "ti,omap4-hsmmc";
                        reg = <0x480d5000 0x400>;
-                        interrupts = <0 59 0x4>;
+                        interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "mmc5";
                        ti,needs-special-reset;
                        dmas = <&sdma 59>, <&sdma 60>;
@@ -394,7 +397,7 @@
                wdt2: wdt@4a314000 {
                        compatible = "ti,omap4-wdt", "ti,omap3-wdt";
                        reg = <0x4a314000 0x80>;
-                        interrupts = <0 80 0x4>;
+                        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "wd_timer2";
                };
@@ -403,7 +406,7 @@
                        reg = <0x40132000 0x7f>, /* MPU private access */
                              <0x49032000 0x7f>; /* L3 Interconnect */
                        reg-names = "mpu", "dma";
-                        interrupts = <0 112 0x4>;
+                        interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "mcpdm";
                        dmas = <&sdma 65>,
                               <&sdma 66>;
@@ -415,7 +418,7 @@
                        reg = <0x4012e000 0x7f>, /* MPU private access */
                              <0x4902e000 0x7f>; /* L3 Interconnect */
                        reg-names = "mpu", "dma";
-                        interrupts = <0 114 0x4>;
+                        interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "dmic";
                        dmas = <&sdma 67>;
                        dma-names = "up_link";
@@ -426,7 +429,7 @@
                        reg = <0x40122000 0xff>, /* MPU private access */
                              <0x49022000 0xff>; /* L3 Interconnect */
                        reg-names = "mpu", "dma";
-                        interrupts = <0 17 0x4>;
+                        interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "common";
                        ti,buffer-size = <128>;
                        ti,hwmods = "mcbsp1";
@@ -440,7 +443,7 @@
                        reg = <0x40124000 0xff>, /* MPU private access */
                              <0x49024000 0xff>; /* L3 Interconnect */
                        reg-names = "mpu", "dma";
-                        interrupts = <0 22 0x4>;
+                        interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "common";
                        ti,buffer-size = <128>;
                        ti,hwmods = "mcbsp2";
@@ -454,7 +457,7 @@
                        reg = <0x40126000 0xff>, /* MPU private access */
                              <0x49026000 0xff>; /* L3 Interconnect */
                        reg-names = "mpu", "dma";
-                        interrupts = <0 23 0x4>;
+                        interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "common";
                        ti,buffer-size = <128>;
                        ti,hwmods = "mcbsp3";
@@ -467,7 +470,7 @@
                        compatible = "ti,omap4-mcbsp";
                        reg = <0x48096000 0xff>; /* L4 Interconnect */
                        reg-names = "mpu";
-                        interrupts = <0 16 0x4>;
+                        interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "common";
                        ti,buffer-size = <128>;
                        ti,hwmods = "mcbsp4";
@@ -479,7 +482,7 @@
                keypad: keypad@4a31c000 {
                        compatible = "ti,omap4-keypad";
                        reg = <0x4a31c000 0x80>;
-                        interrupts = <0 120 0x4>;
+                        interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
                        reg-names = "mpu";
                        ti,hwmods = "kbd";
                };
@@ -487,7 +490,7 @@
                emif1: emif@4c000000 {
                        compatible = "ti,emif-4d";
                        reg = <0x4c000000 0x100>;
-                        interrupts = <0 110 0x4>;
+                        interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "emif1";
                        phy-type = <1>;
                        hw-caps-read-idle-ctrl;
@@ -498,7 +501,7 @@
                emif2: emif@4d000000 {
                        compatible = "ti,emif-4d";
                        reg = <0x4d000000 0x100>;
-                        interrupts = <0 111 0x4>;
+                        interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "emif2";
                        phy-type = <1>;
                        hw-caps-read-idle-ctrl;
@@ -523,7 +526,7 @@
                timer1: timer@4a318000 {
                        compatible = "ti,omap3430-timer";
                        reg = <0x4a318000 0x80>;
-                        interrupts = <0 37 0x4>;
+                        interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "timer1";
                        ti,timer-alwon;
                };
@@ -531,21 +534,21 @@
                timer2: timer@48032000 {
                        compatible = "ti,omap3430-timer";
                        reg = <0x48032000 0x80>;
-                        interrupts = <0 38 0x4>;
+                        interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "timer2";
                };
                timer3: timer@48034000 {
                        compatible = "ti,omap4430-timer";
                        reg = <0x48034000 0x80>;
-                        interrupts = <0 39 0x4>;
+                        interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "timer3";
                };
                timer4: timer@48036000 {
                        compatible = "ti,omap4430-timer";
                        reg = <0x48036000 0x80>;
-                        interrupts = <0 40 0x4>;
+                        interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "timer4";
                };
@@ -553,7 +556,7 @@
                        compatible = "ti,omap4430-timer";
                        reg = <0x40138000 0x80>,
                              <0x49038000 0x80>;
-                        interrupts = <0 41 0x4>;
+                        interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "timer5";
                        ti,timer-dsp;
                };
@@ -562,7 +565,7 @@
                        compatible = "ti,omap4430-timer";
                        reg = <0x4013a000 0x80>,
                              <0x4903a000 0x80>;
-                        interrupts = <0 42 0x4>;
+                        interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "timer6";
                        ti,timer-dsp;
                };
@@ -571,7 +574,7 @@
                        compatible = "ti,omap4430-timer";
                        reg = <0x4013c000 0x80>,
                              <0x4903c000 0x80>;
-                        interrupts = <0 43 0x4>;
+                        interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "timer7";
                        ti,timer-dsp;
                };
@@ -580,7 +583,7 @@
                        compatible = "ti,omap4430-timer";
                        reg = <0x4013e000 0x80>,
                              <0x4903e000 0x80>;
-                        interrupts = <0 44 0x4>;
+                        interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "timer8";
                        ti,timer-pwm;
                        ti,timer-dsp;
@@ -589,7 +592,7 @@
                timer9: timer@4803e000 {
                        compatible = "ti,omap4430-timer";
                        reg = <0x4803e000 0x80>;
-                        interrupts = <0 45 0x4>;
+                        interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "timer9";
                        ti,timer-pwm;
                };
@@ -597,7 +600,7 @@
                timer10: timer@48086000 {
                        compatible = "ti,omap3430-timer";
                        reg = <0x48086000 0x80>;
-                        interrupts = <0 46 0x4>;
+                        interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "timer10";
                        ti,timer-pwm;
                };
@@ -605,7 +608,7 @@
                timer11: timer@48088000 {
                        compatible = "ti,omap4430-timer";
                        reg = <0x48088000 0x80>;
-                        interrupts = <0 47 0x4>;
+                        interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "timer11";
                        ti,timer-pwm;
                };
@@ -613,7 +616,7 @@
                usbhstll: usbhstll@4a062000 {
                        compatible = "ti,usbhs-tll";
                        reg = <0x4a062000 0x1000>;
-                        interrupts = <0 78 0x4>;
+                        interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "usb_tll_hs";
                };
@@ -629,14 +632,14 @@
                                compatible = "ti,ohci-omap3", "usb-ohci";
                                reg = <0x4a064800 0x400>;
                                interrupt-parent = <&gic>;
-                                interrupts = <0 76 0x4>;
+                                interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
                        };
                        usbhsehci: ehci@4a064c00 {
                                compatible = "ti,ehci-omap", "usb-ehci";
                                reg = <0x4a064c00 0x400>;
                                interrupt-parent = <&gic>;
-                                interrupts = <0 77 0x4>;
+                                interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
                        };
                };
@@ -651,7 +654,7 @@
                usb_otg_hs: usb_otg_hs@4a0ab000 {
                        compatible = "ti,omap4-musb";
                        reg = <0x4a0ab000 0x7ff>;
-                        interrupts = <0 92 0x4>, <0 93 0x4>;
+                        interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "mc", "dma";
                        ti,hwmods = "usb_otg_hs";
                        usb-phy = <&usb2_phy>;
diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi
index cccf39af4925..bcf455efe18d 100644
--- a/arch/arm/boot/dts/omap443x.dtsi
+++ b/arch/arm/boot/dts/omap443x.dtsi
@@ -8,7 +8,7 @@
 * kind, whether express or implied.
 */
-/include/ "omap4.dtsi"
+#include "omap4.dtsi"
 / {
        cpus {
@@ -24,4 +24,10 @@
                        clock-latency = <300000>; /* From legacy driver */
                };
        };
+        bandgap {
+                reg = <0x4a002260 0x4
+                       0x4a00232C 0x4>;
+                compatible = "ti,omap4430-bandgap";
+        };
 };
diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
index 2cf227c86099..c2f0f39b5a24 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -7,7 +7,7 @@
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */
-/include/ "omap4.dtsi"
+#include "omap4.dtsi"
 / {
        cpus {
@@ -25,8 +25,17 @@
        pmu {
                compatible = "arm,cortex-a9-pmu";
-                interrupts = <0 54 0x4>,
+                interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
-                             <0 55 0x4>;
+                             <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
                ti,hwmods = "debugss";
        };
+        bandgap {
+                reg = <0x4a002260 0x4
+                       0x4a00232C 0x4
+                       0x4a002378 0x18>;
+                compatible = "ti,omap4460-bandgap";
+                interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */
+                gpios = <&gpio3 22 0>; /* tshut */
+        };
 };
diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
deleted file mode 100644
index 982acd19477d..000000000000
--- a/arch/arm/boot/dts/omap5-evm.dts
+++ /dev/null
@@ -1,261 +0,0 @@
-/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-/dts-v1/;
-/include/ "omap5.dtsi"
-/include/ "samsung_k3pe0e000b.dtsi"
-/ {
-        model = "TI OMAP5 EVM board";
-        compatible = "ti,omap5-evm", "ti,omap5";
-        memory {
-                device_type = "memory";
-                reg = <0x80000000 0x7F000000>; /* 2032 MB */
-        };
-        vmmcsd_fixed: fixedregulator-mmcsd {
-                compatible = "regulator-fixed";
-                regulator-name = "vmmcsd_fixed";
-                regulator-min-microvolt = <3000000>;
-                regulator-max-microvolt = <3000000>;
-        };
-};
-&omap5_pmx_core {
-        pinctrl-names = "default";
-        pinctrl-0 = <
-                        &twl6040_pins
-                        &mcpdm_pins
-                        &dmic_pins
-                        &mcbsp1_pins
-                        &mcbsp2_pins
-        >;
-        twl6040_pins: pinmux_twl6040_pins {
-                pinctrl-single,pins = <
-                        0x18a 0x6       /* perslimbus2_clock.gpio5_145 OUTPUT | MODE6 */
-                >;
-        };
-        mcpdm_pins: pinmux_mcpdm_pins {
-                pinctrl-single,pins = <
-                        0x142 0x108     /* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */
-                        0x15c 0x108     /* abemcpdm_ul_data.abemcpdm_ul_data INPUT PULLDOWN | MODE0 */
-                        0x15e 0x108     /* abemcpdm_dl_data.abemcpdm_dl_data INPUT PULLDOWN | MODE0 */
-                        0x160 0x118     /* abemcpdm_frame.abemcpdm_frame INPUT PULLUP | MODE0 */
-                        0x162 0x108     /* abemcpdm_lb_clk.abemcpdm_lb_clk INPUT PULLDOWN | MODE0 */
-                >;
-        };
-        dmic_pins: pinmux_dmic_pins {
-                pinctrl-single,pins = <
-                        0x144 0x100     /* abedmic_din1.abedmic_din1 INPUT | MODE0 */
-                        0x146 0x100     /* abedmic_din2.abedmic_din2 INPUT | MODE0 */
-                        0x148 0x100     /* abedmic_din3.abedmic_din3 INPUT | MODE0 */
-                        0x14a 0         /* abedmic_clk1.abedmic_clk1 OUTPUT | MODE0 */
-                >;
-        };
-        mcbsp1_pins: pinmux_mcbsp1_pins {
-                pinctrl-single,pins = <
-                        0x14c 0x101     /* abedmic_clk2.abemcbsp1_fsx INPUT | MODE1 */
-                        0x14e 0x9       /* abedmic_clk3.abemcbsp1_dx OUTPUT PULLDOWN | MODE1 */
-                        0x150 0x101     /* abeslimbus1_clock.abemcbsp1_clkx INPUT | MODE0 */
-                        0x152 0x109     /* abeslimbus1_data.abemcbsp1_dr INPUT PULLDOWN | MODE1 */
-                >;
-        };
-        mcbsp2_pins: pinmux_mcbsp2_pins {
-                pinctrl-single,pins = <
-                        0x154 0x108     /* abemcbsp2_dr.abemcbsp2_dr INPUT PULLDOWN | MODE0 */
-                        0x156 0x8       /* abemcbsp2_dx.abemcbsp2_dx OUTPUT PULLDOWN | MODE0 */
-                        0x158 0x100     /* abemcbsp2_fsx.abemcbsp2_fsx INPUT | MODE0 */
-                        0x15a 0x100     /* abemcbsp2_clkx.abemcbsp2_clkx INPUT | MODE0 */
-                >;
-        };
-        i2c1_pins: pinmux_i2c1_pins {
-                pinctrl-single,pins = <
-                        0x1b2 0x118        /* i2c1_scl PULLUP | INPUTENABLE | MODE0 */
-                        0x1b4 0x118        /* i2c1_sda PULLUP | INPUTENABLE | MODE0 */
-                >;
-        };
-        i2c2_pins: pinmux_i2c2_pins {
-                pinctrl-single,pins = <
-                        0x178 0x100        /* i2c2_scl INPUTENABLE | MODE0 */
-                        0x17a 0x100        /* i2c2_sda INPUTENABLE | MODE0 */
-                >;
-        };
-        i2c3_pins: pinmux_i2c3_pins {
-                pinctrl-single,pins = <
-                        0x13a 0x100        /* i2c3_scl INPUTENABLE | MODE0 */
-                        0x13c 0x100     /* i2c3_sda INPUTENABLE | MODE0 */
-                >;
-        };
-        i2c4_pins: pinmux_i2c4_pins {
-                pinctrl-single,pins = <
-                        0xb8 0x100        /* i2c4_scl INPUTENABLE | MODE0 */
-                        0xba 0x100     /* i2c4_sda INPUTENABLE | MODE0 */
-                >;
-        };
-        i2c5_pins: pinmux_i2c5_pins {
-                pinctrl-single,pins = <
-                        0x184 0x100        /* i2c5_scl INPUTENABLE | MODE0 */
-                        0x186 0x100     /* i2c5_sda INPUTENABLE | MODE0 */
-                >;
-        };
-        mcspi2_pins: pinmux_mcspi2_pins {
-                pinctrl-single,pins = <
-                        0xbc 0x100      /*  MCSPI2_CLK INPUTENABLE | MODE0 */
-                        0xbe 0x100      /*  MCSPI2_SIMO INPUTENABLE | MODE0 */
-                        0xc0 0x118      /*  MCSPI2_SOMI PULLUP | INPUTENABLE | MODE0*/
-                        0xc2 0x0        /*  MCSPI2_CS MODE0*/
-                >;
-        };
-        mcspi3_pins: pinmux_mcspi3_pins {
-                pinctrl-single,pins = <
-                        0x78 0x101      /*  MCSPI2_SOMI INPUTENABLE | MODE1 */
-                        0x7a 0x101      /*  MCSPI2_CS INPUTENABLE | MODE1 */
-                        0x7c 0x101      /*  MCSPI2_SIMO INPUTENABLE | MODE1 */
-                        0x7e 0x101      /*  MCSPI2_CLK INPUTENABLE | MODE1 */
-                >;
-        };
-        mcspi4_pins: pinmux_mcspi4_pins {
-                pinctrl-single,pins = <
-                        0x164 0x101     /*  MCSPI2_CLK INPUTENABLE | MODE1 */
-                        0x168 0x101     /*  MCSPI2_SIMO INPUTENABLE | MODE1 */
-                        0x16a 0x101     /*  MCSPI2_SOMI INPUTENABLE | MODE1 */
-                        0x16c 0x101     /*  MCSPI2_CS INPUTENABLE | MODE1 */
-                >;
-        };
-};
-&mmc1 {
-        vmmc-supply = <&vmmcsd_fixed>;
-        bus-width = <4>;
-};
-&mmc2 {
-        vmmc-supply = <&vmmcsd_fixed>;
-        bus-width = <8>;
-        ti,non-removable;
-};
-&mmc3 {
-        bus-width = <4>;
-        ti,non-removable;
-};
-&mmc4 {
-        status = "disabled";
-};
-&mmc5 {
-        status = "disabled";
-};
-&i2c1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&i2c1_pins>;
-        clock-frequency = <400000>;
-};
-&i2c2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&i2c2_pins>;
-        clock-frequency = <400000>;
-        /* Pressure Sensor */
-        bmp085@77 {
-                compatible = "bosch,bmp085";
-                reg = <0x77>;
-        };
-};
-&i2c3 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&i2c3_pins>;
-        clock-frequency = <400000>;
-};
-&i2c4 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&i2c4_pins>;
-        clock-frequency = <400000>;
-        /* Temperature Sensor */
-        tmp102@48{
-                compatible = "ti,tmp102";
-                reg = <0x48>;
-        };
-};
-&i2c5 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&i2c5_pins>;
-        clock-frequency = <400000>;
-};
-&keypad {
-        keypad,num-rows = <8>;
-        keypad,num-columns = <8>;
-        linux,keymap = <0x02020073      /* VOLUP */
-                        0x02030072      /* VOLDOWM */
-                        0x020400e7      /* SEND */
-                        0x02050066      /* HOME */
-                        0x0206006b      /* END */
-                        0x020700d9>;    /* SEARCH */
-        linux,input-no-autorepeat;
-};
-&mcbsp3 {
-        status = "disabled";
-};
-&emif1 {
-        cs1-used;
-        device-handle = <&samsung_K3PE0E000B>;
-};
-&emif2 {
-        cs1-used;
-        device-handle = <&samsung_K3PE0E000B>;
-};
-&mcspi1 {
-};
-&mcspi2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mcspi2_pins>;
-};
-&mcspi3 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mcspi3_pins>;
-};
-&mcspi4 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mcspi4_pins>;
-};
diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
new file mode 100644
index 000000000000..65d7b601651c
--- /dev/null
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -0,0 +1,505 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "omap5.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+/ {
+        model = "TI OMAP5 uEVM board";
+        compatible = "ti,omap5-uevm", "ti,omap5";
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x7F000000>; /* 2032 MB */
+        };
+        vmmcsd_fixed: fixedregulator-mmcsd {
+                compatible = "regulator-fixed";
+                regulator-name = "vmmcsd_fixed";
+                regulator-min-microvolt = <3000000>;
+                regulator-max-microvolt = <3000000>;
+        };
+        /* HS USB Port 2 RESET */
+        hsusb2_reset: hsusb2_reset_reg {
+                compatible = "regulator-fixed";
+                regulator-name = "hsusb2_reset";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; /* gpio3_80 HUB_NRESET */
+                startup-delay-us = <70000>;
+                enable-active-high;
+        };
+        /* HS USB Host PHY on PORT 2 */
+        hsusb2_phy: hsusb2_phy {
+                compatible = "usb-nop-xceiv";
+                reset-supply = <&hsusb2_reset>;
+        /**
+          * FIXME
+          * Put the right clock phandle here when available
+          *     clocks = <&auxclk1>;
+          *     clock-names = "main_clk";
+          */
+                clock-frequency = <19200000>;
+        };
+        /* HS USB Port 3 RESET */
+        hsusb3_reset: hsusb3_reset_reg {
+                compatible = "regulator-fixed";
+                regulator-name = "hsusb3_reset";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>; /* gpio3_79 ETH_NRESET */
+                startup-delay-us = <70000>;
+                enable-active-high;
+        };
+        /* HS USB Host PHY on PORT 3 */
+        hsusb3_phy: hsusb3_phy {
+                compatible = "usb-nop-xceiv";
+                reset-supply = <&hsusb3_reset>;
+        };
+        leds {
+                compatible = "gpio-leds";
+                led@1 {
+                        label = "omap5:blue:usr1";
+                        gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; /* gpio5_153 D1 LED */
+                        linux,default-trigger = "heartbeat";
+                        default-state = "off";
+                };
+        };
+};
+&omap5_pmx_core {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                        &twl6040_pins
+                        &mcpdm_pins
+                        &dmic_pins
+                        &mcbsp1_pins
+                        &mcbsp2_pins
+                        &usbhost_pins
+                        &led_gpio_pins
+        >;
+        twl6040_pins: pinmux_twl6040_pins {
+                pinctrl-single,pins = <
+                        0x18a (PIN_OUTPUT | MUX_MODE6)  /* perslimbus2_clock.gpio5_145 */
+                >;
+        };
+        mcpdm_pins: pinmux_mcpdm_pins {
+                pinctrl-single,pins = <
+                        0x142 (PIN_INPUT_PULLDOWN | MUX_MODE0)  /* abe_clks.abe_clks */
+                        0x15c (PIN_INPUT_PULLDOWN | MUX_MODE0)  /* abemcpdm_ul_data.abemcpdm_ul_data */
+                        0x15e (PIN_INPUT_PULLDOWN | MUX_MODE0)  /* abemcpdm_dl_data.abemcpdm_dl_data */
+                        0x160 (PIN_INPUT_PULLUP | MUX_MODE0)    /* abemcpdm_frame.abemcpdm_frame */
+                        0x162 (PIN_INPUT_PULLDOWN | MUX_MODE0)  /* abemcpdm_lb_clk.abemcpdm_lb_clk */
+                >;
+        };
+        dmic_pins: pinmux_dmic_pins {
+                pinctrl-single,pins = <
+                        0x144 (PIN_INPUT | MUX_MODE0)           /* abedmic_din1.abedmic_din1 */
+                        0x146 (PIN_INPUT | MUX_MODE0)           /* abedmic_din2.abedmic_din2 */
+                        0x148 (PIN_INPUT | MUX_MODE0)           /* abedmic_din3.abedmic_din3 */
+                        0x14a (PIN_OUTPUT | MUX_MODE0)          /* abedmic_clk1.abedmic_clk1 */
+                >;
+        };
+        mcbsp1_pins: pinmux_mcbsp1_pins {
+                pinctrl-single,pins = <
+                        0x14c (PIN_INPUT | MUX_MODE1)           /* abedmic_clk2.abemcbsp1_fsx */
+                        0x14e (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* abedmic_clk3.abemcbsp1_dx */
+                        0x150 (PIN_INPUT | MUX_MODE1)           /* abeslimbus1_clock.abemcbsp1_clkx */
+                        0x152 (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* abeslimbus1_data.abemcbsp1_dr */
+                >;
+        };
+        mcbsp2_pins: pinmux_mcbsp2_pins {
+                pinctrl-single,pins = <
+                        0x154 (PIN_INPUT_PULLDOWN | MUX_MODE0)  /* abemcbsp2_dr.abemcbsp2_dr */
+                        0x156 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dx.abemcbsp2_dx */
+                        0x158 (PIN_INPUT | MUX_MODE0)           /* abemcbsp2_fsx.abemcbsp2_fsx */
+                        0x15a (PIN_INPUT | MUX_MODE0)           /* abemcbsp2_clkx.abemcbsp2_clkx */
+                >;
+        };
+        i2c1_pins: pinmux_i2c1_pins {
+                pinctrl-single,pins = <
+                        0x1b2 (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c1_scl */
+                        0x1b4 (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c1_sda */
+                >;
+        };
+        i2c5_pins: pinmux_i2c5_pins {
+                pinctrl-single,pins = <
+                        0x184 (PIN_INPUT | MUX_MODE0)           /* i2c5_scl */
+                        0x186 (PIN_INPUT | MUX_MODE0)           /* i2c5_sda */
+                >;
+        };
+        mcspi2_pins: pinmux_mcspi2_pins {
+                pinctrl-single,pins = <
+                        0xbc (PIN_INPUT | MUX_MODE0)            /*  mcspi2_clk */
+                        0xbe (PIN_INPUT | MUX_MODE0)            /*  mcspi2_simo */
+                        0xc0 (PIN_INPUT_PULLUP | MUX_MODE0)     /*  mcspi2_somi */
+                        0xc2 (PIN_OUTPUT | MUX_MODE0)           /*  mcspi2_cs */
+                >;
+        };
+        mcspi3_pins: pinmux_mcspi3_pins {
+                pinctrl-single,pins = <
+                        0x78 (PIN_INPUT | MUX_MODE1)            /*  mcspi2_somi */
+                        0x7a (PIN_INPUT | MUX_MODE1)            /*  mcspi2_cs */
+                        0x7c (PIN_INPUT | MUX_MODE1)            /*  mcspi2_simo */
+                        0x7e (PIN_INPUT | MUX_MODE1)            /*  mcspi2_clk */
+                >;
+        };
+        mcspi4_pins: pinmux_mcspi4_pins {
+                pinctrl-single,pins = <
+                        0x164 (PIN_INPUT | MUX_MODE1)           /*  mcspi2_clk */
+                        0x168 (PIN_INPUT | MUX_MODE1)           /*  mcspi2_simo */
+                        0x16a (PIN_INPUT | MUX_MODE1)           /*  mcspi2_somi */
+                        0x16c (PIN_INPUT | MUX_MODE1)           /*  mcspi2_cs */
+                >;
+        };
+        usbhost_pins: pinmux_usbhost_pins {
+                pinctrl-single,pins = <
+                        0x84 (PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */
+                        0x86 (PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data */
+                        0x19e (PIN_INPUT | MUX_MODE0) /* usbb3_hsic_strobe */
+                        0x1a0 (PIN_INPUT | MUX_MODE0) /* usbb3_hsic_data */
+                        0x70 (PIN_OUTPUT | MUX_MODE6) /* gpio3_80 HUB_NRESET */
+                        0x6e (PIN_OUTPUT | MUX_MODE6) /* gpio3_79 ETH_NRESET */
+                >;
+        };
+        led_gpio_pins: pinmux_led_gpio_pins {
+                pinctrl-single,pins = <
+                        0x196 (PIN_OUTPUT | MUX_MODE6) /* uart3_cts_rctx.gpio5_153 */
+                >;
+        };
+        uart1_pins: pinmux_uart1_pins {
+                pinctrl-single,pins = <
+                        0x60 (PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_cts */
+                        0x62 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_tx.uart1_cts */
+                        0x64 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rx.uart1_rts */
+                        0x66 (PIN_OUTPUT | MUX_MODE0) /* uart1_rx.uart1_rts */
+                >;
+        };
+        uart3_pins: pinmux_uart3_pins {
+                pinctrl-single,pins = <
+                        0x19a (PIN_OUTPUT | MUX_MODE0) /* uart3_rts_irsd.uart3_tx_irtx */
+                        0x19c (PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_rx_irrx.uart3_usbb3_hsic */
+                >;
+        };
+        uart5_pins: pinmux_uart5_pins {
+                pinctrl-single,pins = <
+                        0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_rx.uart5_rx */
+                        0x172 (PIN_OUTPUT | MUX_MODE0) /* uart5_tx.uart5_tx */
+                        0x174 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_cts.uart5_rts */
+                        0x176 (PIN_OUTPUT | MUX_MODE0) /* uart5_cts.uart5_rts */
+                >;
+        };
+};
+&omap5_pmx_wkup {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                        &usbhost_wkup_pins
+        >;
+        usbhost_wkup_pins: pinmux_usbhost_wkup_pins {
+                pinctrl-single,pins = <
+                        0x1A (PIN_OUTPUT | MUX_MODE0) /* fref_clk1_out, USB hub clk */
+                >;
+        };
+};
+&mmc1 {
+        vmmc-supply = <&ldo9_reg>;
+        bus-width = <4>;
+};
+&mmc2 {
+        vmmc-supply = <&vmmcsd_fixed>;
+        bus-width = <8>;
+        ti,non-removable;
+};
+&mmc3 {
+        bus-width = <4>;
+        ti,non-removable;
+};
+&mmc4 {
+        status = "disabled";
+};
+&mmc5 {
+        status = "disabled";
+};
+&i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c1_pins>;
+        clock-frequency = <400000>;
+        palmas: palmas@48 {
+                compatible = "ti,palmas";
+                interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
+                interrupt-parent = <&gic>;
+                reg = <0x48>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                palmas_pmic {
+                        compatible = "ti,palmas-pmic";
+                        interrupt-parent = <&palmas>;
+                        interrupts = <14 IRQ_TYPE_NONE>;
+                        interrupt-name = "short-irq";
+                        ti,ldo6-vibrator;
+                        regulators {
+                                smps123_reg: smps123 {
+                                        /* VDD_OPP_MPU */
+                                        regulator-name = "smps123";
+                                        regulator-min-microvolt = < 600000>;
+                                        regulator-max-microvolt = <1500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                smps45_reg: smps45 {
+                                        /* VDD_OPP_MM */
+                                        regulator-name = "smps45";
+                                        regulator-min-microvolt = < 600000>;
+                                        regulator-max-microvolt = <1310000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                smps6_reg: smps6 {
+                                        /* VDD_DDR3 - over VDD_SMPS6 */
+                                        regulator-name = "smps6";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                smps7_reg: smps7 {
+                                        /* VDDS_1v8_OMAP over VDDS_1v8_MAIN */
+                                        regulator-name = "smps7";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                smps8_reg: smps8 {
+                                        /* VDD_OPP_CORE */
+                                        regulator-name = "smps8";
+                                        regulator-min-microvolt = < 600000>;
+                                        regulator-max-microvolt = <1310000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                smps9_reg: smps9 {
+                                        /* VDDA_2v1_AUD over VDD_2v1 */
+                                        regulator-name = "smps9";
+                                        regulator-min-microvolt = <2100000>;
+                                        regulator-max-microvolt = <2100000>;
+                                        ti,smps-range = <0x80>;
+                                };
+                                smps10_reg: smps10 {
+                                        /* VBUS_5V_OTG */
+                                        regulator-name = "smps10";
+                                        regulator-min-microvolt = <5000000>;
+                                        regulator-max-microvolt = <5000000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                ldo1_reg: ldo1 {
+                                        /* VDDAPHY_CAM: vdda_csiport */
+                                        regulator-name = "ldo1";
+                                        regulator-min-microvolt = <1500000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                                ldo2_reg: ldo2 {
+                                        /* VCC_2V8_DISP: Does not go anywhere */
+                                        regulator-name = "ldo2";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        /* Unused */
+                                        status = "disabled";
+                                };
+                                ldo3_reg: ldo3 {
+                                        /* VDDAPHY_MDM: vdda_lli */
+                                        regulator-name = "ldo3";
+                                        regulator-min-microvolt = <1500000>;
+                                        regulator-max-microvolt = <1500000>;
+                                        regulator-boot-on;
+                                        /* Only if Modem is used */
+                                        status = "disabled";
+                                };
+                                ldo4_reg: ldo4 {
+                                        /* VDDAPHY_DISP: vdda_dsiport/hdmi */
+                                        regulator-name = "ldo4";
+                                        regulator-min-microvolt = <1500000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                                ldo5_reg: ldo5 {
+                                        /* VDDA_1V8_PHY: usb/sata/hdmi.. */
+                                        regulator-name = "ldo5";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                ldo6_reg: ldo6 {
+                                        /* VDDS_1V2_WKUP: hsic/ldo_emu_wkup */
+                                        regulator-name = "ldo6";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                ldo7_reg: ldo7 {
+                                        /* VDD_VPP: vpp1 */
+                                        regulator-name = "ldo7";
+                                        regulator-min-microvolt = <2000000>;
+                                        regulator-max-microvolt = <2000000>;
+                                        /* Only for efuse reprograming! */
+                                        status = "disabled";
+                                };
+                                ldo8_reg: ldo8 {
+                                        /* VDD_3v0: Does not go anywhere */
+                                        regulator-name = "ldo8";
+                                        regulator-min-microvolt = <3000000>;
+                                        regulator-max-microvolt = <3000000>;
+                                        regulator-boot-on;
+                                        /* Unused */
+                                        status = "disabled";
+                                };
+                                ldo9_reg: ldo9 {
+                                        /* VCC_DV_SDIO: vdds_sdcard */
+                                        regulator-name = "ldo9";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <3000000>;
+                                        regulator-boot-on;
+                                };
+                                ldoln_reg: ldoln {
+                                        /* VDDA_1v8_REF: vdds_osc/mm_l4per.. */
+                                        regulator-name = "ldoln";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                ldousb_reg: ldousb {
+                                        /* VDDA_3V_USB: VDDA_USBHS33 */
+                                        regulator-name = "ldousb";
+                                        regulator-min-microvolt = <3250000>;
+                                        regulator-max-microvolt = <3250000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                regen3_reg: regen3 {
+                                        /* REGEN3 controls LDO9 supply to card */
+                                        regulator-name = "regen3";
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                        };
+                };
+        };
+};
+&i2c5 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c5_pins>;
+        clock-frequency = <400000>;
+};
+&mcbsp3 {
+        status = "disabled";
+};
+&usbhshost {
+        port2-mode = "ehci-hsic";
+        port3-mode = "ehci-hsic";
+};
+&usbhsehci {
+        phys = <0 &hsusb2_phy &hsusb3_phy>;
+};
+&mcspi1 {
+};
+&mcspi2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mcspi2_pins>;
+};
+&mcspi3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mcspi3_pins>;
+};
+&mcspi4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mcspi4_pins>;
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart1_pins>;
+};
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart3_pins>;
+};
+&uart5 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart5_pins>;
+};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 635cae283011..e643620417a9 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -7,15 +7,11 @@
 * Based on "omap4.dtsi"
 */
-/*
+#include <dt-bindings/gpio/gpio.h>
- * Carveout for multimedia usecases
+#include <dt-bindings/interrupt-controller/arm-gic.h>
- * It should be the last 48MB of the first 512MB memory part
+#include <dt-bindings/pinctrl/omap.h>
- * In theory, it should not even exist. That zone should be reserved
- * dynamically during the .reserve callback.
- */
-/memreserve/ 0x9d000000 0x03000000;
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 / {
        #address-cells = <1>;
@@ -34,21 +30,28 @@
        };
        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
                cpu@0 {
+                        device_type = "cpu";
                        compatible = "arm,cortex-a15";
+                        reg = <0x0>;
                };
                cpu@1 {
+                        device_type = "cpu";
                        compatible = "arm,cortex-a15";
+                        reg = <0x1>;
                };
        };
        timer {
                compatible = "arm,armv7-timer";
-                /* PPI secure/nonsecure IRQ, active low level-sensitive */
+                /* PPI secure/nonsecure IRQ */
-                interrupts = <1 13 0x308>,
+                interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
-                             <1 14 0x308>,
+                             <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
-                             <1 11 0x308>,
+                             <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
-                             <1 10 0x308>;
+                             <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
                clock-frequency = <6144000>;
        };
@@ -90,8 +93,8 @@
                reg = <0x44000000 0x2000>,
                      <0x44800000 0x3000>,
                      <0x45000000 0x4000>;
-                interrupts = <0 9 0x4>,
+                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
-                             <0 10 0x4>;
+                             <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
                counter32k: counter@4ae04000 {
                        compatible = "ti,omap-counter32k";
@@ -119,10 +122,10 @@
                sdma: dma-controller@4a056000 {
                        compatible = "ti,omap4430-sdma";
                        reg = <0x4a056000 0x1000>;
-                        interrupts = <0 12 0x4>,
+                        interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
-                                     <0 13 0x4>,
+                                     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
-                                     <0 14 0x4>,
+                                     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
-                                     <0 15 0x4>;
+                                     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
                        #dma-cells = <1>;
                        #dma-channels = <32>;
                        #dma-requests = <127>;
@@ -131,7 +134,7 @@
                gpio1: gpio@4ae10000 {
                        compatible = "ti,omap4-gpio";
                        reg = <0x4ae10000 0x200>;
-                        interrupts = <0 29 0x4>;
+                        interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "gpio1";
                        ti,gpio-always-on;
                        gpio-controller;
@@ -143,7 +146,7 @@
                gpio2: gpio@48055000 {
                        compatible = "ti,omap4-gpio";
                        reg = <0x48055000 0x200>;
-                        interrupts = <0 30 0x4>;
+                        interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "gpio2";
                        gpio-controller;
                        #gpio-cells = <2>;
@@ -154,7 +157,7 @@
                gpio3: gpio@48057000 {
                        compatible = "ti,omap4-gpio";
                        reg = <0x48057000 0x200>;
-                        interrupts = <0 31 0x4>;
+                        interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "gpio3";
                        gpio-controller;
                        #gpio-cells = <2>;
@@ -165,7 +168,7 @@
                gpio4: gpio@48059000 {
                        compatible = "ti,omap4-gpio";
                        reg = <0x48059000 0x200>;
-                        interrupts = <0 32 0x4>;
+                        interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "gpio4";
                        gpio-controller;
                        #gpio-cells = <2>;
@@ -176,7 +179,7 @@
                gpio5: gpio@4805b000 {
                        compatible = "ti,omap4-gpio";
                        reg = <0x4805b000 0x200>;
-                        interrupts = <0 33 0x4>;
+                        interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "gpio5";
                        gpio-controller;
                        #gpio-cells = <2>;
@@ -187,7 +190,7 @@
                gpio6: gpio@4805d000 {
                        compatible = "ti,omap4-gpio";
                        reg = <0x4805d000 0x200>;
-                        interrupts = <0 34 0x4>;
+                        interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "gpio6";
                        gpio-controller;
                        #gpio-cells = <2>;
@@ -198,7 +201,7 @@
                gpio7: gpio@48051000 {
                        compatible = "ti,omap4-gpio";
                        reg = <0x48051000 0x200>;
-                        interrupts = <0 35 0x4>;
+                        interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "gpio7";
                        gpio-controller;
                        #gpio-cells = <2>;
@@ -209,7 +212,7 @@
                gpio8: gpio@48053000 {
                        compatible = "ti,omap4-gpio";
                        reg = <0x48053000 0x200>;
-                        interrupts = <0 121 0x4>;
+                        interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "gpio8";
                        gpio-controller;
                        #gpio-cells = <2>;
@@ -222,7 +225,7 @@
                        reg = <0x50000000 0x1000>;
                        #address-cells = <2>;
                        #size-cells = <1>;
-                        interrupts = <0 20 0x4>;
+                        interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
                        gpmc,num-cs = <8>;
                        gpmc,num-waitpins = <4>;
                        ti,hwmods = "gpmc";
@@ -231,7 +234,7 @@
                i2c1: i2c@48070000 {
                        compatible = "ti,omap4-i2c";
                        reg = <0x48070000 0x100>;
-                        interrupts = <0 56 0x4>;
+                        interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        ti,hwmods = "i2c1";
@@ -240,7 +243,7 @@
                i2c2: i2c@48072000 {
                        compatible = "ti,omap4-i2c";
                        reg = <0x48072000 0x100>;
-                        interrupts = <0 57 0x4>;
+                        interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        ti,hwmods = "i2c2";
@@ -249,7 +252,7 @@
                i2c3: i2c@48060000 {
                        compatible = "ti,omap4-i2c";
                        reg = <0x48060000 0x100>;
-                        interrupts = <0 61 0x4>;
+                        interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        ti,hwmods = "i2c3";
@@ -258,7 +261,7 @@
                i2c4: i2c@4807a000 {
                        compatible = "ti,omap4-i2c";
                        reg = <0x4807a000 0x100>;
-                        interrupts = <0 62 0x4>;
+                        interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        ti,hwmods = "i2c4";
@@ -267,7 +270,7 @@
                i2c5: i2c@4807c000 {
                        compatible = "ti,omap4-i2c";
                        reg = <0x4807c000 0x100>;
-                        interrupts = <0 60 0x4>;
+                        interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        ti,hwmods = "i2c5";
@@ -276,7 +279,7 @@
                mcspi1: spi@48098000 {
                        compatible = "ti,omap4-mcspi";
                        reg = <0x48098000 0x200>;
-                        interrupts = <0 65 0x4>;
+                        interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        ti,hwmods = "mcspi1";
@@ -296,7 +299,7 @@
                mcspi2: spi@4809a000 {
                        compatible = "ti,omap4-mcspi";
                        reg = <0x4809a000 0x200>;
-                        interrupts = <0 66 0x4>;
+                        interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        ti,hwmods = "mcspi2";
@@ -311,7 +314,7 @@
                mcspi3: spi@480b8000 {
                        compatible = "ti,omap4-mcspi";
                        reg = <0x480b8000 0x200>;
-                        interrupts = <0 91 0x4>;
+                        interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        ti,hwmods = "mcspi3";
@@ -323,7 +326,7 @@
                mcspi4: spi@480ba000 {
                        compatible = "ti,omap4-mcspi";
                        reg = <0x480ba000 0x200>;
-                        interrupts = <0 48 0x4>;
+                        interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        ti,hwmods = "mcspi4";
@@ -335,7 +338,7 @@
                uart1: serial@4806a000 {
                        compatible = "ti,omap4-uart";
                        reg = <0x4806a000 0x100>;
-                        interrupts = <0 72 0x4>;
+                        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "uart1";
                        clock-frequency = <48000000>;
                };
@@ -343,7 +346,7 @@
                uart2: serial@4806c000 {
                        compatible = "ti,omap4-uart";
                        reg = <0x4806c000 0x100>;
-                        interrupts = <0 73 0x4>;
+                        interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "uart2";
                        clock-frequency = <48000000>;
                };
@@ -351,7 +354,7 @@
                uart3: serial@48020000 {
                        compatible = "ti,omap4-uart";
                        reg = <0x48020000 0x100>;
-                        interrupts = <0 74 0x4>;
+                        interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "uart3";
                        clock-frequency = <48000000>;
                };
@@ -359,7 +362,7 @@
                uart4: serial@4806e000 {
                        compatible = "ti,omap4-uart";
                        reg = <0x4806e000 0x100>;
-                        interrupts = <0 70 0x4>;
+                        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "uart4";
                        clock-frequency = <48000000>;
                };
@@ -367,7 +370,7 @@
                uart5: serial@48066000 {
                        compatible = "ti,omap4-uart";
                        reg = <0x48066000 0x100>;
-                        interrupts = <0 105 0x4>;
+                        interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "uart5";
                        clock-frequency = <48000000>;
                };
@@ -375,7 +378,7 @@
                uart6: serial@48068000 {
                        compatible = "ti,omap4-uart";
                        reg = <0x48068000 0x100>;
-                        interrupts = <0 106 0x4>;
+                        interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "uart6";
                        clock-frequency = <48000000>;
                };
@@ -383,7 +386,7 @@
                mmc1: mmc@4809c000 {
                        compatible = "ti,omap4-hsmmc";
                        reg = <0x4809c000 0x400>;
-                        interrupts = <0 83 0x4>;
+                        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "mmc1";
                        ti,dual-volt;
                        ti,needs-special-reset;
@@ -394,7 +397,7 @@
                mmc2: mmc@480b4000 {
                        compatible = "ti,omap4-hsmmc";
                        reg = <0x480b4000 0x400>;
-                        interrupts = <0 86 0x4>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "mmc2";
                        ti,needs-special-reset;
                        dmas = <&sdma 47>, <&sdma 48>;
@@ -404,7 +407,7 @@
                mmc3: mmc@480ad000 {
                        compatible = "ti,omap4-hsmmc";
                        reg = <0x480ad000 0x400>;
-                        interrupts = <0 94 0x4>;
+                        interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "mmc3";
                        ti,needs-special-reset;
                        dmas = <&sdma 77>, <&sdma 78>;
@@ -414,7 +417,7 @@
                mmc4: mmc@480d1000 {
                        compatible = "ti,omap4-hsmmc";
                        reg = <0x480d1000 0x400>;
-                        interrupts = <0 96 0x4>;
+                        interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "mmc4";
                        ti,needs-special-reset;
                        dmas = <&sdma 57>, <&sdma 58>;
@@ -424,7 +427,7 @@
                mmc5: mmc@480d5000 {
                        compatible = "ti,omap4-hsmmc";
                        reg = <0x480d5000 0x400>;
-                        interrupts = <0 59 0x4>;
+                        interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "mmc5";
                        ti,needs-special-reset;
                        dmas = <&sdma 59>, <&sdma 60>;
@@ -442,7 +445,7 @@
                        reg = <0x40132000 0x7f>, /* MPU private access */
                              <0x49032000 0x7f>; /* L3 Interconnect */
                        reg-names = "mpu", "dma";
-                        interrupts = <0 112 0x4>;
+                        interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "mcpdm";
                        dmas = <&sdma 65>,
                               <&sdma 66>;
@@ -454,7 +457,7 @@
                        reg = <0x4012e000 0x7f>, /* MPU private access */
                              <0x4902e000 0x7f>; /* L3 Interconnect */
                        reg-names = "mpu", "dma";
-                        interrupts = <0 114 0x4>;
+                        interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "dmic";
                        dmas = <&sdma 67>;
                        dma-names = "up_link";
@@ -465,7 +468,7 @@
                        reg = <0x40122000 0xff>, /* MPU private access */
                              <0x49022000 0xff>; /* L3 Interconnect */
                        reg-names = "mpu", "dma";
-                        interrupts = <0 17 0x4>;
+                        interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "common";
                        ti,buffer-size = <128>;
                        ti,hwmods = "mcbsp1";
@@ -479,7 +482,7 @@
                        reg = <0x40124000 0xff>, /* MPU private access */
                              <0x49024000 0xff>; /* L3 Interconnect */
                        reg-names = "mpu", "dma";
-                        interrupts = <0 22 0x4>;
+                        interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "common";
                        ti,buffer-size = <128>;
                        ti,hwmods = "mcbsp2";
@@ -493,7 +496,7 @@
                        reg = <0x40126000 0xff>, /* MPU private access */
                              <0x49026000 0xff>; /* L3 Interconnect */
                        reg-names = "mpu", "dma";
-                        interrupts = <0 23 0x4>;
+                        interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "common";
                        ti,buffer-size = <128>;
                        ti,hwmods = "mcbsp3";
@@ -505,7 +508,7 @@
                timer1: timer@4ae18000 {
                        compatible = "ti,omap5430-timer";
                        reg = <0x4ae18000 0x80>;
-                        interrupts = <0 37 0x4>;
+                        interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "timer1";
                        ti,timer-alwon;
                };
@@ -513,21 +516,21 @@
                timer2: timer@48032000 {
                        compatible = "ti,omap5430-timer";
                        reg = <0x48032000 0x80>;
-                        interrupts = <0 38 0x4>;
+                        interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "timer2";
                };
                timer3: timer@48034000 {
                        compatible = "ti,omap5430-timer";
                        reg = <0x48034000 0x80>;
-                        interrupts = <0 39 0x4>;
+                        interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "timer3";
                };
                timer4: timer@48036000 {
                        compatible = "ti,omap5430-timer";
                        reg = <0x48036000 0x80>;
-                        interrupts = <0 40 0x4>;
+                        interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "timer4";
                };
@@ -535,7 +538,7 @@
                        compatible = "ti,omap5430-timer";
                        reg = <0x40138000 0x80>,
                              <0x49038000 0x80>;
-                        interrupts = <0 41 0x4>;
+                        interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "timer5";
                        ti,timer-dsp;
                        ti,timer-pwm;
@@ -545,7 +548,7 @@
                        compatible = "ti,omap5430-timer";
                        reg = <0x4013a000 0x80>,
                              <0x4903a000 0x80>;
-                        interrupts = <0 42 0x4>;
+                        interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "timer6";
                        ti,timer-dsp;
                        ti,timer-pwm;
@@ -555,7 +558,7 @@
                        compatible = "ti,omap5430-timer";
                        reg = <0x4013c000 0x80>,
                              <0x4903c000 0x80>;
-                        interrupts = <0 43 0x4>;
+                        interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "timer7";
                        ti,timer-dsp;
                };
@@ -564,7 +567,7 @@
                        compatible = "ti,omap5430-timer";
                        reg = <0x4013e000 0x80>,
                              <0x4903e000 0x80>;
-                        interrupts = <0 44 0x4>;
+                        interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "timer8";
                        ti,timer-dsp;
                        ti,timer-pwm;
@@ -573,7 +576,7 @@
                timer9: timer@4803e000 {
                        compatible = "ti,omap5430-timer";
                        reg = <0x4803e000 0x80>;
-                        interrupts = <0 45 0x4>;
+                        interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "timer9";
                        ti,timer-pwm;
                };
@@ -581,7 +584,7 @@
                timer10: timer@48086000 {
                        compatible = "ti,omap5430-timer";
                        reg = <0x48086000 0x80>;
-                        interrupts = <0 46 0x4>;
+                        interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "timer10";
                        ti,timer-pwm;
                };
@@ -589,7 +592,7 @@
                timer11: timer@48088000 {
                        compatible = "ti,omap5430-timer";
                        reg = <0x48088000 0x80>;
-                        interrupts = <0 47 0x4>;
+                        interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "timer11";
                        ti,timer-pwm;
                };
@@ -597,7 +600,7 @@
                wdt2: wdt@4ae14000 {
                        compatible = "ti,omap5-wdt", "ti,omap3-wdt";
                        reg = <0x4ae14000 0x80>;
-                        interrupts = <0 80 0x4>;
+                        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "wd_timer2";
                };
@@ -606,7 +609,7 @@
                        ti,hwmods       = "emif1";
                        phy-type        = <2>; /* DDR PHY type: Intelli PHY */
                        reg = <0x4c000000 0x400>;
-                        interrupts = <0 110 0x4>;
+                        interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
                        hw-caps-read-idle-ctrl;
                        hw-caps-ll-interface;
                        hw-caps-temp-alert;
@@ -617,7 +620,7 @@
                        ti,hwmods       = "emif2";
                        phy-type        = <2>; /* DDR PHY type: Intelli PHY */
                        reg = <0x4d000000 0x400>;
-                        interrupts = <0 111 0x4>;
+                        interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
                        hw-caps-read-idle-ctrl;
                        hw-caps-ll-interface;
                        hw-caps-temp-alert;
@@ -635,7 +638,7 @@
                        compatible = "ti,dwc3";
                        ti,hwmods = "usb_otg_ss";
                        reg = <0x4a020000 0x1000>;
-                        interrupts = <0 93 4>;
+                        interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
                        #address-cells = <1>;
                        #size-cells = <1>;
                        utmi-mode = <2>;
@@ -643,7 +646,7 @@
                        dwc3@4a030000 {
                                compatible = "synopsys,dwc3";
                                reg = <0x4a030000 0x1000>;
-                                interrupts = <0 92 4>;
+                                interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
                                usb-phy = <&usb2_phy>, <&usb3_phy>;
                                tx-fifo-resize;
                        };
@@ -670,5 +673,44 @@
                                ctrl-module = <&omap_control_usb>;
                        };
                };
+                usbhstll: usbhstll@4a062000 {
+                        compatible = "ti,usbhs-tll";
+                        reg = <0x4a062000 0x1000>;
+                        interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+                        ti,hwmods = "usb_tll_hs";
+                };
+                usbhshost: usbhshost@4a064000 {
+                        compatible = "ti,usbhs-host";
+                        reg = <0x4a064000 0x800>;
+                        ti,hwmods = "usb_host_hs";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+                        usbhsohci: ohci@4a064800 {
+                                compatible = "ti,ohci-omap3", "usb-ohci";
+                                reg = <0x4a064800 0x400>;
+                                interrupt-parent = <&gic>;
+                                interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+                        usbhsehci: ehci@4a064c00 {
+                                compatible = "ti,ehci-omap", "usb-ehci";
+                                reg = <0x4a064c00 0x400>;
+                                interrupt-parent = <&gic>;
+                                interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+                };
+                bandgap@4a0021e0 {
+                        reg = <0x4a0021e0 0xc
+                               0x4a00232c 0xc
+                               0x4a002380 0x2c
+                               0x4a0023C0 0x3c>;
+                        interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+                        compatible = "ti,omap5430-bandgap";
+                };
        };
 };
diff --git a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
index f0a8c2068ea7..533919e96eae 100644
--- a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
+++ b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
@@ -18,13 +18,13 @@
        #size-cells = <1>;
        cpus {
-                #address-cells = <1>;
+                #address-cells = <0>;
                #size-cells = <0>;
-                cpu@0 {
+                cpu {
-                        compatible = "arm,1176jz-s";
+                        compatible = "arm,arm1176jz-s";
+                        device_type = "cpu";
                        clock-frequency = <400000000>;
-                        reg = <0>;
                        d-cache-line-size = <32>;
                        d-cache-size = <32768>;
                        i-cache-line-size = <32>;
diff --git a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
index daa962d191e6..ab3e80085511 100644
--- a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
+++ b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
@@ -18,13 +18,13 @@
        #size-cells = <1>;
        cpus {
-                #address-cells = <1>;
+                #address-cells = <0>;
                #size-cells = <0>;
-                cpu@0 {
+                cpu {
-                        compatible = "arm,1176jz-s";
+                        compatible = "arm,arm1176jz-s";
+                        device_type = "cpu";
                        cpu-clock = <&arm_clk>, "cpu";
-                        reg = <0>;
                        d-cache-line-size = <32>;
                        d-cache-size = <32768>;
                        i-cache-line-size = <32>;
diff --git a/arch/arm/boot/dts/pm9g45.dts b/arch/arm/boot/dts/pm9g45.dts
index 387fedb58988..33ffabe9c4c8 100644
--- a/arch/arm/boot/dts/pm9g45.dts
+++ b/arch/arm/boot/dts/pm9g45.dts
@@ -6,7 +6,7 @@
 * Licensed under GPLv2.
 */
 /dts-v1/;
-/include/ "at91sam9g45.dtsi"
+#include "at91sam9g45.dtsi"
 / {
        model = "Ronetix pm9g45";
@@ -42,15 +42,15 @@
                                board {
                                        pinctrl_board_nand: nand0-board {
                                                atmel,pins =
-                                                        <3 3 0x0 0x1    /* PD3 gpio RDY pin pull_up*/
+                                                        <AT91_PIOD 3 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP      /* PD3 gpio RDY pin pull_up*/
-                                                         2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
+                                                         AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;   /* PC14 gpio enable pin pull_up */
                                        };
                                };
                                mmc {
                                        pinctrl_board_mmc: mmc0-board {
                                                atmel,pins =
-                                                        <3 6 0x0 0x5>;  /* PD6 gpio CD pin pull_up and deglitch */
+                                                        <AT91_PIOD 6 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;   /* PD6 gpio CD pin pull_up and deglitch */
                                        };
                                };
                        };
@@ -64,7 +64,7 @@
                                slot@0 {
                                        reg = <0>;
                                        bus-width = <4>;
-                                        cd-gpios = <&pioD 6 0>;
+                                        cd-gpios = <&pioD 6 GPIO_ACTIVE_HIGH>;
                                };
                        };
@@ -81,8 +81,8 @@
                        nand-on-flash-bbt;
                        pinctrl-0 = <&pinctrl_board_nand>;
-                        gpios = <&pioD 3 0
+                        gpios = <&pioD 3 GPIO_ACTIVE_HIGH
-                                 &pioC 14 0
+                                 &pioC 14 GPIO_ACTIVE_HIGH
                                 0
                                >;
@@ -134,13 +134,13 @@
                led0 {
                        label = "led0";
-                        gpios = <&pioD 0 1>;
+                        gpios = <&pioD 0 GPIO_ACTIVE_LOW>;
                        linux,default-trigger = "nand-disk";
                };
                led1 {
                        label = "led1";
-                        gpios = <&pioD 31 0>;
+                        gpios = <&pioD 31 GPIO_ACTIVE_HIGH>;
                        linux,default-trigger = "heartbeat";
                };
        };
@@ -152,13 +152,13 @@
                right {
                        label = "SW4";
-                        gpios = <&pioE 7 1>;
+                        gpios = <&pioE 7 GPIO_ACTIVE_LOW>;
                        linux,code = <106>;
                };
                up {
                        label = "SW3";
-                        gpios = <&pioE 8 1>;
+                        gpios = <&pioE 8 GPIO_ACTIVE_LOW>;
                        linux,code = <103>;
                };
        };
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index 3329719a9412..bbeb623fc2c6 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -18,6 +18,8 @@
                #size-cells = <0>;
                cpu@0 {
+                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
                        reg = <0x0>;
                        d-cache-line-size = <32>;
                        i-cache-line-size = <32>;
@@ -513,16 +515,16 @@
                                                sirf,function = "pulse_count";
                                        };
                                };
-                                cko0_rst_pins_a: cko0_rst@0 {
+                                cko0_pins_a: cko0@0 {
-                                        cko0_rst {
+                                        cko0 {
-                                                sirf,pins = "cko0_rstgrp";
+                                                sirf,pins = "cko0grp";
-                                                sirf,function = "cko0_rst";
+                                                sirf,function = "cko0";
                                        };
                                };
-                                cko1_rst_pins_a: cko1_rst@0 {
+                                cko1_pins_a: cko1@0 {
-                                        cko1_rst {
+                                        cko1 {
-                                                sirf,pins = "cko1_rstgrp";
+                                                sirf,pins = "cko1grp";
-                                                sirf,function = "cko1_rst";
+                                                sirf,function = "cko1";
                                        };
                                };
                        };
@@ -608,7 +610,7 @@
                };
                rtc-iobg {
-                        compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus";
+                        compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus";
                        #address-cells = <1>;
                        #size-cells = <1>;
                        reg = <0x80030000 0x10000>;
diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi
index f18aad35e8b3..a5e90f078aa9 100644
--- a/arch/arm/boot/dts/pxa2xx.dtsi
+++ b/arch/arm/boot/dts/pxa2xx.dtsi
@@ -23,8 +23,11 @@
        };
        cpus {
-                cpu@0 {
+                #address-cells = <0>;
-                        compatible = "arm,xscale";
+                #size-cells = <0>;
+                cpu {
+                        compatible = "marvell,xscale";
+                        device_type = "cpu";
                };
        };
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index fde2a337d1ff..4ff2019c0e30 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -37,12 +37,6 @@
                        <0 0xf1004000 0 0x2000>,
                        <0 0xf1006000 0 0x2000>;
                interrupts = <1 9 0xf04>;
-                gic-cpuif@4 {
-                        compatible = "arm,gic-cpuif";
-                        cpuif-id = <4>;
-                        cpu = <&cpu0>;
-                };
        };
        timer {
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
new file mode 100644
index 000000000000..09ea22c26359
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
@@ -0,0 +1,45 @@
+/*
+ * Reference Device Tree Source for the armadillo 800 eva board
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+/dts-v1/;
+/include/ "r8a7740.dtsi"
+/ {
+        model = "armadillo 800 eva reference";
+        compatible = "renesas,armadillo800eva-reference", "renesas,r8a7740";
+        chosen {
+                bootargs = "console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096 rw";
+        };
+        memory {
+                device_type = "memory";
+                reg = <0x40000000 0x20000000>;
+        };
+        reg_3p3v: regulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-3.3V";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+                regulator-boot-on;
+        };
+};
+&i2c0 {
+        touchscreen: st1232@55 {
+                compatible = "sitronix,st1232";
+                reg = <0x55>;
+                interrupt-parent = <&irqpin1>;
+                interrupts = <2 0>; /* IRQ10: hwirq 2 on irqpin1 */
+        };
+};
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index 798fa35c0005..24e930643821 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -14,8 +14,129 @@
        compatible = "renesas,r8a7740";
        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
                cpu@0 {
                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
+                        reg = <0x0>;
                };
        };
+        gic: interrupt-controller@c2800000 {
+                compatible = "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                #address-cells = <1>;
+                interrupt-controller;
+                reg = <0xc2800000 0x1000>,
+                      <0xc2000000 0x1000>;
+        };
+        /* irqpin0: IRQ0 - IRQ7 */
+        irqpin0: irqpin@e6900000 {
+                compatible = "renesas,intc-irqpin";
+                #interrupt-cells = <2>;
+                interrupt-controller;
+                reg = <0xe6900000 4>,
+                        <0xe6900010 4>,
+                        <0xe6900020 1>,
+                        <0xe6900040 1>,
+                        <0xe6900060 1>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4>;
+        };
+        /* irqpin1: IRQ8 - IRQ15 */
+        irqpin1: irqpin@e6900004 {
+                compatible = "renesas,intc-irqpin";
+                #interrupt-cells = <2>;
+                interrupt-controller;
+                reg = <0xe6900004 4>,
+                        <0xe6900014 4>,
+                        <0xe6900024 1>,
+                        <0xe6900044 1>,
+                        <0xe6900064 1>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4>;
+        };
+        /* irqpin2: IRQ16 - IRQ23 */
+        irqpin2: irqpin@e6900008 {
+                compatible = "renesas,intc-irqpin";
+                #interrupt-cells = <2>;
+                interrupt-controller;
+                reg = <0xe6900008 4>,
+                        <0xe6900018 4>,
+                        <0xe6900028 1>,
+                        <0xe6900048 1>,
+                        <0xe6900068 1>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4>;
+        };
+        /* irqpin3: IRQ24 - IRQ31 */
+        irqpin3: irqpin@e690000c {
+                compatible = "renesas,intc-irqpin";
+                #interrupt-cells = <2>;
+                interrupt-controller;
+                reg = <0xe690000c 4>,
+                        <0xe690001c 4>,
+                        <0xe690002c 1>,
+                        <0xe690004c 1>,
+                        <0xe690006c 1>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4>;
+        };
+        i2c0: i2c@fff20000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,rmobile-iic";
+                reg = <0xfff20000 0x425>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 201 0x4
+                              0 202 0x4
+                              0 203 0x4
+                              0 204 0x4>;
+        };
+        i2c1: i2c@e6c20000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,rmobile-iic";
+                reg = <0xe6c20000 0x425>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 70 0x4
+                              0 71 0x4
+                              0 72 0x4
+                              0 73 0x4>;
+        };
 };
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index fe5c6f213271..7f146c6bf756 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -48,6 +48,23 @@
                      <0xf0000100 0x100>;
        };
+        irqpin0: irqpin@fe780010 {
+                compatible = "renesas,intc-irqpin";
+                #interrupt-cells = <2>;
+                interrupt-controller;
+                reg = <0xfe78001c 4>,
+                        <0xfe780010 4>,
+                        <0xfe780024 4>,
+                        <0xfe780044 4>,
+                        <0xfe780064 4>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 27 0x4
+                                0 28 0x4
+                                0 29 0x4
+                                0 30 0x4>;
+                sense-bitfield-width = <2>;
+        };
        i2c0: i2c@0xffc70000 {
                #address-cells = <1>;
                #size-cells = <0>;
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 7a1711027e41..339d9b11721c 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -36,12 +36,6 @@
                        <0 0xf1004000 0 0x2000>,
                        <0 0xf1006000 0 0x2000>;
                interrupts = <1 9 0xf04>;
-                gic-cpuif@4 {
-                        compatible = "arm,gic-cpuif";
-                        cpuif-id = <4>;
-                        cpu = <&cpu0>;
-                };
        };
        timer {
diff --git a/arch/arm/boot/dts/rk3066a-clocks.dtsi b/arch/arm/boot/dts/rk3066a-clocks.dtsi
new file mode 100644
index 000000000000..6e307fc4c451
--- /dev/null
+++ b/arch/arm/boot/dts/rk3066a-clocks.dtsi
@@ -0,0 +1,299 @@
+/*
+ * Copyright (c) 2013 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+/ {
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                /*
+                 * This is a dummy clock, to be used as placeholder on
+                 * other mux clocks when a specific parent clock is not
+                 * yet implemented. It should be dropped when the driver
+                 * is complete.
+                 */
+                dummy: dummy {
+                        compatible = "fixed-clock";
+                        clock-frequency = <0>;
+                        #clock-cells = <0>;
+                };
+                xin24m: xin24m {
+                        compatible = "fixed-clock";
+                        clock-frequency = <24000000>;
+                        #clock-cells = <0>;
+                };
+                dummy48m: dummy48m {
+                        compatible = "fixed-clock";
+                        clock-frequency = <48000000>;
+                        #clock-cells = <0>;
+                };
+                dummy150m: dummy150m {
+                        compatible = "fixed-clock";
+                        clock-frequency = <150000000>;
+                        #clock-cells = <0>;
+                };
+                clk_gates0: gate-clk@200000d0 {
+                        compatible = "rockchip,rk2928-gate-clk";
+                        reg = <0x200000d0 0x4>;
+                        clocks = <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy>;
+                        clock-output-names =
+                                "gate_core_periph", "gate_cpu_gpll",
+                                "gate_ddrphy", "gate_aclk_cpu",
+                                "gate_hclk_cpu", "gate_pclk_cpu",
+                                "gate_atclk_cpu", "gate_i2s0",
+                                "gate_i2s0_frac", "gate_i2s1",
+                                "gate_i2s1_frac", "gate_i2s2",
+                                "gate_i2s2_frac", "gate_spdif",
+                                "gate_spdif_frac", "gate_testclk";
+                        #clock-cells = <1>;
+                };
+                clk_gates1: gate-clk@200000d4 {
+                        compatible = "rockchip,rk2928-gate-clk";
+                        reg = <0x200000d4 0x4>;
+                        clocks = <&xin24m>, <&xin24m>,
+                                 <&xin24m>, <&dummy>,
+                                 <&dummy>, <&xin24m>,
+                                 <&xin24m>, <&dummy>,
+                                 <&xin24m>, <&dummy>,
+                                 <&xin24m>, <&dummy>,
+                                 <&xin24m>, <&dummy>,
+                                 <&xin24m>, <&dummy>;
+                        clock-output-names =
+                                "gate_timer0", "gate_timer1",
+                                "gate_timer2", "gate_jtag",
+                                "gate_aclk_lcdc1_src", "gate_otgphy0",
+                                "gate_otgphy1", "gate_ddr_gpll",
+                                "gate_uart0", "gate_frac_uart0",
+                                "gate_uart1", "gate_frac_uart1",
+                                "gate_uart2", "gate_frac_uart2",
+                                "gate_uart3", "gate_frac_uart3";
+                        #clock-cells = <1>;
+                };
+                clk_gates2: gate-clk@200000d8 {
+                        compatible = "rockchip,rk2928-gate-clk";
+                        reg = <0x200000d8 0x4>;
+                        clocks = <&clk_gates2 1>, <&dummy>,
+                                 <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy>,
+                                 <&clk_gates2 3>, <&dummy>,
+                                 <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy48m>,
+                                 <&dummy>, <&dummy48m>,
+                                 <&dummy>, <&dummy>;
+                        clock-output-names =
+                                "gate_periph_src", "gate_aclk_periph",
+                                "gate_hclk_periph", "gate_pclk_periph",
+                                "gate_smc", "gate_mac",
+                                "gate_hsadc", "gate_hsadc_frac",
+                                "gate_saradc", "gate_spi0",
+                                "gate_spi1", "gate_mmc0",
+                                "gate_mac_lbtest", "gate_mmc1",
+                                "gate_emmc", "gate_tsadc";
+                        #clock-cells = <1>;
+                };
+                clk_gates3: gate-clk@200000dc {
+                        compatible = "rockchip,rk2928-gate-clk";
+                        reg = <0x200000dc 0x4>;
+                        clocks = <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy>;
+                        clock-output-names =
+                                "gate_aclk_lcdc0_src", "gate_dclk_lcdc0",
+                                "gate_dclk_lcdc1", "gate_pclkin_cif0",
+                                "gate_pclkin_cif1", "reserved",
+                                "reserved", "gate_cif0_out",
+                                "gate_cif1_out", "gate_aclk_vepu",
+                                "gate_hclk_vepu", "gate_aclk_vdpu",
+                                "gate_hclk_vdpu", "gate_gpu_src",
+                                "reserved", "gate_xin27m";
+                        #clock-cells = <1>;
+                };
+                clk_gates4: gate-clk@200000e0 {
+                        compatible = "rockchip,rk2928-gate-clk";
+                        reg = <0x200000e0 0x4>;
+                        clocks = <&clk_gates2 2>, <&clk_gates2 3>,
+                                 <&clk_gates2 1>, <&clk_gates2 1>,
+                                 <&clk_gates2 1>, <&clk_gates2 2>,
+                                 <&clk_gates2 2>, <&clk_gates2 2>,
+                                 <&clk_gates0 4>, <&clk_gates0 4>,
+                                 <&clk_gates0 3>, <&clk_gates0 3>,
+                                 <&clk_gates0 3>, <&clk_gates2 3>,
+                                 <&clk_gates0 4>;
+                        clock-output-names =
+                                "gate_hclk_peri_axi_matrix", "gate_pclk_peri_axi_matrix",
+                                "gate_aclk_cpu_peri", "gate_aclk_peri_axi_matrix",
+                                "gate_aclk_pei_niu", "gate_hclk_usb_peri",
+                                "gate_hclk_peri_ahb_arbi", "gate_hclk_emem_peri",
+                                "gate_hclk_cpubus", "gate_hclk_ahb2apb",
+                                "gate_aclk_strc_sys", "gate_aclk_l2mem_con",
+                                "gate_aclk_intmem", "gate_pclk_tsadc",
+                                "gate_hclk_hdmi";
+                        #clock-cells = <1>;
+                };
+                clk_gates5: gate-clk@200000e4 {
+                        compatible = "rockchip,rk2928-gate-clk";
+                        reg = <0x200000e4 0x4>;
+                        clocks = <&clk_gates0 3>, <&clk_gates2 1>,
+                                 <&clk_gates0 5>, <&clk_gates0 5>,
+                                 <&clk_gates0 5>, <&clk_gates0 5>,
+                                 <&clk_gates0 4>, <&clk_gates0 5>,
+                                 <&clk_gates2 1>, <&clk_gates2 2>,
+                                 <&clk_gates2 2>, <&clk_gates2 2>,
+                                 <&clk_gates2 2>, <&clk_gates4 5>,
+                                 <&clk_gates4 5>, <&dummy>;
+                        clock-output-names =
+                                "gate_aclk_dmac1", "gate_aclk_dmac2",
+                                "gate_pclk_efuse", "gate_pclk_tzpc",
+                                "gate_pclk_grf", "gate_pclk_pmu",
+                                "gate_hclk_rom", "gate_pclk_ddrupctl",
+                                "gate_aclk_smc", "gate_hclk_nandc",
+                                "gate_hclk_mmc0", "gate_hclk_mmc1",
+                                "gate_hclk_emmc", "gate_hclk_otg0",
+                                "gate_hclk_otg1", "gate_aclk_gpu";
+                        #clock-cells = <1>;
+                };
+                clk_gates6: gate-clk@200000e8 {
+                        compatible = "rockchip,rk2928-gate-clk";
+                        reg = <0x200000e8 0x4>;
+                        clocks = <&clk_gates3 0>, <&clk_gates0 4>,
+                                 <&clk_gates0 4>, <&clk_gates1 4>,
+                                 <&clk_gates0 4>, <&clk_gates3 0>,
+                                 <&clk_gates0 4>, <&clk_gates1 4>,
+                                 <&clk_gates3 0>, <&clk_gates0 4>,
+                                 <&clk_gates0 4>, <&clk_gates1 4>,
+                                 <&clk_gates0 4>, <&clk_gates3 0>,
+                                 <&dummy>, <&dummy>;
+                        clock-output-names =
+                                "gate_aclk_lcdc0", "gate_hclk_lcdc0",
+                                "gate_hclk_lcdc1", "gate_aclk_lcdc1",
+                                "gate_hclk_cif0", "gate_aclk_cif0",
+                                "gate_hclk_cif1", "gate_aclk_cif1",
+                                "gate_aclk_ipp", "gate_hclk_ipp",
+                                "gate_hclk_rga", "gate_aclk_rga",
+                                "gate_hclk_vio_bus", "gate_aclk_vio0",
+                                "gate_aclk_vcodec", "gate_shclk_vio_h2h";
+                        #clock-cells = <1>;
+                };
+                clk_gates7: gate-clk@200000ec {
+                        compatible = "rockchip,rk2928-gate-clk";
+                        reg = <0x200000ec 0x4>;
+                        clocks = <&clk_gates2 2>, <&clk_gates0 4>,
+                                 <&clk_gates0 4>, <&clk_gates0 4>,
+                                 <&clk_gates0 4>, <&clk_gates2 2>,
+                                 <&clk_gates2 2>, <&clk_gates0 5>,
+                                 <&clk_gates0 5>, <&clk_gates0 5>,
+                                 <&clk_gates0 5>, <&clk_gates2 3>,
+                                 <&clk_gates2 3>, <&clk_gates2 3>,
+                                 <&clk_gates2 3>, <&clk_gates2 3>;
+                        clock-output-names =
+                                "gate_hclk_emac", "gate_hclk_spdif",
+                                "gate_hclk_i2s0_2ch", "gate_hclk_i2s1_2ch",
+                                "gate_hclk_i2s_8ch", "gate_hclk_hsadc",
+                                "gate_hclk_pidf", "gate_pclk_timer0",
+                                "gate_pclk_timer1", "gate_pclk_timer2",
+                                "gate_pclk_pwm01", "gate_pclk_pwm23",
+                                "gate_pclk_spi0", "gate_pclk_spi1",
+                                "gate_pclk_saradc", "gate_pclk_wdt";
+                        #clock-cells = <1>;
+                };
+                clk_gates8: gate-clk@200000f0 {
+                        compatible = "rockchip,rk2928-gate-clk";
+                        reg = <0x200000f0 0x4>;
+                        clocks = <&clk_gates0 5>, <&clk_gates0 5>,
+                                 <&clk_gates2 3>, <&clk_gates2 3>,
+                                 <&clk_gates0 5>, <&clk_gates0 5>,
+                                 <&clk_gates2 3>, <&clk_gates2 3>,
+                                 <&clk_gates2 3>, <&clk_gates0 5>,
+                                 <&clk_gates0 5>, <&clk_gates0 5>,
+                                 <&clk_gates2 3>, <&clk_gates2 3>,
+                                 <&dummy>, <&clk_gates0 5>;
+                        clock-output-names =
+                                "gate_pclk_uart0", "gate_pclk_uart1",
+                                "gate_pclk_uart2", "gate_pclk_uart3",
+                                "gate_pclk_i2c0", "gate_pclk_i2c1",
+                                "gate_pclk_i2c2", "gate_pclk_i2c3",
+                                "gate_pclk_i2c4", "gate_pclk_gpio0",
+                                "gate_pclk_gpio1", "gate_pclk_gpio2",
+                                "gate_pclk_gpio3", "gate_pclk_gpio4",
+                                "reserved", "gate_pclk_gpio6";
+                        #clock-cells = <1>;
+                };
+                clk_gates9: gate-clk@200000f4 {
+                        compatible = "rockchip,rk2928-gate-clk";
+                        reg = <0x200000f4 0x4>;
+                        clocks = <&dummy>, <&clk_gates0 5>,
+                                 <&dummy>, <&dummy>,
+                                 <&dummy>, <&clk_gates1 4>,
+                                 <&clk_gates0 5>, <&dummy>,
+                                 <&dummy>, <&dummy>,
+                                 <&dummy>;
+                        clock-output-names =
+                                "gate_clk_core_dbg", "gate_pclk_dbg",
+                                "gate_clk_trace", "gate_atclk",
+                                "gate_clk_l2c", "gate_aclk_vio1",
+                                "gate_pclk_publ", "gate_aclk_intmem0",
+                                "gate_aclk_intmem1", "gate_aclk_intmem2",
+                                "gate_aclk_intmem3";
+                        #clock-cells = <1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
new file mode 100644
index 000000000000..56bfac93d3f6
--- /dev/null
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -0,0 +1,390 @@
+/*
+ * Copyright (c) 2013 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "skeleton.dtsi"
+#include "rk3066a-clocks.dtsi"
+/ {
+        compatible = "rockchip,rk3066a";
+        interrupt-parent = <&gic>;
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        next-level-cache = <&L2>;
+                        reg = <0x0>;
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        next-level-cache = <&L2>;
+                        reg = <0x1>;
+                };
+        };
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges;
+                gic: interrupt-controller@1013d000 {
+                        compatible = "arm,cortex-a9-gic";
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+                        reg = <0x1013d000 0x1000>,
+                              <0x1013c100 0x0100>;
+                };
+                L2: l2-cache-controller@10138000 {
+                        compatible = "arm,pl310-cache";
+                        reg = <0x10138000 0x1000>;
+                        cache-unified;
+                        cache-level = <2>;
+                };
+                local-timer@1013c600 {
+                        compatible = "arm,cortex-a9-twd-timer";
+                        reg = <0x1013c600 0x20>;
+                        interrupts = <GIC_PPI 13 0x304>;
+                        clocks = <&dummy150m>;
+                };
+                timer@20038000 {
+                        compatible = "snps,dw-apb-timer-osc";
+                        reg = <0x20038000 0x100>;
+                        interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clk_gates1 0>, <&clk_gates7 7>;
+                        clock-names = "timer", "pclk";
+                };
+                timer@2003a000 {
+                        compatible = "snps,dw-apb-timer-osc";
+                        reg = <0x2003a000 0x100>;
+                        interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clk_gates1 1>, <&clk_gates7 8>;
+                        clock-names = "timer", "pclk";
+                };
+                timer@2000e000 {
+                        compatible = "snps,dw-apb-timer-osc";
+                        reg = <0x2000e000 0x100>;
+                        interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clk_gates1 2>, <&clk_gates7 9>;
+                        clock-names = "timer", "pclk";
+                };
+                pinctrl@20008000 {
+                        compatible = "rockchip,rk3066a-pinctrl";
+                        reg = <0x20008000 0x150>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+                        gpio0: gpio0@20034000 {
+                                compatible = "rockchip,gpio-bank";
+                                reg = <0x20034000 0x100>;
+                                interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clk_gates8 9>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+                        gpio1: gpio1@2003c000 {
+                                compatible = "rockchip,gpio-bank";
+                                reg = <0x2003c000 0x100>;
+                                interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clk_gates8 10>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+                        gpio2: gpio2@2003e000 {
+                                compatible = "rockchip,gpio-bank";
+                                reg = <0x2003e000 0x100>;
+                                interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clk_gates8 11>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+                        gpio3: gpio3@20080000 {
+                                compatible = "rockchip,gpio-bank";
+                                reg = <0x20080000 0x100>;
+                                interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clk_gates8 12>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+                        gpio4: gpio4@20084000 {
+                                compatible = "rockchip,gpio-bank";
+                                reg = <0x20084000 0x100>;
+                                interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clk_gates8 13>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+                        gpio6: gpio6@2000a000 {
+                                compatible = "rockchip,gpio-bank";
+                                reg = <0x2000a000 0x100>;
+                                interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clk_gates8 15>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+                        pcfg_pull_default: pcfg_pull_default {
+                                bias-pull-pin-default;
+                        };
+                        pcfg_pull_none: pcfg_pull_none {
+                                bias-disable;
+                        };
+                        uart0 {
+                                uart0_xfer: uart0-xfer {
+                                        rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
+                                                        <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+                                uart0_cts: uart0-cts {
+                                        rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+                                uart0_rts: uart0-rts {
+                                        rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+                        };
+                        uart1 {
+                                uart1_xfer: uart1-xfer {
+                                        rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
+                                                        <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+                                uart1_cts: uart1-cts {
+                                        rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+                                uart1_rts: uart1-rts {
+                                        rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+                        };
+                        uart2 {
+                                uart2_xfer: uart2-xfer {
+                                        rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
+                                                        <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+                                /* no rts / cts for uart2 */
+                        };
+                        uart3 {
+                                uart3_xfer: uart3-xfer {
+                                        rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
+                                                        <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+                                uart3_cts: uart3-cts {
+                                        rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+                                uart3_rts: uart3-rts {
+                                        rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+                        };
+                        sd0 {
+                                sd0_clk: sd0-clk {
+                                        rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+                                sd0_cmd: sd0-cmd {
+                                        rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+                                sd0_cd: sd0-cd {
+                                        rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+                                sd0_wp: sd0-wp {
+                                        rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+                                sd0_bus1: sd0-bus-width1 {
+                                        rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+                                sd0_bus4: sd0-bus-width4 {
+                                        rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
+                                                        <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
+                                                        <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
+                                                        <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+                        };
+                        sd1 {
+                                sd1_clk: sd1-clk {
+                                        rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+                                sd1_cmd: sd1-cmd {
+                                        rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+                                sd1_cd: sd1-cd {
+                                        rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+                                sd1_wp: sd1-wp {
+                                        rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+                                sd1_bus1: sd1-bus-width1 {
+                                        rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+                                sd1_bus4: sd1-bus-width4 {
+                                        rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
+                                                        <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
+                                                        <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
+                                                        <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+                        };
+                };
+                uart0: serial@10124000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x10124000 0x400>;
+                        interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <1>;
+                        clocks = <&clk_gates1 8>;
+                        status = "disabled";
+                };
+                uart1: serial@10126000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x10126000 0x400>;
+                        interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <1>;
+                        clocks = <&clk_gates1 10>;
+                        status = "disabled";
+                };
+                uart2: serial@20064000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x20064000 0x400>;
+                        interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <1>;
+                        clocks = <&clk_gates1 12>;
+                        status = "disabled";
+                };
+                uart3: serial@20068000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x20068000 0x400>;
+                        interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <1>;
+                        clocks = <&clk_gates1 14>;
+                        status = "disabled";
+                };
+                dwmmc@10214000 {
+                        compatible = "rockchip,rk2928-dw-mshc";
+                        reg = <0x10214000 0x1000>;
+                        interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&clk_gates5 10>, <&clk_gates2 11>;
+                        clock-names = "biu", "ciu";
+                        status = "disabled";
+                };
+                dwmmc@10218000 {
+                        compatible = "rockchip,rk2928-dw-mshc";
+                        reg = <0x10218000 0x1000>;
+                        interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&clk_gates5 11>, <&clk_gates2 13>;
+                        clock-names = "biu", "ciu";
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/s3c2416-pinctrl.dtsi b/arch/arm/boot/dts/s3c2416-pinctrl.dtsi
new file mode 100644
index 000000000000..527e3193817f
--- /dev/null
+++ b/arch/arm/boot/dts/s3c2416-pinctrl.dtsi
@@ -0,0 +1,173 @@
+/*
+ * Samsung S3C2416 pinctrl settings
+ *
+ * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&pinctrl_0 {
+        /*
+         * Pin banks
+         */
+        gpa: gpa {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+        gpb: gpb {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+        gpc: gpc {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+        gpd: gpd {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+        gpe: gpe {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+        gpf: gpf {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpg: gpg {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gph: gph {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+        gpj: gpj {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+        gpk: gpk {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+        gpl: gpl {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+        gpm: gpm {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+        /*
+         * Pin groups
+         */
+        uart0_data: uart0-data {
+                samsung,pins = "gph-0", "gph-1";
+                samsung,pin-function = <2>;
+        };
+        uart0_fctl: uart0-fctl {
+                samsung,pins = "gph-8", "gph-9";
+                samsung,pin-function = <2>;
+        };
+        uart1_data: uart1-data {
+                samsung,pins = "gph-2", "gph-3";
+                samsung,pin-function = <2>;
+        };
+        uart1_fctl: uart1-fctl {
+                samsung,pins = "gph-10", "gph-11";
+                samsung,pin-function = <2>;
+        };
+        uart2_data: uart2-data {
+                samsung,pins = "gph-4", "gph-5";
+                samsung,pin-function = <2>;
+        };
+        uart2_fctl: uart2-fctl {
+                samsung,pins = "gph-6", "gph-7";
+                samsung,pin-function = <2>;
+        };
+        uart3_data: uart3-data {
+                samsung,pins = "gph-6", "gph-7";
+                samsung,pin-function = <2>;
+        };
+        extuart_clk: extuart-clk {
+                samsung,pins = "gph-12";
+                samsung,pin-function = <2>;
+        };
+        i2c0_bus: i2c0-bus {
+                samsung,pins = "gpe-14", "gpe-15";
+                samsung,pin-function = <2>;
+        };
+        spi0_bus: spi0-bus {
+                samsung,pins = "gpe-11", "gpe-12", "gpe-13";
+                samsung,pin-function = <2>;
+        };
+        sd0_clk: sd0-clk {
+                samsung,pins = "gpe-5";
+                samsung,pin-function = <2>;
+        };
+        sd0_cmd: sd0-cmd {
+                samsung,pins = "gpe-6";
+                samsung,pin-function = <2>;
+        };
+        sd0_bus1: sd0-bus1 {
+                samsung,pins = "gpe-7";
+                samsung,pin-function = <2>;
+        };
+        sd0_bus4: sd0-bus4 {
+                samsung,pins = "gpe-8", "gpe-9", "gpe-10";
+                samsung,pin-function = <2>;
+        };
+        sd1_cmd: sd1-cmd {
+                samsung,pins = "gpl-8";
+                samsung,pin-function = <2>;
+        };
+        sd1_clk: sd1-clk {
+                samsung,pins = "gpl-9";
+                samsung,pin-function = <2>;
+        };
+        sd1_bus1: sd1-bus1 {
+                samsung,pins = "gpl-0";
+                samsung,pin-function = <2>;
+        };
+        sd1_bus4: sd1-bus4 {
+                samsung,pins = "gpl-1", "gpl-2", "gpl-3";
+                samsung,pin-function = <2>;
+        };
+};
diff --git a/arch/arm/boot/dts/s3c2416-smdk2416.dts b/arch/arm/boot/dts/s3c2416-smdk2416.dts
new file mode 100644
index 000000000000..59594cf15998
--- /dev/null
+++ b/arch/arm/boot/dts/s3c2416-smdk2416.dts
@@ -0,0 +1,72 @@
+/*
+ * SAMSUNG SMDK2416 board device tree source
+ *
+ * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "s3c2416.dtsi"
+/ {
+        model = "SMDK2416";
+        compatible = "samsung,s3c2416";
+        memory {
+                reg =  <0x30000000 0x4000000>;
+        };
+        serial@50000000 {
+                status = "okay";
+                pinctrl-names = "default";
+                pinctrl-0 = <&uart0_data>, <&uart0_fctl>;
+        };
+        serial@50004000 {
+                status = "okay";
+                pinctrl-names = "default";
+                pinctrl-0 = <&uart1_data>, <&uart1_fctl>;
+        };
+        serial@50008000 {
+                status = "okay";
+                pinctrl-names = "default";
+                pinctrl-0 = <&uart2_data>;
+        };
+        serial@5000C000 {
+                status = "okay";
+                pinctrl-names = "default";
+                pinctrl-0 = <&uart3_data>;
+        };
+        watchdog@53000000 {
+                status = "okay";
+        };
+        rtc@57000000 {
+                status = "okay";
+        };
+        sdhci@4AC00000 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&sd0_clk>, <&sd0_cmd>,
+                                <&sd0_bus1>, <&sd0_bus4>;
+                bus-width = <4>;
+                cd-gpios = <&gpf 1 0>;
+                cd-inverted;
+                status = "okay";
+        };
+        sdhci@4A800000 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&sd1_clk>, <&sd1_cmd>,
+                                <&sd1_bus1>, <&sd1_bus4>;
+                bus-width = <4>;
+                broken-cd;
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/s3c2416.dtsi b/arch/arm/boot/dts/s3c2416.dtsi
new file mode 100644
index 000000000000..e6555bdd81b8
--- /dev/null
+++ b/arch/arm/boot/dts/s3c2416.dtsi
@@ -0,0 +1,79 @@
+/*
+ * Samsung's S3C2416 SoC device tree source
+ *
+ * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include "s3c24xx.dtsi"
+#include "s3c2416-pinctrl.dtsi"
+/ {
+        model = "Samsung S3C2416 SoC";
+        compatible = "samsung,s3c2416";
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu {
+                        compatible = "arm,arm926ejs";
+                };
+        };
+        interrupt-controller@4a000000 {
+                compatible = "samsung,s3c2416-irq";
+        };
+        pinctrl@56000000 {
+                compatible = "samsung,s3c2416-pinctrl";
+        };
+        serial@50000000 {
+                compatible = "samsung,s3c2440-uart";
+        };
+        serial@50004000 {
+                compatible = "samsung,s3c2440-uart";
+        };
+        serial@50008000 {
+                compatible = "samsung,s3c2440-uart";
+        };
+        serial@5000C000 {
+                compatible = "samsung,s3c2440-uart";
+                reg = <0x5000C000 0x4000>;
+                interrupts = <1 18 24 4>, <1 18 25 4>;
+                status = "disabled";
+        };
+        sdhci@4AC00000 {
+                compatible = "samsung,s3c6410-sdhci";
+                reg = <0x4AC00000 0x100>;
+                interrupts = <0 0 21 3>;
+                status = "disabled";
+        };
+        sdhci@4A800000 {
+                compatible = "samsung,s3c6410-sdhci";
+                reg = <0x4A800000 0x100>;
+                interrupts = <0 0 20 3>;
+                status = "disabled";
+        };
+        watchdog@53000000 {
+                interrupts = <1 9 27 3>;
+        };
+        rtc@57000000 {
+                compatible = "samsung,s3c2416-rtc";
+        };
+        i2c@54000000 {
+                compatible = "samsung,s3c2440-i2c";
+        };
+};
diff --git a/arch/arm/boot/dts/s3c24xx.dtsi b/arch/arm/boot/dts/s3c24xx.dtsi
new file mode 100644
index 000000000000..2d1d7dc9418a
--- /dev/null
+++ b/arch/arm/boot/dts/s3c24xx.dtsi
@@ -0,0 +1,92 @@
+/*
+ * Samsung's S3C24XX family device tree source
+ *
+ * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include "skeleton.dtsi"
+/ {
+        compatible = "samsung,s3c24xx";
+        interrupt-parent = <&intc>;
+        aliases {
+                pinctrl0 = &pinctrl_0;
+        };
+        intc:interrupt-controller@4a000000 {
+                compatible = "samsung,s3c2410-irq";
+                reg = <0x4a000000 0x100>;
+                interrupt-controller;
+                #interrupt-cells = <4>;
+        };
+        pinctrl_0: pinctrl@56000000 {
+                reg = <0x56000000 0x1000>;
+                wakeup-interrupt-controller {
+                        compatible = "samsung,s3c2410-wakeup-eint";
+                        interrupts = <0 0 0 3>,
+                                     <0 0 1 3>,
+                                     <0 0 2 3>,
+                                     <0 0 3 3>,
+                                     <0 0 4 4>,
+                                     <0 0 5 4>;
+                };
+        };
+        timer@51000000 {
+                compatible = "samsung,s3c2410-pwm";
+                reg = <0x51000000 0x1000>;
+                interrupts = <0 0 10 3>, <0 0 11 3>, <0 0 12 3>, <0 0 13 3>, <0 0 14 3>;
+                #pwm-cells = <4>;
+        };
+        serial@50000000 {
+                compatible = "samsung,s3c2410-uart";
+                reg = <0x50000000 0x4000>;
+                interrupts = <1 28 0 4>, <1 28 1 4>;
+                status = "disabled";
+        };
+        serial@50004000 {
+                compatible = "samsung,s3c2410-uart";
+                reg = <0x50004000 0x4000>;
+                interrupts = <1 23 3 4>, <1 23 4 4>;
+                status = "disabled";
+        };
+        serial@50008000 {
+                compatible = "samsung,s3c2410-uart";
+                reg = <0x50008000 0x4000>;
+                interrupts = <1 15 6 4>, <1 15 7 4>;
+                status = "disabled";
+        };
+        watchdog@53000000 {
+                compatible = "samsung,s3c2410-wdt";
+                reg = <0x53000000 0x100>;
+                interrupts = <0 0 9 3>;
+                status = "disabled";
+        };
+        rtc@57000000 {
+                compatible = "samsung,s3c2410-rtc";
+                reg = <0x57000000 0x100>;
+                interrupts = <0 0 30 3>, <0 0 8 3>;
+                status = "disabled";
+        };
+        i2c@54000000 {
+                compatible = "samsung,s3c2410-i2c";
+                reg = <0x54000000 0x100>;
+                interrupts = <0 0 27 3>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+};
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index 5000e0d42849..a1d5e25a6698 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -8,7 +8,11 @@
 * Licensed under GPLv2 or later.
 */
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
+#include <dt-bindings/dma/at91.h>
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
 / {
        model = "Atmel SAMA5D3 family SoC";
@@ -35,8 +39,12 @@
                ssc1 = &ssc1;
        };
        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
                cpu@0 {
+                        device_type = "cpu";
                        compatible = "arm,cortex-a5";
+                        reg = <0x0>;
                };
        };
@@ -59,8 +67,8 @@
                        mmc0: mmc@f0000000 {
                                compatible = "atmel,hsmci";
                                reg = <0xf0000000 0x600>;
-                                interrupts = <21 4 0>;
+                                interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
-                                dmas = <&dma0 2 0>;
+                                dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>;
                                dma-names = "rxtx";
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
@@ -72,9 +80,12 @@
                        spi0: spi@f0004000 {
                                #address-cells = <1>;
                                #size-cells = <0>;
-                                compatible = "atmel,at91sam9x5-spi";
+                                compatible = "atmel,at91rm9200-spi";
                                reg = <0xf0004000 0x100>;
-                                interrupts = <24 4 3>;
+                                interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
+                                dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>,
+                                       <&dma0 2 AT91_DMA_CFG_PER_ID(2)>;
+                                dma-names = "tx", "rx";
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_spi0>;
                                status = "disabled";
@@ -83,7 +94,7 @@
                        ssc0: ssc@f0008000 {
                                compatible = "atmel,at91sam9g45-ssc";
                                reg = <0xf0008000 0x4000>;
-                                interrupts = <38 4 4>;
+                                interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
                                status = "disabled";
@@ -92,7 +103,7 @@
                        can0: can@f000c000 {
                                compatible = "atmel,at91sam9x5-can";
                                reg = <0xf000c000 0x300>;
-                                interrupts = <40 4 3>;
+                                interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_can0_rx_tx>;
                                status = "disabled";
@@ -101,15 +112,15 @@
                        tcb0: timer@f0010000 {
                                compatible = "atmel,at91sam9x5-tcb";
                                reg = <0xf0010000 0x100>;
-                                interrupts = <26 4 0>;
+                                interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
                        };
                        i2c0: i2c@f0014000 {
                                compatible = "atmel,at91sam9x5-i2c";
                                reg = <0xf0014000 0x4000>;
-                                interrupts = <18 4 6>;
+                                interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>;
-                                dmas = <&dma0 2 7>,
+                                dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>,
-                                       <&dma0 2 8>;
+                                       <&dma0 2 AT91_DMA_CFG_PER_ID(8)>;
                                dma-names = "tx", "rx";
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_i2c0>;
@@ -121,9 +132,9 @@
                        i2c1: i2c@f0018000 {
                                compatible = "atmel,at91sam9x5-i2c";
                                reg = <0xf0018000 0x4000>;
-                                interrupts = <19 4 6>;
+                                interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>;
-                                dmas = <&dma0 2 9>,
+                                dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>,
-                                       <&dma0 2 10>;
+                                       <&dma0 2 AT91_DMA_CFG_PER_ID(10)>;
                                dma-names = "tx", "rx";
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_i2c1>;
@@ -135,7 +146,7 @@
                        usart0: serial@f001c000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xf001c000 0x100>;
-                                interrupts = <12 4 5>;
+                                interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_usart0>;
                                status = "disabled";
@@ -144,7 +155,7 @@
                        usart1: serial@f0020000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xf0020000 0x100>;
-                                interrupts = <13 4 5>;
+                                interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_usart1>;
                                status = "disabled";
@@ -153,7 +164,7 @@
                        macb0: ethernet@f0028000 {
                                compatible = "cdns,pc302-gem", "cdns,gem";
                                reg = <0xf0028000 0x100>;
-                                interrupts = <34 4 3>;
+                                interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>;
                                status = "disabled";
@@ -162,15 +173,15 @@
                        isi: isi@f0034000 {
                                compatible = "atmel,at91sam9g45-isi";
                                reg = <0xf0034000 0x4000>;
-                                interrupts = <37 4 5>;
+                                interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>;
                                status = "disabled";
                        };
                        mmc1: mmc@f8000000 {
                                compatible = "atmel,hsmci";
                                reg = <0xf8000000 0x600>;
-                                interrupts = <22 4 0>;
+                                interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>;
-                                dmas = <&dma1 2 0>;
+                                dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>;
                                dma-names = "rxtx";
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
@@ -182,8 +193,8 @@
                        mmc2: mmc@f8004000 {
                                compatible = "atmel,hsmci";
                                reg = <0xf8004000 0x600>;
-                                interrupts = <23 4 0>;
+                                interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
-                                dmas = <&dma1 2 1>;
+                                dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(1)>;
                                dma-names = "rxtx";
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>;
@@ -195,9 +206,12 @@
                        spi1: spi@f8008000 {
                                #address-cells = <1>;
                                #size-cells = <0>;
-                                compatible = "atmel,at91sam9x5-spi";
+                                compatible = "atmel,at91rm9200-spi";
                                reg = <0xf8008000 0x100>;
-                                interrupts = <25 4 3>;
+                                interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
+                                dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(15)>,
+                                       <&dma1 2 AT91_DMA_CFG_PER_ID(16)>;
+                                dma-names = "tx", "rx";
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_spi1>;
                                status = "disabled";
@@ -206,7 +220,7 @@
                        ssc1: ssc@f800c000 {
                                compatible = "atmel,at91sam9g45-ssc";
                                reg = <0xf800c000 0x4000>;
-                                interrupts = <39 4 4>;
+                                interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
                                status = "disabled";
@@ -215,7 +229,7 @@
                        can1: can@f8010000 {
                                compatible = "atmel,at91sam9x5-can";
                                reg = <0xf8010000 0x300>;
-                                interrupts = <41 4 3>;
+                                interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_can1_rx_tx>;
                        };
@@ -223,13 +237,13 @@
                        tcb1: timer@f8014000 {
                                compatible = "atmel,at91sam9x5-tcb";
                                reg = <0xf8014000 0x100>;
-                                interrupts = <27 4 0>;
+                                interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
                        };
                        adc0: adc@f8018000 {
                                compatible = "atmel,at91sam9260-adc";
                                reg = <0xf8018000 0x100>;
-                                interrupts = <29 4 5>;
+                                interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <
                                        &pinctrl_adc0_adtrg
@@ -283,7 +297,7 @@
                        tsadcc: tsadcc@f8018000 {
                                compatible = "atmel,at91sam9x5-tsadcc";
                                reg = <0xf8018000 0x4000>;
-                                interrupts = <29 4 5>;
+                                interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
                                atmel,tsadcc_clock = <300000>;
                                atmel,filtering_average = <0x03>;
                                atmel,pendet_debounce = <0x08>;
@@ -295,9 +309,9 @@
                        i2c2: i2c@f801c000 {
                                compatible = "atmel,at91sam9x5-i2c";
                                reg = <0xf801c000 0x4000>;
-                                interrupts = <20 4 6>;
+                                interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>;
-                                dmas = <&dma1 2 11>,
+                                dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>,
-                                       <&dma1 2 12>;
+                                       <&dma1 2 AT91_DMA_CFG_PER_ID(12)>;
                                dma-names = "tx", "rx";
                                #address-cells = <1>;
                                #size-cells = <0>;
@@ -307,7 +321,7 @@
                        usart2: serial@f8020000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xf8020000 0x100>;
-                                interrupts = <14 4 5>;
+                                interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_usart2>;
                                status = "disabled";
@@ -316,7 +330,7 @@
                        usart3: serial@f8024000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xf8024000 0x100>;
-                                interrupts = <15 4 5>;
+                                interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_usart3>;
                                status = "disabled";
@@ -325,7 +339,7 @@
                        macb1: ethernet@f802c000 {
                                compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                reg = <0xf802c000 0x100>;
-                                interrupts = <35 4 3>;
+                                interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_macb1_rmii>;
                                status = "disabled";
@@ -334,7 +348,7 @@
                        sha@f8034000 {
                                compatible = "atmel,sam9g46-sha";
                                reg = <0xf8034000 0x100>;
-                                interrupts = <42 4 0>;
+                                interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
                        };
                        aes@f8038000 {
@@ -346,20 +360,20 @@
                        tdes@f803c000 {
                                compatible = "atmel,sam9g46-tdes";
                                reg = <0xf803c000 0x100>;
-                                interrupts = <44 4 0>;
+                                interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>;
                        };
                        dma0: dma-controller@ffffe600 {
                                compatible = "atmel,at91sam9g45-dma";
                                reg = <0xffffe600 0x200>;
-                                interrupts = <30 4 0>;
+                                interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>;
                                #dma-cells = <2>;
                        };
                        dma1: dma-controller@ffffe800 {
                                compatible = "atmel,at91sam9g45-dma";
                                reg = <0xffffe800 0x200>;
-                                interrupts = <31 4 0>;
+                                interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
                                #dma-cells = <2>;
                        };
@@ -371,7 +385,7 @@
                        dbgu: serial@ffffee00 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xffffee00 0x200>;
-                                interrupts = <2 4 7>;
+                                interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_dbgu>;
                                status = "disabled";
@@ -403,202 +417,202 @@
                                adc0 {
                                        pinctrl_adc0_adtrg: adc0_adtrg {
                                                atmel,pins =
-                                                        <3 19 0x1 0x0>; /* PD19 periph A ADTRG */
+                                                        <AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD19 periph A ADTRG */
                                        };
                                        pinctrl_adc0_ad0: adc0_ad0 {
                                                atmel,pins =
-                                                        <3 20 0x1 0x0>; /* PD20 periph A AD0 */
+                                                        <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD20 periph A AD0 */
                                        };
                                        pinctrl_adc0_ad1: adc0_ad1 {
                                                atmel,pins =
-                                                        <3 21 0x1 0x0>; /* PD21 periph A AD1 */
+                                                        <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A AD1 */
                                        };
                                        pinctrl_adc0_ad2: adc0_ad2 {
                                                atmel,pins =
-                                                        <3 22 0x1 0x0>; /* PD22 periph A AD2 */
+                                                        <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD22 periph A AD2 */
                                        };
                                        pinctrl_adc0_ad3: adc0_ad3 {
                                                atmel,pins =
-                                                        <3 23 0x1 0x0>; /* PD23 periph A AD3 */
+                                                        <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD23 periph A AD3 */
                                        };
                                        pinctrl_adc0_ad4: adc0_ad4 {
                                                atmel,pins =
-                                                        <3 24 0x1 0x0>; /* PD24 periph A AD4 */
+                                                        <AT91_PIOD 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD24 periph A AD4 */
                                        };
                                        pinctrl_adc0_ad5: adc0_ad5 {
                                                atmel,pins =
-                                                        <3 25 0x1 0x0>; /* PD25 periph A AD5 */
+                                                        <AT91_PIOD 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD25 periph A AD5 */
                                        };
                                        pinctrl_adc0_ad6: adc0_ad6 {
                                                atmel,pins =
-                                                        <3 26 0x1 0x0>; /* PD26 periph A AD6 */
+                                                        <AT91_PIOD 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD26 periph A AD6 */
                                        };
                                        pinctrl_adc0_ad7: adc0_ad7 {
                                                atmel,pins =
-                                                        <3 27 0x1 0x0>; /* PD27 periph A AD7 */
+                                                        <AT91_PIOD 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD27 periph A AD7 */
                                        };
                                        pinctrl_adc0_ad8: adc0_ad8 {
                                                atmel,pins =
-                                                        <3 28 0x1 0x0>; /* PD28 periph A AD8 */
+                                                        <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD28 periph A AD8 */
                                        };
                                        pinctrl_adc0_ad9: adc0_ad9 {
                                                atmel,pins =
-                                                        <3 29 0x1 0x0>; /* PD29 periph A AD9 */
+                                                        <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD29 periph A AD9 */
                                        };
                                        pinctrl_adc0_ad10: adc0_ad10 {
                                                atmel,pins =
-                                                        <3 30 0x1 0x0>; /* PD30 periph A AD10, conflicts with PCK0 */
+                                                        <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD30 periph A AD10, conflicts with PCK0 */
                                        };
                                        pinctrl_adc0_ad11: adc0_ad11 {
                                                atmel,pins =
-                                                        <3 31 0x1 0x0>; /* PD31 periph A AD11, conflicts with PCK1 */
+                                                        <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD31 periph A AD11, conflicts with PCK1 */
                                        };
                                };
                                can0 {
                                        pinctrl_can0_rx_tx: can0_rx_tx {
                                                atmel,pins =
-                                                        <3 14 0x3 0x0   /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */
+                                                        <AT91_PIOD 14 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */
-                                                         3 15 0x3 0x0>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */
+                                                         AT91_PIOD 15 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */
                                        };
                                };
                                can1 {
                                        pinctrl_can1_rx_tx: can1_rx_tx {
                                                atmel,pins =
-                                                        <1 14 0x2 0x0   /* PB14 periph B RX, conflicts with GCRS */
+                                                        <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB14 periph B RX, conflicts with GCRS */
-                                                         1 15 0x2 0x0>; /* PB15 periph B TX, conflicts with GCOL */
+                                                         AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B TX, conflicts with GCOL */
                                        };
                                };
                                dbgu {
                                        pinctrl_dbgu: dbgu-0 {
                                                atmel,pins =
-                                                        <1 30 0x1 0x0   /* PB30 periph A */
+                                                        <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB30 periph A */
-                                                         1 31 0x1 0x1>; /* PB31 periph A with pullup */
+                                                         AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PB31 periph A with pullup */
                                        };
                                };
                                i2c0 {
                                        pinctrl_i2c0: i2c0-0 {
                                                atmel,pins =
-                                                        <0 30 0x1 0x0   /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */
+                                                        <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */
-                                                         0 31 0x1 0x0>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */
+                                                         AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */
                                        };
                                };
                                i2c1 {
                                        pinctrl_i2c1: i2c1-0 {
                                                atmel,pins =
-                                                        <2 26 0x2 0x0   /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */
+                                                        <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */
-                                                         2 27 0x2 0x0>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */
+                                                         AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */
                                        };
                                };
                                isi {
                                        pinctrl_isi: isi-0 {
                                                atmel,pins =
-                                                        <0 16 0x3 0x0   /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */
+                                                        <AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */
-                                                         0 17 0x3 0x0   /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */
+                                                         AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */
-                                                         0 18 0x3 0x0   /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */
+                                                         AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */
-                                                         0 19 0x3 0x0   /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */
+                                                         AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */
-                                                         0 20 0x3 0x0   /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */
+                                                         AT91_PIOA 20 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */
-                                                         0 21 0x3 0x0   /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */
+                                                         AT91_PIOA 21 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */
-                                                         0 22 0x3 0x0   /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */
+                                                         AT91_PIOA 22 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */
-                                                         0 23 0x3 0x0   /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */
+                                                         AT91_PIOA 23 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */
-                                                         2 30 0x3 0x0   /* PC30 periph C ISI_PCK, conflicts with UTXD0 */
+                                                         AT91_PIOC 30 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PC30 periph C ISI_PCK, conflicts with UTXD0 */
-                                                         0 31 0x3 0x0   /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */
+                                                         AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */
-                                                         0 30 0x3 0x0   /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */
+                                                         AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */
-                                                         2 29 0x3 0x0   /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */
+                                                         AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */
-                                                         2 28 0x3 0x0>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */
+                                                         AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */
                                        };
                                        pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 {
                                                atmel,pins =
-                                                        <3 31 0x2 0x0>; /* PD31 periph B ISI_MCK */
+                                                        <AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD31 periph B ISI_MCK */
                                        };
                                };
                                lcd {
                                        pinctrl_lcd: lcd-0 {
                                                atmel,pins =
-                                                        <0 24 0x1 0x0   /* PA24 periph A LCDPWM */
+                                                        <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA24 periph A LCDPWM */
-                                                         0 26 0x1 0x0   /* PA26 periph A LCDVSYNC */
+                                                         AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA26 periph A LCDVSYNC */
-                                                         0 27 0x1 0x0   /* PA27 periph A LCDHSYNC */
+                                                         AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA27 periph A LCDHSYNC */
-                                                         0 25 0x1 0x0   /* PA25 periph A LCDDISP */
+                                                         AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA25 periph A LCDDISP */
-                                                         0 29 0x1 0x0   /* PA29 periph A LCDDEN */
+                                                         AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA29 periph A LCDDEN */
-                                                         0 28 0x1 0x0   /* PA28 periph A LCDPCK */
+                                                         AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA28 periph A LCDPCK */
-                                                         0 0 0x1 0x0    /* PA0 periph A LCDD0 pin */
+                                                         AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA0 periph A LCDD0 pin */
-                                                         0 1 0x1 0x0    /* PA1 periph A LCDD1 pin */
+                                                         AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA1 periph A LCDD1 pin */
-                                                         0 2 0x1 0x0    /* PA2 periph A LCDD2 pin */
+                                                         AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA2 periph A LCDD2 pin */
-                                                         0 3 0x1 0x0    /* PA3 periph A LCDD3 pin */
+                                                         AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA3 periph A LCDD3 pin */
-                                                         0 4 0x1 0x0    /* PA4 periph A LCDD4 pin */
+                                                         AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA4 periph A LCDD4 pin */
-                                                         0 5 0x1 0x0    /* PA5 periph A LCDD5 pin */
+                                                         AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA5 periph A LCDD5 pin */
-                                                         0 6 0x1 0x0    /* PA6 periph A LCDD6 pin */
+                                                         AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA6 periph A LCDD6 pin */
-                                                         0 7 0x1 0x0    /* PA7 periph A LCDD7 pin */
+                                                         AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA7 periph A LCDD7 pin */
-                                                         0 8 0x1 0x0    /* PA8 periph A LCDD8 pin */
+                                                         AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA8 periph A LCDD8 pin */
-                                                         0 9 0x1 0x0    /* PA9 periph A LCDD9 pin */
+                                                         AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA9 periph A LCDD9 pin */
-                                                         0 10 0x1 0x0   /* PA10 periph A LCDD10 pin */
+                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA10 periph A LCDD10 pin */
-                                                         0 11 0x1 0x0   /* PA11 periph A LCDD11 pin */
+                                                         AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA11 periph A LCDD11 pin */
-                                                         0 12 0x1 0x0   /* PA12 periph A LCDD12 pin */
+                                                         AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA12 periph A LCDD12 pin */
-                                                         0 13 0x1 0x0   /* PA13 periph A LCDD13 pin */
+                                                         AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA13 periph A LCDD13 pin */
-                                                         0 14 0x1 0x0   /* PA14 periph A LCDD14 pin */
+                                                         AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA14 periph A LCDD14 pin */
-                                                         0 15 0x1 0x0   /* PA15 periph A LCDD15 pin */
+                                                         AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA15 periph A LCDD15 pin */
-                                                         2 14 0x3 0x0   /* PC14 periph C LCDD16 pin */
+                                                         AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PC14 periph C LCDD16 pin */
-                                                         2 13 0x3 0x0   /* PC13 periph C LCDD17 pin */
+                                                         AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PC13 periph C LCDD17 pin */
-                                                         2 12 0x3 0x0   /* PC12 periph C LCDD18 pin */
+                                                         AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PC12 periph C LCDD18 pin */
-                                                         2 11 0x3 0x0   /* PC11 periph C LCDD19 pin */
+                                                         AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PC11 periph C LCDD19 pin */
-                                                         2 10 0x3 0x0   /* PC10 periph C LCDD20 pin */
+                                                         AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PC10 periph C LCDD20 pin */
-                                                         2 15 0x3 0x0   /* PC15 periph C LCDD21 pin */
+                                                         AT91_PIOC 15 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PC15 periph C LCDD21 pin */
-                                                         4 27 0x3 0x0   /* PE27 periph C LCDD22 pin */
+                                                         AT91_PIOE 27 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PE27 periph C LCDD22 pin */
-                                                         4 28 0x3 0x0>; /* PE28 periph C LCDD23 pin */
+                                                         AT91_PIOE 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PE28 periph C LCDD23 pin */
                                        };
                                };
                                macb0 {
                                        pinctrl_macb0_data_rgmii: macb0_data_rgmii {
                                                atmel,pins =
-                                                        <1 0 0x1 0x0    /* PB0 periph A GTX0, conflicts with PWMH0 */
+                                                        <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB0 periph A GTX0, conflicts with PWMH0 */
-                                                         1 1 0x1 0x0    /* PB1 periph A GTX1, conflicts with PWML0 */
+                                                         AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB1 periph A GTX1, conflicts with PWML0 */
-                                                         1 2 0x1 0x0    /* PB2 periph A GTX2, conflicts with TK1 */
+                                                         AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB2 periph A GTX2, conflicts with TK1 */
-                                                         1 3 0x1 0x0    /* PB3 periph A GTX3, conflicts with TF1 */
+                                                         AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB3 periph A GTX3, conflicts with TF1 */
-                                                         1 4 0x1 0x0    /* PB4 periph A GRX0, conflicts with PWMH1 */
+                                                         AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB4 periph A GRX0, conflicts with PWMH1 */
-                                                         1 5 0x1 0x0    /* PB5 periph A GRX1, conflicts with PWML1 */
+                                                         AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB5 periph A GRX1, conflicts with PWML1 */
-                                                         1 6 0x1 0x0    /* PB6 periph A GRX2, conflicts with TD1 */
+                                                         AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB6 periph A GRX2, conflicts with TD1 */
-                                                         1 7 0x1 0x0>;  /* PB7 periph A GRX3, conflicts with RK1 */
+                                                         AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB7 periph A GRX3, conflicts with RK1 */
                                        };
                                        pinctrl_macb0_data_gmii: macb0_data_gmii {
                                                atmel,pins =
-                                                        <1 19 0x2 0x0   /* PB19 periph B GTX4, conflicts with MCI1_CDA */
+                                                        <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB19 periph B GTX4, conflicts with MCI1_CDA */
-                                                         1 20 0x2 0x0   /* PB20 periph B GTX5, conflicts with MCI1_DA0 */
+                                                         AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB20 periph B GTX5, conflicts with MCI1_DA0 */
-                                                         1 21 0x2 0x0   /* PB21 periph B GTX6, conflicts with MCI1_DA1 */
+                                                         AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB21 periph B GTX6, conflicts with MCI1_DA1 */
-                                                         1 22 0x2 0x0   /* PB22 periph B GTX7, conflicts with MCI1_DA2 */
+                                                         AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB22 periph B GTX7, conflicts with MCI1_DA2 */
-                                                         1 23 0x2 0x0   /* PB23 periph B GRX4, conflicts with MCI1_DA3 */
+                                                         AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB23 periph B GRX4, conflicts with MCI1_DA3 */
-                                                         1 24 0x2 0x0   /* PB24 periph B GRX5, conflicts with MCI1_CK */
+                                                         AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB24 periph B GRX5, conflicts with MCI1_CK */
-                                                         1 25 0x2 0x0   /* PB25 periph B GRX6, conflicts with SCK1 */
+                                                         AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB25 periph B GRX6, conflicts with SCK1 */
-                                                         1 26 0x2 0x0>; /* PB26 periph B GRX7, conflicts with CTS1 */
+                                                         AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB26 periph B GRX7, conflicts with CTS1 */
                                        };
                                        pinctrl_macb0_signal_rgmii: macb0_signal_rgmii {
                                                atmel,pins =
-                                                        <1 8 0x1 0x0    /* PB8 periph A GTXCK, conflicts with PWMH2 */
+                                                        <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB8 periph A GTXCK, conflicts with PWMH2 */
-                                                         1 9 0x1 0x0    /* PB9 periph A GTXEN, conflicts with PWML2 */
+                                                         AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB9 periph A GTXEN, conflicts with PWML2 */
-                                                         1 11 0x1 0x0   /* PB11 periph A GRXCK, conflicts with RD1 */
+                                                         AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB11 periph A GRXCK, conflicts with RD1 */
-                                                         1 13 0x1 0x0   /* PB13 periph A GRXER, conflicts with PWML3 */
+                                                         AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB13 periph A GRXER, conflicts with PWML3 */
-                                                         1 16 0x1 0x0   /* PB16 periph A GMDC */
+                                                         AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB16 periph A GMDC */
-                                                         1 17 0x1 0x0   /* PB17 periph A GMDIO */
+                                                         AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB17 periph A GMDIO */
-                                                         1 18 0x1 0x0>; /* PB18 periph A G125CK */
+                                                         AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A G125CK */
                                        };
                                        pinctrl_macb0_signal_gmii: macb0_signal_gmii {
                                                atmel,pins =
-                                                        <1 9 0x1 0x0    /* PB9 periph A GTXEN, conflicts with PWML2 */
+                                                        <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB9 periph A GTXEN, conflicts with PWML2 */
-                                                         1 10 0x1 0x0   /* PB10 periph A GTXER, conflicts with RF1 */
+                                                         AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB10 periph A GTXER, conflicts with RF1 */
-                                                         1 11 0x1 0x0   /* PB11 periph A GRXCK, conflicts with RD1 */
+                                                         AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB11 periph A GRXCK, conflicts with RD1 */
-                                                         1 12 0x1 0x0   /* PB12 periph A GRXDV, conflicts with PWMH3 */
+                                                         AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB12 periph A GRXDV, conflicts with PWMH3 */
-                                                         1 13 0x1 0x0   /* PB13 periph A GRXER, conflicts with PWML3 */
+                                                         AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB13 periph A GRXER, conflicts with PWML3 */
-                                                         1 14 0x1 0x0   /* PB14 periph A GCRS, conflicts with CANRX1 */
+                                                         AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB14 periph A GCRS, conflicts with CANRX1 */
-                                                         1 15 0x1 0x0   /* PB15 periph A GCOL, conflicts with CANTX1 */
+                                                         AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB15 periph A GCOL, conflicts with CANTX1 */
-                                                         1 16 0x1 0x0   /* PB16 periph A GMDC */
+                                                         AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB16 periph A GMDC */
-                                                         1 17 0x1 0x0   /* PB17 periph A GMDIO */
+                                                         AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB17 periph A GMDIO */
-                                                         1 27 0x2 0x0>; /* PB27 periph B G125CKO */
+                                                         AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB27 periph B G125CKO */
                                        };
                                };
@@ -606,252 +620,251 @@
                                macb1 {
                                        pinctrl_macb1_rmii: macb1_rmii-0 {
                                                atmel,pins =
-                                                        <2 0 0x1 0x0    /* PC0 periph A ETX0, conflicts with TIOA3 */
+                                                        <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC0 periph A ETX0, conflicts with TIOA3 */
-                                                         2 1 0x1 0x0    /* PC1 periph A ETX1, conflicts with TIOB3 */
+                                                         AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC1 periph A ETX1, conflicts with TIOB3 */
-                                                         2 2 0x1 0x0    /* PC2 periph A ERX0, conflicts with TCLK3 */
+                                                         AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC2 periph A ERX0, conflicts with TCLK3 */
-                                                         2 3 0x1 0x0    /* PC3 periph A ERX1, conflicts with TIOA4 */
+                                                         AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC3 periph A ERX1, conflicts with TIOA4 */
-                                                         2 4 0x1 0x0    /* PC4 periph A ETXEN, conflicts with TIOB4 */
+                                                         AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC4 periph A ETXEN, conflicts with TIOB4 */
-                                                         2 5 0x1 0x0    /* PC5 periph A ECRSDV,conflicts with TCLK4 */
+                                                         AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC5 periph A ECRSDV,conflicts with TCLK4 */
-                                                         2 6 0x1 0x0    /* PC6 periph A ERXER, conflicts with TIOA5 */
+                                                         AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC6 periph A ERXER, conflicts with TIOA5 */
-                                                         2 7 0x1 0x0    /* PC7 periph A EREFCK, conflicts with TIOB5 */
+                                                         AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC7 periph A EREFCK, conflicts with TIOB5 */
-                                                         2 8 0x1 0x0    /* PC8 periph A EMDC, conflicts with TCLK5 */
+                                                         AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC8 periph A EMDC, conflicts with TCLK5 */
-                                                         2 9 0x1 0x0>;  /* PC9 periph A EMDIO  */
+                                                         AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PC9 periph A EMDIO  */
                                        };
                                };
                                mmc0 {
                                        pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
                                                atmel,pins =
-                                                        <3 9 0x1 0x0    /* PD9 periph A MCI0_CK */
+                                                        <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PD9 periph A MCI0_CK */
-                                                         3 0 0x1 0x1    /* PD0 periph A MCI0_CDA with pullup */
+                                                         AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */
-                                                         3 1 0x1 0x1>;  /* PD1 periph A MCI0_DA0 with pullup */
+                                                         AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;       /* PD1 periph A MCI0_DA0 with pullup */
                                        };
                                        pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
                                                atmel,pins =
-                                                        <3 2 0x1 0x1    /* PD2 periph A MCI0_DA1 with pullup */
+                                                        <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A MCI0_DA1 with pullup */
-                                                         3 3 0x1 0x1    /* PD3 periph A MCI0_DA2 with pullup */
+                                                         AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD3 periph A MCI0_DA2 with pullup */
-                                                         3 4 0x1 0x1>;  /* PD4 periph A MCI0_DA3 with pullup */
+                                                         AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;       /* PD4 periph A MCI0_DA3 with pullup */
                                        };
                                        pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
                                                atmel,pins =
-                                                        <3 5 0x1 0x1    /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */
+                                                        <AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */
-                                                         3 6 0x1 0x1    /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */
+                                                         AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */
-                                                         3 7 0x1 0x1    /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */
+                                                         AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */
-                                                         3 8 0x1 0x1>;  /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */
+                                                         AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;       /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */
                                        };
                                };
                                mmc1 {
                                        pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
                                                atmel,pins =
-                                                        <1 24 0x1 0x0   /* PB24 periph A MCI1_CK, conflicts with GRX5 */
+                                                        <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB24 periph A MCI1_CK, conflicts with GRX5 */
-                                                         1 19 0x1 0x1   /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */
+                                                         AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */
-                                                         1 20 0x1 0x1>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */
+                                                         AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */
                                        };
                                        pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
                                                atmel,pins =
-                                                        <1 21 0x1 0x1   /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */
+                                                        <AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */
-                                                         1 22 0x1 0x1   /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */
+                                                         AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */
-                                                         1 23 0x1 0x1>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */
+                                                         AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */
                                        };
                                };
                                mmc2 {
                                        pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 {
                                                atmel,pins =
-                                                        <2 15 0x1 0x0   /* PC15 periph A MCI2_CK, conflicts with PCK2 */
+                                                        <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC15 periph A MCI2_CK, conflicts with PCK2 */
-                                                         2 10 0x1 0x1   /* PC10 periph A MCI2_CDA with pullup */
+                                                         AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PC10 periph A MCI2_CDA with pullup */
-                                                         2 11 0x1 0x1>; /* PC11 periph A MCI2_DA0 with pullup */
+                                                         AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PC11 periph A MCI2_DA0 with pullup */
                                        };
                                        pinctrl_mmc2_dat1_3: mmc2_dat1_3 {
                                                atmel,pins =
-                                                        <2 12 0x1 0x0   /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */
+                                                        <AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */
-                                                         2 13 0x1 0x0   /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */
+                                                         AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */
-                                                         2 14 0x1 0x0>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */
+                                                         AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */
                                        };
                                };
                                nand0 {
                                        pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
                                                atmel,pins =
-                                                        <4 21 0x1 0x1   /* PE21 periph A with pullup */
+                                                        <AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PE21 periph A with pullup */
-                                                         4 22 0x1 0x1>; /* PE22 periph A with pullup */
+                                                         AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PE22 periph A with pullup */
                                        };
                                };
-                                pioA: gpio@fffff200 {
-                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-                                        reg = <0xfffff200 0x100>;
-                                        interrupts = <6 4 1>;
-                                        #gpio-cells = <2>;
-                                        gpio-controller;
-                                        interrupt-controller;
-                                        #interrupt-cells = <2>;
-                                };
-                                pioB: gpio@fffff400 {
-                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-                                        reg = <0xfffff400 0x100>;
-                                        interrupts = <7 4 1>;
-                                        #gpio-cells = <2>;
-                                        gpio-controller;
-                                        interrupt-controller;
-                                        #interrupt-cells = <2>;
-                                };
-                                pioC: gpio@fffff600 {
-                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-                                        reg = <0xfffff600 0x100>;
-                                        interrupts = <8 4 1>;
-                                        #gpio-cells = <2>;
-                                        gpio-controller;
-                                        interrupt-controller;
-                                        #interrupt-cells = <2>;
-                                };
-                                pioD: gpio@fffff800 {
-                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-                                        reg = <0xfffff800 0x100>;
-                                        interrupts = <9 4 1>;
-                                        #gpio-cells = <2>;
-                                        gpio-controller;
-                                        interrupt-controller;
-                                        #interrupt-cells = <2>;
-                                };
-                                pioE: gpio@fffffa00 {
-                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-                                        reg = <0xfffffa00 0x100>;
-                                        interrupts = <10 4 1>;
-                                        #gpio-cells = <2>;
-                                        gpio-controller;
-                                        interrupt-controller;
-                                        #interrupt-cells = <2>;
-                                };
                                spi0 {
                                        pinctrl_spi0: spi0-0 {
                                                atmel,pins =
-                                                        <3 10 0x1 0x0   /* PD10 periph A SPI0_MISO pin */
+                                                        <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD10 periph A SPI0_MISO pin */
-                                                         3 11 0x1 0x0   /* PD11 periph A SPI0_MOSI pin */
+                                                         AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD11 periph A SPI0_MOSI pin */
-                                                         3 12 0x1 0x0   /* PD12 periph A SPI0_SPCK pin */
+                                                         AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A SPI0_SPCK pin */
-                                                         3 13 0x0 0x0>; /* PD13 GPIO SPI0_NPCS0 pin */
                                        };
                                };
                                spi1 {
                                        pinctrl_spi1: spi1-0 {
                                                atmel,pins =
-                                                        <2 22 0x1 0x0   /* PC22 periph A SPI1_MISO pin */
+                                                        <AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC22 periph A SPI1_MISO pin */
-                                                         2 23 0x1 0x0   /* PC23 periph A SPI1_MOSI pin */
+                                                         AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC23 periph A SPI1_MOSI pin */
-                                                         2 24 0x1 0x0   /* PC24 periph A SPI1_SPCK pin */
+                                                         AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC24 periph A SPI1_SPCK pin */
-                                                         2 25 0x0 0x0>; /* PC25 GPIO SPI1_NPCS0 pin */
                                        };
                                };
                                ssc0 {
                                        pinctrl_ssc0_tx: ssc0_tx {
                                                atmel,pins =
-                                                        <2 16 0x1 0x0   /* PC16 periph A TK0 */
+                                                        <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC16 periph A TK0 */
-                                                         2 17 0x1 0x0   /* PC17 periph A TF0 */
+                                                         AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC17 periph A TF0 */
-                                                         2 18 0x1 0x0>; /* PC18 periph A TD0 */
+                                                         AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC18 periph A TD0 */
                                        };
                                        pinctrl_ssc0_rx: ssc0_rx {
                                                atmel,pins =
-                                                        <2 19 0x1 0x0   /* PC19 periph A RK0 */
+                                                        <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC19 periph A RK0 */
-                                                         2 20 0x1 0x0   /* PC20 periph A RF0 */
+                                                         AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC20 periph A RF0 */
-                                                         2 21 0x1 0x0>; /* PC21 periph A RD0 */
+                                                         AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC21 periph A RD0 */
                                        };
                                };
                                ssc1 {
                                        pinctrl_ssc1_tx: ssc1_tx {
                                                atmel,pins =
-                                                        <1 2 0x2 0x0    /* PB2 periph B TK1, conflicts with GTX2 */
+                                                        <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE    /* PB2 periph B TK1, conflicts with GTX2 */
-                                                         1 3 0x2 0x0    /* PB3 periph B TF1, conflicts with GTX3 */
+                                                         AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE    /* PB3 periph B TF1, conflicts with GTX3 */
-                                                         1 6 0x2 0x0>;  /* PB6 periph B TD1, conflicts with TD1 */
+                                                         AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PB6 periph B TD1, conflicts with TD1 */
                                        };
                                        pinctrl_ssc1_rx: ssc1_rx {
                                                atmel,pins =
-                                                        <1 7 0x2 0x0    /* PB7 periph B RK1, conflicts with EREFCK */
+                                                        <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE    /* PB7 periph B RK1, conflicts with EREFCK */
-                                                         1 10 0x2 0x0   /* PB10 periph B RF1, conflicts with GTXER */
+                                                         AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB10 periph B RF1, conflicts with GTXER */
-                                                         1 11 0x2 0x0>; /* PB11 periph B RD1, conflicts with GRXCK */
+                                                         AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB11 periph B RD1, conflicts with GRXCK */
                                        };
                                };
                                uart0 {
                                        pinctrl_uart0: uart0-0 {
                                                atmel,pins =
-                                                        <2 29 0x1 0x0   /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */
+                                                        <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */
-                                                         2 30 0x1 0x1>; /* PC30 periph A with pullup, conflicts with ISI_PCK */
+                                                         AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PC30 periph A with pullup, conflicts with ISI_PCK */
                                        };
                                };
                                uart1 {
                                        pinctrl_uart1: uart1-0 {
                                                atmel,pins =
-                                                        <0 30 0x2 0x0   /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */
+                                                        <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */
-                                                         0 31 0x2 0x1>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */
+                                                         AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;      /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */
                                        };
                                };
                                usart0 {
                                        pinctrl_usart0: usart0-0 {
                                                atmel,pins =
-                                                        <3 17 0x1 0x0   /* PD17 periph A */
+                                                        <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD17 periph A */
-                                                         3 18 0x1 0x1>; /* PD18 periph A with pullup */
+                                                         AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PD18 periph A with pullup */
                                        };
                                        pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
                                                atmel,pins =
-                                                        <3 15 0x1 0x0   /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */
+                                                        <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */
-                                                         3 16 0x1 0x0>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */
+                                                         AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */
                                        };
                                };
                                usart1 {
                                        pinctrl_usart1: usart1-0 {
                                                atmel,pins =
-                                                        <1 28 0x1 0x0   /* PB28 periph A */
+                                                        <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB28 periph A */
-                                                         1 29 0x1 0x1>; /* PB29 periph A with pullup */
+                                                         AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PB29 periph A with pullup */
                                        };
                                        pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
                                                atmel,pins =
-                                                        <1 26 0x1 0x0   /* PB26 periph A, conflicts with GRX7 */
+                                                        <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB26 periph A, conflicts with GRX7 */
-                                                         1 27 0x1 0x0>; /* PB27 periph A, conflicts with G125CKO */
+                                                         AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A, conflicts with G125CKO */
                                        };
                                };
                                usart2 {
                                        pinctrl_usart2: usart2-0 {
                                                atmel,pins =
-                                                        <4 25 0x2 0x0   /* PE25 periph B, conflicts with A25 */
+                                                        <AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PE25 periph B, conflicts with A25 */
-                                                         4 26 0x2 0x1>; /* PE26 periph B with pullup, conflicts NCS0 */
+                                                         AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;      /* PE26 periph B with pullup, conflicts NCS0 */
                                        };
                                        pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
                                                atmel,pins =
-                                                        <4 23 0x2 0x0   /* PE23 periph B, conflicts with A23 */
+                                                        <AT91_PIOE 23 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PE23 periph B, conflicts with A23 */
-                                                         4 24 0x2 0x0>; /* PE24 periph B, conflicts with A24 */
+                                                         AT91_PIOE 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE24 periph B, conflicts with A24 */
                                        };
                                };
                                usart3 {
                                        pinctrl_usart3: usart3-0 {
                                                atmel,pins =
-                                                        <4 18 0x2 0x0   /* PE18 periph B, conflicts with A18 */
+                                                        <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PE18 periph B, conflicts with A18 */
-                                                         4 19 0x2 0x1>; /* PE19 periph B with pullup, conflicts with A19 */
+                                                         AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;      /* PE19 periph B with pullup, conflicts with A19 */
                                        };
                                        pinctrl_usart3_rts_cts: usart3_rts_cts-0 {
                                                atmel,pins =
-                                                        <4 16 0x2 0x0   /* PE16 periph B, conflicts with A16 */
+                                                        <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PE16 periph B, conflicts with A16 */
-                                                         4 17 0x2 0x0>; /* PE17 periph B, conflicts with A17 */
+                                                         AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE17 periph B, conflicts with A17 */
                                        };
                                };
+                                pioA: gpio@fffff200 {
+                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff200 0x100>;
+                                        interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+                                pioB: gpio@fffff400 {
+                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff400 0x100>;
+                                        interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+                                pioC: gpio@fffff600 {
+                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff600 0x100>;
+                                        interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+                                pioD: gpio@fffff800 {
+                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff800 0x100>;
+                                        interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+                                pioE: gpio@fffffa00 {
+                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        reg = <0xfffffa00 0x100>;
+                                        interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
                        };
                        pmc: pmc@fffffc00 {
@@ -867,7 +880,7 @@
                        pit: timer@fffffe30 {
                                compatible = "atmel,at91sam9260-pit";
                                reg = <0xfffffe30 0xf>;
-                                interrupts = <3 4 5>;
+                                interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
                        };
                        watchdog@fffffe40 {
@@ -879,7 +892,7 @@
                        rtc@fffffeb0 {
                                compatible = "atmel,at91rm9200-rtc";
                                reg = <0xfffffeb0 0x30>;
-                                interrupts = <1 4 7>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                        };
                };
@@ -889,7 +902,7 @@
                        compatible = "atmel,at91sam9rl-udc";
                        reg = <0x00500000 0x100000
                               0xf8030000 0x4000>;
-                        interrupts = <33 4 2>;
+                        interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>;
                        status = "disabled";
                        ep0 {
@@ -1001,14 +1014,14 @@
                usb1: ohci@00600000 {
                        compatible = "atmel,at91rm9200-ohci", "usb-ohci";
                        reg = <0x00600000 0x100000>;
-                        interrupts = <32 4 2>;
+                        interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
                        status = "disabled";
                };
                usb2: ehci@00700000 {
                        compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
                        reg = <0x00700000 0x100000>;
-                        interrupts = <32 4 2>;
+                        interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
                        status = "disabled";
                };
@@ -1024,7 +1037,7 @@
                                0xffffc000 0x00000070   /* NFC HSMC regs */
                                0x00200000 0x00100000   /* NFC SRAM banks */
                                >;
-                        interrupts = <5 4 6>;
+                        interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
                        atmel,nand-addr-offset = <21>;
                        atmel,nand-cmd-offset = <22>;
                        pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/sama5d31ek.dts b/arch/arm/boot/dts/sama5d31ek.dts
index fa5d216f1db7..027bac7510b6 100644
--- a/arch/arm/boot/dts/sama5d31ek.dts
+++ b/arch/arm/boot/dts/sama5d31ek.dts
@@ -7,8 +7,8 @@
 * Licensed under GPLv2 or later.
 */
 /dts-v1/;
-/include/ "sama5d3xmb.dtsi"
+#include "sama5d3xmb.dtsi"
-/include/ "sama5d3xdm.dtsi"
+#include "sama5d3xdm.dtsi"
 / {
        model = "Atmel SAMA5D31-EK";
@@ -41,7 +41,7 @@
        leds {
                d3 {
                        label = "d3";
-                        gpios = <&pioE 24 0>;
+                        gpios = <&pioE 24 GPIO_ACTIVE_HIGH>;
                };
        };
diff --git a/arch/arm/boot/dts/sama5d33ek.dts b/arch/arm/boot/dts/sama5d33ek.dts
index c38c9433d7a5..99bd0c8e0471 100644
--- a/arch/arm/boot/dts/sama5d33ek.dts
+++ b/arch/arm/boot/dts/sama5d33ek.dts
@@ -7,8 +7,8 @@
 * Licensed under GPLv2 or later.
 */
 /dts-v1/;
-/include/ "sama5d3xmb.dtsi"
+#include "sama5d3xmb.dtsi"
-/include/ "sama5d3xdm.dtsi"
+#include "sama5d3xdm.dtsi"
 / {
        model = "Atmel SAMA5D33-EK";
diff --git a/arch/arm/boot/dts/sama5d34ek.dts b/arch/arm/boot/dts/sama5d34ek.dts
index 6bebfcdcb1d1..fb8ee11cf282 100644
--- a/arch/arm/boot/dts/sama5d34ek.dts
+++ b/arch/arm/boot/dts/sama5d34ek.dts
@@ -7,8 +7,8 @@
 * Licensed under GPLv2 or later.
 */
 /dts-v1/;
-/include/ "sama5d3xmb.dtsi"
+#include "sama5d3xmb.dtsi"
-/include/ "sama5d3xdm.dtsi"
+#include "sama5d3xdm.dtsi"
 / {
        model = "Atmel SAMA5D34-EK";
@@ -51,7 +51,7 @@
        leds {
                d3 {
                        label = "d3";
-                        gpios = <&pioE 24 0>;
+                        gpios = <&pioE 24 GPIO_ACTIVE_HIGH>;
                };
        };
diff --git a/arch/arm/boot/dts/sama5d35ek.dts b/arch/arm/boot/dts/sama5d35ek.dts
index a488fc4e9777..509a53d9cc7b 100644
--- a/arch/arm/boot/dts/sama5d35ek.dts
+++ b/arch/arm/boot/dts/sama5d35ek.dts
@@ -7,7 +7,7 @@
 * Licensed under GPLv2 or later.
 */
 /dts-v1/;
-/include/ "sama5d3xmb.dtsi"
+#include "sama5d3xmb.dtsi"
 / {
        model = "Atmel SAMA5D35-EK";
@@ -48,7 +48,7 @@
                pb_user1 {
                        label = "pb_user1";
-                        gpios = <&pioE 27 0>;
+                        gpios = <&pioE 27 GPIO_ACTIVE_HIGH>;
                        linux,code = <0x100>;
                        gpio-key,wakeup;
                };
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
index b336e7787cb3..1f8050813a54 100644
--- a/arch/arm/boot/dts/sama5d3xcm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
@@ -6,7 +6,7 @@
 *
 * Licensed under GPLv2 or later.
 */
-/include/ "sama5d3.dtsi"
+#include "sama5d3.dtsi"
 / {
        compatible = "atmel,samad3xcm", "atmel,sama5d3", "atmel,sama5";
@@ -89,7 +89,7 @@
                d2 {
                        label = "d2";
-                        gpios = <&pioE 25 1>;   /* PE25, conflicts with A25, RXD2 */
+                        gpios = <&pioE 25 GPIO_ACTIVE_LOW>;     /* PE25, conflicts with A25, RXD2 */
                };
        };
 };
diff --git a/arch/arm/boot/dts/sama5d3xdm.dtsi b/arch/arm/boot/dts/sama5d3xdm.dtsi
index 4b8830eb2060..1c296d6b2f2a 100644
--- a/arch/arm/boot/dts/sama5d3xdm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xdm.dtsi
@@ -33,7 +33,7 @@
                                board {
                                        pinctrl_qt1070_irq: qt1070_irq {
                                                atmel,pins =
-                                                        <4 31 0x0 0x5>; /* PE31 GPIO with pull up deglith */
+                                                        <AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PE31 GPIO with pull up deglith */
                                        };
                                };
                        };
diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi
index 661d7ca9c309..8a9e05d8a4b8 100644
--- a/arch/arm/boot/dts/sama5d3xmb.dtsi
+++ b/arch/arm/boot/dts/sama5d3xmb.dtsi
@@ -6,7 +6,7 @@
 *
 * Licensed under GPLv2 or later.
 */
-/include/ "sama5d3xcm.dtsi"
+#include "sama5d3xcm.dtsi"
 / {
        compatible = "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
@@ -20,7 +20,7 @@
                                slot@0 {
                                        reg = <0>;
                                        bus-width = <4>;
-                                        cd-gpios = <&pioD 17 0>;
+                                        cd-gpios = <&pioD 17 GPIO_ACTIVE_HIGH>;
                                };
                        };
@@ -62,7 +62,7 @@
                                slot@0 {
                                        reg = <0>;
                                        bus-width = <4>;
-                                        cd-gpios = <&pioD 18 0>;
+                                        cd-gpios = <&pioD 18 GPIO_ACTIVE_HIGH>;
                                };
                        };
@@ -87,32 +87,32 @@
                                board {
                                        pinctrl_mmc0_cd: mmc0_cd {
                                                atmel,pins =
-                                                        <3 17 0x0 0x5>; /* PD17 GPIO with pullup deglitch */
+                                                        <AT91_PIOD 17 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD17 GPIO with pullup deglitch */
                                        };
                                        pinctrl_mmc1_cd: mmc1_cd {
                                                atmel,pins =
-                                                        <3 18 0x0 0x5>; /* PD18 GPIO with pullup deglitch */
+                                                        <AT91_PIOD 18 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD18 GPIO with pullup deglitch */
                                        };
                                        pinctrl_pck0_as_audio_mck: pck0_as_audio_mck {
                                                atmel,pins =
-                                                        <3 30 0x2 0x0>; /* PD30 periph B */
+                                                        <AT91_PIOD 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD30 periph B */
                                        };
                                        pinctrl_isi_reset: isi_reset-0 {
                                                atmel,pins =
-                                                        <4 24 0x0 0x0>;   /* PE24 gpio */
+                                                        <AT91_PIOE 24 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;   /* PE24 gpio */
                                        };
                                        pinctrl_isi_power: isi_power-0 {
                                                atmel,pins =
-                                                        <4 29 0x0 0x0>; /* PE29 gpio */
+                                                        <AT91_PIOE 29 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; /* PE29 gpio */
                                        };
                                        pinctrl_usba_vbus: usba_vbus {
                                                atmel,pins =
-                                                        <3 29 0x0 0x4>; /* PD29 GPIO with deglitch */
+                                                        <AT91_PIOD 29 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; /* PD29 GPIO with deglitch */
                                        };
                                };
                        };
@@ -127,7 +127,7 @@
                };
                usb0: gadget@00500000 {
-                        atmel,vbus-gpio = <&pioD 29 0>;
+                        atmel,vbus-gpio = <&pioD 29 GPIO_ACTIVE_HIGH>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_usba_vbus>;
                        status = "okay";
@@ -135,9 +135,9 @@
                usb1: ohci@00600000 {
                        num-ports = <3>;
-                        atmel,vbus-gpio = <&pioD 25 0
+                        atmel,vbus-gpio = <&pioD 25 GPIO_ACTIVE_HIGH
-                                           &pioD 26 1
+                                           &pioD 26 GPIO_ACTIVE_LOW
-                                           &pioD 27 1
+                                           &pioD 27 GPIO_ACTIVE_LOW
                                          >;
                        status = "okay";
                };
diff --git a/arch/arm/boot/dts/sh7372.dtsi b/arch/arm/boot/dts/sh7372.dtsi
index 677fc603f8b3..7bf020ecadf5 100644
--- a/arch/arm/boot/dts/sh7372.dtsi
+++ b/arch/arm/boot/dts/sh7372.dtsi
@@ -14,8 +14,13 @@
        compatible = "renesas,sh7372";
        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
                cpu@0 {
                        compatible = "arm,cortex-a8";
+                        device_type = "cpu";
+                        reg = <0x0>;
                };
        };
 };
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
index 5972abb55f9c..b6f759e830ed 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
@@ -18,6 +18,19 @@
        model = "KZM-A9-GT";
        compatible = "renesas,kzm9g-reference", "renesas,sh73a0";
+        cpus {
+                cpu@0 {
+                        cpu0-supply = <&vdd_dvfs>;
+                        operating-points = <
+                                /* kHz  uV */
+                                1196000 1315000
+                                 598000 1175000
+                                 398667 1065000
+                        >;
+                        voltage-tolerance = <1>; /* 1% */
+                };
+        };
        chosen {
                bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel earlyprintk=sh-sci.4,115200";
        };
@@ -59,6 +72,79 @@
        };
 };
+&i2c0 {
+        as3711@40 {
+                compatible = "ams,as3711";
+                reg = <0x40>;
+                regulators {
+                        vdd_dvfs: sd1 {
+                                regulator-name = "1.315V CPU";
+                                regulator-min-microvolt = <1050000>;
+                                regulator-max-microvolt = <1350000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        sd2 {
+                                regulator-name = "1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        sd4 {
+                                regulator-name = "1.215V";
+                                regulator-min-microvolt = <1215000>;
+                                regulator-max-microvolt = <1235000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        ldo2 {
+                                regulator-name = "2.8V CPU";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        ldo3 {
+                                regulator-name = "3.0V CPU";
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        ldo4 {
+                                regulator-name = "2.8V";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        ldo5 {
+                                regulator-name = "2.8V #2";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        ldo7 {
+                                regulator-name = "1.15V CPU";
+                                regulator-min-microvolt = <1150000>;
+                                regulator-max-microvolt = <1150000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        ldo8 {
+                                regulator-name = "1.15V CPU #2";
+                                regulator-min-microvolt = <1150000>;
+                                regulator-max-microvolt = <1150000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                };
+        };
+};
 &mmcif {
        bus-width = <8>;
        vmmc-supply = <&reg_1p8v>;
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index ec40bf78289e..b97750256003 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -119,7 +119,7 @@
                              0 32 0x4>;
        };
-        i2c0: i2c@0xe6820000 {
+        i2c0: i2c@e6820000 {
                #address-cells = <1>;
                #size-cells = <0>;
                compatible = "renesas,rmobile-iic";
@@ -131,7 +131,7 @@
                              0 170 0x4>;
        };
-        i2c1: i2c@0xe6822000 {
+        i2c1: i2c@e6822000 {
                #address-cells = <1>;
                #size-cells = <0>;
                compatible = "renesas,rmobile-iic";
@@ -143,7 +143,7 @@
                              0 54 0x4>;
        };
-        i2c2: i2c@0xe6824000 {
+        i2c2: i2c@e6824000 {
                #address-cells = <1>;
                #size-cells = <0>;
                compatible = "renesas,rmobile-iic";
@@ -155,7 +155,7 @@
                              0 174 0x4>;
        };
-        i2c3: i2c@0xe6826000 {
+        i2c3: i2c@e6826000 {
                #address-cells = <1>;
                #size-cells = <0>;
                compatible = "renesas,rmobile-iic";
@@ -167,7 +167,7 @@
                              0 186 0x4>;
        };
-        i2c4: i2c@0xe6828000 {
+        i2c4: i2c@e6828000 {
                #address-cells = <1>;
                #size-cells = <0>;
                compatible = "renesas,rmobile-iic";
@@ -179,7 +179,7 @@
                              0 190 0x4>;
        };
-        mmcif: mmcif@0x10010000 {
+        mmcif: mmcif@e6bd0000 {
                compatible = "renesas,sh-mmcif";
                reg = <0xe6bd0000 0x100>;
                interrupt-parent = <&gic>;
@@ -189,7 +189,7 @@
                status = "disabled";
        };
-        sdhi0: sdhi@0xee100000 {
+        sdhi0: sdhi@ee100000 {
                compatible = "renesas,r8a7740-sdhi";
                reg = <0xee100000 0x100>;
                interrupt-parent = <&gic>;
@@ -201,7 +201,7 @@
        };
        /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
-        sdhi1: sdhi@0xee120000 {
+        sdhi1: sdhi@ee120000 {
                compatible = "renesas,r8a7740-sdhi";
                reg = <0xee120000 0x100>;
                interrupt-parent = <&gic>;
@@ -212,7 +212,7 @@
                status = "disabled";
        };
-        sdhi2: sdhi@0xee140000 {
+        sdhi2: sdhi@ee140000 {
                compatible = "renesas,r8a7740-sdhi";
                reg = <0xee140000 0x100>;
                interrupt-parent = <&gic>;
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
index db5db24fd544..49824be66845 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/snowball.dts
@@ -10,7 +10,7 @@
 */
 /dts-v1/;
-/include/ "dbx5x0.dtsi"
+#include "dbx5x0.dtsi"
 / {
        model = "Calao Systems Snowball platform with device tree";
@@ -22,12 +22,13 @@
        en_3v3_reg: en_3v3 {
                compatible = "regulator-fixed";
-                regulator-name = "en-3v3-fixed-supply";
+                regulator-name = "en-3v3-fixed-supply";
-                regulator-min-microvolt = <3300000>;
+                regulator-min-microvolt = <3300000>;
-                regulator-max-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
-                gpios = <&gpio0 26  0x4>; // 26
+                /* AB8500 GPIOs start from 1 - offset 25 is GPIO26. */
-                startup-delay-us = <5000>;
+                gpio = <&ab8500_gpio 25 0x4>;
-                enable-active-high;
+                startup-delay-us = <5000>;
+                enable-active-high;
        };
        gpio_keys {
@@ -82,7 +83,7 @@
                };
        };
-        soc-u9500 {
+        soc {
                sound {
                        compatible = "stericsson,snd-soc-mop500";
@@ -99,40 +100,13 @@
                        status = "okay";
                };
-                prcmu@80157000 {
-                        thermal@801573c0 {
-                                num-trips = <4>;
-                                trip0-temp = <70000>;
-                                trip0-type = "active";
-                                trip0-cdev-num = <1>;
-                                trip0-cdev-name0 = "thermal-cpufreq-0";
-                                trip1-temp = <75000>;
-                                trip1-type = "active";
-                                trip1-cdev-num = <1>;
-                                trip1-cdev-name0 = "thermal-cpufreq-0";
-                                trip2-temp = <80000>;
-                                trip2-type = "active";
-                                trip2-cdev-num = <1>;
-                                trip2-cdev-name0 = "thermal-cpufreq-0";
-                                trip3-temp = <85000>;
-                                trip3-type = "critical";
-                                trip3-cdev-num = <0>;
-                                status = "okay";
-                         };
-                };
                external-bus@50000000 {
                        status = "okay";
                        ethernet@0 {
                                compatible = "smsc,lan9115";
                                reg = <0 0x10000>;
-                                interrupts = <12 0x1>;
+                                interrupts = <12 IRQ_TYPE_EDGE_RISING>;
                                interrupt-parent = <&gpio4>;
                                vdd33a-supply = <&en_3v3_reg>;
                                vddvario-supply = <&db8500_vape_reg>;
@@ -146,13 +120,21 @@
                        };
                };
+                vmmci: regulator-gpio {
+                        gpios = <&gpio6 25 0x4>;
+                        enable-gpio = <&gpio7 4 0x4>;
+                        status = "okay";
+                };
                // External Micro SD slot
                sdi0_per1@80126000 {
                        arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <50000000>;
+                        max-frequency = <100000000>;
                        bus-width = <4>;
                        mmc-cap-mmc-highspeed;
                        vmmc-supply = <&ab8500_ldo_aux3_reg>;
+                        vqmmc-supply = <&vmmci>;
                        cd-gpios  = <&gpio6 26 0x4>; // 218
                        cd-inverted;
@@ -163,7 +145,7 @@
                // On-board eMMC
                sdi4_per2@80114000 {
                        arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <50000000>;
+                        max-frequency = <100000000>;
                        bus-width = <8>;
                        mmc-cap-mmc-highspeed;
                        vmmc-supply = <&ab8500_ldo_aux2_reg>;
@@ -197,15 +179,15 @@
                };
                i2c@80128000 {
-                        lp5521@0x33 {
+                        lp5521@33 {
                                // compatible = "lp5521";
                                reg = <0x33>;
                        };
-                        lp5521@0x34 {
+                        lp5521@34 {
                                // compatible = "lp5521";
                                reg = <0x34>;
                        };
-                        bh1780@0x29 {
+                        bh1780@29 {
                                // compatible = "rohm,bh1780gli";
                                reg = <0x33>;
                        };
@@ -298,6 +280,31 @@
                                };
                        };
+                        thermal@801573c0 {
+                                num-trips = <4>;
+                                trip0-temp = <70000>;
+                                trip0-type = "active";
+                                trip0-cdev-num = <1>;
+                                trip0-cdev-name0 = "thermal-cpufreq-0";
+                                trip1-temp = <75000>;
+                                trip1-type = "active";
+                                trip1-cdev-num = <1>;
+                                trip1-cdev-name0 = "thermal-cpufreq-0";
+                                trip2-temp = <80000>;
+                                trip2-type = "active";
+                                trip2-cdev-num = <1>;
+                                trip2-cdev-name0 = "thermal-cpufreq-0";
+                                trip3-temp = <85000>;
+                                trip3-type = "critical";
+                                trip3-cdev-num = <0>;
+                                status = "okay";
+                        };
                        ab8500 {
                                ab8500-gpio {
                                        compatible = "stericsson,ab8500-gpio";
@@ -316,7 +323,7 @@
                                                regulator-name = "V-MMC-SD";
                                        };
-                                        ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
+                                        ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
                                                regulator-name = "V-INTCORE";
                                        };
@@ -336,7 +343,7 @@
                                                regulator-name = "V-AMIC1";
                                        };
-                                        ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
+                                        ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
                                                regulator-name = "V-AMIC2";
                                        };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 16a6e13e08b4..bee62a2cf6d6 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -23,6 +23,7 @@
        aliases {
                ethernet0 = &gmac0;
+                ethernet1 = &gmac1;
                serial0 = &uart0;
                serial1 = &uart1;
                timer0 = &timer0;
@@ -94,6 +95,12 @@
                                                compatible = "fixed-clock";
                                        };
+                                        f2s_periph_ref_clk: f2s_periph_ref_clk {
+                                                #clock-cells = <0>;
+                                                compatible = "fixed-clock";
+                                                clock-frequency = <10000000>;
+                                        };
                                        main_pll: main_pll {
                                                #address-cells = <1>;
                                                #size-cells = <0>;
@@ -235,16 +242,222 @@
                                                        reg = <0xD4>;
                                                };
                                        };
+                                mpu_periph_clk: mpu_periph_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&mpuclk>;
+                                        fixed-divider = <4>;
+                                        };
+                                mpu_l2_ram_clk: mpu_l2_ram_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&mpuclk>;
+                                        fixed-divider = <2>;
+                                        };
+                                l4_main_clk: l4_main_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&mainclk>;
+                                        clk-gate = <0x60 0>;
+                                        };
+                                l3_main_clk: l3_main_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&mainclk>;
+                                        };
+                                l3_mp_clk: l3_mp_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&mainclk>;
+                                        div-reg = <0x64 0 2>;
+                                        clk-gate = <0x60 1>;
+                                        };
+                                l3_sp_clk: l3_sp_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&mainclk>;
+                                        div-reg = <0x64 2 2>;
+                                };
+                                l4_mp_clk: l4_mp_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&mainclk>, <&per_base_clk>;
+                                        div-reg = <0x64 4 3>;
+                                        clk-gate = <0x60 2>;
+                                        };
+                                l4_sp_clk: l4_sp_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&mainclk>, <&per_base_clk>;
+                                        div-reg = <0x64 7 3>;
+                                        clk-gate = <0x60 3>;
+                                        };
+                                dbg_at_clk: dbg_at_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&dbg_base_clk>;
+                                        div-reg = <0x68 0 2>;
+                                        clk-gate = <0x60 4>;
+                                        };
+                                dbg_clk: dbg_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&dbg_base_clk>;
+                                        div-reg = <0x68 2 2>;
+                                        clk-gate = <0x60 5>;
+                                        };
+                                dbg_trace_clk: dbg_trace_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&dbg_base_clk>;
+                                        div-reg = <0x6C 0 3>;
+                                        clk-gate = <0x60 6>;
+                                        };
+                                dbg_timer_clk: dbg_timer_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&dbg_base_clk>;
+                                        clk-gate = <0x60 7>;
+                                        };
+                                cfg_clk: cfg_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&cfg_s2f_usr0_clk>;
+                                        clk-gate = <0x60 8>;
+                                        };
+                                s2f_user0_clk: s2f_user0_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&cfg_s2f_usr0_clk>;
+                                        clk-gate = <0x60 9>;
+                                        };
+                                emac_0_clk: emac_0_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&emac0_clk>;
+                                        clk-gate = <0xa0 0>;
+                                        };
+                                emac_1_clk: emac_1_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&emac1_clk>;
+                                        clk-gate = <0xa0 1>;
+                                        };
+                                usb_mp_clk: usb_mp_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&per_base_clk>;
+                                        clk-gate = <0xa0 2>;
+                                        div-reg = <0xa4 0 3>;
+                                        };
+                                spi_m_clk: spi_m_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&per_base_clk>;
+                                        clk-gate = <0xa0 3>;
+                                        div-reg = <0xa4 3 3>;
+                                        };
+                                can0_clk: can0_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&per_base_clk>;
+                                        clk-gate = <0xa0 4>;
+                                        div-reg = <0xa4 6 3>;
+                                        };
+                                can1_clk: can1_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&per_base_clk>;
+                                        clk-gate = <0xa0 5>;
+                                        div-reg = <0xa4 9 3>;
+                                        };
+                                gpio_db_clk: gpio_db_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&per_base_clk>;
+                                        clk-gate = <0xa0 6>;
+                                        div-reg = <0xa8 0 24>;
+                                        };
+                                s2f_user1_clk: s2f_user1_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&s2f_usr1_clk>;
+                                        clk-gate = <0xa0 7>;
+                                        };
+                                sdmmc_clk: sdmmc_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+                                        clk-gate = <0xa0 8>;
+                                        };
+                                nand_x_clk: nand_x_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+                                        clk-gate = <0xa0 9>;
+                                        };
+                                nand_clk: nand_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+                                        clk-gate = <0xa0 10>;
+                                        fixed-divider = <4>;
+                                        };
+                                qspi_clk: qspi_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
+                                        clk-gate = <0xa0 11>;
+                                        };
                                };
                        };
-                gmac0: stmmac@ff700000 {
+                gmac0: ethernet@ff700000 {
                        compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
                        reg = <0xff700000 0x2000>;
                        interrupts = <0 115 4>;
                        interrupt-names = "macirq";
                        mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
-                        phy-mode = "gmii";
+                        clocks = <&emac0_clk>;
+                        clock-names = "stmmaceth";
+                        status = "disabled";
+                };
+                gmac1: ethernet@ff702000 {
+                        compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
+                        reg = <0xff702000 0x2000>;
+                        interrupts = <0 120 4>;
+                        interrupt-names = "macirq";
+                        mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
+                        clocks = <&emac1_clk>;
+                        clock-names = "stmmaceth";
+                        status = "disabled";
                };
                L2: l2-cache@fffef000 {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts
index 2495958f1016..973999d2c697 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dts
@@ -32,6 +32,13 @@
                reg = <0x0 0x40000000>; /* 1GB */
        };
+        aliases {
+                /* this allow the ethaddr uboot environmnet variable contents
+                 * to be added to the gmac1 device tree blob.
+                 */
+                ethernet0 = &gmac1;
+        };
        soc {
                clkmgr@ffd04000 {
                        clocks {
@@ -41,6 +48,12 @@
                        };
                };
+                ethernet@ff702000 {
+                        phy-mode = "rgmii";
+                        phy-addr = <0xffffffff>; /* probe for phy addr */
+                        status = "okay";
+                };
                timer0@ffc08000 {
                        clock-frequency = <100000000>;
                };
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
index 0bf035d607f0..d1ec0cab2dee 100644
--- a/arch/arm/boot/dts/socfpga_vt.dts
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -41,6 +41,11 @@
                        };
                };
+                ethernet@ff700000 {
+                        phy-mode = "gmii";
+                        status = "okay";
+                };
                timer0@ffc08000 {
                        clock-frequency = <7000000>;
                };
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index 45597fd91050..4382547df58a 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -22,12 +22,14 @@
                cpu@0 {
                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
                        reg = <0>;
                        next-level-cache = <&L2>;
                };
                cpu@1 {
                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
                        reg = <1>;
                        next-level-cache = <&L2>;
                };
diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi
index c2a852d43c48..f0e3fcf8e323 100644
--- a/arch/arm/boot/dts/spear3xx.dtsi
+++ b/arch/arm/boot/dts/spear3xx.dtsi
@@ -17,8 +17,12 @@
        interrupt-parent = <&vic>;
        cpus {
-                cpu@0 {
+                #address-cells = <0>;
-                        compatible = "arm,arm926ejs";
+                #size-cells = <0>;
+                cpu {
+                        compatible = "arm,arm926ej-s";
+                        device_type = "cpu";
                };
        };
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
index 19f99dc4115e..9f60a7b6a42b 100644
--- a/arch/arm/boot/dts/spear600.dtsi
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -15,8 +15,12 @@
        compatible = "st,spear600";
        cpus {
-                cpu@0 {
+                #address-cells = <0>;
-                        compatible = "arm,arm926ejs";
+                #size-cells = <0>;
+                cpu {
+                        compatible = "arm,arm926ej-s";
+                        device_type = "cpu";
                };
        };
diff --git a/arch/arm/boot/dts/st-pincfg.h b/arch/arm/boot/dts/st-pincfg.h
new file mode 100644
index 000000000000..8c45d85ac13e
--- /dev/null
+++ b/arch/arm/boot/dts/st-pincfg.h
@@ -0,0 +1,71 @@
+#ifndef _ST_PINCFG_H_
+#define _ST_PINCFG_H_
+/* Alternate functions */
+#define ALT1    1
+#define ALT2    2
+#define ALT3    3
+#define ALT4    4
+#define ALT5    5
+#define ALT6    6
+#define ALT7    7
+/* Output enable */
+#define OE                      (1 << 27)
+/* Pull Up */
+#define PU                      (1 << 26)
+/* Open Drain */
+#define OD                      (1 << 26)
+#define RT                      (1 << 23)
+#define INVERTCLK               (1 << 22)
+#define CLKNOTDATA              (1 << 21)
+#define DOUBLE_EDGE             (1 << 20)
+#define CLK_A                   (0 << 18)
+#define CLK_B                   (1 << 18)
+#define CLK_C                   (2 << 18)
+#define CLK_D                   (3 << 18)
+/* User-frendly defines for Pin Direction */
+                /* oe = 0, pu = 0, od = 0 */
+#define IN                      (0)
+                /* oe = 0, pu = 1, od = 0 */
+#define IN_PU                   (PU)
+                /* oe = 1, pu = 0, od = 0 */
+#define OUT                     (OE)
+                /* oe = 1, pu = 0, od = 1 */
+#define BIDIR                   (OE | OD)
+                /* oe = 1, pu = 1, od = 1 */
+#define BIDIR_PU                (OE | PU | OD)
+/* RETIME_TYPE */
+/*
+ * B Mode
+ * Bypass retime with optional delay parameter
+ */
+#define BYPASS          (0)
+/*
+ * R0, R1, R0D, R1D modes
+ * single-edge data non inverted clock, retime data with clk
+ */
+#define SE_NICLK_IO     (RT)
+/*
+ * RIV0, RIV1, RIV0D, RIV1D modes
+ * single-edge data inverted clock, retime data with clk
+ */
+#define SE_ICLK_IO      (RT | INVERTCLK)
+/*
+ * R0E, R1E, R0ED, R1ED modes
+ * double-edge data, retime data with clk
+ */
+#define DE_IO           (RT | DOUBLE_EDGE)
+/*
+ * CIV0, CIV1 modes with inverted clock
+ * Retiming the clk pins will park clock & reduce the noise within the core.
+ */
+#define ICLK            (RT | CLKNOTDATA | INVERTCLK)
+/*
+ * CLK0, CLK1 modes with non-inverted clock
+ * Retiming the clk pins will park clock & reduce the noise within the core.
+ */
+#define NICLK           (RT | CLKNOTDATA)
+#endif /* _ST_PINCFG_H_ */
diff --git a/arch/arm/boot/dts/ste-nomadik-s8815.dts b/arch/arm/boot/dts/ste-nomadik-s8815.dts
index 6f82d9368948..16c3888b7b15 100644
--- a/arch/arm/boot/dts/ste-nomadik-s8815.dts
+++ b/arch/arm/boot/dts/ste-nomadik-s8815.dts
@@ -22,6 +22,49 @@
                };
        };
+        src@101e0000 {
+                /* These chrystal drivers are not used on this board */
+                disable-sxtalo;
+                disable-mxtalo;
+        };
+        pinctrl {
+                /* Hog CD pins */
+                pinctrl-names = "default";
+                pinctrl-0 = <&cd_default_mode>;
+                mmcsd-cd {
+                        cd_default_mode: cd_default {
+                                cd_default_cfg1 {
+                                        /* CD input GPIO */
+                                        ste,pins = "GPIO111_H21";
+                                        ste,input = <0>;
+                                };
+                                cd_default_cfg2 {
+                                        /* CD GPIO biasing */
+                                        ste,pins = "GPIO112_J21";
+                                        ste,output = <0>;
+                                };
+                        };
+                };
+                user-led {
+                        user_led_default_mode: user_led_default {
+                                user_led_default_cfg {
+                                        ste,pins = "GPIO2_C5";
+                                        ste,output = <1>;
+                                };
+                        };
+                };
+                user-button {
+                        user_button_default_mode: user_button_default {
+                                user_button_default_cfg {
+                                        ste,pins = "GPIO3_A4";
+                                        ste,input = <0>;
+                                };
+                        };
+                };
+        };
        /* Custom board node with GPIO pins to active etc */
        usb-s8815 {
                /* The S8815 is using this very GPIO pin for the SMSC91x IRQs */
@@ -33,4 +76,30 @@
                        gpios = <&gpio3 16 0x1>;
                };
        };
+        /* The user LED on the board is set up to be used for heartbeat */
+        leds {
+                compatible = "gpio-leds";
+                user-led {
+                        label = "user_led";
+                        gpios = <&gpio0 2 0x1>;
+                        default-state = "off";
+                        linux,default-trigger = "heartbeat";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&user_led_default_mode>;
+                };
+        };
+        /* User key mapped in as "escape" */
+        gpio-keys {
+                compatible = "gpio-keys";
+                user-button {
+                        label = "user_button";
+                        gpios = <&gpio0 3 0x1>;
+                        linux,code = <1>; /* KEY_ESC */
+                        gpio-key,wakeup;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&user_button_default_mode>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
index 4a4aab395141..a3acfa7b3dc9 100644
--- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
+++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
@@ -21,18 +21,23 @@
                cache-level = <2>;
        };
-        mtu0 {
+        mtu0: mtu@101e2000 {
                /* Nomadik system timer */
+                compatible = "st,nomadik-mtu";
                reg = <0x101e2000 0x1000>;
                interrupt-parent = <&vica>;
                interrupts = <4>;
+                clocks = <&timclk>, <&pclk>;
+                clock-names = "timclk", "apb_pclk";
        };
-        mtu1 {
+        mtu1: mtu@101e3000 {
                /* Secondary timer */
                reg = <0x101e3000 0x1000>;
                interrupt-parent = <&vica>;
                interrupts = <5>;
+                clocks = <&timclk>, <&pclk>;
+                clock-names = "timclk", "apb_pclk";
        };
        gpio0: gpio@101e4000 {
@@ -45,6 +50,7 @@
                gpio-controller;
                #gpio-cells = <2>;
                gpio-bank = <0>;
+                clocks = <&pclk>;
        };
        gpio1: gpio@101e5000 {
@@ -57,6 +63,7 @@
                gpio-controller;
                #gpio-cells = <2>;
                gpio-bank = <1>;
+                clocks = <&pclk>;
        };
        gpio2: gpio@101e6000 {
@@ -69,6 +76,7 @@
                gpio-controller;
                #gpio-cells = <2>;
                gpio-bank = <2>;
+                clocks = <&pclk>;
        };
        gpio3: gpio@101e7000 {
@@ -81,10 +89,544 @@
                gpio-controller;
                #gpio-cells = <2>;
                gpio-bank = <3>;
+                clocks = <&pclk>;
        };
        pinctrl {
-                compatible = "stericsson,nmk-pinctrl-stn8815";
+                compatible = "stericsson,stn8815-pinctrl";
+                /* Pin configurations */
+                uart0 {
+                        uart0_default_mux: uart0_mux {
+                                u0_default_mux {
+                                        ste,function = "u0";
+                                        ste,pins = "u0_a_1";
+                                };
+                        };
+                };
+                uart1 {
+                        uart1_default_mux: uart1_mux {
+                                u1_default_mux {
+                                        ste,function = "u1";
+                                        ste,pins = "u1_a_1";
+                                };
+                        };
+                };
+                mmcsd {
+                        mmcsd_default_mux: mmcsd_mux {
+                                mmcsd_default_mux {
+                                        ste,function = "mmcsd";
+                                        ste,pins = "mmcsd_a_1";
+                                };
+                        };
+                        mmcsd_default_mode: mmcsd_default {
+                                mmcsd_default_cfg1 {
+                                        /* MCCLK */
+                                        ste,pins = "GPIO8_B10";
+                                        ste,output = <0>;
+                                };
+                                mmcsd_default_cfg2 {
+                                        /* MCCMDDIR, MCDAT0DIR, MCDAT31DIR */
+                                        ste,pins = "GPIO10_C11", "GPIO15_A12",
+                                        "GPIO16_C13";
+                                        ste,output = <1>;
+                                };
+                                mmcsd_default_cfg3 {
+                                        /* MCCMD, MCDAT3-0, MCMSFBCLK */
+                                        ste,pins = "GPIO9_A10", "GPIO11_B11",
+                                        "GPIO12_A11", "GPIO13_C12",
+                                        "GPIO14_B12", "GPIO24_C15";
+                                        ste,input = <1>;
+                                };
+                        };
+                };
+                i2c0 {
+                        i2c0_default_mode: i2c0_default {
+                                i2c0_default_cfg {
+                                        ste,pins = "GPIO62_D3", "GPIO63_D2";
+                                        ste,input = <1>;
+                                };
+                        };
+                };
+                i2c1 {
+                        i2c1_default_mode: i2c1_default {
+                                i2c1_default_cfg {
+                                        ste,pins = "GPIO53_L4", "GPIO54_L3";
+                                        ste,input = <1>;
+                                };
+                        };
+                };
+                i2c2 {
+                        i2c2_default_mode: i2c2_default {
+                                i2c2_default_cfg {
+                                        ste,pins = "GPIO73_C21", "GPIO74_C20";
+                                        ste,input = <1>;
+                                };
+                        };
+                };
+        };
+        src: src@101e0000 {
+                compatible = "stericsson,nomadik-src";
+                reg = <0x101e0000 0x1000>;
+                disable-sxtalo;
+                disable-mxtalo;
+                /*
+                 * MXTAL "Main Chrystal" is a chrystal oscillator @19.2 MHz
+                 * that is parent of TIMCLK, PLL1 and PLL2
+                 */
+                mxtal: mxtal@19.2M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <19200000>;
+                };
+                /*
+                 * The 2.4 MHz TIMCLK reference clock is active at
+                 * boot time, this is actually the MXTALCLK @19.2 MHz
+                 * divided by 8. This clock is used by the timers and
+                 * watchdog. See page 105 ff.
+                 */
+                timclk: timclk@2.4M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <8>;
+                        clock-mult = <1>;
+                        clocks = <&mxtal>;
+                };
+                /* PLL1 is locked to MXTALI and variable from 20.4 to 334 MHz */
+                pll1: pll1@0 {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-pll-clock";
+                        pll-id = <1>;
+                        clocks = <&mxtal>;
+                };
+                /* HCLK divides the PLL1 with 1,2,3 or 4 */
+                hclk: hclk@0 {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-hclk-clock";
+                        clocks = <&pll1>;
+                };
+                /* The PCLK domain uses HCLK right off */
+                pclk: pclk@0 {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <1>;
+                        clock-mult = <1>;
+                        clocks = <&hclk>;
+                };
+                /* PLL2 is usually 864 MHz and divided into a few fixed rates */
+                pll2: pll2@0 {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-pll-clock";
+                        pll-id = <2>;
+                        clocks = <&mxtal>;
+                };
+                clk216: clk216@216M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <4>;
+                        clock-mult = <1>;
+                        clocks = <&pll2>;
+                };
+                clk108: clk108@108M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clocks = <&clk216>;
+                };
+                clk72: clk72@72M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        /* The data sheet does not say how this is derived */
+                        clock-div = <12>;
+                        clock-mult = <1>;
+                        clocks = <&pll2>;
+                };
+                clk48: clk48@48M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        /* The data sheet does not say how this is derived */
+                        clock-div = <18>;
+                        clock-mult = <1>;
+                        clocks = <&pll2>;
+                };
+                clk27: clk27@27M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <4>;
+                        clock-mult = <1>;
+                        clocks = <&clk108>;
+                };
+                /* This apparently exists as well */
+                ulpiclk: ulpiclk@60M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <60000000>;
+                };
+                /*
+                 * IP AMBA bus clocks, driving the bus side of the
+                 * peripheral clocking, clock gates.
+                 */
+                hclkdma0: hclkdma0@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <0>;
+                        clocks = <&hclk>;
+                };
+                hclksmc: hclksmc@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <1>;
+                        clocks = <&hclk>;
+                };
+                hclksdram: hclksdram@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <2>;
+                        clocks = <&hclk>;
+                };
+                hclkdma1: hclkdma1@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <3>;
+                        clocks = <&hclk>;
+                };
+                hclkclcd: hclkclcd@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <4>;
+                        clocks = <&hclk>;
+                };
+                pclkirda: pclkirda@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <5>;
+                        clocks = <&pclk>;
+                };
+                pclkssp: pclkssp@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <6>;
+                        clocks = <&pclk>;
+                };
+                pclkuart0: pclkuart0@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <7>;
+                        clocks = <&pclk>;
+                };
+                pclksdi: pclksdi@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <8>;
+                        clocks = <&pclk>;
+                };
+                pclki2c0: pclki2c0@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <9>;
+                        clocks = <&pclk>;
+                };
+                pclki2c1: pclki2c1@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <10>;
+                        clocks = <&pclk>;
+                };
+                pclkuart1: pclkuart1@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <11>;
+                        clocks = <&pclk>;
+                };
+                pclkmsp0: pclkmsp0@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <12>;
+                        clocks = <&pclk>;
+                };
+                hclkusb: hclkusb@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <13>;
+                        clocks = <&hclk>;
+                };
+                hclkdif: hclkdif@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <14>;
+                        clocks = <&hclk>;
+                };
+                hclksaa: hclksaa@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <15>;
+                        clocks = <&hclk>;
+                };
+                hclksva: hclksva@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <16>;
+                        clocks = <&hclk>;
+                };
+                pclkhsi: pclkhsi@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <17>;
+                        clocks = <&pclk>;
+                };
+                pclkxti: pclkxti@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <18>;
+                        clocks = <&pclk>;
+                };
+                pclkuart2: pclkuart2@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <19>;
+                        clocks = <&pclk>;
+                };
+                pclkmsp1: pclkmsp1@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <20>;
+                        clocks = <&pclk>;
+                };
+                pclkmsp2: pclkmsp2@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <21>;
+                        clocks = <&pclk>;
+                };
+                pclkowm: pclkowm@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <22>;
+                        clocks = <&pclk>;
+                };
+                hclkhpi: hclkhpi@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <23>;
+                        clocks = <&hclk>;
+                };
+                pclkske: pclkske@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <24>;
+                        clocks = <&pclk>;
+                };
+                pclkhsem: pclkhsem@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <25>;
+                        clocks = <&pclk>;
+                };
+                hclk3d: hclk3d@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <26>;
+                        clocks = <&hclk>;
+                };
+                hclkhash: hclkhash@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <27>;
+                        clocks = <&hclk>;
+                };
+                hclkcryp: hclkcryp@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <28>;
+                        clocks = <&hclk>;
+                };
+                pclkmshc: pclkmshc@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <29>;
+                        clocks = <&pclk>;
+                };
+                hclkusbm: hclkusbm@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <30>;
+                        clocks = <&hclk>;
+                };
+                hclkrng: hclkrng@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <31>;
+                        clocks = <&hclk>;
+                };
+                /* IP kernel clocks */
+                clcdclk: clcdclk@0 {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <36>;
+                        clocks = <&clk72 &clk48>;
+                };
+                irdaclk: irdaclk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <37>;
+                        clocks = <&clk48>;
+                };
+                sspiclk: sspiclk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <38>;
+                        clocks = <&clk48>;
+                };
+                uart0clk: uart0clk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <39>;
+                        clocks = <&clk48>;
+                };
+                sdiclk: sdiclk@48M {
+                        /* Also called MCCLK in some documents */
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <40>;
+                        clocks = <&clk48>;
+                };
+                i2c0clk: i2c0clk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <41>;
+                        clocks = <&clk48>;
+                };
+                i2c1clk: i2c1clk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <42>;
+                        clocks = <&clk48>;
+                };
+                uart1clk: uart1clk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <43>;
+                        clocks = <&clk48>;
+                };
+                mspclk0: mspclk0@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <44>;
+                        clocks = <&clk48>;
+                };
+                usbclk: usbclk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <45>;
+                        clocks = <&clk48>; /* 48 MHz not ULPI */
+                };
+                difclk: difclk@72M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <46>;
+                        clocks = <&clk72>;
+                };
+                ipi2cclk: ipi2cclk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <47>;
+                        clocks = <&clk48>; /* Guess */
+                };
+                ipbmcclk: ipbmcclk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <48>;
+                        clocks = <&clk48>; /* Guess */
+                };
+                hsiclkrx: hsiclkrx@216M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <49>;
+                        clocks = <&clk216>;
+                };
+                hsiclktx: hsiclktx@108M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <50>;
+                        clocks = <&clk108>;
+                };
+                uart2clk: uart2clk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <51>;
+                        clocks = <&clk48>;
+                };
+                mspclk1: mspclk1@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <52>;
+                        clocks = <&clk48>;
+                };
+                mspclk2: mspclk2@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <53>;
+                        clocks = <&clk48>;
+                };
+                owmclk: owmclk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <54>;
+                        clocks = <&clk48>; /* Guess */
+                };
+                skeclk: skeclk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <56>;
+                        clocks = <&clk48>; /* Guess */
+                };
+                x3dclk: x3dclk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <58>;
+                        clocks = <&clk48>; /* Guess */
+                };
+                pclkmsp3: pclkmsp3@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <59>;
+                        clocks = <&pclk>;
+                };
+                mspclk3: mspclk3@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <60>;
+                        clocks = <&clk48>;
+                };
+                mshcclk: mshcclk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <61>;
+                        clocks = <&clk48>; /* Guess */
+                };
+                usbmclk: usbmclk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <62>;
+                        /* Stated as "48 MHz not ULPI clock" */
+                        clocks = <&clk48>;
+                };
+                rngcclk: rngcclk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <63>;
+                        clocks = <&clk48>; /* Guess */
+                };
        };
        /* A NAND flash of 128 MiB */
@@ -97,6 +639,7 @@
                        <0x41000000 0x2000>,    /* NAND Base ADDR */
                        <0x40800000 0x2000>;    /* NAND Base CMD */
                reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
+                clocks = <&hclksmc>;
                status = "okay";
                partition@0 {
@@ -144,6 +687,8 @@
                        <&gpio1 30 0>; /* scl */
                #address-cells = <1>;
                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c0_default_mode>;
                stw4811@2d {
                           compatible = "st,stw4811";
@@ -158,6 +703,8 @@
                        <&gpio1 21 0>; /* scl */
                #address-cells = <1>;
                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c1_default_mode>;
                camera@2d {
                           compatible = "st,camera";
@@ -180,6 +727,9 @@
                        <&gpio2 9 0>; /* scl */
                #address-cells = <1>;
                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c2_default_mode>;
                stw4811@2d {
                           compatible = "st,stw4811-usb";
                           reg = <0x2d>;
@@ -211,6 +761,10 @@
                        reg = <0x101fd000 0x1000>;
                        interrupt-parent = <&vica>;
                        interrupts = <12>;
+                        clocks = <&uart0clk>, <&pclkuart0>;
+                        clock-names = "uartclk", "apb_pclk";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_default_mux>;
                };
                uart1: uart@101fb000 {
@@ -218,6 +772,10 @@
                        reg = <0x101fb000 0x1000>;
                        interrupt-parent = <&vica>;
                        interrupts = <17>;
+                        clocks = <&uart1clk>, <&pclkuart1>;
+                        clock-names = "uartclk", "apb_pclk";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart1_default_mux>;
                };
                uart2: uart@101f2000 {
@@ -225,17 +783,23 @@
                        reg = <0x101f2000 0x1000>;
                        interrupt-parent = <&vica>;
                        interrupts = <28>;
+                        clocks = <&uart2clk>, <&pclkuart2>;
+                        clock-names = "uartclk", "apb_pclk";
                        status = "disabled";
                };
                rng: rng@101b0000 {
                        compatible = "arm,primecell";
                        reg = <0x101b0000 0x1000>;
+                        clocks = <&rngcclk>, <&hclkrng>;
+                        clock-names = "rng", "apb_pclk";
                };
                rtc: rtc@101e8000 {
                        compatible = "arm,pl031", "arm,primecell";
                        reg = <0x101e8000 0x1000>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
                        interrupt-parent = <&vica>;
                        interrupts = <10>;
                };
@@ -243,6 +807,8 @@
                mmcsd: sdi@101f6000 {
                        compatible = "arm,pl18x", "arm,primecell";
                        reg = <0x101f6000 0x1000>;
+                        clocks = <&sdiclk>, <&pclksdi>;
+                        clock-names = "mclk", "apb_pclk";
                        interrupt-parent = <&vica>;
                        interrupts = <22>;
                        max-frequency = <48000000>;
@@ -251,6 +817,8 @@
                        mmc-cap-sd-highspeed;
                        cd-gpios = <&gpio3 15 0x1>;
                        cd-inverted;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>;
                };
        };
 };
diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
new file mode 100644
index 000000000000..8a1032c1ffc9
--- /dev/null
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -0,0 +1,473 @@
+/*
+ * Device Tree for the ST-Ericsson U300 Machine and SoC
+ */
+/dts-v1/;
+/include/ "skeleton.dtsi"
+/ {
+        model = "ST-Ericsson U300";
+        compatible = "stericsson,u300";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        chosen {
+                bootargs = "root=/dev/ram0 console=ttyAMA0,115200n8 earlyprintk";
+        };
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+        };
+        memory {
+                reg = <0x48000000 0x03c00000>;
+        };
+        s365 {
+                compatible = "stericsson,s365";
+                vana15-supply = <&ab3100_ldo_d_reg>;
+                syscon = <&syscon>;
+        };
+        syscon: syscon@c0011000 {
+                compatible = "stericsson,u300-syscon", "syscon";
+                reg = <0xc0011000 0x1000>;
+                clk32: app_32_clk@32k {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <32768>;
+                };
+                pll13: pll13@13M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <13000000>;
+                };
+                /* Slow bridge clocks under PLL13 */
+                slow_clk: slow_clk@13M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <0>; /* Slow */
+                        clock-id = <0>;
+                        clocks = <&pll13>;
+                };
+                uart0_clk: uart0_clk@13M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <0>; /* Slow */
+                        clock-id = <1>;
+                        clocks = <&slow_clk>;
+                };
+                gpio_clk: gpio_clk@13M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <0>; /* Slow */
+                        clock-id = <4>;
+                        clocks = <&slow_clk>;
+                };
+                rtc_clk: rtc_clk@13M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <0>; /* Slow */
+                        clock-id = <6>;
+                        clocks = <&slow_clk>;
+                };
+                apptimer_clk: app_tmr_clk@13M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <0>; /* Slow */
+                        clock-id = <7>;
+                        clocks = <&slow_clk>;
+                };
+                acc_tmr_clk@13M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <0>; /* Slow */
+                        clock-id = <8>;
+                        clocks = <&slow_clk>;
+                };
+                pll208: pll208@208M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <208000000>;
+                };
+                app208: app_208_clk@208M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <1>;
+                        clock-mult = <1>;
+                        clocks = <&pll208>;
+                };
+                cpu_clk@208M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <2>; /* Rest */
+                        clock-id = <3>;
+                        clocks = <&app208>;
+                };
+                app104: app_104_clk@104M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clocks = <&pll208>;
+                };
+                semi_clk@104M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <2>; /* Rest */
+                        clock-id = <9>;
+                        clocks = <&app104>;
+                };
+                app52: app_52_clk@52M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <4>;
+                        clock-mult = <1>;
+                        clocks = <&pll208>;
+                };
+                /* AHB subsystem clocks */
+                ahb_clk: ahb_subsys_clk@52M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <2>; /* Rest */
+                        clock-id = <10>;
+                        clocks = <&app52>;
+                };
+                intcon_clk@52M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <2>; /* Rest */
+                        clock-id = <12>;
+                        clocks = <&ahb_clk>;
+                };
+                emif_clk@52M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <2>; /* Rest */
+                        clock-id = <5>;
+                        clocks = <&ahb_clk>;
+                };
+                dmac_clk: dmac_clk@52M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <2>; /* Rest */
+                        clock-id = <4>;
+                        clocks = <&app52>;
+                };
+                fsmc_clk: fsmc_clk@52M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <2>; /* Rest */
+                        clock-id = <6>;
+                        clocks = <&app52>;
+                };
+                xgam_clk: xgam_clk@52M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <2>; /* Rest */
+                        clock-id = <8>;
+                        clocks = <&app52>;
+                };
+                app26: app_26_clk@26M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clocks = <&app52>;
+                };
+                /* Fast bridge  clocks */
+                fast_clk: fast_clk@26M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <1>; /* Fast */
+                        clock-id = <0>;
+                        clocks = <&app26>;
+                };
+                i2c0_clk: i2c0_clk@26M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <1>; /* Fast */
+                        clock-id = <1>;
+                        clocks = <&fast_clk>;
+                };
+                i2c1_clk: i2c1_clk@26M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <1>; /* Fast */
+                        clock-id = <2>;
+                        clocks = <&fast_clk>;
+                };
+                mmc_pclk: mmc_p_clk@26M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <1>; /* Fast */
+                        clock-id = <5>;
+                        clocks = <&fast_clk>;
+                };
+                mmc_mclk: mmc_mclk {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-mclk";
+                        clocks = <&mmc_pclk>;
+                };
+                spi_clk: spi_p_clk@26M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <1>; /* Fast */
+                        clock-id = <6>;
+                        clocks = <&fast_clk>;
+                };
+        };
+        timer: timer@c0014000 {
+                compatible = "stericsson,u300-apptimer";
+                reg = <0xc0014000 0x1000>;
+                interrupt-parent = <&vica>;
+                interrupts = <24 25 26 27>;
+                clocks = <&apptimer_clk>;
+        };
+        gpio: gpio@c0016000 {
+                compatible = "stericsson,gpio-coh901";
+                reg = <0xc0016000 0x1000>;
+                interrupt-parent = <&vicb>;
+                interrupts = <0 1 2 18 21 22 23>;
+                clocks = <&gpio_clk>;
+                interrupt-names = "gpio0", "gpio1", "gpio2", "gpio3",
+                                "gpio4", "gpio5", "gpio6";
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+        pinctrl: pinctrl@c0011000 {
+                compatible = "stericsson,pinctrl-u300";
+                reg = <0xc0011000 0x1000>;
+        };
+        watchdog: watchdog@c0012000 {
+                compatible = "stericsson,coh901327";
+                reg = <0xc0012000 0x1000>;
+                interrupt-parent = <&vicb>;
+                interrupts = <3>;
+                clocks = <&clk32>;
+        };
+        rtc: rtc@c0017000 {
+                compatible = "stericsson,coh901331";
+                reg = <0xc0017000 0x1000>;
+                interrupt-parent = <&vicb>;
+                interrupts = <10>;
+                clocks = <&rtc_clk>;
+        };
+        dmac: dma-controller@c00020000 {
+                compatible = "stericsson,coh901318";
+                reg = <0xc0020000 0x1000>;
+                interrupt-parent = <&vica>;
+                interrupts = <2>;
+                #dma-cells = <1>;
+                dma-channels = <40>;
+                clocks = <&dmac_clk>;
+        };
+        /* A NAND flash of 128 MiB */
+        fsmc: flash@40000000 {
+                compatible = "stericsson,fsmc-nand";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0x9f800000 0x1000>,      /* FSMC Register*/
+                        <0x80000000 0x4000>,    /* NAND Base DATA */
+                        <0x80020000 0x4000>,    /* NAND Base ADDR */
+                        <0x80010000 0x4000>;    /* NAND Base CMD */
+                reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
+                nand-skip-bbtscan;
+                clocks = <&fsmc_clk>;
+                partition@0 {
+                label = "boot records";
+                        reg = <0x0 0x20000>;
+                };
+                partition@20000 {
+                        label = "free";
+                        reg = <0x20000 0x7e0000>;
+                };
+                partition@800000 {
+                        label = "platform";
+                        reg = <0x800000 0xf800000>;
+                };
+        };
+        i2c0: i2c@c0004000 {
+                compatible = "st,ddci2c";
+                reg = <0xc0004000 0x1000>;
+                interrupt-parent = <&vicb>;
+                interrupts = <8>;
+                clocks = <&i2c0_clk>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                ab3100: ab3100@0x48 {
+                        compatible = "stericsson,ab3100";
+                        reg = <0x48>;
+                        interrupt-parent = <&vica>;
+                        interrupts = <0>; /* EXT0 IRQ */
+                        ab3100-regulators {
+                                compatible = "stericsson,ab3100-regulators";
+                                ab3100_ldo_a_reg: ab3100_ldo_a {
+                                        regulator-compatible = "ab3100_ldo_a";
+                                        startup-delay-us = <200>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                ab3100_ldo_c_reg: ab3100_ldo_c {
+                                        regulator-compatible = "ab3100_ldo_c";
+                                        startup-delay-us = <200>;
+                                };
+                                ab3100_ldo_d_reg: ab3100_ldo_d {
+                                        regulator-compatible = "ab3100_ldo_d";
+                                        startup-delay-us = <200>;
+                                };
+                                ab3100_ldo_e_reg: ab3100_ldo_e {
+                                        regulator-compatible = "ab3100_ldo_e";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        startup-delay-us = <200>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                ab3100_ldo_f_reg: ab3100_ldo_f {
+                                        regulator-compatible = "ab3100_ldo_f";
+                                        regulator-min-microvolt = <2500000>;
+                                        regulator-max-microvolt = <2500000>;
+                                        startup-delay-us = <600>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                ab3100_ldo_g_reg: ab3100_ldo_g {
+                                        regulator-compatible = "ab3100_ldo_g";
+                                        regulator-min-microvolt = <1500000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        startup-delay-us = <400>;
+                                };
+                                ab3100_ldo_h_reg: ab3100_ldo_h {
+                                        regulator-compatible = "ab3100_ldo_h";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <2750000>;
+                                        startup-delay-us = <200>;
+                                };
+                                ab3100_ldo_k_reg: ab3100_ldo_k {
+                                        regulator-compatible = "ab3100_ldo_k";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <2750000>;
+                                        startup-delay-us = <200>;
+                                };
+                                ab3100_ext_reg: ab3100_ext {
+                                        regulator-compatible = "ab3100_ext";
+                                };
+                                ab3100_buck_reg: ab3100_buck {
+                                        regulator-compatible = "ab3100_buck";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        startup-delay-us = <1000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                        };
+                };
+        };
+        i2c1: i2c@c0005000 {
+                compatible = "st,ddci2c";
+                reg = <0xc0005000 0x1000>;
+                interrupt-parent = <&vicb>;
+                interrupts = <9>;
+                clocks = <&i2c1_clk>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                fwcam0: fwcam@0x10 {
+                        reg = <0x10>;
+                };
+                fwcam1: fwcam@0x5d {
+                        reg = <0x5d>;
+                };
+        };
+        amba {
+                compatible = "arm,amba-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                vica: interrupt-controller@a0001000 {
+                        compatible = "arm,versatile-vic";
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        reg = <0xa0001000 0x20>;
+                };
+                vicb: interrupt-controller@a0002000 {
+                        compatible = "arm,versatile-vic";
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        reg = <0xa0002000 0x20>;
+                };
+                uart0: serial@c0013000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0xc0013000 0x1000>;
+                        interrupt-parent = <&vica>;
+                        interrupts = <22>;
+                        clocks = <&uart0_clk>, <&uart0_clk>;
+                        clock-names = "apb_pclk", "uart0_clk";
+                        dmas = <&dmac 17 &dmac 18>;
+                        dma-names = "tx", "rx";
+                };
+                uart1: serial@c0007000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0xc0007000 0x1000>;
+                        interrupt-parent = <&vicb>;
+                        interrupts = <20>;
+                        dmas = <&dmac 38 &dmac 39>;
+                        dma-names = "tx", "rx";
+                };
+                mmcsd: mmcsd@c0001000 {
+                        compatible = "arm,pl18x", "arm,primecell";
+                        reg = <0xc0001000 0x1000>;
+                        interrupt-parent = <&vicb>;
+                        interrupts = <6 7>;
+                        clocks = <&mmc_pclk>, <&mmc_mclk>;
+                        clock-names = "apb_pclk", "mclk";
+                        max-frequency = <24000000>;
+                        bus-width = <4>; // SD-card slot
+                        mmc-cap-mmc-highspeed;
+                        mmc-cap-sd-highspeed;
+                        cd-gpios = <&gpio 12 0x4>;
+                        cd-inverted;
+                        vmmc-supply = <&ab3100_ldo_g_reg>;
+                        dmas = <&dmac 14>;
+                        dma-names = "rx";
+                };
+                spi: ssp@c0006000 {
+                        compatible = "arm,pl022", "arm,primecell";
+                        reg = <0xc0006000 0x1000>;
+                        interrupt-parent = <&vica>;
+                        interrupts = <23>;
+                        clocks = <&spi_clk>, <&spi_clk>;
+                        clock-names = "apb_pclk", "spi_clk";
+                        dmas = <&dmac 27 &dmac 28>;
+                        dma-names = "tx", "rx";
+                        num-cs = <3>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        spi-dummy@1 {
+                                compatible = "arm,pl022-dummy";
+                                reg = <1>;
+                                spi-max-frequency = <20000000>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/stih415-b2000.dts b/arch/arm/boot/dts/stih415-b2000.dts
new file mode 100644
index 000000000000..d4af53160435
--- /dev/null
+++ b/arch/arm/boot/dts/stih415-b2000.dts
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "stih415.dtsi"
+#include "stih41x-b2000.dtsi"
+/ {
+        model = "STiH415 B2000 Board";
+        compatible = "st,stih415", "st,stih415-b2000";
+};
diff --git a/arch/arm/boot/dts/stih415-b2020.dts b/arch/arm/boot/dts/stih415-b2020.dts
new file mode 100644
index 000000000000..442b019e9a3a
--- /dev/null
+++ b/arch/arm/boot/dts/stih415-b2020.dts
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "stih415.dtsi"
+#include "stih41x-b2020.dtsi"
+/ {
+        model = "STiH415 B2020 Board";
+        compatible = "st,stih415", "st,stih415-b2020";
+};
diff --git a/arch/arm/boot/dts/stih415-clock.dtsi b/arch/arm/boot/dts/stih415-clock.dtsi
new file mode 100644
index 000000000000..174c799df741
--- /dev/null
+++ b/arch/arm/boot/dts/stih415-clock.dtsi
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/ {
+        clocks {
+                /*
+                 * Fixed 30MHz oscillator input to SoC
+                 */
+                CLK_SYSIN: CLK_SYSIN {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <30000000>;
+                };
+                /*
+                 * ARM Peripheral clock for timers
+                 */
+                arm_periph_clk: arm_periph_clk {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <500000000>;
+                };
+                /*
+                 * Bootloader initialized system infrastructure clock for
+                 * serial devices.
+                 */
+                CLKS_ICN_REG_0: CLKS_ICN_REG_0 {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <100000000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi
new file mode 100644
index 000000000000..1d322b24d1e4
--- /dev/null
+++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi
@@ -0,0 +1,268 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#include "st-pincfg.h"
+/ {
+        aliases {
+                gpio0   = &PIO0;
+                gpio1   = &PIO1;
+                gpio2   = &PIO2;
+                gpio3   = &PIO3;
+                gpio4   = &PIO4;
+                gpio5   = &PIO5;
+                gpio6   = &PIO6;
+                gpio7   = &PIO7;
+                gpio8   = &PIO8;
+                gpio9   = &PIO9;
+                gpio10  = &PIO10;
+                gpio11  = &PIO11;
+                gpio12  = &PIO12;
+                gpio13  = &PIO13;
+                gpio14  = &PIO14;
+                gpio15  = &PIO15;
+                gpio16  = &PIO16;
+                gpio17  = &PIO17;
+                gpio18  = &PIO18;
+                gpio19  = &PIO100;
+                gpio20  = &PIO101;
+                gpio21  = &PIO102;
+                gpio22  = &PIO103;
+                gpio23  = &PIO104;
+                gpio24  = &PIO105;
+                gpio25  = &PIO106;
+                gpio26  = &PIO107;
+        };
+        soc {
+                pin-controller-sbc {
+                        #address-cells  = <1>;
+                        #size-cells     = <1>;
+                        compatible      = "st,stih415-sbc-pinctrl";
+                        st,syscfg       = <&syscfg_sbc>;
+                        ranges          = <0 0xfe610000 0x5000>;
+                        PIO0: gpio@fe610000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0 0x100>;
+                                st,bank-name    = "PIO0";
+                        };
+                        PIO1: gpio@fe611000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x1000 0x100>;
+                                st,bank-name    = "PIO1";
+                        };
+                        PIO2: gpio@fe612000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x2000 0x100>;
+                                st,bank-name    = "PIO2";
+                        };
+                        PIO3: gpio@fe613000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x3000 0x100>;
+                                st,bank-name    = "PIO3";
+                        };
+                        PIO4: gpio@fe614000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x4000 0x100>;
+                                st,bank-name    = "PIO4";
+                        };
+                        sbc_serial1 {
+                                pinctrl_sbc_serial1:sbc_serial1 {
+                                        st,pins {
+                                                tx      = <&PIO2 6 ALT3 OUT>;
+                                                rx      = <&PIO2 7 ALT3 IN>;
+                                        };
+                                };
+                        };
+                };
+                pin-controller-front {
+                        #address-cells  = <1>;
+                        #size-cells     = <1>;
+                        compatible      = "st,stih415-front-pinctrl";
+                        st,syscfg       = <&syscfg_front>;
+                        ranges          = <0 0xfee00000 0x8000>;
+                        PIO5: gpio@fee00000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0 0x100>;
+                                st,bank-name    = "PIO5";
+                        };
+                        PIO6: gpio@fee01000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x1000 0x100>;
+                                st,bank-name    = "PIO6";
+                        };
+                        PIO7: gpio@fee02000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x2000 0x100>;
+                                st,bank-name    = "PIO7";
+                        };
+                        PIO8: gpio@fee03000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x3000 0x100>;
+                                st,bank-name    = "PIO8";
+                        };
+                        PIO9: gpio@fee04000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x4000 0x100>;
+                                st,bank-name    = "PIO9";
+                        };
+                        PIO10: gpio@fee05000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x5000 0x100>;
+                                st,bank-name    = "PIO10";
+                        };
+                        PIO11: gpio@fee06000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x6000 0x100>;
+                                st,bank-name    = "PIO11";
+                        };
+                        PIO12: gpio@fee07000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x7000 0x100>;
+                                st,bank-name    = "PIO12";
+                        };
+                };
+                pin-controller-rear {
+                        #address-cells  = <1>;
+                        #size-cells     = <1>;
+                        compatible      = "st,stih415-rear-pinctrl";
+                        st,syscfg       = <&syscfg_rear>;
+                        ranges          = <0 0xfe820000 0x8000>;
+                        PIO13: gpio@fe820000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0 0x100>;
+                                st,bank-name    = "PIO13";
+                        };
+                        PIO14: gpio@fe821000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x1000 0x100>;
+                                st,bank-name    = "PIO14";
+                        };
+                        PIO15: gpio@fe822000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x2000 0x100>;
+                                st,bank-name    = "PIO15";
+                        };
+                        PIO16: gpio@fe823000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x3000 0x100>;
+                                st,bank-name    = "PIO16";
+                        };
+                        PIO17: gpio@fe824000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x4000 0x100>;
+                                st,bank-name    = "PIO17";
+                        };
+                        PIO18: gpio@fe825000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x5000 0x100>;
+                                st,bank-name    = "PIO18";
+                        };
+                        serial2 {
+                                pinctrl_serial2: serial2-0 {
+                                        st,pins {
+                                                tx      = <&PIO17 4 ALT2 OUT>;
+                                                rx      = <&PIO17 5 ALT2 IN>;
+                                        };
+                                };
+                        };
+                };
+                pin-controller-left {
+                        #address-cells  = <1>;
+                        #size-cells     = <1>;
+                        compatible      = "st,stih415-left-pinctrl";
+                        st,syscfg       = <&syscfg_left>;
+                        ranges          = <0 0xfd6b0000 0x3000>;
+                        PIO100: gpio@fd6b0000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0 0x100>;
+                                st,bank-name    = "PIO100";
+                        };
+                        PIO101: gpio@fd6b1000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x1000 0x100>;
+                                st,bank-name    = "PIO101";
+                        };
+                        PIO102: gpio@fd6b2000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x2000 0x100>;
+                                st,bank-name    = "PIO102";
+                        };
+                };
+                pin-controller-right {
+                        #address-cells  = <1>;
+                        #size-cells     = <1>;
+                        compatible      = "st,stih415-right-pinctrl";
+                        st,syscfg       = <&syscfg_right>;
+                        ranges          = <0 0xfd330000 0x5000>;
+                        PIO103: gpio@fd330000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0 0x100>;
+                                st,bank-name    = "PIO103";
+                        };
+                        PIO104: gpio@fd331000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x1000 0x100>;
+                                st,bank-name    = "PIO104";
+                        };
+                        PIO105: gpio@fd332000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x2000 0x100>;
+                                st,bank-name    = "PIO105";
+                        };
+                        PIO106: gpio@fd333000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x3000 0x100>;
+                                st,bank-name    = "PIO106";
+                        };
+                        PIO107: gpio@fd334000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x4000 0x100>;
+                                st,bank-name    = "PIO107";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
new file mode 100644
index 000000000000..74ab8ded4b49
--- /dev/null
+++ b/arch/arm/boot/dts/stih415.dtsi
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#include "stih41x.dtsi"
+#include "stih415-clock.dtsi"
+#include "stih415-pinctrl.dtsi"
+/ {
+        L2: cache-controller {
+                compatible = "arm,pl310-cache";
+                reg = <0xfffe2000 0x1000>;
+                arm,data-latency = <3 2 2>;
+                arm,tag-latency = <1 1 1>;
+                cache-unified;
+                cache-level = <2>;
+        };
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                interrupt-parent = <&intc>;
+                ranges;
+                compatible      = "simple-bus";
+                syscfg_sbc: sbc-syscfg@fe600000{
+                        compatible      = "st,stih415-sbc-syscfg", "syscon";
+                        reg             = <0xfe600000 0xb4>;
+                };
+                syscfg_front: front-syscfg@fee10000{
+                        compatible      = "st,stih415-front-syscfg", "syscon";
+                        reg             = <0xfee10000 0x194>;
+                };
+                syscfg_rear: rear-syscfg@fe830000{
+                        compatible      = "st,stih415-rear-syscfg", "syscon";
+                        reg             = <0xfe830000 0x190>;
+                };
+                /* MPE syscfgs */
+                syscfg_left: left-syscfg@fd690000{
+                        compatible      = "st,stih415-left-syscfg", "syscon";
+                        reg             = <0xfd690000 0x78>;
+                };
+                syscfg_right: right-syscfg@fd320000{
+                        compatible      = "st,stih415-right-syscfg", "syscon";
+                        reg             = <0xfd320000 0x180>;
+                };
+                syscfg_system: system-syscfg@fdde0000  {
+                        compatible      = "st,stih415-system-syscfg", "syscon";
+                        reg             = <0xfdde0000 0x15c>;
+                };
+                syscfg_lpm: lpm-syscfg@fe4b5100{
+                        compatible      = "st,stih415-lpm-syscfg", "syscon";
+                        reg             = <0xfe4b5100 0x08>;
+                };
+                serial2: serial@fed32000 {
+                        compatible      = "st,asc";
+                        status          = "disabled";
+                        reg             = <0xfed32000 0x2c>;
+                        interrupts      = <0 197 0>;
+                        pinctrl-names   = "default";
+                        pinctrl-0       = <&pinctrl_serial2>;
+                        clocks          = <&CLKS_ICN_REG_0>;
+                };
+                /* SBC comms block ASCs in SASG1 */
+                sbc_serial1: serial@fe531000 {
+                        compatible      = "st,asc";
+                        status          = "disabled";
+                        reg             = <0xfe531000 0x2c>;
+                        interrupts      = <0 210 0>;
+                        clocks          = <&CLK_SYSIN>;
+                        pinctrl-names   = "default";
+                        pinctrl-0       = <&pinctrl_sbc_serial1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/stih416-b2000.dts b/arch/arm/boot/dts/stih416-b2000.dts
new file mode 100644
index 000000000000..a5eb6eee10bf
--- /dev/null
+++ b/arch/arm/boot/dts/stih416-b2000.dts
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "stih416.dtsi"
+#include "stih41x-b2000.dtsi"
+/ {
+        compatible = "st,stih416", "st,stih416-b2000";
+        model = "STiH416 B2000";
+};
diff --git a/arch/arm/boot/dts/stih416-b2020.dts b/arch/arm/boot/dts/stih416-b2020.dts
new file mode 100644
index 000000000000..276f28da573a
--- /dev/null
+++ b/arch/arm/boot/dts/stih416-b2020.dts
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "stih416.dtsi"
+#include "stih41x-b2020.dtsi"
+/ {
+        model = "STiH416 B2020";
+        compatible = "st,stih416", "st,stih416-b2020";
+};
diff --git a/arch/arm/boot/dts/stih416-clock.dtsi b/arch/arm/boot/dts/stih416-clock.dtsi
new file mode 100644
index 000000000000..7026bf1158d8
--- /dev/null
+++ b/arch/arm/boot/dts/stih416-clock.dtsi
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics R&D Limited
+ * <stlinux-devel@stlinux.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/ {
+        clocks {
+                /*
+                 * Fixed 30MHz oscillator inputs to SoC
+                 */
+                CLK_SYSIN: CLK_SYSIN {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <30000000>;
+                        clock-output-names = "CLK_SYSIN";
+                };
+                /*
+                 * ARM Peripheral clock for timers
+                 */
+                arm_periph_clk: arm_periph_clk {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <600000000>;
+                };
+                /*
+                 * Bootloader initialized system infrastructure clock for
+                 * serial devices.
+                 */
+                CLK_S_ICN_REG_0: clockgenA0@4 {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <100000000>;
+                        clock-output-names = "CLK_S_ICN_REG_0";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi
new file mode 100644
index 000000000000..0f246c979262
--- /dev/null
+++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi
@@ -0,0 +1,303 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics Limited.
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#include "st-pincfg.h"
+/ {
+        aliases {
+                gpio0   = &PIO0;
+                gpio1   = &PIO1;
+                gpio2   = &PIO2;
+                gpio3   = &PIO3;
+                gpio4   = &PIO4;
+                gpio5   = &PIO40;
+                gpio6   = &PIO5;
+                gpio7   = &PIO6;
+                gpio8   = &PIO7;
+                gpio9   = &PIO8;
+                gpio10  = &PIO9;
+                gpio11  = &PIO10;
+                gpio12  = &PIO11;
+                gpio13  = &PIO12;
+                gpio14  = &PIO30;
+                gpio15  = &PIO31;
+                gpio16  = &PIO13;
+                gpio17  = &PIO14;
+                gpio18  = &PIO15;
+                gpio19  = &PIO16;
+                gpio20  = &PIO17;
+                gpio21  = &PIO18;
+                gpio22  = &PIO100;
+                gpio23  = &PIO101;
+                gpio24  = &PIO102;
+                gpio25  = &PIO103;
+                gpio26  = &PIO104;
+                gpio27  = &PIO105;
+                gpio28  = &PIO106;
+                gpio29  = &PIO107;
+        };
+        soc {
+                pin-controller-sbc {
+                        #address-cells  = <1>;
+                        #size-cells     = <1>;
+                        compatible      = "st,stih416-sbc-pinctrl";
+                        st,syscfg       = <&syscfg_sbc>;
+                        ranges          = <0 0xfe610000 0x6000>;
+                        PIO0: gpio@fe610000 {
+                                gpio-controller;
+                                #gpio-cells = <1>;
+                                reg             = <0 0x100>;
+                                st,bank-name    = "PIO0";
+                        };
+                        PIO1: gpio@fe611000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x1000 0x100>;
+                                st,bank-name    = "PIO1";
+                        };
+                        PIO2: gpio@fe612000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x2000 0x100>;
+                                st,bank-name    = "PIO2";
+                        };
+                        PIO3: gpio@fe613000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x3000 0x100>;
+                                st,bank-name    = "PIO3";
+                        };
+                        PIO4: gpio@fe614000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x4000 0x100>;
+                                st,bank-name    = "PIO4";
+                        };
+                        PIO40: gpio@fe615000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x5000 0x100>;
+                                st,bank-name    = "PIO40";
+                                st,retime-pin-mask = <0x7f>;
+                        };
+                        sbc_serial1 {
+                                pinctrl_sbc_serial1: sbc_serial1 {
+                                        st,pins {
+                                                tx      = <&PIO2 6 ALT3 OUT>;
+                                                rx      = <&PIO2 7 ALT3 IN>;
+                                        };
+                                };
+                        };
+                };
+                pin-controller-front {
+                        #address-cells  = <1>;
+                        #size-cells     = <1>;
+                        compatible      = "st,stih416-front-pinctrl";
+                        st,syscfg       = <&syscfg_front>;
+                        ranges          = <0 0xfee00000 0x10000>;
+                        PIO5: gpio@fee00000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0 0x100>;
+                                st,bank-name    = "PIO5";
+                        };
+                        PIO6: gpio@fee01000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x1000 0x100>;
+                                st,bank-name    = "PIO6";
+                        };
+                        PIO7: gpio@fee02000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x2000 0x100>;
+                                st,bank-name    = "PIO7";
+                        };
+                        PIO8: gpio@fee03000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x3000 0x100>;
+                                st,bank-name    = "PIO8";
+                        };
+                        PIO9: gpio@fee04000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x4000 0x100>;
+                                st,bank-name    = "PIO9";
+                        };
+                        PIO10: gpio@fee05000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x5000 0x100>;
+                                st,bank-name    = "PIO10";
+                        };
+                        PIO11: gpio@fee06000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x6000 0x100>;
+                                st,bank-name    = "PIO11";
+                        };
+                        PIO12: gpio@fee07000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x7000 0x100>;
+                                st,bank-name    = "PIO12";
+                        };
+                        PIO30: gpio@fee08000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x8000 0x100>;
+                                st,bank-name    = "PIO30";
+                        };
+                        PIO31: gpio@fee09000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x9000 0x100>;
+                                st,bank-name    = "PIO31";
+                        };
+                        serial2-oe {
+                                pinctrl_serial2_oe: serial2-1 {
+                                        st,pins {
+                                                output-enable   = <&PIO11 3 ALT2 OUT>;
+                                        };
+                                };
+                        };
+                };
+                pin-controller-rear {
+                        #address-cells  = <1>;
+                        #size-cells     = <1>;
+                        compatible      = "st,stih416-rear-pinctrl";
+                        st,syscfg       = <&syscfg_rear>;
+                        ranges          = <0 0xfe820000 0x6000>;
+                        PIO13: gpio@fe820000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0 0x100>;
+                                st,bank-name    = "PIO13";
+                        };
+                        PIO14: gpio@fe821000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x1000 0x100>;
+                                st,bank-name    = "PIO14";
+                        };
+                        PIO15: gpio@fe822000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x2000 0x100>;
+                                st,bank-name    = "PIO15";
+                        };
+                        PIO16: gpio@fe823000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x3000 0x100>;
+                                st,bank-name    = "PIO16";
+                        };
+                        PIO17: gpio@fe824000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x4000 0x100>;
+                                st,bank-name    = "PIO17";
+                        };
+                        PIO18: gpio@fe825000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x5000 0x100>;
+                                st,bank-name    = "PIO18";
+                                st,retime-pin-mask = <0xf>;
+                        };
+                        serial2 {
+                                pinctrl_serial2: serial2-0 {
+                                        st,pins {
+                                                tx      = <&PIO17 4 ALT2 OUT>;
+                                                rx      = <&PIO17 5 ALT2 IN>;
+                                        };
+                                };
+                        };
+                };
+                pin-controller-fvdp-fe {
+                        #address-cells  = <1>;
+                        #size-cells     = <1>;
+                        compatible      = "st,stih416-fvdp-fe-pinctrl";
+                        st,syscfg       = <&syscfg_fvdp_fe>;
+                        ranges          = <0 0xfd6b0000 0x3000>;
+                        PIO100: gpio@fd6b0000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0 0x100>;
+                                st,bank-name    = "PIO100";
+                        };
+                        PIO101: gpio@fd6b1000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x1000 0x100>;
+                                st,bank-name    = "PIO101";
+                        };
+                        PIO102: gpio@fd6b2000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x2000 0x100>;
+                                st,bank-name    = "PIO102";
+                        };
+                };
+                pin-controller-fvdp-lite {
+                        #address-cells  = <1>;
+                        #size-cells     = <1>;
+                        compatible      = "st,stih416-fvdp-lite-pinctrl";
+                        st,syscfg               = <&syscfg_fvdp_lite>;
+                        ranges                  = <0 0xfd330000 0x5000>;
+                        PIO103: gpio@fd330000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0 0x100>;
+                                st,bank-name    = "PIO103";
+                        };
+                        PIO104: gpio@fd331000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x1000 0x100>;
+                                st,bank-name    = "PIO104";
+                        };
+                        PIO105: gpio@fd332000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x2000 0x100>;
+                                st,bank-name    = "PIO105";
+                        };
+                        PIO106: gpio@fd333000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x3000 0x100>;
+                                st,bank-name    = "PIO106";
+                        };
+                        PIO107: gpio@fd334000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x4000 0x100>;
+                                st,bank-name    = "PIO107";
+                                st,retime-pin-mask = <0xf>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
new file mode 100644
index 000000000000..1a0326ea7d07
--- /dev/null
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2012 STMicroelectronics Limited.
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#include "stih41x.dtsi"
+#include "stih416-clock.dtsi"
+#include "stih416-pinctrl.dtsi"
+/ {
+        L2: cache-controller {
+                compatible = "arm,pl310-cache";
+                reg = <0xfffe2000 0x1000>;
+                arm,data-latency = <3 3 3>;
+                arm,tag-latency = <2 2 2>;
+                cache-unified;
+                cache-level = <2>;
+        };
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                interrupt-parent = <&intc>;
+                ranges;
+                compatible      = "simple-bus";
+                syscfg_sbc:sbc-syscfg@fe600000{
+                        compatible      = "st,stih416-sbc-syscfg", "syscon";
+                        reg             = <0xfe600000 0x1000>;
+                };
+                syscfg_front:front-syscfg@fee10000{
+                        compatible      = "st,stih416-front-syscfg", "syscon";
+                        reg             = <0xfee10000 0x1000>;
+                };
+                syscfg_rear:rear-syscfg@fe830000{
+                        compatible      = "st,stih416-rear-syscfg", "syscon";
+                        reg             = <0xfe830000 0x1000>;
+                };
+                /* MPE */
+                syscfg_fvdp_fe:fvdp-fe-syscfg@fddf0000{
+                        compatible      = "st,stih416-fvdp-fe-syscfg", "syscon";
+                        reg             = <0xfddf0000 0x1000>;
+                };
+                syscfg_fvdp_lite:fvdp-lite-syscfg@fd6a0000{
+                        compatible      = "st,stih416-fvdp-lite-syscfg", "syscon";
+                        reg             = <0xfd6a0000 0x1000>;
+                };
+                syscfg_cpu:cpu-syscfg@fdde0000{
+                        compatible      = "st,stih416-cpu-syscfg", "syscon";
+                        reg             = <0xfdde0000 0x1000>;
+                };
+                syscfg_compo:compo-syscfg@fd320000{
+                        compatible      = "st,stih416-compo-syscfg", "syscon";
+                        reg             = <0xfd320000 0x1000>;
+                };
+                syscfg_transport:transport-syscfg@fd690000{
+                        compatible      = "st,stih416-transport-syscfg", "syscon";
+                        reg             = <0xfd690000 0x1000>;
+                };
+                syscfg_lpm:lpm-syscfg@fe4b5100{
+                        compatible      = "st,stih416-lpm-syscfg", "syscon";
+                        reg             = <0xfe4b5100 0x8>;
+                };
+                serial2: serial@fed32000{
+                        compatible      = "st,asc";
+                        status          = "disabled";
+                        reg             = <0xfed32000 0x2c>;
+                        interrupts      = <0 197 0>;
+                        clocks          = <&CLK_S_ICN_REG_0>;
+                        pinctrl-names   = "default";
+                        pinctrl-0       = <&pinctrl_serial2 &pinctrl_serial2_oe>;
+                };
+                /* SBC_UART1 */
+                sbc_serial1: serial@fe531000 {
+                        compatible      = "st,asc";
+                        status          = "disabled";
+                        reg             = <0xfe531000 0x2c>;
+                        interrupts      = <0 210 0>;
+                        pinctrl-names   = "default";
+                        pinctrl-0       = <&pinctrl_sbc_serial1>;
+                        clocks          = <&CLK_SYSIN>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/stih41x-b2000.dtsi b/arch/arm/boot/dts/stih41x-b2000.dtsi
new file mode 100644
index 000000000000..8e694d2b8f5b
--- /dev/null
+++ b/arch/arm/boot/dts/stih41x-b2000.dtsi
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+/ {
+        memory{
+                device_type = "memory";
+                reg = <0x60000000 0x40000000>;
+        };
+        chosen {
+                bootargs = "console=ttyAS0,115200";
+                linux,stdout-path = &serial2;
+        };
+        aliases {
+                ttyAS0 = &serial2;
+        };
+        soc {
+                serial2: serial@fed32000 {
+                        status = "okay";
+                };
+                leds {
+                        compatible      = "gpio-leds";
+                        fp_led {
+                                #gpio-cells = <1>;
+                                label   = "Front Panel LED";
+                                gpios   = <&PIO105 7>;
+                                linux,default-trigger   = "heartbeat";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi
new file mode 100644
index 000000000000..133e18143b1b
--- /dev/null
+++ b/arch/arm/boot/dts/stih41x-b2020.dtsi
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+/ {
+        memory{
+                device_type = "memory";
+                reg = <0x40000000 0x80000000>;
+        };
+        chosen {
+                bootargs = "console=ttyAS0,115200";
+                linux,stdout-path = &sbc_serial1;
+        };
+        aliases {
+                ttyAS0 = &sbc_serial1;
+        };
+        soc {
+                sbc_serial1: serial@fe531000 {
+                        status = "okay";
+                };
+                leds {
+                        compatible      = "gpio-leds";
+                        red {
+                                #gpio-cells = <1>;
+                                label   = "Front Panel LED";
+                                gpios   = <&PIO4 1>;
+                                linux,default-trigger   = "heartbeat";
+                        };
+                        green {
+                                gpios   = <&PIO4 7>;
+                                default-state = "off";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/stih41x.dtsi b/arch/arm/boot/dts/stih41x.dtsi
new file mode 100644
index 000000000000..f5b9898d9c6e
--- /dev/null
+++ b/arch/arm/boot/dts/stih41x.dtsi
@@ -0,0 +1,40 @@
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0>;
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <1>;
+                };
+        };
+        intc: interrupt-controller@fffe1000 {
+                compatible = "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                interrupt-controller;
+                reg = <0xfffe1000 0x1000>,
+                      <0xfffe0100 0x100>;
+        };
+        scu@fffe0000 {
+                compatible = "arm,cortex-a9-scu";
+                reg = <0xfffe0000 0x1000>;
+        };
+        timer@fffe0200 {
+                interrupt-parent = <&intc>;
+                compatible = "arm,cortex-a9-global-timer";
+                reg = <0xfffe0200 0x100>;
+                interrupts = <1 11 0x04>;
+                clocks = <&arm_periph_clk>;
+        };
+};
diff --git a/arch/arm/boot/dts/stuib.dtsi b/arch/arm/boot/dts/stuib.dtsi
index 615392a75676..524e33240ad4 100644
--- a/arch/arm/boot/dts/stuib.dtsi
+++ b/arch/arm/boot/dts/stuib.dtsi
@@ -9,13 +9,15 @@
 * http://www.gnu.org/copyleft/gpl.html
 */
+#include <dt-bindings/interrupt-controller/irq.h>
 / {
-        soc-u9500 {
+        soc {
                i2c@80004000 {
                        stmpe1601: stmpe1601@40 {
                                compatible = "st,stmpe1601";
                                reg = <0x40>;
-                                interrupts = <26 0x2>;
+                                interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
                                interrupt-parent = <&gpio6>;
                                interrupt-controller;
@@ -52,26 +54,26 @@
                };
                i2c@80110000 {
-                        bu21013_tp@0x5c {
+                        bu21013_tp@5c {
-                                compatible = "rhom,bu21013_tp";
+                                compatible = "rohm,bu21013_tp";
                                reg = <0x5c>;
                                touch-gpio = <&gpio2 20 0x4>;
                                avdd-supply = <&ab8500_ldo_aux1_reg>;
-                                rhom,touch-max-x = <384>;
+                                rohm,touch-max-x = <384>;
-                                rhom,touch-max-y = <704>;
+                                rohm,touch-max-y = <704>;
-                                rhom,flip-y;
+                                rohm,flip-y;
                        };
-                        bu21013_tp@0x5d {
+                        bu21013_tp@5d {
-                                compatible = "rhom,bu21013_tp";
+                                compatible = "rohm,bu21013_tp";
                                reg = <0x5d>;
                                touch-gpio = <&gpio2 20 0x4>;
                                avdd-supply = <&ab8500_ldo_aux1_reg>;
-                                rhom,touch-max-x = <384>;
+                                rohm,touch-max-x = <384>;
-                                rhom,touch-max-y = <704>;
+                                rohm,touch-max-y = <704>;
-                                rhom,flip-y;
+                                rohm,flip-y;
                        };
                };
        };
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index b70fe0db6bb7..757c4cd900ee 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -27,6 +27,21 @@
        };
        soc@01c20000 {
+                emac: ethernet@01c0b000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&emac_pins_a>;
+                        phy = <&phy1>;
+                        status = "okay";
+                };
+                mdio@01c0b080 {
+                        status = "okay";
+                        phy1: ethernet-phy@1 {
+                                reg = <1>;
+                        };
+                };
                pinctrl@01c20800 {
                        led_pins_cubieboard: led_pins@0 {
                                allwinner,pins = "PH20", "PH21";
@@ -41,6 +56,18 @@
                        pinctrl-0 = <&uart0_pins_a>;
                        status = "okay";
                };
+                i2c0: i2c@01c2ac00 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_pins_a>;
+                        status = "okay";
+                };
+                i2c1: i2c@01c2b000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c1_pins_a>;
+                        status = "okay";
+                };
        };
        leds {
diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
index b9efac100c85..3514b37d66bc 100644
--- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
+++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
@@ -23,10 +23,51 @@
        };
        soc@01c20000 {
+                emac: ethernet@01c0b000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&emac_pins_a>;
+                        phy = <&phy0>;
+                        status = "okay";
+                };
+                mdio@01c0b080 {
+                        phy-supply = <&reg_emac_3v3>;
+                        status = "okay";
+                        phy0: ethernet-phy@0 {
+                                reg = <0>;
+                        };
+                };
+                pio: pinctrl@01c20800 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&hackberry_hogs>;
+                        hackberry_hogs: hogs@0 {
+                                allwinner,pins = "PH19";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                };
                uart0: serial@01c28000 {
                        pinctrl-names = "default";
                        pinctrl-0 = <&uart0_pins_a>;
                        status = "okay";
                };
        };
+        regulators {
+                compatible = "simple-bus";
+                reg_emac_3v3: emac-3v3 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "emac-3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        enable-active-high;
+                        gpio = <&pio 7 19 0>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index e7ef619a70a2..b2bd6e124250 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -16,8 +16,12 @@
        interrupt-parent = <&intc>;
        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
                cpu@0 {
+                        device_type = "cpu";
                        compatible = "arm,cortex-a8";
+                        reg = <0x0>;
                };
        };
@@ -163,6 +167,22 @@
                reg = <0x01c20000 0x300000>;
                ranges;
+                emac: ethernet@01c0b000 {
+                        compatible = "allwinner,sun4i-emac";
+                        reg = <0x01c0b000 0x1000>;
+                        interrupts = <55>;
+                        clocks = <&ahb_gates 17>;
+                        status = "disabled";
+                };
+                mdio@01c0b080 {
+                        compatible = "allwinner,sun4i-mdio";
+                        reg = <0x01c0b080 0x14>;
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
                intc: interrupt-controller@01c20400 {
                        compatible = "allwinner,sun4i-ic";
                        reg = <0x01c20400 0x400>;
@@ -173,8 +193,10 @@
                pio: pinctrl@01c20800 {
                        compatible = "allwinner,sun4i-a10-pinctrl";
                        reg = <0x01c20800 0x400>;
+                        interrupts = <28>;
                        clocks = <&apb0_gates 5>;
                        gpio-controller;
+                        interrupt-controller;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        #gpio-cells = <3>;
@@ -199,6 +221,38 @@
                                allwinner,drive = <0>;
                                allwinner,pull = <0>;
                        };
+                        i2c0_pins_a: i2c0@0 {
+                                allwinner,pins = "PB0", "PB1";
+                                allwinner,function = "i2c0";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                        i2c1_pins_a: i2c1@0 {
+                                allwinner,pins = "PB18", "PB19";
+                                allwinner,function = "i2c1";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                        i2c2_pins_a: i2c2@0 {
+                                allwinner,pins = "PB20", "PB21";
+                                allwinner,function = "i2c2";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                        emac_pins_a: emac0@0 {
+                                allwinner,pins = "PA0", "PA1", "PA2",
+                                                "PA3", "PA4", "PA5", "PA6",
+                                                "PA7", "PA8", "PA9", "PA10",
+                                                "PA11", "PA12", "PA13", "PA14",
+                                                "PA15", "PA16";
+                                allwinner,function = "emac";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
                };
                timer@01c20c00 {
@@ -292,5 +346,32 @@
                        clocks = <&apb1_gates 23>;
                        status = "disabled";
                };
+                i2c0: i2c@01c2ac00 {
+                        compatible = "allwinner,sun4i-i2c";
+                        reg = <0x01c2ac00 0x400>;
+                        interrupts = <7>;
+                        clocks = <&apb1_gates 0>;
+                        clock-frequency = <100000>;
+                        status = "disabled";
+                };
+                i2c1: i2c@01c2b000 {
+                        compatible = "allwinner,sun4i-i2c";
+                        reg = <0x01c2b000 0x400>;
+                        interrupts = <8>;
+                        clocks = <&apb1_gates 1>;
+                        clock-frequency = <100000>;
+                        status = "disabled";
+                };
+                i2c2: i2c@01c2b400 {
+                        compatible = "allwinner,sun4i-i2c";
+                        reg = <0x01c2b400 0x400>;
+                        interrupts = <9>;
+                        clocks = <&apb1_gates 2>;
+                        clock-frequency = <100000>;
+                        status = "disabled";
+                };
        };
 };
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
new file mode 100644
index 000000000000..64dc0c42c43a
--- /dev/null
+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+/include/ "sun5i-a10s.dtsi"
+/ {
+        model = "Olimex A10s-Olinuxino Micro";
+        compatible = "olimex,a10s-olinuxino-micro", "allwinner,sun5i-a10s";
+        soc@01c20000 {
+                emac: ethernet@01c0b000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&emac_pins_a>;
+                        phy = <&phy1>;
+                        status = "okay";
+                };
+                mdio@01c0b080 {
+                        status = "okay";
+                        phy1: ethernet-phy@1 {
+                                reg = <1>;
+                        };
+                };
+                pinctrl@01c20800 {
+                        led_pins_olinuxino: led_pins@0 {
+                                allwinner,pins = "PE3";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <1>;
+                                allwinner,pull = <0>;
+                        };
+                };
+                uart0: serial@01c28000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins_a>;
+                        status = "okay";
+                };
+                uart2: serial@01c28800 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart2_pins_a>;
+                        status = "okay";
+                };
+                uart3: serial@01c28c00 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart3_pins_a>;
+                        status = "okay";
+                };
+        };
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins_olinuxino>;
+                green {
+                        label = "a10s-olinuxino-micro:green:usr";
+                        gpios = <&pio 4 3 0>;
+                        default-state = "on";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
new file mode 100644
index 000000000000..2307ce827ae0
--- /dev/null
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -0,0 +1,286 @@
+/*
+ * Copyright 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/include/ "skeleton.dtsi"
+/ {
+        interrupt-parent = <&intc>;
+        cpus {
+                cpu@0 {
+                        compatible = "arm,cortex-a8";
+                };
+        };
+        memory {
+                reg = <0x40000000 0x20000000>;
+        };
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                /*
+                 * This is a dummy clock, to be used as placeholder on
+                 * other mux clocks when a specific parent clock is not
+                 * yet implemented. It should be dropped when the driver
+                 * is complete.
+                 */
+                dummy: dummy {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <0>;
+                };
+                osc24M: osc24M@01c20050 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-osc-clk";
+                        reg = <0x01c20050 0x4>;
+                        clock-frequency = <24000000>;
+                };
+                osc32k: osc32k {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <32768>;
+                };
+                pll1: pll1@01c20000 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-pll1-clk";
+                        reg = <0x01c20000 0x4>;
+                        clocks = <&osc24M>;
+                };
+                /* dummy is 200M */
+                cpu: cpu@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-cpu-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
+                };
+                axi: axi@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-axi-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&cpu>;
+                };
+                axi_gates: axi_gates@01c2005c {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-axi-gates-clk";
+                        reg = <0x01c2005c 0x4>;
+                        clocks = <&axi>;
+                        clock-output-names = "axi_dram";
+                };
+                ahb: ahb@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-ahb-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&axi>;
+                };
+                ahb_gates: ahb_gates@01c20060 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-ahb-gates-clk";
+                        reg = <0x01c20060 0x8>;
+                        clocks = <&ahb>;
+                        clock-output-names = "ahb_usb0", "ahb_ehci0",
+                                "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
+                                "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
+                                "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
+                                "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
+                                "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
+                                "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
+                                "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
+                                "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
+                                "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
+                                "ahb_de_fe1", "ahb_mp", "ahb_mali400";
+                };
+                apb0: apb0@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-apb0-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&ahb>;
+                };
+                apb0_gates: apb0_gates@01c20068 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-apb0-gates-clk";
+                        reg = <0x01c20068 0x4>;
+                        clocks = <&apb0>;
+                        clock-output-names = "apb0_codec", "apb0_spdif",
+                                "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
+                                "apb0_ir1", "apb0_keypad";
+                };
+                /* dummy is pll62 */
+                apb1_mux: apb1_mux@01c20058 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-apb1-mux-clk";
+                        reg = <0x01c20058 0x4>;
+                        clocks = <&osc24M>, <&dummy>, <&osc32k>;
+                };
+                apb1: apb1@01c20058 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-apb1-clk";
+                        reg = <0x01c20058 0x4>;
+                        clocks = <&apb1_mux>;
+                };
+                apb1_gates: apb1_gates@01c2006c {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-apb1-gates-clk";
+                        reg = <0x01c2006c 0x4>;
+                        clocks = <&apb1>;
+                        clock-output-names = "apb1_i2c0", "apb1_i2c1",
+                                "apb1_i2c2", "apb1_can", "apb1_scr",
+                                "apb1_ps20", "apb1_ps21", "apb1_uart0",
+                                "apb1_uart1", "apb1_uart2", "apb1_uart3",
+                                "apb1_uart4", "apb1_uart5", "apb1_uart6",
+                                "apb1_uart7";
+                };
+        };
+        soc@01c20000 {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0x01c20000 0x300000>;
+                ranges;
+                emac: ethernet@01c0b000 {
+                        compatible = "allwinner,sun4i-emac";
+                        reg = <0x01c0b000 0x1000>;
+                        interrupts = <55>;
+                        clocks = <&ahb_gates 17>;
+                        status = "disabled";
+                };
+                mdio@01c0b080 {
+                        compatible = "allwinner,sun4i-mdio";
+                        reg = <0x01c0b080 0x14>;
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+                intc: interrupt-controller@01c20400 {
+                        compatible = "allwinner,sun4i-ic";
+                        reg = <0x01c20400 0x400>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+                pio: pinctrl@01c20800 {
+                        compatible = "allwinner,sun5i-a10s-pinctrl";
+                        reg = <0x01c20800 0x400>;
+                        interrupts = <28>;
+                        clocks = <&apb0_gates 5>;
+                        gpio-controller;
+                        interrupt-controller;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        #gpio-cells = <3>;
+                        uart0_pins_a: uart0@0 {
+                                allwinner,pins = "PB19", "PB20";
+                                allwinner,function = "uart0";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                        uart2_pins_a: uart2@0 {
+                                allwinner,pins = "PC18", "PC19";
+                                allwinner,function = "uart2";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                        uart3_pins_a: uart3@0 {
+                                allwinner,pins = "PG9", "PG10";
+                                allwinner,function = "uart3";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                        emac_pins_a: emac0@0 {
+                                allwinner,pins = "PA0", "PA1", "PA2",
+                                                "PA3", "PA4", "PA5", "PA6",
+                                                "PA7", "PA8", "PA9", "PA10",
+                                                "PA11", "PA12", "PA13", "PA14",
+                                                "PA15", "PA16";
+                                allwinner,function = "emac";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                };
+                timer@01c20c00 {
+                        compatible = "allwinner,sun4i-timer";
+                        reg = <0x01c20c00 0x90>;
+                        interrupts = <22>;
+                        clocks = <&osc24M>;
+                };
+                wdt: watchdog@01c20c90 {
+                        compatible = "allwinner,sun4i-wdt";
+                        reg = <0x01c20c90 0x10>;
+                };
+                uart0: serial@01c28000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c28000 0x400>;
+                        interrupts = <1>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 16>;
+                        status = "disabled";
+                };
+                uart1: serial@01c28400 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c28400 0x400>;
+                        interrupts = <2>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 17>;
+                        status = "disabled";
+                };
+                uart2: serial@01c28800 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c28800 0x400>;
+                        interrupts = <3>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 18>;
+                        status = "disabled";
+                };
+                uart3: serial@01c28c00 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c28c00 0x400>;
+                        interrupts = <4>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 19>;
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index 3ca55067f868..80497e376706 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -37,6 +37,24 @@
                        pinctrl-0 = <&uart1_pins_b>;
                        status = "okay";
                };
+                i2c0: i2c@01c2ac00 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_pins_a>;
+                        status = "okay";
+                };
+                i2c1: i2c@01c2b000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c1_pins_a>;
+                        status = "okay";
+                };
+                i2c2: i2c@01c2b400 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c2_pins_a>;
+                        status = "okay";
+                };
        };
        leds {
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 31fa38f8cc98..7363211daf84 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -17,8 +17,12 @@
        interrupt-parent = <&intc>;
        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
                cpu@0 {
+                        device_type = "cpu";
                        compatible = "arm,cortex-a8";
+                        reg = <0x0>;
                };
        };
@@ -95,20 +99,15 @@
                ahb_gates: ahb_gates@01c20060 {
                        #clock-cells = <1>;
-                        compatible = "allwinner,sun4i-ahb-gates-clk";
+                        compatible = "allwinner,sun5i-a13-ahb-gates-clk";
                        reg = <0x01c20060 0x8>;
                        clocks = <&ahb>;
-                        clock-output-names = "ahb_usb0", "ahb_ehci0",
+                        clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
-                                "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
+                                "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
-                                "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
+                                "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
-                                "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
+                                "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer",
-                                "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
+                                "ahb_ve", "ahb_lcd", "ahb_csi", "ahb_de_be",
-                                "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
+                                "ahb_de_fe", "ahb_iep", "ahb_mali400";
-                                "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
-                                "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
-                                "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
-                                "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
-                                "ahb_de_fe1", "ahb_mp", "ahb_mali400";
                };
                apb0: apb0@01c20054 {
@@ -120,15 +119,13 @@
                apb0_gates: apb0_gates@01c20068 {
                        #clock-cells = <1>;
-                        compatible = "allwinner,sun4i-apb0-gates-clk";
+                        compatible = "allwinner,sun5i-a13-apb0-gates-clk";
                        reg = <0x01c20068 0x4>;
                        clocks = <&apb0>;
-                        clock-output-names = "apb0_codec", "apb0_spdif",
+                        clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
-                                "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
-                                "apb0_ir1", "apb0_keypad";
                };
-                /* dummy is pll62 */
+                /* dummy is pll6 */
                apb1_mux: apb1_mux@01c20058 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-apb1-mux-clk";
@@ -145,15 +142,11 @@
                apb1_gates: apb1_gates@01c2006c {
                        #clock-cells = <1>;
-                        compatible = "allwinner,sun4i-apb1-gates-clk";
+                        compatible = "allwinner,sun5i-a13-apb1-gates-clk";
                        reg = <0x01c2006c 0x4>;
                        clocks = <&apb1>;
                        clock-output-names = "apb1_i2c0", "apb1_i2c1",
-                                "apb1_i2c2", "apb1_can", "apb1_scr",
+                                "apb1_i2c2", "apb1_uart1", "apb1_uart3";
-                                "apb1_ps20", "apb1_ps21", "apb1_uart0",
-                                "apb1_uart1", "apb1_uart2", "apb1_uart3",
-                                "apb1_uart4", "apb1_uart5", "apb1_uart6",
-                                "apb1_uart7";
                };
        };
@@ -174,8 +167,10 @@
                pio: pinctrl@01c20800 {
                        compatible = "allwinner,sun5i-a13-pinctrl";
                        reg = <0x01c20800 0x400>;
+                        interrupts = <28>;
                        clocks = <&apb0_gates 5>;
                        gpio-controller;
+                        interrupt-controller;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        #gpio-cells = <3>;
@@ -193,6 +188,27 @@
                                allwinner,drive = <0>;
                                allwinner,pull = <0>;
                        };
+                        i2c0_pins_a: i2c0@0 {
+                                allwinner,pins = "PB0", "PB1";
+                                allwinner,function = "i2c0";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                        i2c1_pins_a: i2c1@0 {
+                                allwinner,pins = "PB15", "PB16";
+                                allwinner,function = "i2c1";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                        i2c2_pins_a: i2c2@0 {
+                                allwinner,pins = "PB17", "PB18";
+                                allwinner,function = "i2c2";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
                };
                timer@01c20c00 {
@@ -226,5 +242,32 @@
                        clocks = <&apb1_gates 19>;
                        status = "disabled";
                };
+                i2c0: i2c@01c2ac00 {
+                        compatible = "allwinner,sun4i-i2c";
+                        reg = <0x01c2ac00 0x400>;
+                        interrupts = <7>;
+                        clocks = <&apb1_gates 0>;
+                        clock-frequency = <100000>;
+                        status = "disabled";
+                };
+                i2c1: i2c@01c2b000 {
+                        compatible = "allwinner,sun4i-i2c";
+                        reg = <0x01c2b000 0x400>;
+                        interrupts = <8>;
+                        clocks = <&apb1_gates 1>;
+                        clock-frequency = <100000>;
+                        status = "disabled";
+                };
+                i2c2: i2c@01c2b400 {
+                        compatible = "allwinner,sun4i-i2c";
+                        reg = <0x01c2b400 0x400>;
+                        interrupts = <9>;
+                        clocks = <&apb1_gates 2>;
+                        clock-frequency = <100000>;
+                        status = "disabled";
+                };
        };
 };
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index 72c1f27af7f3..cb640eb6c932 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
-/include/ "tegra114.dtsi"
+#include "tegra114.dtsi"
 / {
        model = "NVIDIA Tegra114 Dalmore evaluation board";
@@ -727,6 +727,16 @@
                        battery-name = "battery";
                        sbs,i2c-retry-count = <2>;
                        sbs,poll-retry-count = <100>;
+                        power-supplies = <&charger>;
+                };
+                rt5640: rt5640 {
+                        compatible = "realtek,rt5640";
+                        reg = <0x1c>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>;
+                        realtek,ldo1-en-gpios =
+                                <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
                };
        };
@@ -748,7 +758,7 @@
                        compatible = "ti,tps65090";
                        reg = <0x48>;
                        interrupt-parent = <&gpio>;
-                        interrupts = <72 0x04>; /* gpio PJ0 */
+                        interrupts = <TEGRA_GPIO(J, 0) IRQ_TYPE_LEVEL_HIGH>;
                        vsys1-supply = <&vdd_ac_bat_reg>;
                        vsys2-supply = <&vdd_ac_bat_reg>;
@@ -763,6 +773,11 @@
                        vsys-l1-supply = <&vdd_ac_bat_reg>;
                        vsys-l2-supply = <&vdd_ac_bat_reg>;
+                        charger: charger {
+                                compatible = "ti,tps65090-charger";
+                                ti,enable-low-current-chrg;
+                        };
                        regulators {
                                tps65090_dcdc1_reg: dcdc1 {
                                        regulator-name = "vdd-sys-5v0";
@@ -823,12 +838,28 @@
                };
        };
+        spi@7000da00 {
+                status = "okay";
+                spi-max-frequency = <25000000>;
+                spi-flash@0 {
+                        compatible = "winbond,w25q32dw";
+                        reg = <0>;
+                        spi-max-frequency = <20000000>;
+                };
+        };
        pmc {
                nvidia,invert-interrupt;
        };
+        ahub {
+                i2s@70080400 {
+                        status = "okay";
+                };
+        };
        sdhci@78000400 {
-                cd-gpios = <&gpio 170 1>; /* gpio PV2 */
+                cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
                bus-width = <4>;
                status = "okay";
        };
@@ -873,7 +904,7 @@
                        regulator-min-microvolt = <1800000>;
                        regulator-max-microvolt = <1800000>;
                        enable-active-high;
-                        gpio = <&gpio 61 0>; /* GPIO PH5 */
+                        gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
                };
                lcd_bl_en_reg: regulator@2 {
@@ -883,7 +914,7 @@
                        regulator-min-microvolt = <5000000>;
                        regulator-max-microvolt = <5000000>;
                        enable-active-high;
-                        gpio = <&gpio 58 0>; /* GPIO PH2 */
+                        gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
                };
                usb1_vbus_reg: regulator@3 {
@@ -893,7 +924,7 @@
                        regulator-min-microvolt = <5000000>;
                        regulator-max-microvolt = <5000000>;
                        enable-active-high;
-                        gpio = <&gpio 108 0>; /* GPIO PN4 */
+                        gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
                        gpio-open-drain;
                        vin-supply = <&tps65090_dcdc1_reg>;
                };
@@ -905,7 +936,7 @@
                        regulator-min-microvolt = <5000000>;
                        regulator-max-microvolt = <5000000>;
                        enable-active-high;
-                        gpio = <&gpio 86 0>; /* GPIO PK6 */
+                        gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
                        gpio-open-drain;
                        vin-supply = <&tps65090_dcdc1_reg>;
                };
@@ -917,8 +948,32 @@
                        regulator-min-microvolt = <5000000>;
                        regulator-max-microvolt = <5000000>;
                        enable-active-high;
-                        gpio = <&gpio 81 0>; /* GPIO PK1 */
+                        gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
                        vin-supply = <&tps65090_dcdc1_reg>;
                };
        };
+        sound {
+                compatible = "nvidia,tegra-audio-rt5640-dalmore",
+                             "nvidia,tegra-audio-rt5640";
+                nvidia,model = "NVIDIA Tegra Dalmore";
+                nvidia,audio-routing =
+                        "Headphones", "HPOR",
+                        "Headphones", "HPOL",
+                        "Speakers", "SPORP",
+                        "Speakers", "SPORN",
+                        "Speakers", "SPOLP",
+                        "Speakers", "SPOLN";
+                nvidia,i2s-controller = <&tegra_i2s1>;
+                nvidia,audio-codec = <&rt5640>;
+                nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
+                clocks = <&tegra_car TEGRA114_CLK_PLL_A>,
+                         <&tegra_car TEGRA114_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA114_CLK_EXTERN1>;
+                clock-names = "pll_a", "pll_a_out0", "mclk";
+        };
 };
diff --git a/arch/arm/boot/dts/tegra114-pluto.dts b/arch/arm/boot/dts/tegra114-pluto.dts
index 6bbc8efae9c0..d5f8d3e0bde2 100644
--- a/arch/arm/boot/dts/tegra114-pluto.dts
+++ b/arch/arm/boot/dts/tegra114-pluto.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
-/include/ "tegra114.dtsi"
+#include "tegra114.dtsi"
 / {
        model = "NVIDIA Tegra114 Pluto evaluation board";
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 629415ffd8dc..abf6c40d28c6 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -1,4 +1,8 @@
-/include/ "skeleton.dtsi"
+#include <dt-bindings/clock/tegra114-car.h>
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "skeleton.dtsi"
 / {
        compatible = "nvidia,tegra114";
@@ -19,19 +23,20 @@
                      <0x50042000 0x1000>,
                      <0x50044000 0x2000>,
                      <0x50046000 0x2000>;
-                interrupts = <1 9 0xf04>;
+                interrupts = <GIC_PPI 9
+                        (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
        };
        timer@60005000 {
                compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
                reg = <0x60005000 0x400>;
-                interrupts = <0 0 0x04
+                interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
-                              0 1 0x04
+                             <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
-                              0 41 0x04
+                             <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
-                              0 42 0x04
+                             <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
-                              0 121 0x04
+                             <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
-                              0 122 0x04>;
+                             <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&tegra_car 5>;
+                clocks = <&tegra_car TEGRA114_CLK_TIMER>;
        };
        tegra_car: clock {
@@ -43,39 +48,39 @@
        apbdma: dma {
                compatible = "nvidia,tegra114-apbdma";
                reg = <0x6000a000 0x1400>;
-                interrupts = <0 104 0x04
+                interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
-                              0 105 0x04
+                             <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
-                              0 106 0x04
+                             <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
-                              0 107 0x04
+                             <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
-                              0 108 0x04
+                             <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
-                              0 109 0x04
+                             <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
-                              0 110 0x04
+                             <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
-                              0 111 0x04
+                             <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
-                              0 112 0x04
+                             <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
-                              0 113 0x04
+                             <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
-                              0 114 0x04
+                             <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
-                              0 115 0x04
+                             <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
-                              0 116 0x04
+                             <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
-                              0 117 0x04
+                             <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
-                              0 118 0x04
+                             <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
-                              0 119 0x04
+                             <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
-                              0 128 0x04
+                             <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
-                              0 129 0x04
+                             <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
-                              0 130 0x04
+                             <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
-                              0 131 0x04
+                             <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
-                              0 132 0x04
+                             <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
-                              0 133 0x04
+                             <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
-                              0 134 0x04
+                             <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
-                              0 135 0x04
+                             <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
-                              0 136 0x04
+                             <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
-                              0 137 0x04
+                             <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
-                              0 138 0x04
+                             <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
-                              0 139 0x04
+                             <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
-                              0 140 0x04
+                             <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
-                              0 141 0x04
+                             <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
-                              0 142 0x04
+                             <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-                              0 143 0x04>;
+                             <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&tegra_car 34>;
+                clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
        };
        ahb: ahb {
@@ -86,14 +91,14 @@
        gpio: gpio {
                compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
                reg = <0x6000d000 0x1000>;
-                interrupts = <0 32 0x04
+                interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
-                              0 33 0x04
+                             <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
-                              0 34 0x04
+                             <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
-                              0 35 0x04
+                             <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
-                              0 55 0x04
+                             <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
-                              0 87 0x04
+                             <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
-                              0 89 0x04
+                             <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
-                              0 125 0x04>;
+                             <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
                #interrupt-cells = <2>;
@@ -118,57 +123,57 @@
                compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
                reg = <0x70006000 0x40>;
                reg-shift = <2>;
-                interrupts = <0 36 0x04>;
+                interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 8>;
                status = "disabled";
-                clocks = <&tegra_car 6>;
+                clocks = <&tegra_car TEGRA114_CLK_UARTA>;
        };
        uartb: serial@70006040 {
                compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
                reg = <0x70006040 0x40>;
                reg-shift = <2>;
-                interrupts = <0 37 0x04>;
+                interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 9>;
                status = "disabled";
-                clocks = <&tegra_car 192>;
+                clocks = <&tegra_car TEGRA114_CLK_UARTB>;
        };
        uartc: serial@70006200 {
                compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
                reg = <0x70006200 0x100>;
                reg-shift = <2>;
-                interrupts = <0 46 0x04>;
+                interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 10>;
                status = "disabled";
-                clocks = <&tegra_car 55>;
+                clocks = <&tegra_car TEGRA114_CLK_UARTC>;
        };
        uartd: serial@70006300 {
                compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
                reg = <0x70006300 0x100>;
                reg-shift = <2>;
-                interrupts = <0 90 0x04>;
+                interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 19>;
                status = "disabled";
-                clocks = <&tegra_car 65>;
+                clocks = <&tegra_car TEGRA114_CLK_UARTD>;
        };
        pwm: pwm {
                compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
                reg = <0x7000a000 0x100>;
                #pwm-cells = <2>;
-                clocks = <&tegra_car 17>;
+                clocks = <&tegra_car TEGRA114_CLK_PWM>;
                status = "disabled";
        };
        i2c@7000c000 {
                compatible = "nvidia,tegra114-i2c";
                reg = <0x7000c000 0x100>;
-                interrupts = <0 38 0x04>;
+                interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&tegra_car 12>;
+                clocks = <&tegra_car TEGRA114_CLK_I2C1>;
                clock-names = "div-clk";
                status = "disabled";
        };
@@ -176,10 +181,10 @@
        i2c@7000c400 {
                compatible = "nvidia,tegra114-i2c";
                reg = <0x7000c400 0x100>;
-                interrupts = <0 84 0x04>;
+                interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&tegra_car 54>;
+                clocks = <&tegra_car TEGRA114_CLK_I2C2>;
                clock-names = "div-clk";
                status = "disabled";
        };
@@ -187,10 +192,10 @@
        i2c@7000c500 {
                compatible = "nvidia,tegra114-i2c";
                reg = <0x7000c500 0x100>;
-                interrupts = <0 92 0x04>;
+                interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&tegra_car 67>;
+                clocks = <&tegra_car TEGRA114_CLK_I2C3>;
                clock-names = "div-clk";
                status = "disabled";
        };
@@ -198,10 +203,10 @@
        i2c@7000c700 {
                compatible = "nvidia,tegra114-i2c";
                reg = <0x7000c700 0x100>;
-                interrupts = <0 120 0x04>;
+                interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&tegra_car 103>;
+                clocks = <&tegra_car TEGRA114_CLK_I2C4>;
                clock-names = "div-clk";
                status = "disabled";
        };
@@ -209,10 +214,10 @@
        i2c@7000d000 {
                compatible = "nvidia,tegra114-i2c";
                reg = <0x7000d000 0x100>;
-                interrupts = <0 53 0x04>;
+                interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&tegra_car 47>;
+                clocks = <&tegra_car TEGRA114_CLK_I2C5>;
                clock-names = "div-clk";
                status = "disabled";
        };
@@ -220,11 +225,11 @@
        spi@7000d400 {
                compatible = "nvidia,tegra114-spi";
                reg = <0x7000d400 0x200>;
-                interrupts = <0 59 0x04>;
+                interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 15>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&tegra_car 41>;
+                clocks = <&tegra_car TEGRA114_CLK_SBC1>;
                clock-names = "spi";
                status = "disabled";
        };
@@ -232,11 +237,11 @@
        spi@7000d600 {
                compatible = "nvidia,tegra114-spi";
                reg = <0x7000d600 0x200>;
-                interrupts = <0 82 0x04>;
+                interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 16>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&tegra_car 44>;
+                clocks = <&tegra_car TEGRA114_CLK_SBC2>;
                clock-names = "spi";
                status = "disabled";
        };
@@ -244,11 +249,11 @@
        spi@7000d800 {
                compatible = "nvidia,tegra114-spi";
                reg = <0x7000d800 0x200>;
-                interrupts = <0 83 0x04>;
+                interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 17>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&tegra_car 46>;
+                clocks = <&tegra_car TEGRA114_CLK_SBC3>;
                clock-names = "spi";
                status = "disabled";
        };
@@ -256,11 +261,11 @@
        spi@7000da00 {
                compatible = "nvidia,tegra114-spi";
                reg = <0x7000da00 0x200>;
-                interrupts = <0 93 0x04>;
+                interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 18>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&tegra_car 68>;
+                clocks = <&tegra_car TEGRA114_CLK_SBC4>;
                clock-names = "spi";
                status = "disabled";
        };
@@ -268,11 +273,11 @@
        spi@7000dc00 {
                compatible = "nvidia,tegra114-spi";
                reg = <0x7000dc00 0x200>;
-                interrupts = <0 94 0x04>;
+                interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 27>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&tegra_car 104>;
+                clocks = <&tegra_car TEGRA114_CLK_SBC5>;
                clock-names = "spi";
                status = "disabled";
        };
@@ -280,11 +285,11 @@
        spi@7000de00 {
                compatible = "nvidia,tegra114-spi";
                reg = <0x7000de00 0x200>;
-                interrupts = <0 79 0x04>;
+                interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 28>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&tegra_car 105>;
+                clocks = <&tegra_car TEGRA114_CLK_SBC6>;
                clock-names = "spi";
                status = "disabled";
        };
@@ -292,22 +297,22 @@
        rtc {
                compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
                reg = <0x7000e000 0x100>;
-                interrupts = <0 2 0x04>;
+                interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&tegra_car 4>;
+                clocks = <&tegra_car TEGRA114_CLK_RTC>;
        };
        kbc {
                compatible = "nvidia,tegra114-kbc";
                reg = <0x7000e200 0x100>;
-                interrupts = <0 85 0x04>;
+                interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&tegra_car 36>;
+                clocks = <&tegra_car TEGRA114_CLK_KBC>;
                status = "disabled";
        };
        pmc {
                compatible = "nvidia,tegra114-pmc";
                reg = <0x7000e400 0x400>;
-                clocks = <&tegra_car 261>, <&clk32k_in>;
+                clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
                clock-names = "pclk", "clk32k_in";
        };
@@ -322,35 +327,106 @@
                nvidia,ahb = <&ahb>;
        };
+        ahub {
+                compatible = "nvidia,tegra114-ahub";
+                reg = <0x70080000 0x200>,
+                      <0x70080200 0x100>,
+                      <0x70081000 0x200>;
+                interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+                nvidia,dma-request-selector = <&apbdma 1>, <&apbdma 2>,
+                        <&apbdma 3>, <&apbdma 4>, <&apbdma 6>, <&apbdma 7>,
+                        <&apbdma 12>, <&apbdma 13>, <&apbdma 14>,
+                        <&apbdma 29>;
+                clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
+                         <&tegra_car TEGRA114_CLK_APBIF>,
+                         <&tegra_car TEGRA114_CLK_I2S0>,
+                         <&tegra_car TEGRA114_CLK_I2S1>,
+                         <&tegra_car TEGRA114_CLK_I2S2>,
+                         <&tegra_car TEGRA114_CLK_I2S3>,
+                         <&tegra_car TEGRA114_CLK_I2S4>,
+                         <&tegra_car TEGRA114_CLK_DAM0>,
+                         <&tegra_car TEGRA114_CLK_DAM1>,
+                         <&tegra_car TEGRA114_CLK_DAM2>,
+                         <&tegra_car TEGRA114_CLK_SPDIF_IN>,
+                         <&tegra_car TEGRA114_CLK_AMX>,
+                         <&tegra_car TEGRA114_CLK_ADX>;
+                clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
+                              "i2s3", "i2s4", "dam0", "dam1", "dam2",
+                              "spdif_in", "amx", "adx";
+                ranges;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                tegra_i2s0: i2s@70080300 {
+                        compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
+                        reg = <0x70080300 0x100>;
+                        nvidia,ahub-cif-ids = <4 4>;
+                        clocks = <&tegra_car TEGRA114_CLK_I2S0>;
+                        status = "disabled";
+                };
+                tegra_i2s1: i2s@70080400 {
+                        compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
+                        reg = <0x70080400 0x100>;
+                        nvidia,ahub-cif-ids = <5 5>;
+                        clocks = <&tegra_car TEGRA114_CLK_I2S1>;
+                        status = "disabled";
+                };
+                tegra_i2s2: i2s@70080500 {
+                        compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
+                        reg = <0x70080500 0x100>;
+                        nvidia,ahub-cif-ids = <6 6>;
+                        clocks = <&tegra_car TEGRA114_CLK_I2S2>;
+                        status = "disabled";
+                };
+                tegra_i2s3: i2s@70080600 {
+                        compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
+                        reg = <0x70080600 0x100>;
+                        nvidia,ahub-cif-ids = <7 7>;
+                        clocks = <&tegra_car TEGRA114_CLK_I2S3>;
+                        status = "disabled";
+                };
+                tegra_i2s4: i2s@70080700 {
+                        compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
+                        reg = <0x70080700 0x100>;
+                        nvidia,ahub-cif-ids = <8 8>;
+                        clocks = <&tegra_car TEGRA114_CLK_I2S4>;
+                        status = "disabled";
+                };
+        };
        sdhci@78000000 {
                compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
                reg = <0x78000000 0x200>;
-                interrupts = <0 14 0x04>;
+                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&tegra_car 14>;
+                clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
                status = "disable";
        };
        sdhci@78000200 {
                compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
                reg = <0x78000200 0x200>;
-                interrupts = <0 15 0x04>;
+                interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&tegra_car 9>;
+                clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
                status = "disable";
        };
        sdhci@78000400 {
                compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
                reg = <0x78000400 0x200>;
-                interrupts = <0 19 0x04>;
+                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&tegra_car 69>;
+                clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
                status = "disable";
        };
        sdhci@78000600 {
                compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
                reg = <0x78000600 0x200>;
-                interrupts = <0 31 0x04>;
+                interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&tegra_car 15>;
+                clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
                status = "disable";
        };
@@ -385,9 +461,14 @@
        timer {
                compatible = "arm,armv7-timer";
-                interrupts = <1 13 0xf08>,
+                interrupts =
-                             <1 14 0xf08>,
+                        <GIC_PPI 13
-                             <1 11 0xf08>,
+                                (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-                             <1 10 0xf08>;
+                        <GIC_PPI 14
+                                (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                        <GIC_PPI 11
+                                (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                        <GIC_PPI 10
+                                (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
        };
 };
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index a573b94b7c93..5592be6f2f7a 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -1,4 +1,4 @@
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsi"
 / {
        model = "Toradex Colibri T20 512MB";
@@ -14,7 +14,8 @@
                        pll-supply = <&hdmi_pll_reg>;
                        nvidia,ddc-i2c-bus = <&i2c_ddc>;
-                        nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+                        nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+                                GPIO_ACTIVE_HIGH>;
                };
        };
@@ -217,7 +218,7 @@
                pmic: tps6586x@34 {
                        compatible = "ti,tps6586x";
                        reg = <0x34>;
-                        interrupts = <0 86 0x4>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
                        ti,system-power-controller;
@@ -443,17 +444,26 @@
        ac97: ac97 {
                status = "okay";
-                nvidia,codec-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+                nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
-                nvidia,codec-sync-gpio = <&gpio 120 0>; /* gpio PP0 */
+                        GPIO_ACTIVE_HIGH>;
+                nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0)
+                        GPIO_ACTIVE_HIGH>;
        };
        usb@c5004000 {
                status = "okay";
-                nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+                        GPIO_ACTIVE_LOW>;
+        };
+        usb-phy@c5004000 {
+                status = "okay";
+                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+                        GPIO_ACTIVE_LOW>;
        };
        sdhci@c8000600 {
-                cd-gpios = <&gpio 23 1>; /* gpio PC7 */
+                cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
        };
        clocks {
@@ -483,7 +493,9 @@
                nvidia,ac97-controller = <&ac97>;
-                clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+                clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+                         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA20_CLK_CDEV1>;
                clock-names = "pll_a", "pll_a_out0", "mclk";
        };
@@ -510,7 +522,7 @@
                        enable-active-high;
                        regulator-boot-on;
                        regulator-always-on;
-                        gpio = <&gpio 217 0>;
+                        gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
                };
        };
 };
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index e7d5de4e00b9..d9f89cd879a7 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsi"
 / {
        model = "NVIDIA Tegra20 Harmony evaluation board";
@@ -18,7 +18,8 @@
                        pll-supply = <&hdmi_pll_reg>;
                        nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-                        nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+                        nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+                                GPIO_ACTIVE_HIGH>;
                };
        };
@@ -262,7 +263,7 @@
                        compatible = "wlf,wm8903";
                        reg = <0x1a>;
                        interrupt-parent = <&gpio>;
-                        interrupts = <187 0x04>;
+                        interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
                        gpio-controller;
                        #gpio-cells = <2>;
@@ -290,7 +291,7 @@
                pmic: tps6586x@34 {
                        compatible = "ti,tps6586x";
                        reg = <0x34>;
-                        interrupts = <0 86 0x4>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
                        ti,system-power-controller;
@@ -428,32 +429,43 @@
                status = "okay";
        };
+        usb-phy@c5000000 {
+                status = "okay";
+        };
        usb@c5004000 {
                status = "okay";
-                nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+                        GPIO_ACTIVE_LOW>;
+        };
+        usb-phy@c5004000 {
+                status = "okay";
+                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+                        GPIO_ACTIVE_LOW>;
        };
        usb@c5008000 {
                status = "okay";
        };
-        usb-phy@c5004400 {
+        usb-phy@c5008000 {
-                nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+                status = "okay";
        };
        sdhci@c8000200 {
                status = "okay";
-                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
+                cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
-                wp-gpios = <&gpio 57 0>; /* gpio PH1 */
+                wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
-                power-gpios = <&gpio 155 0>; /* gpio PT3 */
+                power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
                bus-width = <4>;
        };
        sdhci@c8000600 {
                status = "okay";
-                cd-gpios = <&gpio 58 1>; /* gpio PH2 */
+                cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
-                wp-gpios = <&gpio 59 0>; /* gpio PH3 */
+                wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
-                power-gpios = <&gpio 70 0>; /* gpio PI6 */
+                power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
                bus-width = <8>;
        };
@@ -475,7 +487,7 @@
                power {
                        label = "Power";
-                        gpios = <&gpio 170 1>; /* gpio PV2, active low */
+                        gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
                        linux,code = <116>; /* KEY_POWER */
                        gpio-key,wakeup;
                };
@@ -618,7 +630,7 @@
                        regulator-name = "vdd_1v5";
                        regulator-min-microvolt = <1500000>;
                        regulator-max-microvolt = <1500000>;
-                        gpio = <&pmic 0 0>;
+                        gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
                };
                regulator@2 {
@@ -627,7 +639,7 @@
                        regulator-name = "vdd_1v2";
                        regulator-min-microvolt = <1200000>;
                        regulator-max-microvolt = <1200000>;
-                        gpio = <&pmic 1 0>;
+                        gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
                        enable-active-high;
                };
@@ -637,7 +649,7 @@
                        regulator-name = "vdd_1v05";
                        regulator-min-microvolt = <1050000>;
                        regulator-max-microvolt = <1050000>;
-                        gpio = <&pmic 2 0>;
+                        gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
                        enable-active-high;
                        /* Hack until board-harmony-pcie.c is removed */
                        status = "disabled";
@@ -649,7 +661,7 @@
                        regulator-name = "vdd_pnl";
                        regulator-min-microvolt = <2800000>;
                        regulator-max-microvolt = <2800000>;
-                        gpio = <&gpio 22 0>; /* gpio PC6 */
+                        gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
                        enable-active-high;
                };
@@ -659,7 +671,7 @@
                        regulator-name = "vdd_bl";
                        regulator-min-microvolt = <2800000>;
                        regulator-max-microvolt = <2800000>;
-                        gpio = <&gpio 176 0>; /* gpio PW0 */
+                        gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
                        enable-active-high;
                };
        };
@@ -682,12 +694,17 @@
                nvidia,i2s-controller = <&tegra_i2s1>;
                nvidia,audio-codec = <&wm8903>;
-                nvidia,spkr-en-gpios = <&wm8903 2 0>;
+                nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
-                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+                nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
-                nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
+                        GPIO_ACTIVE_HIGH>;
-                nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
+                nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
+                        GPIO_ACTIVE_HIGH>;
-                clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+                nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
+                        GPIO_ACTIVE_HIGH>;
+                clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+                         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA20_CLK_CDEV1>;
                clock-names = "pll_a", "pll_a_out0", "mclk";
        };
 };
diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts b/arch/arm/boot/dts/tegra20-iris-512.dts
index 52f1103907d7..f2222bd74eab 100644
--- a/arch/arm/boot/dts/tegra20-iris-512.dts
+++ b/arch/arm/boot/dts/tegra20-iris-512.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
-/include/ "tegra20-colibri-512.dtsi"
+#include "tegra20-colibri-512.dtsi"
 / {
        model = "Toradex Colibri T20 512MB on Iris";
@@ -38,13 +38,20 @@
        usb@c5000000 {
                status = "okay";
-                dr_mode = "otg";
+        };
+        usb-phy@c5000000 {
+                status = "okay";
        };
        usb@c5008000 {
                status = "okay";
        };
+        usb-phy@c5008000 {
+                status = "okay";
+        };
        serial@70006000 {
                status = "okay";
        };
@@ -73,7 +80,7 @@
                        regulator-max-microvolt = <5000000>;
                        regulator-boot-on;
                        regulator-always-on;
-                        gpio = <&gpio 178 0>;
+                        gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
                };
                vcc_sd_reg: regulator@1 {
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts
index ace23437da89..7580578903cf 100644
--- a/arch/arm/boot/dts/tegra20-medcom-wide.dts
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
-/include/ "tegra20-tamonten.dtsi"
+#include "tegra20-tamonten.dtsi"
 / {
        model = "Avionic Design Medcom-Wide board";
@@ -15,7 +15,7 @@
                        compatible = "wlf,wm8903";
                        reg = <0x1a>;
                        interrupt-parent = <&gpio>;
-                        interrupts = <187 0x04>;
+                        interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
                        gpio-controller;
                        #gpio-cells = <2>;
@@ -56,10 +56,12 @@
                nvidia,i2s-controller = <&tegra_i2s1>;
                nvidia,audio-codec = <&wm8903>;
-                nvidia,spkr-en-gpios = <&wm8903 2 0>;
+                nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
-                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+                nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
-                clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+                clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+                         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA20_CLK_CDEV1>;
                clock-names = "pll_a", "pll_a_out0", "mclk";
        };
 };
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index e3e0c9977df4..cfd12763b1b2 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsi"
 / {
        model = "Toshiba AC100 / Dynabook AZ";
@@ -18,7 +18,8 @@
                        pll-supply = <&hdmi_pll_reg>;
                        nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-                        nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+                        nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+                                GPIO_ACTIVE_HIGH>;
                };
        };
@@ -270,13 +271,14 @@
        nvec {
                compatible = "nvidia,nvec";
                reg = <0x7000c500 0x100>;
-                interrupts = <0 92 0x04>;
+                interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
                clock-frequency = <80000>;
-                request-gpios = <&gpio 170 0>; /* gpio PV2 */
+                request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
                slave-addr = <138>;
-                clocks = <&tegra_car 67>, <&tegra_car 124>;
+                clocks = <&tegra_car TEGRA20_CLK_I2C3>,
+                         <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
                clock-names = "div-clk", "fast-clk";
        };
@@ -287,7 +289,7 @@
                pmic: tps6586x@34 {
                        compatible = "ti,tps6586x";
                        reg = <0x34>;
-                        interrupts = <0 86 0x4>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
                        #gpio-cells = <2>;
                        gpio-controller;
@@ -427,24 +429,35 @@
                status = "okay";
        };
+        usb-phy@c5000000 {
+                status = "okay";
+        };
        usb@c5004000 {
                status = "okay";
-                nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+                        GPIO_ACTIVE_LOW>;
+        };
+        usb-phy@c5004000 {
+                status = "okay";
+                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+                        GPIO_ACTIVE_LOW>;
        };
        usb@c5008000 {
                status = "okay";
        };
-        usb-phy@c5004400 {
+        usb-phy@c5008000 {
-                nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+                status = "okay";
        };
        sdhci@c8000000 {
                status = "okay";
-                cd-gpios = <&gpio 173 1>; /* gpio PV5 */
+                cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
-                wp-gpios = <&gpio 57 0>;  /* gpio PH1 */
+                wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
-                power-gpios = <&gpio 169 0>; /* gpio PV1 */
+                power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
                bus-width = <4>;
        };
@@ -472,7 +485,7 @@
                power {
                        label = "Power";
-                        gpios = <&gpio 79 1>; /* gpio PJ7, active low */
+                        gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
                        linux,code = <116>; /* KEY_POWER */
                        gpio-key,wakeup;
                };
@@ -483,7 +496,7 @@
                wifi {
                        label = "wifi-led";
-                        gpios = <&gpio 24 0>; /* gpio PD0 */
+                        gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
                        linux,default-trigger = "rfkill0";
                };
        };
@@ -520,9 +533,12 @@
                nvidia,audio-codec = <&alc5632>;
                nvidia,i2s-controller = <&tegra_i2s1>;
-                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+                nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
+                        GPIO_ACTIVE_HIGH>;
-                clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+                clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+                         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA20_CLK_CDEV1>;
                clock-names = "pll_a", "pll_a_out0", "mclk";
        };
 };
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts
index 1a17cc30bb9d..d7a358a6a647 100644
--- a/arch/arm/boot/dts/tegra20-plutux.dts
+++ b/arch/arm/boot/dts/tegra20-plutux.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
-/include/ "tegra20-tamonten.dtsi"
+#include "tegra20-tamonten.dtsi"
 / {
        model = "Avionic Design Plutux board";
@@ -17,7 +17,7 @@
                        compatible = "wlf,wm8903";
                        reg = <0x1a>;
                        interrupt-parent = <&gpio>;
-                        interrupts = <187 0x04>;
+                        interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
                        gpio-controller;
                        #gpio-cells = <2>;
@@ -50,10 +50,12 @@
                nvidia,i2s-controller = <&tegra_i2s1>;
                nvidia,audio-codec = <&wm8903>;
-                nvidia,spkr-en-gpios = <&wm8903 2 0>;
+                nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
-                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+                nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
-                clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+                clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+                         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA20_CLK_CDEV1>;
                clock-names = "pll_a", "pll_a_out0", "mclk";
        };
 };
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index cee4c34010fe..365760b33a26 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsi"
 / {
        model = "NVIDIA Seaboard";
@@ -18,7 +18,8 @@
                        pll-supply = <&hdmi_pll_reg>;
                        nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-                        nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+                        nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+                                GPIO_ACTIVE_HIGH>;
                };
        };
@@ -313,7 +314,7 @@
                        compatible = "wlf,wm8903";
                        reg = <0x1a>;
                        interrupt-parent = <&gpio>;
-                        interrupts = <187 0x04>;
+                        interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
                        gpio-controller;
                        #gpio-cells = <2>;
@@ -328,14 +329,14 @@
                        compatible = "isil,isl29018";
                        reg = <0x44>;
                        interrupt-parent = <&gpio>;
-                        interrupts = <202 0x04>; /* GPIO PZ2 */
+                        interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
                };
                gyrometer@68 {
                        compatible = "invn,mpu3050";
                        reg = <0x68>;
                        interrupt-parent = <&gpio>;
-                        interrupts = <204 0x04>; /* gpio PZ4 */
+                        interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_LEVEL_HIGH>;
                };
        };
@@ -388,7 +389,7 @@
                pmic: tps6586x@34 {
                        compatible = "ti,tps6586x";
                        reg = <0x34>;
-                        interrupts = <0 86 0x4>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
                        ti,system-power-controller;
@@ -511,7 +512,7 @@
                        compatible = "ak,ak8975";
                        reg = <0xc>;
                        interrupt-parent = <&gpio>;
-                        interrupts = <109 0x04>; /* gpio PN5 */
+                        interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>;
                };
        };
@@ -565,35 +566,48 @@
        usb@c5000000 {
                status = "okay";
-                nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
+                nvidia,vbus-gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
+                dr_mode = "otg";
+        };
+        usb-phy@c5000000 {
+                status = "okay";
+                vbus-supply = <&vbus_reg>;
                dr_mode = "otg";
        };
        usb@c5004000 {
                status = "okay";
-                nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+                        GPIO_ACTIVE_LOW>;
+        };
+        usb-phy@c5004000 {
+                status = "okay";
+                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+                        GPIO_ACTIVE_LOW>;
        };
        usb@c5008000 {
                status = "okay";
        };
-        usb-phy@c5004400 {
+        usb-phy@c5008000 {
-                nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+                status = "okay";
        };
        sdhci@c8000000 {
                status = "okay";
-                power-gpios = <&gpio 86 0>; /* gpio PK6 */
+                power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
                bus-width = <4>;
                keep-power-in-suspend;
        };
        sdhci@c8000400 {
                status = "okay";
-                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
+                cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
-                wp-gpios = <&gpio 57 0>; /* gpio PH1 */
+                wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
-                power-gpios = <&gpio 70 0>; /* gpio PI6 */
+                power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
                bus-width = <4>;
        };
@@ -621,14 +635,14 @@
                power {
                        label = "Power";
-                        gpios = <&gpio 170 1>; /* gpio PV2, active low */
+                        gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
                        linux,code = <116>; /* KEY_POWER */
                        gpio-key,wakeup;
                };
                lid {
                        label = "Lid";
-                        gpios = <&gpio 23 0>; /* gpio PC7 */
+                        gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
                        linux,input-type = <5>; /* EV_SW */
                        linux,code = <0>; /* SW_LID */
                        debounce-interval = <1>;
@@ -795,7 +809,7 @@
                        regulator-name = "vdd_1v5";
                        regulator-min-microvolt = <1500000>;
                        regulator-max-microvolt = <1500000>;
-                        gpio = <&pmic 0 0>;
+                        gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
                };
                regulator@2 {
@@ -804,8 +818,18 @@
                        regulator-name = "vdd_1v2";
                        regulator-min-microvolt = <1200000>;
                        regulator-max-microvolt = <1200000>;
-                        gpio = <&pmic 1 0>;
+                        gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                };
+                vbus_reg: regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "vdd_vbus_wup1";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
                        enable-active-high;
+                        gpio = <&gpio 24 0>; /* PD0 */
                };
        };
@@ -827,10 +851,12 @@
                nvidia,i2s-controller = <&tegra_i2s1>;
                nvidia,audio-codec = <&wm8903>;
-                nvidia,spkr-en-gpios = <&wm8903 2 0>;
+                nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
-                nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */
+                nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>;
-                clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+                clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+                         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA20_CLK_CDEV1>;
                clock-names = "pll_a", "pll_a_out0", "mclk";
        };
 };
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index 50b3ec16b93a..c54faae7cfb3 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -1,4 +1,4 @@
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsi"
 / {
        model = "Avionic Design Tamonten SOM";
@@ -14,7 +14,8 @@
                        pll-supply = <&hdmi_pll_reg>;
                        nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-                        nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+                        nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+                                GPIO_ACTIVE_HIGH>;
                };
        };
@@ -321,7 +322,7 @@
                pmic: tps6586x@34 {
                        compatible = "ti,tps6586x";
                        reg = <0x34>;
-                        interrupts = <0 86 0x4>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
                        ti,system-power-controller;
@@ -470,9 +471,13 @@
                status = "okay";
        };
+        usb-phy@c5008000 {
+                status = "okay";
+        };
        sdhci@c8000600 {
-                cd-gpios = <&gpio 58 1>; /* gpio PH2 */
+                cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
-                wp-gpios = <&gpio 59 0>; /* gpio PH3 */
+                wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
                bus-width = <4>;
                status = "okay";
        };
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts
index 742f0b38d21d..c572c43751b1 100644
--- a/arch/arm/boot/dts/tegra20-tec.dts
+++ b/arch/arm/boot/dts/tegra20-tec.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
-/include/ "tegra20-tamonten.dtsi"
+#include "tegra20-tamonten.dtsi"
 / {
        model = "Avionic Design Tamonten Evaluation Carrier";
@@ -17,7 +17,7 @@
                        compatible = "wlf,wm8903";
                        reg = <0x1a>;
                        interrupt-parent = <&gpio>;
-                        interrupts = <187 0x04>;
+                        interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
                        gpio-controller;
                        #gpio-cells = <2>;
@@ -50,10 +50,13 @@
                nvidia,i2s-controller = <&tegra_i2s1>;
                nvidia,audio-codec = <&wm8903>;
-                nvidia,spkr-en-gpios = <&wm8903 2 0>;
+                nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
-                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+                nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
+                        GPIO_ACTIVE_HIGH>;
-                clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+                clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+                         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA20_CLK_CDEV1>;
                clock-names = "pll_a", "pll_a_out0", "mclk";
        };
 };
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 9cc78a15d739..ed4b901b0227 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsi"
 / {
        model = "Compulab TrimSlice board";
@@ -18,7 +18,8 @@
                        pll-supply = <&hdmi_pll_reg>;
                        nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-                        nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+                        nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+                                GPIO_ACTIVE_HIGH>;
                };
        };
@@ -311,20 +312,32 @@
        usb@c5000000 {
                status = "okay";
-                nvidia,vbus-gpio = <&gpio 170 0>; /* gpio PV2 */
+                nvidia,vbus-gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
+        };
+        usb-phy@c5000000 {
+                status = "okay";
+                vbus-supply = <&vbus_reg>;
        };
        usb@c5004000 {
                status = "okay";
-                nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+                        GPIO_ACTIVE_LOW>;
+        };
+        usb-phy@c5004000 {
+                status = "okay";
+                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+                        GPIO_ACTIVE_LOW>;
        };
        usb@c5008000 {
                status = "okay";
        };
-        usb-phy@c5004400 {
+        usb-phy@c5008000 {
-                nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+                status = "okay";
        };
        sdhci@c8000000 {
@@ -334,8 +347,8 @@
        sdhci@c8000600 {
                status = "okay";
-                cd-gpios = <&gpio 121 1>; /* gpio PP1 */
+                cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>;
-                wp-gpios = <&gpio 122 0>; /* gpio PP2 */
+                wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
                bus-width = <4>;
        };
@@ -357,7 +370,7 @@
                power {
                        label = "Power";
-                        gpios = <&gpio 190 1>; /* gpio PX6, active low */
+                        gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
                        linux,code = <116>; /* KEY_POWER */
                        gpio-key,wakeup;
                };
@@ -365,7 +378,7 @@
        poweroff {
                compatible = "gpio-poweroff";
-                gpios = <&gpio 191 1>; /* gpio PX7, active low */
+                gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
        };
        regulators {
@@ -390,6 +403,16 @@
                        regulator-max-microvolt = <1800000>;
                        regulator-always-on;
                };
+                vbus_reg: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "usb1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        gpio = <&gpio 170 0>; /* PV2 */
+                };
        };
        sound {
@@ -397,7 +420,9 @@
                nvidia,i2s-controller = <&tegra_i2s1>;
                nvidia,audio-codec = <&codec>;
-                clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+                clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+                         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA20_CLK_CDEV1>;
                clock-names = "pll_a", "pll_a_out0", "mclk";
        };
 };
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index dd38f1f03834..7f8c28d1121f 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsi"
 / {
        model = "NVIDIA Tegra20 Ventana evaluation board";
@@ -18,7 +18,8 @@
                        pll-supply = <&hdmi_pll_reg>;
                        nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-                        nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+                        nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+                                GPIO_ACTIVE_HIGH>;
                };
        };
@@ -310,7 +311,7 @@
                        compatible = "wlf,wm8903";
                        reg = <0x1a>;
                        interrupt-parent = <&gpio>;
-                        interrupts = <187 0x04>;
+                        interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
                        gpio-controller;
                        #gpio-cells = <2>;
@@ -325,7 +326,7 @@
                        compatible = "isil,isl29018";
                        reg = <0x44>;
                        interrupt-parent = <&gpio>;
-                        interrupts = <202 0x04>; /*gpio PZ2 */
+                        interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
                };
        };
@@ -371,7 +372,7 @@
                pmic: tps6586x@34 {
                        compatible = "ti,tps6586x";
                        reg = <0x34>;
-                        interrupts = <0 86 0x4>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
                        ti,system-power-controller;
@@ -505,31 +506,42 @@
                status = "okay";
        };
+        usb-phy@c5000000 {
+                status = "okay";
+        };
        usb@c5004000 {
                status = "okay";
-                nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+                        GPIO_ACTIVE_LOW>;
+        };
+        usb-phy@c5004000 {
+                status = "okay";
+                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+                        GPIO_ACTIVE_LOW>;
        };
        usb@c5008000 {
                status = "okay";
        };
-        usb-phy@c5004400 {
+        usb-phy@c5008000 {
-                nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+                status = "okay";
        };
        sdhci@c8000000 {
                status = "okay";
-                power-gpios = <&gpio 86 0>; /* gpio PK6 */
+                power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
                bus-width = <4>;
                keep-power-in-suspend;
        };
        sdhci@c8000400 {
                status = "okay";
-                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
+                cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
-                wp-gpios = <&gpio 57 0>; /* gpio PH1 */
+                wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
-                power-gpios = <&gpio 70 0>; /* gpio PI6 */
+                power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
                bus-width = <4>;
        };
@@ -557,7 +569,7 @@
                power {
                        label = "Power";
-                        gpios = <&gpio 170 1>; /* gpio PV2, active low */
+                        gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
                        linux,code = <116>; /* KEY_POWER */
                        gpio-key,wakeup;
                };
@@ -583,7 +595,7 @@
                        regulator-name = "vdd_1v5";
                        regulator-min-microvolt = <1500000>;
                        regulator-max-microvolt = <1500000>;
-                        gpio = <&pmic 0 0>;
+                        gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
                };
                regulator@2 {
@@ -592,7 +604,7 @@
                        regulator-name = "vdd_1v2";
                        regulator-min-microvolt = <1200000>;
                        regulator-max-microvolt = <1200000>;
-                        gpio = <&pmic 1 0>;
+                        gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
                        enable-active-high;
                };
@@ -602,7 +614,7 @@
                        regulator-name = "vdd_pnl";
                        regulator-min-microvolt = <2800000>;
                        regulator-max-microvolt = <2800000>;
-                        gpio = <&gpio 22 0>; /* gpio PC6 */
+                        gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
                        enable-active-high;
                };
@@ -612,7 +624,7 @@
                        regulator-name = "vdd_bl";
                        regulator-min-microvolt = <2800000>;
                        regulator-max-microvolt = <2800000>;
-                        gpio = <&gpio 176 0>; /* gpio PW0 */
+                        gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
                        enable-active-high;
                };
        };
@@ -635,12 +647,16 @@
                nvidia,i2s-controller = <&tegra_i2s1>;
                nvidia,audio-codec = <&wm8903>;
-                nvidia,spkr-en-gpios = <&wm8903 2 0>;
+                nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
-                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+                nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
-                nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */
+                nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
-                nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
+                        GPIO_ACTIVE_HIGH>;
+                nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
+                        GPIO_ACTIVE_HIGH>;
-                clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+                clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+                         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA20_CLK_CDEV1>;
                clock-names = "pll_a", "pll_a_out0", "mclk";
        };
 };
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index d2567f83aaff..ab67c94db280 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsi"
 / {
        model = "NVIDIA Tegra20 Whistler evaluation board";
@@ -18,7 +18,8 @@
                        pll-supply = <&hdmi_pll_reg>;
                        nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-                        nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+                        nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+                                GPIO_ACTIVE_HIGH>;
                };
        };
@@ -281,7 +282,7 @@
                max8907@3c {
                        compatible = "maxim,max8907";
                        reg = <0x3c>;
-                        interrupts = <0 86 0x4>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
                        maxim,system-power-controller;
@@ -508,18 +509,28 @@
        usb@c5000000 {
                status = "okay";
-                nvidia,vbus-gpio = <&tca6416 0 0>; /* GPIO_PMU0 */
+                nvidia,vbus-gpio = <&tca6416 0 GPIO_ACTIVE_HIGH>;
+        };
+        usb-phy@c5000000 {
+                status = "okay";
+                vbus-supply = <&vbus1_reg>;
        };
        usb@c5008000 {
                status = "okay";
-                nvidia,vbus-gpio = <&tca6416 1 0>; /* GPIO_PMU1 */
+                nvidia,vbus-gpio = <&tca6416 1 GPIO_ACTIVE_HIGH>;
+        };
+        usb-phy@c5008000 {
+                status = "okay";
+                vbus-supply = <&vbus3_reg>;
        };
        sdhci@c8000400 {
                status = "okay";
-                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
+                cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
-                wp-gpios = <&gpio 173 0>; /* gpio PV5 */
+                wp-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
                bus-width = <8>;
        };
@@ -568,6 +579,26 @@
                        regulator-max-microvolt = <5000000>;
                        regulator-always-on;
                };
+                vbus1_reg: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "vbus1";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        gpio = <&tca6416 0 0>; /* GPIO_PMU0 */
+                };
+                vbus3_reg: regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "vbus3";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        gpio = <&tca6416 1 0>; /* GPIO_PMU1 */
+                };
        };
        sound {
@@ -584,7 +615,9 @@
                nvidia,i2s-controller = <&tegra_i2s1>;
                nvidia,audio-codec = <&codec>;
-                clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+                clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+                         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA20_CLK_CDEV1>;
                clock-names = "pll_a", "pll_a_out0", "mclk";
        };
 };
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 56a91106041b..9653fd8288d2 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -1,4 +1,8 @@
-/include/ "skeleton.dtsi"
+#include <dt-bindings/clock/tegra20-car.h>
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "skeleton.dtsi"
 / {
        compatible = "nvidia,tegra20";
@@ -15,9 +19,9 @@
        host1x {
                compatible = "nvidia,tegra20-host1x", "simple-bus";
                reg = <0x50000000 0x00024000>;
-                interrupts = <0 65 0x04   /* mpcore syncpt */
+                interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
-                              0 67 0x04>; /* mpcore general */
+                             <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
-                clocks = <&tegra_car 28>;
+                clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
                #address-cells = <1>;
                #size-cells = <1>;
@@ -27,49 +31,50 @@
                mpe {
                        compatible = "nvidia,tegra20-mpe";
                        reg = <0x54040000 0x00040000>;
-                        interrupts = <0 68 0x04>;
+                        interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&tegra_car 60>;
+                        clocks = <&tegra_car TEGRA20_CLK_MPE>;
                };
                vi {
                        compatible = "nvidia,tegra20-vi";
                        reg = <0x54080000 0x00040000>;
-                        interrupts = <0 69 0x04>;
+                        interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&tegra_car 100>;
+                        clocks = <&tegra_car TEGRA20_CLK_VI>;
                };
                epp {
                        compatible = "nvidia,tegra20-epp";
                        reg = <0x540c0000 0x00040000>;
-                        interrupts = <0 70 0x04>;
+                        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&tegra_car 19>;
+                        clocks = <&tegra_car TEGRA20_CLK_EPP>;
                };
                isp {
                        compatible = "nvidia,tegra20-isp";
                        reg = <0x54100000 0x00040000>;
-                        interrupts = <0 71 0x04>;
+                        interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&tegra_car 23>;
+                        clocks = <&tegra_car TEGRA20_CLK_ISP>;
                };
                gr2d {
                        compatible = "nvidia,tegra20-gr2d";
                        reg = <0x54140000 0x00040000>;
-                        interrupts = <0 72 0x04>;
+                        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&tegra_car 21>;
+                        clocks = <&tegra_car TEGRA20_CLK_GR2D>;
                };
                gr3d {
                        compatible = "nvidia,tegra20-gr3d";
                        reg = <0x54180000 0x00040000>;
-                        clocks = <&tegra_car 24>;
+                        clocks = <&tegra_car TEGRA20_CLK_GR3D>;
                };
                dc@54200000 {
                        compatible = "nvidia,tegra20-dc";
                        reg = <0x54200000 0x00040000>;
-                        interrupts = <0 73 0x04>;
+                        interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&tegra_car 27>, <&tegra_car 121>;
+                        clocks = <&tegra_car TEGRA20_CLK_DISP1>,
+                                 <&tegra_car TEGRA20_CLK_PLL_P>;
                        clock-names = "disp1", "parent";
                        rgb {
@@ -80,8 +85,9 @@
                dc@54240000 {
                        compatible = "nvidia,tegra20-dc";
                        reg = <0x54240000 0x00040000>;
-                        interrupts = <0 74 0x04>;
+                        interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&tegra_car 26>, <&tegra_car 121>;
+                        clocks = <&tegra_car TEGRA20_CLK_DISP2>,
+                                 <&tegra_car TEGRA20_CLK_PLL_P>;
                        clock-names = "disp2", "parent";
                        rgb {
@@ -92,8 +98,9 @@
                hdmi {
                        compatible = "nvidia,tegra20-hdmi";
                        reg = <0x54280000 0x00040000>;
-                        interrupts = <0 75 0x04>;
+                        interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&tegra_car 51>, <&tegra_car 117>;
+                        clocks = <&tegra_car TEGRA20_CLK_HDMI>,
+                                 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
                        clock-names = "hdmi", "parent";
                        status = "disabled";
                };
@@ -101,15 +108,15 @@
                tvo {
                        compatible = "nvidia,tegra20-tvo";
                        reg = <0x542c0000 0x00040000>;
-                        interrupts = <0 76 0x04>;
+                        interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&tegra_car 102>;
+                        clocks = <&tegra_car TEGRA20_CLK_TVO>;
                        status = "disabled";
                };
                dsi {
                        compatible = "nvidia,tegra20-dsi";
                        reg = <0x54300000 0x00040000>;
-                        clocks = <&tegra_car 48>;
+                        clocks = <&tegra_car TEGRA20_CLK_DSI>;
                        status = "disabled";
                };
        };
@@ -117,8 +124,9 @@
        timer@50004600 {
                compatible = "arm,cortex-a9-twd-timer";
                reg = <0x50040600 0x20>;
-                interrupts = <1 13 0x304>;
+                interrupts = <GIC_PPI 13
-                clocks = <&tegra_car 132>;
+                        (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+                clocks = <&tegra_car TEGRA20_CLK_TWD>;
        };
        intc: interrupt-controller {
@@ -141,11 +149,11 @@
        timer@60005000 {
                compatible = "nvidia,tegra20-timer";
                reg = <0x60005000 0x60>;
-                interrupts = <0 0 0x04
+                interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
-                              0 1 0x04
+                             <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
-                              0 41 0x04
+                             <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
-                              0 42 0x04>;
+                             <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&tegra_car 5>;
+                clocks = <&tegra_car TEGRA20_CLK_TIMER>;
        };
        tegra_car: clock {
@@ -157,23 +165,23 @@
        apbdma: dma {
                compatible = "nvidia,tegra20-apbdma";
                reg = <0x6000a000 0x1200>;
-                interrupts = <0 104 0x04
+                interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
-                              0 105 0x04
+                             <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
-                              0 106 0x04
+                             <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
-                              0 107 0x04
+                             <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
-                              0 108 0x04
+                             <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
-                              0 109 0x04
+                             <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
-                              0 110 0x04
+                             <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
-                              0 111 0x04
+                             <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
-                              0 112 0x04
+                             <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
-                              0 113 0x04
+                             <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
-                              0 114 0x04
+                             <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
-                              0 115 0x04
+                             <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
-                              0 116 0x04
+                             <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
-                              0 117 0x04
+                             <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
-                              0 118 0x04
+                             <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
-                              0 119 0x04>;
+                             <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&tegra_car 34>;
+                clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
        };
        ahb {
@@ -184,13 +192,13 @@
        gpio: gpio {
                compatible = "nvidia,tegra20-gpio";
                reg = <0x6000d000 0x1000>;
-                interrupts = <0 32 0x04
+                interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
-                              0 33 0x04
+                             <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
-                              0 34 0x04
+                             <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
-                              0 35 0x04
+                             <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
-                              0 55 0x04
+                             <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
-                              0 87 0x04
+                             <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
-                              0 89 0x04>;
+                             <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
                #interrupt-cells = <2>;
@@ -213,27 +221,27 @@
        tegra_ac97: ac97 {
                compatible = "nvidia,tegra20-ac97";
                reg = <0x70002000 0x200>;
-                interrupts = <0 81 0x04>;
+                interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 12>;
-                clocks = <&tegra_car 3>;
+                clocks = <&tegra_car TEGRA20_CLK_AC97>;
                status = "disabled";
        };
        tegra_i2s1: i2s@70002800 {
                compatible = "nvidia,tegra20-i2s";
                reg = <0x70002800 0x200>;
-                interrupts = <0 13 0x04>;
+                interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 2>;
-                clocks = <&tegra_car 11>;
+                clocks = <&tegra_car TEGRA20_CLK_I2S1>;
                status = "disabled";
        };
        tegra_i2s2: i2s@70002a00 {
                compatible = "nvidia,tegra20-i2s";
                reg = <0x70002a00 0x200>;
-                interrupts = <0 3 0x04>;
+                interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 1>;
-                clocks = <&tegra_car 18>;
+                clocks = <&tegra_car TEGRA20_CLK_I2S2>;
                status = "disabled";
        };
@@ -248,9 +256,9 @@
                compatible = "nvidia,tegra20-uart";
                reg = <0x70006000 0x40>;
                reg-shift = <2>;
-                interrupts = <0 36 0x04>;
+                interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 8>;
-                clocks = <&tegra_car 6>;
+                clocks = <&tegra_car TEGRA20_CLK_UARTA>;
                status = "disabled";
        };
@@ -258,9 +266,9 @@
                compatible = "nvidia,tegra20-uart";
                reg = <0x70006040 0x40>;
                reg-shift = <2>;
-                interrupts = <0 37 0x04>;
+                interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 9>;
-                clocks = <&tegra_car 96>;
+                clocks = <&tegra_car TEGRA20_CLK_UARTB>;
                status = "disabled";
        };
@@ -268,9 +276,9 @@
                compatible = "nvidia,tegra20-uart";
                reg = <0x70006200 0x100>;
                reg-shift = <2>;
-                interrupts = <0 46 0x04>;
+                interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 10>;
-                clocks = <&tegra_car 55>;
+                clocks = <&tegra_car TEGRA20_CLK_UARTC>;
                status = "disabled";
        };
@@ -278,9 +286,9 @@
                compatible = "nvidia,tegra20-uart";
                reg = <0x70006300 0x100>;
                reg-shift = <2>;
-                interrupts = <0 90 0x04>;
+                interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 19>;
-                clocks = <&tegra_car 65>;
+                clocks = <&tegra_car TEGRA20_CLK_UARTD>;
                status = "disabled";
        };
@@ -288,9 +296,9 @@
                compatible = "nvidia,tegra20-uart";
                reg = <0x70006400 0x100>;
                reg-shift = <2>;
-                interrupts = <0 91 0x04>;
+                interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 20>;
-                clocks = <&tegra_car 66>;
+                clocks = <&tegra_car TEGRA20_CLK_UARTE>;
                status = "disabled";
        };
@@ -298,24 +306,25 @@
                compatible = "nvidia,tegra20-pwm";
                reg = <0x7000a000 0x100>;
                #pwm-cells = <2>;
-                clocks = <&tegra_car 17>;
+                clocks = <&tegra_car TEGRA20_CLK_PWM>;
                status = "disabled";
        };
        rtc {
                compatible = "nvidia,tegra20-rtc";
                reg = <0x7000e000 0x100>;
-                interrupts = <0 2 0x04>;
+                interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&tegra_car 4>;
+                clocks = <&tegra_car TEGRA20_CLK_RTC>;
        };
        i2c@7000c000 {
                compatible = "nvidia,tegra20-i2c";
                reg = <0x7000c000 0x100>;
-                interrupts = <0 38 0x04>;
+                interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&tegra_car 12>, <&tegra_car 124>;
+                clocks = <&tegra_car TEGRA20_CLK_I2C1>,
+                         <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
                clock-names = "div-clk", "fast-clk";
                status = "disabled";
        };
@@ -323,21 +332,22 @@
        spi@7000c380 {
                compatible = "nvidia,tegra20-sflash";
                reg = <0x7000c380 0x80>;
-                interrupts = <0 39 0x04>;
+                interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 11>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&tegra_car 43>;
+                clocks = <&tegra_car TEGRA20_CLK_SPI>;
                status = "disabled";
        };
        i2c@7000c400 {
                compatible = "nvidia,tegra20-i2c";
                reg = <0x7000c400 0x100>;
-                interrupts = <0 84 0x04>;
+                interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&tegra_car 54>, <&tegra_car 124>;
+                clocks = <&tegra_car TEGRA20_CLK_I2C2>,
+                         <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
                clock-names = "div-clk", "fast-clk";
                status = "disabled";
        };
@@ -345,10 +355,11 @@
        i2c@7000c500 {
                compatible = "nvidia,tegra20-i2c";
                reg = <0x7000c500 0x100>;
-                interrupts = <0 92 0x04>;
+                interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&tegra_car 67>, <&tegra_car 124>;
+                clocks = <&tegra_car TEGRA20_CLK_I2C3>,
+                         <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
                clock-names = "div-clk", "fast-clk";
                status = "disabled";
        };
@@ -356,10 +367,11 @@
        i2c@7000d000 {
                compatible = "nvidia,tegra20-i2c-dvc";
                reg = <0x7000d000 0x200>;
-                interrupts = <0 53 0x04>;
+                interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&tegra_car 47>, <&tegra_car 124>;
+                clocks = <&tegra_car TEGRA20_CLK_DVC>,
+                         <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
                clock-names = "div-clk", "fast-clk";
                status = "disabled";
        };
@@ -367,59 +379,59 @@
        spi@7000d400 {
                compatible = "nvidia,tegra20-slink";
                reg = <0x7000d400 0x200>;
-                interrupts = <0 59 0x04>;
+                interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 15>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&tegra_car 41>;
+                clocks = <&tegra_car TEGRA20_CLK_SBC1>;
                status = "disabled";
        };
        spi@7000d600 {
                compatible = "nvidia,tegra20-slink";
                reg = <0x7000d600 0x200>;
-                interrupts = <0 82 0x04>;
+                interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 16>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&tegra_car 44>;
+                clocks = <&tegra_car TEGRA20_CLK_SBC2>;
                status = "disabled";
        };
        spi@7000d800 {
                compatible = "nvidia,tegra20-slink";
                reg = <0x7000d800 0x200>;
-                interrupts = <0 83 0x04>;
+                interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 17>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&tegra_car 46>;
+                clocks = <&tegra_car TEGRA20_CLK_SBC3>;
                status = "disabled";
        };
        spi@7000da00 {
                compatible = "nvidia,tegra20-slink";
                reg = <0x7000da00 0x200>;
-                interrupts = <0 93 0x04>;
+                interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 18>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&tegra_car 68>;
+                clocks = <&tegra_car TEGRA20_CLK_SBC4>;
                status = "disabled";
        };
        kbc {
                compatible = "nvidia,tegra20-kbc";
                reg = <0x7000e200 0x100>;
-                interrupts = <0 85 0x04>;
+                interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&tegra_car 36>;
+                clocks = <&tegra_car TEGRA20_CLK_KBC>;
                status = "disabled";
        };
        pmc {
                compatible = "nvidia,tegra20-pmc";
                reg = <0x7000e400 0x400>;
-                clocks = <&tegra_car 110>, <&clk32k_in>;
+                clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
                clock-names = "pclk", "clk32k_in";
        };
@@ -427,7 +439,7 @@
                compatible = "nvidia,tegra20-mc";
                reg = <0x7000f000 0x024
                       0x7000f03c 0x3c4>;
-                interrupts = <0 77 0x04>;
+                interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
        };
        iommu {
@@ -446,89 +458,114 @@
        usb@c5000000 {
                compatible = "nvidia,tegra20-ehci", "usb-ehci";
                reg = <0xc5000000 0x4000>;
-                interrupts = <0 20 0x04>;
+                interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
                phy_type = "utmi";
                nvidia,has-legacy-mode;
-                clocks = <&tegra_car 22>;
+                clocks = <&tegra_car TEGRA20_CLK_USBD>;
                nvidia,needs-double-reset;
                nvidia,phy = <&phy1>;
                status = "disabled";
        };
-        phy1: usb-phy@c5000400 {
+        phy1: usb-phy@c5000000 {
                compatible = "nvidia,tegra20-usb-phy";
-                reg = <0xc5000400 0x3c00>;
+                reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
                phy_type = "utmi";
+                clocks = <&tegra_car TEGRA20_CLK_USBD>,
+                         <&tegra_car TEGRA20_CLK_PLL_U>,
+                         <&tegra_car TEGRA20_CLK_CLK_M>,
+                         <&tegra_car TEGRA20_CLK_USBD>;
+                clock-names = "reg", "pll_u", "timer", "utmi-pads";
                nvidia,has-legacy-mode;
-                clocks = <&tegra_car 22>, <&tegra_car 127>;
+                hssync_start_delay = <9>;
-                clock-names = "phy", "pll_u";
+                idle_wait_delay = <17>;
+                elastic_limit = <16>;
+                term_range_adj = <6>;
+                xcvr_setup = <9>;
+                xcvr_lsfslew = <1>;
+                xcvr_lsrslew = <1>;
+                status = "disabled";
        };
        usb@c5004000 {
                compatible = "nvidia,tegra20-ehci", "usb-ehci";
                reg = <0xc5004000 0x4000>;
-                interrupts = <0 21 0x04>;
+                interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
                phy_type = "ulpi";
-                clocks = <&tegra_car 58>;
+                clocks = <&tegra_car TEGRA20_CLK_USB2>;
                nvidia,phy = <&phy2>;
                status = "disabled";
        };
-        phy2: usb-phy@c5004400 {
+        phy2: usb-phy@c5004000 {
                compatible = "nvidia,tegra20-usb-phy";
-                reg = <0xc5004400 0x3c00>;
+                reg = <0xc5004000 0x4000>;
                phy_type = "ulpi";
-                clocks = <&tegra_car 93>, <&tegra_car 127>;
+                clocks = <&tegra_car TEGRA20_CLK_USB2>,
-                clock-names = "phy", "pll_u";
+                         <&tegra_car TEGRA20_CLK_PLL_U>,
+                         <&tegra_car TEGRA20_CLK_CDEV2>;
+                clock-names = "reg", "pll_u", "ulpi-link";
+                status = "disabled";
        };
        usb@c5008000 {
                compatible = "nvidia,tegra20-ehci", "usb-ehci";
                reg = <0xc5008000 0x4000>;
-                interrupts = <0 97 0x04>;
+                interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
                phy_type = "utmi";
-                clocks = <&tegra_car 59>;
+                clocks = <&tegra_car TEGRA20_CLK_USB3>;
                nvidia,phy = <&phy3>;
                status = "disabled";
        };
-        phy3: usb-phy@c5008400 {
+        phy3: usb-phy@c5008000 {
                compatible = "nvidia,tegra20-usb-phy";
-                reg = <0xc5008400 0x3c00>;
+                reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
                phy_type = "utmi";
-                clocks = <&tegra_car 22>, <&tegra_car 127>;
+                clocks = <&tegra_car TEGRA20_CLK_USB3>,
-                clock-names = "phy", "pll_u";
+                         <&tegra_car TEGRA20_CLK_PLL_U>,
+                         <&tegra_car TEGRA20_CLK_CLK_M>,
+                         <&tegra_car TEGRA20_CLK_USBD>;
+                clock-names = "reg", "pll_u", "timer", "utmi-pads";
+                hssync_start_delay = <9>;
+                idle_wait_delay = <17>;
+                elastic_limit = <16>;
+                term_range_adj = <6>;
+                xcvr_setup = <9>;
+                xcvr_lsfslew = <2>;
+                xcvr_lsrslew = <2>;
+                status = "disabled";
        };
        sdhci@c8000000 {
                compatible = "nvidia,tegra20-sdhci";
                reg = <0xc8000000 0x200>;
-                interrupts = <0 14 0x04>;
+                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&tegra_car 14>;
+                clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
                status = "disabled";
        };
        sdhci@c8000200 {
                compatible = "nvidia,tegra20-sdhci";
                reg = <0xc8000200 0x200>;
-                interrupts = <0 15 0x04>;
+                interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&tegra_car 9>;
+                clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
                status = "disabled";
        };
        sdhci@c8000400 {
                compatible = "nvidia,tegra20-sdhci";
                reg = <0xc8000400 0x200>;
-                interrupts = <0 19 0x04>;
+                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&tegra_car 69>;
+                clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
                status = "disabled";
        };
        sdhci@c8000600 {
                compatible = "nvidia,tegra20-sdhci";
                reg = <0xc8000600 0x200>;
-                interrupts = <0 31 0x04>;
+                interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&tegra_car 15>;
+                clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
                status = "disabled";
        };
@@ -551,7 +588,7 @@
        pmu {
                compatible = "arm,cortex-a9-pmu";
-                interrupts = <0 56 0x04
+                interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
-                              0 57 0x04>;
+                             <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
        };
 };
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index b732f7c13a66..87c5f7b7c271 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -1,13 +1,13 @@
 /dts-v1/;
-/include/ "tegra30.dtsi"
+#include "tegra30.dtsi"
 / {
        model = "NVIDIA Tegra30 Beaver evaluation board";
        compatible = "nvidia,beaver", "nvidia,tegra30";
        memory {
-                reg = <0x80000000 0x80000000>;
+                reg = <0x80000000 0x7ff00000>;
        };
        pinmux {
@@ -116,6 +116,15 @@
                status = "okay";
                clock-frequency = <100000>;
+                rt5640: rt5640 {
+                        compatible = "realtek,rt5640";
+                        reg = <0x1c>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <TEGRA_GPIO(X, 3) GPIO_ACTIVE_HIGH>;
+                        realtek,ldo1-en-gpios =
+                                <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>;
+                };
                tps62361 {
                        compatible = "ti,tps62361";
                        reg = <0x60>;
@@ -133,7 +142,7 @@
                        compatible = "ti,tps65911";
                        reg = <0x2d>;
-                        interrupts = <0 86 0x4>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
                        #interrupt-cells = <2>;
                        interrupt-controller;
@@ -264,9 +273,9 @@
        sdhci@78000000 {
                status = "okay";
-                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
+                cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
-                wp-gpios = <&gpio 155 0>; /* gpio PT3 */
+                wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
-                power-gpios = <&gpio 31 0>; /* gpio PD7 */
+                power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
                bus-width = <4>;
        };
@@ -312,7 +321,7 @@
                        regulator-boot-on;
                        regulator-always-on;
                        enable-active-high;
-                        gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */
+                        gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
                };
                ddr_reg: regulator@2 {
@@ -324,7 +333,7 @@
                        regulator-always-on;
                        regulator-boot-on;
                        enable-active-high;
-                        gpio = <&pmic 7 0>; /* PMIC TPS65911 GPIO7 */
+                        gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
                        vin-supply = <&vdd_5v_in_reg>;
                };
@@ -337,7 +346,7 @@
                        regulator-always-on;
                        regulator-boot-on;
                        enable-active-high;
-                        gpio = <&gpio 30 0>; /* gpio PD6 */
+                        gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
                        vin-supply = <&vdd_5v_in_reg>;
                };
@@ -348,7 +357,7 @@
                        regulator-min-microvolt = <5000000>;
                        regulator-max-microvolt = <5000000>;
                        enable-active-high;
-                        gpio = <&gpio 68 0>; /* GPIO PI4 */
+                        gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>;
                        gpio-open-drain;
                        vin-supply = <&vdd_5v_in_reg>;
                };
@@ -360,7 +369,7 @@
                        regulator-min-microvolt = <5000000>;
                        regulator-max-microvolt = <5000000>;
                        enable-active-high;
-                        gpio = <&gpio 63 0>; /* GPIO PH7 */
+                        gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
                        gpio-open-drain;
                        vin-supply = <&vdd_5v_in_reg>;
                };
@@ -374,7 +383,7 @@
                        regulator-always-on;
                        regulator-boot-on;
                        enable-active-high;
-                        gpio = <&pmic 6 0>; /* PMIC TPS65911 GPIO6 */
+                        gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
                        vin-supply = <&vdd_5v_in_reg>;
                };
@@ -387,8 +396,41 @@
                        regulator-always-on;
                        regulator-boot-on;
                        enable-active-high;
-                        gpio = <&gpio 95 0>; /* gpio PL7 */
+                        gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
                        vin-supply = <&sys_3v3_reg>;
                };
        };
+        gpio-leds {
+                compatible = "gpio-leds";
+                gpled1 {
+                        label = "LED1"; /* CR5A1 (blue) */
+                        gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>;
+                };
+                gpled2 {
+                        label = "LED2"; /* CR4A2 (green) */
+                        gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>;
+                };
+        };
+        sound {
+                compatible = "nvidia,tegra-audio-rt5640-beaver",
+                             "nvidia,tegra-audio-rt5640";
+                nvidia,model = "NVIDIA Tegra Beaver";
+                nvidia,audio-routing =
+                        "Headphones", "HPOR",
+                        "Headphones", "HPOL";
+                nvidia,i2s-controller = <&tegra_i2s1>;
+                nvidia,audio-codec = <&rt5640>;
+                nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
+                clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
+                         <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA30_CLK_EXTERN1>;
+                clock-names = "pll_a", "pll_a_out0", "mclk";
+        };
 };
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
index e392bd2dab9b..1082c5ed90d1 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a02.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
-/include/ "tegra30-cardhu.dtsi"
+#include "tegra30-cardhu.dtsi"
 /* This dts file support the cardhu A02 version of board */
@@ -22,7 +22,7 @@
                        regulator-always-on;
                        regulator-boot-on;
                        enable-active-high;
-                        gpio = <&pmic 6 0>;
+                        gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
                };
                sys_3v3_reg: regulator@101 {
@@ -34,7 +34,7 @@
                        regulator-always-on;
                        regulator-boot-on;
                        enable-active-high;
-                        gpio = <&pmic 7 0>;
+                        gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
                };
                usb1_vbus_reg: regulator@102 {
@@ -44,7 +44,7 @@
                        regulator-min-microvolt = <5000000>;
                        regulator-max-microvolt = <5000000>;
                        enable-active-high;
-                        gpio = <&gpio 68 0>; /* GPIO PI4 */
+                        gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>;
                        gpio-open-drain;
                        vin-supply = <&vdd_5v0_reg>;
                };
@@ -56,7 +56,7 @@
                        regulator-min-microvolt = <5000000>;
                        regulator-max-microvolt = <5000000>;
                        enable-active-high;
-                        gpio = <&gpio 63 0>; /* GPIO PH7 */
+                        gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
                        gpio-open-drain;
                        vin-supply = <&vdd_5v0_reg>;
                };
@@ -68,7 +68,7 @@
                        regulator-min-microvolt = <5000000>;
                        regulator-max-microvolt = <5000000>;
                        enable-active-high;
-                        gpio = <&pmic 2 0>;
+                        gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
                };
                vdd_bl_reg: regulator@105 {
@@ -80,13 +80,13 @@
                        regulator-always-on;
                        regulator-boot-on;
                        enable-active-high;
-                        gpio = <&gpio 83 0>; /* GPIO PK3 */
+                        gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>;
                };
        };
        sdhci@78000400 {
                status = "okay";
-                power-gpios = <&gpio 28 0>; /* gpio PD4 */
+                power-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
                bus-width = <4>;
                keep-power-in-suspend;
        };
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
index d0db6c7e774f..bf012bddaafb 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
-/include/ "tegra30-cardhu.dtsi"
+#include "tegra30-cardhu.dtsi"
 /* This dts file support the cardhu A04 and later versions of board */
@@ -22,7 +22,7 @@
                        regulator-always-on;
                        regulator-boot-on;
                        enable-active-high;
-                        gpio = <&pmic 7 0>;
+                        gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
                };
                sys_3v3_reg: regulator@101 {
@@ -34,7 +34,7 @@
                        regulator-always-on;
                        regulator-boot-on;
                        enable-active-high;
-                        gpio = <&pmic 6 0>;
+                        gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
                };
                usb1_vbus_reg: regulator@102 {
@@ -44,7 +44,7 @@
                        regulator-min-microvolt = <5000000>;
                        regulator-max-microvolt = <5000000>;
                        enable-active-high;
-                        gpio = <&gpio 238 0>; /* GPIO PDD6 */
+                        gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>;
                        gpio-open-drain;
                        vin-supply = <&vdd_5v0_reg>;
                };
@@ -56,7 +56,7 @@
                        regulator-min-microvolt = <5000000>;
                        regulator-max-microvolt = <5000000>;
                        enable-active-high;
-                        gpio = <&gpio 236 0>; /* GPIO PDD4 */
+                        gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
                        gpio-open-drain;
                        vin-supply = <&vdd_5v0_reg>;
                };
@@ -68,7 +68,7 @@
                        regulator-min-microvolt = <5000000>;
                        regulator-max-microvolt = <5000000>;
                        enable-active-high;
-                        gpio = <&pmic 8 0>;
+                        gpio = <&pmic 8 GPIO_ACTIVE_HIGH>;
                };
                vdd_bl_reg: regulator@105 {
@@ -80,7 +80,7 @@
                        regulator-always-on;
                        regulator-boot-on;
                        enable-active-high;
-                        gpio = <&gpio 234 0>; /* GPIO PDD2 */
+                        gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
                };
                vdd_bl2_reg: regulator@106 {
@@ -92,13 +92,13 @@
                        regulator-always-on;
                        regulator-boot-on;
                        enable-active-high;
-                        gpio = <&gpio 232 0>; /* GPIO PDD0 */
+                        gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
                };
        };
        sdhci@78000400 {
                status = "okay";
-                power-gpios = <&gpio 27 0>; /* gpio PD3 */
+                power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
                bus-width = <4>;
                keep-power-in-suspend;
        };
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 01b4c26fad96..f65b53d32416 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -1,4 +1,4 @@
-/include/ "tegra30.dtsi"
+#include "tegra30.dtsi"
 /**
 * This file contains common DT entry for all fab version of Cardhu.
@@ -146,7 +146,7 @@
                        compatible = "isil,isl29028";
                        reg = <0x44>;
                        interrupt-parent = <&gpio>;
-                        interrupts = <88 0x04>; /*gpio PL0 */
+                        interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
                };
        };
@@ -163,7 +163,7 @@
                        compatible = "wlf,wm8903";
                        reg = <0x1a>;
                        interrupt-parent = <&gpio>;
-                        interrupts = <179 0x04>; /* gpio PW3 */
+                        interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>;
                        gpio-controller;
                        #gpio-cells = <2>;
@@ -190,7 +190,7 @@
                        compatible = "ti,tps65911";
                        reg = <0x2d>;
-                        interrupts = <0 86 0x4>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
                        #interrupt-cells = <2>;
                        interrupt-controller;
@@ -318,9 +318,9 @@
        sdhci@78000000 {
                status = "okay";
-                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
+                cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
-                wp-gpios = <&gpio 155 0>; /* gpio PT3 */
+                wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
-                power-gpios = <&gpio 31 0>; /* gpio PD7 */
+                power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
                bus-width = <4>;
        };
@@ -364,7 +364,7 @@
                        regulator-min-microvolt = <1800000>;
                        regulator-max-microvolt = <1800000>;
                        enable-active-high;
-                        gpio = <&gpio 220 0>; /* gpio PBB4 */
+                        gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
                        vin-supply = <&vio_reg>;
                };
@@ -377,7 +377,7 @@
                        regulator-boot-on;
                        regulator-always-on;
                        enable-active-high;
-                        gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */
+                        gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
                };
                emmc_3v3_reg: regulator@3 {
@@ -389,7 +389,7 @@
                        regulator-always-on;
                        regulator-boot-on;
                        enable-active-high;
-                        gpio = <&gpio 25 0>; /* gpio PD1 */
+                        gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
                        vin-supply = <&sys_3v3_reg>;
                };
@@ -400,7 +400,7 @@
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
                        enable-active-high;
-                        gpio = <&gpio 30 0>; /* gpio PD6 */
+                        gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
                };
                pex_hvdd_3v3_reg: regulator@5 {
@@ -410,7 +410,7 @@
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
                        enable-active-high;
-                        gpio = <&gpio 95 0>; /* gpio PL7 */
+                        gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
                        vin-supply = <&sys_3v3_reg>;
                };
@@ -421,7 +421,7 @@
                        regulator-min-microvolt = <2800000>;
                        regulator-max-microvolt = <2800000>;
                        enable-active-high;
-                        gpio = <&gpio 142 0>; /* gpio PR6 */
+                        gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
                        vin-supply = <&sys_3v3_reg>;
                };
@@ -432,7 +432,7 @@
                        regulator-min-microvolt = <2800000>;
                        regulator-max-microvolt = <2800000>;
                        enable-active-high;
-                        gpio = <&gpio 143 0>; /* gpio PR7 */
+                        gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
                        vin-supply = <&sys_3v3_reg>;
                };
@@ -443,7 +443,7 @@
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
                        enable-active-high;
-                        gpio = <&gpio 144 0>; /* gpio PS0 */
+                        gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
                        vin-supply = <&sys_3v3_reg>;
                };
@@ -456,7 +456,7 @@
                        regulator-always-on;
                        regulator-boot-on;
                        enable-active-high;
-                        gpio = <&gpio 24 0>; /* gpio PD0 */
+                        gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
                        vin-supply = <&sys_3v3_reg>;
                };
@@ -467,7 +467,7 @@
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
                        enable-active-high;
-                        gpio = <&gpio 94 0>; /* gpio PL6 */
+                        gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
                        vin-supply = <&sys_3v3_reg>;
                };
@@ -480,7 +480,7 @@
                        regulator-always-on;
                        regulator-boot-on;
                        enable-active-high;
-                        gpio = <&gpio 92 0>; /* gpio PL4 */
+                        gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
                        vin-supply = <&sys_3v3_reg>;
                };
@@ -491,7 +491,7 @@
                        regulator-min-microvolt = <5000000>;
                        regulator-max-microvolt = <5000000>;
                        enable-active-high;
-                        gpio = <&gpio 152 0>; /* GPIO PT0 */
+                        gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
                        gpio-open-drain;
                        vin-supply = <&vdd_5v0_reg>;
                };
@@ -515,10 +515,13 @@
                nvidia,i2s-controller = <&tegra_i2s1>;
                nvidia,audio-codec = <&wm8903>;
-                nvidia,spkr-en-gpios = <&wm8903 2 0>;
+                nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
-                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+                nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
+                        GPIO_ACTIVE_HIGH>;
-                clocks = <&tegra_car 184>, <&tegra_car 185>, <&tegra_car 120>;
+                clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
+                         <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA30_CLK_EXTERN1>;
                clock-names = "pll_a", "pll_a_out0", "mclk";
        };
 };
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 15ded605142a..d8783f0fae63 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -1,4 +1,8 @@
-/include/ "skeleton.dtsi"
+#include <dt-bindings/clock/tegra30-car.h>
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "skeleton.dtsi"
 / {
        compatible = "nvidia,tegra30";
@@ -15,9 +19,9 @@
        host1x {
                compatible = "nvidia,tegra30-host1x", "simple-bus";
                reg = <0x50000000 0x00024000>;
-                interrupts = <0 65 0x04   /* mpcore syncpt */
+                interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
-                              0 67 0x04>; /* mpcore general */
+                             <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
-                clocks = <&tegra_car 28>;
+                clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
                #address-cells = <1>;
                #size-cells = <1>;
@@ -27,36 +31,36 @@
                mpe {
                        compatible = "nvidia,tegra30-mpe";
                        reg = <0x54040000 0x00040000>;
-                        interrupts = <0 68 0x04>;
+                        interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&tegra_car 60>;
+                        clocks = <&tegra_car TEGRA30_CLK_MPE>;
                };
                vi {
                        compatible = "nvidia,tegra30-vi";
                        reg = <0x54080000 0x00040000>;
-                        interrupts = <0 69 0x04>;
+                        interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&tegra_car 164>;
+                        clocks = <&tegra_car TEGRA30_CLK_VI>;
                };
                epp {
                        compatible = "nvidia,tegra30-epp";
                        reg = <0x540c0000 0x00040000>;
-                        interrupts = <0 70 0x04>;
+                        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&tegra_car 19>;
+                        clocks = <&tegra_car TEGRA30_CLK_EPP>;
                };
                isp {
                        compatible = "nvidia,tegra30-isp";
                        reg = <0x54100000 0x00040000>;
-                        interrupts = <0 71 0x04>;
+                        interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&tegra_car 23>;
+                        clocks = <&tegra_car TEGRA30_CLK_ISP>;
                };
                gr2d {
                        compatible = "nvidia,tegra30-gr2d";
                        reg = <0x54140000 0x00040000>;
-                        interrupts = <0 72 0x04>;
+                        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&tegra_car 21>;
+                        clocks = <&tegra_car TEGRA30_CLK_GR2D>;
                };
                gr3d {
@@ -69,8 +73,9 @@
                dc@54200000 {
                        compatible = "nvidia,tegra30-dc";
                        reg = <0x54200000 0x00040000>;
-                        interrupts = <0 73 0x04>;
+                        interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&tegra_car 27>, <&tegra_car 179>;
+                        clocks = <&tegra_car TEGRA30_CLK_DISP1>,
+                                 <&tegra_car TEGRA30_CLK_PLL_P>;
                        clock-names = "disp1", "parent";
                        rgb {
@@ -81,8 +86,9 @@
                dc@54240000 {
                        compatible = "nvidia,tegra30-dc";
                        reg = <0x54240000 0x00040000>;
-                        interrupts = <0 74 0x04>;
+                        interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&tegra_car 26>, <&tegra_car 179>;
+                        clocks = <&tegra_car TEGRA30_CLK_DISP2>,
+                                 <&tegra_car TEGRA30_CLK_PLL_P>;
                        clock-names = "disp2", "parent";
                        rgb {
@@ -93,8 +99,9 @@
                hdmi {
                        compatible = "nvidia,tegra30-hdmi";
                        reg = <0x54280000 0x00040000>;
-                        interrupts = <0 75 0x04>;
+                        interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&tegra_car 51>, <&tegra_car 189>;
+                        clocks = <&tegra_car TEGRA30_CLK_HDMI>,
+                                 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
                        clock-names = "hdmi", "parent";
                        status = "disabled";
                };
@@ -102,15 +109,15 @@
                tvo {
                        compatible = "nvidia,tegra30-tvo";
                        reg = <0x542c0000 0x00040000>;
-                        interrupts = <0 76 0x04>;
+                        interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&tegra_car 169>;
+                        clocks = <&tegra_car TEGRA30_CLK_TVO>;
                        status = "disabled";
                };
                dsi {
                        compatible = "nvidia,tegra30-dsi";
                        reg = <0x54300000 0x00040000>;
-                        clocks = <&tegra_car 48>;
+                        clocks = <&tegra_car TEGRA30_CLK_DSIA>;
                        status = "disabled";
                };
        };
@@ -118,8 +125,9 @@
        timer@50004600 {
                compatible = "arm,cortex-a9-twd-timer";
                reg = <0x50040600 0x20>;
-                interrupts = <1 13 0xf04>;
+                interrupts = <GIC_PPI 13
-                clocks = <&tegra_car 214>;
+                        (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+                clocks = <&tegra_car TEGRA30_CLK_TWD>;
        };
        intc: interrupt-controller {
@@ -142,13 +150,13 @@
        timer@60005000 {
                compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
                reg = <0x60005000 0x400>;
-                interrupts = <0 0 0x04
+                interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
-                              0 1 0x04
+                             <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
-                              0 41 0x04
+                             <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
-                              0 42 0x04
+                             <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
-                              0 121 0x04
+                             <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
-                              0 122 0x04>;
+                             <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&tegra_car 5>;
+                clocks = <&tegra_car TEGRA30_CLK_TIMER>;
        };
        tegra_car: clock {
@@ -160,39 +168,39 @@
        apbdma: dma {
                compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
                reg = <0x6000a000 0x1400>;
-                interrupts = <0 104 0x04
+                interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
-                              0 105 0x04
+                             <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
-                              0 106 0x04
+                             <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
-                              0 107 0x04
+                             <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
-                              0 108 0x04
+                             <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
-                              0 109 0x04
+                             <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
-                              0 110 0x04
+                             <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
-                              0 111 0x04
+                             <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
-                              0 112 0x04
+                             <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
-                              0 113 0x04
+                             <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
-                              0 114 0x04
+                             <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
-                              0 115 0x04
+                             <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
-                              0 116 0x04
+                             <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
-                              0 117 0x04
+                             <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
-                              0 118 0x04
+                             <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
-                              0 119 0x04
+                             <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
-                              0 128 0x04
+                             <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
-                              0 129 0x04
+                             <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
-                              0 130 0x04
+                             <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
-                              0 131 0x04
+                             <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
-                              0 132 0x04
+                             <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
-                              0 133 0x04
+                             <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
-                              0 134 0x04
+                             <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
-                              0 135 0x04
+                             <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
-                              0 136 0x04
+                             <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
-                              0 137 0x04
+                             <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
-                              0 138 0x04
+                             <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
-                              0 139 0x04
+                             <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
-                              0 140 0x04
+                             <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
-                              0 141 0x04
+                             <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
-                              0 142 0x04
+                             <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-                              0 143 0x04>;
+                             <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&tegra_car 34>;
+                clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
        };
        ahb: ahb {
@@ -203,14 +211,14 @@
        gpio: gpio {
                compatible = "nvidia,tegra30-gpio";
                reg = <0x6000d000 0x1000>;
-                interrupts = <0 32 0x04
+                interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
-                              0 33 0x04
+                             <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
-                              0 34 0x04
+                             <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
-                              0 35 0x04
+                             <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
-                              0 55 0x04
+                             <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
-                              0 87 0x04
+                             <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
-                              0 89 0x04
+                             <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
-                              0 125 0x04>;
+                             <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
                #interrupt-cells = <2>;
@@ -235,9 +243,9 @@
                compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
                reg = <0x70006000 0x40>;
                reg-shift = <2>;
-                interrupts = <0 36 0x04>;
+                interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 8>;
-                clocks = <&tegra_car 6>;
+                clocks = <&tegra_car TEGRA30_CLK_UARTA>;
                status = "disabled";
        };
@@ -245,9 +253,9 @@
                compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
                reg = <0x70006040 0x40>;
                reg-shift = <2>;
-                interrupts = <0 37 0x04>;
+                interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 9>;
-                clocks = <&tegra_car 160>;
+                clocks = <&tegra_car TEGRA30_CLK_UARTB>;
                status = "disabled";
        };
@@ -255,9 +263,9 @@
                compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
                reg = <0x70006200 0x100>;
                reg-shift = <2>;
-                interrupts = <0 46 0x04>;
+                interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 10>;
-                clocks = <&tegra_car 55>;
+                clocks = <&tegra_car TEGRA30_CLK_UARTC>;
                status = "disabled";
        };
@@ -265,9 +273,9 @@
                compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
                reg = <0x70006300 0x100>;
                reg-shift = <2>;
-                interrupts = <0 90 0x04>;
+                interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 19>;
-                clocks = <&tegra_car 65>;
+                clocks = <&tegra_car TEGRA30_CLK_UARTD>;
                status = "disabled";
        };
@@ -275,9 +283,9 @@
                compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
                reg = <0x70006400 0x100>;
                reg-shift = <2>;
-                interrupts = <0 91 0x04>;
+                interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 20>;
-                clocks = <&tegra_car 66>;
+                clocks = <&tegra_car TEGRA30_CLK_UARTE>;
                status = "disabled";
        };
@@ -285,24 +293,25 @@
                compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
                reg = <0x7000a000 0x100>;
                #pwm-cells = <2>;
-                clocks = <&tegra_car 17>;
+                clocks = <&tegra_car TEGRA30_CLK_PWM>;
                status = "disabled";
        };
        rtc {
                compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
                reg = <0x7000e000 0x100>;
-                interrupts = <0 2 0x04>;
+                interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&tegra_car 4>;
+                clocks = <&tegra_car TEGRA30_CLK_RTC>;
        };
        i2c@7000c000 {
                compatible =  "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
                reg = <0x7000c000 0x100>;
-                interrupts = <0 38 0x04>;
+                interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&tegra_car 12>, <&tegra_car 182>;
+                clocks = <&tegra_car TEGRA30_CLK_I2C1>,
+                         <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
                clock-names = "div-clk", "fast-clk";
                status = "disabled";
        };
@@ -310,10 +319,11 @@
        i2c@7000c400 {
                compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
                reg = <0x7000c400 0x100>;
-                interrupts = <0 84 0x04>;
+                interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&tegra_car 54>, <&tegra_car 182>;
+                clocks = <&tegra_car TEGRA30_CLK_I2C2>,
+                         <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
                clock-names = "div-clk", "fast-clk";
                status = "disabled";
        };
@@ -321,10 +331,11 @@
        i2c@7000c500 {
                compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
                reg = <0x7000c500 0x100>;
-                interrupts = <0 92 0x04>;
+                interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&tegra_car 67>, <&tegra_car 182>;
+                clocks = <&tegra_car TEGRA30_CLK_I2C3>,
+                         <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
                clock-names = "div-clk", "fast-clk";
                status = "disabled";
        };
@@ -332,10 +343,11 @@
        i2c@7000c700 {
                compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
                reg = <0x7000c700 0x100>;
-                interrupts = <0 120 0x04>;
+                interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&tegra_car 103>, <&tegra_car 182>;
+                clocks = <&tegra_car TEGRA30_CLK_I2C4>,
+                         <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
                clock-names = "div-clk", "fast-clk";
                status = "disabled";
        };
@@ -343,10 +355,11 @@
        i2c@7000d000 {
                compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
                reg = <0x7000d000 0x100>;
-                interrupts = <0 53 0x04>;
+                interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&tegra_car 47>, <&tegra_car 182>;
+                clocks = <&tegra_car TEGRA30_CLK_I2C5>,
+                         <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
                clock-names = "div-clk", "fast-clk";
                status = "disabled";
        };
@@ -354,81 +367,81 @@
        spi@7000d400 {
                compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
                reg = <0x7000d400 0x200>;
-                interrupts = <0 59 0x04>;
+                interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 15>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&tegra_car 41>;
+                clocks = <&tegra_car TEGRA30_CLK_SBC1>;
                status = "disabled";
        };
        spi@7000d600 {
                compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
                reg = <0x7000d600 0x200>;
-                interrupts = <0 82 0x04>;
+                interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 16>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&tegra_car 44>;
+                clocks = <&tegra_car TEGRA30_CLK_SBC2>;
                status = "disabled";
        };
        spi@7000d800 {
                compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
                reg = <0x7000d800 0x200>;
-                interrupts = <0 83 0x04>;
+                interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 17>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&tegra_car 46>;
+                clocks = <&tegra_car TEGRA30_CLK_SBC3>;
                status = "disabled";
        };
        spi@7000da00 {
                compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
                reg = <0x7000da00 0x200>;
-                interrupts = <0 93 0x04>;
+                interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 18>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&tegra_car 68>;
+                clocks = <&tegra_car TEGRA30_CLK_SBC4>;
                status = "disabled";
        };
        spi@7000dc00 {
                compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
                reg = <0x7000dc00 0x200>;
-                interrupts = <0 94 0x04>;
+                interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 27>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&tegra_car 104>;
+                clocks = <&tegra_car TEGRA30_CLK_SBC5>;
                status = "disabled";
        };
        spi@7000de00 {
                compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
                reg = <0x7000de00 0x200>;
-                interrupts = <0 79 0x04>;
+                interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 28>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&tegra_car 105>;
+                clocks = <&tegra_car TEGRA30_CLK_SBC6>;
                status = "disabled";
        };
        kbc {
                compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
                reg = <0x7000e200 0x100>;
-                interrupts = <0 85 0x04>;
+                interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&tegra_car 36>;
+                clocks = <&tegra_car TEGRA30_CLK_KBC>;
                status = "disabled";
        };
        pmc {
                compatible = "nvidia,tegra30-pmc";
                reg = <0x7000e400 0x400>;
-                clocks = <&tegra_car 218>, <&clk32k_in>;
+                clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
                clock-names = "pclk", "clk32k_in";
        };
@@ -438,7 +451,7 @@
                       0x7000f03c 0x1b4
                       0x7000f200 0x028
                       0x7000f284 0x17c>;
-                interrupts = <0 77 0x04>;
+                interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
        };
        iommu {
@@ -455,12 +468,19 @@
                compatible = "nvidia,tegra30-ahub";
                reg = <0x70080000 0x200
                       0x70080200 0x100>;
-                interrupts = <0 103 0x04>;
+                interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 1>;
-                clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
+                clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
-                         <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
+                         <&tegra_car TEGRA30_CLK_APBIF>,
-                         <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
+                         <&tegra_car TEGRA30_CLK_I2S0>,
-                         <&tegra_car 110>, <&tegra_car 162>;
+                         <&tegra_car TEGRA30_CLK_I2S1>,
+                         <&tegra_car TEGRA30_CLK_I2S2>,
+                         <&tegra_car TEGRA30_CLK_I2S3>,
+                         <&tegra_car TEGRA30_CLK_I2S4>,
+                         <&tegra_car TEGRA30_CLK_DAM0>,
+                         <&tegra_car TEGRA30_CLK_DAM1>,
+                         <&tegra_car TEGRA30_CLK_DAM2>,
+                         <&tegra_car TEGRA30_CLK_SPDIF_IN>;
                clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
                              "i2s3", "i2s4", "dam0", "dam1", "dam2",
                              "spdif_in";
@@ -472,7 +492,7 @@
                        compatible = "nvidia,tegra30-i2s";
                        reg = <0x70080300 0x100>;
                        nvidia,ahub-cif-ids = <4 4>;
-                        clocks = <&tegra_car 30>;
+                        clocks = <&tegra_car TEGRA30_CLK_I2S0>;
                        status = "disabled";
                };
@@ -480,7 +500,7 @@
                        compatible = "nvidia,tegra30-i2s";
                        reg = <0x70080400 0x100>;
                        nvidia,ahub-cif-ids = <5 5>;
-                        clocks = <&tegra_car 11>;
+                        clocks = <&tegra_car TEGRA30_CLK_I2S1>;
                        status = "disabled";
                };
@@ -488,7 +508,7 @@
                        compatible = "nvidia,tegra30-i2s";
                        reg = <0x70080500 0x100>;
                        nvidia,ahub-cif-ids = <6 6>;
-                        clocks = <&tegra_car 18>;
+                        clocks = <&tegra_car TEGRA30_CLK_I2S2>;
                        status = "disabled";
                };
@@ -496,7 +516,7 @@
                        compatible = "nvidia,tegra30-i2s";
                        reg = <0x70080600 0x100>;
                        nvidia,ahub-cif-ids = <7 7>;
-                        clocks = <&tegra_car 101>;
+                        clocks = <&tegra_car TEGRA30_CLK_I2S3>;
                        status = "disabled";
                };
@@ -504,7 +524,7 @@
                        compatible = "nvidia,tegra30-i2s";
                        reg = <0x70080700 0x100>;
                        nvidia,ahub-cif-ids = <8 8>;
-                        clocks = <&tegra_car 102>;
+                        clocks = <&tegra_car TEGRA30_CLK_I2S4>;
                        status = "disabled";
                };
        };
@@ -512,32 +532,32 @@
        sdhci@78000000 {
                compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
                reg = <0x78000000 0x200>;
-                interrupts = <0 14 0x04>;
+                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&tegra_car 14>;
+                clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
                status = "disabled";
        };
        sdhci@78000200 {
                compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
                reg = <0x78000200 0x200>;
-                interrupts = <0 15 0x04>;
+                interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&tegra_car 9>;
+                clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
                status = "disabled";
        };
        sdhci@78000400 {
                compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
                reg = <0x78000400 0x200>;
-                interrupts = <0 19 0x04>;
+                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&tegra_car 69>;
+                clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
                status = "disabled";
        };
        sdhci@78000600 {
                compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
                reg = <0x78000600 0x200>;
-                interrupts = <0 31 0x04>;
+                interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&tegra_car 15>;
+                clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
                status = "disabled";
        };
@@ -572,9 +592,9 @@
        pmu {
                compatible = "arm,cortex-a9-pmu";
-                interrupts = <0 144 0x04
+                interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
-                              0 145 0x04
+                             <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
-                              0 146 0x04
+                             <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
-                              0 147 0x04>;
+                             <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
        };
 };
diff --git a/arch/arm/boot/dts/tny_a9260.dts b/arch/arm/boot/dts/tny_a9260.dts
index 367a16dcd5ef..dabe232216b4 100644
--- a/arch/arm/boot/dts/tny_a9260.dts
+++ b/arch/arm/boot/dts/tny_a9260.dts
@@ -6,8 +6,8 @@
 * Licensed under GPLv2.
 */
 /dts-v1/;
-/include/ "at91sam9260.dtsi"
+#include "at91sam9260.dtsi"
-/include/ "tny_a9260_common.dtsi"
+#include "tny_a9260_common.dtsi"
 / {
        model = "Calao TNY A9260";
diff --git a/arch/arm/boot/dts/tny_a9263.dts b/arch/arm/boot/dts/tny_a9263.dts
index dee9c571306b..0751a6a979a8 100644
--- a/arch/arm/boot/dts/tny_a9263.dts
+++ b/arch/arm/boot/dts/tny_a9263.dts
@@ -6,7 +6,7 @@
 * Licensed under GPLv2 only
 */
 /dts-v1/;
-/include/ "at91sam9263.dtsi"
+#include "at91sam9263.dtsi"
 / {
        model = "Calao TNY A9263";
@@ -38,7 +38,7 @@
                        };
                        usb1: gadget@fff78000 {
-                                atmel,vbus-gpio = <&pioB 11 0>;
+                                atmel,vbus-gpio = <&pioB 11 GPIO_ACTIVE_HIGH>;
                                status = "okay";
                        };
                };
diff --git a/arch/arm/boot/dts/tny_a9g20.dts b/arch/arm/boot/dts/tny_a9g20.dts
index e1ab64c72dba..8456d70bb42b 100644
--- a/arch/arm/boot/dts/tny_a9g20.dts
+++ b/arch/arm/boot/dts/tny_a9g20.dts
@@ -6,8 +6,8 @@
 * Licensed under GPLv2.
 */
 /dts-v1/;
-/include/ "at91sam9g20.dtsi"
+#include "at91sam9g20.dtsi"
-/include/ "tny_a9260_common.dtsi"
+#include "tny_a9260_common.dtsi"
 / {
        model = "Calao TNY A9G20";
diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi
index b3034da00a37..ae6a17aed9ee 100644
--- a/arch/arm/boot/dts/twl4030.dtsi
+++ b/arch/arm/boot/dts/twl4030.dtsi
@@ -47,6 +47,12 @@
                regulator-max-microvolt = <3150000>;
        };
+        vmmc2: regulator-vmmc2 {
+                compatible = "ti,twl4030-vmmc2";
+                regulator-min-microvolt = <1850000>;
+                regulator-max-microvolt = <3150000>;
+        };
        vusb1v5: regulator-vusb1v5 {
                compatible = "ti,twl4030-vusb1v5";
        };
diff --git a/arch/arm/boot/dts/twl4030_omap3.dtsi b/arch/arm/boot/dts/twl4030_omap3.dtsi
new file mode 100644
index 000000000000..c353ef0a6ac7
--- /dev/null
+++ b/arch/arm/boot/dts/twl4030_omap3.dtsi
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2013 Linaro, Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&twl {
+        pinctrl-names = "default";
+        pinctrl-0 = <&twl4030_pins>;
+};
+&omap3_pmx_core {
+        /*
+         * On most OMAP3 platforms, the twl4030 IRQ line is connected
+         * to the SYS_NIRQ line on OMAP.  Therefore, configure the
+         * defaults for the SYS_NIRQ pin here.
+         */
+        twl4030_pins: pinmux_twl4030_pins {
+                pinctrl-single,pins = <
+                        0x1b0 (PIN_INPUT_PULLUP | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* sys_nirq.sys_nirq */
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/usb_a9260.dts b/arch/arm/boot/dts/usb_a9260.dts
index 296216058c11..de0c24f5210a 100644
--- a/arch/arm/boot/dts/usb_a9260.dts
+++ b/arch/arm/boot/dts/usb_a9260.dts
@@ -6,8 +6,8 @@
 * Licensed under GPLv2 or later.
 */
 /dts-v1/;
-/include/ "at91sam9260.dtsi"
+#include "at91sam9260.dtsi"
-/include/ "usb_a9260_common.dtsi"
+#include "usb_a9260_common.dtsi"
 / {
        model = "Calao USB A9260";
@@ -20,4 +20,13 @@
        memory {
                reg = <0x20000000 0x4000000>;
        };
+        ahb {
+                apb {
+                        shdwc@fffffd10 {
+                                atmel,wakeup-counter = <10>;
+                                atmel,wakeup-rtt-timer;
+                        };
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/usb_a9260_common.dtsi b/arch/arm/boot/dts/usb_a9260_common.dtsi
index e70d229baef5..285977682cf3 100644
--- a/arch/arm/boot/dts/usb_a9260_common.dtsi
+++ b/arch/arm/boot/dts/usb_a9260_common.dtsi
@@ -30,7 +30,7 @@
                        };
                        usb1: gadget@fffa4000 {
-                                atmel,vbus-gpio = <&pioC 5 0>;
+                                atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
                                status = "okay";
                        };
                };
@@ -93,7 +93,7 @@
                user_led {
                        label = "user_led";
-                        gpios = <&pioB 21 1>;
+                        gpios = <&pioB 21 GPIO_ACTIVE_LOW>;
                        linux,default-trigger = "heartbeat";
                };
        };
@@ -105,7 +105,7 @@
                user_pb {
                        label = "user_pb";
-                        gpios = <&pioB 10 1>;
+                        gpios = <&pioB 10 GPIO_ACTIVE_LOW>;
                        linux,code = <28>;
                        gpio-key,wakeup;
                };
diff --git a/arch/arm/boot/dts/usb_a9263.dts b/arch/arm/boot/dts/usb_a9263.dts
index 6fe05ccb6203..290e60383baf 100644
--- a/arch/arm/boot/dts/usb_a9263.dts
+++ b/arch/arm/boot/dts/usb_a9263.dts
@@ -6,7 +6,7 @@
 * Licensed under GPLv2 only
 */
 /dts-v1/;
-/include/ "at91sam9263.dtsi"
+#include "at91sam9263.dtsi"
 / {
        model = "Calao USB A9263";
@@ -43,10 +43,24 @@
                        };
                        usb1: gadget@fff78000 {
-                                atmel,vbus-gpio = <&pioB 11 0>;
+                                atmel,vbus-gpio = <&pioB 11 GPIO_ACTIVE_HIGH>;
                                status = "okay";
                        };
+                        spi0: spi@fffa4000 {
+                                cs-gpios = <&pioB 15 GPIO_ACTIVE_HIGH>;
+                                status = "okay";
+                                mtd_dataflash@0 {
+                                        compatible = "atmel,at45", "atmel,dataflash";
+                                        reg = <0>;
+                                        spi-max-frequency = <15000000>;
+                                };
+                        };
+                        shdwc@fffffd10 {
+                                atmel,wakeup-counter = <10>;
+                                atmel,wakeup-rtt-timer;
+                        };
                };
                nand0: nand@40000000 {
@@ -107,7 +121,7 @@
                user_led {
                        label = "user_led";
-                        gpios = <&pioB 21 0>;
+                        gpios = <&pioB 21 GPIO_ACTIVE_HIGH>;
                        linux,default-trigger = "heartbeat";
                };
        };
@@ -119,7 +133,7 @@
                user_pb {
                        label = "user_pb";
-                        gpios = <&pioB 10 1>;
+                        gpios = <&pioB 10 GPIO_ACTIVE_LOW>;
                        linux,code = <28>;
                        gpio-key,wakeup;
                };
diff --git a/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi b/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi
index ad3eca17c436..5b0ffc1a0b24 100644
--- a/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi
+++ b/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi
@@ -28,39 +28,39 @@
                user_led1 {
                        label = "user_led1";
-                        gpios = <&pioB 20 1>;
+                        gpios = <&pioB 20 GPIO_ACTIVE_LOW>;
                };
 /*
 * led already used by mother board but active as high
 *               user_led2 {
 *                       label = "user_led2";
-*                       gpios = <&pioB 21 1>;
+*                       gpios = <&pioB 21 GPIO_ACTIVE_LOW>;
 *               };
 */
                user_led3 {
                        label = "user_led3";
-                        gpios = <&pioB 22 1>;
+                        gpios = <&pioB 22 GPIO_ACTIVE_LOW>;
                };
                user_led4 {
                        label = "user_led4";
-                        gpios = <&pioB 23 1>;
+                        gpios = <&pioB 23 GPIO_ACTIVE_LOW>;
                };
                red {
                        label = "red";
-                        gpios = <&pioB 24 1>;
+                        gpios = <&pioB 24 GPIO_ACTIVE_LOW>;
                };
                orange {
                        label = "orange";
-                        gpios = <&pioB 30 1>;
+                        gpios = <&pioB 30 GPIO_ACTIVE_LOW>;
                };
                green {
                        label = "green";
-                        gpios = <&pioB 31 1>;
+                        gpios = <&pioB 31 GPIO_ACTIVE_LOW>;
                };
        };
@@ -71,25 +71,25 @@
                user_pb1 {
                        label = "user_pb1";
-                        gpios = <&pioB 25 1>;
+                        gpios = <&pioB 25 GPIO_ACTIVE_LOW>;
                        linux,code = <0x100>;
                };
                user_pb2 {
                        label = "user_pb2";
-                        gpios = <&pioB 13 1>;
+                        gpios = <&pioB 13 GPIO_ACTIVE_LOW>;
                        linux,code = <0x101>;
                };
                user_pb3 {
                        label = "user_pb3";
-                        gpios = <&pioA 26 1>;
+                        gpios = <&pioA 26 GPIO_ACTIVE_LOW>;
                        linux,code = <0x102>;
                };
                user_pb4 {
                        label = "user_pb4";
-                        gpios = <&pioC 9 1>;
+                        gpios = <&pioC 9 GPIO_ACTIVE_LOW>;
                        linux,code = <0x103>;
                };
        };
diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/usb_a9g20.dts
index 2dacb16ce4ae..ec77cf8f9695 100644
--- a/arch/arm/boot/dts/usb_a9g20.dts
+++ b/arch/arm/boot/dts/usb_a9g20.dts
@@ -6,25 +6,9 @@
 * Licensed under GPLv2 or later.
 */
 /dts-v1/;
-/include/ "at91sam9g20.dtsi"
+#include "usb_a9g20_common.dtsi"
-/include/ "usb_a9260_common.dtsi"
 / {
        model = "Calao USB A9G20";
        compatible = "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9";
-        chosen {
-                bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
-        };
-        memory {
-                reg = <0x20000000 0x4000000>;
-        };
-        i2c@0 {
-                rv3029c2@56 {
-                        compatible = "rv3029c2";
-                        reg = <0x56>;
-                };
-        };
 };
diff --git a/arch/arm/boot/dts/usb_a9g20_common.dtsi b/arch/arm/boot/dts/usb_a9g20_common.dtsi
new file mode 100644
index 000000000000..0b3b36182fe5
--- /dev/null
+++ b/arch/arm/boot/dts/usb_a9g20_common.dtsi
@@ -0,0 +1,27 @@
+/*
+ * usb_a9g20.dts - Device Tree file for Caloa USB A9G20 board
+ *
+ *  Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+#include "at91sam9g20.dtsi"
+#include "usb_a9260_common.dtsi"
+/ {
+        chosen {
+                bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
+        };
+        memory {
+                reg = <0x20000000 0x4000000>;
+        };
+        i2c@0 {
+                rv3029c2@56 {
+                        compatible = "rv3029c2";
+                        reg = <0x56>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/usb_a9g20_lpw.dts b/arch/arm/boot/dts/usb_a9g20_lpw.dts
new file mode 100644
index 000000000000..f8cb1b9a01c5
--- /dev/null
+++ b/arch/arm/boot/dts/usb_a9g20_lpw.dts
@@ -0,0 +1,31 @@
+/*
+ * usb_a9g20_lpw.dts - Device Tree file for Caloa USB A9G20 Low Power board
+ *
+ *  Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+#include "usb_a9g20_common.dtsi"
+/ {
+        model = "Calao USB A9G20 Low Power";
+        compatible = "calao,usb-a9g20-lpw", "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9";
+        ahb {
+                apb {
+                        spi1: spi@fffcc000 {
+                                cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>;
+                                status = "okay";
+                                mmc-slot@0 {
+                                        compatible = "mmc-spi-slot";
+                                        reg = <0>;
+                                        voltage-ranges = <3200 3400>;
+                                        spi-max-frequency = <25000000>;
+                                        interrupt-parent = <&pioC>;
+                                        interrupts = <4 IRQ_TYPE_EDGE_BOTH>;
+                                };
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/vf610-pinfunc.h b/arch/arm/boot/dts/vf610-pinfunc.h
new file mode 100644
index 000000000000..1ee681f7ce2f
--- /dev/null
+++ b/arch/arm/boot/dts/vf610-pinfunc.h
@@ -0,0 +1,810 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#ifndef __DTS_VF610_PINFUNC_H
+#define __DTS_VF610_PINFUNC_H
+/*
+ * The pin function ID for VF610 is a tuple of:
+ * <mux_reg input_reg mux_mode input_val>
+ */
+#define ALT0    0x0
+#define ALT1    0x1
+#define ALT2    0x2
+#define ALT3    0x3
+#define ALT4    0x4
+#define ALT5    0x5
+#define ALT6    0x6
+#define ALT7    0x7
+#define VF610_PAD_PTA6__GPIO_0                  0x000 0x000 ALT0 0x0
+#define VF610_PAD_PTA6__RMII_CLKOUT             0x000 0x000 ALT1 0x0
+#define VF610_PAD_PTA6__RMII_CLKIN              0x000 0x2F0 ALT2 0x0
+#define VF610_PAD_PTA6__DCU1_TCON11             0x000 0x000 ALT4 0x0
+#define VF610_PAD_PTA6__DCU1_R2                 0x000 0x000 ALT7 0x0
+#define VF610_PAD_PTA8__GPIO_1                  0x004 0x000 ALT0 0x0
+#define VF610_PAD_PTA8__TCLK                    0x004 0x000 ALT1 0x0
+#define VF610_PAD_PTA8__DCU0_R0                 0x004 0x000 ALT4 0x0
+#define VF610_PAD_PTA8__MLB_CLK                 0x004 0x354 ALT7 0x0
+#define VF610_PAD_PTA9__GPIO_2                  0x008 0x000 ALT0 0x0
+#define VF610_PAD_PTA9__TDI                     0x008 0x000 ALT1 0x0
+#define VF610_PAD_PTA9__RMII_CLKOUT             0x008 0x000 ALT2 0x0
+#define VF610_PAD_PTA9__RMII_CLKIN              0x008 0x2F0 ALT3 0x1
+#define VF610_PAD_PTA9__DCU0_R1                 0x008 0x000 ALT4 0x0
+#define VF610_PAD_PTA9__WDOG_B                  0x008 0x000 ALT6 0x0
+#define VF610_PAD_PTA10__GPIO_3                 0x00C 0x000 ALT0 0x0
+#define VF610_PAD_PTA10__TDO                    0x00C 0x000 ALT1 0x0
+#define VF610_PAD_PTA10__EXT_AUDIO_MCLK         0x00C 0x2EC ALT2 0x0
+#define VF610_PAD_PTA10__DCU0_G0                0x00C 0x000 ALT4 0x0
+#define VF610_PAD_PTA10__ENET_TS_CLKIN          0x00C 0x2F4 ALT6 0x0
+#define VF610_PAD_PTA10__MLB_SIGNAL             0x00C 0x35C ALT7 0x0
+#define VF610_PAD_PTA11__GPIO_4                 0x010 0x000 ALT0 0x0
+#define VF610_PAD_PTA11__TMS                    0x010 0x000 ALT1 0x0
+#define VF610_PAD_PTA11__DCU0_G1                0x010 0x000 ALT4 0x0
+#define VF610_PAD_PTA11__MLB_DATA               0x010 0x358 ALT7 0x0
+#define VF610_PAD_PTA12__GPIO_5                 0x014 0x000 ALT0 0x0
+#define VF610_PAD_PTA12__TRACECK                0x014 0x000 ALT1 0x0
+#define VF610_PAD_PTA12__EXT_AUDIO_MCLK         0x014 0x2EC ALT2 0x1
+#define VF610_PAD_PTA12__VIU_DATA13             0x014 0x000 ALT6 0x0
+#define VF610_PAD_PTA12__I2C0_SCL               0x014 0x33C ALT7 0x0
+#define VF610_PAD_PTA16__GPIO_6                 0x018 0x000 ALT0 0x0
+#define VF610_PAD_PTA16__TRACED0                0x018 0x000 ALT1 0x0
+#define VF610_PAD_PTA16__USB0_VBUS_EN           0x018 0x000 ALT2 0x0
+#define VF610_PAD_PTA16__ADC1_SE0               0x018 0x000 ALT3 0x0
+#define VF610_PAD_PTA16__LCD29                  0x018 0x000 ALT4 0x0
+#define VF610_PAD_PTA16__SAI2_TX_BCLK           0x018 0x370 ALT5 0x0
+#define VF610_PAD_PTA16__VIU_DATA14             0x018 0x000 ALT6 0x0
+#define VF610_PAD_PTA16__I2C0_SDA               0x018 0x340 ALT7 0x0
+#define VF610_PAD_PTA17__GPIO_7                 0x01C 0x000 ALT0 0x0
+#define VF610_PAD_PTA17__TRACED1                0x01C 0x000 ALT1 0x0
+#define VF610_PAD_PTA17__USB0_VBUS_OC           0x01C 0x000 ALT2 0x0
+#define VF610_PAD_PTA17__ADC1_SE1               0x01C 0x000 ALT3 0x0
+#define VF610_PAD_PTA17__LCD30                  0x01C 0x000 ALT4 0x0
+#define VF610_PAD_PTA17__USB0_SOF_PULSE         0x01C 0x000 ALT5 0x0
+#define VF610_PAD_PTA17__VIU_DATA15             0x01C 0x000 ALT6 0x0
+#define VF610_PAD_PTA17__I2C1_SCL               0x01C 0x344 ALT7 0x0
+#define VF610_PAD_PTA18__GPIO_8                 0x020 0x000 ALT0 0x0
+#define VF610_PAD_PTA18__TRACED2                0x020 0x000 ALT1 0x0
+#define VF610_PAD_PTA18__ADC0_SE0               0x020 0x000 ALT2 0x0
+#define VF610_PAD_PTA18__FTM1_QD_PHA            0x020 0x334 ALT3 0x0
+#define VF610_PAD_PTA18__LCD31                  0x020 0x000 ALT4 0x0
+#define VF610_PAD_PTA18__SAI2_TX_DATA           0x020 0x000 ALT5 0x0
+#define VF610_PAD_PTA18__VIU_DATA16             0x020 0x000 ALT6 0x0
+#define VF610_PAD_PTA18__I2C1_SDA               0x020 0x348 ALT7 0x0
+#define VF610_PAD_PTA19__GPIO_9                 0x024 0x000 ALT0 0x0
+#define VF610_PAD_PTA19__TRACED3                0x024 0x000 ALT1 0x0
+#define VF610_PAD_PTA19__ADC0_SE1               0x024 0x000 ALT2 0x0
+#define VF610_PAD_PTA19__FTM1_QD_PHB            0x024 0x338 ALT3 0x0
+#define VF610_PAD_PTA19__LCD32                  0x024 0x000 ALT4 0x0
+#define VF610_PAD_PTA19__SAI2_TX_SYNC           0x024 0x000 ALT5 0x0
+#define VF610_PAD_PTA19__VIU_DATA17             0x024 0x000 ALT6 0x0
+#define VF610_PAD_PTA19__QSPI1_A_QSCK           0x024 0x374 ALT7 0x0
+#define VF610_PAD_PTA20__GPIO_10                0x028 0x000 ALT0 0x0
+#define VF610_PAD_PTA20__TRACED4                0x028 0x000 ALT1 0x0
+#define VF610_PAD_PTA20__LCD33                  0x028 0x000 ALT4 0x0
+#define VF610_PAD_PTA20__UART3_TX               0x028 0x394 ALT6 0x0
+#define VF610_PAD_PTA20__DCU1_HSYNC             0x028 0x000 ALT7 0x0
+#define VF610_PAD_PTA21__GPIO_11                0x02C 0x000 ALT0 0x0
+#define VF610_PAD_PTA21__TRACED5                0x02C 0x000 ALT1 0x0
+#define VF610_PAD_PTA21__SAI2_RX_BCLK           0x02C 0x364 ALT5 0x0
+#define VF610_PAD_PTA21__UART3_RX               0x02C 0x390 ALT6 0x0
+#define VF610_PAD_PTA21__DCU1_VSYNC             0x02C 0x000 ALT7 0x0
+#define VF610_PAD_PTA22__GPIO_12                0x030 0x000 ALT0 0x0
+#define VF610_PAD_PTA22__TRACED6                0x030 0x000 ALT1 0x0
+#define VF610_PAD_PTA22__SAI2_RX_DATA           0x030 0x368 ALT5 0x0
+#define VF610_PAD_PTA22__I2C2_SCL               0x030 0x34C ALT6 0x0
+#define VF610_PAD_PTA22__DCU1_TAG               0x030 0x000 ALT7 0x0
+#define VF610_PAD_PTA23__GPIO_13                0x034 0x000 ALT0 0x0
+#define VF610_PAD_PTA23__TRACED7                0x034 0x000 ALT1 0x0
+#define VF610_PAD_PTA23__SAI2_RX_SYNC           0x034 0x36C ALT5 0x0
+#define VF610_PAD_PTA23__I2C2_SDA               0x034 0x350 ALT6 0x0
+#define VF610_PAD_PTA23__DCU1_DE                0x034 0x000 ALT7 0x0
+#define VF610_PAD_PTA24__GPIO_14                0x038 0x000 ALT0 0x0
+#define VF610_PAD_PTA24__TRACED8                0x038 0x000 ALT1 0x0
+#define VF610_PAD_PTA24__USB1_VBUS_EN           0x038 0x000 ALT2 0x0
+#define VF610_PAD_PTA24__ESDHC1_CLK             0x038 0x000 ALT5 0x0
+#define VF610_PAD_PTA24__DCU1_TCON4             0x038 0x000 ALT6 0x0
+#define VF610_PAD_PTA24__DDR_TEST_PAD_CTRL      0x038 0x000 ALT7 0x0
+#define VF610_PAD_PTA25__GPIO_15                0x03C 0x000 ALT0 0x0
+#define VF610_PAD_PTA25__TRACED9                0x03C 0x000 ALT1 0x0
+#define VF610_PAD_PTA25__USB1_VBUS_OC           0x03C 0x000 ALT2 0x0
+#define VF610_PAD_PTA25__ESDHC1_CMD             0x03C 0x000 ALT5 0x0
+#define VF610_PAD_PTA25__DCU1_TCON5             0x03C 0x000 ALT6 0x0
+#define VF610_PAD_PTA26__GPIO_16                0x040 0x000 ALT0 0x0
+#define VF610_PAD_PTA26__TRACED10               0x040 0x000 ALT1 0x0
+#define VF610_PAD_PTA26__SAI3_TX_BCLK           0x040 0x000 ALT2 0x0
+#define VF610_PAD_PTA26__ESDHC1_DAT0            0x040 0x000 ALT5 0x0
+#define VF610_PAD_PTA26__DCU1_TCON6             0x040 0x000 ALT6 0x0
+#define VF610_PAD_PTA27__GPIO_17                0x044 0x000 ALT0 0x0
+#define VF610_PAD_PTA27__TRACED11               0x044 0x000 ALT1 0x0
+#define VF610_PAD_PTA27__SAI3_RX_BCLK           0x044 0x000 ALT2 0x0
+#define VF610_PAD_PTA27__ESDHC1_DAT1            0x044 0x000 ALT5 0x0
+#define VF610_PAD_PTA27__DCU1_TCON7             0x044 0x000 ALT6 0x0
+#define VF610_PAD_PTA28__GPIO_18                0x048 0x000 ALT0 0x0
+#define VF610_PAD_PTA28__TRACED12               0x048 0x000 ALT1 0x0
+#define VF610_PAD_PTA28__SAI3_RX_DATA           0x048 0x000 ALT2 0x0
+#define VF610_PAD_PTA28__ENET1_1588_TMR0        0x048 0x000 ALT3 0x0
+#define VF610_PAD_PTA28__UART4_TX               0x048 0x000 ALT4 0x0
+#define VF610_PAD_PTA28__ESDHC1_DATA2           0x048 0x000 ALT5 0x0
+#define VF610_PAD_PTA28__DCU1_TCON8             0x048 0x000 ALT6 0x0
+#define VF610_PAD_PTA29__GPIO_19                0x04C 0x000 ALT0 0x0
+#define VF610_PAD_PTA29__TRACED13               0x04C 0x000 ALT1 0x0
+#define VF610_PAD_PTA29__SAI3_TX_DATA           0x04C 0x000 ALT2 0x0
+#define VF610_PAD_PTA29__ENET1_1588_TMR1        0x04C 0x000 ALT3 0x0
+#define VF610_PAD_PTA29__UART4_RX               0x04C 0x000 ALT4 0x0
+#define VF610_PAD_PTA29__ESDHC1_DAT3            0x04C 0x000 ALT5 0x0
+#define VF610_PAD_PTA29__DCU1_TCON9             0x04C 0x000 ALT6 0x0
+#define VF610_PAD_PTA30__GPIO_20                0x050 0x000 ALT0 0x0
+#define VF610_PAD_PTA30__TRACED14               0x050 0x000 ALT1 0x0
+#define VF610_PAD_PTA30__SAI3_RX_SYNC           0x050 0x000 ALT2 0x0
+#define VF610_PAD_PTA30__ENET1_1588_TMR2        0x050 0x000 ALT3 0x0
+#define VF610_PAD_PTA30__UART4_RTS              0x050 0x000 ALT4 0x0
+#define VF610_PAD_PTA30__I2C3_SCL               0x050 0x000 ALT5 0x0
+#define VF610_PAD_PTA30__UART3_TX               0x050 0x394 ALT7 0x1
+#define VF610_PAD_PTA31__GPIO_21                0x054 0x000 ALT0 0x0
+#define VF610_PAD_PTA31__TRACED15               0x054 0x000 ALT1 0x0
+#define VF610_PAD_PTA31__SAI3_TX_SYNC           0x054 0x000 ALT2 0x0
+#define VF610_PAD_PTA31__ENET1_1588_TMR3        0x054 0x000 ALT3 0x0
+#define VF610_PAD_PTA31__UART4_CTS              0x054 0x000 ALT4 0x0
+#define VF610_PAD_PTA31__I2C3_SDA               0x054 0x000 ALT5 0x0
+#define VF610_PAD_PTA31__UART3_RX               0x054 0x390 ALT7 0x1
+#define VF610_PAD_PTB0__GPIO_22                 0x058 0x000 ALT0 0x0
+#define VF610_PAD_PTB0__FTM0_CH0                0x058 0x000 ALT1 0x0
+#define VF610_PAD_PTB0__ADC0_SE2                0x058 0x000 ALT2 0x0
+#define VF610_PAD_PTB0__TRACE_CTL               0x058 0x000 ALT3 0x0
+#define VF610_PAD_PTB0__LCD34                   0x058 0x000 ALT4 0x0
+#define VF610_PAD_PTB0__SAI2_RX_BCLK            0x058 0x364 ALT5 0x1
+#define VF610_PAD_PTB0__VIU_DATA18              0x058 0x000 ALT6 0x0
+#define VF610_PAD_PTB0__QSPI1_A_QPCS0           0x058 0x000 ALT7 0x0
+#define VF610_PAD_PTB1__GPIO_23                 0x05C 0x000 ALT0 0x0
+#define VF610_PAD_PTB1__FTM0_CH1                0x05C 0x000 ALT1 0x0
+#define VF610_PAD_PTB1__ADC0_SE3                0x05C 0x000 ALT2 0x0
+#define VF610_PAD_PTB1__SRC_RCON30              0x05C 0x000 ALT3 0x0
+#define VF610_PAD_PTB1__LCD35                   0x05C 0x000 ALT4 0x0
+#define VF610_PAD_PTB1__SAI2_RX_DATA            0x05C 0x368 ALT5 0x1
+#define VF610_PAD_PTB1__VIU_DATA19              0x05C 0x000 ALT6 0x0
+#define VF610_PAD_PTB1__QSPI1_A_DATA3           0x05C 0x000 ALT7 0x0
+#define VF610_PAD_PTB2__GPIO_24                 0x060 0x000 ALT0 0x0
+#define VF610_PAD_PTB2__FTM0_CH2                0x060 0x000 ALT1 0x0
+#define VF610_PAD_PTB2__ADC1_SE2                0x060 0x000 ALT2 0x0
+#define VF610_PAD_PTB2__SRC_RCON31              0x060 0x000 ALT3 0x0
+#define VF610_PAD_PTB2__LCD36                   0x060 0x000 ALT4 0x0
+#define VF610_PAD_PTB2__SAI2_RX_SYNC            0x060 0x36C ALT5 0x1
+#define VF610_PAD_PTB2__VIDEO_IN0_DATA20        0x060 0x000 ALT6 0x0
+#define VF610_PAD_PTB2__QSPI1_A_DATA2           0x060 0x000 ALT7 0x0
+#define VF610_PAD_PTB3__GPIO_25                 0x064 0x000 ALT0 0x0
+#define VF610_PAD_PTB3__FTM0_CH3                0x064 0x000 ALT1 0x0
+#define VF610_PAD_PTB3__ADC1_SE3                0x064 0x000 ALT2 0x0
+#define VF610_PAD_PTB3__PDB_EXTRIG              0x064 0x000 ALT3 0x0
+#define VF610_PAD_PTB3__LCD37                   0x064 0x000 ALT4 0x0
+#define VF610_PAD_PTB3__VIU_DATA21              0x064 0x000 ALT6 0x0
+#define VF610_PAD_PTB3__QSPI1_A_DATA1           0x064 0x000 ALT7 0x0
+#define VF610_PAD_PTB4__GPIO_26                 0x068 0x000 ALT0 0x0
+#define VF610_PAD_PTB4__FTM0_CH4                0x068 0x000 ALT1 0x0
+#define VF610_PAD_PTB4__UART1_TX                0x068 0x380 ALT2 0x0
+#define VF610_PAD_PTB4__ADC0_SE4                0x068 0x000 ALT3 0x0
+#define VF610_PAD_PTB4__LCD38                   0x068 0x000 ALT4 0x0
+#define VF610_PAD_PTB4__VIU_FID                 0x068 0x3A8 ALT5 0x0
+#define VF610_PAD_PTB4__VIU_DATA22              0x068 0x000 ALT6 0x0
+#define VF610_PAD_PTB4__QSPI1_A_DATA0           0x068 0x000 ALT7 0x0
+#define VF610_PAD_PTB5__GPIO_27                 0x06C 0x000 ALT0 0x0
+#define VF610_PAD_PTB5__FTM0_CH5                0x06C 0x000 ALT1 0x0
+#define VF610_PAD_PTB5__UART1_RX                0x06C 0x37C ALT2 0x0
+#define VF610_PAD_PTB5__ADC1_SE4                0x06C 0x000 ALT3 0x0
+#define VF610_PAD_PTB5__LCD39                   0x06C 0x000 ALT4 0x0
+#define VF610_PAD_PTB5__VIU_DE                  0x06C 0x3A4 ALT5 0x0
+#define VF610_PAD_PTB5__QSPI1_A_DQS             0x06C 0x000 ALT7 0x0
+#define VF610_PAD_PTB6__GPIO_28                 0x070 0x000 ALT0 0x0
+#define VF610_PAD_PTB6__FTM0_CH6                0x070 0x000 ALT1 0x0
+#define VF610_PAD_PTB6__UART1_RTS               0x070 0x000 ALT2 0x0
+#define VF610_PAD_PTB6__QSPI0_QPCS1_A           0x070 0x000 ALT3 0x0
+#define VF610_PAD_PTB6__LCD_LCD40               0x070 0x000 ALT4 0x0
+#define VF610_PAD_PTB6__FB_CLKOUT               0x070 0x000 ALT5 0x0
+#define VF610_PAD_PTB6__VIU_HSYNC               0x070 0x000 ALT6 0x0
+#define VF610_PAD_PTB6__UART2_TX                0x070 0x38C ALT7 0x0
+#define VF610_PAD_PTB7__GPIO_29                 0x074 0x000 ALT0 0x0
+#define VF610_PAD_PTB7__FTM0_CH7                0x074 0x000 ALT1 0x0
+#define VF610_PAD_PTB7__UART1_CTS               0x074 0x378 ALT2 0x0
+#define VF610_PAD_PTB7__QSPI0_B_QPCS1           0x074 0x000 ALT3 0x0
+#define VF610_PAD_PTB7__LCD41                   0x074 0x000 ALT4 0x0
+#define VF610_PAD_PTB7__VIU_VSYNC               0x074 0x000 ALT6 0x0
+#define VF610_PAD_PTB7__UART2_RX                0x074 0x388 ALT7 0x0
+#define VF610_PAD_PTB8__GPIO_30                 0x078 0x000 ALT0 0x0
+#define VF610_PAD_PTB8__FTM1_CH0                0x078 0x32C ALT1 0x0
+#define VF610_PAD_PTB8__FTM1_QD_PHA             0x078 0x334 ALT3 0x1
+#define VF610_PAD_PTB8__VIU_DE                  0x078 0x3A4 ALT5 0x1
+#define VF610_PAD_PTB8__DCU1_R6                 0x078 0x000 ALT7 0x0
+#define VF610_PAD_PTB9__GPIO_31                 0x07C 0x000 ALT0 0x0
+#define VF610_PAD_PTB9__FTM1_CH1                0x07C 0x330 ALT1 0x0
+#define VF610_PAD_PTB9__FTM1_QD_PHB             0x07C 0x338 ALT3 0x1
+#define VF610_PAD_PTB9__DCU1_R7                 0x07C 0x000 ALT7 0x0
+#define VF610_PAD_PTB10__GPIO_32                0x080 0x000 ALT0 0x0
+#define VF610_PAD_PTB10__UART0_TX               0x080 0x000 ALT1 0x0
+#define VF610_PAD_PTB10__DCU0_TCON4             0x080 0x000 ALT4 0x0
+#define VF610_PAD_PTB10__VIU_DE                 0x080 0x3A4 ALT5 0x2
+#define VF610_PAD_PTB10__CKO1                   0x080 0x000 ALT6 0x0
+#define VF610_PAD_PTB10__ENET_TS_CLKIN          0x080 0x2F4 ALT7 0x1
+#define VF610_PAD_PTB11__GPIO_33                0x084 0x000 ALT0 0x0
+#define VF610_PAD_PTB11__UART0_RX               0x084 0x000 ALT1 0x0
+#define VF610_PAD_PTB11__DCU0_TCON5             0x084 0x000 ALT4 0x0
+#define VF610_PAD_PTB11__SNVS_ALARM_OUT_B       0x084 0x000 ALT5 0x0
+#define VF610_PAD_PTB11__CKO2                   0x084 0x000 ALT6 0x0
+#define VF610_PAD_PTB11_ENET0_1588_TMR0         0x084 0x304 ALT7 0x0
+#define VF610_PAD_PTB12__GPIO_34                0x088 0x000 ALT0 0x0
+#define VF610_PAD_PTB12__UART0_RTS              0x088 0x000 ALT1 0x0
+#define VF610_PAD_PTB12__DSPI0_CS5              0x088 0x000 ALT3 0x0
+#define VF610_PAD_PTB12__DCU0_TCON6             0x088 0x000 ALT4 0x0
+#define VF610_PAD_PTB12__FB_AD1                 0x088 0x000 ALT5 0x0
+#define VF610_PAD_PTB12__NMI                    0x088 0x000 ALT6 0x0
+#define VF610_PAD_PTB12__ENET0_1588_TMR1        0x088 0x308 ALT7 0x0
+#define VF610_PAD_PTB13__GPIO_35                0x08C 0x000 ALT0 0x0
+#define VF610_PAD_PTB13__UART0_CTS              0x08C 0x000 ALT1 0x0
+#define VF610_PAD_PTB13__DSPI0_CS4              0x08C 0x000 ALT3 0x0
+#define VF610_PAD_PTB13__DCU0_TCON7             0x08C 0x000 ALT4 0x0
+#define VF610_PAD_PTB13__FB_AD0                 0x08C 0x000 ALT5 0x0
+#define VF610_PAD_PTB13__TRACE_CTL              0x08C 0x000 ALT6 0x0
+#define VF610_PAD_PTB14__GPIO_36                0x090 0x000 ALT0 0x0
+#define VF610_PAD_PTB14__CAN0_RX                0x090 0x000 ALT1 0x0
+#define VF610_PAD_PTB14__I2C0_SCL               0x090 0x33C ALT2 0x1
+#define VF610_PAD_PTB14__DCU0_TCON8             0x090 0x000 ALT4 0x0
+#define VF610_PAD_PTB14__DCU1_PCLK              0x090 0x000 ALT7 0x0
+#define VF610_PAD_PTB15__GPIO_37                0x094 0x000 ALT0 0x0
+#define VF610_PAD_PTB15__CAN0_TX                0x094 0x000 ALT1 0x0
+#define VF610_PAD_PTB15__I2C0_SDA               0x094 0x340 ALT2 0x1
+#define VF610_PAD_PTB15__DCU0_TCON9             0x094 0x000 ALT4 0x0
+#define VF610_PAD_PTB15__VIU_PIX_CLK            0x094 0x3AC ALT7 0x0
+#define VF610_PAD_PTB16__GPIO_38                0x098 0x000 ALT0 0x0
+#define VF610_PAD_PTB16__CAN1_RX                0x098 0x000 ALT1 0x0
+#define VF610_PAD_PTB16__I2C1_SCL               0x098 0x344 ALT2 0x1
+#define VF610_PAD_PTB16__DCU0_TCON10            0x098 0x000 ALT4 0x0
+#define VF610_PAD_PTB17__GPIO_39                0x09C 0x000 ALT0 0x0
+#define VF610_PAD_PTB17__CAN1_TX                0x09C 0x000 ALT1 0x0
+#define VF610_PAD_PTB17__I2C1_SDA               0x09C 0x348 ALT2 0x1
+#define VF610_PAD_PTB17__DCU0_TCON11            0x09C 0x000 ALT4 0x0
+#define VF610_PAD_PTB18__GPIO_40                0x0A0 0x000 ALT0 0x0
+#define VF610_PAD_PTB18__DSPI0_CS1              0x0A0 0x000 ALT1 0x0
+#define VF610_PAD_PTB18__EXT_AUDIO_MCLK         0x0A0 0x2EC ALT2 0x2
+#define VF610_PAD_PTB18__VIU_DATA9              0x0A0 0x000 ALT6 0x0
+#define VF610_PAD_PTB19__GPIO_41                0x0A4 0x000 ALT0 0x0
+#define VF610_PAD_PTB19__DSPI0_CS0              0x0A4 0x000 ALT1 0x0
+#define VF610_PAD_PTB19__VIU_DATA10             0x0A4 0x000 ALT6 0x0
+#define VF610_PAD_PTB20__GPIO_42                0x0A8 0x000 ALT0 0x0
+#define VF610_PAD_PTB20__DSPI0_SIN              0x0A8 0x000 ALT1 0x0
+#define VF610_PAD_PTB20__LCD42                  0x0A8 0x000 ALT4 0x0
+#define VF610_PAD_PTB20__VIU_DATA11             0x0A8 0x000 ALT6 0x0
+#define VF610_PAD_PTB21__GPIO_43                0x0AC 0x000 ALT0 0x0
+#define VF610_PAD_PTB21__DSPI0_SOUT             0x0AC 0x000 ALT1 0x0
+#define VF610_PAD_PTB21__LCD43                  0x0AC 0x000 ALT4 0x0
+#define VF610_PAD_PTB21__VIU_DATA12             0x0AC 0x000 ALT6 0x0
+#define VF610_PAD_PTB21__DCU1_PCLK              0x0AC 0x000 ALT7 0x0
+#define VF610_PAD_PTB22__GPIO_44                0x0B0 0x000 ALT0 0x0
+#define VF610_PAD_PTB22__DSPI0_SCK              0x0B0 0x000 ALT1 0x0
+#define VF610_PAD_PTB22__VLCD                   0x0B0 0x000 ALT4 0x0
+#define VF610_PAD_PTB22__VIU_FID                0x0B0 0x3A8 ALT5 0x1
+#define VF610_PAD_PTC0__GPIO_45                 0x0B4 0x000 ALT0 0x0
+#define VF610_PAD_PTC0__ENET_RMII0_MDC          0x0B4 0x000 ALT1 0x0
+#define VF610_PAD_PTC0__FTM1_CH0                0x0B4 0x32C ALT2 0x1
+#define VF610_PAD_PTC0__DSPI0_CS3               0x0B4 0x000 ALT3 0x0
+#define VF610_PAD_PTC0__ESAI_SCKT               0x0B4 0x310 ALT4 0x0
+#define VF610_PAD_PTC0__ESDHC0_CLK              0x0B4 0x000 ALT5 0x0
+#define VF610_PAD_PTC0__VIU_DATA0               0x0B4 0x000 ALT6 0x0
+#define VF610_PAD_PTC0__SRC_RCON18              0x0B4 0x398 ALT7 0x0
+#define VF610_PAD_PTC1__GPIO_46                 0x0B8 0x000 ALT0 0x0
+#define VF610_PAD_PTC1__ENET_RMII0_MDIO         0x0B8 0x000 ALT1 0x0
+#define VF610_PAD_PTC1__FTM1_CH1                0x0B8 0x330 ALT2 0x1
+#define VF610_PAD_PTC1__DSPI0_CS2               0x0B8 0x000 ALT3 0x0
+#define VF610_PAD_PTC1__ESAI_FST                0x0B8 0x30C ALT4 0x0
+#define VF610_PAD_PTC1__ESDHC0_CMD              0x0B8 0x000 ALT5 0x0
+#define VF610_PAD_PTC1__VIU_DATA1               0x0B8 0x000 ALT6 0x0
+#define VF610_PAD_PTC1__SRC_RCON19              0x0B8 0x39C ALT7 0x0
+#define VF610_PAD_PTC2__GPIO_47                 0x0BC 0x000 ALT0 0x0
+#define VF610_PAD_PTC2__ENET_RMII0_CRS          0x0BC 0x000 ALT1 0x0
+#define VF610_PAD_PTC2__UART1_TX                0x0BC 0x380 ALT2 0x1
+#define VF610_PAD_PTC2__ESAI_SDO0               0x0BC 0x314 ALT4 0x0
+#define VF610_PAD_PTC2__ESDHC0_DAT0             0x0BC 0x000 ALT5 0x0
+#define VF610_PAD_PTC2__VIU_DATA2               0x0BC 0x000 ALT6 0x0
+#define VF610_PAD_PTC2__SRC_RCON20              0x0BC 0x3A0 ALT7 0x0
+#define VF610_PAD_PTC3__GPIO_48                 0x0C0 0x000 ALT0 0x0
+#define VF610_PAD_PTC3__ENET_RMII0_RXD1         0x0C0 0x000 ALT1 0x0
+#define VF610_PAD_PTC3__UART1_RX                0x0C0 0x37C ALT2 0x1
+#define VF610_PAD_PTC3__ESAI_SDO1               0x0C0 0x318 ALT4 0x0
+#define VF610_PAD_PTC3__ESDHC0_DAT1             0x0C0 0x000 ALT5 0x0
+#define VF610_PAD_PTC3__VIU_DATA3               0x0C0 0x000 ALT6 0x0
+#define VF610_PAD_PTC3__DCU0_R0                 0x0C0 0x000 ALT7 0x0
+#define VF610_PAD_PTC4__GPIO_49                 0x0C4 0x000 ALT0 0x0
+#define VF610_PAD_PTC4__ENET_RMII0_RXD0         0x0C4 0x000 ALT1 0x0
+#define VF610_PAD_PTC4__UART1_RTS               0x0C4 0x000 ALT2 0x0
+#define VF610_PAD_PTC4__DSPI1_CS1               0x0C4 0x000 ALT3 0x0
+#define VF610_PAD_PTC4__ESAI_SDO2               0x0C4 0x31C ALT4 0x0
+#define VF610_PAD_PTC4__ESDHC0_DAT2             0x0C4 0x000 ALT5 0x0
+#define VF610_PAD_PTC4__VIU_DATA4               0x0C4 0x000 ALT6 0x0
+#define VF610_PAD_PTC4__DCU0_R1                 0x0C4 0x000 ALT7 0x0
+#define VF610_PAD_PTC5__GPIO_50                 0x0C8 0x000 ALT0 0x0
+#define VF610_PAD_PTC5__ENET_RMII0_RXER         0x0C8 0x000 ALT1 0x0
+#define VF610_PAD_PTC5__UART1_CTS               0x0C8 0x378 ALT2 0x1
+#define VF610_PAD_PTC5__DSPI1_CS0               0x0C8 0x300 ALT3 0x0
+#define VF610_PAD_PTC5__ESAI_SDO3               0x0C8 0x320 ALT4 0x0
+#define VF610_PAD_PTC5__ESDHC0_DAT3             0x0C8 0x000 ALT5 0x0
+#define VF610_PAD_PTC5__VIU_DATA5               0x0C8 0x000 ALT6 0x0
+#define VF610_PAD_PTC5__DCU0_G0                 0x0C8 0x000 ALT7 0x0
+#define VF610_PAD_PTC6__GPIO_51                 0x0CC 0x000 ALT0 0x0
+#define VF610_PAD_PTC6__ENET_RMII0_TXD1         0x0CC 0x000 ALT1 0x0
+#define VF610_PAD_PTC6__DSPI1_SIN               0x0CC 0x2FC ALT3 0x0
+#define VF610_PAD_PTC6__ESAI_SDI0               0x0CC 0x328 ALT4 0x0
+#define VF610_PAD_PTC6__ESDHC0_WP               0x0CC 0x000 ALT5 0x0
+#define VF610_PAD_PTC6__VIU_DATA6               0x0CC 0x000 ALT6 0x0
+#define VF610_PAD_PTC6__DCU0_G1                 0x0CC 0x000 ALT7 0x0
+#define VF610_PAD_PTC7__GPIO_52                 0x0D0 0x000 ALT0 0x0
+#define VF610_PAD_PTC7__ENET_RMII0_TXD0         0x0D0 0x000 ALT1 0x0
+#define VF610_PAD_PTC7__DSPI1_SOUT              0x0D0 0x000 ALT3 0x0
+#define VF610_PAD_PTC7__ESAI_SDI1               0x0D0 0x324 ALT4 0x0
+#define VF610_PAD_PTC7__VIU_DATA7               0x0D0 0x000 ALT6 0x0
+#define VF610_PAD_PTC7__DCU0_B0                 0x0D0 0x000 ALT7 0x0
+#define VF610_PAD_PTC8__GPIO_53                 0x0D4 0x000 ALT0 0x0
+#define VF610_PAD_PTC8__ENET_RMII0_TXEN         0x0D4 0x000 ALT1 0x0
+#define VF610_PAD_PTC8__DSPI1_SCK               0x0D4 0x2F8 ALT3 0x0
+#define VF610_PAD_PTC8__VIU_DATA8               0x0D4 0x000 ALT6 0x0
+#define VF610_PAD_PTC8__DCU0_B1                 0x0D4 0x000 ALT7 0x0
+#define VF610_PAD_PTC9__GPIO_54                 0x0D8 0x000 ALT0 0x0
+#define VF610_PAD_PTC9__ENET_RMII1_MDC          0x0D8 0x000 ALT1 0x0
+#define VF610_PAD_PTC9__ESAI_SCKT               0x0D8 0x310 ALT3 0x1
+#define VF610_PAD_PTC9__MLB_CLK                 0x0D8 0x354 ALT6 0x1
+#define VF610_PAD_PTC9__DEBUG_OUT0              0x0D8 0x000 ALT7 0x0
+#define VF610_PAD_PTC10__GPIO_55                0x0DC 0x000 ALT0 0x0
+#define VF610_PAD_PTC10__ENET_RMII1_MDIO        0x0DC 0x000 ALT1 0x0
+#define VF610_PAD_PTC10__ESAI_FST               0x0DC 0x30C ALT3 0x1
+#define VF610_PAD_PTC10__MLB_SIGNAL             0x0DC 0x35C ALT6 0x1
+#define VF610_PAD_PTC10__DEBUG_OUT1             0x0DC 0x000 ALT7 0x0
+#define VF610_PAD_PTC11__GPIO_56                0x0E0 0x000 ALT0 0x0
+#define VF610_PAD_PTC11__ENET_RMII1_CRS         0x0E0 0x000 ALT1 0x0
+#define VF610_PAD_PTC11__ESAI_SDO0              0x0E0 0x314 ALT3 0x1
+#define VF610_PAD_PTC11__MLB_DATA               0x0E0 0x358 ALT6 0x1
+#define VF610_PAD_PTC11__DEBUG_OUT              0x0E0 0x000 ALT7 0x0
+#define VF610_PAD_PTC12__GPIO_57                0x0E4 0x000 ALT0 0x0
+#define VF610_PAD_PTC12__ENET_RMII_RXD1         0x0E4 0x000 ALT1 0x0
+#define VF610_PAD_PTC12__ESAI_SDO1              0x0E4 0x318 ALT3 0x1
+#define VF610_PAD_PTC12__SAI2_TX_BCLK           0x0E4 0x370 ALT5 0x1
+#define VF610_PAD_PTC12__DEBUG_OUT3             0x0E4 0x000 ALT7 0x0
+#define VF610_PAD_PTC13__GPIO_58                0x0E8 0x000 ALT0 0x0
+#define VF610_PAD_PTC13__ENET_RMII1_RXD0        0x0E8 0x000 ALT1 0x0
+#define VF610_PAD_PTC13__ESAI_SDO2              0x0E8 0x31C ALT3 0x1
+#define VF610_PAD_PTC13__SAI2_RX_BCLK           0x0E8 0x364 ALT5 0x2
+#define VF610_PAD_PTC13__DEBUG_OUT4             0x0E8 0x000 ALT7 0x0
+#define VF610_PAD_PTC14__GPIO_59                0x0EC 0x000 ALT0 0x0
+#define VF610_PAD_PTC14__ENET_RMII1_RXER        0x0EC 0x000 ALT1 0x0
+#define VF610_PAD_PTC14__ESAI_SDO3              0x0EC 0x320 ALT3 0x1
+#define VF610_PAD_PTC14__UART5_TX               0x0EC 0x000 ALT4 0x0
+#define VF610_PAD_PTC14__SAI2_RX_DATA           0x0EC 0x368 ALT5 0x2
+#define VF610_PAD_PTC14__ADC0_SE6               0x0EC 0x000 ALT6 0x0
+#define VF610_PAD_PTC14__DEBUG_OUT5             0x0EC 0x000 ALT7 0x0
+#define VF610_PAD_PTC15__GPIO_60                0x0F0 0x000 ALT0 0x0
+#define VF610_PAD_PTC15__ENET_RMII1_TXD1        0x0F0 0x000 ALT1 0x0
+#define VF610_PAD_PTC15__ESAI_SDI0              0x0F0 0x328 ALT3 0x1
+#define VF610_PAD_PTC15__UART5_RX               0x0F0 0x000 ALT4 0x0
+#define VF610_PAD_PTC15__SAI2_TX_DATA           0x0F0 0x000 ALT5 0x0
+#define VF610_PAD_PTC15__ADC0_SE7               0x0F0 0x000 ALT6 0x0
+#define VF610_PAD_PTC15__DEBUG_OUT6             0x0F0 0x000 ALT7 0x0
+#define VF610_PAD_PTC16__GPIO_61                0x0F4 0x000 ALT0 0x0
+#define VF610_PAD_PTC16__ENET_RMII1_TXD0        0x0F4 0x000 ALT1 0x0
+#define VF610_PAD_PTC16__ESAI_SDI1              0x0F4 0x324 ALT3 0x1
+#define VF610_PAD_PTC16__UART5_RTS              0x0F4 0x000 ALT4 0x0
+#define VF610_PAD_PTC16__SAI2_RX_SYNC           0x0F4 0x36C ALT5 0x2
+#define VF610_PAD_PTC16__ADC1_SE6               0x0F4 0x000 ALT6 0x0
+#define VF610_PAD_PTC16__DEBUG_OUT7             0x0F4 0x000 ALT7 0x0
+#define VF610_PAD_PTC17__GPIO_62                0x0F8 0x000 ALT0 0x0
+#define VF610_PAD_PTC17__ENET_RMII1_TXEN        0x0F8 0x000 ALT1 0x0
+#define VF610_PAD_PTC17__ADC1_SE7               0x0F8 0x000 ALT3 0x0
+#define VF610_PAD_PTC17__UART5_CTS              0x0F8 0x000 ALT4 0x0
+#define VF610_PAD_PTC17__SAI2_TX_SYNC           0x0F8 0x374 ALT5 0x1
+#define VF610_PAD_PTC17__USB1_SOF_PULSE         0x0F8 0x000 ALT6 0x0
+#define VF610_PAD_PTC17__DEBUG_OUT8             0x0F8 0x000 ALT7 0x0
+#define VF610_PAD_PTD31__GPIO_63                0x0FC 0x000 ALT0 0x0
+#define VF610_PAD_PTD31__FB_AD31                0x0FC 0x000 ALT1 0x0
+#define VF610_PAD_PTD31__NF_IO15                0x0FC 0x000 ALT2 0x0
+#define VF610_PAD_PTD31__FTM3_CH0               0x0FC 0x000 ALT4 0x0
+#define VF610_PAD_PTD31__DSPI2_CS1              0x0FC 0x000 ALT5 0x0
+#define VF610_PAD_PTD31__DEBUG_OUT9             0x0FC 0x000 ALT7 0x0
+#define VF610_PAD_PTD30__GPIO_64                0x100 0x000 ALT0 0x0
+#define VF610_PAD_PTD30__FB_AD30                0x100 0x000 ALT1 0x0
+#define VF610_PAD_PTD30__NF_IO14                0x100 0x000 ALT2 0x0
+#define VF610_PAD_PTD30__FTM3_CH1               0x100 0x000 ALT4 0x0
+#define VF610_PAD_PTD30__DSPI2_CS0              0x100 0x000 ALT5 0x0
+#define VF610_PAD_PTD30__DEBUG_OUT10            0x100 0x000 ALT7 0x0
+#define VF610_PAD_PTD29__GPIO_65                0x104 0x000 ALT0 0x0
+#define VF610_PAD_PTD29__FB_AD29                0x104 0x000 ALT1 0x0
+#define VF610_PAD_PTD29__NF_IO13                0x104 0x000 ALT2 0x0
+#define VF610_PAD_PTD29__FTM3_CH2               0x104 0x000 ALT4 0x0
+#define VF610_PAD_PTD29__DSPI2_SIN              0x104 0x000 ALT5 0x0
+#define VF610_PAD_PTD29__DEBUG_OUT11            0x104 0x000 ALT7 0x0
+#define VF610_PAD_PTD28__GPIO_66                0x108 0x000 ALT0 0x0
+#define VF610_PAD_PTD28__FB_AD28                0x108 0x000 ALT1 0x0
+#define VF610_PAD_PTD28__NF_IO12                0x108 0x000 ALT2 0x0
+#define VF610_PAD_PTD28__I2C2_SCL               0x108 0x34C ALT3 0x1
+#define VF610_PAD_PTD28__FTM3_CH3               0x108 0x000 ALT4 0x0
+#define VF610_PAD_PTD28__DSPI2_SOUT             0x108 0x000 ALT5 0x0
+#define VF610_PAD_PTD28__DEBUG_OUT12            0x108 0x000 ALT7 0x0
+#define VF610_PAD_PTD27__GPIO_67                0x10C 0x000 ALT0 0x0
+#define VF610_PAD_PTD27__FB_AD27                0x10C 0x000 ALT1 0x0
+#define VF610_PAD_PTD27__NF_IO11                0x10C 0x000 ALT2 0x0
+#define VF610_PAD_PTD27__I2C2_SDA               0x10C 0x350 ALT3 0x1
+#define VF610_PAD_PTD27__FTM3_CH4               0x10C 0x000 ALT4 0x0
+#define VF610_PAD_PTD27__DSPI2_SCK              0x10C 0x000 ALT5 0x0
+#define VF610_PAD_PTD27__DEBUG_OUT13            0x10C 0x000 ALT7 0x0
+#define VF610_PAD_PTD26__GPIO_68                0x110 0x000 ALT0 0x0
+#define VF610_PAD_PTD26__FB_AD26                0x110 0x000 ALT1 0x0
+#define VF610_PAD_PTD26__NF_IO10                0x110 0x000 ALT2 0x0
+#define VF610_PAD_PTD26__FTM3_CH5               0x110 0x000 ALT4 0x0
+#define VF610_PAD_PTD26__ESDHC1_WP              0x110 0x000 ALT5 0x0
+#define VF610_PAD_PTD26__DEBUG_OUT14            0x110 0x000 ALT7 0x0
+#define VF610_PAD_PTD25__GPIO_69                0x114 0x000 ALT0 0x0
+#define VF610_PAD_PTD25__FB_AD25                0x114 0x000 ALT1 0x0
+#define VF610_PAD_PTD25__NF_IO9                 0x114 0x000 ALT2 0x0
+#define VF610_PAD_PTD25__FTM3_CH6               0x114 0x000 ALT4 0x0
+#define VF610_PAD_PTD25__DEBUG_OUT15            0x114 0x000 ALT7 0x0
+#define VF610_PAD_PTD24__GPIO_70                0x118 0x000 ALT0 0x0
+#define VF610_PAD_PTD24__FB_AD24                0x118 0x000 ALT1 0x0
+#define VF610_PAD_PTD24__NF_IO8                 0x118 0x000 ALT2 0x0
+#define VF610_PAD_PTD24__FTM3_CH7               0x118 0x000 ALT4 0x0
+#define VF610_PAD_PTD24__DEBUG_OUT16            0x118 0x000 ALT7 0x0
+#define VF610_PAD_PTD23__GPIO_71                0x11C 0x000 ALT0 0x0
+#define VF610_PAD_PTD23__FB_AD23                0x11C 0x000 ALT1 0x0
+#define VF610_PAD_PTD23__NF_IO7                 0x11C 0x000 ALT2 0x0
+#define VF610_PAD_PTD23__FTM2_CH0               0x11C 0x000 ALT3 0x0
+#define VF610_PAD_PTD23__ENET0_1588_TMR0        0x11C 0x304 ALT4 0x1
+#define VF610_PAD_PTD23__ESDHC0_DAT4            0x11C 0x000 ALT5 0x0
+#define VF610_PAD_PTD23__UART2_TX               0x11C 0x38C ALT6 0x1
+#define VF610_PAD_PTD23__DCU1_R3                0x11C 0x000 ALT7 0x0
+#define VF610_PAD_PTD22__GPIO_72                0x120 0x000 ALT0 0x0
+#define VF610_PAD_PTD22__FB_AD22                0x120 0x000 ALT1 0x0
+#define VF610_PAD_PTD22__NF_IO6                 0x120 0x000 ALT2 0x0
+#define VF610_PAD_PTD22__FTM2_CH1               0x120 0x000 ALT3 0x0
+#define VF610_PAD_PTD22__ENET0_1588_TMR1        0x120 0x308 ALT4 0x1
+#define VF610_PAD_PTD22__ESDHC0_DAT5            0x120 0x000 ALT5 0x0
+#define VF610_PAD_PTD22__UART2_RX               0x120 0x388 ALT6 0x1
+#define VF610_PAD_PTD22__DCU1_R4                0x120 0x000 ALT7 0x0
+#define VF610_PAD_PTD21__GPIO_73                0x124 0x000 ALT0 0x0
+#define VF610_PAD_PTD21__FB_AD21                0x124 0x000 ALT1 0x0
+#define VF610_PAD_PTD21__NF_IO5                 0x124 0x000 ALT2 0x0
+#define VF610_PAD_PTD21__ENET0_1588_TMR2        0x124 0x000 ALT4 0x0
+#define VF610_PAD_PTD21__ESDHC0_DAT6            0x124 0x000 ALT5 0x0
+#define VF610_PAD_PTD21__UART2_RTS              0x124 0x000 ALT6 0x0
+#define VF610_PAD_PTD21__DCU1_R5                0x124 0x000 ALT7 0x0
+#define VF610_PAD_PTD20__GPIO_74                0x128 0x000 ALT0 0x0
+#define VF610_PAD_PTD20__FB_AD20                0x128 0x000 ALT1 0x0
+#define VF610_PAD_PTD20__NF_IO4                 0x128 0x000 ALT2 0x0
+#define VF610_PAD_PTD20__ENET0_1588_TMR3        0x128 0x000 ALT4 0x0
+#define VF610_PAD_PTD20__ESDHC0_DAT7            0x128 0x000 ALT5 0x0
+#define VF610_PAD_PTD20__UART2_CTS              0x128 0x384 ALT6 0x0
+#define VF610_PAD_PTD20__DCU1_R0                0x128 0x000 ALT7 0x0
+#define VF610_PAD_PTD19__GPIO_75                0x12C 0x000 ALT0 0x0
+#define VF610_PAD_PTD19__FB_AD19                0x12C 0x000 ALT1 0x0
+#define VF610_PAD_PTD19__NF_IO3                 0x12C 0x000 ALT2 0x0
+#define VF610_PAD_PTD19__ESAI_SCKR              0x12C 0x000 ALT3 0x0
+#define VF610_PAD_PTD19__I2C0_SCL               0x12C 0x33C ALT4 0x2
+#define VF610_PAD_PTD19__FTM2_QD_PHA            0x12C 0x000 ALT5 0x0
+#define VF610_PAD_PTD19__DCU1_R1                0x12C 0x000 ALT7 0x0
+#define VF610_PAD_PTD18__GPIO_76                0x130 0x000 ALT0 0x0
+#define VF610_PAD_PTD18__FB_AD18                0x130 0x000 ALT1 0x0
+#define VF610_PAD_PTD18__NF_IO2                 0x130 0x000 ALT2 0x0
+#define VF610_PAD_PTD18__ESAI_FSR               0x130 0x000 ALT3 0x0
+#define VF610_PAD_PTD18__I2C0_SDA               0x130 0x340 ALT4 0x2
+#define VF610_PAD_PTD18__FTM2_QD_PHB            0x130 0x000 ALT5 0x0
+#define VF610_PAD_PTD18__DCU1_G0                0x130 0x000 ALT7 0x0
+#define VF610_PAD_PTD17__GPIO_77                0x134 0x000 ALT0 0x0
+#define VF610_PAD_PTD17__FB_AD17                0x134 0x000 ALT1 0x0
+#define VF610_PAD_PTD17__NF_IO1                 0x134 0x000 ALT2 0x0
+#define VF610_PAD_PTD17__ESAI_HCKR              0x134 0x000 ALT3 0x0
+#define VF610_PAD_PTD17__I2C1_SCL               0x134 0x344 ALT4 0x2
+#define VF610_PAD_PTD17__DCU1_G1                0x134 0x000 ALT7 0x0
+#define VF610_PAD_PTD16__GPIO_78                0x138 0x000 ALT0 0x0
+#define VF610_PAD_PTD16__FB_AD16                0x138 0x000 ALT1 0x0
+#define VF610_PAD_PTD16__NF_IO0                 0x138 0x000 ALT2 0x0
+#define VF610_PAD_PTD16__ESAI_HCKT              0x138 0x000 ALT3 0x0
+#define VF610_PAD_PTD16__I2C1_SDA               0x138 0x348 ALT4 0x2
+#define VF610_PAD_PTD16__DCU1_G2                0x138 0x000 ALT7 0x0
+#define VF610_PAD_PTD0__GPIO_79                 0x13C 0x000 ALT0 0x0
+#define VF610_PAD_PTD0__QSPI0_A_QSCK            0x13C 0x000 ALT1 0x0
+#define VF610_PAD_PTD0__UART2_TX                0x13C 0x38C ALT2 0x2
+#define VF610_PAD_PTD0__FB_AD15                 0x13C 0x000 ALT4 0x0
+#define VF610_PAD_PTD0__SPDIF_EXTCLK            0x13C 0x000 ALT5 0x0
+#define VF610_PAD_PTD0__DEBUG_OUT17             0x13C 0x000 ALT7 0x0
+#define VF610_PAD_PTD1__GPIO_80                 0x140 0x000 ALT0 0x0
+#define VF610_PAD_PTD1__QSPI0_A_CS0             0x140 0x000 ALT1 0x0
+#define VF610_PAD_PTD1__UART2_RX                0x140 0x388 ALT2 0x2
+#define VF610_PAD_PTD1__FB_AD14                 0x140 0x000 ALT4 0x0
+#define VF610_PAD_PTD1__SPDIF_IN1               0x140 0x000 ALT5 0x0
+#define VF610_PAD_PTD1__DEBUG_OUT18             0x140 0x000 ALT7 0x0
+#define VF610_PAD_PTD2__GPIO_81                 0x144 0x000 ALT0 0x0
+#define VF610_PAD_PTD2__QSPI0_A_DATA3           0x144 0x000 ALT1 0x0
+#define VF610_PAD_PTD2__UART2_RTS               0x144 0x000 ALT2 0x0
+#define VF610_PAD_PTD2__DSPI1_CS3               0x144 0x000 ALT3 0x0
+#define VF610_PAD_PTD2__FB_AD13                 0x144 0x000 ALT4 0x0
+#define VF610_PAD_PTD2__SPDIF_OUT1              0x144 0x000 ALT5 0x0
+#define VF610_PAD_PTD2__DEBUG_OUT19             0x144 0x000 ALT7 0x0
+#define VF610_PAD_PTD3__GPIO_82                 0x148 0x000 ALT0 0x0
+#define VF610_PAD_PTD3__QSPI0_A_DATA2           0x148 0x000 ALT1 0x0
+#define VF610_PAD_PTD3__UART2_CTS               0x148 0x384 ALT2 0x1
+#define VF610_PAD_PTD3__DSPI1_CS2               0x148 0x000 ALT3 0x0
+#define VF610_PAD_PTD3__FB_AD12                 0x148 0x000 ALT4 0x0
+#define VF610_PAD_PTD3__SPDIF_PLOCK             0x148 0x000 ALT5 0x0
+#define VF610_PAD_PTD3__DEBUG_OUT20             0x148 0x000 ALT7 0x0
+#define VF610_PAD_PTD4__GPIO_83                 0x14C 0x000 ALT0 0x0
+#define VF610_PAD_PTD4__QSPI0_A_DATA1           0x14C 0x000 ALT1 0x0
+#define VF610_PAD_PTD4__DSPI1_CS1               0x14C 0x000 ALT3 0x0
+#define VF610_PAD_PTD4__FB_AD11                 0x14C 0x000 ALT4 0x0
+#define VF610_PAD_PTD4__SPDIF_SRCLK             0x14C 0x000 ALT5 0x0
+#define VF610_PAD_PTD4__DEBUG_OUT21             0x14C 0x000 ALT7 0x0
+#define VF610_PAD_PTD5__GPIO_84                 0x150 0x000 ALT0 0x0
+#define VF610_PAD_PTD5__QSPI0_A_DATA0           0x150 0x000 ALT1 0x0
+#define VF610_PAD_PTD5__DSPI1_CS0               0x150 0x300 ALT3 0x1
+#define VF610_PAD_PTD5__FB_AD10                 0x150 0x000 ALT4 0x0
+#define VF610_PAD_PTD5__DEBUG_OUT22             0x150 0x000 ALT7 0x0
+#define VF610_PAD_PTD6__GPIO_85                 0x154 0x000 ALT0 0x0
+#define VF610_PAD_PTD6__QSPI1_A_DQS             0x154 0x000 ALT1 0x0
+#define VF610_PAD_PTD6__DSPI1_SIN               0x154 0x2FC ALT3 0x1
+#define VF610_PAD_PTD6__FB_AD9                  0x154 0x000 ALT4 0x0
+#define VF610_PAD_PTD6__DEBUG_OUT23             0x154 0x000 ALT7 0x0
+#define VF610_PAD_PTD7__GPIO_86                 0x158 0x000 ALT0 0x0
+#define VF610_PAD_PTD7__QSPI0_B_QSCK            0x158 0x000 ALT1 0x0
+#define VF610_PAD_PTD7__DSPI1_SOUT              0x158 0x000 ALT3 0x0
+#define VF610_PAD_PTD7__FB_AD8                  0x158 0x000 ALT4 0x0
+#define VF610_PAD_PTD7__DEBUG_OUT24             0x158 0x000 ALT7 0x0
+#define VF610_PAD_PTD8__GPIO_87                 0x15C 0x000 ALT0 0x0
+#define VF610_PAD_PTD8__QSPI0_B_CS0             0x15C 0x000 ALT1 0x0
+#define VF610_PAD_PTD8__FB_CLKOUT               0x15C 0x000 ALT2 0x0
+#define VF610_PAD_PTD8__DSPI1_SCK               0x15C 0x2F8 ALT3 0x1
+#define VF610_PAD_PTD8__FB_AD7                  0x15C 0x000 ALT4 0x0
+#define VF610_PAD_PTD8__DEBUG_OUT25             0x15C 0x000 ALT7 0x0
+#define VF610_PAD_PTD9__GPIO_88                 0x160 0x000 ALT0 0x0
+#define VF610_PAD_PTD9__QSPI0_B_DATA3           0x160 0x000 ALT1 0x0
+#define VF610_PAD_PTD9__DSPI3_CS1               0x160 0x000 ALT2 0x0
+#define VF610_PAD_PTD9__FB_AD6                  0x160 0x000 ALT4 0x0
+#define VF610_PAD_PTD9__SAI1_TX_SYNC            0x160 0x360 ALT6 0x0
+#define VF610_PAD_PTD9__DCU1_B0                 0x160 0x000 ALT7 0x0
+#define VF610_PAD_PTD10__GPIO_89                0x164 0x000 ALT0 0x0
+#define VF610_PAD_PTD10__QSPI0_B_DATA2          0x164 0x000 ALT1 0x0
+#define VF610_PAD_PTD10__DSPI3_CS0              0x164 0x000 ALT2 0x0
+#define VF610_PAD_PTD10__FB_AD5                 0x164 0x000 ALT4 0x0
+#define VF610_PAD_PTD10__DCU1_B1                0x164 0x000 ALT7 0x0
+#define VF610_PAD_PTD11__GPIO_90                0x168 0x000 ALT0 0x0
+#define VF610_PAD_PTD11__QSPI0_B_DATA1          0x168 0x000 ALT1 0x0
+#define VF610_PAD_PTD11__DSPI3_SIN              0x168 0x000 ALT2 0x0
+#define VF610_PAD_PTD11__FB_AD4                 0x168 0x000 ALT4 0x0
+#define VF610_PAD_PTD11__DEBUG_OUT26            0x168 0x000 ALT7 0x0
+#define VF610_PAD_PTD12__GPIO_91                0x16C 0x000 ALT0 0x0
+#define VF610_PAD_PTD12__QSPI0_B_DATA0          0x16C 0x000 ALT1 0x0
+#define VF610_PAD_PTD12__DSPI3_SOUT             0x16C 0x000 ALT2 0x0
+#define VF610_PAD_PTD12__FB_AD3                 0x16C 0x000 ALT4 0x0
+#define VF610_PAD_PTD12__DEBUG_OUT27            0x16C 0x000 ALT7 0x0
+#define VF610_PAD_PTD13__GPIO_92                0x170 0x000 ALT0 0x0
+#define VF610_PAD_PTD13__QSPI0_B_DQS            0x170 0x000 ALT1 0x0
+#define VF610_PAD_PTD13__DSPI3_SCK              0x170 0x000 ALT2 0x0
+#define VF610_PAD_PTD13__FB_AD2                 0x170 0x000 ALT4 0x0
+#define VF610_PAD_PTD13__DEBUG_OUT28            0x170 0x000 ALT7 0x0
+#define VF610_PAD_PTB23__GPIO_93                0x174 0x000 ALT0 0x0
+#define VF610_PAD_PTB23__SAI0_TX_BCLK           0x174 0x000 ALT1 0x0
+#define VF610_PAD_PTB23__UART1_TX               0x174 0x380 ALT2 0x2
+#define VF610_PAD_PTB23__SRC_RCON18             0x174 0x398 ALT3 0x1
+#define VF610_PAD_PTB23__FB_MUXED_ALE           0x174 0x000 ALT4 0x0
+#define VF610_PAD_PTB23__FB_TS_B                0x174 0x000 ALT5 0x0
+#define VF610_PAD_PTB23__UART3_RTS              0x174 0x000 ALT6 0x0
+#define VF610_PAD_PTB23__DCU1_G3                0x174 0x000 ALT7 0x0
+#define VF610_PAD_PTB24__GPIO_94                0x178 0x000 ALT0 0x0
+#define VF610_PAD_PTB24__SAI0_RX_BCLK           0x178 0x000 ALT1 0x0
+#define VF610_PAD_PTB24__UART1_RX               0x178 0x37C ALT2 0x2
+#define VF610_PAD_PTB24__SRC_RCON19             0x178 0x39C ALT3 0x1
+#define VF610_PAD_PTB24__FB_MUXED_TSIZ0         0x178 0x000 ALT4 0x0
+#define VF610_PAD_PTB24__NF_WE_B                0x178 0x000 ALT5 0x0
+#define VF610_PAD_PTB24__UART3_CTS              0x178 0x000 ALT6 0x0
+#define VF610_PAD_PTB24__DCU1_G4                0x178 0x000 ALT7 0x0
+#define VF610_PAD_PTB25__GPIO_95                0x17C 0x000 ALT0 0x0
+#define VF610_PAD_PTB25__SAI0_RX_DATA           0x17C 0x000 ALT1 0x0
+#define VF610_PAD_PTB25__UART1_RTS              0x17C 0x000 ALT2 0x0
+#define VF610_PAD_PTB25__SRC_RCON20             0x17C 0x3A0 ALT3 0x1
+#define VF610_PAD_PTB25__FB_CS1_B               0x17C 0x000 ALT4 0x0
+#define VF610_PAD_PTB25__NF_CE0_B               0x17C 0x000 ALT5 0x0
+#define VF610_PAD_PTB25__DCU1_G5                0x17C 0x000 ALT7 0x0
+#define VF610_PAD_PTB26__GPIO_96                0x180 0x000 ALT0 0x0
+#define VF610_PAD_PTB26__SAI0_TX_DATA           0x180 0x000 ALT1 0x0
+#define VF610_PAD_PTB26__UART1_CTS              0x180 0x378 ALT2 0x2
+#define VF610_PAD_PTB26__SRC_RCON21             0x180 0x000 ALT3 0x0
+#define VF610_PAD_PTB26__FB_CS0_B               0x180 0x000 ALT4 0x0
+#define VF610_PAD_PTB26__NF_CE1_B               0x180 0x000 ALT5 0x0
+#define VF610_PAD_PTB26__DCU1_G6                0x180 0x000 ALT7 0x0
+#define VF610_PAD_PTB27__GPIO_97                0x184 0x000 ALT0 0x0
+#define VF610_PAD_PTB27__SAI0_RX_SYNC           0x184 0x000 ALT1 0x0
+#define VF610_PAD_PTB27__SRC_RCON22             0x184 0x000 ALT3 0x0
+#define VF610_PAD_PTB27__FB_OE_B                0x184 0x000 ALT4 0x0
+#define VF610_PAD_PTB27__FB_MUXED_TBST_B        0x184 0x000 ALT5 0x0
+#define VF610_PAD_PTB27__NF_RE_B                0x184 0x000 ALT6 0x0
+#define VF610_PAD_PTB27__DCU1_G7                0x184 0x000 ALT7 0x0
+#define VF610_PAD_PTB28__GPIO_98                0x188 0x000 ALT0 0x0
+#define VF610_PAD_PTB28__SAI0_TX_SYNC           0x188 0x000 ALT1 0x0
+#define VF610_PAD_PTB28__SRC_RCON23             0x188 0x000 ALT3 0x0
+#define VF610_PAD_PTB28__FB_RW_B                0x188 0x000 ALT4 0x0
+#define VF610_PAD_PTB28__DCU1_B6                0x188 0x000 ALT7 0x0
+#define VF610_PAD_PTC26__GPIO_99                0x18C 0x000 ALT0 0x0
+#define VF610_PAD_PTC26__SAI1_TX_BCLK           0x18C 0x000 ALT1 0x0
+#define VF610_PAD_PTC26__DSPI0_CS5              0x18C 0x000 ALT2 0x0
+#define VF610_PAD_PTC26__SRC_RCON24             0x18C 0x000 ALT3 0x0
+#define VF610_PAD_PTC26__FB_TA_B                0x18C 0x000 ALT4 0x0
+#define VF610_PAD_PTC26__NF_RB_B                0x18C 0x000 ALT5 0x0
+#define VF610_PAD_PTC26__DCU1_B7                0x18C 0x000 ALT7 0x0
+#define VF610_PAD_PTC27__GPIO_100               0x190 0x000 ALT0 0x0
+#define VF610_PAD_PTC27__SAI1_RX_BCLK           0x190 0x000 ALT1 0x0
+#define VF610_PAD_PTC27__DSPI0_CS4              0x190 0x000 ALT2 0x0
+#define VF610_PAD_PTC27__SRC_RCON25             0x190 0x000 ALT3 0x0
+#define VF610_PAD_PTC27__FB_BE3_B               0x190 0x000 ALT4 0x0
+#define VF610_PAD_PTC27__FB_CS3_B               0x190 0x000 ALT5 0x0
+#define VF610_PAD_PTC27__NF_ALE                 0x190 0x000 ALT6 0x0
+#define VF610_PAD_PTC27__DCU1_B2                0x190 0x000 ALT7 0x0
+#define VF610_PAD_PTC28__GPIO_101               0x194 0x000 ALT0 0x0
+#define VF610_PAD_PTC28__SAI1_RX_DATA           0x194 0x000 ALT1 0x0
+#define VF610_PAD_PTC28__DSPI0_CS3              0x194 0x000 ALT2 0x0
+#define VF610_PAD_PTC28__SRC_RCON26             0x194 0x000 ALT3 0x0
+#define VF610_PAD_PTC28__FB_BE2_B               0x194 0x000 ALT4 0x0
+#define VF610_PAD_PTC28__FB_CS2_B               0x194 0x000 ALT5 0x0
+#define VF610_PAD_PTC28__NF_CLE                 0x194 0x000 ALT6 0x0
+#define VF610_PAD_PTC28__DCU1_B3                0x194 0x000 ALT7 0x0
+#define VF610_PAD_PTC29__GPIO_102               0x198 0x000 ALT0 0x0
+#define VF610_PAD_PTC29__SAI1_TX_DATA           0x198 0x000 ALT1 0x0
+#define VF610_PAD_PTC29__DSPI0_CS2              0x198 0x000 ALT2 0x0
+#define VF610_PAD_PTC29__SRC_RCON27             0x198 0x000 ALT3 0x0
+#define VF610_PAD_PTC29__FB_BE1_B               0x198 0x000 ALT4 0x0
+#define VF610_PAD_PTC29__FB_MUXED_TSIZE1        0x198 0x000 ALT5 0x0
+#define VF610_PAD_PTC29__DCU1_B4                0x198 0x000 ALT7 0x0
+#define VF610_PAD_PTC30__GPIO_103               0x19C 0x000 ALT0 0x0
+#define VF610_PAD_PTC30__SAI1_RX_SYNC           0x19C 0x000 ALT1 0x0
+#define VF610_PAD_PTC30__DSPI1_CS2              0x19C 0x000 ALT2 0x0
+#define VF610_PAD_PTC30__SRC_RCON28             0x19C 0x000 ALT3 0x0
+#define VF610_PAD_PTC30__FB_MUXED_BE0_B         0x19C 0x000 ALT4 0x0
+#define VF610_PAD_PTC30__FB_TSIZ0               0x19C 0x000 ALT5 0x0
+#define VF610_PAD_PTC30__ADC0_SE5               0x19C 0x000 ALT6 0x0
+#define VF610_PAD_PTC30__DCU1_B5                0x19C 0x000 ALT7 0x0
+#define VF610_PAD_PTC31__GPIO_104               0x1A0 0x000 ALT0 0x0
+#define VF610_PAD_PTC31__SAI1_TX_SYNC           0x1A0 0x360 ALT1 0x1
+#define VF610_PAD_PTC31__SRC_RCON29             0x1A0 0x000 ALT3 0x0
+#define VF610_PAD_PTC31__ADC1_SE5               0x1A0 0x000 ALT6 0x0
+#define VF610_PAD_PTC31__DCU1_B6                0x1A0 0x000 ALT7 0x0
+#define VF610_PAD_PTE0__GPIO_105                0x1A4 0x000 ALT0 0x0
+#define VF610_PAD_PTE0__DCU0_HSYNC              0x1A4 0x000 ALT1 0x0
+#define VF610_PAD_PTE0__SRC_BMODE1              0x1A4 0x000 ALT2 0x0
+#define VF610_PAD_PTE0__LCD0                    0x1A4 0x000 ALT4 0x0
+#define VF610_PAD_PTE0__DEBUG_OUT29             0x1A4 0x000 ALT7 0x0
+#define VF610_PAD_PTE1__GPIO_106                0x1A8 0x000 ALT0 0x0
+#define VF610_PAD_PTE1__DCU0_VSYNC              0x1A8 0x000 ALT1 0x0
+#define VF610_PAD_PTE1__SRC_BMODE0              0x1A8 0x000 ALT2 0x0
+#define VF610_PAD_PTE1__LCD1                    0x1A8 0x000 ALT4 0x0
+#define VF610_PAD_PTE1__DEBUG_OUT30             0x1A8 0x000 ALT7 0x0
+#define VF610_PAD_PTE2__GPIO_107                0x1AC 0x000 ALT0 0x0
+#define VF610_PAD_PTE2__DCU0_PCLK               0x1AC 0x000 ALT1 0x0
+#define VF610_PAD_PTE2__LCD2                    0x1AC 0x000 ALT4 0x0
+#define VF610_PAD_PTE2__DEBUG_OUT31             0x1AC 0x000 ALT7 0x0
+#define VF610_PAD_PTE3__GPIO_108                0x1B0 0x000 ALT0 0x0
+#define VF610_PAD_PTE3__DCU0_TAG                0x1B0 0x000 ALT1 0x0
+#define VF610_PAD_PTE3__LCD3                    0x1B0 0x000 ALT4 0x0
+#define VF610_PAD_PTE3__DEBUG_OUT32             0x1B0 0x000 ALT7 0x0
+#define VF610_PAD_PTE4__GPIO_109                0x1B4 0x000 ALT0 0x0
+#define VF610_PAD_PTE4__DCU0_DE                 0x1B4 0x000 ALT1 0x0
+#define VF610_PAD_PTE4__LCD4                    0x1B4 0x000 ALT4 0x0
+#define VF610_PAD_PTE4__DEBUG_OUT33             0x1B4 0x000 ALT7 0x0
+#define VF610_PAD_PTE5__GPIO_110                0x1B8 0x000 ALT0 0x0
+#define VF610_PAD_PTE5__DCU0_R0                 0x1B8 0x000 ALT1 0x0
+#define VF610_PAD_PTE5__LCD5                    0x1B8 0x000 ALT4 0x0
+#define VF610_PAD_PTE5__DEBUG_OUT34             0x1B8 0x000 ALT7 0x0
+#define VF610_PAD_PTE6__GPIO_111                0x1BC 0x000 ALT0 0x0
+#define VF610_PAD_PTE6__DCU0_R1                 0x1BC 0x000 ALT1 0x0
+#define VF610_PAD_PTE6__LCD6                    0x1BC 0x000 ALT4 0x0
+#define VF610_PAD_PTE6__DEBUG_OUT35             0x1BC 0x000 ALT7 0x0
+#define VF610_PAD_PTE7__GPIO_112                0x1C0 0x000 ALT0 0x0
+#define VF610_PAD_PTE7__DCU0_R2                 0x1C0 0x000 ALT1 0x0
+#define VF610_PAD_PTE7__SRC_RCON0               0x1C0 0x000 ALT3 0x0
+#define VF610_PAD_PTE7__LCD7                    0x1C0 0x000 ALT4 0x0
+#define VF610_PAD_PTE7__DEBUG_OUT36             0x1C0 0x000 ALT7 0x0
+#define VF610_PAD_PTE8__GPIO_113                0x1C4 0x000 ALT0 0x0
+#define VF610_PAD_PTE8__DCU0_R3                 0x1C4 0x000 ALT1 0x0
+#define VF610_PAD_PTE8__SRC_RCON1               0x1C4 0x000 ALT3 0x0
+#define VF610_PAD_PTE8__LCD8                    0x1C4 0x000 ALT4 0x0
+#define VF610_PAD_PTE8__DEBUG_OUT37             0x1C4 0x000 ALT7 0x0
+#define VF610_PAD_PTE9__GPIO_114                0x1C8 0x000 ALT0 0x0
+#define VF610_PAD_PTE9__DCU0_R4                 0x1C8 0x000 ALT1 0x0
+#define VF610_PAD_PTE9__SRC_RCON2               0x1C8 0x000 ALT3 0x0
+#define VF610_PAD_PTE9__LCD9                    0x1C8 0x000 ALT4 0x0
+#define VF610_PAD_PTE9__DEBUG_OUT38             0x1C8 0x000 ALT7 0x0
+#define VF610_PAD_PTE10__GPIO_115               0x1CC 0x000 ALT0 0x0
+#define VF610_PAD_PTE10__DCU0_R5                0x1CC 0x000 ALT1 0x0
+#define VF610_PAD_PTE10__SRC_RCON3              0x1CC 0x000 ALT3 0x0
+#define VF610_PAD_PTE10__LCD10                  0x1CC 0x000 ALT4 0x0
+#define VF610_PAD_PTE10__DEBUG_OUT39            0x1CC 0x000 ALT7 0x0
+#define VF610_PAD_PTE11__GPIO_116               0x1D0 0x000 ALT0 0x0
+#define VF610_PAD_PTE11__DCU0_R6                0x1D0 0x000 ALT1 0x0
+#define VF610_PAD_PTE11__SRC_RCON4              0x1D0 0x000 ALT3 0x0
+#define VF610_PAD_PTE11__LCD11                  0x1D0 0x000 ALT4 0x0
+#define VF610_PAD_PTE11__DEBUG_OUT40            0x1D0 0x000 ALT7 0x0
+#define VF610_PAD_PTE12__GPIO_117               0x1D4 0x000 ALT0 0x0
+#define VF610_PAD_PTE12__DCU0_R7                0x1D4 0x000 ALT1 0x0
+#define VF610_PAD_PTE12__DSPI1_CS3              0x1D4 0x000 ALT2 0x0
+#define VF610_PAD_PTE12__SRC_RCON5              0x1D4 0x000 ALT3 0x0
+#define VF610_PAD_PTE12__LCD12                  0x1D4 0x000 ALT4 0x0
+#define VF610_PAD_PTE12__LPT_ALT0               0x1D4 0x000 ALT7 0x0
+#define VF610_PAD_PTE13__GPIO_118               0x1D8 0x000 ALT0 0x0
+#define VF610_PAD_PTE13__DCU0_G0                0x1D8 0x000 ALT1 0x0
+#define VF610_PAD_PTE13__LCD13                  0x1D8 0x000 ALT4 0x0
+#define VF610_PAD_PTE13__DEBUG_OUT41            0x1D8 0x000 ALT7 0x0
+#define VF610_PAD_PTE14__GPIO_119               0x1DC 0x000 ALT0 0x0
+#define VF610_PAD_PTE14__DCU0_G1                0x1DC 0x000 ALT1 0x0
+#define VF610_PAD_PTE14__LCD14                  0x1DC 0x000 ALT4 0x0
+#define VF610_PAD_PTE14__DEBUG_OUT42            0x1DC 0x000 ALT7 0x0
+#define VF610_PAD_PTE15__GPIO_120               0x1E0 0x000 ALT0 0x0
+#define VF610_PAD_PTE15__DCU0_G2                0x1E0 0x000 ALT1 0x0
+#define VF610_PAD_PTE15__SRC_RCON6              0x1E0 0x000 ALT3 0x0
+#define VF610_PAD_PTE15__LCD15                  0x1E0 0x000 ALT4 0x0
+#define VF610_PAD_PTE15__DEBUG_OUT43            0x1E0 0x000 ALT7 0x0
+#define VF610_PAD_PTE16__GPIO_121               0x1E4 0x000 ALT0 0x0
+#define VF610_PAD_PTE16__DCU0_G3                0x1E4 0x000 ALT1 0x0
+#define VF610_PAD_PTE16__SRC_RCON7              0x1E4 0x000 ALT3 0x0
+#define VF610_PAD_PTE16__LCD16                  0x1E4 0x000 ALT4 0x0
+#define VF610_PAD_PTE17__GPIO_122               0x1E8 0x000 ALT0 0x0
+#define VF610_PAD_PTE17__DCU0_G4                0x1E8 0x000 ALT1 0x0
+#define VF610_PAD_PTE17__SRC_RCON8              0x1E8 0x000 ALT3 0x0
+#define VF610_PAD_PTE17__LCD17                  0x1E8 0x000 ALT4 0x0
+#define VF610_PAD_PTE18__GPIO_123               0x1EC 0x000 ALT0 0x0
+#define VF610_PAD_PTE18__DCU0_G5                0x1EC 0x000 ALT1 0x0
+#define VF610_PAD_PTE18__SRC_RCON9              0x1EC 0x000 ALT3 0x0
+#define VF610_PAD_PTE18__LCD18                  0x1EC 0x000 ALT4 0x0
+#define VF610_PAD_PTE19__GPIO_124               0x1F0 0x000 ALT0 0x0
+#define VF610_PAD_PTE19__DCU0_G6                0x1F0 0x000 ALT1 0x0
+#define VF610_PAD_PTE19__SRC_RCON10             0x1F0 0x000 ALT3 0x0
+#define VF610_PAD_PTE19__LCD19                  0x1F0 0x000 ALT4 0x0
+#define VF610_PAD_PTE19__I2C0_SCL               0x1F0 0x33C ALT5 0x3
+#define VF610_PAD_PTE20__GPIO_125               0x1F4 0x000 ALT0 0x0
+#define VF610_PAD_PTE20__DCU0_G7                0x1F4 0x000 ALT1 0x0
+#define VF610_PAD_PTE20__SRC_RCON11             0x1F4 0x000 ALT3 0x0
+#define VF610_PAD_PTE20__LCD20                  0x1F4 0x000 ALT4 0x0
+#define VF610_PAD_PTE20__I2C0_SDA               0x1F4 0x340 ALT5 0x3
+#define VF610_PAD_PTE20__EWM_IN                 0x1F4 0x000 ALT7 0x0
+#define VF610_PAD_PTE21__GPIO_126               0x1F8 0x000 ALT0 0x0
+#define VF610_PAD_PTE21__DCU0_B0                0x1F8 0x000 ALT1 0x0
+#define VF610_PAD_PTE21__LCD21                  0x1F8 0x000 ALT4 0x0
+#define VF610_PAD_PTE22__GPIO_127               0x1FC 0x000 ALT0 0x0
+#define VF610_PAD_PTE22__DCU0_B1                0x1FC 0x000 ALT1 0x0
+#define VF610_PAD_PTE22__LCD22                  0x1FC 0x000 ALT4 0x0
+#define VF610_PAD_PTE23__GPIO_128               0x200 0x000 ALT0 0x0
+#define VF610_PAD_PTE23__DCU0_B2                0x200 0x000 ALT1 0x0
+#define VF610_PAD_PTE23__SRC_RCON12             0x200 0x000 ALT3 0x0
+#define VF610_PAD_PTE23__LCD23                  0x200 0x000 ALT4 0x0
+#define VF610_PAD_PTE24__GPIO_129               0x204 0x000 ALT0 0x0
+#define VF610_PAD_PTE24__DCU0_B3                0x204 0x000 ALT1 0x0
+#define VF610_PAD_PTE24__SRC_RCON13             0x204 0x000 ALT3 0x0
+#define VF610_PAD_PTE24__LCD24                  0x204 0x000 ALT4 0x0
+#define VF610_PAD_PTE25__GPIO_130               0x208 0x000 ALT0 0x0
+#define VF610_PAD_PTE25__DCU0_B4                0x208 0x000 ALT1 0x0
+#define VF610_PAD_PTE25__SRC_RCON14             0x208 0x000 ALT3 0x0
+#define VF610_PAD_PTE25__LCD25                  0x208 0x000 ALT4 0x0
+#define VF610_PAD_PTE26__GPIO_131               0x20C 0x000 ALT0 0x0
+#define VF610_PAD_PTE26__DCU0_B5                0x20C 0x000 ALT1 0x0
+#define VF610_PAD_PTE26__SRC_RCON15             0x20C 0x000 ALT3 0x0
+#define VF610_PAD_PTE26__LCD26                  0x20C 0x000 ALT4 0x0
+#define VF610_PAD_PTE27__GPIO_132               0x210 0x000 ALT0 0x0
+#define VF610_PAD_PTE27__DCU0_B6                0x210 0x000 ALT1 0x0
+#define VF610_PAD_PTE27__SRC_RCON16             0x210 0x000 ALT3 0x0
+#define VF610_PAD_PTE27__LCD27                  0x210 0x000 ALT4 0x0
+#define VF610_PAD_PTE27__I2C1_SCL               0x210 0x344 ALT5 0x3
+#define VF610_PAD_PTE28__GPIO_133               0x214 0x000 ALT0 0x0
+#define VF610_PAD_PTE28__DCU0_B7                0x214 0x000 ALT1 0x0
+#define VF610_PAD_PTE28__SRC_RCON17             0x214 0x000 ALT3 0x0
+#define VF610_PAD_PTE28__LCD28                  0x214 0x000 ALT4 0x0
+#define VF610_PAD_PTE28__I2C1_SDA               0x214 0x348 ALT5 0x3
+#define VF610_PAD_PTE28__EWM_OUT                0x214 0x000 ALT7 0x0
+#define VF610_PAD_PTA7__GPIO_134                0x218 0x000 ALT0 0x0
+#define VF610_PAD_PTA7__VIU_PIX_CLK             0x218 0x3AC ALT1 0x1
+#endif
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts
new file mode 100644
index 000000000000..b3905f5bcaf9
--- /dev/null
+++ b/arch/arm/boot/dts/vf610-twr.dts
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+/dts-v1/;
+#include "vf610.dtsi"
+/ {
+        model = "VF610 Tower Board";
+        compatible = "fsl,vf610-twr", "fsl,vf610";
+        chosen {
+                bootargs = "console=ttyLP1,115200";
+        };
+        memory {
+                reg = <0x80000000 0x8000000>;
+        };
+        clocks {
+                audio_ext {
+                        compatible = "fixed-clock";
+                        clock-frequency = <24576000>;
+                };
+                enet_ext {
+                        compatible = "fixed-clock";
+                        clock-frequency = <50000000>;
+                };
+        };
+};
+&fec0 {
+        phy-mode = "rmii";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec0_1>;
+        status = "okay";
+};
+&fec1 {
+        phy-mode = "rmii";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec1_1>;
+        status = "okay";
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1_1>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi
new file mode 100644
index 000000000000..67d929cf9804
--- /dev/null
+++ b/arch/arm/boot/dts/vf610.dtsi
@@ -0,0 +1,464 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include "skeleton.dtsi"
+#include "vf610-pinfunc.h"
+#include <dt-bindings/clock/vf610-clock.h>
+/ {
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &uart2;
+                serial3 = &uart3;
+                serial4 = &uart4;
+                serial5 = &uart5;
+                gpio0 = &gpio1;
+                gpio1 = &gpio2;
+                gpio2 = &gpio3;
+                gpio3 = &gpio4;
+                gpio4 = &gpio5;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        compatible = "arm,cortex-a5";
+                        device_type = "cpu";
+                        reg = <0x0>;
+                        next-level-cache = <&L2>;
+                };
+        };
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                sxosc {
+                        compatible = "fixed-clock";
+                        clock-frequency = <32768>;
+                };
+                fxosc {
+                        compatible = "fixed-clock";
+                        clock-frequency = <24000000>;
+                };
+        };
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                interrupt-parent = <&intc>;
+                ranges;
+                aips0: aips-bus@40000000 {
+                        compatible = "fsl,aips-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        interrupt-parent = <&intc>;
+                        reg = <0x40000000 0x70000>;
+                        ranges;
+                        intc: interrupt-controller@40002000 {
+                                compatible = "arm,cortex-a9-gic";
+                                #interrupt-cells = <3>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                interrupt-controller;
+                                reg = <0x40003000 0x1000>,
+                                      <0x40002100 0x100>;
+                        };
+                        L2: l2-cache@40006000 {
+                                compatible = "arm,pl310-cache";
+                                reg = <0x40006000 0x1000>;
+                                cache-unified;
+                                cache-level = <2>;
+                                arm,data-latency = <1 1 1>;
+                                arm,tag-latency = <2 2 2>;
+                        };
+                        uart0: serial@40027000 {
+                                compatible = "fsl,vf610-lpuart";
+                                reg = <0x40027000 0x1000>;
+                                interrupts = <0 61 0x00>;
+                                clocks = <&clks VF610_CLK_UART0>;
+                                clock-names = "ipg";
+                                status = "disabled";
+                        };
+                        uart1: serial@40028000 {
+                                compatible = "fsl,vf610-lpuart";
+                                reg = <0x40028000 0x1000>;
+                                interrupts = <0 62 0x04>;
+                                clocks = <&clks VF610_CLK_UART1>;
+                                clock-names = "ipg";
+                                status = "disabled";
+                        };
+                        uart2: serial@40029000 {
+                                compatible = "fsl,vf610-lpuart";
+                                reg = <0x40029000 0x1000>;
+                                interrupts = <0 63 0x04>;
+                                clocks = <&clks VF610_CLK_UART2>;
+                                clock-names = "ipg";
+                                status = "disabled";
+                        };
+                        uart3: serial@4002a000 {
+                                compatible = "fsl,vf610-lpuart";
+                                reg = <0x4002a000 0x1000>;
+                                interrupts = <0 64 0x04>;
+                                clocks = <&clks VF610_CLK_UART3>;
+                                clock-names = "ipg";
+                                status = "disabled";
+                        };
+                        sai2: sai@40031000 {
+                                compatible = "fsl,vf610-sai";
+                                reg = <0x40031000 0x1000>;
+                                interrupts = <0 86 0x04>;
+                                clocks = <&clks VF610_CLK_SAI2>;
+                                clock-names = "sai";
+                                status = "disabled";
+                        };
+                        pit: pit@40037000 {
+                                compatible = "fsl,vf610-pit";
+                                reg = <0x40037000 0x1000>;
+                                interrupts = <0 39 0x04>;
+                                clocks = <&clks VF610_CLK_PIT>;
+                                clock-names = "pit";
+                        };
+                        wdog@4003e000 {
+                                compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
+                                reg = <0x4003e000 0x1000>;
+                                clocks = <&clks VF610_CLK_WDT>;
+                                clock-names = "wdog";
+                        };
+                        qspi0: quadspi@40044000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,vf610-qspi";
+                                reg = <0x40044000 0x1000>;
+                                interrupts = <0 24 0x04>;
+                                clocks = <&clks VF610_CLK_QSPI0_EN>,
+                                        <&clks VF610_CLK_QSPI0>;
+                                clock-names = "qspi_en", "qspi";
+                                status = "disabled";
+                        };
+                        iomuxc: iomuxc@40048000 {
+                                compatible = "fsl,vf610-iomuxc";
+                                reg = <0x40048000 0x1000>;
+                                #gpio-range-cells = <3>;
+                                /* functions and groups pins */
+                                dcu0 {
+                                        pinctrl_dcu0_1: dcu0grp_1 {
+                                                fsl,pins = <
+                                                VF610_PAD_PTB8__GPIO_30         0x42
+                                                VF610_PAD_PTE0__DCU0_HSYNC      0x42
+                                                VF610_PAD_PTE1__DCU0_VSYNC      0x42
+                                                VF610_PAD_PTE2__DCU0_PCLK       0x42
+                                                VF610_PAD_PTE4__DCU0_DE         0x42
+                                                VF610_PAD_PTE5__DCU0_R0         0x42
+                                                VF610_PAD_PTE6__DCU0_R1         0x42
+                                                VF610_PAD_PTE7__DCU0_R2         0x42
+                                                VF610_PAD_PTE8__DCU0_R3         0x42
+                                                VF610_PAD_PTE9__DCU0_R4         0x42
+                                                VF610_PAD_PTE10__DCU0_R5        0x42
+                                                VF610_PAD_PTE11__DCU0_R6        0x42
+                                                VF610_PAD_PTE12__DCU0_R7        0x42
+                                                VF610_PAD_PTE13__DCU0_G0        0x42
+                                                VF610_PAD_PTE14__DCU0_G1        0x42
+                                                VF610_PAD_PTE15__DCU0_G2        0x42
+                                                VF610_PAD_PTE16__DCU0_G3        0x42
+                                                VF610_PAD_PTE17__DCU0_G4        0x42
+                                                VF610_PAD_PTE18__DCU0_G5        0x42
+                                                VF610_PAD_PTE19__DCU0_G6        0x42
+                                                VF610_PAD_PTE20__DCU0_G7        0x42
+                                                VF610_PAD_PTE21__DCU0_B0        0x42
+                                                VF610_PAD_PTE22__DCU0_B1        0x42
+                                                VF610_PAD_PTE23__DCU0_B2        0x42
+                                                VF610_PAD_PTE24__DCU0_B3        0x42
+                                                VF610_PAD_PTE25__DCU0_B4        0x42
+                                                VF610_PAD_PTE26__DCU0_B5        0x42
+                                                VF610_PAD_PTE27__DCU0_B6        0x42
+                                                VF610_PAD_PTE28__DCU0_B7        0x42
+                                                >;
+                                        };
+                                };
+                                dspi0 {
+                                        pinctrl_dspi0_1: dspi0grp_1 {
+                                                fsl,pins = <
+                                                VF610_PAD_PTB19__DSPI0_CS0      0x1182
+                                                VF610_PAD_PTB20__DSPI0_SIN      0x1181
+                                                VF610_PAD_PTB21__DSPI0_SOUT     0x1182
+                                                VF610_PAD_PTB22__DSPI0_SCK      0x1182
+                                                >;
+                                        };
+                                };
+                                esdhc1 {
+                                        pinctrl_esdhc1_1: esdhc1grp_1 {
+                                                fsl,pins = <
+                                                VF610_PAD_PTA24__ESDHC1_CLK     0x31ef
+                                                VF610_PAD_PTA25__ESDHC1_CMD     0x31ef
+                                                VF610_PAD_PTA26__ESDHC1_DAT0    0x31ef
+                                                VF610_PAD_PTA27__ESDHC1_DAT1    0x31ef
+                                                VF610_PAD_PTA28__ESDHC1_DATA2   0x31ef
+                                                VF610_PAD_PTA29__ESDHC1_DAT3    0x31ef
+                                                VF610_PAD_PTA7__GPIO_134        0x219d
+                                                >;
+                                        };
+                                };
+                                fec0 {
+                                        pinctrl_fec0_1: fec0grp_1 {
+                                                fsl,pins = <
+                                                VF610_PAD_PTA6__RMII_CLKIN      0x30d1
+                                                VF610_PAD_PTC0__ENET_RMII0_MDC  0x30d3
+                                                VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d1
+                                                VF610_PAD_PTC2__ENET_RMII0_CRS  0x30d1
+                                                VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1
+                                                VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1
+                                                VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1
+                                                VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2
+                                                VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2
+                                                VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2
+                                                >;
+                                        };
+                                };
+                                fec1 {
+                                        pinctrl_fec1_1: fec1grp_1 {
+                                                fsl,pins = <
+                                                VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
+                                                VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
+                                                VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
+                                                VF610_PAD_PTC12__ENET_RMII_RXD1         0x30d1
+                                                VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
+                                                VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
+                                                VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
+                                                VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
+                                                VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
+                                                >;
+                                        };
+                                };
+                                i2c0 {
+                                        pinctrl_i2c0_1: i2c0grp_1 {
+                                                fsl,pins = <
+                                                VF610_PAD_PTB14__I2C0_SCL       0x30d3
+                                                VF610_PAD_PTB15__I2C0_SDA       0x30d3
+                                                >;
+                                        };
+                                };
+                                pwm0 {
+                                        pinctrl_pwm0_1: pwm0grp_1 {
+                                                fsl,pins = <
+                                                VF610_PAD_PTB0__FTM0_CH0        0x1582
+                                                VF610_PAD_PTB1__FTM0_CH1        0x1582
+                                                VF610_PAD_PTB2__FTM0_CH2        0x1582
+                                                VF610_PAD_PTB3__FTM0_CH3        0x1582
+                                                VF610_PAD_PTB6__FTM0_CH6        0x1582
+                                                VF610_PAD_PTB7__FTM0_CH7        0x1582
+                                                >;
+                                        };
+                                };
+                                qspi0 {
+                                        pinctrl_qspi0_1: qspi0grp_1 {
+                                                fsl,pins = <
+                                                VF610_PAD_PTD0__QSPI0_A_QSCK    0x307b
+                                                VF610_PAD_PTD1__QSPI0_A_CS0     0x307f
+                                                VF610_PAD_PTD2__QSPI0_A_DATA3   0x3073
+                                                VF610_PAD_PTD3__QSPI0_A_DATA2   0x3073
+                                                VF610_PAD_PTD4__QSPI0_A_DATA1   0x3073
+                                                VF610_PAD_PTD5__QSPI0_A_DATA0   0x307b
+                                                VF610_PAD_PTD7__QSPI0_B_QSCK    0x307b
+                                                VF610_PAD_PTD8__QSPI0_B_CS0     0x307f
+                                                VF610_PAD_PTD9__QSPI0_B_DATA3   0x3073
+                                                VF610_PAD_PTD10__QSPI0_B_DATA2  0x3073
+                                                VF610_PAD_PTD11__QSPI0_B_DATA1  0x3073
+                                                VF610_PAD_PTD12__QSPI0_B_DATA0  0x307b
+                                                >;
+                                        };
+                                };
+                                sai2 {
+                                        pinctrl_sai2_1: sai2grp_1 {
+                                                fsl,pins = <
+                                                VF610_PAD_PTA16__SAI2_TX_BCLK   0x02ed
+                                                VF610_PAD_PTA18__SAI2_TX_DATA   0x02ee
+                                                VF610_PAD_PTA19__SAI2_TX_SYNC   0x02ed
+                                                VF610_PAD_PTA21__SAI2_RX_BCLK   0x02ed
+                                                VF610_PAD_PTA22__SAI2_RX_DATA   0x02ed
+                                                VF610_PAD_PTA23__SAI2_RX_SYNC   0x02ed
+                                                VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x02ed
+                                                >;
+                                        };
+                                };
+                                uart1 {
+                                        pinctrl_uart1_1: uart1grp_1 {
+                                                fsl,pins = <
+                                                VF610_PAD_PTB4__UART1_TX        0x21a2
+                                                VF610_PAD_PTB5__UART1_RX        0x21a1
+                                                >;
+                                        };
+                                };
+                                usbvbus {
+                                        pinctrl_usbvbus_1: usbvbusgrp_1 {
+                                                fsl,pins = <
+                                                VF610_PAD_PTA24__USB1_VBUS_EN   0x219c
+                                                VF610_PAD_PTA16__USB0_VBUS_EN   0x219c
+                                                >;
+                                        };
+                                };
+                        };
+                        gpio1: gpio@40049000 {
+                                compatible = "fsl,vf610-gpio";
+                                reg = <0x40049000 0x1000 0x400ff000 0x40>;
+                                interrupts = <0 107 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                gpio-ranges = <&iomuxc 0 0 32>;
+                        };
+                        gpio2: gpio@4004a000 {
+                                compatible = "fsl,vf610-gpio";
+                                reg = <0x4004a000 0x1000 0x400ff040 0x40>;
+                                interrupts = <0 108 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                gpio-ranges = <&iomuxc 0 32 32>;
+                        };
+                        gpio3: gpio@4004b000 {
+                                compatible = "fsl,vf610-gpio";
+                                reg = <0x4004b000 0x1000 0x400ff080 0x40>;
+                                interrupts = <0 109 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                gpio-ranges = <&iomuxc 0 64 32>;
+                        };
+                        gpio4: gpio@4004c000 {
+                                compatible = "fsl,vf610-gpio";
+                                reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
+                                interrupts = <0 110 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                gpio-ranges = <&iomuxc 0 96 32>;
+                        };
+                        gpio5: gpio@4004d000 {
+                                compatible = "fsl,vf610-gpio";
+                                reg = <0x4004d000 0x1000 0x400ff100 0x40>;
+                                interrupts = <0 111 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                gpio-ranges = <&iomuxc 0 128 7>;
+                        };
+                        anatop@40050000 {
+                                compatible = "fsl,vf610-anatop";
+                                reg = <0x40050000 0x1000>;
+                        };
+                        i2c0: i2c@40066000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,vf610-i2c";
+                                reg = <0x40066000 0x1000>;
+                                interrupts =<0 71 0x04>;
+                                clocks = <&clks VF610_CLK_I2C0>;
+                                clock-names = "ipg";
+                                status = "disabled";
+                        };
+                        clks: ccm@4006b000 {
+                                compatible = "fsl,vf610-ccm";
+                                reg = <0x4006b000 0x1000>;
+                                #clock-cells = <1>;
+                        };
+                };
+                aips1: aips-bus@40080000 {
+                        compatible = "fsl,aips-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x40080000 0x80000>;
+                        ranges;
+                        uart4: serial@400a9000 {
+                                compatible = "fsl,vf610-lpuart";
+                                reg = <0x400a9000 0x1000>;
+                                interrupts = <0 65 0x04>;
+                                clocks = <&clks VF610_CLK_UART4>;
+                                clock-names = "ipg";
+                                status = "disabled";
+                        };
+                        uart5: serial@400aa000 {
+                                compatible = "fsl,vf610-lpuart";
+                                reg = <0x400aa000 0x1000>;
+                                interrupts = <0 66 0x04>;
+                                clocks = <&clks VF610_CLK_UART5>;
+                                clock-names = "ipg";
+                                status = "disabled";
+                        };
+                        fec0: ethernet@400d0000 {
+                                compatible = "fsl,mvf600-fec";
+                                reg = <0x400d0000 0x1000>;
+                                interrupts = <0 78 0x04>;
+                                clocks = <&clks VF610_CLK_ENET0>,
+                                        <&clks VF610_CLK_ENET0>,
+                                        <&clks VF610_CLK_ENET>;
+                                clock-names = "ipg", "ahb", "ptp";
+                                status = "disabled";
+                        };
+                        fec1: ethernet@400d1000 {
+                                compatible = "fsl,mvf600-fec";
+                                reg = <0x400d1000 0x1000>;
+                                interrupts = <0 79 0x04>;
+                                clocks = <&clks VF610_CLK_ENET1>,
+                                        <&clks VF610_CLK_ENET1>,
+                                        <&clks VF610_CLK_ENET>;
+                                clock-names = "ipg", "ahb", "ptp";
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/vt8500-bv07.dts b/arch/arm/boot/dts/vt8500-bv07.dts
index 877b33afa7ed..87f33310e2bc 100644
--- a/arch/arm/boot/dts/vt8500-bv07.dts
+++ b/arch/arm/boot/dts/vt8500-bv07.dts
@@ -30,3 +30,7 @@
                };
        };
 };
+&uart0 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/vt8500.dtsi b/arch/arm/boot/dts/vt8500.dtsi
index 4a4b96f6827e..51d0e912c8f5 100644
--- a/arch/arm/boot/dts/vt8500.dtsi
+++ b/arch/arm/boot/dts/vt8500.dtsi
@@ -11,6 +11,23 @@
 / {
        compatible = "via,vt8500";
+        cpus {
+                #address-cells = <0>;
+                #size-cells = <0>;
+                cpu {
+                        device_type = "cpu";
+                        compatible = "arm,arm926ej-s";
+                };
+        };
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &uart2;
+                serial3 = &uart3;
+        };
        soc {
                #address-cells = <1>;
                #size-cells = <1>;
@@ -111,32 +128,36 @@
                        reg = <0xd8050400 0x100>;
                };
-                uart@d8200000 {
+                uart0: serial@d8200000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd8200000 0x1040>;
                        interrupts = <32>;
                        clocks = <&clkuart0>;
+                        status = "disabled";
                };
-                uart@d82b0000 {
+                uart1: serial@d82b0000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd82b0000 0x1040>;
                        interrupts = <33>;
                        clocks = <&clkuart1>;
+                        status = "disabled";
                };
-                uart@d8210000 {
+                uart2: serial@d8210000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd8210000 0x1040>;
                        interrupts = <47>;
                        clocks = <&clkuart2>;
+                        status = "disabled";
                };
-                uart@d82c0000 {
+                uart3: serial@d82c0000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd82c0000 0x1040>;
                        interrupts = <50>;
                        clocks = <&clkuart3>;
+                        status = "disabled";
                };
                rtc@d8100000 {
diff --git a/arch/arm/boot/dts/wm8505-ref.dts b/arch/arm/boot/dts/wm8505-ref.dts
index edd2cec3d37f..e3e6b9eb09d0 100644
--- a/arch/arm/boot/dts/wm8505-ref.dts
+++ b/arch/arm/boot/dts/wm8505-ref.dts
@@ -30,3 +30,7 @@
                };
        };
 };
+&uart0 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi
index b2bf359e852f..a1a854b8a454 100644
--- a/arch/arm/boot/dts/wm8505.dtsi
+++ b/arch/arm/boot/dts/wm8505.dtsi
@@ -12,11 +12,24 @@
        compatible = "wm,wm8505";
        cpus {
-                cpu@0 {
+                #address-cells = <0>;
-                        compatible = "arm,arm926ejs";
+                #size-cells = <0>;
+                cpu {
+                        device_type = "cpu";
+                        compatible = "arm,arm926ej-s";
                };
        };
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &uart2;
+                serial3 = &uart3;
+                serial4 = &uart4;
+                serial5 = &uart5;
+        };
        soc {
                #address-cells = <1>;
                #size-cells = <1>;
@@ -68,6 +81,13 @@
                                        clock-frequency = <25000000>;
                                };
+                                plla: plla {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x200>;
+                                };
                                pllb: pllb {
                                        #clock-cells = <0>;
                                        compatible = "via,vt8500-pll-clock";
@@ -75,6 +95,48 @@
                                        reg = <0x204>;
                                };
+                                pllc: pllc {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x208>;
+                                };
+                                plld: plld {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x20c>;
+                                };
+                                clkarm: arm {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&plla>;
+                                        divisor-reg = <0x300>;
+                                };
+                                clkahb: ahb {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x304>;
+                                };
+                                clkapb: apb {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x350>;
+                                };
+                                clkddr: ddr {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&plld>;
+                                        divisor-reg = <0x310>;
+                                };
                                clkuart0: uart0 {
                                        #clock-cells = <0>;
                                        compatible = "via,vt8500-device-clock";
@@ -163,46 +225,52 @@
                        reg = <0xd8050400 0x100>;
                };
-                uart@d8200000 {
+                uart0: serial@d8200000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd8200000 0x1040>;
                        interrupts = <32>;
                        clocks = <&clkuart0>;
+                        status = "disabled";
                };
-                uart@d82b0000 {
+                uart1: serial@d82b0000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd82b0000 0x1040>;
                        interrupts = <33>;
                        clocks = <&clkuart1>;
+                        status = "disabled";
                };
-                uart@d8210000 {
+                uart2: serial@d8210000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd8210000 0x1040>;
                        interrupts = <47>;
                        clocks = <&clkuart2>;
+                        status = "disabled";
                };
-                uart@d82c0000 {
+                uart3: serial@d82c0000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd82c0000 0x1040>;
                        interrupts = <50>;
                        clocks = <&clkuart3>;
+                        status = "disabled";
                };
-                uart@d8370000 {
+                uart4: serial@d8370000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd8370000 0x1040>;
                        interrupts = <31>;
                        clocks = <&clkuart4>;
+                        status = "disabled";
                };
-                uart@d8380000 {
+                uart5: serial@d8380000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd8380000 0x1040>;
                        interrupts = <30>;
                        clocks = <&clkuart5>;
+                        status = "disabled";
                };
                rtc@d8100000 {
diff --git a/arch/arm/boot/dts/wm8650-mid.dts b/arch/arm/boot/dts/wm8650-mid.dts
index 61671a0d9ede..dd0d1b602388 100644
--- a/arch/arm/boot/dts/wm8650-mid.dts
+++ b/arch/arm/boot/dts/wm8650-mid.dts
@@ -32,3 +32,6 @@
        };
 };
+&uart0 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi
index dd8464eeb40d..7525982262ac 100644
--- a/arch/arm/boot/dts/wm8650.dtsi
+++ b/arch/arm/boot/dts/wm8650.dtsi
@@ -11,6 +11,21 @@
 / {
        compatible = "wm,wm8650";
+        cpus {
+                #address-cells = <0>;
+                #size-cells = <0>;
+                cpu {
+                        device_type = "cpu";
+                        compatible = "arm,arm926ej-s";
+                };
+        };
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+        };
        soc {
                #address-cells = <1>;
                #size-cells = <1>;
@@ -77,6 +92,55 @@
                                        reg = <0x204>;
                                };
+                                pllc: pllc {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8650-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x208>;
+                                };
+                                plld: plld {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8650-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x20c>;
+                                };
+                                plle: plle {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8650-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x210>;
+                                };
+                                clkarm: arm {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&plla>;
+                                        divisor-reg = <0x300>;
+                                };
+                                clkahb: ahb {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x304>;
+                                };
+                                clkapb: apb {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x320>;
+                                };
+                                clkddr: ddr {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&plld>;
+                                        divisor-reg = <0x310>;
+                                };
                                clkuart0: uart0 {
                                        #clock-cells = <0>;
                                        compatible = "via,vt8500-device-clock";
@@ -93,14 +157,7 @@
                                        enable-bit = <2>;
                                };
-                                arm: arm {
+                                clksdhc: sdhc {
-                                        #clock-cells = <0>;
-                                        compatible = "via,vt8500-device-clock";
-                                        clocks = <&plla>;
-                                        divisor-reg = <0x300>;
-                                };
-                                sdhc: sdhc {
                                        #clock-cells = <0>;
                                        compatible = "via,vt8500-device-clock";
                                        clocks = <&pllb>;
@@ -140,18 +197,20 @@
                        reg = <0xd8050400 0x100>;
                };
-                uart@d8200000 {
+                uart0: serial@d8200000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd8200000 0x1040>;
                        interrupts = <32>;
                        clocks = <&clkuart0>;
+                        status = "disabled";
                };
-                uart@d82b0000 {
+                uart1: serial@d82b0000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd82b0000 0x1040>;
                        interrupts = <33>;
                        clocks = <&clkuart1>;
+                        status = "disabled";
                };
                rtc@d8100000 {
diff --git a/arch/arm/boot/dts/wm8750-apc8750.dts b/arch/arm/boot/dts/wm8750-apc8750.dts
new file mode 100644
index 000000000000..37e4a408bf39
--- /dev/null
+++ b/arch/arm/boot/dts/wm8750-apc8750.dts
@@ -0,0 +1,30 @@
+/*
+ * wm8750-apc8750.dts
+ *  - Device tree file for VIA APC8750
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+/dts-v1/;
+/include/ "wm8750.dtsi"
+/ {
+        model = "VIA APC8750";
+};
+&pinctrl {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c>;
+        i2c: i2c {
+                wm,pins = <168 169 170 171>;
+                wm,function = <2>;      /* alt */
+                wm,pull = <2>;  /* pull-up */
+        };
+};
+&uart0 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/wm8750.dtsi b/arch/arm/boot/dts/wm8750.dtsi
new file mode 100644
index 000000000000..557a9c2ace49
--- /dev/null
+++ b/arch/arm/boot/dts/wm8750.dtsi
@@ -0,0 +1,347 @@
+/*
+ * wm8750.dtsi - Device tree file for Wondermedia WM8750 SoC
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+/include/ "skeleton.dtsi"
+/ {
+        compatible = "wm,wm8750";
+        cpus {
+                #address-cells = <0>;
+                #size-cells = <0>;
+                cpu {
+                        device_type = "cpu";
+                        compatible = "arm,arm1176ej-s";
+                };
+        };
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &uart2;
+                serial3 = &uart3;
+                serial4 = &uart4;
+                serial5 = &uart5;
+                i2c0 = &i2c_0;
+                i2c1 = &i2c_1;
+        };
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges;
+                interrupt-parent = <&intc0>;
+                intc0: interrupt-controller@d8140000 {
+                        compatible = "via,vt8500-intc";
+                        interrupt-controller;
+                        reg = <0xd8140000 0x10000>;
+                        #interrupt-cells = <1>;
+                };
+                /* Secondary IC cascaded to intc0 */
+                intc1: interrupt-controller@d8150000 {
+                        compatible = "via,vt8500-intc";
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        reg = <0xD8150000 0x10000>;
+                        interrupts = <56 57 58 59 60 61 62 63>;
+                };
+                pinctrl: pinctrl@d8110000 {
+                        compatible = "wm,wm8750-pinctrl";
+                        reg = <0xd8110000 0x10000>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+                pmc@d8130000 {
+                        compatible = "via,vt8500-pmc";
+                        reg = <0xd8130000 0x1000>;
+                        clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                ref24: ref24M {
+                                        #clock-cells = <0>;
+                                        compatible = "fixed-clock";
+                                        clock-frequency = <24000000>;
+                                };
+                                ref25: ref25M {
+                                        #clock-cells = <0>;
+                                        compatible = "fixed-clock";
+                                        clock-frequency = <25000000>;
+                                };
+                                plla: plla {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8750-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x200>;
+                                };
+                                pllb: pllb {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8750-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x204>;
+                                };
+                                pllc: pllc {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8750-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x208>;
+                                };
+                                plld: plld {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8750-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x20C>;
+                                };
+                                plle: plle {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8750-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x210>;
+                                };
+                                clkarm: arm {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&plla>;
+                                        divisor-reg = <0x300>;
+                                };
+                                clkahb: ahb {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x304>;
+                                };
+                                clkapb: apb {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x320>;
+                                };
+                                clkddr: ddr {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&plld>;
+                                        divisor-reg = <0x310>;
+                                };
+                                clkuart0: uart0 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x254>;
+                                        enable-bit = <24>;
+                                };
+                                clkuart1: uart1 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x254>;
+                                        enable-bit = <25>;
+                                };
+                                clkuart2: uart2 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x254>;
+                                        enable-bit = <26>;
+                                };
+                                clkuart3: uart3 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x254>;
+                                        enable-bit = <27>;
+                                };
+                                clkuart4: uart4 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x254>;
+                                        enable-bit = <28>;
+                                };
+                                clkuart5: uart5 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x254>;
+                                        enable-bit = <29>;
+                                };
+                                clkpwm: pwm {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x350>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <17>;
+                                };
+                                clksdhc: sdhc {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x330>;
+                                        divisor-mask = <0x3f>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <0>;
+                                };
+                                clki2c0: i2c0clk {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x3A0>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <8>;
+                                };
+                                clki2c1: i2c1clk {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x3A4>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <9>;
+                                };
+                        };
+                };
+                pwm: pwm@d8220000 {
+                        #pwm-cells = <3>;
+                        compatible = "via,vt8500-pwm";
+                        reg = <0xd8220000 0x100>;
+                        clocks = <&clkpwm>;
+                };
+                timer@d8130100 {
+                        compatible = "via,vt8500-timer";
+                        reg = <0xd8130100 0x28>;
+                        interrupts = <36>;
+                };
+                ehci@d8007900 {
+                        compatible = "via,vt8500-ehci";
+                        reg = <0xd8007900 0x200>;
+                        interrupts = <26>;
+                };
+                uhci@d8007b00 {
+                        compatible = "platform-uhci";
+                        reg = <0xd8007b00 0x200>;
+                        interrupts = <26>;
+                };
+                uhci@d8008d00 {
+                        compatible = "platform-uhci";
+                        reg = <0xd8008d00 0x200>;
+                        interrupts = <26>;
+                };
+                uart0: serial@d8200000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8200000 0x1040>;
+                        interrupts = <32>;
+                        clocks = <&clkuart0>;
+                        status = "disabled";
+                };
+                uart1: serial@d82b0000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd82b0000 0x1040>;
+                        interrupts = <33>;
+                        clocks = <&clkuart1>;
+                        status = "disabled";
+                };
+                uart2: serial@d8210000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8210000 0x1040>;
+                        interrupts = <47>;
+                        clocks = <&clkuart2>;
+                        status = "disabled";
+                };
+                uart3: serial@d82c0000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd82c0000 0x1040>;
+                        interrupts = <50>;
+                        clocks = <&clkuart3>;
+                        status = "disabled";
+                };
+                uart4: serial@d8370000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8370000 0x1040>;
+                        interrupts = <30>;
+                        clocks = <&clkuart4>;
+                        status = "disabled";
+                };
+                uart5: serial@d8380000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8380000 0x1040>;
+                        interrupts = <43>;
+                        clocks = <&clkuart5>;
+                        status = "disabled";
+                };
+                rtc@d8100000 {
+                        compatible = "via,vt8500-rtc";
+                        reg = <0xd8100000 0x10000>;
+                        interrupts = <48>;
+                };
+                sdhc@d800a000 {
+                        compatible = "wm,wm8505-sdhc";
+                        reg = <0xd800a000 0x1000>;
+                        interrupts = <20 21>;
+                        clocks = <&clksdhc>;
+                        bus-width = <4>;
+                        sdon-inverted;
+                };
+                i2c_0: i2c@d8280000 {
+                        compatible = "wm,wm8505-i2c";
+                        reg = <0xd8280000 0x1000>;
+                        interrupts = <19>;
+                        clocks = <&clki2c0>;
+                        clock-frequency = <400000>;
+                };
+                i2c_1: i2c@d8320000 {
+                        compatible = "wm,wm8505-i2c";
+                        reg = <0xd8320000 0x1000>;
+                        interrupts = <18>;
+                        clocks = <&clki2c1>;
+                        clock-frequency = <400000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/wm8850-w70v2.dts b/arch/arm/boot/dts/wm8850-w70v2.dts
index 32d22532cd6c..90e913fb64be 100644
--- a/arch/arm/boot/dts/wm8850-w70v2.dts
+++ b/arch/arm/boot/dts/wm8850-w70v2.dts
@@ -41,3 +41,7 @@
                };
        };
 };
+&uart0 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/wm8850.dtsi b/arch/arm/boot/dts/wm8850.dtsi
index fc790d0aee66..d98386dd2882 100644
--- a/arch/arm/boot/dts/wm8850.dtsi
+++ b/arch/arm/boot/dts/wm8850.dtsi
@@ -11,6 +11,17 @@
 / {
        compatible = "wm,wm8850";
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0x0>;
+                };
+        };
        aliases {
                serial0 = &uart0;
                serial1 = &uart1;
@@ -72,18 +83,81 @@
                                plla: plla {
                                        #clock-cells = <0>;
-                                        compatible = "wm,wm8750-pll-clock";
+                                        compatible = "wm,wm8850-pll-clock";
-                                        clocks = <&ref25>;
+                                        clocks = <&ref24>;
                                        reg = <0x200>;
                                };
                                pllb: pllb {
                                        #clock-cells = <0>;
-                                        compatible = "wm,wm8750-pll-clock";
+                                        compatible = "wm,wm8850-pll-clock";
-                                        clocks = <&ref25>;
+                                        clocks = <&ref24>;
                                        reg = <0x204>;
                                };
+                                pllc: pllc {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8850-pll-clock";
+                                        clocks = <&ref24>;
+                                        reg = <0x208>;
+                                };
+                                plld: plld {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8850-pll-clock";
+                                        clocks = <&ref24>;
+                                        reg = <0x20c>;
+                                };
+                                plle: plle {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8850-pll-clock";
+                                        clocks = <&ref24>;
+                                        reg = <0x210>;
+                                };
+                                pllf: pllf {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8850-pll-clock";
+                                        clocks = <&ref24>;
+                                        reg = <0x214>;
+                                };
+                                pllg: pllg {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8850-pll-clock";
+                                        clocks = <&ref24>;
+                                        reg = <0x218>;
+                                };
+                                clkarm: arm {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&plla>;
+                                        divisor-reg = <0x300>;
+                                };
+                                clkahb: ahb {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x304>;
+                                };
+                                clkapb: apb {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x320>;
+                                };
+                                clkddr: ddr {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&plld>;
+                                        divisor-reg = <0x310>;
+                                };
                                clkuart0: uart0 {
                                        #clock-cells = <0>;
                                        compatible = "via,vt8500-device-clock";
@@ -178,32 +252,36 @@
                        interrupts = <26>;
                };
-                uart0: uart@d8200000 {
+                uart0: serial@d8200000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd8200000 0x1040>;
                        interrupts = <32>;
                        clocks = <&clkuart0>;
+                        status = "disabled";
                };
-                uart1: uart@d82b0000 {
+                uart1: serial@d82b0000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd82b0000 0x1040>;
                        interrupts = <33>;
                        clocks = <&clkuart1>;
+                        status = "disabled";
                };
-                uart2: uart@d8210000 {
+                uart2: serial@d8210000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd8210000 0x1040>;
                        interrupts = <47>;
                        clocks = <&clkuart2>;
+                        status = "disabled";
                };
-                uart3: uart@d82c0000 {
+                uart3: serial@d82c0000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd82c0000 0x1040>;
                        interrupts = <50>;
                        clocks = <&clkuart3>;
+                        status = "disabled";
                };
                rtc@d8100000 {
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 14fb2e609bab..6f54a64850eb 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -49,16 +49,20 @@
                uart0: uart@e0000000 {
                        compatible = "xlnx,xuartps";
+                        status = "disabled";
+                        clocks = <&clkc 23>, <&clkc 40>;
+                        clock-names = "ref_clk", "aper_clk";
                        reg = <0xE0000000 0x1000>;
                        interrupts = <0 27 4>;
-                        clocks = <&uart_clk 0>;
                };
                uart1: uart@e0001000 {
                        compatible = "xlnx,xuartps";
+                        status = "disabled";
+                        clocks = <&clkc 24>, <&clkc 41>;
+                        clock-names = "ref_clk", "aper_clk";
                        reg = <0xE0001000 0x1000>;
                        interrupts = <0 50 4>;
-                        clocks = <&uart_clk 1>;
                };
                slcr: slcr@f8000000 {
@@ -69,50 +73,21 @@
                                #address-cells = <1>;
                                #size-cells = <0>;
-                                ps_clk: ps_clk {
+                                clkc: clkc {
-                                        #clock-cells = <0>;
-                                        compatible = "fixed-clock";
-                                        /* clock-frequency set in board-specific file */
-                                        clock-output-names = "ps_clk";
-                                };
-                                armpll: armpll {
-                                        #clock-cells = <0>;
-                                        compatible = "xlnx,zynq-pll";
-                                        clocks = <&ps_clk>;
-                                        reg = <0x100 0x110>;
-                                        clock-output-names = "armpll";
-                                };
-                                ddrpll: ddrpll {
-                                        #clock-cells = <0>;
-                                        compatible = "xlnx,zynq-pll";
-                                        clocks = <&ps_clk>;
-                                        reg = <0x104 0x114>;
-                                        clock-output-names = "ddrpll";
-                                };
-                                iopll: iopll {
-                                        #clock-cells = <0>;
-                                        compatible = "xlnx,zynq-pll";
-                                        clocks = <&ps_clk>;
-                                        reg = <0x108 0x118>;
-                                        clock-output-names = "iopll";
-                                };
-                                uart_clk: uart_clk {
-                                        #clock-cells = <1>;
-                                        compatible = "xlnx,zynq-periph-clock";
-                                        clocks = <&iopll &armpll &ddrpll>;
-                                        reg = <0x154>;
-                                        clock-output-names = "uart0_ref_clk",
-                                                             "uart1_ref_clk";
-                                };
-                                cpu_clk: cpu_clk {
                                        #clock-cells = <1>;
-                                        compatible = "xlnx,zynq-cpu-clock";
+                                        compatible = "xlnx,ps7-clkc";
-                                        clocks = <&iopll &armpll &ddrpll>;
+                                        ps-clk-frequency = <33333333>;
-                                        reg = <0x120 0x1C4>;
+                                        clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
-                                        clock-output-names = "cpu_6x4x",
+                                                        "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
-                                                             "cpu_3x2x",
+                                                        "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
-                                                             "cpu_2x",
+                                                        "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
-                                                             "cpu_1x";
+                                                        "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
+                                                        "dma", "usb0_aper", "usb1_aper", "gem0_aper",
+                                                        "gem1_aper", "sdio0_aper", "sdio1_aper",
+                                                        "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
+                                                        "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
+                                                        "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
+                                                        "dbg_trc", "dbg_apb";
                                };
                        };
                };
@@ -121,9 +96,8 @@
                        interrupt-parent = <&intc>;
                        interrupts = < 0 10 4 0 11 4 0 12 4 >;
                        compatible = "cdns,ttc";
+                        clocks = <&clkc 6>;
                        reg = <0xF8001000 0x1000>;
-                        clocks = <&cpu_clk 3>;
-                        clock-names = "cpu_1x";
                        clock-ranges;
                };
@@ -131,9 +105,8 @@
                        interrupt-parent = <&intc>;
                        interrupts = < 0 37 4 0 38 4 0 39 4 >;
                        compatible = "cdns,ttc";
+                        clocks = <&clkc 6>;
                        reg = <0xF8002000 0x1000>;
-                        clocks = <&cpu_clk 3>;
-                        clock-names = "cpu_1x";
                        clock-ranges;
                };
                scutimer: scutimer@f8f00600 {
@@ -141,7 +114,7 @@
                        interrupts = < 1 13 0x301 >;
                        compatible = "arm,cortex-a9-twd-timer";
                        reg = < 0xf8f00600 0x20 >;
-                        clocks = <&cpu_clk 1>;
+                        clocks = <&clkc 4>;
                } ;
        };
 };
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
index 86f44d5b0265..21aea99a067b 100644
--- a/arch/arm/boot/dts/zynq-zc702.dts
+++ b/arch/arm/boot/dts/zynq-zc702.dts
@@ -24,11 +24,11 @@
        };
        chosen {
-                bootargs = "console=ttyPS1,115200 earlyprintk";
+                bootargs = "console=ttyPS0,115200 earlyprintk";
        };
 };
-&ps_clk {
+&uart1 {
-        clock-frequency = <33333330>;
+        status = "okay";
 };
diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts
new file mode 100644
index 000000000000..79009e0b74b9
--- /dev/null
+++ b/arch/arm/boot/dts/zynq-zc706.dts
@@ -0,0 +1,35 @@
+/*
+ *  Copyright (C) 2011 Xilinx
+ *  Copyright (C) 2012 National Instruments Corp.
+ *  Copyright (C) 2013 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+/ {
+        model = "Zynq ZC706 Development Board";
+        compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
+        memory {
+                device_type = "memory";
+                reg = <0 0x40000000>;
+        };
+        chosen {
+                bootargs = "console=ttyPS0,115200 earlyprintk";
+        };
+};
+&uart1 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/zynq-zed.dts
new file mode 100644
index 000000000000..d6acf2b1cdf4
--- /dev/null
+++ b/arch/arm/boot/dts/zynq-zed.dts
@@ -0,0 +1,35 @@
+/*
+ *  Copyright (C) 2011 Xilinx
+ *  Copyright (C) 2012 National Instruments Corp.
+ *  Copyright (C) 2013 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+/ {
+        model = "Zynq Zed Development Board";
+        compatible = "xlnx,zynq-7000";
+        memory {
+                device_type = "memory";
+                reg = <0 0x20000000>;
+        };
+        chosen {
+                bootargs = "console=ttyPS0,115200 earlyprintk";
+        };
+};
+&uart1 {
+        status = "okay";
+};
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index 9353184d730d..c3a4e9ceba34 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -17,3 +17,6 @@ config SHARP_PARAM
 config SHARP_SCOOP
        bool
+config TI_PRIV_EDMA
+        bool
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index 48434cbe3e89..8c60f473e976 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -16,3 +16,4 @@ obj-$(CONFIG_ARM_TIMER_SP804)	+= timer-sp.o
 obj-$(CONFIG_MCPM)              += mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o
 AFLAGS_mcpm_head.o              := -march=armv7-a
 AFLAGS_vlock.o                  := -march=armv7-a
+obj-$(CONFIG_TI_PRIV_EDMA)      += edma.o
diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/common/edma.c
index 45b7c71d9cc1..39ad030ac0c7 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/common/edma.c
@@ -17,6 +17,7 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */
+#include <linux/err.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/module.h>
@@ -24,8 +25,14 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/slab.h>
+#include <linux/edma.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_dma.h>
+#include <linux/of_irq.h>
+#include <linux/pm_runtime.h>
-#include <mach/edma.h>
+#include <linux/platform_data/edma.h>
 /* Offsets matching "struct edmacc_param" */
 #define PARM_OPT                0x00
@@ -494,26 +501,6 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
        return IRQ_HANDLED;
 }
-/******************************************************************************
- *
- * Transfer controller error interrupt handlers
- *
- *****************************************************************************/
-#define tc_errs_handled false   /* disabled as long as they're NOPs */
-static irqreturn_t dma_tc0err_handler(int irq, void *data)
-{
-        dev_dbg(data, "dma_tc0err_handler\n");
-        return IRQ_HANDLED;
-}
-static irqreturn_t dma_tc1err_handler(int irq, void *data)
-{
-        dev_dbg(data, "dma_tc1err_handler\n");
-        return IRQ_HANDLED;
-}
 static int reserve_contiguous_slots(int ctlr, unsigned int id,
                                     unsigned int num_slots,
                                     unsigned int start_slot)
@@ -1388,32 +1375,236 @@ void edma_clear_event(unsigned channel)
 }
 EXPORT_SYMBOL(edma_clear_event);
-/*-----------------------------------------------------------------------*/
+#if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DMADEVICES)
+static int edma_of_read_u32_to_s16_array(const struct device_node *np,
+                                         const char *propname, s16 *out_values,
+                                         size_t sz)
+{
+        int ret;
+        ret = of_property_read_u16_array(np, propname, out_values, sz);
+        if (ret)
+                return ret;
+        /* Terminate it */
+        *out_values++ = -1;
+        *out_values++ = -1;
+        return 0;
+}
+static int edma_xbar_event_map(struct device *dev,
+                               struct device_node *node,
+                               struct edma_soc_info *pdata, int len)
+{
+        int ret, i;
+        struct resource res;
+        void __iomem *xbar;
+        const s16 (*xbar_chans)[2];
+        u32 shift, offset, mux;
+        xbar_chans = devm_kzalloc(dev,
+                                  len/sizeof(s16) + 2*sizeof(s16),
+                                  GFP_KERNEL);
+        if (!xbar_chans)
+                return -ENOMEM;
+        ret = of_address_to_resource(node, 1, &res);
+        if (ret)
+                return -EIO;
+        xbar = devm_ioremap(dev, res.start, resource_size(&res));
+        if (!xbar)
+                return -ENOMEM;
+        ret = edma_of_read_u32_to_s16_array(node,
+                                            "ti,edma-xbar-event-map",
+                                            (s16 *)xbar_chans,
+                                            len/sizeof(u32));
+        if (ret)
+                return -EIO;
+        for (i = 0; xbar_chans[i][0] != -1; i++) {
+                shift = (xbar_chans[i][1] & 0x03) << 3;
+                offset = xbar_chans[i][1] & 0xfffffffc;
+                mux = readl(xbar + offset);
+                mux &= ~(0xff << shift);
+                mux |= xbar_chans[i][0] << shift;
+                writel(mux, (xbar + offset));
+        }
+        pdata->xbar_chans = xbar_chans;
+        return 0;
+}
+static int edma_of_parse_dt(struct device *dev,
+                            struct device_node *node,
+                            struct edma_soc_info *pdata)
+{
+        int ret = 0, i;
+        u32 value;
+        struct property *prop;
+        size_t sz;
+        struct edma_rsv_info *rsv_info;
+        s8 (*queue_tc_map)[2], (*queue_priority_map)[2];
+        memset(pdata, 0, sizeof(struct edma_soc_info));
+        ret = of_property_read_u32(node, "dma-channels", &value);
+        if (ret < 0)
+                return ret;
+        pdata->n_channel = value;
+        ret = of_property_read_u32(node, "ti,edma-regions", &value);
+        if (ret < 0)
+                return ret;
+        pdata->n_region = value;
+        ret = of_property_read_u32(node, "ti,edma-slots", &value);
+        if (ret < 0)
+                return ret;
+        pdata->n_slot = value;
+        pdata->n_cc = 1;
+        rsv_info = devm_kzalloc(dev, sizeof(struct edma_rsv_info), GFP_KERNEL);
+        if (!rsv_info)
+                return -ENOMEM;
+        pdata->rsv = rsv_info;
+        queue_tc_map = devm_kzalloc(dev, 8*sizeof(s8), GFP_KERNEL);
+        if (!queue_tc_map)
+                return -ENOMEM;
+        for (i = 0; i < 3; i++) {
+                queue_tc_map[i][0] = i;
+                queue_tc_map[i][1] = i;
+        }
+        queue_tc_map[i][0] = -1;
+        queue_tc_map[i][1] = -1;
+        pdata->queue_tc_mapping = queue_tc_map;
+        queue_priority_map = devm_kzalloc(dev, 8*sizeof(s8), GFP_KERNEL);
+        if (!queue_priority_map)
+                return -ENOMEM;
+        for (i = 0; i < 3; i++) {
+                queue_priority_map[i][0] = i;
+                queue_priority_map[i][1] = i;
+        }
+        queue_priority_map[i][0] = -1;
+        queue_priority_map[i][1] = -1;
+        pdata->queue_priority_mapping = queue_priority_map;
+        pdata->default_queue = 0;
+        prop = of_find_property(node, "ti,edma-xbar-event-map", &sz);
+        if (prop)
+                ret = edma_xbar_event_map(dev, node, pdata, sz);
+        return ret;
+}
+static struct of_dma_filter_info edma_filter_info = {
+        .filter_fn = edma_filter_fn,
+};
+static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
+                                                      struct device_node *node)
+{
+        struct edma_soc_info *info;
+        int ret;
+        info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL);
+        if (!info)
+                return ERR_PTR(-ENOMEM);
-static int __init edma_probe(struct platform_device *pdev)
+        ret = edma_of_parse_dt(dev, node, info);
+        if (ret)
+                return ERR_PTR(ret);
+        dma_cap_set(DMA_SLAVE, edma_filter_info.dma_cap);
+        of_dma_controller_register(dev->of_node, of_dma_simple_xlate,
+                                   &edma_filter_info);
+        return info;
+}
+#else
+static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
+                                                      struct device_node *node)
+{
+        return ERR_PTR(-ENOSYS);
+}
+#endif
+static int edma_probe(struct platform_device *pdev)
 {
        struct edma_soc_info    **info = pdev->dev.platform_data;
-        const s8                (*queue_priority_mapping)[2];
+        struct edma_soc_info    *ninfo[EDMA_MAX_CC] = {NULL};
-        const s8                (*queue_tc_mapping)[2];
+        s8              (*queue_priority_mapping)[2];
+        s8              (*queue_tc_mapping)[2];
        int                     i, j, off, ln, found = 0;
        int                     status = -1;
        const s16               (*rsv_chans)[2];
        const s16               (*rsv_slots)[2];
+        const s16               (*xbar_chans)[2];
        int                     irq[EDMA_MAX_CC] = {0, 0};
        int                     err_irq[EDMA_MAX_CC] = {0, 0};
        struct resource         *r[EDMA_MAX_CC] = {NULL};
-        resource_size_t         len[EDMA_MAX_CC];
+        struct resource         res[EDMA_MAX_CC];
        char                    res_name[10];
        char                    irq_name[10];
+        struct device_node      *node = pdev->dev.of_node;
+        struct device           *dev = &pdev->dev;
+        int                     ret;
+        if (node) {
+                /* Check if this is a second instance registered */
+                if (arch_num_cc) {
+                        dev_err(dev, "only one EDMA instance is supported via DT\n");
+                        return -ENODEV;
+                }
+                ninfo[0] = edma_setup_info_from_dt(dev, node);
+                if (IS_ERR(ninfo[0])) {
+                        dev_err(dev, "failed to get DT data\n");
+                        return PTR_ERR(ninfo[0]);
+                }
+                info = ninfo;
+        }
        if (!info)
                return -ENODEV;
+        pm_runtime_enable(dev);
+        ret = pm_runtime_get_sync(dev);
+        if (ret < 0) {
+                dev_err(dev, "pm_runtime_get_sync() failed\n");
+                return ret;
+        }
        for (j = 0; j < EDMA_MAX_CC; j++) {
-                sprintf(res_name, "edma_cc%d", j);
+                if (!info[j]) {
-                r[j] = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+                        if (!found)
+                                return -ENODEV;
+                        break;
+                }
+                if (node) {
+                        ret = of_address_to_resource(node, j, &res[j]);
+                        if (!ret)
+                                r[j] = &res[j];
+                } else {
+                        sprintf(res_name, "edma_cc%d", j);
+                        r[j] = platform_get_resource_byname(pdev,
+                                                IORESOURCE_MEM,
                                                res_name);
-                if (!r[j] || !info[j]) {
+                }
+                if (!r[j]) {
                        if (found)
                                break;
                        else
@@ -1422,26 +1613,14 @@ static int __init edma_probe(struct platform_device *pdev)
                        found = 1;
                }
-                len[j] = resource_size(r[j]);
+                edmacc_regs_base[j] = devm_ioremap_resource(&pdev->dev, r[j]);
+                if (IS_ERR(edmacc_regs_base[j]))
-                r[j] = request_mem_region(r[j]->start, len[j],
+                        return PTR_ERR(edmacc_regs_base[j]);
-                        dev_name(&pdev->dev));
-                if (!r[j]) {
-                        status = -EBUSY;
-                        goto fail1;
-                }
-                edmacc_regs_base[j] = ioremap(r[j]->start, len[j]);
-                if (!edmacc_regs_base[j]) {
-                        status = -EBUSY;
-                        goto fail1;
-                }
-                edma_cc[j] = kzalloc(sizeof(struct edma), GFP_KERNEL);
+                edma_cc[j] = devm_kzalloc(&pdev->dev, sizeof(struct edma),
-                if (!edma_cc[j]) {
+                                          GFP_KERNEL);
-                        status = -ENOMEM;
+                if (!edma_cc[j])
-                        goto fail1;
+                        return -ENOMEM;
-                }
                edma_cc[j]->num_channels = min_t(unsigned, info[j]->n_channel,
                                                        EDMA_MAX_DMACH);
@@ -1472,7 +1651,7 @@ static int __init edma_probe(struct platform_device *pdev)
                                        off = rsv_chans[i][0];
                                        ln = rsv_chans[i][1];
                                        clear_bits(off, ln,
-                                                edma_cc[j]->edma_unused);
+                                                  edma_cc[j]->edma_unused);
                                }
                        }
@@ -1488,26 +1667,48 @@ static int __init edma_probe(struct platform_device *pdev)
                        }
                }
-                sprintf(irq_name, "edma%d", j);
+                /* Clear the xbar mapped channels in unused list */
-                irq[j] = platform_get_irq_byname(pdev, irq_name);
+                xbar_chans = info[j]->xbar_chans;
+                if (xbar_chans) {
+                        for (i = 0; xbar_chans[i][1] != -1; i++) {
+                                off = xbar_chans[i][1];
+                                clear_bits(off, 1,
+                                           edma_cc[j]->edma_unused);
+                        }
+                }
+                if (node) {
+                        irq[j] = irq_of_parse_and_map(node, 0);
+                } else {
+                        sprintf(irq_name, "edma%d", j);
+                        irq[j] = platform_get_irq_byname(pdev, irq_name);
+                }
                edma_cc[j]->irq_res_start = irq[j];
-                status = request_irq(irq[j], dma_irq_handler, 0, "edma",
+                status = devm_request_irq(&pdev->dev, irq[j],
-                                        &pdev->dev);
+                                          dma_irq_handler, 0, "edma",
+                                          &pdev->dev);
                if (status < 0) {
-                        dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
+                        dev_dbg(&pdev->dev,
+                                "devm_request_irq %d failed --> %d\n",
                                irq[j], status);
-                        goto fail;
+                        return status;
                }
-                sprintf(irq_name, "edma%d_err", j);
+                if (node) {
-                err_irq[j] = platform_get_irq_byname(pdev, irq_name);
+                        err_irq[j] = irq_of_parse_and_map(node, 2);
+                } else {
+                        sprintf(irq_name, "edma%d_err", j);
+                        err_irq[j] = platform_get_irq_byname(pdev, irq_name);
+                }
                edma_cc[j]->irq_res_end = err_irq[j];
-                status = request_irq(err_irq[j], dma_ccerr_handler, 0,
+                status = devm_request_irq(&pdev->dev, err_irq[j],
-                                        "edma_error", &pdev->dev);
+                                          dma_ccerr_handler, 0,
+                                          "edma_error", &pdev->dev);
                if (status < 0) {
-                        dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
+                        dev_dbg(&pdev->dev,
+                                "devm_request_irq %d failed --> %d\n",
                                err_irq[j], status);
-                        goto fail;
+                        return status;
                }
                for (i = 0; i < edma_cc[j]->num_channels; i++)
@@ -1541,46 +1742,20 @@ static int __init edma_probe(struct platform_device *pdev)
                arch_num_cc++;
        }
-        if (tc_errs_handled) {
-                status = request_irq(IRQ_TCERRINT0, dma_tc0err_handler, 0,
-                                        "edma_tc0", &pdev->dev);
-                if (status < 0) {
-                        dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
-                                IRQ_TCERRINT0, status);
-                        return status;
-                }
-                status = request_irq(IRQ_TCERRINT, dma_tc1err_handler, 0,
-                                        "edma_tc1", &pdev->dev);
-                if (status < 0) {
-                        dev_dbg(&pdev->dev, "request_irq %d --> %d\n",
-                                IRQ_TCERRINT, status);
-                        return status;
-                }
-        }
        return 0;
-fail:
-        for (i = 0; i < EDMA_MAX_CC; i++) {
-                if (err_irq[i])
-                        free_irq(err_irq[i], &pdev->dev);
-                if (irq[i])
-                        free_irq(irq[i], &pdev->dev);
-        }
-fail1:
-        for (i = 0; i < EDMA_MAX_CC; i++) {
-                if (r[i])
-                        release_mem_region(r[i]->start, len[i]);
-                if (edmacc_regs_base[i])
-                        iounmap(edmacc_regs_base[i]);
-                kfree(edma_cc[i]);
-        }
-        return status;
 }
+static const struct of_device_id edma_of_ids[] = {
+        { .compatible = "ti,edma3", },
+        {}
+};
 static struct platform_driver edma_driver = {
-        .driver.name    = "edma",
+        .driver = {
+                .name   = "edma",
+                .of_match_table = edma_of_ids,
+        },
+        .probe = edma_probe,
 };
 static int __init edma_init(void)
diff --git a/arch/arm/common/mcpm_head.S b/arch/arm/common/mcpm_head.S
index 8178705c4b24..80f033614a1f 100644
--- a/arch/arm/common/mcpm_head.S
+++ b/arch/arm/common/mcpm_head.S
@@ -32,11 +32,11 @@
 1901:   adr     r0, 1902b
        bl      printascii
        mov     r0, r9
-        bl      printhex8
+        bl      printhex2
        adr     r0, 1903b
        bl      printascii
        mov     r0, r10
-        bl      printhex8
+        bl      printhex2
        adr     r0, 1904b
        bl      printascii
 #endif
diff --git a/arch/arm/common/mcpm_platsmp.c b/arch/arm/common/mcpm_platsmp.c
index 3caed0db6986..1bc34c7567fd 100644
--- a/arch/arm/common/mcpm_platsmp.c
+++ b/arch/arm/common/mcpm_platsmp.c
@@ -19,11 +19,7 @@
 #include <asm/smp.h>
 #include <asm/smp_plat.h>
-static void __init simple_smp_init_cpus(void)
+static int mcpm_boot_secondary(unsigned int cpu, struct task_struct *idle)
-{
-}
-static int __cpuinit mcpm_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
        unsigned int mpidr, pcpu, pcluster, ret;
        extern void secondary_startup(void);
@@ -44,7 +40,7 @@ static int __cpuinit mcpm_boot_secondary(unsigned int cpu, struct task_struct *i
        return 0;
 }
-static void __cpuinit mcpm_secondary_init(unsigned int cpu)
+static void mcpm_secondary_init(unsigned int cpu)
 {
        mcpm_cpu_powered_up();
 }
@@ -74,7 +70,6 @@ static void mcpm_cpu_die(unsigned int cpu)
 #endif
 static struct smp_operations __initdata mcpm_smp_ops = {
-        .smp_init_cpus          = simple_smp_init_cpus,
        .smp_boot_secondary     = mcpm_boot_secondary,
        .smp_secondary_init     = mcpm_secondary_init,
 #ifdef CONFIG_HOTPLUG_CPU
diff --git a/arch/arm/common/timer-sp.c b/arch/arm/common/timer-sp.c
index ddc740769601..023ee63827a2 100644
--- a/arch/arm/common/timer-sp.c
+++ b/arch/arm/common/timer-sp.c
@@ -28,8 +28,8 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
+#include <linux/sched_clock.h>
-#include <asm/sched_clock.h>
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/timer-sp.h>
diff --git a/arch/arm/configs/ap4evb_defconfig b/arch/arm/configs/ap4evb_defconfig
deleted file mode 100644
index 66894f736d04..000000000000
--- a/arch/arm/configs/ap4evb_defconfig
+++ /dev/null
@@ -1,56 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=16
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_SHMOBILE=y
-CONFIG_ARCH_SH7372=y
-CONFIG_MACH_AP4EVB=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttySC0,115200 earlyprintk=sh-sci.0,115200"
-CONFIG_KEXEC=y
-CONFIG_PM=y
-# CONFIG_SUSPEND is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_NAND=y
-# CONFIG_BLK_DEV is not set
-# CONFIG_MISC_DEVICES is not set
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_SH_SCI=y
-CONFIG_SERIAL_SH_SCI_NR_UARTS=8
-CONFIG_SERIAL_SH_SCI_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DETECT_SOFTLOCKUP is not set
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_FTRACE is not set
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/armadillo800eva_defconfig b/arch/arm/configs/armadillo800eva_defconfig
index 0f2d80da7378..fae939d3d7f0 100644
--- a/arch/arm/configs/armadillo800eva_defconfig
+++ b/arch/arm/configs/armadillo800eva_defconfig
@@ -86,7 +86,7 @@ CONFIG_TOUCHSCREEN_ST1232=y
 # CONFIG_SERIO is not set
 # CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_SH_SCI=y
-CONFIG_SERIAL_SH_SCI_NR_UARTS=8
+CONFIG_SERIAL_SH_SCI_NR_UARTS=9
 CONFIG_SERIAL_SH_SCI_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index 047f2a415309..75fd842d4071 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -1,4 +1,3 @@
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
@@ -25,8 +24,6 @@ CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
 CONFIG_AT91_TIMER_HZ=128
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
-CONFIG_LEDS=y
-CONFIG_LEDS_CPU=y
 CONFIG_UACCESS_WITH_MEMCPY=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
@@ -42,6 +39,9 @@ CONFIG_UNIX=y
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
 CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET_XFRM_MODE_BEET is not set
@@ -51,7 +51,8 @@ CONFIG_IPV6=y
 # CONFIG_INET6_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET6_XFRM_MODE_BEET is not set
 CONFIG_IPV6_SIT_6RD=y
-# CONFIG_WIRELESS is not set
+CONFIG_CFG80211=y
+CONFIG_MAC80211=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
@@ -72,7 +73,6 @@ CONFIG_BLK_DEV_RAM_COUNT=4
 CONFIG_BLK_DEV_RAM_SIZE=8192
 CONFIG_ATMEL_PWM=y
 CONFIG_ATMEL_TCLIB=y
-CONFIG_EEPROM_93CX6=m
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
@@ -81,7 +81,6 @@ CONFIG_NETDEVICES=y
 CONFIG_MII=y
 CONFIG_MACB=y
 # CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
 # CONFIG_NET_VENDOR_FARADAY is not set
 # CONFIG_NET_VENDOR_INTEL is not set
 # CONFIG_NET_VENDOR_MARVELL is not set
@@ -92,7 +91,23 @@ CONFIG_MACB=y
 # CONFIG_NET_VENDOR_STMICRO is not set
 CONFIG_DAVICOM_PHY=y
 CONFIG_MICREL_PHY=y
-# CONFIG_WLAN is not set
+CONFIG_RTL8187=m
+CONFIG_LIBERTAS=m
+CONFIG_LIBERTAS_SDIO=m
+CONFIG_LIBERTAS_SPI=m
+CONFIG_RT2X00=m
+CONFIG_RT2500USB=m
+CONFIG_RT73USB=m
+CONFIG_RT2800USB=m
+CONFIG_RT2800USB_RT53XX=y
+CONFIG_RT2800USB_RT55XX=y
+CONFIG_RT2800USB_UNKNOWN=y
+CONFIG_RTLWIFI=m
+# CONFIG_RTLWIFI_DEBUG is not set
+CONFIG_RTL8192CU=m
+CONFIG_MWIFIEX=m
+CONFIG_MWIFIEX_SDIO=m
+CONFIG_MWIFIEX_USB=m
 CONFIG_INPUT_POLLDEV=y
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=480
@@ -112,13 +127,11 @@ CONFIG_I2C=y
 CONFIG_I2C_GPIO=y
 CONFIG_SPI=y
 CONFIG_SPI_ATMEL=y
-CONFIG_PINCTRL_AT91=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_AT91SAM9X_WATCHDOG=y
 CONFIG_SSB=m
 CONFIG_FB=y
-CONFIG_FB_MODE_HELPERS=y
 CONFIG_FB_ATMEL=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 # CONFIG_LCD_CLASS_DEVICE is not set
@@ -132,11 +145,8 @@ CONFIG_FONT_8x8=y
 CONFIG_FONT_ACORN_8x8=y
 CONFIG_FONT_MINI_4x6=y
 CONFIG_LOGO=y
-# CONFIG_HID_SUPPORT is not set
 CONFIG_USB=y
 CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_ACM=y
@@ -146,16 +156,12 @@ CONFIG_USB_SERIAL_GENERIC=y
 CONFIG_USB_SERIAL_FTDI_SIO=y
 CONFIG_USB_SERIAL_PL2303=y
 CONFIG_USB_GADGET=y
-CONFIG_USB_AT91=m
+CONFIG_USB_AT91=y
-CONFIG_USB_ATMEL_USBA=m
+CONFIG_USB_ATMEL_USBA=y
-CONFIG_USB_ETH=m
+CONFIG_USB_G_SERIAL=y
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_CDC_COMPOSITE=m
-CONFIG_USB_G_ACM_MS=m
-CONFIG_USB_G_MULTI=m
-CONFIG_USB_G_MULTI_CDC=y
 CONFIG_MMC=y
 CONFIG_MMC_ATMELMCI=y
+CONFIG_MMC_SPI=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
@@ -164,20 +170,23 @@ CONFIG_LEDS_TRIGGER_TIMER=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_LEDS_TRIGGER_GPIO=y
 CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_RV3029C2=y
 CONFIG_RTC_DRV_AT91RM9200=y
 CONFIG_RTC_DRV_AT91SAM9=y
 CONFIG_DMADEVICES=y
 # CONFIG_IOMMU_SUPPORT is not set
-CONFIG_EXT2_FS=y
+CONFIG_EXT4_FS=y
 CONFIG_FANOTIFY=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
 CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
 CONFIG_STRIP_ASM_SYMS=y
 CONFIG_DEBUG_FS=y
 # CONFIG_SCHED_DEBUG is not set
@@ -192,7 +201,7 @@ CONFIG_CRYPTO_ARC4=y
 CONFIG_CRYPTO_USER_API_HASH=m
 CONFIG_CRYPTO_USER_API_SKCIPHER=m
 # CONFIG_CRYPTO_HW is not set
-CONFIG_CRC_CCITT=m
+CONFIG_CRC_CCITT=y
-CONFIG_CRC_ITU_T=m
+CONFIG_CRC_ITU_T=y
 CONFIG_CRC7=m
 CONFIG_AVERAGE=y
diff --git a/arch/arm/configs/at91rm9200_defconfig b/arch/arm/configs/at91rm9200_defconfig
index 4ae57a34a582..75502c4d222c 100644
--- a/arch/arm/configs/at91rm9200_defconfig
+++ b/arch/arm/configs/at91rm9200_defconfig
@@ -1,10 +1,12 @@
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
+CONFIG_USER_NS=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_MODULES=y
 CONFIG_MODULE_FORCE_LOAD=y
@@ -16,7 +18,6 @@ CONFIG_MODULE_SRCVERSION_ALL=y
 CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91RM9200=y
 CONFIG_MACH_ONEARM=y
-CONFIG_ARCH_AT91RM9200DK=y
 CONFIG_MACH_AT91RM9200EK=y
 CONFIG_MACH_CSB337=y
 CONFIG_MACH_CSB637=y
@@ -35,49 +36,37 @@ CONFIG_AT91_TIMER_HZ=100
 # CONFIG_ARM_THUMB is not set
 CONFIG_PCCARD=y
 CONFIG_AT91_CF=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
 CONFIG_AEABI=y
-CONFIG_LEDS=y
+# CONFIG_COMPACTION is not set
-CONFIG_LEDS_CPU=y
 CONFIG_ZBOOT_ROM_TEXT=0x10000000
 CONFIG_ZBOOT_ROM_BSS=0x20040000
 CONFIG_KEXEC=y
+CONFIG_AUTO_ZRELADDR=y
 CONFIG_FPE_NWFPE=y
 CONFIG_BINFMT_MISC=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
-CONFIG_XFRM_USER=m
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
-CONFIG_NET_IPIP=m
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-CONFIG_INET_AH=m
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-CONFIG_INET_ESP=m
+# CONFIG_INET_XFRM_MODE_BEET is not set
-CONFIG_INET_IPCOMP=m
+# CONFIG_INET_DIAG is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_IPV6=y
-CONFIG_INET_XFRM_MODE_TUNNEL=m
-CONFIG_INET_XFRM_MODE_BEET=m
 CONFIG_IPV6_PRIVACY=y
 CONFIG_IPV6_ROUTER_PREF=y
 CONFIG_IPV6_ROUTE_INFO=y
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_IPCOMP=m
-CONFIG_IPV6_MIP6=m
-CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
-CONFIG_IPV6_TUNNEL=m
-CONFIG_BRIDGE=m
-CONFIG_VLAN_8021Q=m
-CONFIG_BT=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_AFS_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
@@ -94,55 +83,21 @@ CONFIG_MTD_NAND_PLATFORM=y
 CONFIG_MTD_UBI=y
 CONFIG_MTD_UBI_GLUEBI=y
 CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_DEV_SR=m
-CONFIG_BLK_DEV_SR_VENDOR=y
-CONFIG_CHR_DEV_SG=m
-CONFIG_SCSI_MULTI_LUN=y
-# CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_NETDEVICES=y
-CONFIG_TUN=m
+CONFIG_MII=y
 CONFIG_ARM_AT91_ETHER=y
-CONFIG_PHYLIB=y
 CONFIG_DAVICOM_PHY=y
 CONFIG_SMSC_PHY=y
 CONFIG_MICREL_PHY=y
-CONFIG_PPP=y
+# CONFIG_WLAN is not set
-CONFIG_PPP_BSDCOMP=y
+# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_MPPE=m
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPPOE=m
-CONFIG_PPP_ASYNC=y
-CONFIG_SLIP=m
-CONFIG_SLIP_COMPRESSED=y
-CONFIG_SLIP_SMART=y
-CONFIG_SLIP_MODE_SLIP6=y
-CONFIG_USB_CATC=m
-CONFIG_USB_KAWETH=m
-CONFIG_USB_PEGASUS=m
-CONFIG_USB_RTL8150=m
-CONFIG_USB_USBNET=m
-CONFIG_USB_NET_DM9601=m
-CONFIG_USB_NET_GL620A=m
-CONFIG_USB_NET_PLUSB=m
-CONFIG_USB_NET_RNDIS_HOST=m
-CONFIG_USB_ALI_M5632=y
-CONFIG_USB_AN2720=y
-CONFIG_USB_EPSON2888=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=640
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480
 CONFIG_INPUT_EVDEV=y
 CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_LEGACY_PTY_COUNT=32
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_ATMEL=y
 CONFIG_SERIAL_ATMEL_CONSOLE=y
 CONFIG_HW_RANDOM=y
@@ -151,38 +106,8 @@ CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_GPIO=y
 CONFIG_SPI=y
 CONFIG_SPI_ATMEL=y
-CONFIG_SPI_BITBANG=y
 CONFIG_GPIO_SYSFS=y
-CONFIG_HWMON=m
+# CONFIG_HWMON is not set
-CONFIG_SENSORS_ADM1021=m
-CONFIG_SENSORS_ADM1025=m
-CONFIG_SENSORS_ADM1026=m
-CONFIG_SENSORS_ADM1029=m
-CONFIG_SENSORS_ADM1031=m
-CONFIG_SENSORS_ADM9240=m
-CONFIG_SENSORS_DS1621=m
-CONFIG_SENSORS_GL518SM=m
-CONFIG_SENSORS_GL520SM=m
-CONFIG_SENSORS_IT87=m
-CONFIG_SENSORS_LM63=m
-CONFIG_SENSORS_LM73=m
-CONFIG_SENSORS_LM75=m
-CONFIG_SENSORS_LM77=m
-CONFIG_SENSORS_LM78=m
-CONFIG_SENSORS_LM80=m
-CONFIG_SENSORS_LM83=m
-CONFIG_SENSORS_LM85=m
-CONFIG_SENSORS_LM87=m
-CONFIG_SENSORS_LM90=m
-CONFIG_SENSORS_LM92=m
-CONFIG_SENSORS_MAX1619=m
-CONFIG_SENSORS_PCF8591=m
-CONFIG_SENSORS_SMSC47B397=m
-CONFIG_SENSORS_W83781D=m
-CONFIG_SENSORS_W83791D=m
-CONFIG_SENSORS_W83792D=m
-CONFIG_SENSORS_W83793=m
-CONFIG_SENSORS_W83L785TS=m
 CONFIG_WATCHDOG=y
 CONFIG_WATCHDOG_NOWAYOUT=y
 CONFIG_AT91RM9200_WATCHDOG=y
@@ -194,43 +119,14 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
 # CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_FONTS=y
-CONFIG_FONT_MINI_4x6=y
 CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
 CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_MON=y
 CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_ACM=m
-CONFIG_USB_PRINTER=m
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_CONSOLE=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_FTDI_SIO=y
-CONFIG_USB_SERIAL_KEYSPAN=y
-CONFIG_USB_SERIAL_KEYSPAN_MPR=y
-CONFIG_USB_SERIAL_KEYSPAN_USA28=y
-CONFIG_USB_SERIAL_KEYSPAN_USA28X=y
-CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y
-CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y
-CONFIG_USB_SERIAL_KEYSPAN_USA19=y
-CONFIG_USB_SERIAL_KEYSPAN_USA18X=y
-CONFIG_USB_SERIAL_KEYSPAN_USA19W=y
-CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y
-CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y
-CONFIG_USB_SERIAL_KEYSPAN_USA49W=y
-CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
-CONFIG_USB_SERIAL_MCT_U232=y
-CONFIG_USB_SERIAL_PL2303=y
 CONFIG_USB_GADGET=y
-CONFIG_USB_ETH=m
+CONFIG_USB_AT91=y
-CONFIG_USB_MASS_STORAGE=m
+CONFIG_USB_G_SERIAL=y
 CONFIG_MMC=y
 CONFIG_MMC_ATMELMCI=y
 CONFIG_NEW_LEDS=y
@@ -240,84 +136,27 @@ CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_LEDS_TRIGGER_GPIO=y
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
 CONFIG_RTC_CLASS=y
-# CONFIG_RTC_HCTOSYS is not set
-CONFIG_RTC_DRV_DS1307=y
-CONFIG_RTC_DRV_PCF8563=y
 CONFIG_RTC_DRV_AT91RM9200=y
-CONFIG_EXT2_FS=y
+CONFIG_EXT4_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_REISERFS_FS=y
 CONFIG_AUTOFS4_FS=y
-CONFIG_ISO9660_FS=y
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_UDF_FS=y
-CONFIG_MSDOS_FS=y
 CONFIG_VFAT_FS=y
-CONFIG_NTFS_FS=m
 CONFIG_TMPFS=y
-CONFIG_CONFIGFS_FS=y
+CONFIG_UBIFS_FS=y
-CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_JFFS2_LZO=y
-CONFIG_JFFS2_RUBIN=y
-CONFIG_CRAMFS=y
-CONFIG_MINIX_FS=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=y
 CONFIG_ROOT_NFS=y
-CONFIG_NFSD=y
-CONFIG_CIFS=m
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_MAC_PARTITION=y
 CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_CODEPAGE_775=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_CODEPAGE_855=m
-CONFIG_NLS_CODEPAGE_857=m
-CONFIG_NLS_CODEPAGE_860=m
-CONFIG_NLS_CODEPAGE_861=m
-CONFIG_NLS_CODEPAGE_862=m
-CONFIG_NLS_CODEPAGE_863=m
-CONFIG_NLS_CODEPAGE_864=m
-CONFIG_NLS_CODEPAGE_865=m
-CONFIG_NLS_CODEPAGE_866=m
-CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
-CONFIG_NLS_CODEPAGE_932=m
-CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-CONFIG_NLS_ASCII=m
 CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_3=m
-CONFIG_NLS_ISO8859_4=m
-CONFIG_NLS_ISO8859_5=m
-CONFIG_NLS_ISO8859_6=m
-CONFIG_NLS_ISO8859_7=m
-CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_KOI8_R=m
-CONFIG_NLS_KOI8_U=m
 CONFIG_NLS_UTF8=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_KERNEL=y
 # CONFIG_FTRACE is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_EARLY_PRINTK=y
 CONFIG_CRYPTO_PCBC=y
 CONFIG_CRYPTO_SHA1=y
+CONFIG_XZ_DEC_ARMTHUMB=y
diff --git a/arch/arm/configs/at91sam9g20_defconfig b/arch/arm/configs/at91sam9260_9g20_defconfig
index 892e8287ed73..69b6928d3d9d 100644
--- a/arch/arm/configs/at91sam9g20_defconfig
+++ b/arch/arm/configs/at91sam9260_9g20_defconfig
@@ -1,4 +1,3 @@
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
@@ -11,7 +10,14 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT91SAM9G20=y
+CONFIG_ARCH_AT91SAM9260=y
+CONFIG_MACH_AT91SAM9260EK=y
+CONFIG_MACH_CAM60=y
+CONFIG_MACH_SAM9_L9260=y
+CONFIG_MACH_AFEB9260=y
+CONFIG_MACH_QIL_A9260=y
+CONFIG_MACH_CPU9260=y
+CONFIG_MACH_FLEXIBITY=y
 CONFIG_MACH_AT91SAM9G20EK=y
 CONFIG_MACH_AT91SAM9G20EK_2MMC=y
 CONFIG_MACH_CPU9G20=y
@@ -20,10 +26,10 @@ CONFIG_MACH_PORTUXG20=y
 CONFIG_MACH_STAMP9G20=y
 CONFIG_MACH_PCONTROL_G20=y
 CONFIG_MACH_GSIA18S=y
-CONFIG_MACH_USB_A9G20=y
 CONFIG_MACH_SNAPPER_9260=y
 CONFIG_MACH_AT91SAM9_DT=y
 CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+CONFIG_AT91_SLOW_CLOCK=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_AEABI=y
 CONFIG_LEDS=y
@@ -33,12 +39,14 @@ CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_ARM_APPENDED_DTB=y
 CONFIG_ARM_ATAG_DTB_COMPAT=y
 CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
+CONFIG_AUTO_ZRELADDR=y
 CONFIG_FPE_NWFPE=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_INET=y
 CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
@@ -46,8 +54,11 @@ CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_LRO is not set
 # CONFIG_IPV6 is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_DATAFLASH=y
@@ -56,6 +67,8 @@ CONFIG_MTD_NAND_ATMEL=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_MISC_DEVICES=y
+CONFIG_EEPROM_AT25=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
@@ -63,23 +76,36 @@ CONFIG_SCSI_MULTI_LUN=y
 CONFIG_NETDEVICES=y
 CONFIG_MII=y
 CONFIG_MACB=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+CONFIG_SMSC_PHY=y
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
 CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
-CONFIG_LEGACY_PTY_COUNT=16
+# CONFIG_SERIO is not set
 CONFIG_SERIAL_ATMEL=y
 CONFIG_SERIAL_ATMEL_CONSOLE=y
 CONFIG_HW_RANDOM=y
 CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_GPIO=y
 CONFIG_SPI=y
 CONFIG_SPI_ATMEL=y
 CONFIG_SPI_SPIDEV=y
+CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+CONFIG_AT91SAM9X_WATCHDOG=y
 CONFIG_SOUND=y
 CONFIG_SND=y
 CONFIG_SND_SEQUENCER=y
@@ -94,12 +120,11 @@ CONFIG_USB_MON=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
-CONFIG_USB_ZERO=m
+CONFIG_USB_AT91=y
-CONFIG_USB_GADGETFS=m
+CONFIG_USB_G_SERIAL=y
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
 CONFIG_MMC=y
-CONFIG_MMC_ATMELMCI=m
+CONFIG_MMC_ATMELMCI=y
+CONFIG_MMC_SPI=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
@@ -109,15 +134,12 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_RV3029C2=y
 CONFIG_RTC_DRV_AT91SAM9=y
-CONFIG_EXT2_FS=y
+CONFIG_EXT4_FS=y
-CONFIG_MSDOS_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
-CONFIG_JFFS2_SUMMARY=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
-CONFIG_CRAMFS=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
@@ -125,3 +147,9 @@ CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_15=y
 CONFIG_NLS_UTF8=y
 # CONFIG_ENABLE_WARN_DEPRECATED is not set
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_LL=y
+CONFIG_AT91_DEBUG_LL_DBGU0=y
+CONFIG_EARLY_PRINTK=y
diff --git a/arch/arm/configs/at91sam9260_defconfig b/arch/arm/configs/at91sam9260_defconfig
deleted file mode 100644
index 05618eb694f8..000000000000
--- a/arch/arm/configs/at91sam9260_defconfig
+++ /dev/null
@@ -1,91 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT91SAM9260=y
-CONFIG_ARCH_AT91SAM9260_SAM9XE=y
-CONFIG_MACH_AT91SAM9260EK=y
-CONFIG_MACH_CAM60=y
-CONFIG_MACH_SAM9_L9260=y
-CONFIG_MACH_AFEB9260=y
-CONFIG_MACH_USB_A9260=y
-CONFIG_MACH_QIL_A9260=y
-CONFIG_MACH_CPU9260=y
-CONFIG_MACH_FLEXIBITY=y
-CONFIG_MACH_SNAPPER_9260=y
-CONFIG_MACH_AT91SAM9_DT=y
-CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
-CONFIG_FPE_NWFPE=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_NETDEVICES=y
-CONFIG_MII=y
-CONFIG_MACB=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_GPIO=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_AT91SAM9X_WATCHDOG=y
-# CONFIG_USB_HID is not set
-CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_STORAGE_DEBUG=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ZERO=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_AT91SAM9=y
-CONFIG_EXT2_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_CRAMFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
diff --git a/arch/arm/configs/at91sam9261_defconfig b/arch/arm/configs/at91sam9261_9g10_defconfig
index c87beb973b37..9d35cd81c611 100644
--- a/arch/arm/configs/at91sam9261_defconfig
+++ b/arch/arm/configs/at91sam9261_9g10_defconfig
@@ -17,6 +17,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9261=y
 CONFIG_MACH_AT91SAM9261EK=y
+CONFIG_MACH_AT91SAM9G10EK=y
 CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_AEABI=y
@@ -38,11 +39,11 @@ CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_LRO is not set
 # CONFIG_IPV6 is not set
 CONFIG_CFG80211=y
-CONFIG_LIB80211=y
 CONFIG_MAC80211=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_NAND=y
@@ -51,17 +52,13 @@ CONFIG_MTD_UBI=y
 CONFIG_MTD_UBI_GLUEBI=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_MISC_DEVICES=y
 CONFIG_ATMEL_TCLIB=y
 CONFIG_ATMEL_SSC=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
 CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
 CONFIG_DM9000=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
 CONFIG_USB_ZD1201=m
 CONFIG_RTL8187=m
 CONFIG_LIBERTAS=m
@@ -118,15 +115,11 @@ CONFIG_SND_AT73C213=y
 CONFIG_SND_USB_AUDIO=m
 # CONFIG_USB_HID is not set
 CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
-CONFIG_USB_ZERO=m
+CONFIG_USB_AT91=y
-CONFIG_USB_ETH=m
+CONFIG_USB_G_SERIAL=y
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
 CONFIG_MMC=y
 CONFIG_MMC_ATMELMCI=m
 CONFIG_NEW_LEDS=y
@@ -147,12 +140,10 @@ CONFIG_SQUASHFS=y
 CONFIG_SQUASHFS_LZO=y
 CONFIG_SQUASHFS_XZ=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_15=y
 CONFIG_NLS_UTF8=y
-CONFIG_FTRACE=y
 CONFIG_CRC_CCITT=m
diff --git a/arch/arm/configs/at91sam9263_defconfig b/arch/arm/configs/at91sam9263_defconfig
index 36fed66bd4b5..e40026364e57 100644
--- a/arch/arm/configs/at91sam9263_defconfig
+++ b/arch/arm/configs/at91sam9263_defconfig
@@ -1,6 +1,4 @@
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZMA=y
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
 CONFIG_IKCONFIG=y
@@ -17,7 +15,6 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9263=y
 CONFIG_MACH_AT91SAM9263EK=y
-CONFIG_MACH_USB_A9263=y
 CONFIG_MTD_AT91_DATAFLASH_CARD=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_AEABI=y
@@ -48,9 +45,11 @@ CONFIG_IP_PIMSM_V2=y
 # CONFIG_INET_LRO is not set
 # CONFIG_INET_DIAG is not set
 CONFIG_IPV6=y
+# CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
@@ -65,7 +64,6 @@ CONFIG_MTD_UBI_GLUEBI=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_MISC_DEVICES=y
 CONFIG_ATMEL_PWM=y
 CONFIG_ATMEL_TCLIB=y
 CONFIG_SCSI=y
@@ -73,23 +71,18 @@ CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
 CONFIG_NETDEVICES=y
 CONFIG_MII=y
-CONFIG_SMSC_PHY=y
-CONFIG_NET_ETHERNET=y
 CONFIG_MACB=y
-# CONFIG_NETDEV_1000 is not set
+CONFIG_SMSC_PHY=y
-# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
-CONFIG_USB_ZD1201=m
 CONFIG_INPUT_POLLDEV=m
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=240
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320
 CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
 CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_ADS7846=y
-CONFIG_LEGACY_PTY_COUNT=4
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_ATMEL=y
 CONFIG_SERIAL_ATMEL_CONSOLE=y
 CONFIG_HW_RANDOM=y
@@ -98,6 +91,7 @@ CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_GPIO=y
 CONFIG_SPI=y
 CONFIG_SPI_ATMEL=y
+CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_WATCHDOG_NOWAYOUT=y
@@ -107,9 +101,9 @@ CONFIG_FB_ATMEL=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_ATMEL_LCDC=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FONTS=y
 CONFIG_LOGO=y
 CONFIG_SOUND=y
 CONFIG_SND=y
@@ -124,16 +118,12 @@ CONFIG_SND_ATMEL_AC97C=y
 # CONFIG_SND_SPI is not set
 CONFIG_SND_USB_AUDIO=m
 CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
 CONFIG_USB_MON=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
-CONFIG_USB_ZERO=m
+CONFIG_USB_ATMEL_USBA=y
-CONFIG_USB_ETH=m
+CONFIG_USB_G_SERIAL=y
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
 CONFIG_MMC=y
 CONFIG_SDIO_UART=m
 CONFIG_MMC_ATMELMCI=m
@@ -145,22 +135,18 @@ CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_AT91SAM9=y
-CONFIG_EXT2_FS=y
+CONFIG_EXT4_FS=y
-CONFIG_FUSE_FS=m
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
 CONFIG_UBIFS_FS=y
 CONFIG_UBIFS_FS_ADVANCED_COMPR=y
-CONFIG_CRAMFS=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_NFS_V3_ACL=y
 CONFIG_NFS_V4=y
 CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
 CONFIG_NLS_ISO8859_1=y
-CONFIG_FTRACE=y
+CONFIG_NLS_UTF8=y
 CONFIG_DEBUG_USER=y
 CONFIG_XZ_DEC=y
diff --git a/arch/arm/configs/at91sam9g45_defconfig b/arch/arm/configs/at91sam9g45_defconfig
index 18964cdacd68..08166cd4e7d6 100644
--- a/arch/arm/configs/at91sam9g45_defconfig
+++ b/arch/arm/configs/at91sam9g45_defconfig
@@ -1,4 +1,3 @@
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
@@ -23,8 +22,6 @@ CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
 CONFIG_AT91_SLOW_CLOCK=y
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
-CONFIG_LEDS=y
-CONFIG_LEDS_CPU=y
 CONFIG_UACCESS_WITH_MEMCPY=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
@@ -36,6 +33,9 @@ CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET_XFRM_MODE_BEET is not set
@@ -45,9 +45,6 @@ CONFIG_IPV6=y
 # CONFIG_INET6_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET6_XFRM_MODE_BEET is not set
 CONFIG_IPV6_SIT_6RD=y
-CONFIG_CFG80211=y
-CONFIG_LIB80211=y
-CONFIG_MAC80211=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
@@ -61,13 +58,14 @@ CONFIG_MTD_DATAFLASH=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ATMEL=y
 CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=4
 CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_MISC_DEVICES=y
 CONFIG_ATMEL_PWM=y
 CONFIG_ATMEL_TCLIB=y
+CONFIG_ATMEL_SSC=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
@@ -76,67 +74,40 @@ CONFIG_NETDEVICES=y
 CONFIG_MII=y
 CONFIG_MACB=y
 CONFIG_DAVICOM_PHY=y
-CONFIG_LIBERTAS_THINFIRM=m
+# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_LIBERTAS_THINFIRM_USB=m
-CONFIG_AT76C50X_USB=m
-CONFIG_USB_ZD1201=m
-CONFIG_RTL8187=m
-CONFIG_ATH_COMMON=m
-CONFIG_ATH9K=m
-CONFIG_CARL9170=m
-CONFIG_B43=m
-CONFIG_B43_PHY_N=y
-CONFIG_LIBERTAS=m
-CONFIG_LIBERTAS_USB=m
-CONFIG_LIBERTAS_SDIO=m
-CONFIG_LIBERTAS_SPI=m
-CONFIG_RT2X00=m
-CONFIG_RT2500USB=m
-CONFIG_RT73USB=m
-CONFIG_RT2800USB=m
-CONFIG_RT2800USB_RT53XX=y
-CONFIG_RT2800USB_UNKNOWN=y
-CONFIG_RTL8192CU=m
-CONFIG_WL1251=m
-CONFIG_WL1251_SDIO=m
-CONFIG_WL12XX_MENU=m
-CONFIG_WL12XX=m
-CONFIG_WL12XX_SDIO=m
-CONFIG_ZD1211RW=m
-CONFIG_MWIFIEX=m
-CONFIG_MWIFIEX_SDIO=m
-CONFIG_INPUT_POLLDEV=m
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=480
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=272
 CONFIG_INPUT_JOYDEV=y
 CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_QT1070=m
+CONFIG_KEYBOARD_QT1070=y
-CONFIG_KEYBOARD_QT2160=m
+CONFIG_KEYBOARD_QT2160=y
 CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_ATMEL_MXT=m
 CONFIG_TOUCHSCREEN_ATMEL_TSADCC=y
 # CONFIG_SERIO is not set
-CONFIG_LEGACY_PTY_COUNT=4
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_ATMEL=y
 CONFIG_SERIAL_ATMEL_CONSOLE=y
 CONFIG_HW_RANDOM=y
 CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_GPIO=y
 CONFIG_SPI=y
 CONFIG_SPI_ATMEL=y
 # CONFIG_HWMON is not set
 CONFIG_FB=y
 CONFIG_FB_ATMEL=y
-CONFIG_FB_UDL=m
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_ATMEL_LCDC=y
+CONFIG_BACKLIGHT_ATMEL_PWM=y
 # CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FONTS=y
+CONFIG_LOGO=y
 CONFIG_SOUND=y
 CONFIG_SND=y
 CONFIG_SND_SEQUENCER=y
@@ -148,33 +119,25 @@ CONFIG_SND_PCM_OSS=y
 # CONFIG_SND_ARM is not set
 CONFIG_SND_ATMEL_AC97C=y
 # CONFIG_SND_SPI is not set
-CONFIG_SND_USB_AUDIO=m
+# CONFIG_SND_USB is not set
 # CONFIG_USB_HID is not set
 CONFIG_USB=y
 CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_ACM=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
-CONFIG_USB_ATMEL_USBA=m
+CONFIG_USB_ATMEL_USBA=y
-CONFIG_USB_ZERO=m
+CONFIG_USB_G_MULTI=y
-CONFIG_USB_AUDIO=m
-CONFIG_USB_ETH=m
-CONFIG_USB_ETH_EEM=y
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_CDC_COMPOSITE=m
-CONFIG_USB_G_MULTI=m
 CONFIG_USB_G_MULTI_CDC=y
 CONFIG_MMC=y
 # CONFIG_MMC_BLOCK_BOUNCE is not set
-CONFIG_SDIO_UART=m
 CONFIG_MMC_ATMELMCI=y
-CONFIG_LEDS_ATMEL_PWM=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_LEDS_TRIGGER_GPIO=y
@@ -184,17 +147,14 @@ CONFIG_DMADEVICES=y
 CONFIG_AT_HDMAC=y
 CONFIG_DMATEST=m
 # CONFIG_IOMMU_SUPPORT is not set
-CONFIG_EXT2_FS=y
+CONFIG_EXT4_FS=y
 CONFIG_FANOTIFY=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
-CONFIG_JFFS2_SUMMARY=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
-CONFIG_CRAMFS=m
-CONFIG_SQUASHFS=m
-CONFIG_SQUASHFS_EMBEDDED=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
 CONFIG_NLS_ISO8859_1=y
@@ -203,6 +163,8 @@ CONFIG_STRIP_ASM_SYMS=y
 CONFIG_DEBUG_MEMORY_INIT=y
 # CONFIG_FTRACE is not set
 CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_EARLY_PRINTK=y
 CONFIG_CRYPTO_ECB=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_CRYPTO_USER_API_HASH=m
diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig
index ce987211a609..34e9780e63ba 100644
--- a/arch/arm/configs/bcm2835_defconfig
+++ b/arch/arm/configs/bcm2835_defconfig
@@ -55,14 +55,11 @@ CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_SERIO is not set
-# CONFIG_VT is not set
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_DEVKMEM is not set
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 CONFIG_TTY_PRINTK=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_BCM2835=y
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_BCM2835=y
@@ -70,11 +67,27 @@ CONFIG_SPI=y
 CONFIG_SPI_BCM2835=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
+CONFIG_FB=y
+CONFIG_FB_SIMPLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
 # CONFIG_USB_SUPPORT is not set
 CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_SDHCI_BCM2835=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_LEDS_TRIGGER_TRANSIENT=y
+CONFIG_LEDS_TRIGGER_CAMERA=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig
index e3bf2d65618e..65edf6d47215 100644
--- a/arch/arm/configs/bcm_defconfig
+++ b/arch/arm/configs/bcm_defconfig
@@ -78,6 +78,13 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
 # CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+CONFIG_MMC_UNSAFE_RESUME=y
+CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_MMC_TEST=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_BCM_KONA=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_TRIGGERS=y
diff --git a/arch/arm/configs/bockw_defconfig b/arch/arm/configs/bockw_defconfig
index 6524cdf3b08d..845f5cdf62b5 100644
--- a/arch/arm/configs/bockw_defconfig
+++ b/arch/arm/configs/bockw_defconfig
@@ -31,6 +31,7 @@ CONFIG_CMDLINE="console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp"
 CONFIG_CMDLINE_FORCE=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 # CONFIG_SUSPEND is not set
+CONFIG_PM_RUNTIME=y
 CONFIG_NET=y
 CONFIG_UNIX=y
 CONFIG_INET=y
@@ -48,6 +49,14 @@ CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_STANDALONE is not set
 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
 # CONFIG_FW_LOADER is not set
+CONFIG_MTD=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_M25P80=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
 CONFIG_NETDEVICES=y
 # CONFIG_NET_CADENCE is not set
 # CONFIG_NET_VENDOR_BROADCOM is not set
@@ -71,7 +80,23 @@ CONFIG_SERIAL_SH_SCI_NR_UARTS=6
 CONFIG_SERIAL_SH_SCI_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
 # CONFIG_HWMON is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_I2C=y
+CONFIG_I2C_RCAR=y
+CONFIG_SPI=y
+CONFIG_SPI_SH_HSPI=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_RCAR_PHY=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHI=y
+CONFIG_MMC_SH_MMCIF=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_RX8581=y
 CONFIG_UIO=y
 CONFIG_UIO_PDRV_GENIRQ=y
 # CONFIG_IOMMU_SUPPORT is not set
diff --git a/arch/arm/configs/bonito_defconfig b/arch/arm/configs/bonito_defconfig
deleted file mode 100644
index 54571082d920..000000000000
--- a/arch/arm/configs/bonito_defconfig
+++ /dev/null
@@ -1,72 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=16
-# CONFIG_UTS_NS is not set
-# CONFIG_IPC_NS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_SHMOBILE=y
-CONFIG_ARCH_R8A7740=y
-CONFIG_MACH_BONITO=y
-# CONFIG_SH_TIMER_TMU is not set
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_FORCE_MAX_ZONEORDER=12
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttySC5,115200 earlyprintk=sh-sci.5,115200 ignore_loglevel"
-CONFIG_KEXEC=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-# CONFIG_SUSPEND is not set
-CONFIG_PM_RUNTIME=y
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_ARM_INTEGRATOR=y
-CONFIG_MTD_BLOCK2MTD=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-# CONFIG_SCSI_LOWLEVEL is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_SH_SCI=y
-CONFIG_SERIAL_SH_SCI_NR_UARTS=9
-CONFIG_SERIAL_SH_SCI_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_SH_MOBILE=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-# CONFIG_MFD_SUPPORT is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_UIO=y
-CONFIG_UIO_PDRV=y
-CONFIG_UIO_PDRV_GENIRQ=y
-# CONFIG_DNOTIFY is not set
-# CONFIG_INOTIFY_USER is not set
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-# CONFIG_ENABLE_MUST_CHECK is not set
-# CONFIG_ARM_UNWIND is not set
diff --git a/arch/arm/configs/clps711x_defconfig b/arch/arm/configs/clps711x_defconfig
index 1cd94c36321f..9e8c8316d6b0 100644
--- a/arch/arm/configs/clps711x_defconfig
+++ b/arch/arm/configs/clps711x_defconfig
@@ -31,21 +31,18 @@ CONFIG_EP7211_DONGLE=y
 # CONFIG_WIRELESS is not set
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
 CONFIG_MTD_JEDECPROBE=y
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_AUTCPU12=y
 CONFIG_MTD_PLATRAM=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_GPIO=y
 CONFIG_NETDEVICES=y
 # CONFIG_NET_CADENCE is not set
 # CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
 CONFIG_CS89x0=y
 CONFIG_CS89x0_PLATFORM=y
 # CONFIG_NET_VENDOR_FARADAY is not set
@@ -63,7 +60,11 @@ CONFIG_CS89x0_PLATFORM=y
 # CONFIG_VT is not set
 CONFIG_SERIAL_CLPS711X_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_GPIO=y
 CONFIG_SPI=y
+CONFIG_SPI_CLPS711X=y
+CONFIG_GPIO_CLPS711X=y
 CONFIG_GPIO_GENERIC_PLATFORM=y
 # CONFIG_HWMON is not set
 CONFIG_FB=y
@@ -87,4 +88,3 @@ CONFIG_DEBUG_LL=y
 CONFIG_EARLY_PRINTK=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 # CONFIG_CRYPTO_HW is not set
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/da8xx_omapl_defconfig b/arch/arm/configs/da8xx_omapl_defconfig
index 7c868139bdb0..1571bea48bed 100644
--- a/arch/arm/configs/da8xx_omapl_defconfig
+++ b/arch/arm/configs/da8xx_omapl_defconfig
@@ -102,6 +102,8 @@ CONFIG_SND_SOC=m
 CONFIG_SND_DAVINCI_SOC=m
 # CONFIG_HID_SUPPORT is not set
 # CONFIG_USB_SUPPORT is not set
+CONFIG_DMADEVICES=y
+CONFIG_TI_EDMA=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 CONFIG_XFS_FS=m
diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig
index c86fd75e181a..ab2f7378352c 100644
--- a/arch/arm/configs/davinci_all_defconfig
+++ b/arch/arm/configs/davinci_all_defconfig
@@ -162,6 +162,8 @@ CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=m
 CONFIG_LEDS_TRIGGER_HEARTBEAT=m
 CONFIG_RTC_CLASS=y
+CONFIG_DMADEVICES=y
+CONFIG_TI_EDMA=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 CONFIG_XFS_FS=m
diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig
index 227abf9cc601..ad7dfbbafa45 100644
--- a/arch/arm/configs/exynos_defconfig
+++ b/arch/arm/configs/exynos_defconfig
@@ -50,6 +50,7 @@ CONFIG_USB_USBNET=y
 CONFIG_USB_NET_SMSC75XX=y
 CONFIG_USB_NET_SMSC95XX=y
 CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_GPIO=y
 CONFIG_KEYBOARD_CROS_EC=y
 # CONFIG_MOUSE_PS2 is not set
 CONFIG_MOUSE_CYAPA=y
@@ -104,6 +105,8 @@ CONFIG_MMC_SDHCI_S3C=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_IDMAC=y
 CONFIG_MMC_DW_EXYNOS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_S3C=y
 CONFIG_COMMON_CLK_MAX77686=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 6ec010f248b5..06686e7303a9 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -37,6 +37,8 @@ CONFIG_MACH_IMX51_DT=y
 CONFIG_MACH_EUKREA_CPUIMX51SD=y
 CONFIG_SOC_IMX53=y
 CONFIG_SOC_IMX6Q=y
+CONFIG_SOC_IMX6SL=y
+CONFIG_SOC_VF610=y
 CONFIG_MXC_PWM=y
 CONFIG_SMP=y
 CONFIG_VMSPLIT_2G=y
@@ -47,6 +49,7 @@ CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
 CONFIG_VFP=y
 CONFIG_NEON=y
 CONFIG_BINFMT_MISC=m
+CONFIG_PM_RUNTIME=y
 CONFIG_PM_DEBUG=y
 CONFIG_PM_TEST_SUSPEND=y
 CONFIG_NET=y
@@ -170,6 +173,7 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_LCD_L4F00242T03=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_PWM=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
 CONFIG_FONTS=y
@@ -182,6 +186,7 @@ CONFIG_SND_SOC=y
 CONFIG_SND_IMX_SOC=y
 CONFIG_SND_SOC_PHYCORE_AC97=y
 CONFIG_SND_SOC_EUKREA_TLV320=y
+CONFIG_SND_SOC_IMX_WM8962=y
 CONFIG_SND_SOC_IMX_SGTL5000=y
 CONFIG_SND_SOC_IMX_MC13783=y
 CONFIG_USB=y
@@ -208,10 +213,15 @@ CONFIG_IMX_SDMA=y
 CONFIG_MXS_DMA=y
 CONFIG_STAGING=y
 CONFIG_DRM_IMX=y
+CONFIG_DRM_IMX_TVE=y
+CONFIG_DRM_IMX_FB_HELPER=y
+CONFIG_DRM_IMX_PARALLEL_DISPLAY=y
 CONFIG_DRM_IMX_IPUV3_CORE=y
 CONFIG_DRM_IMX_IPUV3=y
 CONFIG_COMMON_CLK_DEBUG=y
 # CONFIG_IOMMU_SUPPORT is not set
+CONFIG_PWM=y
+CONFIG_PWM_IMX=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_POSIX_ACL=y
diff --git a/arch/arm/configs/keystone_defconfig b/arch/arm/configs/keystone_defconfig
new file mode 100644
index 000000000000..62e968cac9dc
--- /dev/null
+++ b/arch/arm/configs/keystone_defconfig
@@ -0,0 +1,157 @@
+# CONFIG_SWAP is not set
+CONFIG_POSIX_MQUEUE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_ELF_CORE is not set
+# CONFIG_BASE_FULL is not set
+CONFIG_EMBEDDED=y
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=y
+CONFIG_KPROBES=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_ARCH_KEYSTONE=y
+CONFIG_ARM_LPAE=y
+CONFIG_SMP=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+# CONFIG_SUSPEND is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_UNIX_DIAG=y
+CONFIG_XFRM_USER=y
+CONFIG_XFRM_SUB_POLICY=y
+CONFIG_XFRM_STATISTICS=y
+CONFIG_NET_KEY=y
+CONFIG_NET_KEY_MIGRATE=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_NET_IPIP=y
+CONFIG_NET_IPGRE_DEMUX=y
+CONFIG_NET_IPGRE=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
+CONFIG_IP_PIMSM_V2=y
+CONFIG_INET_AH=y
+CONFIG_INET_IPCOMP=y
+CONFIG_IPV6=y
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_IPV6_MROUTE=y
+CONFIG_IPV6_PIMSM_V2=y
+CONFIG_NETFILTER=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
+CONFIG_NETFILTER_XT_TARGET_MARK=y
+CONFIG_NETFILTER_XT_MATCH_COMMENT=y
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_CPU=y
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+CONFIG_NETFILTER_XT_MATCH_LENGTH=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_AH=y
+CONFIG_IP_NF_MATCH_ECN=y
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_TARGET_ULOG=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_TARGET_CLUSTERIP=y
+CONFIG_IP_NF_TARGET_ECN=y
+CONFIG_IP_NF_TARGET_TTL=y
+CONFIG_IP_NF_RAW=y
+CONFIG_IP_NF_ARPTABLES=y
+CONFIG_IP_NF_ARPFILTER=y
+CONFIG_IP_NF_ARP_MANGLE=y
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP_SCTP=y
+CONFIG_VLAN_8021Q=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_CMA=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_PLATRAM=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_PROC_DEVICETREE=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_EEPROM_AT24=y
+CONFIG_NETDEVICES=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+CONFIG_SPI=y
+CONFIG_SPI_SPIDEV=y
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+# CONFIG_USB_SUPPORT is not set
+CONFIG_DMADEVICES=y
+CONFIG_COMMON_CLK_DEBUG=y
+CONFIG_MEMORY=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_WBUF_VERIFY=y
+CONFIG_UBIFS_FS=y
+CONFIG_CRAMFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+CONFIG_NFSD_V3_ACL=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_USER=y
+CONFIG_CRYPTO_USER=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_AUTHENC=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=y
+CONFIG_CRYPTO_XCBC=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_ANSI_CPRNG=y
+CONFIG_CRYPTO_USER_API_HASH=y
+CONFIG_CRYPTO_USER_API_SKCIPHER=y
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index a1d8252e9ec7..0f2aa61911a3 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -1,4 +1,3 @@
-CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
@@ -31,6 +30,7 @@ CONFIG_MACH_T5325=y
 CONFIG_MACH_TS219=y
 CONFIG_MACH_TS41X=y
 CONFIG_MACH_CLOUDBOX_DT=y
+CONFIG_MACH_DB88F628X_BP_DT=y
 CONFIG_MACH_DLINK_KIRKWOOD_DT=y
 CONFIG_MACH_DOCKSTAR_DT=y
 CONFIG_MACH_DREAMPLUG_DT=y
@@ -50,14 +50,19 @@ CONFIG_MACH_NETSPACE_V2_DT=y
 CONFIG_MACH_NSA310_DT=y
 CONFIG_MACH_OPENBLOCKS_A6_DT=y
 CONFIG_MACH_READYNAS_DT=y
+CONFIG_MACH_SHEEVAPLUG_DT=y
 CONFIG_MACH_TOPKICK_DT=y
 CONFIG_MACH_TS219_DT=y
 # CONFIG_CPU_FEROCEON_OLD_ID is not set
+CONFIG_PCI_MVEBU=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_STAT_DETAILS=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
 CONFIG_CPU_IDLE=y
 CONFIG_NET=y
 CONFIG_PACKET=y
@@ -68,14 +73,12 @@ CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
 # CONFIG_IPV6 is not set
-CONFIG_NET_DSA=y
 CONFIG_NET_PKTGEN=m
 CONFIG_CFG80211=y
 CONFIG_MAC80211=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
 CONFIG_MTD_JEDECPROBE=y
@@ -140,6 +143,7 @@ CONFIG_HID_TOPSEED=y
 CONFIG_HID_THRUSTMASTER=y
 CONFIG_HID_ZEROPLUS=y
 CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
 CONFIG_USB_PRINTER=m
diff --git a/arch/arm/configs/kzm9g_defconfig b/arch/arm/configs/kzm9g_defconfig
index f6e585b353a4..1ad028023a64 100644
--- a/arch/arm/configs/kzm9g_defconfig
+++ b/arch/arm/configs/kzm9g_defconfig
@@ -84,9 +84,12 @@ CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_SH_MOBILE=y
 CONFIG_GPIO_PCF857X=y
 # CONFIG_HWMON is not set
+CONFIG_MFD_AS3711=y
 CONFIG_REGULATOR=y
+CONFIG_REGULATOR_AS3711=y
 CONFIG_FB=y
 CONFIG_FB_SH_MOBILE_LCDC=y
+CONFIG_BACKLIGHT_AS3711=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_LOGO=y
 CONFIG_FB_SH_MOBILE_MERAM=y
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 2e67a272df70..6e572c64cf5a 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -1,83 +1,171 @@
-CONFIG_EXPERIMENTAL=y
+CONFIG_IRQ_DOMAIN_DEBUG=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BLK_DEV_INITRD=y
 CONFIG_ARCH_MVEBU=y
 CONFIG_MACH_ARMADA_370=y
-CONFIG_ARCH_SIRF=y
 CONFIG_MACH_ARMADA_XP=y
+CONFIG_ARCH_BCM=y
+CONFIG_GPIO_PCA953X=y
 CONFIG_ARCH_HIGHBANK=y
+CONFIG_ARCH_KEYSTONE=y
+CONFIG_ARCH_MXC=y
+CONFIG_MACH_IMX51_DT=y
+CONFIG_SOC_IMX53=y
+CONFIG_SOC_IMX6Q=y
+CONFIG_SOC_IMX6SL=y
+CONFIG_SOC_VF610=y
+CONFIG_ARCH_OMAP3=y
+CONFIG_ARCH_OMAP4=y
+CONFIG_SOC_OMAP5=y
+CONFIG_SOC_AM33XX=y
+CONFIG_SOC_AM43XX=y
+CONFIG_ARCH_ROCKCHIP=y
 CONFIG_ARCH_SOCFPGA=y
-CONFIG_ARCH_SUNXI=y
-CONFIG_ARCH_WM8850=y
-# CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set
-CONFIG_ARCH_ZYNQ=y
-CONFIG_ARM_ERRATA_754322=y
 CONFIG_PLAT_SPEAR=y
 CONFIG_ARCH_SPEAR13XX=y
 CONFIG_MACH_SPEAR1310=y
 CONFIG_MACH_SPEAR1340=y
+CONFIG_ARCH_STI=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_ARCH_SIRF=y
+CONFIG_ARCH_TEGRA=y
+CONFIG_ARCH_TEGRA_2x_SOC=y
+CONFIG_ARCH_TEGRA_3x_SOC=y
+CONFIG_ARCH_TEGRA_114_SOC=y
+CONFIG_TEGRA_PCI=y
+CONFIG_TEGRA_EMC_SCALING_ENABLE=y
+CONFIG_ARCH_U8500=y
+CONFIG_MACH_SNOWBALL=y
+CONFIG_MACH_UX500_DT=y
+CONFIG_ARCH_VEXPRESS=y
+CONFIG_ARCH_VEXPRESS_CA9X4=y
+CONFIG_ARCH_VIRT=y
+CONFIG_ARCH_WM8850=y
+CONFIG_ARCH_ZYNQ=y
 CONFIG_SMP=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_AEABI=y
-CONFIG_HIGHMEM=y
 CONFIG_HIGHPTE=y
 CONFIG_ARM_APPENDED_DTB=y
-CONFIG_VFP=y
-CONFIG_NEON=y
 CONFIG_NET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_OMAP_OCP2SCP=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_ATA=y
+CONFIG_SATA_AHCI_PLATFORM=y
 CONFIG_SATA_HIGHBANK=y
 CONFIG_SATA_MV=y
-CONFIG_SATA_AHCI_PLATFORM=y
 CONFIG_NETDEVICES=y
+CONFIG_SUN4I_EMAC=y
 CONFIG_NET_CALXEDA_XGMAC=y
+CONFIG_KS8851=y
 CONFIG_SMSC911X=y
 CONFIG_STMMAC_ETH=y
+CONFIG_MDIO_SUN4I=y
+CONFIG_KEYBOARD_SPEAR=y
 CONFIG_SERIO_AMBAKMI=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_DW=y
-CONFIG_KEYBOARD_SPEAR=y
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_SERIAL_SIRFSOC=y
 CONFIG_SERIAL_SIRFSOC_CONSOLE=y
+CONFIG_SERIAL_TEGRA=y
+CONFIG_SERIAL_IMX=y
+CONFIG_SERIAL_IMX_CONSOLE=y
 CONFIG_SERIAL_VT8500=y
 CONFIG_SERIAL_VT8500_CONSOLE=y
-CONFIG_IPMI_HANDLER=y
+CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_IPMI_SI=y
+CONFIG_SERIAL_OMAP=y
-CONFIG_I2C=y
+CONFIG_SERIAL_OMAP_CONSOLE=y
+CONFIG_SERIAL_XILINX_PS_UART=y
+CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
+CONFIG_SERIAL_FSL_LPUART=y
+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
 CONFIG_I2C_DESIGNWARE_PLATFORM=y
 CONFIG_I2C_SIRF=y
+CONFIG_I2C_TEGRA=y
 CONFIG_SPI=y
+CONFIG_SPI_OMAP24XX=y
 CONFIG_SPI_PL022=y
 CONFIG_SPI_SIRF=y
-CONFIG_GPIO_PL061=y
+CONFIG_SPI_TEGRA114=y
-CONFIG_FB=y
+CONFIG_SPI_TEGRA20_SLINK=y
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_TWL4030=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_AB8500=y
+CONFIG_REGULATOR_TPS51632=y
+CONFIG_REGULATOR_TPS62360=y
+CONFIG_REGULATOR_TWL4030=y
+CONFIG_REGULATOR_VEXPRESS=y
+CONFIG_DRM=y
+CONFIG_TEGRA_HOST1X=y
+CONFIG_DRM_TEGRA=y
 CONFIG_FB_ARMCLCD=y
 CONFIG_FB_WM8505=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FB_SIMPLE=y
 CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
 CONFIG_USB_ISP1760_HCD=y
 CONFIG_USB_STORAGE=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_AB8500_USB=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_OMAP_USB2=y
+CONFIG_OMAP_USB3=y
+CONFIG_SAMSUNG_USB2PHY=y
+CONFIG_SAMSUNG_USB3PHY=y
+CONFIG_USB_GPIO_VBUS=y
+CONFIG_USB_ISP1301=y
+CONFIG_USB_MXS_PHY=y
 CONFIG_MMC=y
 CONFIG_MMC_ARMMMCI=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_TEGRA=y
 CONFIG_MMC_SDHCI_SPEAR=y
-CONFIG_MMC_WMT=y
+CONFIG_MMC_OMAP=y
+CONFIG_MMC_OMAP_HS=y
 CONFIG_EDAC=y
 CONFIG_EDAC_MM_EDAC=y
 CONFIG_EDAC_HIGHBANK_MC=y
 CONFIG_EDAC_HIGHBANK_L2=y
 CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_TWL4030=y
 CONFIG_RTC_DRV_PL031=y
 CONFIG_RTC_DRV_VT8500=y
-CONFIG_PWM=y
+CONFIG_RTC_DRV_TEGRA=y
-CONFIG_PWM_VT8500=y
 CONFIG_DMADEVICES=y
-CONFIG_PL330_DMA=y
-CONFIG_SIRF_DMA=y
 CONFIG_DW_DMAC=y
+CONFIG_TEGRA20_APB_DMA=y
+CONFIG_STE_DMA40=y
+CONFIG_SIRF_DMA=y
+CONFIG_TI_EDMA=y
+CONFIG_PL330_DMA=y
+CONFIG_IMX_SDMA=y
+CONFIG_IMX_DMA=y
+CONFIG_MXS_DMA=y
+CONFIG_DMA_OMAP=y
+CONFIG_PWM=y
+CONFIG_PWM_VT8500=y
+CONFIG_EXT4_FS=y
+CONFIG_TMPFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_LOCKUP_DETECTOR=y
diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
index f3e8ae001ff1..731814e2c189 100644
--- a/arch/arm/configs/mvebu_defconfig
+++ b/arch/arm/configs/mvebu_defconfig
@@ -13,6 +13,8 @@ CONFIG_MACH_ARMADA_370=y
 CONFIG_MACH_ARMADA_XP=y
 # CONFIG_CACHE_L2X0 is not set
 # CONFIG_SWP_EMULATE is not set
+CONFIG_PCI=y
+CONFIG_PCI_MVEBU=y
 CONFIG_SMP=y
 CONFIG_AEABI=y
 CONFIG_HIGHMEM=y
@@ -60,6 +62,8 @@ CONFIG_USB_SUPPORT=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_MMC=y
 CONFIG_MMC_MVSDIO=y
 CONFIG_NEW_LEDS=y
@@ -96,5 +100,3 @@ CONFIG_TIMER_STATS=y
 # CONFIG_DEBUG_BUGVERBOSE is not set
 CONFIG_DEBUG_INFO=y
 CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
-CONFIG_EARLY_PRINTK=y
diff --git a/arch/arm/configs/nhk8815_defconfig b/arch/arm/configs/nhk8815_defconfig
index b01e7632ed2e..263ae3869e32 100644
--- a/arch/arm/configs/nhk8815_defconfig
+++ b/arch/arm/configs/nhk8815_defconfig
@@ -1,6 +1,8 @@
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
@@ -48,7 +50,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
 CONFIG_MTD_TESTS=m
 CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_NAND_ECC_SMC=y
 CONFIG_MTD_NAND=y
@@ -81,6 +82,7 @@ CONFIG_PPP_SYNC_TTY=m
 # CONFIG_INPUT_MOUSEDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_GPIO=y
 # CONFIG_MOUSE_PS2 is not set
 # CONFIG_SERIO is not set
 # CONFIG_LEGACY_PTYS is not set
@@ -93,9 +95,16 @@ CONFIG_I2C_GPIO=y
 CONFIG_I2C_NOMADIK=y
 CONFIG_DEBUG_GPIO=y
 # CONFIG_HWMON is not set
+CONFIG_REGULATOR=y
 CONFIG_MMC=y
-CONFIG_MMC_CLKGATE=y
+CONFIG_MMC_UNSAFE_RESUME=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
 CONFIG_MMC_ARMMMCI=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_PL031=y
 CONFIG_DMADEVICES=y
diff --git a/arch/arm/configs/omap1_defconfig b/arch/arm/configs/omap1_defconfig
index 9940f7b4e438..d74edbad18fc 100644
--- a/arch/arm/configs/omap1_defconfig
+++ b/arch/arm/configs/omap1_defconfig
@@ -26,7 +26,8 @@ CONFIG_ARCH_OMAP=y
 CONFIG_ARCH_OMAP1=y
 CONFIG_OMAP_RESET_CLOCKS=y
 # CONFIG_OMAP_MUX is not set
-CONFIG_OMAP_MBOX_FWK=y
+CONFIG_MAILBOX=y
+CONFIG_OMAP1_MBOX=y
 CONFIG_OMAP_32K_TIMER=y
 CONFIG_OMAP_DM_TIMER=y
 CONFIG_ARCH_OMAP730=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index abbe31937c65..5339e6a4d639 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -22,6 +22,10 @@ CONFIG_MODULE_SRCVERSION_ALL=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_ARCH_MULTI_V6=y
 CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_ARCH_OMAP2=y
+CONFIG_ARCH_OMAP3=y
+CONFIG_ARCH_OMAP4=y
+CONFIG_SOC_AM33XX=y
 CONFIG_OMAP_RESET_CLOCKS=y
 CONFIG_OMAP_MUX_DEBUG=y
 CONFIG_ARCH_VEXPRESS_CA9X4=y
@@ -34,6 +38,8 @@ CONFIG_NR_CPUS=2
 CONFIG_LEDS=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
 CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyO2,115200"
 CONFIG_KEXEC=y
 CONFIG_FPE_NWFPE=y
@@ -152,6 +158,13 @@ CONFIG_W1=y
 CONFIG_POWER_SUPPLY=y
 CONFIG_SENSORS_LM75=m
 CONFIG_WATCHDOG=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_GOV_FAIR_SHARE=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_GOV_USER_SPACE=y
+CONFIG_CPU_THERMAL=y
 CONFIG_OMAP_WATCHDOG=y
 CONFIG_TWL4030_WATCHDOG=y
 CONFIG_MFD_TPS65217=y
@@ -210,6 +223,8 @@ CONFIG_USB_WDM=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_LIBUSUAL=y
 CONFIG_USB_TEST=y
+CONFIG_USB_PHY=y
+CONFIG_NOP_USB_XCEIV=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DEBUG=y
 CONFIG_USB_GADGET_DEBUG_FILES=y
@@ -236,7 +251,13 @@ CONFIG_RTC_DRV_TWL92330=y
 CONFIG_RTC_DRV_TWL4030=y
 CONFIG_RTC_DRV_OMAP=y
 CONFIG_DMADEVICES=y
+CONFIG_TI_EDMA=y
 CONFIG_DMA_OMAP=y
+CONFIG_TI_SOC_THERMAL=y
+CONFIG_TI_THERMAL=y
+CONFIG_OMAP4_THERMAL=y
+CONFIG_OMAP5_THERMAL=y
+CONFIG_DRA752_THERMAL=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
@@ -284,3 +305,4 @@ CONFIG_SOC_OMAP5=y
 CONFIG_TI_DAVINCI_MDIO=y
 CONFIG_TI_DAVINCI_CPDMA=y
 CONFIG_TI_CPSW=y
+CONFIG_AT803X_PHY=y
diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig
index 4d0dc3c16063..f6e78f83c3c3 100644
--- a/arch/arm/configs/sama5_defconfig
+++ b/arch/arm/configs/sama5_defconfig
@@ -26,7 +26,9 @@ CONFIG_AEABI=y
 CONFIG_UACCESS_WITH_MEMCPY=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARM_APPENDED_DTB=y
 CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw"
+CONFIG_KEXEC=y
 CONFIG_AUTO_ZRELADDR=y
 CONFIG_VFP=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
@@ -39,6 +41,9 @@ CONFIG_UNIX=y
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
 CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET_XFRM_MODE_BEET is not set
@@ -68,6 +73,8 @@ CONFIG_MTD_M25P80=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ATMEL=y
 CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=4
@@ -95,7 +102,19 @@ CONFIG_MACB=y
 # CONFIG_NET_VENDOR_STMICRO is not set
 # CONFIG_NET_VENDOR_WIZNET is not set
 CONFIG_MICREL_PHY=y
-# CONFIG_WLAN is not set
+CONFIG_LIBERTAS_THINFIRM=m
+CONFIG_LIBERTAS_THINFIRM_USB=m
+CONFIG_RTL8187=m
+CONFIG_RT2X00=m
+CONFIG_RT2500USB=m
+CONFIG_RT73USB=m
+CONFIG_RT2800USB=m
+CONFIG_RT2800USB_RT53XX=y
+CONFIG_RT2800USB_RT55XX=y
+CONFIG_RT2800USB_UNKNOWN=y
+CONFIG_MWIFIEX=m
+CONFIG_MWIFIEX_SDIO=m
+CONFIG_MWIFIEX_USB=m
 # CONFIG_INPUT_MOUSEDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
@@ -133,9 +152,13 @@ CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_ACM=y
 CONFIG_USB_STORAGE=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_FTDI_SIO=y
+CONFIG_USB_SERIAL_PL2303=y
 CONFIG_USB_GADGET=y
-CONFIG_USB_AT91=y
+CONFIG_USB_ATMEL_USBA=y
-CONFIG_USB_MASS_STORAGE=m
+CONFIG_USB_G_SERIAL=y
 CONFIG_MMC=y
 # CONFIG_MMC_BLOCK_BOUNCE is not set
 CONFIG_MMC_ATMELMCI=y
@@ -151,18 +174,18 @@ CONFIG_DMADEVICES=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_IIO=y
 CONFIG_AT91_ADC=y
-CONFIG_EXT2_FS=y
+CONFIG_EXT4_FS=y
 CONFIG_FANOTIFY=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
 CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
 CONFIG_NFS_FS=y
 CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
 CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
 CONFIG_STRIP_ASM_SYMS=y
 CONFIG_DEBUG_FS=y
 # CONFIG_SCHED_DEBUG is not set
diff --git a/arch/arm/configs/spear13xx_defconfig b/arch/arm/configs/spear13xx_defconfig
index 1fdb82694ca2..82eaa552ed14 100644
--- a/arch/arm/configs/spear13xx_defconfig
+++ b/arch/arm/configs/spear13xx_defconfig
@@ -61,7 +61,6 @@ CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_PL061=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
-CONFIG_MPCORE_WATCHDOG=y
 # CONFIG_HID_SUPPORT is not set
 CONFIG_USB=y
 # CONFIG_USB_DEVICE_CLASS is not set
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index f7ba316164d4..1effb43dab80 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -21,8 +21,8 @@ CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_PARTITION_ADVANCED=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_TEGRA=y
 CONFIG_GPIO_PCA953X=y
+CONFIG_ARCH_TEGRA=y
 CONFIG_ARCH_TEGRA_2x_SOC=y
 CONFIG_ARCH_TEGRA_3x_SOC=y
 CONFIG_ARCH_TEGRA_114_SOC=y
@@ -36,7 +36,6 @@ CONFIG_HIGHMEM=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_KEXEC=y
-CONFIG_AUTO_ZRELADDR=y
 CONFIG_CPU_FREQ=y
 CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
 CONFIG_CPU_IDLE=y
@@ -81,7 +80,6 @@ CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
 CONFIG_CMA=y
 CONFIG_MTD=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_M25P80=y
 CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
@@ -105,8 +103,8 @@ CONFIG_BRCMFMAC=m
 CONFIG_RT2X00=y
 CONFIG_RT2800USB=m
 CONFIG_INPUT_EVDEV=y
-CONFIG_KEYBOARD_TEGRA=y
 CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_TEGRA=y
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_MPU3050=y
 # CONFIG_LEGACY_PTYS is not set
@@ -121,6 +119,7 @@ CONFIG_I2C_MUX=y
 CONFIG_I2C_MUX_PINCTRL=y
 CONFIG_I2C_TEGRA=y
 CONFIG_SPI=y
+CONFIG_SPI_TEGRA114=y
 CONFIG_SPI_TEGRA20_SFLASH=y
 CONFIG_SPI_TEGRA20_SLINK=y
 CONFIG_GPIO_PCA953X_IRQ=y
@@ -129,14 +128,15 @@ CONFIG_GPIO_TPS6586X=y
 CONFIG_GPIO_TPS65910=y
 CONFIG_POWER_SUPPLY=y
 CONFIG_BATTERY_SBS=y
+CONFIG_CHARGER_TPS65090=y
 CONFIG_POWER_RESET=y
 CONFIG_POWER_RESET_GPIO=y
 CONFIG_SENSORS_LM90=y
-CONFIG_MFD_TPS6586X=y
-CONFIG_MFD_TPS65910=y
 CONFIG_MFD_MAX8907=y
-CONFIG_MFD_TPS65090=y
 CONFIG_MFD_PALMAS=y
+CONFIG_MFD_TPS65090=y
+CONFIG_MFD_TPS6586X=y
+CONFIG_MFD_TPS65910=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
@@ -171,6 +171,7 @@ CONFIG_SND=y
 # CONFIG_SND_USB is not set
 CONFIG_SND_SOC=y
 CONFIG_SND_SOC_TEGRA=y
+CONFIG_SND_SOC_TEGRA_RT5640=y
 CONFIG_SND_SOC_TEGRA_WM8753=y
 CONFIG_SND_SOC_TEGRA_WM8903=y
 CONFIG_SND_SOC_TEGRA_TRIMSLICE=y
@@ -190,7 +191,13 @@ CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
 CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_LEDS_TRIGGER_TRANSIENT=y
+CONFIG_LEDS_TRIGGER_CAMERA=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_MAX8907=y
 CONFIG_RTC_DRV_PALMAS=y
@@ -203,7 +210,6 @@ CONFIG_TEGRA20_APB_DMA=y
 CONFIG_STAGING=y
 CONFIG_SENSORS_ISL29018=y
 CONFIG_SENSORS_ISL29028=y
-CONFIG_AK8975=y
 CONFIG_MFD_NVEC=y
 CONFIG_KEYBOARD_NVEC=y
 CONFIG_SERIO_NVEC_PS2=y
@@ -213,6 +219,7 @@ CONFIG_TEGRA_IOMMU_GART=y
 CONFIG_TEGRA_IOMMU_SMMU=y
 CONFIG_MEMORY=y
 CONFIG_IIO=y
+CONFIG_AK8975=y
 CONFIG_PWM=y
 CONFIG_PWM_TEGRA=y
 CONFIG_EXT2_FS=y
diff --git a/arch/arm/configs/u300_defconfig b/arch/arm/configs/u300_defconfig
index 374000ec4e4e..fd81a1b99cce 100644
--- a/arch/arm/configs/u300_defconfig
+++ b/arch/arm/configs/u300_defconfig
@@ -1,7 +1,8 @@
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_EXPERT=y
 # CONFIG_AIO is not set
@@ -11,12 +12,9 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_LBDAF is not set
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_CFQ is not set
+# CONFIG_ARCH_MULTI_V7 is not set
 CONFIG_ARCH_U300=y
-CONFIG_MACH_U300=y
-CONFIG_MACH_U300_BS335=y
 CONFIG_MACH_U300_SPIDUMMY=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
@@ -44,14 +42,15 @@ CONFIG_I2C=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_FB=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 # CONFIG_LCD_CLASS_DEVICE is not set
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_HID_SUPPORT is not set
 # CONFIG_USB_SUPPORT is not set
 CONFIG_MMC=y
-CONFIG_MMC_CLKGATE=y
+CONFIG_MMC_UNSAFE_RESUME=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
 CONFIG_MMC_ARMMMCI=y
 CONFIG_RTC_CLASS=y
 # CONFIG_RTC_HCTOSYS is not set
@@ -70,4 +69,3 @@ CONFIG_DEBUG_FS=y
 CONFIG_TIMER_STATS=y
 # CONFIG_DEBUG_PREEMPT is not set
 CONFIG_DEBUG_INFO=y
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
index c037aa1065b7..a0025dc13021 100644
--- a/arch/arm/configs/u8500_defconfig
+++ b/arch/arm/configs/u8500_defconfig
@@ -1,6 +1,8 @@
-CONFIG_EXPERIMENTAL=y
+CONFIG_HIGHMEM=y
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_KALLSYMS_ALL=y
 CONFIG_MODULES=y
@@ -9,10 +11,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_ARCH_U8500=y
 CONFIG_MACH_HREFV60=y
 CONFIG_MACH_SNOWBALL=y
-CONFIG_MACH_U5500=y
 CONFIG_MACH_UX500_DT=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
 CONFIG_SMP=y
 CONFIG_NR_CPUS=2
 CONFIG_PREEMPT=y
@@ -20,6 +19,7 @@ CONFIG_AEABI=y
 CONFIG_CMDLINE="root=/dev/ram0 console=ttyAMA2,115200n8"
 CONFIG_CPU_FREQ=y
 CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+CONFIG_CPU_IDLE=y
 CONFIG_VFP=y
 CONFIG_NEON=y
 CONFIG_PM_RUNTIME=y
@@ -36,7 +36,6 @@ CONFIG_CAIF=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=65536
-CONFIG_AB8500_PWM=y
 CONFIG_SENSORS_BH1780=y
 CONFIG_NETDEVICES=y
 CONFIG_SMSC911X=y
@@ -60,35 +59,39 @@ CONFIG_VT_HW_CONSOLE_BINDING=y
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_NOMADIK=y
 CONFIG_SPI=y
 CONFIG_SPI_PL022=y
 CONFIG_GPIO_STMPE=y
 CONFIG_GPIO_TC3589X=y
-# CONFIG_POWER_SUPPLY is not set
-# CONFIG_AB8500_BM is not set
-# CONFIG_AB8500_BATTERY_THERM_ON_BATCTRL is not set
 CONFIG_THERMAL=y
 CONFIG_CPU_THERMAL=y
+CONFIG_WATCHDOG=y
 CONFIG_MFD_STMPE=y
 CONFIG_MFD_TC3589X=y
-CONFIG_AB5500_CORE=y
-CONFIG_AB8500_CORE=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_AB8500=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_GPIO=y
-# CONFIG_HID_SUPPORT is not set
+CONFIG_REGULATOR_AB8500=y
-CONFIG_USB_GADGET=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_UX500=y
+CONFIG_SND_SOC_UX500_MACH_MOP500=y
+CONFIG_USB=y
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_UX500=y
+CONFIG_USB_PHY=y
 CONFIG_AB8500_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MUSB_HDRC=y
+CONFIG_USB_ETH=m
 CONFIG_MMC=y
-CONFIG_MMC_CLKGATE=y
+CONFIG_MMC_UNSAFE_RESUME=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
 CONFIG_MMC_ARMMMCI=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_LM3530=y
-CONFIG_LEDS_LP5521=y
 CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_LP5521=y
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_RTC_CLASS=y
@@ -108,7 +111,6 @@ CONFIG_EXT4_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
 CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_CONFIGFS_FS=m
 # CONFIG_MISC_FILESYSTEMS is not set
 CONFIG_NFS_FS=y
 CONFIG_ROOT_NFS=y
@@ -122,3 +124,7 @@ CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_INFO=y
 # CONFIG_FTRACE is not set
 CONFIG_DEBUG_USER=y
+CONFIG_CRYPTO_DEV_UX500=y
+CONFIG_CRYPTO_DEV_UX500_CRYP=y
+CONFIG_CRYPTO_DEV_UX500_HASH=y
+CONFIG_CRYPTO_DEV_UX500_DEBUG=y
diff --git a/arch/arm/include/asm/a.out-core.h b/arch/arm/include/asm/a.out-core.h
deleted file mode 100644
index 92f10cb5c70c..000000000000
--- a/arch/arm/include/asm/a.out-core.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* a.out coredump register dumper
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_A_OUT_CORE_H
-#define _ASM_A_OUT_CORE_H
-#ifdef __KERNEL__
-#include <linux/user.h>
-#include <linux/elfcore.h>
-/*
- * fill in the user structure for an a.out core dump
- */
-static inline void aout_dump_thread(struct pt_regs *regs, struct user *dump)
-{
-        struct task_struct *tsk = current;
-        dump->magic = CMAGIC;
-        dump->start_code = tsk->mm->start_code;
-        dump->start_stack = regs->ARM_sp & ~(PAGE_SIZE - 1);
-        dump->u_tsize = (tsk->mm->end_code - tsk->mm->start_code) >> PAGE_SHIFT;
-        dump->u_dsize = (tsk->mm->brk - tsk->mm->start_data + PAGE_SIZE - 1) >> PAGE_SHIFT;
-        dump->u_ssize = 0;
-        memset(dump->u_debugreg, 0, sizeof(dump->u_debugreg));
-        if (dump->start_stack < 0x04000000)
-                dump->u_ssize = (0x04000000 - dump->start_stack) >> PAGE_SHIFT;
-        dump->regs = *regs;
-        dump->u_fpvalid = dump_fpu (regs, &dump->u_fp);
-}
-#endif /* __KERNEL__ */
-#endif /* _ASM_A_OUT_CORE_H */
diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
index 7c1bfc0aea0c..e406d575c94f 100644
--- a/arch/arm/include/asm/arch_timer.h
+++ b/arch/arm/include/asm/arch_timer.h
@@ -80,15 +80,6 @@ static inline u32 arch_timer_get_cntfrq(void)
        return val;
 }
-static inline u64 arch_counter_get_cntpct(void)
-{
-        u64 cval;
-        isb();
-        asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval));
-        return cval;
-}
 static inline u64 arch_counter_get_cntvct(void)
 {
        u64 cval;
@@ -98,7 +89,7 @@ static inline u64 arch_counter_get_cntvct(void)
        return cval;
 }
-static inline void __cpuinit arch_counter_set_user_access(void)
+static inline void arch_counter_set_user_access(void)
 {
        u32 cntkctl;
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 05ee9eebad6b..a5fef710af32 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -136,7 +136,11 @@
 * assumes FIQs are enabled, and that the processor is in SVC mode.
 */
        .macro  save_and_disable_irqs, oldcpsr
+#ifdef CONFIG_CPU_V7M
+        mrs     \oldcpsr, primask
+#else
        mrs     \oldcpsr, cpsr
+#endif
        disable_irq
        .endm
@@ -150,7 +154,11 @@
 * guarantee that this will preserve the flags.
 */
        .macro  restore_irqs_notrace, oldcpsr
+#ifdef CONFIG_CPU_V7M
+        msr     primask, \oldcpsr
+#else
        msr     cpsr_c, \oldcpsr
+#endif
        .endm
        .macro restore_irqs, oldcpsr
@@ -229,7 +237,14 @@
 #endif
        .endm
-#ifdef CONFIG_THUMB2_KERNEL
+#if defined(CONFIG_CPU_V7M)
+        /*
+         * setmode is used to assert to be in svc mode during boot. For v7-M
+         * this is done in __v7m_setup, so setmode can be empty here.
+         */
+        .macro  setmode, mode, reg
+        .endm
+#elif defined(CONFIG_THUMB2_KERNEL)
        .macro  setmode, mode, reg
        mov     \reg, #\mode
        msr     cpsr_c, \reg
diff --git a/arch/arm/include/asm/cp15.h b/arch/arm/include/asm/cp15.h
index 1f3262e99d81..6493802f880a 100644
--- a/arch/arm/include/asm/cp15.h
+++ b/arch/arm/include/asm/cp15.h
@@ -23,6 +23,11 @@
 #define CR_RR   (1 << 14)       /* Round Robin cache replacement        */
 #define CR_L4   (1 << 15)       /* LDR pc can set T bit                 */
 #define CR_DT   (1 << 16)
+#ifdef CONFIG_MMU
+#define CR_HA   (1 << 17)       /* Hardware management of Access Flag   */
+#else
+#define CR_BR   (1 << 17)       /* MPU Background region enable (PMSA)  */
+#endif
 #define CR_IT   (1 << 18)
 #define CR_ST   (1 << 19)
 #define CR_FI   (1 << 21)       /* Fast interrupt (lower latency mode)  */
@@ -61,6 +66,20 @@ static inline void set_cr(unsigned int val)
        isb();
 }
+static inline unsigned int get_auxcr(void)
+{
+        unsigned int val;
+        asm("mrc p15, 0, %0, c1, c0, 1  @ get AUXCR" : "=r" (val));
+        return val;
+}
+static inline void set_auxcr(unsigned int val)
+{
+        asm volatile("mcr p15, 0, %0, c1, c0, 1 @ set AUXCR"
+          : : "r" (val));
+        isb();
+}
 #ifndef CONFIG_SMP
 extern void adjust_cr(unsigned long mask, unsigned long set);
 #endif
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index dba62cb1ad08..9672e978d50d 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -8,8 +8,25 @@
 #define CPUID_CACHETYPE 1
 #define CPUID_TCM       2
 #define CPUID_TLBTYPE   3
+#define CPUID_MPUIR     4
 #define CPUID_MPIDR     5
+#ifdef CONFIG_CPU_V7M
+#define CPUID_EXT_PFR0  0x40
+#define CPUID_EXT_PFR1  0x44
+#define CPUID_EXT_DFR0  0x48
+#define CPUID_EXT_AFR0  0x4c
+#define CPUID_EXT_MMFR0 0x50
+#define CPUID_EXT_MMFR1 0x54
+#define CPUID_EXT_MMFR2 0x58
+#define CPUID_EXT_MMFR3 0x5c
+#define CPUID_EXT_ISAR0 0x60
+#define CPUID_EXT_ISAR1 0x64
+#define CPUID_EXT_ISAR2 0x68
+#define CPUID_EXT_ISAR3 0x6c
+#define CPUID_EXT_ISAR4 0x70
+#define CPUID_EXT_ISAR5 0x74
+#else
 #define CPUID_EXT_PFR0  "c1, 0"
 #define CPUID_EXT_PFR1  "c1, 1"
 #define CPUID_EXT_DFR0  "c1, 2"
@@ -24,6 +41,7 @@
 #define CPUID_EXT_ISAR3 "c2, 3"
 #define CPUID_EXT_ISAR4 "c2, 4"
 #define CPUID_EXT_ISAR5 "c2, 5"
+#endif
 #define MPIDR_SMP_BITMASK (0x3 << 30)
 #define MPIDR_SMP_VALUE (0x2 << 30)
@@ -71,17 +89,38 @@ extern unsigned int processor_id;
                __val;                                                  \
        })
+/*
+ * The memory clobber prevents gcc 4.5 from reordering the mrc before
+ * any is_smp() tests, which can cause undefined instruction aborts on
+ * ARM1136 r0 due to the missing extended CP15 registers.
+ */
 #define read_cpuid_ext(ext_reg)                                         \
        ({                                                              \
                unsigned int __val;                                     \
                asm("mrc        p15, 0, %0, c0, " ext_reg               \
                    : "=r" (__val)                                      \
                    :                                                   \
-                    : "cc");                                            \
+                    : "memory");                                        \
                __val;                                                  \
        })
-#else /* ifdef CONFIG_CPU_CP15 */
+#elif defined(CONFIG_CPU_V7M)
+#include <asm/io.h>
+#include <asm/v7m.h>
+#define read_cpuid(reg)                                                 \
+        ({                                                              \
+                WARN_ON_ONCE(1);                                        \
+                0;                                                      \
+        })
+static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset)
+{
+        return readl(BASEADDR_V7M_SCB + offset);
+}
+#else /* ifdef CONFIG_CPU_CP15 / elif defined (CONFIG_CPU_V7M) */
 /*
 * read_cpuid and read_cpuid_ext should only ever be called on machines that
@@ -108,7 +147,14 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void)
        return read_cpuid(CPUID_ID);
 }
-#else /* ifdef CONFIG_CPU_CP15 */
+#elif defined(CONFIG_CPU_V7M)
+static inline unsigned int __attribute_const__ read_cpuid_id(void)
+{
+        return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID);
+}
+#else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */
 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 {
diff --git a/arch/arm/include/asm/div64.h b/arch/arm/include/asm/div64.h
index fe92ccf1d0b0..191ada6e4d2d 100644
--- a/arch/arm/include/asm/div64.h
+++ b/arch/arm/include/asm/div64.h
@@ -46,7 +46,7 @@
        __rem;                                                  \
 })
-#if __GNUC__ < 4
+#if __GNUC__ < 4 || !defined(CONFIG_AEABI)
 /*
 * gcc versions earlier than 4.0 are simply too problematic for the
diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index 38050b1c4800..56211f2084ef 100644
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -130,4 +130,10 @@ struct mm_struct;
 extern unsigned long arch_randomize_brk(struct mm_struct *mm);
 #define arch_randomize_brk arch_randomize_brk
+#ifdef CONFIG_MMU
+#define ARCH_HAS_SETUP_ADDITIONAL_PAGES 1
+struct linux_binprm;
+int arch_setup_additional_pages(struct linux_binprm *, int);
+#endif
 #endif
diff --git a/arch/arm/include/asm/glue-cache.h b/arch/arm/include/asm/glue-cache.h
index ea289e1435e7..c81adc08b3fb 100644
--- a/arch/arm/include/asm/glue-cache.h
+++ b/arch/arm/include/asm/glue-cache.h
@@ -117,10 +117,37 @@
 # endif
 #endif
+#if defined(CONFIG_CPU_V7M)
+# ifdef _CACHE
+#  define MULTI_CACHE 1
+# else
+#  define _CACHE nop
+# endif
+#endif
 #if !defined(_CACHE) && !defined(MULTI_CACHE)
 #error Unknown cache maintenance model
 #endif
+#ifndef __ASSEMBLER__
+extern inline void nop_flush_icache_all(void) { }
+extern inline void nop_flush_kern_cache_all(void) { }
+extern inline void nop_flush_kern_cache_louis(void) { }
+extern inline void nop_flush_user_cache_all(void) { }
+extern inline void nop_flush_user_cache_range(unsigned long a,
+                unsigned long b, unsigned int c) { }
+extern inline void nop_coherent_kern_range(unsigned long a, unsigned long b) { }
+extern inline int nop_coherent_user_range(unsigned long a,
+                unsigned long b) { return 0; }
+extern inline void nop_flush_kern_dcache_area(void *a, size_t s) { }
+extern inline void nop_dma_flush_range(const void *a, const void *b) { }
+extern inline void nop_dma_map_area(const void *s, size_t l, int f) { }
+extern inline void nop_dma_unmap_area(const void *s, size_t l, int f) { }
+#endif
 #ifndef MULTI_CACHE
 #define __cpuc_flush_icache_all         __glue(_CACHE,_flush_icache_all)
 #define __cpuc_flush_kern_all           __glue(_CACHE,_flush_kern_cache_all)
diff --git a/arch/arm/include/asm/glue-df.h b/arch/arm/include/asm/glue-df.h
index b6e9f2c108b5..6b70f1b46a6e 100644
--- a/arch/arm/include/asm/glue-df.h
+++ b/arch/arm/include/asm/glue-df.h
@@ -95,6 +95,14 @@
 # endif
 #endif
+#ifdef CONFIG_CPU_ABRT_NOMMU
+# ifdef CPU_DABORT_HANDLER
+#  define MULTI_DABORT 1
+# else
+#  define CPU_DABORT_HANDLER nommu_early_abort
+# endif
+#endif
 #ifndef CPU_DABORT_HANDLER
 #error Unknown data abort handler type
 #endif
diff --git a/arch/arm/include/asm/glue-proc.h b/arch/arm/include/asm/glue-proc.h
index 8017e94acc5e..74a8b84f3cb1 100644
--- a/arch/arm/include/asm/glue-proc.h
+++ b/arch/arm/include/asm/glue-proc.h
@@ -230,6 +230,15 @@
 # endif
 #endif
+#ifdef CONFIG_CPU_V7M
+# ifdef CPU_NAME
+#  undef  MULTI_CPU
+#  define MULTI_CPU
+# else
+#  define CPU_NAME cpu_v7m
+# endif
+#endif
 #ifdef CONFIG_CPU_PJ4B
 # ifdef CPU_NAME
 #  undef  MULTI_CPU
diff --git a/arch/arm/include/asm/hardware/iop3xx.h b/arch/arm/include/asm/hardware/iop3xx.h
index ed94b1a366ae..423744bf18eb 100644
--- a/arch/arm/include/asm/hardware/iop3xx.h
+++ b/arch/arm/include/asm/hardware/iop3xx.h
@@ -223,11 +223,12 @@ extern int iop3xx_get_init_atu(void);
 #ifndef __ASSEMBLY__
 #include <linux/types.h>
+#include <linux/reboot.h>
 void iop3xx_map_io(void);
 void iop_init_cp6_handler(void);
 void iop_init_time(unsigned long tickrate);
-void iop3xx_restart(char, const char *);
+void iop3xx_restart(enum reboot_mode, const char *);
 static inline u32 read_tmr0(void)
 {
diff --git a/arch/arm/include/asm/hardware/pci_v3.h b/arch/arm/include/asm/hardware/pci_v3.h
deleted file mode 100644
index 2811c7e2cfdf..000000000000
--- a/arch/arm/include/asm/hardware/pci_v3.h
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- *  arch/arm/include/asm/hardware/pci_v3.h
- *
- *  Internal header file PCI V3 chip
- *
- *  Copyright (C) ARM Limited
- *  Copyright (C) 2000-2001 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef ASM_ARM_HARDWARE_PCI_V3_H
-#define ASM_ARM_HARDWARE_PCI_V3_H
-/* -------------------------------------------------------------------------------
- *  V3 Local Bus to PCI Bridge definitions
- * -------------------------------------------------------------------------------
- *  Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04
- *  All V3 register names are prefaced by V3_ to avoid clashing with any other
- *  PCI definitions.  Their names match the user's manual.
- * 
- *  I'm assuming that I20 is disabled.
- * 
- */
-#define V3_PCI_VENDOR                   0x00000000
-#define V3_PCI_DEVICE                   0x00000002
-#define V3_PCI_CMD                      0x00000004
-#define V3_PCI_STAT                     0x00000006
-#define V3_PCI_CC_REV                   0x00000008
-#define V3_PCI_HDR_CFG                  0x0000000C
-#define V3_PCI_IO_BASE                  0x00000010
-#define V3_PCI_BASE0                    0x00000014
-#define V3_PCI_BASE1                    0x00000018
-#define V3_PCI_SUB_VENDOR               0x0000002C
-#define V3_PCI_SUB_ID                   0x0000002E
-#define V3_PCI_ROM                      0x00000030
-#define V3_PCI_BPARAM                   0x0000003C
-#define V3_PCI_MAP0                     0x00000040
-#define V3_PCI_MAP1                     0x00000044
-#define V3_PCI_INT_STAT                 0x00000048
-#define V3_PCI_INT_CFG                  0x0000004C 
-#define V3_LB_BASE0                     0x00000054
-#define V3_LB_BASE1                     0x00000058
-#define V3_LB_MAP0                      0x0000005E
-#define V3_LB_MAP1                      0x00000062
-#define V3_LB_BASE2                     0x00000064
-#define V3_LB_MAP2                      0x00000066
-#define V3_LB_SIZE                      0x00000068
-#define V3_LB_IO_BASE                   0x0000006E
-#define V3_FIFO_CFG                     0x00000070
-#define V3_FIFO_PRIORITY                0x00000072
-#define V3_FIFO_STAT                    0x00000074
-#define V3_LB_ISTAT                     0x00000076
-#define V3_LB_IMASK                     0x00000077
-#define V3_SYSTEM                       0x00000078
-#define V3_LB_CFG                       0x0000007A
-#define V3_PCI_CFG                      0x0000007C
-#define V3_DMA_PCI_ADR0                 0x00000080
-#define V3_DMA_PCI_ADR1                 0x00000090
-#define V3_DMA_LOCAL_ADR0               0x00000084
-#define V3_DMA_LOCAL_ADR1               0x00000094
-#define V3_DMA_LENGTH0                  0x00000088
-#define V3_DMA_LENGTH1                  0x00000098
-#define V3_DMA_CSR0                     0x0000008B
-#define V3_DMA_CSR1                     0x0000009B
-#define V3_DMA_CTLB_ADR0                0x0000008C
-#define V3_DMA_CTLB_ADR1                0x0000009C
-#define V3_DMA_DELAY                    0x000000E0
-#define V3_MAIL_DATA                    0x000000C0
-#define V3_PCI_MAIL_IEWR                0x000000D0
-#define V3_PCI_MAIL_IERD                0x000000D2
-#define V3_LB_MAIL_IEWR                 0x000000D4
-#define V3_LB_MAIL_IERD                 0x000000D6
-#define V3_MAIL_WR_STAT                 0x000000D8
-#define V3_MAIL_RD_STAT                 0x000000DA
-#define V3_QBA_MAP                      0x000000DC
-/*  PCI COMMAND REGISTER bits
- */
-#define V3_COMMAND_M_FBB_EN             (1 << 9)
-#define V3_COMMAND_M_SERR_EN            (1 << 8)
-#define V3_COMMAND_M_PAR_EN             (1 << 6)
-#define V3_COMMAND_M_MASTER_EN          (1 << 2)
-#define V3_COMMAND_M_MEM_EN             (1 << 1)
-#define V3_COMMAND_M_IO_EN              (1 << 0)
-/*  SYSTEM REGISTER bits
- */
-#define V3_SYSTEM_M_RST_OUT             (1 << 15)
-#define V3_SYSTEM_M_LOCK                (1 << 14)
-/*  PCI_CFG bits
- */
-#define V3_PCI_CFG_M_I2O_EN             (1 << 15)
-#define V3_PCI_CFG_M_IO_REG_DIS         (1 << 14)
-#define V3_PCI_CFG_M_IO_DIS             (1 << 13)
-#define V3_PCI_CFG_M_EN3V               (1 << 12)
-#define V3_PCI_CFG_M_RETRY_EN           (1 << 10)
-#define V3_PCI_CFG_M_AD_LOW1            (1 << 9)
-#define V3_PCI_CFG_M_AD_LOW0            (1 << 8)
-/*  PCI_BASE register bits (PCI -> Local Bus)
- */
-#define V3_PCI_BASE_M_ADR_BASE          0xFFF00000
-#define V3_PCI_BASE_M_ADR_BASEL         0x000FFF00
-#define V3_PCI_BASE_M_PREFETCH          (1 << 3)
-#define V3_PCI_BASE_M_TYPE              (3 << 1)
-#define V3_PCI_BASE_M_IO                (1 << 0)
-/*  PCI MAP register bits (PCI -> Local bus)
- */
-#define V3_PCI_MAP_M_MAP_ADR            0xFFF00000
-#define V3_PCI_MAP_M_RD_POST_INH        (1 << 15)
-#define V3_PCI_MAP_M_ROM_SIZE           (3 << 10)
-#define V3_PCI_MAP_M_SWAP               (3 << 8)
-#define V3_PCI_MAP_M_ADR_SIZE           0x000000F0
-#define V3_PCI_MAP_M_REG_EN             (1 << 1)
-#define V3_PCI_MAP_M_ENABLE             (1 << 0)
-/*
- *  LB_BASE0,1 register bits (Local bus -> PCI)
- */
-#define V3_LB_BASE_ADR_BASE             0xfff00000
-#define V3_LB_BASE_SWAP                 (3 << 8)
-#define V3_LB_BASE_ADR_SIZE             (15 << 4)
-#define V3_LB_BASE_PREFETCH             (1 << 3)
-#define V3_LB_BASE_ENABLE               (1 << 0)
-#define V3_LB_BASE_ADR_SIZE_1MB         (0 << 4)
-#define V3_LB_BASE_ADR_SIZE_2MB         (1 << 4)
-#define V3_LB_BASE_ADR_SIZE_4MB         (2 << 4)
-#define V3_LB_BASE_ADR_SIZE_8MB         (3 << 4)
-#define V3_LB_BASE_ADR_SIZE_16MB        (4 << 4)
-#define V3_LB_BASE_ADR_SIZE_32MB        (5 << 4)
-#define V3_LB_BASE_ADR_SIZE_64MB        (6 << 4)
-#define V3_LB_BASE_ADR_SIZE_128MB       (7 << 4)
-#define V3_LB_BASE_ADR_SIZE_256MB       (8 << 4)
-#define V3_LB_BASE_ADR_SIZE_512MB       (9 << 4)
-#define V3_LB_BASE_ADR_SIZE_1GB         (10 << 4)
-#define V3_LB_BASE_ADR_SIZE_2GB         (11 << 4)
-#define v3_addr_to_lb_base(a)   ((a) & V3_LB_BASE_ADR_BASE)
-/*
- *  LB_MAP0,1 register bits (Local bus -> PCI)
- */
-#define V3_LB_MAP_MAP_ADR               0xfff0
-#define V3_LB_MAP_TYPE                  (7 << 1)
-#define V3_LB_MAP_AD_LOW_EN             (1 << 0)
-#define V3_LB_MAP_TYPE_IACK             (0 << 1)
-#define V3_LB_MAP_TYPE_IO               (1 << 1)
-#define V3_LB_MAP_TYPE_MEM              (3 << 1)
-#define V3_LB_MAP_TYPE_CONFIG           (5 << 1)
-#define V3_LB_MAP_TYPE_MEM_MULTIPLE     (6 << 1)
-#define v3_addr_to_lb_map(a)    (((a) >> 16) & V3_LB_MAP_MAP_ADR)
-/*
- *  LB_BASE2 register bits (Local bus -> PCI IO)
- */
-#define V3_LB_BASE2_ADR_BASE            0xff00
-#define V3_LB_BASE2_SWAP                (3 << 6)
-#define V3_LB_BASE2_ENABLE              (1 << 0)
-#define v3_addr_to_lb_base2(a)  (((a) >> 16) & V3_LB_BASE2_ADR_BASE)
-/*
- *  LB_MAP2 register bits (Local bus -> PCI IO)
- */
-#define V3_LB_MAP2_MAP_ADR              0xff00
-#define v3_addr_to_lb_map2(a)   (((a) >> 16) & V3_LB_MAP2_MAP_ADR)
-#endif
diff --git a/arch/arm/include/asm/hugetlb-3level.h b/arch/arm/include/asm/hugetlb-3level.h
new file mode 100644
index 000000000000..d4014fbe5ea3
--- /dev/null
+++ b/arch/arm/include/asm/hugetlb-3level.h
@@ -0,0 +1,71 @@
+/*
+ * arch/arm/include/asm/hugetlb-3level.h
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * Based on arch/x86/include/asm/hugetlb.h.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef _ASM_ARM_HUGETLB_3LEVEL_H
+#define _ASM_ARM_HUGETLB_3LEVEL_H
+/*
+ * If our huge pte is non-zero then mark the valid bit.
+ * This allows pte_present(huge_ptep_get(ptep)) to return true for non-zero
+ * ptes.
+ * (The valid bit is automatically cleared by set_pte_at for PROT_NONE ptes).
+ */
+static inline pte_t huge_ptep_get(pte_t *ptep)
+{
+        pte_t retval = *ptep;
+        if (pte_val(retval))
+                pte_val(retval) |= L_PTE_VALID;
+        return retval;
+}
+static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
+                                   pte_t *ptep, pte_t pte)
+{
+        set_pte_at(mm, addr, ptep, pte);
+}
+static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
+                                         unsigned long addr, pte_t *ptep)
+{
+        ptep_clear_flush(vma, addr, ptep);
+}
+static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
+                                           unsigned long addr, pte_t *ptep)
+{
+        ptep_set_wrprotect(mm, addr, ptep);
+}
+static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
+                                            unsigned long addr, pte_t *ptep)
+{
+        return ptep_get_and_clear(mm, addr, ptep);
+}
+static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
+                                             unsigned long addr, pte_t *ptep,
+                                             pte_t pte, int dirty)
+{
+        return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
+}
+#endif /* _ASM_ARM_HUGETLB_3LEVEL_H */
diff --git a/arch/arm/include/asm/hugetlb.h b/arch/arm/include/asm/hugetlb.h
new file mode 100644
index 000000000000..1f1b1cd112f3
--- /dev/null
+++ b/arch/arm/include/asm/hugetlb.h
@@ -0,0 +1,84 @@
+/*
+ * arch/arm/include/asm/hugetlb.h
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * Based on arch/x86/include/asm/hugetlb.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef _ASM_ARM_HUGETLB_H
+#define _ASM_ARM_HUGETLB_H
+#include <asm/page.h>
+#include <asm-generic/hugetlb.h>
+#include <asm/hugetlb-3level.h>
+static inline void hugetlb_free_pgd_range(struct mmu_gather *tlb,
+                                          unsigned long addr, unsigned long end,
+                                          unsigned long floor,
+                                          unsigned long ceiling)
+{
+        free_pgd_range(tlb, addr, end, floor, ceiling);
+}
+static inline int is_hugepage_only_range(struct mm_struct *mm,
+                                         unsigned long addr, unsigned long len)
+{
+        return 0;
+}
+static inline int prepare_hugepage_range(struct file *file,
+                                         unsigned long addr, unsigned long len)
+{
+        struct hstate *h = hstate_file(file);
+        if (len & ~huge_page_mask(h))
+                return -EINVAL;
+        if (addr & ~huge_page_mask(h))
+                return -EINVAL;
+        return 0;
+}
+static inline void hugetlb_prefault_arch_hook(struct mm_struct *mm)
+{
+}
+static inline int huge_pte_none(pte_t pte)
+{
+        return pte_none(pte);
+}
+static inline pte_t huge_pte_wrprotect(pte_t pte)
+{
+        return pte_wrprotect(pte);
+}
+static inline int arch_prepare_hugepage(struct page *page)
+{
+        return 0;
+}
+static inline void arch_release_hugepage(struct page *page)
+{
+}
+static inline void arch_clear_hugepage_flags(struct page *page)
+{
+        clear_bit(PG_dcache_clean, &page->flags);
+}
+#endif /* _ASM_ARM_HUGETLB_H */
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 652b56086de7..d070741b2b37 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -130,16 +130,16 @@ static inline u32 __raw_readl(const volatile void __iomem *addr)
 */
 extern void __iomem *__arm_ioremap_pfn_caller(unsigned long, unsigned long,
        size_t, unsigned int, void *);
-extern void __iomem *__arm_ioremap_caller(unsigned long, size_t, unsigned int,
+extern void __iomem *__arm_ioremap_caller(phys_addr_t, size_t, unsigned int,
        void *);
 extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int);
-extern void __iomem *__arm_ioremap(unsigned long, size_t, unsigned int);
+extern void __iomem *__arm_ioremap(phys_addr_t, size_t, unsigned int);
-extern void __iomem *__arm_ioremap_exec(unsigned long, size_t, bool cached);
+extern void __iomem *__arm_ioremap_exec(phys_addr_t, size_t, bool cached);
 extern void __iounmap(volatile void __iomem *addr);
 extern void __arm_iounmap(volatile void __iomem *addr);
-extern void __iomem * (*arch_ioremap_caller)(unsigned long, size_t,
+extern void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t,
        unsigned int, void *);
 extern void (*arch_iounmap)(volatile void __iomem *);
diff --git a/arch/arm/include/asm/irqflags.h b/arch/arm/include/asm/irqflags.h
index 1e6cca55c750..3b763d6652a0 100644
--- a/arch/arm/include/asm/irqflags.h
+++ b/arch/arm/include/asm/irqflags.h
@@ -8,6 +8,16 @@
 /*
 * CPU interrupt mask handling.
 */
+#ifdef CONFIG_CPU_V7M
+#define IRQMASK_REG_NAME_R "primask"
+#define IRQMASK_REG_NAME_W "primask"
+#define IRQMASK_I_BIT   1
+#else
+#define IRQMASK_REG_NAME_R "cpsr"
+#define IRQMASK_REG_NAME_W "cpsr_c"
+#define IRQMASK_I_BIT   PSR_I_BIT
+#endif
 #if __LINUX_ARM_ARCH__ >= 6
 static inline unsigned long arch_local_irq_save(void)
@@ -15,7 +25,7 @@ static inline unsigned long arch_local_irq_save(void)
        unsigned long flags;
        asm volatile(
-                "       mrs     %0, cpsr        @ arch_local_irq_save\n"
+                "       mrs     %0, " IRQMASK_REG_NAME_R "      @ arch_local_irq_save\n"
                "       cpsid   i"
                : "=r" (flags) : : "memory", "cc");
        return flags;
@@ -129,7 +139,7 @@ static inline unsigned long arch_local_save_flags(void)
 {
        unsigned long flags;
        asm volatile(
-                "       mrs     %0, cpsr        @ local_save_flags"
+                "       mrs     %0, " IRQMASK_REG_NAME_R "      @ local_save_flags"
                : "=r" (flags) : : "memory", "cc");
        return flags;
 }
@@ -140,7 +150,7 @@ static inline unsigned long arch_local_save_flags(void)
 static inline void arch_local_irq_restore(unsigned long flags)
 {
        asm volatile(
-                "       msr     cpsr_c, %0      @ local_irq_restore"
+                "       msr     " IRQMASK_REG_NAME_W ", %0      @ local_irq_restore"
                :
                : "r" (flags)
                : "memory", "cc");
@@ -148,8 +158,8 @@ static inline void arch_local_irq_restore(unsigned long flags)
 static inline int arch_irqs_disabled_flags(unsigned long flags)
 {
-        return flags & PSR_I_BIT;
+        return flags & IRQMASK_I_BIT;
 }
-#endif
+#endif /* ifdef __KERNEL__ */
-#endif
+#endif /* ifndef __ASM_ARM_IRQFLAGS_H */
diff --git a/arch/arm/include/asm/kvm_arch_timer.h b/arch/arm/include/asm/kvm_arch_timer.h
deleted file mode 100644
index 68cb9e1dfb81..000000000000
--- a/arch/arm/include/asm/kvm_arch_timer.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Copyright (C) 2012 ARM Ltd.
- * Author: Marc Zyngier <marc.zyngier@arm.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef __ASM_ARM_KVM_ARCH_TIMER_H
-#define __ASM_ARM_KVM_ARCH_TIMER_H
-#include <linux/clocksource.h>
-#include <linux/hrtimer.h>
-#include <linux/workqueue.h>
-struct arch_timer_kvm {
-#ifdef CONFIG_KVM_ARM_TIMER
-        /* Is the timer enabled */
-        bool                    enabled;
-        /* Virtual offset */
-        cycle_t                 cntvoff;
-#endif
-};
-struct arch_timer_cpu {
-#ifdef CONFIG_KVM_ARM_TIMER
-        /* Registers: control register, timer value */
-        u32                             cntv_ctl;       /* Saved/restored */
-        cycle_t                         cntv_cval;      /* Saved/restored */
-        /*
-         * Anything that is not used directly from assembly code goes
-         * here.
-         */
-        /* Background timer used when the guest is not running */
-        struct hrtimer                  timer;
-        /* Work queued with the above timer expires */
-        struct work_struct              expired;
-        /* Background timer active */
-        bool                            armed;
-        /* Timer IRQ */
-        const struct kvm_irq_level      *irq;
-#endif
-};
-#ifdef CONFIG_KVM_ARM_TIMER
-int kvm_timer_hyp_init(void);
-int kvm_timer_init(struct kvm *kvm);
-void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu);
-void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu);
-void kvm_timer_sync_hwstate(struct kvm_vcpu *vcpu);
-void kvm_timer_vcpu_terminate(struct kvm_vcpu *vcpu);
-#else
-static inline int kvm_timer_hyp_init(void)
-{
-        return 0;
-};
-static inline int kvm_timer_init(struct kvm *kvm)
-{
-        return 0;
-}
-static inline void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu) {}
-static inline void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu) {}
-static inline void kvm_timer_sync_hwstate(struct kvm_vcpu *vcpu) {}
-static inline void kvm_timer_vcpu_terminate(struct kvm_vcpu *vcpu) {}
-#endif
-#endif
diff --git a/arch/arm/include/asm/kvm_arm.h b/arch/arm/include/asm/kvm_arm.h
index 124623e5ef14..64e96960de29 100644
--- a/arch/arm/include/asm/kvm_arm.h
+++ b/arch/arm/include/asm/kvm_arm.h
@@ -135,7 +135,6 @@
 #define KVM_PHYS_MASK   (KVM_PHYS_SIZE - 1ULL)
 #define PTRS_PER_S2_PGD (1ULL << (KVM_PHYS_SHIFT - 30))
 #define S2_PGD_ORDER    get_order(PTRS_PER_S2_PGD * sizeof(pgd_t))
-#define S2_PGD_SIZE     (1 << S2_PGD_ORDER)
 /* Virtualization Translation Control Register (VTCR) bits */
 #define VTCR_SH0        (3 << 12)
diff --git a/arch/arm/include/asm/kvm_asm.h b/arch/arm/include/asm/kvm_asm.h
index 18d50322a9e2..a2f43ddcc300 100644
--- a/arch/arm/include/asm/kvm_asm.h
+++ b/arch/arm/include/asm/kvm_asm.h
@@ -37,16 +37,18 @@
 #define c5_AIFSR        15      /* Auxilary Instrunction Fault Status R */
 #define c6_DFAR         16      /* Data Fault Address Register */
 #define c6_IFAR         17      /* Instruction Fault Address Register */
-#define c9_L2CTLR       18      /* Cortex A15 L2 Control Register */
+#define c7_PAR          18      /* Physical Address Register */
-#define c10_PRRR        19      /* Primary Region Remap Register */
+#define c7_PAR_high     19      /* PAR top 32 bits */
-#define c10_NMRR        20      /* Normal Memory Remap Register */
+#define c9_L2CTLR       20      /* Cortex A15 L2 Control Register */
-#define c12_VBAR        21      /* Vector Base Address Register */
+#define c10_PRRR        21      /* Primary Region Remap Register */
-#define c13_CID         22      /* Context ID Register */
+#define c10_NMRR        22      /* Normal Memory Remap Register */
-#define c13_TID_URW     23      /* Thread ID, User R/W */
+#define c12_VBAR        23      /* Vector Base Address Register */
-#define c13_TID_URO     24      /* Thread ID, User R/O */
+#define c13_CID         24      /* Context ID Register */
-#define c13_TID_PRIV    25      /* Thread ID, Privileged */
+#define c13_TID_URW     25      /* Thread ID, User R/W */
-#define c14_CNTKCTL     26      /* Timer Control Register (PL1) */
+#define c13_TID_URO     26      /* Thread ID, User R/O */
-#define NR_CP15_REGS    27      /* Number of regs (incl. invalid) */
+#define c13_TID_PRIV    27      /* Thread ID, Privileged */
+#define c14_CNTKCTL     28      /* Timer Control Register (PL1) */
+#define NR_CP15_REGS    29      /* Number of regs (incl. invalid) */
 #define ARM_EXCEPTION_RESET       0
 #define ARM_EXCEPTION_UNDEFINED   1
@@ -72,8 +74,6 @@ extern char __kvm_hyp_vector[];
 extern char __kvm_hyp_code_start[];
 extern char __kvm_hyp_code_end[];
-extern void __kvm_tlb_flush_vmid(struct kvm *kvm);
 extern void __kvm_flush_vm_context(void);
 extern void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);
diff --git a/arch/arm/include/asm/kvm_emulate.h b/arch/arm/include/asm/kvm_emulate.h
index 82b4babead2c..a464e8d7b6c5 100644
--- a/arch/arm/include/asm/kvm_emulate.h
+++ b/arch/arm/include/asm/kvm_emulate.h
@@ -65,11 +65,6 @@ static inline bool vcpu_mode_priv(struct kvm_vcpu *vcpu)
        return cpsr_mode > USR_MODE;;
 }
-static inline bool kvm_vcpu_reg_is_pc(struct kvm_vcpu *vcpu, int reg)
-{
-        return reg == 15;
-}
 static inline u32 kvm_vcpu_get_hsr(struct kvm_vcpu *vcpu)
 {
        return vcpu->arch.fault.hsr;
diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h
index 57cb786a6203..7d22517d8071 100644
--- a/arch/arm/include/asm/kvm_host.h
+++ b/arch/arm/include/asm/kvm_host.h
@@ -23,9 +23,14 @@
 #include <asm/kvm_asm.h>
 #include <asm/kvm_mmio.h>
 #include <asm/fpstate.h>
-#include <asm/kvm_arch_timer.h>
+#include <kvm/arm_arch_timer.h>
+#if defined(CONFIG_KVM_ARM_MAX_VCPUS)
 #define KVM_MAX_VCPUS CONFIG_KVM_ARM_MAX_VCPUS
+#else
+#define KVM_MAX_VCPUS 0
+#endif
 #define KVM_USER_MEM_SLOTS 32
 #define KVM_PRIVATE_MEM_SLOTS 4
 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
@@ -38,7 +43,7 @@
 #define KVM_NR_PAGE_SIZES       1
 #define KVM_PAGES_PER_HPAGE(x)  (1UL<<31)
-#include <asm/kvm_vgic.h>
+#include <kvm/arm_vgic.h>
 struct kvm_vcpu;
 u32 *kvm_vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num, u32 mode);
@@ -190,8 +195,8 @@ int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
 int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
                int exception_index);
-static inline void __cpu_init_hyp_mode(unsigned long long boot_pgd_ptr,
+static inline void __cpu_init_hyp_mode(phys_addr_t boot_pgd_ptr,
-                                       unsigned long long pgd_ptr,
+                                       phys_addr_t pgd_ptr,
                                       unsigned long hyp_stack_ptr,
                                       unsigned long vector_ptr)
 {
diff --git a/arch/arm/include/asm/kvm_vgic.h b/arch/arm/include/asm/kvm_vgic.h
deleted file mode 100644
index 343744e4809c..000000000000
--- a/arch/arm/include/asm/kvm_vgic.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- * Copyright (C) 2012 ARM Ltd.
- * Author: Marc Zyngier <marc.zyngier@arm.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef __ASM_ARM_KVM_VGIC_H
-#define __ASM_ARM_KVM_VGIC_H
-#include <linux/kernel.h>
-#include <linux/kvm.h>
-#include <linux/irqreturn.h>
-#include <linux/spinlock.h>
-#include <linux/types.h>
-#include <linux/irqchip/arm-gic.h>
-#define VGIC_NR_IRQS            128
-#define VGIC_NR_SGIS            16
-#define VGIC_NR_PPIS            16
-#define VGIC_NR_PRIVATE_IRQS    (VGIC_NR_SGIS + VGIC_NR_PPIS)
-#define VGIC_NR_SHARED_IRQS     (VGIC_NR_IRQS - VGIC_NR_PRIVATE_IRQS)
-#define VGIC_MAX_CPUS           KVM_MAX_VCPUS
-#define VGIC_MAX_LRS            (1 << 6)
-/* Sanity checks... */
-#if (VGIC_MAX_CPUS > 8)
-#error  Invalid number of CPU interfaces
-#endif
-#if (VGIC_NR_IRQS & 31)
-#error "VGIC_NR_IRQS must be a multiple of 32"
-#endif
-#if (VGIC_NR_IRQS > 1024)
-#error "VGIC_NR_IRQS must be <= 1024"
-#endif
-/*
- * The GIC distributor registers describing interrupts have two parts:
- * - 32 per-CPU interrupts (SGI + PPI)
- * - a bunch of shared interrupts (SPI)
- */
-struct vgic_bitmap {
-        union {
-                u32 reg[VGIC_NR_PRIVATE_IRQS / 32];
-                DECLARE_BITMAP(reg_ul, VGIC_NR_PRIVATE_IRQS);
-        } percpu[VGIC_MAX_CPUS];
-        union {
-                u32 reg[VGIC_NR_SHARED_IRQS / 32];
-                DECLARE_BITMAP(reg_ul, VGIC_NR_SHARED_IRQS);
-        } shared;
-};
-struct vgic_bytemap {
-        u32 percpu[VGIC_MAX_CPUS][VGIC_NR_PRIVATE_IRQS / 4];
-        u32 shared[VGIC_NR_SHARED_IRQS  / 4];
-};
-struct vgic_dist {
-#ifdef CONFIG_KVM_ARM_VGIC
-        spinlock_t              lock;
-        bool                    ready;
-        /* Virtual control interface mapping */
-        void __iomem            *vctrl_base;
-        /* Distributor and vcpu interface mapping in the guest */
-        phys_addr_t             vgic_dist_base;
-        phys_addr_t             vgic_cpu_base;
-        /* Distributor enabled */
-        u32                     enabled;
-        /* Interrupt enabled (one bit per IRQ) */
-        struct vgic_bitmap      irq_enabled;
-        /* Interrupt 'pin' level */
-        struct vgic_bitmap      irq_state;
-        /* Level-triggered interrupt in progress */
-        struct vgic_bitmap      irq_active;
-        /* Interrupt priority. Not used yet. */
-        struct vgic_bytemap     irq_priority;
-        /* Level/edge triggered */
-        struct vgic_bitmap      irq_cfg;
-        /* Source CPU per SGI and target CPU */
-        u8                      irq_sgi_sources[VGIC_MAX_CPUS][VGIC_NR_SGIS];
-        /* Target CPU for each IRQ */
-        u8                      irq_spi_cpu[VGIC_NR_SHARED_IRQS];
-        struct vgic_bitmap      irq_spi_target[VGIC_MAX_CPUS];
-        /* Bitmap indicating which CPU has something pending */
-        unsigned long           irq_pending_on_cpu;
-#endif
-};
-struct vgic_cpu {
-#ifdef CONFIG_KVM_ARM_VGIC
-        /* per IRQ to LR mapping */
-        u8              vgic_irq_lr_map[VGIC_NR_IRQS];
-        /* Pending interrupts on this VCPU */
-        DECLARE_BITMAP( pending_percpu, VGIC_NR_PRIVATE_IRQS);
-        DECLARE_BITMAP( pending_shared, VGIC_NR_SHARED_IRQS);
-        /* Bitmap of used/free list registers */
-        DECLARE_BITMAP( lr_used, VGIC_MAX_LRS);
-        /* Number of list registers on this CPU */
-        int             nr_lr;
-        /* CPU vif control registers for world switch */
-        u32             vgic_hcr;
-        u32             vgic_vmcr;
-        u32             vgic_misr;      /* Saved only */
-        u32             vgic_eisr[2];   /* Saved only */
-        u32             vgic_elrsr[2];  /* Saved only */
-        u32             vgic_apr;
-        u32             vgic_lr[VGIC_MAX_LRS];
-#endif
-};
-#define LR_EMPTY        0xff
-struct kvm;
-struct kvm_vcpu;
-struct kvm_run;
-struct kvm_exit_mmio;
-#ifdef CONFIG_KVM_ARM_VGIC
-int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr);
-int kvm_vgic_hyp_init(void);
-int kvm_vgic_init(struct kvm *kvm);
-int kvm_vgic_create(struct kvm *kvm);
-int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
-void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
-void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
-int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
-                        bool level);
-int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
-bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
-                      struct kvm_exit_mmio *mmio);
-#define irqchip_in_kernel(k)    (!!((k)->arch.vgic.vctrl_base))
-#define vgic_initialized(k)     ((k)->arch.vgic.ready)
-#else
-static inline int kvm_vgic_hyp_init(void)
-{
-        return 0;
-}
-static inline int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr)
-{
-        return 0;
-}
-static inline int kvm_vgic_init(struct kvm *kvm)
-{
-        return 0;
-}
-static inline int kvm_vgic_create(struct kvm *kvm)
-{
-        return 0;
-}
-static inline int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
-{
-        return 0;
-}
-static inline void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) {}
-static inline void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) {}
-static inline int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid,
-                                      unsigned int irq_num, bool level)
-{
-        return 0;
-}
-static inline int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
-{
-        return 0;
-}
-static inline bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
-                                    struct kvm_exit_mmio *mmio)
-{
-        return false;
-}
-static inline int irqchip_in_kernel(struct kvm *kvm)
-{
-        return 0;
-}
-static inline bool vgic_initialized(struct kvm *kvm)
-{
-        return true;
-}
-#endif
-#endif
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 308ad7d6f98b..441efc491b50 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -8,7 +8,10 @@
 * published by the Free Software Foundation.
 */
+#include <linux/types.h>
 #ifndef __ASSEMBLY__
+#include <linux/reboot.h>
 struct tag;
 struct meminfo;
@@ -16,8 +19,10 @@ struct pt_regs;
 struct smp_operations;
 #ifdef CONFIG_SMP
 #define smp_ops(ops) (&(ops))
+#define smp_init_ops(ops) (&(ops))
 #else
 #define smp_ops(ops) (struct smp_operations *)NULL
+#define smp_init_ops(ops) (bool (*)(void))NULL
 #endif
 struct machine_desc {
@@ -39,8 +44,9 @@ struct machine_desc {
        unsigned char           reserve_lp0 :1; /* never has lp0        */
        unsigned char           reserve_lp1 :1; /* never has lp1        */
        unsigned char           reserve_lp2 :1; /* never has lp2        */
-        char                    restart_mode;   /* default restart mode */
+        enum reboot_mode        reboot_mode;    /* default restart mode */
        struct smp_operations   *smp;           /* SMP operations       */
+        bool                    (*smp_init)(void);
        void                    (*fixup)(struct tag *, char **,
                                         struct meminfo *);
        void                    (*reserve)(void);/* reserve mem blocks  */
@@ -53,7 +59,7 @@ struct machine_desc {
 #ifdef CONFIG_MULTI_IRQ_HANDLER
        void                    (*handle_irq)(struct pt_regs *);
 #endif
-        void                    (*restart)(char, const char *);
+        void                    (*restart)(enum reboot_mode, const char *);
 };
 /*
diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
index 7d2c3c843801..a1c90d7feb0e 100644
--- a/arch/arm/include/asm/mach/pci.h
+++ b/arch/arm/include/asm/mach/pci.h
@@ -16,6 +16,7 @@
 struct pci_sys_data;
 struct pci_ops;
 struct pci_bus;
+struct device;
 struct hw_pci {
 #ifdef CONFIG_PCI_DOMAINS
@@ -68,7 +69,16 @@ struct pci_sys_data {
 /*
 * Call this with your hw_pci struct to initialise the PCI system.
 */
-void pci_common_init(struct hw_pci *);
+void pci_common_init_dev(struct device *, struct hw_pci *);
+/*
+ * Compatibility wrapper for older platforms that do not care about
+ * passing the parent device.
+ */
+static inline void pci_common_init(struct hw_pci *hw)
+{
+        pci_common_init_dev(NULL, hw);
+}
 /*
 * Setup early fixed I/O mapping.
@@ -96,9 +106,4 @@ extern struct pci_ops via82c505_ops;
 extern int via82c505_setup(int nr, struct pci_sys_data *);
 extern void via82c505_init(void *sysdata);
-extern struct pci_ops pci_v3_ops;
-extern int pci_v3_setup(int nr, struct pci_sys_data *);
-extern void pci_v3_preinit(void);
-extern void pci_v3_postinit(void);
 #endif /* __ASM_MACH_PCI_H */
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 57870ab313c5..e750a938fd3c 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -18,6 +18,8 @@
 #include <linux/types.h>
 #include <linux/sizes.h>
+#include <asm/cache.h>
 #ifdef CONFIG_NEED_MACH_MEMORY_H
 #include <mach/memory.h>
 #endif
@@ -141,6 +143,20 @@
 #define page_to_phys(page)      (__pfn_to_phys(page_to_pfn(page)))
 #define phys_to_page(phys)      (pfn_to_page(__phys_to_pfn(phys)))
+/*
+ * Minimum guaranted alignment in pgd_alloc().  The page table pointers passed
+ * around in head.S and proc-*.S are shifted by this amount, in order to
+ * leave spare high bits for systems with physical address extension.  This
+ * does not fully accomodate the 40-bit addressing capability of ARM LPAE, but
+ * gives us about 38-bits or so.
+ */
+#ifdef CONFIG_ARM_LPAE
+#define ARCH_PGD_SHIFT          L1_CACHE_SHIFT
+#else
+#define ARCH_PGD_SHIFT          0
+#endif
+#define ARCH_PGD_MASK           ((1 << ARCH_PGD_SHIFT) - 1)
 #ifndef __ASSEMBLY__
 /*
@@ -207,7 +223,7 @@ static inline unsigned long __phys_to_virt(unsigned long x)
 * direct-mapped view.  We assume this is the first page
 * of RAM in the mem_map as well.
 */
-#define PHYS_PFN_OFFSET (PHYS_OFFSET >> PAGE_SHIFT)
+#define PHYS_PFN_OFFSET ((unsigned long)(PHYS_OFFSET >> PAGE_SHIFT))
 /*
 * These are *only* valid on the kernel direct mapped RAM memory.
@@ -260,12 +276,6 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
 /*
 * Conversion between a struct page and a physical address.
 *
- * Note: when converting an unknown physical address to a
- * struct page, the resulting pointer must be validated
- * using VALID_PAGE().  It must return an invalid struct page
- * for any physical address not corresponding to a system
- * RAM address.
- *
 *  page_to_pfn(page)   convert a struct page * to a PFN number
 *  pfn_to_page(pfn)    convert a _valid_ PFN number to struct page *
 *
diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h
index e3d55547e755..6f18da09668b 100644
--- a/arch/arm/include/asm/mmu.h
+++ b/arch/arm/include/asm/mmu.h
@@ -6,8 +6,11 @@
 typedef struct {
 #ifdef CONFIG_CPU_HAS_ASID
        atomic64_t      id;
+#else
+        int             switch_pending;
 #endif
        unsigned int    vmalloc_seq;
+        unsigned long   sigpage;
 } mm_context_t;
 #ifdef CONFIG_CPU_HAS_ASID
diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h
index a7b85e0d0cc1..9b32f76bb0dd 100644
--- a/arch/arm/include/asm/mmu_context.h
+++ b/arch/arm/include/asm/mmu_context.h
@@ -18,6 +18,7 @@
 #include <asm/cacheflush.h>
 #include <asm/cachetype.h>
 #include <asm/proc-fns.h>
+#include <asm/smp_plat.h>
 #include <asm-generic/mm_hooks.h>
 void __check_vmalloc_seq(struct mm_struct *mm);
@@ -27,7 +28,15 @@ void __check_vmalloc_seq(struct mm_struct *mm);
 void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk);
 #define init_new_context(tsk,mm)        ({ atomic64_set(&mm->context.id, 0); 0; })
-DECLARE_PER_CPU(atomic64_t, active_asids);
+#ifdef CONFIG_ARM_ERRATA_798181
+void a15_erratum_get_cpumask(int this_cpu, struct mm_struct *mm,
+                             cpumask_t *mask);
+#else  /* !CONFIG_ARM_ERRATA_798181 */
+static inline void a15_erratum_get_cpumask(int this_cpu, struct mm_struct *mm,
+                                           cpumask_t *mask)
+{
+}
+#endif /* CONFIG_ARM_ERRATA_798181 */
 #else   /* !CONFIG_CPU_HAS_ASID */
@@ -47,7 +56,7 @@ static inline void check_and_switch_context(struct mm_struct *mm,
                 * on non-ASID CPUs, the old mm will remain valid until the
                 * finish_arch_post_lock_switch() call.
                 */
-                set_ti_thread_flag(task_thread_info(tsk), TIF_SWITCH_MM);
+                mm->context.switch_pending = 1;
        else
                cpu_switch_mm(mm->pgd, mm);
 }
@@ -56,9 +65,21 @@ static inline void check_and_switch_context(struct mm_struct *mm,
        finish_arch_post_lock_switch
 static inline void finish_arch_post_lock_switch(void)
 {
-        if (test_and_clear_thread_flag(TIF_SWITCH_MM)) {
+        struct mm_struct *mm = current->mm;
-                struct mm_struct *mm = current->mm;
-                cpu_switch_mm(mm->pgd, mm);
+        if (mm && mm->context.switch_pending) {
+                /*
+                 * Preemption must be disabled during cpu_switch_mm() as we
+                 * have some stateful cache flush implementations. Check
+                 * switch_pending again in case we were preempted and the
+                 * switch to this mm was already done.
+                 */
+                preempt_disable();
+                if (mm->context.switch_pending) {
+                        mm->context.switch_pending = 0;
+                        cpu_switch_mm(mm->pgd, mm);
+                }
+                preempt_enable_no_resched();
        }
 }
@@ -98,12 +119,16 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next,
 #ifdef CONFIG_MMU
        unsigned int cpu = smp_processor_id();
-#ifdef CONFIG_SMP
+        /*
-        /* check for possible thread migration */
+         * __sync_icache_dcache doesn't broadcast the I-cache invalidation,
-        if (!cpumask_empty(mm_cpumask(next)) &&
+         * so check for possible thread migration and invalidate the I-cache
+         * if we're new to this CPU.
+         */
+        if (cache_ops_need_broadcast() &&
+            !cpumask_empty(mm_cpumask(next)) &&
            !cpumask_test_cpu(cpu, mm_cpumask(next)))
                __flush_icache_all();
-#endif
        if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next) {
                check_and_switch_context(next, tsk);
                if (cache_is_vivt())
diff --git a/arch/arm/include/asm/mpu.h b/arch/arm/include/asm/mpu.h
new file mode 100644
index 000000000000..c3247cc2fe08
--- /dev/null
+++ b/arch/arm/include/asm/mpu.h
@@ -0,0 +1,76 @@
+#ifndef __ARM_MPU_H
+#define __ARM_MPU_H
+#ifdef CONFIG_ARM_MPU
+/* MPUIR layout */
+#define MPUIR_nU                1
+#define MPUIR_DREGION           8
+#define MPUIR_IREGION           16
+#define MPUIR_DREGION_SZMASK    (0xFF << MPUIR_DREGION)
+#define MPUIR_IREGION_SZMASK    (0xFF << MPUIR_IREGION)
+/* ID_MMFR0 data relevant to MPU */
+#define MMFR0_PMSA              (0xF << 4)
+#define MMFR0_PMSAv7            (3 << 4)
+/* MPU D/I Size Register fields */
+#define MPU_RSR_SZ              1
+#define MPU_RSR_EN              0
+/* The D/I RSR value for an enabled region spanning the whole of memory */
+#define MPU_RSR_ALL_MEM         63
+/* Individual bits in the DR/IR ACR */
+#define MPU_ACR_XN              (1 << 12)
+#define MPU_ACR_SHARED          (1 << 2)
+/* C, B and TEX[2:0] bits only have semantic meanings when grouped */
+#define MPU_RGN_CACHEABLE       0xB
+#define MPU_RGN_SHARED_CACHEABLE (MPU_RGN_CACHEABLE | MPU_ACR_SHARED)
+#define MPU_RGN_STRONGLY_ORDERED 0
+/* Main region should only be shared for SMP */
+#ifdef CONFIG_SMP
+#define MPU_RGN_NORMAL          (MPU_RGN_CACHEABLE | MPU_ACR_SHARED)
+#else
+#define MPU_RGN_NORMAL          MPU_RGN_CACHEABLE
+#endif
+/* Access permission bits of ACR (only define those that we use)*/
+#define MPU_AP_PL1RW_PL0RW      (0x3 << 8)
+#define MPU_AP_PL1RW_PL0R0      (0x2 << 8)
+#define MPU_AP_PL1RW_PL0NA      (0x1 << 8)
+/* For minimal static MPU region configurations */
+#define MPU_PROBE_REGION        0
+#define MPU_BG_REGION           1
+#define MPU_RAM_REGION          2
+#define MPU_VECTORS_REGION      3
+/* Maximum number of regions Linux is interested in */
+#define MPU_MAX_REGIONS         16
+#define MPU_DATA_SIDE           0
+#define MPU_INSTR_SIDE          1
+#ifndef __ASSEMBLY__
+struct mpu_rgn {
+        /* Assume same attributes for d/i-side  */
+        u32 drbar;
+        u32 drsr;
+        u32 dracr;
+};
+struct mpu_rgn_info {
+        u32 mpuir;
+        struct mpu_rgn rgns[MPU_MAX_REGIONS];
+};
+extern struct mpu_rgn_info mpu_rgn_info;
+#endif /* __ASSEMBLY__ */
+#endif /* CONFIG_ARM_MPU */
+#endif
diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h
index 812a4944e783..4355f0ec44d6 100644
--- a/arch/arm/include/asm/page.h
+++ b/arch/arm/include/asm/page.h
@@ -13,7 +13,7 @@
 /* PAGE_SHIFT determines the page size */
 #define PAGE_SHIFT              12
 #define PAGE_SIZE               (_AC(1,UL) << PAGE_SHIFT)
-#define PAGE_MASK               (~(PAGE_SIZE-1))
+#define PAGE_MASK               (~((1 << PAGE_SHIFT) - 1))
 #ifndef __ASSEMBLY__
@@ -142,7 +142,9 @@ extern void __cpu_copy_user_highpage(struct page *to, struct page *from,
 #define clear_page(page)        memset((void *)(page), 0, PAGE_SIZE)
 extern void copy_page(void *to, const void *from);
+#ifdef CONFIG_KUSER_HELPERS
 #define __HAVE_ARCH_GATE_AREA 1
+#endif
 #ifdef CONFIG_ARM_LPAE
 #include <asm/pgtable-3level-types.h>
diff --git a/arch/arm/include/asm/pgtable-3level-hwdef.h b/arch/arm/include/asm/pgtable-3level-hwdef.h
index 18f5cef82ad5..626989fec4d3 100644
--- a/arch/arm/include/asm/pgtable-3level-hwdef.h
+++ b/arch/arm/include/asm/pgtable-3level-hwdef.h
@@ -30,6 +30,7 @@
 #define PMD_TYPE_FAULT          (_AT(pmdval_t, 0) << 0)
 #define PMD_TYPE_TABLE          (_AT(pmdval_t, 3) << 0)
 #define PMD_TYPE_SECT           (_AT(pmdval_t, 1) << 0)
+#define PMD_TABLE_BIT           (_AT(pmdval_t, 1) << 1)
 #define PMD_BIT4                (_AT(pmdval_t, 0))
 #define PMD_DOMAIN(x)           (_AT(pmdval_t, 0))
 #define PMD_APTABLE_SHIFT       (61)
@@ -41,6 +42,8 @@
 */
 #define PMD_SECT_BUFFERABLE     (_AT(pmdval_t, 1) << 2)
 #define PMD_SECT_CACHEABLE      (_AT(pmdval_t, 1) << 3)
+#define PMD_SECT_USER           (_AT(pmdval_t, 1) << 6)         /* AP[1] */
+#define PMD_SECT_RDONLY         (_AT(pmdval_t, 1) << 7)         /* AP[2] */
 #define PMD_SECT_S              (_AT(pmdval_t, 3) << 8)
 #define PMD_SECT_AF             (_AT(pmdval_t, 1) << 10)
 #define PMD_SECT_nG             (_AT(pmdval_t, 1) << 11)
@@ -66,6 +69,7 @@
 #define PTE_TYPE_MASK           (_AT(pteval_t, 3) << 0)
 #define PTE_TYPE_FAULT          (_AT(pteval_t, 0) << 0)
 #define PTE_TYPE_PAGE           (_AT(pteval_t, 3) << 0)
+#define PTE_TABLE_BIT           (_AT(pteval_t, 1) << 1)
 #define PTE_BUFFERABLE          (_AT(pteval_t, 1) << 2)         /* AttrIndx[0] */
 #define PTE_CACHEABLE           (_AT(pteval_t, 1) << 3)         /* AttrIndx[1] */
 #define PTE_EXT_SHARED          (_AT(pteval_t, 3) << 8)         /* SH[1:0], inner shareable */
@@ -79,4 +83,24 @@
 #define PHYS_MASK_SHIFT         (40)
 #define PHYS_MASK               ((1ULL << PHYS_MASK_SHIFT) - 1)
+/*
+ * TTBR0/TTBR1 split (PAGE_OFFSET):
+ *   0x40000000: T0SZ = 2, T1SZ = 0 (not used)
+ *   0x80000000: T0SZ = 0, T1SZ = 1
+ *   0xc0000000: T0SZ = 0, T1SZ = 2
+ *
+ * Only use this feature if PHYS_OFFSET <= PAGE_OFFSET, otherwise
+ * booting secondary CPUs would end up using TTBR1 for the identity
+ * mapping set up in TTBR0.
+ */
+#if defined CONFIG_VMSPLIT_2G
+#define TTBR1_OFFSET    16                      /* skip two L1 entries */
+#elif defined CONFIG_VMSPLIT_3G
+#define TTBR1_OFFSET    (4096 * (1 + 3))        /* only L2, skip pgd + 3*pmd */
+#else
+#define TTBR1_OFFSET    0
+#endif
+#define TTBR1_SIZE      (((PAGE_OFFSET >> 30) - 1) << 16)
 #endif
diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h
index 86b8fe398b95..5689c18c85f5 100644
--- a/arch/arm/include/asm/pgtable-3level.h
+++ b/arch/arm/include/asm/pgtable-3level.h
@@ -33,7 +33,7 @@
 #define PTRS_PER_PMD            512
 #define PTRS_PER_PGD            4
-#define PTE_HWTABLE_PTRS        (PTRS_PER_PTE)
+#define PTE_HWTABLE_PTRS        (0)
 #define PTE_HWTABLE_OFF         (0)
 #define PTE_HWTABLE_SIZE        (PTRS_PER_PTE * sizeof(u64))
@@ -48,20 +48,28 @@
 #define PMD_SHIFT               21
 #define PMD_SIZE                (1UL << PMD_SHIFT)
-#define PMD_MASK                (~(PMD_SIZE-1))
+#define PMD_MASK                (~((1 << PMD_SHIFT) - 1))
 #define PGDIR_SIZE              (1UL << PGDIR_SHIFT)
-#define PGDIR_MASK              (~(PGDIR_SIZE-1))
+#define PGDIR_MASK              (~((1 << PGDIR_SHIFT) - 1))
 /*
 * section address mask and size definitions.
 */
 #define SECTION_SHIFT           21
 #define SECTION_SIZE            (1UL << SECTION_SHIFT)
-#define SECTION_MASK            (~(SECTION_SIZE-1))
+#define SECTION_MASK            (~((1 << SECTION_SHIFT) - 1))
 #define USER_PTRS_PER_PGD       (PAGE_OFFSET / PGDIR_SIZE)
 /*
+ * Hugetlb definitions.
+ */
+#define HPAGE_SHIFT             PMD_SHIFT
+#define HPAGE_SIZE              (_AC(1, UL) << HPAGE_SHIFT)
+#define HPAGE_MASK              (~(HPAGE_SIZE - 1))
+#define HUGETLB_PAGE_ORDER      (HPAGE_SHIFT - PAGE_SHIFT)
+/*
 * "Linux" PTE definitions for LPAE.
 *
 * These bits overlap with the hardware bits but the naming is preserved for
@@ -79,6 +87,11 @@
 #define L_PTE_SPECIAL           (_AT(pteval_t, 1) << 56)        /* unused */
 #define L_PTE_NONE              (_AT(pteval_t, 1) << 57)        /* PROT_NONE */
+#define PMD_SECT_VALID          (_AT(pmdval_t, 1) << 0)
+#define PMD_SECT_DIRTY          (_AT(pmdval_t, 1) << 55)
+#define PMD_SECT_SPLITTING      (_AT(pmdval_t, 1) << 56)
+#define PMD_SECT_NONE           (_AT(pmdval_t, 1) << 57)
 /*
 * To be used in assembly code with the upper page attributes.
 */
@@ -166,8 +179,83 @@ static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
                clean_pmd_entry(pmdp);  \
        } while (0)
+/*
+ * For 3 levels of paging the PTE_EXT_NG bit will be set for user address ptes
+ * that are written to a page table but not for ptes created with mk_pte.
+ *
+ * In hugetlb_no_page, a new huge pte (new_pte) is generated and passed to
+ * hugetlb_cow, where it is compared with an entry in a page table.
+ * This comparison test fails erroneously leading ultimately to a memory leak.
+ *
+ * To correct this behaviour, we mask off PTE_EXT_NG for any pte that is
+ * present before running the comparison.
+ */
+#define __HAVE_ARCH_PTE_SAME
+#define pte_same(pte_a,pte_b)   ((pte_present(pte_a) ? pte_val(pte_a) & ~PTE_EXT_NG     \
+                                        : pte_val(pte_a))                               \
+                                == (pte_present(pte_b) ? pte_val(pte_b) & ~PTE_EXT_NG   \
+                                        : pte_val(pte_b)))
 #define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,__pte(pte_val(pte)|(ext)))
+#define pte_huge(pte)           (pte_val(pte) && !(pte_val(pte) & PTE_TABLE_BIT))
+#define pte_mkhuge(pte)         (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
+#define pmd_young(pmd)          (pmd_val(pmd) & PMD_SECT_AF)
+#define __HAVE_ARCH_PMD_WRITE
+#define pmd_write(pmd)          (!(pmd_val(pmd) & PMD_SECT_RDONLY))
+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
+#define pmd_trans_huge(pmd)     (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT))
+#define pmd_trans_splitting(pmd) (pmd_val(pmd) & PMD_SECT_SPLITTING)
+#endif
+#define PMD_BIT_FUNC(fn,op) \
+static inline pmd_t pmd_##fn(pmd_t pmd) { pmd_val(pmd) op; return pmd; }
+PMD_BIT_FUNC(wrprotect, |= PMD_SECT_RDONLY);
+PMD_BIT_FUNC(mkold,     &= ~PMD_SECT_AF);
+PMD_BIT_FUNC(mksplitting, |= PMD_SECT_SPLITTING);
+PMD_BIT_FUNC(mkwrite,   &= ~PMD_SECT_RDONLY);
+PMD_BIT_FUNC(mkdirty,   |= PMD_SECT_DIRTY);
+PMD_BIT_FUNC(mkyoung,   |= PMD_SECT_AF);
+#define pmd_mkhuge(pmd)         (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
+#define pmd_pfn(pmd)            (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
+#define pfn_pmd(pfn,prot)       (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
+#define mk_pmd(page,prot)       pfn_pmd(page_to_pfn(page),prot)
+/* represent a notpresent pmd by zero, this is used by pmdp_invalidate */
+#define pmd_mknotpresent(pmd)   (__pmd(0))
+static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
+{
+        const pmdval_t mask = PMD_SECT_USER | PMD_SECT_XN | PMD_SECT_RDONLY |
+                                PMD_SECT_VALID | PMD_SECT_NONE;
+        pmd_val(pmd) = (pmd_val(pmd) & ~mask) | (pgprot_val(newprot) & mask);
+        return pmd;
+}
+static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
+                              pmd_t *pmdp, pmd_t pmd)
+{
+        BUG_ON(addr >= TASK_SIZE);
+        /* create a faulting entry if PROT_NONE protected */
+        if (pmd_val(pmd) & PMD_SECT_NONE)
+                pmd_val(pmd) &= ~PMD_SECT_VALID;
+        *pmdp = __pmd(pmd_val(pmd) | PMD_SECT_nG);
+        flush_pmd_entry(pmdp);
+}
+static inline int has_transparent_hugepage(void)
+{
+        return 1;
+}
 #endif /* __ASSEMBLY__ */
 #endif /* _ASM_PGTABLE_3LEVEL_H */
diff --git a/arch/arm/include/asm/pgtable-nommu.h b/arch/arm/include/asm/pgtable-nommu.h
index 7ec60d6075bf..0642228ff785 100644
--- a/arch/arm/include/asm/pgtable-nommu.h
+++ b/arch/arm/include/asm/pgtable-nommu.h
@@ -79,8 +79,6 @@ extern unsigned int kobjsize(const void *objp);
 * No page table caches to initialise.
 */
 #define pgtable_cache_init()    do { } while (0)
-#define io_remap_pfn_range      remap_pfn_range
 /*
 * All 32bit addresses are effectively valid for vmalloc...
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 9bcd262a9008..04aeb02d2e11 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -24,6 +24,9 @@
 #include <asm/memory.h>
 #include <asm/pgtable-hwdef.h>
+#include <asm/tlbflush.h>
 #ifdef CONFIG_ARM_LPAE
 #include <asm/pgtable-3level.h>
 #else
@@ -318,13 +321,6 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 #define HAVE_ARCH_UNMAPPED_AREA
 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
-/*
- * remap a physical page `pfn' of size `size' with page protection `prot'
- * into virtual address `from'
- */
-#define io_remap_pfn_range(vma,from,pfn,size,prot) \
-                remap_pfn_range(vma, from, pfn, size, prot)
 #define pgtable_cache_init() do { } while (0)
 #endif /* !__ASSEMBLY__ */
diff --git a/arch/arm/include/asm/proc-fns.h b/arch/arm/include/asm/proc-fns.h
index f3628fb3d2b3..5324c1112f3a 100644
--- a/arch/arm/include/asm/proc-fns.h
+++ b/arch/arm/include/asm/proc-fns.h
@@ -60,7 +60,7 @@ extern struct processor {
        /*
         * Set the page table
         */
-        void (*switch_mm)(unsigned long pgd_phys, struct mm_struct *mm);
+        void (*switch_mm)(phys_addr_t pgd_phys, struct mm_struct *mm);
        /*
         * Set a possibly extended PTE.  Non-extended PTEs should
         * ignore 'ext'.
@@ -82,7 +82,7 @@ extern void cpu_proc_init(void);
 extern void cpu_proc_fin(void);
 extern int cpu_do_idle(void);
 extern void cpu_dcache_clean_area(void *, int);
-extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm);
+extern void cpu_do_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm);
 #ifdef CONFIG_ARM_LPAE
 extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte);
 #else
@@ -116,13 +116,25 @@ extern void cpu_resume(void);
 #define cpu_switch_mm(pgd,mm) cpu_do_switch_mm(virt_to_phys(pgd),mm)
 #ifdef CONFIG_ARM_LPAE
+#define cpu_get_ttbr(nr)                                        \
+        ({                                                      \
+                u64 ttbr;                                       \
+                __asm__("mrrc   p15, " #nr ", %Q0, %R0, c2"     \
+                        : "=r" (ttbr));                         \
+                ttbr;                                           \
+        })
+#define cpu_set_ttbr(nr, val)                                   \
+        do {                                                    \
+                u64 ttbr = val;                                 \
+                __asm__("mcrr   p15, " #nr ", %Q0, %R0, c2"     \
+                        : : "r" (ttbr));                        \
+        } while (0)
 #define cpu_get_pgd()   \
        ({                                              \
-                unsigned long pg, pg2;                  \
+                u64 pg = cpu_get_ttbr(0);               \
-                __asm__("mrrc   p15, 0, %0, %1, c2"     \
-                        : "=r" (pg), "=r" (pg2)         \
-                        :                               \
-                        : "cc");                        \
                pg &= ~(PTRS_PER_PGD*sizeof(pgd_t)-1);  \
                (pgd_t *)phys_to_virt(pg);              \
        })
@@ -137,6 +149,10 @@ extern void cpu_resume(void);
        })
 #endif
+#else   /*!CONFIG_MMU */
+#define cpu_switch_mm(pgd,mm)   { }
 #endif
 #endif /* __ASSEMBLY__ */
diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
index 06e7d509eaac..413f3876341c 100644
--- a/arch/arm/include/asm/processor.h
+++ b/arch/arm/include/asm/processor.h
@@ -54,7 +54,6 @@ struct thread_struct {
 #define start_thread(regs,pc,sp)                                        \
 ({                                                                      \
-        unsigned long *stack = (unsigned long *)sp;                     \
        memset(regs->uregs, 0, sizeof(regs->uregs));                    \
        if (current->personality & ADDR_LIMIT_32BIT)                    \
                regs->ARM_cpsr = USR_MODE;                              \
@@ -65,9 +64,6 @@ struct thread_struct {
        regs->ARM_cpsr |= PSR_ENDSTATE;                                 \
        regs->ARM_pc = pc & ~1;         /* pc */                        \
        regs->ARM_sp = sp;              /* sp */                        \
-        regs->ARM_r2 = stack[2];        /* r2 (envp) */                 \
-        regs->ARM_r1 = stack[1];        /* r1 (argv) */                 \
-        regs->ARM_r0 = stack[0];        /* r0 (argc) */                 \
        nommu_start_thread(regs);                                       \
 })
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index ce0dbe7c1625..c4ae171850f8 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -32,5 +32,14 @@ struct psci_operations {
 };
 extern struct psci_operations psci_ops;
+extern struct smp_operations psci_smp_ops;
+#ifdef CONFIG_ARM_PSCI
+void psci_init(void);
+bool psci_smp_available(void);
+#else
+static inline void psci_init(void) { }
+static inline bool psci_smp_available(void) { return false; }
+#endif
 #endif /* __ASM_ARM_PSCI_H */
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index 3d52ee1bfb31..04c99f36ff7f 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -45,6 +45,7 @@ struct pt_regs {
 */
 static inline int valid_user_regs(struct pt_regs *regs)
 {
+#ifndef CONFIG_CPU_V7M
        unsigned long mode = regs->ARM_cpsr & MODE_MASK;
        /*
@@ -67,6 +68,9 @@ static inline int valid_user_regs(struct pt_regs *regs)
                regs->ARM_cpsr |= USR_MODE;
        return 0;
+#else /* ifndef CONFIG_CPU_V7M */
+        return 1;
+#endif
 }
 static inline long regs_return_value(struct pt_regs *regs)
diff --git a/arch/arm/include/asm/sched_clock.h b/arch/arm/include/asm/sched_clock.h
index 3d520ddca61b..2389b71a8e7c 100644
--- a/arch/arm/include/asm/sched_clock.h
+++ b/arch/arm/include/asm/sched_clock.h
@@ -1,16 +1,4 @@
-/*
+/* You shouldn't include this file. Use linux/sched_clock.h instead.
- * sched_clock.h: support for extending counters to full 64-bit ns counter
+ * Temporary file until all asm/sched_clock.h users are gone
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
 */
-#ifndef ASM_SCHED_CLOCK
+#include <linux/sched_clock.h>
-#define ASM_SCHED_CLOCK
-extern void sched_clock_postinit(void);
-extern void setup_sched_clock(u32 (*read)(void), int bits, unsigned long rate);
-extern unsigned long long (*sched_clock_func)(void);
-#endif
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h
index d3a22bebe6ce..a8cae71caceb 100644
--- a/arch/arm/include/asm/smp.h
+++ b/arch/arm/include/asm/smp.h
@@ -65,7 +65,10 @@ asmlinkage void secondary_start_kernel(void);
 * Initial data for bringing up a secondary CPU.
 */
 struct secondary_data {
-        unsigned long pgdir;
+        union {
+                unsigned long mpu_rgn_szr;
+                unsigned long pgdir;
+        };
        unsigned long swapper_pg_dir;
        void *stack;
 };
diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index e78983202737..6462a721ebd4 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -26,6 +26,9 @@ static inline bool is_smp(void)
 }
 /* all SMP configurations have the extended CPUID registers */
+#ifndef CONFIG_MMU
+#define tlb_ops_need_broadcast()        0
+#else
 static inline int tlb_ops_need_broadcast(void)
 {
        if (!is_smp())
@@ -33,6 +36,7 @@ static inline int tlb_ops_need_broadcast(void)
        return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 2;
 }
+#endif
 #if !defined(CONFIG_SMP) || __LINUX_ARM_ARCH__ >= 7
 #define cache_ops_need_broadcast()      0
@@ -66,4 +70,22 @@ static inline int get_logical_index(u32 mpidr)
        return -EINVAL;
 }
+/*
+ * NOTE ! Assembly code relies on the following
+ * structure memory layout in order to carry out load
+ * multiple from its base address. For more
+ * information check arch/arm/kernel/sleep.S
+ */
+struct mpidr_hash {
+        u32     mask; /* used by sleep.S */
+        u32     shift_aff[3]; /* used by sleep.S */
+        u32     bits;
+};
+extern struct mpidr_hash mpidr_hash;
+static inline u32 mpidr_hash_size(void)
+{
+        return 1 << mpidr_hash.bits;
+}
 #endif
diff --git a/arch/arm/include/asm/smp_scu.h b/arch/arm/include/asm/smp_scu.h
index 18d169373612..0393fbab8dd5 100644
--- a/arch/arm/include/asm/smp_scu.h
+++ b/arch/arm/include/asm/smp_scu.h
@@ -23,10 +23,21 @@ static inline unsigned long scu_a9_get_base(void)
        return pa;
 }
+#ifdef CONFIG_HAVE_ARM_SCU
 unsigned int scu_get_core_count(void __iomem *);
 int scu_power_mode(void __iomem *, unsigned int);
+#else
+static inline unsigned int scu_get_core_count(void __iomem *scu_base)
+{
+        return 0;
+}
+static inline int scu_power_mode(void __iomem *scu_base, unsigned int mode)
+{
+        return -EINVAL;
+}
+#endif
-#ifdef CONFIG_SMP
+#if defined(CONFIG_SMP) && defined(CONFIG_HAVE_ARM_SCU)
 void scu_enable(void __iomem *scu_base);
 #else
 static inline void scu_enable(void __iomem *scu_base) {}
diff --git a/arch/arm/include/asm/spinlock.h b/arch/arm/include/asm/spinlock.h
index 6220e9fdf4c7..f8b8965666e9 100644
--- a/arch/arm/include/asm/spinlock.h
+++ b/arch/arm/include/asm/spinlock.h
@@ -97,19 +97,22 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
 static inline int arch_spin_trylock(arch_spinlock_t *lock)
 {
-        unsigned long tmp;
+        unsigned long contended, res;
        u32 slock;
-        __asm__ __volatile__(
+        do {
-"       ldrex   %0, [%2]\n"
+                __asm__ __volatile__(
-"       subs    %1, %0, %0, ror #16\n"
+                "       ldrex   %0, [%3]\n"
-"       addeq   %0, %0, %3\n"
+                "       mov     %2, #0\n"
-"       strexeq %1, %0, [%2]"
+                "       subs    %1, %0, %0, ror #16\n"
-        : "=&r" (slock), "=&r" (tmp)
+                "       addeq   %0, %0, %4\n"
-        : "r" (&lock->slock), "I" (1 << TICKET_SHIFT)
+                "       strexeq %2, %0, [%3]"
-        : "cc");
+                : "=&r" (slock), "=&r" (contended), "=r" (res)
+                : "r" (&lock->slock), "I" (1 << TICKET_SHIFT)
-        if (tmp == 0) {
+                : "cc");
+        } while (res);
+        if (!contended) {
                smp_mb();
                return 1;
        } else {
diff --git a/arch/arm/include/asm/suspend.h b/arch/arm/include/asm/suspend.h
index 1c0a551ae375..cd20029bcd94 100644
--- a/arch/arm/include/asm/suspend.h
+++ b/arch/arm/include/asm/suspend.h
@@ -1,6 +1,11 @@
 #ifndef __ASM_ARM_SUSPEND_H
 #define __ASM_ARM_SUSPEND_H
+struct sleep_save_sp {
+        u32 *save_ptr_stash;
+        u32 save_ptr_stash_phys;
+};
 extern void cpu_resume(void);
 extern int cpu_suspend(unsigned long, int (*)(unsigned long));
diff --git a/arch/arm/include/asm/system_info.h b/arch/arm/include/asm/system_info.h
index dfd386d0c022..720ea0320a6d 100644
--- a/arch/arm/include/asm/system_info.h
+++ b/arch/arm/include/asm/system_info.h
@@ -11,6 +11,7 @@
 #define CPU_ARCH_ARMv5TEJ       7
 #define CPU_ARCH_ARMv6          8
 #define CPU_ARCH_ARMv7          9
+#define CPU_ARCH_ARMv7M         10
 #ifndef __ASSEMBLY__
diff --git a/arch/arm/include/asm/system_misc.h b/arch/arm/include/asm/system_misc.h
index 21a23e378bbe..a3d61ad984af 100644
--- a/arch/arm/include/asm/system_misc.h
+++ b/arch/arm/include/asm/system_misc.h
@@ -6,11 +6,12 @@
 #include <linux/compiler.h>
 #include <linux/linkage.h>
 #include <linux/irqflags.h>
+#include <linux/reboot.h>
 extern void cpu_init(void);
 void soft_restart(unsigned long);
-extern void (*arm_pm_restart)(char str, const char *cmd);
+extern void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd);
 extern void (*arm_pm_idle)(void);
 #define UDBG_UNDEFINED  (1 << 0)
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index 1995d1a84060..2b8114fcba09 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -58,7 +58,7 @@ struct thread_info {
        struct cpu_context_save cpu_context;    /* cpu context */
        __u32                   syscall;        /* syscall number */
        __u8                    used_cp[16];    /* thread used copro */
-        unsigned long           tp_value;
+        unsigned long           tp_value[2];    /* TLS registers */
 #ifdef CONFIG_CRUNCH
        struct crunch_state     crunchstate;
 #endif
@@ -156,7 +156,6 @@ extern int vfp_restore_user_hwstate(struct user_vfp __user *,
 #define TIF_USING_IWMMXT        17
 #define TIF_MEMDIE              18      /* is terminating due to OOM killer */
 #define TIF_RESTORE_SIGMASK     20
-#define TIF_SWITCH_MM           22      /* deferred switch_mm */
 #define _TIF_SIGPENDING         (1 << TIF_SIGPENDING)
 #define _TIF_NEED_RESCHED       (1 << TIF_NEED_RESCHED)
diff --git a/arch/arm/include/asm/tlb.h b/arch/arm/include/asm/tlb.h
index bdf2b8458ec1..46e7cfb3e721 100644
--- a/arch/arm/include/asm/tlb.h
+++ b/arch/arm/include/asm/tlb.h
@@ -204,6 +204,12 @@ static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp,
 #endif
 }
+static inline void
+tlb_remove_pmd_tlb_entry(struct mmu_gather *tlb, pmd_t *pmdp, unsigned long addr)
+{
+        tlb_add_flush(tlb, addr);
+}
 #define pte_free_tlb(tlb, ptep, addr)   __pte_free_tlb(tlb, ptep, addr)
 #define pmd_free_tlb(tlb, pmdp, addr)   __pmd_free_tlb(tlb, pmdp, addr)
 #define pud_free_tlb(tlb, pudp, addr)   pud_free((tlb)->mm, pudp)
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index a3625d141c1d..f467e9b3f8d5 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -443,7 +443,18 @@ static inline void local_flush_bp_all(void)
                isb();
 }
+#include <asm/cputype.h>
 #ifdef CONFIG_ARM_ERRATA_798181
+static inline int erratum_a15_798181(void)
+{
+        unsigned int midr = read_cpuid_id();
+        /* Cortex-A15 r0p0..r3p2 affected */
+        if ((midr & 0xff0ffff0) != 0x410fc0f0 || midr > 0x413fc0f2)
+                return 0;
+        return 1;
+}
 static inline void dummy_flush_tlb_a15_erratum(void)
 {
        /*
@@ -453,6 +464,11 @@ static inline void dummy_flush_tlb_a15_erratum(void)
        dsb();
 }
 #else
+static inline int erratum_a15_798181(void)
+{
+        return 0;
+}
 static inline void dummy_flush_tlb_a15_erratum(void)
 {
 }
@@ -535,8 +551,33 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
 }
 #endif
+#define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
 #endif
-#endif /* CONFIG_MMU */
+#elif defined(CONFIG_SMP)       /* !CONFIG_MMU */
+#ifndef __ASSEMBLY__
+#include <linux/mm_types.h>
+static inline void local_flush_tlb_all(void)                                                                    { }
+static inline void local_flush_tlb_mm(struct mm_struct *mm)                                                     { }
+static inline void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)                        { }
+static inline void local_flush_tlb_kernel_page(unsigned long kaddr)                                             { }
+static inline void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)    { }
+static inline void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)                         { }
+static inline void local_flush_bp_all(void)                                                                     { }
+extern void flush_tlb_all(void);
+extern void flush_tlb_mm(struct mm_struct *mm);
+extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr);
+extern void flush_tlb_kernel_page(unsigned long kaddr);
+extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
+extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
+extern void flush_bp_all(void);
+#endif  /* __ASSEMBLY__ */
+#endif
 #endif
diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h
index 73409e6c0251..83259b873333 100644
--- a/arch/arm/include/asm/tls.h
+++ b/arch/arm/include/asm/tls.h
@@ -2,27 +2,30 @@
 #define __ASMARM_TLS_H
 #ifdef __ASSEMBLY__
-        .macro set_tls_none, tp, tmp1, tmp2
+#include <asm/asm-offsets.h>
+        .macro switch_tls_none, base, tp, tpuser, tmp1, tmp2
        .endm
-        .macro set_tls_v6k, tp, tmp1, tmp2
+        .macro switch_tls_v6k, base, tp, tpuser, tmp1, tmp2
+        mrc     p15, 0, \tmp2, c13, c0, 2       @ get the user r/w register
        mcr     p15, 0, \tp, c13, c0, 3         @ set TLS register
-        mov     \tmp1, #0
+        mcr     p15, 0, \tpuser, c13, c0, 2     @ and the user r/w register
-        mcr     p15, 0, \tmp1, c13, c0, 2       @ clear user r/w TLS register
+        str     \tmp2, [\base, #TI_TP_VALUE + 4] @ save it
        .endm
-        .macro set_tls_v6, tp, tmp1, tmp2
+        .macro switch_tls_v6, base, tp, tpuser, tmp1, tmp2
        ldr     \tmp1, =elf_hwcap
        ldr     \tmp1, [\tmp1, #0]
        mov     \tmp2, #0xffff0fff
        tst     \tmp1, #HWCAP_TLS               @ hardware TLS available?
-        mcrne   p15, 0, \tp, c13, c0, 3         @ yes, set TLS register
-        movne   \tmp1, #0
-        mcrne   p15, 0, \tmp1, c13, c0, 2       @ clear user r/w TLS register
        streq   \tp, [\tmp2, #-15]              @ set TLS value at 0xffff0ff0
+        mrcne   p15, 0, \tmp2, c13, c0, 2       @ get the user r/w register
+        mcrne   p15, 0, \tp, c13, c0, 3         @ yes, set TLS register
+        mcrne   p15, 0, \tpuser, c13, c0, 2     @ set user r/w register
+        strne   \tmp2, [\base, #TI_TP_VALUE + 4] @ save it
        .endm
-        .macro set_tls_software, tp, tmp1, tmp2
+        .macro switch_tls_software, base, tp, tpuser, tmp1, tmp2
        mov     \tmp1, #0xffff0fff
        str     \tp, [\tmp1, #-15]              @ set TLS value at 0xffff0ff0
        .endm
@@ -31,19 +34,30 @@
 #ifdef CONFIG_TLS_REG_EMUL
 #define tls_emu         1
 #define has_tls_reg             1
-#define set_tls         set_tls_none
+#define switch_tls      switch_tls_none
 #elif defined(CONFIG_CPU_V6)
 #define tls_emu         0
 #define has_tls_reg             (elf_hwcap & HWCAP_TLS)
-#define set_tls         set_tls_v6
+#define switch_tls      switch_tls_v6
 #elif defined(CONFIG_CPU_32v6K)
 #define tls_emu         0
 #define has_tls_reg             1
-#define set_tls         set_tls_v6k
+#define switch_tls      switch_tls_v6k
 #else
 #define tls_emu         0
 #define has_tls_reg             0
-#define set_tls         set_tls_software
+#define switch_tls      switch_tls_software
 #endif
+#ifndef __ASSEMBLY__
+static inline unsigned long get_tpuser(void)
+{
+        unsigned long reg = 0;
+        if (has_tls_reg && !tls_emu)
+                __asm__("mrc p15, 0, %0, c13, c0, 2" : "=r" (reg));
+        return reg;
+}
+#endif
 #endif  /* __ASMARM_TLS_H */
diff --git a/arch/arm/include/asm/v7m.h b/arch/arm/include/asm/v7m.h
new file mode 100644
index 000000000000..fa88d09fa3d9
--- /dev/null
+++ b/arch/arm/include/asm/v7m.h
@@ -0,0 +1,44 @@
+/*
+ * Common defines for v7m cpus
+ */
+#define V7M_SCS_ICTR                    IOMEM(0xe000e004)
+#define V7M_SCS_ICTR_INTLINESNUM_MASK           0x0000000f
+#define BASEADDR_V7M_SCB                IOMEM(0xe000ed00)
+#define V7M_SCB_CPUID                   0x00
+#define V7M_SCB_ICSR                    0x04
+#define V7M_SCB_ICSR_PENDSVSET                  (1 << 28)
+#define V7M_SCB_ICSR_PENDSVCLR                  (1 << 27)
+#define V7M_SCB_ICSR_RETTOBASE                  (1 << 11)
+#define V7M_SCB_VTOR                    0x08
+#define V7M_SCB_SCR                     0x10
+#define V7M_SCB_SCR_SLEEPDEEP                   (1 << 2)
+#define V7M_SCB_CCR                     0x14
+#define V7M_SCB_CCR_STKALIGN                    (1 << 9)
+#define V7M_SCB_SHPR2                   0x1c
+#define V7M_SCB_SHPR3                   0x20
+#define V7M_SCB_SHCSR                   0x24
+#define V7M_SCB_SHCSR_USGFAULTENA               (1 << 18)
+#define V7M_SCB_SHCSR_BUSFAULTENA               (1 << 17)
+#define V7M_SCB_SHCSR_MEMFAULTENA               (1 << 16)
+#define V7M_xPSR_FRAMEPTRALIGN                  0x00000200
+#define V7M_xPSR_EXCEPTIONNO                    0x000001ff
+/*
+ * When branching to an address that has bits [31:28] == 0xf an exception return
+ * occurs. Bits [27:5] are reserved (SBOP). If the processor implements the FP
+ * extension Bit [4] defines if the exception frame has space allocated for FP
+ * state information, SBOP otherwise. Bit [3] defines the mode that is returned
+ * to (0 -> handler mode; 1 -> thread mode). Bit [2] defines which sp is used
+ * (0 -> msp; 1 -> psp). Bits [1:0] are fixed to 0b01.
+ */
+#define EXC_RET_STACK_MASK                      0x00000004
+#define EXC_RET_THREADMODE_PROCESSSTACK         0xfffffffd
diff --git a/arch/arm/include/asm/virt.h b/arch/arm/include/asm/virt.h
index 50af92bac737..4371f45c5784 100644
--- a/arch/arm/include/asm/virt.h
+++ b/arch/arm/include/asm/virt.h
@@ -29,6 +29,7 @@
 #define BOOT_CPU_MODE_MISMATCH  PSR_N_BIT
 #ifndef __ASSEMBLY__
+#include <asm/cacheflush.h>
 #ifdef CONFIG_ARM_VIRT_EXT
 /*
@@ -41,10 +42,21 @@
 */
 extern int __boot_cpu_mode;
+static inline void sync_boot_mode(void)
+{
+        /*
+         * As secondaries write to __boot_cpu_mode with caches disabled, we
+         * must flush the corresponding cache entries to ensure the visibility
+         * of their writes.
+         */
+        sync_cache_r(&__boot_cpu_mode);
+}
 void __hyp_set_vectors(unsigned long phys_vector_base);
 unsigned long __hyp_get_vectors(void);
 #else
 #define __boot_cpu_mode (SVC_MODE)
+#define sync_boot_mode()
 #endif
 #ifndef ZIMAGE
diff --git a/arch/arm/include/asm/xen/hypercall.h b/arch/arm/include/asm/xen/hypercall.h
index 799f42ecca63..7704e28c3483 100644
--- a/arch/arm/include/asm/xen/hypercall.h
+++ b/arch/arm/include/asm/xen/hypercall.h
@@ -47,6 +47,7 @@ unsigned long HYPERVISOR_hvm_op(int op, void *arg);
 int HYPERVISOR_memory_op(unsigned int cmd, void *arg);
 int HYPERVISOR_physdev_op(int cmd, void *arg);
 int HYPERVISOR_vcpu_op(int cmd, int vcpuid, void *extra_args);
+int HYPERVISOR_tmem_op(void *arg);
 static inline void
 MULTI_update_va_mapping(struct multicall_entry *mcl, unsigned long va,
diff --git a/arch/arm/include/asm/xen/page.h b/arch/arm/include/asm/xen/page.h
index 30cdacb675af..359a7b50b158 100644
--- a/arch/arm/include/asm/xen/page.h
+++ b/arch/arm/include/asm/xen/page.h
@@ -1,7 +1,6 @@
 #ifndef _ASM_ARM_XEN_PAGE_H
 #define _ASM_ARM_XEN_PAGE_H
-#include <asm/mach/map.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
@@ -88,6 +87,6 @@ static inline bool set_phys_to_machine(unsigned long pfn, unsigned long mfn)
        return __set_phys_to_machine(pfn, mfn);
 }
-#define xen_remap(cookie, size) __arm_ioremap((cookie), (size), MT_MEMORY);
+#define xen_remap(cookie, size) ioremap_cached((cookie), (size));
 #endif /* _ASM_ARM_XEN_PAGE_H */
diff --git a/arch/arm/include/debug/imx-uart.h b/arch/arm/include/debug/imx-uart.h
index 91d38e38a0b4..29da84e183f4 100644
--- a/arch/arm/include/debug/imx-uart.h
+++ b/arch/arm/include/debug/imx-uart.h
@@ -65,6 +65,14 @@
 #define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR
 #define IMX6Q_UART_BASE(n)      IMX6Q_UART_BASE_ADDR(n)
+#define IMX6SL_UART1_BASE_ADDR  0x02020000
+#define IMX6SL_UART2_BASE_ADDR  0x02024000
+#define IMX6SL_UART3_BASE_ADDR  0x02034000
+#define IMX6SL_UART4_BASE_ADDR  0x02038000
+#define IMX6SL_UART5_BASE_ADDR  0x02018000
+#define IMX6SL_UART_BASE_ADDR(n) IMX6SL_UART##n##_BASE_ADDR
+#define IMX6SL_UART_BASE(n)     IMX6SL_UART_BASE_ADDR(n)
 #define IMX_DEBUG_UART_BASE(soc) soc##_UART_BASE(CONFIG_DEBUG_IMX_UART_PORT)
 #ifdef CONFIG_DEBUG_IMX1_UART
@@ -83,6 +91,8 @@
 #define UART_PADDR      IMX_DEBUG_UART_BASE(IMX53)
 #elif defined(CONFIG_DEBUG_IMX6Q_UART)
 #define UART_PADDR      IMX_DEBUG_UART_BASE(IMX6Q)
+#elif defined(CONFIG_DEBUG_IMX6SL_UART)
+#define UART_PADDR      IMX_DEBUG_UART_BASE(IMX6SL)
 #endif
 #endif /* __DEBUG_IMX_UART_H */
diff --git a/arch/arm/include/debug/keystone.S b/arch/arm/include/debug/keystone.S
new file mode 100644
index 000000000000..9aef9ba3f4f0
--- /dev/null
+++ b/arch/arm/include/debug/keystone.S
@@ -0,0 +1,43 @@
+/*
+ * Early serial debug output macro for Keystone SOCs
+ *
+ * Copyright 2013 Texas Instruments, Inc.
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * Based on RMKs low level debug code.
+ *  Copyright (C) 1994-1999 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/serial_reg.h>
+#define UART_SHIFT 2
+#if defined(CONFIG_DEBUG_KEYSTONE_UART0)
+#define UART_PHYS               0x02530c00
+#define UART_VIRT               0xfeb30c00
+#elif defined(CONFIG_DEBUG_KEYSTONE_UART1)
+#define UART_PHYS               0x02531000
+#define UART_VIRT               0xfeb31000
+#endif
+        .macro  addruart, rp, rv, tmp
+        ldr     \rv, =UART_VIRT                 @ physical base address
+        ldr     \rp, =UART_PHYS                 @ virtual base address
+        .endm
+        .macro  senduart,rd,rx
+        str     \rd, [\rx, #UART_TX << UART_SHIFT]
+        .endm
+        .macro  busyuart,rd,rx
+1002:   ldr     \rd, [\rx, #UART_LSR << UART_SHIFT]
+        and     \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
+        teq     \rd, #UART_LSR_TEMT | UART_LSR_THRE
+        bne     1002b
+        .endm
+        .macro  waituart,rd,rx
+        .endm
diff --git a/arch/arm/include/debug/mvebu.S b/arch/arm/include/debug/mvebu.S
index df191afa3be1..6517311a1c91 100644
--- a/arch/arm/include/debug/mvebu.S
+++ b/arch/arm/include/debug/mvebu.S
@@ -11,7 +11,12 @@
 * published by the Free Software Foundation.
 */
+#ifdef CONFIG_DEBUG_MVEBU_UART_ALTERNATE
+#define ARMADA_370_XP_REGS_PHYS_BASE    0xf1000000
+#else
 #define ARMADA_370_XP_REGS_PHYS_BASE    0xd0000000
+#endif
 #define ARMADA_370_XP_REGS_VIRT_BASE    0xfec00000
        .macro  addruart, rp, rv, tmp
diff --git a/arch/arm/include/debug/nspire.S b/arch/arm/include/debug/nspire.S
new file mode 100644
index 000000000000..886fd276fcbc
--- /dev/null
+++ b/arch/arm/include/debug/nspire.S
@@ -0,0 +1,28 @@
+/*
+ *      linux/arch/arm/include/debug/nspire.S
+ *
+ *      Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+#define NSPIRE_EARLY_UART_PHYS_BASE        0x90020000
+#define NSPIRE_EARLY_UART_VIRT_BASE        0xfee20000
+.macro  addruart, rp, rv, tmp
+        ldr \rp, =(NSPIRE_EARLY_UART_PHYS_BASE)         @ physical base address
+        ldr \rv, =(NSPIRE_EARLY_UART_VIRT_BASE)         @ virtual base address
+.endm
+#ifdef CONFIG_DEBUG_NSPIRE_CX_UART
+#include <asm/hardware/debug-pl01x.S>
+#endif
+#ifdef CONFIG_DEBUG_NSPIRE_CLASSIC_UART
+#define UART_SHIFT 2
+#include <asm/hardware/debug-8250.S>
+#endif
diff --git a/arch/arm/include/debug/rockchip.S b/arch/arm/include/debug/rockchip.S
new file mode 100644
index 000000000000..cfd883e69588
--- /dev/null
+++ b/arch/arm/include/debug/rockchip.S
@@ -0,0 +1,42 @@
+/*
+ * Early serial output macro for Rockchip SoCs
+ *
+ * Copyright (C) 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#if defined(CONFIG_DEBUG_RK29_UART0)
+#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20060000
+#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed60000
+#elif defined(CONFIG_DEBUG_RK29_UART1)
+#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20064000
+#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed64000
+#elif defined(CONFIG_DEBUG_RK29_UART2)
+#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20068000
+#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed68000
+#elif defined(CONFIG_DEBUG_RK3X_UART0)
+#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x10124000
+#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfeb24000
+#elif defined(CONFIG_DEBUG_RK3X_UART1)
+#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x10126000
+#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfeb26000
+#elif defined(CONFIG_DEBUG_RK3X_UART2)
+#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20064000
+#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed64000
+#elif defined(CONFIG_DEBUG_RK3X_UART3)
+#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20068000
+#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed68000
+#endif
+        .macro  addruart, rp, rv, tmp
+        ldr     \rp, =ROCKCHIP_UART_DEBUG_PHYS_BASE
+        ldr     \rv, =ROCKCHIP_UART_DEBUG_VIRT_BASE
+        .endm
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/include/debug/sti.S b/arch/arm/include/debug/sti.S
new file mode 100644
index 000000000000..e3aa58ff1776
--- /dev/null
+++ b/arch/arm/include/debug/sti.S
@@ -0,0 +1,61 @@
+/*
+ * arch/arm/include/debug/sti.S
+ *
+ * Debugging macro include header
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#define STIH41X_COMMS_BASE              0xfed00000
+#define STIH41X_ASC2_BASE               (STIH41X_COMMS_BASE+0x32000)
+#define STIH41X_SBC_LPM_BASE            0xfe400000
+#define STIH41X_SBC_COMMS_BASE          (STIH41X_SBC_LPM_BASE + 0x100000)
+#define STIH41X_SBC_ASC1_BASE           (STIH41X_SBC_COMMS_BASE + 0x31000)
+#define VIRT_ADDRESS(x)         (x - 0x1000000)
+#if IS_ENABLED(CONFIG_STIH41X_DEBUG_ASC2)
+#define DEBUG_LL_UART_BASE      STIH41X_ASC2_BASE
+#endif
+#if IS_ENABLED(CONFIG_STIH41X_DEBUG_SBC_ASC1)
+#define DEBUG_LL_UART_BASE      STIH41X_SBC_ASC1_BASE
+#endif
+#ifndef DEBUG_LL_UART_BASE
+#error "DEBUG UART is not Configured"
+#endif
+#define ASC_TX_BUF_OFF  0x04
+#define ASC_CTRL_OFF    0x0c
+#define ASC_STA_OFF     0x14
+#define ASC_STA_TX_FULL         (1<<9)
+#define ASC_STA_TX_EMPTY        (1<<1)
+                .macro  addruart, rp, rv, tmp
+                ldr     \rp,      =DEBUG_LL_UART_BASE   @ physical base
+                ldr     \rv,      =VIRT_ADDRESS(DEBUG_LL_UART_BASE) @ virt base
+                .endm
+                .macro  senduart,rd,rx
+                strb    \rd, [\rx, #ASC_TX_BUF_OFF]
+                .endm
+                .macro  waituart,rd,rx
+1001:           ldr     \rd, [\rx, #ASC_STA_OFF]
+                tst     \rd, #ASC_STA_TX_FULL
+                bne     1001b
+                .endm
+                .macro  busyuart,rd,rx
+1001:           ldr     \rd, [\rx, #ASC_STA_OFF]
+                tst     \rd, #ASC_STA_TX_EMPTY
+                beq     1001b
+                .endm
diff --git a/arch/arm/mach-u300/include/mach/debug-macro.S b/arch/arm/include/debug/u300.S
index 8ae8e4ab34b0..6f04f08a203c 100644
--- a/arch/arm/mach-u300/include/mach/debug-macro.S
+++ b/arch/arm/include/debug/u300.S
@@ -1,14 +1,11 @@
 /*
- *
+ * Copyright (C) 2006-2013 ST-Ericsson AB
- * arch-arm/mach-u300/include/mach/debug-macro.S
- *
- *
- * Copyright (C) 2006-2009 ST-Ericsson AB
 * License terms: GNU General Public License (GPL) version 2
 * Debugging macro include header.
 * Author: Linus Walleij <linus.walleij@stericsson.com>
 */
-#include <mach/hardware.h>
+#define U300_SLOW_PER_PHYS_BASE         0xc0010000
+#define U300_SLOW_PER_VIRT_BASE         0xff000000
        .macro  addruart, rp, rv, tmp
        /* If we move the address using MMU, use this. */
diff --git a/arch/arm/include/debug/vexpress.S b/arch/arm/include/debug/vexpress.S
index dc8e882a6257..acafb229e2b6 100644
--- a/arch/arm/include/debug/vexpress.S
+++ b/arch/arm/include/debug/vexpress.S
@@ -16,6 +16,8 @@
 #define DEBUG_LL_PHYS_BASE_RS1          0x1c000000
 #define DEBUG_LL_UART_OFFSET_RS1        0x00090000
+#define DEBUG_LL_UART_PHYS_CRX          0xb0090000
 #define DEBUG_LL_VIRT_BASE              0xf8000000
 #if defined(CONFIG_DEBUG_VEXPRESS_UART0_DETECT)
@@ -67,6 +69,14 @@
 #include <asm/hardware/debug-pl01x.S>
+#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_CRX)
+                .macro  addruart,rp,tmp,tmp2
+                ldr     \rp, =DEBUG_LL_UART_PHYS_CRX
+                .endm
+#include <asm/hardware/debug-pl01x.S>
 #else /* CONFIG_DEBUG_LL_UART_NONE */
                .macro  addruart, rp, rv, tmp
diff --git a/arch/arm/include/uapi/asm/Kbuild b/arch/arm/include/uapi/asm/Kbuild
index 47bcb2d254af..18d76fd5a2af 100644
--- a/arch/arm/include/uapi/asm/Kbuild
+++ b/arch/arm/include/uapi/asm/Kbuild
@@ -1,7 +1,6 @@
 # UAPI Header export list
 include include/uapi/asm-generic/Kbuild.asm
-header-y += a.out.h
 header-y += byteorder.h
 header-y += fcntl.h
 header-y += hwcap.h
diff --git a/arch/arm/include/uapi/asm/a.out.h b/arch/arm/include/uapi/asm/a.out.h
deleted file mode 100644
index 083894b2e3bc..000000000000
--- a/arch/arm/include/uapi/asm/a.out.h
+++ /dev/null
@@ -1,34 +0,0 @@
-#ifndef __ARM_A_OUT_H__
-#define __ARM_A_OUT_H__
-#include <linux/personality.h>
-#include <linux/types.h>
-struct exec
-{
-  __u32 a_info;         /* Use macros N_MAGIC, etc for access */
-  __u32 a_text;         /* length of text, in bytes */
-  __u32 a_data;         /* length of data, in bytes */
-  __u32 a_bss;          /* length of uninitialized data area for file, in bytes */
-  __u32 a_syms;         /* length of symbol table data in file, in bytes */
-  __u32 a_entry;        /* start address */
-  __u32 a_trsize;       /* length of relocation info for text, in bytes */
-  __u32 a_drsize;       /* length of relocation info for data, in bytes */
-};
-/*
- * This is always the same
- */
-#define N_TXTADDR(a)    (0x00008000)
-#define N_TRSIZE(a)     ((a).a_trsize)
-#define N_DRSIZE(a)     ((a).a_drsize)
-#define N_SYMSIZE(a)    ((a).a_syms)
-#define M_ARM 103
-#ifndef LIBRARY_START_TEXT
-#define LIBRARY_START_TEXT      (0x00c00000)
-#endif
-#endif /* __A_OUT_GNU_H__ */
diff --git a/arch/arm/include/uapi/asm/hwcap.h b/arch/arm/include/uapi/asm/hwcap.h
index 3688fd15a32d..6d34d080372a 100644
--- a/arch/arm/include/uapi/asm/hwcap.h
+++ b/arch/arm/include/uapi/asm/hwcap.h
@@ -25,6 +25,6 @@
 #define HWCAP_IDIVT     (1 << 18)
 #define HWCAP_VFPD32    (1 << 19)       /* set if VFP has 32 regs (not 16) */
 #define HWCAP_IDIV      (HWCAP_IDIVA | HWCAP_IDIVT)
+#define HWCAP_LPAE      (1 << 20)
 #endif /* _UAPI__ASMARM_HWCAP_H */
diff --git a/arch/arm/include/uapi/asm/ptrace.h b/arch/arm/include/uapi/asm/ptrace.h
index 96ee0929790f..5af0ed1b825a 100644
--- a/arch/arm/include/uapi/asm/ptrace.h
+++ b/arch/arm/include/uapi/asm/ptrace.h
@@ -34,28 +34,47 @@
 /*
 * PSR bits
+ * Note on V7M there is no mode contained in the PSR
 */
 #define USR26_MODE      0x00000000
 #define FIQ26_MODE      0x00000001
 #define IRQ26_MODE      0x00000002
 #define SVC26_MODE      0x00000003
+#if defined(__KERNEL__) && defined(CONFIG_CPU_V7M)
+/*
+ * Use 0 here to get code right that creates a userspace
+ * or kernel space thread.
+ */
+#define USR_MODE        0x00000000
+#define SVC_MODE        0x00000000
+#else
 #define USR_MODE        0x00000010
+#define SVC_MODE        0x00000013
+#endif
 #define FIQ_MODE        0x00000011
 #define IRQ_MODE        0x00000012
-#define SVC_MODE        0x00000013
 #define ABT_MODE        0x00000017
 #define HYP_MODE        0x0000001a
 #define UND_MODE        0x0000001b
 #define SYSTEM_MODE     0x0000001f
 #define MODE32_BIT      0x00000010
 #define MODE_MASK       0x0000001f
-#define PSR_T_BIT       0x00000020
-#define PSR_F_BIT       0x00000040
+#define V4_PSR_T_BIT    0x00000020      /* >= V4T, but not V7M */
-#define PSR_I_BIT       0x00000080
+#define V7M_PSR_T_BIT   0x01000000
-#define PSR_A_BIT       0x00000100
+#if defined(__KERNEL__) && defined(CONFIG_CPU_V7M)
-#define PSR_E_BIT       0x00000200
+#define PSR_T_BIT       V7M_PSR_T_BIT
-#define PSR_J_BIT       0x01000000
+#else
-#define PSR_Q_BIT       0x08000000
+/* for compatibility */
+#define PSR_T_BIT       V4_PSR_T_BIT
+#endif
+#define PSR_F_BIT       0x00000040      /* >= V4, but not V7M */
+#define PSR_I_BIT       0x00000080      /* >= V4, but not V7M */
+#define PSR_A_BIT       0x00000100      /* >= V6, but not V7M */
+#define PSR_E_BIT       0x00000200      /* >= V6, but not V7M */
+#define PSR_J_BIT       0x01000000      /* >= V5J, but not V7M */
+#define PSR_Q_BIT       0x08000000      /* >= V5E, including V7M */
 #define PSR_V_BIT       0x10000000
 #define PSR_C_BIT       0x20000000
 #define PSR_Z_BIT       0x40000000
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 5f3338eacad2..86d10dd47dc4 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -15,14 +15,20 @@ CFLAGS_REMOVE_return_address.o = -pg
 # Object file lists.
-obj-y           := elf.o entry-armv.o entry-common.o irq.o opcodes.o \
+obj-y           := elf.o entry-common.o irq.o opcodes.o \
-                   process.o ptrace.o return_address.o sched_clock.o \
+                   process.o ptrace.o return_address.o \
                   setup.o signal.o stacktrace.o sys_arm.o time.o traps.o
 obj-$(CONFIG_ATAGS)             += atags_parse.o
 obj-$(CONFIG_ATAGS_PROC)        += atags_proc.o
 obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) += atags_compat.o
+ifeq ($(CONFIG_CPU_V7M),y)
+obj-y           += entry-v7m.o
+else
+obj-y           += entry-armv.o
+endif
 obj-$(CONFIG_OC_ETM)            += etm.o
 obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
 obj-$(CONFIG_ISA_DMA_API)       += dma.o
@@ -32,7 +38,10 @@ obj-$(CONFIG_ARTHUR)		+= arthur.o
 obj-$(CONFIG_ISA_DMA)           += dma-isa.o
 obj-$(CONFIG_PCI)               += bios32.o isa.o
 obj-$(CONFIG_ARM_CPU_SUSPEND)   += sleep.o suspend.o
-obj-$(CONFIG_SMP)               += smp.o smp_tlb.o
+obj-$(CONFIG_SMP)               += smp.o
+ifdef CONFIG_MMU
+obj-$(CONFIG_SMP)               += smp_tlb.o
+endif
 obj-$(CONFIG_HAVE_ARM_SCU)      += smp_scu.o
 obj-$(CONFIG_HAVE_ARM_TWD)      += smp_twd.o
 obj-$(CONFIG_ARM_ARCH_TIMER)    += arch_timer.o
@@ -82,6 +91,9 @@ obj-$(CONFIG_DEBUG_LL)	+= debug.o
 obj-$(CONFIG_EARLY_PRINTK)      += early_printk.o
 obj-$(CONFIG_ARM_VIRT_EXT)      += hyp-stub.o
-obj-$(CONFIG_ARM_PSCI)          += psci.o
+ifeq ($(CONFIG_ARM_PSCI),y)
+obj-y                           += psci.o
+obj-$(CONFIG_SMP)               += psci_smp.o
+endif
 extra-y := $(head-y) vmlinux.lds
diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
index 59dcdced6e30..221f07b11ccb 100644
--- a/arch/arm/kernel/arch_timer.c
+++ b/arch/arm/kernel/arch_timer.c
@@ -11,9 +11,9 @@
 #include <linux/init.h>
 #include <linux/types.h>
 #include <linux/errno.h>
+#include <linux/sched_clock.h>
 #include <asm/delay.h>
-#include <asm/sched_clock.h>
 #include <clocksource/arm_arch_timer.h>
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index ee68cce6b48e..ded041711beb 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -23,6 +23,7 @@
 #include <asm/thread_info.h>
 #include <asm/memory.h>
 #include <asm/procinfo.h>
+#include <asm/suspend.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <linux/kbuild.h>
@@ -145,6 +146,11 @@ int main(void)
 #ifdef MULTI_CACHE
  DEFINE(CACHE_FLUSH_KERN_ALL,  offsetof(struct cpu_cache_fns, flush_kern_all));
 #endif
+#ifdef CONFIG_ARM_CPU_SUSPEND
+  DEFINE(SLEEP_SAVE_SP_SZ,      sizeof(struct sleep_save_sp));
+  DEFINE(SLEEP_SAVE_SP_PHYS,    offsetof(struct sleep_save_sp, save_ptr_stash_phys));
+  DEFINE(SLEEP_SAVE_SP_VIRT,    offsetof(struct sleep_save_sp, save_ptr_stash));
+#endif
  BLANK();
  DEFINE(DMA_BIDIRECTIONAL,     DMA_BIDIRECTIONAL);
  DEFINE(DMA_TO_DEVICE,         DMA_TO_DEVICE);
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index b2ed73c45489..261fcc826169 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -445,7 +445,8 @@ static int pcibios_init_resources(int busnr, struct pci_sys_data *sys)
        return 0;
 }
-static void pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
+static void pcibios_init_hw(struct device *parent, struct hw_pci *hw,
+                            struct list_head *head)
 {
        struct pci_sys_data *sys = NULL;
        int ret;
@@ -480,7 +481,7 @@ static void pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
                        if (hw->scan)
                                sys->bus = hw->scan(nr, sys);
                        else
-                                sys->bus = pci_scan_root_bus(NULL, sys->busnr,
+                                sys->bus = pci_scan_root_bus(parent, sys->busnr,
                                                hw->ops, sys, &sys->resources);
                        if (!sys->bus)
@@ -497,7 +498,7 @@ static void pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
        }
 }
-void pci_common_init(struct hw_pci *hw)
+void pci_common_init_dev(struct device *parent, struct hw_pci *hw)
 {
        struct pci_sys_data *sys;
        LIST_HEAD(head);
@@ -505,7 +506,7 @@ void pci_common_init(struct hw_pci *hw)
        pci_add_flags(PCI_REASSIGN_ALL_RSRC);
        if (hw->preinit)
                hw->preinit();
-        pcibios_init_hw(hw, &head);
+        pcibios_init_hw(parent, hw, &head);
        if (hw->postinit)
                hw->postinit();
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 582b405befc5..d40d0ef389db 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -685,15 +685,16 @@ ENTRY(__switch_to)
 UNWIND(.fnstart        )
 UNWIND(.cantunwind     )
        add     ip, r1, #TI_CPU_SAVE
-        ldr     r3, [r2, #TI_TP_VALUE]
 ARM(   stmia   ip!, {r4 - sl, fp, sp, lr} )    @ Store most regs on stack
 THUMB( stmia   ip!, {r4 - sl, fp}         )    @ Store most regs on stack
 THUMB( str     sp, [ip], #4               )
 THUMB( str     lr, [ip], #4               )
+        ldr     r4, [r2, #TI_TP_VALUE]
+        ldr     r5, [r2, #TI_TP_VALUE + 4]
 #ifdef CONFIG_CPU_USE_DOMAINS
        ldr     r6, [r2, #TI_CPU_DOMAIN]
 #endif
-        set_tls r3, r4, r5
+        switch_tls r1, r4, r5, r3, r7
 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
        ldr     r7, [r2, #TI_TASK]
        ldr     r8, =__stack_chk_guard
@@ -741,6 +742,18 @@ ENDPROC(__switch_to)
 #endif
        .endm
+        .macro  kuser_pad, sym, size
+        .if     (. - \sym) & 3
+        .rept   4 - (. - \sym) & 3
+        .byte   0
+        .endr
+        .endif
+        .rept   (\size - (. - \sym)) / 4
+        .word   0xe7fddef1
+        .endr
+        .endm
+#ifdef CONFIG_KUSER_HELPERS
        .align  5
        .globl  __kuser_helper_start
 __kuser_helper_start:
@@ -831,18 +844,13 @@ kuser_cmpxchg64_fixup:
 #error "incoherent kernel configuration"
 #endif
-        /* pad to next slot */
+        kuser_pad __kuser_cmpxchg64, 64
-        .rept   (16 - (. - __kuser_cmpxchg64)/4)
-        .word   0
-        .endr
-        .align  5
 __kuser_memory_barrier:                         @ 0xffff0fa0
        smp_dmb arm
        usr_ret lr
-        .align  5
+        kuser_pad __kuser_memory_barrier, 32
 __kuser_cmpxchg:                                @ 0xffff0fc0
@@ -915,13 +923,14 @@ kuser_cmpxchg32_fixup:
 #endif
-        .align  5
+        kuser_pad __kuser_cmpxchg, 32
 __kuser_get_tls:                                @ 0xffff0fe0
        ldr     r0, [pc, #(16 - 8)]     @ read TLS, set in kuser_get_tls_init
        usr_ret lr
        mrc     p15, 0, r0, c13, c0, 3  @ 0xffff0fe8 hardware TLS code
-        .rep    4
+        kuser_pad __kuser_get_tls, 16
+        .rep    3
        .word   0                       @ 0xffff0ff0 software TLS value, then
        .endr                           @ pad up to __kuser_helper_version
@@ -931,14 +940,16 @@ __kuser_helper_version:				@ 0xffff0ffc
        .globl  __kuser_helper_end
 __kuser_helper_end:
+#endif
 THUMB( .thumb  )
 /*
 * Vector stubs.
 *
- * This code is copied to 0xffff0200 so we can use branches in the
+ * This code is copied to 0xffff1000 so we can use branches in the
- * vectors, rather than ldr's.  Note that this code must not
+ * vectors, rather than ldr's.  Note that this code must not exceed
- * exceed 0x300 bytes.
+ * a page size.
 *
 * Common stub entry macro:
 *   Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
@@ -985,8 +996,17 @@ ENDPROC(vector_\name)
 1:
        .endm
-        .globl  __stubs_start
+        .section .stubs, "ax", %progbits
 __stubs_start:
+        @ This must be the first word
+        .word   vector_swi
+vector_rst:
+ ARM(   swi     SYS_ERROR0      )
+ THUMB( svc     #0              )
+ THUMB( nop                     )
+        b       vector_und
 /*
 * Interrupt dispatcher
 */
@@ -1081,6 +1101,16 @@ __stubs_start:
        .align  5
 /*=============================================================================
+ * Address exception handler
+ *-----------------------------------------------------------------------------
+ * These aren't too critical.
+ * (they're not supposed to happen, and won't happen in 32-bit data mode).
+ */
+vector_addrexcptn:
+        b       vector_addrexcptn
+/*=============================================================================
 * Undefined FIQs
 *-----------------------------------------------------------------------------
 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
@@ -1093,45 +1123,19 @@ __stubs_start:
 vector_fiq:
        subs    pc, lr, #4
-/*=============================================================================
+        .globl  vector_fiq_offset
- * Address exception handler
+        .equ    vector_fiq_offset, vector_fiq
- *-----------------------------------------------------------------------------
- * These aren't too critical.
- * (they're not supposed to happen, and won't happen in 32-bit data mode).
- */
-vector_addrexcptn:
-        b       vector_addrexcptn
-/*
- * We group all the following data together to optimise
- * for CPUs with separate I & D caches.
- */
-        .align  5
-.LCvswi:
-        .word   vector_swi
-        .globl  __stubs_end
-__stubs_end:
-        .equ    stubs_offset, __vectors_start + 0x200 - __stubs_start
-        .globl  __vectors_start
+        .section .vectors, "ax", %progbits
 __vectors_start:
- ARM(   swi     SYS_ERROR0      )
+        W(b)    vector_rst
- THUMB( svc     #0              )
+        W(b)    vector_und
- THUMB( nop                     )
+        W(ldr)  pc, __vectors_start + 0x1000
-        W(b)    vector_und + stubs_offset
+        W(b)    vector_pabt
-        W(ldr)  pc, .LCvswi + stubs_offset
+        W(b)    vector_dabt
-        W(b)    vector_pabt + stubs_offset
+        W(b)    vector_addrexcptn
-        W(b)    vector_dabt + stubs_offset
+        W(b)    vector_irq
-        W(b)    vector_addrexcptn + stubs_offset
+        W(b)    vector_fiq
-        W(b)    vector_irq + stubs_offset
-        W(b)    vector_fiq + stubs_offset
-        .globl  __vectors_end
-__vectors_end:
        .data
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index bc5bc0a97131..94104bf69719 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -350,6 +350,9 @@ ENDPROC(ftrace_stub)
        .align  5
 ENTRY(vector_swi)
+#ifdef CONFIG_CPU_V7M
+        v7m_exception_entry
+#else
        sub     sp, sp, #S_FRAME_SIZE
        stmia   sp, {r0 - r12}                  @ Calling r0 - r12
 ARM(   add     r8, sp, #S_PC           )
@@ -360,8 +363,19 @@ ENTRY(vector_swi)
        str     lr, [sp, #S_PC]                 @ Save calling PC
        str     r8, [sp, #S_PSR]                @ Save CPSR
        str     r0, [sp, #S_OLD_R0]             @ Save OLD_R0
+#endif
        zero_fp
+#ifdef CONFIG_ALIGNMENT_TRAP
+        ldr     ip, __cr_alignment
+        ldr     ip, [ip]
+        mcr     p15, 0, ip, c1, c0              @ update control register
+#endif
+        enable_irq
+        ct_user_exit
+        get_thread_info tsk
        /*
         * Get the system call number.
         */
@@ -375,9 +389,9 @@ ENTRY(vector_swi)
 #ifdef CONFIG_ARM_THUMB
        tst     r8, #PSR_T_BIT
        movne   r10, #0                         @ no thumb OABI emulation
-        ldreq   r10, [lr, #-4]                  @ get SWI instruction
+ USER(  ldreq   r10, [lr, #-4]          )       @ get SWI instruction
 #else
-        ldr     r10, [lr, #-4]                  @ get SWI instruction
+ USER(  ldr     r10, [lr, #-4]          )       @ get SWI instruction
 #endif
 #ifdef CONFIG_CPU_ENDIAN_BE8
        rev     r10, r10                        @ little endian instruction
@@ -392,22 +406,13 @@ ENTRY(vector_swi)
        /* Legacy ABI only, possibly thumb mode. */
        tst     r8, #PSR_T_BIT                  @ this is SPSR from save_user_regs
        addne   scno, r7, #__NR_SYSCALL_BASE    @ put OS number in
-        ldreq   scno, [lr, #-4]
+ USER(  ldreq   scno, [lr, #-4]         )
 #else
        /* Legacy ABI only. */
-        ldr     scno, [lr, #-4]                 @ get SWI instruction
+ USER(  ldr     scno, [lr, #-4]         )       @ get SWI instruction
 #endif
-#ifdef CONFIG_ALIGNMENT_TRAP
-        ldr     ip, __cr_alignment
-        ldr     ip, [ip]
-        mcr     p15, 0, ip, c1, c0              @ update control register
-#endif
-        enable_irq
-        ct_user_exit
-        get_thread_info tsk
        adr     tbl, sys_call_table             @ load syscall table pointer
 #if defined(CONFIG_OABI_COMPAT)
@@ -442,6 +447,21 @@ local_restart:
        eor     r0, scno, #__NR_SYSCALL_BASE    @ put OS number back
        bcs     arm_syscall     
        b       sys_ni_syscall                  @ not private func
+#if defined(CONFIG_OABI_COMPAT) || !defined(CONFIG_AEABI)
+        /*
+         * We failed to handle a fault trying to access the page
+         * containing the swi instruction, but we're not really in a
+         * position to return -EFAULT. Instead, return back to the
+         * instruction and re-enter the user fault handling path trying
+         * to page it in. This will likely result in sending SEGV to the
+         * current task.
+         */
+9001:
+        sub     lr, lr, #4
+        str     lr, [sp, #S_PC]
+        b       ret_fast_syscall
+#endif
 ENDPROC(vector_swi)
        /*
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index 160f3376ba6d..de23a9beed13 100644
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
@@ -5,6 +5,7 @@
 #include <asm/asm-offsets.h>
 #include <asm/errno.h>
 #include <asm/thread_info.h>
+#include <asm/v7m.h>
 @ Bad Abort numbers
 @ -----------------
@@ -44,6 +45,116 @@
 #endif
        .endm
+#ifdef CONFIG_CPU_V7M
+/*
+ * ARMv7-M exception entry/exit macros.
+ *
+ * xPSR, ReturnAddress(), LR (R14), R12, R3, R2, R1, and R0 are
+ * automatically saved on the current stack (32 words) before
+ * switching to the exception stack (SP_main).
+ *
+ * If exception is taken while in user mode, SP_main is
+ * empty. Otherwise, SP_main is aligned to 64 bit automatically
+ * (CCR.STKALIGN set).
+ *
+ * Linux assumes that the interrupts are disabled when entering an
+ * exception handler and it may BUG if this is not the case. Interrupts
+ * are disabled during entry and reenabled in the exit macro.
+ *
+ * v7m_exception_slow_exit is used when returning from SVC or PendSV.
+ * When returning to kernel mode, we don't return from exception.
+ */
+        .macro  v7m_exception_entry
+        @ determine the location of the registers saved by the core during
+        @ exception entry. Depending on the mode the cpu was in when the
+        @ exception happend that is either on the main or the process stack.
+        @ Bit 2 of EXC_RETURN stored in the lr register specifies which stack
+        @ was used.
+        tst     lr, #EXC_RET_STACK_MASK
+        mrsne   r12, psp
+        moveq   r12, sp
+        @ we cannot rely on r0-r3 and r12 matching the value saved in the
+        @ exception frame because of tail-chaining. So these have to be
+        @ reloaded.
+        ldmia   r12!, {r0-r3}
+        @ Linux expects to have irqs off. Do it here before taking stack space
+        cpsid   i
+        sub     sp, #S_FRAME_SIZE-S_IP
+        stmdb   sp!, {r0-r11}
+        @ load saved r12, lr, return address and xPSR.
+        @ r0-r7 are used for signals and never touched from now on. Clobbering
+        @ r8-r12 is OK.
+        mov     r9, r12
+        ldmia   r9!, {r8, r10-r12}
+        @ calculate the original stack pointer value.
+        @ r9 currently points to the memory location just above the auto saved
+        @ xPSR.
+        @ The cpu might automatically 8-byte align the stack. Bit 9
+        @ of the saved xPSR specifies if stack aligning took place. In this case
+        @ another 32-bit value is included in the stack.
+        tst     r12, V7M_xPSR_FRAMEPTRALIGN
+        addne   r9, r9, #4
+        @ store saved r12 using str to have a register to hold the base for stm
+        str     r8, [sp, #S_IP]
+        add     r8, sp, #S_SP
+        @ store r13-r15, xPSR
+        stmia   r8!, {r9-r12}
+        @ store old_r0
+        str     r0, [r8]
+        .endm
+        /*
+         * PENDSV and SVCALL are configured to have the same exception
+         * priorities. As a kernel thread runs at SVCALL execution priority it
+         * can never be preempted and so we will never have to return to a
+         * kernel thread here.
+         */
+        .macro  v7m_exception_slow_exit ret_r0
+        cpsid   i
+        ldr     lr, =EXC_RET_THREADMODE_PROCESSSTACK
+        @ read original r12, sp, lr, pc and xPSR
+        add     r12, sp, #S_IP
+        ldmia   r12, {r1-r5}
+        @ an exception frame is always 8-byte aligned. To tell the hardware if
+        @ the sp to be restored is aligned or not set bit 9 of the saved xPSR
+        @ accordingly.
+        tst     r2, #4
+        subne   r2, r2, #4
+        orrne   r5, V7M_xPSR_FRAMEPTRALIGN
+        biceq   r5, V7M_xPSR_FRAMEPTRALIGN
+        @ write basic exception frame
+        stmdb   r2!, {r1, r3-r5}
+        ldmia   sp, {r1, r3-r5}
+        .if     \ret_r0
+        stmdb   r2!, {r0, r3-r5}
+        .else
+        stmdb   r2!, {r1, r3-r5}
+        .endif
+        @ restore process sp
+        msr     psp, r2
+        @ restore original r4-r11
+        ldmia   sp!, {r0-r11}
+        @ restore main sp
+        add     sp, sp, #S_FRAME_SIZE-S_IP
+        cpsie   i
+        bx      lr
+        .endm
+#endif  /* CONFIG_CPU_V7M */
        @
        @ Store/load the USER SP and LR registers by switching to the SYS
        @ mode. Useful in Thumb-2 mode where "stm/ldm rd, {sp, lr}^" is not
@@ -165,6 +276,18 @@
        rfeia   sp!
        .endm
+#ifdef CONFIG_CPU_V7M
+        /*
+         * Note we don't need to do clrex here as clearing the local monitor is
+         * part of each exception entry and exit sequence.
+         */
+        .macro  restore_user_regs, fast = 0, offset = 0
+        .if     \offset
+        add     sp, #\offset
+        .endif
+        v7m_exception_slow_exit ret_r0 = \fast
+        .endm
+#else   /* ifdef CONFIG_CPU_V7M */
        .macro  restore_user_regs, fast = 0, offset = 0
        clrex                                   @ clear the exclusive monitor
        mov     r2, sp
@@ -181,6 +304,7 @@
        add     sp, sp, #S_FRAME_SIZE - S_SP
        movs    pc, lr                          @ return & move spsr_svc into cpsr
        .endm
+#endif  /* ifdef CONFIG_CPU_V7M / else */
        .macro  get_thread_info, rd
        mov     \rd, sp
diff --git a/arch/arm/kernel/entry-v7m.S b/arch/arm/kernel/entry-v7m.S
new file mode 100644
index 000000000000..52b26432c9a9
--- /dev/null
+++ b/arch/arm/kernel/entry-v7m.S
@@ -0,0 +1,143 @@
+/*
+ * linux/arch/arm/kernel/entry-v7m.S
+ *
+ * Copyright (C) 2008 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Low-level vector interface routines for the ARMv7-M architecture
+ */
+#include <asm/memory.h>
+#include <asm/glue.h>
+#include <asm/thread_notify.h>
+#include <asm/v7m.h>
+#include <mach/entry-macro.S>
+#include "entry-header.S"
+#ifdef CONFIG_TRACE_IRQFLAGS
+#error "CONFIG_TRACE_IRQFLAGS not supported on the current ARMv7M implementation"
+#endif
+__invalid_entry:
+        v7m_exception_entry
+        adr     r0, strerr
+        mrs     r1, ipsr
+        mov     r2, lr
+        bl      printk
+        mov     r0, sp
+        bl      show_regs
+1:      b       1b
+ENDPROC(__invalid_entry)
+strerr: .asciz  "\nUnhandled exception: IPSR = %08lx LR = %08lx\n"
+        .align  2
+__irq_entry:
+        v7m_exception_entry
+        @
+        @ Invoke the IRQ handler
+        @
+        mrs     r0, ipsr
+        ldr     r1, =V7M_xPSR_EXCEPTIONNO
+        and     r0, r1
+        sub     r0, #16
+        mov     r1, sp
+        stmdb   sp!, {lr}
+        @ routine called with r0 = irq number, r1 = struct pt_regs *
+        bl      nvic_handle_irq
+        pop     {lr}
+        @
+        @ Check for any pending work if returning to user
+        @
+        ldr     r1, =BASEADDR_V7M_SCB
+        ldr     r0, [r1, V7M_SCB_ICSR]
+        tst     r0, V7M_SCB_ICSR_RETTOBASE
+        beq     2f
+        get_thread_info tsk
+        ldr     r2, [tsk, #TI_FLAGS]
+        tst     r2, #_TIF_WORK_MASK
+        beq     2f                      @ no work pending
+        mov     r0, #V7M_SCB_ICSR_PENDSVSET
+        str     r0, [r1, V7M_SCB_ICSR]  @ raise PendSV
+2:
+        @ registers r0-r3 and r12 are automatically restored on exception
+        @ return. r4-r7 were not clobbered in v7m_exception_entry so for
+        @ correctness they don't need to be restored. So only r8-r11 must be
+        @ restored here. The easiest way to do so is to restore r0-r7, too.
+        ldmia   sp!, {r0-r11}
+        add     sp, #S_FRAME_SIZE-S_IP
+        cpsie   i
+        bx      lr
+ENDPROC(__irq_entry)
+__pendsv_entry:
+        v7m_exception_entry
+        ldr     r1, =BASEADDR_V7M_SCB
+        mov     r0, #V7M_SCB_ICSR_PENDSVCLR
+        str     r0, [r1, V7M_SCB_ICSR]  @ clear PendSV
+        @ execute the pending work, including reschedule
+        get_thread_info tsk
+        mov     why, #0
+        b       ret_to_user
+ENDPROC(__pendsv_entry)
+/*
+ * Register switch for ARMv7-M processors.
+ * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
+ * previous and next are guaranteed not to be the same.
+ */
+ENTRY(__switch_to)
+        .fnstart
+        .cantunwind
+        add     ip, r1, #TI_CPU_SAVE
+        stmia   ip!, {r4 - r11}         @ Store most regs on stack
+        str     sp, [ip], #4
+        str     lr, [ip], #4
+        mov     r5, r0
+        add     r4, r2, #TI_CPU_SAVE
+        ldr     r0, =thread_notify_head
+        mov     r1, #THREAD_NOTIFY_SWITCH
+        bl      atomic_notifier_call_chain
+        mov     ip, r4
+        mov     r0, r5
+        ldmia   ip!, {r4 - r11}         @ Load all regs saved previously
+        ldr     sp, [ip]
+        ldr     pc, [ip, #4]!
+        .fnend
+ENDPROC(__switch_to)
+        .data
+        .align  8
+/*
+ * Vector table (64 words => 256 bytes natural alignment)
+ */
+ENTRY(vector_table)
+        .long   0                       @ 0 - Reset stack pointer
+        .long   __invalid_entry         @ 1 - Reset
+        .long   __invalid_entry         @ 2 - NMI
+        .long   __invalid_entry         @ 3 - HardFault
+        .long   __invalid_entry         @ 4 - MemManage
+        .long   __invalid_entry         @ 5 - BusFault
+        .long   __invalid_entry         @ 6 - UsageFault
+        .long   __invalid_entry         @ 7 - Reserved
+        .long   __invalid_entry         @ 8 - Reserved
+        .long   __invalid_entry         @ 9 - Reserved
+        .long   __invalid_entry         @ 10 - Reserved
+        .long   vector_swi              @ 11 - SVCall
+        .long   __invalid_entry         @ 12 - Debug Monitor
+        .long   __invalid_entry         @ 13 - Reserved
+        .long   __pendsv_entry          @ 14 - PendSV
+        .long   __invalid_entry         @ 15 - SysTick
+        .rept   64 - 16
+        .long   __irq_entry             @ 16..64 - External Interrupts
+        .endr
diff --git a/arch/arm/kernel/fiq.c b/arch/arm/kernel/fiq.c
index 2adda11f712f..25442f451148 100644
--- a/arch/arm/kernel/fiq.c
+++ b/arch/arm/kernel/fiq.c
@@ -47,6 +47,11 @@
 #include <asm/irq.h>
 #include <asm/traps.h>
+#define FIQ_OFFSET ({                                   \
+                extern void *vector_fiq_offset;         \
+                (unsigned)&vector_fiq_offset;           \
+        })
 static unsigned long no_fiq_insn;
 /* Default reacquire function
@@ -80,13 +85,16 @@ int show_fiq_list(struct seq_file *p, int prec)
 void set_fiq_handler(void *start, unsigned int length)
 {
 #if defined(CONFIG_CPU_USE_DOMAINS)
-        memcpy((void *)0xffff001c, start, length);
+        void *base = (void *)0xffff0000;
 #else
-        memcpy(vectors_page + 0x1c, start, length);
+        void *base = vectors_page;
 #endif
-        flush_icache_range(0xffff001c, 0xffff001c + length);
+        unsigned offset = FIQ_OFFSET;
+        memcpy(base + offset, start, length);
+        flush_icache_range(0xffff0000 + offset, 0xffff0000 + offset + length);
        if (!vectors_high())
-                flush_icache_range(0x1c, 0x1c + length);
+                flush_icache_range(offset, offset + length);
 }
 int claim_fiq(struct fiq_handler *f)
@@ -144,6 +152,7 @@ EXPORT_SYMBOL(disable_fiq);
 void __init init_FIQ(int start)
 {
-        no_fiq_insn = *(unsigned long *)0xffff001c;
+        unsigned offset = FIQ_OFFSET;
+        no_fiq_insn = *(unsigned long *)(0xffff0000 + offset);
        fiq_start = start;
 }
diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S
index 5b391a689b47..47cd974e57ea 100644
--- a/arch/arm/kernel/head-common.S
+++ b/arch/arm/kernel/head-common.S
@@ -133,6 +133,9 @@ ENTRY(lookup_processor_type)
        ldmfd   sp!, {r4 - r6, r9, pc}
 ENDPROC(lookup_processor_type)
+        __FINIT
+        .text
 /*
 * Read processor ID register (CP#15, CR0), and look up in the linker-built
 * supported processor list.  Note that we can't use the absolute addresses
@@ -146,7 +149,6 @@ ENDPROC(lookup_processor_type)
 *      r5 = proc_info pointer in physical address space
 *      r9 = cpuid (preserved)
 */
-        __CPUINIT
 __lookup_processor_type:
        adr     r3, __lookup_processor_type_data
        ldmia   r3, {r4 - r6}
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index 6a2e09c952c7..14235ba64a90 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -17,8 +17,12 @@
 #include <asm/assembler.h>
 #include <asm/ptrace.h>
 #include <asm/asm-offsets.h>
+#include <asm/memory.h>
 #include <asm/cp15.h>
 #include <asm/thread_info.h>
+#include <asm/v7m.h>
+#include <asm/mpu.h>
+#include <asm/page.h>
 /*
 * Kernel startup entry point.
@@ -50,21 +54,86 @@ ENTRY(stext)
        setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
                                                @ and irqs disabled
-#ifndef CONFIG_CPU_CP15
+#if defined(CONFIG_CPU_CP15)
-        ldr     r9, =CONFIG_PROCESSOR_ID
-#else
        mrc     p15, 0, r9, c0, c0              @ get processor id
+#elif defined(CONFIG_CPU_V7M)
+        ldr     r9, =BASEADDR_V7M_SCB
+        ldr     r9, [r9, V7M_SCB_CPUID]
+#else
+        ldr     r9, =CONFIG_PROCESSOR_ID
 #endif
        bl      __lookup_processor_type         @ r5=procinfo r9=cpuid
        movs    r10, r5                         @ invalid processor (r5=0)?
        beq     __error_p                               @ yes, error 'p'
-        adr     lr, BSYM(__after_proc_init)     @ return (PIC) address
+#ifdef CONFIG_ARM_MPU
+        /* Calculate the size of a region covering just the kernel */
+        ldr     r5, =PHYS_OFFSET                @ Region start: PHYS_OFFSET
+        ldr     r6, =(_end)                     @ Cover whole kernel
+        sub     r6, r6, r5                      @ Minimum size of region to map
+        clz     r6, r6                          @ Region size must be 2^N...
+        rsb     r6, r6, #31                     @ ...so round up region size
+        lsl     r6, r6, #MPU_RSR_SZ             @ Put size in right field
+        orr     r6, r6, #(1 << MPU_RSR_EN)      @ Set region enabled bit
+        bl      __setup_mpu
+#endif
+        ldr     r13, =__mmap_switched           @ address to jump to after
+                                                @ initialising sctlr
+        adr     lr, BSYM(1f)                    @ return (PIC) address
 ARM(   add     pc, r10, #PROCINFO_INITFUNC     )
 THUMB( add     r12, r10, #PROCINFO_INITFUNC    )
 THUMB( mov     pc, r12                         )
+ 1:     b       __after_proc_init
 ENDPROC(stext)
+#ifdef CONFIG_SMP
+        .text
+ENTRY(secondary_startup)
+        /*
+         * Common entry point for secondary CPUs.
+         *
+         * Ensure that we're in SVC mode, and IRQs are disabled.  Lookup
+         * the processor type - there is no need to check the machine type
+         * as it has already been validated by the primary processor.
+         */
+        setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9
+#ifndef CONFIG_CPU_CP15
+        ldr     r9, =CONFIG_PROCESSOR_ID
+#else
+        mrc     p15, 0, r9, c0, c0              @ get processor id
+#endif
+        bl      __lookup_processor_type         @ r5=procinfo r9=cpuid
+        movs    r10, r5                         @ invalid processor?
+        beq     __error_p                       @ yes, error 'p'
+        adr     r4, __secondary_data
+        ldmia   r4, {r7, r12}
+#ifdef CONFIG_ARM_MPU
+        /* Use MPU region info supplied by __cpu_up */
+        ldr     r6, [r7]                        @ get secondary_data.mpu_szr
+        bl      __setup_mpu                     @ Initialize the MPU
+#endif
+        adr     lr, BSYM(__after_proc_init)     @ return address
+        mov     r13, r12                        @ __secondary_switched address
+ ARM(   add     pc, r10, #PROCINFO_INITFUNC     )
+ THUMB( add     r12, r10, #PROCINFO_INITFUNC    )
+ THUMB( mov     pc, r12                         )
+ENDPROC(secondary_startup)
+ENTRY(__secondary_switched)
+        ldr     sp, [r7, #8]                    @ set up the stack pointer
+        mov     fp, #0
+        b       secondary_start_kernel
+ENDPROC(__secondary_switched)
+        .type   __secondary_data, %object
+__secondary_data:
+        .long   secondary_data
+        .long   __secondary_switched
+#endif /* CONFIG_SMP */
 /*
 * Set the Control Register and Read the process ID.
 */
@@ -95,10 +164,97 @@ __after_proc_init:
 #endif
        mcr     p15, 0, r0, c1, c0, 0           @ write control reg
 #endif /* CONFIG_CPU_CP15 */
+        mov     pc, r13
-        b       __mmap_switched                 @ clear the BSS and jump
-                                                @ to start_kernel
 ENDPROC(__after_proc_init)
        .ltorg
+#ifdef CONFIG_ARM_MPU
+/* Set which MPU region should be programmed */
+.macro set_region_nr tmp, rgnr
+        mov     \tmp, \rgnr                     @ Use static region numbers
+        mcr     p15, 0, \tmp, c6, c2, 0         @ Write RGNR
+.endm
+/* Setup a single MPU region, either D or I side (D-side for unified) */
+.macro setup_region bar, acr, sr, side = MPU_DATA_SIDE
+        mcr     p15, 0, \bar, c6, c1, (0 + \side)       @ I/DRBAR
+        mcr     p15, 0, \acr, c6, c1, (4 + \side)       @ I/DRACR
+        mcr     p15, 0, \sr, c6, c1, (2 + \side)                @ I/DRSR
+.endm
+/*
+ * Setup the MPU and initial MPU Regions. We create the following regions:
+ * Region 0: Use this for probing the MPU details, so leave disabled.
+ * Region 1: Background region - covers the whole of RAM as strongly ordered
+ * Region 2: Normal, Shared, cacheable for RAM. From PHYS_OFFSET, size from r6
+ * Region 3: Normal, shared, inaccessible from PL0 to protect the vectors page
+ *
+ * r6: Value to be written to DRSR (and IRSR if required) for MPU_RAM_REGION
+*/
+ENTRY(__setup_mpu)
+        /* Probe for v7 PMSA compliance */
+        mrc     p15, 0, r0, c0, c1, 4           @ Read ID_MMFR0
+        and     r0, r0, #(MMFR0_PMSA)           @ PMSA field
+        teq     r0, #(MMFR0_PMSAv7)             @ PMSA v7
+        bne     __error_p                       @ Fail: ARM_MPU on NOT v7 PMSA
+        /* Determine whether the D/I-side memory map is unified. We set the
+         * flags here and continue to use them for the rest of this function */
+        mrc     p15, 0, r0, c0, c0, 4           @ MPUIR
+        ands    r5, r0, #MPUIR_DREGION_SZMASK   @ 0 size d region => No MPU
+        beq     __error_p                       @ Fail: ARM_MPU and no MPU
+        tst     r0, #MPUIR_nU                   @ MPUIR_nU = 0 for unified
+        /* Setup second region first to free up r6 */
+        set_region_nr r0, #MPU_RAM_REGION
+        isb
+        /* Full access from PL0, PL1, shared for CONFIG_SMP, cacheable */
+        ldr     r0, =PHYS_OFFSET                @ RAM starts at PHYS_OFFSET
+        ldr     r5,=(MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL)
+        setup_region r0, r5, r6, MPU_DATA_SIDE  @ PHYS_OFFSET, shared, enabled
+        beq     1f                              @ Memory-map not unified
+        setup_region r0, r5, r6, MPU_INSTR_SIDE @ PHYS_OFFSET, shared, enabled
+1:      isb
+        /* First/background region */
+        set_region_nr r0, #MPU_BG_REGION
+        isb
+        /* Execute Never,  strongly ordered, inaccessible to PL0, rw PL1  */
+        mov     r0, #0                          @ BG region starts at 0x0
+        ldr     r5,=(MPU_ACR_XN | MPU_RGN_STRONGLY_ORDERED | MPU_AP_PL1RW_PL0NA)
+        mov     r6, #MPU_RSR_ALL_MEM            @ 4GB region, enabled
+        setup_region r0, r5, r6, MPU_DATA_SIDE  @ 0x0, BG region, enabled
+        beq     2f                              @ Memory-map not unified
+        setup_region r0, r5, r6, MPU_INSTR_SIDE @ 0x0, BG region, enabled
+2:      isb
+        /* Vectors region */
+        set_region_nr r0, #MPU_VECTORS_REGION
+        isb
+        /* Shared, inaccessible to PL0, rw PL1 */
+        mov     r0, #CONFIG_VECTORS_BASE        @ Cover from VECTORS_BASE
+        ldr     r5,=(MPU_AP_PL1RW_PL0NA | MPU_RGN_NORMAL)
+        /* Writing N to bits 5:1 (RSR_SZ) --> region size 2^N+1 */
+        mov     r6, #(((PAGE_SHIFT - 1) << MPU_RSR_SZ) | 1 << MPU_RSR_EN)
+        setup_region r0, r5, r6, MPU_DATA_SIDE  @ VECTORS_BASE, PL0 NA, enabled
+        beq     3f                              @ Memory-map not unified
+        setup_region r0, r5, r6, MPU_INSTR_SIDE @ VECTORS_BASE, PL0 NA, enabled
+3:      isb
+        /* Enable the MPU */
+        mrc     p15, 0, r0, c1, c0, 0           @ Read SCTLR
+        bic     r0, r0, #CR_BR                  @ Disable the 'default mem-map'
+        orr     r0, r0, #CR_M                   @ Set SCTRL.M (MPU on)
+        mcr     p15, 0, r0, c1, c0, 0           @ Enable MPU
+        isb
+        mov pc,lr
+ENDPROC(__setup_mpu)
+#endif
 #include "head-common.S"
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 8bac553fe213..2c7cc1e03473 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -156,7 +156,7 @@ ENDPROC(stext)
 *
 * Returns:
 *  r0, r3, r5-r7 corrupted
- *  r4 = physical page table address
+ *  r4 = page table (see ARCH_PGD_SHIFT in asm/memory.h)
 */
 __create_page_tables:
        pgtbl   r4, r8                          @ page table address
@@ -331,6 +331,7 @@ __create_page_tables:
 #endif
 #ifdef CONFIG_ARM_LPAE
        sub     r4, r4, #0x1000         @ point to the PGD table
+        mov     r4, r4, lsr #ARCH_PGD_SHIFT
 #endif
        mov     pc, lr
 ENDPROC(__create_page_tables)
@@ -342,7 +343,7 @@ __turn_mmu_on_loc:
        .long   __turn_mmu_on_end
 #if defined(CONFIG_SMP)
-        __CPUINIT
+        .text
 ENTRY(secondary_startup)
        /*
         * Common entry point for secondary CPUs.
@@ -408,7 +409,7 @@ __secondary_data:
 *  r0  = cp#15 control register
 *  r1  = machine ID
 *  r2  = atags or dtb pointer
- *  r4  = page table pointer
+ *  r4  = page table (see ARCH_PGD_SHIFT in asm/memory.h)
 *  r9  = processor ID
 *  r13 = *virtual* address to jump to upon completion
 */
@@ -427,10 +428,7 @@ __enable_mmu:
 #ifdef CONFIG_CPU_ICACHE_DISABLE
        bic     r0, r0, #CR_I
 #endif
-#ifdef CONFIG_ARM_LPAE
+#ifndef CONFIG_ARM_LPAE
-        mov     r5, #0
-        mcrr    p15, 0, r4, r5, c2              @ load TTBR0
-#else
        mov     r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
                      domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
                      domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index 1fd749ee4a1b..7b95de601357 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -1020,7 +1020,7 @@ out_mdbgen:
                cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu));
 }
-static int __cpuinit dbg_reset_notify(struct notifier_block *self,
+static int dbg_reset_notify(struct notifier_block *self,
                                      unsigned long action, void *cpu)
 {
        if ((action & ~CPU_TASKS_FROZEN) == CPU_ONLINE)
@@ -1029,7 +1029,7 @@ static int __cpuinit dbg_reset_notify(struct notifier_block *self,
        return NOTIFY_OK;
 }
-static struct notifier_block __cpuinitdata dbg_reset_nb = {
+static struct notifier_block dbg_reset_nb = {
        .notifier_call = dbg_reset_notify,
 };
diff --git a/arch/arm/kernel/hyp-stub.S b/arch/arm/kernel/hyp-stub.S
index 1315c4ccfa56..797b1a6a4906 100644
--- a/arch/arm/kernel/hyp-stub.S
+++ b/arch/arm/kernel/hyp-stub.S
@@ -56,8 +56,8 @@ ENTRY(__boot_cpu_mode)
        ldr     \reg3, [\reg2]
        ldr     \reg1, [\reg2, \reg3]
        cmp     \mode, \reg1            @ matches primary CPU boot mode?
-        orrne   r7, r7, #BOOT_CPU_MODE_MISMATCH
+        orrne   \reg1, \reg1, #BOOT_CPU_MODE_MISMATCH
-        strne   r7, [r5, r6]            @ record what happened and give up
+        strne   \reg1, [\reg2, \reg3]   @ record what happened and give up
        .endm
 #else   /* ZIMAGE */
@@ -153,6 +153,13 @@ THUMB(	orr	r7, #(1 << 30)	)	@ HSCTLR.TE
        mrc     p15, 4, r7, c14, c1, 0  @ CNTHCTL
        orr     r7, r7, #3              @ PL1PCEN | PL1PCTEN
        mcr     p15, 4, r7, c14, c1, 0  @ CNTHCTL
+        mov     r7, #0
+        mcrr    p15, 4, r7, r7, c14     @ CNTVOFF
+        @ Disable virtual timer in case it was counting
+        mrc     p15, 0, r7, c14, c3, 1  @ CNTV_CTL
+        bic     r7, #1                  @ Clear ENABLE
+        mcr     p15, 0, r7, c14, c3, 1  @ CNTV_CTL
 1:
 #endif
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index 1e9be5d25e56..85c3fb6c93c2 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -288,24 +288,16 @@ int module_finalize(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs,
                if (strcmp(".ARM.exidx.init.text", secname) == 0)
                        maps[ARM_SEC_INIT].unw_sec = s;
-                else if (strcmp(".ARM.exidx.devinit.text", secname) == 0)
-                        maps[ARM_SEC_DEVINIT].unw_sec = s;
                else if (strcmp(".ARM.exidx", secname) == 0)
                        maps[ARM_SEC_CORE].unw_sec = s;
                else if (strcmp(".ARM.exidx.exit.text", secname) == 0)
                        maps[ARM_SEC_EXIT].unw_sec = s;
-                else if (strcmp(".ARM.exidx.devexit.text", secname) == 0)
-                        maps[ARM_SEC_DEVEXIT].unw_sec = s;
                else if (strcmp(".init.text", secname) == 0)
                        maps[ARM_SEC_INIT].txt_sec = s;
-                else if (strcmp(".devinit.text", secname) == 0)
-                        maps[ARM_SEC_DEVINIT].txt_sec = s;
                else if (strcmp(".text", secname) == 0)
                        maps[ARM_SEC_CORE].txt_sec = s;
                else if (strcmp(".exit.text", secname) == 0)
                        maps[ARM_SEC_EXIT].txt_sec = s;
-                else if (strcmp(".devexit.text", secname) == 0)
-                        maps[ARM_SEC_DEVEXIT].txt_sec = s;
        }
        for (i = 0; i < ARM_SEC_MAX; i++)
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 8c3094d0f7b7..21f77906602c 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -53,7 +53,12 @@ armpmu_map_cache_event(const unsigned (*cache_map)
 static int
 armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
 {
-        int mapping = (*event_map)[config];
+        int mapping;
+        if (config >= PERF_COUNT_HW_MAX)
+                return -ENOENT;
+        mapping = (*event_map)[config];
        return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
 }
@@ -569,6 +574,7 @@ perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
                return;
        }
+        perf_callchain_store(entry, regs->ARM_pc);
        tail = (struct frame_tail __user *)regs->ARM_fp - 1;
        while ((entry->nr < PERF_MAX_STACK_DEPTH) &&
diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c
index 1f2740e3dbc0..aebe0e99c153 100644
--- a/arch/arm/kernel/perf_event_cpu.c
+++ b/arch/arm/kernel/perf_event_cpu.c
@@ -157,8 +157,8 @@ static void cpu_pmu_init(struct arm_pmu *cpu_pmu)
 * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
 * junk values out of them.
 */
-static int __cpuinit cpu_pmu_notify(struct notifier_block *b,
+static int cpu_pmu_notify(struct notifier_block *b, unsigned long action,
-                                    unsigned long action, void *hcpu)
+                          void *hcpu)
 {
        if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
                return NOTIFY_DONE;
@@ -171,7 +171,7 @@ static int __cpuinit cpu_pmu_notify(struct notifier_block *b,
        return NOTIFY_OK;
 }
-static struct notifier_block __cpuinitdata cpu_pmu_hotplug_notifier = {
+static struct notifier_block cpu_pmu_hotplug_notifier = {
        .notifier_call = cpu_pmu_notify,
 };
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 6e8931ccf13e..536c85fe72a8 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -32,6 +32,7 @@
 #include <linux/hw_breakpoint.h>
 #include <linux/cpuidle.h>
 #include <linux/leds.h>
+#include <linux/reboot.h>
 #include <asm/cacheflush.h>
 #include <asm/idmap.h>
@@ -39,6 +40,7 @@
 #include <asm/thread_notify.h>
 #include <asm/stacktrace.h>
 #include <asm/mach/time.h>
+#include <asm/tls.h>
 #ifdef CONFIG_CC_STACKPROTECTOR
 #include <linux/stackprotector.h>
@@ -112,7 +114,7 @@ void soft_restart(unsigned long addr)
        BUG();
 }
-static void null_restart(char mode, const char *cmd)
+static void null_restart(enum reboot_mode reboot_mode, const char *cmd)
 {
 }
@@ -122,7 +124,7 @@ static void null_restart(char mode, const char *cmd)
 void (*pm_power_off)(void);
 EXPORT_SYMBOL(pm_power_off);
-void (*arm_pm_restart)(char str, const char *cmd) = null_restart;
+void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd) = null_restart;
 EXPORT_SYMBOL_GPL(arm_pm_restart);
 /*
@@ -174,16 +176,6 @@ void arch_cpu_idle(void)
                default_idle();
 }
-static char reboot_mode = 'h';
-int __init reboot_setup(char *str)
-{
-        reboot_mode = str[0];
-        return 1;
-}
-__setup("reboot=", reboot_setup);
 /*
 * Called by kexec, immediately prior to machine_kexec().
 *
@@ -205,6 +197,7 @@ void machine_shutdown(void)
 */
 void machine_halt(void)
 {
+        local_irq_disable();
        smp_send_stop();
        local_irq_disable();
@@ -219,6 +212,7 @@ void machine_halt(void)
 */
 void machine_power_off(void)
 {
+        local_irq_disable();
        smp_send_stop();
        if (pm_power_off)
@@ -238,6 +232,7 @@ void machine_power_off(void)
 */
 void machine_restart(char *cmd)
 {
+        local_irq_disable();
        smp_send_stop();
        arm_pm_restart(reboot_mode, cmd);
@@ -374,7 +369,8 @@ copy_thread(unsigned long clone_flags, unsigned long stack_start,
        clear_ptrace_hw_breakpoint(p);
        if (clone_flags & CLONE_SETTLS)
-                thread->tp_value = childregs->ARM_r3;
+                thread->tp_value[0] = childregs->ARM_r3;
+        thread->tp_value[1] = get_tpuser();
        thread_notify(THREAD_NOTIFY_COPY, thread);
@@ -433,10 +429,11 @@ unsigned long arch_randomize_brk(struct mm_struct *mm)
 }
 #ifdef CONFIG_MMU
+#ifdef CONFIG_KUSER_HELPERS
 /*
 * The vectors page is always readable from user space for the
- * atomic helpers and the signal restart code. Insert it into the
+ * atomic helpers. Insert it into the gate_vma so that it is visible
- * gate_vma so that it is visible through ptrace and /proc/<pid>/mem.
+ * through ptrace and /proc/<pid>/mem.
 */
 static struct vm_area_struct gate_vma = {
        .vm_start       = 0xffff0000,
@@ -465,9 +462,48 @@ int in_gate_area_no_mm(unsigned long addr)
 {
        return in_gate_area(NULL, addr);
 }
+#define is_gate_vma(vma)        ((vma) = &gate_vma)
+#else
+#define is_gate_vma(vma)        0
+#endif
 const char *arch_vma_name(struct vm_area_struct *vma)
 {
-        return (vma == &gate_vma) ? "[vectors]" : NULL;
+        return is_gate_vma(vma) ? "[vectors]" :
+                (vma->vm_mm && vma->vm_start == vma->vm_mm->context.sigpage) ?
+                 "[sigpage]" : NULL;
+}
+static struct page *signal_page;
+extern struct page *get_signal_page(void);
+int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
+{
+        struct mm_struct *mm = current->mm;
+        unsigned long addr;
+        int ret;
+        if (!signal_page)
+                signal_page = get_signal_page();
+        if (!signal_page)
+                return -ENOMEM;
+        down_write(&mm->mmap_sem);
+        addr = get_unmapped_area(NULL, 0, PAGE_SIZE, 0, 0);
+        if (IS_ERR_VALUE(addr)) {
+                ret = addr;
+                goto up_fail;
+        }
+        ret = install_special_mapping(mm, addr, PAGE_SIZE,
+                VM_READ | VM_EXEC | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC,
+                &signal_page);
+        if (ret == 0)
+                mm->context.sigpage = addr;
+ up_fail:
+        up_write(&mm->mmap_sem);
+        return ret;
 }
 #endif
diff --git a/arch/arm/kernel/psci.c b/arch/arm/kernel/psci.c
index 36531643cc2c..46931880093d 100644
--- a/arch/arm/kernel/psci.c
+++ b/arch/arm/kernel/psci.c
@@ -158,7 +158,7 @@ static const struct of_device_id psci_of_match[] __initconst = {
        {},
 };
-static int __init psci_init(void)
+void __init psci_init(void)
 {
        struct device_node *np;
        const char *method;
@@ -166,7 +166,7 @@ static int __init psci_init(void)
        np = of_find_matching_node(NULL, psci_of_match);
        if (!np)
-                return 0;
+                return;
        pr_info("probing function IDs from device-tree\n");
@@ -206,6 +206,5 @@ static int __init psci_init(void)
 out_put_node:
        of_node_put(np);
-        return 0;
+        return;
 }
-early_initcall(psci_init);
diff --git a/arch/arm/kernel/psci_smp.c b/arch/arm/kernel/psci_smp.c
new file mode 100644
index 000000000000..70ded3fb42d9
--- /dev/null
+++ b/arch/arm/kernel/psci_smp.c
@@ -0,0 +1,83 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2012 ARM Limited
+ *
+ * Author: Will Deacon <will.deacon@arm.com>
+ */
+#include <linux/init.h>
+#include <linux/irqchip/arm-gic.h>
+#include <linux/smp.h>
+#include <linux/of.h>
+#include <asm/psci.h>
+#include <asm/smp_plat.h>
+/*
+ * psci_smp assumes that the following is true about PSCI:
+ *
+ * cpu_suspend   Suspend the execution on a CPU
+ * @state        we don't currently describe affinity levels, so just pass 0.
+ * @entry_point  the first instruction to be executed on return
+ * returns 0  success, < 0 on failure
+ *
+ * cpu_off       Power down a CPU
+ * @state        we don't currently describe affinity levels, so just pass 0.
+ * no return on successful call
+ *
+ * cpu_on        Power up a CPU
+ * @cpuid        cpuid of target CPU, as from MPIDR
+ * @entry_point  the first instruction to be executed on return
+ * returns 0  success, < 0 on failure
+ *
+ * migrate       Migrate the context to a different CPU
+ * @cpuid        cpuid of target CPU, as from MPIDR
+ * returns 0  success, < 0 on failure
+ *
+ */
+extern void secondary_startup(void);
+static int psci_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        if (psci_ops.cpu_on)
+                return psci_ops.cpu_on(cpu_logical_map(cpu),
+                                       __pa(secondary_startup));
+        return -ENODEV;
+}
+#ifdef CONFIG_HOTPLUG_CPU
+void __ref psci_cpu_die(unsigned int cpu)
+{
+       const struct psci_power_state ps = {
+               .type = PSCI_POWER_STATE_TYPE_POWER_DOWN,
+       };
+       if (psci_ops.cpu_off)
+               psci_ops.cpu_off(ps);
+       /* We should never return */
+       panic("psci: cpu %d failed to shutdown\n", cpu);
+}
+#endif
+bool __init psci_smp_available(void)
+{
+        /* is cpu_on available at least? */
+        return (psci_ops.cpu_on != NULL);
+}
+struct smp_operations __initdata psci_smp_ops = {
+        .smp_boot_secondary     = psci_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_die                = psci_cpu_die,
+#endif
+};
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 03deeffd9f6d..0dd3b79b15c3 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -849,7 +849,7 @@ long arch_ptrace(struct task_struct *child, long request,
 #endif
                case PTRACE_GET_THREAD_AREA:
-                        ret = put_user(task_thread_info(child)->tp_value,
+                        ret = put_user(task_thread_info(child)->tp_value[0],
                                       datap);
                        break;
@@ -886,20 +886,12 @@ long arch_ptrace(struct task_struct *child, long request,
 #ifdef CONFIG_HAVE_HW_BREAKPOINT
                case PTRACE_GETHBPREGS:
-                        if (ptrace_get_breakpoints(child) < 0)
-                                return -ESRCH;
                        ret = ptrace_gethbpregs(child, addr,
                                                (unsigned long __user *)data);
-                        ptrace_put_breakpoints(child);
                        break;
                case PTRACE_SETHBPREGS:
-                        if (ptrace_get_breakpoints(child) < 0)
-                                return -ESRCH;
                        ret = ptrace_sethbpregs(child, addr,
                                                (unsigned long __user *)data);
-                        ptrace_put_breakpoints(child);
                        break;
 #endif
diff --git a/arch/arm/kernel/sched_clock.c b/arch/arm/kernel/sched_clock.c
deleted file mode 100644
index e8edcaa0e432..000000000000
--- a/arch/arm/kernel/sched_clock.c
+++ /dev/null
@@ -1,217 +0,0 @@
-/*
- * sched_clock.c: support for extending counters to full 64-bit ns counter
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/clocksource.h>
-#include <linux/init.h>
-#include <linux/jiffies.h>
-#include <linux/kernel.h>
-#include <linux/moduleparam.h>
-#include <linux/sched.h>
-#include <linux/syscore_ops.h>
-#include <linux/timer.h>
-#include <asm/sched_clock.h>
-struct clock_data {
-        u64 epoch_ns;
-        u32 epoch_cyc;
-        u32 epoch_cyc_copy;
-        unsigned long rate;
-        u32 mult;
-        u32 shift;
-        bool suspended;
-        bool needs_suspend;
-};
-static void sched_clock_poll(unsigned long wrap_ticks);
-static DEFINE_TIMER(sched_clock_timer, sched_clock_poll, 0, 0);
-static int irqtime = -1;
-core_param(irqtime, irqtime, int, 0400);
-static struct clock_data cd = {
-        .mult   = NSEC_PER_SEC / HZ,
-};
-static u32 __read_mostly sched_clock_mask = 0xffffffff;
-static u32 notrace jiffy_sched_clock_read(void)
-{
-        return (u32)(jiffies - INITIAL_JIFFIES);
-}
-static u32 __read_mostly (*read_sched_clock)(void) = jiffy_sched_clock_read;
-static inline u64 notrace cyc_to_ns(u64 cyc, u32 mult, u32 shift)
-{
-        return (cyc * mult) >> shift;
-}
-static unsigned long long notrace cyc_to_sched_clock(u32 cyc, u32 mask)
-{
-        u64 epoch_ns;
-        u32 epoch_cyc;
-        if (cd.suspended)
-                return cd.epoch_ns;
-        /*
-         * Load the epoch_cyc and epoch_ns atomically.  We do this by
-         * ensuring that we always write epoch_cyc, epoch_ns and
-         * epoch_cyc_copy in strict order, and read them in strict order.
-         * If epoch_cyc and epoch_cyc_copy are not equal, then we're in
-         * the middle of an update, and we should repeat the load.
-         */
-        do {
-                epoch_cyc = cd.epoch_cyc;
-                smp_rmb();
-                epoch_ns = cd.epoch_ns;
-                smp_rmb();
-        } while (epoch_cyc != cd.epoch_cyc_copy);
-        return epoch_ns + cyc_to_ns((cyc - epoch_cyc) & mask, cd.mult, cd.shift);
-}
-/*
- * Atomically update the sched_clock epoch.
- */
-static void notrace update_sched_clock(void)
-{
-        unsigned long flags;
-        u32 cyc;
-        u64 ns;
-        cyc = read_sched_clock();
-        ns = cd.epoch_ns +
-                cyc_to_ns((cyc - cd.epoch_cyc) & sched_clock_mask,
-                          cd.mult, cd.shift);
-        /*
-         * Write epoch_cyc and epoch_ns in a way that the update is
-         * detectable in cyc_to_fixed_sched_clock().
-         */
-        raw_local_irq_save(flags);
-        cd.epoch_cyc_copy = cyc;
-        smp_wmb();
-        cd.epoch_ns = ns;
-        smp_wmb();
-        cd.epoch_cyc = cyc;
-        raw_local_irq_restore(flags);
-}
-static void sched_clock_poll(unsigned long wrap_ticks)
-{
-        mod_timer(&sched_clock_timer, round_jiffies(jiffies + wrap_ticks));
-        update_sched_clock();
-}
-void __init setup_sched_clock(u32 (*read)(void), int bits, unsigned long rate)
-{
-        unsigned long r, w;
-        u64 res, wrap;
-        char r_unit;
-        if (cd.rate > rate)
-                return;
-        BUG_ON(bits > 32);
-        WARN_ON(!irqs_disabled());
-        read_sched_clock = read;
-        sched_clock_mask = (1 << bits) - 1;
-        cd.rate = rate;
-        /* calculate the mult/shift to convert counter ticks to ns. */
-        clocks_calc_mult_shift(&cd.mult, &cd.shift, rate, NSEC_PER_SEC, 0);
-        r = rate;
-        if (r >= 4000000) {
-                r /= 1000000;
-                r_unit = 'M';
-        } else if (r >= 1000) {
-                r /= 1000;
-                r_unit = 'k';
-        } else
-                r_unit = ' ';
-        /* calculate how many ns until we wrap */
-        wrap = cyc_to_ns((1ULL << bits) - 1, cd.mult, cd.shift);
-        do_div(wrap, NSEC_PER_MSEC);
-        w = wrap;
-        /* calculate the ns resolution of this counter */
-        res = cyc_to_ns(1ULL, cd.mult, cd.shift);
-        pr_info("sched_clock: %u bits at %lu%cHz, resolution %lluns, wraps every %lums\n",
-                bits, r, r_unit, res, w);
-        /*
-         * Start the timer to keep sched_clock() properly updated and
-         * sets the initial epoch.
-         */
-        sched_clock_timer.data = msecs_to_jiffies(w - (w / 10));
-        update_sched_clock();
-        /*
-         * Ensure that sched_clock() starts off at 0ns
-         */
-        cd.epoch_ns = 0;
-        /* Enable IRQ time accounting if we have a fast enough sched_clock */
-        if (irqtime > 0 || (irqtime == -1 && rate >= 1000000))
-                enable_sched_clock_irqtime();
-        pr_debug("Registered %pF as sched_clock source\n", read);
-}
-static unsigned long long notrace sched_clock_32(void)
-{
-        u32 cyc = read_sched_clock();
-        return cyc_to_sched_clock(cyc, sched_clock_mask);
-}
-unsigned long long __read_mostly (*sched_clock_func)(void) = sched_clock_32;
-unsigned long long notrace sched_clock(void)
-{
-        return sched_clock_func();
-}
-void __init sched_clock_postinit(void)
-{
-        /*
-         * If no sched_clock function has been provided at that point,
-         * make it the final one one.
-         */
-        if (read_sched_clock == jiffy_sched_clock_read)
-                setup_sched_clock(jiffy_sched_clock_read, 32, HZ);
-        sched_clock_poll(sched_clock_timer.data);
-}
-static int sched_clock_suspend(void)
-{
-        sched_clock_poll(sched_clock_timer.data);
-        cd.suspended = true;
-        return 0;
-}
-static void sched_clock_resume(void)
-{
-        cd.epoch_cyc = read_sched_clock();
-        cd.epoch_cyc_copy = cd.epoch_cyc;
-        cd.suspended = false;
-}
-static struct syscore_ops sched_clock_ops = {
-        .suspend = sched_clock_suspend,
-        .resume = sched_clock_resume,
-};
-static int __init sched_clock_syscore_init(void)
-{
-        register_syscore_ops(&sched_clock_ops);
-        return 0;
-}
-device_initcall(sched_clock_syscore_init);
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index b4b1d397592b..afc2489ee13b 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -37,6 +37,7 @@
 #include <asm/cputype.h>
 #include <asm/elf.h>
 #include <asm/procinfo.h>
+#include <asm/psci.h>
 #include <asm/sections.h>
 #include <asm/setup.h>
 #include <asm/smp_plat.h>
@@ -73,7 +74,7 @@ __setup("fpe=", fpe_setup);
 extern void paging_init(struct machine_desc *desc);
 extern void sanity_check_meminfo(void);
-extern void reboot_setup(char *str);
+extern enum reboot_mode reboot_mode;
 extern void setup_dma_zone(struct machine_desc *desc);
 unsigned int processor_id;
@@ -128,7 +129,9 @@ struct stack {
        u32 und[3];
 } ____cacheline_aligned;
+#ifndef CONFIG_CPU_V7M
 static struct stack stacks[NR_CPUS];
+#endif
 char elf_platform[ELF_PLATFORM_SIZE];
 EXPORT_SYMBOL(elf_platform);
@@ -207,7 +210,7 @@ static const char *proc_arch[] = {
        "5TEJ",
        "6TEJ",
        "7",
-        "?(11)",
+        "7M",
        "?(12)",
        "?(13)",
        "?(14)",
@@ -216,6 +219,12 @@ static const char *proc_arch[] = {
        "?(17)",
 };
+#ifdef CONFIG_CPU_V7M
+static int __get_cpu_architecture(void)
+{
+        return CPU_ARCH_ARMv7M;
+}
+#else
 static int __get_cpu_architecture(void)
 {
        int cpu_arch;
@@ -248,6 +257,7 @@ static int __get_cpu_architecture(void)
        return cpu_arch;
 }
+#endif
 int __pure cpu_architecture(void)
 {
@@ -293,7 +303,9 @@ static void __init cacheid_init(void)
 {
        unsigned int arch = cpu_architecture();
-        if (arch >= CPU_ARCH_ARMv6) {
+        if (arch == CPU_ARCH_ARMv7M) {
+                cacheid = 0;
+        } else if (arch >= CPU_ARCH_ARMv6) {
                unsigned int cachetype = read_cpuid_cachetype();
                if ((cachetype & (7 << 29)) == 4 << 29) {
                        /* ARMv7 register format */
@@ -355,7 +367,7 @@ void __init early_print(const char *str, ...)
 static void __init cpuid_init_hwcaps(void)
 {
-        unsigned int divide_instrs;
+        unsigned int divide_instrs, vmsa;
        if (cpu_architecture() < CPU_ARCH_ARMv7)
                return;
@@ -368,6 +380,11 @@ static void __init cpuid_init_hwcaps(void)
        case 1:
                elf_hwcap |= HWCAP_IDIVT;
        }
+        /* LPAE implies atomic ldrd/strd instructions */
+        vmsa = (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xf) >> 0;
+        if (vmsa >= 5)
+                elf_hwcap |= HWCAP_LPAE;
 }
 static void __init feat_v6_fixup(void)
@@ -392,6 +409,7 @@ static void __init feat_v6_fixup(void)
 */
 void notrace cpu_init(void)
 {
+#ifndef CONFIG_CPU_V7M
        unsigned int cpu = smp_processor_id();
        struct stack *stk = &stacks[cpu];
@@ -442,6 +460,7 @@ void notrace cpu_init(void)
              "I" (offsetof(struct stack, und[0])),
              PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
            : "r14");
+#endif
 }
 u32 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
@@ -456,9 +475,82 @@ void __init smp_setup_processor_id(void)
        for (i = 1; i < nr_cpu_ids; ++i)
                cpu_logical_map(i) = i == cpu ? 0 : i;
+        /*
+         * clear __my_cpu_offset on boot CPU to avoid hang caused by
+         * using percpu variable early, for example, lockdep will
+         * access percpu variable inside lock_release
+         */
+        set_my_cpu_offset(0);
        printk(KERN_INFO "Booting Linux on physical CPU 0x%x\n", mpidr);
 }
+struct mpidr_hash mpidr_hash;
+#ifdef CONFIG_SMP
+/**
+ * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
+ *                        level in order to build a linear index from an
+ *                        MPIDR value. Resulting algorithm is a collision
+ *                        free hash carried out through shifting and ORing
+ */
+static void __init smp_build_mpidr_hash(void)
+{
+        u32 i, affinity;
+        u32 fs[3], bits[3], ls, mask = 0;
+        /*
+         * Pre-scan the list of MPIDRS and filter out bits that do
+         * not contribute to affinity levels, ie they never toggle.
+         */
+        for_each_possible_cpu(i)
+                mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
+        pr_debug("mask of set bits 0x%x\n", mask);
+        /*
+         * Find and stash the last and first bit set at all affinity levels to
+         * check how many bits are required to represent them.
+         */
+        for (i = 0; i < 3; i++) {
+                affinity = MPIDR_AFFINITY_LEVEL(mask, i);
+                /*
+                 * Find the MSB bit and LSB bits position
+                 * to determine how many bits are required
+                 * to express the affinity level.
+                 */
+                ls = fls(affinity);
+                fs[i] = affinity ? ffs(affinity) - 1 : 0;
+                bits[i] = ls - fs[i];
+        }
+        /*
+         * An index can be created from the MPIDR by isolating the
+         * significant bits at each affinity level and by shifting
+         * them in order to compress the 24 bits values space to a
+         * compressed set of values. This is equivalent to hashing
+         * the MPIDR through shifting and ORing. It is a collision free
+         * hash though not minimal since some levels might contain a number
+         * of CPUs that is not an exact power of 2 and their bit
+         * representation might contain holes, eg MPIDR[7:0] = {0x2, 0x80}.
+         */
+        mpidr_hash.shift_aff[0] = fs[0];
+        mpidr_hash.shift_aff[1] = MPIDR_LEVEL_BITS + fs[1] - bits[0];
+        mpidr_hash.shift_aff[2] = 2*MPIDR_LEVEL_BITS + fs[2] -
+                                                (bits[1] + bits[0]);
+        mpidr_hash.mask = mask;
+        mpidr_hash.bits = bits[2] + bits[1] + bits[0];
+        pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] mask[0x%x] bits[%u]\n",
+                                mpidr_hash.shift_aff[0],
+                                mpidr_hash.shift_aff[1],
+                                mpidr_hash.shift_aff[2],
+                                mpidr_hash.mask,
+                                mpidr_hash.bits);
+        /*
+         * 4x is an arbitrary value used to warn on a hash table much bigger
+         * than expected on most systems.
+         */
+        if (mpidr_hash_size() > 4 * num_possible_cpus())
+                pr_warn("Large number of MPIDR hash buckets detected\n");
+        sync_cache_w(&mpidr_hash);
+}
+#endif
 static void __init setup_processor(void)
 {
        struct proc_info_list *list;
@@ -744,6 +836,8 @@ static int __init meminfo_cmp(const void *_a, const void *_b)
 void __init hyp_mode_check(void)
 {
 #ifdef CONFIG_ARM_VIRT_EXT
+        sync_boot_mode();
        if (is_hyp_mode_available()) {
                pr_info("CPU: All CPU(s) started in HYP mode.\n");
                pr_info("CPU: Virtualization extensions available.\n");
@@ -769,8 +863,8 @@ void __init setup_arch(char **cmdline_p)
        setup_dma_zone(mdesc);
-        if (mdesc->restart_mode)
+        if (mdesc->reboot_mode != REBOOT_HARD)
-                reboot_setup(&mdesc->restart_mode);
+                reboot_mode = mdesc->reboot_mode;
        init_mm.start_code = (unsigned long) _text;
        init_mm.end_code   = (unsigned long) _etext;
@@ -796,10 +890,17 @@ void __init setup_arch(char **cmdline_p)
        unflatten_device_tree();
        arm_dt_init_cpu_maps();
+        psci_init();
 #ifdef CONFIG_SMP
        if (is_smp()) {
-                smp_set_ops(mdesc->smp);
+                if (!mdesc->smp_init || !mdesc->smp_init()) {
+                        if (psci_smp_available())
+                                smp_set_ops(&psci_smp_ops);
+                        else if (mdesc->smp)
+                                smp_set_ops(mdesc->smp);
+                }
                smp_init_cpus();
+                smp_build_mpidr_hash();
        }
 #endif
@@ -872,6 +973,8 @@ static const char *hwcap_str[] = {
        "vfpv4",
        "idiva",
        "idivt",
+        "vfpd32",
+        "lpae",
        NULL
 };
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
index 296786bdbb73..ab3304225272 100644
--- a/arch/arm/kernel/signal.c
+++ b/arch/arm/kernel/signal.c
@@ -8,6 +8,7 @@
 * published by the Free Software Foundation.
 */
 #include <linux/errno.h>
+#include <linux/random.h>
 #include <linux/signal.h>
 #include <linux/personality.h>
 #include <linux/uaccess.h>
@@ -15,12 +16,11 @@
 #include <asm/elf.h>
 #include <asm/cacheflush.h>
+#include <asm/traps.h>
 #include <asm/ucontext.h>
 #include <asm/unistd.h>
 #include <asm/vfp.h>
-#include "signal.h"
 /*
 * For ARM syscalls, we encode the syscall number into the instruction.
 */
@@ -40,11 +40,13 @@
 #define SWI_THUMB_SIGRETURN     (0xdf00 << 16 | 0x2700 | (__NR_sigreturn - __NR_SYSCALL_BASE))
 #define SWI_THUMB_RT_SIGRETURN  (0xdf00 << 16 | 0x2700 | (__NR_rt_sigreturn - __NR_SYSCALL_BASE))
-const unsigned long sigreturn_codes[7] = {
+static const unsigned long sigreturn_codes[7] = {
        MOV_R7_NR_SIGRETURN,    SWI_SYS_SIGRETURN,    SWI_THUMB_SIGRETURN,
        MOV_R7_NR_RT_SIGRETURN, SWI_SYS_RT_SIGRETURN, SWI_THUMB_RT_SIGRETURN,
 };
+static unsigned long signal_return_offset;
 #ifdef CONFIG_CRUNCH
 static int preserve_crunch_context(struct crunch_sigframe __user *frame)
 {
@@ -392,17 +394,28 @@ setup_return(struct pt_regs *regs, struct ksignal *ksig,
                if (ksig->ka.sa.sa_flags & SA_SIGINFO)
                        idx += 3;
+                /*
+                 * Put the sigreturn code on the stack no matter which return
+                 * mechanism we use in order to remain ABI compliant
+                 */
                if (__put_user(sigreturn_codes[idx],   rc) ||
                    __put_user(sigreturn_codes[idx+1], rc+1))
                        return 1;
+#ifdef CONFIG_MMU
                if (cpsr & MODE32_BIT) {
+                        struct mm_struct *mm = current->mm;
                        /*
-                         * 32-bit code can use the new high-page
+                         * 32-bit code can use the signal return page
-                         * signal return code support.
+                         * except when the MPU has protected the vectors
+                         * page from PL0
                         */
-                        retcode = KERN_SIGRETURN_CODE + (idx << 2) + thumb;
+                        retcode = mm->context.sigpage + signal_return_offset +
-                } else {
+                                  (idx << 2) + thumb;
+                } else
+#endif
+                {
                        /*
                         * Ensure that the instruction cache sees
                         * the return code written onto the stack.
@@ -603,3 +616,33 @@ do_work_pending(struct pt_regs *regs, unsigned int thread_flags, int syscall)
        } while (thread_flags & _TIF_WORK_MASK);
        return 0;
 }
+struct page *get_signal_page(void)
+{
+        unsigned long ptr;
+        unsigned offset;
+        struct page *page;
+        void *addr;
+        page = alloc_pages(GFP_KERNEL, 0);
+        if (!page)
+                return NULL;
+        addr = page_address(page);
+        /* Give the signal return code some randomness */
+        offset = 0x200 + (get_random_int() & 0x7fc);
+        signal_return_offset = offset;
+        /*
+         * Copy signal return handlers into the vector page, and
+         * set sigreturn to be a pointer to these.
+         */
+        memcpy(addr + offset, sigreturn_codes, sizeof(sigreturn_codes));
+        ptr = (unsigned long)addr + offset;
+        flush_icache_range(ptr, ptr + sizeof(sigreturn_codes));
+        return page;
+}
diff --git a/arch/arm/kernel/signal.h b/arch/arm/kernel/signal.h
deleted file mode 100644
index 5ff067b7c752..000000000000
--- a/arch/arm/kernel/signal.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- *  linux/arch/arm/kernel/signal.h
- *
- *  Copyright (C) 2005-2009 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#define KERN_SIGRETURN_CODE     (CONFIG_VECTORS_BASE + 0x00000500)
-extern const unsigned long sigreturn_codes[7];
diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
index 987dcf33415c..db1536b8b30b 100644
--- a/arch/arm/kernel/sleep.S
+++ b/arch/arm/kernel/sleep.S
@@ -7,6 +7,49 @@
        .text
 /*
+ * Implementation of MPIDR hash algorithm through shifting
+ * and OR'ing.
+ *
+ * @dst: register containing hash result
+ * @rs0: register containing affinity level 0 bit shift
+ * @rs1: register containing affinity level 1 bit shift
+ * @rs2: register containing affinity level 2 bit shift
+ * @mpidr: register containing MPIDR value
+ * @mask: register containing MPIDR mask
+ *
+ * Pseudo C-code:
+ *
+ *u32 dst;
+ *
+ *compute_mpidr_hash(u32 rs0, u32 rs1, u32 rs2, u32 mpidr, u32 mask) {
+ *      u32 aff0, aff1, aff2;
+ *      u32 mpidr_masked = mpidr & mask;
+ *      aff0 = mpidr_masked & 0xff;
+ *      aff1 = mpidr_masked & 0xff00;
+ *      aff2 = mpidr_masked & 0xff0000;
+ *      dst = (aff0 >> rs0 | aff1 >> rs1 | aff2 >> rs2);
+ *}
+ * Input registers: rs0, rs1, rs2, mpidr, mask
+ * Output register: dst
+ * Note: input and output registers must be disjoint register sets
+         (eg: a macro instance with mpidr = r1 and dst = r1 is invalid)
+ */
+        .macro compute_mpidr_hash dst, rs0, rs1, rs2, mpidr, mask
+        and     \mpidr, \mpidr, \mask                   @ mask out MPIDR bits
+        and     \dst, \mpidr, #0xff                     @ mask=aff0
+ ARM(   mov     \dst, \dst, lsr \rs0            )       @ dst=aff0>>rs0
+ THUMB( lsr     \dst, \dst, \rs0                )
+        and     \mask, \mpidr, #0xff00                  @ mask = aff1
+ ARM(   orr     \dst, \dst, \mask, lsr \rs1     )       @ dst|=(aff1>>rs1)
+ THUMB( lsr     \mask, \mask, \rs1              )
+ THUMB( orr     \dst, \dst, \mask               )
+        and     \mask, \mpidr, #0xff0000                @ mask = aff2
+ ARM(   orr     \dst, \dst, \mask, lsr \rs2     )       @ dst|=(aff2>>rs2)
+ THUMB( lsr     \mask, \mask, \rs2              )
+ THUMB( orr     \dst, \dst, \mask               )
+        .endm
+/*
 * Save CPU state for a suspend.  This saves the CPU general purpose
 * registers, and allocates space on the kernel stack to save the CPU
 * specific registers and some other data for resume.
@@ -29,12 +72,18 @@ ENTRY(__cpu_suspend)
        mov     r1, r4                  @ size of save block
        mov     r2, r5                  @ virtual SP
        ldr     r3, =sleep_save_sp
-#ifdef CONFIG_SMP
+        ldr     r3, [r3, #SLEEP_SAVE_SP_VIRT]
-        ALT_SMP(mrc p15, 0, lr, c0, c0, 5)
+        ALT_SMP(mrc p15, 0, r9, c0, c0, 5)
-        ALT_UP(mov lr, #0)
+        ALT_UP_B(1f)
-        and     lr, lr, #15
+        ldr     r8, =mpidr_hash
+        /*
+         * This ldmia relies on the memory layout of the mpidr_hash
+         * struct mpidr_hash.
+         */
+        ldmia   r8, {r4-r7}     @ r4 = mpidr mask (r5,r6,r7) = l[0,1,2] shifts
+        compute_mpidr_hash      lr, r5, r6, r7, r9, r4
        add     r3, r3, lr, lsl #2
-#endif
+1:
        bl      __cpu_suspend_save
        adr     lr, BSYM(cpu_suspend_abort)
        ldmfd   sp!, {r0, pc}           @ call suspend fn
@@ -81,15 +130,23 @@ ENDPROC(cpu_resume_after_mmu)
        .data
        .align
 ENTRY(cpu_resume)
-#ifdef CONFIG_SMP
+        mov     r1, #0
-        adr     r0, sleep_save_sp
+        ALT_SMP(mrc p15, 0, r0, c0, c0, 5)
-        ALT_SMP(mrc p15, 0, r1, c0, c0, 5)
+        ALT_UP_B(1f)
-        ALT_UP(mov r1, #0)
+        adr     r2, mpidr_hash_ptr
-        and     r1, r1, #15
+        ldr     r3, [r2]
-        ldr     r0, [r0, r1, lsl #2]    @ stack phys addr
+        add     r2, r2, r3              @ r2 = struct mpidr_hash phys address
-#else
+        /*
-        ldr     r0, sleep_save_sp       @ stack phys addr
+         * This ldmia relies on the memory layout of the mpidr_hash
-#endif
+         * struct mpidr_hash.
+         */
+        ldmia   r2, { r3-r6 }   @ r3 = mpidr mask (r4,r5,r6) = l[0,1,2] shifts
+        compute_mpidr_hash      r1, r4, r5, r6, r0, r3
+1:
+        adr     r0, _sleep_save_sp
+        ldr     r0, [r0, #SLEEP_SAVE_SP_PHYS]
+        ldr     r0, [r0, r1, lsl #2]
        setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1  @ set SVC, irqs off
        @ load phys pgd, stack, resume fn
  ARM(  ldmia   r0!, {r1, sp, pc}       )
@@ -98,7 +155,11 @@ THUMB(	mov	sp, r2			)
 THUMB(  bx      r3                      )
 ENDPROC(cpu_resume)
-sleep_save_sp:
+        .align 2
-        .rept   CONFIG_NR_CPUS
+mpidr_hash_ptr:
-        .long   0                               @ preserve stack phys ptr here
+        .long   mpidr_hash - .                  @ mpidr_hash struct offset
-        .endr
+        .type   sleep_save_sp, #object
+ENTRY(sleep_save_sp)
+_sleep_save_sp:
+        .space  SLEEP_SAVE_SP_SZ                @ struct sleep_save_sp
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 5919eb451bb9..c2b4f8f0be9a 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -45,6 +45,7 @@
 #include <asm/smp_plat.h>
 #include <asm/virt.h>
 #include <asm/mach/arch.h>
+#include <asm/mpu.h>
 /*
 * as from 2.5, kernels no longer have an init_tasks structure
@@ -57,7 +58,7 @@ struct secondary_data secondary_data;
 * control for which core is the next to come out of the secondary
 * boot "holding pen"
 */
-volatile int __cpuinitdata pen_release = -1;
+volatile int pen_release = -1;
 enum ipi_msg_type {
        IPI_WAKEUP,
@@ -78,7 +79,14 @@ void __init smp_set_ops(struct smp_operations *ops)
                smp_ops = *ops;
 };
-int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
+static unsigned long get_arch_pgd(pgd_t *pgd)
+{
+        phys_addr_t pgdir = virt_to_phys(pgd);
+        BUG_ON(pgdir & ARCH_PGD_MASK);
+        return pgdir >> ARCH_PGD_SHIFT;
+}
+int __cpu_up(unsigned int cpu, struct task_struct *idle)
 {
        int ret;
@@ -87,8 +95,14 @@ int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
         * its stack and the page tables.
         */
        secondary_data.stack = task_stack_page(idle) + THREAD_START_SP;
-        secondary_data.pgdir = virt_to_phys(idmap_pgd);
+#ifdef CONFIG_ARM_MPU
-        secondary_data.swapper_pg_dir = virt_to_phys(swapper_pg_dir);
+        secondary_data.mpu_rgn_szr = mpu_rgn_info.rgns[MPU_RAM_REGION].drsr;
+#endif
+#ifdef CONFIG_MMU
+        secondary_data.pgdir = get_arch_pgd(idmap_pgd);
+        secondary_data.swapper_pg_dir = get_arch_pgd(swapper_pg_dir);
+#endif
        __cpuc_flush_dcache_area(&secondary_data, sizeof(secondary_data));
        outer_clean_range(__pa(&secondary_data), __pa(&secondary_data + 1));
@@ -112,9 +126,8 @@ int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
                pr_err("CPU%u: failed to boot: %d\n", cpu, ret);
        }
-        secondary_data.stack = NULL;
-        secondary_data.pgdir = 0;
+        memset(&secondary_data, 0, sizeof(secondary_data));
        return ret;
 }
@@ -125,7 +138,7 @@ void __init smp_init_cpus(void)
                smp_ops.smp_init_cpus();
 }
-int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+int boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
        if (smp_ops.smp_boot_secondary)
                return smp_ops.smp_boot_secondary(cpu, idle);
@@ -157,7 +170,7 @@ static int platform_cpu_disable(unsigned int cpu)
 /*
 * __cpu_disable runs on the processor to be shutdown.
 */
-int __cpuinit __cpu_disable(void)
+int __cpu_disable(void)
 {
        unsigned int cpu = smp_processor_id();
        int ret;
@@ -203,7 +216,7 @@ static DECLARE_COMPLETION(cpu_died);
 * called on the thread which is asking for a CPU to be shutdown -
 * waits until shutdown has completed, or it is timed out.
 */
-void __cpuinit __cpu_die(unsigned int cpu)
+void __cpu_die(unsigned int cpu)
 {
        if (!wait_for_completion_timeout(&cpu_died, msecs_to_jiffies(5000))) {
                pr_err("CPU%u: cpu didn't die\n", cpu);
@@ -293,7 +306,7 @@ void __ref cpu_die(void)
 * Called by both boot and secondaries to move global data into
 * per-processor storage.
 */
-static void __cpuinit smp_store_cpu_info(unsigned int cpuid)
+static void smp_store_cpu_info(unsigned int cpuid)
 {
        struct cpuinfo_arm *cpu_info = &per_cpu(cpu_data, cpuid);
@@ -309,7 +322,7 @@ static void percpu_timer_setup(void);
 * This is the secondary CPU boot entry.  We're using this CPUs
 * idle thread stack, but a set of temporary page tables.
 */
-asmlinkage void __cpuinit secondary_start_kernel(void)
+asmlinkage void secondary_start_kernel(void)
 {
        struct mm_struct *mm = &init_mm;
        unsigned int cpu;
@@ -508,7 +521,7 @@ static void broadcast_timer_set_mode(enum clock_event_mode mode,
 {
 }
-static void __cpuinit broadcast_timer_setup(struct clock_event_device *evt)
+static void broadcast_timer_setup(struct clock_event_device *evt)
 {
        evt->name       = "dummy_timer";
        evt->features   = CLOCK_EVT_FEAT_ONESHOT |
@@ -537,7 +550,7 @@ int local_timer_register(struct local_timer_ops *ops)
 }
 #endif
-static void __cpuinit percpu_timer_setup(void)
+static void percpu_timer_setup(void)
 {
        unsigned int cpu = smp_processor_id();
        struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu);
diff --git a/arch/arm/kernel/smp_tlb.c b/arch/arm/kernel/smp_tlb.c
index 9a52a07aa40e..c2edfff573c2 100644
--- a/arch/arm/kernel/smp_tlb.c
+++ b/arch/arm/kernel/smp_tlb.c
@@ -70,23 +70,6 @@ static inline void ipi_flush_bp_all(void *ignored)
        local_flush_bp_all();
 }
-#ifdef CONFIG_ARM_ERRATA_798181
-static int erratum_a15_798181(void)
-{
-        unsigned int midr = read_cpuid_id();
-        /* Cortex-A15 r0p0..r3p2 affected */
-        if ((midr & 0xff0ffff0) != 0x410fc0f0 || midr > 0x413fc0f2)
-                return 0;
-        return 1;
-}
-#else
-static int erratum_a15_798181(void)
-{
-        return 0;
-}
-#endif
 static void ipi_flush_tlb_a15_erratum(void *arg)
 {
        dmb();
@@ -103,7 +86,7 @@ static void broadcast_tlb_a15_erratum(void)
 static void broadcast_tlb_mm_a15_erratum(struct mm_struct *mm)
 {
-        int cpu, this_cpu;
+        int this_cpu;
        cpumask_t mask = { CPU_BITS_NONE };
        if (!erratum_a15_798181())
@@ -111,21 +94,7 @@ static void broadcast_tlb_mm_a15_erratum(struct mm_struct *mm)
        dummy_flush_tlb_a15_erratum();
        this_cpu = get_cpu();
-        for_each_online_cpu(cpu) {
+        a15_erratum_get_cpumask(this_cpu, mm, &mask);
-                if (cpu == this_cpu)
-                        continue;
-                /*
-                 * We only need to send an IPI if the other CPUs are running
-                 * the same ASID as the one being invalidated. There is no
-                 * need for locking around the active_asids check since the
-                 * switch_mm() function has at least one dmb() (as required by
-                 * this workaround) in case a context switch happens on
-                 * another CPU after the condition below.
-                 */
-                if (atomic64_read(&mm->context.id) ==
-                    atomic64_read(&per_cpu(active_asids, cpu)))
-                        cpumask_set_cpu(cpu, &mask);
-        }
        smp_call_function_many(&mask, ipi_flush_tlb_a15_erratum, NULL, 1);
        put_cpu();
 }
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index 90525d9d290b..25956204ef23 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -120,7 +120,7 @@ static int twd_rate_change(struct notifier_block *nb,
         * changing cpu.
         */
        if (flags == POST_RATE_CHANGE)
-                smp_call_function(twd_update_frequency,
+                on_each_cpu(twd_update_frequency,
                                  (void *)&cnd->new_rate, 1);
        return NOTIFY_OK;
@@ -187,7 +187,7 @@ core_initcall(twd_cpufreq_init);
 #endif
-static void __cpuinit twd_calibrate_rate(void)
+static void twd_calibrate_rate(void)
 {
        unsigned long count;
        u64 waitjiffies;
@@ -265,7 +265,7 @@ static void twd_get_clock(struct device_node *np)
 /*
 * Setup the local clock events for a CPU.
 */
-static int __cpuinit twd_timer_setup(struct clock_event_device *clk)
+static int twd_timer_setup(struct clock_event_device *clk)
 {
        struct clock_event_device **this_cpu_clk;
        int cpu = smp_processor_id();
@@ -308,7 +308,7 @@ static int __cpuinit twd_timer_setup(struct clock_event_device *clk)
        return 0;
 }
-static struct local_timer_ops twd_lt_ops __cpuinitdata = {
+static struct local_timer_ops twd_lt_ops = {
        .setup  = twd_timer_setup,
        .stop   = twd_timer_stop,
 };
diff --git a/arch/arm/kernel/suspend.c b/arch/arm/kernel/suspend.c
index c59c97ea8268..41cf3cbf756d 100644
--- a/arch/arm/kernel/suspend.c
+++ b/arch/arm/kernel/suspend.c
@@ -1,15 +1,54 @@
 #include <linux/init.h>
+#include <linux/slab.h>
+#include <asm/cacheflush.h>
 #include <asm/idmap.h>
 #include <asm/pgalloc.h>
 #include <asm/pgtable.h>
 #include <asm/memory.h>
+#include <asm/smp_plat.h>
 #include <asm/suspend.h>
 #include <asm/tlbflush.h>
 extern int __cpu_suspend(unsigned long, int (*)(unsigned long));
 extern void cpu_resume_mmu(void);
+#ifdef CONFIG_MMU
+/*
+ * Hide the first two arguments to __cpu_suspend - these are an implementation
+ * detail which platform code shouldn't have to know about.
+ */
+int cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
+{
+        struct mm_struct *mm = current->active_mm;
+        int ret;
+        if (!idmap_pgd)
+                return -EINVAL;
+        /*
+         * Provide a temporary page table with an identity mapping for
+         * the MMU-enable code, required for resuming.  On successful
+         * resume (indicated by a zero return code), we need to switch
+         * back to the correct page tables.
+         */
+        ret = __cpu_suspend(arg, fn);
+        if (ret == 0) {
+                cpu_switch_mm(mm->pgd, mm);
+                local_flush_bp_all();
+                local_flush_tlb_all();
+        }
+        return ret;
+}
+#else
+int cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
+{
+        return __cpu_suspend(arg, fn);
+}
+#define idmap_pgd       NULL
+#endif
 /*
 * This is called by __cpu_suspend() to save the state, and do whatever
 * flushing is required to ensure that when the CPU goes to sleep we have
@@ -47,30 +86,19 @@ void __cpu_suspend_save(u32 *ptr, u32 ptrsz, u32 sp, u32 *save_ptr)
                          virt_to_phys(save_ptr) + sizeof(*save_ptr));
 }
-/*
+extern struct sleep_save_sp sleep_save_sp;
- * Hide the first two arguments to __cpu_suspend - these are an implementation
- * detail which platform code shouldn't have to know about.
- */
-int cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
-{
-        struct mm_struct *mm = current->active_mm;
-        int ret;
-        if (!idmap_pgd)
-                return -EINVAL;
-        /*
+static int cpu_suspend_alloc_sp(void)
-         * Provide a temporary page table with an identity mapping for
+{
-         * the MMU-enable code, required for resuming.  On successful
+        void *ctx_ptr;
-         * resume (indicated by a zero return code), we need to switch
+        /* ctx_ptr is an array of physical addresses */
-         * back to the correct page tables.
+        ctx_ptr = kcalloc(mpidr_hash_size(), sizeof(u32), GFP_KERNEL);
-         */
-        ret = __cpu_suspend(arg, fn);
-        if (ret == 0) {
-                cpu_switch_mm(mm->pgd, mm);
-                local_flush_bp_all();
-                local_flush_tlb_all();
-        }
-        return ret;
+        if (WARN_ON(!ctx_ptr))
+                return -ENOMEM;
+        sleep_save_sp.save_ptr_stash = ctx_ptr;
+        sleep_save_sp.save_ptr_stash_phys = virt_to_phys(ctx_ptr);
+        sync_cache_w(&sleep_save_sp);
+        return 0;
 }
+early_initcall(cpu_suspend_alloc_sp);
diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c
index abff4e9aaee0..98aee3258398 100644
--- a/arch/arm/kernel/time.c
+++ b/arch/arm/kernel/time.c
@@ -24,9 +24,9 @@
 #include <linux/timer.h>
 #include <linux/clocksource.h>
 #include <linux/irq.h>
+#include <linux/sched_clock.h>
 #include <asm/thread_info.h>
-#include <asm/sched_clock.h>
 #include <asm/stacktrace.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
@@ -120,6 +120,4 @@ void __init time_init(void)
                machine_desc->init_time();
        else
                clocksource_of_init();
-        sched_clock_postinit();
 }
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 18b32e8e4497..ab517fcce21b 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -35,8 +35,6 @@
 #include <asm/tls.h>
 #include <asm/system_misc.h>
-#include "signal.h"
 static const char *handler[]= { "prefetch abort", "data abort", "address exception", "interrupt" };
 void *vectors_page;
@@ -581,7 +579,7 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
                return regs->ARM_r0;
        case NR(set_tls):
-                thread->tp_value = regs->ARM_r0;
+                thread->tp_value[0] = regs->ARM_r0;
                if (tls_emu)
                        return 0;
                if (has_tls_reg) {
@@ -699,7 +697,7 @@ static int get_tp_trap(struct pt_regs *regs, unsigned int instr)
        int reg = (instr >> 12) & 15;
        if (reg == 15)
                return 1;
-        regs->uregs[reg] = current_thread_info()->tp_value;
+        regs->uregs[reg] = current_thread_info()->tp_value[0];
        regs->ARM_pc += 4;
        return 0;
 }
@@ -800,47 +798,63 @@ void __init trap_init(void)
        return;
 }
-static void __init kuser_get_tls_init(unsigned long vectors)
+#ifdef CONFIG_KUSER_HELPERS
+static void __init kuser_init(void *vectors)
 {
+        extern char __kuser_helper_start[], __kuser_helper_end[];
+        int kuser_sz = __kuser_helper_end - __kuser_helper_start;
+        memcpy(vectors + 0x1000 - kuser_sz, __kuser_helper_start, kuser_sz);
        /*
         * vectors + 0xfe0 = __kuser_get_tls
         * vectors + 0xfe8 = hardware TLS instruction at 0xffff0fe8
         */
        if (tls_emu || has_tls_reg)
-                memcpy((void *)vectors + 0xfe0, (void *)vectors + 0xfe8, 4);
+                memcpy(vectors + 0xfe0, vectors + 0xfe8, 4);
 }
+#else
+static void __init kuser_init(void *vectors)
+{
+}
+#endif
 void __init early_trap_init(void *vectors_base)
 {
+#ifndef CONFIG_CPU_V7M
        unsigned long vectors = (unsigned long)vectors_base;
        extern char __stubs_start[], __stubs_end[];
        extern char __vectors_start[], __vectors_end[];
-        extern char __kuser_helper_start[], __kuser_helper_end[];
+        unsigned i;
-        int kuser_sz = __kuser_helper_end - __kuser_helper_start;
        vectors_page = vectors_base;
        /*
+         * Poison the vectors page with an undefined instruction.  This
+         * instruction is chosen to be undefined for both ARM and Thumb
+         * ISAs.  The Thumb version is an undefined instruction with a
+         * branch back to the undefined instruction.
+         */
+        for (i = 0; i < PAGE_SIZE / sizeof(u32); i++)
+                ((u32 *)vectors_base)[i] = 0xe7fddef1;
+        /*
         * Copy the vectors, stubs and kuser helpers (in entry-armv.S)
         * into the vector page, mapped at 0xffff0000, and ensure these
         * are visible to the instruction stream.
         */
        memcpy((void *)vectors, __vectors_start, __vectors_end - __vectors_start);
-        memcpy((void *)vectors + 0x200, __stubs_start, __stubs_end - __stubs_start);
+        memcpy((void *)vectors + 0x1000, __stubs_start, __stubs_end - __stubs_start);
-        memcpy((void *)vectors + 0x1000 - kuser_sz, __kuser_helper_start, kuser_sz);
-        /*
+        kuser_init(vectors_base);
-         * Do processor specific fixups for the kuser helpers
-         */
-        kuser_get_tls_init(vectors);
+        flush_icache_range(vectors, vectors + PAGE_SIZE * 2);
+        modify_domain(DOMAIN_USER, DOMAIN_CLIENT);
+#else /* ifndef CONFIG_CPU_V7M */
        /*
-         * Copy signal return handlers into the vector page, and
+         * on V7-M there is no need to copy the vector table to a dedicated
-         * set sigreturn to be a pointer to these.
+         * memory area. The address is configurable and so a table in the kernel
+         * image can be used.
         */
-        memcpy((void *)(vectors + KERN_SIGRETURN_CODE - CONFIG_VECTORS_BASE),
+#endif
-               sigreturn_codes, sizeof(sigreturn_codes));
-        flush_icache_range(vectors, vectors + PAGE_SIZE);
-        modify_domain(DOMAIN_USER, DOMAIN_CLIENT);
 }
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index a871b8e00fca..7bcee5c9b604 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -70,10 +70,6 @@ SECTIONS
                ARM_EXIT_DISCARD(EXIT_TEXT)
                ARM_EXIT_DISCARD(EXIT_DATA)
                EXIT_CALL
-#ifndef CONFIG_HOTPLUG
-                *(.ARM.exidx.devexit.text)
-                *(.ARM.extab.devexit.text)
-#endif
 #ifndef CONFIG_MMU
                *(.fixup)
                *(__ex_table)
@@ -152,6 +148,23 @@ SECTIONS
        . = ALIGN(PAGE_SIZE);
        __init_begin = .;
 #endif
+        /*
+         * The vectors and stubs are relocatable code, and the
+         * only thing that matters is their relative offsets
+         */
+        __vectors_start = .;
+        .vectors 0 : AT(__vectors_start) {
+                *(.vectors)
+        }
+        . = __vectors_start + SIZEOF(.vectors);
+        __vectors_end = .;
+        __stubs_start = .;
+        .stubs 0x1000 : AT(__stubs_start) {
+                *(.stubs)
+        }
+        . = __stubs_start + SIZEOF(.stubs);
+        __stubs_end = .;
        INIT_TEXT_SECTION(8)
        .exit.text : {
diff --git a/arch/arm/kvm/Kconfig b/arch/arm/kvm/Kconfig
index 370e1a8af6ac..ebf5015508b5 100644
--- a/arch/arm/kvm/Kconfig
+++ b/arch/arm/kvm/Kconfig
@@ -41,9 +41,9 @@ config KVM_ARM_HOST
          Provides host support for ARM processors.
 config KVM_ARM_MAX_VCPUS
-        int "Number maximum supported virtual CPUs per VM" if KVM_ARM_HOST
+        int "Number maximum supported virtual CPUs per VM"
-        default 4 if KVM_ARM_HOST
+        depends on KVM_ARM_HOST
-        default 0
+        default 4
        help
          Static number of max supported virtual CPUs per VM.
@@ -67,6 +67,4 @@ config KVM_ARM_TIMER
        ---help---
          Adds support for the Architected Timers in virtual machines
-source drivers/virtio/Kconfig
 endif # VIRTUALIZATION
diff --git a/arch/arm/kvm/Makefile b/arch/arm/kvm/Makefile
index 53c5ed83d16f..d99bee4950e5 100644
--- a/arch/arm/kvm/Makefile
+++ b/arch/arm/kvm/Makefile
@@ -14,10 +14,11 @@ CFLAGS_mmu.o := -I.
 AFLAGS_init.o := -Wa,-march=armv7-a$(plus_virt)
 AFLAGS_interrupts.o := -Wa,-march=armv7-a$(plus_virt)
-kvm-arm-y = $(addprefix ../../../virt/kvm/, kvm_main.o coalesced_mmio.o)
+KVM := ../../../virt/kvm
+kvm-arm-y = $(KVM)/kvm_main.o $(KVM)/coalesced_mmio.o
 obj-y += kvm-arm.o init.o interrupts.o
 obj-y += arm.o handle_exit.o guest.o mmu.o emulate.o reset.o
 obj-y += coproc.o coproc_a15.o mmio.o psci.o perf.o
-obj-$(CONFIG_KVM_ARM_VGIC) += vgic.o
+obj-$(CONFIG_KVM_ARM_VGIC) += $(KVM)/arm/vgic.o
-obj-$(CONFIG_KVM_ARM_TIMER) += arch_timer.o
+obj-$(CONFIG_KVM_ARM_TIMER) += $(KVM)/arm/arch_timer.o
diff --git a/arch/arm/kvm/arch_timer.c b/arch/arm/kvm/arch_timer.c
deleted file mode 100644
index c55b6089e923..000000000000
--- a/arch/arm/kvm/arch_timer.c
+++ /dev/null
@@ -1,272 +0,0 @@
-/*
- * Copyright (C) 2012 ARM Ltd.
- * Author: Marc Zyngier <marc.zyngier@arm.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#include <linux/cpu.h>
-#include <linux/of_irq.h>
-#include <linux/kvm.h>
-#include <linux/kvm_host.h>
-#include <linux/interrupt.h>
-#include <clocksource/arm_arch_timer.h>
-#include <asm/arch_timer.h>
-#include <asm/kvm_vgic.h>
-#include <asm/kvm_arch_timer.h>
-static struct timecounter *timecounter;
-static struct workqueue_struct *wqueue;
-static struct kvm_irq_level timer_irq = {
-        .level  = 1,
-};
-static cycle_t kvm_phys_timer_read(void)
-{
-        return timecounter->cc->read(timecounter->cc);
-}
-static bool timer_is_armed(struct arch_timer_cpu *timer)
-{
-        return timer->armed;
-}
-/* timer_arm: as in "arm the timer", not as in ARM the company */
-static void timer_arm(struct arch_timer_cpu *timer, u64 ns)
-{
-        timer->armed = true;
-        hrtimer_start(&timer->timer, ktime_add_ns(ktime_get(), ns),
-                      HRTIMER_MODE_ABS);
-}
-static void timer_disarm(struct arch_timer_cpu *timer)
-{
-        if (timer_is_armed(timer)) {
-                hrtimer_cancel(&timer->timer);
-                cancel_work_sync(&timer->expired);
-                timer->armed = false;
-        }
-}
-static void kvm_timer_inject_irq(struct kvm_vcpu *vcpu)
-{
-        struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
-        timer->cntv_ctl |= ARCH_TIMER_CTRL_IT_MASK;
-        kvm_vgic_inject_irq(vcpu->kvm, vcpu->vcpu_id,
-                            vcpu->arch.timer_cpu.irq->irq,
-                            vcpu->arch.timer_cpu.irq->level);
-}
-static irqreturn_t kvm_arch_timer_handler(int irq, void *dev_id)
-{
-        struct kvm_vcpu *vcpu = *(struct kvm_vcpu **)dev_id;
-        /*
-         * We disable the timer in the world switch and let it be
-         * handled by kvm_timer_sync_hwstate(). Getting a timer
-         * interrupt at this point is a sure sign of some major
-         * breakage.
-         */
-        pr_warn("Unexpected interrupt %d on vcpu %p\n", irq, vcpu);
-        return IRQ_HANDLED;
-}
-static void kvm_timer_inject_irq_work(struct work_struct *work)
-{
-        struct kvm_vcpu *vcpu;
-        vcpu = container_of(work, struct kvm_vcpu, arch.timer_cpu.expired);
-        vcpu->arch.timer_cpu.armed = false;
-        kvm_timer_inject_irq(vcpu);
-}
-static enum hrtimer_restart kvm_timer_expire(struct hrtimer *hrt)
-{
-        struct arch_timer_cpu *timer;
-        timer = container_of(hrt, struct arch_timer_cpu, timer);
-        queue_work(wqueue, &timer->expired);
-        return HRTIMER_NORESTART;
-}
-/**
- * kvm_timer_flush_hwstate - prepare to move the virt timer to the cpu
- * @vcpu: The vcpu pointer
- *
- * Disarm any pending soft timers, since the world-switch code will write the
- * virtual timer state back to the physical CPU.
- */
-void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu)
-{
-        struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
-        /*
-         * We're about to run this vcpu again, so there is no need to
-         * keep the background timer running, as we're about to
-         * populate the CPU timer again.
-         */
-        timer_disarm(timer);
-}
-/**
- * kvm_timer_sync_hwstate - sync timer state from cpu
- * @vcpu: The vcpu pointer
- *
- * Check if the virtual timer was armed and either schedule a corresponding
- * soft timer or inject directly if already expired.
- */
-void kvm_timer_sync_hwstate(struct kvm_vcpu *vcpu)
-{
-        struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
-        cycle_t cval, now;
-        u64 ns;
-        if ((timer->cntv_ctl & ARCH_TIMER_CTRL_IT_MASK) ||
-                !(timer->cntv_ctl & ARCH_TIMER_CTRL_ENABLE))
-                return;
-        cval = timer->cntv_cval;
-        now = kvm_phys_timer_read() - vcpu->kvm->arch.timer.cntvoff;
-        BUG_ON(timer_is_armed(timer));
-        if (cval <= now) {
-                /*
-                 * Timer has already expired while we were not
-                 * looking. Inject the interrupt and carry on.
-                 */
-                kvm_timer_inject_irq(vcpu);
-                return;
-        }
-        ns = cyclecounter_cyc2ns(timecounter->cc, cval - now);
-        timer_arm(timer, ns);
-}
-void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu)
-{
-        struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
-        INIT_WORK(&timer->expired, kvm_timer_inject_irq_work);
-        hrtimer_init(&timer->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
-        timer->timer.function = kvm_timer_expire;
-        timer->irq = &timer_irq;
-}
-static void kvm_timer_init_interrupt(void *info)
-{
-        enable_percpu_irq(timer_irq.irq, 0);
-}
-static int kvm_timer_cpu_notify(struct notifier_block *self,
-                                unsigned long action, void *cpu)
-{
-        switch (action) {
-        case CPU_STARTING:
-        case CPU_STARTING_FROZEN:
-                kvm_timer_init_interrupt(NULL);
-                break;
-        case CPU_DYING:
-        case CPU_DYING_FROZEN:
-                disable_percpu_irq(timer_irq.irq);
-                break;
-        }
-        return NOTIFY_OK;
-}
-static struct notifier_block kvm_timer_cpu_nb = {
-        .notifier_call = kvm_timer_cpu_notify,
-};
-static const struct of_device_id arch_timer_of_match[] = {
-        { .compatible   = "arm,armv7-timer",    },
-        {},
-};
-int kvm_timer_hyp_init(void)
-{
-        struct device_node *np;
-        unsigned int ppi;
-        int err;
-        timecounter = arch_timer_get_timecounter();
-        if (!timecounter)
-                return -ENODEV;
-        np = of_find_matching_node(NULL, arch_timer_of_match);
-        if (!np) {
-                kvm_err("kvm_arch_timer: can't find DT node\n");
-                return -ENODEV;
-        }
-        ppi = irq_of_parse_and_map(np, 2);
-        if (!ppi) {
-                kvm_err("kvm_arch_timer: no virtual timer interrupt\n");
-                err = -EINVAL;
-                goto out;
-        }
-        err = request_percpu_irq(ppi, kvm_arch_timer_handler,
-                                 "kvm guest timer", kvm_get_running_vcpus());
-        if (err) {
-                kvm_err("kvm_arch_timer: can't request interrupt %d (%d)\n",
-                        ppi, err);
-                goto out;
-        }
-        timer_irq.irq = ppi;
-        err = register_cpu_notifier(&kvm_timer_cpu_nb);
-        if (err) {
-                kvm_err("Cannot register timer CPU notifier\n");
-                goto out_free;
-        }
-        wqueue = create_singlethread_workqueue("kvm_arch_timer");
-        if (!wqueue) {
-                err = -ENOMEM;
-                goto out_free;
-        }
-        kvm_info("%s IRQ%d\n", np->name, ppi);
-        on_each_cpu(kvm_timer_init_interrupt, NULL, 1);
-        goto out;
-out_free:
-        free_percpu_irq(ppi, kvm_get_running_vcpus());
-out:
-        of_node_put(np);
-        return err;
-}
-void kvm_timer_vcpu_terminate(struct kvm_vcpu *vcpu)
-{
-        struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
-        timer_disarm(timer);
-}
-int kvm_timer_init(struct kvm *kvm)
-{
-        if (timecounter && wqueue) {
-                kvm->arch.timer.cntvoff = kvm_phys_timer_read();
-                kvm->arch.timer.enabled = 1;
-        }
-        return 0;
-}
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index ef1703b9587b..741f66a2edbd 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -800,8 +800,8 @@ long kvm_arch_vm_ioctl(struct file *filp,
 static void cpu_init_hyp_mode(void *dummy)
 {
-        unsigned long long boot_pgd_ptr;
+        phys_addr_t boot_pgd_ptr;
-        unsigned long long pgd_ptr;
+        phys_addr_t pgd_ptr;
        unsigned long hyp_stack_ptr;
        unsigned long stack_page;
        unsigned long vector_ptr;
@@ -809,8 +809,8 @@ static void cpu_init_hyp_mode(void *dummy)
        /* Switch from the HYP stub to our own HYP init vector */
        __hyp_set_vectors(kvm_get_idmap_vector());
-        boot_pgd_ptr = (unsigned long long)kvm_mmu_get_boot_httbr();
+        boot_pgd_ptr = kvm_mmu_get_boot_httbr();
-        pgd_ptr = (unsigned long long)kvm_mmu_get_httbr();
+        pgd_ptr = kvm_mmu_get_httbr();
        stack_page = __get_cpu_var(kvm_arm_hyp_stack_page);
        hyp_stack_ptr = stack_page + PAGE_SIZE;
        vector_ptr = (unsigned long)__kvm_hyp_vector;
diff --git a/arch/arm/kvm/coproc.c b/arch/arm/kvm/coproc.c
index 8eea97be1ed5..4a5199070430 100644
--- a/arch/arm/kvm/coproc.c
+++ b/arch/arm/kvm/coproc.c
@@ -180,6 +180,10 @@ static const struct coproc_reg cp15_regs[] = {
                        NULL, reset_unknown, c6_DFAR },
        { CRn( 6), CRm( 0), Op1( 0), Op2( 2), is32,
                        NULL, reset_unknown, c6_IFAR },
+        /* PAR swapped by interrupt.S */
+        { CRn( 7), Op1( 0), is64, NULL, reset_unknown64, c7_PAR },
        /*
         * DC{C,I,CI}SW operations:
         */
diff --git a/arch/arm/kvm/handle_exit.c b/arch/arm/kvm/handle_exit.c
index 3d74a0be47db..df4c82d47ad7 100644
--- a/arch/arm/kvm/handle_exit.c
+++ b/arch/arm/kvm/handle_exit.c
@@ -52,9 +52,6 @@ static int handle_hvc(struct kvm_vcpu *vcpu, struct kvm_run *run)
 static int handle_smc(struct kvm_vcpu *vcpu, struct kvm_run *run)
 {
-        if (kvm_psci_call(vcpu))
-                return 1;
        kvm_inject_undefined(vcpu);
        return 1;
 }
diff --git a/arch/arm/kvm/interrupts.S b/arch/arm/kvm/interrupts.S
index f7793df62f58..16cd4ba5d7fd 100644
--- a/arch/arm/kvm/interrupts.S
+++ b/arch/arm/kvm/interrupts.S
@@ -49,6 +49,7 @@ __kvm_hyp_code_start:
 ENTRY(__kvm_tlb_flush_vmid_ipa)
        push    {r2, r3}
+        dsb     ishst
        add     r0, r0, #KVM_VTTBR
        ldrd    r2, r3, [r0]
        mcrr    p15, 6, r2, r3, c2      @ Write VTTBR
@@ -291,6 +292,7 @@ THUMB(	orr	r2, r2, #PSR_T_BIT	)
        ldr     r2, =BSYM(panic)
        msr     ELR_hyp, r2
        ldr     r0, =\panic_str
+        clrex                           @ Clear exclusive monitor
        eret
 .endm
@@ -414,6 +416,10 @@ guest_trap:
        mrcne   p15, 4, r2, c6, c0, 4   @ HPFAR
        bne     3f
+        /* Preserve PAR */
+        mrrc    p15, 0, r0, r1, c7      @ PAR
+        push    {r0, r1}
        /* Resolve IPA using the xFAR */
        mcr     p15, 0, r2, c7, c8, 0   @ ATS1CPR
        isb
@@ -424,13 +430,20 @@ guest_trap:
        lsl     r2, r2, #4
        orr     r2, r2, r1, lsl #24
+        /* Restore PAR */
+        pop     {r0, r1}
+        mcrr    p15, 0, r0, r1, c7      @ PAR
 3:      load_vcpu                       @ Load VCPU pointer to r0
        str     r2, [r0, #VCPU_HPFAR]
 1:      mov     r1, #ARM_EXCEPTION_HVC
        b       __kvm_vcpu_return
-4:      pop     {r0, r1, r2}            @ Failed translation, return to guest
+4:      pop     {r0, r1}                @ Failed translation, return to guest
+        mcrr    p15, 0, r0, r1, c7      @ PAR
+        clrex
+        pop     {r0, r1, r2}
        eret
 /*
@@ -456,6 +469,7 @@ switch_to_guest_vfp:
        pop     {r3-r7}
        pop     {r0-r2}
+        clrex
        eret
 #endif
diff --git a/arch/arm/kvm/interrupts_head.S b/arch/arm/kvm/interrupts_head.S
index 3c8f2f0b4c5e..6f18695a09cb 100644
--- a/arch/arm/kvm/interrupts_head.S
+++ b/arch/arm/kvm/interrupts_head.S
@@ -302,11 +302,14 @@ vcpu	.req	r0		@ vcpu pointer always in r0
        .endif
        mrc     p15, 0, r2, c14, c1, 0  @ CNTKCTL
+        mrrc    p15, 0, r4, r5, c7      @ PAR
        .if \store_to_vcpu == 0
-        push    {r2}
+        push    {r2,r4-r5}
        .else
        str     r2, [vcpu, #CP15_OFFSET(c14_CNTKCTL)]
+        add     r12, vcpu, #CP15_OFFSET(c7_PAR)
+        strd    r4, r5, [r12]
        .endif
 .endm
@@ -319,12 +322,15 @@ vcpu	.req	r0		@ vcpu pointer always in r0
 */
 .macro write_cp15_state read_from_vcpu
        .if \read_from_vcpu == 0
-        pop     {r2}
+        pop     {r2,r4-r5}
        .else
        ldr     r2, [vcpu, #CP15_OFFSET(c14_CNTKCTL)]
+        add     r12, vcpu, #CP15_OFFSET(c7_PAR)
+        ldrd    r4, r5, [r12]
        .endif
        mcr     p15, 0, r2, c14, c1, 0  @ CNTKCTL
+        mcrr    p15, 0, r4, r5, c7      @ PAR
        .if \read_from_vcpu == 0
        pop     {r2-r12}
@@ -497,6 +503,10 @@ vcpu	.req	r0		@ vcpu pointer always in r0
        add     r5, vcpu, r4
        strd    r2, r3, [r5]
+        @ Ensure host CNTVCT == CNTPCT
+        mov     r2, #0
+        mcrr    p15, 4, r2, r2, c14     @ CNTVOFF
 1:
 #endif
        @ Allow physical timer/counter access for the host
diff --git a/arch/arm/kvm/mmio.c b/arch/arm/kvm/mmio.c
index 72a12f2171b2..b8e06b7a2833 100644
--- a/arch/arm/kvm/mmio.c
+++ b/arch/arm/kvm/mmio.c
@@ -86,12 +86,6 @@ static int decode_hsr(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
        sign_extend = kvm_vcpu_dabt_issext(vcpu);
        rt = kvm_vcpu_dabt_get_rd(vcpu);
-        if (kvm_vcpu_reg_is_pc(vcpu, rt)) {
-                /* IO memory trying to read/write pc */
-                kvm_inject_pabt(vcpu, kvm_vcpu_get_hfar(vcpu));
-                return 1;
-        }
        mmio->is_write = is_write;
        mmio->phys_addr = fault_ipa;
        mmio->len = len;
diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
index 84ba67b982c0..ca6bea4859b4 100644
--- a/arch/arm/kvm/mmu.c
+++ b/arch/arm/kvm/mmu.c
@@ -382,9 +382,6 @@ int kvm_alloc_stage2_pgd(struct kvm *kvm)
        if (!pgd)
                return -ENOMEM;
-        /* stage-2 pgd must be aligned to its size */
-        VM_BUG_ON((unsigned long)pgd & (S2_PGD_SIZE - 1));
        memset(pgd, 0, PTRS_PER_S2_PGD * sizeof(pgd_t));
        kvm_clean_pgd(pgd);
        kvm->arch.pgd = pgd;
diff --git a/arch/arm/kvm/psci.c b/arch/arm/kvm/psci.c
index 7ee5bb7a3667..86a693a02ba3 100644
--- a/arch/arm/kvm/psci.c
+++ b/arch/arm/kvm/psci.c
@@ -75,7 +75,7 @@ static unsigned long kvm_psci_vcpu_on(struct kvm_vcpu *source_vcpu)
 * kvm_psci_call - handle PSCI call if r0 value is in range
 * @vcpu: Pointer to the VCPU struct
 *
- * Handle PSCI calls from guests through traps from HVC or SMC instructions.
+ * Handle PSCI calls from guests through traps from HVC instructions.
 * The calling convention is similar to SMC calls to the secure world where
 * the function number is placed in r0 and this function returns true if the
 * function number specified in r0 is withing the PSCI range, and false
diff --git a/arch/arm/kvm/reset.c b/arch/arm/kvm/reset.c
index b80256b554cd..b7840e7aa452 100644
--- a/arch/arm/kvm/reset.c
+++ b/arch/arm/kvm/reset.c
@@ -27,6 +27,8 @@
 #include <asm/kvm_arm.h>
 #include <asm/kvm_coproc.h>
+#include <kvm/arm_arch_timer.h>
 /******************************************************************************
 * Cortex-A15 Reset Values
 */
@@ -37,6 +39,11 @@ static struct kvm_regs a15_regs_reset = {
        .usr_regs.ARM_cpsr = SVC_MODE | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT,
 };
+static const struct kvm_irq_level a15_vtimer_irq = {
+        .irq = 27,
+        .level = 1,
+};
 /*******************************************************************************
 * Exported reset function
@@ -52,6 +59,7 @@ static struct kvm_regs a15_regs_reset = {
 int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
 {
        struct kvm_regs *cpu_reset;
+        const struct kvm_irq_level *cpu_vtimer_irq;
        switch (vcpu->arch.target) {
        case KVM_ARM_TARGET_CORTEX_A15:
@@ -59,6 +67,7 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
                        return -EINVAL;
                cpu_reset = &a15_regs_reset;
                vcpu->arch.midr = read_cpuid_id();
+                cpu_vtimer_irq = &a15_vtimer_irq;
                break;
        default:
                return -ENODEV;
@@ -70,5 +79,8 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
        /* Reset CP15 registers */
        kvm_reset_coprocs(vcpu);
+        /* Reset arch_timer context */
+        kvm_timer_vcpu_reset(vcpu, cpu_vtimer_irq);
        return 0;
 }
diff --git a/arch/arm/kvm/vgic.c b/arch/arm/kvm/vgic.c
deleted file mode 100644
index 17c5ac7d10ed..000000000000
--- a/arch/arm/kvm/vgic.c
+++ /dev/null
@@ -1,1499 +0,0 @@
-/*
- * Copyright (C) 2012 ARM Ltd.
- * Author: Marc Zyngier <marc.zyngier@arm.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#include <linux/cpu.h>
-#include <linux/kvm.h>
-#include <linux/kvm_host.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/irqchip/arm-gic.h>
-#include <asm/kvm_emulate.h>
-#include <asm/kvm_arm.h>
-#include <asm/kvm_mmu.h>
-/*
- * How the whole thing works (courtesy of Christoffer Dall):
- *
- * - At any time, the dist->irq_pending_on_cpu is the oracle that knows if
- *   something is pending
- * - VGIC pending interrupts are stored on the vgic.irq_state vgic
- *   bitmap (this bitmap is updated by both user land ioctls and guest
- *   mmio ops, and other in-kernel peripherals such as the
- *   arch. timers) and indicate the 'wire' state.
- * - Every time the bitmap changes, the irq_pending_on_cpu oracle is
- *   recalculated
- * - To calculate the oracle, we need info for each cpu from
- *   compute_pending_for_cpu, which considers:
- *   - PPI: dist->irq_state & dist->irq_enable
- *   - SPI: dist->irq_state & dist->irq_enable & dist->irq_spi_target
- *   - irq_spi_target is a 'formatted' version of the GICD_ICFGR
- *     registers, stored on each vcpu. We only keep one bit of
- *     information per interrupt, making sure that only one vcpu can
- *     accept the interrupt.
- * - The same is true when injecting an interrupt, except that we only
- *   consider a single interrupt at a time. The irq_spi_cpu array
- *   contains the target CPU for each SPI.
- *
- * The handling of level interrupts adds some extra complexity. We
- * need to track when the interrupt has been EOIed, so we can sample
- * the 'line' again. This is achieved as such:
- *
- * - When a level interrupt is moved onto a vcpu, the corresponding
- *   bit in irq_active is set. As long as this bit is set, the line
- *   will be ignored for further interrupts. The interrupt is injected
- *   into the vcpu with the GICH_LR_EOI bit set (generate a
- *   maintenance interrupt on EOI).
- * - When the interrupt is EOIed, the maintenance interrupt fires,
- *   and clears the corresponding bit in irq_active. This allow the
- *   interrupt line to be sampled again.
- */
-#define VGIC_ADDR_UNDEF         (-1)
-#define IS_VGIC_ADDR_UNDEF(_x)  ((_x) == VGIC_ADDR_UNDEF)
-/* Physical address of vgic virtual cpu interface */
-static phys_addr_t vgic_vcpu_base;
-/* Virtual control interface base address */
-static void __iomem *vgic_vctrl_base;
-static struct device_node *vgic_node;
-#define ACCESS_READ_VALUE       (1 << 0)
-#define ACCESS_READ_RAZ         (0 << 0)
-#define ACCESS_READ_MASK(x)     ((x) & (1 << 0))
-#define ACCESS_WRITE_IGNORED    (0 << 1)
-#define ACCESS_WRITE_SETBIT     (1 << 1)
-#define ACCESS_WRITE_CLEARBIT   (2 << 1)
-#define ACCESS_WRITE_VALUE      (3 << 1)
-#define ACCESS_WRITE_MASK(x)    ((x) & (3 << 1))
-static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu);
-static void vgic_update_state(struct kvm *kvm);
-static void vgic_kick_vcpus(struct kvm *kvm);
-static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg);
-static u32 vgic_nr_lr;
-static unsigned int vgic_maint_irq;
-static u32 *vgic_bitmap_get_reg(struct vgic_bitmap *x,
-                                int cpuid, u32 offset)
-{
-        offset >>= 2;
-        if (!offset)
-                return x->percpu[cpuid].reg;
-        else
-                return x->shared.reg + offset - 1;
-}
-static int vgic_bitmap_get_irq_val(struct vgic_bitmap *x,
-                                   int cpuid, int irq)
-{
-        if (irq < VGIC_NR_PRIVATE_IRQS)
-                return test_bit(irq, x->percpu[cpuid].reg_ul);
-        return test_bit(irq - VGIC_NR_PRIVATE_IRQS, x->shared.reg_ul);
-}
-static void vgic_bitmap_set_irq_val(struct vgic_bitmap *x, int cpuid,
-                                    int irq, int val)
-{
-        unsigned long *reg;
-        if (irq < VGIC_NR_PRIVATE_IRQS) {
-                reg = x->percpu[cpuid].reg_ul;
-        } else {
-                reg =  x->shared.reg_ul;
-                irq -= VGIC_NR_PRIVATE_IRQS;
-        }
-        if (val)
-                set_bit(irq, reg);
-        else
-                clear_bit(irq, reg);
-}
-static unsigned long *vgic_bitmap_get_cpu_map(struct vgic_bitmap *x, int cpuid)
-{
-        if (unlikely(cpuid >= VGIC_MAX_CPUS))
-                return NULL;
-        return x->percpu[cpuid].reg_ul;
-}
-static unsigned long *vgic_bitmap_get_shared_map(struct vgic_bitmap *x)
-{
-        return x->shared.reg_ul;
-}
-static u32 *vgic_bytemap_get_reg(struct vgic_bytemap *x, int cpuid, u32 offset)
-{
-        offset >>= 2;
-        BUG_ON(offset > (VGIC_NR_IRQS / 4));
-        if (offset < 4)
-                return x->percpu[cpuid] + offset;
-        else
-                return x->shared + offset - 8;
-}
-#define VGIC_CFG_LEVEL  0
-#define VGIC_CFG_EDGE   1
-static bool vgic_irq_is_edge(struct kvm_vcpu *vcpu, int irq)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-        int irq_val;
-        irq_val = vgic_bitmap_get_irq_val(&dist->irq_cfg, vcpu->vcpu_id, irq);
-        return irq_val == VGIC_CFG_EDGE;
-}
-static int vgic_irq_is_enabled(struct kvm_vcpu *vcpu, int irq)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-        return vgic_bitmap_get_irq_val(&dist->irq_enabled, vcpu->vcpu_id, irq);
-}
-static int vgic_irq_is_active(struct kvm_vcpu *vcpu, int irq)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-        return vgic_bitmap_get_irq_val(&dist->irq_active, vcpu->vcpu_id, irq);
-}
-static void vgic_irq_set_active(struct kvm_vcpu *vcpu, int irq)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-        vgic_bitmap_set_irq_val(&dist->irq_active, vcpu->vcpu_id, irq, 1);
-}
-static void vgic_irq_clear_active(struct kvm_vcpu *vcpu, int irq)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-        vgic_bitmap_set_irq_val(&dist->irq_active, vcpu->vcpu_id, irq, 0);
-}
-static int vgic_dist_irq_is_pending(struct kvm_vcpu *vcpu, int irq)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-        return vgic_bitmap_get_irq_val(&dist->irq_state, vcpu->vcpu_id, irq);
-}
-static void vgic_dist_irq_set(struct kvm_vcpu *vcpu, int irq)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-        vgic_bitmap_set_irq_val(&dist->irq_state, vcpu->vcpu_id, irq, 1);
-}
-static void vgic_dist_irq_clear(struct kvm_vcpu *vcpu, int irq)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-        vgic_bitmap_set_irq_val(&dist->irq_state, vcpu->vcpu_id, irq, 0);
-}
-static void vgic_cpu_irq_set(struct kvm_vcpu *vcpu, int irq)
-{
-        if (irq < VGIC_NR_PRIVATE_IRQS)
-                set_bit(irq, vcpu->arch.vgic_cpu.pending_percpu);
-        else
-                set_bit(irq - VGIC_NR_PRIVATE_IRQS,
-                        vcpu->arch.vgic_cpu.pending_shared);
-}
-static void vgic_cpu_irq_clear(struct kvm_vcpu *vcpu, int irq)
-{
-        if (irq < VGIC_NR_PRIVATE_IRQS)
-                clear_bit(irq, vcpu->arch.vgic_cpu.pending_percpu);
-        else
-                clear_bit(irq - VGIC_NR_PRIVATE_IRQS,
-                          vcpu->arch.vgic_cpu.pending_shared);
-}
-static u32 mmio_data_read(struct kvm_exit_mmio *mmio, u32 mask)
-{
-        return *((u32 *)mmio->data) & mask;
-}
-static void mmio_data_write(struct kvm_exit_mmio *mmio, u32 mask, u32 value)
-{
-        *((u32 *)mmio->data) = value & mask;
-}
-/**
- * vgic_reg_access - access vgic register
- * @mmio:   pointer to the data describing the mmio access
- * @reg:    pointer to the virtual backing of vgic distributor data
- * @offset: least significant 2 bits used for word offset
- * @mode:   ACCESS_ mode (see defines above)
- *
- * Helper to make vgic register access easier using one of the access
- * modes defined for vgic register access
- * (read,raz,write-ignored,setbit,clearbit,write)
- */
-static void vgic_reg_access(struct kvm_exit_mmio *mmio, u32 *reg,
-                            phys_addr_t offset, int mode)
-{
-        int word_offset = (offset & 3) * 8;
-        u32 mask = (1UL << (mmio->len * 8)) - 1;
-        u32 regval;
-        /*
-         * Any alignment fault should have been delivered to the guest
-         * directly (ARM ARM B3.12.7 "Prioritization of aborts").
-         */
-        if (reg) {
-                regval = *reg;
-        } else {
-                BUG_ON(mode != (ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED));
-                regval = 0;
-        }
-        if (mmio->is_write) {
-                u32 data = mmio_data_read(mmio, mask) << word_offset;
-                switch (ACCESS_WRITE_MASK(mode)) {
-                case ACCESS_WRITE_IGNORED:
-                        return;
-                case ACCESS_WRITE_SETBIT:
-                        regval |= data;
-                        break;
-                case ACCESS_WRITE_CLEARBIT:
-                        regval &= ~data;
-                        break;
-                case ACCESS_WRITE_VALUE:
-                        regval = (regval & ~(mask << word_offset)) | data;
-                        break;
-                }
-                *reg = regval;
-        } else {
-                switch (ACCESS_READ_MASK(mode)) {
-                case ACCESS_READ_RAZ:
-                        regval = 0;
-                        /* fall through */
-                case ACCESS_READ_VALUE:
-                        mmio_data_write(mmio, mask, regval >> word_offset);
-                }
-        }
-}
-static bool handle_mmio_misc(struct kvm_vcpu *vcpu,
-                             struct kvm_exit_mmio *mmio, phys_addr_t offset)
-{
-        u32 reg;
-        u32 word_offset = offset & 3;
-        switch (offset & ~3) {
-        case 0:                 /* CTLR */
-                reg = vcpu->kvm->arch.vgic.enabled;
-                vgic_reg_access(mmio, &reg, word_offset,
-                                ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
-                if (mmio->is_write) {
-                        vcpu->kvm->arch.vgic.enabled = reg & 1;
-                        vgic_update_state(vcpu->kvm);
-                        return true;
-                }
-                break;
-        case 4:                 /* TYPER */
-                reg  = (atomic_read(&vcpu->kvm->online_vcpus) - 1) << 5;
-                reg |= (VGIC_NR_IRQS >> 5) - 1;
-                vgic_reg_access(mmio, &reg, word_offset,
-                                ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
-                break;
-        case 8:                 /* IIDR */
-                reg = 0x4B00043B;
-                vgic_reg_access(mmio, &reg, word_offset,
-                                ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
-                break;
-        }
-        return false;
-}
-static bool handle_mmio_raz_wi(struct kvm_vcpu *vcpu,
-                               struct kvm_exit_mmio *mmio, phys_addr_t offset)
-{
-        vgic_reg_access(mmio, NULL, offset,
-                        ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED);
-        return false;
-}
-static bool handle_mmio_set_enable_reg(struct kvm_vcpu *vcpu,
-                                       struct kvm_exit_mmio *mmio,
-                                       phys_addr_t offset)
-{
-        u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_enabled,
-                                       vcpu->vcpu_id, offset);
-        vgic_reg_access(mmio, reg, offset,
-                        ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT);
-        if (mmio->is_write) {
-                vgic_update_state(vcpu->kvm);
-                return true;
-        }
-        return false;
-}
-static bool handle_mmio_clear_enable_reg(struct kvm_vcpu *vcpu,
-                                         struct kvm_exit_mmio *mmio,
-                                         phys_addr_t offset)
-{
-        u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_enabled,
-                                       vcpu->vcpu_id, offset);
-        vgic_reg_access(mmio, reg, offset,
-                        ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT);
-        if (mmio->is_write) {
-                if (offset < 4) /* Force SGI enabled */
-                        *reg |= 0xffff;
-                vgic_retire_disabled_irqs(vcpu);
-                vgic_update_state(vcpu->kvm);
-                return true;
-        }
-        return false;
-}
-static bool handle_mmio_set_pending_reg(struct kvm_vcpu *vcpu,
-                                        struct kvm_exit_mmio *mmio,
-                                        phys_addr_t offset)
-{
-        u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_state,
-                                       vcpu->vcpu_id, offset);
-        vgic_reg_access(mmio, reg, offset,
-                        ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT);
-        if (mmio->is_write) {
-                vgic_update_state(vcpu->kvm);
-                return true;
-        }
-        return false;
-}
-static bool handle_mmio_clear_pending_reg(struct kvm_vcpu *vcpu,
-                                          struct kvm_exit_mmio *mmio,
-                                          phys_addr_t offset)
-{
-        u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_state,
-                                       vcpu->vcpu_id, offset);
-        vgic_reg_access(mmio, reg, offset,
-                        ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT);
-        if (mmio->is_write) {
-                vgic_update_state(vcpu->kvm);
-                return true;
-        }
-        return false;
-}
-static bool handle_mmio_priority_reg(struct kvm_vcpu *vcpu,
-                                     struct kvm_exit_mmio *mmio,
-                                     phys_addr_t offset)
-{
-        u32 *reg = vgic_bytemap_get_reg(&vcpu->kvm->arch.vgic.irq_priority,
-                                        vcpu->vcpu_id, offset);
-        vgic_reg_access(mmio, reg, offset,
-                        ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
-        return false;
-}
-#define GICD_ITARGETSR_SIZE     32
-#define GICD_CPUTARGETS_BITS    8
-#define GICD_IRQS_PER_ITARGETSR (GICD_ITARGETSR_SIZE / GICD_CPUTARGETS_BITS)
-static u32 vgic_get_target_reg(struct kvm *kvm, int irq)
-{
-        struct vgic_dist *dist = &kvm->arch.vgic;
-        struct kvm_vcpu *vcpu;
-        int i, c;
-        unsigned long *bmap;
-        u32 val = 0;
-        irq -= VGIC_NR_PRIVATE_IRQS;
-        kvm_for_each_vcpu(c, vcpu, kvm) {
-                bmap = vgic_bitmap_get_shared_map(&dist->irq_spi_target[c]);
-                for (i = 0; i < GICD_IRQS_PER_ITARGETSR; i++)
-                        if (test_bit(irq + i, bmap))
-                                val |= 1 << (c + i * 8);
-        }
-        return val;
-}
-static void vgic_set_target_reg(struct kvm *kvm, u32 val, int irq)
-{
-        struct vgic_dist *dist = &kvm->arch.vgic;
-        struct kvm_vcpu *vcpu;
-        int i, c;
-        unsigned long *bmap;
-        u32 target;
-        irq -= VGIC_NR_PRIVATE_IRQS;
-        /*
-         * Pick the LSB in each byte. This ensures we target exactly
-         * one vcpu per IRQ. If the byte is null, assume we target
-         * CPU0.
-         */
-        for (i = 0; i < GICD_IRQS_PER_ITARGETSR; i++) {
-                int shift = i * GICD_CPUTARGETS_BITS;
-                target = ffs((val >> shift) & 0xffU);
-                target = target ? (target - 1) : 0;
-                dist->irq_spi_cpu[irq + i] = target;
-                kvm_for_each_vcpu(c, vcpu, kvm) {
-                        bmap = vgic_bitmap_get_shared_map(&dist->irq_spi_target[c]);
-                        if (c == target)
-                                set_bit(irq + i, bmap);
-                        else
-                                clear_bit(irq + i, bmap);
-                }
-        }
-}
-static bool handle_mmio_target_reg(struct kvm_vcpu *vcpu,
-                                   struct kvm_exit_mmio *mmio,
-                                   phys_addr_t offset)
-{
-        u32 reg;
-        /* We treat the banked interrupts targets as read-only */
-        if (offset < 32) {
-                u32 roreg = 1 << vcpu->vcpu_id;
-                roreg |= roreg << 8;
-                roreg |= roreg << 16;
-                vgic_reg_access(mmio, &roreg, offset,
-                                ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
-                return false;
-        }
-        reg = vgic_get_target_reg(vcpu->kvm, offset & ~3U);
-        vgic_reg_access(mmio, &reg, offset,
-                        ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
-        if (mmio->is_write) {
-                vgic_set_target_reg(vcpu->kvm, reg, offset & ~3U);
-                vgic_update_state(vcpu->kvm);
-                return true;
-        }
-        return false;
-}
-static u32 vgic_cfg_expand(u16 val)
-{
-        u32 res = 0;
-        int i;
-        /*
-         * Turn a 16bit value like abcd...mnop into a 32bit word
-         * a0b0c0d0...m0n0o0p0, which is what the HW cfg register is.
-         */
-        for (i = 0; i < 16; i++)
-                res |= ((val >> i) & VGIC_CFG_EDGE) << (2 * i + 1);
-        return res;
-}
-static u16 vgic_cfg_compress(u32 val)
-{
-        u16 res = 0;
-        int i;
-        /*
-         * Turn a 32bit word a0b0c0d0...m0n0o0p0 into 16bit value like
-         * abcd...mnop which is what we really care about.
-         */
-        for (i = 0; i < 16; i++)
-                res |= ((val >> (i * 2 + 1)) & VGIC_CFG_EDGE) << i;
-        return res;
-}
-/*
- * The distributor uses 2 bits per IRQ for the CFG register, but the
- * LSB is always 0. As such, we only keep the upper bit, and use the
- * two above functions to compress/expand the bits
- */
-static bool handle_mmio_cfg_reg(struct kvm_vcpu *vcpu,
-                                struct kvm_exit_mmio *mmio, phys_addr_t offset)
-{
-        u32 val;
-        u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_cfg,
-                                       vcpu->vcpu_id, offset >> 1);
-        if (offset & 2)
-                val = *reg >> 16;
-        else
-                val = *reg & 0xffff;
-        val = vgic_cfg_expand(val);
-        vgic_reg_access(mmio, &val, offset,
-                        ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
-        if (mmio->is_write) {
-                if (offset < 4) {
-                        *reg = ~0U; /* Force PPIs/SGIs to 1 */
-                        return false;
-                }
-                val = vgic_cfg_compress(val);
-                if (offset & 2) {
-                        *reg &= 0xffff;
-                        *reg |= val << 16;
-                } else {
-                        *reg &= 0xffff << 16;
-                        *reg |= val;
-                }
-        }
-        return false;
-}
-static bool handle_mmio_sgi_reg(struct kvm_vcpu *vcpu,
-                                struct kvm_exit_mmio *mmio, phys_addr_t offset)
-{
-        u32 reg;
-        vgic_reg_access(mmio, &reg, offset,
-                        ACCESS_READ_RAZ | ACCESS_WRITE_VALUE);
-        if (mmio->is_write) {
-                vgic_dispatch_sgi(vcpu, reg);
-                vgic_update_state(vcpu->kvm);
-                return true;
-        }
-        return false;
-}
-/*
- * I would have liked to use the kvm_bus_io_*() API instead, but it
- * cannot cope with banked registers (only the VM pointer is passed
- * around, and we need the vcpu). One of these days, someone please
- * fix it!
- */
-struct mmio_range {
-        phys_addr_t base;
-        unsigned long len;
-        bool (*handle_mmio)(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio,
-                            phys_addr_t offset);
-};
-static const struct mmio_range vgic_ranges[] = {
-        {
-                .base           = GIC_DIST_CTRL,
-                .len            = 12,
-                .handle_mmio    = handle_mmio_misc,
-        },
-        {
-                .base           = GIC_DIST_IGROUP,
-                .len            = VGIC_NR_IRQS / 8,
-                .handle_mmio    = handle_mmio_raz_wi,
-        },
-        {
-                .base           = GIC_DIST_ENABLE_SET,
-                .len            = VGIC_NR_IRQS / 8,
-                .handle_mmio    = handle_mmio_set_enable_reg,
-        },
-        {
-                .base           = GIC_DIST_ENABLE_CLEAR,
-                .len            = VGIC_NR_IRQS / 8,
-                .handle_mmio    = handle_mmio_clear_enable_reg,
-        },
-        {
-                .base           = GIC_DIST_PENDING_SET,
-                .len            = VGIC_NR_IRQS / 8,
-                .handle_mmio    = handle_mmio_set_pending_reg,
-        },
-        {
-                .base           = GIC_DIST_PENDING_CLEAR,
-                .len            = VGIC_NR_IRQS / 8,
-                .handle_mmio    = handle_mmio_clear_pending_reg,
-        },
-        {
-                .base           = GIC_DIST_ACTIVE_SET,
-                .len            = VGIC_NR_IRQS / 8,
-                .handle_mmio    = handle_mmio_raz_wi,
-        },
-        {
-                .base           = GIC_DIST_ACTIVE_CLEAR,
-                .len            = VGIC_NR_IRQS / 8,
-                .handle_mmio    = handle_mmio_raz_wi,
-        },
-        {
-                .base           = GIC_DIST_PRI,
-                .len            = VGIC_NR_IRQS,
-                .handle_mmio    = handle_mmio_priority_reg,
-        },
-        {
-                .base           = GIC_DIST_TARGET,
-                .len            = VGIC_NR_IRQS,
-                .handle_mmio    = handle_mmio_target_reg,
-        },
-        {
-                .base           = GIC_DIST_CONFIG,
-                .len            = VGIC_NR_IRQS / 4,
-                .handle_mmio    = handle_mmio_cfg_reg,
-        },
-        {
-                .base           = GIC_DIST_SOFTINT,
-                .len            = 4,
-                .handle_mmio    = handle_mmio_sgi_reg,
-        },
-        {}
-};
-static const
-struct mmio_range *find_matching_range(const struct mmio_range *ranges,
-                                       struct kvm_exit_mmio *mmio,
-                                       phys_addr_t base)
-{
-        const struct mmio_range *r = ranges;
-        phys_addr_t addr = mmio->phys_addr - base;
-        while (r->len) {
-                if (addr >= r->base &&
-                    (addr + mmio->len) <= (r->base + r->len))
-                        return r;
-                r++;
-        }
-        return NULL;
-}
-/**
- * vgic_handle_mmio - handle an in-kernel MMIO access
- * @vcpu:       pointer to the vcpu performing the access
- * @run:        pointer to the kvm_run structure
- * @mmio:       pointer to the data describing the access
- *
- * returns true if the MMIO access has been performed in kernel space,
- * and false if it needs to be emulated in user space.
- */
-bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
-                      struct kvm_exit_mmio *mmio)
-{
-        const struct mmio_range *range;
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-        unsigned long base = dist->vgic_dist_base;
-        bool updated_state;
-        unsigned long offset;
-        if (!irqchip_in_kernel(vcpu->kvm) ||
-            mmio->phys_addr < base ||
-            (mmio->phys_addr + mmio->len) > (base + KVM_VGIC_V2_DIST_SIZE))
-                return false;
-        /* We don't support ldrd / strd or ldm / stm to the emulated vgic */
-        if (mmio->len > 4) {
-                kvm_inject_dabt(vcpu, mmio->phys_addr);
-                return true;
-        }
-        range = find_matching_range(vgic_ranges, mmio, base);
-        if (unlikely(!range || !range->handle_mmio)) {
-                pr_warn("Unhandled access %d %08llx %d\n",
-                        mmio->is_write, mmio->phys_addr, mmio->len);
-                return false;
-        }
-        spin_lock(&vcpu->kvm->arch.vgic.lock);
-        offset = mmio->phys_addr - range->base - base;
-        updated_state = range->handle_mmio(vcpu, mmio, offset);
-        spin_unlock(&vcpu->kvm->arch.vgic.lock);
-        kvm_prepare_mmio(run, mmio);
-        kvm_handle_mmio_return(vcpu, run);
-        if (updated_state)
-                vgic_kick_vcpus(vcpu->kvm);
-        return true;
-}
-static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg)
-{
-        struct kvm *kvm = vcpu->kvm;
-        struct vgic_dist *dist = &kvm->arch.vgic;
-        int nrcpus = atomic_read(&kvm->online_vcpus);
-        u8 target_cpus;
-        int sgi, mode, c, vcpu_id;
-        vcpu_id = vcpu->vcpu_id;
-        sgi = reg & 0xf;
-        target_cpus = (reg >> 16) & 0xff;
-        mode = (reg >> 24) & 3;
-        switch (mode) {
-        case 0:
-                if (!target_cpus)
-                        return;
-        case 1:
-                target_cpus = ((1 << nrcpus) - 1) & ~(1 << vcpu_id) & 0xff;
-                break;
-        case 2:
-                target_cpus = 1 << vcpu_id;
-                break;
-        }
-        kvm_for_each_vcpu(c, vcpu, kvm) {
-                if (target_cpus & 1) {
-                        /* Flag the SGI as pending */
-                        vgic_dist_irq_set(vcpu, sgi);
-                        dist->irq_sgi_sources[c][sgi] |= 1 << vcpu_id;
-                        kvm_debug("SGI%d from CPU%d to CPU%d\n", sgi, vcpu_id, c);
-                }
-                target_cpus >>= 1;
-        }
-}
-static int compute_pending_for_cpu(struct kvm_vcpu *vcpu)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-        unsigned long *pending, *enabled, *pend_percpu, *pend_shared;
-        unsigned long pending_private, pending_shared;
-        int vcpu_id;
-        vcpu_id = vcpu->vcpu_id;
-        pend_percpu = vcpu->arch.vgic_cpu.pending_percpu;
-        pend_shared = vcpu->arch.vgic_cpu.pending_shared;
-        pending = vgic_bitmap_get_cpu_map(&dist->irq_state, vcpu_id);
-        enabled = vgic_bitmap_get_cpu_map(&dist->irq_enabled, vcpu_id);
-        bitmap_and(pend_percpu, pending, enabled, VGIC_NR_PRIVATE_IRQS);
-        pending = vgic_bitmap_get_shared_map(&dist->irq_state);
-        enabled = vgic_bitmap_get_shared_map(&dist->irq_enabled);
-        bitmap_and(pend_shared, pending, enabled, VGIC_NR_SHARED_IRQS);
-        bitmap_and(pend_shared, pend_shared,
-                   vgic_bitmap_get_shared_map(&dist->irq_spi_target[vcpu_id]),
-                   VGIC_NR_SHARED_IRQS);
-        pending_private = find_first_bit(pend_percpu, VGIC_NR_PRIVATE_IRQS);
-        pending_shared = find_first_bit(pend_shared, VGIC_NR_SHARED_IRQS);
-        return (pending_private < VGIC_NR_PRIVATE_IRQS ||
-                pending_shared < VGIC_NR_SHARED_IRQS);
-}
-/*
- * Update the interrupt state and determine which CPUs have pending
- * interrupts. Must be called with distributor lock held.
- */
-static void vgic_update_state(struct kvm *kvm)
-{
-        struct vgic_dist *dist = &kvm->arch.vgic;
-        struct kvm_vcpu *vcpu;
-        int c;
-        if (!dist->enabled) {
-                set_bit(0, &dist->irq_pending_on_cpu);
-                return;
-        }
-        kvm_for_each_vcpu(c, vcpu, kvm) {
-                if (compute_pending_for_cpu(vcpu)) {
-                        pr_debug("CPU%d has pending interrupts\n", c);
-                        set_bit(c, &dist->irq_pending_on_cpu);
-                }
-        }
-}
-#define LR_CPUID(lr)    \
-        (((lr) & GICH_LR_PHYSID_CPUID) >> GICH_LR_PHYSID_CPUID_SHIFT)
-#define MK_LR_PEND(src, irq)    \
-        (GICH_LR_PENDING_BIT | ((src) << GICH_LR_PHYSID_CPUID_SHIFT) | (irq))
-/*
- * An interrupt may have been disabled after being made pending on the
- * CPU interface (the classic case is a timer running while we're
- * rebooting the guest - the interrupt would kick as soon as the CPU
- * interface gets enabled, with deadly consequences).
- *
- * The solution is to examine already active LRs, and check the
- * interrupt is still enabled. If not, just retire it.
- */
-static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu)
-{
-        struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
-        int lr;
-        for_each_set_bit(lr, vgic_cpu->lr_used, vgic_cpu->nr_lr) {
-                int irq = vgic_cpu->vgic_lr[lr] & GICH_LR_VIRTUALID;
-                if (!vgic_irq_is_enabled(vcpu, irq)) {
-                        vgic_cpu->vgic_irq_lr_map[irq] = LR_EMPTY;
-                        clear_bit(lr, vgic_cpu->lr_used);
-                        vgic_cpu->vgic_lr[lr] &= ~GICH_LR_STATE;
-                        if (vgic_irq_is_active(vcpu, irq))
-                                vgic_irq_clear_active(vcpu, irq);
-                }
-        }
-}
-/*
- * Queue an interrupt to a CPU virtual interface. Return true on success,
- * or false if it wasn't possible to queue it.
- */
-static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq)
-{
-        struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
-        int lr;
-        /* Sanitize the input... */
-        BUG_ON(sgi_source_id & ~7);
-        BUG_ON(sgi_source_id && irq >= VGIC_NR_SGIS);
-        BUG_ON(irq >= VGIC_NR_IRQS);
-        kvm_debug("Queue IRQ%d\n", irq);
-        lr = vgic_cpu->vgic_irq_lr_map[irq];
-        /* Do we have an active interrupt for the same CPUID? */
-        if (lr != LR_EMPTY &&
-            (LR_CPUID(vgic_cpu->vgic_lr[lr]) == sgi_source_id)) {
-                kvm_debug("LR%d piggyback for IRQ%d %x\n",
-                          lr, irq, vgic_cpu->vgic_lr[lr]);
-                BUG_ON(!test_bit(lr, vgic_cpu->lr_used));
-                vgic_cpu->vgic_lr[lr] |= GICH_LR_PENDING_BIT;
-                return true;
-        }
-        /* Try to use another LR for this interrupt */
-        lr = find_first_zero_bit((unsigned long *)vgic_cpu->lr_used,
-                               vgic_cpu->nr_lr);
-        if (lr >= vgic_cpu->nr_lr)
-                return false;
-        kvm_debug("LR%d allocated for IRQ%d %x\n", lr, irq, sgi_source_id);
-        vgic_cpu->vgic_lr[lr] = MK_LR_PEND(sgi_source_id, irq);
-        vgic_cpu->vgic_irq_lr_map[irq] = lr;
-        set_bit(lr, vgic_cpu->lr_used);
-        if (!vgic_irq_is_edge(vcpu, irq))
-                vgic_cpu->vgic_lr[lr] |= GICH_LR_EOI;
-        return true;
-}
-static bool vgic_queue_sgi(struct kvm_vcpu *vcpu, int irq)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-        unsigned long sources;
-        int vcpu_id = vcpu->vcpu_id;
-        int c;
-        sources = dist->irq_sgi_sources[vcpu_id][irq];
-        for_each_set_bit(c, &sources, VGIC_MAX_CPUS) {
-                if (vgic_queue_irq(vcpu, c, irq))
-                        clear_bit(c, &sources);
-        }
-        dist->irq_sgi_sources[vcpu_id][irq] = sources;
-        /*
-         * If the sources bitmap has been cleared it means that we
-         * could queue all the SGIs onto link registers (see the
-         * clear_bit above), and therefore we are done with them in
-         * our emulated gic and can get rid of them.
-         */
-        if (!sources) {
-                vgic_dist_irq_clear(vcpu, irq);
-                vgic_cpu_irq_clear(vcpu, irq);
-                return true;
-        }
-        return false;
-}
-static bool vgic_queue_hwirq(struct kvm_vcpu *vcpu, int irq)
-{
-        if (vgic_irq_is_active(vcpu, irq))
-                return true; /* level interrupt, already queued */
-        if (vgic_queue_irq(vcpu, 0, irq)) {
-                if (vgic_irq_is_edge(vcpu, irq)) {
-                        vgic_dist_irq_clear(vcpu, irq);
-                        vgic_cpu_irq_clear(vcpu, irq);
-                } else {
-                        vgic_irq_set_active(vcpu, irq);
-                }
-                return true;
-        }
-        return false;
-}
-/*
- * Fill the list registers with pending interrupts before running the
- * guest.
- */
-static void __kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
-{
-        struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-        int i, vcpu_id;
-        int overflow = 0;
-        vcpu_id = vcpu->vcpu_id;
-        /*
-         * We may not have any pending interrupt, or the interrupts
-         * may have been serviced from another vcpu. In all cases,
-         * move along.
-         */
-        if (!kvm_vgic_vcpu_pending_irq(vcpu)) {
-                pr_debug("CPU%d has no pending interrupt\n", vcpu_id);
-                goto epilog;
-        }
-        /* SGIs */
-        for_each_set_bit(i, vgic_cpu->pending_percpu, VGIC_NR_SGIS) {
-                if (!vgic_queue_sgi(vcpu, i))
-                        overflow = 1;
-        }
-        /* PPIs */
-        for_each_set_bit_from(i, vgic_cpu->pending_percpu, VGIC_NR_PRIVATE_IRQS) {
-                if (!vgic_queue_hwirq(vcpu, i))
-                        overflow = 1;
-        }
-        /* SPIs */
-        for_each_set_bit(i, vgic_cpu->pending_shared, VGIC_NR_SHARED_IRQS) {
-                if (!vgic_queue_hwirq(vcpu, i + VGIC_NR_PRIVATE_IRQS))
-                        overflow = 1;
-        }
-epilog:
-        if (overflow) {
-                vgic_cpu->vgic_hcr |= GICH_HCR_UIE;
-        } else {
-                vgic_cpu->vgic_hcr &= ~GICH_HCR_UIE;
-                /*
-                 * We're about to run this VCPU, and we've consumed
-                 * everything the distributor had in store for
-                 * us. Claim we don't have anything pending. We'll
-                 * adjust that if needed while exiting.
-                 */
-                clear_bit(vcpu_id, &dist->irq_pending_on_cpu);
-        }
-}
-static bool vgic_process_maintenance(struct kvm_vcpu *vcpu)
-{
-        struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
-        bool level_pending = false;
-        kvm_debug("MISR = %08x\n", vgic_cpu->vgic_misr);
-        if (vgic_cpu->vgic_misr & GICH_MISR_EOI) {
-                /*
-                 * Some level interrupts have been EOIed. Clear their
-                 * active bit.
-                 */
-                int lr, irq;
-                for_each_set_bit(lr, (unsigned long *)vgic_cpu->vgic_eisr,
-                                 vgic_cpu->nr_lr) {
-                        irq = vgic_cpu->vgic_lr[lr] & GICH_LR_VIRTUALID;
-                        vgic_irq_clear_active(vcpu, irq);
-                        vgic_cpu->vgic_lr[lr] &= ~GICH_LR_EOI;
-                        /* Any additional pending interrupt? */
-                        if (vgic_dist_irq_is_pending(vcpu, irq)) {
-                                vgic_cpu_irq_set(vcpu, irq);
-                                level_pending = true;
-                        } else {
-                                vgic_cpu_irq_clear(vcpu, irq);
-                        }
-                        /*
-                         * Despite being EOIed, the LR may not have
-                         * been marked as empty.
-                         */
-                        set_bit(lr, (unsigned long *)vgic_cpu->vgic_elrsr);
-                        vgic_cpu->vgic_lr[lr] &= ~GICH_LR_ACTIVE_BIT;
-                }
-        }
-        if (vgic_cpu->vgic_misr & GICH_MISR_U)
-                vgic_cpu->vgic_hcr &= ~GICH_HCR_UIE;
-        return level_pending;
-}
-/*
- * Sync back the VGIC state after a guest run. The distributor lock is
- * needed so we don't get preempted in the middle of the state processing.
- */
-static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
-{
-        struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-        int lr, pending;
-        bool level_pending;
-        level_pending = vgic_process_maintenance(vcpu);
-        /* Clear mappings for empty LRs */
-        for_each_set_bit(lr, (unsigned long *)vgic_cpu->vgic_elrsr,
-                         vgic_cpu->nr_lr) {
-                int irq;
-                if (!test_and_clear_bit(lr, vgic_cpu->lr_used))
-                        continue;
-                irq = vgic_cpu->vgic_lr[lr] & GICH_LR_VIRTUALID;
-                BUG_ON(irq >= VGIC_NR_IRQS);
-                vgic_cpu->vgic_irq_lr_map[irq] = LR_EMPTY;
-        }
-        /* Check if we still have something up our sleeve... */
-        pending = find_first_zero_bit((unsigned long *)vgic_cpu->vgic_elrsr,
-                                      vgic_cpu->nr_lr);
-        if (level_pending || pending < vgic_cpu->nr_lr)
-                set_bit(vcpu->vcpu_id, &dist->irq_pending_on_cpu);
-}
-void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-        if (!irqchip_in_kernel(vcpu->kvm))
-                return;
-        spin_lock(&dist->lock);
-        __kvm_vgic_flush_hwstate(vcpu);
-        spin_unlock(&dist->lock);
-}
-void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-        if (!irqchip_in_kernel(vcpu->kvm))
-                return;
-        spin_lock(&dist->lock);
-        __kvm_vgic_sync_hwstate(vcpu);
-        spin_unlock(&dist->lock);
-}
-int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-        if (!irqchip_in_kernel(vcpu->kvm))
-                return 0;
-        return test_bit(vcpu->vcpu_id, &dist->irq_pending_on_cpu);
-}
-static void vgic_kick_vcpus(struct kvm *kvm)
-{
-        struct kvm_vcpu *vcpu;
-        int c;
-        /*
-         * We've injected an interrupt, time to find out who deserves
-         * a good kick...
-         */
-        kvm_for_each_vcpu(c, vcpu, kvm) {
-                if (kvm_vgic_vcpu_pending_irq(vcpu))
-                        kvm_vcpu_kick(vcpu);
-        }
-}
-static int vgic_validate_injection(struct kvm_vcpu *vcpu, int irq, int level)
-{
-        int is_edge = vgic_irq_is_edge(vcpu, irq);
-        int state = vgic_dist_irq_is_pending(vcpu, irq);
-        /*
-         * Only inject an interrupt if:
-         * - edge triggered and we have a rising edge
-         * - level triggered and we change level
-         */
-        if (is_edge)
-                return level > state;
-        else
-                return level != state;
-}
-static bool vgic_update_irq_state(struct kvm *kvm, int cpuid,
-                                  unsigned int irq_num, bool level)
-{
-        struct vgic_dist *dist = &kvm->arch.vgic;
-        struct kvm_vcpu *vcpu;
-        int is_edge, is_level;
-        int enabled;
-        bool ret = true;
-        spin_lock(&dist->lock);
-        vcpu = kvm_get_vcpu(kvm, cpuid);
-        is_edge = vgic_irq_is_edge(vcpu, irq_num);
-        is_level = !is_edge;
-        if (!vgic_validate_injection(vcpu, irq_num, level)) {
-                ret = false;
-                goto out;
-        }
-        if (irq_num >= VGIC_NR_PRIVATE_IRQS) {
-                cpuid = dist->irq_spi_cpu[irq_num - VGIC_NR_PRIVATE_IRQS];
-                vcpu = kvm_get_vcpu(kvm, cpuid);
-        }
-        kvm_debug("Inject IRQ%d level %d CPU%d\n", irq_num, level, cpuid);
-        if (level)
-                vgic_dist_irq_set(vcpu, irq_num);
-        else
-                vgic_dist_irq_clear(vcpu, irq_num);
-        enabled = vgic_irq_is_enabled(vcpu, irq_num);
-        if (!enabled) {
-                ret = false;
-                goto out;
-        }
-        if (is_level && vgic_irq_is_active(vcpu, irq_num)) {
-                /*
-                 * Level interrupt in progress, will be picked up
-                 * when EOId.
-                 */
-                ret = false;
-                goto out;
-        }
-        if (level) {
-                vgic_cpu_irq_set(vcpu, irq_num);
-                set_bit(cpuid, &dist->irq_pending_on_cpu);
-        }
-out:
-        spin_unlock(&dist->lock);
-        return ret;
-}
-/**
- * kvm_vgic_inject_irq - Inject an IRQ from a device to the vgic
- * @kvm:     The VM structure pointer
- * @cpuid:   The CPU for PPIs
- * @irq_num: The IRQ number that is assigned to the device
- * @level:   Edge-triggered:  true:  to trigger the interrupt
- *                            false: to ignore the call
- *           Level-sensitive  true:  activates an interrupt
- *                            false: deactivates an interrupt
- *
- * The GIC is not concerned with devices being active-LOW or active-HIGH for
- * level-sensitive interrupts.  You can think of the level parameter as 1
- * being HIGH and 0 being LOW and all devices being active-HIGH.
- */
-int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
-                        bool level)
-{
-        if (vgic_update_irq_state(kvm, cpuid, irq_num, level))
-                vgic_kick_vcpus(kvm);
-        return 0;
-}
-static irqreturn_t vgic_maintenance_handler(int irq, void *data)
-{
-        /*
-         * We cannot rely on the vgic maintenance interrupt to be
-         * delivered synchronously. This means we can only use it to
-         * exit the VM, and we perform the handling of EOIed
-         * interrupts on the exit path (see vgic_process_maintenance).
-         */
-        return IRQ_HANDLED;
-}
-int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
-{
-        struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-        int i;
-        if (!irqchip_in_kernel(vcpu->kvm))
-                return 0;
-        if (vcpu->vcpu_id >= VGIC_MAX_CPUS)
-                return -EBUSY;
-        for (i = 0; i < VGIC_NR_IRQS; i++) {
-                if (i < VGIC_NR_PPIS)
-                        vgic_bitmap_set_irq_val(&dist->irq_enabled,
-                                                vcpu->vcpu_id, i, 1);
-                if (i < VGIC_NR_PRIVATE_IRQS)
-                        vgic_bitmap_set_irq_val(&dist->irq_cfg,
-                                                vcpu->vcpu_id, i, VGIC_CFG_EDGE);
-                vgic_cpu->vgic_irq_lr_map[i] = LR_EMPTY;
-        }
-        /*
-         * By forcing VMCR to zero, the GIC will restore the binary
-         * points to their reset values. Anything else resets to zero
-         * anyway.
-         */
-        vgic_cpu->vgic_vmcr = 0;
-        vgic_cpu->nr_lr = vgic_nr_lr;
-        vgic_cpu->vgic_hcr = GICH_HCR_EN; /* Get the show on the road... */
-        return 0;
-}
-static void vgic_init_maintenance_interrupt(void *info)
-{
-        enable_percpu_irq(vgic_maint_irq, 0);
-}
-static int vgic_cpu_notify(struct notifier_block *self,
-                           unsigned long action, void *cpu)
-{
-        switch (action) {
-        case CPU_STARTING:
-        case CPU_STARTING_FROZEN:
-                vgic_init_maintenance_interrupt(NULL);
-                break;
-        case CPU_DYING:
-        case CPU_DYING_FROZEN:
-                disable_percpu_irq(vgic_maint_irq);
-                break;
-        }
-        return NOTIFY_OK;
-}
-static struct notifier_block vgic_cpu_nb = {
-        .notifier_call = vgic_cpu_notify,
-};
-int kvm_vgic_hyp_init(void)
-{
-        int ret;
-        struct resource vctrl_res;
-        struct resource vcpu_res;
-        vgic_node = of_find_compatible_node(NULL, NULL, "arm,cortex-a15-gic");
-        if (!vgic_node) {
-                kvm_err("error: no compatible vgic node in DT\n");
-                return -ENODEV;
-        }
-        vgic_maint_irq = irq_of_parse_and_map(vgic_node, 0);
-        if (!vgic_maint_irq) {
-                kvm_err("error getting vgic maintenance irq from DT\n");
-                ret = -ENXIO;
-                goto out;
-        }
-        ret = request_percpu_irq(vgic_maint_irq, vgic_maintenance_handler,
-                                 "vgic", kvm_get_running_vcpus());
-        if (ret) {
-                kvm_err("Cannot register interrupt %d\n", vgic_maint_irq);
-                goto out;
-        }
-        ret = register_cpu_notifier(&vgic_cpu_nb);
-        if (ret) {
-                kvm_err("Cannot register vgic CPU notifier\n");
-                goto out_free_irq;
-        }
-        ret = of_address_to_resource(vgic_node, 2, &vctrl_res);
-        if (ret) {
-                kvm_err("Cannot obtain VCTRL resource\n");
-                goto out_free_irq;
-        }
-        vgic_vctrl_base = of_iomap(vgic_node, 2);
-        if (!vgic_vctrl_base) {
-                kvm_err("Cannot ioremap VCTRL\n");
-                ret = -ENOMEM;
-                goto out_free_irq;
-        }
-        vgic_nr_lr = readl_relaxed(vgic_vctrl_base + GICH_VTR);
-        vgic_nr_lr = (vgic_nr_lr & 0x3f) + 1;
-        ret = create_hyp_io_mappings(vgic_vctrl_base,
-                                     vgic_vctrl_base + resource_size(&vctrl_res),
-                                     vctrl_res.start);
-        if (ret) {
-                kvm_err("Cannot map VCTRL into hyp\n");
-                goto out_unmap;
-        }
-        kvm_info("%s@%llx IRQ%d\n", vgic_node->name,
-                 vctrl_res.start, vgic_maint_irq);
-        on_each_cpu(vgic_init_maintenance_interrupt, NULL, 1);
-        if (of_address_to_resource(vgic_node, 3, &vcpu_res)) {
-                kvm_err("Cannot obtain VCPU resource\n");
-                ret = -ENXIO;
-                goto out_unmap;
-        }
-        vgic_vcpu_base = vcpu_res.start;
-        goto out;
-out_unmap:
-        iounmap(vgic_vctrl_base);
-out_free_irq:
-        free_percpu_irq(vgic_maint_irq, kvm_get_running_vcpus());
-out:
-        of_node_put(vgic_node);
-        return ret;
-}
-int kvm_vgic_init(struct kvm *kvm)
-{
-        int ret = 0, i;
-        mutex_lock(&kvm->lock);
-        if (vgic_initialized(kvm))
-                goto out;
-        if (IS_VGIC_ADDR_UNDEF(kvm->arch.vgic.vgic_dist_base) ||
-            IS_VGIC_ADDR_UNDEF(kvm->arch.vgic.vgic_cpu_base)) {
-                kvm_err("Need to set vgic cpu and dist addresses first\n");
-                ret = -ENXIO;
-                goto out;
-        }
-        ret = kvm_phys_addr_ioremap(kvm, kvm->arch.vgic.vgic_cpu_base,
-                                    vgic_vcpu_base, KVM_VGIC_V2_CPU_SIZE);
-        if (ret) {
-                kvm_err("Unable to remap VGIC CPU to VCPU\n");
-                goto out;
-        }
-        for (i = VGIC_NR_PRIVATE_IRQS; i < VGIC_NR_IRQS; i += 4)
-                vgic_set_target_reg(kvm, 0, i);
-        kvm_timer_init(kvm);
-        kvm->arch.vgic.ready = true;
-out:
-        mutex_unlock(&kvm->lock);
-        return ret;
-}
-int kvm_vgic_create(struct kvm *kvm)
-{
-        int ret = 0;
-        mutex_lock(&kvm->lock);
-        if (atomic_read(&kvm->online_vcpus) || kvm->arch.vgic.vctrl_base) {
-                ret = -EEXIST;
-                goto out;
-        }
-        spin_lock_init(&kvm->arch.vgic.lock);
-        kvm->arch.vgic.vctrl_base = vgic_vctrl_base;
-        kvm->arch.vgic.vgic_dist_base = VGIC_ADDR_UNDEF;
-        kvm->arch.vgic.vgic_cpu_base = VGIC_ADDR_UNDEF;
-out:
-        mutex_unlock(&kvm->lock);
-        return ret;
-}
-static bool vgic_ioaddr_overlap(struct kvm *kvm)
-{
-        phys_addr_t dist = kvm->arch.vgic.vgic_dist_base;
-        phys_addr_t cpu = kvm->arch.vgic.vgic_cpu_base;
-        if (IS_VGIC_ADDR_UNDEF(dist) || IS_VGIC_ADDR_UNDEF(cpu))
-                return 0;
-        if ((dist <= cpu && dist + KVM_VGIC_V2_DIST_SIZE > cpu) ||
-            (cpu <= dist && cpu + KVM_VGIC_V2_CPU_SIZE > dist))
-                return -EBUSY;
-        return 0;
-}
-static int vgic_ioaddr_assign(struct kvm *kvm, phys_addr_t *ioaddr,
-                              phys_addr_t addr, phys_addr_t size)
-{
-        int ret;
-        if (!IS_VGIC_ADDR_UNDEF(*ioaddr))
-                return -EEXIST;
-        if (addr + size < addr)
-                return -EINVAL;
-        ret = vgic_ioaddr_overlap(kvm);
-        if (ret)
-                return ret;
-        *ioaddr = addr;
-        return ret;
-}
-int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr)
-{
-        int r = 0;
-        struct vgic_dist *vgic = &kvm->arch.vgic;
-        if (addr & ~KVM_PHYS_MASK)
-                return -E2BIG;
-        if (addr & (SZ_4K - 1))
-                return -EINVAL;
-        mutex_lock(&kvm->lock);
-        switch (type) {
-        case KVM_VGIC_V2_ADDR_TYPE_DIST:
-                r = vgic_ioaddr_assign(kvm, &vgic->vgic_dist_base,
-                                       addr, KVM_VGIC_V2_DIST_SIZE);
-                break;
-        case KVM_VGIC_V2_ADDR_TYPE_CPU:
-                r = vgic_ioaddr_assign(kvm, &vgic->vgic_cpu_base,
-                                       addr, KVM_VGIC_V2_CPU_SIZE);
-                break;
-        default:
-                r = -ENODEV;
-        }
-        mutex_unlock(&kvm->lock);
-        return r;
-}
diff --git a/arch/arm/lib/delay.c b/arch/arm/lib/delay.c
index 64dbfa57204a..5306de350133 100644
--- a/arch/arm/lib/delay.c
+++ b/arch/arm/lib/delay.c
@@ -86,7 +86,7 @@ void __init register_current_timer_delay(const struct delay_timer *timer)
        }
 }
-unsigned long __cpuinit calibrate_delay_is_known(void)
+unsigned long calibrate_delay_is_known(void)
 {
        delay_calibrated = true;
        return lpj_fine;
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 02802386b894..699b71e7f7ec 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -163,6 +163,7 @@ config MACH_SAMA5_DT
        bool "Atmel SAMA5 Evaluation Kits with device-tree support"
        depends on SOC_SAMA5
        select USE_OF
+        select PHYLIB if NETDEVICES
        help
          Select this if you want to experiment device-tree with
          an Atmel Evaluation Kit.
diff --git a/arch/arm/mach-at91/Kconfig.non_dt b/arch/arm/mach-at91/Kconfig.non_dt
index 6c24985515a2..ca900be144ce 100644
--- a/arch/arm/mach-at91/Kconfig.non_dt
+++ b/arch/arm/mach-at91/Kconfig.non_dt
@@ -14,15 +14,11 @@ config ARCH_AT91RM9200
        select SOC_AT91RM9200
 config ARCH_AT91SAM9260
-        bool "AT91SAM9260 or AT91SAM9XE"
+        bool "AT91SAM9260 or AT91SAM9XE or AT91SAM9G20"
        select SOC_AT91SAM9260
 config ARCH_AT91SAM9261
-        bool "AT91SAM9261"
+        bool "AT91SAM9261 or AT91SAM9G10"
-        select SOC_AT91SAM9261
-config ARCH_AT91SAM9G10
-        bool "AT91SAM9G10"
        select SOC_AT91SAM9261
 config ARCH_AT91SAM9263
@@ -33,10 +29,6 @@ config ARCH_AT91SAM9RL
        bool "AT91SAM9RL"
        select SOC_AT91SAM9RL
-config ARCH_AT91SAM9G20
-        bool "AT91SAM9G20"
-        select SOC_AT91SAM9260
 config ARCH_AT91SAM9G45
        bool "AT91SAM9G45"
        select SOC_AT91SAM9G45
@@ -50,6 +42,14 @@ config ARCH_AT91X40
 endchoice
+config ARCH_AT91SAM9G20
+        bool
+        select ARCH_AT91SAM9260
+config ARCH_AT91SAM9G10
+        bool
+        select ARCH_AT91SAM9261
 # ----------------------------------------------------------
 if ARCH_AT91RM9200
@@ -62,13 +62,6 @@ config MACH_ONEARM
          Select this if you are using Ajeco's 1ARM Single Board Computer.
          <http://www.ajeco.fi/>
-config ARCH_AT91RM9200DK
-        bool "Atmel AT91RM9200-DK Development board"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Atmel's AT91RM9200-DK Development board.
-          (Discontinued)
 config MACH_AT91RM9200EK
        bool "Atmel AT91RM9200-EK Evaluation Kit"
        select HAVE_AT91_DATAFLASH_CARD
@@ -183,12 +176,6 @@ config MACH_AFEB9260
          <svn://194.85.238.22/home/users/george/svn/arm9eb>
          <http://groups.google.com/group/arm9fpga-evolution-board>
-config MACH_USB_A9260
-        bool "CALAO USB-A9260"
-        help
-          Select this if you are using a Calao Systems USB-A9260.
-          <http://www.calao-systems.com>
 config MACH_QIL_A9260
        bool "CALAO QIL-A9260 board"
        help
@@ -207,76 +194,6 @@ config MACH_FLEXIBITY
          Select this if you are using Flexibity Connect board
          <http://www.flexibity.com>
-endif
-# ----------------------------------------------------------
-if ARCH_AT91SAM9261
-comment "AT91SAM9261 Board Type"
-config MACH_AT91SAM9261EK
-        bool "Atmel AT91SAM9261-EK Evaluation Kit"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit.
-          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820>
-endif
-# ----------------------------------------------------------
-if ARCH_AT91SAM9G10
-comment "AT91SAM9G10 Board Type"
-config MACH_AT91SAM9G10EK
-        bool "Atmel AT91SAM9G10-EK Evaluation Kit"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit.
-          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4588>
-endif
-# ----------------------------------------------------------
-if ARCH_AT91SAM9263
-comment "AT91SAM9263 Board Type"
-config MACH_AT91SAM9263EK
-        bool "Atmel AT91SAM9263-EK Evaluation Kit"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit.
-          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057>
-config MACH_USB_A9263
-        bool "CALAO USB-A9263"
-        help
-          Select this if you are using a Calao Systems USB-A9263.
-          <http://www.calao-systems.com>
-endif
-# ----------------------------------------------------------
-if ARCH_AT91SAM9RL
-comment "AT91SAM9RL Board Type"
-config MACH_AT91SAM9RLEK
-        bool "Atmel AT91SAM9RL-EK Evaluation Kit"
-        help
-          Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit.
-endif
-# ----------------------------------------------------------
-if ARCH_AT91SAM9G20
 comment "AT91SAM9G20 Board Type"
 config MACH_AT91SAM9G20EK
@@ -334,24 +251,64 @@ config MACH_GSIA18S
          produced by GeoSIG Ltd company. This is an internet accelerograph.
          <http://www.geosig.com>
-config MACH_USB_A9G20
+config MACH_SNAPPER_9260
-        bool "CALAO USB-A9G20"
+        bool "Bluewater Systems Snapper 9260/9G20 module"
-        depends on ARCH_AT91SAM9G20
+        help
+          Select this if you are using the Bluewater Systems Snapper 9260 or
+          Snapper 9G20 modules.
+          <http://www.bluewatersys.com/>
+endif
+# ----------------------------------------------------------
+if ARCH_AT91SAM9261
+comment "AT91SAM9261 Board Type"
+config MACH_AT91SAM9261EK
+        bool "Atmel AT91SAM9261-EK Evaluation Kit"
+        select HAVE_AT91_DATAFLASH_CARD
        help
-          Select this if you are using a Calao Systems USB-A9G20.
+          Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit.
-          <http://www.calao-systems.com>
+          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820>
+comment "AT91SAM9G10 Board Type"
+config MACH_AT91SAM9G10EK
+        bool "Atmel AT91SAM9G10-EK Evaluation Kit"
+        select HAVE_AT91_DATAFLASH_CARD
+        help
+          Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit.
+          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4588>
 endif
-if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20)
+# ----------------------------------------------------------
-comment "AT91SAM9260/AT91SAM9G20 boards"
+if ARCH_AT91SAM9263
+comment "AT91SAM9263 Board Type"
+config MACH_AT91SAM9263EK
+        bool "Atmel AT91SAM9263-EK Evaluation Kit"
+        select HAVE_AT91_DATAFLASH_CARD
+        help
+          Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit.
+          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057>
+endif
+# ----------------------------------------------------------
+if ARCH_AT91SAM9RL
+comment "AT91SAM9RL Board Type"
+config MACH_AT91SAM9RLEK
+        bool "Atmel AT91SAM9RL-EK Evaluation Kit"
+        help
+          Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit.
-config MACH_SNAPPER_9260
-        bool "Bluewater Systems Snapper 9260/9G20 module"
-        help
-          Select this if you are using the Bluewater Systems Snapper 9260 or
-          Snapper 9G20 modules.
-          <http://www.bluewatersys.com/>
 endif
 # ----------------------------------------------------------
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 788562dccb43..3b0a9538093c 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -27,16 +27,13 @@ obj-$(CONFIG_SOC_SAMA5D3)	+= sama5d3.o
 obj-$(CONFIG_ARCH_AT91RM9200)   += at91rm9200_devices.o
 obj-$(CONFIG_ARCH_AT91SAM9260)  += at91sam9260_devices.o
 obj-$(CONFIG_ARCH_AT91SAM9261)  += at91sam9261_devices.o
-obj-$(CONFIG_ARCH_AT91SAM9G10)  += at91sam9261_devices.o
 obj-$(CONFIG_ARCH_AT91SAM9263)  += at91sam9263_devices.o
 obj-$(CONFIG_ARCH_AT91SAM9RL)   += at91sam9rl_devices.o
-obj-$(CONFIG_ARCH_AT91SAM9G20)  += at91sam9260_devices.o
 obj-$(CONFIG_ARCH_AT91SAM9G45)  += at91sam9g45_devices.o
 obj-$(CONFIG_ARCH_AT91X40)      += at91x40.o at91x40_time.o
 # AT91RM9200 board-specific support
 obj-$(CONFIG_MACH_ONEARM)       += board-1arm.o
-obj-$(CONFIG_ARCH_AT91RM9200DK) += board-rm9200dk.o
 obj-$(CONFIG_MACH_AT91RM9200EK) += board-rm9200ek.o
 obj-$(CONFIG_MACH_CSB337)       += board-csb337.o
 obj-$(CONFIG_MACH_CSB637)       += board-csb637.o
@@ -55,7 +52,6 @@ obj-$(CONFIG_MACH_RSI_EWS)	+= board-rsi-ews.o
 obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o
 obj-$(CONFIG_MACH_CAM60)        += board-cam60.o
 obj-$(CONFIG_MACH_SAM9_L9260)   += board-sam9-l9260.o
-obj-$(CONFIG_MACH_USB_A9260)    += board-usb-a926x.o
 obj-$(CONFIG_MACH_QIL_A9260)    += board-qil-a9260.o
 obj-$(CONFIG_MACH_AFEB9260)     += board-afeb-9260v1.o
 obj-$(CONFIG_MACH_CPU9260)      += board-cpu9krea.o
@@ -67,7 +63,6 @@ obj-$(CONFIG_MACH_AT91SAM9G10EK) += board-sam9261ek.o
 # AT91SAM9263 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o
-obj-$(CONFIG_MACH_USB_A9263)    += board-usb-a926x.o
 # AT91SAM9RL board-specific support
 obj-$(CONFIG_MACH_AT91SAM9RLEK) += board-sam9rlek.o
@@ -80,7 +75,6 @@ obj-$(CONFIG_MACH_STAMP9G20)	+= board-stamp9g20.o
 obj-$(CONFIG_MACH_PORTUXG20)    += board-stamp9g20.o
 obj-$(CONFIG_MACH_PCONTROL_G20) += board-pcontrol-g20.o board-stamp9g20.o
 obj-$(CONFIG_MACH_GSIA18S)      += board-gsia18s.o board-stamp9g20.o
-obj-$(CONFIG_MACH_USB_A9G20)    += board-usb-a926x.o
 # AT91SAM9260/AT91SAM9G20 board-specific support
 obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index d193a409bc45..4aad93d54d6f 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -11,6 +11,7 @@
 */
 #include <linux/module.h>
+#include <linux/reboot.h>
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
@@ -304,7 +305,7 @@ static void at91rm9200_idle(void)
        at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
 }
-static void at91rm9200_restart(char mode, const char *cmd)
+static void at91rm9200_restart(enum reboot_mode reboot_mode, const char *cmd)
 {
        /*
         * Perform a hardware reset with the use of the Watchdog timer.
@@ -332,10 +333,6 @@ static void __init at91rm9200_initialize(void)
 {
        arm_pm_idle = at91rm9200_idle;
        arm_pm_restart = at91rm9200_restart;
-        at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
-                        | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
-                        | (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5)
-                        | (1 << AT91RM9200_ID_IRQ6);
        /* Initialize GPIO subsystem */
        at91_gpio_init(at91rm9200_gpio,
@@ -388,6 +385,10 @@ static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
 AT91_SOC_START(at91rm9200)
        .map_io = at91rm9200_map_io,
        .default_irq_priority = at91rm9200_default_irq_priority,
+        .extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
+                    | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
+                    | (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5)
+                    | (1 << AT91RM9200_ID_IRQ6),
        .ioremap_registers = at91rm9200_ioremap_registers,
        .register_clocks = at91rm9200_register_clocks,
        .init = at91rm9200_initialize,
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index a8ce24538da6..5de6074b4f4f 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -348,8 +348,6 @@ static void __init at91sam9260_initialize(void)
 {
        arm_pm_idle = at91sam9_idle;
        arm_pm_restart = at91sam9_alt_restart;
-        at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
-                        | (1 << AT91SAM9260_ID_IRQ2);
        /* Register GPIO subsystem */
        at91_gpio_init(at91sam9260_gpio, 3);
@@ -400,6 +398,8 @@ static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
 AT91_SOC_START(at91sam9260)
        .map_io = at91sam9260_map_io,
        .default_irq_priority = at91sam9260_default_irq_priority,
+        .extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
+                    | (1 << AT91SAM9260_ID_IRQ2),
        .ioremap_registers = at91sam9260_ioremap_registers,
        .register_clocks = at91sam9260_register_clocks,
        .init = at91sam9260_initialize,
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 25efb5ac30f1..0e0793241ab7 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -290,8 +290,6 @@ static void __init at91sam9261_initialize(void)
 {
        arm_pm_idle = at91sam9_idle;
        arm_pm_restart = at91sam9_alt_restart;
-        at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
-                        | (1 << AT91SAM9261_ID_IRQ2);
        /* Register GPIO subsystem */
        at91_gpio_init(at91sam9261_gpio, 3);
@@ -342,6 +340,8 @@ static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
 AT91_SOC_START(at91sam9261)
        .map_io = at91sam9261_map_io,
        .default_irq_priority = at91sam9261_default_irq_priority,
+        .extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
+                    | (1 << AT91SAM9261_ID_IRQ2),
        .ioremap_registers = at91sam9261_ioremap_registers,
        .register_clocks = at91sam9261_register_clocks,
        .init = at91sam9261_initialize,
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index f44ffd2105a7..6ce7d1850893 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -327,7 +327,6 @@ static void __init at91sam9263_initialize(void)
 {
        arm_pm_idle = at91sam9_idle;
        arm_pm_restart = at91sam9_alt_restart;
-        at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
        /* Register GPIO subsystem */
        at91_gpio_init(at91sam9263_gpio, 5);
@@ -378,6 +377,7 @@ static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
 AT91_SOC_START(at91sam9263)
        .map_io = at91sam9263_map_io,
        .default_irq_priority = at91sam9263_default_irq_priority,
+        .extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1),
        .ioremap_registers = at91sam9263_ioremap_registers,
        .register_clocks = at91sam9263_register_clocks,
        .init = at91sam9263_initialize,
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 8b7fce067652..474ee04d24b9 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -266,6 +266,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
        CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
        CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
+        CLKDEV_CON_DEV_ID("hclk", "600000.gadget", &utmi_clk),
+        CLKDEV_CON_DEV_ID("pclk", "600000.gadget", &udphs_clk),
        /* fake hclk clock */
        CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
        CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
@@ -374,7 +376,6 @@ static void __init at91sam9g45_initialize(void)
 {
        arm_pm_idle = at91sam9_idle;
        arm_pm_restart = at91sam9g45_restart;
-        at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
        /* Register GPIO subsystem */
        at91_gpio_init(at91sam9g45_gpio, 5);
@@ -425,6 +426,7 @@ static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
 AT91_SOC_START(at91sam9g45)
        .map_io = at91sam9g45_map_io,
        .default_irq_priority = at91sam9g45_default_irq_priority,
+        .extern_irq = (1 << AT91SAM9G45_ID_IRQ0),
        .ioremap_registers = at91sam9g45_ioremap_registers,
        .register_clocks = at91sam9g45_register_clocks,
        .init = at91sam9g45_initialize,
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index f77fae5591bc..d4ec0d9a9872 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -293,7 +293,6 @@ static void __init at91sam9rl_initialize(void)
 {
        arm_pm_idle = at91sam9_idle;
        arm_pm_restart = at91sam9_alt_restart;
-        at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
        /* Register GPIO subsystem */
        at91_gpio_init(at91sam9rl_gpio, 4);
@@ -344,6 +343,7 @@ static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
 AT91_SOC_START(at91sam9rl)
        .map_io = at91sam9rl_map_io,
        .default_irq_priority = at91sam9rl_default_irq_priority,
+        .extern_irq = (1 << AT91SAM9RL_ID_IRQ0),
        .ioremap_registers = at91sam9rl_ioremap_registers,
        .register_clocks = at91sam9rl_register_clocks,
        .init = at91sam9rl_initialize,
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index e631fec040ce..2abee6626aac 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -249,6 +249,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk),
        CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
        CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
+        CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk),
+        CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk),
 };
 /*
diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c
index 19ca79396905..bad94b84a46f 100644
--- a/arch/arm/mach-at91/at91x40.c
+++ b/arch/arm/mach-at91/at91x40.c
@@ -55,8 +55,6 @@ static void at91x40_idle(void)
 void __init at91x40_initialize(unsigned long main_clock)
 {
        arm_pm_idle = at91x40_idle;
-        at91_extern_irq = (1 << AT91X40_ID_IRQ0) | (1 << AT91X40_ID_IRQ1)
-                        | (1 << AT91X40_ID_IRQ2);
 }
 /*
@@ -86,9 +84,10 @@ static unsigned int at91x40_default_irq_priority[NR_AIC_IRQS] __initdata = {
 void __init at91x40_init_interrupts(unsigned int priority[NR_AIC_IRQS])
 {
+        u32  extern_irq = (1 << AT91X40_ID_IRQ0) | (1 << AT91X40_ID_IRQ1)
+                        | (1 << AT91X40_ID_IRQ2);
        if (!priority)
                priority = at91x40_default_irq_priority;
-        at91_aic_init(priority, at91_extern_irq);
+        at91_aic_init(priority, extern_irq);
 }
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
index 705305e62bbc..ad95f6a23a28 100644
--- a/arch/arm/mach-at91/board-dt-sama5.c
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -62,7 +62,8 @@ static int ksz9021rn_phy_fixup(struct phy_device *phy)
 static void __init sama5_dt_device_init(void)
 {
-        if (of_machine_is_compatible("atmel,sama5d3xcm"))
+        if (of_machine_is_compatible("atmel,sama5d3xcm") &&
+            IS_ENABLED(CONFIG_PHYLIB))
                phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
                        ksz9021rn_phy_fixup);
diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c
deleted file mode 100644
index 690541b18cbc..000000000000
--- a/arch/arm/mach-at91/board-rm9200dk.c
+++ /dev/null
@@ -1,228 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/board-rm9200dk.c
- *
- *  Copyright (C) 2005 SAN People
- *
- *  Epson S1D framebuffer glue code is:
- *     Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/types.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/mtd/physmap.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <mach/hardware.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
-#include "at91_aic.h"
-#include "board.h"
-#include "generic.h"
-static void __init dk_init_early(void)
-{
-        /* Initialize processor: 18.432 MHz crystal */
-        at91_initialize(18432000);
-}
-static struct macb_platform_data __initdata dk_eth_data = {
-        .phy_irq_pin    = AT91_PIN_PC4,
-        .is_rmii        = 1,
-};
-static struct at91_usbh_data __initdata dk_usbh_data = {
-        .ports          = 2,
-        .vbus_pin       = {-EINVAL, -EINVAL},
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-static struct at91_udc_data __initdata dk_udc_data = {
-        .vbus_pin       = AT91_PIN_PD4,
-        .pullup_pin     = AT91_PIN_PD5,
-};
-static struct at91_cf_data __initdata dk_cf_data = {
-        .irq_pin        = -EINVAL,
-        .det_pin        = AT91_PIN_PB0,
-        .vcc_pin        = -EINVAL,
-        .rst_pin        = AT91_PIN_PC5,
-};
-#ifndef CONFIG_MTD_AT91_DATAFLASH_CARD
-static struct mci_platform_data __initdata dk_mci0_data = {
-        .slot[0] = {
-                .bus_width      = 4,
-                .detect_pin     = -EINVAL,
-                .wp_pin         = -EINVAL,
-        },
-};
-#endif
-static struct spi_board_info dk_spi_devices[] = {
-        {       /* DataFlash chip */
-                .modalias       = "mtd_dataflash",
-                .chip_select    = 0,
-                .max_speed_hz   = 15 * 1000 * 1000,
-        },
-        {       /* UR6HCPS2-SP40 PS2-to-SPI adapter */
-                .modalias       = "ur6hcps2",
-                .chip_select    = 1,
-                .max_speed_hz   = 250 *  1000,
-        },
-        {       /* TLV1504 ADC, 4 channels, 10 bits; one is a temp sensor */
-                .modalias       = "tlv1504",
-                .chip_select    = 2,
-                .max_speed_hz   = 20 * 1000 * 1000,
-        },
-#ifdef CONFIG_MTD_AT91_DATAFLASH_CARD
-        {       /* DataFlash card */
-                .modalias       = "mtd_dataflash",
-                .chip_select    = 3,
-                .max_speed_hz   = 15 * 1000 * 1000,
-        }
-#endif
-};
-static struct i2c_board_info __initdata dk_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("ics1523", 0x26),
-        },
-        {
-                I2C_BOARD_INFO("x9429", 0x28),
-        },
-        {
-                I2C_BOARD_INFO("24c1024", 0x50),
-        }
-};
-static struct mtd_partition __initdata dk_nand_partition[] = {
-        {
-                .name   = "NAND Partition 1",
-                .offset = 0,
-                .size   = MTDPART_SIZ_FULL,
-        },
-};
-static struct atmel_nand_data __initdata dk_nand_data = {
-        .ale            = 22,
-        .cle            = 21,
-        .det_pin        = AT91_PIN_PB1,
-        .rdy_pin        = AT91_PIN_PC2,
-        .enable_pin     = -EINVAL,
-        .ecc_mode       = NAND_ECC_SOFT,
-        .on_flash_bbt   = 1,
-        .parts          = dk_nand_partition,
-        .num_parts      = ARRAY_SIZE(dk_nand_partition),
-};
-#define DK_FLASH_BASE   AT91_CHIPSELECT_0
-#define DK_FLASH_SIZE   SZ_2M
-static struct physmap_flash_data dk_flash_data = {
-        .width          = 2,
-};
-static struct resource dk_flash_resource = {
-        .start          = DK_FLASH_BASE,
-        .end            = DK_FLASH_BASE + DK_FLASH_SIZE - 1,
-        .flags          = IORESOURCE_MEM,
-};
-static struct platform_device dk_flash = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                                .platform_data  = &dk_flash_data,
-                        },
-        .resource       = &dk_flash_resource,
-        .num_resources  = 1,
-};
-static struct gpio_led dk_leds[] = {
-        {
-                .name                   = "led0",
-                .gpio                   = AT91_PIN_PB2,
-                .active_low             = 1,
-                .default_trigger        = "heartbeat",
-        }
-};
-static void __init dk_board_init(void)
-{
-        /* Serial */
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
-                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
-                           | ATMEL_UART_RI);
-        at91_add_device_serial();
-        /* Ethernet */
-        at91_add_device_eth(&dk_eth_data);
-        /* USB Host */
-        at91_add_device_usbh(&dk_usbh_data);
-        /* USB Device */
-        at91_add_device_udc(&dk_udc_data);
-        at91_set_multi_drive(dk_udc_data.pullup_pin, 1);        /* pullup_pin is connected to reset */
-        /* Compact Flash */
-        at91_add_device_cf(&dk_cf_data);
-        /* I2C */
-        at91_add_device_i2c(dk_i2c_devices, ARRAY_SIZE(dk_i2c_devices));
-        /* SPI */
-        at91_add_device_spi(dk_spi_devices, ARRAY_SIZE(dk_spi_devices));
-#ifdef CONFIG_MTD_AT91_DATAFLASH_CARD
-        /* DataFlash card */
-        at91_set_gpio_output(AT91_PIN_PB7, 0);
-#else
-        /* MMC */
-        at91_set_gpio_output(AT91_PIN_PB7, 1);  /* this MMC card slot can optionally use SPI signaling (CS3). */
-        at91_add_device_mci(0, &dk_mci0_data);
-#endif
-        /* NAND */
-        at91_add_device_nand(&dk_nand_data);
-        /* NOR Flash */
-        platform_device_register(&dk_flash);
-        /* LEDs */
-        at91_gpio_leds(dk_leds, ARRAY_SIZE(dk_leds));
-        /* VGA */
-//      dk_add_device_video();
-}
-MACHINE_START(AT91RM9200DK, "Atmel AT91RM9200-DK")
-        /* Maintainer: SAN People/Atmel */
-        .init_time      = at91rm9200_timer_init,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = dk_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = dk_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index b446645c7727..d3437624ca4e 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -264,11 +264,7 @@ static void __init ek_add_device_ts(void) {}
 */
 static struct at73c213_board_info at73c213_data = {
        .ssc_id         = 1,
-#if defined(CONFIG_MACH_AT91SAM9261EK)
+        .shortname      = "AT91SAM9261/9G10-EK external DAC",
-        .shortname      = "AT91SAM9261-EK external DAC",
-#else
-        .shortname      = "AT91SAM9G10-EK external DAC",
-#endif
 };
 #if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE)
@@ -412,9 +408,6 @@ static struct atmel_lcdfb_info __initdata ek_lcdc_data = {
        .default_monspecs               = &at91fb_default_stn_monspecs,
        .atmel_lcdfb_power_control      = at91_lcdc_stn_power_control,
        .guard_time                     = 1,
-#if defined(CONFIG_MACH_AT91SAM9G10EK)
-        .lcd_wiring_mode                = ATMEL_LCDC_WIRING_RGB,
-#endif
 };
 #else
@@ -468,9 +461,6 @@ static struct atmel_lcdfb_info __initdata ek_lcdc_data = {
        .default_monspecs               = &at91fb_default_tft_monspecs,
        .atmel_lcdfb_power_control      = at91_lcdc_tft_power_control,
        .guard_time                     = 1,
-#if defined(CONFIG_MACH_AT91SAM9G10EK)
-        .lcd_wiring_mode                = ATMEL_LCDC_WIRING_RGB,
-#endif
 };
 #endif
@@ -574,6 +564,10 @@ static void __init ek_board_init(void)
        /* DBGU on ttyS0. (Rx & Tx only) */
        at91_register_uart(0, 0, 0);
        at91_add_device_serial();
+        if (cpu_is_at91sam9g10())
+                ek_lcdc_data.lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB;
        /* USB Host */
        at91_add_device_usbh(&ek_usbh_data);
        /* USB Device */
@@ -606,11 +600,17 @@ static void __init ek_board_init(void)
        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
 }
-#if defined(CONFIG_MACH_AT91SAM9261EK)
 MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK")
-#else
+        /* Maintainer: Atmel */
+        .init_time      = at91sam926x_pit_init,
+        .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
+        .init_early     = ek_init_early,
+        .init_irq       = at91_init_irq_default,
+        .init_machine   = ek_board_init,
+MACHINE_END
 MACHINE_START(AT91SAM9G10EK, "Atmel AT91SAM9G10-EK")
-#endif
        /* Maintainer: Atmel */
        .init_time      = at91sam926x_pit_init,
        .map_io         = at91_map_io,
diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c
deleted file mode 100644
index 2487d944a1bc..000000000000
--- a/arch/arm/mach-at91/board-usb-a926x.c
+++ /dev/null
@@ -1,384 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/board-usb-a926x.c
- *
- *  Copyright (C) 2005 SAN People
- *  Copyright (C) 2007 Atmel Corporation.
- *  Copyright (C) 2007 Calao-systems
- *  Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/gpio_keys.h>
-#include <linux/gpio.h>
-#include <linux/input.h>
-#include <linux/spi/mmc_spi.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <mach/hardware.h>
-#include <mach/at91sam9_smc.h>
-#include "at91_aic.h"
-#include "at91_shdwc.h"
-#include "board.h"
-#include "sam9_smc.h"
-#include "generic.h"
-static void __init ek_init_early(void)
-{
-        /* Initialize processor: 12.00 MHz crystal */
-        at91_initialize(12000000);
-}
-/*
- * USB Host port
- */
-static struct at91_usbh_data __initdata ek_usbh_data = {
-        .ports          = 2,
-        .vbus_pin       = {-EINVAL, -EINVAL},
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-/*
- * USB Device port
- */
-static struct at91_udc_data __initdata ek_udc_data = {
-        .vbus_pin       = AT91_PIN_PB11,
-        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
-};
-static void __init ek_add_device_udc(void)
-{
-        if (machine_is_usb_a9260() || machine_is_usb_a9g20())
-                ek_udc_data.vbus_pin = AT91_PIN_PC5;
-        at91_add_device_udc(&ek_udc_data);
-}
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
-#define MMC_SPI_CARD_DETECT_INT AT91_PIN_PC4
-static int at91_mmc_spi_init(struct device *dev,
-        irqreturn_t (*detect_int)(int, void *), void *data)
-{
-        /* Configure Interrupt pin as input, no pull-up */
-        at91_set_gpio_input(MMC_SPI_CARD_DETECT_INT, 0);
-        return request_irq(gpio_to_irq(MMC_SPI_CARD_DETECT_INT), detect_int,
-                IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
-                "mmc-spi-detect", data);
-}
-static void at91_mmc_spi_exit(struct device *dev, void *data)
-{
-        free_irq(gpio_to_irq(MMC_SPI_CARD_DETECT_INT), data);
-}
-static struct mmc_spi_platform_data at91_mmc_spi_pdata = {
-        .init = at91_mmc_spi_init,
-        .exit = at91_mmc_spi_exit,
-        .detect_delay = 100, /* msecs */
-};
-#endif
-/*
- * SPI devices.
- */
-static struct spi_board_info usb_a9263_spi_devices[] = {
-        {       /* DataFlash chip */
-                .modalias       = "mtd_dataflash",
-                .chip_select    = 0,
-                .max_speed_hz   = 15 * 1000 * 1000,
-                .bus_num        = 0,
-        }
-};
-static struct spi_board_info usb_a9g20_spi_devices[] = {
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
-        {
-                .modalias = "mmc_spi",
-                .max_speed_hz = 20000000,       /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1,
-                .chip_select = 0,
-                .platform_data = &at91_mmc_spi_pdata,
-                .mode = SPI_MODE_3,
-        },
-#endif
-};
-static void __init ek_add_device_spi(void)
-{
-        if (machine_is_usb_a9263())
-                at91_add_device_spi(usb_a9263_spi_devices, ARRAY_SIZE(usb_a9263_spi_devices));
-        else if (machine_is_usb_a9g20())
-                at91_add_device_spi(usb_a9g20_spi_devices, ARRAY_SIZE(usb_a9g20_spi_devices));
-}
-/*
- * MACB Ethernet device
- */
-static struct macb_platform_data __initdata ek_macb_data = {
-        .phy_irq_pin    = AT91_PIN_PE31,
-        .is_rmii        = 1,
-};
-static void __init ek_add_device_eth(void)
-{
-        if (machine_is_usb_a9260() || machine_is_usb_a9g20())
-                ek_macb_data.phy_irq_pin = AT91_PIN_PA31;
-        at91_add_device_eth(&ek_macb_data);
-}
-/*
- * NAND flash
- */
-static struct mtd_partition __initdata ek_nand_partition[] = {
-        {
-                .name   = "barebox",
-                .offset = 0,
-                .size   = 3 * SZ_128K,
-        }, {
-                .name   = "bareboxenv",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = SZ_128K,
-        }, {
-                .name   = "bareboxenv2",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = SZ_128K,
-        }, {
-                .name   = "oftree",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = SZ_128K,
-        }, {
-                .name   = "kernel",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = 4 * SZ_1M,
-        }, {
-                .name   = "rootfs",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = 120 * SZ_1M,
-        }, {
-                .name   = "data",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = MTDPART_SIZ_FULL,
-        }
-};
-static struct atmel_nand_data __initdata ek_nand_data = {
-        .ale            = 21,
-        .cle            = 22,
-        .det_pin        = -EINVAL,
-        .rdy_pin        = AT91_PIN_PA22,
-        .enable_pin     = AT91_PIN_PD15,
-        .ecc_mode       = NAND_ECC_SOFT,
-        .on_flash_bbt   = 1,
-        .parts          = ek_nand_partition,
-        .num_parts      = ARRAY_SIZE(ek_nand_partition),
-};
-static struct sam9_smc_config __initdata usb_a9260_nand_smc_config = {
-        .ncs_read_setup         = 0,
-        .nrd_setup              = 1,
-        .ncs_write_setup        = 0,
-        .nwe_setup              = 1,
-        .ncs_read_pulse         = 3,
-        .nrd_pulse              = 3,
-        .ncs_write_pulse        = 3,
-        .nwe_pulse              = 3,
-        .read_cycle             = 5,
-        .write_cycle            = 5,
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
-        .tdf_cycles             = 2,
-};
-static struct sam9_smc_config __initdata usb_a9g20_nand_smc_config = {
-        .ncs_read_setup         = 0,
-        .nrd_setup              = 2,
-        .ncs_write_setup        = 0,
-        .nwe_setup              = 2,
-        .ncs_read_pulse         = 4,
-        .nrd_pulse              = 4,
-        .ncs_write_pulse        = 4,
-        .nwe_pulse              = 4,
-        .read_cycle             = 7,
-        .write_cycle            = 7,
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
-        .tdf_cycles             = 3,
-};
-static void __init ek_add_device_nand(void)
-{
-        if (machine_is_usb_a9260() || machine_is_usb_a9g20()) {
-                ek_nand_data.rdy_pin    = AT91_PIN_PC13;
-                ek_nand_data.enable_pin = AT91_PIN_PC14;
-        }
-        /* configure chip-select 3 (NAND) */
-        if (machine_is_usb_a9g20())
-                sam9_smc_configure(0, 3, &usb_a9g20_nand_smc_config);
-        else
-                sam9_smc_configure(0, 3, &usb_a9260_nand_smc_config);
-        at91_add_device_nand(&ek_nand_data);
-}
-/*
- * GPIO Buttons
- */
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
-static struct gpio_keys_button ek_buttons[] = {
-        {       /* USER PUSH BUTTON */
-                .code           = KEY_ENTER,
-                .gpio           = AT91_PIN_PB10,
-                .active_low     = 1,
-                .desc           = "user_pb",
-                .wakeup         = 1,
-        }
-};
-static struct gpio_keys_platform_data ek_button_data = {
-        .buttons        = ek_buttons,
-        .nbuttons       = ARRAY_SIZE(ek_buttons),
-};
-static struct platform_device ek_button_device = {
-        .name           = "gpio-keys",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev            = {
-                .platform_data  = &ek_button_data,
-        }
-};
-static void __init ek_add_device_buttons(void)
-{
-        at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* user push button, pull up enabled */
-        at91_set_deglitch(AT91_PIN_PB10, 1);
-        platform_device_register(&ek_button_device);
-}
-#else
-static void __init ek_add_device_buttons(void) {}
-#endif
-/*
- * LEDs
- */
-static struct gpio_led ek_leds[] = {
-        {       /* user_led (green) */
-                .name                   = "user_led",
-                .gpio                   = AT91_PIN_PB21,
-                .active_low             = 1,
-                .default_trigger        = "heartbeat",
-        }
-};
-static struct i2c_board_info __initdata ek_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("rv3029c2", 0x56),
-        },
-};
-static void __init ek_add_device_leds(void)
-{
-        if (machine_is_usb_a9260() || machine_is_usb_a9g20())
-                ek_leds[0].active_low = 0;
-        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
-}
-static void __init ek_board_init(void)
-{
-        /* Serial */
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        at91_add_device_serial();
-        /* USB Host */
-        at91_add_device_usbh(&ek_usbh_data);
-        /* USB Device */
-        ek_add_device_udc();
-        /* SPI */
-        ek_add_device_spi();
-        /* Ethernet */
-        ek_add_device_eth();
-        /* NAND */
-        ek_add_device_nand();
-        /* Push Buttons */
-        ek_add_device_buttons();
-        /* LEDs */
-        ek_add_device_leds();
-        if (machine_is_usb_a9g20()) {
-                /* I2C */
-                at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices));
-        } else {
-                /* I2C */
-                at91_add_device_i2c(NULL, 0);
-                /* shutdown controller, wakeup button (5 msec low) */
-                at91_shdwc_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10)
-                                | AT91_SHDW_WKMODE0_LOW
-                                | AT91_SHDW_RTTWKEN);
-        }
-}
-MACHINE_START(USB_A9263, "CALAO USB_A9263")
-        /* Maintainer: calao-systems */
-        .init_time      = at91sam926x_pit_init,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = ek_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = ek_board_init,
-MACHINE_END
-MACHINE_START(USB_A9260, "CALAO USB_A9260")
-        /* Maintainer: calao-systems */
-        .init_time      = at91sam926x_pit_init,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = ek_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = ek_board_init,
-MACHINE_END
-MACHINE_START(USB_A9G20, "CALAO USB_A92G0")
-        /* Maintainer: Jean-Christophe PLAGNIOL-VILLARD */
-        .init_time      = at91sam926x_pit_init,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = ek_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = ek_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index da841885d01c..6b2630a92f71 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -75,7 +75,7 @@ EXPORT_SYMBOL_GPL(at91_pmc_base);
 #define cpu_has_pllb()          (!(cpu_is_at91sam9rl() \
                                || cpu_is_at91sam9g45() \
                                || cpu_is_at91sam9x5() \
-                                || cpu_is_at91sam9n12()))
+                                || cpu_is_sama5d3()))
 #define cpu_has_upll()          (cpu_is_at91sam9g45() \
                                || cpu_is_at91sam9x5() \
@@ -489,7 +489,7 @@ static int at91_clk_show(struct seq_file *s, void *unused)
                seq_printf(s, "UCKR = %8x\n", uckr);
        }
        seq_printf(s, "MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR));
-        if (cpu_has_upll())
+        if (cpu_has_upll() || cpu_is_at91sam9n12())
                seq_printf(s, "USB  = %8x\n", at91_pmc_read(AT91_PMC_USB));
        seq_printf(s, "SR   = %8x\n", sr);
@@ -614,6 +614,8 @@ static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
 {
        if (pll == &pllb && (reg & AT91_PMC_USB96M))
                return freq / 2;
+        else if (pll == &utmi_clk || cpu_is_at91sam9n12())
+                return freq / (1 + ((reg & AT91_PMC_OHCIUSBDIV) >> 8));
        else
                return freq;
 }
@@ -683,6 +685,8 @@ static struct clk *const standard_pmc_clocks[] __initconst = {
 /* PLLB generated USB full speed clock init */
 static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
 {
+        unsigned int reg;
        /*
         * USB clock init:  choose 48 MHz PLLB value,
         * disable 48MHz clock during usb peripheral suspend.
@@ -691,22 +695,35 @@ static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
         */
        uhpck.parent = &pllb;
-        at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
+        reg = at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2);
        pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
        if (cpu_is_at91rm9200()) {
+                reg = at91_pllb_usb_init |= AT91_PMC_USB96M;
                uhpck.pmc_mask = AT91RM9200_PMC_UHP;
                udpck.pmc_mask = AT91RM9200_PMC_UDP;
                at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
        } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
                   cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
                   cpu_is_at91sam9g10()) {
+                reg = at91_pllb_usb_init |= AT91_PMC_USB96M;
+                uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
+                udpck.pmc_mask = AT91SAM926x_PMC_UDP;
+        } else if (cpu_is_at91sam9n12()) {
+                /* Divider for USB clock is in USB clock register for 9n12 */
+                reg = AT91_PMC_USBS_PLLB;
+                /* For PLLB output 96M, set usb divider 2 (USBDIV + 1) */
+                reg |= AT91_PMC_OHCIUSBDIV_2;
+                at91_pmc_write(AT91_PMC_USB, reg);
+                /* Still setup masks */
                uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
                udpck.pmc_mask = AT91SAM926x_PMC_UDP;
        }
        at91_pmc_write(AT91_CKGR_PLLBR, 0);
-        udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
+        udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, reg);
-        uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
+        uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, reg);
 }
 /* UPLL generated USB full speed clock init */
@@ -725,8 +742,7 @@ static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
        /* Now set uhpck values */
        uhpck.parent = &utmi_clk;
        uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
-        uhpck.rate_hz = utmi_clk.rate_hz;
+        uhpck.rate_hz = at91_usb_rate(&utmi_clk, utmi_clk.rate_hz, usbr);
-        uhpck.rate_hz /= 1 + ((at91_pmc_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
 }
 static int __init at91_pmc_init(unsigned long main_clock)
diff --git a/arch/arm/mach-at91/cpuidle.c b/arch/arm/mach-at91/cpuidle.c
index 69f9e3bbf4e5..4ec6a6d9b9be 100644
--- a/arch/arm/mach-at91/cpuidle.c
+++ b/arch/arm/mach-at91/cpuidle.c
@@ -51,7 +51,7 @@ static struct cpuidle_driver at91_idle_driver = {
        .states[1]              = {
                .enter                  = at91_enter_idle,
                .exit_latency           = 10,
-                .target_residency       = 100000,
+                .target_residency       = 10000,
                .flags                  = CPUIDLE_FLAG_TIME_VALID,
                .name                   = "RAM_SR",
                .desc                   = "WFI and DDR Self Refresh",
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 78ab06548658..dc6e2f5f804d 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -10,6 +10,7 @@
 #include <linux/clkdev.h>
 #include <linux/of.h>
+#include <linux/reboot.h>
 /* Map io */
 extern void __init at91_map_io(void);
@@ -60,8 +61,8 @@ extern void at91sam9_idle(void);
 /* reset */
 extern void at91_ioremap_rstc(u32 base_addr);
-extern void at91sam9_alt_restart(char, const char *);
+extern void at91sam9_alt_restart(enum reboot_mode, const char *);
-extern void at91sam9g45_restart(char, const char *);
+extern void at91sam9g45_restart(enum reboot_mode, const char *);
 /* shutdown */
 extern void at91_ioremap_shdwc(u32 base_addr);
@@ -85,4 +86,4 @@ extern void __init at91_gpio_irq_setup(void);
 extern int  __init at91_gpio_of_irq_setup(struct device_node *node,
                                          struct device_node *parent);
-extern int at91_extern_irq;
+extern u32 at91_get_extern_irq(void);
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index 2bd7f51b0b82..c604cc69acb5 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -130,7 +130,10 @@ extern void __iomem *at91_pmc_base;
 #define         AT91_PMC_USBS           (0x1 <<  0)             /* USB OHCI Input clock selection */
 #define                 AT91_PMC_USBS_PLLA              (0 << 0)
 #define                 AT91_PMC_USBS_UPLL              (1 << 0)
+#define                 AT91_PMC_USBS_PLLB              (1 << 0)        /* [AT91SAMN12 only] */
 #define         AT91_PMC_OHCIUSBDIV     (0xF <<  8)             /* Divider for USB OHCI Clock */
+#define                 AT91_PMC_OHCIUSBDIV_1   (0x0 <<  8)
+#define                 AT91_PMC_OHCIUSBDIV_2   (0x1 <<  8)
 #define AT91_PMC_SMD            0x3c                    /* Soft Modem Clock Register [some SAM9 only] */
 #define         AT91_PMC_SMDS           (0x1  <<  0)            /* SMD input clock selection */
diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c
index e0ca59171022..3d192c5aee66 100644
--- a/arch/arm/mach-at91/irq.c
+++ b/arch/arm/mach-at91/irq.c
@@ -232,7 +232,14 @@ static void __maybe_unused at91_aic5_eoi(struct irq_data *d)
        at91_aic_write(AT91_AIC5_EOICR, 0);
 }
-unsigned long *at91_extern_irq;
+static unsigned long *at91_extern_irq;
+u32 at91_get_extern_irq(void)
+{
+        if (!at91_extern_irq)
+                return 0;
+        return *at91_extern_irq;
+}
 #define is_extern_irq(hwirq) test_bit(hwirq, at91_extern_irq)
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 530db304ec5e..15afb5d9271f 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -212,7 +212,7 @@ static int at91_pm_enter(suspend_state_t state)
                        (at91_pmc_read(AT91_PMC_PCSR)
                                        | (1 << AT91_ID_FIQ)
                                        | (1 << AT91_ID_SYS)
-                                        | (at91_extern_irq))
+                                        | (at91_get_extern_irq()))
                                & at91_aic_read(AT91_AIC_IMR),
                        state);
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index e2f4bdd146d6..b17fbcf4d9e8 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -48,7 +48,7 @@ void __init at91_init_irq_default(void)
 void __init at91_init_interrupts(unsigned int *priority)
 {
        /* Initialize the AIC interrupt controller */
-        at91_aic_init(priority, at91_extern_irq);
+        at91_aic_init(priority, at91_boot_soc.extern_irq);
        /* Enable GPIO interrupts */
        at91_gpio_irq_setup();
@@ -80,7 +80,7 @@ void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
        desc->pfn = __phys_to_pfn(base);
        desc->length = length;
-        desc->type = MT_DEVICE;
+        desc->type = MT_MEMORY_NONCACHED;
        pr_info("AT91: sram at 0x%lx of 0x%x mapped at 0x%lx\n",
                base, length, desc->virtual);
diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h
index 43a225f9e713..a1e1482c6da8 100644
--- a/arch/arm/mach-at91/soc.h
+++ b/arch/arm/mach-at91/soc.h
@@ -6,6 +6,7 @@
 struct at91_init_soc {
        int builtin;
+        u32 extern_irq;
        unsigned int *default_irq_priority;
        void (*map_io)(void);
        void (*ioremap_registers)(void);
diff --git a/arch/arm/mach-bcm/board_bcm.c b/arch/arm/mach-bcm/board_bcm.c
index 22e8421b1df3..28599326d4ad 100644
--- a/arch/arm/mach-bcm/board_bcm.c
+++ b/arch/arm/mach-bcm/board_bcm.c
@@ -15,7 +15,6 @@
 #include <linux/init.h>
 #include <linux/device.h>
 #include <linux/platform_device.h>
-#include <linux/irqchip.h>
 #include <linux/clocksource.h>
 #include <asm/mach/arch.h>
@@ -54,7 +53,6 @@ static void __init board_init(void)
 static const char * const bcm11351_dt_compat[] = { "bcm,bcm11351", NULL, };
 DT_MACHINE_START(BCM11351_DT, "Broadcom Application Processor")
-        .init_irq = irqchip_init,
        .init_time = clocksource_of_init,
        .init_machine = board_init,
        .dt_compat = bcm11351_dt_compat,
diff --git a/arch/arm/mach-bcm2835/bcm2835.c b/arch/arm/mach-bcm2835/bcm2835.c
index 740fa9ebe249..40686d7ef500 100644
--- a/arch/arm/mach-bcm2835/bcm2835.c
+++ b/arch/arm/mach-bcm2835/bcm2835.c
@@ -53,7 +53,7 @@ static void bcm2835_setup_restart(void)
        WARN(!wdt_regs, "failed to remap watchdog regs");
 }
-static void bcm2835_restart(char mode, const char *cmd)
+static void bcm2835_restart(enum reboot_mode mode, const char *cmd)
 {
        u32 val;
@@ -91,7 +91,7 @@ static void bcm2835_power_off(void)
        writel_relaxed(val, wdt_regs + PM_RSTS);
        /* Continue with normal reset mechanism */
-        bcm2835_restart(0, "");
+        bcm2835_restart(REBOOT_HARD, "");
 }
 static struct map_desc io_map __initdata = {
diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig
index 2d00165e85ec..01ad4d41e728 100644
--- a/arch/arm/mach-clps711x/Kconfig
+++ b/arch/arm/mach-clps711x/Kconfig
@@ -22,8 +22,7 @@ config ARCH_CLEP7312
 config ARCH_EDB7211
        bool "EDB7211"
-        select ARCH_SELECT_MEMORY_MODEL
+        select ARCH_HAS_HOLES_MEMORYMODEL
-        select ARCH_SPARSEMEM_ENABLE
        help
          Say Y here if you intend to run this kernel on a Cirrus Logic EDB-7211
          evaluation board.
diff --git a/arch/arm/mach-clps711x/Makefile b/arch/arm/mach-clps711x/Makefile
index 992995af666a..f30ed2b496fb 100644
--- a/arch/arm/mach-clps711x/Makefile
+++ b/arch/arm/mach-clps711x/Makefile
@@ -4,10 +4,7 @@
 # Object file lists.
-obj-y                   := common.o
+obj-y                           := common.o devices.o
-obj-m                   :=
-obj-n                   :=
-obj-                    :=
 obj-$(CONFIG_ARCH_AUTCPU12)     += board-autcpu12.o
 obj-$(CONFIG_ARCH_CDB89712)     += board-cdb89712.o
diff --git a/arch/arm/mach-clps711x/board-autcpu12.c b/arch/arm/mach-clps711x/board-autcpu12.c
index f38584709df7..5867aebd8d0c 100644
--- a/arch/arm/mach-clps711x/board-autcpu12.c
+++ b/arch/arm/mach-clps711x/board-autcpu12.c
@@ -26,6 +26,8 @@
 #include <linux/gpio.h>
 #include <linux/ioport.h>
 #include <linux/interrupt.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/plat-ram.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand-gpio.h>
 #include <linux/platform_device.h>
@@ -40,38 +42,49 @@
 #include <asm/page.h>
 #include <asm/mach/map.h>
-#include <mach/autcpu12.h>
 #include "common.h"
+#include "devices.h"
-#define AUTCPU12_CS8900_BASE    (CS2_PHYS_BASE + 0x300)
+/* NOR flash */
-#define AUTCPU12_CS8900_IRQ     (IRQ_EINT3)
+#define AUTCPU12_FLASH_BASE     (CS0_PHYS_BASE)
+/* Board specific hardware definitions */
+#define AUTCPU12_CHAR_LCD_BASE  (CS1_PHYS_BASE + 0x00000000)
+#define AUTCPU12_CSAUX1_BASE    (CS1_PHYS_BASE + 0x04000000)
+#define AUTCPU12_CAN_BASE       (CS1_PHYS_BASE + 0x08000000)
+#define AUTCPU12_TOUCH_BASE     (CS1_PHYS_BASE + 0x0a000000)
+#define AUTCPU12_IO_BASE        (CS1_PHYS_BASE + 0x0c000000)
+#define AUTCPU12_LPT_BASE       (CS1_PHYS_BASE + 0x0e000000)
+/* NVRAM */
+#define AUTCPU12_NVRAM_BASE     (CS1_PHYS_BASE + 0x02000000)
+/* SmartMedia flash */
 #define AUTCPU12_SMC_BASE       (CS1_PHYS_BASE + 0x06000000)
 #define AUTCPU12_SMC_SEL_BASE   (AUTCPU12_SMC_BASE + 0x10)
+/* Ethernet */
+#define AUTCPU12_CS8900_BASE    (CS2_PHYS_BASE + 0x300)
+#define AUTCPU12_CS8900_IRQ     (IRQ_EINT3)
+/* NAND flash */
 #define AUTCPU12_MMGPIO_BASE    (CLPS711X_NR_GPIO)
 #define AUTCPU12_SMC_NCE        (AUTCPU12_MMGPIO_BASE + 0) /* Bit 0 */
 #define AUTCPU12_SMC_RDY        CLPS711X_GPIO(1, 2)
 #define AUTCPU12_SMC_ALE        CLPS711X_GPIO(1, 3)
 #define AUTCPU12_SMC_CLE        CLPS711X_GPIO(1, 3)
+/* LCD contrast digital potentiometer */
+#define AUTCPU12_DPOT_CS        CLPS711X_GPIO(4, 0)
+#define AUTCPU12_DPOT_CLK       CLPS711X_GPIO(4, 1)
+#define AUTCPU12_DPOT_UD        CLPS711X_GPIO(4, 2)
 static struct resource autcpu12_cs8900_resource[] __initdata = {
        DEFINE_RES_MEM(AUTCPU12_CS8900_BASE, SZ_1K),
        DEFINE_RES_IRQ(AUTCPU12_CS8900_IRQ),
 };
-static struct resource autcpu12_nvram_resource[] __initdata = {
-        DEFINE_RES_MEM_NAMED(AUTCPU12_PHYS_NVRAM, SZ_128K, "SRAM"),
-};
-static struct platform_device autcpu12_nvram_pdev __initdata = {
-        .name           = "autcpu12_nvram",
-        .id             = -1,
-        .resource       = autcpu12_nvram_resource,
-        .num_resources  = ARRAY_SIZE(autcpu12_nvram_resource),
-};
 static struct resource autcpu12_nand_resource[] __initdata = {
        DEFINE_RES_MEM(AUTCPU12_SMC_BASE, SZ_16),
 };
@@ -147,17 +160,106 @@ static struct platform_device autcpu12_mmgpio_pdev __initdata = {
        },
 };
+static const struct gpio autcpu12_gpios[] __initconst = {
+        { AUTCPU12_DPOT_CS,     GPIOF_OUT_INIT_HIGH,    "DPOT CS" },
+        { AUTCPU12_DPOT_CLK,    GPIOF_OUT_INIT_LOW,     "DPOT CLK" },
+        { AUTCPU12_DPOT_UD,     GPIOF_OUT_INIT_LOW,     "DPOT UD" },
+};
+static struct mtd_partition autcpu12_flash_partitions[] = {
+        {
+                .name   = "NOR.0",
+                .offset = 0,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+static struct physmap_flash_data autcpu12_flash_pdata = {
+        .width          = 4,
+        .parts          = autcpu12_flash_partitions,
+        .nr_parts       = ARRAY_SIZE(autcpu12_flash_partitions),
+};
+static struct resource autcpu12_flash_resources[] __initdata = {
+        DEFINE_RES_MEM(AUTCPU12_FLASH_BASE, SZ_8M),
+};
+static struct platform_device autcpu12_flash_pdev __initdata = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .resource       = autcpu12_flash_resources,
+        .num_resources  = ARRAY_SIZE(autcpu12_flash_resources),
+        .dev            = {
+                .platform_data  = &autcpu12_flash_pdata,
+        },
+};
+static struct resource autcpu12_nvram_resource[] __initdata = {
+        DEFINE_RES_MEM(AUTCPU12_NVRAM_BASE, 0),
+};
+static struct platdata_mtd_ram autcpu12_nvram_pdata = {
+        .bankwidth      = 4,
+};
+static struct platform_device autcpu12_nvram_pdev __initdata = {
+        .name           = "mtd-ram",
+        .id             = 0,
+        .resource       = autcpu12_nvram_resource,
+        .num_resources  = ARRAY_SIZE(autcpu12_nvram_resource),
+        .dev            = {
+                .platform_data  = &autcpu12_nvram_pdata,
+        },
+};
+static void __init autcpu12_nvram_init(void)
+{
+        void __iomem *nvram;
+        unsigned int save[2];
+        resource_size_t nvram_size = SZ_128K;
+        /*
+         * Check for 32K/128K
+         * Read ofs 0K
+         * Read ofs 64K
+         * Write complement to ofs 64K
+         * Read and check result on ofs 0K
+         * Restore contents
+         */
+        nvram = ioremap(autcpu12_nvram_resource[0].start, SZ_128K);
+        if (nvram) {
+                save[0] = readl(nvram + 0);
+                save[1] = readl(nvram + SZ_64K);
+                writel(~save[0], nvram + SZ_64K);
+                if (readl(nvram + 0) != save[0]) {
+                        writel(save[0], nvram + 0);
+                        nvram_size = SZ_32K;
+                } else
+                        writel(save[1], nvram + SZ_64K);
+                iounmap(nvram);
+                autcpu12_nvram_resource[0].end =
+                        autcpu12_nvram_resource[0].start + nvram_size - 1;
+                platform_device_register(&autcpu12_nvram_pdev);
+        } else
+                pr_err("Failed to remap NVRAM resource\n");
+}
 static void __init autcpu12_init(void)
 {
+        clps711x_devices_init();
+        platform_device_register(&autcpu12_flash_pdev);
        platform_device_register_simple("video-clps711x", 0, NULL, 0);
        platform_device_register_simple("cs89x0", 0, autcpu12_cs8900_resource,
                                        ARRAY_SIZE(autcpu12_cs8900_resource));
        platform_device_register(&autcpu12_mmgpio_pdev);
-        platform_device_register(&autcpu12_nvram_pdev);
+        autcpu12_nvram_init();
 }
 static void __init autcpu12_init_late(void)
 {
+        gpio_request_array(autcpu12_gpios, ARRAY_SIZE(autcpu12_gpios));
        if (IS_ENABLED(MTD_NAND_GPIO) && IS_ENABLED(GPIO_GENERIC_PLATFORM)) {
                /* We are need both drivers to handle NAND */
                platform_device_register(&autcpu12_nand_pdev);
@@ -169,6 +271,7 @@ MACHINE_START(AUTCPU12, "autronix autcpu12")
        .atag_offset    = 0x20000,
        .nr_irqs        = CLPS711X_NR_IRQS,
        .map_io         = clps711x_map_io,
+        .init_early     = clps711x_init_early,
        .init_irq       = clps711x_init_irq,
        .init_time      = clps711x_timer_init,
        .init_machine   = autcpu12_init,
diff --git a/arch/arm/mach-clps711x/board-cdb89712.c b/arch/arm/mach-clps711x/board-cdb89712.c
index baab7da33c9b..a9e38c6bcfb4 100644
--- a/arch/arm/mach-clps711x/board-cdb89712.c
+++ b/arch/arm/mach-clps711x/board-cdb89712.c
@@ -39,6 +39,7 @@
 #include <asm/mach/map.h>
 #include "common.h"
+#include "devices.h"
 #define CDB89712_CS8900_BASE    (CS2_PHYS_BASE + 0x300)
 #define CDB89712_CS8900_IRQ     (IRQ_EINT3)
@@ -127,6 +128,7 @@ static struct platform_device cdb89712_sram_pdev __initdata = {
 static void __init cdb89712_init(void)
 {
+        clps711x_devices_init();
        platform_device_register(&cdb89712_flash_pdev);
        platform_device_register(&cdb89712_bootrom_pdev);
        platform_device_register(&cdb89712_sram_pdev);
@@ -139,6 +141,7 @@ MACHINE_START(CDB89712, "Cirrus-CDB89712")
        .atag_offset    = 0x100,
        .nr_irqs        = CLPS711X_NR_IRQS,
        .map_io         = clps711x_map_io,
+        .init_early     = clps711x_init_early,
        .init_irq       = clps711x_init_irq,
        .init_time      = clps711x_timer_init,
        .init_machine   = cdb89712_init,
diff --git a/arch/arm/mach-clps711x/board-clep7312.c b/arch/arm/mach-clps711x/board-clep7312.c
index 014aa3c19a03..b4764246d0f8 100644
--- a/arch/arm/mach-clps711x/board-clep7312.c
+++ b/arch/arm/mach-clps711x/board-clep7312.c
@@ -39,6 +39,7 @@ MACHINE_START(CLEP7212, "Cirrus Logic 7212/7312")
        .nr_irqs        = CLPS711X_NR_IRQS,
        .fixup          = fixup_clep7312,
        .map_io         = clps711x_map_io,
+        .init_early     = clps711x_init_early,
        .init_irq       = clps711x_init_irq,
        .init_time      = clps711x_timer_init,
        .handle_irq     = clps711x_handle_irq,
diff --git a/arch/arm/mach-clps711x/board-edb7211.c b/arch/arm/mach-clps711x/board-edb7211.c
index 5f928e9ed2ef..9dfb990f0801 100644
--- a/arch/arm/mach-clps711x/board-edb7211.c
+++ b/arch/arm/mach-clps711x/board-edb7211.c
@@ -12,6 +12,7 @@
 #include <linux/delay.h>
 #include <linux/memblock.h>
 #include <linux/types.h>
+#include <linux/i2c-gpio.h>
 #include <linux/interrupt.h>
 #include <linux/backlight.h>
 #include <linux/platform_device.h>
@@ -29,6 +30,7 @@
 #include <mach/hardware.h>
 #include "common.h"
+#include "devices.h"
 #define VIDEORAM_SIZE           SZ_128K
@@ -36,11 +38,24 @@
 #define EDB7211_LCDEN           CLPS711X_GPIO(3, 2)
 #define EDB7211_LCDBL           CLPS711X_GPIO(3, 3)
+#define EDB7211_I2C_SDA         CLPS711X_GPIO(3, 4)
+#define EDB7211_I2C_SCL         CLPS711X_GPIO(3, 5)
 #define EDB7211_FLASH0_BASE     (CS0_PHYS_BASE)
 #define EDB7211_FLASH1_BASE     (CS1_PHYS_BASE)
 #define EDB7211_CS8900_BASE     (CS2_PHYS_BASE + 0x300)
 #define EDB7211_CS8900_IRQ      (IRQ_EINT3)
+/* The extra 8 lines of the keyboard matrix */
+#define EDB7211_EXTKBD_BASE     (CS3_PHYS_BASE)
+static struct i2c_gpio_platform_data edb7211_i2c_pdata __initdata = {
+        .sda_pin        = EDB7211_I2C_SDA,
+        .scl_pin        = EDB7211_I2C_SCL,
+        .scl_is_output_only = 1,
+};
 static struct resource edb7211_cs8900_resource[] __initdata = {
        DEFINE_RES_MEM(EDB7211_CS8900_BASE, SZ_1K),
        DEFINE_RES_IRQ(EDB7211_CS8900_IRQ),
@@ -94,13 +109,14 @@ static struct plat_lcd_data edb7211_lcd_power_pdata = {
 static void edb7211_lcd_backlight_set_intensity(int intensity)
 {
-        gpio_set_value(EDB7211_LCDBL, intensity);
+        gpio_set_value(EDB7211_LCDBL, !!intensity);
+        clps_writel((clps_readl(PMPCON) & 0xf0ff) | (intensity << 8), PMPCON);
 }
 static struct generic_bl_info edb7211_lcd_backlight_pdata = {
        .name                   = "lcd-backlight.0",
        .default_intensity      = 0x01,
-        .max_intensity          = 0x01,
+        .max_intensity          = 0x0f,
        .set_bl_intensity       = edb7211_lcd_backlight_set_intensity,
 };
@@ -112,8 +128,8 @@ static struct gpio edb7211_gpios[] __initconst = {
 static struct map_desc edb7211_io_desc[] __initdata = {
        {       /* Memory-mapped extra keyboard row */
-                .virtual        = IO_ADDRESS(EP7211_PHYS_EXTKBD),
+                .virtual        = IO_ADDRESS(EDB7211_EXTKBD_BASE),
-                .pfn            = __phys_to_pfn(EP7211_PHYS_EXTKBD),
+                .pfn            = __phys_to_pfn(EDB7211_EXTKBD_BASE),
                .length         = SZ_1M,
                .type           = MT_DEVICE,
        },
@@ -151,6 +167,11 @@ fixup_edb7211(struct tag *tags, char **cmdline, struct meminfo *mi)
 static void __init edb7211_init(void)
 {
+        clps711x_devices_init();
+}
+static void __init edb7211_init_late(void)
+{
        gpio_request_array(edb7211_gpios, ARRAY_SIZE(edb7211_gpios));
        platform_device_register(&edb7211_flash_pdev);
@@ -163,6 +184,9 @@ static void __init edb7211_init(void)
        platform_device_register_simple("video-clps711x", 0, NULL, 0);
        platform_device_register_simple("cs89x0", 0, edb7211_cs8900_resource,
                                        ARRAY_SIZE(edb7211_cs8900_resource));
+        platform_device_register_data(&platform_bus, "i2c-gpio", 0,
+                                      &edb7211_i2c_pdata,
+                                      sizeof(edb7211_i2c_pdata));
 }
 MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
@@ -172,9 +196,11 @@ MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
        .fixup          = fixup_edb7211,
        .reserve        = edb7211_reserve,
        .map_io         = edb7211_map_io,
+        .init_early     = clps711x_init_early,
        .init_irq       = clps711x_init_irq,
        .init_time      = clps711x_timer_init,
        .init_machine   = edb7211_init,
+        .init_late      = edb7211_init_late,
        .handle_irq     = clps711x_handle_irq,
        .restart        = clps711x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-clps711x/board-fortunet.c b/arch/arm/mach-clps711x/board-fortunet.c
index c5675efc8c6a..b1561e3d7c5c 100644
--- a/arch/arm/mach-clps711x/board-fortunet.c
+++ b/arch/arm/mach-clps711x/board-fortunet.c
@@ -77,6 +77,7 @@ MACHINE_START(FORTUNET, "ARM-FortuNet")
        .nr_irqs        = CLPS711X_NR_IRQS,
        .fixup          = fortunet_fixup,
        .map_io         = clps711x_map_io,
+        .init_early     = clps711x_init_early,
        .init_irq       = clps711x_init_irq,
        .init_time      = clps711x_timer_init,
        .handle_irq     = clps711x_handle_irq,
diff --git a/arch/arm/mach-clps711x/board-p720t.c b/arch/arm/mach-clps711x/board-p720t.c
index 8d3ee6771135..dd81b06f68fe 100644
--- a/arch/arm/mach-clps711x/board-p720t.c
+++ b/arch/arm/mach-clps711x/board-p720t.c
@@ -23,10 +23,12 @@
 #include <linux/string.h>
 #include <linux/mm.h>
 #include <linux/io.h>
+#include <linux/gpio.h>
 #include <linux/slab.h>
 #include <linux/leds.h>
 #include <linux/sizes.h>
 #include <linux/backlight.h>
+#include <linux/basic_mmio_gpio.h>
 #include <linux/platform_device.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand-gpio.h>
@@ -38,11 +40,11 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <mach/syspld.h>
 #include <video/platform_lcd.h>
 #include "common.h"
+#include "devices.h"
 #define P720T_USERLED           CLPS711X_GPIO(3, 0)
 #define P720T_NAND_CLE          CLPS711X_GPIO(4, 0)
@@ -51,6 +53,178 @@
 #define P720T_NAND_BASE         (CLPS711X_SDRAM1_BASE)
+#define P720T_MMGPIO_BASE       (CLPS711X_NR_GPIO)
+#define SYSPLD_PHYS_BASE        IOMEM(CS1_PHYS_BASE)
+#define PLD_INT                 (SYSPLD_PHYS_BASE + 0x000000)
+#define PLD_INT_MMGPIO_BASE     (P720T_MMGPIO_BASE + 0)
+#define PLD_INT_PENIRQ          (PLD_INT_MMGPIO_BASE + 5)
+#define PLD_INT_UCB_IRQ         (PLD_INT_MMGPIO_BASE + 1)
+#define PLD_INT_KBD_ATN         (PLD_INT_MMGPIO_BASE + 0) /* EINT1 */
+#define PLD_PWR                 (SYSPLD_PHYS_BASE + 0x000004)
+#define PLD_PWR_MMGPIO_BASE     (P720T_MMGPIO_BASE + 8)
+#define PLD_PWR_EXT             (PLD_PWR_MMGPIO_BASE + 5)
+#define PLD_PWR_MODE            (PLD_PWR_MMGPIO_BASE + 4) /* 1 = PWM, 0 = PFM */
+#define PLD_S4_ON               (PLD_PWR_MMGPIO_BASE + 3) /* LCD bias voltage enable */
+#define PLD_S3_ON               (PLD_PWR_MMGPIO_BASE + 2) /* LCD backlight enable */
+#define PLD_S2_ON               (PLD_PWR_MMGPIO_BASE + 1) /* LCD 3V3 supply enable */
+#define PLD_S1_ON               (PLD_PWR_MMGPIO_BASE + 0) /* LCD 3V supply enable */
+#define PLD_KBD                 (SYSPLD_PHYS_BASE + 0x000008)
+#define PLD_KBD_MMGPIO_BASE     (P720T_MMGPIO_BASE + 16)
+#define PLD_KBD_WAKE            (PLD_KBD_MMGPIO_BASE + 1)
+#define PLD_KBD_EN              (PLD_KBD_MMGPIO_BASE + 0)
+#define PLD_SPI                 (SYSPLD_PHYS_BASE + 0x00000c)
+#define PLD_SPI_MMGPIO_BASE     (P720T_MMGPIO_BASE + 24)
+#define PLD_SPI_EN              (PLD_SPI_MMGPIO_BASE + 0)
+#define PLD_IO                  (SYSPLD_PHYS_BASE + 0x000010)
+#define PLD_IO_MMGPIO_BASE      (P720T_MMGPIO_BASE + 32)
+#define PLD_IO_BOOTSEL          (PLD_IO_MMGPIO_BASE + 6) /* Boot sel switch */
+#define PLD_IO_USER             (PLD_IO_MMGPIO_BASE + 5) /* User defined switch */
+#define PLD_IO_LED3             (PLD_IO_MMGPIO_BASE + 4)
+#define PLD_IO_LED2             (PLD_IO_MMGPIO_BASE + 3)
+#define PLD_IO_LED1             (PLD_IO_MMGPIO_BASE + 2)
+#define PLD_IO_LED0             (PLD_IO_MMGPIO_BASE + 1)
+#define PLD_IO_LEDEN            (PLD_IO_MMGPIO_BASE + 0)
+#define PLD_IRDA                (SYSPLD_PHYS_BASE + 0x000014)
+#define PLD_IRDA_MMGPIO_BASE    (P720T_MMGPIO_BASE + 40)
+#define PLD_IRDA_EN             (PLD_IRDA_MMGPIO_BASE + 0)
+#define PLD_COM2                (SYSPLD_PHYS_BASE + 0x000018)
+#define PLD_COM2_MMGPIO_BASE    (P720T_MMGPIO_BASE + 48)
+#define PLD_COM2_EN             (PLD_COM2_MMGPIO_BASE + 0)
+#define PLD_COM1                (SYSPLD_PHYS_BASE + 0x00001c)
+#define PLD_COM1_MMGPIO_BASE    (P720T_MMGPIO_BASE + 56)
+#define PLD_COM1_EN             (PLD_COM1_MMGPIO_BASE + 0)
+#define PLD_AUD                 (SYSPLD_PHYS_BASE + 0x000020)
+#define PLD_AUD_MMGPIO_BASE     (P720T_MMGPIO_BASE + 64)
+#define PLD_AUD_DIV1            (PLD_AUD_MMGPIO_BASE + 6)
+#define PLD_AUD_DIV0            (PLD_AUD_MMGPIO_BASE + 5)
+#define PLD_AUD_CLK_SEL1        (PLD_AUD_MMGPIO_BASE + 4)
+#define PLD_AUD_CLK_SEL0        (PLD_AUD_MMGPIO_BASE + 3)
+#define PLD_AUD_MIC_PWR         (PLD_AUD_MMGPIO_BASE + 2)
+#define PLD_AUD_MIC_GAIN        (PLD_AUD_MMGPIO_BASE + 1)
+#define PLD_AUD_CODEC_EN        (PLD_AUD_MMGPIO_BASE + 0)
+#define PLD_CF                  (SYSPLD_PHYS_BASE + 0x000024)
+#define PLD_CF_MMGPIO_BASE      (P720T_MMGPIO_BASE + 72)
+#define PLD_CF2_SLEEP           (PLD_CF_MMGPIO_BASE + 5)
+#define PLD_CF1_SLEEP           (PLD_CF_MMGPIO_BASE + 4)
+#define PLD_CF2_nPDREQ          (PLD_CF_MMGPIO_BASE + 3)
+#define PLD_CF1_nPDREQ          (PLD_CF_MMGPIO_BASE + 2)
+#define PLD_CF2_nIRQ            (PLD_CF_MMGPIO_BASE + 1)
+#define PLD_CF1_nIRQ            (PLD_CF_MMGPIO_BASE + 0)
+#define PLD_SDC                 (SYSPLD_PHYS_BASE + 0x000028)
+#define PLD_SDC_MMGPIO_BASE     (P720T_MMGPIO_BASE + 80)
+#define PLD_SDC_INT_EN          (PLD_SDC_MMGPIO_BASE + 2)
+#define PLD_SDC_WP              (PLD_SDC_MMGPIO_BASE + 1)
+#define PLD_SDC_CD              (PLD_SDC_MMGPIO_BASE + 0)
+#define PLD_CODEC               (SYSPLD_PHYS_BASE + 0x400000)
+#define PLD_CODEC_MMGPIO_BASE   (P720T_MMGPIO_BASE + 88)
+#define PLD_CODEC_IRQ3          (PLD_CODEC_MMGPIO_BASE + 4)
+#define PLD_CODEC_IRQ2          (PLD_CODEC_MMGPIO_BASE + 3)
+#define PLD_CODEC_IRQ1          (PLD_CODEC_MMGPIO_BASE + 2)
+#define PLD_CODEC_EN            (PLD_CODEC_MMGPIO_BASE + 0)
+#define PLD_BRITE               (SYSPLD_PHYS_BASE + 0x400004)
+#define PLD_BRITE_MMGPIO_BASE   (P720T_MMGPIO_BASE + 96)
+#define PLD_BRITE_UP            (PLD_BRITE_MMGPIO_BASE + 1)
+#define PLD_BRITE_DN            (PLD_BRITE_MMGPIO_BASE + 0)
+#define PLD_LCDEN               (SYSPLD_PHYS_BASE + 0x400008)
+#define PLD_LCDEN_MMGPIO_BASE   (P720T_MMGPIO_BASE + 104)
+#define PLD_LCDEN_EN            (PLD_LCDEN_MMGPIO_BASE + 0)
+#define PLD_TCH                 (SYSPLD_PHYS_BASE + 0x400010)
+#define PLD_TCH_MMGPIO_BASE     (P720T_MMGPIO_BASE + 112)
+#define PLD_TCH_PENIRQ          (PLD_TCH_MMGPIO_BASE + 1)
+#define PLD_TCH_EN              (PLD_TCH_MMGPIO_BASE + 0)
+#define PLD_GPIO                (SYSPLD_PHYS_BASE + 0x400014)
+#define PLD_GPIO_MMGPIO_BASE    (P720T_MMGPIO_BASE + 120)
+#define PLD_GPIO2               (PLD_GPIO_MMGPIO_BASE + 2)
+#define PLD_GPIO1               (PLD_GPIO_MMGPIO_BASE + 1)
+#define PLD_GPIO0               (PLD_GPIO_MMGPIO_BASE + 0)
+static struct gpio p720t_gpios[] __initconst = {
+        { PLD_S1_ON,    GPIOF_OUT_INIT_LOW,     "PLD_S1_ON" },
+        { PLD_S2_ON,    GPIOF_OUT_INIT_LOW,     "PLD_S2_ON" },
+        { PLD_S3_ON,    GPIOF_OUT_INIT_LOW,     "PLD_S3_ON" },
+        { PLD_S4_ON,    GPIOF_OUT_INIT_LOW,     "PLD_S4_ON" },
+        { PLD_KBD_EN,   GPIOF_OUT_INIT_LOW,     "PLD_KBD_EN" },
+        { PLD_SPI_EN,   GPIOF_OUT_INIT_LOW,     "PLD_SPI_EN" },
+        { PLD_IO_USER,  GPIOF_OUT_INIT_LOW,     "PLD_IO_USER" },
+        { PLD_IO_LED0,  GPIOF_OUT_INIT_LOW,     "PLD_IO_LED0" },
+        { PLD_IO_LED1,  GPIOF_OUT_INIT_LOW,     "PLD_IO_LED1" },
+        { PLD_IO_LED2,  GPIOF_OUT_INIT_LOW,     "PLD_IO_LED2" },
+        { PLD_IO_LED3,  GPIOF_OUT_INIT_LOW,     "PLD_IO_LED3" },
+        { PLD_IO_LEDEN, GPIOF_OUT_INIT_LOW,     "PLD_IO_LEDEN" },
+        { PLD_IRDA_EN,  GPIOF_OUT_INIT_LOW,     "PLD_IRDA_EN" },
+        { PLD_COM1_EN,  GPIOF_OUT_INIT_HIGH,    "PLD_COM1_EN" },
+        { PLD_COM2_EN,  GPIOF_OUT_INIT_HIGH,    "PLD_COM2_EN" },
+        { PLD_CODEC_EN, GPIOF_OUT_INIT_LOW,     "PLD_CODEC_EN" },
+        { PLD_LCDEN_EN, GPIOF_OUT_INIT_LOW,     "PLD_LCDEN_EN" },
+        { PLD_TCH_EN,   GPIOF_OUT_INIT_LOW,     "PLD_TCH_EN" },
+        { P720T_USERLED,GPIOF_OUT_INIT_LOW,     "USER_LED" },
+};
+static struct resource p720t_mmgpio_resource[] __initdata = {
+        DEFINE_RES_MEM_NAMED(0, 4, "dat"),
+};
+static struct bgpio_pdata p720t_mmgpio_pdata = {
+        .ngpio  = 8,
+};
+static struct platform_device p720t_mmgpio __initdata = {
+        .name           = "basic-mmio-gpio",
+        .id             = -1,
+        .resource       = p720t_mmgpio_resource,
+        .num_resources  = ARRAY_SIZE(p720t_mmgpio_resource),
+        .dev            = {
+                .platform_data  = &p720t_mmgpio_pdata,
+        },
+};
+static void __init p720t_mmgpio_init(void __iomem *addrbase, int gpiobase)
+{
+        p720t_mmgpio_resource[0].start = (unsigned long)addrbase;
+        p720t_mmgpio_pdata.base = gpiobase;
+        platform_device_register(&p720t_mmgpio);
+}
+static struct {
+        void __iomem    *addrbase;
+        int             gpiobase;
+} mmgpios[] __initconst = {
+        { PLD_INT,      PLD_INT_MMGPIO_BASE },
+        { PLD_PWR,      PLD_PWR_MMGPIO_BASE },
+        { PLD_KBD,      PLD_KBD_MMGPIO_BASE },
+        { PLD_SPI,      PLD_SPI_MMGPIO_BASE },
+        { PLD_IO,       PLD_IO_MMGPIO_BASE },
+        { PLD_IRDA,     PLD_IRDA_MMGPIO_BASE },
+        { PLD_COM2,     PLD_COM2_MMGPIO_BASE },
+        { PLD_COM1,     PLD_COM1_MMGPIO_BASE },
+        { PLD_AUD,      PLD_AUD_MMGPIO_BASE },
+        { PLD_CF,       PLD_CF_MMGPIO_BASE },
+        { PLD_SDC,      PLD_SDC_MMGPIO_BASE },
+        { PLD_CODEC,    PLD_CODEC_MMGPIO_BASE },
+        { PLD_BRITE,    PLD_BRITE_MMGPIO_BASE },
+        { PLD_LCDEN,    PLD_LCDEN_MMGPIO_BASE },
+        { PLD_TCH,      PLD_TCH_MMGPIO_BASE },
+        { PLD_GPIO,     PLD_GPIO_MMGPIO_BASE },
+};
 static struct resource p720t_nand_resource[] __initdata = {
        DEFINE_RES_MEM(P720T_NAND_BASE, SZ_4),
 };
@@ -92,11 +266,15 @@ static struct platform_device p720t_nand_pdev __initdata = {
 static void p720t_lcd_power_set(struct plat_lcd_data *pd, unsigned int power)
 {
        if (power) {
-                PLD_LCDEN = PLD_LCDEN_EN;
+                gpio_set_value(PLD_LCDEN_EN, 1);
-                PLD_PWR |= PLD_S4_ON | PLD_S2_ON | PLD_S1_ON;
+                gpio_set_value(PLD_S1_ON, 1);
+                gpio_set_value(PLD_S2_ON, 1);
+                gpio_set_value(PLD_S4_ON, 1);
        } else {
-                PLD_PWR &= ~(PLD_S4_ON | PLD_S2_ON | PLD_S1_ON);
+                gpio_set_value(PLD_S1_ON, 0);
-                PLD_LCDEN = 0;
+                gpio_set_value(PLD_S2_ON, 0);
+                gpio_set_value(PLD_S4_ON, 0);
+                gpio_set_value(PLD_LCDEN_EN, 0);
        }
 }
@@ -106,10 +284,7 @@ static struct plat_lcd_data p720t_lcd_power_pdata = {
 static void p720t_lcd_backlight_set_intensity(int intensity)
 {
-        if (intensity)
+        gpio_set_value(PLD_S3_ON, intensity);
-                PLD_PWR |= PLD_S3_ON;
-        else
-                PLD_PWR = 0;
 }
 static struct generic_bl_info p720t_lcd_backlight_pdata = {
@@ -119,19 +294,6 @@ static struct generic_bl_info p720t_lcd_backlight_pdata = {
        .set_bl_intensity       = p720t_lcd_backlight_set_intensity,
 };
-/*
- * Map the P720T system PLD. It occupies two address spaces:
- * 0x10000000 and 0x10400000. We map both regions as one.
- */
-static struct map_desc p720t_io_desc[] __initdata = {
-        {
-                .virtual        = SYSPLD_VIRT_BASE,
-                .pfn            = __phys_to_pfn(SYSPLD_PHYS_BASE),
-                .length         = SZ_8M,
-                .type           = MT_DEVICE,
-        },
-};
 static void __init
 fixup_p720t(struct tag *tag, char **cmdline, struct meminfo *mi)
 {
@@ -157,33 +319,6 @@ fixup_p720t(struct tag *tag, char **cmdline, struct meminfo *mi)
        }
 }
-static void __init p720t_map_io(void)
-{
-        clps711x_map_io();
-        iotable_init(p720t_io_desc, ARRAY_SIZE(p720t_io_desc));
-}
-static void __init p720t_init_early(void)
-{
-        /*
-         * Power down as much as possible in case we don't
-         * have the drivers loaded.
-         */
-        PLD_LCDEN = 0;
-        PLD_PWR  &= ~(PLD_S4_ON|PLD_S3_ON|PLD_S2_ON|PLD_S1_ON);
-        PLD_KBD   = 0;
-        PLD_IO    = 0;
-        PLD_IRDA  = 0;
-        PLD_CODEC = 0;
-        PLD_TCH   = 0;
-        PLD_SPI   = 0;
-        if (!IS_ENABLED(CONFIG_DEBUG_LL)) {
-                PLD_COM2 = 0;
-                PLD_COM1 = 0;
-        }
-}
 static struct gpio_led p720t_gpio_leds[] = {
        {
                .name                   = "User LED",
@@ -199,7 +334,20 @@ static struct gpio_led_platform_data p720t_gpio_led_pdata __initdata = {
 static void __init p720t_init(void)
 {
+        int i;
+        clps711x_devices_init();
+        for (i = 0; i < ARRAY_SIZE(mmgpios); i++)
+                p720t_mmgpio_init(mmgpios[i].addrbase, mmgpios[i].gpiobase);
        platform_device_register(&p720t_nand_pdev);
+}
+static void __init p720t_init_late(void)
+{
+        WARN_ON(gpio_request_array(p720t_gpios, ARRAY_SIZE(p720t_gpios)));
        platform_device_register_data(&platform_bus, "platform-lcd", 0,
                                      &p720t_lcd_power_pdata,
                                      sizeof(p720t_lcd_power_pdata));
@@ -207,10 +355,6 @@ static void __init p720t_init(void)
                                      &p720t_lcd_backlight_pdata,
                                      sizeof(p720t_lcd_backlight_pdata));
        platform_device_register_simple("video-clps711x", 0, NULL, 0);
-}
-static void __init p720t_init_late(void)
-{
        platform_device_register_data(&platform_bus, "leds-gpio", 0,
                                      &p720t_gpio_led_pdata,
                                      sizeof(p720t_gpio_led_pdata));
@@ -221,8 +365,8 @@ MACHINE_START(P720T, "ARM-Prospector720T")
        .atag_offset    = 0x100,
        .nr_irqs        = CLPS711X_NR_IRQS,
        .fixup          = fixup_p720t,
-        .map_io         = p720t_map_io,
+        .map_io         = clps711x_map_io,
-        .init_early     = p720t_init_early,
+        .init_early     = clps711x_init_early,
        .init_irq       = clps711x_init_irq,
        .init_time      = clps711x_timer_init,
        .init_machine   = p720t_init,
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index 20ff50f3ccf0..4ca2f3ca2de4 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -27,12 +27,14 @@
 #include <linux/clk.h>
 #include <linux/clkdev.h>
 #include <linux/clockchips.h>
+#include <linux/clocksource.h>
 #include <linux/clk-provider.h>
 #include <asm/exception.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
+#include <asm/sched_clock.h>
 #include <asm/system_misc.h>
 #include <mach/hardware.h>
@@ -213,7 +215,7 @@ void __init clps711x_init_irq(void)
        }
 }
-inline u32 fls16(u32 x)
+static inline u32 fls16(u32 x)
 {
        u32 r = 15;
@@ -237,27 +239,52 @@ inline u32 fls16(u32 x)
 asmlinkage void __exception_irq_entry clps711x_handle_irq(struct pt_regs *regs)
 {
-        u32 irqstat;
+        do {
-        void __iomem *base = CLPS711X_VIRT_BASE;
+                u32 irqstat;
+                void __iomem *base = CLPS711X_VIRT_BASE;
-        irqstat = readl_relaxed(base + INTSR1) & readl_relaxed(base + INTMR1);
-        if (irqstat) {
+                irqstat = readw_relaxed(base + INTSR1) &
-                handle_IRQ(fls16(irqstat), regs);
+                          readw_relaxed(base + INTMR1);
-                return;
+                if (irqstat)
-        }
+                        handle_IRQ(fls16(irqstat), regs);
+                irqstat = readw_relaxed(base + INTSR2) &
+                          readw_relaxed(base + INTMR2);
+                if (irqstat) {
+                        handle_IRQ(fls16(irqstat) + 16, regs);
+                        continue;
+                }
+                break;
+        } while (1);
+}
-        irqstat = readl_relaxed(base + INTSR2) & readl_relaxed(base + INTMR2);
+static u32 notrace clps711x_sched_clock_read(void)
-        if (likely(irqstat))
+{
-                handle_IRQ(fls16(irqstat) + 16, regs);
+        return ~readw_relaxed(CLPS711X_VIRT_BASE + TC1D);
 }
 static void clps711x_clockevent_set_mode(enum clock_event_mode mode,
                                         struct clock_event_device *evt)
 {
+        disable_irq(IRQ_TC2OI);
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                enable_irq(IRQ_TC2OI);
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+                /* Not supported */
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_RESUME:
+                /* Left event sources disabled, no more interrupts appear */
+                break;
+        }
 }
 static struct clock_event_device clockevent_clps711x = {
-        .name           = "CLPS711x Clockevents",
+        .name           = "clps711x-clockevent",
        .rating         = 300,
        .features       = CLOCK_EVT_FEAT_PERIODIC,
        .set_mode       = clps711x_clockevent_set_mode,
@@ -271,8 +298,8 @@ static irqreturn_t clps711x_timer_interrupt(int irq, void *dev_id)
 }
 static struct irqaction clps711x_timer_irq = {
-        .name           = "CLPS711x Timer Tick",
+        .name           = "clps711x-timer",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .flags          = IRQF_TIMER | IRQF_IRQPOLL,
        .handler        = clps711x_timer_interrupt,
 };
@@ -301,6 +328,7 @@ void __init clps711x_timer_init(void)
                cpu = ext;
                bus = cpu;
                spi = 135400;
+                pll = 0;
        } else {
                cpu = pll;
                if (cpu >= 36864000)
@@ -319,9 +347,9 @@ void __init clps711x_timer_init(void)
                else
                        timh = 541440;
        } else
-                timh = cpu / 144;
+                timh = DIV_ROUND_CLOSEST(cpu, 144);
-        timl = timh / 256;
+        timl = DIV_ROUND_CLOSEST(timh, 256);
        /* All clocks are fixed */
        add_fixed_clk(clk_pll, "pll", pll);
@@ -334,18 +362,29 @@ void __init clps711x_timer_init(void)
        pr_info("CPU frequency set at %i Hz.\n", cpu);
+        /* Start Timer1 in free running mode (Low frequency) */
+        tmp = clps_readl(SYSCON1) & ~(SYSCON1_TC1S | SYSCON1_TC1M);
+        clps_writel(tmp, SYSCON1);
+        setup_sched_clock(clps711x_sched_clock_read, 16, timl);
+        clocksource_mmio_init(CLPS711X_VIRT_BASE + TC1D,
+                              "clps711x_clocksource", timl, 300, 16,
+                              clocksource_mmio_readw_down);
+        /* Set Timer2 prescaler */
        clps_writew(DIV_ROUND_CLOSEST(timh, HZ), TC2D);
-        tmp = clps_readl(SYSCON1);
+        /* Start Timer2 in prescale mode (High frequency)*/
-        tmp |= SYSCON1_TC2S | SYSCON1_TC2M;
+        tmp = clps_readl(SYSCON1) | SYSCON1_TC2M | SYSCON1_TC2S;
        clps_writel(tmp, SYSCON1);
-        clockevents_config_and_register(&clockevent_clps711x, timh, 1, 0xffff);
+        clockevents_config_and_register(&clockevent_clps711x, timh, 0, 0);
        setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
 }
-void clps711x_restart(char mode, const char *cmd)
+void clps711x_restart(enum reboot_mode mode, const char *cmd)
 {
        soft_restart(0);
 }
@@ -353,15 +392,11 @@ void clps711x_restart(char mode, const char *cmd)
 static void clps711x_idle(void)
 {
        clps_writel(1, HALT);
-        __asm__ __volatile__(
+        asm("mov r0, r0");
-        "mov    r0, r0\n\
+        asm("mov r0, r0");
-        mov     r0, r0");
 }
-static int __init clps711x_idle_init(void)
+void __init clps711x_init_early(void)
 {
        arm_pm_idle = clps711x_idle;
-        return 0;
 }
-arch_initcall(clps711x_idle_init);
diff --git a/arch/arm/mach-clps711x/common.h b/arch/arm/mach-clps711x/common.h
index f84a7292c70e..9a6767bfdc47 100644
--- a/arch/arm/mach-clps711x/common.h
+++ b/arch/arm/mach-clps711x/common.h
@@ -4,6 +4,8 @@
 * Common bits.
 */
+#include <linux/reboot.h>
 #define CLPS711X_NR_IRQS        (33)
 #define CLPS711X_NR_GPIO        (4 * 8 + 3)
 #define CLPS711X_GPIO(prt, bit) ((prt) * 8 + (bit))
@@ -12,4 +14,5 @@ extern void clps711x_map_io(void);
 extern void clps711x_init_irq(void);
 extern void clps711x_timer_init(void);
 extern void clps711x_handle_irq(struct pt_regs *regs);
-extern void clps711x_restart(char mode, const char *cmd);
+extern void clps711x_restart(enum reboot_mode mode, const char *cmd);
+extern void clps711x_init_early(void);
diff --git a/arch/arm/mach-clps711x/devices.c b/arch/arm/mach-clps711x/devices.c
new file mode 100644
index 000000000000..856b81cf2f8a
--- /dev/null
+++ b/arch/arm/mach-clps711x/devices.c
@@ -0,0 +1,68 @@
+/*
+ *  CLPS711X common devices definitions
+ *
+ *  Author: Alexander Shiyan <shc_work@mail.ru>, 2013
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/platform_device.h>
+#include <linux/sizes.h>
+#include <mach/hardware.h>
+static const phys_addr_t clps711x_gpios[][2] __initconst = {
+        { PADR, PADDR },
+        { PBDR, PBDDR },
+        { PCDR, PCDDR },
+        { PDDR, PDDDR },
+        { PEDR, PEDDR },
+};
+static void __init clps711x_add_gpio(void)
+{
+        unsigned i;
+        struct resource gpio_res[2];
+        memset(gpio_res, 0, sizeof(gpio_res));
+        gpio_res[0].flags = IORESOURCE_MEM;
+        gpio_res[1].flags = IORESOURCE_MEM;
+        for (i = 0; i < ARRAY_SIZE(clps711x_gpios); i++) {
+                gpio_res[0].start = CLPS711X_PHYS_BASE + clps711x_gpios[i][0];
+                gpio_res[0].end = gpio_res[0].start;
+                gpio_res[1].start = CLPS711X_PHYS_BASE + clps711x_gpios[i][1];
+                gpio_res[1].end = gpio_res[1].start;
+                platform_device_register_simple("clps711x-gpio", i,
+                                                gpio_res, ARRAY_SIZE(gpio_res));
+        }
+}
+const struct resource clps711x_syscon_res[] __initconst = {
+        /* SYSCON1, SYSFLG1 */
+        DEFINE_RES_MEM(CLPS711X_PHYS_BASE + SYSCON1, SZ_128),
+        /* SYSCON2, SYSFLG2 */
+        DEFINE_RES_MEM(CLPS711X_PHYS_BASE + SYSCON2, SZ_128),
+        /* SYSCON3 */
+        DEFINE_RES_MEM(CLPS711X_PHYS_BASE + SYSCON3, SZ_64),
+};
+static void __init clps711x_add_syscon(void)
+{
+        unsigned i;
+        for (i = 0; i < ARRAY_SIZE(clps711x_syscon_res); i++)
+                platform_device_register_simple("clps711x-syscon", i + 1,
+                                                &clps711x_syscon_res[i], 1);
+}
+void __init clps711x_devices_init(void)
+{
+        clps711x_add_gpio();
+        clps711x_add_syscon();
+}
diff --git a/arch/arm/mach-clps711x/devices.h b/arch/arm/mach-clps711x/devices.h
new file mode 100644
index 000000000000..a5efc1744b84
--- /dev/null
+++ b/arch/arm/mach-clps711x/devices.h
@@ -0,0 +1,12 @@
+/*
+ *  CLPS711X common devices definitions
+ *
+ *  Copyright (C) 2013 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+void clps711x_devices_init(void);
diff --git a/arch/arm/mach-clps711x/include/mach/autcpu12.h b/arch/arm/mach-clps711x/include/mach/autcpu12.h
deleted file mode 100644
index 0452f5f3f034..000000000000
--- a/arch/arm/mach-clps711x/include/mach/autcpu12.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * AUTCPU12 specific defines
- *
- * (c) 2001 Thomas Gleixner, autronix automation <gleixner@autronix.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_AUTCPU12_H
-#define __ASM_ARCH_AUTCPU12_H
-/*
- * The flash bank is wired to chip select 0
- */
-#define AUTCPU12_PHYS_FLASH             CS0_PHYS_BASE           /* physical */
-/* offset for device specific information structure */
-#define AUTCPU12_LCDINFO_OFFS           (0x00010000)    
-/* Videomemory in the internal SRAM (CS 6) */
-#define AUTCPU12_PHYS_VIDEO             CS6_PHYS_BASE
-/*
-* All special IO's are tied to CS1
-*/
-#define AUTCPU12_PHYS_CHAR_LCD          CS1_PHYS_BASE +0x00000000  /* physical */
-#define AUTCPU12_PHYS_NVRAM             CS1_PHYS_BASE +0x02000000  /* physical */
-#define AUTCPU12_PHYS_CSAUX1            CS1_PHYS_BASE +0x04000000  /* physical */
-#define AUTCPU12_PHYS_CAN               CS1_PHYS_BASE +0x08000000  /* physical */
-#define AUTCPU12_PHYS_TOUCH             CS1_PHYS_BASE +0x0A000000  /* physical */
-#define AUTCPU12_PHYS_IO                CS1_PHYS_BASE +0x0C000000  /* physical */
-#define AUTCPU12_PHYS_LPT               CS1_PHYS_BASE +0x0E000000  /* physical */
-/*
-* defines for lcd contrast 
-*/
-#define AUTCPU12_DPOT_PORT_OFFSET       PEDR
-#define AUTCPU12_DPOT_CS                (1<<0)
-#define AUTCPU12_DPOT_CLK               (1<<1)
-#define AUTCPU12_DPOT_UD                (1<<2)
-#endif
diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h
index 01d1b9559710..0286f4bf9945 100644
--- a/arch/arm/mach-clps711x/include/mach/clps711x.h
+++ b/arch/arm/mach-clps711x/include/mach/clps711x.h
@@ -21,6 +21,8 @@
 #ifndef __MACH_CLPS711X_H
 #define __MACH_CLPS711X_H
+#include <linux/mfd/syscon/clps711x.h>
 #define CLPS711X_PHYS_BASE      (0x80000000)
 #define PADR            (0x0000)
@@ -96,83 +98,9 @@
 #define RANDID2         (0x2708)
 #define RANDID3         (0x270c)
-/* common bits: SYSCON1 / SYSCON2 */
-#define SYSCON_UARTEN           (1 << 8)
-#define SYSCON1_KBDSCAN(x)      ((x) & 15)
-#define SYSCON1_KBDSCANMASK     (15)
-#define SYSCON1_TC1M            (1 << 4)
-#define SYSCON1_TC1S            (1 << 5)
-#define SYSCON1_TC2M            (1 << 6)
-#define SYSCON1_TC2S            (1 << 7)
-#define SYSCON1_UART1EN         SYSCON_UARTEN
-#define SYSCON1_BZTOG           (1 << 9)
-#define SYSCON1_BZMOD           (1 << 10)
-#define SYSCON1_DBGEN           (1 << 11)
-#define SYSCON1_LCDEN           (1 << 12)
-#define SYSCON1_CDENTX          (1 << 13)
-#define SYSCON1_CDENRX          (1 << 14)
-#define SYSCON1_SIREN           (1 << 15)
-#define SYSCON1_ADCKSEL(x)      (((x) & 3) << 16)
-#define SYSCON1_ADCKSEL_MASK    (3 << 16)
-#define SYSCON1_EXCKEN          (1 << 18)
-#define SYSCON1_WAKEDIS         (1 << 19)
-#define SYSCON1_IRTXM           (1 << 20)
-/* common bits: SYSFLG1 / SYSFLG2 */
-#define SYSFLG_UBUSY            (1 << 11)
-#define SYSFLG_URXFE            (1 << 22)
-#define SYSFLG_UTXFF            (1 << 23)
-#define SYSFLG1_MCDR            (1 << 0)
-#define SYSFLG1_DCDET           (1 << 1)
-#define SYSFLG1_WUDR            (1 << 2)
-#define SYSFLG1_WUON            (1 << 3)
-#define SYSFLG1_CTS             (1 << 8)
-#define SYSFLG1_DSR             (1 << 9)
-#define SYSFLG1_DCD             (1 << 10)
-#define SYSFLG1_UBUSY           SYSFLG_UBUSY
-#define SYSFLG1_NBFLG           (1 << 12)
-#define SYSFLG1_RSTFLG          (1 << 13)
-#define SYSFLG1_PFFLG           (1 << 14)
-#define SYSFLG1_CLDFLG          (1 << 15)
-#define SYSFLG1_URXFE           SYSFLG_URXFE
-#define SYSFLG1_UTXFF           SYSFLG_UTXFF
-#define SYSFLG1_CRXFE           (1 << 24)
-#define SYSFLG1_CTXFF           (1 << 25)
-#define SYSFLG1_SSIBUSY         (1 << 26)
-#define SYSFLG1_ID              (1 << 29)
-#define SYSFLG1_VERID(x)        (((x) >> 30) & 3)
-#define SYSFLG1_VERID_MASK      (3 << 30)
-#define SYSFLG2_SSRXOF          (1 << 0)
-#define SYSFLG2_RESVAL          (1 << 1)
-#define SYSFLG2_RESFRM          (1 << 2)
-#define SYSFLG2_SS2RXFE         (1 << 3)
-#define SYSFLG2_SS2TXFF         (1 << 4)
-#define SYSFLG2_SS2TXUF         (1 << 5)
-#define SYSFLG2_CKMODE          (1 << 6)
-#define SYSFLG2_UBUSY           SYSFLG_UBUSY
-#define SYSFLG2_URXFE           SYSFLG_URXFE
-#define SYSFLG2_UTXFF           SYSFLG_UTXFF
 #define LCDCON_GSEN             (1 << 30)
 #define LCDCON_GSMD             (1 << 31)
-#define SYSCON2_SERSEL          (1 << 0)
-#define SYSCON2_KBD6            (1 << 1)
-#define SYSCON2_DRAMZ           (1 << 2)
-#define SYSCON2_KBWEN           (1 << 3)
-#define SYSCON2_SS2TXEN         (1 << 4)
-#define SYSCON2_PCCARD1         (1 << 5)
-#define SYSCON2_PCCARD2         (1 << 6)
-#define SYSCON2_SS2RXEN         (1 << 7)
-#define SYSCON2_UART2EN         SYSCON_UARTEN
-#define SYSCON2_SS2MAEN         (1 << 9)
-#define SYSCON2_OSTB            (1 << 12)
-#define SYSCON2_CLKENSL         (1 << 13)
-#define SYSCON2_BUZFREQ         (1 << 14)
 /* common bits: UARTDR1 / UARTDR2 */
 #define UARTDR_FRMERR           (1 << 8)
 #define UARTDR_PARERR           (1 << 9)
@@ -228,18 +156,6 @@
 #define DAI64FS_MCLK256EN       (1 << 3)
 #define DAI64FS_LOOPBACK        (1 << 5)
-#define SYSCON3_ADCCON          (1 << 0)
-#define SYSCON3_CLKCTL0         (1 << 1)
-#define SYSCON3_CLKCTL1         (1 << 2)
-#define SYSCON3_DAISEL          (1 << 3)
-#define SYSCON3_ADCCKNSEN       (1 << 4)
-#define SYSCON3_VERSN(x)        (((x) >> 5) & 7)
-#define SYSCON3_VERSN_MASK      (7 << 5)
-#define SYSCON3_FASTWAKE        (1 << 8)
-#define SYSCON3_DAIEN           (1 << 9)
-#define SYSCON3_128FS           SYSCON3_DAIEN
-#define SYSCON3_ENPD67          (1 << 10)
 #define SDCONF_ACTIVE           (1 << 10)
 #define SDCONF_CLKCTL           (1 << 9)
 #define SDCONF_WIDTH_4          (0 << 7)
diff --git a/arch/arm/mach-clps711x/include/mach/hardware.h b/arch/arm/mach-clps711x/include/mach/hardware.h
index 2f23dd5d73e4..c5a8ea6839ef 100644
--- a/arch/arm/mach-clps711x/include/mach/hardware.h
+++ b/arch/arm/mach-clps711x/include/mach/hardware.h
@@ -70,11 +70,4 @@
 #define CLPS711X_SDRAM0_BASE    (0xc0000000)
 #define CLPS711X_SDRAM1_BASE    (0xd0000000)
-#if defined (CONFIG_ARCH_EDB7211)
-/* The extra 8 lines of the keyboard matrix are wired to chip select 3 */
-#define EP7211_PHYS_EXTKBD      CS3_PHYS_BASE
-#endif /* CONFIG_ARCH_EDB7211 */
 #endif
diff --git a/arch/arm/mach-clps711x/include/mach/memory.h b/arch/arm/mach-clps711x/include/mach/memory.h
deleted file mode 100644
index fc0e028d9405..000000000000
--- a/arch/arm/mach-clps711x/include/mach/memory.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- *  arch/arm/mach-clps711x/include/mach/memory.h
- *
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-/*
- * Physical DRAM offset.
- */
-#define PLAT_PHYS_OFFSET        UL(0xc0000000)
-/*
- * The PS7211 allows up to 256MB max per DRAM bank, but the EDB7211
- * uses only one of the two banks (bank #1).  However, even within
- * bank #1, memory is discontiguous.
- *
- * The EDB7211 has two 8MB DRAM areas with 8MB of empty space between
- * them, so we use 24 for the node max shift to get 16MB node sizes.
- */
-#define SECTION_SIZE_BITS       24
-#define MAX_PHYSMEM_BITS        32
-#endif
diff --git a/arch/arm/mach-clps711x/include/mach/syspld.h b/arch/arm/mach-clps711x/include/mach/syspld.h
deleted file mode 100644
index 9a433155bf58..000000000000
--- a/arch/arm/mach-clps711x/include/mach/syspld.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- *  arch/arm/mach-clps711x/include/mach/syspld.h
- *
- *  System Control PLD register definitions.
- *
- *  Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_SYSPLD_H
-#define __ASM_ARCH_SYSPLD_H
-#define SYSPLD_PHYS_BASE        (0x10000000)
-#define SYSPLD_VIRT_BASE        IO_ADDRESS(SYSPLD_PHYS_BASE)
-#define SYSPLD_REG(type, off)   (*(volatile type *)(SYSPLD_VIRT_BASE + (off)))
-#define PLD_INT         SYSPLD_REG(u32, 0x000000)
-#define PLD_INT_PENIRQ          (1 << 5)
-#define PLD_INT_UCB_IRQ         (1 << 1)
-#define PLD_INT_KBD_ATN         (1 << 0)        /* EINT1 */
-#define PLD_PWR         SYSPLD_REG(u32, 0x000004)
-#define PLD_PWR_EXT             (1 << 5)
-#define PLD_PWR_MODE            (1 << 4)        /* 1 = PWM, 0 = PFM */
-#define PLD_S4_ON               (1 << 3)        /* LCD bias voltage enable */
-#define PLD_S3_ON               (1 << 2)        /* LCD backlight enable */
-#define PLD_S2_ON               (1 << 1)        /* LCD 3V3 supply enable */
-#define PLD_S1_ON               (1 << 0)        /* LCD 3V supply enable */
-#define PLD_KBD         SYSPLD_REG(u32, 0x000008)
-#define PLD_KBD_WAKE            (1 << 1)
-#define PLD_KBD_EN              (1 << 0)
-#define PLD_SPI         SYSPLD_REG(u32, 0x00000c)
-#define PLD_SPI_EN              (1 << 0)
-#define PLD_IO          SYSPLD_REG(u32, 0x000010)
-#define PLD_IO_BOOTSEL          (1 << 6)        /* boot sel switch */
-#define PLD_IO_USER             (1 << 5)        /* user defined switch */
-#define PLD_IO_LED3             (1 << 4)
-#define PLD_IO_LED2             (1 << 3)
-#define PLD_IO_LED1             (1 << 2)
-#define PLD_IO_LED0             (1 << 1)
-#define PLD_IO_LEDEN            (1 << 0)
-#define PLD_IRDA        SYSPLD_REG(u32, 0x000014)
-#define PLD_IRDA_EN             (1 << 0)
-#define PLD_COM2        SYSPLD_REG(u32, 0x000018)
-#define PLD_COM2_EN             (1 << 0)
-#define PLD_COM1        SYSPLD_REG(u32, 0x00001c)
-#define PLD_COM1_EN             (1 << 0)
-#define PLD_AUD         SYSPLD_REG(u32, 0x000020)
-#define PLD_AUD_DIV1            (1 << 6)
-#define PLD_AUD_DIV0            (1 << 5)
-#define PLD_AUD_CLK_SEL1        (1 << 4)
-#define PLD_AUD_CLK_SEL0        (1 << 3)
-#define PLD_AUD_MIC_PWR         (1 << 2)
-#define PLD_AUD_MIC_GAIN        (1 << 1)
-#define PLD_AUD_CODEC_EN        (1 << 0)
-#define PLD_CF          SYSPLD_REG(u32, 0x000024)
-#define PLD_CF2_SLEEP           (1 << 5)
-#define PLD_CF1_SLEEP           (1 << 4)
-#define PLD_CF2_nPDREQ          (1 << 3)
-#define PLD_CF1_nPDREQ          (1 << 2)
-#define PLD_CF2_nIRQ            (1 << 1)
-#define PLD_CF1_nIRQ            (1 << 0)
-#define PLD_SDC         SYSPLD_REG(u32, 0x000028)
-#define PLD_SDC_INT_EN          (1 << 2)
-#define PLD_SDC_WP              (1 << 1)
-#define PLD_SDC_CD              (1 << 0)
-#define PLD_FPGA        SYSPLD_REG(u32, 0x00002c)
-#define PLD_CODEC       SYSPLD_REG(u32, 0x400000)
-#define PLD_CODEC_IRQ3          (1 << 4)
-#define PLD_CODEC_IRQ2          (1 << 3)
-#define PLD_CODEC_IRQ1          (1 << 2)
-#define PLD_CODEC_EN            (1 << 0)
-#define PLD_BRITE       SYSPLD_REG(u32, 0x400004)
-#define PLD_BRITE_UP            (1 << 1)
-#define PLD_BRITE_DN            (1 << 0)
-#define PLD_LCDEN       SYSPLD_REG(u32, 0x400008)
-#define PLD_LCDEN_EN            (1 << 0)
-#define PLD_ID          SYSPLD_REG(u32, 0x40000c)
-#define PLD_TCH         SYSPLD_REG(u32, 0x400010)
-#define PLD_TCH_PENIRQ          (1 << 1)
-#define PLD_TCH_EN              (1 << 0)
-#define PLD_GPIO        SYSPLD_REG(u32, 0x400014)
-#define PLD_GPIO2               (1 << 2)
-#define PLD_GPIO1               (1 << 1)
-#define PLD_GPIO0               (1 << 0)
-#endif
diff --git a/arch/arm/mach-cns3xxx/core.h b/arch/arm/mach-cns3xxx/core.h
index b23b17b4da10..5218b6198dc2 100644
--- a/arch/arm/mach-cns3xxx/core.h
+++ b/arch/arm/mach-cns3xxx/core.h
@@ -11,6 +11,8 @@
 #ifndef __CNS3XXX_CORE_H
 #define __CNS3XXX_CORE_H
+#include <linux/reboot.h>
 extern void cns3xxx_timer_init(void);
 #ifdef CONFIG_CACHE_L2X0
@@ -22,6 +24,6 @@ static inline void cns3xxx_l2x0_init(void) {}
 void __init cns3xxx_map_io(void);
 void __init cns3xxx_init_irq(void);
 void cns3xxx_power_off(void);
-void cns3xxx_restart(char, const char *);
+void cns3xxx_restart(enum reboot_mode, const char *);
 #endif /* __CNS3XXX_CORE_H */
diff --git a/arch/arm/mach-cns3xxx/pm.c b/arch/arm/mach-cns3xxx/pm.c
index 79e3d47aad65..fb38c726e987 100644
--- a/arch/arm/mach-cns3xxx/pm.c
+++ b/arch/arm/mach-cns3xxx/pm.c
@@ -89,7 +89,7 @@ void cns3xxx_pwr_soft_rst(unsigned int block)
 }
 EXPORT_SYMBOL(cns3xxx_pwr_soft_rst);
-void cns3xxx_restart(char mode, const char *cmd)
+void cns3xxx_restart(enum reboot_mode mode, const char *cmd)
 {
        /*
         * To reset, we hit the on-board reset register
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index a075b3e0c5c7..e026b19b23ea 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -40,6 +40,7 @@ config ARCH_DAVINCI_DA850
        bool "DA850/OMAP-L138/AM18x based system"
        select ARCH_DAVINCI_DA8XX
        select ARCH_HAS_CPUFREQ
+        select CPU_FREQ_TABLE
        select CP_INTC
 config ARCH_DAVINCI_DA8XX
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index dd1ffccc75e9..63997a1128e6 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -5,7 +5,7 @@
 # Common objects
 obj-y                   := time.o clock.o serial.o psc.o \
-                           dma.o usb.o common.o sram.o aemif.o
+                           usb.o common.o sram.o aemif.o
 obj-$(CONFIG_DAVINCI_MUX)               += mux.o
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 8a24b6c6339f..bea6793a7ede 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -985,7 +985,6 @@ static struct regulator_init_data tps65070_regulator_data[] = {
 static struct touchscreen_init_data tps6507x_touchscreen_data = {
        .poll_period =  30,     /* ms between touch samples */
        .min_pressure = 0x30,   /* minimum pressure to trigger touch */
-        .vref = 0,              /* turn off vref when not using A/D */
        .vendor = 0,            /* /sys/class/input/input?/id/vendor */
        .product = 65070,       /* /sys/class/input/input?/id/product */
        .version = 0x100,       /* /sys/class/input/input?/id/version */
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index fd38c8d22e3c..4cdb61c54459 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -505,11 +505,10 @@ static struct vpbe_output dm365evm_vpbe_outputs[] = {
 /*
 * Amplifiers on the board
 */
-struct ths7303_platform_data ths7303_pdata = {
+static struct ths7303_platform_data ths7303_pdata = {
        .ch_1 = 3,
        .ch_2 = 3,
        .ch_3 = 3,
-        .init_enable = 1,
 };
 static struct amp_config_info vpbe_amp = {
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index 739be7e738fe..513eee14f77d 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -151,7 +151,6 @@ static __init void davinci_sffsdr_init(void)
 }
 MACHINE_START(SFFSDR, "Lyrtech SFFSDR")
-        /* Maintainer: Hugo Villeneuve hugo.villeneuve@lyrtech.com */
        .atag_offset  = 0x100,
        .map_io       = davinci_sffsdr_map_io,
        .init_irq     = davinci_irq_init,
diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c
index ba798370fc96..78ea395d2aca 100644
--- a/arch/arm/mach-davinci/board-tnetv107x-evm.c
+++ b/arch/arm/mach-davinci/board-tnetv107x-evm.c
@@ -26,12 +26,12 @@
 #include <linux/input.h>
 #include <linux/input/matrix_keypad.h>
 #include <linux/spi/spi.h>
+#include <linux/platform_data/edma.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 #include <mach/irqs.h>
-#include <mach/edma.h>
 #include <mach/mux.h>
 #include <mach/cp_intc.h>
 #include <mach/tnetv107x.h>
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 4d6933848abf..a0d4f6038b60 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1004,7 +1004,7 @@ static const struct da850_opp da850_opp_96 = {
 #define OPP(freq)               \
        {                               \
-                .index = (unsigned int) &da850_opp_##freq,      \
+                .driver_data = (unsigned int) &da850_opp_##freq,        \
                .frequency = freq * 1000, \
        }
@@ -1016,7 +1016,7 @@ static struct cpufreq_frequency_table da850_freq_table[] = {
        OPP(200),
        OPP(96),
        {
-                .index          = 0,
+                .driver_data            = 0,
                .frequency      = CPUFREQ_TABLE_END,
        },
 };
@@ -1044,7 +1044,7 @@ static int da850_set_voltage(unsigned int index)
        if (!cvdd)
                return -ENODEV;
-        opp = (struct da850_opp *) cpufreq_info.freq_table[index].index;
+        opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data;
        return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
 }
@@ -1125,7 +1125,7 @@ static int da850_set_pll0rate(struct clk *clk, unsigned long index)
        struct pll_data *pll = clk->pll_data;
        int ret;
-        opp = (struct da850_opp *) cpufreq_info.freq_table[index].index;
+        opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data;
        prediv = opp->prediv;
        mult = opp->mult;
        postdiv = opp->postdiv;
diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h
index 1ab3df423dac..a883043d0820 100644
--- a/arch/arm/mach-davinci/davinci.h
+++ b/arch/arm/mach-davinci/davinci.h
@@ -23,9 +23,9 @@
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
 #include <linux/platform_data/davinci_asp.h>
+#include <linux/platform_data/edma.h>
 #include <linux/platform_data/keyscan-davinci.h>
 #include <mach/hardware.h>
-#include <mach/edma.h>
 #include <media/davinci/vpfe_capture.h>
 #include <media/davinci/vpif_types.h>
@@ -77,32 +77,32 @@ void davinci_map_sysmod(void);
 #define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000
 /* DM355 function declarations */
-void __init dm355_init(void);
+void dm355_init(void);
 void dm355_init_spi0(unsigned chipselect_mask,
                const struct spi_board_info *info, unsigned len);
-void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata);
+void dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata);
 int dm355_init_video(struct vpfe_config *, struct vpbe_config *);
 /* DM365 function declarations */
-void __init dm365_init(void);
+void dm365_init(void);
-void __init dm365_init_asp(struct snd_platform_data *pdata);
+void dm365_init_asp(struct snd_platform_data *pdata);
-void __init dm365_init_vc(struct snd_platform_data *pdata);
+void dm365_init_vc(struct snd_platform_data *pdata);
-void __init dm365_init_ks(struct davinci_ks_platform_data *pdata);
+void dm365_init_ks(struct davinci_ks_platform_data *pdata);
-void __init dm365_init_rtc(void);
+void dm365_init_rtc(void);
 void dm365_init_spi0(unsigned chipselect_mask,
                        const struct spi_board_info *info, unsigned len);
 int dm365_init_video(struct vpfe_config *, struct vpbe_config *);
 /* DM644x function declarations */
-void __init dm644x_init(void);
+void dm644x_init(void);
-void __init dm644x_init_asp(struct snd_platform_data *pdata);
+void dm644x_init_asp(struct snd_platform_data *pdata);
-int __init dm644x_init_video(struct vpfe_config *, struct vpbe_config *);
+int dm644x_init_video(struct vpfe_config *, struct vpbe_config *);
 /* DM646x function declarations */
-void __init dm646x_init(void);
+void dm646x_init(void);
-void __init dm646x_init_mcasp0(struct snd_platform_data *pdata);
+void dm646x_init_mcasp0(struct snd_platform_data *pdata);
-void __init dm646x_init_mcasp1(struct snd_platform_data *pdata);
+void dm646x_init_mcasp1(struct snd_platform_data *pdata);
-int __init dm646x_init_edma(struct edma_rsv_info *rsv);
+int dm646x_init_edma(struct edma_rsv_info *rsv);
 void dm646x_video_init(void);
 void dm646x_setup_vpif(struct vpif_display_config *,
                       struct vpif_capture_config *);
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index bf572525175d..71a46a348761 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -16,6 +16,7 @@
 #include <linux/serial_8250.h>
 #include <linux/ahci_platform.h>
 #include <linux/clk.h>
+#include <linux/reboot.h>
 #include <mach/cputype.h>
 #include <mach/common.h>
@@ -105,27 +106,27 @@ struct platform_device da8xx_serial_device = {
        },
 };
-static const s8 da8xx_queue_tc_mapping[][2] = {
+static s8 da8xx_queue_tc_mapping[][2] = {
        /* {event queue no, TC no} */
        {0, 0},
        {1, 1},
        {-1, -1}
 };
-static const s8 da8xx_queue_priority_mapping[][2] = {
+static s8 da8xx_queue_priority_mapping[][2] = {
        /* {event queue no, Priority} */
        {0, 3},
        {1, 7},
        {-1, -1}
 };
-static const s8 da850_queue_tc_mapping[][2] = {
+static s8 da850_queue_tc_mapping[][2] = {
        /* {event queue no, TC no} */
        {0, 0},
        {-1, -1}
 };
-static const s8 da850_queue_priority_mapping[][2] = {
+static s8 da850_queue_priority_mapping[][2] = {
        /* {event queue no, Priority} */
        {0, 3},
        {-1, -1}
@@ -366,7 +367,7 @@ static struct platform_device da8xx_wdt_device = {
        .resource       = da8xx_watchdog_resources,
 };
-void da8xx_restart(char mode, const char *cmd)
+void da8xx_restart(enum reboot_mode mode, const char *cmd)
 {
        struct device *dev;
diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c
index cfb194df18ed..128cb9ae80f4 100644
--- a/arch/arm/mach-davinci/devices-tnetv107x.c
+++ b/arch/arm/mach-davinci/devices-tnetv107x.c
@@ -18,10 +18,10 @@
 #include <linux/dma-mapping.h>
 #include <linux/clk.h>
 #include <linux/slab.h>
+#include <linux/platform_data/edma.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
-#include <mach/edma.h>
 #include <mach/tnetv107x.h>
 #include "clock.h"
@@ -58,14 +58,14 @@
 #define TNETV107X_DMACH_SDIO1_RX                28
 #define TNETV107X_DMACH_SDIO1_TX                29
-static const s8 edma_tc_mapping[][2] = {
+static s8 edma_tc_mapping[][2] = {
        /* event queue no       TC no   */
        {        0,              0      },
        {        1,              1      },
        {       -1,             -1      }
 };
-static const s8 edma_priority_mapping[][2] = {
+static s8 edma_priority_mapping[][2] = {
        /* event queue no       Prio    */
        {        0,              3      },
        {        1,              7      },
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index a7068a3aa9d3..111573c0aad1 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -13,15 +13,17 @@
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 #include <mach/hardware.h>
 #include <linux/platform_data/i2c-davinci.h>
 #include <mach/irqs.h>
 #include <mach/cputype.h>
 #include <mach/mux.h>
-#include <mach/edma.h>
 #include <linux/platform_data/mmc-davinci.h>
 #include <mach/time.h>
+#include <linux/platform_data/edma.h>
 #include "davinci.h"
 #include "clock.h"
@@ -34,6 +36,9 @@
 #define DM365_MMCSD0_BASE            0x01D11000
 #define DM365_MMCSD1_BASE            0x01D00000
+#define DAVINCI_DMA_MMCRXEVT    26
+#define DAVINCI_DMA_MMCTXEVT    27
 void __iomem  *davinci_sysmod_base;
 void davinci_map_sysmod(void)
@@ -303,7 +308,7 @@ struct platform_device davinci_wdt_device = {
        .resource       = wdt_resources,
 };
-void davinci_restart(char mode, const char *cmd)
+void davinci_restart(enum reboot_mode mode, const char *cmd)
 {
        davinci_watchdog_reset(&davinci_wdt_device);
 }
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index a11034a358f1..86100d179694 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -19,7 +19,6 @@
 #include <asm/mach/map.h>
 #include <mach/cputype.h>
-#include <mach/edma.h>
 #include <mach/psc.h>
 #include <mach/mux.h>
 #include <mach/irqs.h>
@@ -28,6 +27,7 @@
 #include <mach/common.h>
 #include <linux/platform_data/spi-davinci.h>
 #include <mach/gpio-davinci.h>
+#include <linux/platform_data/edma.h>
 #include "davinci.h"
 #include "clock.h"
@@ -569,7 +569,7 @@ static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 /*----------------------------------------------------------------------*/
-static const s8
+static s8
 queue_tc_mapping[][2] = {
        /* {event queue no, TC no} */
        {0, 0},
@@ -577,7 +577,7 @@ queue_tc_mapping[][2] = {
        {-1, -1},
 };
-static const s8
+static s8
 queue_priority_mapping[][2] = {
        /* {event queue no, Priority} */
        {0, 3},
@@ -860,7 +860,7 @@ static struct platform_device dm355_vpbe_display = {
        },
 };
-struct venc_platform_data dm355_venc_pdata = {
+static struct venc_platform_data dm355_venc_pdata = {
        .setup_pinmux   = dm355_vpbe_setup_pinmux,
        .setup_clock    = dm355_venc_setup_clock,
 };
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 40fa4fee9331..dad28029ba9b 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -18,11 +18,11 @@
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <linux/spi/spi.h>
+#include <linux/platform_data/edma.h>
 #include <asm/mach/map.h>
 #include <mach/cputype.h>
-#include <mach/edma.h>
 #include <mach/psc.h>
 #include <mach/mux.h>
 #include <mach/irqs.h>
@@ -826,7 +826,7 @@ static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 };
 /* Four Transfer Controllers on DM365 */
-static const s8
+static s8
 dm365_queue_tc_mapping[][2] = {
        /* {event queue no, TC no} */
        {0, 0},
@@ -836,7 +836,7 @@ dm365_queue_tc_mapping[][2] = {
        {-1, -1},
 };
-static const s8
+static s8
 dm365_queue_priority_mapping[][2] = {
        /* {event queue no, Priority} */
        {0, 7},
@@ -1349,7 +1349,7 @@ static struct platform_device dm365_vpbe_display = {
        },
 };
-struct venc_platform_data dm365_venc_pdata = {
+static struct venc_platform_data dm365_venc_pdata = {
        .setup_pinmux   = dm365_vpbe_setup_pinmux,
        .setup_clock    = dm365_venc_setup_clock,
 };
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 4d37d3e2a193..a49d18246fe9 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -12,11 +12,11 @@
 #include <linux/clk.h>
 #include <linux/serial_8250.h>
 #include <linux/platform_device.h>
+#include <linux/platform_data/edma.h>
 #include <asm/mach/map.h>
 #include <mach/cputype.h>
-#include <mach/edma.h>
 #include <mach/irqs.h>
 #include <mach/psc.h>
 #include <mach/mux.h>
@@ -497,7 +497,7 @@ static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 /*----------------------------------------------------------------------*/
-static const s8
+static s8
 queue_tc_mapping[][2] = {
        /* {event queue no, TC no} */
        {0, 0},
@@ -505,7 +505,7 @@ queue_tc_mapping[][2] = {
        {-1, -1},
 };
-static const s8
+static s8
 queue_priority_mapping[][2] = {
        /* {event queue no, Priority} */
        {0, 3},
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index ac7b431c4c8e..d1259e80141b 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -13,11 +13,11 @@
 #include <linux/clk.h>
 #include <linux/serial_8250.h>
 #include <linux/platform_device.h>
+#include <linux/platform_data/edma.h>
 #include <asm/mach/map.h>
 #include <mach/cputype.h>
-#include <mach/edma.h>
 #include <mach/irqs.h>
 #include <mach/psc.h>
 #include <mach/mux.h>
@@ -531,7 +531,7 @@ static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 /*----------------------------------------------------------------------*/
 /* Four Transfer Controllers on DM646x */
-static const s8
+static s8
 dm646x_queue_tc_mapping[][2] = {
        /* {event queue no, TC no} */
        {0, 0},
@@ -541,7 +541,7 @@ dm646x_queue_tc_mapping[][2] = {
        {-1, -1},
 };
-static const s8
+static s8
 dm646x_queue_priority_mapping[][2] = {
        /* {event queue no, Priority} */
        {0, 4},
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index b124b77c90c5..cce316b92c06 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -14,6 +14,7 @@
 #include <linux/compiler.h>
 #include <linux/types.h>
+#include <linux/reboot.h>
 extern void davinci_timer_init(void);
@@ -81,7 +82,7 @@ extern struct davinci_soc_info davinci_soc_info;
 extern void davinci_common_init(struct davinci_soc_info *soc_info);
 extern void davinci_init_ide(void);
-void davinci_restart(char mode, const char *cmd);
+void davinci_restart(enum reboot_mode mode, const char *cmd);
 void davinci_init_late(void);
 #ifdef CONFIG_DAVINCI_RESET_CLOCKS
diff --git a/arch/arm/mach-davinci/include/mach/cp_intc.h b/arch/arm/mach-davinci/include/mach/cp_intc.h
index d13d8dfa2b0d..827bbe9baed4 100644
--- a/arch/arm/mach-davinci/include/mach/cp_intc.h
+++ b/arch/arm/mach-davinci/include/mach/cp_intc.h
@@ -51,7 +51,7 @@
 #define CP_INTC_HOST_PRIO_VECTOR(n)     (0x1600 + (n << 2))
 #define CP_INTC_VECTOR_ADDR(n)          (0x2000 + (n << 2))
-void __init cp_intc_init(void);
+void cp_intc_init(void);
-int __init cp_intc_of_init(struct device_node *, struct device_node *);
+int cp_intc_of_init(struct device_node *, struct device_node *);
 #endif  /* __ASM_HARDWARE_CP_INTC_H */
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index 2e1c9eae0a58..7b41a5e9bc31 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -17,11 +17,12 @@
 #include <linux/davinci_emac.h>
 #include <linux/spi/spi.h>
 #include <linux/platform_data/davinci_asp.h>
+#include <linux/reboot.h>
 #include <linux/videodev2.h>
 #include <mach/serial.h>
-#include <mach/edma.h>
 #include <mach/pm.h>
+#include <linux/platform_data/edma.h>
 #include <linux/platform_data/i2c-davinci.h>
 #include <linux/platform_data/mmc-davinci.h>
 #include <linux/platform_data/usb-davinci.h>
@@ -79,8 +80,8 @@ extern unsigned int da850_max_speed;
 #define DA8XX_SHARED_RAM_BASE   0x80000000
 #define DA8XX_ARM_RAM_BASE      0xffff0000
-void __init da830_init(void);
+void da830_init(void);
-void __init da850_init(void);
+void da850_init(void);
 int da830_register_edma(struct edma_rsv_info *rsv);
 int da850_register_edma(struct edma_rsv_info *rsv[2]);
@@ -94,19 +95,19 @@ int da8xx_register_uio_pruss(void);
 int da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata);
 int da8xx_register_mmcsd0(struct davinci_mmc_config *config);
 int da850_register_mmcsd1(struct davinci_mmc_config *config);
-void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata);
+void da8xx_register_mcasp(int id, struct snd_platform_data *pdata);
 int da8xx_register_rtc(void);
 int da850_register_cpufreq(char *async_clk);
 int da8xx_register_cpuidle(void);
-void __iomem * __init da8xx_get_mem_ctlr(void);
+void __iomem *da8xx_get_mem_ctlr(void);
 int da850_register_pm(struct platform_device *pdev);
-int __init da850_register_sata(unsigned long refclkpn);
+int da850_register_sata(unsigned long refclkpn);
-int __init da850_register_vpif(void);
+int da850_register_vpif(void);
-int __init da850_register_vpif_display
+int da850_register_vpif_display
                        (struct vpif_display_config *display_config);
-int __init da850_register_vpif_capture
+int da850_register_vpif_capture
                        (struct vpif_capture_config *capture_config);
-void da8xx_restart(char mode, const char *cmd);
+void da8xx_restart(enum reboot_mode mode, const char *cmd);
 void da8xx_rproc_reserve_cma(void);
 int da8xx_register_rproc(void);
diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h
deleted file mode 100644
index 7e84c906ceff..000000000000
--- a/arch/arm/mach-davinci/include/mach/edma.h
+++ /dev/null
@@ -1,267 +0,0 @@
-/*
- *  TI DAVINCI dma definitions
- *
- *  Copyright (C) 2006-2009 Texas Instruments.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-/*
- * This EDMA3 programming framework exposes two basic kinds of resource:
- *
- *  Channel     Triggers transfers, usually from a hardware event but
- *              also manually or by "chaining" from DMA completions.
- *              Each channel is coupled to a Parameter RAM (PaRAM) slot.
- *
- *  Slot        Each PaRAM slot holds a DMA transfer descriptor (PaRAM
- *              "set"), source and destination addresses, a link to a
- *              next PaRAM slot (if any), options for the transfer, and
- *              instructions for updating those addresses.  There are
- *              more than twice as many slots as event channels.
- *
- * Each PaRAM set describes a sequence of transfers, either for one large
- * buffer or for several discontiguous smaller buffers.  An EDMA transfer
- * is driven only from a channel, which performs the transfers specified
- * in its PaRAM slot until there are no more transfers.  When that last
- * transfer completes, the "link" field may be used to reload the channel's
- * PaRAM slot with a new transfer descriptor.
- *
- * The EDMA Channel Controller (CC) maps requests from channels into physical
- * Transfer Controller (TC) requests when the channel triggers (by hardware
- * or software events, or by chaining).  The two physical DMA channels provided
- * by the TCs are thus shared by many logical channels.
- *
- * DaVinci hardware also has a "QDMA" mechanism which is not currently
- * supported through this interface.  (DSP firmware uses it though.)
- */
-#ifndef EDMA_H_
-#define EDMA_H_
-/* PaRAM slots are laid out like this */
-struct edmacc_param {
-        unsigned int opt;
-        unsigned int src;
-        unsigned int a_b_cnt;
-        unsigned int dst;
-        unsigned int src_dst_bidx;
-        unsigned int link_bcntrld;
-        unsigned int src_dst_cidx;
-        unsigned int ccnt;
-};
-#define CCINT0_INTERRUPT     16
-#define CCERRINT_INTERRUPT   17
-#define TCERRINT0_INTERRUPT   18
-#define TCERRINT1_INTERRUPT   19
-/* fields in edmacc_param.opt */
-#define SAM             BIT(0)
-#define DAM             BIT(1)
-#define SYNCDIM         BIT(2)
-#define STATIC          BIT(3)
-#define EDMA_FWID       (0x07 << 8)
-#define TCCMODE         BIT(11)
-#define EDMA_TCC(t)     ((t) << 12)
-#define TCINTEN         BIT(20)
-#define ITCINTEN        BIT(21)
-#define TCCHEN          BIT(22)
-#define ITCCHEN         BIT(23)
-#define TRWORD (0x7<<2)
-#define PAENTRY (0x1ff<<5)
-/* Drivers should avoid using these symbolic names for dm644x
- * channels, and use platform_device IORESOURCE_DMA resources
- * instead.  (Other DaVinci chips have different peripherals
- * and thus have different DMA channel mappings.)
- */
-#define DAVINCI_DMA_MCBSP_TX              2
-#define DAVINCI_DMA_MCBSP_RX              3
-#define DAVINCI_DMA_VPSS_HIST             4
-#define DAVINCI_DMA_VPSS_H3A              5
-#define DAVINCI_DMA_VPSS_PRVU             6
-#define DAVINCI_DMA_VPSS_RSZ              7
-#define DAVINCI_DMA_IMCOP_IMXINT          8
-#define DAVINCI_DMA_IMCOP_VLCDINT         9
-#define DAVINCI_DMA_IMCO_PASQINT         10
-#define DAVINCI_DMA_IMCOP_DSQINT         11
-#define DAVINCI_DMA_SPI_SPIX             16
-#define DAVINCI_DMA_SPI_SPIR             17
-#define DAVINCI_DMA_UART0_URXEVT0        18
-#define DAVINCI_DMA_UART0_UTXEVT0        19
-#define DAVINCI_DMA_UART1_URXEVT1        20
-#define DAVINCI_DMA_UART1_UTXEVT1        21
-#define DAVINCI_DMA_UART2_URXEVT2        22
-#define DAVINCI_DMA_UART2_UTXEVT2        23
-#define DAVINCI_DMA_MEMSTK_MSEVT         24
-#define DAVINCI_DMA_MMCRXEVT             26
-#define DAVINCI_DMA_MMCTXEVT             27
-#define DAVINCI_DMA_I2C_ICREVT           28
-#define DAVINCI_DMA_I2C_ICXEVT           29
-#define DAVINCI_DMA_GPIO_GPINT0          32
-#define DAVINCI_DMA_GPIO_GPINT1          33
-#define DAVINCI_DMA_GPIO_GPINT2          34
-#define DAVINCI_DMA_GPIO_GPINT3          35
-#define DAVINCI_DMA_GPIO_GPINT4          36
-#define DAVINCI_DMA_GPIO_GPINT5          37
-#define DAVINCI_DMA_GPIO_GPINT6          38
-#define DAVINCI_DMA_GPIO_GPINT7          39
-#define DAVINCI_DMA_GPIO_GPBNKINT0       40
-#define DAVINCI_DMA_GPIO_GPBNKINT1       41
-#define DAVINCI_DMA_GPIO_GPBNKINT2       42
-#define DAVINCI_DMA_GPIO_GPBNKINT3       43
-#define DAVINCI_DMA_GPIO_GPBNKINT4       44
-#define DAVINCI_DMA_TIMER0_TINT0         48
-#define DAVINCI_DMA_TIMER1_TINT1         49
-#define DAVINCI_DMA_TIMER2_TINT2         50
-#define DAVINCI_DMA_TIMER3_TINT3         51
-#define DAVINCI_DMA_PWM0                 52
-#define DAVINCI_DMA_PWM1                 53
-#define DAVINCI_DMA_PWM2                 54
-/* DA830 specific EDMA3 information */
-#define EDMA_DA830_NUM_DMACH            32
-#define EDMA_DA830_NUM_TCC              32
-#define EDMA_DA830_NUM_PARAMENTRY       128
-#define EDMA_DA830_NUM_EVQUE            2
-#define EDMA_DA830_NUM_TC               2
-#define EDMA_DA830_CHMAP_EXIST          0
-#define EDMA_DA830_NUM_REGIONS          4
-#define DA830_DMACH2EVENT_MAP0          0x000FC03Fu
-#define DA830_DMACH2EVENT_MAP1          0x00000000u
-#define DA830_EDMA_ARM_OWN              0x30FFCCFFu
-/*ch_status paramater of callback function possible values*/
-#define DMA_COMPLETE 1
-#define DMA_CC_ERROR 2
-#define DMA_TC1_ERROR 3
-#define DMA_TC2_ERROR 4
-enum address_mode {
-        INCR = 0,
-        FIFO = 1
-};
-enum fifo_width {
-        W8BIT = 0,
-        W16BIT = 1,
-        W32BIT = 2,
-        W64BIT = 3,
-        W128BIT = 4,
-        W256BIT = 5
-};
-enum dma_event_q {
-        EVENTQ_0 = 0,
-        EVENTQ_1 = 1,
-        EVENTQ_2 = 2,
-        EVENTQ_3 = 3,
-        EVENTQ_DEFAULT = -1
-};
-enum sync_dimension {
-        ASYNC = 0,
-        ABSYNC = 1
-};
-#define EDMA_CTLR_CHAN(ctlr, chan)      (((ctlr) << 16) | (chan))
-#define EDMA_CTLR(i)                    ((i) >> 16)
-#define EDMA_CHAN_SLOT(i)               ((i) & 0xffff)
-#define EDMA_CHANNEL_ANY                -1      /* for edma_alloc_channel() */
-#define EDMA_SLOT_ANY                   -1      /* for edma_alloc_slot() */
-#define EDMA_CONT_PARAMS_ANY             1001
-#define EDMA_CONT_PARAMS_FIXED_EXACT     1002
-#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
-#define EDMA_MAX_CC               2
-/* alloc/free DMA channels and their dedicated parameter RAM slots */
-int edma_alloc_channel(int channel,
-        void (*callback)(unsigned channel, u16 ch_status, void *data),
-        void *data, enum dma_event_q);
-void edma_free_channel(unsigned channel);
-/* alloc/free parameter RAM slots */
-int edma_alloc_slot(unsigned ctlr, int slot);
-void edma_free_slot(unsigned slot);
-/* alloc/free a set of contiguous parameter RAM slots */
-int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count);
-int edma_free_cont_slots(unsigned slot, int count);
-/* calls that operate on part of a parameter RAM slot */
-void edma_set_src(unsigned slot, dma_addr_t src_port,
-                                enum address_mode mode, enum fifo_width);
-void edma_set_dest(unsigned slot, dma_addr_t dest_port,
-                                 enum address_mode mode, enum fifo_width);
-void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst);
-void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx);
-void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx);
-void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt,
-                u16 bcnt_rld, enum sync_dimension sync_mode);
-void edma_link(unsigned from, unsigned to);
-void edma_unlink(unsigned from);
-/* calls that operate on an entire parameter RAM slot */
-void edma_write_slot(unsigned slot, const struct edmacc_param *params);
-void edma_read_slot(unsigned slot, struct edmacc_param *params);
-/* channel control operations */
-int edma_start(unsigned channel);
-void edma_stop(unsigned channel);
-void edma_clean_channel(unsigned channel);
-void edma_clear_event(unsigned channel);
-void edma_pause(unsigned channel);
-void edma_resume(unsigned channel);
-struct edma_rsv_info {
-        const s16       (*rsv_chans)[2];
-        const s16       (*rsv_slots)[2];
-};
-/* platform_data for EDMA driver */
-struct edma_soc_info {
-        /* how many dma resources of each type */
-        unsigned        n_channel;
-        unsigned        n_region;
-        unsigned        n_slot;
-        unsigned        n_tc;
-        unsigned        n_cc;
-        /*
-         * Default queue is expected to be a low-priority queue.
-         * This way, long transfers on the default queue started
-         * by the codec engine will not cause audio defects.
-         */
-        enum dma_event_q        default_queue;
-        /* Resource reservation for other cores */
-        struct edma_rsv_info    *rsv;
-        const s8        (*queue_tc_mapping)[2];
-        const s8        (*queue_priority_mapping)[2];
-};
-#endif
diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h
index 1656a02e3eda..16314c64f755 100644
--- a/arch/arm/mach-davinci/include/mach/tnetv107x.h
+++ b/arch/arm/mach-davinci/include/mach/tnetv107x.h
@@ -35,6 +35,7 @@
 #include <linux/serial_8250.h>
 #include <linux/input/matrix_keypad.h>
 #include <linux/mfd/ti_ssp.h>
+#include <linux/reboot.h>
 #include <linux/platform_data/mmc-davinci.h>
 #include <linux/platform_data/mtd-davinci.h>
@@ -51,10 +52,10 @@ struct tnetv107x_device_info {
 extern struct platform_device tnetv107x_wdt_device;
 extern struct platform_device tnetv107x_serial_device;
-extern void __init tnetv107x_init(void);
+extern void tnetv107x_init(void);
-extern void __init tnetv107x_devices_init(struct tnetv107x_device_info *);
+extern void tnetv107x_devices_init(struct tnetv107x_device_info *);
-extern void __init tnetv107x_irq_init(void);
+extern void tnetv107x_irq_init(void);
-void tnetv107x_restart(char mode, const char *cmd);
+void tnetv107x_restart(enum reboot_mode mode, const char *cmd);
 #endif
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index bad361ec1666..7a55b5c95971 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -18,8 +18,8 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/platform_device.h>
+#include <linux/sched_clock.h>
-#include <asm/sched_clock.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c
index 3b2a70d43efa..4545667ecd3c 100644
--- a/arch/arm/mach-davinci/tnetv107x.c
+++ b/arch/arm/mach-davinci/tnetv107x.c
@@ -19,6 +19,7 @@
 #include <linux/io.h>
 #include <linux/err.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 #include <asm/mach/map.h>
@@ -730,7 +731,7 @@ static void tnetv107x_watchdog_reset(struct platform_device *pdev)
        __raw_writel(1, &regs->kick);
 }
-void tnetv107x_restart(char mode, const char *cmd)
+void tnetv107x_restart(enum reboot_mode mode, const char *cmd)
 {
        tnetv107x_watchdog_reset(&tnetv107x_wdt_device);
 }
diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig
index 36469d813951..dff7b2fd4e20 100644
--- a/arch/arm/mach-dove/Kconfig
+++ b/arch/arm/mach-dove/Kconfig
@@ -22,8 +22,7 @@ config MACH_CM_A510
 config MACH_DOVE_DT
        bool "Marvell Dove Flattened Device Tree"
-        select MVEBU_CLK_CORE
+        select DOVE_CLK
-        select MVEBU_CLK_GATING
        select REGULATOR
        select REGULATOR_FIXED_VOLTAGE
        select USE_OF
diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-dove/board-dt.c
index 0b142803b2e1..f3755ac81148 100644
--- a/arch/arm/mach-dove/board-dt.c
+++ b/arch/arm/mach-dove/board-dt.c
@@ -10,7 +10,6 @@
 #include <linux/init.h>
 #include <linux/clk-provider.h>
-#include <linux/clk/mvebu.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
 #include <linux/platform_data/usb-ehci-orion.h>
@@ -49,7 +48,7 @@ static void __init dove_legacy_clk_init(void)
 static void __init dove_of_clk_init(void)
 {
-        mvebu_clocks_init();
+        of_clk_init(NULL);
        dove_legacy_clk_init();
 }
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index e2b5da031f96..00247c771313 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -9,7 +9,6 @@
 */
 #include <linux/clk-provider.h>
-#include <linux/clk/mvebu.h>
 #include <linux/dma-mapping.h>
 #include <linux/init.h>
 #include <linux/of.h>
@@ -382,7 +381,7 @@ void __init dove_init(void)
        dove_xor1_init();
 }
-void dove_restart(char mode, const char *cmd)
+void dove_restart(enum reboot_mode mode, const char *cmd)
 {
        /*
         * Enable soft reset to assert RSTOUTn.
diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
index e86347928b67..1d725224d146 100644
--- a/arch/arm/mach-dove/common.h
+++ b/arch/arm/mach-dove/common.h
@@ -11,6 +11,8 @@
 #ifndef __ARCH_DOVE_COMMON_H
 #define __ARCH_DOVE_COMMON_H
+#include <linux/reboot.h>
 struct mv643xx_eth_platform_data;
 struct mv_sata_platform_data;
@@ -42,6 +44,6 @@ void dove_spi1_init(void);
 void dove_i2c_init(void);
 void dove_sdio0_init(void);
 void dove_sdio1_init(void);
-void dove_restart(char, const char *);
+void dove_restart(enum reboot_mode, const char *);
 #endif
diff --git a/arch/arm/mach-dove/include/mach/bridge-regs.h b/arch/arm/mach-dove/include/mach/bridge-regs.h
index 99f259e8cf33..5362df3df89f 100644
--- a/arch/arm/mach-dove/include/mach/bridge-regs.h
+++ b/arch/arm/mach-dove/include/mach/bridge-regs.h
@@ -26,6 +26,7 @@
 #define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE + 0x010c)
 #define  SOFT_RESET             0x00000001
+#define BRIDGE_CAUSE            (BRIDGE_VIRT_BASE + 0x0110)
 #define  BRIDGE_INT_TIMER1_CLR  (~0x0004)
 #define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE + 0x0200)
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index b13cc74114db..68ac934d4565 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -116,7 +116,7 @@ static void __init ebsa110_map_io(void)
        iotable_init(ebsa110_io_desc, ARRAY_SIZE(ebsa110_io_desc));
 }
-static void __iomem *ebsa110_ioremap_caller(unsigned long cookie, size_t size,
+static void __iomem *ebsa110_ioremap_caller(phys_addr_t cookie, size_t size,
                                            unsigned int flags, void *caller)
 {
        return (void __iomem *)cookie;
@@ -311,7 +311,7 @@ static int __init ebsa110_init(void)
 arch_initcall(ebsa110_init);
-static void ebsa110_restart(char mode, const char *cmd)
+static void ebsa110_restart(enum reboot_mode mode, const char *cmd)
 {
        soft_restart(0x80000000);
 }
@@ -321,7 +321,6 @@ MACHINE_START(EBSA110, "EBSA110")
        .atag_offset    = 0x400,
        .reserve_lp0    = 1,
        .reserve_lp2    = 1,
-        .restart_mode   = 's',
        .map_io         = ebsa110_map_io,
        .init_early     = ebsa110_init_early,
        .init_irq       = ebsa110_init_irq,
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index c49ed3dc1aea..df8612fbbc9c 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -35,6 +35,7 @@
 #include <linux/spi/spi.h>
 #include <linux/export.h>
 #include <linux/irqchip/arm-vic.h>
+#include <linux/reboot.h>
 #include <mach/hardware.h>
 #include <linux/platform_data/video-ep93xx.h>
@@ -921,7 +922,7 @@ void __init ep93xx_init_devices(void)
        gpio_led_register_device(-1, &ep93xx_led_data);
 }
-void ep93xx_restart(char mode, const char *cmd)
+void ep93xx_restart(enum reboot_mode mode, const char *cmd)
 {
        /*
         * Set then clear the SWRST bit to initiate a software reset
diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h
index a14e1b37beff..e256e0baec2e 100644
--- a/arch/arm/mach-ep93xx/include/mach/platform.h
+++ b/arch/arm/mach-ep93xx/include/mach/platform.h
@@ -4,6 +4,8 @@
 #ifndef __ASSEMBLY__
+#include <linux/reboot.h>
 struct i2c_gpio_platform_data;
 struct i2c_board_info;
 struct spi_board_info;
@@ -55,7 +57,7 @@ void ep93xx_ide_release_gpio(struct platform_device *pdev);
 void ep93xx_init_devices(void);
 extern void ep93xx_timer_init(void);
-void ep93xx_restart(char, const char *);
+void ep93xx_restart(enum reboot_mode, const char *);
 void ep93xx_init_late(void);
 #ifdef CONFIG_CRUNCH
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index ff18fc2ea46f..5952e68c76c4 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -14,9 +14,11 @@ menu "SAMSUNG EXYNOS SoCs Support"
 config ARCH_EXYNOS4
        bool "SAMSUNG EXYNOS4"
        default y
+        select GIC_NON_BANKED
        select HAVE_ARM_SCU if SMP
        select HAVE_SMP
        select MIGHT_HAVE_CACHE_L2X0
+        select PINCTRL
        help
          Samsung EXYNOS4 SoCs based systems
@@ -24,6 +26,7 @@ config ARCH_EXYNOS5
        bool "SAMSUNG EXYNOS5"
        select HAVE_ARM_SCU if SMP
        select HAVE_SMP
+        select PINCTRL
        help
          Samsung EXYNOS5 (Cortex-A15) SoC based systems
@@ -34,7 +37,8 @@ config CPU_EXYNOS4210
        default y
        depends on ARCH_EXYNOS4
        select ARM_CPU_SUSPEND if PM
-        select PM_GENERIC_DOMAINS
+        select PINCTRL_EXYNOS
+        select PM_GENERIC_DOMAINS if PM
        select S5P_PM if PM
        select S5P_SLEEP if PM
        select SAMSUNG_DMADEV
@@ -45,6 +49,7 @@ config SOC_EXYNOS4212
        bool "SAMSUNG EXYNOS4212"
        default y
        depends on ARCH_EXYNOS4
+        select PINCTRL_EXYNOS
        select S5P_PM if PM
        select S5P_SLEEP if PM
        select SAMSUNG_DMADEV
@@ -55,6 +60,7 @@ config SOC_EXYNOS4412
        bool "SAMSUNG EXYNOS4412"
        default y
        depends on ARCH_EXYNOS4
+        select PINCTRL_EXYNOS
        select SAMSUNG_DMADEV
        help
          Enable EXYNOS4412 SoC support
@@ -63,6 +69,7 @@ config SOC_EXYNOS5250
        bool "SAMSUNG EXYNOS5250"
        default y
        depends on ARCH_EXYNOS5
+        select PINCTRL_EXYNOS
        select PM_GENERIC_DOMAINS if PM
        select S5P_PM if PM
        select S5P_SLEEP if PM
@@ -71,352 +78,43 @@ config SOC_EXYNOS5250
        help
          Enable EXYNOS5250 SoC support
+config SOC_EXYNOS5420
+        bool "SAMSUNG EXYNOS5420"
+        default y
+        depends on ARCH_EXYNOS5
+        select PM_GENERIC_DOMAINS if PM
+        select S5P_PM if PM
+        select S5P_SLEEP if PM
+        help
+          Enable EXYNOS5420 SoC support
 config SOC_EXYNOS5440
        bool "SAMSUNG EXYNOS5440"
        default y
        depends on ARCH_EXYNOS5
+        select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
        select ARCH_HAS_OPP
-        select ARM_ARCH_TIMER
+        select HAVE_ARM_ARCH_TIMER
        select AUTO_ZRELADDR
-        select PINCTRL
+        select MIGHT_HAVE_PCI
+        select PCI_DOMAINS if PCI
        select PINCTRL_EXYNOS5440
        select PM_OPP
        help
          Enable EXYNOS5440 SoC support
-config EXYNOS_ATAGS
-        bool "ATAGS based boot for EXYNOS (deprecated)"
-        depends on !ARCH_MULTIPLATFORM
-        depends on ATAGS
-        default y
-        help
-          The EXYNOS platform is moving towards being completely probed
-          through device tree. This enables support for board files using
-          the traditional ATAGS boot format.
-          Note that this option is not available for multiplatform builds.
-if EXYNOS_ATAGS
-config EXYNOS_DEV_DMA
-        bool
-        help
-          Compile in amba device definitions for DMA controller
-config EXYNOS4_DEV_AHCI
-        bool
-        help
-          Compile in platform device definitions for AHCI
-config EXYNOS4_SETUP_FIMD0
-        bool
-        help
-          Common setup code for FIMD0.
-config EXYNOS4_DEV_USB_OHCI
-        bool
-        help
-          Compile in platform device definition for USB OHCI
-config EXYNOS4_SETUP_I2C1
-        bool
-        help
-          Common setup code for i2c bus 1.
-config EXYNOS4_SETUP_I2C2
-        bool
-        help
-          Common setup code for i2c bus 2.
-config EXYNOS4_SETUP_I2C3
-        bool
-        help
-          Common setup code for i2c bus 3.
-config EXYNOS4_SETUP_I2C4
-        bool
-        help
-          Common setup code for i2c bus 4.
-config EXYNOS4_SETUP_I2C5
-        bool
-        help
-          Common setup code for i2c bus 5.
-config EXYNOS4_SETUP_I2C6
-        bool
-        help
-          Common setup code for i2c bus 6.
-config EXYNOS4_SETUP_I2C7
-        bool
-        help
-          Common setup code for i2c bus 7.
-config EXYNOS4_SETUP_KEYPAD
-        bool
-        help
-          Common setup code for keypad.
-config EXYNOS4_SETUP_SDHCI
-        bool
-        select EXYNOS4_SETUP_SDHCI_GPIO
-        help
-          Internal helper functions for EXYNOS4 based SDHCI systems.
-config EXYNOS4_SETUP_SDHCI_GPIO
-        bool
-        help
-          Common setup code for SDHCI gpio.
-config EXYNOS4_SETUP_FIMC
-        bool
-        help
-          Common setup code for the camera interfaces.
-config EXYNOS4_SETUP_USB_PHY
-        bool
-        help
-          Common setup code for USB PHY controller
-config EXYNOS_SETUP_SPI
-        bool
-        help
-          Common setup code for SPI GPIO configurations.
-# machine support
-if ARCH_EXYNOS4
-comment "EXYNOS4210 Boards"
-config MACH_SMDKC210
-        bool "SMDKC210"
-        select MACH_SMDKV310
-        help
-          Machine support for Samsung SMDKC210
-config MACH_SMDKV310
-        bool "SMDKV310"
-        select CPU_EXYNOS4210
-        select EXYNOS4_DEV_AHCI
-        select EXYNOS4_DEV_USB_OHCI
-        select EXYNOS4_SETUP_FIMD0
-        select EXYNOS4_SETUP_I2C1
-        select EXYNOS4_SETUP_KEYPAD
-        select EXYNOS4_SETUP_SDHCI
-        select EXYNOS4_SETUP_USB_PHY
-        select EXYNOS_DEV_DMA
-        select EXYNOS_DEV_SYSMMU
-        select S3C24XX_PWM
-        select S3C_DEV_HSMMC
-        select S3C_DEV_HSMMC1
-        select S3C_DEV_HSMMC2
-        select S3C_DEV_HSMMC3
-        select S3C_DEV_I2C1
-        select S3C_DEV_RTC
-        select S3C_DEV_USB_HSOTG
-        select S3C_DEV_WDT
-        select S5P_DEV_FIMC0
-        select S5P_DEV_FIMC1
-        select S5P_DEV_FIMC2
-        select S5P_DEV_FIMC3
-        select S5P_DEV_FIMD0
-        select S5P_DEV_G2D
-        select S5P_DEV_I2C_HDMIPHY
-        select S5P_DEV_JPEG
-        select S5P_DEV_MFC
-        select S5P_DEV_TV
-        select S5P_DEV_USB_EHCI
-        select SAMSUNG_DEV_BACKLIGHT
-        select SAMSUNG_DEV_KEYPAD
-        select SAMSUNG_DEV_PWM
-        help
-          Machine support for Samsung SMDKV310
-config MACH_ARMLEX4210
-        bool "ARMLEX4210"
-        select CPU_EXYNOS4210
-        select EXYNOS4_DEV_AHCI
-        select EXYNOS4_SETUP_SDHCI
-        select EXYNOS_DEV_DMA
-        select S3C_DEV_HSMMC
-        select S3C_DEV_HSMMC2
-        select S3C_DEV_HSMMC3
-        select S3C_DEV_RTC
-        select S3C_DEV_WDT
-        help
-          Machine support for Samsung ARMLEX4210 based on EXYNOS4210
-config MACH_UNIVERSAL_C210
-        bool "Mobile UNIVERSAL_C210 Board"
-        select CLKSRC_MMIO
-        select CLKSRC_SAMSUNG_PWM
-        select CPU_EXYNOS4210
-        select EXYNOS4_SETUP_FIMC
-        select EXYNOS4_SETUP_FIMD0
-        select EXYNOS4_SETUP_I2C1
-        select EXYNOS4_SETUP_I2C3
-        select EXYNOS4_SETUP_I2C5
-        select EXYNOS4_SETUP_SDHCI
-        select EXYNOS4_SETUP_USB_PHY
-        select EXYNOS_DEV_DMA
-        select EXYNOS_DEV_SYSMMU
-        select S3C_DEV_HSMMC
-        select S3C_DEV_HSMMC2
-        select S3C_DEV_HSMMC3
-        select S3C_DEV_I2C1
-        select S3C_DEV_I2C3
-        select S3C_DEV_I2C5
-        select S3C_DEV_USB_HSOTG
-        select S5P_DEV_CSIS0
-        select S5P_DEV_FIMC0
-        select S5P_DEV_FIMC1
-        select S5P_DEV_FIMC2
-        select S5P_DEV_FIMC3
-        select S5P_DEV_FIMD0
-        select S5P_DEV_G2D
-        select S5P_DEV_I2C_HDMIPHY
-        select S5P_DEV_JPEG
-        select S5P_DEV_MFC
-        select S5P_DEV_ONENAND
-        select S5P_DEV_TV
-        select S5P_GPIO_INT
-        select S5P_SETUP_MIPIPHY
-        help
-          Machine support for Samsung Mobile Universal S5PC210 Reference
-          Board.
-config MACH_NURI
-        bool "Mobile NURI Board"
-        select CPU_EXYNOS4210
-        select EXYNOS4_SETUP_FIMC
-        select EXYNOS4_SETUP_FIMD0
-        select EXYNOS4_SETUP_I2C1
-        select EXYNOS4_SETUP_I2C3
-        select EXYNOS4_SETUP_I2C5
-        select EXYNOS4_SETUP_I2C6
-        select EXYNOS4_SETUP_SDHCI
-        select EXYNOS4_SETUP_USB_PHY
-        select EXYNOS_DEV_DMA
-        select S3C_DEV_HSMMC
-        select S3C_DEV_HSMMC2
-        select S3C_DEV_HSMMC3
-        select S3C_DEV_I2C1
-        select S3C_DEV_I2C3
-        select S3C_DEV_I2C5
-        select S3C_DEV_I2C6
-        select S3C_DEV_RTC
-        select S3C_DEV_USB_HSOTG
-        select S3C_DEV_WDT
-        select S5P_DEV_CSIS0
-        select S5P_DEV_FIMC0
-        select S5P_DEV_FIMC1
-        select S5P_DEV_FIMC2
-        select S5P_DEV_FIMC3
-        select S5P_DEV_FIMD0
-        select S5P_DEV_G2D
-        select S5P_DEV_JPEG
-        select S5P_DEV_MFC
-        select S5P_DEV_USB_EHCI
-        select S5P_GPIO_INT
-        select S5P_SETUP_MIPIPHY
-        select SAMSUNG_DEV_ADC
-        select SAMSUNG_DEV_PWM
-        help
-          Machine support for Samsung Mobile NURI Board.
-config MACH_ORIGEN
-        bool "ORIGEN"
-        select CPU_EXYNOS4210
-        select EXYNOS4_DEV_USB_OHCI
-        select EXYNOS4_SETUP_FIMD0
-        select EXYNOS4_SETUP_SDHCI
-        select EXYNOS4_SETUP_USB_PHY
-        select EXYNOS_DEV_DMA
-        select EXYNOS_DEV_SYSMMU
-        select S3C24XX_PWM
-        select S3C_DEV_HSMMC
-        select S3C_DEV_HSMMC2
-        select S3C_DEV_RTC
-        select S3C_DEV_USB_HSOTG
-        select S3C_DEV_WDT
-        select S5P_DEV_FIMC0
-        select S5P_DEV_FIMC1
-        select S5P_DEV_FIMC2
-        select S5P_DEV_FIMC3
-        select S5P_DEV_FIMD0
-        select S5P_DEV_G2D
-        select S5P_DEV_I2C_HDMIPHY
-        select S5P_DEV_JPEG
-        select S5P_DEV_MFC
-        select S5P_DEV_TV
-        select S5P_DEV_USB_EHCI
-        select SAMSUNG_DEV_BACKLIGHT
-        select SAMSUNG_DEV_PWM
-        help
-          Machine support for ORIGEN based on Samsung EXYNOS4210
-comment "EXYNOS4212 Boards"
-config MACH_SMDK4212
-        bool "SMDK4212"
-        select EXYNOS4_SETUP_FIMD0
-        select EXYNOS4_SETUP_I2C1
-        select EXYNOS4_SETUP_I2C3
-        select EXYNOS4_SETUP_I2C7
-        select EXYNOS4_SETUP_KEYPAD
-        select EXYNOS4_SETUP_SDHCI
-        select EXYNOS4_SETUP_USB_PHY
-        select EXYNOS_DEV_DMA
-        select EXYNOS_DEV_SYSMMU
-        select S3C24XX_PWM
-        select S3C_DEV_HSMMC2
-        select S3C_DEV_HSMMC3
-        select S3C_DEV_I2C1
-        select S3C_DEV_I2C3
-        select S3C_DEV_I2C7
-        select S3C_DEV_RTC
-        select S3C_DEV_USB_HSOTG
-        select S3C_DEV_WDT
-        select S5P_DEV_FIMC0
-        select S5P_DEV_FIMC1
-        select S5P_DEV_FIMC2
-        select S5P_DEV_FIMC3
-        select S5P_DEV_FIMD0
-        select S5P_DEV_MFC
-        select SAMSUNG_DEV_BACKLIGHT
-        select SAMSUNG_DEV_KEYPAD
-        select SAMSUNG_DEV_PWM
-        select SOC_EXYNOS4212
-        help
-          Machine support for Samsung SMDK4212
-comment "EXYNOS4412 Boards"
-config MACH_SMDK4412
-        bool "SMDK4412"
-        select MACH_SMDK4212
-        select SOC_EXYNOS4412
-        help
-          Machine support for Samsung SMDK4412
-endif
-endif
 comment "Flattened Device Tree based board for EXYNOS SoCs"
 config MACH_EXYNOS4_DT
        bool "Samsung Exynos4 Machine using device tree"
+        default y
        depends on ARCH_EXYNOS4
        select ARM_AMBA
        select CLKSRC_OF
        select CLKSRC_SAMSUNG_PWM if CPU_EXYNOS4210
        select CPU_EXYNOS4210
        select KEYBOARD_SAMSUNG if INPUT_KEYBOARD
-        select PINCTRL
-        select PINCTRL_EXYNOS
        select S5P_DEV_MFC
-        select USE_OF
        help
          Machine support for Samsung Exynos4 machine with device tree enabled.
          Select this if a fdt blob is available for the Exynos4 SoC based board.
@@ -429,28 +127,11 @@ config MACH_EXYNOS5_DT
        depends on ARCH_EXYNOS5
        select ARM_AMBA
        select CLKSRC_OF
-        select USE_OF
+        select USB_ARCH_HAS_XHCI
        help
          Machine support for Samsung EXYNOS5 machine with device tree enabled.
          Select this if a fdt blob is available for the EXYNOS5 SoC based board.
-if ARCH_EXYNOS4
-comment "Configuration for HSMMC 8-bit bus width"
-config EXYNOS4_SDHCI_CH0_8BIT
-        bool "Channel 0 with 8-bit bus"
-        help
-          Support HSMMC Channel 0 8-bit bus.
-          If selected, Channel 1 is disabled.
-config EXYNOS4_SDHCI_CH2_8BIT
-        bool "Channel 2 with 8-bit bus"
-        help
-          Support HSMMC Channel 2 8-bit bus.
-          If selected, Channel 3 is disabled.
-endif
 endmenu
 endif
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index b09b027178f3..53696154aead 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -14,7 +14,7 @@ obj-				:=
 obj-$(CONFIG_ARCH_EXYNOS)       += common.o
-obj-$(CONFIG_PM)                += pm.o
+obj-$(CONFIG_S5P_PM)            += pm.o
 obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
 obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
@@ -32,38 +32,5 @@ AFLAGS_exynos-smc.o		:=-Wa,-march=armv7-a$(plus_sec)
 # machine support
-obj-$(CONFIG_MACH_SMDKC210)             += mach-smdkv310.o
-obj-$(CONFIG_MACH_SMDKV310)             += mach-smdkv310.o
-obj-$(CONFIG_MACH_ARMLEX4210)           += mach-armlex4210.o
-obj-$(CONFIG_MACH_UNIVERSAL_C210)       += mach-universal_c210.o
-obj-$(CONFIG_MACH_NURI)                 += mach-nuri.o
-obj-$(CONFIG_MACH_ORIGEN)               += mach-origen.o
-obj-$(CONFIG_MACH_SMDK4212)             += mach-smdk4x12.o
-obj-$(CONFIG_MACH_SMDK4412)             += mach-smdk4x12.o
 obj-$(CONFIG_MACH_EXYNOS4_DT)           += mach-exynos4-dt.o
 obj-$(CONFIG_MACH_EXYNOS5_DT)           += mach-exynos5-dt.o
-# device support
-obj-y                                   += dev-uart.o
-obj-$(CONFIG_ARCH_EXYNOS4)              += dev-audio.o
-obj-$(CONFIG_EXYNOS4_DEV_AHCI)          += dev-ahci.o
-obj-$(CONFIG_EXYNOS_DEV_DMA)            += dma.o
-obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI)      += dev-ohci.o
-obj-$(CONFIG_ARCH_EXYNOS)               += setup-i2c0.o
-obj-$(CONFIG_EXYNOS4_SETUP_FIMC)        += setup-fimc.o
-obj-$(CONFIG_EXYNOS4_SETUP_FIMD0)       += setup-fimd0.o
-obj-$(CONFIG_EXYNOS4_SETUP_I2C1)        += setup-i2c1.o
-obj-$(CONFIG_EXYNOS4_SETUP_I2C2)        += setup-i2c2.o
-obj-$(CONFIG_EXYNOS4_SETUP_I2C3)        += setup-i2c3.o
-obj-$(CONFIG_EXYNOS4_SETUP_I2C4)        += setup-i2c4.o
-obj-$(CONFIG_EXYNOS4_SETUP_I2C5)        += setup-i2c5.o
-obj-$(CONFIG_EXYNOS4_SETUP_I2C6)        += setup-i2c6.o
-obj-$(CONFIG_EXYNOS4_SETUP_I2C7)        += setup-i2c7.o
-obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD)      += setup-keypad.o
-obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
-obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY)     += setup-usb-phy.o
-obj-$(CONFIG_EXYNOS_SETUP_SPI)          += setup-spi.o
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index f7e504b7874d..ba95e5db2501 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -40,20 +40,9 @@
 #include <mach/regs-irq.h>
 #include <mach/regs-pmu.h>
-#include <mach/regs-gpio.h>
-#include <mach/irqs.h>
 #include <plat/cpu.h>
-#include <plat/devs.h>
 #include <plat/pm.h>
-#include <plat/sdhci.h>
-#include <plat/gpio-cfg.h>
-#include <plat/adc-core.h>
-#include <plat/fb-core.h>
-#include <plat/fimc-core.h>
-#include <plat/iic-core.h>
-#include <plat/tv-core.h>
-#include <plat/spi-core.h>
 #include <plat/regs-serial.h>
 #include "common.h"
@@ -64,36 +53,30 @@ static const char name_exynos4210[] = "EXYNOS4210";
 static const char name_exynos4212[] = "EXYNOS4212";
 static const char name_exynos4412[] = "EXYNOS4412";
 static const char name_exynos5250[] = "EXYNOS5250";
+static const char name_exynos5420[] = "EXYNOS5420";
 static const char name_exynos5440[] = "EXYNOS5440";
 static void exynos4_map_io(void);
 static void exynos5_map_io(void);
-static void exynos5440_map_io(void);
-static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 static int exynos_init(void);
-unsigned long xxti_f = 0, xusbxti_f = 0;
 static struct cpu_table cpu_ids[] __initdata = {
        {
                .idcode         = EXYNOS4210_CPU_ID,
                .idmask         = EXYNOS4_CPU_MASK,
                .map_io         = exynos4_map_io,
-                .init_uarts     = exynos4_init_uarts,
                .init           = exynos_init,
                .name           = name_exynos4210,
        }, {
                .idcode         = EXYNOS4212_CPU_ID,
                .idmask         = EXYNOS4_CPU_MASK,
                .map_io         = exynos4_map_io,
-                .init_uarts     = exynos4_init_uarts,
                .init           = exynos_init,
                .name           = name_exynos4212,
        }, {
                .idcode         = EXYNOS4412_CPU_ID,
                .idmask         = EXYNOS4_CPU_MASK,
                .map_io         = exynos4_map_io,
-                .init_uarts     = exynos4_init_uarts,
                .init           = exynos_init,
                .name           = name_exynos4412,
        }, {
@@ -103,9 +86,14 @@ static struct cpu_table cpu_ids[] __initdata = {
                .init           = exynos_init,
                .name           = name_exynos5250,
        }, {
+                .idcode         = EXYNOS5420_SOC_ID,
+                .idmask         = EXYNOS5_SOC_MASK,
+                .map_io         = exynos5_map_io,
+                .init           = exynos_init,
+                .name           = name_exynos5420,
+        }, {
                .idcode         = EXYNOS5440_SOC_ID,
                .idmask         = EXYNOS5_SOC_MASK,
-                .map_io         = exynos5440_map_io,
                .init           = exynos_init,
                .name           = name_exynos5440,
        },
@@ -113,15 +101,6 @@ static struct cpu_table cpu_ids[] __initdata = {
 /* Initial IO mappings */
-static struct map_desc exynos_iodesc[] __initdata = {
-        {
-                .virtual        = (unsigned long)S5P_VA_CHIPID,
-                .pfn            = __phys_to_pfn(EXYNOS_PA_CHIPID),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        },
-};
 static struct map_desc exynos4_iodesc[] __initdata = {
        {
                .virtual        = (unsigned long)S3C_VA_SYS,
@@ -169,11 +148,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
                .length         = SZ_64K,
                .type           = MT_DEVICE,
        }, {
-                .virtual        = (unsigned long)S3C_VA_UART,
-                .pfn            = __phys_to_pfn(EXYNOS4_PA_UART),
-                .length         = SZ_512K,
-                .type           = MT_DEVICE,
-        }, {
                .virtual        = (unsigned long)S5P_VA_CMU,
                .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
                .length         = SZ_128K,
@@ -287,45 +261,24 @@ static struct map_desc exynos5_iodesc[] __initdata = {
                .pfn            = __phys_to_pfn(EXYNOS5_PA_PMU),
                .length         = SZ_64K,
                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S3C_VA_UART,
-                .pfn            = __phys_to_pfn(EXYNOS5_PA_UART),
-                .length         = SZ_512K,
-                .type           = MT_DEVICE,
-        },
-};
-static struct map_desc exynos5440_iodesc0[] __initdata = {
-        {
-                .virtual        = (unsigned long)S3C_VA_UART,
-                .pfn            = __phys_to_pfn(EXYNOS5440_PA_UART0),
-                .length         = SZ_512K,
-                .type           = MT_DEVICE,
        },
 };
-static struct samsung_pwm_variant exynos4_pwm_variant = {
+void exynos4_restart(enum reboot_mode mode, const char *cmd)
-        .bits           = 32,
-        .div_base       = 0,
-        .has_tint_cstat = true,
-        .tclk_mask      = 0,
-};
-void exynos4_restart(char mode, const char *cmd)
 {
        __raw_writel(0x1, S5P_SWRESET);
 }
-void exynos5_restart(char mode, const char *cmd)
+void exynos5_restart(enum reboot_mode mode, const char *cmd)
 {
        struct device_node *np;
        u32 val;
        void __iomem *addr;
-        if (of_machine_is_compatible("samsung,exynos5250")) {
+        val = 0x1;
-                val = 0x1;
+        addr = EXYNOS_SWRESET;
-                addr = EXYNOS_SWRESET;
-        } else if (of_machine_is_compatible("samsung,exynos5440")) {
+        if (of_machine_is_compatible("samsung,exynos5440")) {
                u32 status;
                np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
@@ -336,9 +289,6 @@ void exynos5_restart(char mode, const char *cmd)
                val = __raw_readl(addr);
                val = (val & 0xffff0000) | (status & 0xffff);
-        } else {
-                pr_err("%s: cannot support non-DT\n", __func__);
-                return;
        }
        __raw_writel(val, addr);
@@ -353,8 +303,7 @@ void __init exynos_init_late(void)
        exynos_pm_late_initcall();
 }
-#ifdef CONFIG_OF
+static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
-int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
                                        int depth, void *data)
 {
        struct map_desc iodesc;
@@ -376,7 +325,6 @@ int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
        iotable_init(&iodesc, 1);
        return 1;
 }
-#endif
 /*
 * exynos_map_io
@@ -384,19 +332,11 @@ int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
 * register the standard cpu IO areas
 */
-void __init exynos_init_io(struct map_desc *mach_desc, int size)
+void __init exynos_init_io(void)
 {
        debug_ll_io_init();
-#ifdef CONFIG_OF
+        of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
-        if (initial_boot_params)
-                of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
-        else
-#endif
-                iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
-        if (mach_desc)
-                iotable_init(mach_desc, size);
        /* detect cpu id and rev. */
        s5p_init_cpu(S5P_VA_CHIPID);
@@ -417,34 +357,6 @@ static void __init exynos4_map_io(void)
                iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
        if (soc_is_exynos4212() || soc_is_exynos4412())
                iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
-        /* initialize device information early */
-        exynos4_default_sdhci0();
-        exynos4_default_sdhci1();
-        exynos4_default_sdhci2();
-        exynos4_default_sdhci3();
-        s3c_adc_setname("samsung-adc-v3");
-        s3c_fimc_setname(0, "exynos4-fimc");
-        s3c_fimc_setname(1, "exynos4-fimc");
-        s3c_fimc_setname(2, "exynos4-fimc");
-        s3c_fimc_setname(3, "exynos4-fimc");
-        s3c_sdhci_setname(0, "exynos4-sdhci");
-        s3c_sdhci_setname(1, "exynos4-sdhci");
-        s3c_sdhci_setname(2, "exynos4-sdhci");
-        s3c_sdhci_setname(3, "exynos4-sdhci");
-        /* The I2C bus controllers are directly compatible with s3c2440 */
-        s3c_i2c0_setname("s3c2440-i2c");
-        s3c_i2c1_setname("s3c2440-i2c");
-        s3c_i2c2_setname("s3c2440-i2c");
-        s5p_fb_setname(0, "exynos4-fb");
-        s5p_hdmi_setname("exynos4-hdmi");
-        s3c64xx_spi_setname("exynos4210-spi");
 }
 static void __init exynos5_map_io(void)
@@ -455,86 +367,10 @@ static void __init exynos5_map_io(void)
                iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
 }
-static void __init exynos5440_map_io(void)
-{
-        iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
-}
-void __init exynos_set_timer_source(u8 channels)
-{
-        exynos4_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
-        exynos4_pwm_variant.output_mask &= ~channels;
-}
 void __init exynos_init_time(void)
 {
-        unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
+        of_clk_init(NULL);
-                EXYNOS4_IRQ_TIMER0_VIC, EXYNOS4_IRQ_TIMER1_VIC,
+        clocksource_of_init();
-                EXYNOS4_IRQ_TIMER2_VIC, EXYNOS4_IRQ_TIMER3_VIC,
-                EXYNOS4_IRQ_TIMER4_VIC,
-        };
-        if (of_have_populated_dt()) {
-#ifdef CONFIG_OF
-                of_clk_init(NULL);
-                clocksource_of_init();
-#endif
-        } else {
-                /* todo: remove after migrating legacy E4 platforms to dt */
-#ifdef CONFIG_ARCH_EXYNOS4
-                exynos4_clk_init(NULL, !soc_is_exynos4210(), S5P_VA_CMU, readl(S5P_VA_CHIPID + 8) & 1);
-                exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
-#endif
-#ifdef CONFIG_CLKSRC_SAMSUNG_PWM
-                if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
-                        samsung_pwm_clocksource_init(S3C_VA_TIMER,
-                                        timer_irqs, &exynos4_pwm_variant);
-                else
-#endif
-                        mct_init(S5P_VA_SYSTIMER, EXYNOS4_IRQ_MCT_G0,
-                                        EXYNOS4_IRQ_MCT_L0, EXYNOS4_IRQ_MCT_L1);
-        }
-}
-static unsigned int max_combiner_nr(void)
-{
-        if (soc_is_exynos5250())
-                return EXYNOS5_MAX_COMBINER_NR;
-        else if (soc_is_exynos4412())
-                return EXYNOS4412_MAX_COMBINER_NR;
-        else if (soc_is_exynos4212())
-                return EXYNOS4212_MAX_COMBINER_NR;
-        else
-                return EXYNOS4210_MAX_COMBINER_NR;
-}
-void __init exynos4_init_irq(void)
-{
-        unsigned int gic_bank_offset;
-        gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
-        if (!of_have_populated_dt())
-                gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
-#ifdef CONFIG_OF
-        else
-                irqchip_init();
-#endif
-        if (!of_have_populated_dt())
-                combiner_init(S5P_VA_COMBINER_BASE, NULL,
-                              max_combiner_nr(), COMBINER_IRQ(0, 0));
-        gic_arch_extn.irq_set_wake = s3c_irq_wake;
-}
-void __init exynos5_init_irq(void)
-{
-#ifdef CONFIG_OF
-        irqchip_init();
-#endif
-        gic_arch_extn.irq_set_wake = s3c_irq_wake;
 }
 struct bus_type exynos_subsys = {
@@ -552,59 +388,19 @@ static int __init exynos_core_init(void)
 }
 core_initcall(exynos_core_init);
-#ifdef CONFIG_CACHE_L2X0
 static int __init exynos4_l2x0_cache_init(void)
 {
        int ret;
-        if (soc_is_exynos5250() || soc_is_exynos5440())
-                return 0;
        ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
-        if (!ret) {
+        if (ret)
-                l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
+                return ret;
-                clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
-                return 0;
-        }
-        if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
-                l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
-                /* TAG, Data Latency Control: 2 cycles */
-                l2x0_saved_regs.tag_latency = 0x110;
-                if (soc_is_exynos4212() || soc_is_exynos4412())
-                        l2x0_saved_regs.data_latency = 0x120;
-                else
-                        l2x0_saved_regs.data_latency = 0x110;
-                l2x0_saved_regs.prefetch_ctrl = 0x30000007;
+        l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
-                l2x0_saved_regs.pwr_ctrl =
+        clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
-                        (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
-                l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
-                __raw_writel(l2x0_saved_regs.tag_latency,
-                                S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
-                __raw_writel(l2x0_saved_regs.data_latency,
-                                S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
-                /* L2X0 Prefetch Control */
-                __raw_writel(l2x0_saved_regs.prefetch_ctrl,
-                                S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
-                /* L2X0 Power Control */
-                __raw_writel(l2x0_saved_regs.pwr_ctrl,
-                                S5P_VA_L2CC + L2X0_POWER_CTRL);
-                clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
-                clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
-        }
-        l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
        return 0;
 }
 early_initcall(exynos4_l2x0_cache_init);
-#endif
 static int __init exynos_init(void)
 {
@@ -612,350 +408,3 @@ static int __init exynos_init(void)
        return device_register(&exynos4_dev);
 }
-/* uart registration process */
-static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
-{
-        struct s3c2410_uartcfg *tcfg = cfg;
-        u32 ucnt;
-        for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
-                tcfg->has_fracval = 1;
-        s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
-}
-static void __iomem *exynos_eint_base;
-static DEFINE_SPINLOCK(eint_lock);
-static unsigned int eint0_15_data[16];
-static inline int exynos4_irq_to_gpio(unsigned int irq)
-{
-        if (irq < IRQ_EINT(0))
-                return -EINVAL;
-        irq -= IRQ_EINT(0);
-        if (irq < 8)
-                return EXYNOS4_GPX0(irq);
-        irq -= 8;
-        if (irq < 8)
-                return EXYNOS4_GPX1(irq);
-        irq -= 8;
-        if (irq < 8)
-                return EXYNOS4_GPX2(irq);
-        irq -= 8;
-        if (irq < 8)
-                return EXYNOS4_GPX3(irq);
-        return -EINVAL;
-}
-static inline int exynos5_irq_to_gpio(unsigned int irq)
-{
-        if (irq < IRQ_EINT(0))
-                return -EINVAL;
-        irq -= IRQ_EINT(0);
-        if (irq < 8)
-                return EXYNOS5_GPX0(irq);
-        irq -= 8;
-        if (irq < 8)
-                return EXYNOS5_GPX1(irq);
-        irq -= 8;
-        if (irq < 8)
-                return EXYNOS5_GPX2(irq);
-        irq -= 8;
-        if (irq < 8)
-                return EXYNOS5_GPX3(irq);
-        return -EINVAL;
-}
-static unsigned int exynos4_eint0_15_src_int[16] = {
-        EXYNOS4_IRQ_EINT0,
-        EXYNOS4_IRQ_EINT1,
-        EXYNOS4_IRQ_EINT2,
-        EXYNOS4_IRQ_EINT3,
-        EXYNOS4_IRQ_EINT4,
-        EXYNOS4_IRQ_EINT5,
-        EXYNOS4_IRQ_EINT6,
-        EXYNOS4_IRQ_EINT7,
-        EXYNOS4_IRQ_EINT8,
-        EXYNOS4_IRQ_EINT9,
-        EXYNOS4_IRQ_EINT10,
-        EXYNOS4_IRQ_EINT11,
-        EXYNOS4_IRQ_EINT12,
-        EXYNOS4_IRQ_EINT13,
-        EXYNOS4_IRQ_EINT14,
-        EXYNOS4_IRQ_EINT15,
-};
-static unsigned int exynos5_eint0_15_src_int[16] = {
-        EXYNOS5_IRQ_EINT0,
-        EXYNOS5_IRQ_EINT1,
-        EXYNOS5_IRQ_EINT2,
-        EXYNOS5_IRQ_EINT3,
-        EXYNOS5_IRQ_EINT4,
-        EXYNOS5_IRQ_EINT5,
-        EXYNOS5_IRQ_EINT6,
-        EXYNOS5_IRQ_EINT7,
-        EXYNOS5_IRQ_EINT8,
-        EXYNOS5_IRQ_EINT9,
-        EXYNOS5_IRQ_EINT10,
-        EXYNOS5_IRQ_EINT11,
-        EXYNOS5_IRQ_EINT12,
-        EXYNOS5_IRQ_EINT13,
-        EXYNOS5_IRQ_EINT14,
-        EXYNOS5_IRQ_EINT15,
-};
-static inline void exynos_irq_eint_mask(struct irq_data *data)
-{
-        u32 mask;
-        spin_lock(&eint_lock);
-        mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
-        mask |= EINT_OFFSET_BIT(data->irq);
-        __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
-        spin_unlock(&eint_lock);
-}
-static void exynos_irq_eint_unmask(struct irq_data *data)
-{
-        u32 mask;
-        spin_lock(&eint_lock);
-        mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
-        mask &= ~(EINT_OFFSET_BIT(data->irq));
-        __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
-        spin_unlock(&eint_lock);
-}
-static inline void exynos_irq_eint_ack(struct irq_data *data)
-{
-        __raw_writel(EINT_OFFSET_BIT(data->irq),
-                     EINT_PEND(exynos_eint_base, data->irq));
-}
-static void exynos_irq_eint_maskack(struct irq_data *data)
-{
-        exynos_irq_eint_mask(data);
-        exynos_irq_eint_ack(data);
-}
-static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
-{
-        int offs = EINT_OFFSET(data->irq);
-        int shift;
-        u32 ctrl, mask;
-        u32 newvalue = 0;
-        switch (type) {
-        case IRQ_TYPE_EDGE_RISING:
-                newvalue = S5P_IRQ_TYPE_EDGE_RISING;
-                break;
-        case IRQ_TYPE_EDGE_FALLING:
-                newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
-                break;
-        case IRQ_TYPE_EDGE_BOTH:
-                newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
-                break;
-        case IRQ_TYPE_LEVEL_LOW:
-                newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
-                break;
-        case IRQ_TYPE_LEVEL_HIGH:
-                newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
-                break;
-        default:
-                printk(KERN_ERR "No such irq type %d", type);
-                return -EINVAL;
-        }
-        shift = (offs & 0x7) * 4;
-        mask = 0x7 << shift;
-        spin_lock(&eint_lock);
-        ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
-        ctrl &= ~mask;
-        ctrl |= newvalue << shift;
-        __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
-        spin_unlock(&eint_lock);
-        if (soc_is_exynos5250())
-                s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
-        else
-                s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
-        return 0;
-}
-static struct irq_chip exynos_irq_eint = {
-        .name           = "exynos-eint",
-        .irq_mask       = exynos_irq_eint_mask,
-        .irq_unmask     = exynos_irq_eint_unmask,
-        .irq_mask_ack   = exynos_irq_eint_maskack,
-        .irq_ack        = exynos_irq_eint_ack,
-        .irq_set_type   = exynos_irq_eint_set_type,
-#ifdef CONFIG_PM
-        .irq_set_wake   = s3c_irqext_wake,
-#endif
-};
-/*
- * exynos4_irq_demux_eint
- *
- * This function demuxes the IRQ from from EINTs 16 to 31.
- * It is designed to be inlined into the specific handler
- * s5p_irq_demux_eintX_Y.
- *
- * Each EINT pend/mask registers handle eight of them.
- */
-static inline void exynos_irq_demux_eint(unsigned int start)
-{
-        unsigned int irq;
-        u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
-        u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
-        status &= ~mask;
-        status &= 0xff;
-        while (status) {
-                irq = fls(status) - 1;
-                generic_handle_irq(irq + start);
-                status &= ~(1 << irq);
-        }
-}
-static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
-{
-        struct irq_chip *chip = irq_get_chip(irq);
-        chained_irq_enter(chip, desc);
-        exynos_irq_demux_eint(IRQ_EINT(16));
-        exynos_irq_demux_eint(IRQ_EINT(24));
-        chained_irq_exit(chip, desc);
-}
-static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
-{
-        u32 *irq_data = irq_get_handler_data(irq);
-        struct irq_chip *chip = irq_get_chip(irq);
-        chained_irq_enter(chip, desc);
-        generic_handle_irq(*irq_data);
-        chained_irq_exit(chip, desc);
-}
-static int __init exynos_init_irq_eint(void)
-{
-        int irq;
-#ifdef CONFIG_PINCTRL_SAMSUNG
-        /*
-         * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf
-         * functionality along with support for external gpio and wakeup
-         * interrupts. If the samsung pinctrl driver is enabled and includes
-         * the wakeup interrupt support, then the setting up external wakeup
-         * interrupts here can be skipped. This check here is temporary to
-         * allow exynos4 platforms that do not use Samsung pinctrl driver to
-         * co-exist with platforms that do. When all of the Samsung Exynos4
-         * platforms switch over to using the pinctrl driver, the wakeup
-         * interrupt support code here can be completely removed.
-         */
-        static const struct of_device_id exynos_pinctrl_ids[] = {
-                { .compatible = "samsung,exynos4210-pinctrl", },
-                { .compatible = "samsung,exynos4x12-pinctrl", },
-                { .compatible = "samsung,exynos5250-pinctrl", },
-        };
-        struct device_node *pctrl_np, *wkup_np;
-        const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
-        for_each_matching_node(pctrl_np, exynos_pinctrl_ids) {
-                if (of_device_is_available(pctrl_np)) {
-                        wkup_np = of_find_compatible_node(pctrl_np, NULL,
-                                                        wkup_compat);
-                        if (wkup_np)
-                                return -ENODEV;
-                }
-        }
-#endif
-        if (soc_is_exynos5440())
-                return 0;
-        if (soc_is_exynos5250())
-                exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
-        else
-                exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
-        if (exynos_eint_base == NULL) {
-                pr_err("unable to ioremap for EINT base address\n");
-                return -ENOMEM;
-        }
-        for (irq = 0 ; irq <= 31 ; irq++) {
-                irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
-                                         handle_level_irq);
-                set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
-        }
-        irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
-        for (irq = 0 ; irq <= 15 ; irq++) {
-                eint0_15_data[irq] = IRQ_EINT(irq);
-                if (soc_is_exynos5250()) {
-                        irq_set_handler_data(exynos5_eint0_15_src_int[irq],
-                                             &eint0_15_data[irq]);
-                        irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
-                                                exynos_irq_eint0_15);
-                } else {
-                        irq_set_handler_data(exynos4_eint0_15_src_int[irq],
-                                             &eint0_15_data[irq]);
-                        irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
-                                                exynos_irq_eint0_15);
-                }
-        }
-        return 0;
-}
-arch_initcall(exynos_init_irq_eint);
-static struct resource exynos4_pmu_resource[] = {
-        DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
-        DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
-#if defined(CONFIG_SOC_EXYNOS4412)
-        DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU2),
-        DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU3),
-#endif
-};
-static struct platform_device exynos4_device_pmu = {
-        .name           = "arm-pmu",
-        .num_resources  = ARRAY_SIZE(exynos4_pmu_resource),
-        .resource       = exynos4_pmu_resource,
-};
-static int __init exynos_armpmu_init(void)
-{
-        if (!of_have_populated_dt()) {
-                if (soc_is_exynos4210() || soc_is_exynos4212())
-                        exynos4_device_pmu.num_resources = 2;
-                platform_device_register(&exynos4_device_pmu);
-        }
-        return 0;
-}
-arch_initcall(exynos_armpmu_init);
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 11fc1e29819b..972490fc09d6 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -12,6 +12,7 @@
 #ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
 #define __ARCH_ARM_MACH_EXYNOS_COMMON_H
+#include <linux/reboot.h>
 #include <linux/of.h>
 void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1);
@@ -19,11 +20,9 @@ void exynos_init_time(void);
 extern unsigned long xxti_f, xusbxti_f;
 struct map_desc;
-void exynos_init_io(struct map_desc *mach_desc, int size);
+void exynos_init_io(void);
-void exynos4_init_irq(void);
+void exynos4_restart(enum reboot_mode mode, const char *cmd);
-void exynos5_init_irq(void);
+void exynos5_restart(enum reboot_mode mode, const char *cmd);
-void exynos4_restart(char mode, const char *cmd);
-void exynos5_restart(char mode, const char *cmd);
 void exynos_init_late(void);
 /* ToDo: remove these after migrating legacy exynos4 platforms to dt */
@@ -98,6 +97,5 @@ struct exynos_pmu_conf {
 };
 extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
-extern void s3c_cpu_resume(void);
 #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 17a18ff3d71e..225ee8431c72 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -25,6 +25,7 @@
 #include <mach/regs-pmu.h>
 #include <plat/cpu.h>
+#include <plat/pm.h>
 #include "common.h"
diff --git a/arch/arm/mach-exynos/dev-ahci.c b/arch/arm/mach-exynos/dev-ahci.c
deleted file mode 100644
index ce1aad3eeeb9..000000000000
--- a/arch/arm/mach-exynos/dev-ahci.c
+++ /dev/null
@@ -1,255 +0,0 @@
-/* linux/arch/arm/mach-exynos4/dev-ahci.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 - AHCI support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/ahci_platform.h>
-#include <plat/cpu.h>
-#include <mach/irqs.h>
-#include <mach/map.h>
-#include <mach/regs-pmu.h>
-/* PHY Control Register */
-#define SATA_CTRL0              0x0
-/* PHY Link Control Register */
-#define SATA_CTRL1              0x4
-/* PHY Status Register */
-#define SATA_PHY_STATUS         0x8
-#define SATA_CTRL0_RX_DATA_VALID(x)     (x << 27)
-#define SATA_CTRL0_SPEED_MODE           (1 << 26)
-#define SATA_CTRL0_M_PHY_CAL            (1 << 19)
-#define SATA_CTRL0_PHY_CMU_RST_N        (1 << 10)
-#define SATA_CTRL0_M_PHY_LN_RST_N       (1 << 9)
-#define SATA_CTRL0_PHY_POR_N            (1 << 8)
-#define SATA_CTRL1_RST_PMALIVE_N        (1 << 8)
-#define SATA_CTRL1_RST_RXOOB_N          (1 << 7)
-#define SATA_CTRL1_RST_RX_N             (1 << 6)
-#define SATA_CTRL1_RST_TX_N             (1 << 5)
-#define SATA_PHY_STATUS_CMU_OK          (1 << 18)
-#define SATA_PHY_STATUS_LANE_OK         (1 << 16)
-#define LANE0           0x200
-#define COM_LANE        0xA00
-#define HOST_PORTS_IMPL 0xC
-#define SCLK_SATA_FREQ  (67 * MHZ)
-static void __iomem *phy_base, *phy_ctrl;
-struct phy_reg {
-        u8      reg;
-        u8      val;
-};
-/* SATA PHY setup */
-static const struct phy_reg exynos4_sataphy_cmu[] = {
-        { 0x00, 0x06 }, { 0x02, 0x80 }, { 0x22, 0xa0 }, { 0x23, 0x42 },
-        { 0x2e, 0x04 }, { 0x2f, 0x50 }, { 0x30, 0x70 }, { 0x31, 0x02 },
-        { 0x32, 0x25 }, { 0x33, 0x40 }, { 0x34, 0x01 }, { 0x35, 0x40 },
-        { 0x61, 0x2e }, { 0x63, 0x5e }, { 0x65, 0x42 }, { 0x66, 0xd1 },
-        { 0x67, 0x20 }, { 0x68, 0x28 }, { 0x69, 0x78 }, { 0x6a, 0x04 },
-        { 0x6b, 0xc8 }, { 0x6c, 0x06 },
-};
-static const struct phy_reg exynos4_sataphy_lane[] = {
-        { 0x00, 0x02 }, { 0x05, 0x10 }, { 0x06, 0x84 }, { 0x07, 0x04 },
-        { 0x08, 0xe0 }, { 0x10, 0x23 }, { 0x13, 0x05 }, { 0x14, 0x30 },
-        { 0x15, 0x00 }, { 0x17, 0x70 }, { 0x18, 0xf2 }, { 0x19, 0x1e },
-        { 0x1a, 0x18 }, { 0x1b, 0x0d }, { 0x1c, 0x08 }, { 0x50, 0x60 },
-        { 0x51, 0x0f },
-};
-static const struct phy_reg exynos4_sataphy_comlane[] = {
-        { 0x01, 0x20 }, { 0x03, 0x40 }, { 0x04, 0x3c }, { 0x05, 0x7d },
-        { 0x06, 0x1d }, { 0x07, 0xcf }, { 0x08, 0x05 }, { 0x09, 0x63 },
-        { 0x0a, 0x29 }, { 0x0b, 0xc4 }, { 0x0c, 0x01 }, { 0x0d, 0x03 },
-        { 0x0e, 0x28 }, { 0x0f, 0x98 }, { 0x10, 0x19 }, { 0x13, 0x80 },
-        { 0x14, 0xf0 }, { 0x15, 0xd0 }, { 0x39, 0xa0 }, { 0x3a, 0xa0 },
-        { 0x3b, 0xa0 }, { 0x3c, 0xa0 }, { 0x3d, 0xa0 }, { 0x3e, 0xa0 },
-        { 0x3f, 0xa0 }, { 0x40, 0x42 }, { 0x42, 0x80 }, { 0x43, 0x58 },
-        { 0x45, 0x44 }, { 0x46, 0x5c }, { 0x47, 0x86 }, { 0x48, 0x8d },
-        { 0x49, 0xd0 }, { 0x4a, 0x09 }, { 0x4b, 0x90 }, { 0x4c, 0x07 },
-        { 0x4d, 0x40 }, { 0x51, 0x20 }, { 0x52, 0x32 }, { 0x7f, 0xd8 },
-        { 0x80, 0x1a }, { 0x81, 0xff }, { 0x82, 0x11 }, { 0x83, 0x00 },
-        { 0x87, 0xf0 }, { 0x87, 0xff }, { 0x87, 0xff }, { 0x87, 0xff },
-        { 0x87, 0xff }, { 0x8c, 0x1c }, { 0x8d, 0xc2 }, { 0x8e, 0xc3 },
-        { 0x8f, 0x3f }, { 0x90, 0x0a }, { 0x96, 0xf8 },
-};
-static int wait_for_phy_ready(void __iomem *reg, unsigned long bit)
-{
-        unsigned long timeout;
-        /* wait for maximum of 3 sec */
-        timeout = jiffies + msecs_to_jiffies(3000);
-        while (!(__raw_readl(reg) & bit)) {
-                if (time_after(jiffies, timeout))
-                        return -1;
-                cpu_relax();
-        }
-        return 0;
-}
-static int ahci_phy_init(void __iomem *mmio)
-{
-        int i, ctrl0;
-        for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_cmu); i++)
-                __raw_writeb(exynos4_sataphy_cmu[i].val,
-                phy_base + (exynos4_sataphy_cmu[i].reg * 4));
-        for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_lane); i++)
-                __raw_writeb(exynos4_sataphy_lane[i].val,
-                phy_base + (LANE0 + exynos4_sataphy_lane[i].reg) * 4);
-        for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_comlane); i++)
-                __raw_writeb(exynos4_sataphy_comlane[i].val,
-                phy_base + (COM_LANE + exynos4_sataphy_comlane[i].reg) * 4);
-        __raw_writeb(0x07, phy_base);
-        ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
-        ctrl0 |= SATA_CTRL0_PHY_CMU_RST_N;
-        __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
-        if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS,
-                                SATA_PHY_STATUS_CMU_OK) < 0) {
-                printk(KERN_ERR "PHY CMU not ready\n");
-                return -EBUSY;
-        }
-        __raw_writeb(0x03, phy_base + (COM_LANE * 4));
-        ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
-        ctrl0 |= SATA_CTRL0_M_PHY_LN_RST_N;
-        __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
-        if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS,
-                                SATA_PHY_STATUS_LANE_OK) < 0) {
-                printk(KERN_ERR "PHY LANE not ready\n");
-                return -EBUSY;
-        }
-        ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
-        ctrl0 |= SATA_CTRL0_M_PHY_CAL;
-        __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
-        return 0;
-}
-static int exynos4_ahci_init(struct device *dev, void __iomem *mmio)
-{
-        struct clk *clk_sata, *clk_sataphy, *clk_sclk_sata;
-        int val, ret;
-        phy_base = ioremap(EXYNOS4_PA_SATAPHY, SZ_64K);
-        if (!phy_base) {
-                dev_err(dev, "failed to allocate memory for SATA PHY\n");
-                return -ENOMEM;
-        }
-        phy_ctrl = ioremap(EXYNOS4_PA_SATAPHY_CTRL, SZ_16);
-        if (!phy_ctrl) {
-                dev_err(dev, "failed to allocate memory for SATA PHY CTRL\n");
-                ret = -ENOMEM;
-                goto err1;
-        }
-        clk_sata = clk_get(dev, "sata");
-        if (IS_ERR(clk_sata)) {
-                dev_err(dev, "failed to get sata clock\n");
-                ret = PTR_ERR(clk_sata);
-                clk_sata = NULL;
-                goto err2;
-        }
-        clk_enable(clk_sata);
-        clk_sataphy = clk_get(dev, "sataphy");
-        if (IS_ERR(clk_sataphy)) {
-                dev_err(dev, "failed to get sataphy clock\n");
-                ret = PTR_ERR(clk_sataphy);
-                clk_sataphy = NULL;
-                goto err3;
-        }
-        clk_enable(clk_sataphy);
-        clk_sclk_sata = clk_get(dev, "sclk_sata");
-        if (IS_ERR(clk_sclk_sata)) {
-                dev_err(dev, "failed to get sclk_sata\n");
-                ret = PTR_ERR(clk_sclk_sata);
-                clk_sclk_sata = NULL;
-                goto err4;
-        }
-        clk_enable(clk_sclk_sata);
-        clk_set_rate(clk_sclk_sata, SCLK_SATA_FREQ);
-        __raw_writel(S5P_PMU_SATA_PHY_CONTROL_EN, S5P_PMU_SATA_PHY_CONTROL);
-        /* Enable PHY link control */
-        val = SATA_CTRL1_RST_PMALIVE_N | SATA_CTRL1_RST_RXOOB_N |
-                        SATA_CTRL1_RST_RX_N | SATA_CTRL1_RST_TX_N;
-        __raw_writel(val, phy_ctrl + SATA_CTRL1);
-        /* Set communication speed as 3Gbps and enable PHY power */
-        val = SATA_CTRL0_RX_DATA_VALID(3) | SATA_CTRL0_SPEED_MODE |
-                        SATA_CTRL0_PHY_POR_N;
-        __raw_writel(val, phy_ctrl + SATA_CTRL0);
-        /* Port0 is available */
-        __raw_writel(0x1, mmio + HOST_PORTS_IMPL);
-        return ahci_phy_init(mmio);
-err4:
-        clk_disable(clk_sataphy);
-        clk_put(clk_sataphy);
-err3:
-        clk_disable(clk_sata);
-        clk_put(clk_sata);
-err2:
-        iounmap(phy_ctrl);
-err1:
-        iounmap(phy_base);
-        return ret;
-}
-static struct ahci_platform_data exynos4_ahci_pdata = {
-        .init = exynos4_ahci_init,
-};
-static struct resource exynos4_ahci_resource[] = {
-        [0] = DEFINE_RES_MEM(EXYNOS4_PA_SATA, SZ_64K),
-        [1] = DEFINE_RES_IRQ(EXYNOS4_IRQ_SATA),
-};
-static u64 exynos4_ahci_dmamask = DMA_BIT_MASK(32);
-struct platform_device exynos4_device_ahci = {
-        .name           = "ahci",
-        .id             = -1,
-        .resource       = exynos4_ahci_resource,
-        .num_resources  = ARRAY_SIZE(exynos4_ahci_resource),
-        .dev            = {
-                .platform_data          = &exynos4_ahci_pdata,
-                .dma_mask               = &exynos4_ahci_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-};
diff --git a/arch/arm/mach-exynos/dev-audio.c b/arch/arm/mach-exynos/dev-audio.c
deleted file mode 100644
index c662c89794b2..000000000000
--- a/arch/arm/mach-exynos/dev-audio.c
+++ /dev/null
@@ -1,254 +0,0 @@
-/* linux/arch/arm/mach-exynos4/dev-audio.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Copyright (c) 2010 Samsung Electronics Co. Ltd
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/gpio.h>
-#include <linux/platform_data/asoc-s3c.h>
-#include <plat/gpio-cfg.h>
-#include <mach/map.h>
-#include <mach/dma.h>
-#include <mach/irqs.h>
-#define EXYNOS4_AUDSS_INT_MEM   (0x03000000)
-static int exynos4_cfg_i2s(struct platform_device *pdev)
-{
-        /* configure GPIO for i2s port */
-        switch (pdev->id) {
-        case 0:
-                s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 7, S3C_GPIO_SFN(2));
-                break;
-        case 1:
-                s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(2));
-                break;
-        case 2:
-                s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(4));
-                break;
-        default:
-                printk(KERN_ERR "Invalid Device %d\n", pdev->id);
-                return -EINVAL;
-        }
-        return 0;
-}
-static struct s3c_audio_pdata i2sv5_pdata = {
-        .cfg_gpio = exynos4_cfg_i2s,
-        .type = {
-                .i2s = {
-                        .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
-                                         | QUIRK_NEED_RSTCLR,
-                        .idma_addr = EXYNOS4_AUDSS_INT_MEM,
-                },
-        },
-};
-static struct resource exynos4_i2s0_resource[] = {
-        [0] = DEFINE_RES_MEM(EXYNOS4_PA_I2S0, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_I2S0_TX),
-        [2] = DEFINE_RES_DMA(DMACH_I2S0_RX),
-        [3] = DEFINE_RES_DMA(DMACH_I2S0S_TX),
-};
-struct platform_device exynos4_device_i2s0 = {
-        .name = "samsung-i2s",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(exynos4_i2s0_resource),
-        .resource = exynos4_i2s0_resource,
-        .dev = {
-                .platform_data = &i2sv5_pdata,
-        },
-};
-static struct s3c_audio_pdata i2sv3_pdata = {
-        .cfg_gpio = exynos4_cfg_i2s,
-        .type = {
-                .i2s = {
-                        .quirks = QUIRK_NO_MUXPSR,
-                },
-        },
-};
-static struct resource exynos4_i2s1_resource[] = {
-        [0] = DEFINE_RES_MEM(EXYNOS4_PA_I2S1, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_I2S1_TX),
-        [2] = DEFINE_RES_DMA(DMACH_I2S1_RX),
-};
-struct platform_device exynos4_device_i2s1 = {
-        .name = "samsung-i2s",
-        .id = 1,
-        .num_resources = ARRAY_SIZE(exynos4_i2s1_resource),
-        .resource = exynos4_i2s1_resource,
-        .dev = {
-                .platform_data = &i2sv3_pdata,
-        },
-};
-static struct resource exynos4_i2s2_resource[] = {
-        [0] = DEFINE_RES_MEM(EXYNOS4_PA_I2S2, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_I2S2_TX),
-        [2] = DEFINE_RES_DMA(DMACH_I2S2_RX),
-};
-struct platform_device exynos4_device_i2s2 = {
-        .name = "samsung-i2s",
-        .id = 2,
-        .num_resources = ARRAY_SIZE(exynos4_i2s2_resource),
-        .resource = exynos4_i2s2_resource,
-        .dev = {
-                .platform_data = &i2sv3_pdata,
-        },
-};
-/* PCM Controller platform_devices */
-static int exynos4_pcm_cfg_gpio(struct platform_device *pdev)
-{
-        switch (pdev->id) {
-        case 0:
-                s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 5, S3C_GPIO_SFN(3));
-                break;
-        case 1:
-                s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(3));
-                break;
-        case 2:
-                s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(3));
-                break;
-        default:
-                printk(KERN_DEBUG "Invalid PCM Controller number!");
-                return -EINVAL;
-        }
-        return 0;
-}
-static struct s3c_audio_pdata s3c_pcm_pdata = {
-        .cfg_gpio = exynos4_pcm_cfg_gpio,
-};
-static struct resource exynos4_pcm0_resource[] = {
-        [0] = DEFINE_RES_MEM(EXYNOS4_PA_PCM0, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_PCM0_TX),
-        [2] = DEFINE_RES_DMA(DMACH_PCM0_RX),
-};
-struct platform_device exynos4_device_pcm0 = {
-        .name = "samsung-pcm",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(exynos4_pcm0_resource),
-        .resource = exynos4_pcm0_resource,
-        .dev = {
-                .platform_data = &s3c_pcm_pdata,
-        },
-};
-static struct resource exynos4_pcm1_resource[] = {
-        [0] = DEFINE_RES_MEM(EXYNOS4_PA_PCM1, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_PCM1_TX),
-        [2] = DEFINE_RES_DMA(DMACH_PCM1_RX),
-};
-struct platform_device exynos4_device_pcm1 = {
-        .name = "samsung-pcm",
-        .id = 1,
-        .num_resources = ARRAY_SIZE(exynos4_pcm1_resource),
-        .resource = exynos4_pcm1_resource,
-        .dev = {
-                .platform_data = &s3c_pcm_pdata,
-        },
-};
-static struct resource exynos4_pcm2_resource[] = {
-        [0] = DEFINE_RES_MEM(EXYNOS4_PA_PCM2, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_PCM2_TX),
-        [2] = DEFINE_RES_DMA(DMACH_PCM2_RX),
-};
-struct platform_device exynos4_device_pcm2 = {
-        .name = "samsung-pcm",
-        .id = 2,
-        .num_resources = ARRAY_SIZE(exynos4_pcm2_resource),
-        .resource = exynos4_pcm2_resource,
-        .dev = {
-                .platform_data = &s3c_pcm_pdata,
-        },
-};
-/* AC97 Controller platform devices */
-static int exynos4_ac97_cfg_gpio(struct platform_device *pdev)
-{
-        return s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(4));
-}
-static struct resource exynos4_ac97_resource[] = {
-        [0] = DEFINE_RES_MEM(EXYNOS4_PA_AC97, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_AC97_PCMOUT),
-        [2] = DEFINE_RES_DMA(DMACH_AC97_PCMIN),
-        [3] = DEFINE_RES_DMA(DMACH_AC97_MICIN),
-        [4] = DEFINE_RES_IRQ(EXYNOS4_IRQ_AC97),
-};
-static struct s3c_audio_pdata s3c_ac97_pdata = {
-        .cfg_gpio = exynos4_ac97_cfg_gpio,
-};
-static u64 exynos4_ac97_dmamask = DMA_BIT_MASK(32);
-struct platform_device exynos4_device_ac97 = {
-        .name = "samsung-ac97",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(exynos4_ac97_resource),
-        .resource = exynos4_ac97_resource,
-        .dev = {
-                .platform_data = &s3c_ac97_pdata,
-                .dma_mask = &exynos4_ac97_dmamask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-        },
-};
-/* S/PDIF Controller platform_device */
-static int exynos4_spdif_cfg_gpio(struct platform_device *pdev)
-{
-        s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(4));
-        return 0;
-}
-static struct resource exynos4_spdif_resource[] = {
-        [0] = DEFINE_RES_MEM(EXYNOS4_PA_SPDIF, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_SPDIF),
-};
-static struct s3c_audio_pdata samsung_spdif_pdata = {
-        .cfg_gpio = exynos4_spdif_cfg_gpio,
-};
-static u64 exynos4_spdif_dmamask = DMA_BIT_MASK(32);
-struct platform_device exynos4_device_spdif = {
-        .name = "samsung-spdif",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(exynos4_spdif_resource),
-        .resource = exynos4_spdif_resource,
-        .dev = {
-                .platform_data = &samsung_spdif_pdata,
-                .dma_mask = &exynos4_spdif_dmamask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-        },
-};
diff --git a/arch/arm/mach-exynos/dev-ohci.c b/arch/arm/mach-exynos/dev-ohci.c
deleted file mode 100644
index d5bc129e6bb7..000000000000
--- a/arch/arm/mach-exynos/dev-ohci.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/* linux/arch/arm/mach-exynos/dev-ohci.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS - OHCI support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/platform_data/usb-ohci-exynos.h>
-#include <mach/irqs.h>
-#include <mach/map.h>
-#include <plat/devs.h>
-#include <plat/usb-phy.h>
-static struct resource exynos4_ohci_resource[] = {
-        [0] = DEFINE_RES_MEM(EXYNOS4_PA_OHCI, SZ_256),
-        [1] = DEFINE_RES_IRQ(IRQ_USB_HOST),
-};
-static u64 exynos4_ohci_dma_mask = DMA_BIT_MASK(32);
-struct platform_device exynos4_device_ohci = {
-        .name           = "exynos-ohci",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(exynos4_ohci_resource),
-        .resource       = exynos4_ohci_resource,
-        .dev            = {
-                .dma_mask               = &exynos4_ohci_dma_mask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        }
-};
-void __init exynos4_ohci_set_platdata(struct exynos4_ohci_platdata *pd)
-{
-        struct exynos4_ohci_platdata *npd;
-        npd = s3c_set_platdata(pd, sizeof(struct exynos4_ohci_platdata),
-                        &exynos4_device_ohci);
-        if (!npd->phy_init)
-                npd->phy_init = s5p_usb_phy_init;
-        if (!npd->phy_exit)
-                npd->phy_exit = s5p_usb_phy_exit;
-}
diff --git a/arch/arm/mach-exynos/dev-uart.c b/arch/arm/mach-exynos/dev-uart.c
deleted file mode 100644
index c48aff02c786..000000000000
--- a/arch/arm/mach-exynos/dev-uart.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright (c) 2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Base EXYNOS UART resource and device definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/ioport.h>
-#include <linux/platform_device.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/irq.h>
-#include <mach/hardware.h>
-#include <mach/map.h>
-#include <mach/irqs.h>
-#include <plat/devs.h>
-#define EXYNOS_UART_RESOURCE(_series, _nr)      \
-static struct resource exynos##_series##_uart##_nr##_resource[] = {     \
-        [0] = DEFINE_RES_MEM(EXYNOS##_series##_PA_UART##_nr, EXYNOS##_series##_SZ_UART),        \
-        [1] = DEFINE_RES_IRQ(EXYNOS##_series##_IRQ_UART##_nr),  \
-};
-EXYNOS_UART_RESOURCE(4, 0)
-EXYNOS_UART_RESOURCE(4, 1)
-EXYNOS_UART_RESOURCE(4, 2)
-EXYNOS_UART_RESOURCE(4, 3)
-struct s3c24xx_uart_resources exynos4_uart_resources[] __initdata = {
-        [0] = {
-                .resources      = exynos4_uart0_resource,
-                .nr_resources   = ARRAY_SIZE(exynos4_uart0_resource),
-        },
-        [1] = {
-                .resources      = exynos4_uart1_resource,
-                .nr_resources   = ARRAY_SIZE(exynos4_uart1_resource),
-        },
-        [2] = {
-                .resources      = exynos4_uart2_resource,
-                .nr_resources   = ARRAY_SIZE(exynos4_uart2_resource),
-        },
-        [3] = {
-                .resources      = exynos4_uart3_resource,
-                .nr_resources   = ARRAY_SIZE(exynos4_uart3_resource),
-        },
-};
diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c
deleted file mode 100644
index 87e07d6fc615..000000000000
--- a/arch/arm/mach-exynos/dma.c
+++ /dev/null
@@ -1,322 +0,0 @@
-/* linux/arch/arm/mach-exynos4/dma.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Copyright (C) 2010 Samsung Electronics Co. Ltd.
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#include <linux/dma-mapping.h>
-#include <linux/amba/bus.h>
-#include <linux/amba/pl330.h>
-#include <linux/of.h>
-#include <asm/irq.h>
-#include <plat/devs.h>
-#include <plat/irqs.h>
-#include <plat/cpu.h>
-#include <mach/map.h>
-#include <mach/irqs.h>
-#include <mach/dma.h>
-static u8 exynos4210_pdma0_peri[] = {
-        DMACH_PCM0_RX,
-        DMACH_PCM0_TX,
-        DMACH_PCM2_RX,
-        DMACH_PCM2_TX,
-        DMACH_MSM_REQ0,
-        DMACH_MSM_REQ2,
-        DMACH_SPI0_RX,
-        DMACH_SPI0_TX,
-        DMACH_SPI2_RX,
-        DMACH_SPI2_TX,
-        DMACH_I2S0S_TX,
-        DMACH_I2S0_RX,
-        DMACH_I2S0_TX,
-        DMACH_I2S2_RX,
-        DMACH_I2S2_TX,
-        DMACH_UART0_RX,
-        DMACH_UART0_TX,
-        DMACH_UART2_RX,
-        DMACH_UART2_TX,
-        DMACH_UART4_RX,
-        DMACH_UART4_TX,
-        DMACH_SLIMBUS0_RX,
-        DMACH_SLIMBUS0_TX,
-        DMACH_SLIMBUS2_RX,
-        DMACH_SLIMBUS2_TX,
-        DMACH_SLIMBUS4_RX,
-        DMACH_SLIMBUS4_TX,
-        DMACH_AC97_MICIN,
-        DMACH_AC97_PCMIN,
-        DMACH_AC97_PCMOUT,
-};
-static u8 exynos4212_pdma0_peri[] = {
-        DMACH_PCM0_RX,
-        DMACH_PCM0_TX,
-        DMACH_PCM2_RX,
-        DMACH_PCM2_TX,
-        DMACH_MIPI_HSI0,
-        DMACH_MIPI_HSI1,
-        DMACH_SPI0_RX,
-        DMACH_SPI0_TX,
-        DMACH_SPI2_RX,
-        DMACH_SPI2_TX,
-        DMACH_I2S0S_TX,
-        DMACH_I2S0_RX,
-        DMACH_I2S0_TX,
-        DMACH_I2S2_RX,
-        DMACH_I2S2_TX,
-        DMACH_UART0_RX,
-        DMACH_UART0_TX,
-        DMACH_UART2_RX,
-        DMACH_UART2_TX,
-        DMACH_UART4_RX,
-        DMACH_UART4_TX,
-        DMACH_SLIMBUS0_RX,
-        DMACH_SLIMBUS0_TX,
-        DMACH_SLIMBUS2_RX,
-        DMACH_SLIMBUS2_TX,
-        DMACH_SLIMBUS4_RX,
-        DMACH_SLIMBUS4_TX,
-        DMACH_AC97_MICIN,
-        DMACH_AC97_PCMIN,
-        DMACH_AC97_PCMOUT,
-        DMACH_MIPI_HSI4,
-        DMACH_MIPI_HSI5,
-};
-static u8 exynos5250_pdma0_peri[] = {
-        DMACH_PCM0_RX,
-        DMACH_PCM0_TX,
-        DMACH_PCM2_RX,
-        DMACH_PCM2_TX,
-        DMACH_SPI0_RX,
-        DMACH_SPI0_TX,
-        DMACH_SPI2_RX,
-        DMACH_SPI2_TX,
-        DMACH_I2S0S_TX,
-        DMACH_I2S0_RX,
-        DMACH_I2S0_TX,
-        DMACH_I2S2_RX,
-        DMACH_I2S2_TX,
-        DMACH_UART0_RX,
-        DMACH_UART0_TX,
-        DMACH_UART2_RX,
-        DMACH_UART2_TX,
-        DMACH_UART4_RX,
-        DMACH_UART4_TX,
-        DMACH_SLIMBUS0_RX,
-        DMACH_SLIMBUS0_TX,
-        DMACH_SLIMBUS2_RX,
-        DMACH_SLIMBUS2_TX,
-        DMACH_SLIMBUS4_RX,
-        DMACH_SLIMBUS4_TX,
-        DMACH_AC97_MICIN,
-        DMACH_AC97_PCMIN,
-        DMACH_AC97_PCMOUT,
-        DMACH_MIPI_HSI0,
-        DMACH_MIPI_HSI2,
-        DMACH_MIPI_HSI4,
-        DMACH_MIPI_HSI6,
-};
-static struct dma_pl330_platdata exynos_pdma0_pdata;
-static AMBA_AHB_DEVICE(exynos_pdma0, "dma-pl330.0", 0x00041330,
-        EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos_pdma0_pdata);
-static u8 exynos4210_pdma1_peri[] = {
-        DMACH_PCM0_RX,
-        DMACH_PCM0_TX,
-        DMACH_PCM1_RX,
-        DMACH_PCM1_TX,
-        DMACH_MSM_REQ1,
-        DMACH_MSM_REQ3,
-        DMACH_SPI1_RX,
-        DMACH_SPI1_TX,
-        DMACH_I2S0S_TX,
-        DMACH_I2S0_RX,
-        DMACH_I2S0_TX,
-        DMACH_I2S1_RX,
-        DMACH_I2S1_TX,
-        DMACH_UART0_RX,
-        DMACH_UART0_TX,
-        DMACH_UART1_RX,
-        DMACH_UART1_TX,
-        DMACH_UART3_RX,
-        DMACH_UART3_TX,
-        DMACH_SLIMBUS1_RX,
-        DMACH_SLIMBUS1_TX,
-        DMACH_SLIMBUS3_RX,
-        DMACH_SLIMBUS3_TX,
-        DMACH_SLIMBUS5_RX,
-        DMACH_SLIMBUS5_TX,
-};
-static u8 exynos4212_pdma1_peri[] = {
-        DMACH_PCM0_RX,
-        DMACH_PCM0_TX,
-        DMACH_PCM1_RX,
-        DMACH_PCM1_TX,
-        DMACH_MIPI_HSI2,
-        DMACH_MIPI_HSI3,
-        DMACH_SPI1_RX,
-        DMACH_SPI1_TX,
-        DMACH_I2S0S_TX,
-        DMACH_I2S0_RX,
-        DMACH_I2S0_TX,
-        DMACH_I2S1_RX,
-        DMACH_I2S1_TX,
-        DMACH_UART0_RX,
-        DMACH_UART0_TX,
-        DMACH_UART1_RX,
-        DMACH_UART1_TX,
-        DMACH_UART3_RX,
-        DMACH_UART3_TX,
-        DMACH_SLIMBUS1_RX,
-        DMACH_SLIMBUS1_TX,
-        DMACH_SLIMBUS3_RX,
-        DMACH_SLIMBUS3_TX,
-        DMACH_SLIMBUS5_RX,
-        DMACH_SLIMBUS5_TX,
-        DMACH_SLIMBUS0AUX_RX,
-        DMACH_SLIMBUS0AUX_TX,
-        DMACH_SPDIF,
-        DMACH_MIPI_HSI6,
-        DMACH_MIPI_HSI7,
-};
-static u8 exynos5250_pdma1_peri[] = {
-        DMACH_PCM0_RX,
-        DMACH_PCM0_TX,
-        DMACH_PCM1_RX,
-        DMACH_PCM1_TX,
-        DMACH_SPI1_RX,
-        DMACH_SPI1_TX,
-        DMACH_PWM,
-        DMACH_SPDIF,
-        DMACH_I2S0S_TX,
-        DMACH_I2S0_RX,
-        DMACH_I2S0_TX,
-        DMACH_I2S1_RX,
-        DMACH_I2S1_TX,
-        DMACH_UART0_RX,
-        DMACH_UART0_TX,
-        DMACH_UART1_RX,
-        DMACH_UART1_TX,
-        DMACH_UART3_RX,
-        DMACH_UART3_TX,
-        DMACH_SLIMBUS1_RX,
-        DMACH_SLIMBUS1_TX,
-        DMACH_SLIMBUS3_RX,
-        DMACH_SLIMBUS3_TX,
-        DMACH_SLIMBUS5_RX,
-        DMACH_SLIMBUS5_TX,
-        DMACH_SLIMBUS0AUX_RX,
-        DMACH_SLIMBUS0AUX_TX,
-        DMACH_DISP1,
-        DMACH_MIPI_HSI1,
-        DMACH_MIPI_HSI3,
-        DMACH_MIPI_HSI5,
-        DMACH_MIPI_HSI7,
-};
-static struct dma_pl330_platdata exynos_pdma1_pdata;
-static AMBA_AHB_DEVICE(exynos_pdma1,  "dma-pl330.1", 0x00041330,
-        EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos_pdma1_pdata);
-static u8 mdma_peri[] = {
-        DMACH_MTOM_0,
-        DMACH_MTOM_1,
-        DMACH_MTOM_2,
-        DMACH_MTOM_3,
-        DMACH_MTOM_4,
-        DMACH_MTOM_5,
-        DMACH_MTOM_6,
-        DMACH_MTOM_7,
-};
-static struct dma_pl330_platdata exynos_mdma1_pdata = {
-        .nr_valid_peri = ARRAY_SIZE(mdma_peri),
-        .peri_id = mdma_peri,
-};
-static AMBA_AHB_DEVICE(exynos_mdma1,  "dma-pl330.2", 0x00041330,
-        EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos_mdma1_pdata);
-static int __init exynos_dma_init(void)
-{
-        if (of_have_populated_dt())
-                return 0;
-        if (soc_is_exynos4210()) {
-                exynos_pdma0_pdata.nr_valid_peri =
-                        ARRAY_SIZE(exynos4210_pdma0_peri);
-                exynos_pdma0_pdata.peri_id = exynos4210_pdma0_peri;
-                exynos_pdma1_pdata.nr_valid_peri =
-                        ARRAY_SIZE(exynos4210_pdma1_peri);
-                exynos_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
-                if (samsung_rev() == EXYNOS4210_REV_0)
-                        exynos_mdma1_device.res.start = EXYNOS4_PA_S_MDMA1;
-        } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
-                exynos_pdma0_pdata.nr_valid_peri =
-                        ARRAY_SIZE(exynos4212_pdma0_peri);
-                exynos_pdma0_pdata.peri_id = exynos4212_pdma0_peri;
-                exynos_pdma1_pdata.nr_valid_peri =
-                        ARRAY_SIZE(exynos4212_pdma1_peri);
-                exynos_pdma1_pdata.peri_id = exynos4212_pdma1_peri;
-        } else if (soc_is_exynos5250()) {
-                exynos_pdma0_pdata.nr_valid_peri =
-                        ARRAY_SIZE(exynos5250_pdma0_peri);
-                exynos_pdma0_pdata.peri_id = exynos5250_pdma0_peri;
-                exynos_pdma1_pdata.nr_valid_peri =
-                        ARRAY_SIZE(exynos5250_pdma1_peri);
-                exynos_pdma1_pdata.peri_id = exynos5250_pdma1_peri;
-                exynos_pdma0_device.res.start = EXYNOS5_PA_PDMA0;
-                exynos_pdma0_device.res.end = EXYNOS5_PA_PDMA0 + SZ_4K;
-                exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA0;
-                exynos_pdma1_device.res.start = EXYNOS5_PA_PDMA1;
-                exynos_pdma1_device.res.end = EXYNOS5_PA_PDMA1 + SZ_4K;
-                exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA1;
-                exynos_mdma1_device.res.start = EXYNOS5_PA_MDMA1;
-                exynos_mdma1_device.res.end = EXYNOS5_PA_MDMA1 + SZ_4K;
-                exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_MDMA1;
-        }
-        dma_cap_set(DMA_SLAVE, exynos_pdma0_pdata.cap_mask);
-        dma_cap_set(DMA_CYCLIC, exynos_pdma0_pdata.cap_mask);
-        dma_cap_set(DMA_PRIVATE, exynos_pdma0_pdata.cap_mask);
-        amba_device_register(&exynos_pdma0_device, &iomem_resource);
-        dma_cap_set(DMA_SLAVE, exynos_pdma1_pdata.cap_mask);
-        dma_cap_set(DMA_CYCLIC, exynos_pdma1_pdata.cap_mask);
-        dma_cap_set(DMA_PRIVATE, exynos_pdma1_pdata.cap_mask);
-        amba_device_register(&exynos_pdma1_device, &iomem_resource);
-        dma_cap_set(DMA_MEMCPY, exynos_mdma1_pdata.cap_mask);
-        amba_device_register(&exynos_mdma1_device, &iomem_resource);
-        return 0;
-}
-arch_initcall(exynos_dma_init);
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index ed11f100d479..932129ef26c6 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -48,20 +48,18 @@ static const struct firmware_ops exynos_firmware_ops = {
 void __init exynos_firmware_init(void)
 {
-        if (of_have_populated_dt()) {
+        struct device_node *nd;
-                struct device_node *nd;
+        const __be32 *addr;
-                const __be32 *addr;
-                nd = of_find_compatible_node(NULL, NULL,
+        nd = of_find_compatible_node(NULL, NULL,
-                                                "samsung,secure-firmware");
+                                        "samsung,secure-firmware");
-                if (!nd)
+        if (!nd)
-                        return;
+                return;
-                addr = of_get_address(nd, 0, NULL, NULL);
+        addr = of_get_address(nd, 0, NULL, NULL);
-                if (!addr) {
+        if (!addr) {
-                        pr_err("%s: No address specified.\n", __func__);
+                pr_err("%s: No address specified.\n", __func__);
-                        return;
+                return;
-                }
        }
        pr_info("Running under secure firmware.\n");
diff --git a/arch/arm/mach-exynos/headsmp.S b/arch/arm/mach-exynos/headsmp.S
index 5364d4bfa8bc..cdd9d91e9933 100644
--- a/arch/arm/mach-exynos/headsmp.S
+++ b/arch/arm/mach-exynos/headsmp.S
@@ -13,8 +13,6 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
-        __CPUINIT
 /*
 * exynos4 specific entry point for secondary CPUs.  This provides
 * a "holding pen" into which all secondary cores are held until we're
diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
deleted file mode 100644
index eb24f1eb8e3b..000000000000
--- a/arch/arm/mach-exynos/include/mach/gpio.h
+++ /dev/null
@@ -1,289 +0,0 @@
-/*
- * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS - GPIO lib support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H __FILE__
-/* Macro for EXYNOS GPIO numbering */
-#define EXYNOS_GPIO_NEXT(__gpio) \
-        ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
-/* EXYNOS4 GPIO bank sizes */
-#define EXYNOS4_GPIO_A0_NR      (8)
-#define EXYNOS4_GPIO_A1_NR      (6)
-#define EXYNOS4_GPIO_B_NR       (8)
-#define EXYNOS4_GPIO_C0_NR      (5)
-#define EXYNOS4_GPIO_C1_NR      (5)
-#define EXYNOS4_GPIO_D0_NR      (4)
-#define EXYNOS4_GPIO_D1_NR      (4)
-#define EXYNOS4_GPIO_E0_NR      (5)
-#define EXYNOS4_GPIO_E1_NR      (8)
-#define EXYNOS4_GPIO_E2_NR      (6)
-#define EXYNOS4_GPIO_E3_NR      (8)
-#define EXYNOS4_GPIO_E4_NR      (8)
-#define EXYNOS4_GPIO_F0_NR      (8)
-#define EXYNOS4_GPIO_F1_NR      (8)
-#define EXYNOS4_GPIO_F2_NR      (8)
-#define EXYNOS4_GPIO_F3_NR      (6)
-#define EXYNOS4_GPIO_J0_NR      (8)
-#define EXYNOS4_GPIO_J1_NR      (5)
-#define EXYNOS4_GPIO_K0_NR      (7)
-#define EXYNOS4_GPIO_K1_NR      (7)
-#define EXYNOS4_GPIO_K2_NR      (7)
-#define EXYNOS4_GPIO_K3_NR      (7)
-#define EXYNOS4_GPIO_L0_NR      (8)
-#define EXYNOS4_GPIO_L1_NR      (3)
-#define EXYNOS4_GPIO_L2_NR      (8)
-#define EXYNOS4_GPIO_X0_NR      (8)
-#define EXYNOS4_GPIO_X1_NR      (8)
-#define EXYNOS4_GPIO_X2_NR      (8)
-#define EXYNOS4_GPIO_X3_NR      (8)
-#define EXYNOS4_GPIO_Y0_NR      (6)
-#define EXYNOS4_GPIO_Y1_NR      (4)
-#define EXYNOS4_GPIO_Y2_NR      (6)
-#define EXYNOS4_GPIO_Y3_NR      (8)
-#define EXYNOS4_GPIO_Y4_NR      (8)
-#define EXYNOS4_GPIO_Y5_NR      (8)
-#define EXYNOS4_GPIO_Y6_NR      (8)
-#define EXYNOS4_GPIO_Z_NR       (7)
-/* EXYNOS4 GPIO bank numbers */
-enum exynos4_gpio_number {
-        EXYNOS4_GPIO_A0_START   = 0,
-        EXYNOS4_GPIO_A1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_A0),
-        EXYNOS4_GPIO_B_START    = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_A1),
-        EXYNOS4_GPIO_C0_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_B),
-        EXYNOS4_GPIO_C1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C0),
-        EXYNOS4_GPIO_D0_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C1),
-        EXYNOS4_GPIO_D1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D0),
-        EXYNOS4_GPIO_E0_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D1),
-        EXYNOS4_GPIO_E1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E0),
-        EXYNOS4_GPIO_E2_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E1),
-        EXYNOS4_GPIO_E3_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E2),
-        EXYNOS4_GPIO_E4_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E3),
-        EXYNOS4_GPIO_F0_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E4),
-        EXYNOS4_GPIO_F1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F0),
-        EXYNOS4_GPIO_F2_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F1),
-        EXYNOS4_GPIO_F3_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F2),
-        EXYNOS4_GPIO_J0_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F3),
-        EXYNOS4_GPIO_J1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_J0),
-        EXYNOS4_GPIO_K0_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_J1),
-        EXYNOS4_GPIO_K1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K0),
-        EXYNOS4_GPIO_K2_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K1),
-        EXYNOS4_GPIO_K3_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K2),
-        EXYNOS4_GPIO_L0_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K3),
-        EXYNOS4_GPIO_L1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L0),
-        EXYNOS4_GPIO_L2_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L1),
-        EXYNOS4_GPIO_X0_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L2),
-        EXYNOS4_GPIO_X1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X0),
-        EXYNOS4_GPIO_X2_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X1),
-        EXYNOS4_GPIO_X3_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X2),
-        EXYNOS4_GPIO_Y0_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X3),
-        EXYNOS4_GPIO_Y1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y0),
-        EXYNOS4_GPIO_Y2_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y1),
-        EXYNOS4_GPIO_Y3_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y2),
-        EXYNOS4_GPIO_Y4_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y3),
-        EXYNOS4_GPIO_Y5_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y4),
-        EXYNOS4_GPIO_Y6_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y5),
-        EXYNOS4_GPIO_Z_START    = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y6),
-};
-/* EXYNOS4 GPIO number definitions */
-#define EXYNOS4_GPA0(_nr)       (EXYNOS4_GPIO_A0_START + (_nr))
-#define EXYNOS4_GPA1(_nr)       (EXYNOS4_GPIO_A1_START + (_nr))
-#define EXYNOS4_GPB(_nr)        (EXYNOS4_GPIO_B_START + (_nr))
-#define EXYNOS4_GPC0(_nr)       (EXYNOS4_GPIO_C0_START + (_nr))
-#define EXYNOS4_GPC1(_nr)       (EXYNOS4_GPIO_C1_START + (_nr))
-#define EXYNOS4_GPD0(_nr)       (EXYNOS4_GPIO_D0_START + (_nr))
-#define EXYNOS4_GPD1(_nr)       (EXYNOS4_GPIO_D1_START + (_nr))
-#define EXYNOS4_GPE0(_nr)       (EXYNOS4_GPIO_E0_START + (_nr))
-#define EXYNOS4_GPE1(_nr)       (EXYNOS4_GPIO_E1_START + (_nr))
-#define EXYNOS4_GPE2(_nr)       (EXYNOS4_GPIO_E2_START + (_nr))
-#define EXYNOS4_GPE3(_nr)       (EXYNOS4_GPIO_E3_START + (_nr))
-#define EXYNOS4_GPE4(_nr)       (EXYNOS4_GPIO_E4_START + (_nr))
-#define EXYNOS4_GPF0(_nr)       (EXYNOS4_GPIO_F0_START + (_nr))
-#define EXYNOS4_GPF1(_nr)       (EXYNOS4_GPIO_F1_START + (_nr))
-#define EXYNOS4_GPF2(_nr)       (EXYNOS4_GPIO_F2_START + (_nr))
-#define EXYNOS4_GPF3(_nr)       (EXYNOS4_GPIO_F3_START + (_nr))
-#define EXYNOS4_GPJ0(_nr)       (EXYNOS4_GPIO_J0_START + (_nr))
-#define EXYNOS4_GPJ1(_nr)       (EXYNOS4_GPIO_J1_START + (_nr))
-#define EXYNOS4_GPK0(_nr)       (EXYNOS4_GPIO_K0_START + (_nr))
-#define EXYNOS4_GPK1(_nr)       (EXYNOS4_GPIO_K1_START + (_nr))
-#define EXYNOS4_GPK2(_nr)       (EXYNOS4_GPIO_K2_START + (_nr))
-#define EXYNOS4_GPK3(_nr)       (EXYNOS4_GPIO_K3_START + (_nr))
-#define EXYNOS4_GPL0(_nr)       (EXYNOS4_GPIO_L0_START + (_nr))
-#define EXYNOS4_GPL1(_nr)       (EXYNOS4_GPIO_L1_START + (_nr))
-#define EXYNOS4_GPL2(_nr)       (EXYNOS4_GPIO_L2_START + (_nr))
-#define EXYNOS4_GPX0(_nr)       (EXYNOS4_GPIO_X0_START + (_nr))
-#define EXYNOS4_GPX1(_nr)       (EXYNOS4_GPIO_X1_START + (_nr))
-#define EXYNOS4_GPX2(_nr)       (EXYNOS4_GPIO_X2_START + (_nr))
-#define EXYNOS4_GPX3(_nr)       (EXYNOS4_GPIO_X3_START + (_nr))
-#define EXYNOS4_GPY0(_nr)       (EXYNOS4_GPIO_Y0_START + (_nr))
-#define EXYNOS4_GPY1(_nr)       (EXYNOS4_GPIO_Y1_START + (_nr))
-#define EXYNOS4_GPY2(_nr)       (EXYNOS4_GPIO_Y2_START + (_nr))
-#define EXYNOS4_GPY3(_nr)       (EXYNOS4_GPIO_Y3_START + (_nr))
-#define EXYNOS4_GPY4(_nr)       (EXYNOS4_GPIO_Y4_START + (_nr))
-#define EXYNOS4_GPY5(_nr)       (EXYNOS4_GPIO_Y5_START + (_nr))
-#define EXYNOS4_GPY6(_nr)       (EXYNOS4_GPIO_Y6_START + (_nr))
-#define EXYNOS4_GPZ(_nr)        (EXYNOS4_GPIO_Z_START + (_nr))
-/* the end of the EXYNOS4 specific gpios */
-#define EXYNOS4_GPIO_END        (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + 1)
-/* EXYNOS5 GPIO bank sizes */
-#define EXYNOS5_GPIO_A0_NR      (8)
-#define EXYNOS5_GPIO_A1_NR      (6)
-#define EXYNOS5_GPIO_A2_NR      (8)
-#define EXYNOS5_GPIO_B0_NR      (5)
-#define EXYNOS5_GPIO_B1_NR      (5)
-#define EXYNOS5_GPIO_B2_NR      (4)
-#define EXYNOS5_GPIO_B3_NR      (4)
-#define EXYNOS5_GPIO_C0_NR      (7)
-#define EXYNOS5_GPIO_C1_NR      (4)
-#define EXYNOS5_GPIO_C2_NR      (7)
-#define EXYNOS5_GPIO_C3_NR      (7)
-#define EXYNOS5_GPIO_C4_NR      (7)
-#define EXYNOS5_GPIO_D0_NR      (4)
-#define EXYNOS5_GPIO_D1_NR      (8)
-#define EXYNOS5_GPIO_Y0_NR      (6)
-#define EXYNOS5_GPIO_Y1_NR      (4)
-#define EXYNOS5_GPIO_Y2_NR      (6)
-#define EXYNOS5_GPIO_Y3_NR      (8)
-#define EXYNOS5_GPIO_Y4_NR      (8)
-#define EXYNOS5_GPIO_Y5_NR      (8)
-#define EXYNOS5_GPIO_Y6_NR      (8)
-#define EXYNOS5_GPIO_X0_NR      (8)
-#define EXYNOS5_GPIO_X1_NR      (8)
-#define EXYNOS5_GPIO_X2_NR      (8)
-#define EXYNOS5_GPIO_X3_NR      (8)
-#define EXYNOS5_GPIO_E0_NR      (8)
-#define EXYNOS5_GPIO_E1_NR      (2)
-#define EXYNOS5_GPIO_F0_NR      (4)
-#define EXYNOS5_GPIO_F1_NR      (4)
-#define EXYNOS5_GPIO_G0_NR      (8)
-#define EXYNOS5_GPIO_G1_NR      (8)
-#define EXYNOS5_GPIO_G2_NR      (2)
-#define EXYNOS5_GPIO_H0_NR      (4)
-#define EXYNOS5_GPIO_H1_NR      (8)
-#define EXYNOS5_GPIO_V0_NR      (8)
-#define EXYNOS5_GPIO_V1_NR      (8)
-#define EXYNOS5_GPIO_V2_NR      (8)
-#define EXYNOS5_GPIO_V3_NR      (8)
-#define EXYNOS5_GPIO_V4_NR      (2)
-#define EXYNOS5_GPIO_Z_NR       (7)
-/* EXYNOS5 GPIO bank numbers */
-enum exynos5_gpio_number {
-        EXYNOS5_GPIO_A0_START           = 0,
-        EXYNOS5_GPIO_A1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A0),
-        EXYNOS5_GPIO_A2_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A1),
-        EXYNOS5_GPIO_B0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A2),
-        EXYNOS5_GPIO_B1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B0),
-        EXYNOS5_GPIO_B2_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B1),
-        EXYNOS5_GPIO_B3_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B2),
-        EXYNOS5_GPIO_C0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B3),
-        EXYNOS5_GPIO_C1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C0),
-        EXYNOS5_GPIO_C2_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C1),
-        EXYNOS5_GPIO_C3_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C2),
-        EXYNOS5_GPIO_C4_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
-        EXYNOS5_GPIO_D0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C4),
-        EXYNOS5_GPIO_D1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D0),
-        EXYNOS5_GPIO_Y0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D1),
-        EXYNOS5_GPIO_Y1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y0),
-        EXYNOS5_GPIO_Y2_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y1),
-        EXYNOS5_GPIO_Y3_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y2),
-        EXYNOS5_GPIO_Y4_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y3),
-        EXYNOS5_GPIO_Y5_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y4),
-        EXYNOS5_GPIO_Y6_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y5),
-        EXYNOS5_GPIO_X0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y6),
-        EXYNOS5_GPIO_X1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X0),
-        EXYNOS5_GPIO_X2_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X1),
-        EXYNOS5_GPIO_X3_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X2),
-        EXYNOS5_GPIO_E0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X3),
-        EXYNOS5_GPIO_E1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_E0),
-        EXYNOS5_GPIO_F0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_E1),
-        EXYNOS5_GPIO_F1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_F0),
-        EXYNOS5_GPIO_G0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_F1),
-        EXYNOS5_GPIO_G1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G0),
-        EXYNOS5_GPIO_G2_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G1),
-        EXYNOS5_GPIO_H0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G2),
-        EXYNOS5_GPIO_H1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_H0),
-        EXYNOS5_GPIO_V0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_H1),
-        EXYNOS5_GPIO_V1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V0),
-        EXYNOS5_GPIO_V2_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V1),
-        EXYNOS5_GPIO_V3_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V2),
-        EXYNOS5_GPIO_V4_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V3),
-        EXYNOS5_GPIO_Z_START            = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V4),
-};
-/* EXYNOS5 GPIO number definitions */
-#define EXYNOS5_GPA0(_nr)       (EXYNOS5_GPIO_A0_START + (_nr))
-#define EXYNOS5_GPA1(_nr)       (EXYNOS5_GPIO_A1_START + (_nr))
-#define EXYNOS5_GPA2(_nr)       (EXYNOS5_GPIO_A2_START + (_nr))
-#define EXYNOS5_GPB0(_nr)       (EXYNOS5_GPIO_B0_START + (_nr))
-#define EXYNOS5_GPB1(_nr)       (EXYNOS5_GPIO_B1_START + (_nr))
-#define EXYNOS5_GPB2(_nr)       (EXYNOS5_GPIO_B2_START + (_nr))
-#define EXYNOS5_GPB3(_nr)       (EXYNOS5_GPIO_B3_START + (_nr))
-#define EXYNOS5_GPC0(_nr)       (EXYNOS5_GPIO_C0_START + (_nr))
-#define EXYNOS5_GPC1(_nr)       (EXYNOS5_GPIO_C1_START + (_nr))
-#define EXYNOS5_GPC2(_nr)       (EXYNOS5_GPIO_C2_START + (_nr))
-#define EXYNOS5_GPC3(_nr)       (EXYNOS5_GPIO_C3_START + (_nr))
-#define EXYNOS5_GPC4(_nr)       (EXYNOS5_GPIO_C4_START + (_nr))
-#define EXYNOS5_GPD0(_nr)       (EXYNOS5_GPIO_D0_START + (_nr))
-#define EXYNOS5_GPD1(_nr)       (EXYNOS5_GPIO_D1_START + (_nr))
-#define EXYNOS5_GPY0(_nr)       (EXYNOS5_GPIO_Y0_START + (_nr))
-#define EXYNOS5_GPY1(_nr)       (EXYNOS5_GPIO_Y1_START + (_nr))
-#define EXYNOS5_GPY2(_nr)       (EXYNOS5_GPIO_Y2_START + (_nr))
-#define EXYNOS5_GPY3(_nr)       (EXYNOS5_GPIO_Y3_START + (_nr))
-#define EXYNOS5_GPY4(_nr)       (EXYNOS5_GPIO_Y4_START + (_nr))
-#define EXYNOS5_GPY5(_nr)       (EXYNOS5_GPIO_Y5_START + (_nr))
-#define EXYNOS5_GPY6(_nr)       (EXYNOS5_GPIO_Y6_START + (_nr))
-#define EXYNOS5_GPX0(_nr)       (EXYNOS5_GPIO_X0_START + (_nr))
-#define EXYNOS5_GPX1(_nr)       (EXYNOS5_GPIO_X1_START + (_nr))
-#define EXYNOS5_GPX2(_nr)       (EXYNOS5_GPIO_X2_START + (_nr))
-#define EXYNOS5_GPX3(_nr)       (EXYNOS5_GPIO_X3_START + (_nr))
-#define EXYNOS5_GPE0(_nr)       (EXYNOS5_GPIO_E0_START + (_nr))
-#define EXYNOS5_GPE1(_nr)       (EXYNOS5_GPIO_E1_START + (_nr))
-#define EXYNOS5_GPF0(_nr)       (EXYNOS5_GPIO_F0_START + (_nr))
-#define EXYNOS5_GPF1(_nr)       (EXYNOS5_GPIO_F1_START + (_nr))
-#define EXYNOS5_GPG0(_nr)       (EXYNOS5_GPIO_G0_START + (_nr))
-#define EXYNOS5_GPG1(_nr)       (EXYNOS5_GPIO_G1_START + (_nr))
-#define EXYNOS5_GPG2(_nr)       (EXYNOS5_GPIO_G2_START + (_nr))
-#define EXYNOS5_GPH0(_nr)       (EXYNOS5_GPIO_H0_START + (_nr))
-#define EXYNOS5_GPH1(_nr)       (EXYNOS5_GPIO_H1_START + (_nr))
-#define EXYNOS5_GPV0(_nr)       (EXYNOS5_GPIO_V0_START + (_nr))
-#define EXYNOS5_GPV1(_nr)       (EXYNOS5_GPIO_V1_START + (_nr))
-#define EXYNOS5_GPV2(_nr)       (EXYNOS5_GPIO_V2_START + (_nr))
-#define EXYNOS5_GPV3(_nr)       (EXYNOS5_GPIO_V3_START + (_nr))
-#define EXYNOS5_GPV4(_nr)       (EXYNOS5_GPIO_V4_START + (_nr))
-#define EXYNOS5_GPZ(_nr)        (EXYNOS5_GPIO_Z_START + (_nr))
-/* the end of the EXYNOS5 specific gpios */
-#define EXYNOS5_GPIO_END        (EXYNOS5_GPZ(EXYNOS5_GPIO_Z_NR) + 1)
-/* actually, EXYNOS5_GPIO_END is bigger than EXYNOS4 */
-#define S3C_GPIO_END            (EXYNOS5_GPIO_END)
-/* define the number of gpios */
-#define ARCH_NR_GPIOS           (CONFIG_SAMSUNG_GPIO_EXTRA + S3C_GPIO_END)
-#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
deleted file mode 100644
index c72f59d91fce..000000000000
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ /dev/null
@@ -1,476 +0,0 @@
-/*
- * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS - IRQ definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H __FILE__
-#include <plat/irqs.h>
-/* PPI: Private Peripheral Interrupt */
-#define IRQ_PPI(x)                      (x + 16)
-/* SPI: Shared Peripheral Interrupt */
-#define IRQ_SPI(x)                      (x + 32)
-/* COMBINER */
-#define MAX_IRQ_IN_COMBINER             8
-#define COMBINER_GROUP(x)               ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
-#define COMBINER_IRQ(x, y)              (COMBINER_GROUP(x) + y)
-/* For EXYNOS4 and EXYNOS5 */
-#define EXYNOS_IRQ_EINT16_31            IRQ_SPI(32)
-/* For EXYNOS4 SoCs */
-#define EXYNOS4_IRQ_EINT0               IRQ_SPI(16)
-#define EXYNOS4_IRQ_EINT1               IRQ_SPI(17)
-#define EXYNOS4_IRQ_EINT2               IRQ_SPI(18)
-#define EXYNOS4_IRQ_EINT3               IRQ_SPI(19)
-#define EXYNOS4_IRQ_EINT4               IRQ_SPI(20)
-#define EXYNOS4_IRQ_EINT5               IRQ_SPI(21)
-#define EXYNOS4_IRQ_EINT6               IRQ_SPI(22)
-#define EXYNOS4_IRQ_EINT7               IRQ_SPI(23)
-#define EXYNOS4_IRQ_EINT8               IRQ_SPI(24)
-#define EXYNOS4_IRQ_EINT9               IRQ_SPI(25)
-#define EXYNOS4_IRQ_EINT10              IRQ_SPI(26)
-#define EXYNOS4_IRQ_EINT11              IRQ_SPI(27)
-#define EXYNOS4_IRQ_EINT12              IRQ_SPI(28)
-#define EXYNOS4_IRQ_EINT13              IRQ_SPI(29)
-#define EXYNOS4_IRQ_EINT14              IRQ_SPI(30)
-#define EXYNOS4_IRQ_EINT15              IRQ_SPI(31)
-#define EXYNOS4_IRQ_MDMA0               IRQ_SPI(33)
-#define EXYNOS4_IRQ_MDMA1               IRQ_SPI(34)
-#define EXYNOS4_IRQ_PDMA0               IRQ_SPI(35)
-#define EXYNOS4_IRQ_PDMA1               IRQ_SPI(36)
-#define EXYNOS4_IRQ_TIMER0_VIC          IRQ_SPI(37)
-#define EXYNOS4_IRQ_TIMER1_VIC          IRQ_SPI(38)
-#define EXYNOS4_IRQ_TIMER2_VIC          IRQ_SPI(39)
-#define EXYNOS4_IRQ_TIMER3_VIC          IRQ_SPI(40)
-#define EXYNOS4_IRQ_TIMER4_VIC          IRQ_SPI(41)
-#define EXYNOS4_IRQ_MCT_L0              IRQ_SPI(42)
-#define EXYNOS4_IRQ_WDT                 IRQ_SPI(43)
-#define EXYNOS4_IRQ_RTC_ALARM           IRQ_SPI(44)
-#define EXYNOS4_IRQ_RTC_TIC             IRQ_SPI(45)
-#define EXYNOS4_IRQ_GPIO_XB             IRQ_SPI(46)
-#define EXYNOS4_IRQ_GPIO_XA             IRQ_SPI(47)
-#define EXYNOS4_IRQ_MCT_L1              IRQ_SPI(48)
-#define EXYNOS4_IRQ_UART0               IRQ_SPI(52)
-#define EXYNOS4_IRQ_UART1               IRQ_SPI(53)
-#define EXYNOS4_IRQ_UART2               IRQ_SPI(54)
-#define EXYNOS4_IRQ_UART3               IRQ_SPI(55)
-#define EXYNOS4_IRQ_UART4               IRQ_SPI(56)
-#define EXYNOS4_IRQ_MCT_G0              IRQ_SPI(57)
-#define EXYNOS4_IRQ_IIC                 IRQ_SPI(58)
-#define EXYNOS4_IRQ_IIC1                IRQ_SPI(59)
-#define EXYNOS4_IRQ_IIC2                IRQ_SPI(60)
-#define EXYNOS4_IRQ_IIC3                IRQ_SPI(61)
-#define EXYNOS4_IRQ_IIC4                IRQ_SPI(62)
-#define EXYNOS4_IRQ_IIC5                IRQ_SPI(63)
-#define EXYNOS4_IRQ_IIC6                IRQ_SPI(64)
-#define EXYNOS4_IRQ_IIC7                IRQ_SPI(65)
-#define EXYNOS4_IRQ_SPI0                IRQ_SPI(66)
-#define EXYNOS4_IRQ_SPI1                IRQ_SPI(67)
-#define EXYNOS4_IRQ_SPI2                IRQ_SPI(68)
-#define EXYNOS4_IRQ_USB_HOST            IRQ_SPI(70)
-#define EXYNOS4_IRQ_USB_HSOTG           IRQ_SPI(71)
-#define EXYNOS4_IRQ_MODEM_IF            IRQ_SPI(72)
-#define EXYNOS4_IRQ_HSMMC0              IRQ_SPI(73)
-#define EXYNOS4_IRQ_HSMMC1              IRQ_SPI(74)
-#define EXYNOS4_IRQ_HSMMC2              IRQ_SPI(75)
-#define EXYNOS4_IRQ_HSMMC3              IRQ_SPI(76)
-#define EXYNOS4_IRQ_DWMCI               IRQ_SPI(77)
-#define EXYNOS4_IRQ_MIPI_CSIS0          IRQ_SPI(78)
-#define EXYNOS4_IRQ_MIPI_CSIS1          IRQ_SPI(80)
-#define EXYNOS4_IRQ_ONENAND_AUDI        IRQ_SPI(82)
-#define EXYNOS4_IRQ_ROTATOR             IRQ_SPI(83)
-#define EXYNOS4_IRQ_FIMC0               IRQ_SPI(84)
-#define EXYNOS4_IRQ_FIMC1               IRQ_SPI(85)
-#define EXYNOS4_IRQ_FIMC2               IRQ_SPI(86)
-#define EXYNOS4_IRQ_FIMC3               IRQ_SPI(87)
-#define EXYNOS4_IRQ_JPEG                IRQ_SPI(88)
-#define EXYNOS4_IRQ_2D                  IRQ_SPI(89)
-#define EXYNOS4_IRQ_PCIE                IRQ_SPI(90)
-#define EXYNOS4_IRQ_MIXER               IRQ_SPI(91)
-#define EXYNOS4_IRQ_HDMI                IRQ_SPI(92)
-#define EXYNOS4_IRQ_IIC_HDMIPHY         IRQ_SPI(93)
-#define EXYNOS4_IRQ_MFC                 IRQ_SPI(94)
-#define EXYNOS4_IRQ_SDO                 IRQ_SPI(95)
-#define EXYNOS4_IRQ_AUDIO_SS            IRQ_SPI(96)
-#define EXYNOS4_IRQ_I2S0                IRQ_SPI(97)
-#define EXYNOS4_IRQ_I2S1                IRQ_SPI(98)
-#define EXYNOS4_IRQ_I2S2                IRQ_SPI(99)
-#define EXYNOS4_IRQ_AC97                IRQ_SPI(100)
-#define EXYNOS4_IRQ_SPDIF               IRQ_SPI(104)
-#define EXYNOS4_IRQ_ADC0                IRQ_SPI(105)
-#define EXYNOS4_IRQ_PEN0                IRQ_SPI(106)
-#define EXYNOS4_IRQ_ADC1                IRQ_SPI(107)
-#define EXYNOS4_IRQ_PEN1                IRQ_SPI(108)
-#define EXYNOS4_IRQ_KEYPAD              IRQ_SPI(109)
-#define EXYNOS4_IRQ_POWER_PMU           IRQ_SPI(110)
-#define EXYNOS4_IRQ_GPS                 IRQ_SPI(111)
-#define EXYNOS4_IRQ_INTFEEDCTRL_SSS     IRQ_SPI(112)
-#define EXYNOS4_IRQ_SLIMBUS             IRQ_SPI(113)
-#define EXYNOS4_IRQ_TSI                 IRQ_SPI(115)
-#define EXYNOS4_IRQ_SATA                IRQ_SPI(116)
-#define EXYNOS4_IRQ_PMU                 COMBINER_IRQ(2, 2)
-#define EXYNOS4_IRQ_PMU_CPU1            COMBINER_IRQ(3, 2)
-#define EXYNOS4_IRQ_PMU_CPU2            COMBINER_IRQ(18, 2)
-#define EXYNOS4_IRQ_PMU_CPU3            COMBINER_IRQ(19, 2)
-#define EXYNOS4_IRQ_TMU_TRIG0           COMBINER_IRQ(2, 4)
-#define EXYNOS4_IRQ_TMU_TRIG1           COMBINER_IRQ(3, 4)
-#define EXYNOS4_IRQ_SYSMMU_MDMA0_0      COMBINER_IRQ(4, 0)
-#define EXYNOS4_IRQ_SYSMMU_SSS_0        COMBINER_IRQ(4, 1)
-#define EXYNOS4_IRQ_SYSMMU_FIMC0_0      COMBINER_IRQ(4, 2)
-#define EXYNOS4_IRQ_SYSMMU_FIMC1_0      COMBINER_IRQ(4, 3)
-#define EXYNOS4_IRQ_SYSMMU_FIMC2_0      COMBINER_IRQ(4, 4)
-#define EXYNOS4_IRQ_SYSMMU_FIMC3_0      COMBINER_IRQ(4, 5)
-#define EXYNOS4_IRQ_SYSMMU_JPEG_0       COMBINER_IRQ(4, 6)
-#define EXYNOS4_IRQ_SYSMMU_2D_0         COMBINER_IRQ(4, 7)
-#define EXYNOS4_IRQ_SYSMMU_ROTATOR_0    COMBINER_IRQ(5, 0)
-#define EXYNOS4_IRQ_SYSMMU_MDMA1_0      COMBINER_IRQ(5, 1)
-#define EXYNOS4_IRQ_SYSMMU_LCD0_M0_0    COMBINER_IRQ(5, 2)
-#define EXYNOS4_IRQ_SYSMMU_LCD1_M1_0    COMBINER_IRQ(5, 3)
-#define EXYNOS4_IRQ_SYSMMU_TV_M0_0      COMBINER_IRQ(5, 4)
-#define EXYNOS4_IRQ_SYSMMU_MFC_M0_0     COMBINER_IRQ(5, 5)
-#define EXYNOS4_IRQ_SYSMMU_MFC_M1_0     COMBINER_IRQ(5, 6)
-#define EXYNOS4_IRQ_SYSMMU_PCIE_0       COMBINER_IRQ(5, 7)
-#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE0_0 COMBINER_IRQ(16, 0)
-#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE1_0 COMBINER_IRQ(16, 1)
-#define EXYNOS4_IRQ_SYSMMU_FIMC_ISP_0   COMBINER_IRQ(16, 2)
-#define EXYNOS4_IRQ_SYSMMU_FIMC_DRC_0   COMBINER_IRQ(16, 3)
-#define EXYNOS4_IRQ_SYSMMU_FIMC_FD_0    COMBINER_IRQ(16, 4)
-#define EXYNOS4_IRQ_SYSMMU_FIMC_CX_0    COMBINER_IRQ(16, 5)
-#define EXYNOS4_IRQ_FIMD0_FIFO          COMBINER_IRQ(11, 0)
-#define EXYNOS4_IRQ_FIMD0_VSYNC         COMBINER_IRQ(11, 1)
-#define EXYNOS4_IRQ_FIMD0_SYSTEM        COMBINER_IRQ(11, 2)
-#define EXYNOS4210_MAX_COMBINER_NR      16
-#define EXYNOS4212_MAX_COMBINER_NR      18
-#define EXYNOS4412_MAX_COMBINER_NR      20
-#define EXYNOS4_MAX_COMBINER_NR         EXYNOS4412_MAX_COMBINER_NR
-#define EXYNOS4_IRQ_GPIO1_NR_GROUPS     16
-#define EXYNOS4_IRQ_GPIO2_NR_GROUPS     9
-/*
- * For Compatibility:
- * the default is for EXYNOS4, and
- * for exynos5, should be re-mapped at function
- */
-#define IRQ_TIMER0_VIC                  EXYNOS4_IRQ_TIMER0_VIC
-#define IRQ_TIMER1_VIC                  EXYNOS4_IRQ_TIMER1_VIC
-#define IRQ_TIMER2_VIC                  EXYNOS4_IRQ_TIMER2_VIC
-#define IRQ_TIMER3_VIC                  EXYNOS4_IRQ_TIMER3_VIC
-#define IRQ_TIMER4_VIC                  EXYNOS4_IRQ_TIMER4_VIC
-#define IRQ_WDT                         EXYNOS4_IRQ_WDT
-#define IRQ_RTC_ALARM                   EXYNOS4_IRQ_RTC_ALARM
-#define IRQ_RTC_TIC                     EXYNOS4_IRQ_RTC_TIC
-#define IRQ_GPIO_XB                     EXYNOS4_IRQ_GPIO_XB
-#define IRQ_GPIO_XA                     EXYNOS4_IRQ_GPIO_XA
-#define IRQ_IIC                         EXYNOS4_IRQ_IIC
-#define IRQ_IIC1                        EXYNOS4_IRQ_IIC1
-#define IRQ_IIC3                        EXYNOS4_IRQ_IIC3
-#define IRQ_IIC5                        EXYNOS4_IRQ_IIC5
-#define IRQ_IIC6                        EXYNOS4_IRQ_IIC6
-#define IRQ_IIC7                        EXYNOS4_IRQ_IIC7
-#define IRQ_SPI0                        EXYNOS4_IRQ_SPI0
-#define IRQ_SPI1                        EXYNOS4_IRQ_SPI1
-#define IRQ_SPI2                        EXYNOS4_IRQ_SPI2
-#define IRQ_USB_HOST                    EXYNOS4_IRQ_USB_HOST
-#define IRQ_OTG                         EXYNOS4_IRQ_USB_HSOTG
-#define IRQ_HSMMC0                      EXYNOS4_IRQ_HSMMC0
-#define IRQ_HSMMC1                      EXYNOS4_IRQ_HSMMC1
-#define IRQ_HSMMC2                      EXYNOS4_IRQ_HSMMC2
-#define IRQ_HSMMC3                      EXYNOS4_IRQ_HSMMC3
-#define IRQ_MIPI_CSIS0                  EXYNOS4_IRQ_MIPI_CSIS0
-#define IRQ_ONENAND_AUDI                EXYNOS4_IRQ_ONENAND_AUDI
-#define IRQ_FIMC0                       EXYNOS4_IRQ_FIMC0
-#define IRQ_FIMC1                       EXYNOS4_IRQ_FIMC1
-#define IRQ_FIMC2                       EXYNOS4_IRQ_FIMC2
-#define IRQ_FIMC3                       EXYNOS4_IRQ_FIMC3
-#define IRQ_JPEG                        EXYNOS4_IRQ_JPEG
-#define IRQ_2D                          EXYNOS4_IRQ_2D
-#define IRQ_MIXER                       EXYNOS4_IRQ_MIXER
-#define IRQ_HDMI                        EXYNOS4_IRQ_HDMI
-#define IRQ_IIC_HDMIPHY                 EXYNOS4_IRQ_IIC_HDMIPHY
-#define IRQ_MFC                         EXYNOS4_IRQ_MFC
-#define IRQ_SDO                         EXYNOS4_IRQ_SDO
-#define IRQ_I2S0                        EXYNOS4_IRQ_I2S0
-#define IRQ_ADC                         EXYNOS4_IRQ_ADC0
-#define IRQ_TC                          EXYNOS4_IRQ_PEN0
-#define IRQ_KEYPAD                      EXYNOS4_IRQ_KEYPAD
-#define IRQ_FIMD0_FIFO                  EXYNOS4_IRQ_FIMD0_FIFO
-#define IRQ_FIMD0_VSYNC                 EXYNOS4_IRQ_FIMD0_VSYNC
-#define IRQ_FIMD0_SYSTEM                EXYNOS4_IRQ_FIMD0_SYSTEM
-#define IRQ_GPIO1_NR_GROUPS             EXYNOS4_IRQ_GPIO1_NR_GROUPS
-#define IRQ_GPIO2_NR_GROUPS             EXYNOS4_IRQ_GPIO2_NR_GROUPS
-/* For EXYNOS5 SoCs */
-#define EXYNOS5_IRQ_MDMA0               IRQ_SPI(33)
-#define EXYNOS5_IRQ_PDMA0               IRQ_SPI(34)
-#define EXYNOS5_IRQ_PDMA1               IRQ_SPI(35)
-#define EXYNOS5_IRQ_TIMER0_VIC          IRQ_SPI(36)
-#define EXYNOS5_IRQ_TIMER1_VIC          IRQ_SPI(37)
-#define EXYNOS5_IRQ_TIMER2_VIC          IRQ_SPI(38)
-#define EXYNOS5_IRQ_TIMER3_VIC          IRQ_SPI(39)
-#define EXYNOS5_IRQ_TIMER4_VIC          IRQ_SPI(40)
-#define EXYNOS5_IRQ_RTIC                IRQ_SPI(41)
-#define EXYNOS5_IRQ_WDT                 IRQ_SPI(42)
-#define EXYNOS5_IRQ_RTC_ALARM           IRQ_SPI(43)
-#define EXYNOS5_IRQ_RTC_TIC             IRQ_SPI(44)
-#define EXYNOS5_IRQ_GPIO_XB             IRQ_SPI(45)
-#define EXYNOS5_IRQ_GPIO_XA             IRQ_SPI(46)
-#define EXYNOS5_IRQ_GPIO                IRQ_SPI(47)
-#define EXYNOS5_IRQ_IEM_IEC             IRQ_SPI(48)
-#define EXYNOS5_IRQ_IEM_APC             IRQ_SPI(49)
-#define EXYNOS5_IRQ_GPIO_C2C            IRQ_SPI(50)
-#define EXYNOS5_IRQ_IIC                 IRQ_SPI(56)
-#define EXYNOS5_IRQ_IIC1                IRQ_SPI(57)
-#define EXYNOS5_IRQ_IIC2                IRQ_SPI(58)
-#define EXYNOS5_IRQ_IIC3                IRQ_SPI(59)
-#define EXYNOS5_IRQ_IIC4                IRQ_SPI(60)
-#define EXYNOS5_IRQ_IIC5                IRQ_SPI(61)
-#define EXYNOS5_IRQ_IIC6                IRQ_SPI(62)
-#define EXYNOS5_IRQ_IIC7                IRQ_SPI(63)
-#define EXYNOS5_IRQ_IIC_HDMIPHY         IRQ_SPI(64)
-#define EXYNOS5_IRQ_TMU                 IRQ_SPI(65)
-#define EXYNOS5_IRQ_FIQ_0               IRQ_SPI(66)
-#define EXYNOS5_IRQ_FIQ_1               IRQ_SPI(67)
-#define EXYNOS5_IRQ_SPI0                IRQ_SPI(68)
-#define EXYNOS5_IRQ_SPI1                IRQ_SPI(69)
-#define EXYNOS5_IRQ_SPI2                IRQ_SPI(70)
-#define EXYNOS5_IRQ_USB_HOST            IRQ_SPI(71)
-#define EXYNOS5_IRQ_USB3_DRD            IRQ_SPI(72)
-#define EXYNOS5_IRQ_MIPI_HSI            IRQ_SPI(73)
-#define EXYNOS5_IRQ_USB_HSOTG           IRQ_SPI(74)
-#define EXYNOS5_IRQ_HSMMC0              IRQ_SPI(75)
-#define EXYNOS5_IRQ_HSMMC1              IRQ_SPI(76)
-#define EXYNOS5_IRQ_HSMMC2              IRQ_SPI(77)
-#define EXYNOS5_IRQ_HSMMC3              IRQ_SPI(78)
-#define EXYNOS5_IRQ_MIPICSI0            IRQ_SPI(79)
-#define EXYNOS5_IRQ_MIPICSI1            IRQ_SPI(80)
-#define EXYNOS5_IRQ_EFNFCON_DMA_ABORT   IRQ_SPI(81)
-#define EXYNOS5_IRQ_MIPIDSI0            IRQ_SPI(82)
-#define EXYNOS5_IRQ_WDT_IOP             IRQ_SPI(83)
-#define EXYNOS5_IRQ_ROTATOR             IRQ_SPI(84)
-#define EXYNOS5_IRQ_GSC0                IRQ_SPI(85)
-#define EXYNOS5_IRQ_GSC1                IRQ_SPI(86)
-#define EXYNOS5_IRQ_GSC2                IRQ_SPI(87)
-#define EXYNOS5_IRQ_GSC3                IRQ_SPI(88)
-#define EXYNOS5_IRQ_JPEG                IRQ_SPI(89)
-#define EXYNOS5_IRQ_EFNFCON_DMA         IRQ_SPI(90)
-#define EXYNOS5_IRQ_2D                  IRQ_SPI(91)
-#define EXYNOS5_IRQ_EFNFCON_0           IRQ_SPI(92)
-#define EXYNOS5_IRQ_EFNFCON_1           IRQ_SPI(93)
-#define EXYNOS5_IRQ_MIXER               IRQ_SPI(94)
-#define EXYNOS5_IRQ_HDMI                IRQ_SPI(95)
-#define EXYNOS5_IRQ_MFC                 IRQ_SPI(96)
-#define EXYNOS5_IRQ_AUDIO_SS            IRQ_SPI(97)
-#define EXYNOS5_IRQ_I2S0                IRQ_SPI(98)
-#define EXYNOS5_IRQ_I2S1                IRQ_SPI(99)
-#define EXYNOS5_IRQ_I2S2                IRQ_SPI(100)
-#define EXYNOS5_IRQ_AC97                IRQ_SPI(101)
-#define EXYNOS5_IRQ_PCM0                IRQ_SPI(102)
-#define EXYNOS5_IRQ_PCM1                IRQ_SPI(103)
-#define EXYNOS5_IRQ_PCM2                IRQ_SPI(104)
-#define EXYNOS5_IRQ_SPDIF               IRQ_SPI(105)
-#define EXYNOS5_IRQ_ADC0                IRQ_SPI(106)
-#define EXYNOS5_IRQ_ADC1                IRQ_SPI(107)
-#define EXYNOS5_IRQ_SATA_PHY            IRQ_SPI(108)
-#define EXYNOS5_IRQ_SATA_PMEMREQ        IRQ_SPI(109)
-#define EXYNOS5_IRQ_CAM_C               IRQ_SPI(110)
-#define EXYNOS5_IRQ_EAGLE_PMU           IRQ_SPI(111)
-#define EXYNOS5_IRQ_INTFEEDCTRL_SSS     IRQ_SPI(112)
-#define EXYNOS5_IRQ_DP1_INTP1           IRQ_SPI(113)
-#define EXYNOS5_IRQ_CEC                 IRQ_SPI(114)
-#define EXYNOS5_IRQ_SATA                IRQ_SPI(115)
-#define EXYNOS5_IRQ_MMC44               IRQ_SPI(123)
-#define EXYNOS5_IRQ_MDMA1               IRQ_SPI(124)
-#define EXYNOS5_IRQ_FIMC_LITE0          IRQ_SPI(125)
-#define EXYNOS5_IRQ_FIMC_LITE1          IRQ_SPI(126)
-#define EXYNOS5_IRQ_RP_TIMER            IRQ_SPI(127)
-/* EXYNOS5440 */
-#define EXYNOS5440_IRQ_UART0            IRQ_SPI(2)
-#define EXYNOS5440_IRQ_UART1            IRQ_SPI(3)
-#define EXYNOS5_IRQ_PMU                 COMBINER_IRQ(1, 2)
-#define EXYNOS5_IRQ_SYSMMU_GSC0_0       COMBINER_IRQ(2, 0)
-#define EXYNOS5_IRQ_SYSMMU_GSC0_1       COMBINER_IRQ(2, 1)
-#define EXYNOS5_IRQ_SYSMMU_GSC1_0       COMBINER_IRQ(2, 2)
-#define EXYNOS5_IRQ_SYSMMU_GSC1_1       COMBINER_IRQ(2, 3)
-#define EXYNOS5_IRQ_SYSMMU_GSC2_0       COMBINER_IRQ(2, 4)
-#define EXYNOS5_IRQ_SYSMMU_GSC2_1       COMBINER_IRQ(2, 5)
-#define EXYNOS5_IRQ_SYSMMU_GSC3_0       COMBINER_IRQ(2, 6)
-#define EXYNOS5_IRQ_SYSMMU_GSC3_1       COMBINER_IRQ(2, 7)
-#define EXYNOS5_IRQ_SYSMMU_LITE2_0      COMBINER_IRQ(3, 0)
-#define EXYNOS5_IRQ_SYSMMU_LITE2_1      COMBINER_IRQ(3, 1)
-#define EXYNOS5_IRQ_SYSMMU_FIMD1_0      COMBINER_IRQ(3, 2)
-#define EXYNOS5_IRQ_SYSMMU_FIMD1_1      COMBINER_IRQ(3, 3)
-#define EXYNOS5_IRQ_SYSMMU_LITE0_0      COMBINER_IRQ(3, 4)
-#define EXYNOS5_IRQ_SYSMMU_LITE0_1      COMBINER_IRQ(3, 5)
-#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_0 COMBINER_IRQ(3, 6)
-#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_1 COMBINER_IRQ(3, 7)
-#define EXYNOS5_IRQ_SYSMMU_ROTATOR_0    COMBINER_IRQ(4, 0)
-#define EXYNOS5_IRQ_SYSMMU_ROTATOR_1    COMBINER_IRQ(4, 1)
-#define EXYNOS5_IRQ_SYSMMU_JPEG_0       COMBINER_IRQ(4, 2)
-#define EXYNOS5_IRQ_SYSMMU_JPEG_1       COMBINER_IRQ(4, 3)
-#define EXYNOS5_IRQ_SYSMMU_FD_0         COMBINER_IRQ(5, 0)
-#define EXYNOS5_IRQ_SYSMMU_FD_1         COMBINER_IRQ(5, 1)
-#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_0 COMBINER_IRQ(5, 2)
-#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_1 COMBINER_IRQ(5, 3)
-#define EXYNOS5_IRQ_SYSMMU_MCUISP_0     COMBINER_IRQ(5, 4)
-#define EXYNOS5_IRQ_SYSMMU_MCUISP_1     COMBINER_IRQ(5, 5)
-#define EXYNOS5_IRQ_SYSMMU_3DNR_0       COMBINER_IRQ(5, 6)
-#define EXYNOS5_IRQ_SYSMMU_3DNR_1       COMBINER_IRQ(5, 7)
-#define EXYNOS5_IRQ_SYSMMU_ARM_0        COMBINER_IRQ(6, 0)
-#define EXYNOS5_IRQ_SYSMMU_ARM_1        COMBINER_IRQ(6, 1)
-#define EXYNOS5_IRQ_SYSMMU_MFC_R_0      COMBINER_IRQ(6, 2)
-#define EXYNOS5_IRQ_SYSMMU_MFC_R_1      COMBINER_IRQ(6, 3)
-#define EXYNOS5_IRQ_SYSMMU_RTIC_0       COMBINER_IRQ(6, 4)
-#define EXYNOS5_IRQ_SYSMMU_RTIC_1       COMBINER_IRQ(6, 5)
-#define EXYNOS5_IRQ_SYSMMU_SSS_0        COMBINER_IRQ(6, 6)
-#define EXYNOS5_IRQ_SYSMMU_SSS_1        COMBINER_IRQ(6, 7)
-#define EXYNOS5_IRQ_SYSMMU_MDMA0_0      COMBINER_IRQ(7, 0)
-#define EXYNOS5_IRQ_SYSMMU_MDMA0_1      COMBINER_IRQ(7, 1)
-#define EXYNOS5_IRQ_SYSMMU_MDMA1_0      COMBINER_IRQ(7, 2)
-#define EXYNOS5_IRQ_SYSMMU_MDMA1_1      COMBINER_IRQ(7, 3)
-#define EXYNOS5_IRQ_SYSMMU_TV_0         COMBINER_IRQ(7, 4)
-#define EXYNOS5_IRQ_SYSMMU_TV_1         COMBINER_IRQ(7, 5)
-#define EXYNOS5_IRQ_SYSMMU_MFC_L_0      COMBINER_IRQ(8, 5)
-#define EXYNOS5_IRQ_SYSMMU_MFC_L_1      COMBINER_IRQ(8, 6)
-#define EXYNOS5_IRQ_SYSMMU_DIS1_0       COMBINER_IRQ(9, 4)
-#define EXYNOS5_IRQ_SYSMMU_DIS1_1       COMBINER_IRQ(9, 5)
-#define EXYNOS5_IRQ_DP                  COMBINER_IRQ(10, 3)
-#define EXYNOS5_IRQ_SYSMMU_DIS0_0       COMBINER_IRQ(10, 4)
-#define EXYNOS5_IRQ_SYSMMU_DIS0_1       COMBINER_IRQ(10, 5)
-#define EXYNOS5_IRQ_SYSMMU_ISP_0        COMBINER_IRQ(10, 6)
-#define EXYNOS5_IRQ_SYSMMU_ISP_1        COMBINER_IRQ(10, 7)
-#define EXYNOS5_IRQ_SYSMMU_ODC_0        COMBINER_IRQ(11, 0)
-#define EXYNOS5_IRQ_SYSMMU_ODC_1        COMBINER_IRQ(11, 1)
-#define EXYNOS5_IRQ_SYSMMU_DRC_0        COMBINER_IRQ(11, 6)
-#define EXYNOS5_IRQ_SYSMMU_DRC_1        COMBINER_IRQ(11, 7)
-#define EXYNOS5_IRQ_MDMA1_ABORT         COMBINER_IRQ(13, 1)
-#define EXYNOS5_IRQ_MDMA0_ABORT         COMBINER_IRQ(15, 3)
-#define EXYNOS5_IRQ_FIMD1_FIFO          COMBINER_IRQ(18, 4)
-#define EXYNOS5_IRQ_FIMD1_VSYNC         COMBINER_IRQ(18, 5)
-#define EXYNOS5_IRQ_FIMD1_SYSTEM        COMBINER_IRQ(18, 6)
-#define EXYNOS5_IRQ_ARMIOP_GIC          COMBINER_IRQ(19, 0)
-#define EXYNOS5_IRQ_ARMISP_GIC          COMBINER_IRQ(19, 1)
-#define EXYNOS5_IRQ_IOP_GIC             COMBINER_IRQ(19, 3)
-#define EXYNOS5_IRQ_ISP_GIC             COMBINER_IRQ(19, 4)
-#define EXYNOS5_IRQ_PMU_CPU1            COMBINER_IRQ(22, 4)
-#define EXYNOS5_IRQ_EINT0               COMBINER_IRQ(23, 0)
-#define EXYNOS5_IRQ_EINT1               COMBINER_IRQ(24, 0)
-#define EXYNOS5_IRQ_SYSMMU_LITE1_0      COMBINER_IRQ(24, 1)
-#define EXYNOS5_IRQ_SYSMMU_LITE1_1      COMBINER_IRQ(24, 2)
-#define EXYNOS5_IRQ_SYSMMU_2D_0         COMBINER_IRQ(24, 5)
-#define EXYNOS5_IRQ_SYSMMU_2D_1         COMBINER_IRQ(24, 6)
-#define EXYNOS5_IRQ_EINT2               COMBINER_IRQ(25, 0)
-#define EXYNOS5_IRQ_EINT3               COMBINER_IRQ(25, 1)
-#define EXYNOS5_IRQ_EINT4               COMBINER_IRQ(26, 0)
-#define EXYNOS5_IRQ_EINT5               COMBINER_IRQ(26, 1)
-#define EXYNOS5_IRQ_EINT6               COMBINER_IRQ(27, 0)
-#define EXYNOS5_IRQ_EINT7               COMBINER_IRQ(27, 1)
-#define EXYNOS5_IRQ_EINT8               COMBINER_IRQ(28, 0)
-#define EXYNOS5_IRQ_EINT9               COMBINER_IRQ(28, 1)
-#define EXYNOS5_IRQ_EINT10              COMBINER_IRQ(29, 0)
-#define EXYNOS5_IRQ_EINT11              COMBINER_IRQ(29, 1)
-#define EXYNOS5_IRQ_EINT12              COMBINER_IRQ(30, 0)
-#define EXYNOS5_IRQ_EINT13              COMBINER_IRQ(30, 1)
-#define EXYNOS5_IRQ_EINT14              COMBINER_IRQ(31, 0)
-#define EXYNOS5_IRQ_EINT15              COMBINER_IRQ(31, 1)
-#define EXYNOS5_MAX_COMBINER_NR         32
-#define EXYNOS5_IRQ_GPIO1_NR_GROUPS     14
-#define EXYNOS5_IRQ_GPIO2_NR_GROUPS     9
-#define EXYNOS5_IRQ_GPIO3_NR_GROUPS     5
-#define EXYNOS5_IRQ_GPIO4_NR_GROUPS     1
-#define MAX_COMBINER_NR                 (EXYNOS4_MAX_COMBINER_NR > EXYNOS5_MAX_COMBINER_NR ? \
-                                        EXYNOS4_MAX_COMBINER_NR : EXYNOS5_MAX_COMBINER_NR)
-#define S5P_EINT_BASE1                  COMBINER_IRQ(MAX_COMBINER_NR, 0)
-#define S5P_EINT_BASE2                  (S5P_EINT_BASE1 + 16)
-#define S5P_GPIOINT_BASE                (S5P_EINT_BASE1 + 32)
-#define IRQ_GPIO_END                    (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
-#define IRQ_TIMER_BASE                  (IRQ_GPIO_END + 64)
-/* Set the default NR_IRQS */
-#define EXYNOS_NR_IRQS                  (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
-#ifndef CONFIG_SPARSE_IRQ
-#define NR_IRQS                         EXYNOS_NR_IRQS
-#endif
-#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 92b29bb583cb..7b046b59d9ec 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -30,31 +30,6 @@
 #define EXYNOS4x12_PA_SYSRAM_NS         0x0204F000
 #define EXYNOS5250_PA_SYSRAM_NS         0x0204F000
-#define EXYNOS4_PA_FIMC0                0x11800000
-#define EXYNOS4_PA_FIMC1                0x11810000
-#define EXYNOS4_PA_FIMC2                0x11820000
-#define EXYNOS4_PA_FIMC3                0x11830000
-#define EXYNOS4_PA_JPEG                 0x11840000
-/* x = 0...1 */
-#define EXYNOS4_PA_FIMC_LITE(x)         (0x12390000 + ((x) * 0x10000))
-#define EXYNOS4_PA_G2D                  0x12800000
-#define EXYNOS4_PA_I2S0                 0x03830000
-#define EXYNOS4_PA_I2S1                 0xE3100000
-#define EXYNOS4_PA_I2S2                 0xE2A00000
-#define EXYNOS4_PA_PCM0                 0x03840000
-#define EXYNOS4_PA_PCM1                 0x13980000
-#define EXYNOS4_PA_PCM2                 0x13990000
-#define EXYNOS4_PA_SROM_BANK(x)         (0x04000000 + ((x) * 0x01000000))
-#define EXYNOS4_PA_ONENAND              0x0C000000
-#define EXYNOS4_PA_ONENAND_DMA          0x0C600000
 #define EXYNOS_PA_CHIPID                0x10000000
 #define EXYNOS4_PA_SYSCON               0x10010000
@@ -71,10 +46,6 @@
 #define EXYNOS4_PA_WATCHDOG             0x10060000
 #define EXYNOS5_PA_WATCHDOG             0x101D0000
-#define EXYNOS4_PA_RTC                  0x10070000
-#define EXYNOS4_PA_KEYPAD               0x100A0000
 #define EXYNOS4_PA_DMC0                 0x10400000
 #define EXYNOS4_PA_DMC1                 0x10410000
@@ -87,207 +58,22 @@
 #define EXYNOS5_PA_GIC_DIST             0x10481000
 #define EXYNOS4_PA_COREPERI             0x10500000
-#define EXYNOS4_PA_TWD                  0x10500600
 #define EXYNOS4_PA_L2CC                 0x10502000
-#define EXYNOS4_PA_TMU                  0x100C0000
-#define EXYNOS4_PA_MDMA0                0x10810000
-#define EXYNOS4_PA_MDMA1                0x12850000
-#define EXYNOS4_PA_S_MDMA1              0x12840000
-#define EXYNOS4_PA_PDMA0                0x12680000
-#define EXYNOS4_PA_PDMA1                0x12690000
-#define EXYNOS5_PA_MDMA0                0x10800000
-#define EXYNOS5_PA_MDMA1                0x11C10000
-#define EXYNOS5_PA_PDMA0                0x121A0000
-#define EXYNOS5_PA_PDMA1                0x121B0000
-#define EXYNOS4_PA_SYSMMU_MDMA          0x10A40000
-#define EXYNOS4_PA_SYSMMU_2D_ACP        0x10A40000
-#define EXYNOS4_PA_SYSMMU_SSS           0x10A50000
-#define EXYNOS4_PA_SYSMMU_FIMC0         0x11A20000
-#define EXYNOS4_PA_SYSMMU_FIMC1         0x11A30000
-#define EXYNOS4_PA_SYSMMU_FIMC2         0x11A40000
-#define EXYNOS4_PA_SYSMMU_FIMC3         0x11A50000
-#define EXYNOS4_PA_SYSMMU_JPEG          0x11A60000
-#define EXYNOS4_PA_SYSMMU_FIMD0         0x11E20000
-#define EXYNOS4_PA_SYSMMU_FIMD1         0x12220000
-#define EXYNOS4_PA_SYSMMU_FIMC_ISP      0x12260000
-#define EXYNOS4_PA_SYSMMU_FIMC_DRC      0x12270000
-#define EXYNOS4_PA_SYSMMU_FIMC_FD       0x122A0000
-#define EXYNOS4_PA_SYSMMU_ISPCPU        0x122B0000
-#define EXYNOS4_PA_SYSMMU_FIMC_LITE0    0x123B0000
-#define EXYNOS4_PA_SYSMMU_FIMC_LITE1    0x123C0000
-#define EXYNOS4_PA_SYSMMU_PCIe          0x12620000
-#define EXYNOS4_PA_SYSMMU_G2D           0x12A20000
-#define EXYNOS4_PA_SYSMMU_ROTATOR       0x12A30000
-#define EXYNOS4_PA_SYSMMU_MDMA2         0x12A40000
-#define EXYNOS4_PA_SYSMMU_TV            0x12E20000
-#define EXYNOS4_PA_SYSMMU_MFC_L         0x13620000
-#define EXYNOS4_PA_SYSMMU_MFC_R         0x13630000
-#define EXYNOS5_PA_GSC0                 0x13E00000
-#define EXYNOS5_PA_GSC1                 0x13E10000
-#define EXYNOS5_PA_GSC2                 0x13E20000
-#define EXYNOS5_PA_GSC3                 0x13E30000
-#define EXYNOS5_PA_SYSMMU_MDMA1         0x10A40000
-#define EXYNOS5_PA_SYSMMU_SSS           0x10A50000
-#define EXYNOS5_PA_SYSMMU_2D            0x10A60000
-#define EXYNOS5_PA_SYSMMU_MFC_L         0x11200000
-#define EXYNOS5_PA_SYSMMU_MFC_R         0x11210000
-#define EXYNOS5_PA_SYSMMU_ROTATOR       0x11D40000
-#define EXYNOS5_PA_SYSMMU_MDMA2         0x11D50000
-#define EXYNOS5_PA_SYSMMU_JPEG          0x11F20000
-#define EXYNOS5_PA_SYSMMU_IOP           0x12360000
-#define EXYNOS5_PA_SYSMMU_RTIC          0x12370000
-#define EXYNOS5_PA_SYSMMU_ISP           0x13260000
-#define EXYNOS5_PA_SYSMMU_DRC           0x12370000
-#define EXYNOS5_PA_SYSMMU_SCALERC       0x13280000
-#define EXYNOS5_PA_SYSMMU_SCALERP       0x13290000
-#define EXYNOS5_PA_SYSMMU_FD            0x132A0000
-#define EXYNOS5_PA_SYSMMU_ISPCPU        0x132B0000
-#define EXYNOS5_PA_SYSMMU_ODC           0x132C0000
-#define EXYNOS5_PA_SYSMMU_DIS0          0x132D0000
-#define EXYNOS5_PA_SYSMMU_DIS1          0x132E0000
-#define EXYNOS5_PA_SYSMMU_3DNR          0x132F0000
-#define EXYNOS5_PA_SYSMMU_LITE0         0x13C40000
-#define EXYNOS5_PA_SYSMMU_LITE1         0x13C50000
-#define EXYNOS5_PA_SYSMMU_GSC0          0x13E80000
-#define EXYNOS5_PA_SYSMMU_GSC1          0x13E90000
-#define EXYNOS5_PA_SYSMMU_GSC2          0x13EA0000
-#define EXYNOS5_PA_SYSMMU_GSC3          0x13EB0000
-#define EXYNOS5_PA_SYSMMU_FIMD1         0x14640000
-#define EXYNOS5_PA_SYSMMU_TV            0x14650000
-#define EXYNOS4_PA_SPI0                 0x13920000
-#define EXYNOS4_PA_SPI1                 0x13930000
-#define EXYNOS4_PA_SPI2                 0x13940000
-#define EXYNOS5_PA_SPI0                 0x12D20000
-#define EXYNOS5_PA_SPI1                 0x12D30000
-#define EXYNOS5_PA_SPI2                 0x12D40000
-#define EXYNOS4_PA_GPIO1                0x11400000
-#define EXYNOS4_PA_GPIO2                0x11000000
-#define EXYNOS4_PA_GPIO3                0x03860000
-#define EXYNOS5_PA_GPIO1                0x11400000
-#define EXYNOS5_PA_GPIO2                0x13400000
-#define EXYNOS5_PA_GPIO3                0x10D10000
-#define EXYNOS5_PA_GPIO4                0x03860000
-#define EXYNOS4_PA_MIPI_CSIS0           0x11880000
-#define EXYNOS4_PA_MIPI_CSIS1           0x11890000
-#define EXYNOS4_PA_FIMD0                0x11C00000
-#define EXYNOS4_PA_HSMMC(x)             (0x12510000 + ((x) * 0x10000))
-#define EXYNOS4_PA_DWMCI                0x12550000
-#define EXYNOS5_PA_DWMCI0               0x12200000
-#define EXYNOS5_PA_DWMCI1               0x12210000
-#define EXYNOS5_PA_DWMCI2               0x12220000
-#define EXYNOS5_PA_DWMCI3               0x12230000
-#define EXYNOS4_PA_HSOTG                0x12480000
-#define EXYNOS4_PA_USB_HSPHY            0x125B0000
-#define EXYNOS4_PA_SATA                 0x12560000
-#define EXYNOS4_PA_SATAPHY              0x125D0000
-#define EXYNOS4_PA_SATAPHY_CTRL         0x126B0000
 #define EXYNOS4_PA_SROMC                0x12570000
 #define EXYNOS5_PA_SROMC                0x12250000
-#define EXYNOS4_PA_EHCI                 0x12580000
-#define EXYNOS4_PA_OHCI                 0x12590000
 #define EXYNOS4_PA_HSPHY                0x125B0000
-#define EXYNOS4_PA_MFC                  0x13400000
 #define EXYNOS4_PA_UART                 0x13800000
 #define EXYNOS5_PA_UART                 0x12C00000
-#define EXYNOS4_PA_VP                   0x12C00000
-#define EXYNOS4_PA_MIXER                0x12C10000
-#define EXYNOS4_PA_SDO                  0x12C20000
-#define EXYNOS4_PA_HDMI                 0x12D00000
-#define EXYNOS4_PA_IIC_HDMIPHY          0x138E0000
-#define EXYNOS4_PA_IIC(x)               (0x13860000 + ((x) * 0x10000))
-#define EXYNOS5_PA_IIC(x)               (0x12C60000 + ((x) * 0x10000))
-#define EXYNOS4_PA_ADC                  0x13910000
-#define EXYNOS4_PA_ADC1                 0x13911000
-#define EXYNOS4_PA_AC97                 0x139A0000
-#define EXYNOS4_PA_SPDIF                0x139B0000
 #define EXYNOS4_PA_TIMER                0x139D0000
 #define EXYNOS5_PA_TIMER                0x12DD0000
-#define EXYNOS4_PA_SDRAM                0x40000000
-#define EXYNOS5_PA_SDRAM                0x40000000
-/* Compatibiltiy Defines */
-#define S3C_PA_HSMMC0                   EXYNOS4_PA_HSMMC(0)
-#define S3C_PA_HSMMC1                   EXYNOS4_PA_HSMMC(1)
-#define S3C_PA_HSMMC2                   EXYNOS4_PA_HSMMC(2)
-#define S3C_PA_HSMMC3                   EXYNOS4_PA_HSMMC(3)
-#define S3C_PA_IIC                      EXYNOS4_PA_IIC(0)
-#define S3C_PA_IIC1                     EXYNOS4_PA_IIC(1)
-#define S3C_PA_IIC2                     EXYNOS4_PA_IIC(2)
-#define S3C_PA_IIC3                     EXYNOS4_PA_IIC(3)
-#define S3C_PA_IIC4                     EXYNOS4_PA_IIC(4)
-#define S3C_PA_IIC5                     EXYNOS4_PA_IIC(5)
-#define S3C_PA_IIC6                     EXYNOS4_PA_IIC(6)
-#define S3C_PA_IIC7                     EXYNOS4_PA_IIC(7)
-#define S3C_PA_RTC                      EXYNOS4_PA_RTC
-#define S3C_PA_WDT                      EXYNOS4_PA_WATCHDOG
-#define S3C_PA_SPI0                     EXYNOS4_PA_SPI0
-#define S3C_PA_SPI1                     EXYNOS4_PA_SPI1
-#define S3C_PA_SPI2                     EXYNOS4_PA_SPI2
-#define S3C_PA_USB_HSOTG                EXYNOS4_PA_HSOTG
-#define S5P_PA_EHCI                     EXYNOS4_PA_EHCI
-#define S5P_PA_FIMC0                    EXYNOS4_PA_FIMC0
-#define S5P_PA_FIMC1                    EXYNOS4_PA_FIMC1
-#define S5P_PA_FIMC2                    EXYNOS4_PA_FIMC2
-#define S5P_PA_FIMC3                    EXYNOS4_PA_FIMC3
-#define S5P_PA_JPEG                     EXYNOS4_PA_JPEG
-#define S5P_PA_G2D                      EXYNOS4_PA_G2D
-#define S5P_PA_FIMD0                    EXYNOS4_PA_FIMD0
-#define S5P_PA_HDMI                     EXYNOS4_PA_HDMI
-#define S5P_PA_IIC_HDMIPHY              EXYNOS4_PA_IIC_HDMIPHY
-#define S5P_PA_MFC                      EXYNOS4_PA_MFC
-#define S5P_PA_MIPI_CSIS0               EXYNOS4_PA_MIPI_CSIS0
-#define S5P_PA_MIPI_CSIS1               EXYNOS4_PA_MIPI_CSIS1
-#define S5P_PA_MIXER                    EXYNOS4_PA_MIXER
-#define S5P_PA_ONENAND                  EXYNOS4_PA_ONENAND
-#define S5P_PA_ONENAND_DMA              EXYNOS4_PA_ONENAND_DMA
-#define S5P_PA_SDO                      EXYNOS4_PA_SDO
-#define S5P_PA_SDRAM                    EXYNOS4_PA_SDRAM
-#define S5P_PA_VP                       EXYNOS4_PA_VP
-#define SAMSUNG_PA_ADC                  EXYNOS4_PA_ADC
-#define SAMSUNG_PA_ADC1                 EXYNOS4_PA_ADC1
-#define SAMSUNG_PA_KEYPAD               EXYNOS4_PA_KEYPAD
 /* Compatibility UART */
-#define EXYNOS4_PA_UART0                0x13800000
-#define EXYNOS4_PA_UART1                0x13810000
-#define EXYNOS4_PA_UART2                0x13820000
-#define EXYNOS4_PA_UART3                0x13830000
-#define EXYNOS4_SZ_UART                 SZ_256
-#define EXYNOS5_PA_UART0                0x12C00000
-#define EXYNOS5_PA_UART1                0x12C10000
-#define EXYNOS5_PA_UART2                0x12C20000
-#define EXYNOS5_PA_UART3                0x12C30000
 #define EXYNOS5440_PA_UART0             0x000B0000
-#define EXYNOS5440_PA_UART1             0x000C0000
-#define EXYNOS5440_SZ_UART              SZ_256
 #define S3C_VA_UARTx(x)                 (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
diff --git a/arch/arm/mach-exynos/include/mach/memory.h b/arch/arm/mach-exynos/include/mach/memory.h
index 374ef2cf7152..2a4cdb7cb326 100644
--- a/arch/arm/mach-exynos/include/mach/memory.h
+++ b/arch/arm/mach-exynos/include/mach/memory.h
@@ -15,8 +15,13 @@
 #define PLAT_PHYS_OFFSET                UL(0x40000000)
+#ifndef CONFIG_ARM_LPAE
 /* Maximum of 256MiB in one bank */
 #define MAX_PHYSMEM_BITS        32
 #define SECTION_SIZE_BITS       28
+#else
+#define MAX_PHYSMEM_BITS        36
+#define SECTION_SIZE_BITS       31
+#endif
 #endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/mach-exynos/include/mach/pm-core.h b/arch/arm/mach-exynos/include/mach/pm-core.h
index 296090e7f423..2b00833b6641 100644
--- a/arch/arm/mach-exynos/include/mach/pm-core.h
+++ b/arch/arm/mach-exynos/include/mach/pm-core.h
@@ -34,12 +34,7 @@ static inline void s3c_pm_debug_init_uart(void)
 static inline void s3c_pm_arch_prepare_irqs(void)
 {
-        u32 eintmask = s3c_irqwake_eintmask;
+        __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
-        if (of_have_populated_dt())
-                eintmask = exynos_get_eint_wake_mask();
-        __raw_writel(eintmask, S5P_EINT_WAKEUP_MASK);
        __raw_writel(s3c_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
 }
@@ -69,4 +64,9 @@ static inline void samsung_pm_saved_gpios(void)
        /* nothing here yet */
 }
+/* Compatibility definitions to make plat-samsung/pm.c compile */
+#define IRQ_EINT_BIT(x)         1
+#define s3c_irqwake_intallow    0
+#define s3c_irqwake_eintallow   0
 #endif /* __ASM_ARCH_PM_CORE_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-gpio.h b/arch/arm/mach-exynos/include/mach/regs-gpio.h
deleted file mode 100644
index e4b5b60dcb85..000000000000
--- a/arch/arm/mach-exynos/include/mach/regs-gpio.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/regs-gpio.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 - GPIO (including EINT) register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_REGS_GPIO_H
-#define __ASM_ARCH_REGS_GPIO_H __FILE__
-#include <mach/map.h>
-#include <mach/irqs.h>
-#define EINT_REG_NR(x)                  (EINT_OFFSET(x) >> 3)
-#define EINT_CON(b, x)                  (b + 0xE00 + (EINT_REG_NR(x) * 4))
-#define EINT_FLTCON(b, x)               (b + 0xE80 + (EINT_REG_NR(x) * 4))
-#define EINT_MASK(b, x)                 (b + 0xF00 + (EINT_REG_NR(x) * 4))
-#define EINT_PEND(b, x)                 (b + 0xF40 + (EINT_REG_NR(x) * 4))
-#define EINT_OFFSET_BIT(x)              (1 << (EINT_OFFSET(x) & 0x7))
-/* compatibility for plat-s5p/irq-pm.c */
-#define EXYNOS4_EINT40CON               (S5P_VA_GPIO2 + 0xE00)
-#define S5P_EINT_CON(x)                 (EXYNOS4_EINT40CON + ((x) * 0x4))
-#define EXYNOS4_EINT40FLTCON0           (S5P_VA_GPIO2 + 0xE80)
-#define S5P_EINT_FLTCON(x)              (EXYNOS4_EINT40FLTCON0 + ((x) * 0x4))
-#define EXYNOS4_EINT40MASK              (S5P_VA_GPIO2 + 0xF00)
-#define S5P_EINT_MASK(x)                (EXYNOS4_EINT40MASK + ((x) * 0x4))
-#define EXYNOS4_EINT40PEND              (S5P_VA_GPIO2 + 0xF40)
-#define S5P_EINT_PEND(x)                (EXYNOS4_EINT40PEND + ((x) * 0x4))
-#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
deleted file mode 100644
index 07277735252e..000000000000
--- a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright (C) 2011 Samsung Electronics Co.Ltd
- * Author: Joonyoung Shim <jy0922.shim@samsung.com>
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-#ifndef __PLAT_S5P_REGS_USB_PHY_H
-#define __PLAT_S5P_REGS_USB_PHY_H
-#define EXYNOS4_HSOTG_PHYREG(x)         ((x) + S3C_VA_USB_HSPHY)
-#define EXYNOS4_PHYPWR                  EXYNOS4_HSOTG_PHYREG(0x00)
-#define PHY1_HSIC_NORMAL_MASK           (0xf << 9)
-#define PHY1_HSIC1_SLEEP                (1 << 12)
-#define PHY1_HSIC1_FORCE_SUSPEND        (1 << 11)
-#define PHY1_HSIC0_SLEEP                (1 << 10)
-#define PHY1_HSIC0_FORCE_SUSPEND        (1 << 9)
-#define PHY1_STD_NORMAL_MASK            (0x7 << 6)
-#define PHY1_STD_SLEEP                  (1 << 8)
-#define PHY1_STD_ANALOG_POWERDOWN       (1 << 7)
-#define PHY1_STD_FORCE_SUSPEND          (1 << 6)
-#define PHY0_NORMAL_MASK                (0x39 << 0)
-#define PHY0_SLEEP                      (1 << 5)
-#define PHY0_OTG_DISABLE                (1 << 4)
-#define PHY0_ANALOG_POWERDOWN           (1 << 3)
-#define PHY0_FORCE_SUSPEND              (1 << 0)
-#define EXYNOS4_PHYCLK                  EXYNOS4_HSOTG_PHYREG(0x04)
-#define PHY1_COMMON_ON_N                (1 << 7)
-#define PHY0_COMMON_ON_N                (1 << 4)
-#define PHY0_ID_PULLUP                  (1 << 2)
-#define EXYNOS4_CLKSEL_SHIFT            (0)
-#define EXYNOS4210_CLKSEL_MASK          (0x3 << 0)
-#define EXYNOS4210_CLKSEL_48M           (0x0 << 0)
-#define EXYNOS4210_CLKSEL_12M           (0x2 << 0)
-#define EXYNOS4210_CLKSEL_24M           (0x3 << 0)
-#define EXYNOS4X12_CLKSEL_MASK          (0x7 << 0)
-#define EXYNOS4X12_CLKSEL_9600K         (0x0 << 0)
-#define EXYNOS4X12_CLKSEL_10M           (0x1 << 0)
-#define EXYNOS4X12_CLKSEL_12M           (0x2 << 0)
-#define EXYNOS4X12_CLKSEL_19200K        (0x3 << 0)
-#define EXYNOS4X12_CLKSEL_20M           (0x4 << 0)
-#define EXYNOS4X12_CLKSEL_24M           (0x5 << 0)
-#define EXYNOS4_RSTCON                  EXYNOS4_HSOTG_PHYREG(0x08)
-#define HOST_LINK_PORT_SWRST_MASK       (0xf << 6)
-#define HOST_LINK_PORT2_SWRST           (1 << 9)
-#define HOST_LINK_PORT1_SWRST           (1 << 8)
-#define HOST_LINK_PORT0_SWRST           (1 << 7)
-#define HOST_LINK_ALL_SWRST             (1 << 6)
-#define PHY1_SWRST_MASK                 (0x7 << 3)
-#define PHY1_HSIC_SWRST                 (1 << 5)
-#define PHY1_STD_SWRST                  (1 << 4)
-#define PHY1_ALL_SWRST                  (1 << 3)
-#define PHY0_SWRST_MASK                 (0x7 << 0)
-#define PHY0_PHYLINK_SWRST              (1 << 2)
-#define PHY0_HLINK_SWRST                (1 << 1)
-#define PHY0_SWRST                      (1 << 0)
-#define EXYNOS4_PHY1CON                 EXYNOS4_HSOTG_PHYREG(0x34)
-#define FPENABLEN                       (1 << 0)
-#endif /* __PLAT_S5P_REGS_USB_PHY_H */
diff --git a/arch/arm/mach-exynos/include/mach/uncompress.h b/arch/arm/mach-exynos/include/mach/uncompress.h
index 2979995d5a6a..5d7ce36be46f 100644
--- a/arch/arm/mach-exynos/include/mach/uncompress.h
+++ b/arch/arm/mach-exynos/include/mach/uncompress.h
@@ -15,9 +15,6 @@
 #include <asm/mach-types.h>
 #include <mach/map.h>
-volatile u8 *uart_base;
 #include <plat/uncompress.h>
 static unsigned int __raw_readl(unsigned int ptr)
@@ -31,13 +28,12 @@ static void arch_detect_cpu(void)
        /*
         * product_id is bits 31:12
-         *    bits 23:20 describe the exynosX family
+         * bits 23:20 describe the exynosX family
-         *
+         * bits 27:24 describe the exynosX family in exynos5420
         */
        chip_id >>= 20;
-        chip_id &= 0xf;
-        if (chip_id == 0x5)
+        if ((chip_id & 0x0f) == 0x5 || (chip_id & 0xf0) == 0x50)
                uart_base = (volatile u8 *)EXYNOS5_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
        else
                uart_base = (volatile u8 *)EXYNOS4_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c
deleted file mode 100644
index 5f0f55701374..000000000000
--- a/arch/arm/mach-exynos/mach-armlex4210.c
+++ /dev/null
@@ -1,207 +0,0 @@
-/* linux/arch/arm/mach-exynos4/mach-armlex4210.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/gpio.h>
-#include <linux/io.h>
-#include <linux/mmc/host.h>
-#include <linux/platform_device.h>
-#include <linux/serial_core.h>
-#include <linux/smsc911x.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/gpio-cfg.h>
-#include <plat/regs-serial.h>
-#include <plat/regs-srom.h>
-#include <plat/sdhci.h>
-#include <mach/irqs.h>
-#include <mach/map.h>
-#include "common.h"
-/* Following are default values for UCON, ULCON and UFCON UART registers */
-#define ARMLEX4210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL |        \
-                                 S3C2410_UCON_RXILEVEL |        \
-                                 S3C2410_UCON_TXIRQMODE |       \
-                                 S3C2410_UCON_RXIRQMODE |       \
-                                 S3C2410_UCON_RXFIFO_TOI |      \
-                                 S3C2443_UCON_RXERR_IRQEN)
-#define ARMLEX4210_ULCON_DEFAULT        S3C2410_LCON_CS8
-#define ARMLEX4210_UFCON_DEFAULT        (S3C2410_UFCON_FIFOMODE |       \
-                                 S5PV210_UFCON_TXTRIG4 |        \
-                                 S5PV210_UFCON_RXTRIG4)
-static struct s3c2410_uartcfg armlex4210_uartcfgs[] __initdata = {
-        [0] = {
-                .hwport         = 0,
-                .flags          = 0,
-                .ucon           = ARMLEX4210_UCON_DEFAULT,
-                .ulcon          = ARMLEX4210_ULCON_DEFAULT,
-                .ufcon          = ARMLEX4210_UFCON_DEFAULT,
-        },
-        [1] = {
-                .hwport         = 1,
-                .flags          = 0,
-                .ucon           = ARMLEX4210_UCON_DEFAULT,
-                .ulcon          = ARMLEX4210_ULCON_DEFAULT,
-                .ufcon          = ARMLEX4210_UFCON_DEFAULT,
-        },
-        [2] = {
-                .hwport         = 2,
-                .flags          = 0,
-                .ucon           = ARMLEX4210_UCON_DEFAULT,
-                .ulcon          = ARMLEX4210_ULCON_DEFAULT,
-                .ufcon          = ARMLEX4210_UFCON_DEFAULT,
-        },
-        [3] = {
-                .hwport         = 3,
-                .flags          = 0,
-                .ucon           = ARMLEX4210_UCON_DEFAULT,
-                .ulcon          = ARMLEX4210_ULCON_DEFAULT,
-                .ufcon          = ARMLEX4210_UFCON_DEFAULT,
-        },
-};
-static struct s3c_sdhci_platdata armlex4210_hsmmc0_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_PERMANENT,
-#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
-        .max_width              = 8,
-        .host_caps              = MMC_CAP_8_BIT_DATA,
-#endif
-};
-static struct s3c_sdhci_platdata armlex4210_hsmmc2_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_GPIO,
-        .ext_cd_gpio            = EXYNOS4_GPX2(5),
-        .ext_cd_gpio_invert     = 1,
-        .max_width              = 4,
-};
-static struct s3c_sdhci_platdata armlex4210_hsmmc3_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_PERMANENT,
-        .max_width              = 4,
-};
-static void __init armlex4210_sdhci_init(void)
-{
-        s3c_sdhci0_set_platdata(&armlex4210_hsmmc0_pdata);
-        s3c_sdhci2_set_platdata(&armlex4210_hsmmc2_pdata);
-        s3c_sdhci3_set_platdata(&armlex4210_hsmmc3_pdata);
-}
-static void __init armlex4210_wlan_init(void)
-{
-        /* enable */
-        s3c_gpio_cfgpin(EXYNOS4_GPX2(0), S3C_GPIO_SFN(0xf));
-        s3c_gpio_setpull(EXYNOS4_GPX2(0), S3C_GPIO_PULL_UP);
-        /* reset */
-        s3c_gpio_cfgpin(EXYNOS4_GPX1(6), S3C_GPIO_SFN(0xf));
-        s3c_gpio_setpull(EXYNOS4_GPX1(6), S3C_GPIO_PULL_UP);
-        /* wakeup */
-        s3c_gpio_cfgpin(EXYNOS4_GPX1(5), S3C_GPIO_SFN(0xf));
-        s3c_gpio_setpull(EXYNOS4_GPX1(5), S3C_GPIO_PULL_UP);
-}
-static struct resource armlex4210_smsc911x_resources[] = {
-        [0] = DEFINE_RES_MEM(EXYNOS4_PA_SROM_BANK(3), SZ_64K),
-        [1] = DEFINE_RES_NAMED(IRQ_EINT(27), 1, NULL, IORESOURCE_IRQ \
-                                        | IRQF_TRIGGER_HIGH),
-};
-static struct smsc911x_platform_config smsc9215_config = {
-        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
-        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
-        .flags          = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
-        .phy_interface  = PHY_INTERFACE_MODE_MII,
-        .mac            = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
-};
-static struct platform_device armlex4210_smsc911x = {
-        .name           = "smsc911x",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(armlex4210_smsc911x_resources),
-        .resource       = armlex4210_smsc911x_resources,
-        .dev            = {
-                .platform_data  = &smsc9215_config,
-        },
-};
-static struct platform_device *armlex4210_devices[] __initdata = {
-        &s3c_device_hsmmc0,
-        &s3c_device_hsmmc2,
-        &s3c_device_hsmmc3,
-        &s3c_device_rtc,
-        &s3c_device_wdt,
-        &armlex4210_smsc911x,
-        &exynos4_device_ahci,
-};
-static void __init armlex4210_smsc911x_init(void)
-{
-        u32 cs1;
-        /* configure nCS1 width to 16 bits */
-        cs1 = __raw_readl(S5P_SROM_BW) &
-                ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
-        cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
-                (0 << S5P_SROM_BW__WAITENABLE__SHIFT) |
-                (1 << S5P_SROM_BW__ADDRMODE__SHIFT) |
-                (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
-                S5P_SROM_BW__NCS1__SHIFT;
-        __raw_writel(cs1, S5P_SROM_BW);
-        /* set timing for nCS1 suitable for ethernet chip */
-        __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
-                     (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
-                     (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
-                     (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
-                     (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
-                     (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
-                     (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
-}
-static void __init armlex4210_map_io(void)
-{
-        exynos_init_io(NULL, 0);
-        s3c24xx_init_uarts(armlex4210_uartcfgs,
-                           ARRAY_SIZE(armlex4210_uartcfgs));
-}
-static void __init armlex4210_machine_init(void)
-{
-        armlex4210_smsc911x_init();
-        armlex4210_sdhci_init();
-        armlex4210_wlan_init();
-        platform_add_devices(armlex4210_devices,
-                             ARRAY_SIZE(armlex4210_devices));
-}
-MACHINE_START(ARMLEX4210, "ARMLEX4210")
-        /* Maintainer: Alim Akhtar <alim.akhtar@samsung.com> */
-        .atag_offset    = 0x100,
-        .smp            = smp_ops(exynos_smp_ops),
-        .init_irq       = exynos4_init_irq,
-        .map_io         = armlex4210_map_io,
-        .init_machine   = armlex4210_machine_init,
-        .init_late      = exynos_init_late,
-        .init_time      = exynos_init_time,
-        .restart        = exynos4_restart,
-MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index b9ed834a7eee..0099c6c13bba 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -23,11 +23,6 @@
 #include "common.h"
-static void __init exynos4_dt_map_io(void)
-{
-        exynos_init_io(NULL, 0);
-}
 static void __init exynos4_dt_machine_init(void)
 {
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
@@ -55,8 +50,7 @@ static void __init exynos4_reserve(void)
 DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
        /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
        .smp            = smp_ops(exynos_smp_ops),
-        .init_irq       = exynos4_init_irq,
+        .map_io         = exynos_init_io,
-        .map_io         = exynos4_dt_map_io,
        .init_early     = exynos_firmware_init,
        .init_machine   = exynos4_dt_machine_init,
        .init_late      = exynos_init_late,
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 753b94f3fca7..f874b773ca13 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -23,11 +23,6 @@
 #include "common.h"
-static void __init exynos5_dt_map_io(void)
-{
-        exynos_init_io(NULL, 0);
-}
 static void __init exynos5_dt_machine_init(void)
 {
        struct device_node *i2c_np;
@@ -57,6 +52,7 @@ static void __init exynos5_dt_machine_init(void)
 static char const *exynos5_dt_compat[] __initdata = {
        "samsung,exynos5250",
+        "samsung,exynos5420",
        "samsung,exynos5440",
        NULL
 };
@@ -76,9 +72,8 @@ static void __init exynos5_reserve(void)
 DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
-        .init_irq       = exynos5_init_irq,
        .smp            = smp_ops(exynos_smp_ops),
-        .map_io         = exynos5_dt_map_io,
+        .map_io         = exynos_init_io,
        .init_machine   = exynos5_dt_machine_init,
        .init_late      = exynos_init_late,
        .init_time      = exynos_init_time,
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
deleted file mode 100644
index 5c8b2878dbbd..000000000000
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ /dev/null
@@ -1,1388 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/mach-nuri.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/platform_device.h>
-#include <linux/serial_core.h>
-#include <linux/input.h>
-#include <linux/i2c.h>
-#include <linux/i2c/atmel_mxt_ts.h>
-#include <linux/i2c-gpio.h>
-#include <linux/gpio_keys.h>
-#include <linux/gpio.h>
-#include <linux/power/max8903_charger.h>
-#include <linux/power/max17042_battery.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-#include <linux/mfd/max8997.h>
-#include <linux/mfd/max8997-private.h>
-#include <linux/mmc/host.h>
-#include <linux/fb.h>
-#include <linux/pwm_backlight.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <linux/platform_data/mipi-csis.h>
-#include <linux/platform_data/s3c-hsotg.h>
-#include <linux/platform_data/usb-ehci-s5p.h>
-#include <drm/exynos_drm.h>
-#include <video/platform_lcd.h>
-#include <video/samsung_fimd.h>
-#include <media/m5mols.h>
-#include <media/s5k6aa.h>
-#include <media/s5p_fimc.h>
-#include <media/v4l2-mediabus.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <plat/adc.h>
-#include <plat/regs-serial.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/fb.h>
-#include <plat/sdhci.h>
-#include <plat/clock.h>
-#include <plat/gpio-cfg.h>
-#include <plat/mfc.h>
-#include <plat/fimc-core.h>
-#include <plat/camport.h>
-#include <mach/irqs.h>
-#include <mach/map.h>
-#include "common.h"
-/* Following are default values for UCON, ULCON and UFCON UART registers */
-#define NURI_UCON_DEFAULT       (S3C2410_UCON_TXILEVEL |        \
-                                 S3C2410_UCON_RXILEVEL |        \
-                                 S3C2410_UCON_TXIRQMODE |       \
-                                 S3C2410_UCON_RXIRQMODE |       \
-                                 S3C2410_UCON_RXFIFO_TOI |      \
-                                 S3C2443_UCON_RXERR_IRQEN)
-#define NURI_ULCON_DEFAULT      S3C2410_LCON_CS8
-#define NURI_UFCON_DEFAULT      (S3C2410_UFCON_FIFOMODE |       \
-                                 S5PV210_UFCON_TXTRIG256 |      \
-                                 S5PV210_UFCON_RXTRIG256)
-enum fixed_regulator_id {
-        FIXED_REG_ID_MMC = 0,
-        FIXED_REG_ID_MAX8903,
-        FIXED_REG_ID_CAM_A28V,
-        FIXED_REG_ID_CAM_12V,
-        FIXED_REG_ID_CAM_VT_15V,
-};
-static struct s3c2410_uartcfg nuri_uartcfgs[] __initdata = {
-        {
-                .hwport         = 0,
-                .ucon           = NURI_UCON_DEFAULT,
-                .ulcon          = NURI_ULCON_DEFAULT,
-                .ufcon          = NURI_UFCON_DEFAULT,
-        },
-        {
-                .hwport         = 1,
-                .ucon           = NURI_UCON_DEFAULT,
-                .ulcon          = NURI_ULCON_DEFAULT,
-                .ufcon          = NURI_UFCON_DEFAULT,
-        },
-        {
-                .hwport         = 2,
-                .ucon           = NURI_UCON_DEFAULT,
-                .ulcon          = NURI_ULCON_DEFAULT,
-                .ufcon          = NURI_UFCON_DEFAULT,
-        },
-        {
-                .hwport         = 3,
-                .ucon           = NURI_UCON_DEFAULT,
-                .ulcon          = NURI_ULCON_DEFAULT,
-                .ufcon          = NURI_UFCON_DEFAULT,
-        },
-};
-/* eMMC */
-static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = {
-        .max_width              = 8,
-        .host_caps              = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
-                                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
-                                MMC_CAP_ERASE),
-        .cd_type                = S3C_SDHCI_CD_PERMANENT,
-};
-static struct regulator_consumer_supply emmc_supplies[] = {
-        REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.0"),
-        REGULATOR_SUPPLY("vmmc", "dw_mmc"),
-};
-static struct regulator_init_data emmc_fixed_voltage_init_data = {
-        .constraints            = {
-                .name           = "VMEM_VDD_2.8V",
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(emmc_supplies),
-        .consumer_supplies      = emmc_supplies,
-};
-static struct fixed_voltage_config emmc_fixed_voltage_config = {
-        .supply_name            = "MASSMEMORY_EN (inverted)",
-        .microvolts             = 2800000,
-        .gpio                   = EXYNOS4_GPL1(1),
-        .enable_high            = false,
-        .init_data              = &emmc_fixed_voltage_init_data,
-};
-static struct platform_device emmc_fixed_voltage = {
-        .name                   = "reg-fixed-voltage",
-        .id                     = FIXED_REG_ID_MMC,
-        .dev                    = {
-                .platform_data  = &emmc_fixed_voltage_config,
-        },
-};
-/* SD */
-static struct s3c_sdhci_platdata nuri_hsmmc2_data __initdata = {
-        .max_width              = 4,
-        .host_caps              = MMC_CAP_4_BIT_DATA |
-                                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-        .ext_cd_gpio            = EXYNOS4_GPX3(3),      /* XEINT_27 */
-        .ext_cd_gpio_invert     = 1,
-        .cd_type                = S3C_SDHCI_CD_GPIO,
-};
-/* WLAN */
-static struct s3c_sdhci_platdata nuri_hsmmc3_data __initdata = {
-        .max_width              = 4,
-        .host_caps              = MMC_CAP_4_BIT_DATA |
-                                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-        .cd_type                = S3C_SDHCI_CD_EXTERNAL,
-};
-static void __init nuri_sdhci_init(void)
-{
-        s3c_sdhci0_set_platdata(&nuri_hsmmc0_data);
-        s3c_sdhci2_set_platdata(&nuri_hsmmc2_data);
-        s3c_sdhci3_set_platdata(&nuri_hsmmc3_data);
-}
-/* GPIO KEYS */
-static struct gpio_keys_button nuri_gpio_keys_tables[] = {
-        {
-                .code                   = KEY_VOLUMEUP,
-                .gpio                   = EXYNOS4_GPX2(0),      /* XEINT16 */
-                .desc                   = "gpio-keys: KEY_VOLUMEUP",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .debounce_interval      = 1,
-        }, {
-                .code                   = KEY_VOLUMEDOWN,
-                .gpio                   = EXYNOS4_GPX2(1),      /* XEINT17 */
-                .desc                   = "gpio-keys: KEY_VOLUMEDOWN",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .debounce_interval      = 1,
-        }, {
-                .code                   = KEY_POWER,
-                .gpio                   = EXYNOS4_GPX2(7),      /* XEINT23 */
-                .desc                   = "gpio-keys: KEY_POWER",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .wakeup                 = 1,
-                .debounce_interval      = 1,
-        },
-};
-static struct gpio_keys_platform_data nuri_gpio_keys_data = {
-        .buttons                = nuri_gpio_keys_tables,
-        .nbuttons               = ARRAY_SIZE(nuri_gpio_keys_tables),
-};
-static struct platform_device nuri_gpio_keys = {
-        .name                   = "gpio-keys",
-        .dev                    = {
-                .platform_data  = &nuri_gpio_keys_data,
-        },
-};
-#ifdef CONFIG_DRM_EXYNOS
-static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
-        .panel = {
-                .timing = {
-                        .xres           = 1024,
-                        .yres           = 600,
-                        .hsync_len      = 40,
-                        .left_margin    = 79,
-                        .right_margin   = 200,
-                        .vsync_len      = 10,
-                        .upper_margin   = 10,
-                        .lower_margin   = 11,
-                        .refresh        = 60,
-                },
-        },
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
-                          VIDCON0_CLKSEL_LCD,
-        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
-        .default_win    = 3,
-        .bpp            = 32,
-};
-#else
-/* Frame Buffer */
-static struct s3c_fb_pd_win nuri_fb_win0 = {
-        .max_bpp        = 24,
-        .default_bpp    = 16,
-        .xres           = 1024,
-        .yres           = 600,
-        .virtual_x      = 1024,
-        .virtual_y      = 2 * 600,
-};
-static struct fb_videomode nuri_lcd_timing = {
-        .left_margin    = 64,
-        .right_margin   = 16,
-        .upper_margin   = 64,
-        .lower_margin   = 1,
-        .hsync_len      = 48,
-        .vsync_len      = 3,
-        .xres           = 1024,
-        .yres           = 600,
-        .refresh        = 60,
-};
-static struct s3c_fb_platdata nuri_fb_pdata __initdata = {
-        .win[0]         = &nuri_fb_win0,
-        .vtiming        = &nuri_lcd_timing,
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
-                          VIDCON0_CLKSEL_LCD,
-        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
-        .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
-};
-#endif
-static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power)
-{
-        int gpio = EXYNOS4_GPE1(5);
-        gpio_request(gpio, "LVDS_nSHDN");
-        gpio_direction_output(gpio, power);
-        gpio_free(gpio);
-}
-static int nuri_bl_init(struct device *dev)
-{
-        return gpio_request_one(EXYNOS4_GPE2(3), GPIOF_OUT_INIT_LOW,
-                                "LCD_LD0_EN");
-}
-static int nuri_bl_notify(struct device *dev, int brightness)
-{
-        if (brightness < 1)
-                brightness = 0;
-        gpio_set_value(EXYNOS4_GPE2(3), 1);
-        return brightness;
-}
-static void nuri_bl_exit(struct device *dev)
-{
-        gpio_free(EXYNOS4_GPE2(3));
-}
-/* nuri pwm backlight */
-static struct platform_pwm_backlight_data nuri_backlight_data = {
-        .pwm_id                 = 0,
-        .pwm_period_ns          = 30000,
-        .max_brightness         = 100,
-        .dft_brightness         = 50,
-        .init                   = nuri_bl_init,
-        .notify                 = nuri_bl_notify,
-        .exit                   = nuri_bl_exit,
-};
-static struct platform_device nuri_backlight_device = {
-        .name                   = "pwm-backlight",
-        .id                     = -1,
-        .dev                    = {
-                .parent         = &s3c_device_timer[0].dev,
-                .platform_data  = &nuri_backlight_data,
-        },
-};
-static struct plat_lcd_data nuri_lcd_platform_data = {
-        .set_power              = nuri_lcd_power_on,
-};
-static struct platform_device nuri_lcd_device = {
-        .name                   = "platform-lcd",
-        .id                     = -1,
-        .dev                    = {
-                .platform_data  = &nuri_lcd_platform_data,
-        },
-};
-/* I2C1 */
-static struct i2c_board_info i2c1_devs[] __initdata = {
-        /* Gyro, To be updated */
-};
-/* TSP */
-static struct mxt_platform_data mxt_platform_data = {
-        .x_line                 = 18,
-        .y_line                 = 11,
-        .x_size                 = 1024,
-        .y_size                 = 600,
-        .blen                   = 0x1,
-        .threshold              = 0x28,
-        .voltage                = 2800000,              /* 2.8V */
-        .orient                 = MXT_DIAGONAL_COUNTER,
-        .irqflags               = IRQF_TRIGGER_FALLING,
-};
-static struct s3c2410_platform_i2c i2c3_data __initdata = {
-        .flags          = 0,
-        .bus_num        = 3,
-        .slave_addr     = 0x10,
-        .frequency      = 400 * 1000,
-        .sda_delay      = 100,
-};
-static struct i2c_board_info i2c3_devs[] __initdata = {
-        {
-                I2C_BOARD_INFO("atmel_mxt_ts", 0x4a),
-                .platform_data  = &mxt_platform_data,
-                .irq            = IRQ_EINT(4),
-        },
-};
-static void __init nuri_tsp_init(void)
-{
-        int gpio;
-        /* TOUCH_INT: XEINT_4 */
-        gpio = EXYNOS4_GPX0(4);
-        gpio_request(gpio, "TOUCH_INT");
-        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
-        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
-}
-static struct regulator_consumer_supply __initdata max8997_ldo1_[] = {
-        REGULATOR_SUPPLY("vdd", "s5p-adc"), /* Used by CPU's ADC drv */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo3_[] = {
-        REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"), /* USB */
-        REGULATOR_SUPPLY("vddcore", "s5p-mipi-csis.0"), /* MIPI */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo4_[] = {
-        REGULATOR_SUPPLY("vddio", "s5p-mipi-csis.0"), /* MIPI */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo5_[] = {
-        REGULATOR_SUPPLY("vhsic", "modemctl"), /* MODEM */
-};
-static struct regulator_consumer_supply nuri_max8997_ldo6_consumer[] = {
-        REGULATOR_SUPPLY("vdd_reg", "6-003c"), /* S5K6AA camera */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo7_[] = {
-        REGULATOR_SUPPLY("dig_18", "0-001f"), /* HCD803 */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo8_[] = {
-        REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"), /* USB */
-        REGULATOR_SUPPLY("vdac", NULL), /* Used by CPU */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo11_[] = {
-        REGULATOR_SUPPLY("vcc", "platform-lcd"), /* U804 LVDS */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo12_[] = {
-        REGULATOR_SUPPLY("vddio", "6-003c"), /* HDC802 */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo13_[] = {
-        REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.2"), /* TFLASH */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo14_[] = {
-        REGULATOR_SUPPLY("inmotor", "max8997-haptic"),
-};
-static struct regulator_consumer_supply __initdata max8997_ldo15_[] = {
-        REGULATOR_SUPPLY("avdd", "3-004a"), /* Touch Screen */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo16_[] = {
-        REGULATOR_SUPPLY("d_sensor", "0-001f"), /* HDC803 */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo18_[] = {
-        REGULATOR_SUPPLY("vdd", "3-004a"), /* Touch Screen */
-};
-static struct regulator_consumer_supply __initdata max8997_buck1_[] = {
-        REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */
-};
-static struct regulator_consumer_supply __initdata max8997_buck2_[] = {
-        REGULATOR_SUPPLY("vdd_int", "exynos4210-busfreq.0"), /* CPUFREQ */
-};
-static struct regulator_consumer_supply __initdata max8997_buck3_[] = {
-        REGULATOR_SUPPLY("vdd", "mali_dev.0"), /* G3D of Exynos 4 */
-};
-static struct regulator_consumer_supply __initdata max8997_buck4_[] = {
-        REGULATOR_SUPPLY("core", "0-001f"), /* HDC803 */
-};
-static struct regulator_consumer_supply __initdata max8997_buck6_[] = {
-        REGULATOR_SUPPLY("dig_28", "0-001f"), /* pin "7" of HDC803 */
-};
-static struct regulator_consumer_supply __initdata max8997_esafeout1_[] = {
-        REGULATOR_SUPPLY("usb_vbus", NULL), /* CPU's USB OTG */
-};
-static struct regulator_consumer_supply __initdata max8997_esafeout2_[] = {
-        REGULATOR_SUPPLY("usb_vbus", "modemctl"), /* VBUS of Modem */
-};
-static struct regulator_consumer_supply __initdata max8997_charger_[] = {
-        REGULATOR_SUPPLY("vinchg1", "charger-manager.0"),
-};
-static struct regulator_consumer_supply __initdata max8997_chg_toff_[] = {
-        REGULATOR_SUPPLY("vinchg_stop", NULL), /* for jack interrupt handlers */
-};
-static struct regulator_consumer_supply __initdata max8997_32khz_ap_[] = {
-        REGULATOR_SUPPLY("gps_clk", "bcm4751"),
-        REGULATOR_SUPPLY("bt_clk", "bcm4330-b1"),
-        REGULATOR_SUPPLY("wifi_clk", "bcm433-b1"),
-};
-static struct regulator_init_data __initdata max8997_ldo1_data = {
-        .constraints    = {
-                .name           = "VADC_3.3V_C210",
-                .min_uV         = 3300000,
-                .max_uV         = 3300000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo1_),
-        .consumer_supplies      = max8997_ldo1_,
-};
-static struct regulator_init_data __initdata max8997_ldo2_data = {
-        .constraints    = {
-                .name           = "VALIVE_1.1V_C210",
-                .min_uV         = 1100000,
-                .max_uV         = 1100000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-};
-static struct regulator_init_data __initdata max8997_ldo3_data = {
-        .constraints    = {
-                .name           = "VUSB_1.1V_C210",
-                .min_uV         = 1100000,
-                .max_uV         = 1100000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo3_),
-        .consumer_supplies      = max8997_ldo3_,
-};
-static struct regulator_init_data __initdata max8997_ldo4_data = {
-        .constraints    = {
-                .name           = "VMIPI_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo4_),
-        .consumer_supplies      = max8997_ldo4_,
-};
-static struct regulator_init_data __initdata max8997_ldo5_data = {
-        .constraints    = {
-                .name           = "VHSIC_1.2V_C210",
-                .min_uV         = 1200000,
-                .max_uV         = 1200000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo5_),
-        .consumer_supplies      = max8997_ldo5_,
-};
-static struct regulator_init_data __initdata max8997_ldo6_data = {
-        .constraints    = {
-                .name           = "VCC_1.8V_PDA",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(nuri_max8997_ldo6_consumer),
-        .consumer_supplies      = nuri_max8997_ldo6_consumer,
-};
-static struct regulator_init_data __initdata max8997_ldo7_data = {
-        .constraints    = {
-                .name           = "CAM_ISP_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo7_),
-        .consumer_supplies      = max8997_ldo7_,
-};
-static struct regulator_init_data __initdata max8997_ldo8_data = {
-        .constraints    = {
-                .name           = "VUSB+VDAC_3.3V_C210",
-                .min_uV         = 3300000,
-                .max_uV         = 3300000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo8_),
-        .consumer_supplies      = max8997_ldo8_,
-};
-static struct regulator_init_data __initdata max8997_ldo9_data = {
-        .constraints    = {
-                .name           = "VCC_2.8V_PDA",
-                .min_uV         = 2800000,
-                .max_uV         = 2800000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-};
-static struct regulator_init_data __initdata max8997_ldo10_data = {
-        .constraints    = {
-                .name           = "VPLL_1.1V_C210",
-                .min_uV         = 1100000,
-                .max_uV         = 1100000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-static struct regulator_init_data __initdata max8997_ldo11_data = {
-        .constraints    = {
-                .name           = "LVDS_VDD3.3V",
-                .min_uV         = 3300000,
-                .max_uV         = 3300000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .boot_on        = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo11_),
-        .consumer_supplies      = max8997_ldo11_,
-};
-static struct regulator_init_data __initdata max8997_ldo12_data = {
-        .constraints    = {
-                .name           = "VT_CAM_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo12_),
-        .consumer_supplies      = max8997_ldo12_,
-};
-static struct regulator_init_data __initdata max8997_ldo13_data = {
-        .constraints    = {
-                .name           = "VTF_2.8V",
-                .min_uV         = 2800000,
-                .max_uV         = 2800000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo13_),
-        .consumer_supplies      = max8997_ldo13_,
-};
-static struct regulator_init_data __initdata max8997_ldo14_data = {
-        .constraints    = {
-                .name           = "VCC_3.0V_MOTOR",
-                .min_uV         = 3000000,
-                .max_uV         = 3000000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo14_),
-        .consumer_supplies      = max8997_ldo14_,
-};
-static struct regulator_init_data __initdata max8997_ldo15_data = {
-        .constraints    = {
-                .name           = "VTOUCH_ADVV2.8V",
-                .min_uV         = 2800000,
-                .max_uV         = 2800000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo15_),
-        .consumer_supplies      = max8997_ldo15_,
-};
-static struct regulator_init_data __initdata max8997_ldo16_data = {
-        .constraints    = {
-                .name           = "CAM_SENSOR_IO_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo16_),
-        .consumer_supplies      = max8997_ldo16_,
-};
-static struct regulator_init_data __initdata max8997_ldo18_data = {
-        .constraints    = {
-                .name           = "VTOUCH_VDD2.8V",
-                .min_uV         = 2800000,
-                .max_uV         = 2800000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo18_),
-        .consumer_supplies      = max8997_ldo18_,
-};
-static struct regulator_init_data __initdata max8997_ldo21_data = {
-        .constraints    = {
-                .name           = "VDDQ_M1M2_1.2V",
-                .min_uV         = 1200000,
-                .max_uV         = 1200000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-static struct regulator_init_data __initdata max8997_buck1_data = {
-        .constraints    = {
-                .name           = "VARM_1.2V_C210",
-                .min_uV         = 900000,
-                .max_uV         = 1350000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                .always_on      = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies = ARRAY_SIZE(max8997_buck1_),
-        .consumer_supplies = max8997_buck1_,
-};
-static struct regulator_init_data __initdata max8997_buck2_data = {
-        .constraints    = {
-                .name           = "VINT_1.1V_C210",
-                .min_uV         = 900000,
-                .max_uV         = 1200000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                .always_on      = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies = ARRAY_SIZE(max8997_buck2_),
-        .consumer_supplies = max8997_buck2_,
-};
-static struct regulator_init_data __initdata max8997_buck3_data = {
-        .constraints    = {
-                .name           = "VG3D_1.1V_C210",
-                .min_uV         = 900000,
-                .max_uV         = 1100000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
-                                  REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies = ARRAY_SIZE(max8997_buck3_),
-        .consumer_supplies = max8997_buck3_,
-};
-static struct regulator_init_data __initdata max8997_buck4_data = {
-        .constraints    = {
-                .name           = "CAM_ISP_CORE_1.2V",
-                .min_uV         = 1200000,
-                .max_uV         = 1200000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies = ARRAY_SIZE(max8997_buck4_),
-        .consumer_supplies = max8997_buck4_,
-};
-static struct regulator_init_data __initdata max8997_buck5_data = {
-        .constraints    = {
-                .name           = "VMEM_1.2V_C210",
-                .min_uV         = 1200000,
-                .max_uV         = 1200000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-};
-static struct regulator_init_data __initdata max8997_buck6_data = {
-        .constraints    = {
-                .name           = "CAM_AF_2.8V",
-                .min_uV         = 2800000,
-                .max_uV         = 2800000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies = ARRAY_SIZE(max8997_buck6_),
-        .consumer_supplies = max8997_buck6_,
-};
-static struct regulator_init_data __initdata max8997_buck7_data = {
-        .constraints    = {
-                .name           = "VCC_SUB_2.0V",
-                .min_uV         = 2000000,
-                .max_uV         = 2000000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-};
-static struct regulator_init_data __initdata max8997_32khz_ap_data = {
-        .constraints    = {
-                .name           = "32KHz AP",
-                .always_on      = 1,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-        .num_consumer_supplies = ARRAY_SIZE(max8997_32khz_ap_),
-        .consumer_supplies = max8997_32khz_ap_,
-};
-static struct regulator_init_data __initdata max8997_32khz_cp_data = {
-        .constraints    = {
-                .name           = "32KHz CP",
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-static struct regulator_init_data __initdata max8997_vichg_data = {
-        .constraints    = {
-                .name           = "VICHG",
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-static struct regulator_init_data __initdata max8997_esafeout1_data = {
-        .constraints    = {
-                .name           = "SAFEOUT1",
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .always_on      = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_esafeout1_),
-        .consumer_supplies      = max8997_esafeout1_,
-};
-static struct regulator_init_data __initdata max8997_esafeout2_data = {
-        .constraints    = {
-                .name           = "SAFEOUT2",
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_esafeout2_),
-        .consumer_supplies      = max8997_esafeout2_,
-};
-static struct regulator_init_data __initdata max8997_charger_cv_data = {
-        .constraints    = {
-                .name           = "CHARGER_CV",
-                .min_uV         = 4200000,
-                .max_uV         = 4200000,
-                .apply_uV       = 1,
-        },
-};
-static struct regulator_init_data __initdata max8997_charger_data = {
-        .constraints    = {
-                .name           = "CHARGER",
-                .min_uA         = 200000,
-                .max_uA         = 950000,
-                .boot_on        = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS |
-                                REGULATOR_CHANGE_CURRENT,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_charger_),
-        .consumer_supplies      = max8997_charger_,
-};
-static struct regulator_init_data __initdata max8997_charger_topoff_data = {
-        .constraints    = {
-                .name           = "CHARGER TOPOFF",
-                .min_uA         = 50000,
-                .max_uA         = 200000,
-                .valid_ops_mask = REGULATOR_CHANGE_CURRENT,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_chg_toff_),
-        .consumer_supplies      = max8997_chg_toff_,
-};
-static struct max8997_regulator_data __initdata nuri_max8997_regulators[] = {
-        { MAX8997_LDO1, &max8997_ldo1_data },
-        { MAX8997_LDO2, &max8997_ldo2_data },
-        { MAX8997_LDO3, &max8997_ldo3_data },
-        { MAX8997_LDO4, &max8997_ldo4_data },
-        { MAX8997_LDO5, &max8997_ldo5_data },
-        { MAX8997_LDO6, &max8997_ldo6_data },
-        { MAX8997_LDO7, &max8997_ldo7_data },
-        { MAX8997_LDO8, &max8997_ldo8_data },
-        { MAX8997_LDO9, &max8997_ldo9_data },
-        { MAX8997_LDO10, &max8997_ldo10_data },
-        { MAX8997_LDO11, &max8997_ldo11_data },
-        { MAX8997_LDO12, &max8997_ldo12_data },
-        { MAX8997_LDO13, &max8997_ldo13_data },
-        { MAX8997_LDO14, &max8997_ldo14_data },
-        { MAX8997_LDO15, &max8997_ldo15_data },
-        { MAX8997_LDO16, &max8997_ldo16_data },
-        { MAX8997_LDO18, &max8997_ldo18_data },
-        { MAX8997_LDO21, &max8997_ldo21_data },
-        { MAX8997_BUCK1, &max8997_buck1_data },
-        { MAX8997_BUCK2, &max8997_buck2_data },
-        { MAX8997_BUCK3, &max8997_buck3_data },
-        { MAX8997_BUCK4, &max8997_buck4_data },
-        { MAX8997_BUCK5, &max8997_buck5_data },
-        { MAX8997_BUCK6, &max8997_buck6_data },
-        { MAX8997_BUCK7, &max8997_buck7_data },
-        { MAX8997_EN32KHZ_AP, &max8997_32khz_ap_data },
-        { MAX8997_EN32KHZ_CP, &max8997_32khz_cp_data },
-        { MAX8997_ENVICHG, &max8997_vichg_data },
-        { MAX8997_ESAFEOUT1, &max8997_esafeout1_data },
-        { MAX8997_ESAFEOUT2, &max8997_esafeout2_data },
-        { MAX8997_CHARGER_CV, &max8997_charger_cv_data },
-        { MAX8997_CHARGER, &max8997_charger_data },
-        { MAX8997_CHARGER_TOPOFF, &max8997_charger_topoff_data },
-};
-static struct max8997_platform_data __initdata nuri_max8997_pdata = {
-        .wakeup                 = 1,
-        .num_regulators         = ARRAY_SIZE(nuri_max8997_regulators),
-        .regulators             = nuri_max8997_regulators,
-        .buck125_gpios = { EXYNOS4_GPX0(5), EXYNOS4_GPX0(6), EXYNOS4_GPL0(0) },
-        .buck1_voltage[0] = 1350000, /* 1.35V */
-        .buck1_voltage[1] = 1300000, /* 1.3V */
-        .buck1_voltage[2] = 1250000, /* 1.25V */
-        .buck1_voltage[3] = 1200000, /* 1.2V */
-        .buck1_voltage[4] = 1150000, /* 1.15V */
-        .buck1_voltage[5] = 1100000, /* 1.1V */
-        .buck1_voltage[6] = 1000000, /* 1.0V */
-        .buck1_voltage[7] = 950000, /* 0.95V */
-        .buck2_voltage[0] = 1100000, /* 1.1V */
-        .buck2_voltage[1] = 1000000, /* 1.0V */
-        .buck2_voltage[2] = 950000, /* 0.95V */
-        .buck2_voltage[3] = 900000, /* 0.9V */
-        .buck2_voltage[4] = 1100000, /* 1.1V */
-        .buck2_voltage[5] = 1000000, /* 1.0V */
-        .buck2_voltage[6] = 950000, /* 0.95V */
-        .buck2_voltage[7] = 900000, /* 0.9V */
-        .buck5_voltage[0] = 1200000, /* 1.2V */
-        .buck5_voltage[1] = 1200000, /* 1.2V */
-        .buck5_voltage[2] = 1200000, /* 1.2V */
-        .buck5_voltage[3] = 1200000, /* 1.2V */
-        .buck5_voltage[4] = 1200000, /* 1.2V */
-        .buck5_voltage[5] = 1200000, /* 1.2V */
-        .buck5_voltage[6] = 1200000, /* 1.2V */
-        .buck5_voltage[7] = 1200000, /* 1.2V */
-};
-/* GPIO I2C 5 (PMIC) */
-enum { I2C5_MAX8997 };
-static struct i2c_board_info i2c5_devs[] __initdata = {
-        [I2C5_MAX8997] = {
-                I2C_BOARD_INFO("max8997", 0xCC >> 1),
-                .platform_data  = &nuri_max8997_pdata,
-        },
-};
-static struct max17042_platform_data nuri_battery_platform_data = {
-};
-/* GPIO I2C 9 (Fuel Gauge) */
-static struct i2c_gpio_platform_data i2c9_gpio_data = {
-        .sda_pin                = EXYNOS4_GPY4(0),      /* XM0ADDR_8 */
-        .scl_pin                = EXYNOS4_GPY4(1),      /* XM0ADDR_9 */
-};
-static struct platform_device i2c9_gpio = {
-        .name                   = "i2c-gpio",
-        .id                     = 9,
-        .dev                    = {
-                .platform_data  = &i2c9_gpio_data,
-        },
-};
-enum { I2C9_MAX17042};
-static struct i2c_board_info i2c9_devs[] __initdata = {
-        [I2C9_MAX17042] = {
-                I2C_BOARD_INFO("max17042", 0x36),
-                .platform_data = &nuri_battery_platform_data,
-        },
-};
-/* MAX8903 Secondary Charger */
-static struct regulator_consumer_supply supplies_max8903[] = {
-        REGULATOR_SUPPLY("vinchg2", "charger-manager.0"),
-};
-static struct regulator_init_data max8903_charger_en_data = {
-        .constraints = {
-                .name           = "VOUT_CHARGER",
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .boot_on        = 1,
-        },
-        .num_consumer_supplies = ARRAY_SIZE(supplies_max8903),
-        .consumer_supplies = supplies_max8903,
-};
-static struct fixed_voltage_config max8903_charger_en = {
-        .supply_name = "VOUT_CHARGER",
-        .microvolts = 5000000, /* Assume 5VDC */
-        .gpio = EXYNOS4_GPY4(5), /* TA_EN negaged */
-        .enable_high = 0, /* Enable = Low */
-        .enabled_at_boot = 1,
-        .init_data = &max8903_charger_en_data,
-};
-static struct platform_device max8903_fixed_reg_dev = {
-        .name = "reg-fixed-voltage",
-        .id = FIXED_REG_ID_MAX8903,
-        .dev = { .platform_data = &max8903_charger_en },
-};
-static struct max8903_pdata nuri_max8903 = {
-        /*
-         * cen: don't control with the driver, let it be
-         * controlled by regulator above
-         */
-        .dok = EXYNOS4_GPX1(4), /* TA_nCONNECTED */
-        /* uok, usus: not connected */
-        .chg = EXYNOS4_GPE2(0), /* TA_nCHG */
-        /* flt: vcc_1.8V_pda */
-        .dcm = EXYNOS4_GPL0(1), /* CURR_ADJ */
-        .dc_valid = true,
-        .usb_valid = false, /* USB is not wired to MAX8903 */
-};
-static struct platform_device nuri_max8903_device = {
-        .name                   = "max8903-charger",
-        .dev                    = {
-                .platform_data  = &nuri_max8903,
-        },
-};
-static void __init nuri_power_init(void)
-{
-        int gpio;
-        int ta_en = 0;
-        gpio = EXYNOS4_GPX0(7);
-        gpio_request(gpio, "AP_PMIC_IRQ");
-        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
-        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-        gpio = EXYNOS4_GPX2(3);
-        gpio_request(gpio, "FUEL_ALERT");
-        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
-        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-        gpio = nuri_max8903.dok;
-        gpio_request(gpio, "TA_nCONNECTED");
-        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
-        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-        ta_en = gpio_get_value(gpio) ? 0 : 1;
-        gpio = nuri_max8903.chg;
-        gpio_request(gpio, "TA_nCHG");
-        gpio_direction_input(gpio);
-        gpio = nuri_max8903.dcm;
-        gpio_request(gpio, "CURR_ADJ");
-        gpio_direction_output(gpio, ta_en);
-}
-/* USB EHCI */
-static struct s5p_ehci_platdata nuri_ehci_pdata;
-static void __init nuri_ehci_init(void)
-{
-        struct s5p_ehci_platdata *pdata = &nuri_ehci_pdata;
-        s5p_ehci_set_platdata(pdata);
-}
-/* USB OTG */
-static struct s3c_hsotg_plat nuri_hsotg_pdata;
-/* CAMERA */
-static struct regulator_consumer_supply cam_vt_cam15_supply =
-        REGULATOR_SUPPLY("vdd_core", "6-003c");
-static struct regulator_init_data cam_vt_cam15_reg_init_data = {
-        .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
-        .num_consumer_supplies = 1,
-        .consumer_supplies = &cam_vt_cam15_supply,
-};
-static struct fixed_voltage_config cam_vt_cam15_fixed_voltage_cfg = {
-        .supply_name    = "VT_CAM_1.5V",
-        .microvolts     = 1500000,
-        .gpio           = EXYNOS4_GPE2(2), /* VT_CAM_1.5V_EN */
-        .enable_high    = 1,
-        .init_data      = &cam_vt_cam15_reg_init_data,
-};
-static struct platform_device cam_vt_cam15_fixed_rdev = {
-        .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_VT_15V,
-        .dev = { .platform_data = &cam_vt_cam15_fixed_voltage_cfg },
-};
-static struct regulator_consumer_supply cam_vdda_supply[] = {
-        REGULATOR_SUPPLY("vdda", "6-003c"),
-        REGULATOR_SUPPLY("a_sensor", "0-001f"),
-};
-static struct regulator_init_data cam_vdda_reg_init_data = {
-        .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
-        .num_consumer_supplies = ARRAY_SIZE(cam_vdda_supply),
-        .consumer_supplies = cam_vdda_supply,
-};
-static struct fixed_voltage_config cam_vdda_fixed_voltage_cfg = {
-        .supply_name    = "CAM_IO_EN",
-        .microvolts     = 2800000,
-        .gpio           = EXYNOS4_GPE2(1), /* CAM_IO_EN */
-        .enable_high    = 1,
-        .init_data      = &cam_vdda_reg_init_data,
-};
-static struct platform_device cam_vdda_fixed_rdev = {
-        .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_A28V,
-        .dev = { .platform_data = &cam_vdda_fixed_voltage_cfg },
-};
-static struct regulator_consumer_supply camera_8m_12v_supply =
-        REGULATOR_SUPPLY("dig_12", "0-001f");
-static struct regulator_init_data cam_8m_12v_reg_init_data = {
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &camera_8m_12v_supply,
-        .constraints = {
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS
-        },
-};
-static struct fixed_voltage_config cam_8m_12v_fixed_voltage_cfg = {
-        .supply_name    = "8M_1.2V",
-        .microvolts     = 1200000,
-        .gpio           = EXYNOS4_GPE2(5), /* 8M_1.2V_EN */
-        .enable_high    = 1,
-        .init_data      = &cam_8m_12v_reg_init_data,
-};
-static struct platform_device cam_8m_12v_fixed_rdev = {
-        .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_12V,
-        .dev = { .platform_data = &cam_8m_12v_fixed_voltage_cfg },
-};
-static struct s5p_platform_mipi_csis mipi_csis_platdata = {
-        .clk_rate       = 166000000UL,
-        .lanes          = 2,
-        .hs_settle      = 12,
-};
-#define GPIO_CAM_MEGA_RST       EXYNOS4_GPY3(7) /* ISP_RESET */
-#define GPIO_CAM_8M_ISP_INT     EXYNOS4_GPL2(5)
-#define GPIO_CAM_VT_NSTBY       EXYNOS4_GPL2(0)
-#define GPIO_CAM_VT_NRST        EXYNOS4_GPL2(1)
-static struct s5k6aa_platform_data s5k6aa_pldata = {
-        .mclk_frequency = 24000000UL,
-        .gpio_reset     = { GPIO_CAM_VT_NRST, 0 },
-        .gpio_stby      = { GPIO_CAM_VT_NSTBY, 0 },
-        .bus_type       = V4L2_MBUS_PARALLEL,
-        .horiz_flip     = 1,
-};
-static struct i2c_board_info s5k6aa_board_info = {
-        I2C_BOARD_INFO("S5K6AA", 0x3c),
-        .platform_data = &s5k6aa_pldata,
-};
-static struct m5mols_platform_data m5mols_platdata = {
-        .gpio_reset = GPIO_CAM_MEGA_RST,
-};
-static struct i2c_board_info m5mols_board_info = {
-        I2C_BOARD_INFO("M5MOLS", 0x1F),
-        .platform_data  = &m5mols_platdata,
-};
-static struct fimc_source_info nuri_camera_sensors[] = {
-        {
-                .flags          = V4L2_MBUS_PCLK_SAMPLE_RISING |
-                                  V4L2_MBUS_VSYNC_ACTIVE_LOW,
-                .fimc_bus_type  = FIMC_BUS_TYPE_ITU_601,
-                .board_info     = &s5k6aa_board_info,
-                .clk_frequency  = 24000000UL,
-                .i2c_bus_num    = 6,
-        }, {
-                .flags          = V4L2_MBUS_PCLK_SAMPLE_FALLING |
-                                  V4L2_MBUS_VSYNC_ACTIVE_LOW,
-                .fimc_bus_type  = FIMC_BUS_TYPE_MIPI_CSI2,
-                .board_info     = &m5mols_board_info,
-                .clk_frequency  = 24000000UL,
-        },
-};
-static struct s5p_platform_fimc fimc_md_platdata = {
-        .source_info    = nuri_camera_sensors,
-        .num_clients    = ARRAY_SIZE(nuri_camera_sensors),
-};
-static struct gpio nuri_camera_gpios[] = {
-        { GPIO_CAM_VT_NSTBY,    GPIOF_OUT_INIT_LOW, "CAM_VGA_NSTBY" },
-        { GPIO_CAM_VT_NRST,     GPIOF_OUT_INIT_LOW, "CAM_VGA_NRST"  },
-        { GPIO_CAM_8M_ISP_INT,  GPIOF_IN,           "8M_ISP_INT"  },
-        { GPIO_CAM_MEGA_RST,    GPIOF_OUT_INIT_LOW, "CAM_8M_NRST" },
-};
-static void __init nuri_camera_init(void)
-{
-        s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata),
-                         &s5p_device_mipi_csis0);
-        s3c_set_platdata(&fimc_md_platdata,  sizeof(fimc_md_platdata),
-                         &s5p_device_fimc_md);
-        if (gpio_request_array(nuri_camera_gpios,
-                               ARRAY_SIZE(nuri_camera_gpios))) {
-                pr_err("%s: GPIO request failed\n", __func__);
-                return;
-        }
-        m5mols_board_info.irq = s5p_register_gpio_interrupt(GPIO_CAM_8M_ISP_INT);
-        if (m5mols_board_info.irq >= 0)
-                s3c_gpio_cfgpin(GPIO_CAM_8M_ISP_INT, S3C_GPIO_SFN(0xF));
-        else
-                pr_err("%s: Failed to configure 8M_ISP_INT GPIO\n", __func__);
-        /* Free GPIOs controlled directly by the sensor drivers. */
-        gpio_free(GPIO_CAM_VT_NRST);
-        gpio_free(GPIO_CAM_VT_NSTBY);
-        gpio_free(GPIO_CAM_MEGA_RST);
-        if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A)) {
-                pr_err("%s: Camera port A setup failed\n", __func__);
-                return;
-        }
-        /* Increase drive strength of the sensor clock output */
-        s5p_gpio_set_drvstr(EXYNOS4_GPJ1(3), S5P_GPIO_DRVSTR_LV4);
-}
-static struct s3c2410_platform_i2c nuri_i2c6_platdata __initdata = {
-        .frequency      = 400000U,
-        .sda_delay      = 200,
-        .bus_num        = 6,
-};
-static struct s3c2410_platform_i2c nuri_i2c0_platdata __initdata = {
-        .frequency      = 400000U,
-        .sda_delay      = 200,
-};
-/* DEVFREQ controlling memory/bus */
-static struct platform_device exynos4_bus_devfreq = {
-        .name                   = "exynos4210-busfreq",
-};
-static struct platform_device *nuri_devices[] __initdata = {
-        /* Samsung Platform Devices */
-        &s3c_device_i2c5, /* PMIC should initialize first */
-        &s3c_device_i2c0,
-        &s3c_device_i2c6,
-        &emmc_fixed_voltage,
-        &s5p_device_mipi_csis0,
-        &s5p_device_fimc0,
-        &s5p_device_fimc1,
-        &s5p_device_fimc2,
-        &s5p_device_fimc3,
-        &s5p_device_fimd0,
-        &s3c_device_hsmmc0,
-        &s3c_device_hsmmc2,
-        &s3c_device_hsmmc3,
-        &s3c_device_wdt,
-        &s3c_device_timer[0],
-        &s5p_device_ehci,
-        &s3c_device_i2c3,
-        &i2c9_gpio,
-        &s3c_device_adc,
-        &s5p_device_g2d,
-        &s5p_device_jpeg,
-        &s3c_device_rtc,
-        &s5p_device_mfc,
-        &s5p_device_mfc_l,
-        &s5p_device_mfc_r,
-        &s5p_device_fimc_md,
-        &s3c_device_usb_hsotg,
-        /* NURI Devices */
-        &nuri_gpio_keys,
-        &nuri_lcd_device,
-        &nuri_backlight_device,
-        &max8903_fixed_reg_dev,
-        &nuri_max8903_device,
-        &cam_vt_cam15_fixed_rdev,
-        &cam_vdda_fixed_rdev,
-        &cam_8m_12v_fixed_rdev,
-        &exynos4_bus_devfreq,
-};
-static void __init nuri_map_io(void)
-{
-        exynos_init_io(NULL, 0);
-        s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
-        xxti_f = 0;
-        xusbxti_f = 24000000;
-}
-static void __init nuri_reserve(void)
-{
-        s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
-}
-static void __init nuri_machine_init(void)
-{
-        nuri_sdhci_init();
-        nuri_tsp_init();
-        nuri_power_init();
-        s3c_i2c0_set_platdata(&nuri_i2c0_platdata);
-        i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
-        s3c_i2c3_set_platdata(&i2c3_data);
-        i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
-        s3c_i2c5_set_platdata(NULL);
-        i2c5_devs[I2C5_MAX8997].irq = gpio_to_irq(EXYNOS4_GPX0(7));
-        i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
-        i2c9_devs[I2C9_MAX17042].irq = gpio_to_irq(EXYNOS4_GPX2(3));
-        i2c_register_board_info(9, i2c9_devs, ARRAY_SIZE(i2c9_devs));
-        s3c_i2c6_set_platdata(&nuri_i2c6_platdata);
-#ifdef CONFIG_DRM_EXYNOS
-        s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
-        exynos4_fimd0_gpio_setup_24bpp();
-#else
-        s5p_fimd0_set_platdata(&nuri_fb_pdata);
-#endif
-        nuri_camera_init();
-        nuri_ehci_init();
-        s3c_hsotg_set_platdata(&nuri_hsotg_pdata);
-        /* Last */
-        platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices));
-}
-MACHINE_START(NURI, "NURI")
-        /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
-        .atag_offset    = 0x100,
-        .smp            = smp_ops(exynos_smp_ops),
-        .init_irq       = exynos4_init_irq,
-        .map_io         = nuri_map_io,
-        .init_machine   = nuri_machine_init,
-        .init_late      = exynos_init_late,
-        .init_time      = exynos_init_time,
-        .reserve        = &nuri_reserve,
-        .restart        = exynos4_restart,
-MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
deleted file mode 100644
index 27f03ed5d067..000000000000
--- a/arch/arm/mach-exynos/mach-origen.c
+++ /dev/null
@@ -1,823 +0,0 @@
-/* linux/arch/arm/mach-exynos4/mach-origen.c
- *
- * Copyright (c) 2011 Insignal Co., Ltd.
- *              http://www.insignal.co.kr/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/serial_core.h>
-#include <linux/leds.h>
-#include <linux/gpio.h>
-#include <linux/mmc/host.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/input.h>
-#include <linux/pwm.h>
-#include <linux/pwm_backlight.h>
-#include <linux/gpio_keys.h>
-#include <linux/i2c.h>
-#include <linux/regulator/machine.h>
-#include <linux/mfd/max8997.h>
-#include <linux/lcd.h>
-#include <linux/rfkill-gpio.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <linux/platform_data/s3c-hsotg.h>
-#include <linux/platform_data/usb-ehci-s5p.h>
-#include <linux/platform_data/usb-ohci-exynos.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <video/platform_lcd.h>
-#include <video/samsung_fimd.h>
-#include <plat/regs-serial.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/sdhci.h>
-#include <plat/clock.h>
-#include <plat/gpio-cfg.h>
-#include <plat/backlight.h>
-#include <plat/fb.h>
-#include <plat/mfc.h>
-#include <plat/hdmi.h>
-#include <mach/map.h>
-#include <mach/irqs.h>
-#include <drm/exynos_drm.h>
-#include "common.h"
-/* Following are default values for UCON, ULCON and UFCON UART registers */
-#define ORIGEN_UCON_DEFAULT     (S3C2410_UCON_TXILEVEL |        \
-                                 S3C2410_UCON_RXILEVEL |        \
-                                 S3C2410_UCON_TXIRQMODE |       \
-                                 S3C2410_UCON_RXIRQMODE |       \
-                                 S3C2410_UCON_RXFIFO_TOI |      \
-                                 S3C2443_UCON_RXERR_IRQEN)
-#define ORIGEN_ULCON_DEFAULT    S3C2410_LCON_CS8
-#define ORIGEN_UFCON_DEFAULT    (S3C2410_UFCON_FIFOMODE |       \
-                                 S5PV210_UFCON_TXTRIG4 |        \
-                                 S5PV210_UFCON_RXTRIG4)
-static struct s3c2410_uartcfg origen_uartcfgs[] __initdata = {
-        [0] = {
-                .hwport         = 0,
-                .flags          = 0,
-                .ucon           = ORIGEN_UCON_DEFAULT,
-                .ulcon          = ORIGEN_ULCON_DEFAULT,
-                .ufcon          = ORIGEN_UFCON_DEFAULT,
-        },
-        [1] = {
-                .hwport         = 1,
-                .flags          = 0,
-                .ucon           = ORIGEN_UCON_DEFAULT,
-                .ulcon          = ORIGEN_ULCON_DEFAULT,
-                .ufcon          = ORIGEN_UFCON_DEFAULT,
-        },
-        [2] = {
-                .hwport         = 2,
-                .flags          = 0,
-                .ucon           = ORIGEN_UCON_DEFAULT,
-                .ulcon          = ORIGEN_ULCON_DEFAULT,
-                .ufcon          = ORIGEN_UFCON_DEFAULT,
-        },
-        [3] = {
-                .hwport         = 3,
-                .flags          = 0,
-                .ucon           = ORIGEN_UCON_DEFAULT,
-                .ulcon          = ORIGEN_ULCON_DEFAULT,
-                .ufcon          = ORIGEN_UFCON_DEFAULT,
-        },
-};
-static struct regulator_consumer_supply __initdata ldo3_consumer[] = {
-        REGULATOR_SUPPLY("vddcore", "s5p-mipi-csis.0"), /* MIPI */
-        REGULATOR_SUPPLY("vdd", "exynos4-hdmi"), /* HDMI */
-        REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"), /* HDMI */
-        REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"), /* OTG */
-};
-static struct regulator_consumer_supply __initdata ldo6_consumer[] = {
-        REGULATOR_SUPPLY("vddio", "s5p-mipi-csis.0"), /* MIPI */
-};
-static struct regulator_consumer_supply __initdata ldo7_consumer[] = {
-        REGULATOR_SUPPLY("avdd", "alc5625"), /* Realtek ALC5625 */
-};
-static struct regulator_consumer_supply __initdata ldo8_consumer[] = {
-        REGULATOR_SUPPLY("vdd", "s5p-adc"), /* ADC */
-        REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"), /* HDMI */
-        REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"), /* OTG */
-};
-static struct regulator_consumer_supply __initdata ldo9_consumer[] = {
-        REGULATOR_SUPPLY("dvdd", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
-};
-static struct regulator_consumer_supply __initdata ldo11_consumer[] = {
-        REGULATOR_SUPPLY("dvdd", "alc5625"), /* Realtek ALC5625 */
-};
-static struct regulator_consumer_supply __initdata ldo14_consumer[] = {
-        REGULATOR_SUPPLY("avdd18", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
-};
-static struct regulator_consumer_supply __initdata ldo17_consumer[] = {
-        REGULATOR_SUPPLY("vdd33", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
-};
-static struct regulator_consumer_supply __initdata buck1_consumer[] = {
-        REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */
-};
-static struct regulator_consumer_supply __initdata buck2_consumer[] = {
-        REGULATOR_SUPPLY("vdd_int", NULL), /* CPUFREQ */
-};
-static struct regulator_consumer_supply __initdata buck3_consumer[] = {
-        REGULATOR_SUPPLY("vdd_g3d", "mali_drm"), /* G3D */
-};
-static struct regulator_consumer_supply __initdata buck7_consumer[] = {
-        REGULATOR_SUPPLY("vcc", "platform-lcd"), /* LCD */
-};
-static struct regulator_init_data __initdata max8997_ldo1_data = {
-        .constraints    = {
-                .name           = "VDD_ABB_3.3V",
-                .min_uV         = 3300000,
-                .max_uV         = 3300000,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-static struct regulator_init_data __initdata max8997_ldo2_data  = {
-        .constraints    = {
-                .name           = "VDD_ALIVE_1.1V",
-                .min_uV         = 1100000,
-                .max_uV         = 1100000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-};
-static struct regulator_init_data __initdata max8997_ldo3_data = {
-        .constraints    = {
-                .name           = "VMIPI_1.1V",
-                .min_uV         = 1100000,
-                .max_uV         = 1100000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(ldo3_consumer),
-        .consumer_supplies      = ldo3_consumer,
-};
-static struct regulator_init_data __initdata max8997_ldo4_data = {
-        .constraints    = {
-                .name           = "VDD_RTC_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-static struct regulator_init_data __initdata max8997_ldo6_data = {
-        .constraints    = {
-                .name           = "VMIPI_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(ldo6_consumer),
-        .consumer_supplies      = ldo6_consumer,
-};
-static struct regulator_init_data __initdata max8997_ldo7_data = {
-        .constraints    = {
-                .name           = "VDD_AUD_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(ldo7_consumer),
-        .consumer_supplies      = ldo7_consumer,
-};
-static struct regulator_init_data __initdata max8997_ldo8_data = {
-        .constraints    = {
-                .name           = "VADC_3.3V",
-                .min_uV         = 3300000,
-                .max_uV         = 3300000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(ldo8_consumer),
-        .consumer_supplies      = ldo8_consumer,
-};
-static struct regulator_init_data __initdata max8997_ldo9_data = {
-        .constraints    = {
-                .name           = "DVDD_SWB_2.8V",
-                .min_uV         = 2800000,
-                .max_uV         = 2800000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(ldo9_consumer),
-        .consumer_supplies      = ldo9_consumer,
-};
-static struct regulator_init_data __initdata max8997_ldo10_data = {
-        .constraints    = {
-                .name           = "VDD_PLL_1.1V",
-                .min_uV         = 1100000,
-                .max_uV         = 1100000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-static struct regulator_init_data __initdata max8997_ldo11_data = {
-        .constraints    = {
-                .name           = "VDD_AUD_3V",
-                .min_uV         = 3000000,
-                .max_uV         = 3000000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(ldo11_consumer),
-        .consumer_supplies      = ldo11_consumer,
-};
-static struct regulator_init_data __initdata max8997_ldo14_data = {
-        .constraints    = {
-                .name           = "AVDD18_SWB_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(ldo14_consumer),
-        .consumer_supplies      = ldo14_consumer,
-};
-static struct regulator_init_data __initdata max8997_ldo17_data = {
-        .constraints    = {
-                .name           = "VDD_SWB_3.3V",
-                .min_uV         = 3300000,
-                .max_uV         = 3300000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(ldo17_consumer),
-        .consumer_supplies      = ldo17_consumer,
-};
-static struct regulator_init_data __initdata max8997_ldo21_data = {
-        .constraints    = {
-                .name           = "VDD_MIF_1.2V",
-                .min_uV         = 1200000,
-                .max_uV         = 1200000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-static struct regulator_init_data __initdata max8997_buck1_data = {
-        .constraints    = {
-                .name           = "VDD_ARM_1.2V",
-                .min_uV         = 950000,
-                .max_uV         = 1350000,
-                .always_on      = 1,
-                .boot_on        = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(buck1_consumer),
-        .consumer_supplies      = buck1_consumer,
-};
-static struct regulator_init_data __initdata max8997_buck2_data = {
-        .constraints    = {
-                .name           = "VDD_INT_1.1V",
-                .min_uV         = 900000,
-                .max_uV         = 1100000,
-                .always_on      = 1,
-                .boot_on        = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(buck2_consumer),
-        .consumer_supplies      = buck2_consumer,
-};
-static struct regulator_init_data __initdata max8997_buck3_data = {
-        .constraints    = {
-                .name           = "VDD_G3D_1.1V",
-                .min_uV         = 900000,
-                .max_uV         = 1100000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
-                                        REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(buck3_consumer),
-        .consumer_supplies      = buck3_consumer,
-};
-static struct regulator_init_data __initdata max8997_buck5_data = {
-        .constraints    = {
-                .name           = "VDDQ_M1M2_1.2V",
-                .min_uV         = 1200000,
-                .max_uV         = 1200000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-static struct regulator_init_data __initdata max8997_buck7_data = {
-        .constraints    = {
-                .name           = "VDD_LCD_3.3V",
-                .min_uV         = 3300000,
-                .max_uV         = 3300000,
-                .boot_on        = 1,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(buck7_consumer),
-        .consumer_supplies      = buck7_consumer,
-};
-static struct max8997_regulator_data __initdata origen_max8997_regulators[] = {
-        { MAX8997_LDO1,         &max8997_ldo1_data },
-        { MAX8997_LDO2,         &max8997_ldo2_data },
-        { MAX8997_LDO3,         &max8997_ldo3_data },
-        { MAX8997_LDO4,         &max8997_ldo4_data },
-        { MAX8997_LDO6,         &max8997_ldo6_data },
-        { MAX8997_LDO7,         &max8997_ldo7_data },
-        { MAX8997_LDO8,         &max8997_ldo8_data },
-        { MAX8997_LDO9,         &max8997_ldo9_data },
-        { MAX8997_LDO10,        &max8997_ldo10_data },
-        { MAX8997_LDO11,        &max8997_ldo11_data },
-        { MAX8997_LDO14,        &max8997_ldo14_data },
-        { MAX8997_LDO17,        &max8997_ldo17_data },
-        { MAX8997_LDO21,        &max8997_ldo21_data },
-        { MAX8997_BUCK1,        &max8997_buck1_data },
-        { MAX8997_BUCK2,        &max8997_buck2_data },
-        { MAX8997_BUCK3,        &max8997_buck3_data },
-        { MAX8997_BUCK5,        &max8997_buck5_data },
-        { MAX8997_BUCK7,        &max8997_buck7_data },
-};
-static struct max8997_platform_data __initdata origen_max8997_pdata = {
-        .num_regulators = ARRAY_SIZE(origen_max8997_regulators),
-        .regulators     = origen_max8997_regulators,
-        .wakeup = true,
-        .buck1_gpiodvs  = false,
-        .buck2_gpiodvs  = false,
-        .buck5_gpiodvs  = false,
-        .ignore_gpiodvs_side_effect = true,
-        .buck125_default_idx = 0x0,
-        .buck125_gpios[0]       = EXYNOS4_GPX0(0),
-        .buck125_gpios[1]       = EXYNOS4_GPX0(1),
-        .buck125_gpios[2]       = EXYNOS4_GPX0(2),
-        .buck1_voltage[0]       = 1350000,
-        .buck1_voltage[1]       = 1300000,
-        .buck1_voltage[2]       = 1250000,
-        .buck1_voltage[3]       = 1200000,
-        .buck1_voltage[4]       = 1150000,
-        .buck1_voltage[5]       = 1100000,
-        .buck1_voltage[6]       = 1000000,
-        .buck1_voltage[7]       = 950000,
-        .buck2_voltage[0]       = 1100000,
-        .buck2_voltage[1]       = 1100000,
-        .buck2_voltage[2]       = 1100000,
-        .buck2_voltage[3]       = 1100000,
-        .buck2_voltage[4]       = 1000000,
-        .buck2_voltage[5]       = 1000000,
-        .buck2_voltage[6]       = 1000000,
-        .buck2_voltage[7]       = 1000000,
-        .buck5_voltage[0]       = 1200000,
-        .buck5_voltage[1]       = 1200000,
-        .buck5_voltage[2]       = 1200000,
-        .buck5_voltage[3]       = 1200000,
-        .buck5_voltage[4]       = 1200000,
-        .buck5_voltage[5]       = 1200000,
-        .buck5_voltage[6]       = 1200000,
-        .buck5_voltage[7]       = 1200000,
-};
-/* I2C0 */
-static struct i2c_board_info i2c0_devs[] __initdata = {
-        {
-                I2C_BOARD_INFO("max8997", (0xCC >> 1)),
-                .platform_data  = &origen_max8997_pdata,
-                .irq            = IRQ_EINT(4),
-        },
-};
-static struct s3c_sdhci_platdata origen_hsmmc0_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_INTERNAL,
-};
-static struct s3c_sdhci_platdata origen_hsmmc2_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_INTERNAL,
-};
-/* USB EHCI */
-static struct s5p_ehci_platdata origen_ehci_pdata;
-static void __init origen_ehci_init(void)
-{
-        struct s5p_ehci_platdata *pdata = &origen_ehci_pdata;
-        s5p_ehci_set_platdata(pdata);
-}
-/* USB OHCI */
-static struct exynos4_ohci_platdata origen_ohci_pdata;
-static void __init origen_ohci_init(void)
-{
-        struct exynos4_ohci_platdata *pdata = &origen_ohci_pdata;
-        exynos4_ohci_set_platdata(pdata);
-}
-/* USB OTG */
-static struct s3c_hsotg_plat origen_hsotg_pdata;
-static struct gpio_led origen_gpio_leds[] = {
-        {
-                .name                   = "origen::status1",
-                .default_trigger        = "heartbeat",
-                .gpio                   = EXYNOS4_GPX1(3),
-                .active_low             = 1,
-        },
-        {
-                .name                   = "origen::status2",
-                .default_trigger        = "mmc0",
-                .gpio                   = EXYNOS4_GPX1(4),
-                .active_low             = 1,
-        },
-};
-static struct gpio_led_platform_data origen_gpio_led_info = {
-        .leds           = origen_gpio_leds,
-        .num_leds       = ARRAY_SIZE(origen_gpio_leds),
-};
-static struct platform_device origen_leds_gpio = {
-        .name   = "leds-gpio",
-        .id     = -1,
-        .dev    = {
-                .platform_data  = &origen_gpio_led_info,
-        },
-};
-static struct gpio_keys_button origen_gpio_keys_table[] = {
-        {
-                .code                   = KEY_MENU,
-                .gpio                   = EXYNOS4_GPX1(5),
-                .desc                   = "gpio-keys: KEY_MENU",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .wakeup                 = 1,
-                .debounce_interval      = 1,
-        }, {
-                .code                   = KEY_HOME,
-                .gpio                   = EXYNOS4_GPX1(6),
-                .desc                   = "gpio-keys: KEY_HOME",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .wakeup                 = 1,
-                .debounce_interval      = 1,
-        }, {
-                .code                   = KEY_BACK,
-                .gpio                   = EXYNOS4_GPX1(7),
-                .desc                   = "gpio-keys: KEY_BACK",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .wakeup                 = 1,
-                .debounce_interval      = 1,
-        }, {
-                .code                   = KEY_UP,
-                .gpio                   = EXYNOS4_GPX2(0),
-                .desc                   = "gpio-keys: KEY_UP",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .wakeup                 = 1,
-                .debounce_interval      = 1,
-        }, {
-                .code                   = KEY_DOWN,
-                .gpio                   = EXYNOS4_GPX2(1),
-                .desc                   = "gpio-keys: KEY_DOWN",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .wakeup                 = 1,
-                .debounce_interval      = 1,
-        },
-};
-static struct gpio_keys_platform_data origen_gpio_keys_data = {
-        .buttons        = origen_gpio_keys_table,
-        .nbuttons       = ARRAY_SIZE(origen_gpio_keys_table),
-};
-static struct platform_device origen_device_gpiokeys = {
-        .name           = "gpio-keys",
-        .dev            = {
-                .platform_data  = &origen_gpio_keys_data,
-        },
-};
-static void lcd_hv070wsa_set_power(struct plat_lcd_data *pd, unsigned int power)
-{
-        int ret;
-        if (power)
-                ret = gpio_request_one(EXYNOS4_GPE3(4),
-                                        GPIOF_OUT_INIT_HIGH, "GPE3_4");
-        else
-                ret = gpio_request_one(EXYNOS4_GPE3(4),
-                                        GPIOF_OUT_INIT_LOW, "GPE3_4");
-        gpio_free(EXYNOS4_GPE3(4));
-        if (ret)
-                pr_err("failed to request gpio for LCD power: %d\n", ret);
-}
-static struct plat_lcd_data origen_lcd_hv070wsa_data = {
-        .set_power = lcd_hv070wsa_set_power,
-};
-static struct platform_device origen_lcd_hv070wsa = {
-        .name                   = "platform-lcd",
-        .dev.parent             = &s5p_device_fimd0.dev,
-        .dev.platform_data      = &origen_lcd_hv070wsa_data,
-};
-static struct pwm_lookup origen_pwm_lookup[] = {
-        PWM_LOOKUP("s3c24xx-pwm.0", 0, "pwm-backlight.0", NULL),
-};
-#ifdef CONFIG_DRM_EXYNOS_FIMD
-static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
-        .panel  = {
-                .timing = {
-                        .left_margin    = 64,
-                        .right_margin   = 16,
-                        .upper_margin   = 64,
-                        .lower_margin   = 16,
-                        .hsync_len      = 48,
-                        .vsync_len      = 3,
-                        .xres           = 1024,
-                        .yres           = 600,
-                },
-        },
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
-        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC |
-                                VIDCON1_INV_VCLK,
-        .default_win    = 0,
-        .bpp            = 32,
-};
-#else
-static struct s3c_fb_pd_win origen_fb_win0 = {
-        .xres                   = 1024,
-        .yres                   = 600,
-        .max_bpp                = 32,
-        .default_bpp            = 24,
-        .virtual_x              = 1024,
-        .virtual_y              = 2 * 600,
-};
-static struct fb_videomode origen_lcd_timing = {
-        .left_margin    = 64,
-        .right_margin   = 16,
-        .upper_margin   = 64,
-        .lower_margin   = 16,
-        .hsync_len      = 48,
-        .vsync_len      = 3,
-        .xres           = 1024,
-        .yres           = 600,
-};
-static struct s3c_fb_platdata origen_lcd_pdata __initdata = {
-        .win[0]         = &origen_fb_win0,
-        .vtiming        = &origen_lcd_timing,
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
-        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC |
-                                VIDCON1_INV_VCLK,
-        .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
-};
-#endif
-/* Bluetooth rfkill gpio platform data */
-static struct rfkill_gpio_platform_data origen_bt_pdata = {
-        .reset_gpio     = EXYNOS4_GPX2(2),
-        .shutdown_gpio  = -1,
-        .type           = RFKILL_TYPE_BLUETOOTH,
-        .name           = "origen-bt",
-};
-/* Bluetooth Platform device */
-static struct platform_device origen_device_bluetooth = {
-        .name           = "rfkill_gpio",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &origen_bt_pdata,
-        },
-};
-static struct platform_device *origen_devices[] __initdata = {
-        &s3c_device_hsmmc2,
-        &s3c_device_hsmmc0,
-        &s3c_device_i2c0,
-        &s3c_device_rtc,
-        &s3c_device_usb_hsotg,
-        &s3c_device_wdt,
-        &s5p_device_ehci,
-        &s5p_device_fimc0,
-        &s5p_device_fimc1,
-        &s5p_device_fimc2,
-        &s5p_device_fimc3,
-        &s5p_device_fimc_md,
-        &s5p_device_fimd0,
-        &s5p_device_g2d,
-        &s5p_device_hdmi,
-        &s5p_device_i2c_hdmiphy,
-        &s5p_device_jpeg,
-        &s5p_device_mfc,
-        &s5p_device_mfc_l,
-        &s5p_device_mfc_r,
-        &s5p_device_mixer,
-        &exynos4_device_ohci,
-        &origen_device_gpiokeys,
-        &origen_lcd_hv070wsa,
-        &origen_leds_gpio,
-        &origen_device_bluetooth,
-};
-/* LCD Backlight data */
-static struct samsung_bl_gpio_info origen_bl_gpio_info = {
-        .no             = EXYNOS4_GPD0(0),
-        .func           = S3C_GPIO_SFN(2),
-};
-static struct platform_pwm_backlight_data origen_bl_data = {
-        .pwm_id         = 0,
-        .pwm_period_ns  = 1000,
-};
-static void __init origen_bt_setup(void)
-{
-        gpio_request(EXYNOS4_GPA0(0), "GPIO BT_UART");
-        /* 4 UART Pins configuration */
-        s3c_gpio_cfgrange_nopull(EXYNOS4_GPA0(0), 4, S3C_GPIO_SFN(2));
-        /* Setup BT Reset, this gpio will be requesed by rfkill-gpio */
-        s3c_gpio_cfgpin(EXYNOS4_GPX2(2), S3C_GPIO_OUTPUT);
-        s3c_gpio_setpull(EXYNOS4_GPX2(2), S3C_GPIO_PULL_NONE);
-}
-/* I2C module and id for HDMIPHY */
-static struct i2c_board_info hdmiphy_info = {
-        I2C_BOARD_INFO("hdmiphy-exynos4210", 0x38),
-};
-static void s5p_tv_setup(void)
-{
-        /* Direct HPD to HDMI chip */
-        gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug");
-        s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
-        s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
-}
-static void __init origen_map_io(void)
-{
-        exynos_init_io(NULL, 0);
-        s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
-        xxti_f = 0;
-        xusbxti_f = 24000000;
-}
-static void __init origen_power_init(void)
-{
-        gpio_request(EXYNOS4_GPX0(4), "PMIC_IRQ");
-        s3c_gpio_cfgpin(EXYNOS4_GPX0(4), S3C_GPIO_SFN(0xf));
-        s3c_gpio_setpull(EXYNOS4_GPX0(4), S3C_GPIO_PULL_NONE);
-}
-static void __init origen_reserve(void)
-{
-        s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
-}
-static void __init origen_machine_init(void)
-{
-        origen_power_init();
-        s3c_i2c0_set_platdata(NULL);
-        i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
-        /*
-         * Since sdhci instance 2 can contain a bootable media,
-         * sdhci instance 0 is registered after instance 2.
-         */
-        s3c_sdhci2_set_platdata(&origen_hsmmc2_pdata);
-        s3c_sdhci0_set_platdata(&origen_hsmmc0_pdata);
-        origen_ehci_init();
-        origen_ohci_init();
-        s3c_hsotg_set_platdata(&origen_hsotg_pdata);
-        s5p_tv_setup();
-        s5p_i2c_hdmiphy_set_platdata(NULL);
-        s5p_hdmi_set_platdata(&hdmiphy_info, NULL, 0);
-#ifdef CONFIG_DRM_EXYNOS_FIMD
-        s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
-        exynos4_fimd0_gpio_setup_24bpp();
-#else
-        s5p_fimd0_set_platdata(&origen_lcd_pdata);
-#endif
-        platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices));
-        pwm_add_table(origen_pwm_lookup, ARRAY_SIZE(origen_pwm_lookup));
-        samsung_bl_set(&origen_bl_gpio_info, &origen_bl_data);
-        origen_bt_setup();
-}
-MACHINE_START(ORIGEN, "ORIGEN")
-        /* Maintainer: JeongHyeon Kim <jhkim@insignal.co.kr> */
-        .atag_offset    = 0x100,
-        .smp            = smp_ops(exynos_smp_ops),
-        .init_irq       = exynos4_init_irq,
-        .map_io         = origen_map_io,
-        .init_machine   = origen_machine_init,
-        .init_late      = exynos_init_late,
-        .init_time      = exynos_init_time,
-        .reserve        = &origen_reserve,
-        .restart        = exynos4_restart,
-MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c
deleted file mode 100644
index 2c8af9617920..000000000000
--- a/arch/arm/mach-exynos/mach-smdk4x12.c
+++ /dev/null
@@ -1,396 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/mach-smdk4x12.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/gpio.h>
-#include <linux/i2c.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/lcd.h>
-#include <linux/mfd/max8997.h>
-#include <linux/mmc/host.h>
-#include <linux/platform_device.h>
-#include <linux/pwm.h>
-#include <linux/pwm_backlight.h>
-#include <linux/regulator/machine.h>
-#include <linux/serial_core.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <linux/platform_data/s3c-hsotg.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <video/samsung_fimd.h>
-#include <plat/backlight.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/fb.h>
-#include <plat/gpio-cfg.h>
-#include <plat/keypad.h>
-#include <plat/mfc.h>
-#include <plat/regs-serial.h>
-#include <plat/sdhci.h>
-#include <mach/irqs.h>
-#include <mach/map.h>
-#include <drm/exynos_drm.h>
-#include "common.h"
-/* Following are default values for UCON, ULCON and UFCON UART registers */
-#define SMDK4X12_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
-                                 S3C2410_UCON_RXILEVEL |        \
-                                 S3C2410_UCON_TXIRQMODE |       \
-                                 S3C2410_UCON_RXIRQMODE |       \
-                                 S3C2410_UCON_RXFIFO_TOI |      \
-                                 S3C2443_UCON_RXERR_IRQEN)
-#define SMDK4X12_ULCON_DEFAULT  S3C2410_LCON_CS8
-#define SMDK4X12_UFCON_DEFAULT  (S3C2410_UFCON_FIFOMODE |       \
-                                 S5PV210_UFCON_TXTRIG4 |        \
-                                 S5PV210_UFCON_RXTRIG4)
-static struct s3c2410_uartcfg smdk4x12_uartcfgs[] __initdata = {
-        [0] = {
-                .hwport         = 0,
-                .flags          = 0,
-                .ucon           = SMDK4X12_UCON_DEFAULT,
-                .ulcon          = SMDK4X12_ULCON_DEFAULT,
-                .ufcon          = SMDK4X12_UFCON_DEFAULT,
-        },
-        [1] = {
-                .hwport         = 1,
-                .flags          = 0,
-                .ucon           = SMDK4X12_UCON_DEFAULT,
-                .ulcon          = SMDK4X12_ULCON_DEFAULT,
-                .ufcon          = SMDK4X12_UFCON_DEFAULT,
-        },
-        [2] = {
-                .hwport         = 2,
-                .flags          = 0,
-                .ucon           = SMDK4X12_UCON_DEFAULT,
-                .ulcon          = SMDK4X12_ULCON_DEFAULT,
-                .ufcon          = SMDK4X12_UFCON_DEFAULT,
-        },
-        [3] = {
-                .hwport         = 3,
-                .flags          = 0,
-                .ucon           = SMDK4X12_UCON_DEFAULT,
-                .ulcon          = SMDK4X12_ULCON_DEFAULT,
-                .ufcon          = SMDK4X12_UFCON_DEFAULT,
-        },
-};
-static struct s3c_sdhci_platdata smdk4x12_hsmmc2_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_INTERNAL,
-#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
-        .max_width              = 8,
-        .host_caps              = MMC_CAP_8_BIT_DATA,
-#endif
-};
-static struct s3c_sdhci_platdata smdk4x12_hsmmc3_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_INTERNAL,
-};
-static struct regulator_consumer_supply max8997_buck1 =
-        REGULATOR_SUPPLY("vdd_arm", NULL);
-static struct regulator_consumer_supply max8997_buck2 =
-        REGULATOR_SUPPLY("vdd_int", NULL);
-static struct regulator_consumer_supply max8997_buck3 =
-        REGULATOR_SUPPLY("vdd_g3d", NULL);
-static struct regulator_init_data max8997_buck1_data = {
-        .constraints    = {
-                .name           = "VDD_ARM_SMDK4X12",
-                .min_uV         = 925000,
-                .max_uV         = 1350000,
-                .always_on      = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &max8997_buck1,
-};
-static struct regulator_init_data max8997_buck2_data = {
-        .constraints    = {
-                .name           = "VDD_INT_SMDK4X12",
-                .min_uV         = 950000,
-                .max_uV         = 1150000,
-                .always_on      = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &max8997_buck2,
-};
-static struct regulator_init_data max8997_buck3_data = {
-        .constraints    = {
-                .name           = "VDD_G3D_SMDK4X12",
-                .min_uV         = 950000,
-                .max_uV         = 1150000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
-                                  REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &max8997_buck3,
-};
-static struct max8997_regulator_data smdk4x12_max8997_regulators[] = {
-        { MAX8997_BUCK1, &max8997_buck1_data },
-        { MAX8997_BUCK2, &max8997_buck2_data },
-        { MAX8997_BUCK3, &max8997_buck3_data },
-};
-static struct max8997_platform_data smdk4x12_max8997_pdata = {
-        .num_regulators = ARRAY_SIZE(smdk4x12_max8997_regulators),
-        .regulators     = smdk4x12_max8997_regulators,
-        .buck1_voltage[0] = 1100000,    /* 1.1V */
-        .buck1_voltage[1] = 1100000,    /* 1.1V */
-        .buck1_voltage[2] = 1100000,    /* 1.1V */
-        .buck1_voltage[3] = 1100000,    /* 1.1V */
-        .buck1_voltage[4] = 1100000,    /* 1.1V */
-        .buck1_voltage[5] = 1100000,    /* 1.1V */
-        .buck1_voltage[6] = 1000000,    /* 1.0V */
-        .buck1_voltage[7] = 950000,     /* 0.95V */
-        .buck2_voltage[0] = 1100000,    /* 1.1V */
-        .buck2_voltage[1] = 1000000,    /* 1.0V */
-        .buck2_voltage[2] = 950000,     /* 0.95V */
-        .buck2_voltage[3] = 900000,     /* 0.9V */
-        .buck2_voltage[4] = 1100000,    /* 1.1V */
-        .buck2_voltage[5] = 1000000,    /* 1.0V */
-        .buck2_voltage[6] = 950000,     /* 0.95V */
-        .buck2_voltage[7] = 900000,     /* 0.9V */
-        .buck5_voltage[0] = 1100000,    /* 1.1V */
-        .buck5_voltage[1] = 1100000,    /* 1.1V */
-        .buck5_voltage[2] = 1100000,    /* 1.1V */
-        .buck5_voltage[3] = 1100000,    /* 1.1V */
-        .buck5_voltage[4] = 1100000,    /* 1.1V */
-        .buck5_voltage[5] = 1100000,    /* 1.1V */
-        .buck5_voltage[6] = 1100000,    /* 1.1V */
-        .buck5_voltage[7] = 1100000,    /* 1.1V */
-};
-static struct i2c_board_info smdk4x12_i2c_devs0[] __initdata = {
-        {
-                I2C_BOARD_INFO("max8997", 0x66),
-                .platform_data  = &smdk4x12_max8997_pdata,
-        }
-};
-static struct i2c_board_info smdk4x12_i2c_devs1[] __initdata = {
-        { I2C_BOARD_INFO("wm8994", 0x1a), }
-};
-static struct i2c_board_info smdk4x12_i2c_devs3[] __initdata = {
-        /* nothing here yet */
-};
-static struct i2c_board_info smdk4x12_i2c_devs7[] __initdata = {
-        /* nothing here yet */
-};
-static struct samsung_bl_gpio_info smdk4x12_bl_gpio_info = {
-        .no = EXYNOS4_GPD0(1),
-        .func = S3C_GPIO_SFN(2),
-};
-static struct platform_pwm_backlight_data smdk4x12_bl_data = {
-        .pwm_id = 1,
-        .pwm_period_ns  = 1000,
-};
-static struct pwm_lookup smdk4x12_pwm_lookup[] = {
-        PWM_LOOKUP("s3c24xx-pwm.1", 0, "pwm-backlight.0", NULL),
-};
-static uint32_t smdk4x12_keymap[] __initdata = {
-        /* KEY(row, col, keycode) */
-        KEY(1, 3, KEY_1), KEY(1, 4, KEY_2), KEY(1, 5, KEY_3),
-        KEY(1, 6, KEY_4), KEY(1, 7, KEY_5),
-        KEY(2, 5, KEY_D), KEY(2, 6, KEY_A), KEY(2, 7, KEY_B),
-        KEY(0, 7, KEY_E), KEY(0, 5, KEY_C)
-};
-static struct matrix_keymap_data smdk4x12_keymap_data __initdata = {
-        .keymap         = smdk4x12_keymap,
-        .keymap_size    = ARRAY_SIZE(smdk4x12_keymap),
-};
-static struct samsung_keypad_platdata smdk4x12_keypad_data __initdata = {
-        .keymap_data    = &smdk4x12_keymap_data,
-        .rows           = 3,
-        .cols           = 8,
-};
-#ifdef CONFIG_DRM_EXYNOS_FIMD
-static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
-        .panel  = {
-                .timing = {
-                        .left_margin    = 8,
-                        .right_margin   = 8,
-                        .upper_margin   = 6,
-                        .lower_margin   = 6,
-                        .hsync_len      = 6,
-                        .vsync_len      = 4,
-                        .xres           = 480,
-                        .yres           = 800,
-                },
-        },
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
-        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
-        .default_win    = 0,
-        .bpp            = 32,
-};
-#else
-static struct s3c_fb_pd_win smdk4x12_fb_win0 = {
-        .xres           = 480,
-        .yres           = 800,
-        .virtual_x      = 480,
-        .virtual_y      = 800 * 2,
-        .max_bpp        = 32,
-        .default_bpp    = 24,
-};
-static struct fb_videomode smdk4x12_lcd_timing = {
-        .left_margin    = 8,
-        .right_margin   = 8,
-        .upper_margin   = 6,
-        .lower_margin   = 6,
-        .hsync_len      = 6,
-        .vsync_len      = 4,
-        .xres           = 480,
-        .yres           = 800,
-};
-static struct s3c_fb_platdata smdk4x12_lcd_pdata __initdata = {
-        .win[0]         = &smdk4x12_fb_win0,
-        .vtiming        = &smdk4x12_lcd_timing,
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
-        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
-        .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
-};
-#endif
-/* USB OTG */
-static struct s3c_hsotg_plat smdk4x12_hsotg_pdata;
-static struct platform_device *smdk4x12_devices[] __initdata = {
-        &s3c_device_hsmmc2,
-        &s3c_device_hsmmc3,
-        &s3c_device_i2c0,
-        &s3c_device_i2c1,
-        &s3c_device_i2c3,
-        &s3c_device_i2c7,
-        &s3c_device_rtc,
-        &s3c_device_usb_hsotg,
-        &s3c_device_wdt,
-        &s5p_device_fimc0,
-        &s5p_device_fimc1,
-        &s5p_device_fimc2,
-        &s5p_device_fimc3,
-        &s5p_device_fimc_md,
-        &s5p_device_fimd0,
-        &s5p_device_mfc,
-        &s5p_device_mfc_l,
-        &s5p_device_mfc_r,
-        &samsung_device_keypad,
-};
-static void __init smdk4x12_map_io(void)
-{
-        exynos_init_io(NULL, 0);
-        s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs));
-}
-static void __init smdk4x12_reserve(void)
-{
-        s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
-}
-static void __init smdk4x12_machine_init(void)
-{
-        s3c_i2c0_set_platdata(NULL);
-        i2c_register_board_info(0, smdk4x12_i2c_devs0,
-                                ARRAY_SIZE(smdk4x12_i2c_devs0));
-        s3c_i2c1_set_platdata(NULL);
-        i2c_register_board_info(1, smdk4x12_i2c_devs1,
-                                ARRAY_SIZE(smdk4x12_i2c_devs1));
-        s3c_i2c3_set_platdata(NULL);
-        i2c_register_board_info(3, smdk4x12_i2c_devs3,
-                                ARRAY_SIZE(smdk4x12_i2c_devs3));
-        s3c_i2c7_set_platdata(NULL);
-        i2c_register_board_info(7, smdk4x12_i2c_devs7,
-                                ARRAY_SIZE(smdk4x12_i2c_devs7));
-        samsung_bl_set(&smdk4x12_bl_gpio_info, &smdk4x12_bl_data);
-        pwm_add_table(smdk4x12_pwm_lookup, ARRAY_SIZE(smdk4x12_pwm_lookup));
-        samsung_keypad_set_platdata(&smdk4x12_keypad_data);
-        s3c_sdhci2_set_platdata(&smdk4x12_hsmmc2_pdata);
-        s3c_sdhci3_set_platdata(&smdk4x12_hsmmc3_pdata);
-        s3c_hsotg_set_platdata(&smdk4x12_hsotg_pdata);
-#ifdef CONFIG_DRM_EXYNOS_FIMD
-        s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
-        exynos4_fimd0_gpio_setup_24bpp();
-#else
-        s5p_fimd0_set_platdata(&smdk4x12_lcd_pdata);
-#endif
-        platform_add_devices(smdk4x12_devices, ARRAY_SIZE(smdk4x12_devices));
-}
-MACHINE_START(SMDK4212, "SMDK4212")
-        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
-        .atag_offset    = 0x100,
-        .smp            = smp_ops(exynos_smp_ops),
-        .init_irq       = exynos4_init_irq,
-        .map_io         = smdk4x12_map_io,
-        .init_machine   = smdk4x12_machine_init,
-        .init_time      = exynos_init_time,
-        .restart        = exynos4_restart,
-        .reserve        = &smdk4x12_reserve,
-MACHINE_END
-MACHINE_START(SMDK4412, "SMDK4412")
-        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
-        /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
-        .atag_offset    = 0x100,
-        .smp            = smp_ops(exynos_smp_ops),
-        .init_irq       = exynos4_init_irq,
-        .map_io         = smdk4x12_map_io,
-        .init_machine   = smdk4x12_machine_init,
-        .init_late      = exynos_init_late,
-        .init_time      = exynos_init_time,
-        .restart        = exynos4_restart,
-        .reserve        = &smdk4x12_reserve,
-MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
deleted file mode 100644
index d95b8cf85253..000000000000
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ /dev/null
@@ -1,444 +0,0 @@
-/* linux/arch/arm/mach-exynos4/mach-smdkv310.c
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/serial_core.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/lcd.h>
-#include <linux/mmc/host.h>
-#include <linux/platform_device.h>
-#include <linux/smsc911x.h>
-#include <linux/io.h>
-#include <linux/i2c.h>
-#include <linux/input.h>
-#include <linux/pwm.h>
-#include <linux/pwm_backlight.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <linux/platform_data/s3c-hsotg.h>
-#include <linux/platform_data/usb-ehci-s5p.h>
-#include <linux/platform_data/usb-ohci-exynos.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <video/platform_lcd.h>
-#include <video/samsung_fimd.h>
-#include <plat/regs-serial.h>
-#include <plat/regs-srom.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/fb.h>
-#include <plat/keypad.h>
-#include <plat/sdhci.h>
-#include <plat/gpio-cfg.h>
-#include <plat/backlight.h>
-#include <plat/mfc.h>
-#include <plat/clock.h>
-#include <plat/hdmi.h>
-#include <mach/irqs.h>
-#include <mach/map.h>
-#include <drm/exynos_drm.h>
-#include "common.h"
-/* Following are default values for UCON, ULCON and UFCON UART registers */
-#define SMDKV310_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
-                                 S3C2410_UCON_RXILEVEL |        \
-                                 S3C2410_UCON_TXIRQMODE |       \
-                                 S3C2410_UCON_RXIRQMODE |       \
-                                 S3C2410_UCON_RXFIFO_TOI |      \
-                                 S3C2443_UCON_RXERR_IRQEN)
-#define SMDKV310_ULCON_DEFAULT  S3C2410_LCON_CS8
-#define SMDKV310_UFCON_DEFAULT  (S3C2410_UFCON_FIFOMODE |       \
-                                 S5PV210_UFCON_TXTRIG4 |        \
-                                 S5PV210_UFCON_RXTRIG4)
-static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = {
-        [0] = {
-                .hwport         = 0,
-                .flags          = 0,
-                .ucon           = SMDKV310_UCON_DEFAULT,
-                .ulcon          = SMDKV310_ULCON_DEFAULT,
-                .ufcon          = SMDKV310_UFCON_DEFAULT,
-        },
-        [1] = {
-                .hwport         = 1,
-                .flags          = 0,
-                .ucon           = SMDKV310_UCON_DEFAULT,
-                .ulcon          = SMDKV310_ULCON_DEFAULT,
-                .ufcon          = SMDKV310_UFCON_DEFAULT,
-        },
-        [2] = {
-                .hwport         = 2,
-                .flags          = 0,
-                .ucon           = SMDKV310_UCON_DEFAULT,
-                .ulcon          = SMDKV310_ULCON_DEFAULT,
-                .ufcon          = SMDKV310_UFCON_DEFAULT,
-        },
-        [3] = {
-                .hwport         = 3,
-                .flags          = 0,
-                .ucon           = SMDKV310_UCON_DEFAULT,
-                .ulcon          = SMDKV310_ULCON_DEFAULT,
-                .ufcon          = SMDKV310_UFCON_DEFAULT,
-        },
-};
-static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_INTERNAL,
-#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
-        .max_width              = 8,
-        .host_caps              = MMC_CAP_8_BIT_DATA,
-#endif
-};
-static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_GPIO,
-        .ext_cd_gpio            = EXYNOS4_GPK0(2),
-        .ext_cd_gpio_invert     = 1,
-};
-static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_INTERNAL,
-#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
-        .max_width              = 8,
-        .host_caps              = MMC_CAP_8_BIT_DATA,
-#endif
-};
-static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_GPIO,
-        .ext_cd_gpio            = EXYNOS4_GPK2(2),
-        .ext_cd_gpio_invert     = 1,
-};
-static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
-                                   unsigned int power)
-{
-        if (power) {
-#if !defined(CONFIG_BACKLIGHT_PWM)
-                gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0");
-                gpio_free(EXYNOS4_GPD0(1));
-#endif
-                /* fire nRESET on power up */
-                gpio_request_one(EXYNOS4_GPX0(6), GPIOF_OUT_INIT_HIGH, "GPX0");
-                mdelay(100);
-                gpio_set_value(EXYNOS4_GPX0(6), 0);
-                mdelay(10);
-                gpio_set_value(EXYNOS4_GPX0(6), 1);
-                mdelay(10);
-                gpio_free(EXYNOS4_GPX0(6));
-        } else {
-#if !defined(CONFIG_BACKLIGHT_PWM)
-                gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0");
-                gpio_free(EXYNOS4_GPD0(1));
-#endif
-        }
-}
-static struct plat_lcd_data smdkv310_lcd_lte480wv_data = {
-        .set_power              = lcd_lte480wv_set_power,
-};
-static struct platform_device smdkv310_lcd_lte480wv = {
-        .name                   = "platform-lcd",
-        .dev.parent             = &s5p_device_fimd0.dev,
-        .dev.platform_data      = &smdkv310_lcd_lte480wv_data,
-};
-#ifdef CONFIG_DRM_EXYNOS_FIMD
-static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
-        .panel  = {
-                .timing = {
-                        .left_margin    = 13,
-                        .right_margin   = 8,
-                        .upper_margin   = 7,
-                        .lower_margin   = 5,
-                        .hsync_len      = 3,
-                        .vsync_len      = 1,
-                        .xres           = 800,
-                        .yres           = 480,
-                },
-        },
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
-        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
-        .default_win    = 0,
-        .bpp            = 32,
-};
-#else
-static struct s3c_fb_pd_win smdkv310_fb_win0 = {
-        .max_bpp        = 32,
-        .default_bpp    = 24,
-        .xres           = 800,
-        .yres           = 480,
-};
-static struct fb_videomode smdkv310_lcd_timing = {
-        .left_margin    = 13,
-        .right_margin   = 8,
-        .upper_margin   = 7,
-        .lower_margin   = 5,
-        .hsync_len      = 3,
-        .vsync_len      = 1,
-        .xres           = 800,
-        .yres           = 480,
-};
-static struct s3c_fb_platdata smdkv310_lcd0_pdata __initdata = {
-        .win[0]         = &smdkv310_fb_win0,
-        .vtiming        = &smdkv310_lcd_timing,
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
-        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
-        .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
-};
-#endif
-static struct resource smdkv310_smsc911x_resources[] = {
-        [0] = DEFINE_RES_MEM(EXYNOS4_PA_SROM_BANK(1), SZ_64K),
-        [1] = DEFINE_RES_NAMED(IRQ_EINT(5), 1, NULL, IORESOURCE_IRQ \
-                                                | IRQF_TRIGGER_LOW),
-};
-static struct smsc911x_platform_config smsc9215_config = {
-        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
-        .flags          = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
-        .phy_interface  = PHY_INTERFACE_MODE_MII,
-        .mac            = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
-};
-static struct platform_device smdkv310_smsc911x = {
-        .name           = "smsc911x",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(smdkv310_smsc911x_resources),
-        .resource       = smdkv310_smsc911x_resources,
-        .dev            = {
-                .platform_data  = &smsc9215_config,
-        },
-};
-static uint32_t smdkv310_keymap[] __initdata = {
-        /* KEY(row, col, keycode) */
-        KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3),
-        KEY(0, 6, KEY_4), KEY(0, 7, KEY_5),
-        KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C),
-        KEY(1, 6, KEY_D), KEY(1, 7, KEY_E)
-};
-static struct matrix_keymap_data smdkv310_keymap_data __initdata = {
-        .keymap         = smdkv310_keymap,
-        .keymap_size    = ARRAY_SIZE(smdkv310_keymap),
-};
-static struct samsung_keypad_platdata smdkv310_keypad_data __initdata = {
-        .keymap_data    = &smdkv310_keymap_data,
-        .rows           = 2,
-        .cols           = 8,
-};
-static struct i2c_board_info i2c_devs1[] __initdata = {
-        {I2C_BOARD_INFO("wm8994", 0x1a),},
-};
-/* USB EHCI */
-static struct s5p_ehci_platdata smdkv310_ehci_pdata;
-static void __init smdkv310_ehci_init(void)
-{
-        struct s5p_ehci_platdata *pdata = &smdkv310_ehci_pdata;
-        s5p_ehci_set_platdata(pdata);
-}
-/* USB OHCI */
-static struct exynos4_ohci_platdata smdkv310_ohci_pdata;
-static void __init smdkv310_ohci_init(void)
-{
-        struct exynos4_ohci_platdata *pdata = &smdkv310_ohci_pdata;
-        exynos4_ohci_set_platdata(pdata);
-}
-/* USB OTG */
-static struct s3c_hsotg_plat smdkv310_hsotg_pdata;
-/* Audio device */
-static struct platform_device smdkv310_device_audio = {
-        .name = "smdk-audio",
-        .id = -1,
-};
-static struct platform_device *smdkv310_devices[] __initdata = {
-        &s3c_device_hsmmc0,
-        &s3c_device_hsmmc1,
-        &s3c_device_hsmmc2,
-        &s3c_device_hsmmc3,
-        &s3c_device_i2c1,
-        &s5p_device_i2c_hdmiphy,
-        &s3c_device_rtc,
-        &s3c_device_usb_hsotg,
-        &s3c_device_wdt,
-        &s5p_device_ehci,
-        &s5p_device_fimc0,
-        &s5p_device_fimc1,
-        &s5p_device_fimc2,
-        &s5p_device_fimc3,
-        &s5p_device_fimc_md,
-        &s5p_device_g2d,
-        &s5p_device_jpeg,
-        &exynos4_device_ac97,
-        &exynos4_device_i2s0,
-        &exynos4_device_ohci,
-        &samsung_device_keypad,
-        &s5p_device_mfc,
-        &s5p_device_mfc_l,
-        &s5p_device_mfc_r,
-        &exynos4_device_spdif,
-        &samsung_asoc_idma,
-        &s5p_device_fimd0,
-        &smdkv310_device_audio,
-        &smdkv310_lcd_lte480wv,
-        &smdkv310_smsc911x,
-        &exynos4_device_ahci,
-        &s5p_device_hdmi,
-        &s5p_device_mixer,
-};
-static void __init smdkv310_smsc911x_init(void)
-{
-        u32 cs1;
-        /* configure nCS1 width to 16 bits */
-        cs1 = __raw_readl(S5P_SROM_BW) &
-                ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
-        cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
-                (1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
-                (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
-                S5P_SROM_BW__NCS1__SHIFT;
-        __raw_writel(cs1, S5P_SROM_BW);
-        /* set timing for nCS1 suitable for ethernet chip */
-        __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
-                     (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
-                     (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
-                     (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
-                     (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
-                     (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
-                     (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
-}
-/* LCD Backlight data */
-static struct samsung_bl_gpio_info smdkv310_bl_gpio_info = {
-        .no = EXYNOS4_GPD0(1),
-        .func = S3C_GPIO_SFN(2),
-};
-static struct platform_pwm_backlight_data smdkv310_bl_data = {
-        .pwm_id = 1,
-        .pwm_period_ns  = 1000,
-};
-/* I2C module and id for HDMIPHY */
-static struct i2c_board_info hdmiphy_info = {
-        I2C_BOARD_INFO("hdmiphy-exynos4210", 0x38),
-};
-static struct pwm_lookup smdkv310_pwm_lookup[] = {
-        PWM_LOOKUP("s3c24xx-pwm.1", 0, "pwm-backlight.0", NULL),
-};
-static void s5p_tv_setup(void)
-{
-        /* direct HPD to HDMI chip */
-        WARN_ON(gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug"));
-        s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
-        s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
-}
-static void __init smdkv310_map_io(void)
-{
-        exynos_init_io(NULL, 0);
-        s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
-        xxti_f = 12000000;
-        xusbxti_f = 24000000;
-}
-static void __init smdkv310_reserve(void)
-{
-        s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
-}
-static void __init smdkv310_machine_init(void)
-{
-        s3c_i2c1_set_platdata(NULL);
-        i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
-        smdkv310_smsc911x_init();
-        s3c_sdhci0_set_platdata(&smdkv310_hsmmc0_pdata);
-        s3c_sdhci1_set_platdata(&smdkv310_hsmmc1_pdata);
-        s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata);
-        s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata);
-        s5p_tv_setup();
-        s5p_i2c_hdmiphy_set_platdata(NULL);
-        s5p_hdmi_set_platdata(&hdmiphy_info, NULL, 0);
-        samsung_keypad_set_platdata(&smdkv310_keypad_data);
-        samsung_bl_set(&smdkv310_bl_gpio_info, &smdkv310_bl_data);
-        pwm_add_table(smdkv310_pwm_lookup, ARRAY_SIZE(smdkv310_pwm_lookup));
-#ifdef CONFIG_DRM_EXYNOS_FIMD
-        s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
-        exynos4_fimd0_gpio_setup_24bpp();
-#else
-        s5p_fimd0_set_platdata(&smdkv310_lcd0_pdata);
-#endif
-        smdkv310_ehci_init();
-        smdkv310_ohci_init();
-        s3c_hsotg_set_platdata(&smdkv310_hsotg_pdata);
-        platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
-}
-MACHINE_START(SMDKV310, "SMDKV310")
-        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
-        /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
-        .atag_offset    = 0x100,
-        .smp            = smp_ops(exynos_smp_ops),
-        .init_irq       = exynos4_init_irq,
-        .map_io         = smdkv310_map_io,
-        .init_machine   = smdkv310_machine_init,
-        .init_time      = exynos_init_time,
-        .reserve        = &smdkv310_reserve,
-        .restart        = exynos4_restart,
-MACHINE_END
-MACHINE_START(SMDKC210, "SMDKC210")
-        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
-        .atag_offset    = 0x100,
-        .smp            = smp_ops(exynos_smp_ops),
-        .init_irq       = exynos4_init_irq,
-        .map_io         = smdkv310_map_io,
-        .init_machine   = smdkv310_machine_init,
-        .init_late      = exynos_init_late,
-        .init_time      = exynos_init_time,
-        .reserve        = &smdkv310_reserve,
-        .restart        = exynos4_restart,
-MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
deleted file mode 100644
index 74ddb2b55614..000000000000
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ /dev/null
@@ -1,1159 +0,0 @@
-/* linux/arch/arm/mach-exynos4/mach-universal_c210.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/platform_device.h>
-#include <linux/serial_core.h>
-#include <linux/input.h>
-#include <linux/i2c.h>
-#include <linux/gpio_keys.h>
-#include <linux/gpio.h>
-#include <linux/interrupt.h>
-#include <linux/fb.h>
-#include <linux/mfd/max8998.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/max8952.h>
-#include <linux/mmc/host.h>
-#include <linux/i2c-gpio.h>
-#include <linux/i2c/mcs.h>
-#include <linux/i2c/atmel_mxt_ts.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <linux/platform_data/mipi-csis.h>
-#include <linux/platform_data/s3c-hsotg.h>
-#include <drm/exynos_drm.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <video/samsung_fimd.h>
-#include <plat/regs-serial.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/gpio-cfg.h>
-#include <plat/fb.h>
-#include <plat/mfc.h>
-#include <plat/sdhci.h>
-#include <plat/fimc-core.h>
-#include <plat/camport.h>
-#include <mach/map.h>
-#include <media/v4l2-mediabus.h>
-#include <media/s5p_fimc.h>
-#include <media/m5mols.h>
-#include <media/s5k6aa.h>
-#include "common.h"
-/* Following are default values for UCON, ULCON and UFCON UART registers */
-#define UNIVERSAL_UCON_DEFAULT  (S3C2410_UCON_TXILEVEL |        \
-                                 S3C2410_UCON_RXILEVEL |        \
-                                 S3C2410_UCON_TXIRQMODE |       \
-                                 S3C2410_UCON_RXIRQMODE |       \
-                                 S3C2410_UCON_RXFIFO_TOI |      \
-                                 S3C2443_UCON_RXERR_IRQEN)
-#define UNIVERSAL_ULCON_DEFAULT S3C2410_LCON_CS8
-#define UNIVERSAL_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE |       \
-                                 S5PV210_UFCON_TXTRIG256 |      \
-                                 S5PV210_UFCON_RXTRIG256)
-static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = {
-        [0] = {
-                .hwport         = 0,
-                .ucon           = UNIVERSAL_UCON_DEFAULT,
-                .ulcon          = UNIVERSAL_ULCON_DEFAULT,
-                .ufcon          = UNIVERSAL_UFCON_DEFAULT,
-        },
-        [1] = {
-                .hwport         = 1,
-                .ucon           = UNIVERSAL_UCON_DEFAULT,
-                .ulcon          = UNIVERSAL_ULCON_DEFAULT,
-                .ufcon          = UNIVERSAL_UFCON_DEFAULT,
-        },
-        [2] = {
-                .hwport         = 2,
-                .ucon           = UNIVERSAL_UCON_DEFAULT,
-                .ulcon          = UNIVERSAL_ULCON_DEFAULT,
-                .ufcon          = UNIVERSAL_UFCON_DEFAULT,
-        },
-        [3] = {
-                .hwport         = 3,
-                .ucon           = UNIVERSAL_UCON_DEFAULT,
-                .ulcon          = UNIVERSAL_ULCON_DEFAULT,
-                .ufcon          = UNIVERSAL_UFCON_DEFAULT,
-        },
-};
-static struct regulator_consumer_supply max8952_consumer =
-        REGULATOR_SUPPLY("vdd_arm", NULL);
-static struct regulator_init_data universal_max8952_reg_data = {
-        .constraints    = {
-                .name           = "VARM_1.2V",
-                .min_uV         = 770000,
-                .max_uV         = 1400000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                .always_on      = 1,
-                .boot_on        = 1,
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &max8952_consumer,
-};
-static struct max8952_platform_data universal_max8952_pdata __initdata = {
-        .gpio_vid0      = EXYNOS4_GPX0(3),
-        .gpio_vid1      = EXYNOS4_GPX0(4),
-        .gpio_en        = -1, /* Not controllable, set "Always High" */
-        .default_mode   = 0, /* vid0 = 0, vid1 = 0 */
-        .dvs_mode       = { 48, 32, 28, 18 }, /* 1.25, 1.20, 1.05, 0.95V */
-        .sync_freq      = 0, /* default: fastest */
-        .ramp_speed     = 0, /* default: fastest */
-        .reg_data       = &universal_max8952_reg_data,
-};
-static struct regulator_consumer_supply lp3974_buck1_consumer =
-        REGULATOR_SUPPLY("vdd_int", NULL);
-static struct regulator_consumer_supply lp3974_buck2_consumer =
-        REGULATOR_SUPPLY("vddg3d", NULL);
-static struct regulator_consumer_supply lp3974_buck3_consumer[] = {
-        REGULATOR_SUPPLY("vdet", "s5p-sdo"),
-        REGULATOR_SUPPLY("vdd_reg", "0-003c"),
-};
-static struct regulator_init_data lp3974_buck1_data = {
-        .constraints    = {
-                .name           = "VINT_1.1V",
-                .min_uV         = 750000,
-                .max_uV         = 1500000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
-                        REGULATOR_CHANGE_STATUS,
-                .boot_on        = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies = 1,
-        .consumer_supplies = &lp3974_buck1_consumer,
-};
-static struct regulator_init_data lp3974_buck2_data = {
-        .constraints    = {
-                .name           = "VG3D_1.1V",
-                .min_uV         = 750000,
-                .max_uV         = 1500000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
-                        REGULATOR_CHANGE_STATUS,
-                .boot_on        = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies = 1,
-        .consumer_supplies = &lp3974_buck2_consumer,
-};
-static struct regulator_init_data lp3974_buck3_data = {
-        .constraints    = {
-                .name           = "VCC_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-        .num_consumer_supplies = ARRAY_SIZE(lp3974_buck3_consumer),
-        .consumer_supplies = lp3974_buck3_consumer,
-};
-static struct regulator_init_data lp3974_buck4_data = {
-        .constraints    = {
-                .name           = "VMEM_1.2V",
-                .min_uV         = 1200000,
-                .max_uV         = 1200000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-static struct regulator_init_data lp3974_ldo2_data = {
-        .constraints    = {
-                .name           = "VALIVE_1.2V",
-                .min_uV         = 1200000,
-                .max_uV         = 1200000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-};
-static struct regulator_consumer_supply lp3974_ldo3_consumer[] = {
-        REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"),
-        REGULATOR_SUPPLY("vdd", "exynos4-hdmi"),
-        REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"),
-        REGULATOR_SUPPLY("vddcore", "s5p-mipi-csis.0"),
-};
-static struct regulator_init_data lp3974_ldo3_data = {
-        .constraints    = {
-                .name           = "VUSB+MIPI_1.1V",
-                .min_uV         = 1100000,
-                .max_uV         = 1100000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo3_consumer),
-        .consumer_supplies = lp3974_ldo3_consumer,
-};
-static struct regulator_consumer_supply lp3974_ldo4_consumer[] = {
-        REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"),
-};
-static struct regulator_init_data lp3974_ldo4_data = {
-        .constraints    = {
-                .name           = "VADC_3.3V",
-                .min_uV         = 3300000,
-                .max_uV         = 3300000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo4_consumer),
-        .consumer_supplies = lp3974_ldo4_consumer,
-};
-static struct regulator_init_data lp3974_ldo5_data = {
-        .constraints    = {
-                .name           = "VTF_2.8V",
-                .min_uV         = 2800000,
-                .max_uV         = 2800000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-static struct regulator_init_data lp3974_ldo6_data = {
-        .constraints    = {
-                .name           = "LDO6",
-                .min_uV         = 2000000,
-                .max_uV         = 2000000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-static struct regulator_consumer_supply lp3974_ldo7_consumer[] = {
-        REGULATOR_SUPPLY("vddio", "s5p-mipi-csis.0"),
-};
-static struct regulator_init_data lp3974_ldo7_data = {
-        .constraints    = {
-                .name           = "VLCD+VMIPI_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(lp3974_ldo7_consumer),
-        .consumer_supplies      = lp3974_ldo7_consumer,
-};
-static struct regulator_consumer_supply lp3974_ldo8_consumer[] = {
-        REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"),
-        REGULATOR_SUPPLY("vdd33a_dac", "s5p-sdo"),
-};
-static struct regulator_init_data lp3974_ldo8_data = {
-        .constraints    = {
-                .name           = "VUSB+VDAC_3.3V",
-                .min_uV         = 3300000,
-                .max_uV         = 3300000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo8_consumer),
-        .consumer_supplies = lp3974_ldo8_consumer,
-};
-static struct regulator_consumer_supply lp3974_ldo9_consumer =
-        REGULATOR_SUPPLY("vddio", "0-003c");
-static struct regulator_init_data lp3974_ldo9_data = {
-        .constraints    = {
-                .name           = "VCC_2.8V",
-                .min_uV         = 2800000,
-                .max_uV         = 2800000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &lp3974_ldo9_consumer,
-};
-static struct regulator_init_data lp3974_ldo10_data = {
-        .constraints    = {
-                .name           = "VPLL_1.1V",
-                .min_uV         = 1100000,
-                .max_uV         = 1100000,
-                .boot_on        = 1,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-static struct regulator_consumer_supply lp3974_ldo11_consumer =
-        REGULATOR_SUPPLY("dig_28", "0-001f");
-static struct regulator_init_data lp3974_ldo11_data = {
-        .constraints    = {
-                .name           = "CAM_AF_3.3V",
-                .min_uV         = 3300000,
-                .max_uV         = 3300000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &lp3974_ldo11_consumer,
-};
-static struct regulator_init_data lp3974_ldo12_data = {
-        .constraints    = {
-                .name           = "PS_2.8V",
-                .min_uV         = 2800000,
-                .max_uV         = 2800000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-static struct regulator_init_data lp3974_ldo13_data = {
-        .constraints    = {
-                .name           = "VHIC_1.2V",
-                .min_uV         = 1200000,
-                .max_uV         = 1200000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-static struct regulator_consumer_supply lp3974_ldo14_consumer =
-        REGULATOR_SUPPLY("dig_18", "0-001f");
-static struct regulator_init_data lp3974_ldo14_data = {
-        .constraints    = {
-                .name           = "CAM_I_HOST_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &lp3974_ldo14_consumer,
-};
-static struct regulator_consumer_supply lp3974_ldo15_consumer =
-        REGULATOR_SUPPLY("dig_12", "0-001f");
-static struct regulator_init_data lp3974_ldo15_data = {
-        .constraints    = {
-                .name           = "CAM_S_DIG+FM33_CORE_1.2V",
-                .min_uV         = 1200000,
-                .max_uV         = 1200000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &lp3974_ldo15_consumer,
-};
-static struct regulator_consumer_supply lp3974_ldo16_consumer[] = {
-        REGULATOR_SUPPLY("vdda", "0-003c"),
-        REGULATOR_SUPPLY("a_sensor", "0-001f"),
-};
-static struct regulator_init_data lp3974_ldo16_data = {
-        .constraints    = {
-                .name           = "CAM_S_ANA_2.8V",
-                .min_uV         = 2800000,
-                .max_uV         = 2800000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(lp3974_ldo16_consumer),
-        .consumer_supplies      = lp3974_ldo16_consumer,
-};
-static struct regulator_init_data lp3974_ldo17_data = {
-        .constraints    = {
-                .name           = "VCC_3.0V_LCD",
-                .min_uV         = 3000000,
-                .max_uV         = 3000000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .boot_on        = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-static struct regulator_init_data lp3974_32khz_ap_data = {
-        .constraints    = {
-                .name           = "32KHz AP",
-                .always_on      = 1,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-};
-static struct regulator_init_data lp3974_32khz_cp_data = {
-        .constraints    = {
-                .name           = "32KHz CP",
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-static struct regulator_init_data lp3974_vichg_data = {
-        .constraints    = {
-                .name           = "VICHG",
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-static struct regulator_init_data lp3974_esafeout1_data = {
-        .constraints    = {
-                .name           = "SAFEOUT1",
-                .min_uV         = 4800000,
-                .max_uV         = 4800000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .always_on      = 1,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-};
-static struct regulator_init_data lp3974_esafeout2_data = {
-        .constraints    = {
-                .name           = "SAFEOUT2",
-                .boot_on        = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-};
-static struct max8998_regulator_data lp3974_regulators[] = {
-        { MAX8998_LDO2,  &lp3974_ldo2_data },
-        { MAX8998_LDO3,  &lp3974_ldo3_data },
-        { MAX8998_LDO4,  &lp3974_ldo4_data },
-        { MAX8998_LDO5,  &lp3974_ldo5_data },
-        { MAX8998_LDO6,  &lp3974_ldo6_data },
-        { MAX8998_LDO7,  &lp3974_ldo7_data },
-        { MAX8998_LDO8,  &lp3974_ldo8_data },
-        { MAX8998_LDO9,  &lp3974_ldo9_data },
-        { MAX8998_LDO10, &lp3974_ldo10_data },
-        { MAX8998_LDO11, &lp3974_ldo11_data },
-        { MAX8998_LDO12, &lp3974_ldo12_data },
-        { MAX8998_LDO13, &lp3974_ldo13_data },
-        { MAX8998_LDO14, &lp3974_ldo14_data },
-        { MAX8998_LDO15, &lp3974_ldo15_data },
-        { MAX8998_LDO16, &lp3974_ldo16_data },
-        { MAX8998_LDO17, &lp3974_ldo17_data },
-        { MAX8998_BUCK1, &lp3974_buck1_data },
-        { MAX8998_BUCK2, &lp3974_buck2_data },
-        { MAX8998_BUCK3, &lp3974_buck3_data },
-        { MAX8998_BUCK4, &lp3974_buck4_data },
-        { MAX8998_EN32KHZ_AP, &lp3974_32khz_ap_data },
-        { MAX8998_EN32KHZ_CP, &lp3974_32khz_cp_data },
-        { MAX8998_ENVICHG, &lp3974_vichg_data },
-        { MAX8998_ESAFEOUT1, &lp3974_esafeout1_data },
-        { MAX8998_ESAFEOUT2, &lp3974_esafeout2_data },
-};
-static struct max8998_platform_data universal_lp3974_pdata = {
-        .num_regulators         = ARRAY_SIZE(lp3974_regulators),
-        .regulators             = lp3974_regulators,
-        .buck1_voltage1         = 1100000,      /* INT */
-        .buck1_voltage2         = 1000000,
-        .buck1_voltage3         = 1100000,
-        .buck1_voltage4         = 1000000,
-        .buck1_set1             = EXYNOS4_GPX0(5),
-        .buck1_set2             = EXYNOS4_GPX0(6),
-        .buck2_voltage1         = 1200000,      /* G3D */
-        .buck2_voltage2         = 1100000,
-        .buck1_default_idx      = 0,
-        .buck2_set3             = EXYNOS4_GPE2(0),
-        .buck2_default_idx      = 0,
-        .wakeup                 = true,
-};
-enum fixed_regulator_id {
-        FIXED_REG_ID_MMC0,
-        FIXED_REG_ID_HDMI_5V,
-        FIXED_REG_ID_CAM_S_IF,
-        FIXED_REG_ID_CAM_I_CORE,
-        FIXED_REG_ID_CAM_VT_DIO,
-};
-static struct regulator_consumer_supply hdmi_fixed_consumer =
-        REGULATOR_SUPPLY("hdmi-en", "exynos4-hdmi");
-static struct regulator_init_data hdmi_fixed_voltage_init_data = {
-        .constraints            = {
-                .name           = "HDMI_5V",
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &hdmi_fixed_consumer,
-};
-static struct fixed_voltage_config hdmi_fixed_voltage_config = {
-        .supply_name            = "HDMI_EN1",
-        .microvolts             = 5000000,
-        .gpio                   = EXYNOS4_GPE0(1),
-        .enable_high            = true,
-        .init_data              = &hdmi_fixed_voltage_init_data,
-};
-static struct platform_device hdmi_fixed_voltage = {
-        .name                   = "reg-fixed-voltage",
-        .id                     = FIXED_REG_ID_HDMI_5V,
-        .dev                    = {
-                .platform_data  = &hdmi_fixed_voltage_config,
-        },
-};
-/* GPIO I2C 5 (PMIC) */
-static struct i2c_board_info i2c5_devs[] __initdata = {
-        {
-                I2C_BOARD_INFO("max8952", 0xC0 >> 1),
-                .platform_data  = &universal_max8952_pdata,
-        }, {
-                I2C_BOARD_INFO("lp3974", 0xCC >> 1),
-                .platform_data  = &universal_lp3974_pdata,
-        },
-};
-/* I2C3 (TSP) */
-static struct mxt_platform_data qt602240_platform_data = {
-        .x_line         = 19,
-        .y_line         = 11,
-        .x_size         = 800,
-        .y_size         = 480,
-        .blen           = 0x11,
-        .threshold      = 0x28,
-        .voltage        = 2800000,              /* 2.8V */
-        .orient         = MXT_DIAGONAL,
-        .irqflags       = IRQF_TRIGGER_FALLING,
-};
-static struct i2c_board_info i2c3_devs[] __initdata = {
-        {
-                I2C_BOARD_INFO("qt602240_ts", 0x4a),
-                .platform_data = &qt602240_platform_data,
-        },
-};
-static void __init universal_tsp_init(void)
-{
-        int gpio;
-        /* TSP_LDO_ON: XMDMADDR_11 */
-        gpio = EXYNOS4_GPE2(3);
-        gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "TSP_LDO_ON");
-        gpio_export(gpio, 0);
-        /* TSP_INT: XMDMADDR_7 */
-        gpio = EXYNOS4_GPE1(7);
-        gpio_request(gpio, "TSP_INT");
-        s5p_register_gpio_interrupt(gpio);
-        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
-        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
-        i2c3_devs[0].irq = gpio_to_irq(gpio);
-}
-/* GPIO I2C 12 (3 Touchkey) */
-static uint32_t touchkey_keymap[] = {
-        /* MCS_KEY_MAP(value, keycode) */
-        MCS_KEY_MAP(0, KEY_MENU),               /* KEY_SEND */
-        MCS_KEY_MAP(1, KEY_BACK),               /* KEY_END */
-};
-static struct mcs_platform_data touchkey_data = {
-        .keymap         = touchkey_keymap,
-        .keymap_size    = ARRAY_SIZE(touchkey_keymap),
-        .key_maxval     = 2,
-};
-/* GPIO I2C 3_TOUCH 2.8V */
-#define I2C_GPIO_BUS_12         12
-static struct i2c_gpio_platform_data i2c_gpio12_data = {
-        .sda_pin        = EXYNOS4_GPE4(0),      /* XMDMDATA_8 */
-        .scl_pin        = EXYNOS4_GPE4(1),      /* XMDMDATA_9 */
-};
-static struct platform_device i2c_gpio12 = {
-        .name           = "i2c-gpio",
-        .id             = I2C_GPIO_BUS_12,
-        .dev            = {
-                .platform_data  = &i2c_gpio12_data,
-        },
-};
-static struct i2c_board_info i2c_gpio12_devs[] __initdata = {
-        {
-                I2C_BOARD_INFO("mcs5080_touchkey", 0x20),
-                .platform_data = &touchkey_data,
-        },
-};
-static void __init universal_touchkey_init(void)
-{
-        int gpio;
-        gpio = EXYNOS4_GPE3(7);                 /* XMDMDATA_7 */
-        gpio_request(gpio, "3_TOUCH_INT");
-        s5p_register_gpio_interrupt(gpio);
-        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
-        i2c_gpio12_devs[0].irq = gpio_to_irq(gpio);
-        gpio = EXYNOS4_GPE3(3);                 /* XMDMDATA_3 */
-        gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "3_TOUCH_EN");
-}
-static struct s3c2410_platform_i2c universal_i2c0_platdata __initdata = {
-        .frequency      = 300 * 1000,
-        .sda_delay      = 200,
-};
-/* GPIO KEYS */
-static struct gpio_keys_button universal_gpio_keys_tables[] = {
-        {
-                .code                   = KEY_VOLUMEUP,
-                .gpio                   = EXYNOS4_GPX2(0),      /* XEINT16 */
-                .desc                   = "gpio-keys: KEY_VOLUMEUP",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .debounce_interval      = 1,
-        }, {
-                .code                   = KEY_VOLUMEDOWN,
-                .gpio                   = EXYNOS4_GPX2(1),      /* XEINT17 */
-                .desc                   = "gpio-keys: KEY_VOLUMEDOWN",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .debounce_interval      = 1,
-        }, {
-                .code                   = KEY_CONFIG,
-                .gpio                   = EXYNOS4_GPX2(2),      /* XEINT18 */
-                .desc                   = "gpio-keys: KEY_CONFIG",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .debounce_interval      = 1,
-        }, {
-                .code                   = KEY_CAMERA,
-                .gpio                   = EXYNOS4_GPX2(3),      /* XEINT19 */
-                .desc                   = "gpio-keys: KEY_CAMERA",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .debounce_interval      = 1,
-        }, {
-                .code                   = KEY_OK,
-                .gpio                   = EXYNOS4_GPX3(5),      /* XEINT29 */
-                .desc                   = "gpio-keys: KEY_OK",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .debounce_interval      = 1,
-        },
-};
-static struct gpio_keys_platform_data universal_gpio_keys_data = {
-        .buttons        = universal_gpio_keys_tables,
-        .nbuttons       = ARRAY_SIZE(universal_gpio_keys_tables),
-};
-static struct platform_device universal_gpio_keys = {
-        .name                   = "gpio-keys",
-        .dev                    = {
-                .platform_data  = &universal_gpio_keys_data,
-        },
-};
-/* eMMC */
-static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
-        .max_width              = 8,
-        .host_caps              = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
-                                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-        .cd_type                = S3C_SDHCI_CD_PERMANENT,
-};
-static struct regulator_consumer_supply mmc0_supplies[] = {
-        REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.0"),
-};
-static struct regulator_init_data mmc0_fixed_voltage_init_data = {
-        .constraints            = {
-                .name           = "VMEM_VDD_2.8V",
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(mmc0_supplies),
-        .consumer_supplies      = mmc0_supplies,
-};
-static struct fixed_voltage_config mmc0_fixed_voltage_config = {
-        .supply_name            = "MASSMEMORY_EN",
-        .microvolts             = 2800000,
-        .gpio                   = EXYNOS4_GPE1(3),
-        .enable_high            = true,
-        .init_data              = &mmc0_fixed_voltage_init_data,
-};
-static struct platform_device mmc0_fixed_voltage = {
-        .name                   = "reg-fixed-voltage",
-        .id                     = FIXED_REG_ID_MMC0,
-        .dev                    = {
-                .platform_data  = &mmc0_fixed_voltage_config,
-        },
-};
-/* SD */
-static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {
-        .max_width              = 4,
-        .host_caps              = MMC_CAP_4_BIT_DATA |
-                                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-        .ext_cd_gpio            = EXYNOS4_GPX3(4),      /* XEINT_28 */
-        .ext_cd_gpio_invert     = 1,
-        .cd_type                = S3C_SDHCI_CD_GPIO,
-};
-/* WiFi */
-static struct s3c_sdhci_platdata universal_hsmmc3_data __initdata = {
-        .max_width              = 4,
-        .host_caps              = MMC_CAP_4_BIT_DATA |
-                                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-        .cd_type                = S3C_SDHCI_CD_EXTERNAL,
-};
-static void __init universal_sdhci_init(void)
-{
-        s3c_sdhci0_set_platdata(&universal_hsmmc0_data);
-        s3c_sdhci2_set_platdata(&universal_hsmmc2_data);
-        s3c_sdhci3_set_platdata(&universal_hsmmc3_data);
-}
-/* I2C1 */
-static struct i2c_board_info i2c1_devs[] __initdata = {
-        /* Gyro, To be updated */
-};
-#ifdef CONFIG_DRM_EXYNOS
-static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
-        .panel = {
-                .timing = {
-                        .left_margin    = 16,
-                        .right_margin   = 16,
-                        .upper_margin   = 2,
-                        .lower_margin   = 28,
-                        .hsync_len      = 2,
-                        .vsync_len      = 1,
-                        .xres           = 480,
-                        .yres           = 800,
-                        .refresh        = 55,
-                },
-        },
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
-                          VIDCON0_CLKSEL_LCD,
-        .vidcon1        = VIDCON1_INV_VCLK | VIDCON1_INV_VDEN
-                          | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
-        .default_win    = 3,
-        .bpp            = 32,
-};
-#else
-/* Frame Buffer */
-static struct s3c_fb_pd_win universal_fb_win0 = {
-        .max_bpp        = 32,
-        .default_bpp    = 16,
-        .xres           = 480,
-        .yres           = 800,
-        .virtual_x      = 480,
-        .virtual_y      = 2 * 800,
-};
-static struct fb_videomode universal_lcd_timing = {
-        .left_margin    = 16,
-        .right_margin   = 16,
-        .upper_margin   = 2,
-        .lower_margin   = 28,
-        .hsync_len      = 2,
-        .vsync_len      = 1,
-        .xres           = 480,
-        .yres           = 800,
-        .refresh        = 55,
-};
-static struct s3c_fb_platdata universal_lcd_pdata __initdata = {
-        .win[0]         = &universal_fb_win0,
-        .vtiming        = &universal_lcd_timing,
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
-                          VIDCON0_CLKSEL_LCD,
-        .vidcon1        = VIDCON1_INV_VCLK | VIDCON1_INV_VDEN
-                          | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
-        .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
-};
-#endif
-static struct regulator_consumer_supply cam_vt_dio_supply =
-        REGULATOR_SUPPLY("vdd_core", "0-003c");
-static struct regulator_init_data cam_vt_dio_reg_init_data = {
-        .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
-        .num_consumer_supplies = 1,
-        .consumer_supplies = &cam_vt_dio_supply,
-};
-static struct fixed_voltage_config cam_vt_dio_fixed_voltage_cfg = {
-        .supply_name    = "CAM_VT_D_IO",
-        .microvolts     = 2800000,
-        .gpio           = EXYNOS4_GPE2(1), /* CAM_PWR_EN2 */
-        .enable_high    = 1,
-        .init_data      = &cam_vt_dio_reg_init_data,
-};
-static struct platform_device cam_vt_dio_fixed_reg_dev = {
-        .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_VT_DIO,
-        .dev = { .platform_data = &cam_vt_dio_fixed_voltage_cfg },
-};
-static struct regulator_consumer_supply cam_i_core_supply =
-        REGULATOR_SUPPLY("core", "0-001f");
-static struct regulator_init_data cam_i_core_reg_init_data = {
-        .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
-        .num_consumer_supplies = 1,
-        .consumer_supplies = &cam_i_core_supply,
-};
-static struct fixed_voltage_config cam_i_core_fixed_voltage_cfg = {
-        .supply_name    = "CAM_I_CORE_1.2V",
-        .microvolts     = 1200000,
-        .gpio           = EXYNOS4_GPE2(2),      /* CAM_8M_CORE_EN */
-        .enable_high    = 1,
-        .init_data      = &cam_i_core_reg_init_data,
-};
-static struct platform_device cam_i_core_fixed_reg_dev = {
-        .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_I_CORE,
-        .dev = { .platform_data = &cam_i_core_fixed_voltage_cfg },
-};
-static struct regulator_consumer_supply cam_s_if_supply =
-        REGULATOR_SUPPLY("d_sensor", "0-001f");
-static struct regulator_init_data cam_s_if_reg_init_data = {
-        .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
-        .num_consumer_supplies = 1,
-        .consumer_supplies = &cam_s_if_supply,
-};
-static struct fixed_voltage_config cam_s_if_fixed_voltage_cfg = {
-        .supply_name    = "CAM_S_IF_1.8V",
-        .microvolts     = 1800000,
-        .gpio           = EXYNOS4_GPE3(0),      /* CAM_PWR_EN1 */
-        .enable_high    = 1,
-        .init_data      = &cam_s_if_reg_init_data,
-};
-static struct platform_device cam_s_if_fixed_reg_dev = {
-        .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_S_IF,
-        .dev = { .platform_data = &cam_s_if_fixed_voltage_cfg },
-};
-static struct s5p_platform_mipi_csis mipi_csis_platdata = {
-        .clk_rate       = 166000000UL,
-        .lanes          = 2,
-        .hs_settle      = 12,
-};
-#define GPIO_CAM_LEVEL_EN(n)    EXYNOS4_GPE4(n + 3)
-#define GPIO_CAM_8M_ISP_INT     EXYNOS4_GPX1(5) /* XEINT_13 */
-#define GPIO_CAM_MEGA_nRST      EXYNOS4_GPE2(5)
-#define GPIO_CAM_VGA_NRST       EXYNOS4_GPE4(7)
-#define GPIO_CAM_VGA_NSTBY      EXYNOS4_GPE4(6)
-static int s5k6aa_set_power(int on)
-{
-        gpio_set_value(GPIO_CAM_LEVEL_EN(2), !!on);
-        return 0;
-}
-static struct s5k6aa_platform_data s5k6aa_platdata = {
-        .mclk_frequency = 21600000UL,
-        .gpio_reset     = { GPIO_CAM_VGA_NRST, 0 },
-        .gpio_stby      = { GPIO_CAM_VGA_NSTBY, 0 },
-        .bus_type       = V4L2_MBUS_PARALLEL,
-        .horiz_flip     = 1,
-        .set_power      = s5k6aa_set_power,
-};
-static struct i2c_board_info s5k6aa_board_info = {
-        I2C_BOARD_INFO("S5K6AA", 0x3C),
-        .platform_data = &s5k6aa_platdata,
-};
-static int m5mols_set_power(struct device *dev, int on)
-{
-        gpio_set_value(GPIO_CAM_LEVEL_EN(1), !on);
-        gpio_set_value(GPIO_CAM_LEVEL_EN(2), !!on);
-        return 0;
-}
-static struct m5mols_platform_data m5mols_platdata = {
-        .gpio_reset     = GPIO_CAM_MEGA_nRST,
-        .reset_polarity = 0,
-        .set_power      = m5mols_set_power,
-};
-static struct i2c_board_info m5mols_board_info = {
-        I2C_BOARD_INFO("M5MOLS", 0x1F),
-        .platform_data = &m5mols_platdata,
-};
-static struct fimc_source_info universal_camera_sensors[] = {
-        {
-                .mux_id         = 0,
-                .flags          = V4L2_MBUS_PCLK_SAMPLE_FALLING |
-                                  V4L2_MBUS_VSYNC_ACTIVE_LOW,
-                .fimc_bus_type  = FIMC_BUS_TYPE_ITU_601,
-                .board_info     = &s5k6aa_board_info,
-                .i2c_bus_num    = 0,
-                .clk_frequency  = 24000000UL,
-        }, {
-                .mux_id         = 0,
-                .flags          = V4L2_MBUS_PCLK_SAMPLE_FALLING |
-                                  V4L2_MBUS_VSYNC_ACTIVE_LOW,
-                .fimc_bus_type  = FIMC_BUS_TYPE_MIPI_CSI2,
-                .board_info     = &m5mols_board_info,
-                .i2c_bus_num    = 0,
-                .clk_frequency  = 24000000UL,
-        },
-};
-static struct s5p_platform_fimc fimc_md_platdata = {
-        .source_info    = universal_camera_sensors,
-        .num_clients    = ARRAY_SIZE(universal_camera_sensors),
-};
-static struct gpio universal_camera_gpios[] = {
-        { GPIO_CAM_LEVEL_EN(1), GPIOF_OUT_INIT_HIGH, "CAM_LVL_EN1" },
-        { GPIO_CAM_LEVEL_EN(2), GPIOF_OUT_INIT_LOW,  "CAM_LVL_EN2" },
-        { GPIO_CAM_8M_ISP_INT,  GPIOF_IN,            "8M_ISP_INT"  },
-        { GPIO_CAM_MEGA_nRST,   GPIOF_OUT_INIT_LOW,  "CAM_8M_NRST" },
-        { GPIO_CAM_VGA_NRST,    GPIOF_OUT_INIT_LOW,  "CAM_VGA_NRST"  },
-        { GPIO_CAM_VGA_NSTBY,   GPIOF_OUT_INIT_LOW,  "CAM_VGA_NSTBY" },
-};
-/* USB OTG */
-static struct s3c_hsotg_plat universal_hsotg_pdata;
-static void __init universal_camera_init(void)
-{
-        s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata),
-                         &s5p_device_mipi_csis0);
-        s3c_set_platdata(&fimc_md_platdata,  sizeof(fimc_md_platdata),
-                         &s5p_device_fimc_md);
-        if (gpio_request_array(universal_camera_gpios,
-                               ARRAY_SIZE(universal_camera_gpios))) {
-                pr_err("%s: GPIO request failed\n", __func__);
-                return;
-        }
-        if (!s3c_gpio_cfgpin(GPIO_CAM_8M_ISP_INT, S3C_GPIO_SFN(0xf)))
-                m5mols_board_info.irq = gpio_to_irq(GPIO_CAM_8M_ISP_INT);
-        else
-                pr_err("Failed to configure 8M_ISP_INT GPIO\n");
-        /* Free GPIOs controlled directly by the sensor drivers. */
-        gpio_free(GPIO_CAM_MEGA_nRST);
-        gpio_free(GPIO_CAM_8M_ISP_INT);
-        gpio_free(GPIO_CAM_VGA_NRST);
-        gpio_free(GPIO_CAM_VGA_NSTBY);
-        if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A))
-                pr_err("Camera port A setup failed\n");
-}
-static struct platform_device *universal_devices[] __initdata = {
-        /* Samsung Platform Devices */
-        &s5p_device_mipi_csis0,
-        &s5p_device_fimc0,
-        &s5p_device_fimc1,
-        &s5p_device_fimc2,
-        &s5p_device_fimc3,
-        &s5p_device_g2d,
-        &mmc0_fixed_voltage,
-        &s3c_device_hsmmc0,
-        &s3c_device_hsmmc2,
-        &s3c_device_hsmmc3,
-        &s3c_device_i2c0,
-        &s3c_device_i2c3,
-        &s3c_device_i2c5,
-        &s5p_device_i2c_hdmiphy,
-        &hdmi_fixed_voltage,
-        &s5p_device_hdmi,
-        &s5p_device_sdo,
-        &s5p_device_mixer,
-        /* Universal Devices */
-        &i2c_gpio12,
-        &universal_gpio_keys,
-        &s5p_device_onenand,
-        &s5p_device_fimd0,
-        &s5p_device_jpeg,
-        &s3c_device_usb_hsotg,
-        &s5p_device_mfc,
-        &s5p_device_mfc_l,
-        &s5p_device_mfc_r,
-        &cam_vt_dio_fixed_reg_dev,
-        &cam_i_core_fixed_reg_dev,
-        &cam_s_if_fixed_reg_dev,
-        &s5p_device_fimc_md,
-};
-static void __init universal_map_io(void)
-{
-        exynos_init_io(NULL, 0);
-        s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
-        exynos_set_timer_source(BIT(2) | BIT(4));
-        xxti_f = 0;
-        xusbxti_f = 24000000;
-}
-static void s5p_tv_setup(void)
-{
-        /* direct HPD to HDMI chip */
-        gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug");
-        s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
-        s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
-}
-static void __init universal_reserve(void)
-{
-        s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
-}
-static void __init universal_machine_init(void)
-{
-        universal_sdhci_init();
-        s5p_tv_setup();
-        s3c_i2c0_set_platdata(&universal_i2c0_platdata);
-        i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
-        universal_tsp_init();
-        s3c_i2c3_set_platdata(NULL);
-        i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
-        s3c_i2c5_set_platdata(NULL);
-        s5p_i2c_hdmiphy_set_platdata(NULL);
-        i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
-#ifdef CONFIG_DRM_EXYNOS
-        s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
-        exynos4_fimd0_gpio_setup_24bpp();
-#else
-        s5p_fimd0_set_platdata(&universal_lcd_pdata);
-#endif
-        universal_touchkey_init();
-        i2c_register_board_info(I2C_GPIO_BUS_12, i2c_gpio12_devs,
-                        ARRAY_SIZE(i2c_gpio12_devs));
-        s3c_hsotg_set_platdata(&universal_hsotg_pdata);
-        universal_camera_init();
-        /* Last */
-        platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
-}
-MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
-        /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
-        .atag_offset    = 0x100,
-        .smp            = smp_ops(exynos_smp_ops),
-        .init_irq       = exynos4_init_irq,
-        .map_io         = universal_map_io,
-        .init_machine   = universal_machine_init,
-        .init_late      = exynos_init_late,
-        .init_time      = exynos_init_time,
-        .reserve        = &universal_reserve,
-        .restart        = exynos4_restart,
-MACHINE_END
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index a0e8ff7758a4..58b43e6f9262 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -50,6 +50,8 @@ static inline void __iomem *cpu_boot_reg(int cpu)
        boot_reg = cpu_boot_reg_base();
        if (soc_is_exynos4412())
                boot_reg += 4*cpu;
+        else if (soc_is_exynos5420())
+                boot_reg += 4;
        return boot_reg;
 }
@@ -73,7 +75,7 @@ static void __iomem *scu_base_addr(void)
 static DEFINE_SPINLOCK(boot_lock);
-static void __cpuinit exynos_secondary_init(unsigned int cpu)
+static void exynos_secondary_init(unsigned int cpu)
 {
        /*
         * let the primary processor know we're out of the
@@ -88,7 +90,7 @@ static void __cpuinit exynos_secondary_init(unsigned int cpu)
        spin_unlock(&boot_lock);
 }
-static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
        unsigned long timeout;
        unsigned long phys_cpu = cpu_logical_map(cpu);
@@ -180,10 +182,14 @@ static void __init exynos_smp_init_cpus(void)
        void __iomem *scu_base = scu_base_addr();
        unsigned int i, ncores;
-        if (soc_is_exynos5250())
+        if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
-                ncores = 2;
-        else
                ncores = scu_base ? scu_get_core_count(scu_base) : 1;
+        else
+                /*
+                 * CPU Nodes are passed thru DT and set_cpu_possible
+                 * is set by "arm_dt_init_cpu_maps".
+                 */
+                return;
        /* sanity check */
        if (ncores > nr_cpu_ids) {
@@ -200,7 +206,7 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
 {
        int i;
-        if (!(soc_is_exynos5250() || soc_is_exynos5440()))
+        if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
                scu_enable(scu_base_addr());
        /*
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index e3faaa812016..c679db577269 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -30,7 +30,6 @@
 #include <plat/regs-srom.h>
 #include <mach/regs-irq.h>
-#include <mach/regs-gpio.h>
 #include <mach/regs-clock.h>
 #include <mach/regs-pmu.h>
 #include <mach/pm-core.h>
@@ -218,6 +217,9 @@ static __init int exynos_pm_drvinit(void)
        struct clk *pll_base;
        unsigned int tmp;
+        if (soc_is_exynos5440())
+                return 0;
        s3c_pm_init();
        /* All wakeup disable */
@@ -341,6 +343,9 @@ static struct syscore_ops exynos_pm_syscore_ops = {
 static __init int exynos_pm_syscore_init(void)
 {
+        if (soc_is_exynos5440())
+                return 0;
        register_syscore_ops(&exynos_pm_syscore_ops);
        return 0;
 }
diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c
index 9f1351de52f7..1703593e366c 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -74,17 +74,6 @@ static int exynos_pd_power_off(struct generic_pm_domain *domain)
        return exynos_pd_power(domain, false);
 }
-#define EXYNOS_GPD(PD, BASE, NAME)                      \
-static struct exynos_pm_domain PD = {                   \
-        .base = (void __iomem *)BASE,                   \
-        .name = NAME,                                   \
-        .pd = {                                         \
-                .power_off = exynos_pd_power_off,       \
-                .power_on = exynos_pd_power_on, \
-        },                                              \
-}
-#ifdef CONFIG_OF
 static void exynos_add_device_to_domain(struct exynos_pm_domain *pd,
                                         struct device *dev)
 {
@@ -157,7 +146,7 @@ static struct notifier_block platform_nb = {
        .notifier_call = exynos_pm_notifier_call,
 };
-static __init int exynos_pm_dt_parse_domains(void)
+static __init int exynos4_pm_init_power_domain(void)
 {
        struct platform_device *pdev;
        struct device_node *np;
@@ -193,94 +182,6 @@ static __init int exynos_pm_dt_parse_domains(void)
        return 0;
 }
-#else
-static __init int exynos_pm_dt_parse_domains(void)
-{
-        return 0;
-}
-#endif /* CONFIG_OF */
-static __init __maybe_unused void exynos_pm_add_dev_to_genpd(struct platform_device *pdev,
-                                                struct exynos_pm_domain *pd)
-{
-        if (pdev->dev.bus) {
-                if (!pm_genpd_add_device(&pd->pd, &pdev->dev))
-                        pm_genpd_dev_need_restore(&pdev->dev, true);
-                else
-                        pr_info("%s: error in adding %s device to %s power"
-                                "domain\n", __func__, dev_name(&pdev->dev),
-                                pd->name);
-        }
-}
-EXYNOS_GPD(exynos4_pd_mfc, S5P_PMU_MFC_CONF, "pd-mfc");
-EXYNOS_GPD(exynos4_pd_g3d, S5P_PMU_G3D_CONF, "pd-g3d");
-EXYNOS_GPD(exynos4_pd_lcd0, S5P_PMU_LCD0_CONF, "pd-lcd0");
-EXYNOS_GPD(exynos4_pd_lcd1, S5P_PMU_LCD1_CONF, "pd-lcd1");
-EXYNOS_GPD(exynos4_pd_tv, S5P_PMU_TV_CONF, "pd-tv");
-EXYNOS_GPD(exynos4_pd_cam, S5P_PMU_CAM_CONF, "pd-cam");
-EXYNOS_GPD(exynos4_pd_gps, S5P_PMU_GPS_CONF, "pd-gps");
-static struct exynos_pm_domain *exynos4_pm_domains[] = {
-        &exynos4_pd_mfc,
-        &exynos4_pd_g3d,
-        &exynos4_pd_lcd0,
-        &exynos4_pd_lcd1,
-        &exynos4_pd_tv,
-        &exynos4_pd_cam,
-        &exynos4_pd_gps,
-};
-static __init int exynos4_pm_init_power_domain(void)
-{
-        int idx;
-        if (of_have_populated_dt())
-                return exynos_pm_dt_parse_domains();
-        for (idx = 0; idx < ARRAY_SIZE(exynos4_pm_domains); idx++) {
-                struct exynos_pm_domain *pd = exynos4_pm_domains[idx];
-                int on = __raw_readl(pd->base + 0x4) & S5P_INT_LOCAL_PWR_EN;
-                pm_genpd_init(&pd->pd, NULL, !on);
-        }
-#ifdef CONFIG_S5P_DEV_FIMD0
-        exynos_pm_add_dev_to_genpd(&s5p_device_fimd0, &exynos4_pd_lcd0);
-#endif
-#ifdef CONFIG_S5P_DEV_TV
-        exynos_pm_add_dev_to_genpd(&s5p_device_hdmi, &exynos4_pd_tv);
-        exynos_pm_add_dev_to_genpd(&s5p_device_mixer, &exynos4_pd_tv);
-#endif
-#ifdef CONFIG_S5P_DEV_MFC
-        exynos_pm_add_dev_to_genpd(&s5p_device_mfc, &exynos4_pd_mfc);
-#endif
-#ifdef CONFIG_S5P_DEV_FIMC0
-        exynos_pm_add_dev_to_genpd(&s5p_device_fimc0, &exynos4_pd_cam);
-#endif
-#ifdef CONFIG_S5P_DEV_FIMC1
-        exynos_pm_add_dev_to_genpd(&s5p_device_fimc1, &exynos4_pd_cam);
-#endif
-#ifdef CONFIG_S5P_DEV_FIMC2
-        exynos_pm_add_dev_to_genpd(&s5p_device_fimc2, &exynos4_pd_cam);
-#endif
-#ifdef CONFIG_S5P_DEV_FIMC3
-        exynos_pm_add_dev_to_genpd(&s5p_device_fimc3, &exynos4_pd_cam);
-#endif
-#ifdef CONFIG_S5P_DEV_CSIS0
-        exynos_pm_add_dev_to_genpd(&s5p_device_mipi_csis0, &exynos4_pd_cam);
-#endif
-#ifdef CONFIG_S5P_DEV_CSIS1
-        exynos_pm_add_dev_to_genpd(&s5p_device_mipi_csis1, &exynos4_pd_cam);
-#endif
-#ifdef CONFIG_S5P_DEV_G2D
-        exynos_pm_add_dev_to_genpd(&s5p_device_g2d, &exynos4_pd_lcd0);
-#endif
-#ifdef CONFIG_S5P_DEV_JPEG
-        exynos_pm_add_dev_to_genpd(&s5p_device_jpeg, &exynos4_pd_cam);
-#endif
-        return 0;
-}
 arch_initcall(exynos4_pm_init_power_domain);
 int __init exynos_pm_late_initcall(void)
diff --git a/arch/arm/mach-exynos/setup-fimc.c b/arch/arm/mach-exynos/setup-fimc.c
deleted file mode 100644
index 6a45078d9d12..000000000000
--- a/arch/arm/mach-exynos/setup-fimc.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (C) 2011 Samsung Electronics Co., Ltd.
- *
- * Exynos4 camera interface GPIO configuration.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/gpio.h>
-#include <plat/gpio-cfg.h>
-#include <plat/camport.h>
-int exynos4_fimc_setup_gpio(enum s5p_camport_id id)
-{
-        u32 gpio8, gpio5;
-        u32 sfn;
-        int ret;
-        switch (id) {
-        case S5P_CAMPORT_A:
-                gpio8 = EXYNOS4_GPJ0(0); /* PCLK, VSYNC, HREF, DATA[0:4] */
-                gpio5 = EXYNOS4_GPJ1(0); /* DATA[5:7], CLKOUT, FIELD */
-                sfn = S3C_GPIO_SFN(2);
-                break;
-        case S5P_CAMPORT_B:
-                gpio8 = EXYNOS4_GPE0(0); /* DATA[0:7] */
-                gpio5 = EXYNOS4_GPE1(0); /* PCLK, VSYNC, HREF, CLKOUT, FIELD */
-                sfn = S3C_GPIO_SFN(3);
-                break;
-        default:
-                WARN(1, "Wrong camport id: %d\n", id);
-                return -EINVAL;
-        }
-        ret = s3c_gpio_cfgall_range(gpio8, 8, sfn, S3C_GPIO_PULL_UP);
-        if (ret)
-                return ret;
-        return s3c_gpio_cfgall_range(gpio5, 5, sfn, S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-exynos/setup-fimd0.c b/arch/arm/mach-exynos/setup-fimd0.c
deleted file mode 100644
index 5665bb4e980b..000000000000
--- a/arch/arm/mach-exynos/setup-fimd0.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/* linux/arch/arm/mach-exynos4/setup-fimd0.c
- *
- * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * Base Exynos4 FIMD 0 configuration
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/fb.h>
-#include <linux/gpio.h>
-#include <video/samsung_fimd.h>
-#include <plat/gpio-cfg.h>
-#include <mach/map.h>
-void exynos4_fimd0_gpio_setup_24bpp(void)
-{
-        unsigned int reg;
-        s3c_gpio_cfgrange_nopull(EXYNOS4_GPF0(0), 8, S3C_GPIO_SFN(2));
-        s3c_gpio_cfgrange_nopull(EXYNOS4_GPF1(0), 8, S3C_GPIO_SFN(2));
-        s3c_gpio_cfgrange_nopull(EXYNOS4_GPF2(0), 8, S3C_GPIO_SFN(2));
-        s3c_gpio_cfgrange_nopull(EXYNOS4_GPF3(0), 4, S3C_GPIO_SFN(2));
-        /*
-         * Set DISPLAY_CONTROL register for Display path selection.
-         *
-         * DISPLAY_CONTROL[1:0]
-         * ---------------------
-         *  00 | MIE
-         *  01 | MDINE
-         *  10 | FIMD : selected
-         *  11 | FIMD
-         */
-        reg = __raw_readl(S3C_VA_SYS + 0x0210);
-        reg |= (1 << 1);
-        __raw_writel(reg, S3C_VA_SYS + 0x0210);
-}
diff --git a/arch/arm/mach-exynos/setup-i2c0.c b/arch/arm/mach-exynos/setup-i2c0.c
deleted file mode 100644
index e2d9dfbf102c..000000000000
--- a/arch/arm/mach-exynos/setup-i2c0.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright (c) 2009-2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * I2C0 GPIO configuration.
- *
- * Based on plat-s3c64xx/setup-i2c0.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-struct platform_device; /* don't need the contents */
-#include <linux/gpio.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/gpio-cfg.h>
-#include <plat/cpu.h>
-void s3c_i2c0_cfg_gpio(struct platform_device *dev)
-{
-        if (soc_is_exynos5250() || soc_is_exynos5440())
-                /* will be implemented with gpio function */
-                return;
-        s3c_gpio_cfgall_range(EXYNOS4_GPD1(0), 2,
-                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-exynos/setup-i2c1.c b/arch/arm/mach-exynos/setup-i2c1.c
deleted file mode 100644
index 8d2279cc85dc..000000000000
--- a/arch/arm/mach-exynos/setup-i2c1.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/setup-i2c1.c
- *
- * Copyright (C) 2010 Samsung Electronics Co., Ltd.
- *
- * I2C1 GPIO configuration.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-struct platform_device; /* don't need the contents */
-#include <linux/gpio.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/gpio-cfg.h>
-void s3c_i2c1_cfg_gpio(struct platform_device *dev)
-{
-        s3c_gpio_cfgall_range(EXYNOS4_GPD1(2), 2,
-                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-exynos/setup-i2c2.c b/arch/arm/mach-exynos/setup-i2c2.c
deleted file mode 100644
index 0ed62fc42a77..000000000000
--- a/arch/arm/mach-exynos/setup-i2c2.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/setup-i2c2.c
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- *
- * I2C2 GPIO configuration.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-struct platform_device; /* don't need the contents */
-#include <linux/gpio.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/gpio-cfg.h>
-void s3c_i2c2_cfg_gpio(struct platform_device *dev)
-{
-        s3c_gpio_cfgall_range(EXYNOS4_GPA0(6), 2,
-                              S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-exynos/setup-i2c3.c b/arch/arm/mach-exynos/setup-i2c3.c
deleted file mode 100644
index 7787fd26076b..000000000000
--- a/arch/arm/mach-exynos/setup-i2c3.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/setup-i2c3.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *
- * I2C3 GPIO configuration.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-struct platform_device; /* don't need the contents */
-#include <linux/gpio.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/gpio-cfg.h>
-void s3c_i2c3_cfg_gpio(struct platform_device *dev)
-{
-        s3c_gpio_cfgall_range(EXYNOS4_GPA1(2), 2,
-                              S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-exynos/setup-i2c4.c b/arch/arm/mach-exynos/setup-i2c4.c
deleted file mode 100644
index edc847f89826..000000000000
--- a/arch/arm/mach-exynos/setup-i2c4.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/setup-i2c4.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *
- * I2C4 GPIO configuration.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-struct platform_device; /* don't need the contents */
-#include <linux/gpio.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/gpio-cfg.h>
-void s3c_i2c4_cfg_gpio(struct platform_device *dev)
-{
-        s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2,
-                              S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-exynos/setup-i2c5.c b/arch/arm/mach-exynos/setup-i2c5.c
deleted file mode 100644
index d88af7f75954..000000000000
--- a/arch/arm/mach-exynos/setup-i2c5.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/setup-i2c5.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *
- * I2C5 GPIO configuration.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-struct platform_device; /* don't need the contents */
-#include <linux/gpio.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/gpio-cfg.h>
-void s3c_i2c5_cfg_gpio(struct platform_device *dev)
-{
-        s3c_gpio_cfgall_range(EXYNOS4_GPB(6), 2,
-                              S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-exynos/setup-i2c6.c b/arch/arm/mach-exynos/setup-i2c6.c
deleted file mode 100644
index c590286c9d3a..000000000000
--- a/arch/arm/mach-exynos/setup-i2c6.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/setup-i2c6.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *
- * I2C6 GPIO configuration.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-struct platform_device; /* don't need the contents */
-#include <linux/gpio.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/gpio-cfg.h>
-void s3c_i2c6_cfg_gpio(struct platform_device *dev)
-{
-        s3c_gpio_cfgall_range(EXYNOS4_GPC1(3), 2,
-                              S3C_GPIO_SFN(4), S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-exynos/setup-i2c7.c b/arch/arm/mach-exynos/setup-i2c7.c
deleted file mode 100644
index 1bba75568a5f..000000000000
--- a/arch/arm/mach-exynos/setup-i2c7.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/setup-i2c7.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *
- * I2C7 GPIO configuration.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-struct platform_device; /* don't need the contents */
-#include <linux/gpio.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/gpio-cfg.h>
-void s3c_i2c7_cfg_gpio(struct platform_device *dev)
-{
-        s3c_gpio_cfgall_range(EXYNOS4_GPD0(2), 2,
-                              S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-exynos/setup-keypad.c b/arch/arm/mach-exynos/setup-keypad.c
deleted file mode 100644
index 7862bfb5933d..000000000000
--- a/arch/arm/mach-exynos/setup-keypad.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* linux/arch/arm/mach-exynos4/setup-keypad.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * GPIO configuration for Exynos4 KeyPad device
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/gpio.h>
-#include <plat/gpio-cfg.h>
-void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
-{
-        /* Keypads can be of various combinations, Just making sure */
-        if (rows > 8) {
-                /* Set all the necessary GPX2 pins: KP_ROW[0~7] */
-                s3c_gpio_cfgall_range(EXYNOS4_GPX2(0), 8, S3C_GPIO_SFN(3),
-                                        S3C_GPIO_PULL_UP);
-                /* Set all the necessary GPX3 pins: KP_ROW[8~] */
-                s3c_gpio_cfgall_range(EXYNOS4_GPX3(0), (rows - 8),
-                                         S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
-        } else {
-                /* Set all the necessary GPX2 pins: KP_ROW[x] */
-                s3c_gpio_cfgall_range(EXYNOS4_GPX2(0), rows, S3C_GPIO_SFN(3),
-                                        S3C_GPIO_PULL_UP);
-        }
-        /* Set all the necessary GPX1 pins to special-function 3: KP_COL[x] */
-        s3c_gpio_cfgrange_nopull(EXYNOS4_GPX1(0), cols, S3C_GPIO_SFN(3));
-}
diff --git a/arch/arm/mach-exynos/setup-sdhci-gpio.c b/arch/arm/mach-exynos/setup-sdhci-gpio.c
deleted file mode 100644
index d5b98c866738..000000000000
--- a/arch/arm/mach-exynos/setup-sdhci-gpio.c
+++ /dev/null
@@ -1,152 +0,0 @@
-/* linux/arch/arm/mach-exynos4/setup-sdhci-gpio.c
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/mmc/host.h>
-#include <linux/mmc/card.h>
-#include <mach/gpio.h>
-#include <plat/gpio-cfg.h>
-#include <plat/sdhci.h>
-void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
-{
-        struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
-        unsigned int gpio;
-        /* Set all the necessary GPK0[0:1] pins to special-function 2 */
-        for (gpio = EXYNOS4_GPK0(0); gpio < EXYNOS4_GPK0(2); gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
-        switch (width) {
-        case 8:
-                for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) {
-                        /* Data pin GPK1[3:6] to special-function 3 */
-                        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
-                        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
-                        s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-                }
-        case 4:
-                for (gpio = EXYNOS4_GPK0(3); gpio <= EXYNOS4_GPK0(6); gpio++) {
-                        /* Data pin GPK0[3:6] to special-function 2 */
-                        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
-                        s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-                }
-        default:
-                break;
-        }
-        if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
-                s3c_gpio_cfgpin(EXYNOS4_GPK0(2), S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(EXYNOS4_GPK0(2), S3C_GPIO_PULL_UP);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
-}
-void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
-{
-        struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
-        unsigned int gpio;
-        /* Set all the necessary GPK1[0:1] pins to special-function 2 */
-        for (gpio = EXYNOS4_GPK1(0); gpio < EXYNOS4_GPK1(2); gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
-        for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) {
-                /* Data pin GPK1[3:6] to special-function 2 */
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
-        if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
-                s3c_gpio_cfgpin(EXYNOS4_GPK1(2), S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(EXYNOS4_GPK1(2), S3C_GPIO_PULL_UP);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
-}
-void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
-{
-        struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
-        unsigned int gpio;
-        /* Set all the necessary GPK2[0:1] pins to special-function 2 */
-        for (gpio = EXYNOS4_GPK2(0); gpio < EXYNOS4_GPK2(2); gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
-        switch (width) {
-        case 8:
-                for (gpio = EXYNOS4_GPK3(3); gpio <= EXYNOS4_GPK3(6); gpio++) {
-                        /* Data pin GPK3[3:6] to special-function 3 */
-                        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
-                        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
-                        s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-                }
-        case 4:
-                for (gpio = EXYNOS4_GPK2(3); gpio <= EXYNOS4_GPK2(6); gpio++) {
-                        /* Data pin GPK2[3:6] to special-function 2 */
-                        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
-                        s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-                }
-        default:
-                break;
-        }
-        if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
-                s3c_gpio_cfgpin(EXYNOS4_GPK2(2), S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(EXYNOS4_GPK2(2), S3C_GPIO_PULL_UP);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
-}
-void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
-{
-        struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
-        unsigned int gpio;
-        /* Set all the necessary GPK3[0:1] pins to special-function 2 */
-        for (gpio = EXYNOS4_GPK3(0); gpio < EXYNOS4_GPK3(2); gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
-        for (gpio = EXYNOS4_GPK3(3); gpio <= EXYNOS4_GPK3(6); gpio++) {
-                /* Data pin GPK3[3:6] to special-function 2 */
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
-        if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
-                s3c_gpio_cfgpin(EXYNOS4_GPK3(2), S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(EXYNOS4_GPK3(2), S3C_GPIO_PULL_UP);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
-}
diff --git a/arch/arm/mach-exynos/setup-spi.c b/arch/arm/mach-exynos/setup-spi.c
deleted file mode 100644
index 4999829d1c6e..000000000000
--- a/arch/arm/mach-exynos/setup-spi.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/* linux/arch/arm/mach-exynos4/setup-spi.c
- *
- * Copyright (C) 2011 Samsung Electronics Ltd.
- *             http://www.samsung.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/gpio.h>
-#include <plat/gpio-cfg.h>
-#ifdef CONFIG_S3C64XX_DEV_SPI0
-int s3c64xx_spi0_cfg_gpio(void)
-{
-        s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2));
-        s3c_gpio_setpull(EXYNOS4_GPB(0), S3C_GPIO_PULL_UP);
-        s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2,
-                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-        return 0;
-}
-#endif
-#ifdef CONFIG_S3C64XX_DEV_SPI1
-int s3c64xx_spi1_cfg_gpio(void)
-{
-        s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2));
-        s3c_gpio_setpull(EXYNOS4_GPB(4), S3C_GPIO_PULL_UP);
-        s3c_gpio_cfgall_range(EXYNOS4_GPB(6), 2,
-                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-        return 0;
-}
-#endif
-#ifdef CONFIG_S3C64XX_DEV_SPI2
-int s3c64xx_spi2_cfg_gpio(void)
-{
-        s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5));
-        s3c_gpio_setpull(EXYNOS4_GPC1(1), S3C_GPIO_PULL_UP);
-        s3c_gpio_cfgall_range(EXYNOS4_GPC1(3), 2,
-                              S3C_GPIO_SFN(5), S3C_GPIO_PULL_UP);
-        return 0;
-}
-#endif
diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c
deleted file mode 100644
index 6af40662a449..000000000000
--- a/arch/arm/mach-exynos/setup-usb-phy.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * Copyright (C) 2011 Samsung Electronics Co.Ltd
- * Author: Joonyoung Shim <jy0922.shim@samsung.com>
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- */
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-#include <mach/regs-pmu.h>
-#include <mach/regs-usb-phy.h>
-#include <plat/cpu.h>
-#include <plat/usb-phy.h>
-static atomic_t host_usage;
-static int exynos4_usb_host_phy_is_on(void)
-{
-        return (readl(EXYNOS4_PHYPWR) & PHY1_STD_ANALOG_POWERDOWN) ? 0 : 1;
-}
-static void exynos4210_usb_phy_clkset(struct platform_device *pdev)
-{
-        struct clk *xusbxti_clk;
-        u32 phyclk;
-        xusbxti_clk = clk_get(&pdev->dev, "xusbxti");
-        if (xusbxti_clk && !IS_ERR(xusbxti_clk)) {
-                if (soc_is_exynos4210()) {
-                        /* set clock frequency for PLL */
-                        phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4210_CLKSEL_MASK;
-                        switch (clk_get_rate(xusbxti_clk)) {
-                        case 12 * MHZ:
-                                phyclk |= EXYNOS4210_CLKSEL_12M;
-                                break;
-                        case 48 * MHZ:
-                                phyclk |= EXYNOS4210_CLKSEL_48M;
-                                break;
-                        default:
-                        case 24 * MHZ:
-                                phyclk |= EXYNOS4210_CLKSEL_24M;
-                                break;
-                        }
-                        writel(phyclk, EXYNOS4_PHYCLK);
-                } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
-                        /* set clock frequency for PLL */
-                        phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4X12_CLKSEL_MASK;
-                        switch (clk_get_rate(xusbxti_clk)) {
-                        case 9600 * KHZ:
-                                phyclk |= EXYNOS4X12_CLKSEL_9600K;
-                                break;
-                        case 10 * MHZ:
-                                phyclk |= EXYNOS4X12_CLKSEL_10M;
-                                break;
-                        case 12 * MHZ:
-                                phyclk |= EXYNOS4X12_CLKSEL_12M;
-                                break;
-                        case 19200 * KHZ:
-                                phyclk |= EXYNOS4X12_CLKSEL_19200K;
-                                break;
-                        case 20 * MHZ:
-                                phyclk |= EXYNOS4X12_CLKSEL_20M;
-                                break;
-                        default:
-                        case 24 * MHZ:
-                                /* default reference clock */
-                                phyclk |= EXYNOS4X12_CLKSEL_24M;
-                                break;
-                        }
-                        writel(phyclk, EXYNOS4_PHYCLK);
-                }
-                clk_put(xusbxti_clk);
-        }
-}
-static int exynos4210_usb_phy0_init(struct platform_device *pdev)
-{
-        u32 rstcon;
-        writel(readl(S5P_USBDEVICE_PHY_CONTROL) | S5P_USBDEVICE_PHY_ENABLE,
-                        S5P_USBDEVICE_PHY_CONTROL);
-        exynos4210_usb_phy_clkset(pdev);
-        /* set to normal PHY0 */
-        writel((readl(EXYNOS4_PHYPWR) & ~PHY0_NORMAL_MASK), EXYNOS4_PHYPWR);
-        /* reset PHY0 and Link */
-        rstcon = readl(EXYNOS4_RSTCON) | PHY0_SWRST_MASK;
-        writel(rstcon, EXYNOS4_RSTCON);
-        udelay(10);
-        rstcon &= ~PHY0_SWRST_MASK;
-        writel(rstcon, EXYNOS4_RSTCON);
-        return 0;
-}
-static int exynos4210_usb_phy0_exit(struct platform_device *pdev)
-{
-        writel((readl(EXYNOS4_PHYPWR) | PHY0_ANALOG_POWERDOWN |
-                                PHY0_OTG_DISABLE), EXYNOS4_PHYPWR);
-        writel(readl(S5P_USBDEVICE_PHY_CONTROL) & ~S5P_USBDEVICE_PHY_ENABLE,
-                        S5P_USBDEVICE_PHY_CONTROL);
-        return 0;
-}
-static int exynos4210_usb_phy1_init(struct platform_device *pdev)
-{
-        struct clk *otg_clk;
-        u32 rstcon;
-        int err;
-        atomic_inc(&host_usage);
-        otg_clk = clk_get(&pdev->dev, "otg");
-        if (IS_ERR(otg_clk)) {
-                dev_err(&pdev->dev, "Failed to get otg clock\n");
-                return PTR_ERR(otg_clk);
-        }
-        err = clk_enable(otg_clk);
-        if (err) {
-                clk_put(otg_clk);
-                return err;
-        }
-        if (exynos4_usb_host_phy_is_on())
-                return 0;
-        writel(readl(S5P_USBHOST_PHY_CONTROL) | S5P_USBHOST_PHY_ENABLE,
-                        S5P_USBHOST_PHY_CONTROL);
-        exynos4210_usb_phy_clkset(pdev);
-        /* floating prevention logic: disable */
-        writel((readl(EXYNOS4_PHY1CON) | FPENABLEN), EXYNOS4_PHY1CON);
-        /* set to normal HSIC 0 and 1 of PHY1 */
-        writel((readl(EXYNOS4_PHYPWR) & ~PHY1_HSIC_NORMAL_MASK),
-                        EXYNOS4_PHYPWR);
-        /* set to normal standard USB of PHY1 */
-        writel((readl(EXYNOS4_PHYPWR) & ~PHY1_STD_NORMAL_MASK), EXYNOS4_PHYPWR);
-        /* reset all ports of both PHY and Link */
-        rstcon = readl(EXYNOS4_RSTCON) | HOST_LINK_PORT_SWRST_MASK |
-                PHY1_SWRST_MASK;
-        writel(rstcon, EXYNOS4_RSTCON);
-        udelay(10);
-        rstcon &= ~(HOST_LINK_PORT_SWRST_MASK | PHY1_SWRST_MASK);
-        writel(rstcon, EXYNOS4_RSTCON);
-        udelay(80);
-        clk_disable(otg_clk);
-        clk_put(otg_clk);
-        return 0;
-}
-static int exynos4210_usb_phy1_exit(struct platform_device *pdev)
-{
-        struct clk *otg_clk;
-        int err;
-        if (atomic_dec_return(&host_usage) > 0)
-                return 0;
-        otg_clk = clk_get(&pdev->dev, "otg");
-        if (IS_ERR(otg_clk)) {
-                dev_err(&pdev->dev, "Failed to get otg clock\n");
-                return PTR_ERR(otg_clk);
-        }
-        err = clk_enable(otg_clk);
-        if (err) {
-                clk_put(otg_clk);
-                return err;
-        }
-        writel((readl(EXYNOS4_PHYPWR) | PHY1_STD_ANALOG_POWERDOWN),
-                        EXYNOS4_PHYPWR);
-        writel(readl(S5P_USBHOST_PHY_CONTROL) & ~S5P_USBHOST_PHY_ENABLE,
-                        S5P_USBHOST_PHY_CONTROL);
-        clk_disable(otg_clk);
-        clk_put(otg_clk);
-        return 0;
-}
-int s5p_usb_phy_init(struct platform_device *pdev, int type)
-{
-        if (type == USB_PHY_TYPE_DEVICE)
-                return exynos4210_usb_phy0_init(pdev);
-        else if (type == USB_PHY_TYPE_HOST)
-                return exynos4210_usb_phy1_init(pdev);
-        return -EINVAL;
-}
-int s5p_usb_phy_exit(struct platform_device *pdev, int type)
-{
-        if (type == USB_PHY_TYPE_DEVICE)
-                return exynos4210_usb_phy0_exit(pdev);
-        else if (type == USB_PHY_TYPE_HOST)
-                return exynos4210_usb_phy1_exit(pdev);
-        return -EINVAL;
-}
diff --git a/arch/arm/mach-footbridge/cats-hw.c b/arch/arm/mach-footbridge/cats-hw.c
index 6987a09ec219..9669cc0b6318 100644
--- a/arch/arm/mach-footbridge/cats-hw.c
+++ b/arch/arm/mach-footbridge/cats-hw.c
@@ -86,7 +86,7 @@ fixup_cats(struct tag *tags, char **cmdline, struct meminfo *mi)
 MACHINE_START(CATS, "Chalice-CATS")
        /* Maintainer: Philip Blundell */
        .atag_offset    = 0x100,
-        .restart_mode   = 's',
+        .reboot_mode    = REBOOT_SOFT,
        .fixup          = fixup_cats,
        .map_io         = footbridge_map_io,
        .init_irq       = footbridge_init_irq,
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index a42b369bc439..2739ca2c1334 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -198,9 +198,9 @@ void __init footbridge_map_io(void)
        }
 }
-void footbridge_restart(char mode, const char *cmd)
+void footbridge_restart(enum reboot_mode mode, const char *cmd)
 {
-        if (mode == 's') {
+        if (mode == REBOOT_SOFT) {
                /* Jump into the ROM */
                soft_restart(0x41000000);
        } else {
diff --git a/arch/arm/mach-footbridge/common.h b/arch/arm/mach-footbridge/common.h
index a846e50a07b8..56607b3a773e 100644
--- a/arch/arm/mach-footbridge/common.h
+++ b/arch/arm/mach-footbridge/common.h
@@ -1,3 +1,4 @@
+#include <linux/reboot.h>
 extern void footbridge_timer_init(void);
 extern void isa_timer_init(void);
@@ -8,4 +9,4 @@ extern void footbridge_map_io(void);
 extern void footbridge_init_irq(void);
 extern void isa_init_irq(unsigned int irq);
-extern void footbridge_restart(char, const char *);
+extern void footbridge_restart(enum reboot_mode, const char *);
diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c
index a7cd2cf5e08d..3490a24f969e 100644
--- a/arch/arm/mach-footbridge/dc21285.c
+++ b/arch/arm/mach-footbridge/dc21285.c
@@ -276,8 +276,6 @@ int __init dc21285_setup(int nr, struct pci_sys_data *sys)
        sys->mem_offset  = DC21285_PCI_MEM;
-        pci_ioremap_io(0, DC21285_PCI_IO);
        pci_add_resource_offset(&sys->resources, &res[0], sys->mem_offset);
        pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
diff --git a/arch/arm/mach-footbridge/netwinder-hw.c b/arch/arm/mach-footbridge/netwinder-hw.c
index 90ea23fdce4c..1fd2cf097e30 100644
--- a/arch/arm/mach-footbridge/netwinder-hw.c
+++ b/arch/arm/mach-footbridge/netwinder-hw.c
@@ -634,9 +634,9 @@ fixup_netwinder(struct tag *tags, char **cmdline, struct meminfo *mi)
 #endif
 }
-static void netwinder_restart(char mode, const char *cmd)
+static void netwinder_restart(enum reboot_mode mode, const char *cmd)
 {
-        if (mode == 's') {
+        if (mode == REBOOT_SOFT) {
                /* Jump into the ROM */
                soft_restart(0x41000000);
        } else {
diff --git a/arch/arm/mach-highbank/core.h b/arch/arm/mach-highbank/core.h
index 3f65206a9b92..aea1ec5ab6f8 100644
--- a/arch/arm/mach-highbank/core.h
+++ b/arch/arm/mach-highbank/core.h
@@ -1,8 +1,10 @@
 #ifndef __HIGHBANK_CORE_H
 #define __HIGHBANK_CORE_H
+#include <linux/reboot.h>
 extern void highbank_set_cpu_jump(int cpu, void *jump_addr);
-extern void highbank_restart(char, const char *);
+extern void highbank_restart(enum reboot_mode, const char *);
 extern void __iomem *scu_base_addr;
 #ifdef CONFIG_PM_SLEEP
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index e7df2dd43a40..88815795fe26 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -115,6 +115,7 @@ static int highbank_platform_notifier(struct notifier_block *nb,
 {
        struct resource *res;
        int reg = -1;
+        u32 val;
        struct device *dev = __dev;
        if (event != BUS_NOTIFY_ADD_DEVICE)
@@ -141,10 +142,10 @@ static int highbank_platform_notifier(struct notifier_block *nb,
                return NOTIFY_DONE;
        if (of_property_read_bool(dev->of_node, "dma-coherent")) {
-                writel(0xff31, sregs_base + reg);
+                val = readl(sregs_base + reg);
+                writel(val | 0xff01, sregs_base + reg);
                set_dma_ops(dev, &arm_coherent_dma_ops);
-        } else
+        }
-                writel(0, sregs_base + reg);
        return NOTIFY_OK;
 }
@@ -176,7 +177,6 @@ static const char *highbank_match[] __initconst = {
 DT_MACHINE_START(HIGHBANK, "Highbank")
        .smp            = smp_ops(highbank_smp_ops),
-        .map_io         = debug_ll_io_init,
        .init_irq       = highbank_init_irq,
        .init_time      = highbank_timer_init,
        .init_machine   = highbank_init,
diff --git a/arch/arm/mach-highbank/platsmp.c b/arch/arm/mach-highbank/platsmp.c
index a984573e0d02..32d75cf55cbc 100644
--- a/arch/arm/mach-highbank/platsmp.c
+++ b/arch/arm/mach-highbank/platsmp.c
@@ -24,7 +24,7 @@
 extern void secondary_startup(void);
-static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int highbank_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
        highbank_set_cpu_jump(cpu, secondary_startup);
        arch_send_wakeup_ipi_mask(cpumask_of(cpu));
diff --git a/arch/arm/mach-highbank/system.c b/arch/arm/mach-highbank/system.c
index 37d8384dcf19..2df5870b7583 100644
--- a/arch/arm/mach-highbank/system.c
+++ b/arch/arm/mach-highbank/system.c
@@ -15,13 +15,14 @@
 */
 #include <linux/io.h>
 #include <asm/proc-fns.h>
+#include <linux/reboot.h>
 #include "core.h"
 #include "sysregs.h"
-void highbank_restart(char mode, const char *cmd)
+void highbank_restart(enum reboot_mode mode, const char *cmd)
 {
-        if (mode == 'h')
+        if (mode == REBOOT_HARD)
                highbank_set_pwr_hard_reset();
        else
                highbank_set_pwr_soft_reset();
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index ba44328464f3..f54656091a9d 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -56,9 +56,6 @@ config MXC_USE_EPIT
          uses the same clocks as the GPT. Anyway, on some systems the GPT
          may be in use for other purposes.
-config MXC_ULPI
-        bool
 config ARCH_HAS_RNGA
        bool
@@ -111,7 +108,6 @@ config SOC_IMX25
        select ARCH_MXC_IOMUX_V3
        select COMMON_CLK
        select CPU_ARM926T
-        select HAVE_CAN_FLEXCAN if CAN
        select MXC_AVIC
 config SOC_IMX27
@@ -137,7 +133,6 @@ config SOC_IMX35
        select ARCH_MXC_IOMUX_V3
        select COMMON_CLK
        select CPU_V6K
-        select HAVE_CAN_FLEXCAN if CAN
        select HAVE_EPIT
        select MXC_AVIC
        select SMP_ON_UP if SMP
@@ -176,6 +171,7 @@ config ARCH_MX1ADS
 config MACH_SCB9328
        bool "Synertronixx scb9328"
        select IMX_HAVE_PLATFORM_IMX_UART
+        select SOC_IMX1
        help
          Say Y here if you are using a Synertronixx scb9328 board
@@ -233,7 +229,7 @@ config MACH_EUKREA_CPUIMX25SD
        select IMX_HAVE_PLATFORM_MXC_EHCI
        select IMX_HAVE_PLATFORM_MXC_NAND
        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
        select SOC_IMX25
 choice
@@ -284,7 +280,7 @@ config MACH_PCM038
        select IMX_HAVE_PLATFORM_MXC_NAND
        select IMX_HAVE_PLATFORM_MXC_W1
        select IMX_HAVE_PLATFORM_SPI_IMX
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
        select SOC_IMX27
        help
          Include support for phyCORE-i.MX27 (aka pcm038) platform. This
@@ -314,7 +310,7 @@ config MACH_CPUIMX27
        select IMX_HAVE_PLATFORM_MXC_EHCI
        select IMX_HAVE_PLATFORM_MXC_NAND
        select IMX_HAVE_PLATFORM_MXC_W1
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
        select SOC_IMX27
        help
          Include support for Eukrea CPUIMX27 platform. This includes
@@ -369,7 +365,7 @@ config MACH_MX27_3DS
        select IMX_HAVE_PLATFORM_MXC_MMC
        select IMX_HAVE_PLATFORM_SPI_IMX
        select MXC_DEBUG_BOARD
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
        select SOC_IMX27
        help
          Include support for MX27PDK platform. This includes specific
@@ -414,7 +410,7 @@ config MACH_PCA100
        select IMX_HAVE_PLATFORM_MXC_NAND
        select IMX_HAVE_PLATFORM_MXC_W1
        select IMX_HAVE_PLATFORM_SPI_IMX
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
        select SOC_IMX27
        help
          Include support for phyCARD-s (aka pca100) platform. This
@@ -481,7 +477,7 @@ config MACH_MX31LILLY
        select IMX_HAVE_PLATFORM_MXC_EHCI
        select IMX_HAVE_PLATFORM_MXC_MMC
        select IMX_HAVE_PLATFORM_SPI_IMX
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
        select SOC_IMX31
        help
          Include support for mx31 based LILLY1131 modules. This includes
@@ -497,7 +493,7 @@ config MACH_MX31LITE
        select IMX_HAVE_PLATFORM_MXC_RTC
        select IMX_HAVE_PLATFORM_SPI_IMX
        select LEDS_GPIO_REGISTER
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
        select SOC_IMX31
        help
          Include support for MX31 LITEKIT platform. This includes specific
@@ -514,7 +510,7 @@ config MACH_PCM037
        select IMX_HAVE_PLATFORM_MXC_MMC
        select IMX_HAVE_PLATFORM_MXC_NAND
        select IMX_HAVE_PLATFORM_MXC_W1
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
        select SOC_IMX31
        help
          Include support for Phytec pcm037 platform. This includes
@@ -544,7 +540,7 @@ config MACH_MX31_3DS
        select IMX_HAVE_PLATFORM_MXC_NAND
        select IMX_HAVE_PLATFORM_SPI_IMX
        select MXC_DEBUG_BOARD
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
        select SOC_IMX31
        help
          Include support for MX31PDK (3DS) platform. This includes specific
@@ -571,7 +567,7 @@ config MACH_MX31MOBOARD
        select IMX_HAVE_PLATFORM_MXC_MMC
        select IMX_HAVE_PLATFORM_SPI_IMX
        select LEDS_GPIO_REGISTER
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
        select SOC_IMX31
        help
          Include support for mx31moboard platform. This includes specific
@@ -595,7 +591,7 @@ config MACH_ARMADILLO5X0
        select IMX_HAVE_PLATFORM_MXC_EHCI
        select IMX_HAVE_PLATFORM_MXC_MMC
        select IMX_HAVE_PLATFORM_MXC_NAND
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
        select SOC_IMX31
        help
          Include support for Atmark Armadillo-500 platform. This includes
@@ -639,7 +635,7 @@ config MACH_PCM043
        select IMX_HAVE_PLATFORM_MXC_EHCI
        select IMX_HAVE_PLATFORM_MXC_NAND
        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
        select SOC_IMX35
        help
          Include support for Phytec pcm043 platform. This includes
@@ -673,7 +669,7 @@ config MACH_EUKREA_CPUIMX35SD
        select IMX_HAVE_PLATFORM_MXC_EHCI
        select IMX_HAVE_PLATFORM_MXC_NAND
        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
        select SOC_IMX35
        help
          Include support for Eukrea CPUIMX35 platform. This includes
@@ -776,7 +772,6 @@ comment "Device tree only"
 config  SOC_IMX53
        bool "i.MX53 support"
-        select HAVE_CAN_FLEXCAN if CAN
        select HAVE_IMX_SRC
        select IMX_HAVE_PLATFORM_IMX2_WDT
        select PINCTRL
@@ -799,7 +794,6 @@ config SOC_IMX6Q
        select CPU_V7
        select HAVE_ARM_SCU if SMP
        select HAVE_ARM_TWD if LOCAL_TIMERS
-        select HAVE_CAN_FLEXCAN if CAN
        select HAVE_IMX_ANATOP
        select HAVE_IMX_GPC
        select HAVE_IMX_MMDC
@@ -816,6 +810,41 @@ config SOC_IMX6Q
        help
          This enables support for Freescale i.MX6 Quad processor.
+config SOC_IMX6SL
+        bool "i.MX6 SoloLite support"
+        select ARM_ERRATA_754322
+        select ARM_ERRATA_775420
+        select ARM_GIC
+        select CPU_V7
+        select HAVE_IMX_ANATOP
+        select HAVE_IMX_GPC
+        select HAVE_IMX_MMDC
+        select HAVE_IMX_SRC
+        select MFD_SYSCON
+        select PINCTRL
+        select PINCTRL_IMX6SL
+        select PL310_ERRATA_588369 if CACHE_PL310
+        select PL310_ERRATA_727915 if CACHE_PL310
+        select PL310_ERRATA_769419 if CACHE_PL310
+        help
+          This enables support for Freescale i.MX6 SoloLite processor.
+config SOC_VF610
+        bool "Vybrid Family VF610 support"
+        select CPU_V7
+        select ARM_GIC
+        select CLKSRC_OF
+        select PINCTRL
+        select PINCTRL_VF610
+        select VF_PIT_TIMER
+        select PL310_ERRATA_588369 if CACHE_PL310
+        select PL310_ERRATA_727915 if CACHE_PL310
+        select PL310_ERRATA_769419 if CACHE_PL310
+        help
+          This enable support for Freescale Vybrid VF610 processor.
 endif
 source "arch/arm/mach-imx/devices/Kconfig"
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 70ae7c490ac0..e20f22d58fd8 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -23,7 +23,6 @@ obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
 obj-$(CONFIG_MXC_TZIC) += tzic.o
 obj-$(CONFIG_MXC_AVIC) += avic.o
-obj-$(CONFIG_MXC_ULPI) += ulpi.o
 obj-$(CONFIG_MXC_USE_EPIT) += epit.o
 obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
@@ -98,6 +97,7 @@ AFLAGS_headsmp.o :=-Wa,-march=armv7-a
 obj-$(CONFIG_SMP) += headsmp.o platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
 obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
+obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o
 ifeq ($(CONFIG_PM),y)
 obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o
@@ -111,4 +111,6 @@ obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o
 obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
 obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
+obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o
 obj-y += devices/
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 6fc486b6a3c6..9afac26fa1cc 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -73,6 +73,12 @@ static const char *mx53_cko2_sel[] = {
        "tve_sel", "lp_apm",
        "uart_root", "dummy"/* spdif0_clk_root */,
        "dummy", "dummy", };
+static const char *mx51_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", };
+static const char *mx53_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", "pll4_sw", };
+static const char *spdif_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "spdif_xtal_sel", };
+static const char *spdif0_com_sel[] = { "spdif0_podf", "ssi1_root_gate", };
+static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", };
 enum imx5_clks {
        dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred,
@@ -110,7 +116,9 @@ enum imx5_clks {
        owire_gate, gpu3d_s, gpu2d_s, gpu3d_gate, gpu2d_gate, garb_gate,
        cko1_sel, cko1_podf, cko1,
        cko2_sel, cko2_podf, cko2,
-        srtc_gate, pata_gate,
+        srtc_gate, pata_gate, sata_gate, spdif_xtal_sel, spdif0_sel,
+        spdif1_sel, spdif0_pred, spdif0_podf, spdif1_pred, spdif1_podf,
+        spdif0_com_s, spdif1_com_sel, spdif0_gate, spdif1_gate, spdif_ipg_gate,
        clk_max
 };
@@ -123,11 +131,13 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
 {
        int i;
+        of_clk_init(NULL);
        clk[dummy] = imx_clk_fixed("dummy", 0);
-        clk[ckil] = imx_clk_fixed("ckil", rate_ckil);
+        clk[ckil] = imx_obtain_fixed_clock("ckil", rate_ckil);
-        clk[osc] = imx_clk_fixed("osc", rate_osc);
+        clk[osc] = imx_obtain_fixed_clock("osc", rate_osc);
-        clk[ckih1] = imx_clk_fixed("ckih1", rate_ckih1);
+        clk[ckih1] = imx_obtain_fixed_clock("ckih1", rate_ckih1);
-        clk[ckih2] = imx_clk_fixed("ckih2", rate_ckih2);
+        clk[ckih2] = imx_obtain_fixed_clock("ckih2", rate_ckih2);
        clk[lp_apm] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
                                lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
@@ -267,6 +277,13 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
        clk[owire_gate] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22);
        clk[srtc_gate] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28);
        clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0);
+        clk[spdif0_sel] = imx_clk_mux("spdif0_sel", MXC_CCM_CSCMR2, 0, 2, spdif_sel, ARRAY_SIZE(spdif_sel));
+        clk[spdif0_pred] = imx_clk_divider("spdif0_pred", "spdif0_sel", MXC_CCM_CDCDR, 25, 3);
+        clk[spdif0_podf] = imx_clk_divider("spdif0_podf", "spdif0_pred", MXC_CCM_CDCDR, 19, 6);
+        clk[spdif0_com_s] = imx_clk_mux_flags("spdif0_com_sel", MXC_CCM_CSCMR2, 4, 1,
+                                spdif0_com_sel, ARRAY_SIZE(spdif0_com_sel), CLK_SET_RATE_PARENT);
+        clk[spdif0_gate] = imx_clk_gate2("spdif0_gate", "spdif0_com_sel", MXC_CCM_CCGR5, 26);
+        clk[spdif_ipg_gate] = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5, 30);
        for (i = 0; i < ARRAY_SIZE(clk); i++)
                if (IS_ERR(clk[i]))
@@ -310,8 +327,6 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
        clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
        clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
        clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2");
-        clk_register_clkdev(clk[ssi_ext1_gate], "ssi_ext1", NULL);
-        clk_register_clkdev(clk[ssi_ext2_gate], "ssi_ext2", NULL);
        clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
        clk_register_clkdev(clk[cpu_podf], NULL, "cpufreq-cpu0.0");
        clk_register_clkdev(clk[iim_gate], "iim", NULL);
@@ -378,6 +393,15 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
        clk[mipi_hsc2_gate] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8);
        clk[mipi_esc_gate] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10);
        clk[mipi_hsp_gate] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12);
+        clk[spdif_xtal_sel] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
+                                mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel));
+        clk[spdif1_sel] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2,
+                                spdif_sel, ARRAY_SIZE(spdif_sel));
+        clk[spdif1_pred] = imx_clk_divider("spdif1_podf", "spdif1_sel", MXC_CCM_CDCDR, 16, 3);
+        clk[spdif1_podf] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6);
+        clk[spdif1_com_sel] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1,
+                                mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel));
+        clk[spdif1_gate] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28);
        for (i = 0; i < ARRAY_SIZE(clk); i++)
                if (IS_ERR(clk[i]))
@@ -485,6 +509,7 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
        clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
        clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
        clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
+        clk[sata_gate] = imx_clk_gate2("sata_gate", "ipg", MXC_CCM_CCGR4, 2);
        clk[cko1_sel] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
                                mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
@@ -495,6 +520,8 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
                                mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
        clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
        clk[cko2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
+        clk[spdif_xtal_sel] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
+                                mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel));
        for (i = 0; i < ARRAY_SIZE(clk); i++)
                if (IS_ERR(clk[i]))
@@ -542,42 +569,12 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
        return 0;
 }
-#ifdef CONFIG_OF
-static void __init clk_get_freq_dt(unsigned long *ckil, unsigned long *osc,
-                                   unsigned long *ckih1, unsigned long *ckih2)
-{
-        struct device_node *np;
-        /* retrieve the freqency of fixed clocks from device tree */
-        for_each_compatible_node(np, NULL, "fixed-clock") {
-                u32 rate;
-                if (of_property_read_u32(np, "clock-frequency", &rate))
-                        continue;
-                if (of_device_is_compatible(np, "fsl,imx-ckil"))
-                        *ckil = rate;
-                else if (of_device_is_compatible(np, "fsl,imx-osc"))
-                        *osc = rate;
-                else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
-                        *ckih1 = rate;
-                else if (of_device_is_compatible(np, "fsl,imx-ckih2"))
-                        *ckih2 = rate;
-        }
-}
 int __init mx51_clocks_init_dt(void)
 {
-        unsigned long ckil, osc, ckih1, ckih2;
+        return mx51_clocks_init(0, 0, 0, 0);
-        clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
-        return mx51_clocks_init(ckil, osc, ckih1, ckih2);
 }
 int __init mx53_clocks_init_dt(void)
 {
-        unsigned long ckil, osc, ckih1, ckih2;
+        return mx53_clocks_init(0, 0, 0, 0);
-        clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
-        return mx53_clocks_init(ckil, osc, ckih1, ckih2);
 }
-#endif
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 4e3148ce852d..86567d980b07 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -199,7 +199,8 @@ static const char *pcie_axi_sels[]	= { "axi", "ahb", };
 static const char *ssi_sels[]           = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_post_div", };
 static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
 static const char *enfc_sels[]  = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", };
-static const char *emi_sels[]           = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
+static const char *emi_sels[]           = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", };
+static const char *emi_slow_sels[]      = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
 static const char *vdo_axi_sels[]       = { "axi", "ahb", };
 static const char *vpu_axi_sels[]       = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", };
 static const char *cko1_sels[]  = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div",
@@ -238,7 +239,7 @@ enum mx6q_clks {
        pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
        ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
        sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
-        usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, clk_max
+        usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow, clk_max
 };
 static struct clk *clk[clk_max];
@@ -270,27 +271,16 @@ static struct clk_div_table video_div_table[] = {
        { }
 };
-int __init mx6q_clocks_init(void)
+static void __init imx6q_clocks_init(struct device_node *ccm_node)
 {
        struct device_node *np;
        void __iomem *base;
        int i, irq;
        clk[dummy] = imx_clk_fixed("dummy", 0);
+        clk[ckil] = imx_obtain_fixed_clock("ckil", 0);
-        /* retrieve the freqency of fixed clocks from device tree */
+        clk[ckih] = imx_obtain_fixed_clock("ckih1", 0);
-        for_each_compatible_node(np, NULL, "fixed-clock") {
+        clk[osc] = imx_obtain_fixed_clock("osc", 0);
-                u32 rate;
-                if (of_property_read_u32(np, "clock-frequency", &rate))
-                        continue;
-                if (of_device_is_compatible(np, "fsl,imx-ckil"))
-                        clk[ckil] = imx_clk_fixed("ckil", rate);
-                else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
-                        clk[ckih] = imx_clk_fixed("ckih", rate);
-                else if (of_device_is_compatible(np, "fsl,imx-osc"))
-                        clk[osc] = imx_clk_fixed("osc", rate);
-        }
        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
        base = of_iomap(np, 0);
@@ -312,7 +302,6 @@ int __init mx6q_clocks_init(void)
        clk[pll5_video]    = imx_clk_pllv3(IMX_PLLV3_AV,        "pll5_video",   "osc", base + 0xa0, 0x7f);
        clk[pll6_enet]     = imx_clk_pllv3(IMX_PLLV3_ENET,      "pll6_enet",    "osc", base + 0xe0, 0x3);
        clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB,       "pll7_usb_host","osc", base + 0x20, 0x3);
-        clk[pll8_mlb]      = imx_clk_pllv3(IMX_PLLV3_MLB,       "pll8_mlb",     "osc", base + 0xd0, 0x0);
        /*
         * Bit 20 is the reserved and read-only bit, we do this only for:
@@ -360,7 +349,7 @@ int __init mx6q_clocks_init(void)
        clk[pll5_post_div] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
        clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ccm");
+        np = ccm_node;
        base = of_iomap(np, 0);
        WARN_ON(!base);
        ccm_base = base;
@@ -404,7 +393,7 @@ int __init mx6q_clocks_init(void)
        clk[usdhc4_sel]       = imx_clk_mux("usdhc4_sel",       base + 0x1c, 19, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
        clk[enfc_sel]         = imx_clk_mux("enfc_sel",         base + 0x2c, 16, 2, enfc_sels,         ARRAY_SIZE(enfc_sels));
        clk[emi_sel]          = imx_clk_mux("emi_sel",          base + 0x1c, 27, 2, emi_sels,          ARRAY_SIZE(emi_sels));
-        clk[emi_slow_sel]     = imx_clk_mux("emi_slow_sel",     base + 0x1c, 29, 2, emi_sels,          ARRAY_SIZE(emi_sels));
+        clk[emi_slow_sel]     = imx_clk_mux("emi_slow_sel",     base + 0x1c, 29, 2, emi_slow_sels,     ARRAY_SIZE(emi_slow_sels));
        clk[vdo_axi_sel]      = imx_clk_mux("vdo_axi_sel",      base + 0x18, 11, 1, vdo_axi_sels,      ARRAY_SIZE(vdo_axi_sels));
        clk[vpu_axi_sel]      = imx_clk_mux("vpu_axi_sel",      base + 0x18, 14, 2, vpu_axi_sels,      ARRAY_SIZE(vpu_axi_sels));
        clk[cko1_sel]         = imx_clk_mux("cko1_sel",         base + 0x60, 0,  4, cko1_sels,         ARRAY_SIZE(cko1_sels));
@@ -481,7 +470,14 @@ int __init mx6q_clocks_init(void)
        clk[esai]         = imx_clk_gate2("esai",          "esai_podf",         base + 0x6c, 16);
        clk[gpt_ipg]      = imx_clk_gate2("gpt_ipg",       "ipg",               base + 0x6c, 20);
        clk[gpt_ipg_per]  = imx_clk_gate2("gpt_ipg_per",   "ipg_per",           base + 0x6c, 22);
-        clk[gpu2d_core]   = imx_clk_gate2("gpu2d_core",    "gpu2d_core_podf",   base + 0x6c, 24);
+        if (cpu_is_imx6dl())
+                /*
+                 * The multiplexer and divider of imx6q clock gpu3d_shader get
+                 * redefined/reused as gpu2d_core_sel and gpu2d_core_podf on imx6dl.
+                 */
+                clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu3d_shader", base + 0x6c, 24);
+        else
+                clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
        clk[gpu3d_core]   = imx_clk_gate2("gpu3d_core",    "gpu3d_core_podf",   base + 0x6c, 26);
        clk[hdmi_iahb]    = imx_clk_gate2("hdmi_iahb",     "ahb",               base + 0x70, 0);
        clk[hdmi_isfr]    = imx_clk_gate2("hdmi_isfr",     "pll3_pfd1_540m",    base + 0x70, 4);
@@ -499,7 +495,14 @@ int __init mx6q_clocks_init(void)
        clk[ldb_di1]      = imx_clk_gate2("ldb_di1",       "ldb_di1_podf",      base + 0x74, 14);
        clk[ipu2_di1]     = imx_clk_gate2("ipu2_di1",      "ipu2_di1_sel",      base + 0x74, 10);
        clk[hsi_tx]       = imx_clk_gate2("hsi_tx",        "hsi_tx_podf",       base + 0x74, 16);
-        clk[mlb]          = imx_clk_gate2("mlb",           "axi",               base + 0x74, 18);
+        if (cpu_is_imx6dl())
+                /*
+                 * The multiplexer and divider of the imx6q clock gpu2d get
+                 * redefined/reused as mlb_sys_sel and mlb_sys_clk_podf on imx6dl.
+                 */
+                clk[mlb] = imx_clk_gate2("mlb",            "gpu2d_core_podf",   base + 0x74, 18);
+        else
+                clk[mlb] = imx_clk_gate2("mlb",            "axi",               base + 0x74, 18);
        clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi",  "mmdc_ch0_axi_podf", base + 0x74, 20);
        clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi",  "mmdc_ch1_axi_podf", base + 0x74, 22);
        clk[ocram]        = imx_clk_gate2("ocram",         "ahb",               base + 0x74, 28);
@@ -528,6 +531,7 @@ int __init mx6q_clocks_init(void)
        clk[usdhc2]       = imx_clk_gate2("usdhc2",        "usdhc2_podf",       base + 0x80, 4);
        clk[usdhc3]       = imx_clk_gate2("usdhc3",        "usdhc3_podf",       base + 0x80, 6);
        clk[usdhc4]       = imx_clk_gate2("usdhc4",        "usdhc4_podf",       base + 0x80, 8);
+        clk[eim_slow]     = imx_clk_gate2("eim_slow",      "emi_slow_podf",     base + 0x80, 10);
        clk[vdo_axi]      = imx_clk_gate2("vdo_axi",       "vdo_axi_sel",       base + 0x80, 12);
        clk[vpu_axi]      = imx_clk_gate2("vpu_axi",       "vpu_axi_podf",      base + 0x80, 14);
        clk[cko1]         = imx_clk_gate("cko1",           "cko1_podf",         base + 0x60, 7);
@@ -547,6 +551,8 @@ int __init mx6q_clocks_init(void)
        clk_register_clkdev(clk[ahb], "ahb", NULL);
        clk_register_clkdev(clk[cko1], "cko1", NULL);
        clk_register_clkdev(clk[arm], NULL, "cpu0");
+        clk_register_clkdev(clk[pll4_post_div], "pll4_post_div", NULL);
+        clk_register_clkdev(clk[pll4_audio], "pll4_audio", NULL);
        if (imx6q_revision() != IMX_CHIP_REVISION_1_0) {
                clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);
@@ -576,6 +582,5 @@ int __init mx6q_clocks_init(void)
        WARN_ON(!base);
        irq = irq_of_parse_and_map(np, 0);
        mxc_timer_init(base, irq);
-        return 0;
 }
+CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);
diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c
new file mode 100644
index 000000000000..a307ac22dffe
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx6sl.c
@@ -0,0 +1,267 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <dt-bindings/clock/imx6sl-clock.h>
+#include "clk.h"
+#include "common.h"
+static const char const *step_sels[]            = { "osc", "pll2_pfd2", };
+static const char const *pll1_sw_sels[]         = { "pll1_sys", "step", };
+static const char const *ocram_alt_sels[]       = { "pll2_pfd2", "pll3_pfd1", };
+static const char const *ocram_sels[]           = { "periph", "ocram_alt_sels", };
+static const char const *pre_periph_sels[]      = { "pll2_bus", "pll2_pfd2", "pll2_pfd0", "pll2_198m", };
+static const char const *periph_clk2_sels[]     = { "pll3_usb_otg", "osc", "osc", "dummy", };
+static const char const *periph2_clk2_sels[]    = { "pll3_usb_otg", "pll2_bus", };
+static const char const *periph_sels[]          = { "pre_periph_sel", "periph_clk2_podf", };
+static const char const *periph2_sels[]         = { "pre_periph2_sel", "periph2_clk2_podf", };
+static const char const *csi_lcdif_sels[]       = { "mmdc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", };
+static const char const *usdhc_sels[]           = { "pll2_pfd2", "pll2_pfd0", };
+static const char const *ssi_sels[]             = { "pll3_pfd2", "pll3_pfd3", "pll4_post_div", "dummy", };
+static const char const *perclk_sels[]          = { "ipg", "osc", };
+static const char const *epdc_pxp_sels[]        = { "mmdc", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd1", };
+static const char const *gpu2d_ovg_sels[]       = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", };
+static const char const *gpu2d_sels[]           = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", };
+static const char const *lcdif_pix_sels[]       = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", };
+static const char const *epdc_pix_sels[]        = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", };
+static const char const *audio_sels[]           = { "pll4_post_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", };
+static const char const *ecspi_sels[]           = { "pll3_60m", "osc", };
+static const char const *uart_sels[]            = { "pll3_80m", "osc", };
+static struct clk_div_table clk_enet_ref_table[] = {
+        { .val = 0, .div = 20, },
+        { .val = 1, .div = 10, },
+        { .val = 2, .div = 5, },
+        { .val = 3, .div = 4, },
+        { }
+};
+static struct clk_div_table post_div_table[] = {
+        { .val = 2, .div = 1, },
+        { .val = 1, .div = 2, },
+        { .val = 0, .div = 4, },
+        { }
+};
+static struct clk_div_table video_div_table[] = {
+        { .val = 0, .div = 1, },
+        { .val = 1, .div = 2, },
+        { .val = 2, .div = 1, },
+        { .val = 3, .div = 4, },
+        { }
+};
+static struct clk *clks[IMX6SL_CLK_CLK_END];
+static struct clk_onecell_data clk_data;
+static void __init imx6sl_clocks_init(struct device_node *ccm_node)
+{
+        struct device_node *np;
+        void __iomem *base;
+        int irq;
+        int i;
+        clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
+        clks[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
+        clks[IMX6SL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop");
+        base = of_iomap(np, 0);
+        WARN_ON(!base);
+        /*                                             type               name            parent  base         div_mask */
+        clks[IMX6SL_CLK_PLL1_SYS]      = imx_clk_pllv3(IMX_PLLV3_SYS,     "pll1_sys",      "osc", base,        0x7f);
+        clks[IMX6SL_CLK_PLL2_BUS]      = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus",      "osc", base + 0x30, 0x1);
+        clks[IMX6SL_CLK_PLL3_USB_OTG]  = imx_clk_pllv3(IMX_PLLV3_USB,     "pll3_usb_otg",  "osc", base + 0x10, 0x3);
+        clks[IMX6SL_CLK_PLL4_AUDIO]    = imx_clk_pllv3(IMX_PLLV3_AV,      "pll4_audio",    "osc", base + 0x70, 0x7f);
+        clks[IMX6SL_CLK_PLL5_VIDEO]    = imx_clk_pllv3(IMX_PLLV3_AV,      "pll5_video",    "osc", base + 0xa0, 0x7f);
+        clks[IMX6SL_CLK_PLL6_ENET]     = imx_clk_pllv3(IMX_PLLV3_ENET,    "pll6_enet",     "osc", base + 0xe0, 0x3);
+        clks[IMX6SL_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB,     "pll7_usb_host", "osc", base + 0x20, 0x3);
+        /*
+         * usbphy1 and usbphy2 are implemented as dummy gates using reserve
+         * bit 20.  They are used by phy driver to keep the refcount of
+         * parent PLL correct. usbphy1_gate and usbphy2_gate only needs to be
+         * turned on during boot, and software will not need to control it
+         * anymore after that.
+         */
+        clks[IMX6SL_CLK_USBPHY1]      = imx_clk_gate("usbphy1",      "pll3_usb_otg",  base + 0x10, 20);
+        clks[IMX6SL_CLK_USBPHY2]      = imx_clk_gate("usbphy2",      "pll7_usb_host", base + 0x20, 20);
+        clks[IMX6SL_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy",         base + 0x10, 6);
+        clks[IMX6SL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy",         base + 0x20, 6);
+        /*                                                           dev   name              parent_name      flags                reg        shift width div: flags, div_table lock */
+        clks[IMX6SL_CLK_PLL4_POST_DIV]  = clk_register_divider_table(NULL, "pll4_post_div",  "pll4_audio",    CLK_SET_RATE_PARENT, base + 0x70,  19, 2,   0, post_div_table, &imx_ccm_lock);
+        clks[IMX6SL_CLK_PLL5_POST_DIV]  = clk_register_divider_table(NULL, "pll5_post_div",  "pll5_video",    CLK_SET_RATE_PARENT, base + 0xa0,  19, 2,   0, post_div_table, &imx_ccm_lock);
+        clks[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2,   0, video_div_table, &imx_ccm_lock);
+        clks[IMX6SL_CLK_ENET_REF]       = clk_register_divider_table(NULL, "enet_ref",       "pll6_enet",     0,                   base + 0xe0,  0,  2,   0, clk_enet_ref_table, &imx_ccm_lock);
+        /*                                       name         parent_name     reg           idx */
+        clks[IMX6SL_CLK_PLL2_PFD0] = imx_clk_pfd("pll2_pfd0", "pll2_bus",     base + 0x100, 0);
+        clks[IMX6SL_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_bus",     base + 0x100, 1);
+        clks[IMX6SL_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_bus",     base + 0x100, 2);
+        clks[IMX6SL_CLK_PLL3_PFD0] = imx_clk_pfd("pll3_pfd0", "pll3_usb_otg", base + 0xf0,  0);
+        clks[IMX6SL_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_usb_otg", base + 0xf0,  1);
+        clks[IMX6SL_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_usb_otg", base + 0xf0,  2);
+        clks[IMX6SL_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_usb_otg", base + 0xf0,  3);
+        /*                                                name         parent_name     mult div */
+        clks[IMX6SL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2",      1, 2);
+        clks[IMX6SL_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg",   1, 4);
+        clks[IMX6SL_CLK_PLL3_80M]  = imx_clk_fixed_factor("pll3_80m",  "pll3_usb_otg",   1, 6);
+        clks[IMX6SL_CLK_PLL3_60M]  = imx_clk_fixed_factor("pll3_60m",  "pll3_usb_otg",   1, 8);
+        np = ccm_node;
+        base = of_iomap(np, 0);
+        WARN_ON(!base);
+        /*                                              name                reg       shift width parent_names     num_parents */
+        clks[IMX6SL_CLK_STEP]             = imx_clk_mux("step",             base + 0xc,  8,  1, step_sels,         ARRAY_SIZE(step_sels));
+        clks[IMX6SL_CLK_PLL1_SW]          = imx_clk_mux("pll1_sw",          base + 0xc,  2,  1, pll1_sw_sels,      ARRAY_SIZE(pll1_sw_sels));
+        clks[IMX6SL_CLK_OCRAM_ALT_SEL]    = imx_clk_mux("ocram_alt_sel",    base + 0x14, 7,  1, ocram_alt_sels,    ARRAY_SIZE(ocram_alt_sels));
+        clks[IMX6SL_CLK_OCRAM_SEL]        = imx_clk_mux("ocram_sel",        base + 0x14, 6,  1, ocram_sels,        ARRAY_SIZE(ocram_sels));
+        clks[IMX6SL_CLK_PRE_PERIPH2_SEL]  = imx_clk_mux("pre_periph2_sel",  base + 0x18, 21, 2, pre_periph_sels,   ARRAY_SIZE(pre_periph_sels));
+        clks[IMX6SL_CLK_PRE_PERIPH_SEL]   = imx_clk_mux("pre_periph_sel",   base + 0x18, 18, 2, pre_periph_sels,   ARRAY_SIZE(pre_periph_sels));
+        clks[IMX6SL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
+        clks[IMX6SL_CLK_PERIPH_CLK2_SEL]  = imx_clk_mux("periph_clk2_sel",  base + 0x18, 12, 2, periph_clk2_sels,  ARRAY_SIZE(periph_clk2_sels));
+        clks[IMX6SL_CLK_CSI_SEL]          = imx_clk_mux("csi_sel",          base + 0x3c, 9,  2, csi_lcdif_sels,    ARRAY_SIZE(csi_lcdif_sels));
+        clks[IMX6SL_CLK_LCDIF_AXI_SEL]    = imx_clk_mux("lcdif_axi_sel",    base + 0x3c, 14, 2, csi_lcdif_sels,    ARRAY_SIZE(csi_lcdif_sels));
+        clks[IMX6SL_CLK_USDHC1_SEL]       = imx_clk_mux("usdhc1_sel",       base + 0x1c, 16, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
+        clks[IMX6SL_CLK_USDHC2_SEL]       = imx_clk_mux("usdhc2_sel",       base + 0x1c, 17, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
+        clks[IMX6SL_CLK_USDHC3_SEL]       = imx_clk_mux("usdhc3_sel",       base + 0x1c, 18, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
+        clks[IMX6SL_CLK_USDHC4_SEL]       = imx_clk_mux("usdhc4_sel",       base + 0x1c, 19, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
+        clks[IMX6SL_CLK_SSI1_SEL]         = imx_clk_mux("ssi1_sel",         base + 0x1c, 10, 2, ssi_sels,          ARRAY_SIZE(ssi_sels));
+        clks[IMX6SL_CLK_SSI2_SEL]         = imx_clk_mux("ssi2_sel",         base + 0x1c, 12, 2, ssi_sels,          ARRAY_SIZE(ssi_sels));
+        clks[IMX6SL_CLK_SSI3_SEL]         = imx_clk_mux("ssi3_sel",         base + 0x1c, 14, 2, ssi_sels,          ARRAY_SIZE(ssi_sels));
+        clks[IMX6SL_CLK_PERCLK_SEL]       = imx_clk_mux("perclk_sel",       base + 0x1c, 6,  1, perclk_sels,       ARRAY_SIZE(perclk_sels));
+        clks[IMX6SL_CLK_PXP_AXI_SEL]      = imx_clk_mux("pxp_axi_sel",      base + 0x34, 6,  3, epdc_pxp_sels,     ARRAY_SIZE(epdc_pxp_sels));
+        clks[IMX6SL_CLK_EPDC_AXI_SEL]     = imx_clk_mux("epdc_axi_sel",     base + 0x34, 15, 3, epdc_pxp_sels,     ARRAY_SIZE(epdc_pxp_sels));
+        clks[IMX6SL_CLK_GPU2D_OVG_SEL]    = imx_clk_mux("gpu2d_ovg_sel",    base + 0x18, 4,  2, gpu2d_ovg_sels,    ARRAY_SIZE(gpu2d_ovg_sels));
+        clks[IMX6SL_CLK_GPU2D_SEL]        = imx_clk_mux("gpu2d_sel",        base + 0x18, 8,  2, gpu2d_sels,        ARRAY_SIZE(gpu2d_sels));
+        clks[IMX6SL_CLK_LCDIF_PIX_SEL]    = imx_clk_mux("lcdif_pix_sel",    base + 0x38, 6,  3, lcdif_pix_sels,    ARRAY_SIZE(lcdif_pix_sels));
+        clks[IMX6SL_CLK_EPDC_PIX_SEL]     = imx_clk_mux("epdc_pix_sel",     base + 0x38, 15, 3, epdc_pix_sels,     ARRAY_SIZE(epdc_pix_sels));
+        clks[IMX6SL_CLK_SPDIF0_SEL]       = imx_clk_mux("spdif0_sel",       base + 0x30, 20, 2, audio_sels,        ARRAY_SIZE(audio_sels));
+        clks[IMX6SL_CLK_SPDIF1_SEL]       = imx_clk_mux("spdif1_sel",       base + 0x30, 7,  2, audio_sels,        ARRAY_SIZE(audio_sels));
+        clks[IMX6SL_CLK_EXTERN_AUDIO_SEL] = imx_clk_mux("extern_audio_sel", base + 0x20, 19, 2, audio_sels,        ARRAY_SIZE(audio_sels));
+        clks[IMX6SL_CLK_ECSPI_SEL]        = imx_clk_mux("ecspi_sel",        base + 0x38, 18, 1, ecspi_sels,        ARRAY_SIZE(ecspi_sels));
+        clks[IMX6SL_CLK_UART_SEL]         = imx_clk_mux("uart_sel",         base + 0x24, 6,  1, uart_sels,         ARRAY_SIZE(uart_sels));
+        /*                                          name       reg        shift width busy: reg, shift parent_names  num_parents */
+        clks[IMX6SL_CLK_PERIPH]  = imx_clk_busy_mux("periph",  base + 0x14, 25,  1,   base + 0x48, 5,  periph_sels,  ARRAY_SIZE(periph_sels));
+        clks[IMX6SL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26,  1,   base + 0x48, 3,  periph2_sels, ARRAY_SIZE(periph2_sels));
+        /*                                                   name                 parent_name          reg       shift width */
+        clks[IMX6SL_CLK_OCRAM_PODF]        = imx_clk_divider("ocram_podf",        "ocram_sel",         base + 0x14, 16, 3);
+        clks[IMX6SL_CLK_PERIPH_CLK2_PODF]  = imx_clk_divider("periph_clk2_podf",  "periph_clk2_sel",   base + 0x14, 27, 3);
+        clks[IMX6SL_CLK_PERIPH2_CLK2_PODF] = imx_clk_divider("periph2_clk2_podf", "periph2_clk2_sel",  base + 0x14, 0,  3);
+        clks[IMX6SL_CLK_IPG]               = imx_clk_divider("ipg",               "ahb",               base + 0x14, 8,  2);
+        clks[IMX6SL_CLK_CSI_PODF]          = imx_clk_divider("csi_podf",          "csi_sel",           base + 0x3c, 11, 3);
+        clks[IMX6SL_CLK_LCDIF_AXI_PODF]    = imx_clk_divider("lcdif_axi_podf",    "lcdif_axi_sel",     base + 0x3c, 16, 3);
+        clks[IMX6SL_CLK_USDHC1_PODF]       = imx_clk_divider("usdhc1_podf",       "usdhc1_sel",        base + 0x24, 11, 3);
+        clks[IMX6SL_CLK_USDHC2_PODF]       = imx_clk_divider("usdhc2_podf",       "usdhc2_sel",        base + 0x24, 16, 3);
+        clks[IMX6SL_CLK_USDHC3_PODF]       = imx_clk_divider("usdhc3_podf",       "usdhc3_sel",        base + 0x24, 19, 3);
+        clks[IMX6SL_CLK_USDHC4_PODF]       = imx_clk_divider("usdhc4_podf",       "usdhc4_sel",        base + 0x24, 22, 3);
+        clks[IMX6SL_CLK_SSI1_PRED]         = imx_clk_divider("ssi1_pred",         "ssi1_sel",          base + 0x28, 6,  3);
+        clks[IMX6SL_CLK_SSI1_PODF]         = imx_clk_divider("ssi1_podf",         "ssi1_pred",         base + 0x28, 0,  6);
+        clks[IMX6SL_CLK_SSI2_PRED]         = imx_clk_divider("ssi2_pred",         "ssi2_sel",          base + 0x2c, 6,  3);
+        clks[IMX6SL_CLK_SSI2_PODF]         = imx_clk_divider("ssi2_podf",         "ssi2_pred",         base + 0x2c, 0,  6);
+        clks[IMX6SL_CLK_SSI3_PRED]         = imx_clk_divider("ssi3_pred",         "ssi3_sel",          base + 0x28, 22, 3);
+        clks[IMX6SL_CLK_SSI3_PODF]         = imx_clk_divider("ssi3_podf",         "ssi3_pred",         base + 0x28, 16, 6);
+        clks[IMX6SL_CLK_PERCLK]            = imx_clk_divider("perclk",            "perclk_sel",        base + 0x1c, 0,  6);
+        clks[IMX6SL_CLK_PXP_AXI_PODF]      = imx_clk_divider("pxp_axi_podf",      "pxp_axi_sel",       base + 0x34, 3,  3);
+        clks[IMX6SL_CLK_EPDC_AXI_PODF]     = imx_clk_divider("epdc_axi_podf",     "epdc_axi_sel",      base + 0x34, 12, 3);
+        clks[IMX6SL_CLK_GPU2D_OVG_PODF]    = imx_clk_divider("gpu2d_ovg_podf",    "gpu2d_ovg_sel",     base + 0x18, 26, 3);
+        clks[IMX6SL_CLK_GPU2D_PODF]        = imx_clk_divider("gpu2d_podf",        "gpu2d_sel",         base + 0x18, 29, 3);
+        clks[IMX6SL_CLK_LCDIF_PIX_PRED]    = imx_clk_divider("lcdif_pix_pred",    "lcdif_pix_sel",     base + 0x38, 3,  3);
+        clks[IMX6SL_CLK_EPDC_PIX_PRED]     = imx_clk_divider("epdc_pix_pred",     "epdc_pix_sel",      base + 0x38, 12, 3);
+        clks[IMX6SL_CLK_LCDIF_PIX_PODF]    = imx_clk_divider("lcdif_pix_podf",    "lcdif_pix_pred",    base + 0x1c, 20, 3);
+        clks[IMX6SL_CLK_EPDC_PIX_PODF]     = imx_clk_divider("epdc_pix_podf",     "epdc_pix_pred",     base + 0x18, 23, 3);
+        clks[IMX6SL_CLK_SPDIF0_PRED]       = imx_clk_divider("spdif0_pred",       "spdif0_sel",        base + 0x30, 25, 3);
+        clks[IMX6SL_CLK_SPDIF0_PODF]       = imx_clk_divider("spdif0_podf",       "spdif0_pred",       base + 0x30, 22, 3);
+        clks[IMX6SL_CLK_SPDIF1_PRED]       = imx_clk_divider("spdif1_pred",       "spdif1_sel",        base + 0x30, 12, 3);
+        clks[IMX6SL_CLK_SPDIF1_PODF]       = imx_clk_divider("spdif1_podf",       "spdif1_pred",       base + 0x30, 9,  3);
+        clks[IMX6SL_CLK_EXTERN_AUDIO_PRED] = imx_clk_divider("extern_audio_pred", "extern_audio_sel",  base + 0x28, 9,  3);
+        clks[IMX6SL_CLK_EXTERN_AUDIO_PODF] = imx_clk_divider("extern_audio_podf", "extern_audio_pred", base + 0x28, 25, 3);
+        clks[IMX6SL_CLK_ECSPI_ROOT]        = imx_clk_divider("ecspi_root",        "ecspi_sel",         base + 0x38, 19, 6);
+        clks[IMX6SL_CLK_UART_ROOT]         = imx_clk_divider("uart_root",         "uart_sel",          base + 0x24, 0,  6);
+        /*                                                name         parent_name reg       shift width busy: reg, shift */
+        clks[IMX6SL_CLK_AHB]       = imx_clk_busy_divider("ahb",       "periph",  base + 0x14, 10, 3,    base + 0x48, 1);
+        clks[IMX6SL_CLK_MMDC_ROOT] = imx_clk_busy_divider("mmdc",      "periph2", base + 0x14, 3,  3,    base + 0x48, 2);
+        clks[IMX6SL_CLK_ARM]       = imx_clk_busy_divider("arm",       "pll1_sw", base + 0x10, 0,  3,    base + 0x48, 16);
+        /*                                            name            parent_name          reg         shift */
+        clks[IMX6SL_CLK_ECSPI1]       = imx_clk_gate2("ecspi1",       "ecspi_root",        base + 0x6c, 0);
+        clks[IMX6SL_CLK_ECSPI2]       = imx_clk_gate2("ecspi2",       "ecspi_root",        base + 0x6c, 2);
+        clks[IMX6SL_CLK_ECSPI3]       = imx_clk_gate2("ecspi3",       "ecspi_root",        base + 0x6c, 4);
+        clks[IMX6SL_CLK_ECSPI4]       = imx_clk_gate2("ecspi4",       "ecspi_root",        base + 0x6c, 6);
+        clks[IMX6SL_CLK_EPIT1]        = imx_clk_gate2("epit1",        "perclk",            base + 0x6c, 12);
+        clks[IMX6SL_CLK_EPIT2]        = imx_clk_gate2("epit2",        "perclk",            base + 0x6c, 14);
+        clks[IMX6SL_CLK_EXTERN_AUDIO] = imx_clk_gate2("extern_audio", "extern_audio_podf", base + 0x6c, 16);
+        clks[IMX6SL_CLK_GPT]          = imx_clk_gate2("gpt",          "perclk",            base + 0x6c, 20);
+        clks[IMX6SL_CLK_GPT_SERIAL]   = imx_clk_gate2("gpt_serial",   "perclk",            base + 0x6c, 22);
+        clks[IMX6SL_CLK_GPU2D_OVG]    = imx_clk_gate2("gpu2d_ovg",    "gpu2d_ovg_podf",    base + 0x6c, 26);
+        clks[IMX6SL_CLK_I2C1]         = imx_clk_gate2("i2c1",         "perclk",            base + 0x70, 6);
+        clks[IMX6SL_CLK_I2C2]         = imx_clk_gate2("i2c2",         "perclk",            base + 0x70, 8);
+        clks[IMX6SL_CLK_I2C3]         = imx_clk_gate2("i2c3",         "perclk",            base + 0x70, 10);
+        clks[IMX6SL_CLK_OCOTP]        = imx_clk_gate2("ocotp",        "ipg",               base + 0x70, 12);
+        clks[IMX6SL_CLK_CSI]          = imx_clk_gate2("csi",          "csi_podf",          base + 0x74, 0);
+        clks[IMX6SL_CLK_PXP_AXI]      = imx_clk_gate2("pxp_axi",      "pxp_axi_podf",      base + 0x74, 2);
+        clks[IMX6SL_CLK_EPDC_AXI]     = imx_clk_gate2("epdc_axi",     "epdc_axi_podf",     base + 0x74, 4);
+        clks[IMX6SL_CLK_LCDIF_AXI]    = imx_clk_gate2("lcdif_axi",    "lcdif_axi_podf",    base + 0x74, 6);
+        clks[IMX6SL_CLK_LCDIF_PIX]    = imx_clk_gate2("lcdif_pix",    "lcdif_pix_podf",    base + 0x74, 8);
+        clks[IMX6SL_CLK_EPDC_PIX]     = imx_clk_gate2("epdc_pix",     "epdc_pix_podf",     base + 0x74, 10);
+        clks[IMX6SL_CLK_OCRAM]        = imx_clk_gate2("ocram",        "ocram_podf",        base + 0x74, 28);
+        clks[IMX6SL_CLK_PWM1]         = imx_clk_gate2("pwm1",         "perclk",            base + 0x78, 16);
+        clks[IMX6SL_CLK_PWM2]         = imx_clk_gate2("pwm2",         "perclk",            base + 0x78, 18);
+        clks[IMX6SL_CLK_PWM3]         = imx_clk_gate2("pwm3",         "perclk",            base + 0x78, 20);
+        clks[IMX6SL_CLK_PWM4]         = imx_clk_gate2("pwm4",         "perclk",            base + 0x78, 22);
+        clks[IMX6SL_CLK_SDMA]         = imx_clk_gate2("sdma",         "ipg",               base + 0x7c, 6);
+        clks[IMX6SL_CLK_SPDIF]        = imx_clk_gate2("spdif",        "spdif0_podf",       base + 0x7c, 14);
+        clks[IMX6SL_CLK_SSI1]         = imx_clk_gate2("ssi1",         "ssi1_podf",         base + 0x7c, 18);
+        clks[IMX6SL_CLK_SSI2]         = imx_clk_gate2("ssi2",         "ssi2_podf",         base + 0x7c, 20);
+        clks[IMX6SL_CLK_SSI3]         = imx_clk_gate2("ssi3",         "ssi3_podf",         base + 0x7c, 22);
+        clks[IMX6SL_CLK_UART]         = imx_clk_gate2("uart",         "ipg",               base + 0x7c, 24);
+        clks[IMX6SL_CLK_UART_SERIAL]  = imx_clk_gate2("uart_serial",  "uart_root",         base + 0x7c, 26);
+        clks[IMX6SL_CLK_USBOH3]       = imx_clk_gate2("usboh3",       "ipg",               base + 0x80, 0);
+        clks[IMX6SL_CLK_USDHC1]       = imx_clk_gate2("usdhc1",       "usdhc1_podf",       base + 0x80, 2);
+        clks[IMX6SL_CLK_USDHC2]       = imx_clk_gate2("usdhc2",       "usdhc2_podf",       base + 0x80, 4);
+        clks[IMX6SL_CLK_USDHC3]       = imx_clk_gate2("usdhc3",       "usdhc3_podf",       base + 0x80, 6);
+        clks[IMX6SL_CLK_USDHC4]       = imx_clk_gate2("usdhc4",       "usdhc4_podf",       base + 0x80, 8);
+        for (i = 0; i < ARRAY_SIZE(clks); i++)
+                if (IS_ERR(clks[i]))
+                        pr_err("i.MX6SL clk %d: register failed with %ld\n",
+                                i, PTR_ERR(clks[i]));
+        clk_data.clks = clks;
+        clk_data.clk_num = ARRAY_SIZE(clks);
+        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+        clk_register_clkdev(clks[IMX6SL_CLK_GPT], "ipg", "imx-gpt.0");
+        clk_register_clkdev(clks[IMX6SL_CLK_GPT_SERIAL], "per", "imx-gpt.0");
+        if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
+                clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]);
+                clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]);
+        }
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt");
+        base = of_iomap(np, 0);
+        WARN_ON(!base);
+        irq = irq_of_parse_and_map(np, 0);
+        mxc_timer_init(base, irq);
+}
+CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init);
diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c
index d09bc3df9a7a..a9fad5f8d340 100644
--- a/arch/arm/mach-imx/clk-pllv3.c
+++ b/arch/arm/mach-imx/clk-pllv3.c
@@ -296,13 +296,6 @@ static const struct clk_ops clk_pllv3_enet_ops = {
        .recalc_rate    = clk_pllv3_enet_recalc_rate,
 };
-static const struct clk_ops clk_pllv3_mlb_ops = {
-        .prepare        = clk_pllv3_prepare,
-        .unprepare      = clk_pllv3_unprepare,
-        .enable         = clk_pllv3_enable,
-        .disable        = clk_pllv3_disable,
-};
 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
                          const char *parent_name, void __iomem *base,
                          u32 div_mask)
@@ -330,9 +323,6 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
        case IMX_PLLV3_ENET:
                ops = &clk_pllv3_enet_ops;
                break;
-        case IMX_PLLV3_MLB:
-                ops = &clk_pllv3_mlb_ops;
-                break;
        default:
                ops = &clk_pllv3_ops;
        }
diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c
new file mode 100644
index 000000000000..b169a396d93b
--- /dev/null
+++ b/arch/arm/mach-imx/clk-vf610.c
@@ -0,0 +1,321 @@
+/*
+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#include <linux/of_address.h>
+#include <linux/clk.h>
+#include <dt-bindings/clock/vf610-clock.h>
+#include "clk.h"
+#define CCM_CCR                 (ccm_base + 0x00)
+#define CCM_CSR                 (ccm_base + 0x04)
+#define CCM_CCSR                (ccm_base + 0x08)
+#define CCM_CACRR               (ccm_base + 0x0c)
+#define CCM_CSCMR1              (ccm_base + 0x10)
+#define CCM_CSCDR1              (ccm_base + 0x14)
+#define CCM_CSCDR2              (ccm_base + 0x18)
+#define CCM_CSCDR3              (ccm_base + 0x1c)
+#define CCM_CSCMR2              (ccm_base + 0x20)
+#define CCM_CSCDR4              (ccm_base + 0x24)
+#define CCM_CLPCR               (ccm_base + 0x2c)
+#define CCM_CISR                (ccm_base + 0x30)
+#define CCM_CIMR                (ccm_base + 0x34)
+#define CCM_CGPR                (ccm_base + 0x3c)
+#define CCM_CCGR0               (ccm_base + 0x40)
+#define CCM_CCGR1               (ccm_base + 0x44)
+#define CCM_CCGR2               (ccm_base + 0x48)
+#define CCM_CCGR3               (ccm_base + 0x4c)
+#define CCM_CCGR4               (ccm_base + 0x50)
+#define CCM_CCGR5               (ccm_base + 0x54)
+#define CCM_CCGR6               (ccm_base + 0x58)
+#define CCM_CCGR7               (ccm_base + 0x5c)
+#define CCM_CCGR8               (ccm_base + 0x60)
+#define CCM_CCGR9               (ccm_base + 0x64)
+#define CCM_CCGR10              (ccm_base + 0x68)
+#define CCM_CCGR11              (ccm_base + 0x6c)
+#define CCM_CMEOR0              (ccm_base + 0x70)
+#define CCM_CMEOR1              (ccm_base + 0x74)
+#define CCM_CMEOR2              (ccm_base + 0x78)
+#define CCM_CMEOR3              (ccm_base + 0x7c)
+#define CCM_CMEOR4              (ccm_base + 0x80)
+#define CCM_CMEOR5              (ccm_base + 0x84)
+#define CCM_CPPDSR              (ccm_base + 0x88)
+#define CCM_CCOWR               (ccm_base + 0x8c)
+#define CCM_CCPGR0              (ccm_base + 0x90)
+#define CCM_CCPGR1              (ccm_base + 0x94)
+#define CCM_CCPGR2              (ccm_base + 0x98)
+#define CCM_CCPGR3              (ccm_base + 0x9c)
+#define CCM_CCGRx_CGn(n)        ((n) * 2)
+#define PFD_PLL1_BASE           (anatop_base + 0x2b0)
+#define PFD_PLL2_BASE           (anatop_base + 0x100)
+#define PFD_PLL3_BASE           (anatop_base + 0xf0)
+static void __iomem *anatop_base;
+static void __iomem *ccm_base;
+/* sources for multiplexer clocks, this is used multiple times */
+static const char const *fast_sels[]    = { "firc", "fxosc", };
+static const char const *slow_sels[]    = { "sirc_32k", "sxosc", };
+static const char const *pll1_sels[]    = { "pll1_main", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4", };
+static const char const *pll2_sels[]    = { "pll2_main", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4", };
+static const char const *sys_sels[]     = { "fast_clk_sel", "slow_clk_sel", "pll2_pfd_sel", "pll2_main", "pll1_pfd_sel", "pll3_main", };
+static const char const *ddr_sels[]     = { "pll2_pfd2", "sys_sel", };
+static const char const *rmii_sels[]    = { "enet_ext", "audio_ext", "enet_50m", "enet_25m", };
+static const char const *enet_ts_sels[] = { "enet_ext", "fxosc", "audio_ext", "usb", "enet_ts", "enet_25m", "enet_50m", };
+static const char const *esai_sels[]    = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", };
+static const char const *sai_sels[]     = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", };
+static const char const *nfc_sels[]     = { "platform_bus", "pll1_pfd1", "pll3_pfd1", "pll3_pfd3", };
+static const char const *qspi_sels[]    = { "pll3_main", "pll3_pfd4", "pll2_pfd4", "pll1_pfd4", };
+static const char const *esdhc_sels[]   = { "pll3_main", "pll3_pfd3", "pll1_pfd3", "platform_bus", };
+static const char const *dcu_sels[]     = { "pll1_pfd2", "pll3_main", };
+static const char const *gpu_sels[]     = { "pll2_pfd2", "pll3_pfd2", };
+static const char const *vadc_sels[]    = { "pll6_main_div", "pll3_main_div", "pll3_main", };
+/* FTM counter clock source, not module clock */
+static const char const *ftm_ext_sels[] = {"sirc_128k", "sxosc", "fxosc_half", "audio_ext", };
+static const char const *ftm_fix_sels[] = { "sxosc", "ipg_bus", };
+static struct clk_div_table pll4_main_div_table[] = {
+        { .val = 0, .div = 1 },
+        { .val = 1, .div = 2 },
+        { .val = 2, .div = 6 },
+        { .val = 3, .div = 8 },
+        { .val = 4, .div = 10 },
+        { .val = 5, .div = 12 },
+        { .val = 6, .div = 14 },
+        { .val = 7, .div = 16 },
+        { }
+};
+static struct clk *clk[VF610_CLK_END];
+static struct clk_onecell_data clk_data;
+static void __init vf610_clocks_init(struct device_node *ccm_node)
+{
+        struct device_node *np;
+        clk[VF610_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
+        clk[VF610_CLK_SIRC_128K] = imx_clk_fixed("sirc_128k", 128000);
+        clk[VF610_CLK_SIRC_32K] = imx_clk_fixed("sirc_32k", 32000);
+        clk[VF610_CLK_FIRC] = imx_clk_fixed("firc", 24000000);
+        clk[VF610_CLK_SXOSC] = imx_obtain_fixed_clock("sxosc", 0);
+        clk[VF610_CLK_FXOSC] = imx_obtain_fixed_clock("fxosc", 0);
+        clk[VF610_CLK_AUDIO_EXT] = imx_obtain_fixed_clock("audio_ext", 0);
+        clk[VF610_CLK_ENET_EXT] = imx_obtain_fixed_clock("enet_ext", 0);
+        clk[VF610_CLK_FXOSC_HALF] = imx_clk_fixed_factor("fxosc_half", "fxosc", 1, 2);
+        np = of_find_compatible_node(NULL, NULL, "fsl,vf610-anatop");
+        anatop_base = of_iomap(np, 0);
+        BUG_ON(!anatop_base);
+        np = ccm_node;
+        ccm_base = of_iomap(np, 0);
+        BUG_ON(!ccm_base);
+        clk[VF610_CLK_SLOW_CLK_SEL] = imx_clk_mux("slow_clk_sel", CCM_CCSR, 4, 1, slow_sels, ARRAY_SIZE(slow_sels));
+        clk[VF610_CLK_FASK_CLK_SEL] = imx_clk_mux("fast_clk_sel", CCM_CCSR, 5, 1, fast_sels, ARRAY_SIZE(fast_sels));
+        clk[VF610_CLK_PLL1_MAIN] = imx_clk_fixed_factor("pll1_main", "fast_clk_sel", 22, 1);
+        clk[VF610_CLK_PLL1_PFD1] = imx_clk_pfd("pll1_pfd1", "pll1_main", PFD_PLL1_BASE, 0);
+        clk[VF610_CLK_PLL1_PFD2] = imx_clk_pfd("pll1_pfd2", "pll1_main", PFD_PLL1_BASE, 1);
+        clk[VF610_CLK_PLL1_PFD3] = imx_clk_pfd("pll1_pfd3", "pll1_main", PFD_PLL1_BASE, 2);
+        clk[VF610_CLK_PLL1_PFD4] = imx_clk_pfd("pll1_pfd4", "pll1_main", PFD_PLL1_BASE, 3);
+        clk[VF610_CLK_PLL2_MAIN] = imx_clk_fixed_factor("pll2_main", "fast_clk_sel", 22, 1);
+        clk[VF610_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_main", PFD_PLL2_BASE, 0);
+        clk[VF610_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_main", PFD_PLL2_BASE, 1);
+        clk[VF610_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3", "pll2_main", PFD_PLL2_BASE, 2);
+        clk[VF610_CLK_PLL2_PFD4] = imx_clk_pfd("pll2_pfd4", "pll2_main", PFD_PLL2_BASE, 3);
+        clk[VF610_CLK_PLL3_MAIN] = imx_clk_fixed_factor("pll3_main", "fast_clk_sel", 20, 1);
+        clk[VF610_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_main", PFD_PLL3_BASE, 0);
+        clk[VF610_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_main", PFD_PLL3_BASE, 1);
+        clk[VF610_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_main", PFD_PLL3_BASE, 2);
+        clk[VF610_CLK_PLL3_PFD4] = imx_clk_pfd("pll3_pfd4", "pll3_main", PFD_PLL3_BASE, 3);
+        clk[VF610_CLK_PLL4_MAIN] = imx_clk_fixed_factor("pll4_main", "fast_clk_sel", 25, 1);
+        /* Enet pll: fixed 50Mhz */
+        clk[VF610_CLK_PLL5_MAIN] = imx_clk_fixed_factor("pll5_main", "fast_clk_sel", 125, 6);
+        /* pll6: default 960Mhz */
+        clk[VF610_CLK_PLL6_MAIN] = imx_clk_fixed_factor("pll6_main", "fast_clk_sel", 40, 1);
+        clk[VF610_CLK_PLL1_PFD_SEL] = imx_clk_mux("pll1_pfd_sel", CCM_CCSR, 16, 3, pll1_sels, 5);
+        clk[VF610_CLK_PLL2_PFD_SEL] = imx_clk_mux("pll2_pfd_sel", CCM_CCSR, 19, 3, pll2_sels, 5);
+        clk[VF610_CLK_SYS_SEL] = imx_clk_mux("sys_sel", CCM_CCSR, 0, 3, sys_sels, ARRAY_SIZE(sys_sels));
+        clk[VF610_CLK_DDR_SEL] = imx_clk_mux("ddr_sel", CCM_CCSR, 6, 1, ddr_sels, ARRAY_SIZE(ddr_sels));
+        clk[VF610_CLK_SYS_BUS] = imx_clk_divider("sys_bus", "sys_sel", CCM_CACRR, 0, 3);
+        clk[VF610_CLK_PLATFORM_BUS] = imx_clk_divider("platform_bus", "sys_bus", CCM_CACRR, 3, 3);
+        clk[VF610_CLK_IPG_BUS] = imx_clk_divider("ipg_bus", "platform_bus", CCM_CACRR, 11, 2);
+        clk[VF610_CLK_PLL3_MAIN_DIV] = imx_clk_divider("pll3_main_div", "pll3_main", CCM_CACRR, 20, 1);
+        clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_main_div", "pll4_main", 0, CCM_CACRR, 6, 3, 0, pll4_main_div_table, &imx_ccm_lock);
+        clk[VF610_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_main_div", "pll6_main", CCM_CACRR, 21, 1);
+        clk[VF610_CLK_USBC0] = imx_clk_gate2("usbc0", "pll3_main", CCM_CCGR1, CCM_CCGRx_CGn(4));
+        clk[VF610_CLK_USBC1] = imx_clk_gate2("usbc1", "pll3_main", CCM_CCGR7, CCM_CCGRx_CGn(4));
+        clk[VF610_CLK_QSPI0_SEL] = imx_clk_mux("qspi0_sel", CCM_CSCMR1, 22, 2, qspi_sels, 4);
+        clk[VF610_CLK_QSPI0_EN] = imx_clk_gate("qspi0_en", "qspi0_sel", CCM_CSCDR3, 4);
+        clk[VF610_CLK_QSPI0_X4_DIV] = imx_clk_divider("qspi0_x4", "qspi0_en", CCM_CSCDR3, 0, 2);
+        clk[VF610_CLK_QSPI0_X2_DIV] = imx_clk_divider("qspi0_x2", "qspi0_x4", CCM_CSCDR3, 2, 1);
+        clk[VF610_CLK_QSPI0_X1_DIV] = imx_clk_divider("qspi0_x1", "qspi0_x2", CCM_CSCDR3, 3, 1);
+        clk[VF610_CLK_QSPI0] = imx_clk_gate2("qspi0", "qspi0_x1", CCM_CCGR2, CCM_CCGRx_CGn(4));
+        clk[VF610_CLK_QSPI1_SEL] = imx_clk_mux("qspi1_sel", CCM_CSCMR1, 24, 2, qspi_sels, 4);
+        clk[VF610_CLK_QSPI1_EN] = imx_clk_gate("qspi1_en", "qspi1_sel", CCM_CSCDR3, 12);
+        clk[VF610_CLK_QSPI1_X4_DIV] = imx_clk_divider("qspi1_x4", "qspi1_en", CCM_CSCDR3, 8, 2);
+        clk[VF610_CLK_QSPI1_X2_DIV] = imx_clk_divider("qspi1_x2", "qspi1_x4", CCM_CSCDR3, 10, 1);
+        clk[VF610_CLK_QSPI1_X1_DIV] = imx_clk_divider("qspi1_x1", "qspi1_x2", CCM_CSCDR3, 11, 1);
+        clk[VF610_CLK_QSPI1] = imx_clk_gate2("qspi1", "qspi1_x1", CCM_CCGR8, CCM_CCGRx_CGn(4));
+        clk[VF610_CLK_ENET_50M] = imx_clk_fixed_factor("enet_50m", "pll5_main", 1, 10);
+        clk[VF610_CLK_ENET_25M] = imx_clk_fixed_factor("enet_25m", "pll5_main", 1, 20);
+        clk[VF610_CLK_ENET_SEL] = imx_clk_mux("enet_sel", CCM_CSCMR2, 4, 2, rmii_sels, 4);
+        clk[VF610_CLK_ENET_TS_SEL] = imx_clk_mux("enet_ts_sel", CCM_CSCMR2, 0, 3, enet_ts_sels, 7);
+        clk[VF610_CLK_ENET] = imx_clk_gate("enet", "enet_sel", CCM_CSCDR1, 24);
+        clk[VF610_CLK_ENET_TS] = imx_clk_gate("enet_ts", "enet_ts_sel", CCM_CSCDR1, 23);
+        clk[VF610_CLK_ENET0] = imx_clk_gate2("enet0", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(0));
+        clk[VF610_CLK_ENET1] = imx_clk_gate2("enet1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(1));
+        clk[VF610_CLK_PIT] = imx_clk_gate2("pit", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(7));
+        clk[VF610_CLK_UART0] = imx_clk_gate2("uart0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(7));
+        clk[VF610_CLK_UART1] = imx_clk_gate2("uart1", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(8));
+        clk[VF610_CLK_UART2] = imx_clk_gate2("uart2", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(9));
+        clk[VF610_CLK_UART3] = imx_clk_gate2("uart3", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(10));
+        clk[VF610_CLK_I2C0] = imx_clk_gate2("i2c0", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(6));
+        clk[VF610_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(7));
+        clk[VF610_CLK_DSPI0] = imx_clk_gate2("dspi0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(12));
+        clk[VF610_CLK_DSPI1] = imx_clk_gate2("dspi1", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(13));
+        clk[VF610_CLK_DSPI2] = imx_clk_gate2("dspi2", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(12));
+        clk[VF610_CLK_DSPI3] = imx_clk_gate2("dspi3", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(13));
+        clk[VF610_CLK_WDT] = imx_clk_gate2("wdt", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(14));
+        clk[VF610_CLK_ESDHC0_SEL] = imx_clk_mux("esdhc0_sel", CCM_CSCMR1, 16, 2, esdhc_sels, 4);
+        clk[VF610_CLK_ESDHC0_EN] = imx_clk_gate("esdhc0_en", "esdhc0_sel", CCM_CSCDR2, 28);
+        clk[VF610_CLK_ESDHC0_DIV] = imx_clk_divider("esdhc0_div", "esdhc0_en", CCM_CSCDR2, 16, 4);
+        clk[VF610_CLK_ESDHC0] = imx_clk_gate2("eshc0", "esdhc0_div", CCM_CCGR7, CCM_CCGRx_CGn(1));
+        clk[VF610_CLK_ESDHC1_SEL] = imx_clk_mux("esdhc1_sel", CCM_CSCMR1, 18, 2, esdhc_sels, 4);
+        clk[VF610_CLK_ESDHC1_EN] = imx_clk_gate("esdhc1_en", "esdhc1_sel", CCM_CSCDR2, 29);
+        clk[VF610_CLK_ESDHC1_DIV] = imx_clk_divider("esdhc1_div", "esdhc1_en", CCM_CSCDR2, 20, 4);
+        clk[VF610_CLK_ESDHC1] = imx_clk_gate2("eshc1", "esdhc1_div", CCM_CCGR7, CCM_CCGRx_CGn(2));
+        /*
+         * ftm_ext_clk and ftm_fix_clk are FTM timer counter's
+         * selectable clock sources, both use a common enable bit
+         * in CCM_CSCDR1, selecting "dummy" clock as parent of
+         * "ftm0_ext_fix" make it serve only for enable/disable.
+         */
+        clk[VF610_CLK_FTM0_EXT_SEL] = imx_clk_mux("ftm0_ext_sel", CCM_CSCMR2, 6, 2, ftm_ext_sels, 4);
+        clk[VF610_CLK_FTM0_FIX_SEL] = imx_clk_mux("ftm0_fix_sel", CCM_CSCMR2, 14, 1, ftm_fix_sels, 2);
+        clk[VF610_CLK_FTM0_EXT_FIX_EN] = imx_clk_gate("ftm0_ext_fix_en", "dummy", CCM_CSCDR1, 25);
+        clk[VF610_CLK_FTM1_EXT_SEL] = imx_clk_mux("ftm1_ext_sel", CCM_CSCMR2, 8, 2, ftm_ext_sels, 4);
+        clk[VF610_CLK_FTM1_FIX_SEL] = imx_clk_mux("ftm1_fix_sel", CCM_CSCMR2, 15, 1, ftm_fix_sels, 2);
+        clk[VF610_CLK_FTM1_EXT_FIX_EN] = imx_clk_gate("ftm1_ext_fix_en", "dummy", CCM_CSCDR1, 26);
+        clk[VF610_CLK_FTM2_EXT_SEL] = imx_clk_mux("ftm2_ext_sel", CCM_CSCMR2, 10, 2, ftm_ext_sels, 4);
+        clk[VF610_CLK_FTM2_FIX_SEL] = imx_clk_mux("ftm2_fix_sel", CCM_CSCMR2, 16, 1, ftm_fix_sels, 2);
+        clk[VF610_CLK_FTM2_EXT_FIX_EN] = imx_clk_gate("ftm2_ext_fix_en", "dummy", CCM_CSCDR1, 27);
+        clk[VF610_CLK_FTM3_EXT_SEL] = imx_clk_mux("ftm3_ext_sel", CCM_CSCMR2, 12, 2, ftm_ext_sels, 4);
+        clk[VF610_CLK_FTM3_FIX_SEL] = imx_clk_mux("ftm3_fix_sel", CCM_CSCMR2, 17, 1, ftm_fix_sels, 2);
+        clk[VF610_CLK_FTM3_EXT_FIX_EN] = imx_clk_gate("ftm3_ext_fix_en", "dummy", CCM_CSCDR1, 28);
+        /* ftm(n)_clk are FTM module operation clock */
+        clk[VF610_CLK_FTM0] = imx_clk_gate2("ftm0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(8));
+        clk[VF610_CLK_FTM1] = imx_clk_gate2("ftm1", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(9));
+        clk[VF610_CLK_FTM2] = imx_clk_gate2("ftm2", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(8));
+        clk[VF610_CLK_FTM3] = imx_clk_gate2("ftm3", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(9));
+        clk[VF610_CLK_DCU0_SEL] = imx_clk_mux("dcu0_sel", CCM_CSCMR1, 28, 1, dcu_sels, 2);
+        clk[VF610_CLK_DCU0_EN] = imx_clk_gate("dcu0_en", "dcu0_sel", CCM_CSCDR3, 19);
+        clk[VF610_CLK_DCU0_DIV] = imx_clk_divider("dcu0_div", "dcu0_en", CCM_CSCDR3, 16, 3);
+        clk[VF610_CLK_DCU0] = imx_clk_gate2("dcu0", "dcu0_div", CCM_CCGR3, CCM_CCGRx_CGn(8));
+        clk[VF610_CLK_DCU1_SEL] = imx_clk_mux("dcu1_sel", CCM_CSCMR1, 29, 1, dcu_sels, 2);
+        clk[VF610_CLK_DCU1_EN] = imx_clk_gate("dcu1_en", "dcu1_sel", CCM_CSCDR3, 23);
+        clk[VF610_CLK_DCU1_DIV] = imx_clk_divider("dcu1_div", "dcu1_en", CCM_CSCDR3, 20, 3);
+        clk[VF610_CLK_DCU1] = imx_clk_gate2("dcu1", "dcu1_div", CCM_CCGR9, CCM_CCGRx_CGn(8));
+        clk[VF610_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", CCM_CSCMR1, 20, 2, esai_sels, 4);
+        clk[VF610_CLK_ESAI_EN] = imx_clk_gate("esai_en", "esai_sel", CCM_CSCDR2, 30);
+        clk[VF610_CLK_ESAI_DIV] = imx_clk_divider("esai_div", "esai_en", CCM_CSCDR2, 24, 4);
+        clk[VF610_CLK_ESAI] = imx_clk_gate2("esai", "esai_div", CCM_CCGR4, CCM_CCGRx_CGn(2));
+        clk[VF610_CLK_SAI0_SEL] = imx_clk_mux("sai0_sel", CCM_CSCMR1, 0, 2, sai_sels, 4);
+        clk[VF610_CLK_SAI0_EN] = imx_clk_gate("sai0_en", "sai0_sel", CCM_CSCDR1, 16);
+        clk[VF610_CLK_SAI0_DIV] = imx_clk_divider("sai0_div", "sai0_en", CCM_CSCDR1, 0, 4);
+        clk[VF610_CLK_SAI0] = imx_clk_gate2("sai0", "sai0_div", CCM_CCGR0, CCM_CCGRx_CGn(15));
+        clk[VF610_CLK_SAI1_SEL] = imx_clk_mux("sai1_sel", CCM_CSCMR1, 2, 2, sai_sels, 4);
+        clk[VF610_CLK_SAI1_EN] = imx_clk_gate("sai1_en", "sai1_sel", CCM_CSCDR1, 17);
+        clk[VF610_CLK_SAI1_DIV] = imx_clk_divider("sai1_div", "sai1_en", CCM_CSCDR1, 4, 4);
+        clk[VF610_CLK_SAI1] = imx_clk_gate2("sai1", "sai1_div", CCM_CCGR1, CCM_CCGRx_CGn(0));
+        clk[VF610_CLK_SAI2_SEL] = imx_clk_mux("sai2_sel", CCM_CSCMR1, 4, 2, sai_sels, 4);
+        clk[VF610_CLK_SAI2_EN] = imx_clk_gate("sai2_en", "sai2_sel", CCM_CSCDR1, 18);
+        clk[VF610_CLK_SAI2_DIV] = imx_clk_divider("sai2_div", "sai2_en", CCM_CSCDR1, 8, 4);
+        clk[VF610_CLK_SAI2] = imx_clk_gate2("sai2", "sai2_div", CCM_CCGR1, CCM_CCGRx_CGn(1));
+        clk[VF610_CLK_SAI3_SEL] = imx_clk_mux("sai3_sel", CCM_CSCMR1, 6, 2, sai_sels, 4);
+        clk[VF610_CLK_SAI3_EN] = imx_clk_gate("sai3_en", "sai3_sel", CCM_CSCDR1, 19);
+        clk[VF610_CLK_SAI3_DIV] = imx_clk_divider("sai3_div", "sai3_en", CCM_CSCDR1, 12, 4);
+        clk[VF610_CLK_SAI3] = imx_clk_gate2("sai3", "sai3_div", CCM_CCGR1, CCM_CCGRx_CGn(2));
+        clk[VF610_CLK_NFC_SEL] = imx_clk_mux("nfc_sel", CCM_CSCMR1, 12, 2, nfc_sels, 4);
+        clk[VF610_CLK_NFC_EN] = imx_clk_gate("nfc_en", "nfc_sel", CCM_CSCDR2, 9);
+        clk[VF610_CLK_NFC_PRE_DIV] = imx_clk_divider("nfc_pre_div", "nfc_en", CCM_CSCDR3, 13, 3);
+        clk[VF610_CLK_NFC_FRAC_DIV] = imx_clk_divider("nfc_frac_div", "nfc_pre_div", CCM_CSCDR2, 4, 4);
+        clk[VF610_CLK_NFC] = imx_clk_gate2("nfc", "nfc_frac_div", CCM_CCGR10, CCM_CCGRx_CGn(0));
+        clk[VF610_CLK_GPU_SEL] = imx_clk_mux("gpu_sel", CCM_CSCMR1, 14, 1, gpu_sels, 2);
+        clk[VF610_CLK_GPU_EN] = imx_clk_gate("gpu_en", "gpu_sel", CCM_CSCDR2, 10);
+        clk[VF610_CLK_GPU2D] = imx_clk_gate2("gpu", "gpu_en", CCM_CCGR8, CCM_CCGRx_CGn(15));
+        clk[VF610_CLK_VADC_SEL] = imx_clk_mux("vadc_sel", CCM_CSCMR1, 8, 2, vadc_sels, 3);
+        clk[VF610_CLK_VADC_EN] = imx_clk_gate("vadc_en", "vadc_sel", CCM_CSCDR1, 22);
+        clk[VF610_CLK_VADC_DIV] = imx_clk_divider("vadc_div", "vadc_en", CCM_CSCDR1, 20, 2);
+        clk[VF610_CLK_VADC_DIV_HALF] = imx_clk_fixed_factor("vadc_div_half", "vadc_div", 1, 2);
+        clk[VF610_CLK_VADC] = imx_clk_gate2("vadc", "vadc_div", CCM_CCGR8, CCM_CCGRx_CGn(7));
+        clk[VF610_CLK_ADC0] = imx_clk_gate2("adc0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(11));
+        clk[VF610_CLK_ADC1] = imx_clk_gate2("adc1", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(11));
+        clk[VF610_CLK_DAC0] = imx_clk_gate2("dac0", "ipg_bus", CCM_CCGR8, CCM_CCGRx_CGn(12));
+        clk[VF610_CLK_DAC1] = imx_clk_gate2("dac1", "ipg_bus", CCM_CCGR8, CCM_CCGRx_CGn(13));
+        clk[VF610_CLK_ASRC] = imx_clk_gate2("asrc", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(1));
+        clk[VF610_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(0));
+        clk[VF610_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(4));
+        clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]);
+        clk_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2);
+        clk_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2);
+        clk_set_rate(clk[VF610_CLK_QSPI0_X1_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X2_DIV]) / 2);
+        clk_set_parent(clk[VF610_CLK_QSPI1_SEL], clk[VF610_CLK_PLL1_PFD4]);
+        clk_set_rate(clk[VF610_CLK_QSPI1_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_SEL]) / 2);
+        clk_set_rate(clk[VF610_CLK_QSPI1_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_X4_DIV]) / 2);
+        clk_set_rate(clk[VF610_CLK_QSPI1_X1_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_X2_DIV]) / 2);
+        clk_set_parent(clk[VF610_CLK_SAI0_SEL], clk[VF610_CLK_AUDIO_EXT]);
+        clk_set_parent(clk[VF610_CLK_SAI1_SEL], clk[VF610_CLK_AUDIO_EXT]);
+        clk_set_parent(clk[VF610_CLK_SAI2_SEL], clk[VF610_CLK_AUDIO_EXT]);
+        clk_set_parent(clk[VF610_CLK_SAI3_SEL], clk[VF610_CLK_AUDIO_EXT]);
+        /* Add the clocks to provider list */
+        clk_data.clks = clk;
+        clk_data.clk_num = ARRAY_SIZE(clk);
+        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+}
+CLK_OF_DECLARE(vf610, "fsl,vf610-ccm", vf610_clocks_init);
diff --git a/arch/arm/mach-imx/clk.c b/arch/arm/mach-imx/clk.c
index 37e884ed1cd4..55bc80a00666 100644
--- a/arch/arm/mach-imx/clk.c
+++ b/arch/arm/mach-imx/clk.c
@@ -1,4 +1,39 @@
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/slab.h>
 #include <linux/spinlock.h>
 #include "clk.h"
 DEFINE_SPINLOCK(imx_ccm_lock);
+static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name)
+{
+        struct of_phandle_args phandle;
+        struct clk *clk = ERR_PTR(-ENODEV);
+        char *path;
+        path = kasprintf(GFP_KERNEL, "/clocks/%s", name);
+        if (!path)
+                return ERR_PTR(-ENOMEM);
+        phandle.np = of_find_node_by_path(path);
+        kfree(path);
+        if (phandle.np) {
+                clk = of_clk_get_from_provider(&phandle);
+                of_node_put(phandle.np);
+        }
+        return clk;
+}
+struct clk * __init imx_obtain_fixed_clock(
+                        const char *name, unsigned long rate)
+{
+        struct clk *clk;
+        clk = imx_obtain_fixed_clock_from_dt(name);
+        if (IS_ERR(clk))
+                clk = imx_clk_fixed(name, rate);
+        return clk;
+}
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index d9d9d9c66dff..0e4e8bb261b9 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -18,7 +18,6 @@ enum imx_pllv3_type {
        IMX_PLLV3_USB,
        IMX_PLLV3_AV,
        IMX_PLLV3_ENET,
-        IMX_PLLV3_MLB,
 };
 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
@@ -29,6 +28,9 @@ struct clk *clk_register_gate2(struct device *dev, const char *name,
                void __iomem *reg, u8 bit_idx,
                u8 clk_gate_flags, spinlock_t *lock);
+struct clk * imx_obtain_fixed_clock(
+                        const char *name, unsigned long rate);
 static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
                void __iomem *reg, u8 shift)
 {
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index c08ae3f99cee..cb6c838b63ed 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -11,6 +11,8 @@
 #ifndef __ASM_ARCH_MXC_COMMON_H__
 #define __ASM_ARCH_MXC_COMMON_H__
+#include <linux/reboot.h>
 struct platform_device;
 struct pt_regs;
 struct clk;
@@ -68,12 +70,12 @@ extern int mx27_clocks_init_dt(void);
 extern int mx31_clocks_init_dt(void);
 extern int mx51_clocks_init_dt(void);
 extern int mx53_clocks_init_dt(void);
-extern int mx6q_clocks_init(void);
 extern struct platform_device *mxc_register_gpio(char *name, int id,
        resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
 extern void mxc_set_cpu_type(unsigned int type);
-extern void mxc_restart(char, const char *);
+extern void mxc_restart(enum reboot_mode, const char *);
 extern void mxc_arch_reset_init(void __iomem *);
+extern void mxc_arch_reset_init_dt(void);
 extern int mx53_revision(void);
 extern int imx6q_revision(void);
 extern int mx53_display_revision(void);
diff --git a/arch/arm/mach-imx/devices-imx25.h b/arch/arm/mach-imx/devices-imx25.h
index 0d2922bc575c..769563fdeaa0 100644
--- a/arch/arm/mach-imx/devices-imx25.h
+++ b/arch/arm/mach-imx/devices-imx25.h
@@ -13,10 +13,10 @@ extern const struct imx_fec_data imx25_fec_data;
        imx_add_fec(&imx25_fec_data, pdata)
 extern const struct imx_flexcan_data imx25_flexcan_data[];
-#define imx25_add_flexcan(id, pdata)    \
+#define imx25_add_flexcan(id)   \
-        imx_add_flexcan(&imx25_flexcan_data[id], pdata)
+        imx_add_flexcan(&imx25_flexcan_data[id])
-#define imx25_add_flexcan0(pdata)       imx25_add_flexcan(0, pdata)
+#define imx25_add_flexcan0()            imx25_add_flexcan(0)
-#define imx25_add_flexcan1(pdata)       imx25_add_flexcan(1, pdata)
+#define imx25_add_flexcan1()            imx25_add_flexcan(1)
 extern const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data;
 #define imx25_add_fsl_usb2_udc(pdata)   \
diff --git a/arch/arm/mach-imx/devices-imx35.h b/arch/arm/mach-imx/devices-imx35.h
index e2675f1b141c..780d8240281b 100644
--- a/arch/arm/mach-imx/devices-imx35.h
+++ b/arch/arm/mach-imx/devices-imx35.h
@@ -17,10 +17,10 @@ extern const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data;
        imx_add_fsl_usb2_udc(&imx35_fsl_usb2_udc_data, pdata)
 extern const struct imx_flexcan_data imx35_flexcan_data[];
-#define imx35_add_flexcan(id, pdata)    \
+#define imx35_add_flexcan(id)   \
-        imx_add_flexcan(&imx35_flexcan_data[id], pdata)
+        imx_add_flexcan(&imx35_flexcan_data[id])
-#define imx35_add_flexcan0(pdata)       imx35_add_flexcan(0, pdata)
+#define imx35_add_flexcan0()            imx35_add_flexcan(0)
-#define imx35_add_flexcan1(pdata)       imx35_add_flexcan(1, pdata)
+#define imx35_add_flexcan1()            imx35_add_flexcan(1)
 extern const struct imx_imx2_wdt_data imx35_imx2_wdt_data;
 #define imx35_add_imx2_wdt()       \
diff --git a/arch/arm/mach-imx/devices/Kconfig b/arch/arm/mach-imx/devices/Kconfig
index 3dd2b1b041d1..68c74fb0373c 100644
--- a/arch/arm/mach-imx/devices/Kconfig
+++ b/arch/arm/mach-imx/devices/Kconfig
@@ -4,7 +4,6 @@ config IMX_HAVE_PLATFORM_FEC
 config IMX_HAVE_PLATFORM_FLEXCAN
        bool
-        select HAVE_CAN_FLEXCAN if CAN
 config IMX_HAVE_PLATFORM_FSL_USB2_UDC
        bool
diff --git a/arch/arm/mach-imx/devices/devices-common.h b/arch/arm/mach-imx/devices/devices-common.h
index 453e20bc2657..c13b76b9f6b3 100644
--- a/arch/arm/mach-imx/devices/devices-common.h
+++ b/arch/arm/mach-imx/devices/devices-common.h
@@ -50,7 +50,6 @@ struct platform_device *__init imx_add_fec(
                const struct imx_fec_data *data,
                const struct fec_platform_data *pdata);
-#include <linux/can/platform/flexcan.h>
 struct imx_flexcan_data {
        int id;
        resource_size_t iobase;
@@ -58,8 +57,7 @@ struct imx_flexcan_data {
        resource_size_t irq;
 };
 struct platform_device *__init imx_add_flexcan(
-                const struct imx_flexcan_data *data,
+                const struct imx_flexcan_data *data);
-                const struct flexcan_platform_data *pdata);
 #include <linux/fsl_devices.h>
 struct imx_fsl_usb2_udc_data {
diff --git a/arch/arm/mach-imx/devices/platform-flexcan.c b/arch/arm/mach-imx/devices/platform-flexcan.c
index 1078bf0a94ef..55d61eaf63c6 100644
--- a/arch/arm/mach-imx/devices/platform-flexcan.c
+++ b/arch/arm/mach-imx/devices/platform-flexcan.c
@@ -38,8 +38,7 @@ const struct imx_flexcan_data imx35_flexcan_data[] __initconst = {
 #endif /* ifdef CONFIG_SOC_IMX35 */
 struct platform_device *__init imx_add_flexcan(
-                const struct imx_flexcan_data *data,
+                const struct imx_flexcan_data *data)
-                const struct flexcan_platform_data *pdata)
 {
        struct resource res[] = {
                {
@@ -54,5 +53,5 @@ struct platform_device *__init imx_add_flexcan(
        };
        return imx_add_platform_device("flexcan", data->id,
-                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
+                        res, ARRAY_SIZE(res), NULL, 0);
 }
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
index e2b70f4c1a2c..e77cc3af6db2 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
@@ -279,7 +279,7 @@ void __init eukrea_mbimxsd25_baseboard_init(void)
        imx25_add_imx_fb(&eukrea_mximxsd_fb_pdata);
        imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
-        imx25_add_flexcan1(NULL);
+        imx25_add_flexcan1();
        imx25_add_sdhci_esdhc_imx(0, &sd1_pdata);
        gpio_request(GPIO_LED1, "LED1");
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
index 5a2d5ef12dd5..14d6c8249b76 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
@@ -287,7 +287,7 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
        imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
-        imx35_add_flexcan1(NULL);
+        imx35_add_flexcan1();
        imx35_add_sdhci_esdhc_imx(0, &sd1_pdata);
        gpio_request(GPIO_LED1, "LED1");
diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h
index 356131f7b591..a3b0b04b45c9 100644
--- a/arch/arm/mach-imx/hardware.h
+++ b/arch/arm/mach-imx/hardware.h
@@ -20,6 +20,7 @@
 #ifndef __ASM_ARCH_MXC_HARDWARE_H__
 #define __ASM_ARCH_MXC_HARDWARE_H__
+#include <asm/io.h>
 #include <asm/sizes.h>
 #define addr_in_module(addr, mod) \
diff --git a/arch/arm/mach-imx/imx25-dt.c b/arch/arm/mach-imx/imx25-dt.c
index 82348391582a..3e1ec5ffe630 100644
--- a/arch/arm/mach-imx/imx25-dt.c
+++ b/arch/arm/mach-imx/imx25-dt.c
@@ -19,6 +19,8 @@
 static void __init imx25_dt_init(void)
 {
+        mxc_arch_reset_init_dt();
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
index 4aaead0a77ff..4e235ecb4021 100644
--- a/arch/arm/mach-imx/imx27-dt.c
+++ b/arch/arm/mach-imx/imx27-dt.c
@@ -22,6 +22,8 @@ static void __init imx27_dt_init(void)
 {
        struct platform_device_info devinfo = { .name = "cpufreq-cpu0", };
+        mxc_arch_reset_init_dt();
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
        platform_device_register_full(&devinfo);
diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c
index 67de611e29ab..818a1cc2fe45 100644
--- a/arch/arm/mach-imx/imx31-dt.c
+++ b/arch/arm/mach-imx/imx31-dt.c
@@ -20,6 +20,8 @@
 static void __init imx31_dt_init(void)
 {
+        mxc_arch_reset_init_dt();
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index ab24cc322111..53e43e579dd7 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -23,6 +23,8 @@ static void __init imx51_dt_init(void)
 {
        struct platform_device_info devinfo = { .name = "cpufreq-cpu0", };
+        mxc_arch_reset_init_dt();
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
        platform_device_register_full(&devinfo);
 }
diff --git a/arch/arm/mach-imx/irq-common.c b/arch/arm/mach-imx/irq-common.c
index 4b34f52dc46b..0a920d184867 100644
--- a/arch/arm/mach-imx/irq-common.c
+++ b/arch/arm/mach-imx/irq-common.c
@@ -18,6 +18,7 @@
 #include <linux/module.h>
 #include <linux/irq.h>
+#include <linux/platform_data/asoc-imx-ssi.h>
 #include "irq-common.h"
diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c
index f579c616feed..98c58944015a 100644
--- a/arch/arm/mach-imx/mach-imx53.c
+++ b/arch/arm/mach-imx/mach-imx53.c
@@ -21,25 +21,12 @@
 #include <asm/mach/time.h>
 #include "common.h"
+#include "hardware.h"
 #include "mx53.h"
-static void __init imx53_qsb_init(void)
-{
-        struct clk *clk;
-        clk = clk_get_sys(NULL, "ssi_ext1");
-        if (IS_ERR(clk)) {
-                pr_err("failed to get clk ssi_ext1\n");
-                return;
-        }
-        clk_register_clkdev(clk, NULL, "0-000a");
-}
 static void __init imx53_dt_init(void)
 {
-        if (of_machine_is_compatible("fsl,imx53-qsb"))
+        mxc_arch_reset_init_dt();
-                imx53_qsb_init();
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 5536fd81379a..7be13f8e69a0 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -11,6 +11,7 @@
 */
 #include <linux/clk.h>
+#include <linux/clk-provider.h>
 #include <linux/clkdev.h>
 #include <linux/clocksource.h>
 #include <linux/cpu.h>
@@ -26,6 +27,7 @@
 #include <linux/of_platform.h>
 #include <linux/opp.h>
 #include <linux/phy.h>
+#include <linux/reboot.h>
 #include <linux/regmap.h>
 #include <linux/micrel_phy.h>
 #include <linux/mfd/syscon.h>
@@ -66,7 +68,7 @@ static void __init imx6q_init_revision(void)
        mxc_set_cpu_type(rev >> 16 & 0xff);
 }
-static void imx6q_restart(char mode, const char *cmd)
+static void imx6q_restart(enum reboot_mode mode, const char *cmd)
 {
        struct device_node *np;
        void __iomem *wdog_base;
@@ -145,6 +147,45 @@ static void __init imx6q_sabrelite_init(void)
        imx6q_sabrelite_cko1_setup();
 }
+static void __init imx6q_sabresd_cko1_setup(void)
+{
+        struct clk *cko1_sel, *pll4, *pll4_post, *cko1;
+        unsigned long rate;
+        cko1_sel = clk_get_sys(NULL, "cko1_sel");
+        pll4 = clk_get_sys(NULL, "pll4_audio");
+        pll4_post = clk_get_sys(NULL, "pll4_post_div");
+        cko1 = clk_get_sys(NULL, "cko1");
+        if (IS_ERR(cko1_sel) || IS_ERR(pll4)
+                        || IS_ERR(pll4_post) || IS_ERR(cko1)) {
+                pr_err("cko1 setup failed!\n");
+                goto put_clk;
+        }
+        /*
+         * Setting pll4 at 768MHz (24MHz * 32)
+         * So its child clock can get 24MHz easily
+         */
+        clk_set_rate(pll4, 768000000);
+        clk_set_parent(cko1_sel, pll4_post);
+        rate = clk_round_rate(cko1, 24000000);
+        clk_set_rate(cko1, rate);
+put_clk:
+        if (!IS_ERR(cko1_sel))
+                clk_put(cko1_sel);
+        if (!IS_ERR(pll4_post))
+                clk_put(pll4_post);
+        if (!IS_ERR(pll4))
+                clk_put(pll4);
+        if (!IS_ERR(cko1))
+                clk_put(cko1);
+}
+static void __init imx6q_sabresd_init(void)
+{
+        imx6q_sabresd_cko1_setup();
+}
 static void __init imx6q_1588_init(void)
 {
        struct regmap *gpr;
@@ -165,6 +206,9 @@ static void __init imx6q_init_machine(void)
 {
        if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
                imx6q_sabrelite_init();
+        else if (of_machine_is_compatible("fsl,imx6q-sabresd") ||
+                        of_machine_is_compatible("fsl,imx6dl-sabresd"))
+                imx6q_sabresd_init();
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
@@ -253,10 +297,44 @@ static void __init imx6q_map_io(void)
        imx_scu_map_io();
 }
+#ifdef CONFIG_CACHE_L2X0
+static void __init imx6q_init_l2cache(void)
+{
+        void __iomem *l2x0_base;
+        struct device_node *np;
+        unsigned int val;
+        np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
+        if (!np)
+                goto out;
+        l2x0_base = of_iomap(np, 0);
+        if (!l2x0_base) {
+                of_node_put(np);
+                goto out;
+        }
+        /* Configure the L2 PREFETCH and POWER registers */
+        val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
+        val |= 0x70800000;
+        writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL);
+        val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN;
+        writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL);
+        iounmap(l2x0_base);
+        of_node_put(np);
+out:
+        l2x0_of_init(0, ~0UL);
+}
+#else
+static inline void imx6q_init_l2cache(void) {}
+#endif
 static void __init imx6q_init_irq(void)
 {
        imx6q_init_revision();
-        l2x0_of_init(0, ~0UL);
+        imx6q_init_l2cache();
        imx_src_init();
        imx_gpc_init();
        irqchip_init();
@@ -264,7 +342,7 @@ static void __init imx6q_init_irq(void)
 static void __init imx6q_timer_init(void)
 {
-        mx6q_clocks_init();
+        of_clk_init(NULL);
        clocksource_of_init();
        imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
                              imx6q_revision());
diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c
new file mode 100644
index 000000000000..132db2609507
--- /dev/null
+++ b/arch/arm/mach-imx/mach-imx6sl.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/clk-provider.h>
+#include <linux/irqchip.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include "common.h"
+static void __init imx6sl_init_machine(void)
+{
+        mxc_arch_reset_init_dt();
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+static void __init imx6sl_init_irq(void)
+{
+        l2x0_of_init(0, ~0UL);
+        imx_src_init();
+        imx_gpc_init();
+        irqchip_init();
+}
+static void __init imx6sl_timer_init(void)
+{
+        of_clk_init(NULL);
+}
+static const char *imx6sl_dt_compat[] __initdata = {
+        "fsl,imx6sl",
+        NULL,
+};
+DT_MACHINE_START(IMX6SL, "Freescale i.MX6 SoloLite (Device Tree)")
+        .map_io         = debug_ll_io_init,
+        .init_irq       = imx6sl_init_irq,
+        .init_time      = imx6sl_timer_init,
+        .init_machine   = imx6sl_init_machine,
+        .dt_compat      = imx6sl_dt_compat,
+        .restart        = mxc_restart,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c
index 8bcda688a006..13490c203050 100644
--- a/arch/arm/mach-imx/mach-mx25_3ds.c
+++ b/arch/arm/mach-imx/mach-mx25_3ds.c
@@ -249,7 +249,7 @@ static void __init mx25pdk_init(void)
        imx25_add_imx_i2c0(&mx25_3ds_i2c0_data);
        gpio_request_one(MX25PDK_CAN_PWDN, GPIOF_OUT_INIT_LOW, "can-pwdn");
-        imx25_add_flexcan0(NULL);
+        imx25_add_flexcan0();
 }
 static void __init mx25pdk_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index dae4cd7be040..6f424eced181 100644
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -268,10 +268,11 @@ static struct mc13xxx_led_platform_data moboard_led[] = {
 static struct mc13xxx_leds_platform_data moboard_leds = {
        .num_leds = ARRAY_SIZE(moboard_led),
        .led = moboard_led,
-        .flags = MC13783_LED_SLEWLIMTC,
+        .led_control[0] = MC13783_LED_C0_ENABLE | MC13783_LED_C0_ABMODE(0),
-        .abmode = MC13783_LED_AB_DISABLED,
+        .led_control[1] = MC13783_LED_C1_SLEWLIM,
-        .tc1_period = MC13783_LED_PERIOD_10MS,
+        .led_control[2] = MC13783_LED_C2_SLEWLIM,
-        .tc2_period = MC13783_LED_PERIOD_10MS,
+        .led_control[3] = MC13783_LED_C3_PERIOD(0),
+        .led_control[4] = MC13783_LED_C3_PERIOD(0),
 };
 static struct mc13xxx_buttons_platform_data moboard_buttons = {
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index b8b15bb1ffdf..19bb6441a7d4 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -398,8 +398,8 @@ static void __init pca100_init(void)
                imx27_add_fsl_usb2_udc(&otg_device_pdata);
        }
-        usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+        usbh2_pdata.otg = imx_otg_ulpi_create(
-                                ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
+                        ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
        if (usbh2_pdata.otg)
                imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c
index 8ed533f0f8ca..b726cb1c5fdd 100644
--- a/arch/arm/mach-imx/mach-pcm043.c
+++ b/arch/arm/mach-imx/mach-pcm043.c
@@ -385,7 +385,7 @@ static void __init pcm043_init(void)
        if (!otg_mode_host)
                imx35_add_fsl_usb2_udc(&otg_device_pdata);
-        imx35_add_flexcan1(NULL);
+        imx35_add_flexcan1();
        imx35_add_sdhci_esdhc_imx(0, &sd1_pdata);
 }
diff --git a/arch/arm/mach-imx/mach-vf610.c b/arch/arm/mach-imx/mach-vf610.c
new file mode 100644
index 000000000000..816991deb9b8
--- /dev/null
+++ b/arch/arm/mach-imx/mach-vf610.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/of_platform.h>
+#include <linux/clocksource.h>
+#include <linux/irqchip.h>
+#include <linux/clk-provider.h>
+#include <asm/mach/arch.h>
+#include <asm/hardware/cache-l2x0.h>
+#include "common.h"
+static void __init vf610_init_machine(void)
+{
+        mxc_arch_reset_init_dt();
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+static void __init vf610_init_irq(void)
+{
+        l2x0_of_init(0, ~0UL);
+        irqchip_init();
+}
+static void __init vf610_init_time(void)
+{
+        of_clk_init(NULL);
+        clocksource_of_init();
+}
+static const char *vf610_dt_compat[] __initdata = {
+        "fsl,vf610",
+        NULL,
+};
+DT_MACHINE_START(VYBRID_VF610, "Freescale Vybrid VF610 (Device Tree)")
+        .init_irq       = vf610_init_irq,
+        .init_time      = vf610_init_time,
+        .init_machine   = vf610_init_machine,
+        .dt_compat      = vf610_dt_compat,
+        .restart        = mxc_restart,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c
index 3c609c52d3eb..e065fedb3ad4 100644
--- a/arch/arm/mach-imx/mm-imx1.c
+++ b/arch/arm/mach-imx/mm-imx1.c
@@ -39,7 +39,6 @@ void __init mx1_map_io(void)
 void __init imx1_init_early(void)
 {
        mxc_set_cpu_type(MXC_CPU_MX1);
-        mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR));
        imx_iomuxv1_init(MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
                        MX1_NUM_GPIO_PORT);
 }
@@ -51,6 +50,7 @@ void __init mx1_init_irq(void)
 void __init imx1_soc_init(void)
 {
+        mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR));
        mxc_device_init();
        mxc_register_gpio("imx1-gpio", 0, MX1_GPIO1_BASE_ADDR, SZ_256,
diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
index d8ccd3a8ec53..2e91ab2ca378 100644
--- a/arch/arm/mach-imx/mm-imx21.c
+++ b/arch/arm/mach-imx/mm-imx21.c
@@ -66,7 +66,6 @@ void __init mx21_map_io(void)
 void __init imx21_init_early(void)
 {
        mxc_set_cpu_type(MXC_CPU_MX21);
-        mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR));
        imx_iomuxv1_init(MX21_IO_ADDRESS(MX21_GPIO_BASE_ADDR),
                        MX21_NUM_GPIO_PORT);
 }
@@ -82,6 +81,7 @@ static const struct resource imx21_audmux_res[] __initconst = {
 void __init imx21_soc_init(void)
 {
+        mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR));
        mxc_device_init();
        mxc_register_gpio("imx21-gpio", 0, MX21_GPIO1_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c
index 9357707bb7af..e065c117f5a6 100644
--- a/arch/arm/mach-imx/mm-imx25.c
+++ b/arch/arm/mach-imx/mm-imx25.c
@@ -54,7 +54,6 @@ void __init imx25_init_early(void)
 {
        mxc_set_cpu_type(MXC_CPU_MX25);
        mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR));
-        mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
 }
 void __init mx25_init_irq(void)
@@ -89,6 +88,7 @@ static const struct resource imx25_audmux_res[] __initconst = {
 void __init imx25_soc_init(void)
 {
+        mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
        mxc_device_init();
        /* i.mx25 has the i.mx35 type gpio */
diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
index 4f1be65a7b5f..7d82a5a5b16b 100644
--- a/arch/arm/mach-imx/mm-imx27.c
+++ b/arch/arm/mach-imx/mm-imx27.c
@@ -66,7 +66,6 @@ void __init mx27_map_io(void)
 void __init imx27_init_early(void)
 {
        mxc_set_cpu_type(MXC_CPU_MX27);
-        mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR));
        imx_iomuxv1_init(MX27_IO_ADDRESS(MX27_GPIO_BASE_ADDR),
                        MX27_NUM_GPIO_PORT);
 }
@@ -82,6 +81,7 @@ static const struct resource imx27_audmux_res[] __initconst = {
 void __init imx27_soc_init(void)
 {
+        mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR));
        mxc_device_init();
        /* i.mx27 has the i.mx21 type gpio */
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index e0e69a682174..0884ca90d15a 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -65,7 +65,7 @@ static void imx3_idle(void)
                : "=r" (reg));
 }
-static void __iomem *imx3_ioremap_caller(unsigned long phys_addr, size_t size,
+static void __iomem *imx3_ioremap_caller(phys_addr_t phys_addr, size_t size,
                                         unsigned int mtype, void *caller)
 {
        if (mtype == MT_DEVICE) {
@@ -138,7 +138,6 @@ void __init mx31_map_io(void)
 void __init imx31_init_early(void)
 {
        mxc_set_cpu_type(MXC_CPU_MX31);
-        mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
        arch_ioremap_caller = imx3_ioremap_caller;
        arm_pm_idle = imx3_idle;
        mx3_ccm_base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
@@ -174,6 +173,7 @@ void __init imx31_soc_init(void)
        imx3_init_l2x0();
+        mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
        mxc_device_init();
        mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
@@ -216,7 +216,6 @@ void __init imx35_init_early(void)
 {
        mxc_set_cpu_type(MXC_CPU_MX35);
        mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
-        mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
        arm_pm_idle = imx3_idle;
        arch_ioremap_caller = imx3_ioremap_caller;
        mx3_ccm_base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR);
@@ -272,6 +271,7 @@ void __init imx35_soc_init(void)
        imx3_init_l2x0();
+        mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
        mxc_device_init();
        mxc_register_gpio("imx35-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index b7c4e70e5081..cf193d87274a 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -83,7 +83,6 @@ void __init imx51_init_early(void)
        imx51_ipu_mipi_setup();
        mxc_set_cpu_type(MXC_CPU_MX51);
        mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
-        mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
        imx_src_init();
 }
@@ -91,7 +90,6 @@ void __init imx53_init_early(void)
 {
        mxc_set_cpu_type(MXC_CPU_MX53);
        mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
-        mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
        imx_src_init();
 }
@@ -129,6 +127,7 @@ static const struct resource imx51_audmux_res[] __initconst = {
 void __init imx51_soc_init(void)
 {
+        mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
        mxc_device_init();
        /* i.mx51 has the i.mx35 type gpio */
diff --git a/arch/arm/mach-imx/mx27.h b/arch/arm/mach-imx/mx27.h
index e074616d54ca..8a65f192e7f3 100644
--- a/arch/arm/mach-imx/mx27.h
+++ b/arch/arm/mach-imx/mx27.h
@@ -135,7 +135,7 @@
 #define MX27_INT_GPT4           (NR_IRQS_LEGACY + 4)
 #define MX27_INT_RTIC           (NR_IRQS_LEGACY + 5)
 #define MX27_INT_CSPI3          (NR_IRQS_LEGACY + 6)
-#define MX27_INT_SDHC           (NR_IRQS_LEGACY + 7)
+#define MX27_INT_MSHC           (NR_IRQS_LEGACY + 7)
 #define MX27_INT_GPIO           (NR_IRQS_LEGACY + 8)
 #define MX27_INT_SDHC3          (NR_IRQS_LEGACY + 9)
 #define MX27_INT_SDHC2          (NR_IRQS_LEGACY + 10)
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
index c6e1ab544882..1f24c1fdfea4 100644
--- a/arch/arm/mach-imx/platsmp.c
+++ b/arch/arm/mach-imx/platsmp.c
@@ -53,7 +53,7 @@ void imx_scu_standby_enable(void)
        writel_relaxed(val, scu_base);
 }
-static int __cpuinit imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
        imx_set_cpu_jump(cpu, v7_secondary_startup);
        imx_enable_cpu(cpu, true);
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
index 695e0d73bf85..6fe81bb4d3c9 100644
--- a/arch/arm/mach-imx/system.c
+++ b/arch/arm/mach-imx/system.c
@@ -21,6 +21,8 @@
 #include <linux/io.h>
 #include <linux/err.h>
 #include <linux/delay.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 #include <asm/system_misc.h>
 #include <asm/proc-fns.h>
@@ -30,24 +32,22 @@
 #include "hardware.h"
 static void __iomem *wdog_base;
+static struct clk *wdog_clk;
 /*
 * Reset the system. It is called by machine_restart().
 */
-void mxc_restart(char mode, const char *cmd)
+void mxc_restart(enum reboot_mode mode, const char *cmd)
 {
        unsigned int wcr_enable;
-        if (cpu_is_mx1()) {
+        if (wdog_clk)
-                wcr_enable = (1 << 0);
+                clk_enable(wdog_clk);
-        } else {
-                struct clk *clk;
-                clk = clk_get_sys("imx2-wdt.0", NULL);
+        if (cpu_is_mx1())
-                if (!IS_ERR(clk))
+                wcr_enable = (1 << 0);
-                        clk_prepare_enable(clk);
+        else
                wcr_enable = (1 << 2);
-        }
        /* Assert SRS signal */
        __raw_writew(wcr_enable, wdog_base);
@@ -55,7 +55,7 @@ void mxc_restart(char mode, const char *cmd)
        /* wait for reset to assert... */
        mdelay(500);
-        printk(KERN_ERR "Watchdog reset failed to assert reset\n");
+        pr_err("%s: Watchdog reset failed to assert reset\n", __func__);
        /* delay to allow the serial port to show the message */
        mdelay(50);
@@ -64,7 +64,34 @@ void mxc_restart(char mode, const char *cmd)
        soft_restart(0);
 }
-void mxc_arch_reset_init(void __iomem *base)
+void __init mxc_arch_reset_init(void __iomem *base)
 {
        wdog_base = base;
+        wdog_clk = clk_get_sys("imx2-wdt.0", NULL);
+        if (IS_ERR(wdog_clk)) {
+                pr_warn("%s: failed to get wdog clock\n", __func__);
+                wdog_clk = NULL;
+                return;
+        }
+        clk_prepare(wdog_clk);
+}
+void __init mxc_arch_reset_init_dt(void)
+{
+        struct device_node *np;
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx21-wdt");
+        wdog_base = of_iomap(np, 0);
+        WARN_ON(!wdog_base);
+        wdog_clk = of_clk_get(np, 0);
+        if (IS_ERR(wdog_clk)) {
+                pr_warn("%s: failed to get wdog clock\n", __func__);
+                wdog_clk = NULL;
+                return;
+        }
+        clk_prepare(wdog_clk);
 }
diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c
index fea91313678b..cd46529e9eaa 100644
--- a/arch/arm/mach-imx/time.c
+++ b/arch/arm/mach-imx/time.c
@@ -26,8 +26,8 @@
 #include <linux/clockchips.h>
 #include <linux/clk.h>
 #include <linux/err.h>
+#include <linux/sched_clock.h>
-#include <asm/sched_clock.h>
 #include <asm/mach/time.h>
 #include "common.h"
diff --git a/arch/arm/mach-imx/ulpi.c b/arch/arm/mach-imx/ulpi.c
deleted file mode 100644
index 0f051957d10c..000000000000
--- a/arch/arm/mach-imx/ulpi.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * Copyright 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
- * Copyright 2009 Daniel Mack <daniel@caiaq.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA  02110-1301, USA.
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-#include "ulpi.h"
-/* ULPIVIEW register bits */
-#define ULPIVW_WU               (1 << 31)       /* Wakeup */
-#define ULPIVW_RUN              (1 << 30)       /* read/write run */
-#define ULPIVW_WRITE            (1 << 29)       /* 0 = read  1 = write */
-#define ULPIVW_SS               (1 << 27)       /* SyncState */
-#define ULPIVW_PORT_MASK        0x07    /* Port field */
-#define ULPIVW_PORT_SHIFT       24
-#define ULPIVW_ADDR_MASK        0xff    /* data address field */
-#define ULPIVW_ADDR_SHIFT       16
-#define ULPIVW_RDATA_MASK       0xff    /* read data field */
-#define ULPIVW_RDATA_SHIFT      8
-#define ULPIVW_WDATA_MASK       0xff    /* write data field */
-#define ULPIVW_WDATA_SHIFT      0
-static int ulpi_poll(void __iomem *view, u32 bit)
-{
-        int timeout = 10000;
-        while (timeout--) {
-                u32 data = __raw_readl(view);
-                if (!(data & bit))
-                        return 0;
-                cpu_relax();
-        };
-        printk(KERN_WARNING "timeout polling for ULPI device\n");
-        return -ETIMEDOUT;
-}
-static int ulpi_read(struct usb_phy *otg, u32 reg)
-{
-        int ret;
-        void __iomem *view = otg->io_priv;
-        /* make sure interface is running */
-        if (!(__raw_readl(view) & ULPIVW_SS)) {
-                __raw_writel(ULPIVW_WU, view);
-                /* wait for wakeup */
-                ret = ulpi_poll(view, ULPIVW_WU);
-                if (ret)
-                        return ret;
-        }
-        /* read the register */
-        __raw_writel((ULPIVW_RUN | (reg << ULPIVW_ADDR_SHIFT)), view);
-        /* wait for completion */
-        ret = ulpi_poll(view, ULPIVW_RUN);
-        if (ret)
-                return ret;
-        return (__raw_readl(view) >> ULPIVW_RDATA_SHIFT) & ULPIVW_RDATA_MASK;
-}
-static int ulpi_write(struct usb_phy *otg, u32 val, u32 reg)
-{
-        int ret;
-        void __iomem *view = otg->io_priv;
-        /* make sure the interface is running */
-        if (!(__raw_readl(view) & ULPIVW_SS)) {
-                __raw_writel(ULPIVW_WU, view);
-                /* wait for wakeup */
-                ret = ulpi_poll(view, ULPIVW_WU);
-                if (ret)
-                        return ret;
-        }
-        __raw_writel((ULPIVW_RUN | ULPIVW_WRITE |
-                      (reg << ULPIVW_ADDR_SHIFT) |
-                      ((val & ULPIVW_WDATA_MASK) << ULPIVW_WDATA_SHIFT)), view);
-        /* wait for completion */
-        return ulpi_poll(view, ULPIVW_RUN);
-}
-struct usb_phy_io_ops mxc_ulpi_access_ops = {
-        .read   = ulpi_read,
-        .write  = ulpi_write,
-};
-EXPORT_SYMBOL_GPL(mxc_ulpi_access_ops);
-struct usb_phy *imx_otg_ulpi_create(unsigned int flags)
-{
-        return otg_ulpi_create(&mxc_ulpi_access_ops, flags);
-}
diff --git a/arch/arm/mach-imx/ulpi.h b/arch/arm/mach-imx/ulpi.h
index 42bdaca6d7d9..23f5c0349e80 100644
--- a/arch/arm/mach-imx/ulpi.h
+++ b/arch/arm/mach-imx/ulpi.h
@@ -1,8 +1,13 @@
 #ifndef __MACH_ULPI_H
 #define __MACH_ULPI_H
-#ifdef CONFIG_USB_ULPI
+#include <linux/usb/ulpi.h>
-struct usb_phy *imx_otg_ulpi_create(unsigned int flags);
+#ifdef CONFIG_USB_ULPI_VIEWPORT
+static inline struct usb_phy *imx_otg_ulpi_create(unsigned int flags)
+{
+        return otg_ulpi_create(&ulpi_viewport_access_ops, flags);
+}
 #else
 static inline struct usb_phy *imx_otg_ulpi_create(unsigned int flags)
 {
@@ -10,7 +15,5 @@ static inline struct usb_phy *imx_otg_ulpi_create(unsigned int flags)
 }
 #endif
-extern struct usb_phy_io_ops mxc_ulpi_access_ops;
 #endif /* __MACH_ULPI_H */
diff --git a/arch/arm/mach-integrator/Makefile b/arch/arm/mach-integrator/Makefile
index d14d6b76f4c2..ec759ded7b60 100644
--- a/arch/arm/mach-integrator/Makefile
+++ b/arch/arm/mach-integrator/Makefile
@@ -8,5 +8,5 @@ obj-y					:= core.o lm.o leds.o
 obj-$(CONFIG_ARCH_INTEGRATOR_AP)        += integrator_ap.o
 obj-$(CONFIG_ARCH_INTEGRATOR_CP)        += integrator_cp.o
-obj-$(CONFIG_PCI)                       += pci_v3.o pci.o
+obj-$(CONFIG_PCI)                       += pci_v3.o
 obj-$(CONFIG_INTEGRATOR_IMPD1)          += impd1.o
diff --git a/arch/arm/mach-integrator/common.h b/arch/arm/mach-integrator/common.h
index 72516658be1e..ad0ac5547b2c 100644
--- a/arch/arm/mach-integrator/common.h
+++ b/arch/arm/mach-integrator/common.h
@@ -1,7 +1,8 @@
+#include <linux/reboot.h>
 #include <linux/amba/serial.h>
 extern struct amba_pl010_data ap_uart_data;
 void integrator_init_early(void);
 int integrator_init(bool is_cp);
 void integrator_reserve(void);
-void integrator_restart(char, const char *);
+void integrator_restart(enum reboot_mode, const char *);
 void integrator_init_sysfs(struct device *parent, u32 id);
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 81461d218717..4cdfd7365925 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -124,7 +124,7 @@ void __init integrator_reserve(void)
 /*
 * To reset, we hit the on-board reset register in the system FPGA
 */
-void integrator_restart(char mode, const char *cmd)
+void integrator_restart(enum reboot_mode mode, const char *cmd)
 {
        cm_control(CM_CTRL_RESET, CM_CTRL_RESET);
 }
diff --git a/arch/arm/mach-integrator/include/mach/platform.h b/arch/arm/mach-integrator/include/mach/platform.h
index be5859efe10e..306d025d9730 100644
--- a/arch/arm/mach-integrator/include/mach/platform.h
+++ b/arch/arm/mach-integrator/include/mach/platform.h
@@ -305,29 +305,6 @@
 /* KMI definitions are now in include/asm-arm/hardware/amba_kmi.h -- rmk */
 /* ------------------------------------------------------------------------
- *  Where in the memory map does PCI live?
- * ------------------------------------------------------------------------
- *  This represents a fairly liberal usage of address space.  Even though
- *  the V3 only has two windows (therefore we need to map stuff on the fly),
- *  we maintain the same addresses, even if they're not mapped.
- *
- */
-#define PHYS_PCI_MEM_BASE               0x40000000   /* 512M to xxx */
-/*  unused 256M from A0000000-AFFFFFFF might be used for I2O ???
- */
-#define PHYS_PCI_IO_BASE                0x60000000   /* 16M to xxx */
-/*  unused (128-16)M from B1000000-B7FFFFFF
- */
-#define PHYS_PCI_CONFIG_BASE            0x61000000   /* 16M to xxx */
-/*  unused ((128-16)M - 64K) from XXX
- */
-#define PHYS_PCI_V3_BASE                0x62000000
-#define PCI_MEMORY_VADDR                IOMEM(0xe8000000)
-#define PCI_CONFIG_VADDR                IOMEM(0xec000000)
-#define PCI_V3_VADDR                    IOMEM(0xed000000)
-/* ------------------------------------------------------------------------
 *  Integrator Interrupt Controllers
 * ------------------------------------------------------------------------
 *
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index b23c8e4f28e8..d9e95e612fcb 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -41,7 +41,7 @@
 #include <linux/stat.h>
 #include <linux/sys_soc.h>
 #include <linux/termios.h>
-#include <video/vga.h>
+#include <linux/sched_clock.h>
 #include <mach/hardware.h>
 #include <mach/platform.h>
@@ -49,7 +49,6 @@
 #include <asm/setup.h>
 #include <asm/param.h>          /* HZ */
 #include <asm/mach-types.h>
-#include <asm/sched_clock.h>
 #include <mach/lm.h>
 #include <mach/irqs.h>
@@ -57,10 +56,10 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
-#include <asm/mach/pci.h>
 #include <asm/mach/time.h>
 #include "common.h"
+#include "pci_v3.h"
 /* Base address to the AP system controller */
 void __iomem *ap_syscon_base;
@@ -78,10 +77,6 @@ void __iomem *ap_syscon_base;
 /*
 * Logical      Physical
- * e8000000     40000000        PCI memory              PHYS_PCI_MEM_BASE       (max 512M)
- * ec000000     61000000        PCI config space        PHYS_PCI_CONFIG_BASE    (max 16M)
- * ed000000     62000000        PCI V3 regs             PHYS_PCI_V3_BASE        (max 64k)
- * fee00000     60000000        PCI IO                  PHYS_PCI_IO_BASE        (max 16M)
 * ef000000                     Cache flush
 * f1000000     10000000        Core module registers
 * f1100000     11000000        System controller registers
@@ -130,29 +125,13 @@ static struct map_desc ap_io_desc[] __initdata __maybe_unused = {
                .pfn            = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
                .length         = SZ_4K,
                .type           = MT_DEVICE
-        }, {
-                .virtual        = (unsigned long)PCI_MEMORY_VADDR,
-                .pfn            = __phys_to_pfn(PHYS_PCI_MEM_BASE),
-                .length         = SZ_16M,
-                .type           = MT_DEVICE
-        }, {
-                .virtual        = (unsigned long)PCI_CONFIG_VADDR,
-                .pfn            = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
-                .length         = SZ_16M,
-                .type           = MT_DEVICE
-        }, {
-                .virtual        = (unsigned long)PCI_V3_VADDR,
-                .pfn            = __phys_to_pfn(PHYS_PCI_V3_BASE),
-                .length         = SZ_64K,
-                .type           = MT_DEVICE
        }
 };
 static void __init ap_map_io(void)
 {
        iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
-        vga_base = (unsigned long)PCI_MEMORY_VADDR;
+        pci_v3_early_init();
-        pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE));
 }
 #ifdef CONFIG_PM
@@ -615,6 +594,11 @@ static void __init ap_map_io_atag(void)
 * for eventual deletion.
 */
+static struct platform_device pci_v3_device = {
+        .name           = "pci-v3",
+        .id             = 0,
+};
 static struct resource cfi_flash_resource = {
        .start          = INTEGRATOR_FLASH_BASE,
        .end            = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
@@ -672,6 +656,7 @@ static void __init ap_init(void)
        unsigned long sc_dec;
        int i;
+        platform_device_register(&pci_v3_device);
        platform_device_register(&cfi_flash_device);
        ap_syscon_base = __io_address(INTEGRATOR_SC_BASE);
diff --git a/arch/arm/mach-integrator/pci.c b/arch/arm/mach-integrator/pci.c
deleted file mode 100644
index 6c1667e728f5..000000000000
--- a/arch/arm/mach-integrator/pci.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- *  linux/arch/arm/mach-integrator/pci-integrator.c
- *
- *  Copyright (C) 1999 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- *
- *  PCI functions for Integrator
- */
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <asm/mach/pci.h>
-#include <asm/mach-types.h>
-#include <mach/irqs.h>
-/* 
- * A small note about bridges and interrupts.  The DECchip 21050 (and
- * later) adheres to the PCI-PCI bridge specification.  This says that
- * the interrupts on the other side of a bridge are swizzled in the
- * following manner:
- *
- * Dev    Interrupt   Interrupt 
- *        Pin on      Pin on 
- *        Device      Connector
- *
- *   4    A           A
- *        B           B
- *        C           C
- *        D           D
- * 
- *   5    A           B
- *        B           C
- *        C           D
- *        D           A
- *
- *   6    A           C
- *        B           D
- *        C           A
- *        D           B
- *
- *   7    A           D
- *        B           A
- *        C           B
- *        D           C
- *
- * Where A = pin 1, B = pin 2 and so on and pin=0 = default = A.
- * Thus, each swizzle is ((pin-1) + (device#-4)) % 4
- */
-/*
- * This routine handles multiple bridges.
- */
-static u8 __init integrator_swizzle(struct pci_dev *dev, u8 *pinp)
-{
-        if (*pinp == 0)
-                *pinp = 1;
-        return pci_common_swizzle(dev, pinp);
-}
-static int irq_tab[4] __initdata = {
-        IRQ_AP_PCIINT0, IRQ_AP_PCIINT1, IRQ_AP_PCIINT2, IRQ_AP_PCIINT3
-};
-/*
- * map the specified device/slot/pin to an IRQ.  This works out such
- * that slot 9 pin 1 is INT0, pin 2 is INT1, and slot 10 pin 1 is INT1.
- */
-static int __init integrator_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
-        int intnr = ((slot - 9) + (pin - 1)) & 3;
-        return irq_tab[intnr];
-}
-extern void pci_v3_init(void *);
-static struct hw_pci integrator_pci __initdata = {
-        .swizzle                = integrator_swizzle,
-        .map_irq                = integrator_map_irq,
-        .setup                  = pci_v3_setup,
-        .nr_controllers         = 1,
-        .ops                    = &pci_v3_ops,
-        .preinit                = pci_v3_preinit,
-        .postinit               = pci_v3_postinit,
-};
-static int __init integrator_pci_init(void)
-{
-        if (machine_is_integrator())
-                pci_common_init(&integrator_pci);
-        return 0;
-}
-subsys_initcall(integrator_pci_init);
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index e7fcea7f3300..bef100527c42 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -27,16 +27,199 @@
 #include <linux/spinlock.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_pci.h>
+#include <video/vga.h>
 #include <mach/hardware.h>
 #include <mach/platform.h>
 #include <mach/irqs.h>
+#include <asm/mach/map.h>
 #include <asm/signal.h>
 #include <asm/mach/pci.h>
 #include <asm/irq_regs.h>
-#include <asm/hardware/pci_v3.h>
+#include "pci_v3.h"
+/*
+ * Where in the memory map does PCI live?
+ *
+ * This represents a fairly liberal usage of address space.  Even though
+ * the V3 only has two windows (therefore we need to map stuff on the fly),
+ * we maintain the same addresses, even if they're not mapped.
+ */
+#define PHYS_PCI_MEM_BASE               0x40000000 /* 256M */
+#define PHYS_PCI_PRE_BASE               0x50000000 /* 256M */
+#define PHYS_PCI_IO_BASE                0x60000000 /* 16M */
+#define PHYS_PCI_CONFIG_BASE            0x61000000 /* 16M */
+#define PHYS_PCI_V3_BASE                0x62000000 /* 64K */
+#define PCI_MEMORY_VADDR               IOMEM(0xe8000000)
+#define PCI_CONFIG_VADDR               IOMEM(0xec000000)
+/*
+ * V3 Local Bus to PCI Bridge definitions
+ *
+ * Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04
+ * All V3 register names are prefaced by V3_ to avoid clashing with any other
+ * PCI definitions.  Their names match the user's manual.
+ *
+ * I'm assuming that I20 is disabled.
+ *
+ */
+#define V3_PCI_VENDOR                   0x00000000
+#define V3_PCI_DEVICE                   0x00000002
+#define V3_PCI_CMD                      0x00000004
+#define V3_PCI_STAT                     0x00000006
+#define V3_PCI_CC_REV                   0x00000008
+#define V3_PCI_HDR_CFG                  0x0000000C
+#define V3_PCI_IO_BASE                  0x00000010
+#define V3_PCI_BASE0                    0x00000014
+#define V3_PCI_BASE1                    0x00000018
+#define V3_PCI_SUB_VENDOR               0x0000002C
+#define V3_PCI_SUB_ID                   0x0000002E
+#define V3_PCI_ROM                      0x00000030
+#define V3_PCI_BPARAM                   0x0000003C
+#define V3_PCI_MAP0                     0x00000040
+#define V3_PCI_MAP1                     0x00000044
+#define V3_PCI_INT_STAT                 0x00000048
+#define V3_PCI_INT_CFG                  0x0000004C
+#define V3_LB_BASE0                     0x00000054
+#define V3_LB_BASE1                     0x00000058
+#define V3_LB_MAP0                      0x0000005E
+#define V3_LB_MAP1                      0x00000062
+#define V3_LB_BASE2                     0x00000064
+#define V3_LB_MAP2                      0x00000066
+#define V3_LB_SIZE                      0x00000068
+#define V3_LB_IO_BASE                   0x0000006E
+#define V3_FIFO_CFG                     0x00000070
+#define V3_FIFO_PRIORITY                0x00000072
+#define V3_FIFO_STAT                    0x00000074
+#define V3_LB_ISTAT                     0x00000076
+#define V3_LB_IMASK                     0x00000077
+#define V3_SYSTEM                       0x00000078
+#define V3_LB_CFG                       0x0000007A
+#define V3_PCI_CFG                      0x0000007C
+#define V3_DMA_PCI_ADR0                 0x00000080
+#define V3_DMA_PCI_ADR1                 0x00000090
+#define V3_DMA_LOCAL_ADR0               0x00000084
+#define V3_DMA_LOCAL_ADR1               0x00000094
+#define V3_DMA_LENGTH0                  0x00000088
+#define V3_DMA_LENGTH1                  0x00000098
+#define V3_DMA_CSR0                     0x0000008B
+#define V3_DMA_CSR1                     0x0000009B
+#define V3_DMA_CTLB_ADR0                0x0000008C
+#define V3_DMA_CTLB_ADR1                0x0000009C
+#define V3_DMA_DELAY                    0x000000E0
+#define V3_MAIL_DATA                    0x000000C0
+#define V3_PCI_MAIL_IEWR                0x000000D0
+#define V3_PCI_MAIL_IERD                0x000000D2
+#define V3_LB_MAIL_IEWR                 0x000000D4
+#define V3_LB_MAIL_IERD                 0x000000D6
+#define V3_MAIL_WR_STAT                 0x000000D8
+#define V3_MAIL_RD_STAT                 0x000000DA
+#define V3_QBA_MAP                      0x000000DC
+/*  PCI COMMAND REGISTER bits
+ */
+#define V3_COMMAND_M_FBB_EN             (1 << 9)
+#define V3_COMMAND_M_SERR_EN            (1 << 8)
+#define V3_COMMAND_M_PAR_EN             (1 << 6)
+#define V3_COMMAND_M_MASTER_EN          (1 << 2)
+#define V3_COMMAND_M_MEM_EN             (1 << 1)
+#define V3_COMMAND_M_IO_EN              (1 << 0)
+/*  SYSTEM REGISTER bits
+ */
+#define V3_SYSTEM_M_RST_OUT             (1 << 15)
+#define V3_SYSTEM_M_LOCK                (1 << 14)
+/*  PCI_CFG bits
+ */
+#define V3_PCI_CFG_M_I2O_EN             (1 << 15)
+#define V3_PCI_CFG_M_IO_REG_DIS         (1 << 14)
+#define V3_PCI_CFG_M_IO_DIS             (1 << 13)
+#define V3_PCI_CFG_M_EN3V               (1 << 12)
+#define V3_PCI_CFG_M_RETRY_EN           (1 << 10)
+#define V3_PCI_CFG_M_AD_LOW1            (1 << 9)
+#define V3_PCI_CFG_M_AD_LOW0            (1 << 8)
+/*  PCI_BASE register bits (PCI -> Local Bus)
+ */
+#define V3_PCI_BASE_M_ADR_BASE          0xFFF00000
+#define V3_PCI_BASE_M_ADR_BASEL         0x000FFF00
+#define V3_PCI_BASE_M_PREFETCH          (1 << 3)
+#define V3_PCI_BASE_M_TYPE              (3 << 1)
+#define V3_PCI_BASE_M_IO                (1 << 0)
+/*  PCI MAP register bits (PCI -> Local bus)
+ */
+#define V3_PCI_MAP_M_MAP_ADR            0xFFF00000
+#define V3_PCI_MAP_M_RD_POST_INH        (1 << 15)
+#define V3_PCI_MAP_M_ROM_SIZE           (3 << 10)
+#define V3_PCI_MAP_M_SWAP               (3 << 8)
+#define V3_PCI_MAP_M_ADR_SIZE           0x000000F0
+#define V3_PCI_MAP_M_REG_EN             (1 << 1)
+#define V3_PCI_MAP_M_ENABLE             (1 << 0)
+/*
+ *  LB_BASE0,1 register bits (Local bus -> PCI)
+ */
+#define V3_LB_BASE_ADR_BASE             0xfff00000
+#define V3_LB_BASE_SWAP                 (3 << 8)
+#define V3_LB_BASE_ADR_SIZE             (15 << 4)
+#define V3_LB_BASE_PREFETCH             (1 << 3)
+#define V3_LB_BASE_ENABLE               (1 << 0)
+#define V3_LB_BASE_ADR_SIZE_1MB         (0 << 4)
+#define V3_LB_BASE_ADR_SIZE_2MB         (1 << 4)
+#define V3_LB_BASE_ADR_SIZE_4MB         (2 << 4)
+#define V3_LB_BASE_ADR_SIZE_8MB         (3 << 4)
+#define V3_LB_BASE_ADR_SIZE_16MB        (4 << 4)
+#define V3_LB_BASE_ADR_SIZE_32MB        (5 << 4)
+#define V3_LB_BASE_ADR_SIZE_64MB        (6 << 4)
+#define V3_LB_BASE_ADR_SIZE_128MB       (7 << 4)
+#define V3_LB_BASE_ADR_SIZE_256MB       (8 << 4)
+#define V3_LB_BASE_ADR_SIZE_512MB       (9 << 4)
+#define V3_LB_BASE_ADR_SIZE_1GB         (10 << 4)
+#define V3_LB_BASE_ADR_SIZE_2GB         (11 << 4)
+#define v3_addr_to_lb_base(a)   ((a) & V3_LB_BASE_ADR_BASE)
+/*
+ *  LB_MAP0,1 register bits (Local bus -> PCI)
+ */
+#define V3_LB_MAP_MAP_ADR               0xfff0
+#define V3_LB_MAP_TYPE                  (7 << 1)
+#define V3_LB_MAP_AD_LOW_EN             (1 << 0)
+#define V3_LB_MAP_TYPE_IACK             (0 << 1)
+#define V3_LB_MAP_TYPE_IO               (1 << 1)
+#define V3_LB_MAP_TYPE_MEM              (3 << 1)
+#define V3_LB_MAP_TYPE_CONFIG           (5 << 1)
+#define V3_LB_MAP_TYPE_MEM_MULTIPLE     (6 << 1)
+#define v3_addr_to_lb_map(a)    (((a) >> 16) & V3_LB_MAP_MAP_ADR)
+/*
+ *  LB_BASE2 register bits (Local bus -> PCI IO)
+ */
+#define V3_LB_BASE2_ADR_BASE            0xff00
+#define V3_LB_BASE2_SWAP                (3 << 6)
+#define V3_LB_BASE2_ENABLE              (1 << 0)
+#define v3_addr_to_lb_base2(a)  (((a) >> 16) & V3_LB_BASE2_ADR_BASE)
+/*
+ *  LB_MAP2 register bits (Local bus -> PCI IO)
+ */
+#define V3_LB_MAP2_MAP_ADR              0xff00
+#define v3_addr_to_lb_map2(a)   (((a) >> 16) & V3_LB_MAP2_MAP_ADR)
 /*
 * The V3 PCI interface chip in Integrator provides several windows from
@@ -101,15 +284,28 @@
 * the mappings into PCI memory.
 */
+/* Filled in by probe */
+static void __iomem *pci_v3_base;
+/* CPU side memory ranges */
+static struct resource conf_mem; /* FIXME: remap this instead of static map */
+static struct resource io_mem;
+static struct resource non_mem;
+static struct resource pre_mem;
+/* PCI side memory ranges */
+static u64 non_mem_pci;
+static u64 non_mem_pci_sz;
+static u64 pre_mem_pci;
+static u64 pre_mem_pci_sz;
 // V3 access routines
-#define v3_writeb(o,v) __raw_writeb(v, PCI_V3_VADDR + (unsigned int)(o))
+#define v3_writeb(o,v) __raw_writeb(v, pci_v3_base + (unsigned int)(o))
-#define v3_readb(o)    (__raw_readb(PCI_V3_VADDR + (unsigned int)(o)))
+#define v3_readb(o)    (__raw_readb(pci_v3_base + (unsigned int)(o)))
-#define v3_writew(o,v) __raw_writew(v, PCI_V3_VADDR + (unsigned int)(o))
+#define v3_writew(o,v) __raw_writew(v, pci_v3_base + (unsigned int)(o))
-#define v3_readw(o)    (__raw_readw(PCI_V3_VADDR + (unsigned int)(o)))
+#define v3_readw(o)    (__raw_readw(pci_v3_base + (unsigned int)(o)))
-#define v3_writel(o,v) __raw_writel(v, PCI_V3_VADDR + (unsigned int)(o))
+#define v3_writel(o,v) __raw_writel(v, pci_v3_base + (unsigned int)(o))
-#define v3_readl(o)    (__raw_readl(PCI_V3_VADDR + (unsigned int)(o)))
+#define v3_readl(o)    (__raw_readl(pci_v3_base + (unsigned int)(o)))
 /*============================================================================
 *
@@ -165,19 +361,6 @@
 */
 static DEFINE_RAW_SPINLOCK(v3_lock);
-#define PCI_BUS_NONMEM_START    0x00000000
-#define PCI_BUS_NONMEM_SIZE     SZ_256M
-#define PCI_BUS_PREMEM_START    PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE
-#define PCI_BUS_PREMEM_SIZE     SZ_256M
-#if PCI_BUS_NONMEM_START & 0x000fffff
-#error PCI_BUS_NONMEM_START must be megabyte aligned
-#endif
-#if PCI_BUS_PREMEM_START & 0x000fffff
-#error PCI_BUS_PREMEM_START must be megabyte aligned
-#endif
 #undef V3_LB_BASE_PREFETCH
 #define V3_LB_BASE_PREFETCH 0
@@ -243,13 +426,13 @@ static void __iomem *v3_open_config_window(struct pci_bus *bus,
         * prefetchable), this frees up base1 for re-use by
         * configuration memory
         */
-        v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
+        v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) |
                        V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE);
        /*
         * Set up base1/map1 to point into configuration space.
         */
-        v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_CONFIG_BASE) |
+        v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(conf_mem.start) |
                        V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE);
        v3_writew(V3_LB_MAP1, mapaddress);
@@ -261,16 +444,16 @@ static void v3_close_config_window(void)
        /*
         * Reassign base1 for use by prefetchable PCI memory
         */
-        v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
+        v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(pre_mem.start) |
                        V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
                        V3_LB_BASE_ENABLE);
-        v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
+        v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(pre_mem_pci) |
                        V3_LB_MAP_TYPE_MEM_MULTIPLE);
        /*
         * And shrink base0 back to a 256M window (NOTE: MAP0 already correct)
         */
-        v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
+        v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) |
                        V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
 }
@@ -337,25 +520,11 @@ static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where,
        return PCIBIOS_SUCCESSFUL;
 }
-struct pci_ops pci_v3_ops = {
+static struct pci_ops pci_v3_ops = {
        .read   = v3_read_config,
        .write  = v3_write_config,
 };
-static struct resource non_mem = {
-        .name   = "PCI non-prefetchable",
-        .start  = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START,
-        .end    = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE - 1,
-        .flags  = IORESOURCE_MEM,
-};
-static struct resource pre_mem = {
-        .name   = "PCI prefetchable",
-        .start  = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START,
-        .end    = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START + PCI_BUS_PREMEM_SIZE - 1,
-        .flags  = IORESOURCE_MEM | IORESOURCE_PREFETCH,
-};
 static int __init pci_v3_setup_resources(struct pci_sys_data *sys)
 {
        if (request_resource(&iomem_resource, &non_mem)) {
@@ -471,7 +640,7 @@ static irqreturn_t v3_irq(int dummy, void *devid)
        return IRQ_HANDLED;
 }
-int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
+static int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
 {
        int ret = 0;
@@ -479,7 +648,7 @@ int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
                return -EINVAL;
        if (nr == 0) {
-                sys->mem_offset = PHYS_PCI_MEM_BASE;
+                sys->mem_offset = non_mem.start;
                ret = pci_v3_setup_resources(sys);
        }
@@ -490,18 +659,10 @@ int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
 * V3_LB_BASE? - local bus address
 * V3_LB_MAP?  - pci bus address
 */
-void __init pci_v3_preinit(void)
+static void __init pci_v3_preinit(void)
 {
        unsigned long flags;
        unsigned int temp;
-        int ret;
-        /* Remap the Integrator system controller */
-        ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100);
-        if (!ap_syscon_base) {
-                pr_err("unable to remap the AP syscon for PCIv3\n");
-                return;
-        }
        pcibios_min_mem = 0x00100000;
@@ -525,25 +686,25 @@ void __init pci_v3_preinit(void)
         * Setup window 0 - PCI non-prefetchable memory
         *  Local: 0x40000000 Bus: 0x00000000 Size: 256MB
         */
-        v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
+        v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) |
                        V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
-        v3_writew(V3_LB_MAP0, v3_addr_to_lb_map(PCI_BUS_NONMEM_START) |
+        v3_writew(V3_LB_MAP0, v3_addr_to_lb_map(non_mem_pci) |
                        V3_LB_MAP_TYPE_MEM);
        /*
         * Setup window 1 - PCI prefetchable memory
         *  Local: 0x50000000 Bus: 0x10000000 Size: 256MB
         */
-        v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
+        v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(pre_mem.start) |
                        V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
                        V3_LB_BASE_ENABLE);
-        v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
+        v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(pre_mem_pci) |
                        V3_LB_MAP_TYPE_MEM_MULTIPLE);
        /*
         * Setup window 2 - PCI IO
         */
-        v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(PHYS_PCI_IO_BASE) |
+        v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(io_mem.start) |
                        V3_LB_BASE_ENABLE);
        v3_writew(V3_LB_MAP2, v3_addr_to_lb_map2(0));
@@ -578,18 +739,10 @@ void __init pci_v3_preinit(void)
        v3_writeb(V3_LB_IMASK, 0x28);
        __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET);
-        /*
-         * Grab the PCI error interrupt.
-         */
-        ret = request_irq(IRQ_AP_V3INT, v3_irq, 0, "V3", NULL);
-        if (ret)
-                printk(KERN_ERR "PCI: unable to grab PCI error "
-                       "interrupt: %d\n", ret);
        raw_spin_unlock_irqrestore(&v3_lock, flags);
 }
-void __init pci_v3_postinit(void)
+static void __init pci_v3_postinit(void)
 {
        unsigned int pci_cmd;
@@ -608,5 +761,284 @@ void __init pci_v3_postinit(void)
                       "interrupt: %d\n", ret);
 #endif
-        register_isa_ports(PHYS_PCI_MEM_BASE, PHYS_PCI_IO_BASE, 0);
+        register_isa_ports(non_mem.start, io_mem.start, 0);
+}
+/*
+ * A small note about bridges and interrupts.  The DECchip 21050 (and
+ * later) adheres to the PCI-PCI bridge specification.  This says that
+ * the interrupts on the other side of a bridge are swizzled in the
+ * following manner:
+ *
+ * Dev    Interrupt   Interrupt
+ *        Pin on      Pin on
+ *        Device      Connector
+ *
+ *   4    A           A
+ *        B           B
+ *        C           C
+ *        D           D
+ *
+ *   5    A           B
+ *        B           C
+ *        C           D
+ *        D           A
+ *
+ *   6    A           C
+ *        B           D
+ *        C           A
+ *        D           B
+ *
+ *   7    A           D
+ *        B           A
+ *        C           B
+ *        D           C
+ *
+ * Where A = pin 1, B = pin 2 and so on and pin=0 = default = A.
+ * Thus, each swizzle is ((pin-1) + (device#-4)) % 4
+ */
+/*
+ * This routine handles multiple bridges.
+ */
+static u8 __init pci_v3_swizzle(struct pci_dev *dev, u8 *pinp)
+{
+        if (*pinp == 0)
+                *pinp = 1;
+        return pci_common_swizzle(dev, pinp);
+}
+static int irq_tab[4] __initdata = {
+        IRQ_AP_PCIINT0, IRQ_AP_PCIINT1, IRQ_AP_PCIINT2, IRQ_AP_PCIINT3
+};
+/*
+ * map the specified device/slot/pin to an IRQ.  This works out such
+ * that slot 9 pin 1 is INT0, pin 2 is INT1, and slot 10 pin 1 is INT1.
+ */
+static int __init pci_v3_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+        int intnr = ((slot - 9) + (pin - 1)) & 3;
+        return irq_tab[intnr];
+}
+static struct hw_pci pci_v3 __initdata = {
+        .swizzle                = pci_v3_swizzle,
+        .setup                  = pci_v3_setup,
+        .nr_controllers         = 1,
+        .ops                    = &pci_v3_ops,
+        .preinit                = pci_v3_preinit,
+        .postinit               = pci_v3_postinit,
+};
+#ifdef CONFIG_OF
+static int __init pci_v3_map_irq_dt(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+        struct of_irq oirq;
+        int ret;
+        ret = of_irq_map_pci(dev, &oirq);
+        if (ret) {
+                dev_err(&dev->dev, "of_irq_map_pci() %d\n", ret);
+                /* Proper return code 0 == NO_IRQ */
+                return 0;
+        }
+        return irq_create_of_mapping(oirq.controller, oirq.specifier,
+                                     oirq.size);
+}
+static int __init pci_v3_dtprobe(struct platform_device *pdev,
+                                struct device_node *np)
+{
+        struct of_pci_range_parser parser;
+        struct of_pci_range range;
+        struct resource *res;
+        int irq, ret;
+        if (of_pci_range_parser_init(&parser, np))
+                return -EINVAL;
+        /* Get base for bridge registers */
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res) {
+                dev_err(&pdev->dev, "unable to obtain PCIv3 base\n");
+                return -ENODEV;
+        }
+        pci_v3_base = devm_ioremap(&pdev->dev, res->start,
+                                   resource_size(res));
+        if (!pci_v3_base) {
+                dev_err(&pdev->dev, "unable to remap PCIv3 base\n");
+                return -ENODEV;
+        }
+        /* Get and request error IRQ resource */
+        irq = platform_get_irq(pdev, 0);
+        if (irq <= 0) {
+                dev_err(&pdev->dev, "unable to obtain PCIv3 error IRQ\n");
+                return -ENODEV;
+        }
+        ret = devm_request_irq(&pdev->dev, irq, v3_irq, 0,
+                        "PCIv3 error", NULL);
+        if (ret < 0) {
+                dev_err(&pdev->dev, "unable to request PCIv3 error IRQ %d (%d)\n", irq, ret);
+                return ret;
+        }
+        for_each_of_pci_range(&parser, &range) {
+                if (!range.flags) {
+                        of_pci_range_to_resource(&range, np, &conf_mem);
+                        conf_mem.name = "PCIv3 config";
+                }
+                if (range.flags & IORESOURCE_IO) {
+                        of_pci_range_to_resource(&range, np, &io_mem);
+                        io_mem.name = "PCIv3 I/O";
+                }
+                if ((range.flags & IORESOURCE_MEM) &&
+                        !(range.flags & IORESOURCE_PREFETCH)) {
+                        non_mem_pci = range.pci_addr;
+                        non_mem_pci_sz = range.size;
+                        of_pci_range_to_resource(&range, np, &non_mem);
+                        non_mem.name = "PCIv3 non-prefetched mem";
+                }
+                if ((range.flags & IORESOURCE_MEM) &&
+                        (range.flags & IORESOURCE_PREFETCH)) {
+                        pre_mem_pci = range.pci_addr;
+                        pre_mem_pci_sz = range.size;
+                        of_pci_range_to_resource(&range, np, &pre_mem);
+                        pre_mem.name = "PCIv3 prefetched mem";
+                }
+        }
+        if (!conf_mem.start || !io_mem.start ||
+            !non_mem.start || !pre_mem.start) {
+                dev_err(&pdev->dev, "missing ranges in device node\n");
+                return -EINVAL;
+        }
+        pci_v3.map_irq = pci_v3_map_irq_dt;
+        pci_common_init_dev(&pdev->dev, &pci_v3);
+        return 0;
+}
+#else
+static inline int pci_v3_dtprobe(struct platform_device *pdev,
+                                  struct device_node *np)
+{
+        return -EINVAL;
+}
+#endif
+static int __init pci_v3_probe(struct platform_device *pdev)
+{
+        struct device_node *np = pdev->dev.of_node;
+        int ret;
+        /* Remap the Integrator system controller */
+        ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100);
+        if (!ap_syscon_base) {
+                dev_err(&pdev->dev, "unable to remap the AP syscon for PCIv3\n");
+                return -ENODEV;
+        }
+        /* Device tree probe path */
+        if (np)
+                return pci_v3_dtprobe(pdev, np);
+        pci_v3_base = devm_ioremap(&pdev->dev, PHYS_PCI_V3_BASE, SZ_64K);
+        if (!pci_v3_base) {
+                dev_err(&pdev->dev, "unable to remap PCIv3 base\n");
+                return -ENODEV;
+        }
+        ret = devm_request_irq(&pdev->dev, IRQ_AP_V3INT, v3_irq, 0, "V3", NULL);
+        if (ret) {
+                dev_err(&pdev->dev, "unable to grab PCI error interrupt: %d\n",
+                        ret);
+                return -ENODEV;
+        }
+        conf_mem.name = "PCIv3 config";
+        conf_mem.start = PHYS_PCI_CONFIG_BASE;
+        conf_mem.end = PHYS_PCI_CONFIG_BASE + SZ_16M - 1;
+        conf_mem.flags = IORESOURCE_MEM;
+        io_mem.name = "PCIv3 I/O";
+        io_mem.start = PHYS_PCI_IO_BASE;
+        io_mem.end = PHYS_PCI_IO_BASE + SZ_16M - 1;
+        io_mem.flags = IORESOURCE_MEM;
+        non_mem_pci = 0x00000000;
+        non_mem_pci_sz = SZ_256M;
+        non_mem.name = "PCIv3 non-prefetched mem";
+        non_mem.start = PHYS_PCI_MEM_BASE;
+        non_mem.end = PHYS_PCI_MEM_BASE + SZ_256M - 1;
+        non_mem.flags = IORESOURCE_MEM;
+        pre_mem_pci = 0x10000000;
+        pre_mem_pci_sz = SZ_256M;
+        pre_mem.name = "PCIv3 prefetched mem";
+        pre_mem.start = PHYS_PCI_PRE_BASE + SZ_256M;
+        pre_mem.end = PHYS_PCI_PRE_BASE + SZ_256M - 1;
+        pre_mem.flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
+        pci_v3.map_irq = pci_v3_map_irq;
+        pci_common_init_dev(&pdev->dev, &pci_v3);
+        return 0;
+}
+static const struct of_device_id pci_ids[] = {
+        { .compatible = "v3,v360epc-pci", },
+        {},
+};
+static struct platform_driver pci_v3_driver = {
+        .driver = {
+                .name = "pci-v3",
+                .of_match_table = pci_ids,
+        },
+};
+static int __init pci_v3_init(void)
+{
+        return platform_driver_probe(&pci_v3_driver, pci_v3_probe);
+}
+subsys_initcall(pci_v3_init);
+/*
+ * Static mappings for the PCIv3 bridge
+ *
+ * e8000000     40000000        PCI memory              PHYS_PCI_MEM_BASE       (max 512M)
+ * ec000000     61000000        PCI config space        PHYS_PCI_CONFIG_BASE    (max 16M)
+ * fee00000     60000000        PCI IO                  PHYS_PCI_IO_BASE        (max 16M)
+ */
+static struct map_desc pci_v3_io_desc[] __initdata __maybe_unused = {
+        {
+                .virtual        = (unsigned long)PCI_MEMORY_VADDR,
+                .pfn            = __phys_to_pfn(PHYS_PCI_MEM_BASE),
+                .length         = SZ_16M,
+                .type           = MT_DEVICE
+        }, {
+                .virtual        = (unsigned long)PCI_CONFIG_VADDR,
+                .pfn            = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
+                .length         = SZ_16M,
+                .type           = MT_DEVICE
+        }
+};
+int __init pci_v3_early_init(void)
+{
+        iotable_init(pci_v3_io_desc, ARRAY_SIZE(pci_v3_io_desc));
+        vga_base = (unsigned long)PCI_MEMORY_VADDR;
+        pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE));
+        return 0;
 }
diff --git a/arch/arm/mach-integrator/pci_v3.h b/arch/arm/mach-integrator/pci_v3.h
new file mode 100644
index 000000000000..755fd29fed4a
--- /dev/null
+++ b/arch/arm/mach-integrator/pci_v3.h
@@ -0,0 +1,2 @@
+/* Simple oneliner include to the PCIv3 early init */
+extern int pci_v3_early_init(void);
diff --git a/arch/arm/mach-iop13xx/include/mach/iop13xx.h b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
index 7480f58267aa..17b40279e0a4 100644
--- a/arch/arm/mach-iop13xx/include/mach/iop13xx.h
+++ b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
@@ -2,6 +2,9 @@
 #define _IOP13XX_HW_H_
 #ifndef __ASSEMBLY__
+#include <linux/reboot.h>
 /* The ATU offsets can change based on the strapping */
 extern u32 iop13xx_atux_pmmr_offset;
 extern u32 iop13xx_atue_pmmr_offset;
@@ -11,7 +14,7 @@ void iop13xx_map_io(void);
 void iop13xx_platform_init(void);
 void iop13xx_add_tpmi_devices(void);
 void iop13xx_init_irq(void);
-void iop13xx_restart(char, const char *);
+void iop13xx_restart(enum reboot_mode, const char *);
 /* CPUID CP6 R0 Page 0 */
 static inline int iop13xx_cpu_id(void)
diff --git a/arch/arm/mach-iop13xx/io.c b/arch/arm/mach-iop13xx/io.c
index 183dc8b5511b..faaf7d4482c5 100644
--- a/arch/arm/mach-iop13xx/io.c
+++ b/arch/arm/mach-iop13xx/io.c
@@ -23,7 +23,7 @@
 #include "pci.h"
-static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie,
+static void __iomem *__iop13xx_ioremap_caller(phys_addr_t cookie,
        size_t size, unsigned int mtype, void *caller)
 {
        void __iomem * retval;
diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c
index 3181f61ea63e..96e6c7a6793b 100644
--- a/arch/arm/mach-iop13xx/setup.c
+++ b/arch/arm/mach-iop13xx/setup.c
@@ -469,7 +469,6 @@ void __init iop13xx_platform_init(void)
                        dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
                        dma_cap_set(DMA_XOR, plat_data->cap_mask);
                        dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask);
-                        dma_cap_set(DMA_MEMSET, plat_data->cap_mask);
                        dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
                        break;
                case IOP13XX_INIT_ADMA_1:
@@ -479,7 +478,6 @@ void __init iop13xx_platform_init(void)
                        dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
                        dma_cap_set(DMA_XOR, plat_data->cap_mask);
                        dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask);
-                        dma_cap_set(DMA_MEMSET, plat_data->cap_mask);
                        dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
                        break;
                case IOP13XX_INIT_ADMA_2:
@@ -489,7 +487,6 @@ void __init iop13xx_platform_init(void)
                        dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
                        dma_cap_set(DMA_XOR, plat_data->cap_mask);
                        dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask);
-                        dma_cap_set(DMA_MEMSET, plat_data->cap_mask);
                        dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
                        dma_cap_set(DMA_PQ, plat_data->cap_mask);
                        dma_cap_set(DMA_PQ_VAL, plat_data->cap_mask);
@@ -597,7 +594,7 @@ __setup("iop13xx_init_adma", iop13xx_init_adma_setup);
 __setup("iop13xx_init_uart", iop13xx_init_uart_setup);
 __setup("iop13xx_init_i2c", iop13xx_init_i2c_setup);
-void iop13xx_restart(char mode, const char *cmd)
+void iop13xx_restart(enum reboot_mode mode, const char *cmd)
 {
        /*
         * Reset the internal bus (warning both cores are reset)
diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c
index ea0984a7449e..069144300b77 100644
--- a/arch/arm/mach-iop32x/n2100.c
+++ b/arch/arm/mach-iop32x/n2100.c
@@ -286,7 +286,7 @@ static void n2100_power_off(void)
                ;
 }
-static void n2100_restart(char mode, const char *cmd)
+static void n2100_restart(enum reboot_mode mode, const char *cmd)
 {
        gpio_line_set(N2100_HARDWARE_RESET, GPIO_LOW);
        gpio_line_config(N2100_HARDWARE_RESET, GPIO_OUT);
diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
index 73a2d905af8a..30e1ebe3a891 100644
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -235,7 +235,6 @@ config IXP4XX_QMGR
 config IXP4XX_NPE
        tristate "IXP4xx Network Processor Engine support"
        select FW_LOADER
-        select HOTPLUG
        help
          This driver supports IXP4xx built-in network coprocessors
          and is automatically selected by Ethernet and HSS drivers.
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 6600cff6bd92..5327decde5a0 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -30,6 +30,7 @@
 #include <linux/export.h>
 #include <linux/gpio.h>
 #include <linux/cpu.h>
+#include <linux/sched_clock.h>
 #include <mach/udc.h>
 #include <mach/hardware.h>
@@ -38,7 +39,6 @@
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/irq.h>
-#include <asm/sched_clock.h>
 #include <asm/system_misc.h>
 #include <asm/mach/map.h>
@@ -531,9 +531,9 @@ static void __init ixp4xx_clockevent_init(void)
                                        0xf, 0xfffffffe);
 }
-void ixp4xx_restart(char mode, const char *cmd)
+void ixp4xx_restart(enum reboot_mode mode, const char *cmd)
 {
-        if ( 1 && mode == 's') {
+        if ( 1 && mode == REBOOT_SOFT) {
                /* Jump into ROM at address 0 */
                soft_restart(0);
        } else {
@@ -559,7 +559,7 @@ void ixp4xx_restart(char mode, const char *cmd)
 * fallback to the default.
 */
-static void __iomem *ixp4xx_ioremap_caller(unsigned long addr, size_t size,
+static void __iomem *ixp4xx_ioremap_caller(phys_addr_t addr, size_t size,
                                           unsigned int mtype, void *caller)
 {
        if (!is_pci_memory(addr))
diff --git a/arch/arm/mach-ixp4xx/dsmg600-setup.c b/arch/arm/mach-ixp4xx/dsmg600-setup.c
index 5d413f8c5700..63de1b3fd06b 100644
--- a/arch/arm/mach-ixp4xx/dsmg600-setup.c
+++ b/arch/arm/mach-ixp4xx/dsmg600-setup.c
@@ -27,6 +27,8 @@
 #include <linux/i2c.h>
 #include <linux/i2c-gpio.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
diff --git a/arch/arm/mach-ixp4xx/include/mach/platform.h b/arch/arm/mach-ixp4xx/include/mach/platform.h
index db5afb69c123..4c4c6a6f4526 100644
--- a/arch/arm/mach-ixp4xx/include/mach/platform.h
+++ b/arch/arm/mach-ixp4xx/include/mach/platform.h
@@ -13,6 +13,8 @@
 #ifndef __ASSEMBLY__
+#include <linux/reboot.h>
 #include <asm/types.h>
 #ifndef __ARMEB__
@@ -123,7 +125,7 @@ extern void ixp4xx_init_early(void);
 extern void ixp4xx_init_irq(void);
 extern void ixp4xx_sys_init(void);
 extern void ixp4xx_timer_init(void);
-extern void ixp4xx_restart(char, const char *);
+extern void ixp4xx_restart(enum reboot_mode, const char *);
 extern void ixp4xx_pci_preinit(void);
 struct pci_sys_data;
 extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
diff --git a/arch/arm/mach-ixp4xx/include/mach/timex.h b/arch/arm/mach-ixp4xx/include/mach/timex.h
index c9e930f29339..0396d89f947c 100644
--- a/arch/arm/mach-ixp4xx/include/mach/timex.h
+++ b/arch/arm/mach-ixp4xx/include/mach/timex.h
@@ -3,7 +3,7 @@
 * 
 */
-#include <mach/hardware.h>
+#include <mach/ixp4xx-regs.h>
 /*
 * We use IXP425 General purpose timer for our timer needs, it runs at 
diff --git a/arch/arm/mach-ixp4xx/omixp-setup.c b/arch/arm/mach-ixp4xx/omixp-setup.c
index 46a89f5e8269..75ef03dc9964 100644
--- a/arch/arm/mach-ixp4xx/omixp-setup.c
+++ b/arch/arm/mach-ixp4xx/omixp-setup.c
@@ -27,6 +27,8 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
+#include <mach/hardware.h>
 static struct resource omixp_flash_resources[] = {
        {
                .flags  = IORESOURCE_MEM,
diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig
new file mode 100644
index 000000000000..51a50e996840
--- /dev/null
+++ b/arch/arm/mach-keystone/Kconfig
@@ -0,0 +1,15 @@
+config ARCH_KEYSTONE
+        bool "Texas Instruments Keystone Devices"
+        depends on ARCH_MULTI_V7
+        select CPU_V7
+        select ARM_GIC
+        select HAVE_ARM_ARCH_TIMER
+        select HAVE_SMP
+        select CLKSRC_MMIO
+        select GENERIC_CLOCKEVENTS
+        select HAVE_SCHED_CLOCK
+        select ARCH_WANT_OPTIONAL_GPIOLIB
+        select ARM_ERRATA_798181 if SMP
+        help
+          Support for boards based on the Texas Instruments Keystone family of
+          SoCs.
diff --git a/arch/arm/mach-keystone/Makefile b/arch/arm/mach-keystone/Makefile
new file mode 100644
index 000000000000..ddc52b05dc84
--- /dev/null
+++ b/arch/arm/mach-keystone/Makefile
@@ -0,0 +1,6 @@
+obj-y                                   := keystone.o smc.o
+plus_sec := $(call as-instr,.arch_extension sec,+sec)
+AFLAGS_smc.o                            :=-Wa,-march=armv7-a$(plus_sec)
+obj-$(CONFIG_SMP)                       += platsmp.o
diff --git a/arch/arm/mach-keystone/Makefile.boot b/arch/arm/mach-keystone/Makefile.boot
new file mode 100644
index 000000000000..f3835c43af61
--- /dev/null
+++ b/arch/arm/mach-keystone/Makefile.boot
@@ -0,0 +1 @@
+zreladdr-y      := 0x80008000
diff --git a/arch/arm/mach-keystone/keystone.c b/arch/arm/mach-keystone/keystone.c
new file mode 100644
index 000000000000..b661c5c2870a
--- /dev/null
+++ b/arch/arm/mach-keystone/keystone.c
@@ -0,0 +1,75 @@
+/*
+ * Keystone2 based boards and SOC related code.
+ *
+ * Copyright 2013 Texas Instruments, Inc.
+ *      Cyril Chemparathy <cyril@ti.com>
+ *      Santosh Shilimkar <santosh.shillimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/init.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <asm/setup.h>
+#include <asm/mach/map.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/smp_plat.h>
+#include "keystone.h"
+#define PLL_RESET_WRITE_KEY_MASK                0xffff0000
+#define PLL_RESET_WRITE_KEY                     0x5a69
+#define PLL_RESET                               BIT(16)
+static void __iomem *keystone_rstctrl;
+static void __init keystone_init(void)
+{
+        struct device_node *node;
+        node = of_find_compatible_node(NULL, NULL, "ti,keystone-reset");
+        if (WARN_ON(!node))
+                pr_warn("ti,keystone-reset node undefined\n");
+        keystone_rstctrl = of_iomap(node, 0);
+        if (WARN_ON(!keystone_rstctrl))
+                pr_warn("ti,keystone-reset iomap error\n");
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+static const char *keystone_match[] __initconst = {
+        "ti,keystone-evm",
+        NULL,
+};
+void keystone_restart(enum reboot_mode mode, const char *cmd)
+{
+        u32 val;
+        BUG_ON(!keystone_rstctrl);
+        /* Enable write access to RSTCTRL */
+        val = readl(keystone_rstctrl);
+        val &= PLL_RESET_WRITE_KEY_MASK;
+        val |= PLL_RESET_WRITE_KEY;
+        writel(val, keystone_rstctrl);
+        /* Reset the SOC */
+        val = readl(keystone_rstctrl);
+        val &= ~PLL_RESET;
+        writel(val, keystone_rstctrl);
+}
+DT_MACHINE_START(KEYSTONE, "Keystone")
+        .smp            = smp_ops(keystone_smp_ops),
+        .init_machine   = keystone_init,
+        .dt_compat      = keystone_match,
+        .restart        = keystone_restart,
+MACHINE_END
diff --git a/arch/arm/mach-keystone/keystone.h b/arch/arm/mach-keystone/keystone.h
new file mode 100644
index 000000000000..60bef9dedb12
--- /dev/null
+++ b/arch/arm/mach-keystone/keystone.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2013 Texas Instruments, Inc.
+ *      Cyril Chemparathy <cyril@ti.com>
+ *      Santosh Shilimkar <santosh.shillimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+#ifndef __KEYSTONE_H__
+#define __KEYSTONE_H__
+#define KEYSTONE_MON_CPU_UP_IDX         0x00
+#ifndef __ASSEMBLER__
+extern struct smp_operations keystone_smp_ops;
+extern void secondary_startup(void);
+extern u32 keystone_cpu_smc(u32 command, u32 cpu, u32 addr);
+#endif /* __ASSEMBLER__ */
+#endif /* __KEYSTONE_H__ */
diff --git a/arch/arm/mach-keystone/platsmp.c b/arch/arm/mach-keystone/platsmp.c
new file mode 100644
index 000000000000..14378e3fef16
--- /dev/null
+++ b/arch/arm/mach-keystone/platsmp.c
@@ -0,0 +1,43 @@
+/*
+ * Keystone SOC SMP platform code
+ *
+ * Copyright 2013 Texas Instruments, Inc.
+ *      Cyril Chemparathy <cyril@ti.com>
+ *      Santosh Shilimkar <santosh.shillimkar@ti.com>
+ *
+ * Based on platsmp.c, Copyright (C) 2002 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <asm/smp_plat.h>
+#include <asm/prom.h>
+#include "keystone.h"
+static int keystone_smp_boot_secondary(unsigned int cpu,
+                                                struct task_struct *idle)
+{
+        unsigned long start = virt_to_phys(&secondary_startup);
+        int error;
+        pr_debug("keystone-smp: booting cpu %d, vector %08lx\n",
+                 cpu, start);
+        error = keystone_cpu_smc(KEYSTONE_MON_CPU_UP_IDX, cpu, start);
+        if (error)
+                pr_err("CPU %d bringup failed with %d\n", cpu, error);
+        return error;
+}
+struct smp_operations keystone_smp_ops __initdata = {
+        .smp_init_cpus          = arm_dt_init_cpu_maps,
+        .smp_boot_secondary     = keystone_smp_boot_secondary,
+};
diff --git a/arch/arm/mach-keystone/smc.S b/arch/arm/mach-keystone/smc.S
new file mode 100644
index 000000000000..9b9e4f7b241e
--- /dev/null
+++ b/arch/arm/mach-keystone/smc.S
@@ -0,0 +1,29 @@
+/*
+ * Keystone Secure APIs
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software,you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+/**
+ * u32 keystone_cpu_smc(u32 command, u32 cpu, u32 addr)
+ *
+ * Low level CPU monitor API
+ * @command:    Monitor command.
+ * @cpu:        CPU Number
+ * @addr:       Kernel jump address for boot CPU
+ *
+ * Return: Non zero value on failure
+ */
+ENTRY(keystone_cpu_smc)
+        stmfd   sp!, {r4-r12, lr}
+        smc     #0
+        dsb
+        ldmfd   sp!, {r4-r12, pc}
+ENDPROC(keystone_cpu_smc)
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 7509a89af967..b634f9650a7b 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -8,12 +8,6 @@ config MACH_D2NET_V2
          Say 'Y' here if you want your kernel to support the
          LaCie d2 Network v2 NAS.
-config MACH_DB88F6281_BP
-        bool "Marvell DB-88F6281-BP Development Board"
-        help
-          Say 'Y' here if you want your kernel to support the
-          Marvell DB-88F6281-BP Development Board.
 config MACH_DOCKSTAR
        bool "Seagate FreeAgent DockStar"
        help
@@ -134,13 +128,12 @@ comment "Device tree entries"
 config ARCH_KIRKWOOD_DT
        bool "Marvell Kirkwood Flattened Device Tree"
+        select KIRKWOOD_CLK
        select POWER_SUPPLY
        select POWER_RESET
        select POWER_RESET_GPIO
        select REGULATOR
        select REGULATOR_FIXED_VOLTAGE
-        select MVEBU_CLK_CORE
-        select MVEBU_CLK_GATING
        select USE_OF
        help
          Say 'Y' here if you want your kernel to support the
@@ -153,6 +146,13 @@ config MACH_CLOUDBOX_DT
          Say 'Y' here if you want your kernel to support the LaCie
          CloudBox NAS, using Flattened Device Tree.
+config MACH_DB88F628X_BP_DT
+        bool "Marvell DB-88F628x-BP Development Board (Flattened Device Tree)"
+        help
+          Say 'Y' here if you want your kernel to support the Marvell
+          DB-88F6281-BP and DB-88F6282-BP Development Board (Flattened
+          Device Tree).
 config MACH_DLINK_KIRKWOOD_DT
        bool "D-Link Kirkwood-based NAS (Flattened Device Tree)"
        select ARCH_KIRKWOOD_DT
@@ -227,6 +227,7 @@ config MACH_KM_KIRKWOOD_DT
 config MACH_LSXL_DT
        bool "Buffalo Linkstation LS-XHL, LS-CHLv2 (Flattened Device Tree)"
        select ARCH_KIRKWOOD_DT
+        select POWER_RESET_RESTART
        help
          Say 'Y' here if you want your kernel to support the
          Buffalo Linkstation LS-XHL & LS-CHLv2 devices, using
@@ -272,14 +273,6 @@ config MACH_NETSPACE_V2_DT
          Say 'Y' here if you want your kernel to support the LaCie
          Network Space v2 NAS, using Flattened Device Tree.
-config MACH_NSA310_DT
-        bool "ZyXEL NSA-310 (Flattened Device Tree)"
-        select ARCH_KIRKWOOD_DT
-        select ARM_ATAG_DTB_COMPAT
-        help
-          Say 'Y' here if you want your kernel to support the
-          ZyXEL NSA-310 board (Flattened Device Tree).
 config MACH_OPENBLOCKS_A6_DT
        bool "Plat'Home OpenBlocks A6 (Flattened Device Tree)"
        select ARCH_KIRKWOOD_DT
@@ -296,6 +289,13 @@ config MACH_READYNAS_DT
          Say 'Y' here if you want your kernel to support the
          NETGEAR ReadyNAS Duo v2 using Fattened Device Tree.
+config MACH_SHEEVAPLUG_DT
+        bool "Marvell (eSATA) SheevaPlug (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell (eSATA) SheevaPlug (Flattened Device Tree).
 config MACH_TOPKICK_DT
        bool "USI Topkick (Flattened Device Tree)"
        select ARCH_KIRKWOOD_DT
@@ -308,6 +308,7 @@ config MACH_TS219_DT
        select ARCH_KIRKWOOD_DT
        select ARM_APPENDED_DTB
        select ARM_ATAG_DTB_COMPAT
+        select POWER_RESET_QNAP
        help
          Say 'Y' here if you want your kernel to support the QNAP
          TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index e1f3735d3415..ac4cd75dd499 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -1,7 +1,6 @@
 obj-y                           += common.o irq.o pcie.o mpp.o
 obj-$(CONFIG_MACH_D2NET_V2)             += d2net_v2-setup.o lacie_v2-common.o
-obj-$(CONFIG_MACH_DB88F6281_BP)         += db88f6281-bp-setup.o
 obj-$(CONFIG_MACH_DOCKSTAR)             += dockstar-setup.o
 obj-$(CONFIG_MACH_ESATA_SHEEVAPLUG)     += sheevaplug-setup.o
 obj-$(CONFIG_MACH_GURUPLUG)             += guruplug-setup.o
@@ -21,6 +20,7 @@ obj-$(CONFIG_MACH_TS41X)		+= ts41x-setup.o tsx1x-common.o
 obj-$(CONFIG_ARCH_KIRKWOOD_DT)          += board-dt.o
 obj-$(CONFIG_MACH_CLOUDBOX_DT)          += board-ns2.o
+obj-$(CONFIG_MACH_DB88F628X_BP_DT)      += board-db88f628x-bp.o
 obj-$(CONFIG_MACH_DLINK_KIRKWOOD_DT)    += board-dnskw.o
 obj-$(CONFIG_MACH_DOCKSTAR_DT)          += board-dockstar.o
 obj-$(CONFIG_MACH_DREAMPLUG_DT)         += board-dreamplug.o
@@ -37,8 +37,8 @@ obj-$(CONFIG_MACH_NETSPACE_LITE_V2_DT)	+= board-ns2.o
 obj-$(CONFIG_MACH_NETSPACE_MAX_V2_DT)   += board-ns2.o
 obj-$(CONFIG_MACH_NETSPACE_MINI_V2_DT)  += board-ns2.o
 obj-$(CONFIG_MACH_NETSPACE_V2_DT)       += board-ns2.o
-obj-$(CONFIG_MACH_NSA310_DT)            += board-nsa310.o
 obj-$(CONFIG_MACH_OPENBLOCKS_A6_DT)     += board-openblocks_a6.o
 obj-$(CONFIG_MACH_READYNAS_DT)          += board-readynas.o
+obj-$(CONFIG_MACH_SHEEVAPLUG_DT)        += board-sheevaplug.o
 obj-$(CONFIG_MACH_TOPKICK_DT)           += board-usi_topkick.o
 obj-$(CONFIG_MACH_TS219_DT)             += board-ts219.o tsx1x-common.o
diff --git a/arch/arm/mach-kirkwood/board-db88f628x-bp.c b/arch/arm/mach-kirkwood/board-db88f628x-bp.c
new file mode 100644
index 000000000000..2f574bc8ed40
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-db88f628x-bp.c
@@ -0,0 +1,24 @@
+/*
+ * Saeed Bishara <saeed@marvell.com>
+ *
+ * Marvell DB-88F628{1,2}-BP Development Board Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/mv643xx_eth.h>
+#include "common.h"
+static struct mv643xx_eth_platform_data db88f628x_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
+};
+void __init db88f628x_init(void)
+{
+        kirkwood_ge00_init(&db88f628x_ge00_data);
+}
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index e9647b80cb59..6e122ed3282f 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -15,7 +15,6 @@
 #include <linux/of.h>
 #include <linux/of_platform.h>
 #include <linux/clk-provider.h>
-#include <linux/clk/mvebu.h>
 #include <linux/kexec.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -25,11 +24,6 @@
 #include <plat/common.h>
 #include "common.h"
-static struct of_device_id kirkwood_dt_match_table[] __initdata = {
-        { .compatible = "simple-bus", },
-        { }
-};
 /*
 * There are still devices that doesn't know about DT yet.  Get clock
 * gates here and add a clock lookup alias, so that old platform
@@ -77,7 +71,7 @@ static void __init kirkwood_legacy_clk_init(void)
 static void __init kirkwood_of_clk_init(void)
 {
-        mvebu_clocks_init();
+        of_clk_init(NULL);
        kirkwood_legacy_clk_init();
 }
@@ -97,6 +91,8 @@ static void __init kirkwood_dt_init(void)
        kirkwood_l2_init();
+        kirkwood_cpufreq_init();
        /* Setup root of clk tree */
        kirkwood_of_clk_init();
@@ -112,6 +108,9 @@ static void __init kirkwood_dt_init(void)
        if (of_machine_is_compatible("globalscale,guruplug"))
                guruplug_dt_init();
+        if (of_machine_is_compatible("globalscale,sheevaplug"))
+                sheevaplug_dt_init();
        if (of_machine_is_compatible("dlink,dns-kirkwood"))
                dnskw_init();
@@ -147,6 +146,10 @@ static void __init kirkwood_dt_init(void)
            of_machine_is_compatible("lacie,netspace_v2"))
                ns2_init();
+        if (of_machine_is_compatible("marvell,db-88f6281-bp") ||
+            of_machine_is_compatible("marvell,db-88f6282-bp"))
+                db88f628x_init();
        if (of_machine_is_compatible("mpl,cec4"))
                mplcec4_init();
@@ -159,12 +162,13 @@ static void __init kirkwood_dt_init(void)
        if (of_machine_is_compatible("usi,topkick"))
                usi_topkick_init();
-        of_platform_populate(NULL, kirkwood_dt_match_table, NULL, NULL);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 static const char * const kirkwood_dt_board_compat[] = {
        "globalscale,dreamplug",
        "globalscale,guruplug",
+        "globalscale,sheevaplug",
        "dlink,dns-320",
        "dlink,dns-325",
        "iom,iconnect",
@@ -181,6 +185,8 @@ static const char * const kirkwood_dt_board_compat[] = {
        "lacie,netspace_max_v2",
        "lacie,netspace_mini_v2",
        "lacie,netspace_v2",
+        "marvell,db-88f6281-bp",
+        "marvell,db-88f6282-bp",
        "mpl,cec4",
        "netgear,readynas-duo-v2",
        "plathome,openblocks-a6",
diff --git a/arch/arm/mach-kirkwood/board-iconnect.c b/arch/arm/mach-kirkwood/board-iconnect.c
index c8ebde4919e2..98b5ad1bba90 100644
--- a/arch/arm/mach-kirkwood/board-iconnect.c
+++ b/arch/arm/mach-kirkwood/board-iconnect.c
@@ -22,11 +22,3 @@ void __init iconnect_init(void)
 {
        kirkwood_ge00_init(&iconnect_ge00_data);
 }
-static int __init iconnect_pci_init(void)
-{
-        if (of_machine_is_compatible("iom,iconnect"))
-                kirkwood_pcie_init(KW_PCIE0);
-        return 0;
-}
-subsys_initcall(iconnect_pci_init);
diff --git a/arch/arm/mach-kirkwood/board-lsxl.c b/arch/arm/mach-kirkwood/board-lsxl.c
index 4ec8b7ae784a..348395238df6 100644
--- a/arch/arm/mach-kirkwood/board-lsxl.c
+++ b/arch/arm/mach-kirkwood/board-lsxl.c
@@ -25,19 +25,6 @@ static struct mv643xx_eth_platform_data lsxl_ge01_data = {
        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
 };
-/*
- * On the LS-XHL/LS-CHLv2, the shutdown process is following:
- * - Userland monitors key events until the power switch goes to off position
- * - The board reboots
- * - U-boot starts and goes into an idle mode waiting for the user
- *   to move the switch to ON position
- *
- */
-static void lsxl_power_off(void)
-{
-        kirkwood_restart('h', NULL);
-}
 void __init lsxl_init(void)
 {
        /*
@@ -46,7 +33,4 @@ void __init lsxl_init(void)
        kirkwood_ge00_init(&lsxl_ge00_data);
        kirkwood_ge01_init(&lsxl_ge01_data);
-        /* register power-off method */
-        pm_power_off = lsxl_power_off;
 }
diff --git a/arch/arm/mach-kirkwood/board-mplcec4.c b/arch/arm/mach-kirkwood/board-mplcec4.c
index 7d6dc669e17f..938712e248f1 100644
--- a/arch/arm/mach-kirkwood/board-mplcec4.c
+++ b/arch/arm/mach-kirkwood/board-mplcec4.c
@@ -29,7 +29,6 @@ void __init mplcec4_init(void)
         */
        kirkwood_ge00_init(&mplcec4_ge00_data);
        kirkwood_ge01_init(&mplcec4_ge01_data);
-        kirkwood_pcie_init(KW_PCIE0);
 }
diff --git a/arch/arm/mach-kirkwood/board-nsa310.c b/arch/arm/mach-kirkwood/board-nsa310.c
deleted file mode 100644
index 55ade93b93bf..000000000000
--- a/arch/arm/mach-kirkwood/board-nsa310.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/nsa-310-setup.c
- *
- * ZyXEL NSA-310 Setup
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <mach/kirkwood.h>
-#include <linux/of.h>
-#include "common.h"
-static int __init nsa310_pci_init(void)
-{
-        if (of_machine_is_compatible("zyxel,nsa310"))
-                kirkwood_pcie_init(KW_PCIE0);
-        return 0;
-}
-subsys_initcall(nsa310_pci_init);
diff --git a/arch/arm/mach-kirkwood/board-readynas.c b/arch/arm/mach-kirkwood/board-readynas.c
index fb42c20e273f..341b82d9cadb 100644
--- a/arch/arm/mach-kirkwood/board-readynas.c
+++ b/arch/arm/mach-kirkwood/board-readynas.c
@@ -24,5 +24,4 @@ static struct mv643xx_eth_platform_data netgear_readynas_ge00_data = {
 void __init netgear_readynas_init(void)
 {
        kirkwood_ge00_init(&netgear_readynas_ge00_data);
-        kirkwood_pcie_init(KW_PCIE0);
 }
diff --git a/arch/arm/mach-kirkwood/board-sheevaplug.c b/arch/arm/mach-kirkwood/board-sheevaplug.c
new file mode 100644
index 000000000000..fa389373ca74
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-sheevaplug.c
@@ -0,0 +1,27 @@
+/*
+ * arch/arm/mach-kirkwood/board-sheevaplug.c
+ *
+ * Marvell Sheevaplug Reference Board Init for drivers not converted to
+ * flattened device tree yet.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mv643xx_eth.h>
+#include "common.h"
+static struct mv643xx_eth_platform_data sheevaplug_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
+};
+void __init sheevaplug_dt_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_ge00_init(&sheevaplug_ge00_data);
+}
diff --git a/arch/arm/mach-kirkwood/board-ts219.c b/arch/arm/mach-kirkwood/board-ts219.c
index 4695d5f35fc9..860f44ab457d 100644
--- a/arch/arm/mach-kirkwood/board-ts219.c
+++ b/arch/arm/mach-kirkwood/board-ts219.c
@@ -23,7 +23,6 @@
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
 #include "common.h"
-#include "tsx1x-common.h"
 static struct mv643xx_eth_platform_data qnap_ts219_ge00_data = {
        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
@@ -38,6 +37,4 @@ void __init qnap_dt_ts219_init(void)
                qnap_ts219_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
        kirkwood_ge00_init(&qnap_ts219_ge00_data);
-        pm_power_off = qnap_tsx1x_power_off;
 }
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index f38922897563..e9238b5567ee 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -20,6 +20,7 @@
 #include <linux/mv643xx_i2c.h>
 #include <linux/timex.h>
 #include <linux/kexec.h>
+#include <linux/reboot.h>
 #include <net/dsa.h>
 #include <asm/page.h>
 #include <asm/mach/map.h>
@@ -598,6 +599,29 @@ void __init kirkwood_audio_init(void)
 }
 /*****************************************************************************
+ * CPU Frequency
+ ****************************************************************************/
+static struct resource kirkwood_cpufreq_resources[] = {
+        [0] = {
+                .start  = CPU_CONTROL_PHYS,
+                .end    = CPU_CONTROL_PHYS + 3,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+static struct platform_device kirkwood_cpufreq_device = {
+        .name           = "kirkwood-cpufreq",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(kirkwood_cpufreq_resources),
+        .resource       = kirkwood_cpufreq_resources,
+};
+void __init kirkwood_cpufreq_init(void)
+{
+        platform_device_register(&kirkwood_cpufreq_device);
+}
+/*****************************************************************************
 * General
 ****************************************************************************/
 /*
@@ -648,30 +672,6 @@ char * __init kirkwood_id(void)
 void __init kirkwood_setup_wins(void)
 {
-        /*
-         * The PCIe windows will no longer be statically allocated
-         * here once Kirkwood is migrated to the pci-mvebu driver.
-         */
-        mvebu_mbus_add_window_remap_flags("pcie0.0",
-                                          KIRKWOOD_PCIE_IO_PHYS_BASE,
-                                          KIRKWOOD_PCIE_IO_SIZE,
-                                          KIRKWOOD_PCIE_IO_BUS_BASE,
-                                          MVEBU_MBUS_PCI_IO);
-        mvebu_mbus_add_window_remap_flags("pcie0.0",
-                                          KIRKWOOD_PCIE_MEM_PHYS_BASE,
-                                          KIRKWOOD_PCIE_MEM_SIZE,
-                                          MVEBU_MBUS_NO_REMAP,
-                                          MVEBU_MBUS_PCI_MEM);
-        mvebu_mbus_add_window_remap_flags("pcie1.0",
-                                          KIRKWOOD_PCIE1_IO_PHYS_BASE,
-                                          KIRKWOOD_PCIE1_IO_SIZE,
-                                          KIRKWOOD_PCIE1_IO_BUS_BASE,
-                                          MVEBU_MBUS_PCI_IO);
-        mvebu_mbus_add_window_remap_flags("pcie1.0",
-                                          KIRKWOOD_PCIE1_MEM_PHYS_BASE,
-                                          KIRKWOOD_PCIE1_MEM_SIZE,
-                                          MVEBU_MBUS_NO_REMAP,
-                                          MVEBU_MBUS_PCI_MEM);
        mvebu_mbus_add_window("nand", KIRKWOOD_NAND_MEM_PHYS_BASE,
                              KIRKWOOD_NAND_MEM_SIZE);
        mvebu_mbus_add_window("sram", KIRKWOOD_SRAM_PHYS_BASE,
@@ -723,7 +723,7 @@ void __init kirkwood_init(void)
 #endif
 }
-void kirkwood_restart(char mode, const char *cmd)
+void kirkwood_restart(enum reboot_mode mode, const char *cmd)
 {
        /*
         * Enable soft reset to assert RSTOUTn.
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 21da3b1ebd7b..fcf3ba682e24 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -11,6 +11,8 @@
 #ifndef __ARCH_KIRKWOOD_COMMON_H
 #define __ARCH_KIRKWOOD_COMMON_H
+#include <linux/reboot.h>
 struct dsa_platform_data;
 struct mv643xx_eth_platform_data;
 struct mv_sata_platform_data;
@@ -51,7 +53,9 @@ void kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
                            int (*dev_ready)(struct mtd_info *));
 void kirkwood_audio_init(void);
 void kirkwood_cpuidle_init(void);
-void kirkwood_restart(char, const char *);
+void kirkwood_cpufreq_init(void);
+void kirkwood_restart(enum reboot_mode, const char *);
 void kirkwood_clk_init(void);
 /* board init functions for boards not fully converted to fdt */
@@ -65,6 +69,11 @@ void guruplug_dt_init(void);
 #else
 static inline void guruplug_dt_init(void) {};
 #endif
+#ifdef CONFIG_MACH_SHEEVAPLUG_DT
+void sheevaplug_dt_init(void);
+#else
+static inline void sheevaplug_dt_init(void) {};
+#endif
 #ifdef CONFIG_MACH_TS219_DT
 void qnap_dt_ts219_init(void);
 #else
@@ -119,6 +128,12 @@ void km_kirkwood_init(void);
 static inline void km_kirkwood_init(void) {};
 #endif
+#ifdef CONFIG_MACH_DB88F628X_BP_DT
+void db88f628x_init(void);
+#else
+static inline void db88f628x_init(void) {};
+#endif
 #ifdef CONFIG_MACH_MPLCEC4_DT
 void mplcec4_init(void);
 #else
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
deleted file mode 100644
index 5a369fe74754..000000000000
--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/db88f6281-bp-setup.c
- *
- * Marvell DB-88F6281-BP Development Board Setup
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/sizes.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/partitions.h>
-#include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/kirkwood.h>
-#include <linux/platform_data/mmc-mvsdio.h>
-#include "common.h"
-#include "mpp.h"
-static struct mtd_partition db88f6281_nand_parts[] = {
-        {
-                .name = "u-boot",
-                .offset = 0,
-                .size = SZ_1M
-        }, {
-                .name = "uImage",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size = SZ_4M
-        }, {
-                .name = "root",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size = MTDPART_SIZ_FULL
-        },
-};
-static struct mv643xx_eth_platform_data db88f6281_ge00_data = {
-        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
-};
-static struct mv_sata_platform_data db88f6281_sata_data = {
-        .n_ports        = 2,
-};
-static struct mvsdio_platform_data db88f6281_mvsdio_data = {
-        .gpio_write_protect     = 37,
-        .gpio_card_detect       = 38,
-};
-static unsigned int db88f6281_mpp_config[] __initdata = {
-        MPP0_NF_IO2,
-        MPP1_NF_IO3,
-        MPP2_NF_IO4,
-        MPP3_NF_IO5,
-        MPP4_NF_IO6,
-        MPP5_NF_IO7,
-        MPP18_NF_IO0,
-        MPP19_NF_IO1,
-        MPP37_GPIO,
-        MPP38_GPIO,
-        0
-};
-static void __init db88f6281_init(void)
-{
-        /*
-         * Basic setup. Needs to be called early.
-         */
-        kirkwood_init();
-        kirkwood_mpp_conf(db88f6281_mpp_config);
-        kirkwood_nand_init(ARRAY_AND_SIZE(db88f6281_nand_parts), 25);
-        kirkwood_ehci_init();
-        kirkwood_ge00_init(&db88f6281_ge00_data);
-        kirkwood_sata_init(&db88f6281_sata_data);
-        kirkwood_uart0_init();
-        kirkwood_sdio_init(&db88f6281_mvsdio_data);
-}
-static int __init db88f6281_pci_init(void)
-{
-        if (machine_is_db88f6281_bp()) {
-                u32 dev, rev;
-                kirkwood_pcie_id(&dev, &rev);
-                if (dev == MV88F6282_DEV_ID)
-                        kirkwood_pcie_init(KW_PCIE1 | KW_PCIE0);
-                else
-                        kirkwood_pcie_init(KW_PCIE0);
-        }
-        return 0;
-}
-subsys_initcall(db88f6281_pci_init);
-MACHINE_START(DB88F6281_BP, "Marvell DB-88F6281-BP Development Board")
-        /* Maintainer: Saeed Bishara <saeed@marvell.com> */
-        .atag_offset    = 0x100,
-        .init_machine   = db88f6281_init,
-        .map_io         = kirkwood_map_io,
-        .init_early     = kirkwood_init_early,
-        .init_irq       = kirkwood_init_irq,
-        .init_time      = kirkwood_timer_init,
-        .restart        = kirkwood_restart,
-MACHINE_END
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
index 5c82b7dce4e2..91242c944d7a 100644
--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
@@ -17,17 +17,16 @@
 #define CPU_CONFIG_ERROR_PROP   0x00000004
 #define CPU_CONTROL             (BRIDGE_VIRT_BASE + 0x0104)
+#define CPU_CONTROL_PHYS        (BRIDGE_PHYS_BASE + 0x0104)
 #define CPU_RESET               0x00000002
 #define RSTOUTn_MASK            (BRIDGE_VIRT_BASE + 0x0108)
-#define WDT_RESET_OUT_EN        0x00000002
 #define SOFT_RESET_OUT_EN       0x00000004
 #define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE + 0x010c)
 #define SOFT_RESET              0x00000001
 #define BRIDGE_CAUSE            (BRIDGE_VIRT_BASE + 0x0110)
-#define WDT_INT_REQ             0x0008
 #define BRIDGE_INT_TIMER1_CLR   (~0x0004)
@@ -69,6 +68,7 @@
 #define CGC_RUNIT               (1 << 7)
 #define CGC_XOR0                (1 << 8)
 #define CGC_AUDIO               (1 << 9)
+#define CGC_POWERSAVE           (1 << 11)
 #define CGC_SATA0               (1 << 14)
 #define CGC_SATA1               (1 << 15)
 #define CGC_XOR1                (1 << 16)
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index 7f43e6c2f8c0..ddcb09f5bdd3 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -12,6 +12,7 @@
 #include <linux/pci.h>
 #include <linux/slab.h>
 #include <linux/clk.h>
+#include <linux/mbus.h>
 #include <video/vga.h>
 #include <asm/irq.h>
 #include <asm/mach/pci.h>
@@ -253,6 +254,27 @@ static void __init add_pcie_port(int index, void __iomem *base)
 void __init kirkwood_pcie_init(unsigned int portmask)
 {
+        mvebu_mbus_add_window_remap_flags("pcie0.0",
+                                          KIRKWOOD_PCIE_IO_PHYS_BASE,
+                                          KIRKWOOD_PCIE_IO_SIZE,
+                                          KIRKWOOD_PCIE_IO_BUS_BASE,
+                                          MVEBU_MBUS_PCI_IO);
+        mvebu_mbus_add_window_remap_flags("pcie0.0",
+                                          KIRKWOOD_PCIE_MEM_PHYS_BASE,
+                                          KIRKWOOD_PCIE_MEM_SIZE,
+                                          MVEBU_MBUS_NO_REMAP,
+                                          MVEBU_MBUS_PCI_MEM);
+        mvebu_mbus_add_window_remap_flags("pcie1.0",
+                                          KIRKWOOD_PCIE1_IO_PHYS_BASE,
+                                          KIRKWOOD_PCIE1_IO_SIZE,
+                                          KIRKWOOD_PCIE1_IO_BUS_BASE,
+                                          MVEBU_MBUS_PCI_IO);
+        mvebu_mbus_add_window_remap_flags("pcie1.0",
+                                          KIRKWOOD_PCIE1_MEM_PHYS_BASE,
+                                          KIRKWOOD_PCIE1_MEM_SIZE,
+                                          MVEBU_MBUS_NO_REMAP,
+                                          MVEBU_MBUS_PCI_MEM);
        vga_base = KIRKWOOD_PCIE_MEM_PHYS_BASE;
        if (portmask & KW_PCIE0)
diff --git a/arch/arm/mach-ks8695/generic.h b/arch/arm/mach-ks8695/generic.h
index 6e97ce462d73..43253f8e6de4 100644
--- a/arch/arm/mach-ks8695/generic.h
+++ b/arch/arm/mach-ks8695/generic.h
@@ -12,5 +12,5 @@
 extern __init void ks8695_map_io(void);
 extern __init void ks8695_init_irq(void);
-extern void ks8695_restart(char, const char *);
+extern void ks8695_restart(enum reboot_mode, const char *);
 extern void ks8695_timer_init(void);
diff --git a/arch/arm/mach-ks8695/time.c b/arch/arm/mach-ks8695/time.c
index c272a3863d5f..426c97662f5b 100644
--- a/arch/arm/mach-ks8695/time.c
+++ b/arch/arm/mach-ks8695/time.c
@@ -154,11 +154,11 @@ void __init ks8695_timer_init(void)
        setup_irq(KS8695_IRQ_TIMER1, &ks8695_timer_irq);
 }
-void ks8695_restart(char mode, const char *cmd)
+void ks8695_restart(enum reboot_mode reboot_mode, const char *cmd)
 {
        unsigned int reg;
-        if (mode == 's')
+        if (reboot_mode == REBOOT_SOFT)
                soft_restart(0);
        /* disable timer0 */
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
index 0d4db8c544b5..d7aa54c25c59 100644
--- a/arch/arm/mach-lpc32xx/common.c
+++ b/arch/arm/mach-lpc32xx/common.c
@@ -207,11 +207,11 @@ void __init lpc32xx_map_io(void)
        iotable_init(lpc32xx_io_desc, ARRAY_SIZE(lpc32xx_io_desc));
 }
-void lpc23xx_restart(char mode, const char *cmd)
+void lpc23xx_restart(enum reboot_mode mode, const char *cmd)
 {
        switch (mode) {
-        case 's':
+        case REBOOT_SOFT:
-        case 'h':
+        case REBOOT_HARD:
                lpc32xx_watchdog_reset();
                break;
diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h
index e0b26062a272..1cd8853b2f9b 100644
--- a/arch/arm/mach-lpc32xx/common.h
+++ b/arch/arm/mach-lpc32xx/common.h
@@ -21,6 +21,7 @@
 #include <mach/board.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 /*
 * Other arch specific structures and functions
@@ -29,7 +30,7 @@ extern void lpc32xx_timer_init(void);
 extern void __init lpc32xx_init_irq(void);
 extern void __init lpc32xx_map_io(void);
 extern void __init lpc32xx_serial_init(void);
-extern void lpc23xx_restart(char, const char *);
+extern void lpc23xx_restart(enum reboot_mode, const char *);
 /*
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index c1cd5a943ab1..e54f87ec2e4a 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -182,8 +182,8 @@ static void pl08x_put_signal(const struct pl08x_channel_data *cd, int ch)
 static struct pl08x_platform_data pl08x_pd = {
        .slave_channels = &pl08x_slave_channels[0],
        .num_slave_channels = ARRAY_SIZE(pl08x_slave_channels),
-        .get_signal = pl08x_get_signal,
+        .get_xfer_signal = pl08x_get_signal,
-        .put_signal = pl08x_put_signal,
+        .put_xfer_signal = pl08x_put_signal,
        .lli_buses = PL08X_AHB1,
        .mem_buses = PL08X_AHB1,
 };
diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c
index 5b660ec09ef5..0c002099c3a3 100644
--- a/arch/arm/mach-mmp/aspenite.c
+++ b/arch/arm/mach-mmp/aspenite.c
@@ -210,7 +210,7 @@ struct pxa168fb_mach_info aspenite_lcd_info = {
        .invert_pixclock        = 0,
 };
-static unsigned int aspenite_matrix_key_map[] = {
+static const unsigned int aspenite_matrix_key_map[] = {
        KEY(0, 6, KEY_UP),      /* SW 4 */
        KEY(0, 7, KEY_DOWN),    /* SW 5 */
        KEY(1, 6, KEY_LEFT),    /* SW 6 */
@@ -219,11 +219,15 @@ static unsigned int aspenite_matrix_key_map[] = {
        KEY(4, 7, KEY_ESC),     /* SW 9 */
 };
+static struct matrix_keymap_data aspenite_matrix_keymap_data = {
+        .keymap                 = aspenite_matrix_key_map,
+        .keymap_size            = ARRAY_SIZE(aspenite_matrix_key_map),
+};
 static struct pxa27x_keypad_platform_data aspenite_keypad_info __initdata = {
        .matrix_key_rows        = 5,
        .matrix_key_cols        = 8,
-        .matrix_key_map         = aspenite_matrix_key_map,
+        .matrix_keymap_data     = &aspenite_matrix_keymap_data,
-        .matrix_key_map_size    = ARRAY_SIZE(aspenite_matrix_key_map),
        .debounce_interval      = 30,
 };
diff --git a/arch/arm/mach-mmp/common.c b/arch/arm/mach-mmp/common.c
index 9292b7966e3b..c03b4ab582db 100644
--- a/arch/arm/mach-mmp/common.c
+++ b/arch/arm/mach-mmp/common.c
@@ -47,7 +47,7 @@ void __init mmp_map_io(void)
        mmp_chip_id = __raw_readl(MMP_CHIPID);
 }
-void mmp_restart(char mode, const char *cmd)
+void mmp_restart(enum reboot_mode mode, const char *cmd)
 {
        soft_restart(0);
 }
diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h
index 0bdc50b134ce..991d7e9877de 100644
--- a/arch/arm/mach-mmp/common.h
+++ b/arch/arm/mach-mmp/common.h
@@ -1,10 +1,11 @@
+#include <linux/reboot.h>
 #define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
 extern void timer_init(int irq);
 extern void __init icu_init_irq(void);
 extern void __init mmp_map_io(void);
-extern void mmp_restart(char, const char *);
+extern void mmp_restart(enum reboot_mode, const char *);
 extern void __init pxa168_clk_init(void);
 extern void __init pxa910_clk_init(void);
 extern void __init mmp2_clk_init(void);
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h
index 7ed1df21ea1c..459c2d03eb5c 100644
--- a/arch/arm/mach-mmp/include/mach/pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -1,9 +1,11 @@
 #ifndef __ASM_MACH_PXA168_H
 #define __ASM_MACH_PXA168_H
+#include <linux/reboot.h>
 extern void pxa168_timer_init(void);
 extern void __init pxa168_init_irq(void);
-extern void pxa168_restart(char, const char *);
+extern void pxa168_restart(enum reboot_mode, const char *);
 extern void pxa168_clear_keypad_wakeup(void);
 #include <linux/i2c.h>
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index a30dcf3b7d9e..144e997624c0 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -172,7 +172,7 @@ int __init pxa168_add_usb_host(struct mv_usb_platform_data *pdata)
        return platform_device_register(&pxa168_device_usb_host);
 }
-void pxa168_restart(char mode, const char *cmd)
+void pxa168_restart(enum reboot_mode mode, const char *cmd)
 {
        soft_restart(0xffff0000);
 }
diff --git a/arch/arm/mach-mmp/teton_bga.c b/arch/arm/mach-mmp/teton_bga.c
index e4d95b4c6bb2..6aa53fb29d26 100644
--- a/arch/arm/mach-mmp/teton_bga.c
+++ b/arch/arm/mach-mmp/teton_bga.c
@@ -61,11 +61,15 @@ static unsigned int teton_bga_matrix_key_map[] = {
        KEY(1, 7, KEY_RIGHT),
 };
+static struct matrix_keymap_data teton_bga_matrix_keymap_data = {
+        .keymap                 = teton_bga_matrix_key_map,
+        .keymap_size            = ARRAY_SIZE(teton_bga_matrix_key_map),
+};
 static struct pxa27x_keypad_platform_data teton_bga_keypad_info __initdata = {
        .matrix_key_rows        = 2,
        .matrix_key_cols        = 8,
-        .matrix_key_map         = teton_bga_matrix_key_map,
+        .matrix_keymap_data     = &teton_bga_matrix_keymap_data,
-        .matrix_key_map_size    = ARRAY_SIZE(teton_bga_matrix_key_map),
        .debounce_interval      = 30,
 };
diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c
index 86a18b3d252e..7ac41e83cfef 100644
--- a/arch/arm/mach-mmp/time.c
+++ b/arch/arm/mach-mmp/time.c
@@ -28,8 +28,8 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
+#include <linux/sched_clock.h>
-#include <asm/sched_clock.h>
 #include <mach/addr-map.h>
 #include <mach/regs-timers.h>
 #include <mach/regs-apbc.h>
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index fceb093b9494..905efc8cac79 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -48,9 +48,7 @@ config ARCH_MSM8X60
        select CPU_V7
        select GPIO_MSM_V2
        select HAVE_SMP
-        select MSM_GPIOMUX
        select MSM_SCM if SMP
-        select MSM_V2_TLMM
        select USE_OF
 config ARCH_MSM8960
@@ -58,9 +56,8 @@ config ARCH_MSM8960
        select ARM_GIC
        select CPU_V7
        select HAVE_SMP
-        select MSM_GPIOMUX
+        select GPIO_MSM_V2
        select MSM_SCM if SMP
-        select MSM_V2_TLMM
        select USE_OF
 config MSM_HAS_DEBUG_UART_HS
@@ -125,9 +122,8 @@ config MSM_SMD
 config MSM_GPIOMUX
        bool
+        help
-config MSM_V2_TLMM
+          Support for MSM V1 TLMM GPIOMUX architecture.
-        bool
 config MSM_SCM
        bool
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 17519faf082f..d257ff40e16b 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -1,16 +1,18 @@
 obj-y += io.o timer.o
 obj-y += clock.o
-obj-$(CONFIG_DEBUG_FS) += clock-debug.o
 obj-$(CONFIG_MSM_VIC) += irq-vic.o
 obj-$(CONFIG_MSM_IOMMU) += devices-iommu.o
-obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o
+obj-$(CONFIG_ARCH_MSM7X00A) += irq.o
-obj-$(CONFIG_ARCH_MSM7X30) += dma.o
+obj-$(CONFIG_ARCH_QSD8X50) += sirc.o
-obj-$(CONFIG_ARCH_QSD8X50) += dma.o sirc.o
 obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o
+obj-$(CONFIG_ARCH_MSM7X00A) += dma.o
+obj-$(CONFIG_ARCH_MSM7X30) += dma.o
+obj-$(CONFIG_ARCH_QSD8X50) += dma.o
 obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o
 obj-$(CONFIG_MSM_SMD) += last_radio_log.o
 obj-$(CONFIG_MSM_SCM) += scm.o scm-boot.o
@@ -27,7 +29,5 @@ obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
 obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
 obj-$(CONFIG_ARCH_MSM8X60) += board-dt-8660.o
 obj-$(CONFIG_ARCH_MSM8960) += board-dt-8960.o
+obj-$(CONFIG_MSM_GPIOMUX) += gpiomux.o
-obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-v1.o gpiomux.o
+obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o
-obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o
-obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o gpiomux-v2.o gpiomux.o
diff --git a/arch/arm/mach-msm/board-dt-8660.c b/arch/arm/mach-msm/board-dt-8660.c
index 7dcfc5300bbd..492f5cd87b0a 100644
--- a/arch/arm/mach-msm/board-dt-8660.c
+++ b/arch/arm/mach-msm/board-dt-8660.c
@@ -11,7 +11,6 @@
 */
 #include <linux/init.h>
-#include <linux/irqchip.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
@@ -44,7 +43,6 @@ static const char *msm8x60_fluid_match[] __initdata = {
 DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)")
        .smp = smp_ops(msm_smp_ops),
        .map_io = msm_map_msm8x60_io,
-        .init_irq = irqchip_init,
        .init_machine = msm8x60_dt_init,
        .init_late = msm8x60_init_late,
        .init_time      = msm_dt_timer_init,
diff --git a/arch/arm/mach-msm/board-dt-8960.c b/arch/arm/mach-msm/board-dt-8960.c
index 73019363ffa4..bb5530957c4f 100644
--- a/arch/arm/mach-msm/board-dt-8960.c
+++ b/arch/arm/mach-msm/board-dt-8960.c
@@ -11,7 +11,6 @@
 */
 #include <linux/init.h>
-#include <linux/irqchip.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
@@ -31,7 +30,6 @@ static const char * const msm8960_dt_match[] __initconst = {
 DT_MACHINE_START(MSM8960_DT, "Qualcomm MSM (Flattened Device Tree)")
        .smp = smp_ops(msm_smp_ops),
        .map_io = msm_map_msm8960_io,
-        .init_irq = irqchip_init,
        .init_time      = msm_dt_timer_init,
        .init_machine = msm_dt_init,
        .dt_compat = msm8960_dt_match,
diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c
index 82eaf88d2026..803651ad4f62 100644
--- a/arch/arm/mach-msm/board-halibut.c
+++ b/arch/arm/mach-msm/board-halibut.c
@@ -59,6 +59,7 @@ static struct platform_device smc91x_device = {
 };
 static struct platform_device *devices[] __initdata = {
+        &msm_clock_7x01a,
        &msm_device_gpio_7201,
        &msm_device_uart3,
        &msm_device_smd,
@@ -91,7 +92,6 @@ static void __init halibut_fixup(struct tag *tags, char **cmdline,
 static void __init halibut_map_io(void)
 {
        msm_map_common_io();
-        msm_clock_init(msm_clocks_7x01a, msm_num_clocks_7x01a);
 }
 static void __init halibut_init_late(void)
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index 520c141acd03..db3d8c0bc8a4 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -89,6 +89,7 @@ struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
 };
 static struct platform_device *devices[] __initdata = {
+        &msm_clock_7x30,
        &msm_device_gpio_7x30,
 #if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER)
        &msm_device_uart2,
@@ -116,7 +117,6 @@ static void __init msm7x30_init(void)
 static void __init msm7x30_map_io(void)
 {
        msm_map_msm7x30_io();
-        msm_clock_init(msm_clocks_7x30, msm_num_clocks_7x30);
 }
 static void __init msm7x30_init_late(void)
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c
index 38a532d6937c..f14a73d86bc0 100644
--- a/arch/arm/mach-msm/board-qsd8x50.c
+++ b/arch/arm/mach-msm/board-qsd8x50.c
@@ -89,6 +89,7 @@ static struct msm_otg_platform_data msm_otg_pdata = {
 };
 static struct platform_device *devices[] __initdata = {
+        &msm_clock_8x50,
        &msm_device_gpio_8x50,
        &msm_device_uart3,
        &msm_device_smd,
@@ -172,7 +173,6 @@ static void __init qsd8x50_init_mmc(void)
 static void __init qsd8x50_map_io(void)
 {
        msm_map_qsd8x50_io();
-        msm_clock_init(msm_clocks_8x50, msm_num_clocks_8x50);
 }
 static void __init qsd8x50_init_irq(void)
diff --git a/arch/arm/mach-msm/board-trout-panel.c b/arch/arm/mach-msm/board-trout-panel.c
index f9a5db6d2ced..77b0a26f897f 100644
--- a/arch/arm/mach-msm/board-trout-panel.c
+++ b/arch/arm/mach-msm/board-trout-panel.c
@@ -7,7 +7,6 @@
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/leds.h>
-#include <linux/clk.h>
 #include <linux/err.h>
 #include <asm/io.h>
@@ -19,6 +18,7 @@
 #include "board-trout.h"
 #include "proc_comm.h"
+#include "clock-pcom.h"
 #include "devices.h"
 #define TROUT_DEFAULT_BACKLIGHT_BRIGHTNESS 255
@@ -170,7 +170,6 @@ static struct mddi_table mddi_toshiba_init_table[] = {
 #define INTMASK_VWAKEOUT (1U << 0)
-static struct clk *gp_clk;
 static int trout_new_backlight = 1;
 static struct vreg *vreg_mddi_1v5;
 static struct vreg *vreg_lcm_2v85;
@@ -273,18 +272,14 @@ int __init trout_init_panel(void)
        } else {
                uint32_t config = PCOM_GPIO_CFG(27, 1, GPIO_OUTPUT,
                                                GPIO_NO_PULL, GPIO_8MA);
+                uint32_t id = P_GP_CLK;
+                uint32_t rate = 19200000;
                msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, 0);
-                gp_clk = clk_get(NULL, "gp_clk");
+                msm_proc_comm(PCOM_CLKCTL_RPC_SET_RATE, &id, &rate);
-                if (IS_ERR(gp_clk)) {
+                if (id < 0)
-                        printk(KERN_ERR "trout_init_panel: could not get gp"
+                        pr_err("trout_init_panel: set clock rate failed\n");
-                               "clock\n");
-                        gp_clk = NULL;
-                }
-                rc = clk_set_rate(gp_clk, 19200000);
-                if (rc)
-                        printk(KERN_ERR "trout_init_panel: set clock rate "
-                               "failed\n");
        }
        rc = platform_device_register(&msm_device_mdp);
diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c
index 80fe1c5ff5c1..64a46eb4fc49 100644
--- a/arch/arm/mach-msm/board-trout.c
+++ b/arch/arm/mach-msm/board-trout.c
@@ -36,6 +36,7 @@
 extern int trout_init_mmc(unsigned int);
 static struct platform_device *devices[] __initdata = {
+        &msm_clock_7x01a,
        &msm_device_gpio_7201,
        &msm_device_uart3,
        &msm_device_smd,
@@ -94,8 +95,6 @@ static void __init trout_map_io(void)
        /* route UART3 to the "H2W" extended usb connector */
        writeb(0x80, TROUT_CPLD_BASE + 0x00);
 #endif
-        msm_clock_init(msm_clocks_7x01a, msm_num_clocks_7x01a);
 }
 static void __init trout_init_late(void)
diff --git a/arch/arm/mach-msm/clock-7x30.h b/arch/arm/mach-msm/clock-7x30.h
deleted file mode 100644
index 14104453688b..000000000000
--- a/arch/arm/mach-msm/clock-7x30.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __ARCH_ARM_MACH_MSM_CLOCK_7X30_H
-#define __ARCH_ARM_MACH_MSM_CLOCK_7X30_H
-enum {
-        L_7X30_NONE_CLK = -1,
-        L_7X30_ADM_CLK,
-        L_7X30_I2C_CLK,
-        L_7X30_I2C_2_CLK,
-        L_7X30_QUP_I2C_CLK,
-        L_7X30_UART1DM_CLK,
-        L_7X30_UART1DM_P_CLK,
-        L_7X30_UART2DM_CLK,
-        L_7X30_UART2DM_P_CLK,
-        L_7X30_EMDH_CLK,
-        L_7X30_EMDH_P_CLK,
-        L_7X30_PMDH_CLK,
-        L_7X30_PMDH_P_CLK,
-        L_7X30_GRP_2D_CLK,
-        L_7X30_GRP_2D_P_CLK,
-        L_7X30_GRP_3D_SRC_CLK,
-        L_7X30_GRP_3D_CLK,
-        L_7X30_GRP_3D_P_CLK,
-        L_7X30_IMEM_CLK,
-        L_7X30_SDC1_CLK,
-        L_7X30_SDC1_P_CLK,
-        L_7X30_SDC2_CLK,
-        L_7X30_SDC2_P_CLK,
-        L_7X30_SDC3_CLK,
-        L_7X30_SDC3_P_CLK,
-        L_7X30_SDC4_CLK,
-        L_7X30_SDC4_P_CLK,
-        L_7X30_MDP_CLK,
-        L_7X30_MDP_P_CLK,
-        L_7X30_MDP_LCDC_PCLK_CLK,
-        L_7X30_MDP_LCDC_PAD_PCLK_CLK,
-        L_7X30_MDP_VSYNC_CLK,
-        L_7X30_MI2S_CODEC_RX_M_CLK,
-        L_7X30_MI2S_CODEC_RX_S_CLK,
-        L_7X30_MI2S_CODEC_TX_M_CLK,
-        L_7X30_MI2S_CODEC_TX_S_CLK,
-        L_7X30_MI2S_M_CLK,
-        L_7X30_MI2S_S_CLK,
-        L_7X30_LPA_CODEC_CLK,
-        L_7X30_LPA_CORE_CLK,
-        L_7X30_LPA_P_CLK,
-        L_7X30_MIDI_CLK,
-        L_7X30_MDC_CLK,
-        L_7X30_ROTATOR_IMEM_CLK,
-        L_7X30_ROTATOR_P_CLK,
-        L_7X30_SDAC_M_CLK,
-        L_7X30_SDAC_CLK,
-        L_7X30_UART1_CLK,
-        L_7X30_UART2_CLK,
-        L_7X30_UART3_CLK,
-        L_7X30_TV_CLK,
-        L_7X30_TV_DAC_CLK,
-        L_7X30_TV_ENC_CLK,
-        L_7X30_HDMI_CLK,
-        L_7X30_TSIF_REF_CLK,
-        L_7X30_TSIF_P_CLK,
-        L_7X30_USB_HS_SRC_CLK,
-        L_7X30_USB_HS_CLK,
-        L_7X30_USB_HS_CORE_CLK,
-        L_7X30_USB_HS_P_CLK,
-        L_7X30_USB_HS2_CLK,
-        L_7X30_USB_HS2_CORE_CLK,
-        L_7X30_USB_HS2_P_CLK,
-        L_7X30_USB_HS3_CLK,
-        L_7X30_USB_HS3_CORE_CLK,
-        L_7X30_USB_HS3_P_CLK,
-        L_7X30_VFE_CLK,
-        L_7X30_VFE_P_CLK,
-        L_7X30_VFE_MDC_CLK,
-        L_7X30_VFE_CAMIF_CLK,
-        L_7X30_CAMIF_PAD_P_CLK,
-        L_7X30_CAM_M_CLK,
-        L_7X30_JPEG_CLK,
-        L_7X30_JPEG_P_CLK,
-        L_7X30_VPE_CLK,
-        L_7X30_MFC_CLK,
-        L_7X30_MFC_DIV2_CLK,
-        L_7X30_MFC_P_CLK,
-        L_7X30_SPI_CLK,
-        L_7X30_SPI_P_CLK,
-        L_7X30_CSI0_CLK,
-        L_7X30_CSI0_VFE_CLK,
-        L_7X30_CSI0_P_CLK,
-        L_7X30_CSI1_CLK,
-        L_7X30_CSI1_VFE_CLK,
-        L_7X30_CSI1_P_CLK,
-        L_7X30_GLBL_ROOT_CLK,
-        L_7X30_AXI_LI_VG_CLK,
-        L_7X30_AXI_LI_GRP_CLK,
-        L_7X30_AXI_LI_JPEG_CLK,
-        L_7X30_AXI_GRP_2D_CLK,
-        L_7X30_AXI_MFC_CLK,
-        L_7X30_AXI_VPE_CLK,
-        L_7X30_AXI_LI_VFE_CLK,
-        L_7X30_AXI_LI_APPS_CLK,
-        L_7X30_AXI_MDP_CLK,
-        L_7X30_AXI_IMEM_CLK,
-        L_7X30_AXI_LI_ADSP_A_CLK,
-        L_7X30_AXI_ROTATOR_CLK,
-        L_7X30_NR_CLKS
-};
-struct clk_ops;
-extern struct clk_ops clk_ops_7x30;
-struct clk_ops *clk_7x30_is_local(uint32_t id);
-int clk_7x30_init(void);
-void pll_enable(uint32_t pll);
-void pll_disable(uint32_t pll);
-extern int internal_pwr_rail_ctl_auto(unsigned rail_id, bool enable);
-#define CLK_7X30(clk_name, clk_id, clk_dev, clk_flags) {        \
-        .con_id = clk_name, \
-        .dev_id = clk_dev, \
-        .clk = &(struct clk){ \
-                .id = L_7X30_##clk_id, \
-                .remote_id = P_##clk_id, \
-                .flags = clk_flags, \
-                .dbg_name = #clk_id, \
-        }, \
-        }
-#define CLK_7X30S(clk_name, l_id, r_id, clk_dev, clk_flags) {   \
-        .con_id = clk_name, \
-        .dev_id = clk_dev, \
-        .clk = &(struct clk){ \
-                .id = L_7X30_##l_id, \
-                .remote_id = P_##r_id, \
-                .flags = clk_flags, \
-                .dbg_name = #l_id, \
-                .ops = &clk_ops_pcom, \
-        }, \
-        }
-#endif
diff --git a/arch/arm/mach-msm/clock-debug.c b/arch/arm/mach-msm/clock-debug.c
deleted file mode 100644
index 4886404d42f5..000000000000
--- a/arch/arm/mach-msm/clock-debug.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2007-2010, Code Aurora Forum. All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/ctype.h>
-#include <linux/debugfs.h>
-#include <linux/clk.h>
-#include "clock.h"
-static int clock_debug_rate_set(void *data, u64 val)
-{
-        struct clk *clock = data;
-        int ret;
-        /* Only increases to max rate will succeed, but that's actually good
-         * for debugging purposes so we don't check for error. */
-        if (clock->flags & CLK_MAX)
-                clk_set_max_rate(clock, val);
-        if (clock->flags & CLK_MIN)
-                ret = clk_set_min_rate(clock, val);
-        else
-                ret = clk_set_rate(clock, val);
-        if (ret != 0)
-                printk(KERN_ERR "clk_set%s_rate failed (%d)\n",
-                        (clock->flags & CLK_MIN) ? "_min" : "", ret);
-        return ret;
-}
-static int clock_debug_rate_get(void *data, u64 *val)
-{
-        struct clk *clock = data;
-        *val = clk_get_rate(clock);
-        return 0;
-}
-DEFINE_SIMPLE_ATTRIBUTE(clock_rate_fops, clock_debug_rate_get,
-                        clock_debug_rate_set, "%llu\n");
-static int clock_debug_enable_set(void *data, u64 val)
-{
-        struct clk *clock = data;
-        int rc = 0;
-        if (val)
-                rc = clock->ops->enable(clock->id);
-        else
-                clock->ops->disable(clock->id);
-        return rc;
-}
-static int clock_debug_enable_get(void *data, u64 *val)
-{
-        struct clk *clock = data;
-        *val = clock->ops->is_enabled(clock->id);
-        return 0;
-}
-DEFINE_SIMPLE_ATTRIBUTE(clock_enable_fops, clock_debug_enable_get,
-                        clock_debug_enable_set, "%llu\n");
-static int clock_debug_local_get(void *data, u64 *val)
-{
-        struct clk *clock = data;
-        *val = clock->ops->is_local(clock->id);
-        return 0;
-}
-DEFINE_SIMPLE_ATTRIBUTE(clock_local_fops, clock_debug_local_get,
-                        NULL, "%llu\n");
-static struct dentry *debugfs_base;
-int __init clock_debug_init(void)
-{
-        debugfs_base = debugfs_create_dir("clk", NULL);
-        if (!debugfs_base)
-                return -ENOMEM;
-        return 0;
-}
-int __init clock_debug_add(struct clk *clock)
-{
-        char temp[50], *ptr;
-        struct dentry *clk_dir;
-        if (!debugfs_base)
-                return -ENOMEM;
-        strncpy(temp, clock->dbg_name, ARRAY_SIZE(temp)-1);
-        for (ptr = temp; *ptr; ptr++)
-                *ptr = tolower(*ptr);
-        clk_dir = debugfs_create_dir(temp, debugfs_base);
-        if (!clk_dir)
-                return -ENOMEM;
-        if (!debugfs_create_file("rate", S_IRUGO | S_IWUSR, clk_dir,
-                                clock, &clock_rate_fops))
-                goto error;
-        if (!debugfs_create_file("enable", S_IRUGO | S_IWUSR, clk_dir,
-                                clock, &clock_enable_fops))
-                goto error;
-        if (!debugfs_create_file("is_local", S_IRUGO, clk_dir, clock,
-                                &clock_local_fops))
-                goto error;
-        return 0;
-error:
-        debugfs_remove_recursive(clk_dir);
-        return -ENOMEM;
-}
diff --git a/arch/arm/mach-msm/clock-pcom.c b/arch/arm/mach-msm/clock-pcom.c
index a52c970df157..9a80449518e6 100644
--- a/arch/arm/mach-msm/clock-pcom.c
+++ b/arch/arm/mach-msm/clock-pcom.c
@@ -1,6 +1,6 @@
 /*
 * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2007-2010, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2007-2012, The Linux Foundation. All rights reserved.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
@@ -13,20 +13,33 @@
 *
 */
+#include <linux/kernel.h>
 #include <linux/err.h>
-#include <linux/ctype.h>
+#include <linux/platform_device.h>
-#include <linux/stddef.h>
+#include <linux/module.h>
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
 #include <mach/clk.h>
 #include "proc_comm.h"
 #include "clock.h"
 #include "clock-pcom.h"
-/*
+struct clk_pcom {
- * glue for the proc_comm interface
+        unsigned id;
- */
+        unsigned long flags;
-static int pc_clk_enable(unsigned id)
+        struct msm_clk msm_clk;
+};
+static inline struct clk_pcom *to_clk_pcom(struct clk_hw *hw)
 {
+        return container_of(to_msm_clk(hw), struct clk_pcom, msm_clk);
+}
+static int pc_clk_enable(struct clk_hw *hw)
+{
+        unsigned id = to_clk_pcom(hw)->id;
        int rc = msm_proc_comm(PCOM_CLKCTL_RPC_ENABLE, &id, NULL);
        if (rc < 0)
                return rc;
@@ -34,14 +47,16 @@ static int pc_clk_enable(unsigned id)
                return (int)id < 0 ? -EINVAL : 0;
 }
-static void pc_clk_disable(unsigned id)
+static void pc_clk_disable(struct clk_hw *hw)
 {
+        unsigned id = to_clk_pcom(hw)->id;
        msm_proc_comm(PCOM_CLKCTL_RPC_DISABLE, &id, NULL);
 }
-int pc_clk_reset(unsigned id, enum clk_reset_action action)
+static int pc_clk_reset(struct clk_hw *hw, enum clk_reset_action action)
 {
        int rc;
+        unsigned id = to_clk_pcom(hw)->id;
        if (action == CLK_RESET_ASSERT)
                rc = msm_proc_comm(PCOM_CLKCTL_RPC_RESET_ASSERT, &id, NULL);
@@ -54,85 +69,109 @@ int pc_clk_reset(unsigned id, enum clk_reset_action action)
                return (int)id < 0 ? -EINVAL : 0;
 }
-static int pc_clk_set_rate(unsigned id, unsigned rate)
+static int pc_clk_set_rate(struct clk_hw *hw, unsigned long new_rate,
+                           unsigned long p_rate)
 {
-        /* The rate _might_ be rounded off to the nearest KHz value by the
+        struct clk_pcom *p = to_clk_pcom(hw);
+        unsigned id = p->id, rate = new_rate;
+        int rc;
+        /*
+         * The rate _might_ be rounded off to the nearest KHz value by the
         * remote function. So a return value of 0 doesn't necessarily mean
         * that the exact rate was set successfully.
         */
-        int rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_RATE, &id, &rate);
+        if (p->flags & CLKFLAG_MIN)
-        if (rc < 0)
+                rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_RATE, &id, &rate);
-                return rc;
-        else
-                return (int)id < 0 ? -EINVAL : 0;
-}
-static int pc_clk_set_min_rate(unsigned id, unsigned rate)
-{
-        int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_RATE, &id, &rate);
-        if (rc < 0)
-                return rc;
-        else
-                return (int)id < 0 ? -EINVAL : 0;
-}
-static int pc_clk_set_max_rate(unsigned id, unsigned rate)
-{
-        int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MAX_RATE, &id, &rate);
-        if (rc < 0)
-                return rc;
        else
-                return (int)id < 0 ? -EINVAL : 0;
+                rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_RATE, &id, &rate);
-}
-static int pc_clk_set_flags(unsigned id, unsigned flags)
-{
-        int rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_FLAGS, &id, &flags);
        if (rc < 0)
                return rc;
        else
                return (int)id < 0 ? -EINVAL : 0;
 }
-static unsigned pc_clk_get_rate(unsigned id)
+static unsigned long pc_clk_recalc_rate(struct clk_hw *hw, unsigned long p_rate)
 {
+        unsigned id = to_clk_pcom(hw)->id;
        if (msm_proc_comm(PCOM_CLKCTL_RPC_RATE, &id, NULL))
                return 0;
        else
                return id;
 }
-static unsigned pc_clk_is_enabled(unsigned id)
+static int pc_clk_is_enabled(struct clk_hw *hw)
 {
+        unsigned id = to_clk_pcom(hw)->id;
        if (msm_proc_comm(PCOM_CLKCTL_RPC_ENABLED, &id, NULL))
                return 0;
        else
                return id;
 }
-static long pc_clk_round_rate(unsigned id, unsigned rate)
+static long pc_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+                              unsigned long *p_rate)
 {
        /* Not really supported; pc_clk_set_rate() does rounding on it's own. */
        return rate;
 }
-static bool pc_clk_is_local(unsigned id)
+static struct clk_ops clk_ops_pcom = {
-{
-        return false;
-}
-struct clk_ops clk_ops_pcom = {
        .enable = pc_clk_enable,
        .disable = pc_clk_disable,
-        .auto_off = pc_clk_disable,
-        .reset = pc_clk_reset,
        .set_rate = pc_clk_set_rate,
-        .set_min_rate = pc_clk_set_min_rate,
+        .recalc_rate = pc_clk_recalc_rate,
-        .set_max_rate = pc_clk_set_max_rate,
-        .set_flags = pc_clk_set_flags,
-        .get_rate = pc_clk_get_rate,
        .is_enabled = pc_clk_is_enabled,
        .round_rate = pc_clk_round_rate,
-        .is_local = pc_clk_is_local,
 };
+static int msm_clock_pcom_probe(struct platform_device *pdev)
+{
+        const struct pcom_clk_pdata *pdata = pdev->dev.platform_data;
+        int i, ret;
+        for (i = 0; i < pdata->num_lookups; i++) {
+                const struct clk_pcom_desc *desc = &pdata->lookup[i];
+                struct clk *c;
+                struct clk_pcom *p;
+                struct clk_hw *hw;
+                struct clk_init_data init;
+                p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
+                if (!p)
+                        return -ENOMEM;
+                p->id = desc->id;
+                p->flags = desc->flags;
+                p->msm_clk.reset = pc_clk_reset;
+                hw = &p->msm_clk.hw;
+                hw->init = &init;
+                init.name = desc->name;
+                init.ops = &clk_ops_pcom;
+                init.num_parents = 0;
+                init.flags = CLK_IS_ROOT;
+                if (!(p->flags & CLKFLAG_AUTO_OFF))
+                        init.flags |= CLK_IGNORE_UNUSED;
+                c = devm_clk_register(&pdev->dev, hw);
+                ret = clk_register_clkdev(c, desc->con, desc->dev);
+                if (ret)
+                        return ret;
+        }
+        return 0;
+}
+static struct platform_driver msm_clock_pcom_driver = {
+        .probe          = msm_clock_pcom_probe,
+        .driver         = {
+                .name   = "msm-clock-pcom",
+                .owner  = THIS_MODULE,
+        },
+};
+module_platform_driver(msm_clock_pcom_driver);
+MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-msm/clock-pcom.h b/arch/arm/mach-msm/clock-pcom.h
index 974d0032f3a3..5bb164fd46a8 100644
--- a/arch/arm/mach-msm/clock-pcom.h
+++ b/arch/arm/mach-msm/clock-pcom.h
@@ -1,4 +1,5 @@
-/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
+/*
+ * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
@@ -120,21 +121,25 @@
 #define P_NR_CLKS               102
-struct clk_ops;
+struct clk_pcom_desc {
-extern struct clk_ops clk_ops_pcom;
+        unsigned id;
+        const char *name;
+        const char *con;
+        const char *dev;
+        unsigned long flags;
+};
-int pc_clk_reset(unsigned id, enum clk_reset_action action);
+struct pcom_clk_pdata {
+        struct clk_pcom_desc *lookup;
+        u32 num_lookups;
+};
 #define CLK_PCOM(clk_name, clk_id, clk_dev, clk_flags) {        \
-        .con_id = clk_name, \
+        .id = P_##clk_id,                                       \
-        .dev_id = clk_dev, \
+        .name = #clk_id,                                        \
-        .clk = &(struct clk){ \
+        .con = clk_name,                                        \
-                .id = P_##clk_id, \
+        .dev = clk_dev,                                         \
-                .remote_id = P_##clk_id, \
+        .flags = clk_flags,                                     \
-                .ops = &clk_ops_pcom, \
-                .flags = clk_flags, \
-                .dbg_name = #clk_id, \
-        }, \
        }
 #endif
diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c
index d9145dfc2a3b..35ea02b52483 100644
--- a/arch/arm/mach-msm/clock.c
+++ b/arch/arm/mach-msm/clock.c
@@ -1,7 +1,7 @@
 /* arch/arm/mach-msm/clock.c
 *
 * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2007-2010, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2007-2012, The Linux Foundation. All rights reserved.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
@@ -14,171 +14,15 @@
 *
 */
-#include <linux/kernel.h>
+#include <linux/clk-provider.h>
-#include <linux/list.h>
-#include <linux/err.h>
-#include <linux/spinlock.h>
-#include <linux/pm_qos.h>
-#include <linux/mutex.h>
-#include <linux/clk.h>
-#include <linux/string.h>
 #include <linux/module.h>
-#include <linux/clkdev.h>
 #include "clock.h"
-static DEFINE_MUTEX(clocks_mutex);
-static DEFINE_SPINLOCK(clocks_lock);
-static LIST_HEAD(clocks);
-/*
- * Standard clock functions defined in include/linux/clk.h
- */
-int clk_enable(struct clk *clk)
-{
-        unsigned long flags;
-        spin_lock_irqsave(&clocks_lock, flags);
-        clk->count++;
-        if (clk->count == 1)
-                clk->ops->enable(clk->id);
-        spin_unlock_irqrestore(&clocks_lock, flags);
-        return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-void clk_disable(struct clk *clk)
-{
-        unsigned long flags;
-        spin_lock_irqsave(&clocks_lock, flags);
-        BUG_ON(clk->count == 0);
-        clk->count--;
-        if (clk->count == 0)
-                clk->ops->disable(clk->id);
-        spin_unlock_irqrestore(&clocks_lock, flags);
-}
-EXPORT_SYMBOL(clk_disable);
 int clk_reset(struct clk *clk, enum clk_reset_action action)
 {
-        return clk->ops->reset(clk->remote_id, action);
+        struct clk_hw *hw = __clk_get_hw(clk);
+        struct msm_clk *m = to_msm_clk(hw);
+        return m->reset(hw, action);
 }
 EXPORT_SYMBOL(clk_reset);
-unsigned long clk_get_rate(struct clk *clk)
-{
-        return clk->ops->get_rate(clk->id);
-}
-EXPORT_SYMBOL(clk_get_rate);
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-        int ret;
-        if (clk->flags & CLKFLAG_MAX) {
-                ret = clk->ops->set_max_rate(clk->id, rate);
-                if (ret)
-                        return ret;
-        }
-        if (clk->flags & CLKFLAG_MIN) {
-                ret = clk->ops->set_min_rate(clk->id, rate);
-                if (ret)
-                        return ret;
-        }
-        if (clk->flags & CLKFLAG_MAX || clk->flags & CLKFLAG_MIN)
-                return ret;
-        return clk->ops->set_rate(clk->id, rate);
-}
-EXPORT_SYMBOL(clk_set_rate);
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
-        return clk->ops->round_rate(clk->id, rate);
-}
-EXPORT_SYMBOL(clk_round_rate);
-int clk_set_min_rate(struct clk *clk, unsigned long rate)
-{
-        return clk->ops->set_min_rate(clk->id, rate);
-}
-EXPORT_SYMBOL(clk_set_min_rate);
-int clk_set_max_rate(struct clk *clk, unsigned long rate)
-{
-        return clk->ops->set_max_rate(clk->id, rate);
-}
-EXPORT_SYMBOL(clk_set_max_rate);
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
-        return -ENOSYS;
-}
-EXPORT_SYMBOL(clk_set_parent);
-struct clk *clk_get_parent(struct clk *clk)
-{
-        return ERR_PTR(-ENOSYS);
-}
-EXPORT_SYMBOL(clk_get_parent);
-int clk_set_flags(struct clk *clk, unsigned long flags)
-{
-        if (clk == NULL || IS_ERR(clk))
-                return -EINVAL;
-        return clk->ops->set_flags(clk->id, flags);
-}
-EXPORT_SYMBOL(clk_set_flags);
-/* EBI1 is the only shared clock that several clients want to vote on as of
- * this commit. If this changes in the future, then it might be better to
- * make clk_min_rate handle the voting or make ebi1_clk_set_min_rate more
- * generic to support different clocks.
- */
-static struct clk *ebi1_clk;
-void __init msm_clock_init(struct clk_lookup *clock_tbl, unsigned num_clocks)
-{
-        unsigned n;
-        mutex_lock(&clocks_mutex);
-        for (n = 0; n < num_clocks; n++) {
-                clkdev_add(&clock_tbl[n]);
-                list_add_tail(&clock_tbl[n].clk->list, &clocks);
-        }
-        mutex_unlock(&clocks_mutex);
-        ebi1_clk = clk_get(NULL, "ebi1_clk");
-        BUG_ON(ebi1_clk == NULL);
-}
-/* The bootloader and/or AMSS may have left various clocks enabled.
- * Disable any clocks that belong to us (CLKFLAG_AUTO_OFF) but have
- * not been explicitly enabled by a clk_enable() call.
- */
-static int __init clock_late_init(void)
-{
-        unsigned long flags;
-        struct clk *clk;
-        unsigned count = 0;
-        clock_debug_init();
-        mutex_lock(&clocks_mutex);
-        list_for_each_entry(clk, &clocks, list) {
-                clock_debug_add(clk);
-                if (clk->flags & CLKFLAG_AUTO_OFF) {
-                        spin_lock_irqsave(&clocks_lock, flags);
-                        if (!clk->count) {
-                                count++;
-                                clk->ops->auto_off(clk->id);
-                        }
-                        spin_unlock_irqrestore(&clocks_lock, flags);
-                }
-        }
-        mutex_unlock(&clocks_mutex);
-        pr_info("clock_late_init() disabled %d unused clocks\n", count);
-        return 0;
-}
-late_initcall(clock_late_init);
diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h
index 2c007f606d29..42d29dd7aafc 100644
--- a/arch/arm/mach-msm/clock.h
+++ b/arch/arm/mach-msm/clock.h
@@ -1,7 +1,7 @@
 /* arch/arm/mach-msm/clock.h
 *
 * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2007-2010, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2007-2012, The Linux Foundation. All rights reserved.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
@@ -17,56 +17,27 @@
 #ifndef __ARCH_ARM_MACH_MSM_CLOCK_H
 #define __ARCH_ARM_MACH_MSM_CLOCK_H
-#include <linux/init.h>
+#include <linux/clk-provider.h>
-#include <linux/list.h>
 #include <mach/clk.h>
-#define CLKFLAG_INVERT                  0x00000001
-#define CLKFLAG_NOINVERT                0x00000002
-#define CLKFLAG_NONEST                  0x00000004
-#define CLKFLAG_NORESET                 0x00000008
 #define CLK_FIRST_AVAILABLE_FLAG        0x00000100
 #define CLKFLAG_AUTO_OFF                0x00000200
 #define CLKFLAG_MIN                     0x00000400
 #define CLKFLAG_MAX                     0x00000800
-struct clk_ops {
-        int (*enable)(unsigned id);
-        void (*disable)(unsigned id);
-        void (*auto_off)(unsigned id);
-        int (*reset)(unsigned id, enum clk_reset_action action);
-        int (*set_rate)(unsigned id, unsigned rate);
-        int (*set_min_rate)(unsigned id, unsigned rate);
-        int (*set_max_rate)(unsigned id, unsigned rate);
-        int (*set_flags)(unsigned id, unsigned flags);
-        unsigned (*get_rate)(unsigned id);
-        unsigned (*is_enabled)(unsigned id);
-        long (*round_rate)(unsigned id, unsigned rate);
-        bool (*is_local)(unsigned id);
-};
-struct clk {
-        uint32_t id;
-        uint32_t remote_id;
-        uint32_t count;
-        uint32_t flags;
-        struct clk_ops *ops;
-        const char *dbg_name;
-        struct list_head list;
-};
 #define OFF CLKFLAG_AUTO_OFF
 #define CLK_MIN CLKFLAG_MIN
 #define CLK_MAX CLKFLAG_MAX
 #define CLK_MINMAX (CLK_MIN | CLK_MAX)
-#ifdef CONFIG_DEBUG_FS
+struct msm_clk {
-int __init clock_debug_init(void);
+        int (*reset)(struct clk_hw *hw, enum clk_reset_action action);
-int __init clock_debug_add(struct clk *clock);
+        struct clk_hw hw;
-#else
+};
-static inline int __init clock_debug_init(void) { return 0; }
-static inline int __init clock_debug_add(struct clk *clock) { return 0; }
+static inline struct msm_clk *to_msm_clk(struct clk_hw *hw)
-#endif
+{
+        return container_of(hw, struct msm_clk, hw);
+}
 #endif
diff --git a/arch/arm/mach-msm/common.h b/arch/arm/mach-msm/common.h
index ce8215a269e5..421cf7751a80 100644
--- a/arch/arm/mach-msm/common.h
+++ b/arch/arm/mach-msm/common.h
@@ -23,7 +23,7 @@ extern void msm_map_msm8x60_io(void);
 extern void msm_map_msm8960_io(void);
 extern void msm_map_qsd8x50_io(void);
-extern void __iomem *__msm_ioremap_caller(unsigned long phys_addr, size_t size,
+extern void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
                                          unsigned int mtype, void *caller);
 extern struct smp_operations msm_smp_ops;
diff --git a/arch/arm/mach-msm/core.h b/arch/arm/mach-msm/core.h
deleted file mode 100644
index a9bab53dddf4..000000000000
--- a/arch/arm/mach-msm/core.h
+++ /dev/null
@@ -1,2 +0,0 @@
-extern struct smp_operations msm_smp_ops;
-extern void msm_cpu_die(unsigned int cpu);
diff --git a/arch/arm/mach-msm/devices-msm7x00.c b/arch/arm/mach-msm/devices-msm7x00.c
index 1a0a2306b115..6d50fb964863 100644
--- a/arch/arm/mach-msm/devices-msm7x00.c
+++ b/arch/arm/mach-msm/devices-msm7x00.c
@@ -425,7 +425,7 @@ struct platform_device msm_device_mdp = {
        .resource = resources_mdp,
 };
-struct clk_lookup msm_clocks_7x01a[] = {
+static struct clk_pcom_desc msm_clocks_7x01a[] = {
        CLK_PCOM("adm_clk",     ADM_CLK,        NULL, 0),
        CLK_PCOM("adsp_clk",    ADSP_CLK,       NULL, 0),
        CLK_PCOM("ebi1_clk",    EBI1_CLK,       NULL, 0),
@@ -469,4 +469,12 @@ struct clk_lookup msm_clocks_7x01a[] = {
        CLK_PCOM("vfe_mdc_clk", VFE_MDC_CLK,    NULL, OFF),
 };
-unsigned msm_num_clocks_7x01a = ARRAY_SIZE(msm_clocks_7x01a);
+static struct pcom_clk_pdata msm_clock_7x01a_pdata = {
+        .lookup = msm_clocks_7x01a,
+        .num_lookups = ARRAY_SIZE(msm_clocks_7x01a),
+};
+struct platform_device msm_clock_7x01a = {
+        .name = "msm-clock-pcom",
+        .dev.platform_data = &msm_clock_7x01a_pdata,
+};
diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c
index 12f482c07740..d4db75acff56 100644
--- a/arch/arm/mach-msm/devices-msm7x30.c
+++ b/arch/arm/mach-msm/devices-msm7x30.c
@@ -28,8 +28,8 @@
 #include <asm/mach/flash.h>
+#include "clock.h"
 #include "clock-pcom.h"
-#include "clock-7x30.h"
 #include <linux/platform_data/mmc-msm_sdcc.h>
@@ -161,7 +161,7 @@ struct platform_device msm_device_hsusb_host = {
        },
 };
-struct clk_lookup msm_clocks_7x30[] = {
+static struct clk_pcom_desc msm_clocks_7x30[] = {
        CLK_PCOM("adm_clk",     ADM_CLK,        NULL, 0),
        CLK_PCOM("adsp_clk",    ADSP_CLK,       NULL, 0),
        CLK_PCOM("cam_m_clk",   CAM_M_CLK,      NULL, 0),
@@ -177,7 +177,6 @@ struct clk_lookup msm_clocks_7x30[] = {
        CLK_PCOM("grp_2d_pclk", GRP_2D_P_CLK,   NULL, 0),
        CLK_PCOM("grp_clk",     GRP_3D_CLK,     NULL, 0),
        CLK_PCOM("grp_pclk",    GRP_3D_P_CLK,   NULL, 0),
-        CLK_7X30S("grp_src_clk", GRP_3D_SRC_CLK, GRP_3D_CLK,    NULL, 0),
        CLK_PCOM("hdmi_clk",    HDMI_CLK,       NULL, 0),
        CLK_PCOM("imem_clk",    IMEM_CLK,       NULL, OFF),
        CLK_PCOM("jpeg_clk",    JPEG_CLK,       NULL, OFF),
@@ -210,7 +209,6 @@ struct clk_lookup msm_clocks_7x30[] = {
        CLK_PCOM("sdac_clk",    SDAC_CLK,       NULL, OFF),
        CLK_PCOM("spi_clk",     SPI_CLK,        NULL, 0),
        CLK_PCOM("spi_pclk",    SPI_P_CLK,      NULL, 0),
-        CLK_7X30S("tv_src_clk", TV_CLK,         TV_ENC_CLK,     NULL, 0),
        CLK_PCOM("tv_dac_clk",  TV_DAC_CLK,     NULL, 0),
        CLK_PCOM("tv_enc_clk",  TV_ENC_CLK,     NULL, 0),
        CLK_PCOM("uart_clk",    UART2_CLK,      "msm_serial.1", 0),
@@ -237,5 +235,12 @@ struct clk_lookup msm_clocks_7x30[] = {
        CLK_PCOM("csi_vfe_clk", CSI0_VFE_CLK,   NULL, 0),
 };
-unsigned msm_num_clocks_7x30 = ARRAY_SIZE(msm_clocks_7x30);
+static struct pcom_clk_pdata msm_clock_7x30_pdata = {
+        .lookup = msm_clocks_7x30,
+        .num_lookups = ARRAY_SIZE(msm_clocks_7x30),
+};
+struct platform_device msm_clock_7x30 = {
+        .name = "msm-clock-pcom",
+        .dev.platform_data = &msm_clock_7x30_pdata,
+};
diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c
index 2e1b3ec9dfc7..f5518112284b 100644
--- a/arch/arm/mach-msm/devices-qsd8x50.c
+++ b/arch/arm/mach-msm/devices-qsd8x50.c
@@ -28,6 +28,7 @@
 #include <asm/mach/flash.h>
 #include <linux/platform_data/mmc-msm_sdcc.h>
+#include "clock.h"
 #include "clock-pcom.h"
 static struct resource msm_gpio_resources[] = {
@@ -322,7 +323,7 @@ int __init msm_add_sdcc(unsigned int controller,
        return platform_device_register(pdev);
 }
-struct clk_lookup msm_clocks_8x50[] = {
+static struct clk_pcom_desc msm_clocks_8x50[] = {
        CLK_PCOM("adm_clk",     ADM_CLK,        NULL, 0),
        CLK_PCOM("ce_clk",      CE_CLK,         NULL, 0),
        CLK_PCOM("ebi1_clk",    EBI1_CLK,       NULL, CLK_MIN),
@@ -376,5 +377,12 @@ struct clk_lookup msm_clocks_8x50[] = {
        CLK_PCOM("usb_phy_clk", USB_PHY_CLK,    NULL, 0),
 };
-unsigned msm_num_clocks_8x50 = ARRAY_SIZE(msm_clocks_8x50);
+static struct pcom_clk_pdata msm_clock_8x50_pdata = {
+        .lookup = msm_clocks_8x50,
+        .num_lookups = ARRAY_SIZE(msm_clocks_8x50),
+};
+struct platform_device msm_clock_8x50 = {
+        .name = "msm-clock-pcom",
+        .dev.platform_data = &msm_clock_8x50_pdata,
+};
diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h
index da902cf51161..dccefad9f9b9 100644
--- a/arch/arm/mach-msm/devices.h
+++ b/arch/arm/mach-msm/devices.h
@@ -16,10 +16,6 @@
 #ifndef __ARCH_ARM_MACH_MSM_DEVICES_H
 #define __ARCH_ARM_MACH_MSM_DEVICES_H
-#include <linux/clkdev.h>
-#include "clock.h"
 extern struct platform_device msm_device_gpio_7201;
 extern struct platform_device msm_device_gpio_7x30;
 extern struct platform_device msm_device_gpio_8x50;
@@ -50,13 +46,8 @@ extern struct platform_device msm_device_mddi0;
 extern struct platform_device msm_device_mddi1;
 extern struct platform_device msm_device_mdp;
-extern struct clk_lookup msm_clocks_7x01a[];
+extern struct platform_device msm_clock_7x01a;
-extern unsigned msm_num_clocks_7x01a;
+extern struct platform_device msm_clock_7x30;
+extern struct platform_device msm_clock_8x50;
-extern struct clk_lookup msm_clocks_7x30[];
-extern unsigned msm_num_clocks_7x30;
-extern struct clk_lookup msm_clocks_8x50[];
-extern unsigned msm_num_clocks_8x50;
 #endif
diff --git a/arch/arm/mach-msm/dma.c b/arch/arm/mach-msm/dma.c
index b279fd8a31b1..f8f6adfa07c6 100644
--- a/arch/arm/mach-msm/dma.c
+++ b/arch/arm/mach-msm/dma.c
@@ -284,6 +284,7 @@ static int __init msm_init_datamover(void)
        clk = clk_get(NULL, "adm_clk");
        if (IS_ERR(clk))
                return PTR_ERR(clk);
+        clk_prepare(clk);
        msm_dmov_clk = clk;
        ret = request_irq(INT_ADM_AARM, msm_datamover_irq_handler, 0, "msmdatamover", NULL);
        if (ret)
@@ -291,6 +292,4 @@ static int __init msm_init_datamover(void)
        disable_irq(INT_ADM_AARM);
        return 0;
 }
+module_init(msm_init_datamover);
-arch_initcall(msm_init_datamover);
diff --git a/arch/arm/mach-msm/gpiomux-8x60.c b/arch/arm/mach-msm/gpiomux-8x60.c
deleted file mode 100644
index 7b380b31bd0e..000000000000
--- a/arch/arm/mach-msm/gpiomux-8x60.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- */
-#include "gpiomux.h"
-struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {};
diff --git a/arch/arm/mach-msm/gpiomux-v1.c b/arch/arm/mach-msm/gpiomux-v1.c
deleted file mode 100644
index 27de2abd7144..000000000000
--- a/arch/arm/mach-msm/gpiomux-v1.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- */
-#include <linux/kernel.h>
-#include "gpiomux.h"
-#include "proc_comm.h"
-void __msm_gpiomux_write(unsigned gpio, gpiomux_config_t val)
-{
-        unsigned tlmm_config  = (val & ~GPIOMUX_CTL_MASK) |
-                                ((gpio & 0x3ff) << 4);
-        unsigned tlmm_disable = 0;
-        int rc;
-        rc = msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX,
-                           &tlmm_config, &tlmm_disable);
-        if (rc)
-                pr_err("%s: unexpected proc_comm failure %d: %08x %08x\n",
-                       __func__, rc, tlmm_config, tlmm_disable);
-}
diff --git a/arch/arm/mach-msm/gpiomux-v2.c b/arch/arm/mach-msm/gpiomux-v2.c
deleted file mode 100644
index 273396d2b127..000000000000
--- a/arch/arm/mach-msm/gpiomux-v2.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- */
-#include <linux/io.h>
-#include <mach/msm_iomap.h>
-#include "gpiomux.h"
-void __msm_gpiomux_write(unsigned gpio, gpiomux_config_t val)
-{
-        writel(val & ~GPIOMUX_CTL_MASK,
-               MSM_TLMM_BASE + 0x1000 + (0x10 * gpio));
-}
diff --git a/arch/arm/mach-msm/gpiomux-v2.h b/arch/arm/mach-msm/gpiomux-v2.h
deleted file mode 100644
index 3bf10e7f0381..000000000000
--- a/arch/arm/mach-msm/gpiomux-v2.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- */
-#ifndef __ARCH_ARM_MACH_MSM_GPIOMUX_V2_H
-#define __ARCH_ARM_MACH_MSM_GPIOMUX_V2_H
-#define GPIOMUX_NGPIOS 173
-typedef u16 gpiomux_config_t;
-enum {
-        GPIOMUX_DRV_2MA  = 0UL << 6,
-        GPIOMUX_DRV_4MA  = 1UL << 6,
-        GPIOMUX_DRV_6MA  = 2UL << 6,
-        GPIOMUX_DRV_8MA  = 3UL << 6,
-        GPIOMUX_DRV_10MA = 4UL << 6,
-        GPIOMUX_DRV_12MA = 5UL << 6,
-        GPIOMUX_DRV_14MA = 6UL << 6,
-        GPIOMUX_DRV_16MA = 7UL << 6,
-};
-enum {
-        GPIOMUX_FUNC_GPIO = 0UL  << 2,
-        GPIOMUX_FUNC_1    = 1UL  << 2,
-        GPIOMUX_FUNC_2    = 2UL  << 2,
-        GPIOMUX_FUNC_3    = 3UL  << 2,
-        GPIOMUX_FUNC_4    = 4UL  << 2,
-        GPIOMUX_FUNC_5    = 5UL  << 2,
-        GPIOMUX_FUNC_6    = 6UL  << 2,
-        GPIOMUX_FUNC_7    = 7UL  << 2,
-        GPIOMUX_FUNC_8    = 8UL  << 2,
-        GPIOMUX_FUNC_9    = 9UL  << 2,
-        GPIOMUX_FUNC_A    = 10UL << 2,
-        GPIOMUX_FUNC_B    = 11UL << 2,
-        GPIOMUX_FUNC_C    = 12UL << 2,
-        GPIOMUX_FUNC_D    = 13UL << 2,
-        GPIOMUX_FUNC_E    = 14UL << 2,
-        GPIOMUX_FUNC_F    = 15UL << 2,
-};
-enum {
-        GPIOMUX_PULL_NONE   = 0UL,
-        GPIOMUX_PULL_DOWN   = 1UL,
-        GPIOMUX_PULL_KEEPER = 2UL,
-        GPIOMUX_PULL_UP     = 3UL,
-};
-#endif
diff --git a/arch/arm/mach-msm/gpiomux.c b/arch/arm/mach-msm/gpiomux.c
index 53af21abd155..2b8e2d217082 100644
--- a/arch/arm/mach-msm/gpiomux.c
+++ b/arch/arm/mach-msm/gpiomux.c
@@ -17,9 +17,24 @@
 #include <linux/module.h>
 #include <linux/spinlock.h>
 #include "gpiomux.h"
+#include "proc_comm.h"
 static DEFINE_SPINLOCK(gpiomux_lock);
+static void __msm_gpiomux_write(unsigned gpio, gpiomux_config_t val)
+{
+        unsigned tlmm_config  = (val & ~GPIOMUX_CTL_MASK) |
+                                ((gpio & 0x3ff) << 4);
+        unsigned tlmm_disable = 0;
+        int rc;
+        rc = msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX,
+                           &tlmm_config, &tlmm_disable);
+        if (rc)
+                pr_err("%s: unexpected proc_comm failure %d: %08x %08x\n",
+                       __func__, rc, tlmm_config, tlmm_disable);
+}
 int msm_gpiomux_write(unsigned gpio,
                      gpiomux_config_t active,
                      gpiomux_config_t suspended)
diff --git a/arch/arm/mach-msm/gpiomux.h b/arch/arm/mach-msm/gpiomux.h
index 00459f6ee13c..4410d7766f93 100644
--- a/arch/arm/mach-msm/gpiomux.h
+++ b/arch/arm/mach-msm/gpiomux.h
@@ -20,12 +20,7 @@
 #include <linux/bitops.h>
 #include <linux/errno.h>
 #include <mach/msm_gpiomux.h>
-#if defined(CONFIG_MSM_V2_TLMM)
-#include "gpiomux-v2.h"
-#else
 #include "gpiomux-v1.h"
-#endif
 /**
 * struct msm_gpiomux_config: gpiomux settings for one gpio line.
@@ -78,16 +73,6 @@ extern struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS];
 int msm_gpiomux_write(unsigned gpio,
                      gpiomux_config_t active,
                      gpiomux_config_t suspended);
-/* Architecture-internal function for use by the framework only.
- * This function can assume the following:
- * - the gpio value has passed a bounds-check
- * - the gpiomux spinlock has been obtained
- *
- * This function is not for public consumption.  External users
- * should use msm_gpiomux_write.
- */
-void __msm_gpiomux_write(unsigned gpio, gpiomux_config_t val);
 #else
 static inline int msm_gpiomux_write(unsigned gpio,
                                    gpiomux_config_t active,
diff --git a/arch/arm/mach-msm/headsmp.S b/arch/arm/mach-msm/headsmp.S
index bcd5af223dea..6c62c3f82fe6 100644
--- a/arch/arm/mach-msm/headsmp.S
+++ b/arch/arm/mach-msm/headsmp.S
@@ -11,8 +11,6 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
-        __CPUINIT
 /*
 * MSM specific entry point for secondary CPUs.  This provides
 * a "holding pen" into which all secondary cores are held until we're
diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h
index 8cebedb11233..c34e246a3e07 100644
--- a/arch/arm/mach-msm/include/mach/board.h
+++ b/arch/arm/mach-msm/include/mach/board.h
@@ -20,16 +20,11 @@
 #include <linux/types.h>
 #include <linux/platform_data/mmc-msm_sdcc.h>
-/* platform device data structures */
-struct clk_lookup;
 /* common init routines for use by arch/arm/mach-msm/board-*.c */
 void __init msm_add_devices(void);
 void __init msm_init_irq(void);
 void __init msm_init_gpio(void);
-void __init msm_clock_init(struct clk_lookup *clock_tbl, unsigned num_clocks);
 int __init msm_add_sdcc(unsigned int controller,
                        struct msm_mmc_platform_data *plat,
                        unsigned int stat_irq, unsigned long stat_irq_flags);
diff --git a/arch/arm/mach-msm/include/mach/clk.h b/arch/arm/mach-msm/include/mach/clk.h
index e8d38428d813..fd4f4a7a83b3 100644
--- a/arch/arm/mach-msm/include/mach/clk.h
+++ b/arch/arm/mach-msm/include/mach/clk.h
@@ -25,16 +25,7 @@ enum clk_reset_action {
 struct clk;
-/* Rate is minimum clock rate in Hz */
-int clk_set_min_rate(struct clk *clk, unsigned long rate);
-/* Rate is maximum clock rate in Hz */
-int clk_set_max_rate(struct clk *clk, unsigned long rate);
 /* Assert/Deassert reset to a hardware block associated with a clock */
 int clk_reset(struct clk *clk, enum clk_reset_action action);
-/* Set clock-specific configuration parameters */
-int clk_set_flags(struct clk *clk, unsigned long flags);
 #endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
index 9819a556acae..7bca8d7108d6 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
@@ -32,13 +32,6 @@
 *
 */
-#define MSM8960_QGIC_DIST_PHYS  0x02000000
-#define MSM8960_QGIC_DIST_SIZE  SZ_4K
-#define MSM8960_QGIC_CPU_PHYS   0x02002000
-#define MSM8960_QGIC_CPU_SIZE   SZ_4K
 #define MSM8960_TMR_PHYS        0x0200A000
 #define MSM8960_TMR_SIZE        SZ_4K
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
index 199372e62def..75a7b62c1c74 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
@@ -35,12 +35,6 @@
 *
 */
-#define MSM8X60_QGIC_DIST_PHYS  0x02080000
-#define MSM8X60_QGIC_DIST_SIZE  SZ_4K
-#define MSM8X60_QGIC_CPU_PHYS   0x02081000
-#define MSM8X60_QGIC_CPU_SIZE   SZ_4K
 #define MSM_TLMM_BASE           IOMEM(0xF0004000)
 #define MSM_TLMM_PHYS           0x00800000
 #define MSM_TLMM_SIZE           SZ_16K
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
index 2ab7cf0919b3..c56e81ffdcde 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
@@ -62,8 +62,6 @@
 /* Virtual addresses shared across all MSM targets. */
 #define MSM_CSR_BASE            IOMEM(0xE0001000)
-#define MSM_QGIC_DIST_BASE      IOMEM(0xF0000000)
-#define MSM_QGIC_CPU_BASE       IOMEM(0xF0001000)
 #define MSM_TMR_BASE            IOMEM(0xF0200000)
 #define MSM_TMR0_BASE           IOMEM(0xF0201000)
 #define MSM_GPIO1_BASE          IOMEM(0xE0003000)
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 123ef9cbce1b..3dc04ccaf59f 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -107,8 +107,6 @@ void __init msm_map_qsd8x50_io(void)
 #ifdef CONFIG_ARCH_MSM8X60
 static struct map_desc msm8x60_io_desc[] __initdata = {
-        MSM_CHIP_DEVICE(QGIC_DIST, MSM8X60),
-        MSM_CHIP_DEVICE(QGIC_CPU, MSM8X60),
        MSM_CHIP_DEVICE(TMR, MSM8X60),
        MSM_CHIP_DEVICE(TMR0, MSM8X60),
 #ifdef CONFIG_DEBUG_MSM8660_UART
@@ -124,8 +122,6 @@ void __init msm_map_msm8x60_io(void)
 #ifdef CONFIG_ARCH_MSM8960
 static struct map_desc msm8960_io_desc[] __initdata = {
-        MSM_CHIP_DEVICE(QGIC_DIST, MSM8960),
-        MSM_CHIP_DEVICE(QGIC_CPU, MSM8960),
        MSM_CHIP_DEVICE(TMR, MSM8960),
        MSM_CHIP_DEVICE(TMR0, MSM8960),
 #ifdef CONFIG_DEBUG_MSM8960_UART
@@ -172,7 +168,7 @@ void __init msm_map_msm7x30_io(void)
 }
 #endif /* CONFIG_ARCH_MSM7X30 */
-void __iomem *__msm_ioremap_caller(unsigned long phys_addr, size_t size,
+void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
                                   unsigned int mtype, void *caller)
 {
        if (mtype == MT_DEVICE) {
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index 00cdb0a5dac8..3f06edcdd0ce 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -38,7 +38,7 @@ static inline int get_core_count(void)
        return ((read_cpuid_id() >> 4) & 3) + 1;
 }
-static void __cpuinit msm_secondary_init(unsigned int cpu)
+static void msm_secondary_init(unsigned int cpu)
 {
        /*
         * let the primary processor know we're out of the
@@ -54,7 +54,7 @@ static void __cpuinit msm_secondary_init(unsigned int cpu)
        spin_unlock(&boot_lock);
 }
-static __cpuinit void prepare_cold_cpu(unsigned int cpu)
+static void prepare_cold_cpu(unsigned int cpu)
 {
        int ret;
        ret = scm_set_boot_addr(virt_to_phys(msm_secondary_startup),
@@ -73,7 +73,7 @@ static __cpuinit void prepare_cold_cpu(unsigned int cpu)
                                  "address\n");
 }
-static int __cpuinit msm_boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int msm_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
        unsigned long timeout;
        static int cold_boot_done;
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 284313f3e02c..8697cfc0d0b6 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -23,10 +23,10 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
+#include <linux/sched_clock.h>
 #include <asm/mach/time.h>
 #include <asm/localtimer.h>
-#include <asm/sched_clock.h>
 #include "common.h"
@@ -139,7 +139,7 @@ static struct clocksource msm_clocksource = {
 };
 #ifdef CONFIG_LOCAL_TIMERS
-static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt)
+static int msm_local_timer_setup(struct clock_event_device *evt)
 {
        /* Use existing clock_event for cpu 0 */
        if (!smp_processor_id())
@@ -164,7 +164,7 @@ static void msm_local_timer_stop(struct clock_event_device *evt)
        disable_percpu_irq(evt->irq);
 }
-static struct local_timer_ops msm_local_timer_ops __cpuinitdata = {
+static struct local_timer_ops msm_local_timer_ops = {
        .setup  = msm_local_timer_setup,
        .stop   = msm_local_timer_stop,
 };
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index 749a7f8c4992..75062eff2494 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -413,7 +413,7 @@ void __init mv78xx0_init(void)
        clk_init();
 }
-void mv78xx0_restart(char mode, const char *cmd)
+void mv78xx0_restart(enum reboot_mode mode, const char *cmd)
 {
        /*
         * Enable soft reset to assert RSTOUTn.
diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h
index 5e9485bad0ac..6889af26077d 100644
--- a/arch/arm/mach-mv78xx0/common.h
+++ b/arch/arm/mach-mv78xx0/common.h
@@ -11,6 +11,8 @@
 #ifndef __ARCH_MV78XX0_COMMON_H
 #define __ARCH_MV78XX0_COMMON_H
+#include <linux/reboot.h>
 struct mv643xx_eth_platform_data;
 struct mv_sata_platform_data;
@@ -45,7 +47,7 @@ void mv78xx0_uart1_init(void);
 void mv78xx0_uart2_init(void);
 void mv78xx0_uart3_init(void);
 void mv78xx0_i2c_init(void);
-void mv78xx0_restart(char, const char *);
+void mv78xx0_restart(enum reboot_mode, const char *);
 extern void mv78xx0_timer_init(void);
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 80a8bcacd9d5..9eb63d724602 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -10,12 +10,11 @@ config ARCH_MVEBU
        select PLAT_ORION
        select SPARSE_IRQ
        select CLKDEV_LOOKUP
-        select MVEBU_CLK_CORE
-        select MVEBU_CLK_CPU
-        select MVEBU_CLK_GATING
        select MVEBU_MBUS
        select ZONE_DMA if ARM_LPAE
        select ARCH_REQUIRE_GPIOLIB
+        select MIGHT_HAVE_PCI
+        select PCI_QUIRKS if PCI
 if ARCH_MVEBU
@@ -30,6 +29,7 @@ config MACH_ARMADA_370_XP
 config MACH_ARMADA_370
        bool "Marvell Armada 370 boards"
+        select ARMADA_370_CLK
        select MACH_ARMADA_370_XP
        select PINCTRL_ARMADA_370
        help
@@ -38,6 +38,7 @@ config MACH_ARMADA_370
 config MACH_ARMADA_XP
        bool "Marvell Armada XP boards"
+        select ARMADA_XP_CLK
        select MACH_ARMADA_370_XP
        select PINCTRL_ARMADA_XP
        help
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index 1c48890bb72b..97cbb8021919 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -14,13 +14,13 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
 #include <linux/of_platform.h>
 #include <linux/io.h>
 #include <linux/time-armada-370-xp.h>
-#include <linux/clk/mvebu.h>
 #include <linux/dma-mapping.h>
 #include <linux/mbus.h>
-#include <linux/irqchip.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -29,45 +29,49 @@
 #include "common.h"
 #include "coherency.h"
-static struct map_desc armada_370_xp_io_desc[] __initdata = {
+static void __init armada_370_xp_map_io(void)
-        {
-                .virtual        = (unsigned long) ARMADA_370_XP_REGS_VIRT_BASE,
-                .pfn            = __phys_to_pfn(ARMADA_370_XP_REGS_PHYS_BASE),
-                .length         = ARMADA_370_XP_REGS_SIZE,
-                .type           = MT_DEVICE,
-        },
-};
-void __init armada_370_xp_map_io(void)
 {
-        iotable_init(armada_370_xp_io_desc, ARRAY_SIZE(armada_370_xp_io_desc));
+        debug_ll_io_init();
 }
-void __init armada_370_xp_timer_and_clk_init(void)
+/*
-{
+ * This initialization will be replaced by a DT-based
-        mvebu_clocks_init();
+ * initialization once the mvebu-mbus driver gains DT support.
-        armada_370_xp_timer_init();
+ */
-}
-void __init armada_370_xp_init_early(void)
+#define ARMADA_370_XP_MBUS_WINS_OFFS   0x20000
+#define ARMADA_370_XP_MBUS_WINS_SIZE   0x100
+#define ARMADA_370_XP_SDRAM_WINS_OFFS  0x20180
+#define ARMADA_370_XP_SDRAM_WINS_SIZE  0x20
+static void __init armada_370_xp_mbus_init(void)
 {
        char *mbus_soc_name;
+        struct device_node *dn;
+        const __be32 mbus_wins_offs = cpu_to_be32(ARMADA_370_XP_MBUS_WINS_OFFS);
+        const __be32 sdram_wins_offs = cpu_to_be32(ARMADA_370_XP_SDRAM_WINS_OFFS);
-        /*
-         * This initialization will be replaced by a DT-based
-         * initialization once the mvebu-mbus driver gains DT support.
-         */
        if (of_machine_is_compatible("marvell,armada370"))
                mbus_soc_name = "marvell,armada370-mbus";
        else
                mbus_soc_name = "marvell,armadaxp-mbus";
+        dn = of_find_node_by_name(NULL, "internal-regs");
+        BUG_ON(!dn);
        mvebu_mbus_init(mbus_soc_name,
-                        ARMADA_370_XP_MBUS_WINS_BASE,
+                        of_translate_address(dn, &mbus_wins_offs),
                        ARMADA_370_XP_MBUS_WINS_SIZE,
-                        ARMADA_370_XP_SDRAM_WINS_BASE,
+                        of_translate_address(dn, &sdram_wins_offs),
                        ARMADA_370_XP_SDRAM_WINS_SIZE);
+}
+static void __init armada_370_xp_timer_and_clk_init(void)
+{
+        of_clk_init(NULL);
+        armada_370_xp_timer_init();
+        coherency_init();
+        armada_370_xp_mbus_init();
 #ifdef CONFIG_CACHE_L2X0
        l2x0_of_init(0, ~0UL);
 #endif
@@ -76,7 +80,6 @@ void __init armada_370_xp_init_early(void)
 static void __init armada_370_xp_dt_init(void)
 {
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-        coherency_init();
 }
 static const char * const armada_370_xp_dt_compat[] = {
@@ -88,8 +91,6 @@ DT_MACHINE_START(ARMADA_XP_DT, "Marvell Armada 370/XP (Device Tree)")
        .smp            = smp_ops(armada_xp_smp_ops),
        .init_machine   = armada_370_xp_dt_init,
        .map_io         = armada_370_xp_map_io,
-        .init_early     = armada_370_xp_init_early,
-        .init_irq       = irqchip_init,
        .init_time      = armada_370_xp_timer_and_clk_init,
        .restart        = mvebu_restart,
        .dt_compat      = armada_370_xp_dt_compat,
diff --git a/arch/arm/mach-mvebu/armada-370-xp.h b/arch/arm/mach-mvebu/armada-370-xp.h
index 2070e1b4f342..c612b2c4ed6c 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.h
+++ b/arch/arm/mach-mvebu/armada-370-xp.h
@@ -15,16 +15,6 @@
 #ifndef __MACH_ARMADA_370_XP_H
 #define __MACH_ARMADA_370_XP_H
-#define ARMADA_370_XP_REGS_PHYS_BASE    0xd0000000
-#define ARMADA_370_XP_REGS_VIRT_BASE    IOMEM(0xfec00000)
-#define ARMADA_370_XP_REGS_SIZE         SZ_1M
-/* These defines can go away once mvebu-mbus has a DT binding */
-#define ARMADA_370_XP_MBUS_WINS_BASE    (ARMADA_370_XP_REGS_PHYS_BASE + 0x20000)
-#define ARMADA_370_XP_MBUS_WINS_SIZE    0x100
-#define ARMADA_370_XP_SDRAM_WINS_BASE   (ARMADA_370_XP_REGS_PHYS_BASE + 0x20180)
-#define ARMADA_370_XP_SDRAM_WINS_SIZE   0x20
 #ifdef CONFIG_SMP
 #include <linux/cpumask.h>
diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c
index 8278960066c3..4c24303ec481 100644
--- a/arch/arm/mach-mvebu/coherency.c
+++ b/arch/arm/mach-mvebu/coherency.c
@@ -25,16 +25,11 @@
 #include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
 #include <asm/smp_plat.h>
+#include <asm/cacheflush.h>
 #include "armada-370-xp.h"
-/*
+unsigned long coherency_phys_base;
- * Some functions in this file are called very early during SMP
+static void __iomem *coherency_base;
- * initialization. At that time the device tree framework is not yet
- * ready, and it is not possible to get the register address to
- * ioremap it. That's why the pointer below is given with an initial
- * value matching its virtual mapping
- */
-static void __iomem *coherency_base = ARMADA_370_XP_REGS_VIRT_BASE + 0x20200;
 static void __iomem *coherency_cpu_base;
 /* Coherency fabric registers */
@@ -47,18 +42,6 @@ static struct of_device_id of_coherency_table[] = {
        { /* end of list */ },
 };
-#ifdef CONFIG_SMP
-int coherency_get_cpu_count(void)
-{
-        int reg, cnt;
-        reg = readl(coherency_base + COHERENCY_FABRIC_CFG_OFFSET);
-        cnt = (reg & 0xF) + 1;
-        return cnt;
-}
-#endif
 /* Function defined in coherency_ll.S */
 int ll_set_cpu_coherent(void __iomem *base_addr, unsigned int hw_cpu_id);
@@ -143,13 +126,31 @@ int __init coherency_init(void)
        np = of_find_matching_node(NULL, of_coherency_table);
        if (np) {
+                struct resource res;
                pr_info("Initializing Coherency fabric\n");
+                of_address_to_resource(np, 0, &res);
+                coherency_phys_base = res.start;
+                /*
+                 * Ensure secondary CPUs will see the updated value,
+                 * which they read before they join the coherency
+                 * fabric, and therefore before they are coherent with
+                 * the boot CPU cache.
+                 */
+                sync_cache_w(&coherency_phys_base);
                coherency_base = of_iomap(np, 0);
                coherency_cpu_base = of_iomap(np, 1);
                set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
-                bus_register_notifier(&platform_bus_type,
-                                        &mvebu_hwcc_platform_nb);
        }
        return 0;
 }
+static int __init coherency_late_init(void)
+{
+        if (of_find_matching_node(NULL, of_coherency_table))
+                bus_register_notifier(&platform_bus_type,
+                                      &mvebu_hwcc_platform_nb);
+        return 0;
+}
+postcore_initcall(coherency_late_init);
diff --git a/arch/arm/mach-mvebu/coherency.h b/arch/arm/mach-mvebu/coherency.h
index 2f428137f6fe..df33ad8a6c08 100644
--- a/arch/arm/mach-mvebu/coherency.h
+++ b/arch/arm/mach-mvebu/coherency.h
@@ -14,10 +14,6 @@
 #ifndef __MACH_370_XP_COHERENCY_H
 #define __MACH_370_XP_COHERENCY_H
-#ifdef CONFIG_SMP
-int coherency_get_cpu_count(void);
-#endif
 int set_cpu_coherent(int cpu_id, int smp_group_id);
 int coherency_init(void);
diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h
index aa27bc2ffb60..e366010e1d91 100644
--- a/arch/arm/mach-mvebu/common.h
+++ b/arch/arm/mach-mvebu/common.h
@@ -15,7 +15,11 @@
 #ifndef __ARCH_MVEBU_COMMON_H
 #define __ARCH_MVEBU_COMMON_H
-void mvebu_restart(char mode, const char *cmd);
+#define ARMADA_XP_MAX_CPUS 4
+#include <linux/reboot.h>
+void mvebu_restart(enum reboot_mode mode, const char *cmd);
 void armada_370_xp_init_irq(void);
 void armada_370_xp_handle_irq(struct pt_regs *regs);
diff --git a/arch/arm/mach-mvebu/headsmp.S b/arch/arm/mach-mvebu/headsmp.S
index a06e0ede8c08..8a1b0c96e9ec 100644
--- a/arch/arm/mach-mvebu/headsmp.S
+++ b/arch/arm/mach-mvebu/headsmp.S
@@ -22,28 +22,26 @@
 #include <linux/init.h>
 /*
- * At this stage the secondary CPUs don't have acces yet to the MMU, so
- * we have to provide physical addresses
- */
-#define ARMADA_XP_CFB_BASE           0xD0020200
-        __CPUINIT
-/*
 * Armada XP specific entry point for secondary CPUs.
 * We add the CPU to the coherency fabric and then jump to secondary
 * startup
 */
 ENTRY(armada_xp_secondary_startup)
+        /* Get coherency fabric base physical address */
+        adr     r0, 1f
+        ldr     r1, [r0]
+        ldr     r0, [r0, r1]
        /* Read CPU id */
        mrc     p15, 0, r1, c0, c0, 5
        and     r1, r1, #0xF
        /* Add CPU to coherency fabric */
-        ldr     r0, =ARMADA_XP_CFB_BASE
        bl      ll_set_cpu_coherent
        b       secondary_startup
 ENDPROC(armada_xp_secondary_startup)
+        .align 2
+1:
+        .long   coherency_phys_base - .
diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
index 875ea748391c..ce81d3031405 100644
--- a/arch/arm/mach-mvebu/platsmp.c
+++ b/arch/arm/mach-mvebu/platsmp.c
@@ -71,13 +71,12 @@ void __init set_secondary_cpus_clock(void)
        }
 }
-static void __cpuinit armada_xp_secondary_init(unsigned int cpu)
+static void armada_xp_secondary_init(unsigned int cpu)
 {
        armada_xp_mpic_smp_cpu_init();
 }
-static int __cpuinit armada_xp_boot_secondary(unsigned int cpu,
+static int armada_xp_boot_secondary(unsigned int cpu, struct task_struct *idle)
-                                              struct task_struct *idle)
 {
        pr_info("Booting CPU %d\n", cpu);
@@ -88,8 +87,16 @@ static int __cpuinit armada_xp_boot_secondary(unsigned int cpu,
 static void __init armada_xp_smp_init_cpus(void)
 {
+        struct device_node *np;
        unsigned int i, ncores;
-        ncores = coherency_get_cpu_count();
+        np = of_find_node_by_name(NULL, "cpus");
+        if (!np)
+                panic("No 'cpus' node found\n");
+        ncores = of_get_child_count(np);
+        if (ncores == 0 || ncores > ARMADA_XP_MAX_CPUS)
+                panic("Invalid number of CPUs in DT\n");
        /* Limit possible CPUs to defconfig */
        if (ncores > nr_cpu_ids) {
diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c
index b8079df8c986..f875124ff4f9 100644
--- a/arch/arm/mach-mvebu/system-controller.c
+++ b/arch/arm/mach-mvebu/system-controller.c
@@ -26,6 +26,7 @@
 #include <linux/init.h>
 #include <linux/of_address.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 static void __iomem *system_controller_base;
@@ -63,7 +64,7 @@ static struct of_device_id of_system_controller_table[] = {
        { /* end of list */ },
 };
-void mvebu_restart(char mode, const char *cmd)
+void mvebu_restart(enum reboot_mode mode, const char *cmd)
 {
        if (!system_controller_base) {
                pr_err("Cannot restart, system-controller not available: check the device tree\n");
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index 4dc2fbba0ecd..8cde9e05b5d6 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -3,7 +3,6 @@ config SOC_IMX23
        select ARM_AMBA
        select ARM_CPU_SUSPEND if PM
        select CPU_ARM926T
-        select HAVE_PWM
        select PINCTRL_IMX23
 config SOC_IMX28
@@ -11,8 +10,6 @@ config SOC_IMX28
        select ARM_AMBA
        select ARM_CPU_SUSPEND if PM
        select CPU_ARM926T
-        select HAVE_CAN_FLEXCAN if CAN
-        select HAVE_PWM
        select PINCTRL_IMX28
 config ARCH_MXS
@@ -25,6 +22,7 @@ config ARCH_MXS
        select GENERIC_CLOCKEVENTS
        select HAVE_CLK_PREPARE
        select PINCTRL
+        select SOC_BUS
        select SOC_IMX23
        select SOC_IMX28
        select STMP_DEVICE
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 5b62b6489d4b..4ce27b536dc9 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -14,18 +14,18 @@
 #include <linux/clk/mxs.h>
 #include <linux/clkdev.h>
 #include <linux/clocksource.h>
-#include <linux/can/platform/flexcan.h>
 #include <linux/delay.h>
 #include <linux/err.h>
 #include <linux/gpio.h>
 #include <linux/init.h>
-#include <linux/irqchip.h>
 #include <linux/irqchip/mxs.h>
+#include <linux/reboot.h>
 #include <linux/micrel_phy.h>
 #include <linux/of_address.h>
 #include <linux/of_platform.h>
 #include <linux/phy.h>
 #include <linux/pinctrl/consumer.h>
+#include <linux/sys_soc.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
@@ -39,12 +39,28 @@
 #define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0         0x2
 #define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR1         0x3
+#define HW_DIGCTL_CHIPID        0x310
+#define HW_DIGCTL_CHIPID_MASK   (0xffff << 16)
+#define HW_DIGCTL_REV_MASK      0xff
+#define HW_DIGCTL_CHIPID_MX23   (0x3780 << 16)
+#define HW_DIGCTL_CHIPID_MX28   (0x2800 << 16)
+#define MXS_CHIP_REVISION_1_0   0x10
+#define MXS_CHIP_REVISION_1_1   0x11
+#define MXS_CHIP_REVISION_1_2   0x12
+#define MXS_CHIP_REVISION_1_3   0x13
+#define MXS_CHIP_REVISION_1_4   0x14
+#define MXS_CHIP_REV_UNKNOWN    0xff
 #define MXS_GPIO_NR(bank, nr)   ((bank) * 32 + (nr))
 #define MXS_SET_ADDR            0x4
 #define MXS_CLR_ADDR            0x8
 #define MXS_TOG_ADDR            0xc
+static u32 chipid;
+static u32 socid;
 static inline void __mxs_setl(u32 mask, void __iomem *reg)
 {
        __raw_writel(mask, reg + MXS_SET_ADDR);
@@ -60,41 +76,6 @@ static inline void __mxs_togl(u32 mask, void __iomem *reg)
        __raw_writel(mask, reg + MXS_TOG_ADDR);
 }
-/*
- * MX28EVK_FLEXCAN_SWITCH is shared between both flexcan controllers
- */
-#define MX28EVK_FLEXCAN_SWITCH  MXS_GPIO_NR(2, 13)
-static int flexcan0_en, flexcan1_en;
-static void mx28evk_flexcan_switch(void)
-{
-        if (flexcan0_en || flexcan1_en)
-                gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 1);
-        else
-                gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 0);
-}
-static void mx28evk_flexcan0_switch(int enable)
-{
-        flexcan0_en = enable;
-        mx28evk_flexcan_switch();
-}
-static void mx28evk_flexcan1_switch(int enable)
-{
-        flexcan1_en = enable;
-        mx28evk_flexcan_switch();
-}
-static struct flexcan_platform_data flexcan_pdata[2];
-static struct of_dev_auxdata mxs_auxdata_lookup[] __initdata = {
-        OF_DEV_AUXDATA("fsl,imx28-flexcan", 0x80032000, NULL, &flexcan_pdata[0]),
-        OF_DEV_AUXDATA("fsl,imx28-flexcan", 0x80034000, NULL, &flexcan_pdata[1]),
-        { /* sentinel */ }
-};
 #define OCOTP_WORD_OFFSET               0x20
 #define OCOTP_WORD_COUNT                0x20
@@ -254,15 +235,6 @@ static void __init imx28_evk_init(void)
        mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0);
 }
-static void __init imx28_evk_post_init(void)
-{
-        if (!gpio_request_one(MX28EVK_FLEXCAN_SWITCH, GPIOF_DIR_OUT,
-                              "flexcan-switch")) {
-                flexcan_pdata[0].transceiver_switch = mx28evk_flexcan0_switch;
-                flexcan_pdata[1].transceiver_switch = mx28evk_flexcan1_switch;
-        }
-}
 static int apx4devkit_phy_fixup(struct phy_device *phy)
 {
        phy->dev_flags |= MICREL_PHY_50MHZ_CLK;
@@ -352,35 +324,126 @@ static void __init tx28_post_init(void)
        pinctrl_put(pctl);
 }
-static void __init cfa10049_init(void)
+static void __init crystalfontz_init(void)
 {
        update_fec_mac_prop(OUI_CRYSTALFONTZ);
 }
-static void __init cfa10037_init(void)
+static const char __init *mxs_get_soc_id(void)
 {
-        update_fec_mac_prop(OUI_CRYSTALFONTZ);
+        struct device_node *np;
+        void __iomem *digctl_base;
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx23-digctl");
+        digctl_base = of_iomap(np, 0);
+        WARN_ON(!digctl_base);
+        chipid = readl(digctl_base + HW_DIGCTL_CHIPID);
+        socid = chipid & HW_DIGCTL_CHIPID_MASK;
+        iounmap(digctl_base);
+        of_node_put(np);
+        switch (socid) {
+        case HW_DIGCTL_CHIPID_MX23:
+                return "i.MX23";
+        case HW_DIGCTL_CHIPID_MX28:
+                return "i.MX28";
+        default:
+                return "Unknown";
+        }
+}
+static u32 __init mxs_get_cpu_rev(void)
+{
+        u32 rev = chipid & HW_DIGCTL_REV_MASK;
+        switch (socid) {
+        case HW_DIGCTL_CHIPID_MX23:
+                switch (rev) {
+                case 0x0:
+                        return MXS_CHIP_REVISION_1_0;
+                case 0x1:
+                        return MXS_CHIP_REVISION_1_1;
+                case 0x2:
+                        return MXS_CHIP_REVISION_1_2;
+                case 0x3:
+                        return MXS_CHIP_REVISION_1_3;
+                case 0x4:
+                        return MXS_CHIP_REVISION_1_4;
+                default:
+                        return MXS_CHIP_REV_UNKNOWN;
+                }
+        case HW_DIGCTL_CHIPID_MX28:
+                switch (rev) {
+                case 0x0:
+                        return MXS_CHIP_REVISION_1_1;
+                case 0x1:
+                        return MXS_CHIP_REVISION_1_2;
+                default:
+                        return MXS_CHIP_REV_UNKNOWN;
+                }
+        default:
+                return MXS_CHIP_REV_UNKNOWN;
+        }
+}
+static const char __init *mxs_get_revision(void)
+{
+        u32 rev = mxs_get_cpu_rev();
+        if (rev != MXS_CHIP_REV_UNKNOWN)
+                return kasprintf(GFP_KERNEL, "TO%d.%d", (rev >> 4) & 0xf,
+                                rev & 0xf);
+        else
+                return kasprintf(GFP_KERNEL, "%s", "Unknown");
 }
 static void __init mxs_machine_init(void)
 {
+        struct device_node *root;
+        struct device *parent;
+        struct soc_device *soc_dev;
+        struct soc_device_attribute *soc_dev_attr;
+        int ret;
+        soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+        if (!soc_dev_attr)
+                return;
+        root = of_find_node_by_path("/");
+        ret = of_property_read_string(root, "model", &soc_dev_attr->machine);
+        if (ret)
+                return;
+        soc_dev_attr->family = "Freescale MXS Family";
+        soc_dev_attr->soc_id = mxs_get_soc_id();
+        soc_dev_attr->revision = mxs_get_revision();
+        soc_dev = soc_device_register(soc_dev_attr);
+        if (IS_ERR(soc_dev)) {
+                kfree(soc_dev_attr->revision);
+                kfree(soc_dev_attr);
+                return;
+        }
+        parent = soc_device_to_device(soc_dev);
        if (of_machine_is_compatible("fsl,imx28-evk"))
                imx28_evk_init();
        else if (of_machine_is_compatible("bluegiga,apx4devkit"))
                apx4devkit_init();
-        else if (of_machine_is_compatible("crystalfontz,cfa10037"))
+        else if (of_machine_is_compatible("crystalfontz,cfa10037") ||
-                cfa10037_init();
+                 of_machine_is_compatible("crystalfontz,cfa10049") ||
-        else if (of_machine_is_compatible("crystalfontz,cfa10049"))
+                 of_machine_is_compatible("crystalfontz,cfa10055") ||
-                cfa10049_init();
+                 of_machine_is_compatible("crystalfontz,cfa10057"))
+                crystalfontz_init();
        of_platform_populate(NULL, of_default_bus_match_table,
-                             mxs_auxdata_lookup, NULL);
+                             NULL, parent);
        if (of_machine_is_compatible("karo,tx28"))
                tx28_post_init();
-        if (of_machine_is_compatible("fsl,imx28-evk"))
-                imx28_evk_post_init();
 }
 #define MX23_CLKCTRL_RESET_OFFSET       0x120
@@ -390,7 +453,7 @@ static void __init mxs_machine_init(void)
 /*
 * Reset the system. It is called by machine_restart().
 */
-static void mxs_restart(char mode, const char *cmd)
+static void mxs_restart(enum reboot_mode mode, const char *cmd)
 {
        struct device_node *np;
        void __iomem *reset_addr;
@@ -434,8 +497,6 @@ static const char *mxs_dt_compat[] __initdata = {
 };
 DT_MACHINE_START(MXS, "Freescale MXS (Device Tree)")
-        .map_io         = debug_ll_io_init,
-        .init_irq       = irqchip_init,
        .handle_irq     = icoll_handle_irq,
        .init_time      = mxs_timer_init,
        .init_machine   = mxs_machine_init,
diff --git a/arch/arm/mach-mxs/pm.h b/arch/arm/mach-mxs/pm.h
index f57e7cdece2e..09d77b00a96b 100644
--- a/arch/arm/mach-mxs/pm.h
+++ b/arch/arm/mach-mxs/pm.h
@@ -9,6 +9,10 @@
 #ifndef __ARCH_MXS_PM_H
 #define __ARCH_MXS_PM_H
+#ifdef CONFIG_PM
 void mxs_pm_init(void);
+#else
+#define mxs_pm_init NULL
+#endif
 #endif
diff --git a/arch/arm/mach-netx/generic.c b/arch/arm/mach-netx/generic.c
index 1504b68f4c66..db25b0cef3a7 100644
--- a/arch/arm/mach-netx/generic.c
+++ b/arch/arm/mach-netx/generic.c
@@ -24,6 +24,7 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/irqchip/arm-vic.h>
+#include <linux/reboot.h>
 #include <mach/hardware.h>
 #include <asm/mach/map.h>
 #include <mach/netx-regs.h>
@@ -187,7 +188,7 @@ static int __init netx_init(void)
 subsys_initcall(netx_init);
-void netx_restart(char mode, const char *cmd)
+void netx_restart(enum reboot_mode mode, const char *cmd)
 {
        writel(NETX_SYSTEM_RES_CR_FIRMW_RES_EN | NETX_SYSTEM_RES_CR_FIRMW_RES,
               NETX_SYSTEM_RES_CR);
diff --git a/arch/arm/mach-netx/generic.h b/arch/arm/mach-netx/generic.h
index 768b26bbb42b..bb2ce471cc28 100644
--- a/arch/arm/mach-netx/generic.h
+++ b/arch/arm/mach-netx/generic.h
@@ -17,8 +17,10 @@
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
+#include <linux/reboot.h>
 extern void __init netx_map_io(void);
 extern void __init netx_init_irq(void);
-extern void netx_restart(char, const char *);
+extern void netx_restart(enum reboot_mode, const char *);
 extern void netx_timer_init(void);
diff --git a/arch/arm/mach-nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig
index 9b9d105f194c..5981c3db9b41 100644
--- a/arch/arm/mach-nomadik/Kconfig
+++ b/arch/arm/mach-nomadik/Kconfig
@@ -6,6 +6,7 @@ config ARCH_NOMADIK
        select ARM_VIC
        select CLKSRC_NOMADIK_MTU
        select CLKSRC_NOMADIK_MTU_SCHED_CLOCK
+        select CLKSRC_OF
        select COMMON_CLK
        select CPU_ARM926T
        select GENERIC_CLOCKEVENTS
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
index 59f6ff5c9bae..13e0df9c11ce 100644
--- a/arch/arm/mach-nomadik/cpu-8815.c
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -25,11 +25,8 @@
 #include <linux/slab.h>
 #include <linux/irq.h>
 #include <linux/dma-mapping.h>
-#include <linux/irqchip.h>
 #include <linux/platform_data/clk-nomadik.h>
-#include <linux/platform_data/pinctrl-nomadik.h>
+#include <linux/clocksource.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/platform_data/clocksource-nomadik-mtu.h>
 #include <linux/of_irq.h>
 #include <linux/of_gpio.h>
 #include <linux/of_address.h>
@@ -91,48 +88,6 @@
 #define NOMADIK_L2CC_BASE       0x10210000      /* L2 Cache controller */
 #define NOMADIK_UART1_VBASE     0xF01FB000
-static unsigned long out_low[] = { PIN_OUTPUT_LOW };
-static unsigned long out_high[] = { PIN_OUTPUT_HIGH };
-static unsigned long in_nopull[] = { PIN_INPUT_NOPULL };
-static unsigned long in_pullup[] = { PIN_INPUT_PULLUP };
-static struct pinctrl_map __initdata nhk8815_pinmap[] = {
-        PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-stn8815", "u0_a_1", "u0"),
-        PIN_MAP_MUX_GROUP_DEFAULT("uart1", "pinctrl-stn8815", "u1_a_1", "u1"),
-        /* Hog in MMC/SD card mux */
-        PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-stn8815", "mmcsd_a_1", "mmcsd"),
-        /* MCCLK */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO8_B10", out_low),
-        /* MCCMD */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO9_A10", in_pullup),
-        /* MCCMDDIR */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO10_C11", out_high),
-        /* MCDAT3-0 */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO11_B11", in_pullup),
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO12_A11", in_pullup),
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO13_C12", in_pullup),
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO14_B12", in_pullup),
-        /* MCDAT0DIR */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO15_A12", out_high),
-        /* MCDAT31DIR */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO16_C13", out_high),
-        /* MCMSFBCLK */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO24_C15", in_pullup),
-        /* CD input GPIO */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO111_H21", in_nopull),
-        /* CD bias drive */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO112_J21", out_low),
-        /* I2C0 */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO62_D3", in_pullup),
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO63_D2", in_pullup),
-        /* I2C1 */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO53_L4", in_pullup),
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO54_L3", in_pullup),
-        /* I2C2 */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO73_C21", in_pullup),
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO74_C20", in_pullup),
-};
 /* This is needed for LL-debug/earlyprintk/debug-macro.S */
 static struct map_desc cpu8815_io_desc[] __initdata = {
        {
@@ -148,7 +103,7 @@ static void __init cpu8815_map_io(void)
        iotable_init(cpu8815_io_desc, ARRAY_SIZE(cpu8815_io_desc));
 }
-static void cpu8815_restart(char mode, const char *cmd)
+static void cpu8815_restart(enum reboot_mode mode, const char *cmd)
 {
        void __iomem *srcbase = ioremap(NOMADIK_SRC_BASE, SZ_4K);
@@ -172,7 +127,7 @@ static void __init cpu8815_timer_init_of(void)
        /* We need this to be up now */
        nomadik_clk_init();
-        mtu = of_find_node_by_path("/mtu0");
+        mtu = of_find_node_by_path("/mtu@101e2000");
        if (!mtu)
                return;
        base = of_iomap(mtu, 0);
@@ -188,7 +143,7 @@ static void __init cpu8815_timer_init_of(void)
        src_cr |= SRC_CR_INIT_VAL;
        writel(src_cr, base);
-        nmdk_timer_init(base, irq);
+        clocksource_of_init();
 }
 static struct fsmc_nand_timings cpu8815_nand_timings = {
@@ -280,28 +235,10 @@ device_initcall(cpu8815_mmcsd_init);
 /* These are mostly to get the right device names for the clock lookups */
 static struct of_dev_auxdata cpu8815_auxdata_lookup[] __initdata = {
-        OF_DEV_AUXDATA("st,nomadik-gpio", NOMADIK_GPIO0_BASE,
-                "gpio.0", NULL),
-        OF_DEV_AUXDATA("st,nomadik-gpio", NOMADIK_GPIO1_BASE,
-                "gpio.1", NULL),
-        OF_DEV_AUXDATA("st,nomadik-gpio", NOMADIK_GPIO2_BASE,
-                "gpio.2", NULL),
-        OF_DEV_AUXDATA("st,nomadik-gpio", NOMADIK_GPIO3_BASE,
-                "gpio.3", NULL),
-        OF_DEV_AUXDATA("stericsson,nmk-pinctrl-stn8815", 0,
-                "pinctrl-stn8815", NULL),
-        OF_DEV_AUXDATA("arm,primecell", NOMADIK_UART0_BASE,
-                "uart0", NULL),
-        OF_DEV_AUXDATA("arm,primecell", NOMADIK_UART1_BASE,
-                "uart1", NULL),
-        OF_DEV_AUXDATA("arm,primecell", NOMADIK_RNG_BASE,
-                "rng", NULL),
-        OF_DEV_AUXDATA("arm,primecell", NOMADIK_RTC_BASE,
-                "rtc-pl031", NULL),
        OF_DEV_AUXDATA("stericsson,fsmc-nand", NOMADIK_FSMC_BASE,
-                "fsmc-nand", &cpu8815_nand_data),
+                NULL, &cpu8815_nand_data),
        OF_DEV_AUXDATA("arm,primecell", NOMADIK_SDI_BASE,
-                "mmci", &mmcsd_plat_data),
+                NULL, &mmcsd_plat_data),
        { /* sentinel */ },
 };
@@ -311,7 +248,6 @@ static void __init cpu8815_init_of(void)
        /* At full speed latency must be >=2, so 0x249 in low bits */
        l2x0_of_init(0x00730249, 0xfe000fff);
 #endif
-        pinctrl_register_mappings(nhk8815_pinmap, ARRAY_SIZE(nhk8815_pinmap));
        of_platform_populate(NULL, of_default_bus_match_table,
                        cpu8815_auxdata_lookup, NULL);
 }
@@ -323,7 +259,6 @@ static const char * cpu8815_board_compat[] = {
 DT_MACHINE_START(NOMADIK_DT, "Nomadik STn8815")
        .map_io         = cpu8815_map_io,
-        .init_irq       = irqchip_init,
        .init_time      = cpu8815_timer_init_of,
        .init_machine   = cpu8815_init_of,
        .restart        = cpu8815_restart,
diff --git a/arch/arm/mach-nspire/Kconfig b/arch/arm/mach-nspire/Kconfig
new file mode 100644
index 000000000000..59d8f0a70919
--- /dev/null
+++ b/arch/arm/mach-nspire/Kconfig
@@ -0,0 +1,16 @@
+config ARCH_NSPIRE
+        bool "TI-NSPIRE based"
+        depends on ARCH_MULTI_V4_V5
+        depends on MMU
+        select CPU_ARM926T
+        select COMMON_CLK
+        select GENERIC_CLOCKEVENTS
+        select GENERIC_IRQ_CHIP
+        select SPARSE_IRQ
+        select ARM_AMBA
+        select ARM_VIC
+        select ARM_TIMER_SP804
+        select USE_OF
+        select CLKSRC_OF
+        help
+          This enables support for systems using the TI-NSPIRE CPU
diff --git a/arch/arm/mach-nspire/Makefile b/arch/arm/mach-nspire/Makefile
new file mode 100644
index 000000000000..1bec256eba07
--- /dev/null
+++ b/arch/arm/mach-nspire/Makefile
@@ -0,0 +1,2 @@
+obj-y                           += nspire.o
+obj-y                           += clcd.o
diff --git a/arch/arm/mach-nspire/Makefile.boot b/arch/arm/mach-nspire/Makefile.boot
new file mode 100644
index 000000000000..e69de29bb2d1
--- /dev/null
+++ b/arch/arm/mach-nspire/Makefile.boot
diff --git a/arch/arm/mach-nspire/clcd.c b/arch/arm/mach-nspire/clcd.c
new file mode 100644
index 000000000000..abea12617b17
--- /dev/null
+++ b/arch/arm/mach-nspire/clcd.c
@@ -0,0 +1,119 @@
+/*
+ *      linux/arch/arm/mach-nspire/clcd.c
+ *
+ *      Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/clcd.h>
+#include <linux/dma-mapping.h>
+static struct clcd_panel nspire_cx_lcd_panel = {
+        .mode           = {
+                .name           = "Color LCD",
+                .refresh        = 60,
+                .xres           = 320,
+                .yres           = 240,
+                .sync           = 0,
+                .vmode          = FB_VMODE_NONINTERLACED,
+                .pixclock       = 1,
+                .hsync_len      = 6,
+                .vsync_len      = 1,
+                .right_margin   = 50,
+                .left_margin    = 38,
+                .lower_margin   = 3,
+                .upper_margin   = 17,
+        },
+        .width          = 65, /* ~6.50 cm */
+        .height         = 49, /* ~4.87 cm */
+        .tim2           = TIM2_IPC,
+        .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
+        .bpp            = 16,
+        .caps           = CLCD_CAP_565,
+};
+static struct clcd_panel nspire_classic_lcd_panel = {
+        .mode           = {
+                .name           = "Grayscale LCD",
+                .refresh        = 60,
+                .xres           = 320,
+                .yres           = 240,
+                .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+                .vmode          = FB_VMODE_NONINTERLACED,
+                .pixclock       = 1,
+                .hsync_len      = 6,
+                .vsync_len      = 1,
+                .right_margin   = 6,
+                .left_margin    = 6,
+        },
+        .width          = 71, /* 7.11cm */
+        .height         = 53, /* 5.33cm */
+        .tim2           = 0x80007d0,
+        .cntl           = CNTL_LCDMONO8,
+        .bpp            = 8,
+        .grayscale      = 1,
+        .caps           = CLCD_CAP_5551,
+};
+int nspire_clcd_setup(struct clcd_fb *fb)
+{
+        struct clcd_panel *panel;
+        size_t panel_size;
+        const char *type;
+        dma_addr_t dma;
+        int err;
+        BUG_ON(!fb->dev->dev.of_node);
+        err = of_property_read_string(fb->dev->dev.of_node, "lcd-type", &type);
+        if (err) {
+                pr_err("CLCD: Could not find lcd-type property\n");
+                return err;
+        }
+        if (!strcmp(type, "cx")) {
+                panel = &nspire_cx_lcd_panel;
+        } else if (!strcmp(type, "classic")) {
+                panel = &nspire_classic_lcd_panel;
+        } else {
+                pr_err("CLCD: Unknown lcd-type %s\n", type);
+                return -EINVAL;
+        }
+        panel_size = ((panel->mode.xres * panel->mode.yres) * panel->bpp) / 8;
+        panel_size = ALIGN(panel_size, PAGE_SIZE);
+        fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev,
+                panel_size, &dma, GFP_KERNEL);
+        if (!fb->fb.screen_base) {
+                pr_err("CLCD: unable to map framebuffer\n");
+                return -ENOMEM;
+        }
+        fb->fb.fix.smem_start = dma;
+        fb->fb.fix.smem_len = panel_size;
+        fb->panel = panel;
+        return 0;
+}
+int nspire_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
+{
+        return dma_mmap_writecombine(&fb->dev->dev, vma,
+                fb->fb.screen_base, fb->fb.fix.smem_start,
+                fb->fb.fix.smem_len);
+}
+void nspire_clcd_remove(struct clcd_fb *fb)
+{
+        dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
+                fb->fb.screen_base, fb->fb.fix.smem_start);
+}
diff --git a/arch/arm/mach-nspire/clcd.h b/arch/arm/mach-nspire/clcd.h
new file mode 100644
index 000000000000..8c33d2c18371
--- /dev/null
+++ b/arch/arm/mach-nspire/clcd.h
@@ -0,0 +1,14 @@
+/*
+ *      linux/arch/arm/mach-nspire/clcd.h
+ *
+ *      Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+int nspire_clcd_setup(struct clcd_fb *fb);
+int nspire_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma);
+void nspire_clcd_remove(struct clcd_fb *fb);
diff --git a/arch/arm/mach-nspire/mmio.h b/arch/arm/mach-nspire/mmio.h
new file mode 100644
index 000000000000..8813471af4cf
--- /dev/null
+++ b/arch/arm/mach-nspire/mmio.h
@@ -0,0 +1,20 @@
+/*
+ *      linux/arch/arm/mach-nspire/mmio.h
+ *
+ *      Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+#define NSPIRE_MISC_PHYS_BASE           0x900A0000
+#define NSPIRE_MISC_HWRESET             0x08
+#define NSPIRE_PWR_PHYS_BASE            0x900B0000
+#define NSPIRE_PWR_VIRT_BASE            0xFEEB0000
+#define NSPIRE_PWR_BUS_DISABLE1         0x18
+#define NSPIRE_PWR_BUS_DISABLE2         0x20
+#define NSPIRE_LCD_PHYS_BASE            0xC0000000
diff --git a/arch/arm/mach-nspire/nspire.c b/arch/arm/mach-nspire/nspire.c
new file mode 100644
index 000000000000..99e26092a9f7
--- /dev/null
+++ b/arch/arm/mach-nspire/nspire.c
@@ -0,0 +1,89 @@
+/*
+ *      linux/arch/arm/mach-nspire/nspire.c
+ *
+ *      Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/init.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/arm-vic.h>
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/clcd.h>
+#include <linux/clocksource.h>
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <asm/mach/map.h>
+#include <asm/hardware/timer-sp.h>
+#include "mmio.h"
+#include "clcd.h"
+static const char *nspire_dt_match[] __initconst = {
+        "ti,nspire",
+        "ti,nspire-cx",
+        "ti,nspire-tp",
+        "ti,nspire-clp",
+        NULL,
+};
+static void __init nspire_map_io(void)
+{
+        debug_ll_io_init();
+}
+static struct clcd_board nspire_clcd_data = {
+        .name           = "LCD",
+        .caps           = CLCD_CAP_5551 | CLCD_CAP_565,
+        .check          = clcdfb_check,
+        .decode         = clcdfb_decode,
+        .setup          = nspire_clcd_setup,
+        .mmap           = nspire_clcd_mmap,
+        .remove         = nspire_clcd_remove,
+};
+static struct of_dev_auxdata nspire_auxdata[] __initdata = {
+        OF_DEV_AUXDATA("arm,pl111", NSPIRE_LCD_PHYS_BASE,
+                        NULL, &nspire_clcd_data),
+        { }
+};
+static void __init nspire_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        nspire_auxdata, NULL);
+}
+static void __init nspire_init_time(void)
+{
+        of_clk_init(NULL);
+        clocksource_of_init();
+}
+static void nspire_restart(char mode, const char *cmd)
+{
+        void __iomem *base = ioremap(NSPIRE_MISC_PHYS_BASE, SZ_4K);
+        if (!base)
+                return;
+        writel(2, base + NSPIRE_MISC_HWRESET);
+}
+DT_MACHINE_START(NSPIRE, "TI-NSPIRE")
+        .dt_compat      = nspire_dt_match,
+        .map_io         = nspire_map_io,
+        .init_time      = nspire_init_time,
+        .init_machine   = nspire_init,
+        .restart        = nspire_restart,
+MACHINE_END
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index 222d58c0ae76..3889b6cd211e 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -19,10 +19,6 @@ obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o
 # Power Management
 obj-$(CONFIG_PM) += pm.o sleep.o
-# DSP
-obj-$(CONFIG_OMAP_MBOX_FWK)     += mailbox_mach.o
-mailbox_mach-objs               := mailbox.o
 i2c-omap-$(CONFIG_I2C_OMAP)             := i2c.o
 obj-y                                   += $(i2c-omap-m) $(i2c-omap-y)
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index 0dac3d239e32..fd90cafc2e36 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -41,7 +41,6 @@
 #include <mach/mux.h>
 #include <linux/omap-dma.h>
 #include <mach/tc.h>
-#include <mach/irda.h>
 #include <linux/platform_data/keypad-omap.h>
 #include <mach/flash.h>
@@ -50,7 +49,6 @@
 #include "common.h"
 #include "board-h2.h"
-#include "dma.h"
 /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
 #define OMAP1610_ETHR_START             0x04000300
@@ -276,39 +274,6 @@ static struct platform_device h2_kp_device = {
        .resource       = h2_kp_resources,
 };
-#define H2_IRDA_FIRSEL_GPIO_PIN 17
-static struct omap_irda_config h2_irda_data = {
-        .transceiver_cap        = IR_SIRMODE | IR_MIRMODE | IR_FIRMODE,
-        .rx_channel             = OMAP_DMA_UART3_RX,
-        .tx_channel             = OMAP_DMA_UART3_TX,
-        .dest_start             = UART3_THR,
-        .src_start              = UART3_RHR,
-        .tx_trigger             = 0,
-        .rx_trigger             = 0,
-};
-static struct resource h2_irda_resources[] = {
-        [0] = {
-                .start  = INT_UART3,
-                .end    = INT_UART3,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static u64 irda_dmamask = 0xffffffff;
-static struct platform_device h2_irda_device = {
-        .name           = "omapirda",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &h2_irda_data,
-                .dma_mask       = &irda_dmamask,
-        },
-        .num_resources  = ARRAY_SIZE(h2_irda_resources),
-        .resource       = h2_irda_resources,
-};
 static struct gpio_led h2_gpio_led_pins[] = {
        {
                .name           = "h2:red",
@@ -339,7 +304,6 @@ static struct platform_device *h2_devices[] __initdata = {
        &h2_nor_device,
        &h2_nand_device,
        &h2_smc91x_device,
-        &h2_irda_device,
        &h2_kp_device,
        &h2_gpio_leds,
 };
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index 62a15e289c79..91449c5cb70f 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -234,16 +234,26 @@ static struct i2c_board_info nokia770_i2c_board_info_2[] __initdata = {
        {
                I2C_BOARD_INFO("retu-mfd", 0x01),
        },
+        {
+                I2C_BOARD_INFO("tahvo-mfd", 0x02),
+        },
 };
 static void __init nokia770_cbus_init(void)
 {
        const int retu_irq_gpio = 62;
+        const int tahvo_irq_gpio = 40;
        if (gpio_request_one(retu_irq_gpio, GPIOF_IN, "Retu IRQ"))
                return;
+        if (gpio_request_one(tahvo_irq_gpio, GPIOF_IN, "Tahvo IRQ")) {
+                gpio_free(retu_irq_gpio);
+                return;
+        }
        irq_set_irq_type(gpio_to_irq(retu_irq_gpio), IRQ_TYPE_EDGE_RISING);
+        irq_set_irq_type(gpio_to_irq(tahvo_irq_gpio), IRQ_TYPE_EDGE_RISING);
        nokia770_i2c_board_info_2[0].irq = gpio_to_irq(retu_irq_gpio);
+        nokia770_i2c_board_info_2[1].irq = gpio_to_irq(tahvo_irq_gpio);
        i2c_register_board_info(2, nokia770_i2c_board_info_2,
                                ARRAY_SIZE(nokia770_i2c_board_info_2));
        platform_device_register(&nokia770_cbus_device);
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 845a1a7aef95..3b8e98f4353c 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -38,14 +38,12 @@
 #include <mach/mux.h>
 #include <mach/tc.h>
 #include <linux/omap-dma.h>
-#include <mach/irda.h>
 #include <linux/platform_data/keypad-omap.h>
 #include <mach/hardware.h>
 #include <mach/usb.h>
 #include "common.h"
-#include "dma.h"
 #define PALMTE_USBDETECT_GPIO   0
 #define PALMTE_USB_OR_DC_GPIO   1
@@ -167,40 +165,11 @@ static struct platform_device palmte_backlight_device = {
        },
 };
-static struct omap_irda_config palmte_irda_config = {
-        .transceiver_cap        = IR_SIRMODE,
-        .rx_channel             = OMAP_DMA_UART3_RX,
-        .tx_channel             = OMAP_DMA_UART3_TX,
-        .dest_start             = UART3_THR,
-        .src_start              = UART3_RHR,
-        .tx_trigger             = 0,
-        .rx_trigger             = 0,
-};
-static struct resource palmte_irda_resources[] = {
-        [0]     = {
-                .start  = INT_UART3,
-                .end    = INT_UART3,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device palmte_irda_device = {
-        .name           = "omapirda",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &palmte_irda_config,
-        },
-        .num_resources  = ARRAY_SIZE(palmte_irda_resources),
-        .resource       = palmte_irda_resources,
-};
 static struct platform_device *palmte_devices[] __initdata = {
        &palmte_rom_device,
        &palmte_kp_device,
        &palmte_lcd_device,
        &palmte_backlight_device,
-        &palmte_irda_device,
 };
 static struct omap_usb_config palmte_usb_config __initdata = {
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index 65a4a3e357f2..ca501208825f 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -38,14 +38,12 @@
 #include <mach/mux.h>
 #include <linux/omap-dma.h>
 #include <mach/tc.h>
-#include <mach/irda.h>
 #include <linux/platform_data/keypad-omap.h>
 #include <mach/hardware.h>
 #include <mach/usb.h>
 #include "common.h"
-#include "dma.h"
 #define PALMTT_USBDETECT_GPIO   0
 #define PALMTT_CABLE_GPIO       1
@@ -163,33 +161,6 @@ static struct platform_device palmtt_lcd_device = {
        .name           = "lcd_palmtt",
        .id             = -1,
 };
-static struct omap_irda_config palmtt_irda_config = {
-        .transceiver_cap        = IR_SIRMODE,
-        .rx_channel             = OMAP_DMA_UART3_RX,
-        .tx_channel             = OMAP_DMA_UART3_TX,
-        .dest_start             = UART3_THR,
-        .src_start              = UART3_RHR,
-        .tx_trigger             = 0,
-        .rx_trigger             = 0,
-};
-static struct resource palmtt_irda_resources[] = {
-        [0]     = {
-                .start  = INT_UART3,
-                .end    = INT_UART3,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device palmtt_irda_device = {
-        .name           = "omapirda",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &palmtt_irda_config,
-        },
-        .num_resources  = ARRAY_SIZE(palmtt_irda_resources),
-        .resource       = palmtt_irda_resources,
-};
 static struct platform_device palmtt_spi_device = {
        .name           = "spi_palmtt",
@@ -234,7 +205,6 @@ static struct platform_device *palmtt_devices[] __initdata = {
        &palmtt_flash_device,
        &palmtt_kp_device,
        &palmtt_lcd_device,
-        &palmtt_irda_device,
        &palmtt_spi_device,
        &palmtt_backlight_device,
        &palmtt_led_device,
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index 01c970071fd8..470e12d67360 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -40,14 +40,12 @@
 #include <mach/mux.h>
 #include <linux/omap-dma.h>
 #include <mach/tc.h>
-#include <mach/irda.h>
 #include <linux/platform_data/keypad-omap.h>
 #include <mach/hardware.h>
 #include <mach/usb.h>
 #include "common.h"
-#include "dma.h"
 #define PALMZ71_USBDETECT_GPIO  0
 #define PALMZ71_PENIRQ_GPIO     6
@@ -153,34 +151,6 @@ static struct platform_device palmz71_lcd_device = {
        .id     = -1,
 };
-static struct omap_irda_config palmz71_irda_config = {
-        .transceiver_cap        = IR_SIRMODE,
-        .rx_channel             = OMAP_DMA_UART3_RX,
-        .tx_channel             = OMAP_DMA_UART3_TX,
-        .dest_start             = UART3_THR,
-        .src_start              = UART3_RHR,
-        .tx_trigger             = 0,
-        .rx_trigger             = 0,
-};
-static struct resource palmz71_irda_resources[] = {
-        [0] = {
-                .start  = INT_UART3,
-                .end    = INT_UART3,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device palmz71_irda_device = {
-        .name   = "omapirda",
-        .id     = -1,
-        .dev = {
-                .platform_data = &palmz71_irda_config,
-        },
-        .num_resources  = ARRAY_SIZE(palmz71_irda_resources),
-        .resource       = palmz71_irda_resources,
-};
 static struct platform_device palmz71_spi_device = {
        .name   = "spi_palmz71",
        .id     = -1,
@@ -202,7 +172,6 @@ static struct platform_device *devices[] __initdata = {
        &palmz71_rom_device,
        &palmz71_kp_device,
        &palmz71_lcd_device,
-        &palmz71_irda_device,
        &palmz71_spi_device,
        &palmz71_backlight_device,
 };
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 9732a98f3e06..0a8d3349149c 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -37,7 +37,6 @@
 #include <mach/flash.h>
 #include <mach/mux.h>
 #include <linux/omap-dma.h>
-#include <mach/irda.h>
 #include <mach/tc.h>
 #include <mach/board-sx1.h>
@@ -45,7 +44,6 @@
 #include <mach/usb.h>
 #include "common.h"
-#include "dma.h"
 /* Write to I2C device */
 int sx1_i2c_write_byte(u8 devaddr, u8 regoffset, u8 value)
@@ -228,39 +226,6 @@ static struct platform_device sx1_kp_device = {
        .resource       = sx1_kp_resources,
 };
-/*----------- IRDA -------------------------*/
-static struct omap_irda_config sx1_irda_data = {
-        .transceiver_cap        = IR_SIRMODE,
-        .rx_channel             = OMAP_DMA_UART3_RX,
-        .tx_channel             = OMAP_DMA_UART3_TX,
-        .dest_start             = UART3_THR,
-        .src_start              = UART3_RHR,
-        .tx_trigger             = 0,
-        .rx_trigger             = 0,
-};
-static struct resource sx1_irda_resources[] = {
-        [0] = {
-                .start  = INT_UART3,
-                .end    = INT_UART3,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static u64 irda_dmamask = 0xffffffff;
-static struct platform_device sx1_irda_device = {
-        .name           = "omapirda",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &sx1_irda_data,
-                .dma_mask       = &irda_dmamask,
-        },
-        .num_resources  = ARRAY_SIZE(sx1_irda_resources),
-        .resource       = sx1_irda_resources,
-};
 /*----------- MTD -------------------------*/
 static struct mtd_partition sx1_partitions[] = {
@@ -366,7 +331,6 @@ static struct omap_lcd_config sx1_lcd_config __initdata = {
 static struct platform_device *sx1_devices[] __initdata = {
        &sx1_flash_device,
        &sx1_kp_device,
-        &sx1_irda_device,
 };
 /*-----------------------------------------*/
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index 6c116e1a4b01..4677a9ccb3cb 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -26,6 +26,7 @@
 #include <linux/serial_reg.h>
 #include <linux/smc91x.h>
 #include <linux/export.h>
+#include <linux/reboot.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -215,7 +216,7 @@ void voiceblue_wdt_ping(void)
        gpio_set_value(0, wdt_gpio_state);
 }
-static void voiceblue_restart(char mode, const char *cmd)
+static void voiceblue_restart(enum reboot_mode mode, const char *cmd)
 {
        /*
         * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
diff --git a/arch/arm/mach-omap1/common.h b/arch/arm/mach-omap1/common.h
index 14f7e9920479..abec019a5281 100644
--- a/arch/arm/mach-omap1/common.h
+++ b/arch/arm/mach-omap1/common.h
@@ -28,6 +28,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/i2c-omap.h>
+#include <linux/reboot.h>
 #include <plat/i2c.h>
@@ -70,7 +71,7 @@ static inline int omap_serial_wakeup_init(void)
 void omap1_init_early(void);
 void omap1_init_irq(void);
 void omap1_init_late(void);
-void omap1_restart(char, const char *);
+void omap1_restart(enum reboot_mode, const char *);
 extern void __init omap_check_revision(void);
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index 0af635205e8a..325e6030095e 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -30,7 +30,6 @@
 #include "common.h"
 #include "clock.h"
-#include "dma.h"
 #include "mmc.h"
 #include "sram.h"
@@ -223,16 +222,16 @@ void __init omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
                case 0:
                        base = OMAP1_MMC1_BASE;
                        irq = INT_MMC;
-                        rx_req = OMAP_DMA_MMC_RX;
+                        rx_req = 22;
-                        tx_req = OMAP_DMA_MMC_TX;
+                        tx_req = 21;
                        break;
                case 1:
                        if (!cpu_is_omap16xx())
                                return;
                        base = OMAP1_MMC2_BASE;
                        irq = INT_1610_MMC2;
-                        rx_req = OMAP_DMA_MMC2_RX;
+                        rx_req = 55;
-                        tx_req = OMAP_DMA_MMC2_TX;
+                        tx_req = 54;
                        break;
                default:
                        continue;
diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index a94b3a718d1a..5bb8ce86d54b 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -30,8 +30,6 @@
 #include <mach/irqs.h>
-#include "dma.h"
 #define OMAP1_DMA_BASE                  (0xfffed800)
 #define OMAP1_LOGICAL_DMA_CH_COUNT      17
 #define OMAP1_DMA_STRIDE                0x40
diff --git a/arch/arm/mach-omap1/dma.h b/arch/arm/mach-omap1/dma.h
deleted file mode 100644
index d05909c96715..000000000000
--- a/arch/arm/mach-omap1/dma.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- *  OMAP1 DMA channel definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef __OMAP1_DMA_CHANNEL_H
-#define __OMAP1_DMA_CHANNEL_H
-/* DMA channels for omap1 */
-#define OMAP_DMA_NO_DEVICE              0
-#define OMAP_DMA_MCBSP1_TX              8
-#define OMAP_DMA_MCBSP1_RX              9
-#define OMAP_DMA_MCBSP3_TX              10
-#define OMAP_DMA_MCBSP3_RX              11
-#define OMAP_DMA_MCBSP2_TX              16
-#define OMAP_DMA_MCBSP2_RX              17
-#define OMAP_DMA_UART3_TX               18
-#define OMAP_DMA_UART3_RX               19
-#define OMAP_DMA_CAMERA_IF_RX           20
-#define OMAP_DMA_MMC_TX                 21
-#define OMAP_DMA_MMC_RX                 22
-#define OMAP_DMA_USB_W2FC_RX0           26
-#define OMAP_DMA_USB_W2FC_TX0           29
-/* These are only for 1610 */
-#define OMAP_DMA_MMC2_TX                54
-#define OMAP_DMA_MMC2_RX                55
-#endif /* __OMAP1_DMA_CHANNEL_H */
diff --git a/arch/arm/mach-omap1/include/mach/irda.h b/arch/arm/mach-omap1/include/mach/irda.h
deleted file mode 100644
index 40f60339d1c6..000000000000
--- a/arch/arm/mach-omap1/include/mach/irda.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- *  arch/arm/plat-omap/include/mach/irda.h
- *
- *  Copyright (C) 2005-2006 Komal Shah <komal_shah802003@yahoo.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef ASMARM_ARCH_IRDA_H
-#define ASMARM_ARCH_IRDA_H
-/* board specific transceiver capabilities */
-#define IR_SEL          1       /* Selects IrDA */
-#define IR_SIRMODE      2
-#define IR_FIRMODE      4
-#define IR_MIRMODE      8
-struct omap_irda_config {
-        int transceiver_cap;
-        int (*transceiver_mode)(struct device *dev, int mode);
-        int (*select_irda)(struct device *dev, int state);
-        int rx_channel;
-        int tx_channel;
-        unsigned long dest_start;
-        unsigned long src_start;
-        int tx_trigger;
-        int rx_trigger;
-        int mode;
-};
-#endif
diff --git a/arch/arm/mach-omap1/lcd_dma.c b/arch/arm/mach-omap1/lcd_dma.c
index 77924be37d41..26a2b01c7c4f 100644
--- a/arch/arm/mach-omap1/lcd_dma.c
+++ b/arch/arm/mach-omap1/lcd_dma.c
@@ -32,8 +32,6 @@
 #include <mach/hardware.h>
 #include <mach/lcdc.h>
-#include "dma.h"
 int omap_lcd_dma_running(void)
 {
        /*
diff --git a/arch/arm/mach-omap1/mailbox.c b/arch/arm/mach-omap1/mailbox.c
deleted file mode 100644
index efc8f207f6fc..000000000000
--- a/arch/arm/mach-omap1/mailbox.c
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
- * Mailbox reservation modules for OMAP1
- *
- * Copyright (C) 2006-2009 Nokia Corporation
- * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <plat/mailbox.h>
-#define MAILBOX_ARM2DSP1                0x00
-#define MAILBOX_ARM2DSP1b               0x04
-#define MAILBOX_DSP2ARM1                0x08
-#define MAILBOX_DSP2ARM1b               0x0c
-#define MAILBOX_DSP2ARM2                0x10
-#define MAILBOX_DSP2ARM2b               0x14
-#define MAILBOX_ARM2DSP1_Flag           0x18
-#define MAILBOX_DSP2ARM1_Flag           0x1c
-#define MAILBOX_DSP2ARM2_Flag           0x20
-static void __iomem *mbox_base;
-struct omap_mbox1_fifo {
-        unsigned long cmd;
-        unsigned long data;
-        unsigned long flag;
-};
-struct omap_mbox1_priv {
-        struct omap_mbox1_fifo tx_fifo;
-        struct omap_mbox1_fifo rx_fifo;
-};
-static inline int mbox_read_reg(size_t ofs)
-{
-        return __raw_readw(mbox_base + ofs);
-}
-static inline void mbox_write_reg(u32 val, size_t ofs)
-{
-        __raw_writew(val, mbox_base + ofs);
-}
-/* msg */
-static mbox_msg_t omap1_mbox_fifo_read(struct omap_mbox *mbox)
-{
-        struct omap_mbox1_fifo *fifo =
-                &((struct omap_mbox1_priv *)mbox->priv)->rx_fifo;
-        mbox_msg_t msg;
-        msg = mbox_read_reg(fifo->data);
-        msg |= ((mbox_msg_t) mbox_read_reg(fifo->cmd)) << 16;
-        return msg;
-}
-static void
-omap1_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
-{
-        struct omap_mbox1_fifo *fifo =
-                &((struct omap_mbox1_priv *)mbox->priv)->tx_fifo;
-        mbox_write_reg(msg & 0xffff, fifo->data);
-        mbox_write_reg(msg >> 16, fifo->cmd);
-}
-static int omap1_mbox_fifo_empty(struct omap_mbox *mbox)
-{
-        return 0;
-}
-static int omap1_mbox_fifo_full(struct omap_mbox *mbox)
-{
-        struct omap_mbox1_fifo *fifo =
-                &((struct omap_mbox1_priv *)mbox->priv)->rx_fifo;
-        return mbox_read_reg(fifo->flag);
-}
-/* irq */
-static void
-omap1_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq)
-{
-        if (irq == IRQ_RX)
-                enable_irq(mbox->irq);
-}
-static void
-omap1_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq)
-{
-        if (irq == IRQ_RX)
-                disable_irq(mbox->irq);
-}
-static int
-omap1_mbox_is_irq(struct omap_mbox *mbox, omap_mbox_type_t irq)
-{
-        if (irq == IRQ_TX)
-                return 0;
-        return 1;
-}
-static struct omap_mbox_ops omap1_mbox_ops = {
-        .type           = OMAP_MBOX_TYPE1,
-        .fifo_read      = omap1_mbox_fifo_read,
-        .fifo_write     = omap1_mbox_fifo_write,
-        .fifo_empty     = omap1_mbox_fifo_empty,
-        .fifo_full      = omap1_mbox_fifo_full,
-        .enable_irq     = omap1_mbox_enable_irq,
-        .disable_irq    = omap1_mbox_disable_irq,
-        .is_irq         = omap1_mbox_is_irq,
-};
-/* FIXME: the following struct should be created automatically by the user id */
-/* DSP */
-static struct omap_mbox1_priv omap1_mbox_dsp_priv = {
-        .tx_fifo = {
-                .cmd    = MAILBOX_ARM2DSP1b,
-                .data   = MAILBOX_ARM2DSP1,
-                .flag   = MAILBOX_ARM2DSP1_Flag,
-        },
-        .rx_fifo = {
-                .cmd    = MAILBOX_DSP2ARM1b,
-                .data   = MAILBOX_DSP2ARM1,
-                .flag   = MAILBOX_DSP2ARM1_Flag,
-        },
-};
-static struct omap_mbox mbox_dsp_info = {
-        .name   = "dsp",
-        .ops    = &omap1_mbox_ops,
-        .priv   = &omap1_mbox_dsp_priv,
-};
-static struct omap_mbox *omap1_mboxes[] = { &mbox_dsp_info, NULL };
-static int omap1_mbox_probe(struct platform_device *pdev)
-{
-        struct resource *mem;
-        int ret;
-        struct omap_mbox **list;
-        list = omap1_mboxes;
-        list[0]->irq = platform_get_irq_byname(pdev, "dsp");
-        mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        mbox_base = ioremap(mem->start, resource_size(mem));
-        if (!mbox_base)
-                return -ENOMEM;
-        ret = omap_mbox_register(&pdev->dev, list);
-        if (ret) {
-                iounmap(mbox_base);
-                return ret;
-        }
-        return 0;
-}
-static int omap1_mbox_remove(struct platform_device *pdev)
-{
-        omap_mbox_unregister();
-        iounmap(mbox_base);
-        return 0;
-}
-static struct platform_driver omap1_mbox_driver = {
-        .probe  = omap1_mbox_probe,
-        .remove = omap1_mbox_remove,
-        .driver = {
-                .name   = "omap-mailbox",
-        },
-};
-static int __init omap1_mbox_init(void)
-{
-        return platform_driver_register(&omap1_mbox_driver);
-}
-static void __exit omap1_mbox_exit(void)
-{
-        platform_driver_unregister(&omap1_mbox_driver);
-}
-module_init(omap1_mbox_init);
-module_exit(omap1_mbox_exit);
-MODULE_LICENSE("GPL v2");
-MODULE_DESCRIPTION("omap mailbox: omap1 architecture specific functions");
-MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>");
-MODULE_ALIAS("platform:omap1-mailbox");
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index b0d4723c9a90..8ed67f8d1762 100644
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -27,7 +27,6 @@
 #include <mach/irqs.h>
 #include "iomap.h"
-#include "dma.h"
 #define DPS_RSTCT2_PER_EN       (1 << 0)
 #define DSP_RSTCT2_WD_PER_EN    (1 << 1)
@@ -114,12 +113,12 @@ struct resource omap7xx_mcbsp_res[][6] = {
                },
                {
                        .name  = "rx",
-                        .start = OMAP_DMA_MCBSP1_RX,
+                        .start = 9,
                        .flags = IORESOURCE_DMA,
                },
                {
                        .name  = "tx",
-                        .start = OMAP_DMA_MCBSP1_TX,
+                        .start = 8,
                        .flags = IORESOURCE_DMA,
                },
        },
@@ -141,12 +140,12 @@ struct resource omap7xx_mcbsp_res[][6] = {
                },
                {
                        .name  = "rx",
-                        .start = OMAP_DMA_MCBSP3_RX,
+                        .start = 11,
                        .flags = IORESOURCE_DMA,
                },
                {
                        .name  = "tx",
-                        .start = OMAP_DMA_MCBSP3_TX,
+                        .start = 10,
                        .flags = IORESOURCE_DMA,
                },
        },
@@ -191,12 +190,12 @@ struct resource omap15xx_mcbsp_res[][6] = {
                },
                {
                        .name  = "rx",
-                        .start = OMAP_DMA_MCBSP1_RX,
+                        .start = 9,
                        .flags = IORESOURCE_DMA,
                },
                {
                        .name  = "tx",
-                        .start = OMAP_DMA_MCBSP1_TX,
+                        .start = 8,
                        .flags = IORESOURCE_DMA,
                },
        },
@@ -218,12 +217,12 @@ struct resource omap15xx_mcbsp_res[][6] = {
                },
                {
                        .name  = "rx",
-                        .start = OMAP_DMA_MCBSP2_RX,
+                        .start = 17,
                        .flags = IORESOURCE_DMA,
                },
                {
                        .name  = "tx",
-                        .start = OMAP_DMA_MCBSP2_TX,
+                        .start = 16,
                        .flags = IORESOURCE_DMA,
                },
        },
@@ -245,12 +244,12 @@ struct resource omap15xx_mcbsp_res[][6] = {
                },
                {
                        .name  = "rx",
-                        .start = OMAP_DMA_MCBSP3_RX,
+                        .start = 11,
                        .flags = IORESOURCE_DMA,
                },
                {
                        .name  = "tx",
-                        .start = OMAP_DMA_MCBSP3_TX,
+                        .start = 10,
                        .flags = IORESOURCE_DMA,
                },
        },
@@ -298,12 +297,12 @@ struct resource omap16xx_mcbsp_res[][6] = {
                },
                {
                        .name  = "rx",
-                        .start = OMAP_DMA_MCBSP1_RX,
+                        .start = 9,
                        .flags = IORESOURCE_DMA,
                },
                {
                        .name  = "tx",
-                        .start = OMAP_DMA_MCBSP1_TX,
+                        .start = 8,
                        .flags = IORESOURCE_DMA,
                },
        },
@@ -325,12 +324,12 @@ struct resource omap16xx_mcbsp_res[][6] = {
                },
                {
                        .name  = "rx",
-                        .start = OMAP_DMA_MCBSP2_RX,
+                        .start = 17,
                        .flags = IORESOURCE_DMA,
                },
                {
                        .name  = "tx",
-                        .start = OMAP_DMA_MCBSP2_TX,
+                        .start = 16,
                        .flags = IORESOURCE_DMA,
                },
        },
@@ -352,12 +351,12 @@ struct resource omap16xx_mcbsp_res[][6] = {
                },
                {
                        .name  = "rx",
-                        .start = OMAP_DMA_MCBSP3_RX,
+                        .start = 11,
                        .flags = IORESOURCE_DMA,
                },
                {
                        .name  = "tx",
-                        .start = OMAP_DMA_MCBSP3_TX,
+                        .start = 10,
                        .flags = IORESOURCE_DMA,
                },
        },
diff --git a/arch/arm/mach-omap1/reset.c b/arch/arm/mach-omap1/reset.c
index 5eebd7e889d0..72bf4bf4a702 100644
--- a/arch/arm/mach-omap1/reset.c
+++ b/arch/arm/mach-omap1/reset.c
@@ -3,6 +3,7 @@
 */
 #include <linux/kernel.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 #include <mach/hardware.h>
@@ -22,7 +23,7 @@
 #define OMAP_EXTWARM_RST_SRC_ID_SHIFT                   5
-void omap1_restart(char mode, const char *cmd)
+void omap1_restart(enum reboot_mode mode, const char *cmd)
 {
        /*
         * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
index 726ec23d29c7..80603d2fef77 100644
--- a/arch/arm/mach-omap1/time.c
+++ b/arch/arm/mach-omap1/time.c
@@ -43,9 +43,9 @@
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
 #include <linux/io.h>
+#include <linux/sched_clock.h>
 #include <asm/irq.h>
-#include <asm/sched_clock.h>
 #include <mach/hardware.h>
 #include <asm/mach/irq.h>
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index f49cd51e162a..3eed0006d189 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -1,61 +1,10 @@
 config ARCH_OMAP
        bool
-config ARCH_OMAP2PLUS
-        bool "TI OMAP2/3/4/5 SoCs with device tree support" if (ARCH_MULTI_V6 || ARCH_MULTI_V7)
-        select ARCH_HAS_CPUFREQ
-        select ARCH_HAS_HOLES_MEMORYMODEL
-        select ARCH_OMAP
-        select ARCH_REQUIRE_GPIOLIB
-        select CLKDEV_LOOKUP
-        select CLKSRC_MMIO
-        select GENERIC_CLOCKEVENTS
-        select GENERIC_IRQ_CHIP
-        select HAVE_CLK
-        select OMAP_DM_TIMER
-        select PINCTRL
-        select PROC_DEVICETREE if PROC_FS
-        select SOC_BUS
-        select SPARSE_IRQ
-        select USE_OF
-        help
-          Systems based on OMAP2, OMAP3, OMAP4 or OMAP5
-if ARCH_OMAP2PLUS
-menu "TI OMAP2/3/4 Specific Features"
-config ARCH_OMAP2PLUS_TYPICAL
-        bool "Typical OMAP configuration"
-        default y
-        select AEABI
-        select HIGHMEM
-        select I2C
-        select I2C_OMAP
-        select MENELAUS if ARCH_OMAP2
-        select NEON if ARCH_OMAP3 || ARCH_OMAP4 || SOC_OMAP5
-        select PM_RUNTIME
-        select REGULATOR
-        select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
-        select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4
-        select VFP
-        help
-          Compile a kernel suitable for booting most boards
-config SOC_HAS_OMAP2_SDRC
-        bool "OMAP2 SDRAM Controller support"
-config SOC_HAS_REALTIME_COUNTER
-        bool "Real time free running counter"
-        depends on SOC_OMAP5
-        default y
 config ARCH_OMAP2
        bool "TI OMAP2"
-        depends on ARCH_OMAP2PLUS
        depends on ARCH_MULTI_V6
-        default y
+        select ARCH_OMAP2PLUS
        select CPU_V6
        select MULTI_IRQ_HANDLER
        select SOC_HAS_OMAP2_SDRC
@@ -63,9 +12,8 @@ config ARCH_OMAP2
 config ARCH_OMAP3
        bool "TI OMAP3"
-        depends on ARCH_OMAP2PLUS
        depends on ARCH_MULTI_V7
-        default y
+        select ARCH_OMAP2PLUS
        select ARCH_HAS_OPP
        select ARM_CPU_SUSPEND if PM
        select CPU_V7
@@ -79,9 +27,8 @@ config ARCH_OMAP3
 config ARCH_OMAP4
        bool "TI OMAP4"
-        default y
-        depends on ARCH_OMAP2PLUS
        depends on ARCH_MULTI_V7
+        select ARCH_OMAP2PLUS
        select ARCH_HAS_OPP
        select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
        select ARM_CPU_SUSPEND if PM
@@ -106,12 +53,87 @@ config ARCH_OMAP4
 config SOC_OMAP5
        bool "TI OMAP5"
        depends on ARCH_MULTI_V7
+        select ARCH_OMAP2PLUS
        select ARM_CPU_SUSPEND if PM
        select ARM_GIC
        select CPU_V7
+        select HAVE_ARM_SCU if SMP
+        select HAVE_ARM_TWD if LOCAL_TIMERS
        select HAVE_SMP
        select COMMON_CLK
        select HAVE_ARM_ARCH_TIMER
+        select ARM_ERRATA_798181 if SMP
+config SOC_AM33XX
+        bool "AM33XX support"
+        depends on ARCH_MULTI_V7
+        select ARCH_OMAP2PLUS
+        select ARM_CPU_SUSPEND if PM
+        select CPU_V7
+        select MULTI_IRQ_HANDLER
+        select COMMON_CLK
+config SOC_AM43XX
+        bool "TI AM43x"
+        depends on ARCH_MULTI_V7
+        select CPU_V7
+        select ARCH_OMAP2PLUS
+        select MULTI_IRQ_HANDLER
+        select ARM_GIC
+        select COMMON_CLK
+        select MACH_OMAP_GENERIC
+config ARCH_OMAP2PLUS
+        bool
+        select ARCH_HAS_BANDGAP
+        select ARCH_HAS_CPUFREQ
+        select ARCH_HAS_HOLES_MEMORYMODEL
+        select ARCH_OMAP
+        select ARCH_REQUIRE_GPIOLIB
+        select CLKDEV_LOOKUP
+        select CLKSRC_MMIO
+        select GENERIC_CLOCKEVENTS
+        select GENERIC_IRQ_CHIP
+        select HAVE_CLK
+        select OMAP_DM_TIMER
+        select PINCTRL
+        select PROC_DEVICETREE if PROC_FS
+        select SOC_BUS
+        select SPARSE_IRQ
+        select TI_PRIV_EDMA
+        select USE_OF
+        help
+          Systems based on OMAP2, OMAP3, OMAP4 or OMAP5
+if ARCH_OMAP2PLUS
+menu "TI OMAP2/3/4 Specific Features"
+config ARCH_OMAP2PLUS_TYPICAL
+        bool "Typical OMAP configuration"
+        default y
+        select AEABI
+        select HIGHMEM
+        select I2C
+        select I2C_OMAP
+        select MENELAUS if ARCH_OMAP2
+        select NEON if ARCH_OMAP3 || ARCH_OMAP4 || SOC_OMAP5
+        select PM_RUNTIME
+        select REGULATOR
+        select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
+        select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4
+        select VFP
+        help
+          Compile a kernel suitable for booting most boards
+config SOC_HAS_OMAP2_SDRC
+        bool "OMAP2 SDRAM Controller support"
+config SOC_HAS_REALTIME_COUNTER
+        bool "Real time free running counter"
+        depends on SOC_OMAP5
+        default y
 comment "OMAP Core Type"
        depends on ARCH_OMAP2
@@ -140,15 +162,6 @@ config SOC_TI81XX
        depends on ARCH_OMAP3
        default y
-config SOC_AM33XX
-        bool "AM33XX support"
-        depends on ARCH_MULTI_V7
-        default y
-        select ARM_CPU_SUSPEND if PM
-        select CPU_V7
-        select MULTI_IRQ_HANDLER
-        select COMMON_CLK
 config OMAP_PACKAGE_ZAF
       bool
@@ -167,12 +180,6 @@ config OMAP_PACKAGE_CUS
 config OMAP_PACKAGE_CBP
       bool
-config OMAP_PACKAGE_CBL
-       bool
-config OMAP_PACKAGE_CBS
-       bool
 comment "OMAP Board Type"
        depends on ARCH_OMAP2PLUS
@@ -378,22 +385,6 @@ config MACH_TI8148EVM
        depends on SOC_TI81XX
        default y
-config MACH_OMAP_4430SDP
-        bool "OMAP 4430 SDP board"
-        default y
-        depends on ARCH_OMAP4
-        select OMAP_PACKAGE_CBL
-        select OMAP_PACKAGE_CBS
-        select REGULATOR_FIXED_VOLTAGE if REGULATOR
-config MACH_OMAP4_PANDA
-        bool "OMAP4 Panda Board"
-        default y
-        depends on ARCH_OMAP4
-        select OMAP_PACKAGE_CBL
-        select OMAP_PACKAGE_CBS
-        select REGULATOR_FIXED_VOLTAGE if REGULATOR
 config OMAP3_EMU
        bool "OMAP3 debugging peripherals"
        depends on ARCH_OMAP3
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 55a9d6777683..d4f671547c37 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
 obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
 obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common)
 obj-$(CONFIG_SOC_OMAP5)  += prm44xx.o $(hwmod-common) $(secure-common)
+obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common)
 ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
 obj-y += mcbsp.o
@@ -34,10 +35,10 @@ obj-$(CONFIG_SOC_HAS_OMAP2_SDRC)	+= sdrc.o
 smp-$(CONFIG_SMP)                       += omap-smp.o omap-headsmp.o
 smp-$(CONFIG_HOTPLUG_CPU)               += omap-hotplug.o
-omap-4-5-common                         =  omap4-common.o omap-wakeupgen.o \
+omap-4-5-common                         =  omap4-common.o omap-wakeupgen.o
-                                           sleep44xx.o
+obj-$(CONFIG_ARCH_OMAP4)                += $(omap-4-5-common) $(smp-y) sleep44xx.o
-obj-$(CONFIG_ARCH_OMAP4)                += $(omap-4-5-common) $(smp-y)
+obj-$(CONFIG_SOC_OMAP5)                 += $(omap-4-5-common) $(smp-y) sleep44xx.o
-obj-$(CONFIG_SOC_OMAP5)                 += $(omap-4-5-common) $(smp-y)
+obj-$(CONFIG_SOC_AM43XX)                += $(omap-4-5-common)
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_omap-headsmp.o                   :=-Wa,-march=armv7-a$(plus_sec)
@@ -58,12 +59,13 @@ obj-$(CONFIG_SOC_OMAP2420)		+= omap2-restart.o
 obj-$(CONFIG_SOC_OMAP2430)              += omap2-restart.o
 obj-$(CONFIG_SOC_AM33XX)                += am33xx-restart.o
 obj-$(CONFIG_ARCH_OMAP3)                += omap3-restart.o
+obj-$(CONFIG_ARCH_OMAP4)                += omap4-restart.o
+obj-$(CONFIG_SOC_OMAP5)                 += omap4-restart.o
 # Pin multiplexing
 obj-$(CONFIG_SOC_OMAP2420)              += mux2420.o
 obj-$(CONFIG_SOC_OMAP2430)              += mux2430.o
 obj-$(CONFIG_ARCH_OMAP3)                += mux34xx.o
-obj-$(CONFIG_ARCH_OMAP4)                += mux44xx.o
 # SMS/SDRC
 obj-$(CONFIG_ARCH_OMAP2)                += sdrc2xxx.o
@@ -93,10 +95,6 @@ obj-$(CONFIG_POWER_AVS_OMAP_CLASS3)    += smartreflex-class3.o
 AFLAGS_sleep24xx.o                      :=-Wa,-march=armv6
 AFLAGS_sleep34xx.o                      :=-Wa,-march=armv7-a$(plus_sec)
-ifeq ($(CONFIG_PM_VERBOSE),y)
-CFLAGS_pm_bus.o                         += -DDEBUG
-endif
 endif
 ifeq ($(CONFIG_CPU_IDLE),y)
@@ -110,6 +108,7 @@ obj-$(CONFIG_ARCH_OMAP2)		+= prm2xxx_3xxx.o prm2xxx.o cm2xxx.o
 obj-$(CONFIG_ARCH_OMAP3)                += prm2xxx_3xxx.o prm3xxx.o cm3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)                += vc3xxx_data.o vp3xxx_data.o
 obj-$(CONFIG_SOC_AM33XX)                += prm33xx.o cm33xx.o
+obj-$(CONFIG_SOC_AM43XX)                += prm33xx.o cm33xx.o
 omap-prcm-4-5-common                    =  cminst44xx.o cm44xx.o prm44xx.o \
                                           prcm_mpu44xx.o prminst44xx.o \
                                           vc44xx_data.o vp44xx_data.o
@@ -125,8 +124,9 @@ obj-$(CONFIG_ARCH_OMAP3)		+= voltagedomains3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP4)                += $(voltagedomain-common)
 obj-$(CONFIG_ARCH_OMAP4)                += voltagedomains44xx_data.o
 obj-$(CONFIG_SOC_AM33XX)                += $(voltagedomain-common)
-obj-$(CONFIG_SOC_AM33XX)                += voltagedomains33xx_data.o
+obj-$(CONFIG_SOC_AM43XX)                += $(voltagedomain-common)
 obj-$(CONFIG_SOC_OMAP5)                 += $(voltagedomain-common)
+obj-$(CONFIG_SOC_OMAP5)                += voltagedomains54xx_data.o
 # OMAP powerdomain framework
 powerdomain-common                      += powerdomain.o powerdomain-common.o
@@ -140,7 +140,9 @@ obj-$(CONFIG_ARCH_OMAP4)		+= $(powerdomain-common)
 obj-$(CONFIG_ARCH_OMAP4)                += powerdomains44xx_data.o
 obj-$(CONFIG_SOC_AM33XX)                += $(powerdomain-common)
 obj-$(CONFIG_SOC_AM33XX)                += powerdomains33xx_data.o
+obj-$(CONFIG_SOC_AM43XX)                += $(powerdomain-common)
 obj-$(CONFIG_SOC_OMAP5)                 += $(powerdomain-common)
+obj-$(CONFIG_SOC_OMAP5)                 += powerdomains54xx_data.o
 # PRCM clockdomain control
 clockdomain-common                      += clockdomain.o
@@ -155,7 +157,9 @@ obj-$(CONFIG_ARCH_OMAP4)		+= $(clockdomain-common)
 obj-$(CONFIG_ARCH_OMAP4)                += clockdomains44xx_data.o
 obj-$(CONFIG_SOC_AM33XX)                += $(clockdomain-common)
 obj-$(CONFIG_SOC_AM33XX)                += clockdomains33xx_data.o
+obj-$(CONFIG_SOC_AM43XX)                += $(clockdomain-common)
 obj-$(CONFIG_SOC_OMAP5)                 += $(clockdomain-common)
+obj-$(CONFIG_SOC_OMAP5)                 += clockdomains54xx_data.o
 # Clock framework
 obj-$(CONFIG_ARCH_OMAP2)                += $(clock-common) clock2xxx.o
@@ -198,14 +202,12 @@ obj-$(CONFIG_ARCH_OMAP3)		+= omap_hwmod_2xxx_3xxx_interconnect_data.o
 obj-$(CONFIG_ARCH_OMAP3)                += omap_hwmod_3xxx_data.o
 obj-$(CONFIG_SOC_AM33XX)                += omap_hwmod_33xx_data.o
 obj-$(CONFIG_ARCH_OMAP4)                += omap_hwmod_44xx_data.o
+obj-$(CONFIG_SOC_OMAP5)                 += omap_hwmod_54xx_data.o
 # EMU peripherals
 obj-$(CONFIG_OMAP3_EMU)                 += emu.o
 obj-$(CONFIG_HW_PERF_EVENTS)            += pmu.o
-obj-$(CONFIG_OMAP_MBOX_FWK)             += mailbox_mach.o
-mailbox_mach-objs                       := mailbox.o
 iommu-$(CONFIG_OMAP_IOMMU)              := omap-iommu.o
 obj-y                                   += $(iommu-m) $(iommu-y)
@@ -251,8 +253,6 @@ obj-$(CONFIG_MACH_CM_T35)		+= board-cm-t35.o
 obj-$(CONFIG_MACH_CM_T3517)             += board-cm-t3517.o
 obj-$(CONFIG_MACH_IGEP0020)             += board-igep0020.o
 obj-$(CONFIG_MACH_TOUCHBOOK)            += board-omap3touchbook.o
-obj-$(CONFIG_MACH_OMAP_4430SDP)         += board-4430sdp.o
-obj-$(CONFIG_MACH_OMAP4_PANDA)          += board-omap4panda.o
 obj-$(CONFIG_MACH_OMAP3517EVM)          += board-am3517evm.o
diff --git a/arch/arm/mach-omap2/am33xx-restart.c b/arch/arm/mach-omap2/am33xx-restart.c
index 88e4fa8af031..1eae96212315 100644
--- a/arch/arm/mach-omap2/am33xx-restart.c
+++ b/arch/arm/mach-omap2/am33xx-restart.c
@@ -6,6 +6,7 @@
 * published by the Free Software Foundation.
 */
 #include <linux/kernel.h>
+#include <linux/reboot.h>
 #include "common.h"
 #include "prm-regbits-33xx.h"
@@ -19,7 +20,7 @@
 * Resets the SoC.  For @cmd, see the 'reboot' syscall in
 * kernel/sys.c.  No return value.
 */
-void am33xx_restart(char mode, const char *cmd)
+void am33xx_restart(enum reboot_mode mode, const char *cmd)
 {
        /* TODO: Handle mode and cmd if necessary */
diff --git a/arch/arm/mach-omap2/am33xx.h b/arch/arm/mach-omap2/am33xx.h
index 43296c1af9ee..5eef093e6738 100644
--- a/arch/arm/mach-omap2/am33xx.h
+++ b/arch/arm/mach-omap2/am33xx.h
@@ -21,6 +21,7 @@
 #define AM33XX_SCM_BASE         0x44E10000
 #define AM33XX_CTRL_BASE        AM33XX_SCM_BASE
 #define AM33XX_PRCM_BASE        0x44E00000
+#define AM43XX_PRCM_BASE        0x44DF0000
 #define AM33XX_TAP_BASE         (AM33XX_CTRL_BASE + 0x3FC)
 #endif /* __ASM_ARCH_AM33XX_H */
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
deleted file mode 100644
index 56a9a4f855c7..000000000000
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ /dev/null
@@ -1,765 +0,0 @@
-/*
- * Board support file for OMAP4430 SDP.
- *
- * Copyright (C) 2009 Texas Instruments
- *
- * Author: Santosh Shilimkar <santosh.shilimkar@ti.com>
- *
- * Based on mach-omap2/board-3430sdp.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/usb/otg.h>
-#include <linux/spi/spi.h>
-#include <linux/i2c/twl.h>
-#include <linux/mfd/twl6040.h>
-#include <linux/gpio_keys.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-#include <linux/pwm.h>
-#include <linux/leds.h>
-#include <linux/leds_pwm.h>
-#include <linux/pwm_backlight.h>
-#include <linux/irqchip/arm-gic.h>
-#include <linux/platform_data/omap4-keypad.h>
-#include <linux/usb/musb.h>
-#include <linux/usb/phy.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include "common.h"
-#include "omap4-keypad.h"
-#include <linux/wl12xx.h>
-#include <linux/platform_data/omap-abe-twl6040.h>
-#include "soc.h"
-#include "mux.h"
-#include "mmc.h"
-#include "hsmmc.h"
-#include "control.h"
-#include "common-board-devices.h"
-#include "dss-common.h"
-#define ETH_KS8851_IRQ                  34
-#define ETH_KS8851_POWER_ON             48
-#define ETH_KS8851_QUART                138
-#define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO        184
-#define OMAP4_SFH7741_ENABLE_GPIO               188
-#define GPIO_WIFI_PMENA         54
-#define GPIO_WIFI_IRQ           53
-static const int sdp4430_keymap[] = {
-        KEY(0, 0, KEY_E),
-        KEY(0, 1, KEY_R),
-        KEY(0, 2, KEY_T),
-        KEY(0, 3, KEY_HOME),
-        KEY(0, 4, KEY_F5),
-        KEY(0, 5, KEY_UNKNOWN),
-        KEY(0, 6, KEY_I),
-        KEY(0, 7, KEY_LEFTSHIFT),
-        KEY(1, 0, KEY_D),
-        KEY(1, 1, KEY_F),
-        KEY(1, 2, KEY_G),
-        KEY(1, 3, KEY_SEND),
-        KEY(1, 4, KEY_F6),
-        KEY(1, 5, KEY_UNKNOWN),
-        KEY(1, 6, KEY_K),
-        KEY(1, 7, KEY_ENTER),
-        KEY(2, 0, KEY_X),
-        KEY(2, 1, KEY_C),
-        KEY(2, 2, KEY_V),
-        KEY(2, 3, KEY_END),
-        KEY(2, 4, KEY_F7),
-        KEY(2, 5, KEY_UNKNOWN),
-        KEY(2, 6, KEY_DOT),
-        KEY(2, 7, KEY_CAPSLOCK),
-        KEY(3, 0, KEY_Z),
-        KEY(3, 1, KEY_KPPLUS),
-        KEY(3, 2, KEY_B),
-        KEY(3, 3, KEY_F1),
-        KEY(3, 4, KEY_F8),
-        KEY(3, 5, KEY_UNKNOWN),
-        KEY(3, 6, KEY_O),
-        KEY(3, 7, KEY_SPACE),
-        KEY(4, 0, KEY_W),
-        KEY(4, 1, KEY_Y),
-        KEY(4, 2, KEY_U),
-        KEY(4, 3, KEY_F2),
-        KEY(4, 4, KEY_VOLUMEUP),
-        KEY(4, 5, KEY_UNKNOWN),
-        KEY(4, 6, KEY_L),
-        KEY(4, 7, KEY_LEFT),
-        KEY(5, 0, KEY_S),
-        KEY(5, 1, KEY_H),
-        KEY(5, 2, KEY_J),
-        KEY(5, 3, KEY_F3),
-        KEY(5, 4, KEY_F9),
-        KEY(5, 5, KEY_VOLUMEDOWN),
-        KEY(5, 6, KEY_M),
-        KEY(5, 7, KEY_RIGHT),
-        KEY(6, 0, KEY_Q),
-        KEY(6, 1, KEY_A),
-        KEY(6, 2, KEY_N),
-        KEY(6, 3, KEY_BACK),
-        KEY(6, 4, KEY_BACKSPACE),
-        KEY(6, 5, KEY_UNKNOWN),
-        KEY(6, 6, KEY_P),
-        KEY(6, 7, KEY_UP),
-        KEY(7, 0, KEY_PROG1),
-        KEY(7, 1, KEY_PROG2),
-        KEY(7, 2, KEY_PROG3),
-        KEY(7, 3, KEY_PROG4),
-        KEY(7, 4, KEY_F4),
-        KEY(7, 5, KEY_UNKNOWN),
-        KEY(7, 6, KEY_OK),
-        KEY(7, 7, KEY_DOWN),
-};
-static struct omap_device_pad keypad_pads[] = {
-        {       .name   = "kpd_col1.kpd_col1",
-                .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
-        },
-        {       .name   = "kpd_col1.kpd_col1",
-                .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
-        },
-        {       .name   = "kpd_col2.kpd_col2",
-                .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
-        },
-        {       .name   = "kpd_col3.kpd_col3",
-                .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
-        },
-        {       .name   = "kpd_col4.kpd_col4",
-                .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
-        },
-        {       .name   = "kpd_col5.kpd_col5",
-                .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
-        },
-        {       .name   = "gpmc_a23.kpd_col7",
-                .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
-        },
-        {       .name   = "gpmc_a22.kpd_col6",
-                .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
-        },
-        {       .name   = "kpd_row0.kpd_row0",
-                .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
-                        OMAP_MUX_MODE1 | OMAP_INPUT_EN,
-        },
-        {       .name   = "kpd_row1.kpd_row1",
-                .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
-                        OMAP_MUX_MODE1 | OMAP_INPUT_EN,
-        },
-        {       .name   = "kpd_row2.kpd_row2",
-                .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
-                        OMAP_MUX_MODE1 | OMAP_INPUT_EN,
-        },
-        {       .name   = "kpd_row3.kpd_row3",
-                .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
-                        OMAP_MUX_MODE1 | OMAP_INPUT_EN,
-        },
-        {       .name   = "kpd_row4.kpd_row4",
-                .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
-                        OMAP_MUX_MODE1 | OMAP_INPUT_EN,
-        },
-        {       .name   = "kpd_row5.kpd_row5",
-                .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
-                        OMAP_MUX_MODE1 | OMAP_INPUT_EN,
-        },
-        {       .name   = "gpmc_a18.kpd_row6",
-                .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
-                        OMAP_MUX_MODE1 | OMAP_INPUT_EN,
-        },
-        {       .name   = "gpmc_a19.kpd_row7",
-                .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
-                        OMAP_MUX_MODE1 | OMAP_INPUT_EN,
-        },
-};
-static struct matrix_keymap_data sdp4430_keymap_data = {
-        .keymap                 = sdp4430_keymap,
-        .keymap_size            = ARRAY_SIZE(sdp4430_keymap),
-};
-static struct omap4_keypad_platform_data sdp4430_keypad_data = {
-        .keymap_data            = &sdp4430_keymap_data,
-        .rows                   = 8,
-        .cols                   = 8,
-};
-static struct omap_board_data keypad_data = {
-        .id                     = 1,
-        .pads                   = keypad_pads,
-        .pads_cnt               = ARRAY_SIZE(keypad_pads),
-};
-static struct gpio_led sdp4430_gpio_leds[] = {
-        {
-                .name   = "omap4:green:debug0",
-                .gpio   = 61,
-        },
-        {
-                .name   = "omap4:green:debug1",
-                .gpio   = 30,
-        },
-        {
-                .name   = "omap4:green:debug2",
-                .gpio   = 7,
-        },
-        {
-                .name   = "omap4:green:debug3",
-                .gpio   = 8,
-        },
-        {
-                .name   = "omap4:green:debug4",
-                .gpio   = 50,
-        },
-        {
-                .name   = "omap4:blue:user",
-                .gpio   = 169,
-        },
-        {
-                .name   = "omap4:red:user",
-                .gpio   = 170,
-        },
-        {
-                .name   = "omap4:green:user",
-                .gpio   = 139,
-        },
-};
-static struct gpio_keys_button sdp4430_gpio_keys[] = {
-        {
-                .desc                   = "Proximity Sensor",
-                .type                   = EV_SW,
-                .code                   = SW_FRONT_PROXIMITY,
-                .gpio                   = OMAP4_SFH7741_SENSOR_OUTPUT_GPIO,
-                .active_low             = 0,
-        }
-};
-static struct gpio_led_platform_data sdp4430_led_data = {
-        .leds   = sdp4430_gpio_leds,
-        .num_leds       = ARRAY_SIZE(sdp4430_gpio_leds),
-};
-static struct pwm_lookup sdp4430_pwm_lookup[] = {
-        PWM_LOOKUP("twl-pwm", 0, "leds_pwm", "omap4::keypad"),
-        PWM_LOOKUP("twl-pwm", 1, "pwm-backlight", NULL),
-        PWM_LOOKUP("twl-pwmled", 0, "leds_pwm", "omap4:green:chrg"),
-};
-static struct led_pwm sdp4430_pwm_leds[] = {
-        {
-                .name           = "omap4::keypad",
-                .max_brightness = 127,
-                .pwm_period_ns  = 7812500,
-        },
-        {
-                .name           = "omap4:green:chrg",
-                .max_brightness = 255,
-                .pwm_period_ns  = 7812500,
-        },
-};
-static struct led_pwm_platform_data sdp4430_pwm_data = {
-        .num_leds       = ARRAY_SIZE(sdp4430_pwm_leds),
-        .leds           = sdp4430_pwm_leds,
-};
-static struct platform_device sdp4430_leds_pwm = {
-        .name   = "leds_pwm",
-        .id     = -1,
-        .dev    = {
-                .platform_data = &sdp4430_pwm_data,
-        },
-};
-/* Dummy regulator for pwm-backlight driver */
-static struct regulator_consumer_supply backlight_supply =
-        REGULATOR_SUPPLY("enable", "pwm-backlight");
-static struct platform_pwm_backlight_data sdp4430_backlight_data = {
-        .max_brightness = 127,
-        .dft_brightness = 127,
-        .pwm_period_ns = 7812500,
-};
-static struct platform_device sdp4430_backlight_pwm = {
-        .name   = "pwm-backlight",
-        .id     = -1,
-        .dev    = {
-                .platform_data = &sdp4430_backlight_data,
-        },
-};
-static int omap_prox_activate(struct device *dev)
-{
-        gpio_set_value(OMAP4_SFH7741_ENABLE_GPIO , 1);
-        return 0;
-}
-static void omap_prox_deactivate(struct device *dev)
-{
-        gpio_set_value(OMAP4_SFH7741_ENABLE_GPIO , 0);
-}
-static struct gpio_keys_platform_data sdp4430_gpio_keys_data = {
-        .buttons        = sdp4430_gpio_keys,
-        .nbuttons       = ARRAY_SIZE(sdp4430_gpio_keys),
-        .enable         = omap_prox_activate,
-        .disable        = omap_prox_deactivate,
-};
-static struct platform_device sdp4430_gpio_keys_device = {
-        .name   = "gpio-keys",
-        .id     = -1,
-        .dev    = {
-                .platform_data  = &sdp4430_gpio_keys_data,
-        },
-};
-static struct platform_device sdp4430_leds_gpio = {
-        .name   = "leds-gpio",
-        .id     = -1,
-        .dev    = {
-                .platform_data = &sdp4430_led_data,
-        },
-};
-static struct spi_board_info sdp4430_spi_board_info[] __initdata = {
-        {
-                .modalias               = "ks8851",
-                .bus_num                = 1,
-                .chip_select            = 0,
-                .max_speed_hz           = 24000000,
-                /*
-                 * .irq is set to gpio_to_irq(ETH_KS8851_IRQ)
-                 * in omap_4430sdp_init
-                 */
-        },
-};
-static struct gpio sdp4430_eth_gpios[] __initdata = {
-        { ETH_KS8851_POWER_ON,  GPIOF_OUT_INIT_HIGH,    "eth_power"     },
-        { ETH_KS8851_QUART,     GPIOF_OUT_INIT_HIGH,    "quart"         },
-        { ETH_KS8851_IRQ,       GPIOF_IN,               "eth_irq"       },
-};
-static int __init omap_ethernet_init(void)
-{
-        int status;
-        /* Request of GPIO lines */
-        status = gpio_request_array(sdp4430_eth_gpios,
-                                    ARRAY_SIZE(sdp4430_eth_gpios));
-        if (status)
-                pr_err("Cannot request ETH GPIOs\n");
-        return status;
-}
-static struct regulator_consumer_supply sdp4430_vbat_supply[] = {
-        REGULATOR_SUPPLY("vddvibl", "twl6040-vibra"),
-        REGULATOR_SUPPLY("vddvibr", "twl6040-vibra"),
-};
-static struct regulator_init_data sdp4430_vbat_data = {
-        .constraints = {
-                .always_on      = 1,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(sdp4430_vbat_supply),
-        .consumer_supplies      = sdp4430_vbat_supply,
-};
-static struct fixed_voltage_config sdp4430_vbat_pdata = {
-        .supply_name    = "VBAT",
-        .microvolts     = 3750000,
-        .init_data      = &sdp4430_vbat_data,
-        .gpio           = -EINVAL,
-};
-static struct platform_device sdp4430_vbat = {
-        .name           = "reg-fixed-voltage",
-        .id             = -1,
-        .dev = {
-                .platform_data = &sdp4430_vbat_pdata,
-        },
-};
-static struct platform_device sdp4430_dmic_codec = {
-        .name   = "dmic-codec",
-        .id     = -1,
-};
-static struct platform_device sdp4430_hdmi_audio_codec = {
-        .name   = "hdmi-audio-codec",
-        .id     = -1,
-};
-static struct omap_abe_twl6040_data sdp4430_abe_audio_data = {
-        .card_name = "SDP4430",
-        .has_hs         = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
-        .has_hf         = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
-        .has_ep         = 1,
-        .has_aux        = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
-        .has_vibra      = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
-        .has_dmic       = 1,
-        .has_hsmic      = 1,
-        .has_mainmic    = 1,
-        .has_submic     = 1,
-        .has_afm        = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
-        .jack_detection = 1,
-        /* MCLK input is 38.4MHz */
-        .mclk_freq      = 38400000,
-};
-static struct platform_device sdp4430_abe_audio = {
-        .name           = "omap-abe-twl6040",
-        .id             = -1,
-        .dev = {
-                .platform_data = &sdp4430_abe_audio_data,
-        },
-};
-static struct platform_device *sdp4430_devices[] __initdata = {
-        &sdp4430_gpio_keys_device,
-        &sdp4430_leds_gpio,
-        &sdp4430_leds_pwm,
-        &sdp4430_backlight_pwm,
-        &sdp4430_vbat,
-        &sdp4430_dmic_codec,
-        &sdp4430_abe_audio,
-        &sdp4430_hdmi_audio_codec,
-};
-static struct omap_musb_board_data musb_board_data = {
-        .interface_type         = MUSB_INTERFACE_UTMI,
-        .mode                   = MUSB_OTG,
-        .power                  = 100,
-};
-static struct omap2_hsmmc_info mmc[] = {
-        {
-                .mmc            = 2,
-                .caps           =  MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
-                .gpio_cd        = -EINVAL,
-                .gpio_wp        = -EINVAL,
-                .nonremovable   = true,
-                .ocr_mask       = MMC_VDD_29_30,
-                .no_off_init    = true,
-        },
-        {
-                .mmc            = 1,
-                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
-                .gpio_cd        = -EINVAL,
-                .gpio_wp        = -EINVAL,
-        },
-        {
-                .mmc            = 5,
-                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
-                .pm_caps        = MMC_PM_KEEP_POWER,
-                .gpio_cd        = -EINVAL,
-                .gpio_wp        = -EINVAL,
-                .ocr_mask       = MMC_VDD_165_195,
-                .nonremovable   = true,
-        },
-        {}      /* Terminator */
-};
-static struct regulator_consumer_supply sdp4430_vaux_supply[] = {
-        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
-};
-static struct regulator_consumer_supply omap4_sdp4430_vmmc5_supply = {
-        .supply = "vmmc",
-        .dev_name = "omap_hsmmc.4",
-};
-static struct regulator_init_data sdp4430_vmmc5 = {
-        .constraints = {
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies = 1,
-        .consumer_supplies = &omap4_sdp4430_vmmc5_supply,
-};
-static struct fixed_voltage_config sdp4430_vwlan = {
-        .supply_name            = "vwl1271",
-        .microvolts             = 1800000, /* 1.8V */
-        .gpio                   = GPIO_WIFI_PMENA,
-        .startup_delay          = 70000, /* 70msec */
-        .enable_high            = 1,
-        .enabled_at_boot        = 0,
-        .init_data              = &sdp4430_vmmc5,
-};
-static struct platform_device omap_vwlan_device = {
-        .name           = "reg-fixed-voltage",
-        .id             = 1,
-        .dev = {
-                .platform_data = &sdp4430_vwlan,
-        },
-};
-static struct regulator_init_data sdp4430_vaux1 = {
-        .constraints = {
-                .min_uV                 = 1000000,
-                .max_uV                 = 3000000,
-                .apply_uV               = true,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask  = REGULATOR_CHANGE_VOLTAGE
-                                        | REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(sdp4430_vaux_supply),
-        .consumer_supplies      = sdp4430_vaux_supply,
-};
-static struct regulator_init_data sdp4430_vusim = {
-        .constraints = {
-                .min_uV                 = 1200000,
-                .max_uV                 = 2900000,
-                .apply_uV               = true,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask  = REGULATOR_CHANGE_VOLTAGE
-                                        | REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-};
-static struct twl6040_codec_data twl6040_codec = {
-        /* single-step ramp for headset and handsfree */
-        .hs_left_step   = 0x0f,
-        .hs_right_step  = 0x0f,
-        .hf_left_step   = 0x1d,
-        .hf_right_step  = 0x1d,
-};
-static struct twl6040_vibra_data twl6040_vibra = {
-        .vibldrv_res = 8,
-        .vibrdrv_res = 3,
-        .viblmotor_res = 10,
-        .vibrmotor_res = 10,
-        .vddvibl_uV = 0,        /* fixed volt supply - VBAT */
-        .vddvibr_uV = 0,        /* fixed volt supply - VBAT */
-};
-static struct twl6040_platform_data twl6040_data = {
-        .codec          = &twl6040_codec,
-        .vibra          = &twl6040_vibra,
-        .audpwron_gpio  = 127,
-};
-static struct i2c_board_info __initdata sdp4430_i2c_1_boardinfo[] = {
-        {
-                I2C_BOARD_INFO("twl6040", 0x4b),
-                .irq = 119 + OMAP44XX_IRQ_GIC_START,
-                .platform_data = &twl6040_data,
-        },
-};
-static struct twl4030_platform_data sdp4430_twldata = {
-        /* Regulators */
-        .vusim          = &sdp4430_vusim,
-        .vaux1          = &sdp4430_vaux1,
-};
-static struct i2c_board_info __initdata sdp4430_i2c_3_boardinfo[] = {
-        {
-                I2C_BOARD_INFO("tmp105", 0x48),
-        },
-        {
-                I2C_BOARD_INFO("bh1780", 0x29),
-        },
-};
-static struct i2c_board_info __initdata sdp4430_i2c_4_boardinfo[] = {
-        {
-                I2C_BOARD_INFO("hmc5843", 0x1e),
-        },
-};
-static int __init omap4_i2c_init(void)
-{
-        omap4_pmic_get_config(&sdp4430_twldata, TWL_COMMON_PDATA_USB,
-                        TWL_COMMON_REGULATOR_VDAC |
-                        TWL_COMMON_REGULATOR_VAUX2 |
-                        TWL_COMMON_REGULATOR_VAUX3 |
-                        TWL_COMMON_REGULATOR_VMMC |
-                        TWL_COMMON_REGULATOR_VPP |
-                        TWL_COMMON_REGULATOR_VANA |
-                        TWL_COMMON_REGULATOR_VCXIO |
-                        TWL_COMMON_REGULATOR_VUSB |
-                        TWL_COMMON_REGULATOR_CLK32KG |
-                        TWL_COMMON_REGULATOR_V1V8 |
-                        TWL_COMMON_REGULATOR_V2V1);
-        omap4_pmic_init("twl6030", &sdp4430_twldata, sdp4430_i2c_1_boardinfo,
-                        ARRAY_SIZE(sdp4430_i2c_1_boardinfo));
-        omap_register_i2c_bus(2, 400, NULL, 0);
-        omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo,
-                                ARRAY_SIZE(sdp4430_i2c_3_boardinfo));
-        omap_register_i2c_bus(4, 400, sdp4430_i2c_4_boardinfo,
-                                ARRAY_SIZE(sdp4430_i2c_4_boardinfo));
-        return 0;
-}
-static void __init omap_sfh7741prox_init(void)
-{
-        int error;
-        error = gpio_request_one(OMAP4_SFH7741_ENABLE_GPIO,
-                                 GPIOF_OUT_INIT_LOW, "sfh7741");
-        if (error < 0)
-                pr_err("%s:failed to request GPIO %d, error %d\n",
-                        __func__, OMAP4_SFH7741_ENABLE_GPIO, error);
-}
-#ifdef CONFIG_OMAP_MUX
-static struct omap_board_mux board_mux[] __initdata = {
-        OMAP4_MUX(USBB2_ULPITLL_CLK, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
-        /* NIRQ2 for twl6040 */
-        OMAP4_MUX(SYS_NIRQ2, OMAP_MUX_MODE0 |
-                  OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE),
-        /* GPIO_127 for twl6040 */
-        OMAP4_MUX(HDQ_SIO, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT),
-        /* McPDM */
-        OMAP4_MUX(ABE_PDM_UL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
-        OMAP4_MUX(ABE_PDM_DL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
-        OMAP4_MUX(ABE_PDM_FRAME, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
-        OMAP4_MUX(ABE_PDM_LB_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
-        OMAP4_MUX(ABE_CLKS, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
-        /* DMIC */
-        OMAP4_MUX(ABE_DMIC_CLK1, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
-        OMAP4_MUX(ABE_DMIC_DIN1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP4_MUX(ABE_DMIC_DIN2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP4_MUX(ABE_DMIC_DIN3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        /* McBSP1 */
-        OMAP4_MUX(ABE_MCBSP1_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP4_MUX(ABE_MCBSP1_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
-        OMAP4_MUX(ABE_MCBSP1_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT |
-                  OMAP_PULL_ENA),
-        OMAP4_MUX(ABE_MCBSP1_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        /* McBSP2 */
-        OMAP4_MUX(ABE_MCBSP2_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP4_MUX(ABE_MCBSP2_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
-        OMAP4_MUX(ABE_MCBSP2_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT |
-                  OMAP_PULL_ENA),
-        OMAP4_MUX(ABE_MCBSP2_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        { .reg_offset = OMAP_MUX_TERMINATOR },
-};
-#else
-#define board_mux       NULL
- #endif
-static void __init omap4_sdp4430_wifi_mux_init(void)
-{
-        omap_mux_init_gpio(GPIO_WIFI_IRQ, OMAP_PIN_INPUT |
-                                OMAP_PIN_OFF_WAKEUPENABLE);
-        omap_mux_init_gpio(GPIO_WIFI_PMENA, OMAP_PIN_OUTPUT);
-        omap_mux_init_signal("sdmmc5_cmd.sdmmc5_cmd",
-                                OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP);
-        omap_mux_init_signal("sdmmc5_clk.sdmmc5_clk",
-                                OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP);
-        omap_mux_init_signal("sdmmc5_dat0.sdmmc5_dat0",
-                                OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP);
-        omap_mux_init_signal("sdmmc5_dat1.sdmmc5_dat1",
-                                OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP);
-        omap_mux_init_signal("sdmmc5_dat2.sdmmc5_dat2",
-                                OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP);
-        omap_mux_init_signal("sdmmc5_dat3.sdmmc5_dat3",
-                                OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP);
-}
-static struct wl12xx_platform_data omap4_sdp4430_wlan_data __initdata = {
-        .board_ref_clock = WL12XX_REFCLOCK_26,
-        .board_tcxo_clock = WL12XX_TCXOCLOCK_26,
-};
-static void __init omap4_sdp4430_wifi_init(void)
-{
-        int ret;
-        omap4_sdp4430_wifi_mux_init();
-        omap4_sdp4430_wlan_data.irq = gpio_to_irq(GPIO_WIFI_IRQ);
-        ret = wl12xx_set_platform_data(&omap4_sdp4430_wlan_data);
-        if (ret)
-                pr_err("Error setting wl12xx data: %d\n", ret);
-        ret = platform_device_register(&omap_vwlan_device);
-        if (ret)
-                pr_err("Error registering wl12xx device: %d\n", ret);
-}
-static void __init omap_4430sdp_init(void)
-{
-        int status;
-        int package = OMAP_PACKAGE_CBS;
-        if (omap_rev() == OMAP4430_REV_ES1_0)
-                package = OMAP_PACKAGE_CBL;
-        omap4_mux_init(board_mux, NULL, package);
-        omap4_i2c_init();
-        omap_sfh7741prox_init();
-        regulator_register_always_on(0, "backlight-enable",
-                                     &backlight_supply, 1, 0);
-        platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
-        omap_serial_init();
-        omap_sdrc_init(NULL, NULL);
-        omap4_sdp4430_wifi_init();
-        omap4_twl6030_hsmmc_init(mmc);
-        usb_bind_phy("musb-hdrc.2.auto", 0, "omap-usb2.3.auto");
-        usb_musb_init(&musb_board_data);
-        status = omap_ethernet_init();
-        if (status) {
-                pr_err("Ethernet initialization failed: %d\n", status);
-        } else {
-                sdp4430_spi_board_info[0].irq = gpio_to_irq(ETH_KS8851_IRQ);
-                spi_register_board_info(sdp4430_spi_board_info,
-                                ARRAY_SIZE(sdp4430_spi_board_info));
-        }
-        pwm_add_table(sdp4430_pwm_lookup, ARRAY_SIZE(sdp4430_pwm_lookup));
-        status = omap4_keyboard_init(&sdp4430_keypad_data, &keypad_data);
-        if (status)
-                pr_err("Keypad initialization failed: %d\n", status);
-        omap_4430sdp_display_init();
-}
-MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
-        /* Maintainer: Santosh Shilimkar - Texas Instruments Inc */
-        .atag_offset    = 0x100,
-        .smp            = smp_ops(omap4_smp_ops),
-        .reserve        = omap_reserve,
-        .map_io         = omap4_map_io,
-        .init_early     = omap4430_init_early,
-        .init_irq       = gic_init_irq,
-        .init_machine   = omap_4430sdp_init,
-        .init_late      = omap4430_init_late,
-        .init_time      = omap4_local_timer_init,
-        .restart        = omap44xx_restart,
-MACHINE_END
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index ee6218c74807..d4622ed26252 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -293,7 +293,8 @@ static struct regulator_consumer_supply cm_t35_vsim_supply[] = {
 static struct regulator_consumer_supply cm_t35_vio_supplies[] = {
        REGULATOR_SUPPLY("vcc", "spi1.0"),
        REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
-        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dpi.0"),
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"),
 };
 /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 576420544178..f1d91ba5d1ac 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -222,6 +222,7 @@ static struct twl4030_gpio_platform_data devkit8000_gpio_data = {
 static struct regulator_consumer_supply devkit8000_vpll1_supplies[] = {
        REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dpi.0"),
        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"),
 };
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index c33adea0247c..fc20a61f6b2a 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -112,6 +112,9 @@ struct gpmc_timings nand_default_timings[1] = {
                .cs_rd_off = 36,
                .cs_wr_off = 36,
+                .we_on = 6,
+                .oe_on = 6,
                .adv_on = 6,
                .adv_rd_off = 24,
                .adv_wr_off = 36,
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 88aa6b1835c3..be5d005ebad2 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -15,6 +15,7 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/irqdomain.h>
+#include <linux/clk.h>
 #include <asm/mach/arch.h>
@@ -35,6 +36,21 @@ static struct of_device_id omap_dt_match_table[] __initdata = {
        { }
 };
+/*
+ * Create alias for USB host PHY clock.
+ * Remove this when clock phandle can be provided via DT
+ */
+static void __init legacy_init_ehci_clk(char *clkname)
+{
+        int ret;
+        ret = clk_add_alias("main_clk", NULL, clkname, NULL);
+        if (ret) {
+                pr_err("%s:Failed to add main_clk alias to %s :%d\n",
+                                                __func__, clkname, ret);
+        }
+}
 static void __init omap_generic_init(void)
 {
        omap_sdrc_init(NULL, NULL);
@@ -45,10 +61,15 @@ static void __init omap_generic_init(void)
         * HACK: call display setup code for selected boards to enable omapdss.
         * This will be removed when omapdss supports DT.
         */
-        if (of_machine_is_compatible("ti,omap4-panda"))
+        if (of_machine_is_compatible("ti,omap4-panda")) {
                omap4_panda_display_init_of();
+                legacy_init_ehci_clk("auxclk3_ck");
+        }
        else if (of_machine_is_compatible("ti,omap4-sdp"))
                omap_4430sdp_display_init_of();
+        else if (of_machine_is_compatible("ti,omap5-uevm"))
+                legacy_init_ehci_clk("auxclk1_ck");
 }
 #ifdef CONFIG_SOC_OMAP2420
@@ -185,3 +206,19 @@ DT_MACHINE_START(OMAP5_DT, "Generic OMAP5 (Flattened Device Tree)")
        .restart        = omap44xx_restart,
 MACHINE_END
 #endif
+#ifdef CONFIG_SOC_AM43XX
+static const char *am43_boards_compat[] __initdata = {
+        "ti,am43",
+        NULL,
+};
+DT_MACHINE_START(AM43_DT, "Generic AM43 (Flattened Device Tree)")
+        .map_io         = am33xx_map_io,
+        .init_early     = am43xx_init_early,
+        .init_irq       = omap_gic_of_init,
+        .init_machine   = omap_generic_init,
+        .init_time      = omap3_sync32k_timer_init,
+        .dt_compat      = am43_boards_compat,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index b54562d1235e..87e65dde8e13 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -553,6 +553,37 @@ static struct usbhs_omap_platform_data igep3_usbhs_bdata __initdata = {
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
+        /* Display Sub System */
+        OMAP3_MUX(DSS_PCLK, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_HSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_VSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_ACBIAS, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA8, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA9, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA10, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA11, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA12, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA13, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA14, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA15, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA16, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA17, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA20, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        /* TFP410 PanelBus DVI Transmitte (GPIO_170) */
+        OMAP3_MUX(HDQ_SIO, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
        /* SMSC9221 LAN Controller ETH IRQ (GPIO_176) */
        OMAP3_MUX(MCSPI1_CS2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
        { .reg_offset = OMAP_MUX_TERMINATOR },
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index d0d17bc58d9b..62e4f701b63b 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -272,7 +272,8 @@ static struct regulator_init_data ldp_vaux1 = {
 static struct regulator_consumer_supply ldp_vpll2_supplies[] = {
        REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
-        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dpi.0"),
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"),
 };
 static struct regulator_init_data ldp_vpll2 = {
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index f76d0de7b406..8c026269baca 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -174,6 +174,7 @@ static struct panel_sharp_ls037v7dw01_data omap3_evm_lcd_data = {
        .ud_gpio = OMAP3EVM_LCD_PANEL_UD,
 };
+#ifdef CONFIG_BROKEN
 static void __init omap3_evm_display_init(void)
 {
        int r;
@@ -193,6 +194,7 @@ static void __init omap3_evm_display_init(void)
        else
                gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
 }
+#endif
 static struct omap_dss_device omap3_evm_lcd_device = {
        .name                   = "lcd",
@@ -715,7 +717,9 @@ static void __init omap3_evm_init(void)
        omap_ads7846_init(1, OMAP3_EVM_TS_GPIO, 310, NULL);
        omap3evm_init_smsc911x();
+#ifdef CONFIG_BROKEN
        omap3_evm_display_init();
+#endif
        omap3_evm_wl12xx_init();
        omap_twl4030_audio_init("omap3evm", NULL);
 }
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 28133d5b4fed..b1547a0edfcd 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -343,6 +343,7 @@ static struct regulator_consumer_supply pandora_vmmc3_supply[] = {
 static struct regulator_consumer_supply pandora_vdds_supplies[] = {
        REGULATOR_SUPPLY("vdds_sdi", "omapdss"),
        REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dpi.0"),
        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"),
 };
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
deleted file mode 100644
index 1e2c75eee912..000000000000
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ /dev/null
@@ -1,455 +0,0 @@
-/*
- * Board support file for OMAP4430 based PandaBoard.
- *
- * Copyright (C) 2010 Texas Instruments
- *
- * Author: David Anders <x0132446@ti.com>
- *
- * Based on mach-omap2/board-4430sdp.c
- *
- * Author: Santosh Shilimkar <santosh.shilimkar@ti.com>
- *
- * Based on mach-omap2/board-3430sdp.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/leds.h>
-#include <linux/gpio.h>
-#include <linux/usb/otg.h>
-#include <linux/i2c/twl.h>
-#include <linux/mfd/twl6040.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-#include <linux/ti_wilink_st.h>
-#include <linux/usb/musb.h>
-#include <linux/usb/phy.h>
-#include <linux/usb/nop-usb-xceiv.h>
-#include <linux/wl12xx.h>
-#include <linux/irqchip/arm-gic.h>
-#include <linux/platform_data/omap-abe-twl6040.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include "common.h"
-#include "soc.h"
-#include "mmc.h"
-#include "hsmmc.h"
-#include "control.h"
-#include "mux.h"
-#include "common-board-devices.h"
-#include "dss-common.h"
-#define GPIO_HUB_POWER          1
-#define GPIO_HUB_NRESET         62
-#define GPIO_WIFI_PMENA         43
-#define GPIO_WIFI_IRQ           53
-/* wl127x BT, FM, GPS connectivity chip */
-static struct ti_st_plat_data wilink_platform_data = {
-        .nshutdown_gpio = 46,
-        .dev_name       = "/dev/ttyO1",
-        .flow_cntrl     = 1,
-        .baud_rate      = 3000000,
-        .chip_enable    = NULL,
-        .suspend        = NULL,
-        .resume         = NULL,
-};
-static struct platform_device wl1271_device = {
-        .name   = "kim",
-        .id     = -1,
-        .dev    = {
-                .platform_data  = &wilink_platform_data,
-        },
-};
-static struct gpio_led gpio_leds[] = {
-        {
-                .name                   = "pandaboard::status1",
-                .default_trigger        = "heartbeat",
-                .gpio                   = 7,
-        },
-        {
-                .name                   = "pandaboard::status2",
-                .default_trigger        = "mmc0",
-                .gpio                   = 8,
-        },
-};
-static struct gpio_led_platform_data gpio_led_info = {
-        .leds           = gpio_leds,
-        .num_leds       = ARRAY_SIZE(gpio_leds),
-};
-static struct platform_device leds_gpio = {
-        .name   = "leds-gpio",
-        .id     = -1,
-        .dev    = {
-                .platform_data  = &gpio_led_info,
-        },
-};
-static struct omap_abe_twl6040_data panda_abe_audio_data = {
-        /* Audio out */
-        .has_hs         = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
-        /* HandsFree through expansion connector */
-        .has_hf         = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
-        /* PandaBoard: FM TX, PandaBoardES: can be connected to audio out */
-        .has_aux        = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
-        /* PandaBoard: FM RX, PandaBoardES: audio in */
-        .has_afm        = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
-        /* No jack detection. */
-        .jack_detection = 0,
-        /* MCLK input is 38.4MHz */
-        .mclk_freq      = 38400000,
-};
-static struct platform_device panda_abe_audio = {
-        .name           = "omap-abe-twl6040",
-        .id             = -1,
-        .dev = {
-                .platform_data = &panda_abe_audio_data,
-        },
-};
-static struct platform_device panda_hdmi_audio_codec = {
-        .name   = "hdmi-audio-codec",
-        .id     = -1,
-};
-static struct platform_device btwilink_device = {
-        .name   = "btwilink",
-        .id     = -1,
-};
-/* PHY device on HS USB Port 1 i.e. nop_usb_xceiv.1 */
-static struct nop_usb_xceiv_platform_data hsusb1_phy_data = {
-        /* FREF_CLK3 provides the 19.2 MHz reference clock to the PHY */
-        .clk_rate = 19200000,
-};
-static struct usbhs_phy_data phy_data[] __initdata = {
-        {
-                .port = 1,
-                .reset_gpio = GPIO_HUB_NRESET,
-                .vcc_gpio = GPIO_HUB_POWER,
-                .vcc_polarity = 1,
-                .platform_data = &hsusb1_phy_data,
-        },
-};
-static struct platform_device *panda_devices[] __initdata = {
-        &leds_gpio,
-        &wl1271_device,
-        &panda_abe_audio,
-        &panda_hdmi_audio_codec,
-        &btwilink_device,
-};
-static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
-        .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
-};
-static void __init omap4_ehci_init(void)
-{
-        int ret;
-        /* FREF_CLK3 provides the 19.2 MHz reference clock to the PHY */
-        ret = clk_add_alias("main_clk", "nop_usb_xceiv.1", "auxclk3_ck", NULL);
-        if (ret)
-                pr_err("Failed to add main_clk alias to auxclk3_ck\n");
-        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
-        usbhs_init(&usbhs_bdata);
-}
-static struct omap_musb_board_data musb_board_data = {
-        .interface_type         = MUSB_INTERFACE_UTMI,
-        .mode                   = MUSB_OTG,
-        .power                  = 100,
-};
-static struct omap2_hsmmc_info mmc[] = {
-        {
-                .mmc            = 1,
-                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
-                .gpio_wp        = -EINVAL,
-                .gpio_cd        = -EINVAL,
-        },
-        {
-                .name           = "wl1271",
-                .mmc            = 5,
-                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
-                .gpio_wp        = -EINVAL,
-                .gpio_cd        = -EINVAL,
-                .ocr_mask       = MMC_VDD_165_195,
-                .nonremovable   = true,
-        },
-        {}      /* Terminator */
-};
-static struct regulator_consumer_supply omap4_panda_vmmc5_supply[] = {
-        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.4"),
-};
-static struct regulator_init_data panda_vmmc5 = {
-        .constraints = {
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies = ARRAY_SIZE(omap4_panda_vmmc5_supply),
-        .consumer_supplies = omap4_panda_vmmc5_supply,
-};
-static struct fixed_voltage_config panda_vwlan = {
-        .supply_name = "vwl1271",
-        .microvolts = 1800000, /* 1.8V */
-        .gpio = GPIO_WIFI_PMENA,
-        .startup_delay = 70000, /* 70msec */
-        .enable_high = 1,
-        .enabled_at_boot = 0,
-        .init_data = &panda_vmmc5,
-};
-static struct platform_device omap_vwlan_device = {
-        .name           = "reg-fixed-voltage",
-        .id             = 1,
-        .dev = {
-                .platform_data = &panda_vwlan,
-        },
-};
-static struct wl12xx_platform_data omap_panda_wlan_data  __initdata = {
-        .board_ref_clock = WL12XX_REFCLOCK_38, /* 38.4 MHz */
-};
-static struct twl6040_codec_data twl6040_codec = {
-        /* single-step ramp for headset and handsfree */
-        .hs_left_step   = 0x0f,
-        .hs_right_step  = 0x0f,
-        .hf_left_step   = 0x1d,
-        .hf_right_step  = 0x1d,
-};
-static struct twl6040_platform_data twl6040_data = {
-        .codec          = &twl6040_codec,
-        .audpwron_gpio  = 127,
-};
-static struct i2c_board_info __initdata panda_i2c_1_boardinfo[] = {
-        {
-                I2C_BOARD_INFO("twl6040", 0x4b),
-                .irq = 119 + OMAP44XX_IRQ_GIC_START,
-                .platform_data = &twl6040_data,
-        },
-};
-/* Panda board uses the common PMIC configuration */
-static struct twl4030_platform_data omap4_panda_twldata;
-/*
- * Display monitor features are burnt in their EEPROM as EDID data. The EEPROM
- * is connected as I2C slave device, and can be accessed at address 0x50
- */
-static struct i2c_board_info __initdata panda_i2c_eeprom[] = {
-        {
-                I2C_BOARD_INFO("eeprom", 0x50),
-        },
-};
-static int __init omap4_panda_i2c_init(void)
-{
-        omap4_pmic_get_config(&omap4_panda_twldata, TWL_COMMON_PDATA_USB,
-                        TWL_COMMON_REGULATOR_VDAC |
-                        TWL_COMMON_REGULATOR_VAUX2 |
-                        TWL_COMMON_REGULATOR_VAUX3 |
-                        TWL_COMMON_REGULATOR_VMMC |
-                        TWL_COMMON_REGULATOR_VPP |
-                        TWL_COMMON_REGULATOR_VANA |
-                        TWL_COMMON_REGULATOR_VCXIO |
-                        TWL_COMMON_REGULATOR_VUSB |
-                        TWL_COMMON_REGULATOR_CLK32KG |
-                        TWL_COMMON_REGULATOR_V1V8 |
-                        TWL_COMMON_REGULATOR_V2V1);
-        omap4_pmic_init("twl6030", &omap4_panda_twldata, panda_i2c_1_boardinfo,
-                        ARRAY_SIZE(panda_i2c_1_boardinfo));
-        omap_register_i2c_bus(2, 400, NULL, 0);
-        /*
-         * Bus 3 is attached to the DVI port where devices like the pico DLP
-         * projector don't work reliably with 400kHz
-         */
-        omap_register_i2c_bus(3, 100, panda_i2c_eeprom,
-                                        ARRAY_SIZE(panda_i2c_eeprom));
-        omap_register_i2c_bus(4, 400, NULL, 0);
-        return 0;
-}
-#ifdef CONFIG_OMAP_MUX
-static struct omap_board_mux board_mux[] __initdata = {
-        /* WLAN IRQ - GPIO 53 */
-        OMAP4_MUX(GPMC_NCS3, OMAP_MUX_MODE3 | OMAP_PIN_INPUT),
-        /* WLAN POWER ENABLE - GPIO 43 */
-        OMAP4_MUX(GPMC_A19, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT),
-        /* WLAN SDIO: MMC5 CMD */
-        OMAP4_MUX(SDMMC5_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
-        /* WLAN SDIO: MMC5 CLK */
-        OMAP4_MUX(SDMMC5_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
-        /* WLAN SDIO: MMC5 DAT[0-3] */
-        OMAP4_MUX(SDMMC5_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
-        OMAP4_MUX(SDMMC5_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
-        OMAP4_MUX(SDMMC5_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
-        OMAP4_MUX(SDMMC5_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
-        /* gpio 0 - TFP410 PD */
-        OMAP4_MUX(KPD_COL1, OMAP_PIN_OUTPUT | OMAP_MUX_MODE3),
-        /* dispc2_data23 */
-        OMAP4_MUX(USBB2_ULPITLL_STP, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data22 */
-        OMAP4_MUX(USBB2_ULPITLL_DIR, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data21 */
-        OMAP4_MUX(USBB2_ULPITLL_NXT, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data20 */
-        OMAP4_MUX(USBB2_ULPITLL_DAT0, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data19 */
-        OMAP4_MUX(USBB2_ULPITLL_DAT1, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data18 */
-        OMAP4_MUX(USBB2_ULPITLL_DAT2, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data15 */
-        OMAP4_MUX(USBB2_ULPITLL_DAT3, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data14 */
-        OMAP4_MUX(USBB2_ULPITLL_DAT4, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data13 */
-        OMAP4_MUX(USBB2_ULPITLL_DAT5, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data12 */
-        OMAP4_MUX(USBB2_ULPITLL_DAT6, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data11 */
-        OMAP4_MUX(USBB2_ULPITLL_DAT7, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data10 */
-        OMAP4_MUX(DPM_EMU3, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data9 */
-        OMAP4_MUX(DPM_EMU4, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data16 */
-        OMAP4_MUX(DPM_EMU5, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data17 */
-        OMAP4_MUX(DPM_EMU6, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_hsync */
-        OMAP4_MUX(DPM_EMU7, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_pclk */
-        OMAP4_MUX(DPM_EMU8, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_vsync */
-        OMAP4_MUX(DPM_EMU9, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_de */
-        OMAP4_MUX(DPM_EMU10, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data8 */
-        OMAP4_MUX(DPM_EMU11, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data7 */
-        OMAP4_MUX(DPM_EMU12, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data6 */
-        OMAP4_MUX(DPM_EMU13, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data5 */
-        OMAP4_MUX(DPM_EMU14, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data4 */
-        OMAP4_MUX(DPM_EMU15, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data3 */
-        OMAP4_MUX(DPM_EMU16, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data2 */
-        OMAP4_MUX(DPM_EMU17, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data1 */
-        OMAP4_MUX(DPM_EMU18, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data0 */
-        OMAP4_MUX(DPM_EMU19, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* NIRQ2 for twl6040 */
-        OMAP4_MUX(SYS_NIRQ2, OMAP_MUX_MODE0 |
-                  OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE),
-        /* GPIO_127 for twl6040 */
-        OMAP4_MUX(HDQ_SIO, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT),
-        /* McPDM */
-        OMAP4_MUX(ABE_PDM_UL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
-        OMAP4_MUX(ABE_PDM_DL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
-        OMAP4_MUX(ABE_PDM_FRAME, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
-        OMAP4_MUX(ABE_PDM_LB_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
-        OMAP4_MUX(ABE_CLKS, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
-        /* McBSP1 */
-        OMAP4_MUX(ABE_MCBSP1_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP4_MUX(ABE_MCBSP1_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
-        OMAP4_MUX(ABE_MCBSP1_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT |
-                  OMAP_PULL_ENA),
-        OMAP4_MUX(ABE_MCBSP1_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        /* UART2 - BT/FM/GPS shared transport */
-        OMAP4_MUX(UART2_CTS,    OMAP_PIN_INPUT  | OMAP_MUX_MODE0),
-        OMAP4_MUX(UART2_RTS,    OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-        OMAP4_MUX(UART2_RX,     OMAP_PIN_INPUT  | OMAP_MUX_MODE0),
-        OMAP4_MUX(UART2_TX,     OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-        { .reg_offset = OMAP_MUX_TERMINATOR },
-};
-#else
-#define board_mux       NULL
-#endif
-static void omap4_panda_init_rev(void)
-{
-        if (cpu_is_omap443x()) {
-                /* PandaBoard 4430 */
-                /* ASoC audio configuration */
-                panda_abe_audio_data.card_name = "PandaBoard";
-                panda_abe_audio_data.has_hsmic = 1;
-        } else {
-                /* PandaBoard ES */
-                /* ASoC audio configuration */
-                panda_abe_audio_data.card_name = "PandaBoardES";
-        }
-}
-static void __init omap4_panda_init(void)
-{
-        int package = OMAP_PACKAGE_CBS;
-        int ret;
-        if (omap_rev() == OMAP4430_REV_ES1_0)
-                package = OMAP_PACKAGE_CBL;
-        omap4_mux_init(board_mux, NULL, package);
-        omap_panda_wlan_data.irq = gpio_to_irq(GPIO_WIFI_IRQ);
-        ret = wl12xx_set_platform_data(&omap_panda_wlan_data);
-        if (ret)
-                pr_err("error setting wl12xx data: %d\n", ret);
-        omap4_panda_init_rev();
-        omap4_panda_i2c_init();
-        platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
-        platform_device_register(&omap_vwlan_device);
-        omap_serial_init();
-        omap_sdrc_init(NULL, NULL);
-        omap4_twl6030_hsmmc_init(mmc);
-        omap4_ehci_init();
-        usb_bind_phy("musb-hdrc.2.auto", 0, "omap-usb2.3.auto");
-        usb_musb_init(&musb_board_data);
-        omap4_panda_display_init();
-}
-MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
-        /* Maintainer: David Anders - Texas Instruments Inc */
-        .atag_offset    = 0x100,
-        .smp            = smp_ops(omap4_smp_ops),
-        .reserve        = omap_reserve,
-        .map_io         = omap4_map_io,
-        .init_early     = omap4430_init_early,
-        .init_irq       = gic_init_irq,
-        .init_machine   = omap4_panda_init,
-        .init_late      = omap4430_init_late,
-        .init_time      = omap4_local_timer_init,
-        .restart        = omap44xx_restart,
-MACHINE_END
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 4ca6b680aa72..5748b5d06c23 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -68,6 +68,7 @@
 #define OVERO_SMSC911X_CS      5
 #define OVERO_SMSC911X_GPIO    176
+#define OVERO_SMSC911X_NRESET  64
 #define OVERO_SMSC911X2_CS     4
 #define OVERO_SMSC911X2_GPIO   65
@@ -122,7 +123,7 @@ static struct omap_smsc911x_platform_data smsc911x_cfg = {
        .id             = 0,
        .cs             = OVERO_SMSC911X_CS,
        .gpio_irq       = OVERO_SMSC911X_GPIO,
-        .gpio_reset     = -EINVAL,
+        .gpio_reset     = OVERO_SMSC911X_NRESET,
        .flags          = SMSC911X_USE_32BIT,
 };
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 18ca61e300b3..9c2dd102fbbb 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -553,6 +553,7 @@ static struct regulator_consumer_supply rx51_vio_supplies[] = {
 static struct regulator_consumer_supply rx51_vaux1_consumers[] = {
        REGULATOR_SUPPLY("vdds_sdi", "omapdss"),
+        REGULATOR_SUPPLY("vdds_sdi", "omapdss_sdi.0"),
        /* Si4713 supply */
        REGULATOR_SUPPLY("vdd", "2-0063"),
        /* lis3lv02d */
diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c
index bd74f9f6063b..bdd1e3a179e1 100644
--- a/arch/arm/mach-omap2/board-rx51-video.c
+++ b/arch/arm/mach-omap2/board-rx51-video.c
@@ -61,7 +61,7 @@ static struct omap_dss_board_info rx51_dss_board_info = {
 static int __init rx51_video_init(void)
 {
-        if (!machine_is_nokia_rx51())
+        if (!machine_is_nokia_rx51() && !of_machine_is_compatible("nokia,omap3-n900"))
                return 0;
        if (omap_mux_init_gpio(RX51_LCD_RESET_GPIO, OMAP_PIN_OUTPUT)) {
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
index af3544ce4f02..ba6534d7f155 100644
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -431,15 +431,11 @@ DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null);
 *  - Driver code is not yet migrated to use hwmod/runtime pm
 *  - Modules outside kernel access (to disable them by default)
 *
- *     - debugss
 *     - mmu (gfx domain)
 *     - cefuse
 *     - usbotg_fck (its additional clock and not really a modulemode)
 *     - ieee5000
 */
-DEFINE_CLK_GATE(debugss_ick, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
-                AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
-                0x0, NULL);
 DEFINE_CLK_GATE(mmu_fck, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
                AM33XX_CM_GFX_MMUDATA_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
@@ -862,6 +858,69 @@ static struct clk_hw_omap wdt1_fck_hw = {
 DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);
+static const char *pwmss_clk_parents[] = {
+        "dpll_per_m2_ck",
+};
+static const struct clk_ops ehrpwm_tbclk_ops = {
+        .enable         = &omap2_dflt_clk_enable,
+        .disable        = &omap2_dflt_clk_disable,
+};
+DEFINE_CLK_OMAP_MUX_GATE(ehrpwm0_tbclk, "l4ls_clkdm",
+                         NULL, NULL, 0,
+                         AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
+                         AM33XX_PWMSS0_TBCLKEN_SHIFT,
+                         NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
+DEFINE_CLK_OMAP_MUX_GATE(ehrpwm1_tbclk, "l4ls_clkdm",
+                         NULL, NULL, 0,
+                         AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
+                         AM33XX_PWMSS1_TBCLKEN_SHIFT,
+                         NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
+DEFINE_CLK_OMAP_MUX_GATE(ehrpwm2_tbclk, "l4ls_clkdm",
+                         NULL, NULL, 0,
+                         AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
+                         AM33XX_PWMSS2_TBCLKEN_SHIFT,
+                         NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
+/*
+ * debugss optional clocks
+ */
+DEFINE_CLK_GATE(dbg_sysclk_ck, "sys_clkin_ck", &sys_clkin_ck,
+                0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
+                AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(dbg_clka_ck, "dpll_core_m4_ck", &dpll_core_m4_ck,
+                0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
+                AM33XX_OPTCLK_DEBUG_CLKA_SHIFT, 0x0, NULL);
+static const char *stm_pmd_clock_mux_ck_parents[] = {
+        "dbg_sysclk_ck", "dbg_clka_ck",
+};
+DEFINE_CLK_MUX(stm_pmd_clock_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0,
+               AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_STM_PMD_CLKSEL_SHIFT,
+               AM33XX_STM_PMD_CLKSEL_WIDTH, 0x0, NULL);
+DEFINE_CLK_MUX(trace_pmd_clk_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0,
+               AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
+               AM33XX_TRC_PMD_CLKSEL_SHIFT,
+               AM33XX_TRC_PMD_CLKSEL_WIDTH, 0x0, NULL);
+DEFINE_CLK_DIVIDER(stm_clk_div_ck, "stm_pmd_clock_mux_ck",
+                   &stm_pmd_clock_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
+                   AM33XX_STM_PMD_CLKDIVSEL_SHIFT,
+                   AM33XX_STM_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
+                   NULL);
+DEFINE_CLK_DIVIDER(trace_clk_div_ck, "trace_pmd_clk_mux_ck",
+                   &trace_pmd_clk_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
+                   AM33XX_TRC_PMD_CLKDIVSEL_SHIFT,
+                   AM33XX_TRC_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
+                   NULL);
 /*
 * clkdev
 */
@@ -899,7 +958,6 @@ static struct omap_clk am33xx_clks[] = {
        CLK("481cc000.d_can",   NULL,           &dcan0_fck),
        CLK(NULL,       "dcan1_fck",            &dcan1_fck),
        CLK("481d0000.d_can",   NULL,           &dcan1_fck),
-        CLK(NULL,       "debugss_ick",          &debugss_ick),
        CLK(NULL,       "pruss_ocp_gclk",       &pruss_ocp_gclk),
        CLK(NULL,       "mcasp0_fck",           &mcasp0_fck),
        CLK(NULL,       "mcasp1_fck",           &mcasp1_fck),
@@ -942,6 +1000,16 @@ static struct omap_clk am33xx_clks[] = {
        CLK(NULL,       "clkout2_div_ck",       &clkout2_div_ck),
        CLK(NULL,       "timer_32k_ck",         &clkdiv32k_ick),
        CLK(NULL,       "timer_sys_ck",         &sys_clkin_ck),
+        CLK(NULL,       "dbg_sysclk_ck",        &dbg_sysclk_ck),
+        CLK(NULL,       "dbg_clka_ck",          &dbg_clka_ck),
+        CLK(NULL,       "stm_pmd_clock_mux_ck", &stm_pmd_clock_mux_ck),
+        CLK(NULL,       "trace_pmd_clk_mux_ck", &trace_pmd_clk_mux_ck),
+        CLK(NULL,       "stm_clk_div_ck",       &stm_clk_div_ck),
+        CLK(NULL,       "trace_clk_div_ck",     &trace_clk_div_ck),
+        CLK(NULL,       "clkout2_ck",           &clkout2_ck),
+        CLK("48300200.ehrpwm",  "tbclk",        &ehrpwm0_tbclk),
+        CLK("48302200.ehrpwm",  "tbclk",        &ehrpwm1_tbclk),
+        CLK("48304200.ehrpwm",  "tbclk",        &ehrpwm2_tbclk),
 };
@@ -952,6 +1020,7 @@ static const char *enable_init_clks[] = {
        "l4hs_gclk",
        "l4fw_gclk",
        "l4ls_gclk",
+        "clkout2_ck",   /* Required for external peripherals like, Audio codecs */
 };
 int __init am33xx_clk_init(void)
diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
index 45cd26430d1f..334b76745900 100644
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -3329,11 +3329,7 @@ static struct omap_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
        CLK(NULL,       "cpefuse_fck",  &cpefuse_fck),
        CLK(NULL,       "ts_fck",       &ts_fck),
        CLK(NULL,       "usbtll_fck",   &usbtll_fck),
-        CLK("usbhs_omap",       "usbtll_fck",   &usbtll_fck),
-        CLK("usbhs_tll",        "usbtll_fck",   &usbtll_fck),
        CLK(NULL,       "usbtll_ick",   &usbtll_ick),
-        CLK("usbhs_omap",       "usbtll_ick",   &usbtll_ick),
-        CLK("usbhs_tll",        "usbtll_ick",   &usbtll_ick),
        CLK("omap_hsmmc.2",     "ick",  &mmchs3_ick),
        CLK(NULL,       "mmchs3_ick",   &mmchs3_ick),
        CLK(NULL,       "mmchs3_fck",   &mmchs3_fck),
@@ -3343,7 +3339,6 @@ static struct omap_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
        CLK(NULL,       "usbhost_120m_fck", &usbhost_120m_fck),
        CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck),
        CLK(NULL,       "usbhost_ick",  &usbhost_ick),
-        CLK("usbhs_omap",       "usbhost_ick",  &usbhost_ick),
 };
 /*
@@ -3463,12 +3458,6 @@ static struct omap_clk omap3xxx_clks[] = {
        CLK(NULL,       "utmi_p2_gfclk",        &dummy_ck),
        CLK(NULL,       "xclk60mhsp1_ck",       &dummy_ck),
        CLK(NULL,       "xclk60mhsp2_ck",       &dummy_ck),
-        CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &dummy_ck),
-        CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &dummy_ck),
-        CLK("usbhs_omap",       "usb_tll_hs_usb_ch0_clk",       &dummy_ck),
-        CLK("usbhs_omap",       "usb_tll_hs_usb_ch1_clk",       &dummy_ck),
-        CLK("usbhs_tll",        "usb_tll_hs_usb_ch0_clk",       &dummy_ck),
-        CLK("usbhs_tll",        "usb_tll_hs_usb_ch1_clk",       &dummy_ck),
        CLK(NULL,       "init_60m_fclk",        &dummy_ck),
        CLK(NULL,       "gpt1_fck",     &gpt1_fck),
        CLK(NULL,       "aes2_ick",     &aes2_ick),
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 2da37656a693..daeecf1b89fa 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -216,6 +216,7 @@ extern void __init omap243x_clockdomains_init(void);
 extern void __init omap3xxx_clockdomains_init(void);
 extern void __init am33xx_clockdomains_init(void);
 extern void __init omap44xx_clockdomains_init(void);
+extern void __init omap54xx_clockdomains_init(void);
 extern void clkdm_add_autodeps(struct clockdomain *clkdm);
 extern void clkdm_del_autodeps(struct clockdomain *clkdm);
diff --git a/arch/arm/mach-omap2/clockdomains54xx_data.c b/arch/arm/mach-omap2/clockdomains54xx_data.c
new file mode 100644
index 000000000000..1a3c69d2e14c
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains54xx_data.c
@@ -0,0 +1,464 @@
+/*
+ * OMAP54XX Clock domains framework
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Abhijit Pagare (abhijitpagare@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ * Paul Walmsley (paul@pwsan.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include "clockdomain.h"
+#include "cm1_54xx.h"
+#include "cm2_54xx.h"
+#include "cm-regbits-54xx.h"
+#include "prm54xx.h"
+#include "prcm44xx.h"
+#include "prcm_mpu54xx.h"
+/* Static Dependencies for OMAP4 Clock Domains */
+static struct clkdm_dep c2c_wkup_sleep_deps[] = {
+        { .clkdm_name = "abe_clkdm" },
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { .clkdm_name = "l3init_clkdm" },
+        { .clkdm_name = "l3main1_clkdm" },
+        { .clkdm_name = "l3main2_clkdm" },
+        { .clkdm_name = "l4cfg_clkdm" },
+        { .clkdm_name = "l4per_clkdm" },
+        { NULL },
+};
+static struct clkdm_dep cam_wkup_sleep_deps[] = {
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { .clkdm_name = "l3main1_clkdm" },
+        { NULL },
+};
+static struct clkdm_dep dma_wkup_sleep_deps[] = {
+        { .clkdm_name = "abe_clkdm" },
+        { .clkdm_name = "dss_clkdm" },
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "ipu_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { .clkdm_name = "l3init_clkdm" },
+        { .clkdm_name = "l3main1_clkdm" },
+        { .clkdm_name = "l4cfg_clkdm" },
+        { .clkdm_name = "l4per_clkdm" },
+        { .clkdm_name = "l4sec_clkdm" },
+        { .clkdm_name = "wkupaon_clkdm" },
+        { NULL },
+};
+static struct clkdm_dep dsp_wkup_sleep_deps[] = {
+        { .clkdm_name = "abe_clkdm" },
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { .clkdm_name = "l3init_clkdm" },
+        { .clkdm_name = "l3main1_clkdm" },
+        { .clkdm_name = "l3main2_clkdm" },
+        { .clkdm_name = "l4cfg_clkdm" },
+        { .clkdm_name = "l4per_clkdm" },
+        { .clkdm_name = "wkupaon_clkdm" },
+        { NULL },
+};
+static struct clkdm_dep dss_wkup_sleep_deps[] = {
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { .clkdm_name = "l3main2_clkdm" },
+        { NULL },
+};
+static struct clkdm_dep gpu_wkup_sleep_deps[] = {
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { .clkdm_name = "l3main1_clkdm" },
+        { NULL },
+};
+static struct clkdm_dep ipu_wkup_sleep_deps[] = {
+        { .clkdm_name = "abe_clkdm" },
+        { .clkdm_name = "dsp_clkdm" },
+        { .clkdm_name = "dss_clkdm" },
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "gpu_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { .clkdm_name = "l3init_clkdm" },
+        { .clkdm_name = "l3main1_clkdm" },
+        { .clkdm_name = "l3main2_clkdm" },
+        { .clkdm_name = "l4cfg_clkdm" },
+        { .clkdm_name = "l4per_clkdm" },
+        { .clkdm_name = "l4sec_clkdm" },
+        { .clkdm_name = "wkupaon_clkdm" },
+        { NULL },
+};
+static struct clkdm_dep iva_wkup_sleep_deps[] = {
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "l3main1_clkdm" },
+        { NULL },
+};
+static struct clkdm_dep l3init_wkup_sleep_deps[] = {
+        { .clkdm_name = "abe_clkdm" },
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { .clkdm_name = "l4cfg_clkdm" },
+        { .clkdm_name = "l4per_clkdm" },
+        { .clkdm_name = "l4sec_clkdm" },
+        { .clkdm_name = "wkupaon_clkdm" },
+        { NULL },
+};
+static struct clkdm_dep l4sec_wkup_sleep_deps[] = {
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "l3main1_clkdm" },
+        { .clkdm_name = "l4per_clkdm" },
+        { NULL },
+};
+static struct clkdm_dep mipiext_wkup_sleep_deps[] = {
+        { .clkdm_name = "abe_clkdm" },
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { .clkdm_name = "l3init_clkdm" },
+        { .clkdm_name = "l3main1_clkdm" },
+        { .clkdm_name = "l3main2_clkdm" },
+        { .clkdm_name = "l4cfg_clkdm" },
+        { .clkdm_name = "l4per_clkdm" },
+        { NULL },
+};
+static struct clkdm_dep mpu_wkup_sleep_deps[] = {
+        { .clkdm_name = "abe_clkdm" },
+        { .clkdm_name = "dsp_clkdm" },
+        { .clkdm_name = "dss_clkdm" },
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "gpu_clkdm" },
+        { .clkdm_name = "ipu_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { .clkdm_name = "l3init_clkdm" },
+        { .clkdm_name = "l3main1_clkdm" },
+        { .clkdm_name = "l3main2_clkdm" },
+        { .clkdm_name = "l4cfg_clkdm" },
+        { .clkdm_name = "l4per_clkdm" },
+        { .clkdm_name = "l4sec_clkdm" },
+        { .clkdm_name = "wkupaon_clkdm" },
+        { NULL },
+};
+static struct clockdomain l4sec_54xx_clkdm = {
+        .name             = "l4sec_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CORE_L4SEC_CDOFFS,
+        .dep_bit          = OMAP54XX_L4SEC_STATDEP_SHIFT,
+        .wkdep_srcs       = l4sec_wkup_sleep_deps,
+        .sleepdep_srcs    = l4sec_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+static struct clockdomain iva_54xx_clkdm = {
+        .name             = "iva_clkdm",
+        .pwrdm            = { .name = "iva_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_IVA_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_IVA_IVA_CDOFFS,
+        .dep_bit          = OMAP54XX_IVA_STATDEP_SHIFT,
+        .wkdep_srcs       = iva_wkup_sleep_deps,
+        .sleepdep_srcs    = iva_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+static struct clockdomain mipiext_54xx_clkdm = {
+        .name             = "mipiext_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CORE_MIPIEXT_CDOFFS,
+        .wkdep_srcs       = mipiext_wkup_sleep_deps,
+        .sleepdep_srcs    = mipiext_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+static struct clockdomain l3main2_54xx_clkdm = {
+        .name             = "l3main2_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CORE_L3MAIN2_CDOFFS,
+        .dep_bit          = OMAP54XX_L3MAIN2_STATDEP_SHIFT,
+        .flags            = CLKDM_CAN_HWSUP,
+};
+static struct clockdomain l3main1_54xx_clkdm = {
+        .name             = "l3main1_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CORE_L3MAIN1_CDOFFS,
+        .dep_bit          = OMAP54XX_L3MAIN1_STATDEP_SHIFT,
+        .flags            = CLKDM_CAN_HWSUP,
+};
+static struct clockdomain custefuse_54xx_clkdm = {
+        .name             = "custefuse_clkdm",
+        .pwrdm            = { .name = "custefuse_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CUSTEFUSE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+static struct clockdomain ipu_54xx_clkdm = {
+        .name             = "ipu_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CORE_IPU_CDOFFS,
+        .dep_bit          = OMAP54XX_IPU_STATDEP_SHIFT,
+        .wkdep_srcs       = ipu_wkup_sleep_deps,
+        .sleepdep_srcs    = ipu_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+static struct clockdomain l4cfg_54xx_clkdm = {
+        .name             = "l4cfg_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CORE_L4CFG_CDOFFS,
+        .dep_bit          = OMAP54XX_L4CFG_STATDEP_SHIFT,
+        .flags            = CLKDM_CAN_HWSUP,
+};
+static struct clockdomain abe_54xx_clkdm = {
+        .name             = "abe_clkdm",
+        .pwrdm            = { .name = "abe_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_AON_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_AON_ABE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_AON_ABE_ABE_CDOFFS,
+        .dep_bit          = OMAP54XX_ABE_STATDEP_SHIFT,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+static struct clockdomain dss_54xx_clkdm = {
+        .name             = "dss_clkdm",
+        .pwrdm            = { .name = "dss_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_DSS_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_DSS_DSS_CDOFFS,
+        .dep_bit          = OMAP54XX_DSS_STATDEP_SHIFT,
+        .wkdep_srcs       = dss_wkup_sleep_deps,
+        .sleepdep_srcs    = dss_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+static struct clockdomain dsp_54xx_clkdm = {
+        .name             = "dsp_clkdm",
+        .pwrdm            = { .name = "dsp_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_AON_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_AON_DSP_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS,
+        .dep_bit          = OMAP54XX_DSP_STATDEP_SHIFT,
+        .wkdep_srcs       = dsp_wkup_sleep_deps,
+        .sleepdep_srcs    = dsp_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+static struct clockdomain c2c_54xx_clkdm = {
+        .name             = "c2c_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CORE_C2C_CDOFFS,
+        .wkdep_srcs       = c2c_wkup_sleep_deps,
+        .sleepdep_srcs    = c2c_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+static struct clockdomain l4per_54xx_clkdm = {
+        .name             = "l4per_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CORE_L4PER_CDOFFS,
+        .dep_bit          = OMAP54XX_L4PER_STATDEP_SHIFT,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+static struct clockdomain gpu_54xx_clkdm = {
+        .name             = "gpu_clkdm",
+        .pwrdm            = { .name = "gpu_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_GPU_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_GPU_GPU_CDOFFS,
+        .dep_bit          = OMAP54XX_GPU_STATDEP_SHIFT,
+        .wkdep_srcs       = gpu_wkup_sleep_deps,
+        .sleepdep_srcs    = gpu_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+static struct clockdomain wkupaon_54xx_clkdm = {
+        .name             = "wkupaon_clkdm",
+        .pwrdm            = { .name = "wkupaon_pwrdm" },
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .cm_inst          = OMAP54XX_PRM_WKUPAON_CM_INST,
+        .clkdm_offs       = OMAP54XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS,
+        .dep_bit          = OMAP54XX_WKUPAON_STATDEP_SHIFT,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+static struct clockdomain mpu0_54xx_clkdm = {
+        .name             = "mpu0_clkdm",
+        .pwrdm            = { .name = "cpu0_pwrdm" },
+        .prcm_partition   = OMAP54XX_PRCM_MPU_PARTITION,
+        .cm_inst          = OMAP54XX_PRCM_MPU_CM_C0_INST,
+        .clkdm_offs       = OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+static struct clockdomain mpu1_54xx_clkdm = {
+        .name             = "mpu1_clkdm",
+        .pwrdm            = { .name = "cpu1_pwrdm" },
+        .prcm_partition   = OMAP54XX_PRCM_MPU_PARTITION,
+        .cm_inst          = OMAP54XX_PRCM_MPU_CM_C1_INST,
+        .clkdm_offs       = OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+static struct clockdomain coreaon_54xx_clkdm = {
+        .name             = "coreaon_clkdm",
+        .pwrdm            = { .name = "coreaon_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_COREAON_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_COREAON_COREAON_CDOFFS,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+static struct clockdomain mpu_54xx_clkdm = {
+        .name             = "mpu_clkdm",
+        .pwrdm            = { .name = "mpu_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_AON_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_AON_MPU_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS,
+        .wkdep_srcs       = mpu_wkup_sleep_deps,
+        .sleepdep_srcs    = mpu_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+static struct clockdomain l3init_54xx_clkdm = {
+        .name             = "l3init_clkdm",
+        .pwrdm            = { .name = "l3init_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_L3INIT_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_L3INIT_L3INIT_CDOFFS,
+        .dep_bit          = OMAP54XX_L3INIT_STATDEP_SHIFT,
+        .wkdep_srcs       = l3init_wkup_sleep_deps,
+        .sleepdep_srcs    = l3init_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+static struct clockdomain dma_54xx_clkdm = {
+        .name             = "dma_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CORE_DMA_CDOFFS,
+        .wkdep_srcs       = dma_wkup_sleep_deps,
+        .sleepdep_srcs    = dma_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+static struct clockdomain l3instr_54xx_clkdm = {
+        .name             = "l3instr_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CORE_L3INSTR_CDOFFS,
+};
+static struct clockdomain emif_54xx_clkdm = {
+        .name             = "emif_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CORE_EMIF_CDOFFS,
+        .dep_bit          = OMAP54XX_EMIF_STATDEP_SHIFT,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+static struct clockdomain emu_54xx_clkdm = {
+        .name             = "emu_clkdm",
+        .pwrdm            = { .name = "emu_pwrdm" },
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .cm_inst          = OMAP54XX_PRM_EMU_CM_INST,
+        .clkdm_offs       = OMAP54XX_PRM_EMU_CM_EMU_CDOFFS,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+static struct clockdomain cam_54xx_clkdm = {
+        .name             = "cam_clkdm",
+        .pwrdm            = { .name = "cam_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CAM_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CAM_CAM_CDOFFS,
+        .wkdep_srcs       = cam_wkup_sleep_deps,
+        .sleepdep_srcs    = cam_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+/* As clockdomains are added or removed above, this list must also be changed */
+static struct clockdomain *clockdomains_omap54xx[] __initdata = {
+        &l4sec_54xx_clkdm,
+        &iva_54xx_clkdm,
+        &mipiext_54xx_clkdm,
+        &l3main2_54xx_clkdm,
+        &l3main1_54xx_clkdm,
+        &custefuse_54xx_clkdm,
+        &ipu_54xx_clkdm,
+        &l4cfg_54xx_clkdm,
+        &abe_54xx_clkdm,
+        &dss_54xx_clkdm,
+        &dsp_54xx_clkdm,
+        &c2c_54xx_clkdm,
+        &l4per_54xx_clkdm,
+        &gpu_54xx_clkdm,
+        &wkupaon_54xx_clkdm,
+        &mpu0_54xx_clkdm,
+        &mpu1_54xx_clkdm,
+        &coreaon_54xx_clkdm,
+        &mpu_54xx_clkdm,
+        &l3init_54xx_clkdm,
+        &dma_54xx_clkdm,
+        &l3instr_54xx_clkdm,
+        &emif_54xx_clkdm,
+        &emu_54xx_clkdm,
+        &cam_54xx_clkdm,
+        NULL
+};
+void __init omap54xx_clockdomains_init(void)
+{
+        clkdm_register_platform_funcs(&omap4_clkdm_operations);
+        clkdm_register_clkdms(clockdomains_omap54xx);
+        clkdm_complete_init();
+}
diff --git a/arch/arm/mach-omap2/cm-regbits-54xx.h b/arch/arm/mach-omap2/cm-regbits-54xx.h
new file mode 100644
index 000000000000..e83b8e352b6e
--- /dev/null
+++ b/arch/arm/mach-omap2/cm-regbits-54xx.h
@@ -0,0 +1,1737 @@
+/*
+ * OMAP54xx Clock Management register bits
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H
+/* Used by CM_DSP_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_MPU_DYNAMICDEP */
+#define OMAP54XX_ABE_DYNDEP_SHIFT                                       3
+#define OMAP54XX_ABE_DYNDEP_WIDTH                                       0x1
+#define OMAP54XX_ABE_DYNDEP_MASK                                        (1 << 3)
+/*
+ * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
+ * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
+ */
+#define OMAP54XX_ABE_STATDEP_SHIFT                                      3
+#define OMAP54XX_ABE_STATDEP_WIDTH                                      0x1
+#define OMAP54XX_ABE_STATDEP_MASK                                       (1 << 3)
+/*
+ * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_IVA,
+ * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO1,
+ * CM_AUTOIDLE_DPLL_UNIPRO2, CM_AUTOIDLE_DPLL_USB
+ */
+#define OMAP54XX_AUTO_DPLL_MODE_SHIFT                                   0
+#define OMAP54XX_AUTO_DPLL_MODE_WIDTH                                   0x3
+#define OMAP54XX_AUTO_DPLL_MODE_MASK                                    (0x7 << 0)
+/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
+#define OMAP54XX_C2C_DYNDEP_SHIFT                                       18
+#define OMAP54XX_C2C_DYNDEP_WIDTH                                       0x1
+#define OMAP54XX_C2C_DYNDEP_MASK                                        (1 << 18)
+/* Used by CM_MPU_STATICDEP */
+#define OMAP54XX_C2C_STATDEP_SHIFT                                      18
+#define OMAP54XX_C2C_STATDEP_WIDTH                                      0x1
+#define OMAP54XX_C2C_STATDEP_MASK                                       (1 << 18)
+/* Used by CM_IPU_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
+#define OMAP54XX_CAM_DYNDEP_SHIFT                                       9
+#define OMAP54XX_CAM_DYNDEP_WIDTH                                       0x1
+#define OMAP54XX_CAM_DYNDEP_MASK                                        (1 << 9)
+/*
+ * Used by CM_DMA_STATICDEP, CM_DSP_STATICDEP, CM_IPU_STATICDEP,
+ * CM_MPU_STATICDEP
+ */
+#define OMAP54XX_CAM_STATDEP_SHIFT                                      9
+#define OMAP54XX_CAM_STATDEP_WIDTH                                      0x1
+#define OMAP54XX_CAM_STATDEP_MASK                                       (1 << 9)
+/* Used by CM_ABE_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_SHIFT                        13
+#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_MASK                         (1 << 13)
+/* Used by CM_ABE_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_SHIFT                          12
+#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_WIDTH                          0x1
+#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_MASK                           (1 << 12)
+/* Used by CM_ABE_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_ABE_GICLK_SHIFT                            9
+#define OMAP54XX_CLKACTIVITY_ABE_GICLK_WIDTH                            0x1
+#define OMAP54XX_CLKACTIVITY_ABE_GICLK_MASK                             (1 << 9)
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_SHIFT                           9
+#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_WIDTH                           0x1
+#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_MASK                            (1 << 9)
+/* Used by CM_ABE_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_SHIFT                          11
+#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_WIDTH                          0x1
+#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_MASK                           (1 << 11)
+/* Used by CM_ABE_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_SHIFT                           8
+#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_WIDTH                           0x1
+#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_MASK                            (1 << 8)
+/* Used by CM_DSS_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_SHIFT                           13
+#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_WIDTH                           0x1
+#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_MASK                            (1 << 13)
+/* Used by CM_C2C_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_SHIFT                            9
+#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_WIDTH                            0x1
+#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_MASK                             (1 << 9)
+/* Used by CM_C2C_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_C2C_GICLK_SHIFT                            10
+#define OMAP54XX_CLKACTIVITY_C2C_GICLK_WIDTH                            0x1
+#define OMAP54XX_CLKACTIVITY_C2C_GICLK_MASK                             (1 << 10)
+/* Used by CM_C2C_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_SHIFT                         8
+#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_MASK                          (1 << 8)
+/* Used by CM_CAM_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_SHIFT                       11
+#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_WIDTH                       0x1
+#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_MASK                        (1 << 11)
+/* Used by CM_CAM_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_CAM_GCLK_SHIFT                             8
+#define OMAP54XX_CLKACTIVITY_CAM_GCLK_WIDTH                             0x1
+#define OMAP54XX_CLKACTIVITY_CAM_GCLK_MASK                              (1 << 8)
+/* Used by CM_CAM_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_SHIFT                         12
+#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_MASK                          (1 << 12)
+/* Used by CM_COREAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_SHIFT                    12
+#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_WIDTH                    0x1
+#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_MASK                     (1 << 12)
+/* Used by CM_COREAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_SHIFT              14
+#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_WIDTH              0x1
+#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_MASK               (1 << 14)
+/* Used by CM_COREAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_SHIFT                     8
+#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_WIDTH                     0x1
+#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_MASK                      (1 << 8)
+/* Used by CM_CAM_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_SHIFT                        9
+#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_MASK                         (1 << 9)
+/* Used by CM_CUSTEFUSE_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_SHIFT                   8
+#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_WIDTH                   0x1
+#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_MASK                    (1 << 8)
+/* Used by CM_CUSTEFUSE_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_SHIFT                  9
+#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_WIDTH                  0x1
+#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_MASK                   (1 << 9)
+/* Used by CM_EMIF_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_DLL_GCLK_SHIFT                             9
+#define OMAP54XX_CLKACTIVITY_DLL_GCLK_WIDTH                             0x1
+#define OMAP54XX_CLKACTIVITY_DLL_GCLK_MASK                              (1 << 9)
+/* Used by CM_DMA_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_SHIFT                         8
+#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_MASK                          (1 << 8)
+/* Used by CM_DSP_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_DSP_GCLK_SHIFT                             8
+#define OMAP54XX_CLKACTIVITY_DSP_GCLK_WIDTH                             0x1
+#define OMAP54XX_CLKACTIVITY_DSP_GCLK_MASK                              (1 << 8)
+/* Used by CM_DSS_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_SHIFT                            9
+#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_WIDTH                            0x1
+#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_MASK                             (1 << 9)
+/* Used by CM_DSS_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_SHIFT                         8
+#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_MASK                          (1 << 8)
+/* Used by CM_DSS_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_SHIFT                        10
+#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_MASK                         (1 << 10)
+/* Used by CM_EMIF_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_SHIFT                        8
+#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_MASK                         (1 << 8)
+/* Used by CM_EMIF_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_SHIFT                         11
+#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_MASK                          (1 << 11)
+/* Used by CM_EMIF_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_SHIFT                        10
+#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_MASK                         (1 << 10)
+/* Used by CM_EMU_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_SHIFT                         8
+#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_MASK                          (1 << 8)
+/* Used by CM_CAM_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_SHIFT                            10
+#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_WIDTH                            0x1
+#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_MASK                             (1 << 10)
+/* Used by CM_ABE_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT                       10
+#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_WIDTH                       0x1
+#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_MASK                        (1 << 10)
+/* Used by CM_GPU_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_SHIFT                        9
+#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_MASK                         (1 << 9)
+/* Used by CM_GPU_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_SHIFT                         10
+#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_MASK                          (1 << 10)
+/* Used by CM_GPU_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_SHIFT                         8
+#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_MASK                          (1 << 8)
+/* Used by CM_DSS_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_SHIFT                       12
+#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_WIDTH                       0x1
+#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_MASK                        (1 << 12)
+/* Used by CM_DSS_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_SHIFT                       11
+#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_WIDTH                       0x1
+#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_MASK                        (1 << 11)
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT                   20
+#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_WIDTH                   0x1
+#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK                    (1 << 20)
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT                        26
+#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_MASK                         (1 << 26)
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT                   21
+#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_WIDTH                   0x1
+#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK                    (1 << 21)
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT                        27
+#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_MASK                         (1 << 27)
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_SHIFT                   6
+#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_WIDTH                   0x1
+#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_MASK                    (1 << 6)
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_SHIFT                        7
+#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_MASK                         (1 << 7)
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_SHIFT                            16
+#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_WIDTH                            0x1
+#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_MASK                             (1 << 16)
+/* Used by CM_IPU_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_IPU_GCLK_SHIFT                             8
+#define OMAP54XX_CLKACTIVITY_IPU_GCLK_WIDTH                             0x1
+#define OMAP54XX_CLKACTIVITY_IPU_GCLK_MASK                              (1 << 8)
+/* Used by CM_IVA_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_IVA_GCLK_SHIFT                             8
+#define OMAP54XX_CLKACTIVITY_IVA_GCLK_WIDTH                             0x1
+#define OMAP54XX_CLKACTIVITY_IVA_GCLK_MASK                              (1 << 8)
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_SHIFT                     12
+#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_WIDTH                     0x1
+#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_MASK                      (1 << 12)
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_SHIFT                  28
+#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_WIDTH                  0x1
+#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_MASK                   (1 << 28)
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_SHIFT                  29
+#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_WIDTH                  0x1
+#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_MASK                   (1 << 29)
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_SHIFT                      8
+#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_WIDTH                      0x1
+#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_MASK                       (1 << 8)
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_SHIFT                      9
+#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_WIDTH                      0x1
+#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_MASK                       (1 << 9)
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_SHIFT      11
+#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_WIDTH      0x1
+#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_MASK       (1 << 11)
+/* Used by CM_L3INSTR_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_SHIFT               9
+#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_WIDTH               0x1
+#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_MASK                (1 << 9)
+/* Used by CM_L3INSTR_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_SHIFT                     8
+#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_WIDTH                     0x1
+#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_MASK                      (1 << 8)
+/* Used by CM_L3INSTR_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_SHIFT                      10
+#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_WIDTH                      0x1
+#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_MASK                       (1 << 10)
+/* Used by CM_L3MAIN1_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_SHIFT                     8
+#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_WIDTH                     0x1
+#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_MASK                      (1 << 8)
+/* Used by CM_L3MAIN2_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_SHIFT                     8
+#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_WIDTH                     0x1
+#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_MASK                      (1 << 8)
+/* Used by CM_L4CFG_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_SHIFT                       8
+#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_WIDTH                       0x1
+#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_MASK                        (1 << 8)
+/* Used by CM_L4PER_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_SHIFT                       8
+#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_WIDTH                       0x1
+#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_MASK                        (1 << 8)
+/* Used by CM_L4SEC_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_SHIFT                       8
+#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_WIDTH                       0x1
+#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_MASK                        (1 << 8)
+/* Used by CM_L4SEC_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_SHIFT                       9
+#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_WIDTH                       0x1
+#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_MASK                        (1 << 9)
+/* Used by CM_MIPIEXT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_SHIFT                     8
+#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_WIDTH                     0x1
+#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_MASK                      (1 << 8)
+/* Used by CM_MIPIEXT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_SHIFT                11
+#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_WIDTH                0x1
+#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_MASK                 (1 << 11)
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_SHIFT                       2
+#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_WIDTH                       0x1
+#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_MASK                        (1 << 2)
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_SHIFT                           17
+#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_WIDTH                           0x1
+#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_MASK                            (1 << 17)
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_SHIFT                           18
+#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_WIDTH                           0x1
+#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_MASK                            (1 << 18)
+/* Used by CM_MPU_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_MPU_GCLK_SHIFT                             8
+#define OMAP54XX_CLKACTIVITY_MPU_GCLK_WIDTH                             0x1
+#define OMAP54XX_CLKACTIVITY_MPU_GCLK_MASK                              (1 << 8)
+/* Used by CM_ABE_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_PAD_CLKS_SHIFT                             14
+#define OMAP54XX_CLKACTIVITY_PAD_CLKS_WIDTH                             0x1
+#define OMAP54XX_CLKACTIVITY_PAD_CLKS_MASK                              (1 << 14)
+/* Used by CM_ABE_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_SHIFT                     15
+#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_WIDTH                     0x1
+#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_MASK                      (1 << 15)
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_SHIFT                      3
+#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_WIDTH                      0x1
+#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_MASK                       (1 << 3)
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_SHIFT                      4
+#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_WIDTH                      0x1
+#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_MASK                       (1 << 4)
+/* Used by CM_L4PER_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_SHIFT                        15
+#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_MASK                         (1 << 15)
+/* Used by CM_L4PER_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_SHIFT                        17
+#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_MASK                         (1 << 17)
+/* Used by CM_L4PER_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_SHIFT                        18
+#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_MASK                         (1 << 18)
+/* Used by CM_L4PER_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_SHIFT                        19
+#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_MASK                         (1 << 19)
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_SHIFT                       19
+#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_WIDTH                       0x1
+#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_MASK                        (1 << 19)
+/* Used by CM_COREAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_SHIFT                    11
+#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_WIDTH                    0x1
+#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_MASK                     (1 << 11)
+/* Used by CM_COREAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_SHIFT                      10
+#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_WIDTH                      0x1
+#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_MASK                       (1 << 10)
+/* Used by CM_COREAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_SHIFT                     9
+#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_WIDTH                     0x1
+#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_MASK                      (1 << 9)
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_SYS_CLK_SHIFT                              8
+#define OMAP54XX_CLKACTIVITY_SYS_CLK_WIDTH                              0x1
+#define OMAP54XX_CLKACTIVITY_SYS_CLK_MASK                               (1 << 8)
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_SHIFT                          15
+#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_WIDTH                          0x1
+#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_MASK                           (1 << 15)
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_SHIFT                         14
+#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_MASK                          (1 << 14)
+/* Used by CM_L4PER_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_SHIFT                        9
+#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_MASK                         (1 << 9)
+/* Used by CM_L4PER_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_SHIFT                        10
+#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_MASK                         (1 << 10)
+/* Used by CM_L4PER_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_SHIFT                         11
+#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_MASK                          (1 << 11)
+/* Used by CM_L4PER_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_SHIFT                         12
+#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_MASK                          (1 << 12)
+/* Used by CM_L4PER_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_SHIFT                         13
+#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_MASK                          (1 << 13)
+/* Used by CM_L4PER_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_SHIFT                         14
+#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_MASK                          (1 << 14)
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT                        22
+#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_MASK                         (1 << 22)
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT                        23
+#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_MASK                         (1 << 23)
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT                        24
+#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_MASK                         (1 << 24)
+/* Used by CM_MIPIEXT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_SHIFT                     10
+#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_WIDTH                     0x1
+#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_MASK                      (1 << 10)
+/* Used by CM_MIPIEXT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_SHIFT                    13
+#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_WIDTH                    0x1
+#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_MASK                     (1 << 13)
+/* Used by CM_MIPIEXT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_SHIFT               12
+#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_WIDTH               0x1
+#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_MASK                (1 << 12)
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_SHIFT                     10
+#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_WIDTH                     0x1
+#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_MASK                      (1 << 10)
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_SHIFT                    13
+#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_WIDTH                    0x1
+#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_MASK                     (1 << 13)
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_SHIFT                5
+#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_WIDTH                0x1
+#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_MASK                 (1 << 5)
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_SHIFT                         14
+#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_MASK                          (1 << 14)
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT                      15
+#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_WIDTH                      0x1
+#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_MASK                       (1 << 15)
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_SHIFT                   31
+#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_WIDTH                   0x1
+#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_MASK                    (1 << 31)
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT                        30
+#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_MASK                         (1 << 30)
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT                      25
+#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_WIDTH                      0x1
+#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK                       (1 << 25)
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_SHIFT                    11
+#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_WIDTH                    0x1
+#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_MASK                     (1 << 11)
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_SHIFT                        12
+#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_MASK                         (1 << 12)
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_SHIFT              13
+#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_WIDTH              0x1
+#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_MASK               (1 << 13)
+/* Used by CM_COREAON_IO_SRCOMP_CLKCTRL, CM_WKUPAON_IO_SRCOMP_CLKCTRL */
+#define OMAP54XX_CLKEN_SRCOMP_FCLK_SHIFT                                8
+#define OMAP54XX_CLKEN_SRCOMP_FCLK_WIDTH                                0x1
+#define OMAP54XX_CLKEN_SRCOMP_FCLK_MASK                                 (1 << 8)
+/*
+ * Used by CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL,
+ * CM_ABE_TIMER8_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL,
+ * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL,
+ * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL
+ */
+#define OMAP54XX_CLKSEL_SHIFT                                           24
+#define OMAP54XX_CLKSEL_WIDTH                                           0x1
+#define OMAP54XX_CLKSEL_MASK                                            (1 << 24)
+/*
+ * Renamed from CLKSEL Used by CM_CLKSEL_ABE_DSS_SYS, CM_CLKSEL_ABE_PLL_REF,
+ * CM_CLKSEL_USB_60MHZ, CM_CLKSEL_WKUPAON
+ */
+#define OMAP54XX_CLKSEL_0_0_SHIFT                                       0
+#define OMAP54XX_CLKSEL_0_0_WIDTH                                       0x1
+#define OMAP54XX_CLKSEL_0_0_MASK                                        (1 << 0)
+/* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */
+#define OMAP54XX_CLKSEL_0_1_SHIFT                                       0
+#define OMAP54XX_CLKSEL_0_1_WIDTH                                       0x2
+#define OMAP54XX_CLKSEL_0_1_MASK                                        (0x3 << 0)
+/* Renamed from CLKSEL Used by CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL */
+#define OMAP54XX_CLKSEL_24_25_SHIFT                                     24
+#define OMAP54XX_CLKSEL_24_25_WIDTH                                     0x2
+#define OMAP54XX_CLKSEL_24_25_MASK                                      (0x3 << 24)
+/* Used by CM_MPU_MPU_CLKCTRL */
+#define OMAP54XX_CLKSEL_ABE_DIV_MODE_SHIFT                              26
+#define OMAP54XX_CLKSEL_ABE_DIV_MODE_WIDTH                              0x1
+#define OMAP54XX_CLKSEL_ABE_DIV_MODE_MASK                               (1 << 26)
+/* Used by CM_ABE_AESS_CLKCTRL */
+#define OMAP54XX_CLKSEL_AESS_FCLK_SHIFT                                 24
+#define OMAP54XX_CLKSEL_AESS_FCLK_WIDTH                                 0x1
+#define OMAP54XX_CLKSEL_AESS_FCLK_MASK                                  (1 << 24)
+/* Used by CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL */
+#define OMAP54XX_CLKSEL_DIV_SHIFT                                       25
+#define OMAP54XX_CLKSEL_DIV_WIDTH                                       0x1
+#define OMAP54XX_CLKSEL_DIV_MASK                                        (1 << 25)
+/* Used by CM_MPU_MPU_CLKCTRL */
+#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_SHIFT                             24
+#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_WIDTH                             0x2
+#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_MASK                              (0x3 << 24)
+/* Used by CM_CAM_FDIF_CLKCTRL */
+#define OMAP54XX_CLKSEL_FCLK_SHIFT                                      24
+#define OMAP54XX_CLKSEL_FCLK_WIDTH                                      0x1
+#define OMAP54XX_CLKSEL_FCLK_MASK                                       (1 << 24)
+/* Used by CM_GPU_GPU_CLKCTRL */
+#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_SHIFT                             24
+#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_WIDTH                             0x1
+#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_MASK                              (1 << 24)
+/* Used by CM_GPU_GPU_CLKCTRL */
+#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_SHIFT                              25
+#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_WIDTH                              0x1
+#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_MASK                               (1 << 25)
+/* Used by CM_GPU_GPU_CLKCTRL */
+#define OMAP54XX_CLKSEL_GPU_SYS_CLK_SHIFT                               26
+#define OMAP54XX_CLKSEL_GPU_SYS_CLK_WIDTH                               0x1
+#define OMAP54XX_CLKSEL_GPU_SYS_CLK_MASK                                (1 << 26)
+/*
+ * Used by CM_ABE_DMIC_CLKCTRL, CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL,
+ * CM_ABE_MCBSP2_CLKCTRL, CM_ABE_MCBSP3_CLKCTRL
+ */
+#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT                           26
+#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH                           0x2
+#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_MASK                            (0x3 << 26)
+/* Used by CM_CLKSEL_CORE */
+#define OMAP54XX_CLKSEL_L3_SHIFT                                        4
+#define OMAP54XX_CLKSEL_L3_WIDTH                                        0x1
+#define OMAP54XX_CLKSEL_L3_MASK                                         (1 << 4)
+/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
+#define OMAP54XX_CLKSEL_L3_1_1_SHIFT                                    1
+#define OMAP54XX_CLKSEL_L3_1_1_WIDTH                                    0x1
+#define OMAP54XX_CLKSEL_L3_1_1_MASK                                     (1 << 1)
+/* Used by CM_CLKSEL_CORE */
+#define OMAP54XX_CLKSEL_L4_SHIFT                                        8
+#define OMAP54XX_CLKSEL_L4_WIDTH                                        0x1
+#define OMAP54XX_CLKSEL_L4_MASK                                         (1 << 8)
+/* Used by CM_EMIF_EMIF1_CLKCTRL */
+#define OMAP54XX_CLKSEL_LL_SHIFT                                        24
+#define OMAP54XX_CLKSEL_LL_WIDTH                                        0x1
+#define OMAP54XX_CLKSEL_LL_MASK                                         (1 << 24)
+/* Used by CM_CLKSEL_ABE */
+#define OMAP54XX_CLKSEL_OPP_SHIFT                                       0
+#define OMAP54XX_CLKSEL_OPP_WIDTH                                       0x2
+#define OMAP54XX_CLKSEL_OPP_MASK                                        (0x3 << 0)
+/* Renamed from CLKSEL_OPP Used by CM_L3INIT_UNIPRO2_CLKCTRL */
+#define OMAP54XX_CLKSEL_OPP_24_24_SHIFT                                 24
+#define OMAP54XX_CLKSEL_OPP_24_24_WIDTH                                 0x1
+#define OMAP54XX_CLKSEL_OPP_24_24_MASK                                  (1 << 24)
+/*
+ * Used by CM_ABE_DMIC_CLKCTRL, CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL,
+ * CM_ABE_MCBSP2_CLKCTRL, CM_ABE_MCBSP3_CLKCTRL
+ */
+#define OMAP54XX_CLKSEL_SOURCE_SHIFT                                    24
+#define OMAP54XX_CLKSEL_SOURCE_WIDTH                                    0x2
+#define OMAP54XX_CLKSEL_SOURCE_MASK                                     (0x3 << 24)
+/*
+ * Renamed from CLKSEL_SOURCE Used by CM_L3INIT_MMC1_CLKCTRL,
+ * CM_L3INIT_MMC2_CLKCTRL
+ */
+#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_SHIFT                        24
+#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_WIDTH                        0x1
+#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_MASK                         (1 << 24)
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OMAP54XX_CLKSEL_UTMI_P1_SHIFT                                   24
+#define OMAP54XX_CLKSEL_UTMI_P1_WIDTH                                   0x1
+#define OMAP54XX_CLKSEL_UTMI_P1_MASK                                    (1 << 24)
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OMAP54XX_CLKSEL_UTMI_P2_SHIFT                                   25
+#define OMAP54XX_CLKSEL_UTMI_P2_WIDTH                                   0x1
+#define OMAP54XX_CLKSEL_UTMI_P2_MASK                                    (1 << 25)
+/*
+ * Used by CM_DIV_H11_DPLL_CORE, CM_DIV_H11_DPLL_IVA, CM_DIV_H11_DPLL_PER,
+ * CM_DIV_H12_DPLL_CORE, CM_DIV_H12_DPLL_IVA, CM_DIV_H12_DPLL_PER,
+ * CM_DIV_H13_DPLL_CORE, CM_DIV_H13_DPLL_PER, CM_DIV_H14_DPLL_CORE,
+ * CM_DIV_H14_DPLL_PER, CM_DIV_H21_DPLL_CORE, CM_DIV_H22_DPLL_CORE,
+ * CM_DIV_H23_DPLL_CORE, CM_DIV_H24_DPLL_CORE, CM_DIV_M2_DPLL_ABE,
+ * CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER,
+ * CM_DIV_M2_DPLL_UNIPRO1, CM_DIV_M2_DPLL_UNIPRO2, CM_DIV_M2_DPLL_USB,
+ * CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER
+ */
+#define OMAP54XX_CLKST_SHIFT                                            9
+#define OMAP54XX_CLKST_WIDTH                                            0x1
+#define OMAP54XX_CLKST_MASK                                             (1 << 9)
+/*
+ * Used by CM_ABE_CLKSTCTRL, CM_C2C_CLKSTCTRL, CM_CAM_CLKSTCTRL,
+ * CM_COREAON_CLKSTCTRL, CM_CUSTEFUSE_CLKSTCTRL, CM_DMA_CLKSTCTRL,
+ * CM_DSP_CLKSTCTRL, CM_DSS_CLKSTCTRL, CM_EMIF_CLKSTCTRL, CM_EMU_CLKSTCTRL,
+ * CM_GPU_CLKSTCTRL, CM_IPU_CLKSTCTRL, CM_IVA_CLKSTCTRL, CM_L3INIT_CLKSTCTRL,
+ * CM_L3INSTR_CLKSTCTRL, CM_L3MAIN1_CLKSTCTRL, CM_L3MAIN2_CLKSTCTRL,
+ * CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL, CM_L4SEC_CLKSTCTRL,
+ * CM_MIPIEXT_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_WKUPAON_CLKSTCTRL
+ */
+#define OMAP54XX_CLKTRCTRL_SHIFT                                        0
+#define OMAP54XX_CLKTRCTRL_WIDTH                                        0x2
+#define OMAP54XX_CLKTRCTRL_MASK                                         (0x3 << 0)
+/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER */
+#define OMAP54XX_CLKX2ST_SHIFT                                          11
+#define OMAP54XX_CLKX2ST_WIDTH                                          0x1
+#define OMAP54XX_CLKX2ST_MASK                                           (1 << 11)
+/* Used by CM_L4CFG_DYNAMICDEP */
+#define OMAP54XX_COREAON_DYNDEP_SHIFT                                   16
+#define OMAP54XX_COREAON_DYNDEP_WIDTH                                   0x1
+#define OMAP54XX_COREAON_DYNDEP_MASK                                    (1 << 16)
+/* Used by CM_DSP_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */
+#define OMAP54XX_COREAON_STATDEP_SHIFT                                  16
+#define OMAP54XX_COREAON_STATDEP_WIDTH                                  0x1
+#define OMAP54XX_COREAON_STATDEP_MASK                                   (1 << 16)
+/* Used by CM_L4CFG_DYNAMICDEP */
+#define OMAP54XX_CUSTEFUSE_DYNDEP_SHIFT                                 17
+#define OMAP54XX_CUSTEFUSE_DYNDEP_WIDTH                                 0x1
+#define OMAP54XX_CUSTEFUSE_DYNDEP_MASK                                  (1 << 17)
+/* Used by CM_DSP_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */
+#define OMAP54XX_CUSTEFUSE_STATDEP_SHIFT                                17
+#define OMAP54XX_CUSTEFUSE_STATDEP_WIDTH                                0x1
+#define OMAP54XX_CUSTEFUSE_STATDEP_MASK                                 (1 << 17)
+/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
+#define OMAP54XX_CUSTOM_SHIFT                                           6
+#define OMAP54XX_CUSTOM_WIDTH                                           0x2
+#define OMAP54XX_CUSTOM_MASK                                            (0x3 << 6)
+/*
+ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
+ * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO1,
+ * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
+ */
+#define OMAP54XX_DCC_EN_SHIFT                                           22
+#define OMAP54XX_DCC_EN_WIDTH                                           0x1
+#define OMAP54XX_DCC_EN_MASK                                            (1 << 22)
+/*
+ * Used by CM_CORE_AON_DEBUG_CM_CORE_AON_FD_TRANS,
+ * CM_CORE_AON_DEBUG_DSS_FD_TRANS, CM_CORE_AON_DEBUG_EMIF_FD_TRANS,
+ * CM_CORE_AON_DEBUG_L4SEC_FD_TRANS
+ */
+#define OMAP54XX_CM_DEBUG_OUT_SHIFT                                     0
+#define OMAP54XX_CM_DEBUG_OUT_WIDTH                                     0xd
+#define OMAP54XX_CM_DEBUG_OUT_MASK                                      (0x1fff << 0)
+/*
+ * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_ABE_FD_TRANS,
+ * CM_CORE_AON_DEBUG_L3INIT_FD_TRANS, CM_CORE_AON_DEBUG_L4PER_FD_TRANS
+ */
+#define OMAP54XX_DEBUG_OUT_0_31_SHIFT                                   0
+#define OMAP54XX_DEBUG_OUT_0_31_WIDTH                                   0x20
+#define OMAP54XX_DEBUG_OUT_0_31_MASK                                    (0xffffffff << 0)
+/*
+ * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_C2C_FD_TRANS,
+ * CM_CORE_AON_DEBUG_COREAON_FD_TRANS, CM_CORE_AON_DEBUG_L4CFG_FD_TRANS
+ */
+#define OMAP54XX_DEBUG_OUT_0_8_SHIFT                                    0
+#define OMAP54XX_DEBUG_OUT_0_8_WIDTH                                    0x9
+#define OMAP54XX_DEBUG_OUT_0_8_MASK                                     (0x1ff << 0)
+/*
+ * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_CUSTEFUSE_FD_TRANS,
+ * CM_CORE_AON_DEBUG_DMA_FD_TRANS, CM_CORE_AON_DEBUG_L3MAIN1_FD_TRANS
+ */
+#define OMAP54XX_DEBUG_OUT_0_4_SHIFT                                    0
+#define OMAP54XX_DEBUG_OUT_0_4_WIDTH                                    0x5
+#define OMAP54XX_DEBUG_OUT_0_4_MASK                                     (0x1f << 0)
+/*
+ * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_DSP_FD_TRANS,
+ * CM_CORE_AON_DEBUG_IPU_FD_TRANS, CM_CORE_AON_DEBUG_MPU_FD_TRANS
+ */
+#define OMAP54XX_DEBUG_OUT_0_5_SHIFT                                    0
+#define OMAP54XX_DEBUG_OUT_0_5_WIDTH                                    0x6
+#define OMAP54XX_DEBUG_OUT_0_5_MASK                                     (0x3f << 0)
+/*
+ * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_CAM_FD_TRANS,
+ * CM_CORE_AON_DEBUG_MIPIEXT_FD_TRANS
+ */
+#define OMAP54XX_DEBUG_OUT_0_10_SHIFT                                   0
+#define OMAP54XX_DEBUG_OUT_0_10_WIDTH                                   0xb
+#define OMAP54XX_DEBUG_OUT_0_10_MASK                                    (0x7ff << 0)
+/*
+ * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_IVA_FD_TRANS,
+ * CM_CORE_AON_DEBUG_L3MAIN2_FD_TRANS
+ */
+#define OMAP54XX_DEBUG_OUT_0_6_SHIFT                                    0
+#define OMAP54XX_DEBUG_OUT_0_6_WIDTH                                    0x7
+#define OMAP54XX_DEBUG_OUT_0_6_MASK                                     (0x7f << 0)
+/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_ABE_FD_TRANS2 */
+#define OMAP54XX_DEBUG_OUT_0_19_SHIFT                                   0
+#define OMAP54XX_DEBUG_OUT_0_19_WIDTH                                   0x14
+#define OMAP54XX_DEBUG_OUT_0_19_MASK                                    (0xfffff << 0)
+/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_GPU_FD_TRANS */
+#define OMAP54XX_DEBUG_OUT_0_9_SHIFT                                    0
+#define OMAP54XX_DEBUG_OUT_0_9_WIDTH                                    0xa
+#define OMAP54XX_DEBUG_OUT_0_9_MASK                                     (0x3ff << 0)
+/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L3INIT_FD_TRANS2 */
+#define OMAP54XX_DEBUG_OUT_0_26_SHIFT                                   0
+#define OMAP54XX_DEBUG_OUT_0_26_WIDTH                                   0x1b
+#define OMAP54XX_DEBUG_OUT_0_26_MASK                                    (0x7ffffff << 0)
+/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L3INSTR_FD_TRANS */
+#define OMAP54XX_DEBUG_OUT_0_13_SHIFT                                   0
+#define OMAP54XX_DEBUG_OUT_0_13_WIDTH                                   0xe
+#define OMAP54XX_DEBUG_OUT_0_13_MASK                                    (0x3fff << 0)
+/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L4PER_FD_TRANS2 */
+#define OMAP54XX_DEBUG_OUT_0_21_SHIFT                                   0
+#define OMAP54XX_DEBUG_OUT_0_21_WIDTH                                   0x16
+#define OMAP54XX_DEBUG_OUT_0_21_MASK                                    (0x3fffff << 0)
+/*
+ * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
+ * CM_SSC_DELTAMSTEP_DPLL_IVA, CM_SSC_DELTAMSTEP_DPLL_MPU,
+ * CM_SSC_DELTAMSTEP_DPLL_PER
+ */
+#define OMAP54XX_DELTAMSTEP_SHIFT                                       0
+#define OMAP54XX_DELTAMSTEP_WIDTH                                       0x14
+#define OMAP54XX_DELTAMSTEP_MASK                                        (0xfffff << 0)
+/*
+ * Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_UNIPRO1,
+ * CM_SSC_DELTAMSTEP_DPLL_UNIPRO2, CM_SSC_DELTAMSTEP_DPLL_USB
+ */
+#define OMAP54XX_DELTAMSTEP_0_20_SHIFT                                  0
+#define OMAP54XX_DELTAMSTEP_0_20_WIDTH                                  0x15
+#define OMAP54XX_DELTAMSTEP_0_20_MASK                                   (0x1fffff << 0)
+/*
+ * Used by CM_DIV_H11_DPLL_CORE, CM_DIV_H11_DPLL_IVA, CM_DIV_H11_DPLL_PER,
+ * CM_DIV_H12_DPLL_CORE, CM_DIV_H12_DPLL_IVA, CM_DIV_H12_DPLL_PER,
+ * CM_DIV_H13_DPLL_CORE, CM_DIV_H13_DPLL_PER, CM_DIV_H14_DPLL_CORE,
+ * CM_DIV_H14_DPLL_PER, CM_DIV_H21_DPLL_CORE, CM_DIV_H22_DPLL_CORE,
+ * CM_DIV_H23_DPLL_CORE, CM_DIV_H24_DPLL_CORE
+ */
+#define OMAP54XX_DIVHS_SHIFT                                            0
+#define OMAP54XX_DIVHS_WIDTH                                            0x6
+#define OMAP54XX_DIVHS_MASK                                             (0x3f << 0)
+/*
+ * Renamed from DIVHS Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
+ * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M3_DPLL_ABE,
+ * CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER
+ */
+#define OMAP54XX_DIVHS_0_4_SHIFT                                        0
+#define OMAP54XX_DIVHS_0_4_WIDTH                                        0x5
+#define OMAP54XX_DIVHS_0_4_MASK                                         (0x1f << 0)
+/*
+ * Renamed from DIVHS Used by CM_DIV_M2_DPLL_UNIPRO1, CM_DIV_M2_DPLL_UNIPRO2,
+ * CM_DIV_M2_DPLL_USB
+ */
+#define OMAP54XX_DIVHS_0_6_SHIFT                                        0
+#define OMAP54XX_DIVHS_0_6_WIDTH                                        0x7
+#define OMAP54XX_DIVHS_0_6_MASK                                         (0x7f << 0)
+/* Used by CM_DLL_CTRL */
+#define OMAP54XX_DLL_OVERRIDE_SHIFT                                     0
+#define OMAP54XX_DLL_OVERRIDE_WIDTH                                     0x1
+#define OMAP54XX_DLL_OVERRIDE_MASK                                      (1 << 0)
+/* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */
+#define OMAP54XX_DLL_OVERRIDE_2_2_SHIFT                                 2
+#define OMAP54XX_DLL_OVERRIDE_2_2_WIDTH                                 0x1
+#define OMAP54XX_DLL_OVERRIDE_2_2_MASK                                  (1 << 2)
+/* Used by CM_SHADOW_FREQ_CONFIG1 */
+#define OMAP54XX_DLL_RESET_SHIFT                                        3
+#define OMAP54XX_DLL_RESET_WIDTH                                        0x1
+#define OMAP54XX_DLL_RESET_MASK                                         (1 << 3)
+/*
+ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
+ * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO1,
+ * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
+ */
+#define OMAP54XX_DPLL_BYP_CLKSEL_SHIFT                                  23
+#define OMAP54XX_DPLL_BYP_CLKSEL_WIDTH                                  0x1
+#define OMAP54XX_DPLL_BYP_CLKSEL_MASK                                   (1 << 23)
+/* Used by CM_CLKSEL_DPLL_CORE */
+#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_SHIFT                            20
+#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_WIDTH                            0x1
+#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_MASK                             (1 << 20)
+/* Used by CM_SHADOW_FREQ_CONFIG1 */
+#define OMAP54XX_DPLL_CORE_DPLL_EN_SHIFT                                8
+#define OMAP54XX_DPLL_CORE_DPLL_EN_WIDTH                                0x3
+#define OMAP54XX_DPLL_CORE_DPLL_EN_MASK                                 (0x7 << 8)
+/* Used by CM_SHADOW_FREQ_CONFIG2 */
+#define OMAP54XX_DPLL_CORE_H12_DIV_SHIFT                                2
+#define OMAP54XX_DPLL_CORE_H12_DIV_WIDTH                                0x6
+#define OMAP54XX_DPLL_CORE_H12_DIV_MASK                                 (0x3f << 2)
+/* Used by CM_SHADOW_FREQ_CONFIG1 */
+#define OMAP54XX_DPLL_CORE_M2_DIV_SHIFT                                 11
+#define OMAP54XX_DPLL_CORE_M2_DIV_WIDTH                                 0x5
+#define OMAP54XX_DPLL_CORE_M2_DIV_MASK                                  (0x1f << 11)
+/*
+ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
+ * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER
+ */
+#define OMAP54XX_DPLL_DIV_SHIFT                                         0
+#define OMAP54XX_DPLL_DIV_WIDTH                                         0x7
+#define OMAP54XX_DPLL_DIV_MASK                                          (0x7f << 0)
+/*
+ * Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_UNIPRO1,
+ * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
+ */
+#define OMAP54XX_DPLL_DIV_0_7_SHIFT                                     0
+#define OMAP54XX_DPLL_DIV_0_7_WIDTH                                     0x8
+#define OMAP54XX_DPLL_DIV_0_7_MASK                                      (0xff << 0)
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
+ */
+#define OMAP54XX_DPLL_DRIFTGUARD_EN_SHIFT                               8
+#define OMAP54XX_DPLL_DRIFTGUARD_EN_WIDTH                               0x1
+#define OMAP54XX_DPLL_DRIFTGUARD_EN_MASK                                (1 << 8)
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
+ * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
+ */
+#define OMAP54XX_DPLL_EN_SHIFT                                          0
+#define OMAP54XX_DPLL_EN_WIDTH                                          0x3
+#define OMAP54XX_DPLL_EN_MASK                                           (0x7 << 0)
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
+ */
+#define OMAP54XX_DPLL_LPMODE_EN_SHIFT                                   10
+#define OMAP54XX_DPLL_LPMODE_EN_WIDTH                                   0x1
+#define OMAP54XX_DPLL_LPMODE_EN_MASK                                    (1 << 10)
+/*
+ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
+ * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER
+ */
+#define OMAP54XX_DPLL_MULT_SHIFT                                        8
+#define OMAP54XX_DPLL_MULT_WIDTH                                        0xb
+#define OMAP54XX_DPLL_MULT_MASK                                         (0x7ff << 8)
+/*
+ * Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_UNIPRO1,
+ * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
+ */
+#define OMAP54XX_DPLL_MULT_UNIPRO1_SHIFT                                8
+#define OMAP54XX_DPLL_MULT_UNIPRO1_WIDTH                                0xc
+#define OMAP54XX_DPLL_MULT_UNIPRO1_MASK                                 (0xfff << 8)
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
+ */
+#define OMAP54XX_DPLL_REGM4XEN_SHIFT                                    11
+#define OMAP54XX_DPLL_REGM4XEN_WIDTH                                    0x1
+#define OMAP54XX_DPLL_REGM4XEN_MASK                                     (1 << 11)
+/* Used by CM_CLKSEL_DPLL_UNIPRO1, CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB */
+#define OMAP54XX_DPLL_SD_DIV_SHIFT                                      24
+#define OMAP54XX_DPLL_SD_DIV_WIDTH                                      0x8
+#define OMAP54XX_DPLL_SD_DIV_MASK                                       (0xff << 24)
+/* Used by CM_CLKSEL_DPLL_UNIPRO1, CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB */
+#define OMAP54XX_DPLL_SELFREQDCO_SHIFT                                  21
+#define OMAP54XX_DPLL_SELFREQDCO_WIDTH                                  0x1
+#define OMAP54XX_DPLL_SELFREQDCO_MASK                                   (1 << 21)
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
+ * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
+ */
+#define OMAP54XX_DPLL_SSC_ACK_SHIFT                                     13
+#define OMAP54XX_DPLL_SSC_ACK_WIDTH                                     0x1
+#define OMAP54XX_DPLL_SSC_ACK_MASK                                      (1 << 13)
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
+ * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
+ */
+#define OMAP54XX_DPLL_SSC_DOWNSPREAD_SHIFT                              14
+#define OMAP54XX_DPLL_SSC_DOWNSPREAD_WIDTH                              0x1
+#define OMAP54XX_DPLL_SSC_DOWNSPREAD_MASK                               (1 << 14)
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
+ * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
+ */
+#define OMAP54XX_DPLL_SSC_EN_SHIFT                                      12
+#define OMAP54XX_DPLL_SSC_EN_WIDTH                                      0x1
+#define OMAP54XX_DPLL_SSC_EN_MASK                                       (1 << 12)
+/* Used by CM_L4CFG_DYNAMICDEP */
+#define OMAP54XX_DSP_DYNDEP_SHIFT                                       1
+#define OMAP54XX_DSP_DYNDEP_WIDTH                                       0x1
+#define OMAP54XX_DSP_DYNDEP_MASK                                        (1 << 1)
+/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */
+#define OMAP54XX_DSP_STATDEP_SHIFT                                      1
+#define OMAP54XX_DSP_STATDEP_WIDTH                                      0x1
+#define OMAP54XX_DSP_STATDEP_MASK                                       (1 << 1)
+/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
+#define OMAP54XX_DSS_DYNDEP_SHIFT                                       8
+#define OMAP54XX_DSS_DYNDEP_WIDTH                                       0x1
+#define OMAP54XX_DSS_DYNDEP_MASK                                        (1 << 8)
+/* Used by CM_DMA_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */
+#define OMAP54XX_DSS_STATDEP_SHIFT                                      8
+#define OMAP54XX_DSS_STATDEP_WIDTH                                      0x1
+#define OMAP54XX_DSS_STATDEP_MASK                                       (1 << 8)
+/*
+ * Used by CM_C2C_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
+ * CM_MIPIEXT_DYNAMICDEP, CM_MPU_DYNAMICDEP
+ */
+#define OMAP54XX_EMIF_DYNDEP_SHIFT                                      4
+#define OMAP54XX_EMIF_DYNDEP_WIDTH                                      0x1
+#define OMAP54XX_EMIF_DYNDEP_MASK                                       (1 << 4)
+/*
+ * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
+ * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
+ * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
+ * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
+ */
+#define OMAP54XX_EMIF_STATDEP_SHIFT                                     4
+#define OMAP54XX_EMIF_STATDEP_WIDTH                                     0x1
+#define OMAP54XX_EMIF_STATDEP_MASK                                      (1 << 4)
+/* Used by CM_SHADOW_FREQ_CONFIG1 */
+#define OMAP54XX_FREQ_UPDATE_SHIFT                                      0
+#define OMAP54XX_FREQ_UPDATE_WIDTH                                      0x1
+#define OMAP54XX_FREQ_UPDATE_MASK                                       (1 << 0)
+/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
+#define OMAP54XX_FUNC_SHIFT                                             16
+#define OMAP54XX_FUNC_WIDTH                                             0xc
+#define OMAP54XX_FUNC_MASK                                              (0xfff << 16)
+/* Used by CM_SHADOW_FREQ_CONFIG2 */
+#define OMAP54XX_GPMC_FREQ_UPDATE_SHIFT                                 0
+#define OMAP54XX_GPMC_FREQ_UPDATE_WIDTH                                 0x1
+#define OMAP54XX_GPMC_FREQ_UPDATE_MASK                                  (1 << 0)
+/* Used by CM_L3MAIN2_DYNAMICDEP */
+#define OMAP54XX_GPU_DYNDEP_SHIFT                                       10
+#define OMAP54XX_GPU_DYNDEP_WIDTH                                       0x1
+#define OMAP54XX_GPU_DYNDEP_MASK                                        (1 << 10)
+/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */
+#define OMAP54XX_GPU_STATDEP_SHIFT                                      10
+#define OMAP54XX_GPU_STATDEP_WIDTH                                      0x1
+#define OMAP54XX_GPU_STATDEP_MASK                                       (1 << 10)
+/*
+ * Used by CM_ABE_AESS_CLKCTRL, CM_ABE_DMIC_CLKCTRL, CM_ABE_L4_ABE_CLKCTRL,
+ * CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, CM_ABE_MCBSP2_CLKCTRL,
+ * CM_ABE_MCBSP3_CLKCTRL, CM_ABE_MCPDM_CLKCTRL, CM_ABE_SLIMBUS1_CLKCTRL,
+ * CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL,
+ * CM_ABE_TIMER8_CLKCTRL, CM_ABE_WD_TIMER3_CLKCTRL, CM_C2C_C2C_CLKCTRL,
+ * CM_C2C_C2C_OCP_FW_CLKCTRL, CM_C2C_MODEM_ICR_CLKCTRL, CM_CAM_CAL_CLKCTRL,
+ * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CM_CORE_AON_PROFILING_CLKCTRL,
+ * CM_CM_CORE_PROFILING_CLKCTRL, CM_COREAON_SMARTREFLEX_CORE_CLKCTRL,
+ * CM_COREAON_SMARTREFLEX_MM_CLKCTRL, CM_COREAON_SMARTREFLEX_MPU_CLKCTRL,
+ * CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL,
+ * CM_DSP_DSP_CLKCTRL, CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL,
+ * CM_EMIF_DMM_CLKCTRL, CM_EMIF_EMIF1_CLKCTRL, CM_EMIF_EMIF2_CLKCTRL,
+ * CM_EMIF_EMIF_OCP_FW_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL,
+ * CM_EMU_MPU_EMU_DBG_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL,
+ * CM_IVA_IVA_CLKCTRL, CM_IVA_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL,
+ * CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
+ * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MPHY_UNIPRO2_CLKCTRL,
+ * CM_L3INIT_OCP2SCP1_CLKCTRL, CM_L3INIT_OCP2SCP3_CLKCTRL,
+ * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_UNIPRO2_CLKCTRL,
+ * CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_OTG_SS_CLKCTRL,
+ * CM_L3INIT_USB_TLL_HS_CLKCTRL, CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL,
+ * CM_L3INSTR_DLL_AGING_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
+ * CM_L3INSTR_L3_MAIN_3_CLKCTRL, CM_L3INSTR_OCP_WP_NOC_CLKCTRL,
+ * CM_L3MAIN1_L3_MAIN_1_CLKCTRL, CM_L3MAIN2_GPMC_CLKCTRL,
+ * CM_L3MAIN2_L3_MAIN_2_CLKCTRL, CM_L3MAIN2_OCMC_RAM_CLKCTRL,
+ * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL,
+ * CM_L4CFG_OCP2SCP2_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
+ * CM_L4CFG_SPINLOCK_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
+ * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
+ * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL,
+ * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL,
+ * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL,
+ * CM_L4PER_L4_PER_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
+ * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMC3_CLKCTRL,
+ * CM_L4PER_MMC4_CLKCTRL, CM_L4PER_MMC5_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL,
+ * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL,
+ * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_L4PER_UART1_CLKCTRL,
+ * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL,
+ * CM_L4PER_UART5_CLKCTRL, CM_L4PER_UART6_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
+ * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
+ * CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_L4SEC_FPKA_CLKCTRL, CM_L4SEC_RNG_CLKCTRL,
+ * CM_L4SEC_SHA2MD5_CLKCTRL, CM_MIPIEXT_LLI_CLKCTRL,
+ * CM_MIPIEXT_LLI_OCP_FW_CLKCTRL, CM_MIPIEXT_MPHY_CLKCTRL, CM_MPU_MPU_CLKCTRL,
+ * CM_MPU_MPU_MPU_DBG_CLKCTRL, CM_WKUPAON_COUNTER_32K_CLKCTRL,
+ * CM_WKUPAON_GPIO1_CLKCTRL, CM_WKUPAON_KBD_CLKCTRL,
+ * CM_WKUPAON_L4_WKUP_CLKCTRL, CM_WKUPAON_SAR_RAM_CLKCTRL,
+ * CM_WKUPAON_TIMER12_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL,
+ * CM_WKUPAON_WD_TIMER1_CLKCTRL, CM_WKUPAON_WD_TIMER2_CLKCTRL
+ */
+#define OMAP54XX_IDLEST_SHIFT                                           16
+#define OMAP54XX_IDLEST_WIDTH                                           0x2
+#define OMAP54XX_IDLEST_MASK                                            (0x3 << 16)
+/* Used by CM_L3MAIN2_DYNAMICDEP */
+#define OMAP54XX_IPU_DYNDEP_SHIFT                                       0
+#define OMAP54XX_IPU_DYNDEP_WIDTH                                       0x1
+#define OMAP54XX_IPU_DYNDEP_MASK                                        (1 << 0)
+/* Used by CM_DMA_STATICDEP, CM_MPU_STATICDEP */
+#define OMAP54XX_IPU_STATDEP_SHIFT                                      0
+#define OMAP54XX_IPU_STATDEP_WIDTH                                      0x1
+#define OMAP54XX_IPU_STATDEP_MASK                                       (1 << 0)
+/* Used by CM_DSP_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP */
+#define OMAP54XX_IVA_DYNDEP_SHIFT                                       2
+#define OMAP54XX_IVA_DYNDEP_WIDTH                                       0x1
+#define OMAP54XX_IVA_DYNDEP_MASK                                        (1 << 2)
+/*
+ * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
+ * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
+ * CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
+ */
+#define OMAP54XX_IVA_STATDEP_SHIFT                                      2
+#define OMAP54XX_IVA_STATDEP_WIDTH                                      0x1
+#define OMAP54XX_IVA_STATDEP_MASK                                       (1 << 2)
+/* Used by CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
+#define OMAP54XX_L3INIT_DYNDEP_SHIFT                                    7
+#define OMAP54XX_L3INIT_DYNDEP_WIDTH                                    0x1
+#define OMAP54XX_L3INIT_DYNDEP_MASK                                     (1 << 7)
+/*
+ * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
+ * CM_IPU_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
+ */
+#define OMAP54XX_L3INIT_STATDEP_SHIFT                                   7
+#define OMAP54XX_L3INIT_STATDEP_WIDTH                                   0x1
+#define OMAP54XX_L3INIT_STATDEP_MASK                                    (1 << 7)
+/*
+ * Used by CM_DSP_DYNAMICDEP, CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP,
+ * CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP
+ */
+#define OMAP54XX_L3MAIN1_DYNDEP_SHIFT                                   5
+#define OMAP54XX_L3MAIN1_DYNDEP_WIDTH                                   0x1
+#define OMAP54XX_L3MAIN1_DYNDEP_MASK                                    (1 << 5)
+/*
+ * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
+ * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
+ * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
+ * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
+ */
+#define OMAP54XX_L3MAIN1_STATDEP_SHIFT                                  5
+#define OMAP54XX_L3MAIN1_STATDEP_WIDTH                                  0x1
+#define OMAP54XX_L3MAIN1_STATDEP_MASK                                   (1 << 5)
+/*
+ * Used by CM_C2C_DYNAMICDEP, CM_CAM_DYNAMICDEP, CM_DMA_DYNAMICDEP,
+ * CM_DSS_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GPU_DYNAMICDEP, CM_IPU_DYNAMICDEP,
+ * CM_IVA_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP,
+ * CM_L4CFG_DYNAMICDEP, CM_L4SEC_DYNAMICDEP, CM_MIPIEXT_DYNAMICDEP
+ */
+#define OMAP54XX_L3MAIN2_DYNDEP_SHIFT                                   6
+#define OMAP54XX_L3MAIN2_DYNDEP_WIDTH                                   0x1
+#define OMAP54XX_L3MAIN2_DYNDEP_MASK                                    (1 << 6)
+/*
+ * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
+ * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
+ * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
+ * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
+ */
+#define OMAP54XX_L3MAIN2_STATDEP_SHIFT                                  6
+#define OMAP54XX_L3MAIN2_STATDEP_WIDTH                                  0x1
+#define OMAP54XX_L3MAIN2_STATDEP_MASK                                   (1 << 6)
+/* Used by CM_L3MAIN1_DYNAMICDEP */
+#define OMAP54XX_L4CFG_DYNDEP_SHIFT                                     12
+#define OMAP54XX_L4CFG_DYNDEP_WIDTH                                     0x1
+#define OMAP54XX_L4CFG_DYNDEP_MASK                                      (1 << 12)
+/*
+ * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
+ * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
+ */
+#define OMAP54XX_L4CFG_STATDEP_SHIFT                                    12
+#define OMAP54XX_L4CFG_STATDEP_WIDTH                                    0x1
+#define OMAP54XX_L4CFG_STATDEP_MASK                                     (1 << 12)
+/* Used by CM_L3MAIN2_DYNAMICDEP */
+#define OMAP54XX_L4PER_DYNDEP_SHIFT                                     13
+#define OMAP54XX_L4PER_DYNDEP_WIDTH                                     0x1
+#define OMAP54XX_L4PER_DYNDEP_MASK                                      (1 << 13)
+/*
+ * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
+ * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
+ * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
+ */
+#define OMAP54XX_L4PER_STATDEP_SHIFT                                    13
+#define OMAP54XX_L4PER_STATDEP_WIDTH                                    0x1
+#define OMAP54XX_L4PER_STATDEP_MASK                                     (1 << 13)
+/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
+#define OMAP54XX_L4SEC_DYNDEP_SHIFT                                     14
+#define OMAP54XX_L4SEC_DYNDEP_WIDTH                                     0x1
+#define OMAP54XX_L4SEC_DYNDEP_MASK                                      (1 << 14)
+/*
+ * Used by CM_DMA_STATICDEP, CM_IPU_STATICDEP, CM_L3INIT_STATICDEP,
+ * CM_MPU_STATICDEP
+ */
+#define OMAP54XX_L4SEC_STATDEP_SHIFT                                    14
+#define OMAP54XX_L4SEC_STATDEP_WIDTH                                    0x1
+#define OMAP54XX_L4SEC_STATDEP_MASK                                     (1 << 14)
+/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
+#define OMAP54XX_MIPIEXT_DYNDEP_SHIFT                                   21
+#define OMAP54XX_MIPIEXT_DYNDEP_WIDTH                                   0x1
+#define OMAP54XX_MIPIEXT_DYNDEP_MASK                                    (1 << 21)
+/* Used by CM_MPU_STATICDEP */
+#define OMAP54XX_MIPIEXT_STATDEP_SHIFT                                  21
+#define OMAP54XX_MIPIEXT_STATDEP_WIDTH                                  0x1
+#define OMAP54XX_MIPIEXT_STATDEP_MASK                                   (1 << 21)
+/*
+ * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
+ * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
+ * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO1,
+ * CM_SSC_MODFREQDIV_DPLL_UNIPRO2, CM_SSC_MODFREQDIV_DPLL_USB
+ */
+#define OMAP54XX_MODFREQDIV_EXPONENT_SHIFT                              8
+#define OMAP54XX_MODFREQDIV_EXPONENT_WIDTH                              0x3
+#define OMAP54XX_MODFREQDIV_EXPONENT_MASK                               (0x7 << 8)
+/*
+ * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
+ * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
+ * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO1,
+ * CM_SSC_MODFREQDIV_DPLL_UNIPRO2, CM_SSC_MODFREQDIV_DPLL_USB
+ */
+#define OMAP54XX_MODFREQDIV_MANTISSA_SHIFT                              0
+#define OMAP54XX_MODFREQDIV_MANTISSA_WIDTH                              0x7
+#define OMAP54XX_MODFREQDIV_MANTISSA_MASK                               (0x7f << 0)
+/*
+ * Used by CM_ABE_AESS_CLKCTRL, CM_ABE_DMIC_CLKCTRL, CM_ABE_L4_ABE_CLKCTRL,
+ * CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, CM_ABE_MCBSP2_CLKCTRL,
+ * CM_ABE_MCBSP3_CLKCTRL, CM_ABE_MCPDM_CLKCTRL, CM_ABE_SLIMBUS1_CLKCTRL,
+ * CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL,
+ * CM_ABE_TIMER8_CLKCTRL, CM_ABE_WD_TIMER3_CLKCTRL, CM_C2C_C2C_CLKCTRL,
+ * CM_C2C_C2C_OCP_FW_CLKCTRL, CM_C2C_MODEM_ICR_CLKCTRL, CM_CAM_CAL_CLKCTRL,
+ * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CM_CORE_AON_PROFILING_CLKCTRL,
+ * CM_CM_CORE_PROFILING_CLKCTRL, CM_COREAON_SMARTREFLEX_CORE_CLKCTRL,
+ * CM_COREAON_SMARTREFLEX_MM_CLKCTRL, CM_COREAON_SMARTREFLEX_MPU_CLKCTRL,
+ * CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL,
+ * CM_DSP_DSP_CLKCTRL, CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL,
+ * CM_EMIF_DMM_CLKCTRL, CM_EMIF_EMIF1_CLKCTRL, CM_EMIF_EMIF2_CLKCTRL,
+ * CM_EMIF_EMIF_OCP_FW_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL,
+ * CM_EMU_MPU_EMU_DBG_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL,
+ * CM_IVA_IVA_CLKCTRL, CM_IVA_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL,
+ * CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
+ * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MPHY_UNIPRO2_CLKCTRL,
+ * CM_L3INIT_OCP2SCP1_CLKCTRL, CM_L3INIT_OCP2SCP3_CLKCTRL,
+ * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_UNIPRO2_CLKCTRL,
+ * CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_OTG_SS_CLKCTRL,
+ * CM_L3INIT_USB_TLL_HS_CLKCTRL, CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL,
+ * CM_L3INSTR_DLL_AGING_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
+ * CM_L3INSTR_L3_MAIN_3_CLKCTRL, CM_L3INSTR_OCP_WP_NOC_CLKCTRL,
+ * CM_L3MAIN1_L3_MAIN_1_CLKCTRL, CM_L3MAIN2_GPMC_CLKCTRL,
+ * CM_L3MAIN2_L3_MAIN_2_CLKCTRL, CM_L3MAIN2_OCMC_RAM_CLKCTRL,
+ * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL,
+ * CM_L4CFG_OCP2SCP2_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
+ * CM_L4CFG_SPINLOCK_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
+ * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
+ * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL,
+ * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL,
+ * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL,
+ * CM_L4PER_L4_PER_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
+ * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMC3_CLKCTRL,
+ * CM_L4PER_MMC4_CLKCTRL, CM_L4PER_MMC5_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL,
+ * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL,
+ * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_L4PER_UART1_CLKCTRL,
+ * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL,
+ * CM_L4PER_UART5_CLKCTRL, CM_L4PER_UART6_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
+ * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
+ * CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_L4SEC_FPKA_CLKCTRL, CM_L4SEC_RNG_CLKCTRL,
+ * CM_L4SEC_SHA2MD5_CLKCTRL, CM_MIPIEXT_LLI_CLKCTRL,
+ * CM_MIPIEXT_LLI_OCP_FW_CLKCTRL, CM_MIPIEXT_MPHY_CLKCTRL, CM_MPU_MPU_CLKCTRL,
+ * CM_MPU_MPU_MPU_DBG_CLKCTRL, CM_WKUPAON_COUNTER_32K_CLKCTRL,
+ * CM_WKUPAON_GPIO1_CLKCTRL, CM_WKUPAON_KBD_CLKCTRL,
+ * CM_WKUPAON_L4_WKUP_CLKCTRL, CM_WKUPAON_SAR_RAM_CLKCTRL,
+ * CM_WKUPAON_TIMER12_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL,
+ * CM_WKUPAON_WD_TIMER1_CLKCTRL, CM_WKUPAON_WD_TIMER2_CLKCTRL
+ */
+#define OMAP54XX_MODULEMODE_SHIFT                                       0
+#define OMAP54XX_MODULEMODE_WIDTH                                       0x2
+#define OMAP54XX_MODULEMODE_MASK                                        (0x3 << 0)
+/* Used by CM_L4CFG_DYNAMICDEP */
+#define OMAP54XX_MPU_DYNDEP_SHIFT                                       19
+#define OMAP54XX_MPU_DYNDEP_WIDTH                                       0x1
+#define OMAP54XX_MPU_DYNDEP_MASK                                        (1 << 19)
+/* Used by CM_DSS_DSS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_SHIFT                              11
+#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_WIDTH                              0x1
+#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_MASK                               (1 << 11)
+/* Renamed from OPTFCLKEN_32KHZ_CLK Used by CM_L3INIT_MMC1_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_SHIFT                          8
+#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_WIDTH                          0x1
+#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_MASK                           (1 << 8)
+/* Used by CM_DSS_DSS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_SHIFT                              9
+#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_WIDTH                              0x1
+#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_MASK                               (1 << 9)
+/* Used by CM_COREAON_USB_PHY_CORE_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_CLK32K_SHIFT                                 8
+#define OMAP54XX_OPTFCLKEN_CLK32K_WIDTH                                 0x1
+#define OMAP54XX_OPTFCLKEN_CLK32K_MASK                                  (1 << 8)
+/* Used by CM_CAM_ISS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_CTRLCLK_SHIFT                                8
+#define OMAP54XX_OPTFCLKEN_CTRLCLK_WIDTH                                0x1
+#define OMAP54XX_OPTFCLKEN_CTRLCLK_MASK                                 (1 << 8)
+/*
+ * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL,
+ * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL,
+ * CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL, CM_WKUPAON_GPIO1_CLKCTRL
+ */
+#define OMAP54XX_OPTFCLKEN_DBCLK_SHIFT                                  8
+#define OMAP54XX_OPTFCLKEN_DBCLK_WIDTH                                  0x1
+#define OMAP54XX_OPTFCLKEN_DBCLK_MASK                                   (1 << 8)
+/* Used by CM_EMIF_EMIF_DLL_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_DLL_CLK_SHIFT                                8
+#define OMAP54XX_OPTFCLKEN_DLL_CLK_WIDTH                                0x1
+#define OMAP54XX_OPTFCLKEN_DLL_CLK_MASK                                 (1 << 8)
+/* Used by CM_DSS_DSS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_DSSCLK_SHIFT                                 8
+#define OMAP54XX_OPTFCLKEN_DSSCLK_WIDTH                                 0x1
+#define OMAP54XX_OPTFCLKEN_DSSCLK_MASK                                  (1 << 8)
+/* Used by CM_ABE_SLIMBUS1_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_FCLK0_SHIFT                                  8
+#define OMAP54XX_OPTFCLKEN_FCLK0_WIDTH                                  0x1
+#define OMAP54XX_OPTFCLKEN_FCLK0_MASK                                   (1 << 8)
+/* Used by CM_ABE_SLIMBUS1_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_FCLK1_SHIFT                                  9
+#define OMAP54XX_OPTFCLKEN_FCLK1_WIDTH                                  0x1
+#define OMAP54XX_OPTFCLKEN_FCLK1_MASK                                   (1 << 9)
+/* Used by CM_ABE_SLIMBUS1_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_FCLK2_SHIFT                                  10
+#define OMAP54XX_OPTFCLKEN_FCLK2_WIDTH                                  0x1
+#define OMAP54XX_OPTFCLKEN_FCLK2_MASK                                   (1 << 10)
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_SHIFT                            15
+#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_WIDTH                            0x1
+#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_MASK                             (1 << 15)
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT                        13
+#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_WIDTH                        0x1
+#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_MASK                         (1 << 13)
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT                        14
+#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_WIDTH                        0x1
+#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_MASK                         (1 << 14)
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_SHIFT                        7
+#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_WIDTH                        0x1
+#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_MASK                         (1 << 7)
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT                         11
+#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_WIDTH                         0x1
+#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_MASK                          (1 << 11)
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT                         12
+#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_WIDTH                         0x1
+#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_MASK                          (1 << 12)
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_SHIFT                         6
+#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_WIDTH                         0x1
+#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_MASK                          (1 << 6)
+/* Used by CM_L3INIT_USB_OTG_SS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_REFCLK960M_SHIFT                             8
+#define OMAP54XX_OPTFCLKEN_REFCLK960M_WIDTH                             0x1
+#define OMAP54XX_OPTFCLKEN_REFCLK960M_MASK                              (1 << 8)
+/* Used by CM_L3INIT_SATA_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_REF_CLK_SHIFT                                8
+#define OMAP54XX_OPTFCLKEN_REF_CLK_WIDTH                                0x1
+#define OMAP54XX_OPTFCLKEN_REF_CLK_MASK                                 (1 << 8)
+/* Used by CM_WKUPAON_SCRM_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_SCRM_CORE_SHIFT                              8
+#define OMAP54XX_OPTFCLKEN_SCRM_CORE_WIDTH                              0x1
+#define OMAP54XX_OPTFCLKEN_SCRM_CORE_MASK                               (1 << 8)
+/* Used by CM_WKUPAON_SCRM_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_SCRM_PER_SHIFT                               9
+#define OMAP54XX_OPTFCLKEN_SCRM_PER_WIDTH                               0x1
+#define OMAP54XX_OPTFCLKEN_SCRM_PER_MASK                                (1 << 9)
+/* Used by CM_ABE_SLIMBUS1_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_SHIFT                            11
+#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_WIDTH                            0x1
+#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_MASK                             (1 << 11)
+/* Used by CM_DSS_DSS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_SYS_CLK_SHIFT                                10
+#define OMAP54XX_OPTFCLKEN_SYS_CLK_WIDTH                                0x1
+#define OMAP54XX_OPTFCLKEN_SYS_CLK_MASK                                 (1 << 10)
+/* Used by CM_MIPIEXT_LLI_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_SHIFT                              8
+#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_WIDTH                              0x1
+#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_MASK                               (1 << 8)
+/* Used by CM_MIPIEXT_LLI_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_SHIFT                           9
+#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_WIDTH                           0x1
+#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_MASK                            (1 << 9)
+/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_SHIFT                            8
+#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_WIDTH                            0x1
+#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_MASK                             (1 << 8)
+/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_SHIFT                            9
+#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_WIDTH                            0x1
+#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_MASK                             (1 << 9)
+/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_SHIFT                            10
+#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_WIDTH                            0x1
+#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_MASK                             (1 << 10)
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_SHIFT                            8
+#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_WIDTH                            0x1
+#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_MASK                             (1 << 8)
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_SHIFT                            9
+#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_WIDTH                            0x1
+#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_MASK                             (1 << 9)
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_SHIFT                            10
+#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_WIDTH                            0x1
+#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_MASK                             (1 << 10)
+/* Used by CM_CORE_AON_DEBUG_OUT, CM_CORE_DEBUG_OUT */
+#define OMAP54XX_OUTPUT_SHIFT                                           0
+#define OMAP54XX_OUTPUT_WIDTH                                           0x20
+#define OMAP54XX_OUTPUT_MASK                                            (0xffffffff << 0)
+/* Used by CM_CLKSEL_ABE */
+#define OMAP54XX_PAD_CLKS_GATE_SHIFT                                    8
+#define OMAP54XX_PAD_CLKS_GATE_WIDTH                                    0x1
+#define OMAP54XX_PAD_CLKS_GATE_MASK                                     (1 << 8)
+/* Used by CM_RESTORE_ST */
+#define OMAP54XX_PHASE1_COMPLETED_SHIFT                                 0
+#define OMAP54XX_PHASE1_COMPLETED_WIDTH                                 0x1
+#define OMAP54XX_PHASE1_COMPLETED_MASK                                  (1 << 0)
+/* Used by CM_RESTORE_ST */
+#define OMAP54XX_PHASE2A_COMPLETED_SHIFT                                1
+#define OMAP54XX_PHASE2A_COMPLETED_WIDTH                                0x1
+#define OMAP54XX_PHASE2A_COMPLETED_MASK                                 (1 << 1)
+/* Used by CM_RESTORE_ST */
+#define OMAP54XX_PHASE2B_COMPLETED_SHIFT                                2
+#define OMAP54XX_PHASE2B_COMPLETED_WIDTH                                0x1
+#define OMAP54XX_PHASE2B_COMPLETED_MASK                                 (1 << 2)
+/* Used by CM_DYN_DEP_PRESCAL */
+#define OMAP54XX_PRESCAL_SHIFT                                          0
+#define OMAP54XX_PRESCAL_WIDTH                                          0x6
+#define OMAP54XX_PRESCAL_MASK                                           (0x3f << 0)
+/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
+#define OMAP54XX_R_RTL_SHIFT                                            11
+#define OMAP54XX_R_RTL_WIDTH                                            0x5
+#define OMAP54XX_R_RTL_MASK                                             (0x1f << 11)
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_TLL_HS_CLKCTRL */
+#define OMAP54XX_SAR_MODE_SHIFT                                         4
+#define OMAP54XX_SAR_MODE_WIDTH                                         0x1
+#define OMAP54XX_SAR_MODE_MASK                                          (1 << 4)
+/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
+#define OMAP54XX_SCHEME_SHIFT                                           30
+#define OMAP54XX_SCHEME_WIDTH                                           0x2
+#define OMAP54XX_SCHEME_MASK                                            (0x3 << 30)
+/* Used by CM_L4CFG_DYNAMICDEP */
+#define OMAP54XX_SDMA_DYNDEP_SHIFT                                      11
+#define OMAP54XX_SDMA_DYNDEP_WIDTH                                      0x1
+#define OMAP54XX_SDMA_DYNDEP_MASK                                       (1 << 11)
+/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */
+#define OMAP54XX_SDMA_STATDEP_SHIFT                                     11
+#define OMAP54XX_SDMA_STATDEP_WIDTH                                     0x1
+#define OMAP54XX_SDMA_STATDEP_MASK                                      (1 << 11)
+/* Used by CM_CORE_AON_DEBUG_CFG */
+#define OMAP54XX_SEL0_SHIFT                                             0
+#define OMAP54XX_SEL0_WIDTH                                             0x7
+#define OMAP54XX_SEL0_MASK                                              (0x7f << 0)
+/* Renamed from SEL0 Used by CM_CORE_DEBUG_CFG */
+#define OMAP54XX_SEL0_0_7_SHIFT                                         0
+#define OMAP54XX_SEL0_0_7_WIDTH                                         0x8
+#define OMAP54XX_SEL0_0_7_MASK                                          (0xff << 0)
+/* Used by CM_CORE_AON_DEBUG_CFG */
+#define OMAP54XX_SEL1_SHIFT                                             8
+#define OMAP54XX_SEL1_WIDTH                                             0x7
+#define OMAP54XX_SEL1_MASK                                              (0x7f << 8)
+/* Renamed from SEL1 Used by CM_CORE_DEBUG_CFG */
+#define OMAP54XX_SEL1_CORE_DEBUG_CFG_SHIFT                              8
+#define OMAP54XX_SEL1_CORE_DEBUG_CFG_WIDTH                              0x8
+#define OMAP54XX_SEL1_CORE_DEBUG_CFG_MASK                               (0xff << 8)
+/* Used by CM_CORE_AON_DEBUG_CFG */
+#define OMAP54XX_SEL2_SHIFT                                             16
+#define OMAP54XX_SEL2_WIDTH                                             0x7
+#define OMAP54XX_SEL2_MASK                                              (0x7f << 16)
+/* Renamed from SEL2 Used by CM_CORE_DEBUG_CFG */
+#define OMAP54XX_SEL2_CORE_DEBUG_CFG_SHIFT                              16
+#define OMAP54XX_SEL2_CORE_DEBUG_CFG_WIDTH                              0x8
+#define OMAP54XX_SEL2_CORE_DEBUG_CFG_MASK                               (0xff << 16)
+/* Used by CM_CORE_AON_DEBUG_CFG */
+#define OMAP54XX_SEL3_SHIFT                                             24
+#define OMAP54XX_SEL3_WIDTH                                             0x7
+#define OMAP54XX_SEL3_MASK                                              (0x7f << 24)
+/* Renamed from SEL3 Used by CM_CORE_DEBUG_CFG */
+#define OMAP54XX_SEL3_CORE_DEBUG_CFG_SHIFT                              24
+#define OMAP54XX_SEL3_CORE_DEBUG_CFG_WIDTH                              0x8
+#define OMAP54XX_SEL3_CORE_DEBUG_CFG_MASK                               (0xff << 24)
+/* Used by CM_CLKSEL_ABE */
+#define OMAP54XX_SLIMBUS1_CLK_GATE_SHIFT                                10
+#define OMAP54XX_SLIMBUS1_CLK_GATE_WIDTH                                0x1
+#define OMAP54XX_SLIMBUS1_CLK_GATE_MASK                                 (1 << 10)
+/*
+ * Used by CM_ABE_AESS_CLKCTRL, CM_C2C_C2C_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
+ * CM_CAM_ISS_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL, CM_DSP_DSP_CLKCTRL,
+ * CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL,
+ * CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL, CM_IVA_IVA_CLKCTRL,
+ * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_IEEE1500_2_OCP_CLKCTRL,
+ * CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_SATA_CLKCTRL,
+ * CM_L3INIT_UNIPRO2_CLKCTRL, CM_L3INIT_USB_HOST_HS_CLKCTRL,
+ * CM_L3INIT_USB_OTG_SS_CLKCTRL, CM_L4SEC_DMA_CRYPTO_CLKCTRL,
+ * CM_MIPIEXT_LLI_CLKCTRL, CM_MPU_MPU_CLKCTRL
+ */
+#define OMAP54XX_STBYST_SHIFT                                           18
+#define OMAP54XX_STBYST_WIDTH                                           0x1
+#define OMAP54XX_STBYST_MASK                                            (1 << 18)
+/*
+ * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA,
+ * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1,
+ * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB
+ */
+#define OMAP54XX_ST_DPLL_CLK_SHIFT                                      0
+#define OMAP54XX_ST_DPLL_CLK_WIDTH                                      0x1
+#define OMAP54XX_ST_DPLL_CLK_MASK                                       (1 << 0)
+/*
+ * Used by CM_CLKDCOLDO_DPLL_UNIPRO1, CM_CLKDCOLDO_DPLL_UNIPRO2,
+ * CM_CLKDCOLDO_DPLL_USB
+ */
+#define OMAP54XX_ST_DPLL_CLKDCOLDO_SHIFT                                9
+#define OMAP54XX_ST_DPLL_CLKDCOLDO_WIDTH                                0x1
+#define OMAP54XX_ST_DPLL_CLKDCOLDO_MASK                                 (1 << 9)
+/*
+ * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA,
+ * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1,
+ * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB
+ */
+#define OMAP54XX_ST_DPLL_INIT_SHIFT                                     4
+#define OMAP54XX_ST_DPLL_INIT_WIDTH                                     0x1
+#define OMAP54XX_ST_DPLL_INIT_MASK                                      (1 << 4)
+/*
+ * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA,
+ * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1,
+ * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB
+ */
+#define OMAP54XX_ST_DPLL_MODE_SHIFT                                     1
+#define OMAP54XX_ST_DPLL_MODE_WIDTH                                     0x3
+#define OMAP54XX_ST_DPLL_MODE_MASK                                      (0x7 << 1)
+/* Used by CM_CLKSEL_SYS */
+#define OMAP54XX_SYS_CLKSEL_SHIFT                                       0
+#define OMAP54XX_SYS_CLKSEL_WIDTH                                       0x3
+#define OMAP54XX_SYS_CLKSEL_MASK                                        (0x7 << 0)
+/*
+ * Used by CM_C2C_DYNAMICDEP, CM_DSP_DYNAMICDEP, CM_EMU_DYNAMICDEP,
+ * CM_IPU_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP,
+ * CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP, CM_MIPIEXT_DYNAMICDEP,
+ * CM_MPU_DYNAMICDEP
+ */
+#define OMAP54XX_WINDOWSIZE_SHIFT                                       24
+#define OMAP54XX_WINDOWSIZE_WIDTH                                       0x4
+#define OMAP54XX_WINDOWSIZE_MASK                                        (0xf << 24)
+/* Used by CM_L3MAIN1_DYNAMICDEP */
+#define OMAP54XX_WKUPAON_DYNDEP_SHIFT                                   15
+#define OMAP54XX_WKUPAON_DYNDEP_WIDTH                                   0x1
+#define OMAP54XX_WKUPAON_DYNDEP_MASK                                    (1 << 15)
+/*
+ * Used by CM_DMA_STATICDEP, CM_DSP_STATICDEP, CM_IPU_STATICDEP,
+ * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP
+ */
+#define OMAP54XX_WKUPAON_STATDEP_SHIFT                                  15
+#define OMAP54XX_WKUPAON_STATDEP_WIDTH                                  0x1
+#define OMAP54XX_WKUPAON_STATDEP_MASK                                   (1 << 15)
+/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
+#define OMAP54XX_X_MAJOR_SHIFT                                          8
+#define OMAP54XX_X_MAJOR_WIDTH                                          0x3
+#define OMAP54XX_X_MAJOR_MASK                                           (0x7 << 8)
+/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
+#define OMAP54XX_Y_MINOR_SHIFT                                          0
+#define OMAP54XX_Y_MINOR_WIDTH                                          0x6
+#define OMAP54XX_Y_MINOR_MASK                                           (0x3f << 0)
+#endif
diff --git a/arch/arm/mach-omap2/cm1_44xx.h b/arch/arm/mach-omap2/cm1_44xx.h
index 1bc00dc4876c..5ae8fe39d6ee 100644
--- a/arch/arm/mach-omap2/cm1_44xx.h
+++ b/arch/arm/mach-omap2/cm1_44xx.h
@@ -25,6 +25,8 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
 #define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
+#include "cm_44xx_54xx.h"
 /* CM1 base address */
 #define OMAP4430_CM1_BASE               0x4a004000
@@ -217,9 +219,4 @@
 #define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET               0x0088
 #define OMAP4430_CM1_ABE_WDT3_CLKCTRL                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088)
-/* Function prototypes */
-extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
-extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);
-extern u32 omap4_cm1_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
 #endif
diff --git a/arch/arm/mach-omap2/cm1_54xx.h b/arch/arm/mach-omap2/cm1_54xx.h
new file mode 100644
index 000000000000..90b3348e6672
--- /dev/null
+++ b/arch/arm/mach-omap2/cm1_54xx.h
@@ -0,0 +1,213 @@
+/*
+ * OMAP54xx CM1 instance offset macros
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#ifndef __ARCH_ARM_MACH_OMAP2_CM1_54XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM1_54XX_H
+#include "cm_44xx_54xx.h"
+/* CM1 base address */
+#define OMAP54XX_CM_CORE_AON_BASE               0x4a004000
+#define OMAP54XX_CM_CORE_AON_REGADDR(inst, reg)                         \
+        OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE + (inst) + (reg))
+/* CM_CORE_AON instances */
+#define OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST    0x0000
+#define OMAP54XX_CM_CORE_AON_CKGEN_INST         0x0100
+#define OMAP54XX_CM_CORE_AON_MPU_INST           0x0300
+#define OMAP54XX_CM_CORE_AON_DSP_INST           0x0400
+#define OMAP54XX_CM_CORE_AON_ABE_INST           0x0500
+#define OMAP54XX_CM_CORE_AON_RESTORE_INST       0x0e00
+#define OMAP54XX_CM_CORE_AON_INSTR_INST         0x0f00
+/* CM_CORE_AON clockdomain register offsets (from instance start) */
+#define OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS     0x0000
+#define OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS     0x0000
+#define OMAP54XX_CM_CORE_AON_ABE_ABE_CDOFFS     0x0000
+/* CM_CORE_AON */
+/* CM_CORE_AON.OCP_SOCKET_CM_CORE_AON register offsets */
+#define OMAP54XX_REVISION_CM_CORE_AON_OFFSET                    0x0000
+#define OMAP54XX_CM_CM_CORE_AON_PROFILING_CLKCTRL_OFFSET        0x0040
+#define OMAP54XX_CM_CM_CORE_AON_PROFILING_CLKCTRL               OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST, 0x0040)
+#define OMAP54XX_CM_CORE_AON_DEBUG_CFG_OFFSET                   0x0080
+#define OMAP54XX_CM_CORE_AON_DEBUG_OUT_OFFSET                   0x0084
+#define OMAP54XX_CM_CORE_AON_DEBUG_MPU_FD_TRANS_OFFSET          0x0090
+#define OMAP54XX_CM_CORE_AON_DEBUG_DSP_FD_TRANS_OFFSET          0x0094
+#define OMAP54XX_CM_CORE_AON_DEBUG_ABE_FD_TRANS_OFFSET          0x0098
+#define OMAP54XX_CM_CORE_AON_DEBUG_ABE_FD_TRANS2_OFFSET         0x009c
+#define OMAP54XX_CM_CORE_AON_DEBUG_CM_CORE_AON_FD_TRANS_OFFSET  0x00a0
+#define OMAP54XX_CM_CORE_AON_DEBUG_C2C_FD_TRANS_OFFSET          0x00a4
+#define OMAP54XX_CM_CORE_AON_DEBUG_CAM_FD_TRANS_OFFSET          0x00a8
+#define OMAP54XX_CM_CORE_AON_DEBUG_COREAON_FD_TRANS_OFFSET      0x00ac
+#define OMAP54XX_CM_CORE_AON_DEBUG_CUSTEFUSE_FD_TRANS_OFFSET    0x00b0
+#define OMAP54XX_CM_CORE_AON_DEBUG_DMA_FD_TRANS_OFFSET          0x00b4
+#define OMAP54XX_CM_CORE_AON_DEBUG_DSS_FD_TRANS_OFFSET          0x00b8
+#define OMAP54XX_CM_CORE_AON_DEBUG_EMIF_FD_TRANS_OFFSET         0x00bc
+#define OMAP54XX_CM_CORE_AON_DEBUG_GPU_FD_TRANS_OFFSET          0x00c0
+#define OMAP54XX_CM_CORE_AON_DEBUG_IPU_FD_TRANS_OFFSET          0x00c4
+#define OMAP54XX_CM_CORE_AON_DEBUG_IVA_FD_TRANS_OFFSET          0x00c8
+#define OMAP54XX_CM_CORE_AON_DEBUG_L3INIT_FD_TRANS_OFFSET       0x00cc
+#define OMAP54XX_CM_CORE_AON_DEBUG_L3INIT_FD_TRANS2_OFFSET      0x00d0
+#define OMAP54XX_CM_CORE_AON_DEBUG_L3INSTR_FD_TRANS_OFFSET      0x00d4
+#define OMAP54XX_CM_CORE_AON_DEBUG_L3MAIN1_FD_TRANS_OFFSET      0x00d8
+#define OMAP54XX_CM_CORE_AON_DEBUG_L3MAIN2_FD_TRANS_OFFSET      0x00dc
+#define OMAP54XX_CM_CORE_AON_DEBUG_L4CFG_FD_TRANS_OFFSET        0x00e0
+#define OMAP54XX_CM_CORE_AON_DEBUG_L4PER_FD_TRANS_OFFSET        0x00e4
+#define OMAP54XX_CM_CORE_AON_DEBUG_L4PER_FD_TRANS2_OFFSET       0x00e8
+#define OMAP54XX_CM_CORE_AON_DEBUG_L4SEC_FD_TRANS_OFFSET        0x00ec
+#define OMAP54XX_CM_CORE_AON_DEBUG_MIPIEXT_FD_TRANS_OFFSET      0x00f0
+/* CM_CORE_AON.CKGEN_CM_CORE_AON register offsets */
+#define OMAP54XX_CM_CLKSEL_CORE_OFFSET                          0x0000
+#define OMAP54XX_CM_CLKSEL_CORE                                 OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0000)
+#define OMAP54XX_CM_CLKSEL_ABE_OFFSET                           0x0008
+#define OMAP54XX_CM_CLKSEL_ABE                                  OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0008)
+#define OMAP54XX_CM_DLL_CTRL_OFFSET                             0x0010
+#define OMAP54XX_CM_CLKMODE_DPLL_CORE_OFFSET                    0x0020
+#define OMAP54XX_CM_CLKMODE_DPLL_CORE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0020)
+#define OMAP54XX_CM_IDLEST_DPLL_CORE_OFFSET                     0x0024
+#define OMAP54XX_CM_IDLEST_DPLL_CORE                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0024)
+#define OMAP54XX_CM_AUTOIDLE_DPLL_CORE_OFFSET                   0x0028
+#define OMAP54XX_CM_AUTOIDLE_DPLL_CORE                          OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0028)
+#define OMAP54XX_CM_CLKSEL_DPLL_CORE_OFFSET                     0x002c
+#define OMAP54XX_CM_CLKSEL_DPLL_CORE                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x002c)
+#define OMAP54XX_CM_DIV_M2_DPLL_CORE_OFFSET                     0x0030
+#define OMAP54XX_CM_DIV_M2_DPLL_CORE                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0030)
+#define OMAP54XX_CM_DIV_M3_DPLL_CORE_OFFSET                     0x0034
+#define OMAP54XX_CM_DIV_M3_DPLL_CORE                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0034)
+#define OMAP54XX_CM_DIV_H11_DPLL_CORE_OFFSET                    0x0038
+#define OMAP54XX_CM_DIV_H11_DPLL_CORE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0038)
+#define OMAP54XX_CM_DIV_H12_DPLL_CORE_OFFSET                    0x003c
+#define OMAP54XX_CM_DIV_H12_DPLL_CORE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x003c)
+#define OMAP54XX_CM_DIV_H13_DPLL_CORE_OFFSET                    0x0040
+#define OMAP54XX_CM_DIV_H13_DPLL_CORE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0040)
+#define OMAP54XX_CM_DIV_H14_DPLL_CORE_OFFSET                    0x0044
+#define OMAP54XX_CM_DIV_H14_DPLL_CORE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0044)
+#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET             0x0048
+#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET             0x004c
+#define OMAP54XX_CM_DIV_H21_DPLL_CORE_OFFSET                    0x0050
+#define OMAP54XX_CM_DIV_H21_DPLL_CORE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0050)
+#define OMAP54XX_CM_DIV_H22_DPLL_CORE_OFFSET                    0x0054
+#define OMAP54XX_CM_DIV_H22_DPLL_CORE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0054)
+#define OMAP54XX_CM_DIV_H23_DPLL_CORE_OFFSET                    0x0058
+#define OMAP54XX_CM_DIV_H23_DPLL_CORE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0058)
+#define OMAP54XX_CM_DIV_H24_DPLL_CORE_OFFSET                    0x005c
+#define OMAP54XX_CM_DIV_H24_DPLL_CORE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x005c)
+#define OMAP54XX_CM_CLKMODE_DPLL_MPU_OFFSET                     0x0060
+#define OMAP54XX_CM_CLKMODE_DPLL_MPU                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0060)
+#define OMAP54XX_CM_IDLEST_DPLL_MPU_OFFSET                      0x0064
+#define OMAP54XX_CM_IDLEST_DPLL_MPU                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0064)
+#define OMAP54XX_CM_AUTOIDLE_DPLL_MPU_OFFSET                    0x0068
+#define OMAP54XX_CM_AUTOIDLE_DPLL_MPU                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0068)
+#define OMAP54XX_CM_CLKSEL_DPLL_MPU_OFFSET                      0x006c
+#define OMAP54XX_CM_CLKSEL_DPLL_MPU                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x006c)
+#define OMAP54XX_CM_DIV_M2_DPLL_MPU_OFFSET                      0x0070
+#define OMAP54XX_CM_DIV_M2_DPLL_MPU                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0070)
+#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET              0x0088
+#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET              0x008c
+#define OMAP54XX_CM_BYPCLK_DPLL_MPU_OFFSET                      0x009c
+#define OMAP54XX_CM_BYPCLK_DPLL_MPU                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x009c)
+#define OMAP54XX_CM_CLKMODE_DPLL_IVA_OFFSET                     0x00a0
+#define OMAP54XX_CM_CLKMODE_DPLL_IVA                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a0)
+#define OMAP54XX_CM_IDLEST_DPLL_IVA_OFFSET                      0x00a4
+#define OMAP54XX_CM_IDLEST_DPLL_IVA                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a4)
+#define OMAP54XX_CM_AUTOIDLE_DPLL_IVA_OFFSET                    0x00a8
+#define OMAP54XX_CM_AUTOIDLE_DPLL_IVA                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a8)
+#define OMAP54XX_CM_CLKSEL_DPLL_IVA_OFFSET                      0x00ac
+#define OMAP54XX_CM_CLKSEL_DPLL_IVA                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00ac)
+#define OMAP54XX_CM_DIV_H11_DPLL_IVA_OFFSET                     0x00b8
+#define OMAP54XX_CM_DIV_H11_DPLL_IVA                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00b8)
+#define OMAP54XX_CM_DIV_H12_DPLL_IVA_OFFSET                     0x00bc
+#define OMAP54XX_CM_DIV_H12_DPLL_IVA                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00bc)
+#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET              0x00c8
+#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET              0x00cc
+#define OMAP54XX_CM_BYPCLK_DPLL_IVA_OFFSET                      0x00dc
+#define OMAP54XX_CM_BYPCLK_DPLL_IVA                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00dc)
+#define OMAP54XX_CM_CLKMODE_DPLL_ABE_OFFSET                     0x00e0
+#define OMAP54XX_CM_CLKMODE_DPLL_ABE                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e0)
+#define OMAP54XX_CM_IDLEST_DPLL_ABE_OFFSET                      0x00e4
+#define OMAP54XX_CM_IDLEST_DPLL_ABE                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e4)
+#define OMAP54XX_CM_AUTOIDLE_DPLL_ABE_OFFSET                    0x00e8
+#define OMAP54XX_CM_AUTOIDLE_DPLL_ABE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e8)
+#define OMAP54XX_CM_CLKSEL_DPLL_ABE_OFFSET                      0x00ec
+#define OMAP54XX_CM_CLKSEL_DPLL_ABE                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00ec)
+#define OMAP54XX_CM_DIV_M2_DPLL_ABE_OFFSET                      0x00f0
+#define OMAP54XX_CM_DIV_M2_DPLL_ABE                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00f0)
+#define OMAP54XX_CM_DIV_M3_DPLL_ABE_OFFSET                      0x00f4
+#define OMAP54XX_CM_DIV_M3_DPLL_ABE                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00f4)
+#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET              0x0108
+#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET              0x010c
+#define OMAP54XX_CM_SHADOW_FREQ_CONFIG1_OFFSET                  0x0160
+#define OMAP54XX_CM_SHADOW_FREQ_CONFIG2_OFFSET                  0x0164
+#define OMAP54XX_CM_DYN_DEP_PRESCAL_OFFSET                      0x0170
+#define OMAP54XX_CM_RESTORE_ST_OFFSET                           0x0180
+/* CM_CORE_AON.MPU_CM_CORE_AON register offsets */
+#define OMAP54XX_CM_MPU_CLKSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_CM_MPU_STATICDEP_OFFSET                        0x0004
+#define OMAP54XX_CM_MPU_DYNAMICDEP_OFFSET                       0x0008
+#define OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET                      0x0020
+#define OMAP54XX_CM_MPU_MPU_CLKCTRL                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_MPU_INST, 0x0020)
+#define OMAP54XX_CM_MPU_MPU_MPU_DBG_CLKCTRL_OFFSET              0x0028
+#define OMAP54XX_CM_MPU_MPU_MPU_DBG_CLKCTRL                     OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_MPU_INST, 0x0028)
+/* CM_CORE_AON.DSP_CM_CORE_AON register offsets */
+#define OMAP54XX_CM_DSP_CLKSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_CM_DSP_STATICDEP_OFFSET                        0x0004
+#define OMAP54XX_CM_DSP_DYNAMICDEP_OFFSET                       0x0008
+#define OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET                      0x0020
+#define OMAP54XX_CM_DSP_DSP_CLKCTRL                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_DSP_INST, 0x0020)
+/* CM_CORE_AON.ABE_CM_CORE_AON register offsets */
+#define OMAP54XX_CM_ABE_CLKSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET                   0x0020
+#define OMAP54XX_CM_ABE_L4_ABE_CLKCTRL                          OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0020)
+#define OMAP54XX_CM_ABE_AESS_CLKCTRL_OFFSET                     0x0028
+#define OMAP54XX_CM_ABE_AESS_CLKCTRL                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0028)
+#define OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET                    0x0030
+#define OMAP54XX_CM_ABE_MCPDM_CLKCTRL                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0030)
+#define OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET                     0x0038
+#define OMAP54XX_CM_ABE_DMIC_CLKCTRL                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0038)
+#define OMAP54XX_CM_ABE_MCASP_CLKCTRL_OFFSET                    0x0040
+#define OMAP54XX_CM_ABE_MCASP_CLKCTRL                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0040)
+#define OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET                   0x0048
+#define OMAP54XX_CM_ABE_MCBSP1_CLKCTRL                          OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0048)
+#define OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET                   0x0050
+#define OMAP54XX_CM_ABE_MCBSP2_CLKCTRL                          OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0050)
+#define OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET                   0x0058
+#define OMAP54XX_CM_ABE_MCBSP3_CLKCTRL                          OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0058)
+#define OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL_OFFSET                 0x0060
+#define OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL                        OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0060)
+#define OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET                   0x0068
+#define OMAP54XX_CM_ABE_TIMER5_CLKCTRL                          OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0068)
+#define OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET                   0x0070
+#define OMAP54XX_CM_ABE_TIMER6_CLKCTRL                          OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0070)
+#define OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET                   0x0078
+#define OMAP54XX_CM_ABE_TIMER7_CLKCTRL                          OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0078)
+#define OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET                   0x0080
+#define OMAP54XX_CM_ABE_TIMER8_CLKCTRL                          OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0080)
+#define OMAP54XX_CM_ABE_WD_TIMER3_CLKCTRL_OFFSET                0x0088
+#define OMAP54XX_CM_ABE_WD_TIMER3_CLKCTRL                       OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0088)
+#endif
diff --git a/arch/arm/mach-omap2/cm2_44xx.h b/arch/arm/mach-omap2/cm2_44xx.h
index b9de72da1a8e..ee5136d7cdda 100644
--- a/arch/arm/mach-omap2/cm2_44xx.h
+++ b/arch/arm/mach-omap2/cm2_44xx.h
@@ -25,6 +25,8 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
 #define __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
+#include "cm_44xx_54xx.h"
 /* CM2 base address */
 #define OMAP4430_CM2_BASE               0x4a008000
@@ -449,9 +451,4 @@
 #define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET           0x0020
 #define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020)
-/* Function prototypes */
-extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx);
-extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx);
-extern u32 omap4_cm2_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
 #endif
diff --git a/arch/arm/mach-omap2/cm2_54xx.h b/arch/arm/mach-omap2/cm2_54xx.h
new file mode 100644
index 000000000000..2683231b299b
--- /dev/null
+++ b/arch/arm/mach-omap2/cm2_54xx.h
@@ -0,0 +1,389 @@
+/*
+ * OMAP54xx CM2 instance offset macros
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ARCH_ARM_MACH_OMAP2_CM2_54XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM2_54XX_H
+#include "cm_44xx_54xx.h"
+/* CM2 base address */
+#define OMAP54XX_CM_CORE_BASE           0x4a008000
+#define OMAP54XX_CM_CORE_REGADDR(inst, reg)                             \
+        OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE + (inst) + (reg))
+/* CM_CORE instances */
+#define OMAP54XX_CM_CORE_OCP_SOCKET_INST        0x0000
+#define OMAP54XX_CM_CORE_CKGEN_INST             0x0100
+#define OMAP54XX_CM_CORE_COREAON_INST           0x0600
+#define OMAP54XX_CM_CORE_CORE_INST              0x0700
+#define OMAP54XX_CM_CORE_IVA_INST               0x1200
+#define OMAP54XX_CM_CORE_CAM_INST               0x1300
+#define OMAP54XX_CM_CORE_DSS_INST               0x1400
+#define OMAP54XX_CM_CORE_GPU_INST               0x1500
+#define OMAP54XX_CM_CORE_L3INIT_INST            0x1600
+#define OMAP54XX_CM_CORE_CUSTEFUSE_INST         0x1700
+#define OMAP54XX_CM_CORE_RESTORE_INST           0x1e00
+#define OMAP54XX_CM_CORE_INSTR_INST             0x1f00
+/* CM_CORE clockdomain register offsets (from instance start) */
+#define OMAP54XX_CM_CORE_COREAON_COREAON_CDOFFS         0x0000
+#define OMAP54XX_CM_CORE_CORE_L3MAIN1_CDOFFS            0x0000
+#define OMAP54XX_CM_CORE_CORE_L3MAIN2_CDOFFS            0x0100
+#define OMAP54XX_CM_CORE_CORE_IPU_CDOFFS                0x0200
+#define OMAP54XX_CM_CORE_CORE_DMA_CDOFFS                0x0300
+#define OMAP54XX_CM_CORE_CORE_EMIF_CDOFFS               0x0400
+#define OMAP54XX_CM_CORE_CORE_C2C_CDOFFS                0x0500
+#define OMAP54XX_CM_CORE_CORE_L4CFG_CDOFFS              0x0600
+#define OMAP54XX_CM_CORE_CORE_L3INSTR_CDOFFS            0x0700
+#define OMAP54XX_CM_CORE_CORE_MIPIEXT_CDOFFS            0x0800
+#define OMAP54XX_CM_CORE_CORE_L4PER_CDOFFS              0x0900
+#define OMAP54XX_CM_CORE_CORE_L4SEC_CDOFFS              0x0a80
+#define OMAP54XX_CM_CORE_IVA_IVA_CDOFFS                 0x0000
+#define OMAP54XX_CM_CORE_CAM_CAM_CDOFFS                 0x0000
+#define OMAP54XX_CM_CORE_DSS_DSS_CDOFFS                 0x0000
+#define OMAP54XX_CM_CORE_GPU_GPU_CDOFFS                 0x0000
+#define OMAP54XX_CM_CORE_L3INIT_L3INIT_CDOFFS           0x0000
+#define OMAP54XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS     0x0000
+/* CM_CORE */
+/* CM_CORE.OCP_SOCKET_CM_CORE register offsets */
+#define OMAP54XX_REVISION_CM_CORE_OFFSET                        0x0000
+#define OMAP54XX_CM_CM_CORE_PROFILING_CLKCTRL_OFFSET            0x0040
+#define OMAP54XX_CM_CM_CORE_PROFILING_CLKCTRL                   OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_OCP_SOCKET_INST, 0x0040)
+#define OMAP54XX_CM_CORE_DEBUG_CFG_OFFSET                       0x0080
+#define OMAP54XX_CM_CORE_DEBUG_OUT_OFFSET                       0x0084
+/* CM_CORE.CKGEN_CM_CORE register offsets */
+#define OMAP54XX_CM_CLKSEL_USB_60MHZ_OFFSET                     0x0004
+#define OMAP54XX_CM_CLKSEL_USB_60MHZ                            OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0004)
+#define OMAP54XX_CM_CLKMODE_DPLL_PER_OFFSET                     0x0040
+#define OMAP54XX_CM_CLKMODE_DPLL_PER                            OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0040)
+#define OMAP54XX_CM_IDLEST_DPLL_PER_OFFSET                      0x0044
+#define OMAP54XX_CM_IDLEST_DPLL_PER                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0044)
+#define OMAP54XX_CM_AUTOIDLE_DPLL_PER_OFFSET                    0x0048
+#define OMAP54XX_CM_AUTOIDLE_DPLL_PER                           OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0048)
+#define OMAP54XX_CM_CLKSEL_DPLL_PER_OFFSET                      0x004c
+#define OMAP54XX_CM_CLKSEL_DPLL_PER                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x004c)
+#define OMAP54XX_CM_DIV_M2_DPLL_PER_OFFSET                      0x0050
+#define OMAP54XX_CM_DIV_M2_DPLL_PER                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0050)
+#define OMAP54XX_CM_DIV_M3_DPLL_PER_OFFSET                      0x0054
+#define OMAP54XX_CM_DIV_M3_DPLL_PER                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0054)
+#define OMAP54XX_CM_DIV_H11_DPLL_PER_OFFSET                     0x0058
+#define OMAP54XX_CM_DIV_H11_DPLL_PER                            OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0058)
+#define OMAP54XX_CM_DIV_H12_DPLL_PER_OFFSET                     0x005c
+#define OMAP54XX_CM_DIV_H12_DPLL_PER                            OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x005c)
+#define OMAP54XX_CM_DIV_H13_DPLL_PER_OFFSET                     0x0060
+#define OMAP54XX_CM_DIV_H13_DPLL_PER                            OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0060)
+#define OMAP54XX_CM_DIV_H14_DPLL_PER_OFFSET                     0x0064
+#define OMAP54XX_CM_DIV_H14_DPLL_PER                            OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0064)
+#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET              0x0068
+#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET              0x006c
+#define OMAP54XX_CM_CLKMODE_DPLL_USB_OFFSET                     0x0080
+#define OMAP54XX_CM_CLKMODE_DPLL_USB                            OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0080)
+#define OMAP54XX_CM_IDLEST_DPLL_USB_OFFSET                      0x0084
+#define OMAP54XX_CM_IDLEST_DPLL_USB                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0084)
+#define OMAP54XX_CM_AUTOIDLE_DPLL_USB_OFFSET                    0x0088
+#define OMAP54XX_CM_AUTOIDLE_DPLL_USB                           OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0088)
+#define OMAP54XX_CM_CLKSEL_DPLL_USB_OFFSET                      0x008c
+#define OMAP54XX_CM_CLKSEL_DPLL_USB                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x008c)
+#define OMAP54XX_CM_DIV_M2_DPLL_USB_OFFSET                      0x0090
+#define OMAP54XX_CM_DIV_M2_DPLL_USB                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0090)
+#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET              0x00a8
+#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET              0x00ac
+#define OMAP54XX_CM_CLKDCOLDO_DPLL_USB_OFFSET                   0x00b4
+#define OMAP54XX_CM_CLKDCOLDO_DPLL_USB                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00b4)
+#define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO2_OFFSET                 0x00c0
+#define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO2                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c0)
+#define OMAP54XX_CM_IDLEST_DPLL_UNIPRO2_OFFSET                  0x00c4
+#define OMAP54XX_CM_IDLEST_DPLL_UNIPRO2                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c4)
+#define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO2_OFFSET                0x00c8
+#define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO2                       OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c8)
+#define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO2_OFFSET                  0x00cc
+#define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO2                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00cc)
+#define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO2_OFFSET                  0x00d0
+#define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO2                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00d0)
+#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_UNIPRO2_OFFSET          0x00e8
+#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_UNIPRO2_OFFSET          0x00ec
+#define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO2_OFFSET               0x00f4
+#define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO2                      OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00f4)
+#define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO1_OFFSET                 0x0100
+#define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO1                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0100)
+#define OMAP54XX_CM_IDLEST_DPLL_UNIPRO1_OFFSET                  0x0104
+#define OMAP54XX_CM_IDLEST_DPLL_UNIPRO1                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0104)
+#define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO1_OFFSET                0x0108
+#define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO1                       OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0108)
+#define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO1_OFFSET                  0x010c
+#define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO1                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x010c)
+#define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO1_OFFSET                  0x0110
+#define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO1                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0110)
+#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_UNIPRO1_OFFSET          0x0128
+#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_UNIPRO1_OFFSET          0x012c
+#define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO1_OFFSET               0x0134
+#define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO1                      OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0134)
+/* CM_CORE.COREAON_CM_CORE register offsets */
+#define OMAP54XX_CM_COREAON_CLKSTCTRL_OFFSET                    0x0000
+#define OMAP54XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET      0x0028
+#define OMAP54XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0028)
+#define OMAP54XX_CM_COREAON_SMARTREFLEX_MM_CLKCTRL_OFFSET       0x0030
+#define OMAP54XX_CM_COREAON_SMARTREFLEX_MM_CLKCTRL              OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0030)
+#define OMAP54XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET     0x0038
+#define OMAP54XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL            OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0038)
+#define OMAP54XX_CM_COREAON_USB_PHY_CORE_CLKCTRL_OFFSET         0x0040
+#define OMAP54XX_CM_COREAON_USB_PHY_CORE_CLKCTRL                OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0040)
+#define OMAP54XX_CM_COREAON_IO_SRCOMP_CLKCTRL_OFFSET            0x0050
+#define OMAP54XX_CM_COREAON_IO_SRCOMP_CLKCTRL                   OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0050)
+/* CM_CORE.CORE_CM_CORE register offsets */
+#define OMAP54XX_CM_L3MAIN1_CLKSTCTRL_OFFSET                    0x0000
+#define OMAP54XX_CM_L3MAIN1_DYNAMICDEP_OFFSET                   0x0008
+#define OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET            0x0020
+#define OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL                   OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0020)
+#define OMAP54XX_CM_L3MAIN2_CLKSTCTRL_OFFSET                    0x0100
+#define OMAP54XX_CM_L3MAIN2_DYNAMICDEP_OFFSET                   0x0108
+#define OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET            0x0120
+#define OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL                   OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0120)
+#define OMAP54XX_CM_L3MAIN2_GPMC_CLKCTRL_OFFSET                 0x0128
+#define OMAP54XX_CM_L3MAIN2_GPMC_CLKCTRL                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0128)
+#define OMAP54XX_CM_L3MAIN2_OCMC_RAM_CLKCTRL_OFFSET             0x0130
+#define OMAP54XX_CM_L3MAIN2_OCMC_RAM_CLKCTRL                    OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0130)
+#define OMAP54XX_CM_IPU_CLKSTCTRL_OFFSET                        0x0200
+#define OMAP54XX_CM_IPU_STATICDEP_OFFSET                        0x0204
+#define OMAP54XX_CM_IPU_DYNAMICDEP_OFFSET                       0x0208
+#define OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET                      0x0220
+#define OMAP54XX_CM_IPU_IPU_CLKCTRL                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0220)
+#define OMAP54XX_CM_DMA_CLKSTCTRL_OFFSET                        0x0300
+#define OMAP54XX_CM_DMA_STATICDEP_OFFSET                        0x0304
+#define OMAP54XX_CM_DMA_DYNAMICDEP_OFFSET                       0x0308
+#define OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET               0x0320
+#define OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL                      OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0320)
+#define OMAP54XX_CM_EMIF_CLKSTCTRL_OFFSET                       0x0400
+#define OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET                     0x0420
+#define OMAP54XX_CM_EMIF_DMM_CLKCTRL                            OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0420)
+#define OMAP54XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET             0x0428
+#define OMAP54XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL                    OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0428)
+#define OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET                   0x0430
+#define OMAP54XX_CM_EMIF_EMIF1_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0430)
+#define OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET                   0x0438
+#define OMAP54XX_CM_EMIF_EMIF2_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0438)
+#define OMAP54XX_CM_EMIF_EMIF_DLL_CLKCTRL_OFFSET                0x0440
+#define OMAP54XX_CM_EMIF_EMIF_DLL_CLKCTRL                       OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0440)
+#define OMAP54XX_CM_C2C_CLKSTCTRL_OFFSET                        0x0500
+#define OMAP54XX_CM_C2C_STATICDEP_OFFSET                        0x0504
+#define OMAP54XX_CM_C2C_DYNAMICDEP_OFFSET                       0x0508
+#define OMAP54XX_CM_C2C_C2C_CLKCTRL_OFFSET                      0x0520
+#define OMAP54XX_CM_C2C_C2C_CLKCTRL                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0520)
+#define OMAP54XX_CM_C2C_MODEM_ICR_CLKCTRL_OFFSET                0x0528
+#define OMAP54XX_CM_C2C_MODEM_ICR_CLKCTRL                       OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0528)
+#define OMAP54XX_CM_C2C_C2C_OCP_FW_CLKCTRL_OFFSET               0x0530
+#define OMAP54XX_CM_C2C_C2C_OCP_FW_CLKCTRL                      OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0530)
+#define OMAP54XX_CM_L4CFG_CLKSTCTRL_OFFSET                      0x0600
+#define OMAP54XX_CM_L4CFG_DYNAMICDEP_OFFSET                     0x0608
+#define OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET                 0x0620
+#define OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0620)
+#define OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET               0x0628
+#define OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL                      OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0628)
+#define OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET                0x0630
+#define OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL                       OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0630)
+#define OMAP54XX_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET                0x0638
+#define OMAP54XX_CM_L4CFG_SAR_ROM_CLKCTRL                       OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0638)
+#define OMAP54XX_CM_L4CFG_OCP2SCP2_CLKCTRL_OFFSET               0x0640
+#define OMAP54XX_CM_L4CFG_OCP2SCP2_CLKCTRL                      OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0640)
+#define OMAP54XX_CM_L3INSTR_CLKSTCTRL_OFFSET                    0x0700
+#define OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET            0x0720
+#define OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL                   OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0720)
+#define OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET             0x0728
+#define OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL                    OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0728)
+#define OMAP54XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET           0x0740
+#define OMAP54XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL                  OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0740)
+#define OMAP54XX_CM_L3INSTR_DLL_AGING_CLKCTRL_OFFSET            0x0748
+#define OMAP54XX_CM_L3INSTR_DLL_AGING_CLKCTRL                   OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0748)
+#define OMAP54XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL_OFFSET  0x0750
+#define OMAP54XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0750)
+#define OMAP54XX_CM_MIPIEXT_CLKSTCTRL_OFFSET                    0x0800
+#define OMAP54XX_CM_MIPIEXT_STATICDEP_OFFSET                    0x0804
+#define OMAP54XX_CM_MIPIEXT_DYNAMICDEP_OFFSET                   0x0808
+#define OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL_OFFSET                  0x0820
+#define OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0820)
+#define OMAP54XX_CM_MIPIEXT_LLI_OCP_FW_CLKCTRL_OFFSET           0x0828
+#define OMAP54XX_CM_MIPIEXT_LLI_OCP_FW_CLKCTRL                  OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0828)
+#define OMAP54XX_CM_MIPIEXT_MPHY_CLKCTRL_OFFSET                 0x0830
+#define OMAP54XX_CM_MIPIEXT_MPHY_CLKCTRL                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0830)
+#define OMAP54XX_CM_L4PER_CLKSTCTRL_OFFSET                      0x0900
+#define OMAP54XX_CM_L4PER_DYNAMICDEP_OFFSET                     0x0908
+#define OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET                0x0928
+#define OMAP54XX_CM_L4PER_TIMER10_CLKCTRL                       OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0928)
+#define OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET                0x0930
+#define OMAP54XX_CM_L4PER_TIMER11_CLKCTRL                       OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0930)
+#define OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET                 0x0938
+#define OMAP54XX_CM_L4PER_TIMER2_CLKCTRL                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0938)
+#define OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET                 0x0940
+#define OMAP54XX_CM_L4PER_TIMER3_CLKCTRL                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0940)
+#define OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET                 0x0948
+#define OMAP54XX_CM_L4PER_TIMER4_CLKCTRL                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0948)
+#define OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET                 0x0950
+#define OMAP54XX_CM_L4PER_TIMER9_CLKCTRL                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0950)
+#define OMAP54XX_CM_L4PER_ELM_CLKCTRL_OFFSET                    0x0958
+#define OMAP54XX_CM_L4PER_ELM_CLKCTRL                           OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0958)
+#define OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET                  0x0960
+#define OMAP54XX_CM_L4PER_GPIO2_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0960)
+#define OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET                  0x0968
+#define OMAP54XX_CM_L4PER_GPIO3_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0968)
+#define OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET                  0x0970
+#define OMAP54XX_CM_L4PER_GPIO4_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0970)
+#define OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET                  0x0978
+#define OMAP54XX_CM_L4PER_GPIO5_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0978)
+#define OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET                  0x0980
+#define OMAP54XX_CM_L4PER_GPIO6_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0980)
+#define OMAP54XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET                  0x0988
+#define OMAP54XX_CM_L4PER_HDQ1W_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0988)
+#define OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET                   0x09a0
+#define OMAP54XX_CM_L4PER_I2C1_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09a0)
+#define OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET                   0x09a8
+#define OMAP54XX_CM_L4PER_I2C2_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09a8)
+#define OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET                   0x09b0
+#define OMAP54XX_CM_L4PER_I2C3_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09b0)
+#define OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET                   0x09b8
+#define OMAP54XX_CM_L4PER_I2C4_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09b8)
+#define OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET                 0x09c0
+#define OMAP54XX_CM_L4PER_L4_PER_CLKCTRL                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09c0)
+#define OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET                 0x09f0
+#define OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09f0)
+#define OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET                 0x09f8
+#define OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09f8)
+#define OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET                 0x0a00
+#define OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a00)
+#define OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET                 0x0a08
+#define OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a08)
+#define OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET                  0x0a10
+#define OMAP54XX_CM_L4PER_GPIO7_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a10)
+#define OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET                  0x0a18
+#define OMAP54XX_CM_L4PER_GPIO8_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a18)
+#define OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET                   0x0a20
+#define OMAP54XX_CM_L4PER_MMC3_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a20)
+#define OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET                   0x0a28
+#define OMAP54XX_CM_L4PER_MMC4_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a28)
+#define OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET                  0x0a40
+#define OMAP54XX_CM_L4PER_UART1_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a40)
+#define OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET                  0x0a48
+#define OMAP54XX_CM_L4PER_UART2_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a48)
+#define OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET                  0x0a50
+#define OMAP54XX_CM_L4PER_UART3_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a50)
+#define OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET                  0x0a58
+#define OMAP54XX_CM_L4PER_UART4_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a58)
+#define OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET                   0x0a60
+#define OMAP54XX_CM_L4PER_MMC5_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a60)
+#define OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET                   0x0a68
+#define OMAP54XX_CM_L4PER_I2C5_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a68)
+#define OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET                  0x0a70
+#define OMAP54XX_CM_L4PER_UART5_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a70)
+#define OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET                  0x0a78
+#define OMAP54XX_CM_L4PER_UART6_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a78)
+#define OMAP54XX_CM_L4SEC_CLKSTCTRL_OFFSET                      0x0a80
+#define OMAP54XX_CM_L4SEC_STATICDEP_OFFSET                      0x0a84
+#define OMAP54XX_CM_L4SEC_DYNAMICDEP_OFFSET                     0x0a88
+#define OMAP54XX_CM_L4SEC_AES1_CLKCTRL_OFFSET                   0x0aa0
+#define OMAP54XX_CM_L4SEC_AES1_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0aa0)
+#define OMAP54XX_CM_L4SEC_AES2_CLKCTRL_OFFSET                   0x0aa8
+#define OMAP54XX_CM_L4SEC_AES2_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0aa8)
+#define OMAP54XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET                0x0ab0
+#define OMAP54XX_CM_L4SEC_DES3DES_CLKCTRL                       OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ab0)
+#define OMAP54XX_CM_L4SEC_FPKA_CLKCTRL_OFFSET                   0x0ab8
+#define OMAP54XX_CM_L4SEC_FPKA_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ab8)
+#define OMAP54XX_CM_L4SEC_RNG_CLKCTRL_OFFSET                    0x0ac0
+#define OMAP54XX_CM_L4SEC_RNG_CLKCTRL                           OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ac0)
+#define OMAP54XX_CM_L4SEC_SHA2MD5_CLKCTRL_OFFSET                0x0ac8
+#define OMAP54XX_CM_L4SEC_SHA2MD5_CLKCTRL                       OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ac8)
+#define OMAP54XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL_OFFSET             0x0ad8
+#define OMAP54XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL                    OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ad8)
+/* CM_CORE.IVA_CM_CORE register offsets */
+#define OMAP54XX_CM_IVA_CLKSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_CM_IVA_STATICDEP_OFFSET                        0x0004
+#define OMAP54XX_CM_IVA_DYNAMICDEP_OFFSET                       0x0008
+#define OMAP54XX_CM_IVA_IVA_CLKCTRL_OFFSET                      0x0020
+#define OMAP54XX_CM_IVA_IVA_CLKCTRL                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_IVA_INST, 0x0020)
+#define OMAP54XX_CM_IVA_SL2_CLKCTRL_OFFSET                      0x0028
+#define OMAP54XX_CM_IVA_SL2_CLKCTRL                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_IVA_INST, 0x0028)
+/* CM_CORE.CAM_CM_CORE register offsets */
+#define OMAP54XX_CM_CAM_CLKSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_CM_CAM_STATICDEP_OFFSET                        0x0004
+#define OMAP54XX_CM_CAM_DYNAMICDEP_OFFSET                       0x0008
+#define OMAP54XX_CM_CAM_ISS_CLKCTRL_OFFSET                      0x0020
+#define OMAP54XX_CM_CAM_ISS_CLKCTRL                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0020)
+#define OMAP54XX_CM_CAM_FDIF_CLKCTRL_OFFSET                     0x0028
+#define OMAP54XX_CM_CAM_FDIF_CLKCTRL                            OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0028)
+#define OMAP54XX_CM_CAM_CAL_CLKCTRL_OFFSET                      0x0030
+#define OMAP54XX_CM_CAM_CAL_CLKCTRL                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0030)
+/* CM_CORE.DSS_CM_CORE register offsets */
+#define OMAP54XX_CM_DSS_CLKSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_CM_DSS_STATICDEP_OFFSET                        0x0004
+#define OMAP54XX_CM_DSS_DYNAMICDEP_OFFSET                       0x0008
+#define OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET                      0x0020
+#define OMAP54XX_CM_DSS_DSS_CLKCTRL                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_DSS_INST, 0x0020)
+#define OMAP54XX_CM_DSS_BB2D_CLKCTRL_OFFSET                     0x0030
+#define OMAP54XX_CM_DSS_BB2D_CLKCTRL                            OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_DSS_INST, 0x0030)
+/* CM_CORE.GPU_CM_CORE register offsets */
+#define OMAP54XX_CM_GPU_CLKSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_CM_GPU_STATICDEP_OFFSET                        0x0004
+#define OMAP54XX_CM_GPU_DYNAMICDEP_OFFSET                       0x0008
+#define OMAP54XX_CM_GPU_GPU_CLKCTRL_OFFSET                      0x0020
+#define OMAP54XX_CM_GPU_GPU_CLKCTRL                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_GPU_INST, 0x0020)
+/* CM_CORE.L3INIT_CM_CORE register offsets */
+#define OMAP54XX_CM_L3INIT_CLKSTCTRL_OFFSET                     0x0000
+#define OMAP54XX_CM_L3INIT_STATICDEP_OFFSET                     0x0004
+#define OMAP54XX_CM_L3INIT_DYNAMICDEP_OFFSET                    0x0008
+#define OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET                  0x0028
+#define OMAP54XX_CM_L3INIT_MMC1_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0028)
+#define OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET                  0x0030
+#define OMAP54XX_CM_L3INIT_MMC2_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0030)
+#define OMAP54XX_CM_L3INIT_HSI_CLKCTRL_OFFSET                   0x0038
+#define OMAP54XX_CM_L3INIT_HSI_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0038)
+#define OMAP54XX_CM_L3INIT_UNIPRO2_CLKCTRL_OFFSET               0x0040
+#define OMAP54XX_CM_L3INIT_UNIPRO2_CLKCTRL                      OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0040)
+#define OMAP54XX_CM_L3INIT_MPHY_UNIPRO2_CLKCTRL_OFFSET          0x0048
+#define OMAP54XX_CM_L3INIT_MPHY_UNIPRO2_CLKCTRL                 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0048)
+#define OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET           0x0058
+#define OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL                  OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0058)
+#define OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET            0x0068
+#define OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL                   OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0068)
+#define OMAP54XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL_OFFSET        0x0078
+#define OMAP54XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL               OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0078)
+#define OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET                  0x0088
+#define OMAP54XX_CM_L3INIT_SATA_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0088)
+#define OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET              0x00e0
+#define OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL                     OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00e0)
+#define OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET              0x00e8
+#define OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL                     OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00e8)
+#define OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET            0x00f0
+#define OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL                   OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00f0)
+/* CM_CORE.CUSTEFUSE_CM_CORE register offsets */
+#define OMAP54XX_CM_CUSTEFUSE_CLKSTCTRL_OFFSET                  0x0000
+#define OMAP54XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL_OFFSET    0x0020
+#define OMAP54XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL           OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CUSTEFUSE_INST, 0x0020)
+#endif
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
index 64f4bafe7bd9..9d1f4fcdebbb 100644
--- a/arch/arm/mach-omap2/cm33xx.h
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -383,7 +383,7 @@ extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs);
 extern void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs);
 extern void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs);
-#ifdef CONFIG_SOC_AM33XX
+#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
 extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
                                        u16 clkctrl_offs);
 extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
diff --git a/arch/arm/mach-omap2/cm_44xx_54xx.h b/arch/arm/mach-omap2/cm_44xx_54xx.h
new file mode 100644
index 000000000000..cbb211690321
--- /dev/null
+++ b/arch/arm/mach-omap2/cm_44xx_54xx.h
@@ -0,0 +1,36 @@
+/*
+ * OMAP44xx and OMAP54xx CM1/CM2 function prototypes
+ *
+ * Copyright (C) 2009-2013 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#ifndef __ARCH_ARM_MACH_OMAP2_CM_44XX_54XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM_44XX_55XX_H
+/* CM1 Function prototypes */
+extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
+extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 omap4_cm1_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
+/* CM2 Function prototypes */
+extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx);
+extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 omap4_cm2_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
+#endif
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index d555cf2459e1..dfcc182ecff9 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -31,6 +31,7 @@
 #include <linux/i2c.h>
 #include <linux/i2c/twl.h>
 #include <linux/i2c-omap.h>
+#include <linux/reboot.h>
 #include <asm/proc-fns.h>
@@ -96,6 +97,7 @@ void am33xx_init_early(void);
 void am35xx_init_early(void);
 void ti81xx_init_early(void);
 void am33xx_init_early(void);
+void am43xx_init_early(void);
 void omap4430_init_early(void);
 void omap5_init_early(void);
 void omap3_init_late(void);     /* Do not use this one */
@@ -118,33 +120,33 @@ static inline void omap_soc_device_init(void)
 #endif
 #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
-void omap2xxx_restart(char mode, const char *cmd);
+void omap2xxx_restart(enum reboot_mode mode, const char *cmd);
 #else
-static inline void omap2xxx_restart(char mode, const char *cmd)
+static inline void omap2xxx_restart(enum reboot_mode mode, const char *cmd)
 {
 }
 #endif
 #ifdef CONFIG_SOC_AM33XX
-void am33xx_restart(char mode, const char *cmd);
+void am33xx_restart(enum reboot_mode mode, const char *cmd);
 #else
-static inline void am33xx_restart(char mode, const char *cmd)
+static inline void am33xx_restart(enum reboot_mode mode, const char *cmd)
 {
 }
 #endif
 #ifdef CONFIG_ARCH_OMAP3
-void omap3xxx_restart(char mode, const char *cmd);
+void omap3xxx_restart(enum reboot_mode mode, const char *cmd);
 #else
-static inline void omap3xxx_restart(char mode, const char *cmd)
+static inline void omap3xxx_restart(enum reboot_mode mode, const char *cmd)
 {
 }
 #endif
 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
-void omap44xx_restart(char mode, const char *cmd);
+void omap44xx_restart(enum reboot_mode mode, const char *cmd);
 #else
-static inline void omap44xx_restart(char mode, const char *cmd)
+static inline void omap44xx_restart(enum reboot_mode mode, const char *cmd)
 {
 }
 #endif
@@ -237,8 +239,8 @@ extern void omap_do_wfi(void);
 #ifdef CONFIG_SMP
 /* Needed for secondary core boot */
-extern void omap_secondary_startup(void);
+extern void omap4_secondary_startup(void);
-extern void omap_secondary_startup_4460(void);
+extern void omap4460_secondary_startup(void);
 extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
 extern void omap_auxcoreboot_addr(u32 cpu_addr);
 extern u32 omap_read_auxcoreboot0(void);
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 2adb2683f074..31e0dfe4a4ea 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -249,6 +249,7 @@ void omap_ctrl_write_dsp_boot_addr(u32 bootaddr)
        u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTADDR :
                     cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTADDR :
                     cpu_is_omap44xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR :
+                     soc_is_omap54xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR :
                     0;
        if (!offset) {
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index e6c328128a0a..f7d7c2ef1b40 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -358,6 +358,18 @@
 #define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH            0x2
 #define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK             (0x3 << 22)
+/* AM33XX PWMSS Control register */
+#define AM33XX_PWMSS_TBCLK_CLKCTRL                      0x664
+/* AM33XX  PWMSS Control bitfields */
+#define AM33XX_PWMSS0_TBCLKEN_SHIFT                     0
+#define AM33XX_PWMSS1_TBCLKEN_SHIFT                     1
+#define AM33XX_PWMSS2_TBCLKEN_SHIFT                     2
+/* DEV Feature register to identify AM33XX features */
+#define AM33XX_DEV_FEATURE              0x604
+#define AM33XX_SGX_MASK                 BIT(29)
 /* CONTROL OMAP STATUS register to identify OMAP3 features */
 #define OMAP3_CONTROL_OMAP_STATUS       0x044c
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 4269fc145698..3c1279f27d1f 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -19,8 +19,8 @@
 #include <linux/of.h>
 #include <linux/pinctrl/machine.h>
 #include <linux/platform_data/omap4-keypad.h>
-#include <linux/platform_data/omap_ocp2scp.h>
+#include <linux/wl12xx.h>
-#include <linux/usb/omap_control_usb.h>
+#include <linux/platform_data/mailbox-omap.h>
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
@@ -37,7 +37,6 @@
 #include "mux.h"
 #include "control.h"
 #include "devices.h"
-#include "dma.h"
 #define L3_MODULES_MAX_LEN 12
 #define L3_MODULES 3
@@ -66,7 +65,7 @@ static int __init omap3_l3_init(void)
        WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
-        return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
+        return PTR_RET(pdev);
 }
 omap_postcore_initcall(omap3_l3_init);
@@ -100,7 +99,7 @@ static int __init omap4_l3_init(void)
        WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
-        return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
+        return PTR_RET(pdev);
 }
 omap_postcore_initcall(omap4_l3_init);
@@ -253,49 +252,6 @@ static inline void omap_init_camera(void)
 #endif
 }
-#if IS_ENABLED(CONFIG_OMAP_CONTROL_USB)
-static struct omap_control_usb_platform_data omap4_control_usb_pdata = {
-        .type = 1,
-};
-struct resource omap4_control_usb_res[] = {
-        {
-                .name   = "control_dev_conf",
-                .start  = 0x4a002300,
-                .end    = 0x4a002303,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .name   = "otghs_control",
-                .start  = 0x4a00233c,
-                .end    = 0x4a00233f,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device omap4_control_usb = {
-        .name = "omap-control-usb",
-        .id = -1,
-        .dev = {
-                .platform_data = &omap4_control_usb_pdata,
-        },
-        .num_resources = 2,
-        .resource = omap4_control_usb_res,
-};
-static inline void __init omap_init_control_usb(void)
-{
-        if (!cpu_is_omap44xx())
-                return;
-        if (platform_device_register(&omap4_control_usb))
-                pr_err("Error registering omap_control_usb device\n");
-}
-#else
-static inline void omap_init_control_usb(void) { }
-#endif /* CONFIG_OMAP_CONTROL_USB */
 int __init omap4_keyboard_init(struct omap4_keypad_platform_data
                        *sdp4430_keypad_data, struct omap_board_data *bdata)
 {
@@ -327,25 +283,31 @@ int __init omap4_keyboard_init(struct omap4_keypad_platform_data
        return 0;
 }
-#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
+#if defined(CONFIG_OMAP2PLUS_MBOX) || defined(CONFIG_OMAP2PLUS_MBOX_MODULE)
 static inline void __init omap_init_mbox(void)
 {
        struct omap_hwmod *oh;
        struct platform_device *pdev;
+        struct omap_mbox_pdata *pdata;
        oh = omap_hwmod_lookup("mailbox");
        if (!oh) {
                pr_err("%s: unable to find hwmod\n", __func__);
                return;
        }
+        if (!oh->dev_attr) {
+                pr_err("%s: hwmod doesn't have valid attrs\n", __func__);
+                return;
+        }
-        pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0);
+        pdata = (struct omap_mbox_pdata *)oh->dev_attr;
+        pdev = omap_device_build("omap-mailbox", -1, oh, pdata, sizeof(*pdata));
        WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n",
                                                __func__, PTR_ERR(pdev));
 }
 #else
 static inline void omap_init_mbox(void) { }
-#endif /* CONFIG_OMAP_MBOX_FWK */
+#endif /* CONFIG_OMAP2PLUS_MBOX */
 static inline void omap_init_sti(void) {}
@@ -374,10 +336,8 @@ static void __init omap_init_mcpdm(void)
        struct platform_device *pdev;
        oh = omap_hwmod_lookup("mcpdm");
-        if (!oh) {
+        if (!oh)
-                printk(KERN_ERR "Could not look up mcpdm hw_mod\n");
                return;
-        }
        pdev = omap_device_build("omap-mcpdm", -1, oh, NULL, 0);
        WARN(IS_ERR(pdev), "Can't build omap_device for omap-mcpdm.\n");
@@ -395,10 +355,8 @@ static void __init omap_init_dmic(void)
        struct platform_device *pdev;
        oh = omap_hwmod_lookup("dmic");
-        if (!oh) {
+        if (!oh)
-                pr_err("Could not look up dmic hw_mod\n");
                return;
-        }
        pdev = omap_device_build("omap-dmic", -1, oh, NULL, 0);
        WARN(IS_ERR(pdev), "Can't build omap_device for omap-dmic.\n");
@@ -421,10 +379,8 @@ static void __init omap_init_hdmi_audio(void)
        struct platform_device *pdev;
        oh = omap_hwmod_lookup("dss_hdmi");
-        if (!oh) {
+        if (!oh)
-                printk(KERN_ERR "Could not look up dss_hdmi hw_mod\n");
                return;
-        }
        pdev = omap_device_build("omap-hdmi-audio-dai", -1, oh, NULL, 0);
        WARN(IS_ERR(pdev),
@@ -557,80 +513,38 @@ static void omap_init_vout(void)
 static inline void omap_init_vout(void) {}
 #endif
-#if defined(CONFIG_OMAP_OCP2SCP) || defined(CONFIG_OMAP_OCP2SCP_MODULE)
+#if IS_ENABLED(CONFIG_WL12XX)
-static int count_ocp2scp_devices(struct omap_ocp2scp_dev *ocp2scp_dev)
-{
-        int cnt = 0;
-        while (ocp2scp_dev->drv_name != NULL) {
+static struct wl12xx_platform_data wl12xx __initdata;
-                cnt++;
-                ocp2scp_dev++;
-        }
-        return cnt;
+void __init omap_init_wl12xx_of(void)
-}
-static void __init omap_init_ocp2scp(void)
 {
-        struct omap_hwmod       *oh;
+        int ret;
-        struct platform_device  *pdev;
-        int                     bus_id = -1, dev_cnt = 0, i;
-        struct omap_ocp2scp_dev *ocp2scp_dev;
-        const char              *oh_name, *name;
-        struct omap_ocp2scp_platform_data *pdata;
-        if (!cpu_is_omap44xx())
-                return;
-        oh_name = "ocp2scp_usb_phy";
-        name    = "omap-ocp2scp";
-        oh = omap_hwmod_lookup(oh_name);
-        if (!oh) {
-                pr_err("%s: could not find omap_hwmod for %s\n", __func__,
-                                                                oh_name);
-                return;
-        }
-        pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
+        if (!of_have_populated_dt())
-        if (!pdata) {
-                pr_err("%s: No memory for ocp2scp pdata\n", __func__);
                return;
-        }
-        ocp2scp_dev = oh->dev_attr;
+        if (of_machine_is_compatible("ti,omap4-sdp")) {
-        dev_cnt = count_ocp2scp_devices(ocp2scp_dev);
+                wl12xx.board_ref_clock = WL12XX_REFCLOCK_26;
+                wl12xx.board_tcxo_clock = WL12XX_TCXOCLOCK_26;
-        if (!dev_cnt) {
+                wl12xx.irq = gpio_to_irq(53);
-                pr_err("%s: No devices connected to ocp2scp\n", __func__);
+        } else if (of_machine_is_compatible("ti,omap4-panda")) {
-                kfree(pdata);
+                wl12xx.board_ref_clock = WL12XX_REFCLOCK_38;
+                wl12xx.irq = gpio_to_irq(53);
+        } else {
                return;
        }
-        pdata->devices = kzalloc(sizeof(struct omap_ocp2scp_dev *)
+        ret = wl12xx_set_platform_data(&wl12xx);
-                                        * dev_cnt, GFP_KERNEL);
+        if (ret) {
-        if (!pdata->devices) {
+                pr_err("error setting wl12xx data: %d\n", ret);
-                pr_err("%s: No memory for ocp2scp pdata devices\n", __func__);
-                kfree(pdata);
-                return;
-        }
-        for (i = 0; i < dev_cnt; i++, ocp2scp_dev++)
-                pdata->devices[i] = ocp2scp_dev;
-        pdata->dev_cnt  = dev_cnt;
-        pdev = omap_device_build(name, bus_id, oh, pdata, sizeof(*pdata));
-        if (IS_ERR(pdev)) {
-                pr_err("Could not build omap_device for %s %s\n",
-                                                name, oh_name);
-                kfree(pdata->devices);
-                kfree(pdata);
                return;
        }
 }
 #else
-static inline void omap_init_ocp2scp(void) { }
+static inline void omap_init_wl12xx_of(void)
+{
+}
 #endif
 /*-------------------------------------------------------------------------*/
@@ -651,17 +565,18 @@ static int __init omap2_init_devices(void)
        omap_init_mbox();
        /* If dtb is there, the devices will be created dynamically */
        if (!of_have_populated_dt()) {
-                omap_init_control_usb();
                omap_init_dmic();
                omap_init_mcpdm();
                omap_init_mcspi();
                omap_init_sham();
                omap_init_aes();
+        } else {
+                /* These can be removed when bindings are done */
+                omap_init_wl12xx_of();
        }
        omap_init_sti();
        omap_init_rng();
        omap_init_vout();
-        omap_init_ocp2scp();
        return 0;
 }
diff --git a/arch/arm/mach-omap2/dma.h b/arch/arm/mach-omap2/dma.h
deleted file mode 100644
index 65f80cacf178..000000000000
--- a/arch/arm/mach-omap2/dma.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- *  OMAP2PLUS DMA channel definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef __OMAP2PLUS_DMA_CHANNEL_H
-#define __OMAP2PLUS_DMA_CHANNEL_H
-/* DMA channels for 24xx */
-#define OMAP24XX_DMA_NO_DEVICE          0
-#define OMAP24XX_DMA_EXT_DMAREQ0        2       /* S_DMA_1 */
-#define OMAP24XX_DMA_EXT_DMAREQ1        3       /* S_DMA_2 */
-#define OMAP24XX_DMA_GPMC               4       /* S_DMA_3 */
-#define OMAP24XX_DMA_AES_TX             9       /* S_DMA_8 */
-#define OMAP24XX_DMA_AES_RX             10      /* S_DMA_9 */
-#define OMAP242X_DMA_EXT_DMAREQ2        14      /* S_DMA_13 */
-#define OMAP242X_DMA_EXT_DMAREQ3        15      /* S_DMA_14 */
-#define OMAP242X_DMA_EXT_DMAREQ4        16      /* S_DMA_15 */
-#define OMAP34XX_DMA_I2C3_TX            25      /* S_DMA_24 */
-#define OMAP34XX_DMA_I2C3_RX            26      /* S_DMA_25 */
-#define OMAP24XX_DMA_I2C1_TX            27      /* S_DMA_26 */
-#define OMAP24XX_DMA_I2C1_RX            28      /* S_DMA_27 */
-#define OMAP24XX_DMA_I2C2_TX            29      /* S_DMA_28 */
-#define OMAP24XX_DMA_I2C2_RX            30      /* S_DMA_29 */
-#define OMAP24XX_DMA_MMC2_TX            47      /* S_DMA_46 */
-#define OMAP24XX_DMA_MMC2_RX            48      /* S_DMA_47 */
-#define OMAP24XX_DMA_UART1_TX           49      /* S_DMA_48 */
-#define OMAP24XX_DMA_UART1_RX           50      /* S_DMA_49 */
-#define OMAP24XX_DMA_UART2_TX           51      /* S_DMA_50 */
-#define OMAP24XX_DMA_UART2_RX           52      /* S_DMA_51 */
-#define OMAP24XX_DMA_UART3_TX           53      /* S_DMA_52 */
-#define OMAP24XX_DMA_UART3_RX           54      /* S_DMA_53 */
-#define OMAP24XX_DMA_MMC1_TX            61      /* S_DMA_60 */
-#define OMAP24XX_DMA_MMC1_RX            62      /* S_DMA_61 */
-#define OMAP242X_DMA_EXT_DMAREQ5        64      /* S_DMA_63 */
-#define OMAP34XX_DMA_AES2_TX            65      /* S_DMA_64 */
-#define OMAP34XX_DMA_AES2_RX            66      /* S_DMA_65 */
-#define OMAP34XX_DMA_SHA1MD5_RX         69      /* S_DMA_68 */
-#define OMAP36XX_DMA_UART4_TX           81      /* S_DMA_80 */
-#define OMAP36XX_DMA_UART4_RX           82      /* S_DMA_81 */
-/* Only for AM35xx */
-#define AM35XX_DMA_UART4_TX             54
-#define AM35XX_DMA_UART4_RX             55
-#endif /* __OMAP2PLUS_DMA_CHANNEL_H */
diff --git a/arch/arm/mach-omap2/dss-common.c b/arch/arm/mach-omap2/dss-common.c
index 393aeefaebb0..043e5705f2a6 100644
--- a/arch/arm/mach-omap2/dss-common.c
+++ b/arch/arm/mach-omap2/dss-common.c
@@ -42,7 +42,7 @@
 /* Using generic display panel */
 static struct tfp410_platform_data omap4_dvi_panel = {
-        .i2c_bus_num            = 3,
+        .i2c_bus_num            = 2,
        .power_down_gpio        = PANDA_DVI_TFP410_POWER_DOWN_GPIO,
 };
diff --git a/arch/arm/mach-omap2/fb.c b/arch/arm/mach-omap2/fb.c
index 190ae493c6ef..2ca33cc0c484 100644
--- a/arch/arm/mach-omap2/fb.c
+++ b/arch/arm/mach-omap2/fb.c
@@ -83,10 +83,7 @@ static int __init omap_init_vrfb(void)
        pdev = platform_device_register_resndata(NULL, "omapvrfb", -1,
                        res, num_res, NULL, 0);
-        if (IS_ERR(pdev))
+        return PTR_RET(pdev);
-                return PTR_ERR(pdev);
-        else
-                return 0;
 }
 omap_arch_initcall(omap_init_vrfb);
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index d9c27195caf0..662c7fd633cc 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -43,44 +43,6 @@ static struct platform_device gpmc_nand_device = {
        .resource       = gpmc_nand_resource,
 };
-static int omap2_nand_gpmc_retime(
-                                struct omap_nand_platform_data *gpmc_nand_data,
-                                struct gpmc_timings *gpmc_t)
-{
-        struct gpmc_timings t;
-        int err;
-        memset(&t, 0, sizeof(t));
-        t.sync_clk = gpmc_t->sync_clk;
-        t.cs_on = gpmc_t->cs_on;
-        t.adv_on = gpmc_t->adv_on;
-        /* Read */
-        t.adv_rd_off = gpmc_t->adv_rd_off;
-        t.oe_on  = t.adv_on;
-        t.access = gpmc_t->access;
-        t.oe_off = gpmc_t->oe_off;
-        t.cs_rd_off = gpmc_t->cs_rd_off;
-        t.rd_cycle = gpmc_t->rd_cycle;
-        /* Write */
-        t.adv_wr_off = gpmc_t->adv_wr_off;
-        t.we_on  = t.oe_on;
-        if (cpu_is_omap34xx()) {
-                t.wr_data_mux_bus = gpmc_t->wr_data_mux_bus;
-                t.wr_access = gpmc_t->wr_access;
-        }
-        t.we_off = gpmc_t->we_off;
-        t.cs_wr_off = gpmc_t->cs_wr_off;
-        t.wr_cycle = gpmc_t->wr_cycle;
-        err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t);
-        if (err)
-                return err;
-        return 0;
-}
 static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
 {
        /* support only OMAP3 class */
@@ -131,7 +93,7 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
                                gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);
        if (gpmc_t) {
-                err = omap2_nand_gpmc_retime(gpmc_nand_data, gpmc_t);
+                err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t);
                if (err < 0) {
                        dev_err(dev, "Unable to set gpmc timings: %d\n", err);
                        return err;
@@ -140,8 +102,6 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
                if (gpmc_nand_data->of_node) {
                        gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);
                } else {
-                        s.device_nand = true;
                        /* Enable RD PIN Monitoring Reg */
                        if (gpmc_nand_data->dev_ready) {
                                s.wait_on_read = true;
@@ -149,6 +109,8 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
                        }
                }
+                s.device_nand = true;
                if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
                        s.device_width = GPMC_DEVWIDTH_16BIT;
                else
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 6c4da1254f53..f3fdd6afa213 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -30,6 +30,7 @@
 #include <linux/of_mtd.h>
 #include <linux/of_device.h>
 #include <linux/mtd/nand.h>
+#include <linux/pm_runtime.h>
 #include <linux/platform_data/mtd-nand-omap2.h>
@@ -155,6 +156,7 @@ static struct resource	gpmc_cs_mem[GPMC_CS_NUM];
 static DEFINE_SPINLOCK(gpmc_mem_lock);
 /* Define chip-selects as reserved by default until probe completes */
 static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1);
+static unsigned int gpmc_cs_num = GPMC_CS_NUM;
 static unsigned int gpmc_nr_waitpins;
 static struct device *gpmc_dev;
 static int gpmc_irq;
@@ -521,8 +523,10 @@ static int gpmc_cs_remap(int cs, u32 base)
        int ret;
        u32 old_base, size;
-        if (cs > GPMC_CS_NUM)
+        if (cs > gpmc_cs_num) {
+                pr_err("%s: requested chip-select is disabled\n", __func__);
                return -ENODEV;
+        }
        gpmc_cs_get_memconf(cs, &old_base, &size);
        if (base == old_base)
                return 0;
@@ -545,9 +549,10 @@ int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
        struct resource *res = &gpmc_cs_mem[cs];
        int r = -1;
-        if (cs > GPMC_CS_NUM)
+        if (cs > gpmc_cs_num) {
+                pr_err("%s: requested chip-select is disabled\n", __func__);
                return -ENODEV;
+        }
        size = gpmc_mem_align(size);
        if (size > (1 << GPMC_SECTION_SHIFT))
                return -ENOMEM;
@@ -582,7 +587,7 @@ EXPORT_SYMBOL(gpmc_cs_request);
 void gpmc_cs_free(int cs)
 {
        spin_lock(&gpmc_mem_lock);
-        if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) {
+        if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
                printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
                BUG();
                spin_unlock(&gpmc_mem_lock);
@@ -777,7 +782,7 @@ static void gpmc_mem_exit(void)
 {
        int cs;
-        for (cs = 0; cs < GPMC_CS_NUM; cs++) {
+        for (cs = 0; cs < gpmc_cs_num; cs++) {
                if (!gpmc_cs_mem_enabled(cs))
                        continue;
                gpmc_cs_delete_mem(cs);
@@ -798,7 +803,7 @@ static void gpmc_mem_init(void)
        gpmc_mem_root.end = GPMC_MEM_END;
        /* Reserve all regions that has been set up by bootloader */
-        for (cs = 0; cs < GPMC_CS_NUM; cs++) {
+        for (cs = 0; cs < gpmc_cs_num; cs++) {
                u32 base, size;
                if (!gpmc_cs_mem_enabled(cs))
@@ -1245,7 +1250,6 @@ void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
        p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
        p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
-        p->device_nand = of_property_read_bool(np, "gpmc,device-nand");
        of_property_read_u32(np, "gpmc,device-width", &p->device_width);
        of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
@@ -1345,6 +1349,13 @@ static const char * const nand_ecc_opts[] = {
        [OMAP_ECC_BCH8_CODE_HW]                 = "bch8",
 };
+static const char * const nand_xfer_types[] = {
+        [NAND_OMAP_PREFETCH_POLLED]             = "prefetch-polled",
+        [NAND_OMAP_POLLED]                      = "polled",
+        [NAND_OMAP_PREFETCH_DMA]                = "prefetch-dma",
+        [NAND_OMAP_PREFETCH_IRQ]                = "prefetch-irq",
+};
 static int gpmc_probe_nand_child(struct platform_device *pdev,
                                 struct device_node *child)
 {
@@ -1374,6 +1385,13 @@ static int gpmc_probe_nand_child(struct platform_device *pdev,
                                break;
                        }
+        if (!of_property_read_string(child, "ti,nand-xfer-type", &s))
+                for (val = 0; val < ARRAY_SIZE(nand_xfer_types); val++)
+                        if (!strcasecmp(s, nand_xfer_types[val])) {
+                                gpmc_nand_data->xfer_type = val;
+                                break;
+                        }
        val = of_get_nand_bus_width(child);
        if (val == 16)
                gpmc_nand_data->devsize = NAND_BUSWIDTH_16;
@@ -1513,6 +1531,20 @@ static int gpmc_probe_dt(struct platform_device *pdev)
        if (!of_id)
                return 0;
+        ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
+                                   &gpmc_cs_num);
+        if (ret < 0) {
+                pr_err("%s: number of chip-selects not defined\n", __func__);
+                return ret;
+        } else if (gpmc_cs_num < 1) {
+                pr_err("%s: all chip-selects are disabled\n", __func__);
+                return -EINVAL;
+        } else if (gpmc_cs_num > GPMC_CS_NUM) {
+                pr_err("%s: number of supported chip-selects cannot be > %d\n",
+                                         __func__, GPMC_CS_NUM);
+                return -EINVAL;
+        }
        ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
                                   &gpmc_nr_waitpins);
        if (ret < 0) {
@@ -1577,7 +1609,8 @@ static int gpmc_probe(struct platform_device *pdev)
                return PTR_ERR(gpmc_l3_clk);
        }
-        clk_prepare_enable(gpmc_l3_clk);
+        pm_runtime_enable(&pdev->dev);
+        pm_runtime_get_sync(&pdev->dev);
        gpmc_dev = &pdev->dev;
@@ -1610,12 +1643,14 @@ static int gpmc_probe(struct platform_device *pdev)
        /* Now the GPMC is initialised, unreserve the chip-selects */
        gpmc_cs_map = 0;
-        if (!pdev->dev.of_node)
+        if (!pdev->dev.of_node) {
+                gpmc_cs_num      = GPMC_CS_NUM;
                gpmc_nr_waitpins = GPMC_NR_WAITPINS;
+        }
        rc = gpmc_probe_dt(pdev);
        if (rc < 0) {
-                clk_disable_unprepare(gpmc_l3_clk);
+                pm_runtime_put_sync(&pdev->dev);
                clk_put(gpmc_l3_clk);
                dev_err(gpmc_dev, "failed to probe DT parameters\n");
                return rc;
@@ -1628,10 +1663,30 @@ static int gpmc_remove(struct platform_device *pdev)
 {
        gpmc_free_irq();
        gpmc_mem_exit();
+        pm_runtime_put_sync(&pdev->dev);
+        pm_runtime_disable(&pdev->dev);
        gpmc_dev = NULL;
        return 0;
 }
+#ifdef CONFIG_PM_SLEEP
+static int gpmc_suspend(struct device *dev)
+{
+        omap3_gpmc_save_context();
+        pm_runtime_put_sync(dev);
+        return 0;
+}
+static int gpmc_resume(struct device *dev)
+{
+        pm_runtime_get_sync(dev);
+        omap3_gpmc_restore_context();
+        return 0;
+}
+#endif
+static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
 static struct platform_driver gpmc_driver = {
        .probe          = gpmc_probe,
        .remove         = gpmc_remove,
@@ -1639,6 +1694,7 @@ static struct platform_driver gpmc_driver = {
                .name   = DEVICE_NAME,
                .owner  = THIS_MODULE,
                .of_match_table = of_match_ptr(gpmc_dt_ids),
+                .pm     = &gpmc_pm_ops,
        },
 };
@@ -1678,7 +1734,7 @@ static int __init omap_gpmc_init(void)
        pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0);
        WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
-        return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
+        return PTR_RET(pdev);
 }
 omap_postcore_initcall(omap_gpmc_init);
@@ -1701,7 +1757,6 @@ static irqreturn_t gpmc_handle_irq(int irq, void *dev)
        return IRQ_HANDLED;
 }
-#ifdef CONFIG_ARCH_OMAP3
 static struct omap3_gpmc_regs gpmc_context;
 void omap3_gpmc_save_context(void)
@@ -1715,7 +1770,7 @@ void omap3_gpmc_save_context(void)
        gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
        gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
        gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
-        for (i = 0; i < GPMC_CS_NUM; i++) {
+        for (i = 0; i < gpmc_cs_num; i++) {
                gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
                if (gpmc_context.cs_context[i].is_valid) {
                        gpmc_context.cs_context[i].config1 =
@@ -1747,7 +1802,7 @@ void omap3_gpmc_restore_context(void)
        gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
        gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
        gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
-        for (i = 0; i < GPMC_CS_NUM; i++) {
+        for (i = 0; i < gpmc_cs_num; i++) {
                if (gpmc_context.cs_context[i].is_valid) {
                        gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
                                gpmc_context.cs_context[i].config1);
@@ -1766,4 +1821,3 @@ void omap3_gpmc_restore_context(void)
                }
        }
 }
-#endif /* CONFIG_ARCH_OMAP3 */
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 2ef1f8714fcf..07d4c7b35754 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -29,7 +29,6 @@
 static u16 control_pbias_offset;
 static u16 control_devconf1_offset;
-static u16 control_mmc1;
 #define HSMMC_NAME_LEN  9
@@ -121,57 +120,6 @@ static void omap_hsmmc1_after_set_reg(struct device *dev, int slot,
        }
 }
-static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
-                                  int power_on, int vdd)
-{
-        u32 reg;
-        /*
-         * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
-         * card with Vcc regulator (from twl4030 or whatever).  OMAP has both
-         * 1.8V and 3.0V modes, controlled by the PBIAS register.
-         */
-        reg = omap4_ctrl_pad_readl(control_pbias_offset);
-        reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
-                OMAP4_MMC1_PWRDNZ_MASK |
-                OMAP4_MMC1_PBIASLITE_VMODE_MASK);
-        omap4_ctrl_pad_writel(reg, control_pbias_offset);
-}
-static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
-                                 int power_on, int vdd)
-{
-        u32 reg;
-        unsigned long timeout;
-        if (power_on) {
-                reg = omap4_ctrl_pad_readl(control_pbias_offset);
-                reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK;
-                if ((1 << vdd) <= MMC_VDD_165_195)
-                        reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK;
-                else
-                        reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK;
-                reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
-                        OMAP4_MMC1_PWRDNZ_MASK);
-                omap4_ctrl_pad_writel(reg, control_pbias_offset);
-                timeout = jiffies + msecs_to_jiffies(5);
-                do {
-                        reg = omap4_ctrl_pad_readl(control_pbias_offset);
-                        if (!(reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK))
-                                break;
-                        usleep_range(100, 200);
-                } while (!time_after(jiffies, timeout));
-                if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) {
-                        pr_err("Pbias Voltage is not same as LDO\n");
-                        /* Caution : On VMODE_ERROR Power Down MMC IO */
-                        reg &= ~(OMAP4_MMC1_PWRDNZ_MASK);
-                        omap4_ctrl_pad_writel(reg, control_pbias_offset);
-                }
-        }
-}
 static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc)
 {
        u32 reg;
@@ -317,11 +265,7 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
        mmc->slots[0].pm_caps = c->pm_caps;
        mmc->slots[0].internal_clock = !c->ext_clock;
        mmc->max_freq = c->max_freq;
-        if (cpu_is_omap44xx())
+        mmc->reg_offset = 0;
-                mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
-        else
-                mmc->reg_offset = 0;
        mmc->get_context_loss_count = hsmmc_get_context_loss;
        mmc->slots[0].switch_pin = c->gpio_cd;
@@ -368,24 +312,14 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
        if (!soc_is_am35xx())
                mmc->slots[0].features |= HSMMC_HAS_PBIAS;
-        if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
-                mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
        switch (c->mmc) {
        case 1:
                if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
                        /* on-chip level shifting via PBIAS0/PBIAS1 */
-                        if (cpu_is_omap44xx()) {
+                        mmc->slots[0].before_set_reg =
-                                mmc->slots[0].before_set_reg =
+                                        omap_hsmmc1_before_set_reg;
-                                                omap4_hsmmc1_before_set_reg;
+                        mmc->slots[0].after_set_reg =
-                                mmc->slots[0].after_set_reg =
+                                        omap_hsmmc1_after_set_reg;
-                                                omap4_hsmmc1_after_set_reg;
-                        } else {
-                                mmc->slots[0].before_set_reg =
-                                                omap_hsmmc1_before_set_reg;
-                                mmc->slots[0].after_set_reg =
-                                                omap_hsmmc1_after_set_reg;
-                        }
                }
                if (soc_is_am35xx())
@@ -563,34 +497,17 @@ free_mmc:
 void __init omap_hsmmc_init(struct omap2_hsmmc_info *controllers)
 {
-        u32 reg;
        if (omap_hsmmc_done)
                return;
        omap_hsmmc_done = 1;
-        if (!cpu_is_omap44xx()) {
+        if (cpu_is_omap2430()) {
-                if (cpu_is_omap2430()) {
+                control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
-                        control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
+                control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
-                        control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
-                } else {
-                        control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
-                        control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
-                }
        } else {
-                control_pbias_offset =
+                control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
-                        OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
+                control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
-                control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
-                reg = omap4_ctrl_pad_readl(control_mmc1);
-                reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
-                        OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
-                reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
-                        OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
-                reg |= (OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK |
-                        OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
-                        OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
-                omap4_ctrl_pad_writel(reg, control_mmc1);
        }
        for (; controllers->mmc; controllers++)
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 1272c41d4749..2dc62a25f2c3 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -55,7 +55,7 @@ int omap_type(void)
        if (cpu_is_omap24xx()) {
                val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
-        } else if (soc_is_am33xx()) {
+        } else if (soc_is_am33xx() || soc_is_am43xx()) {
                val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
        } else if (cpu_is_omap34xx()) {
                val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
@@ -209,6 +209,8 @@ static void __init omap3_cpuinfo(void)
                cpu_name = "TI816X";
        } else if (soc_is_am335x()) {
                cpu_name =  "AM335X";
+        } else if (soc_is_am437x()) {
+                cpu_name =  "AM437x";
        } else if (cpu_is_ti814x()) {
                cpu_name = "TI814X";
        } else if (omap3_has_iva() && omap3_has_sgx()) {
@@ -302,6 +304,19 @@ void __init ti81xx_check_features(void)
        omap3_cpuinfo();
 }
+void __init am33xx_check_features(void)
+{
+        u32 status;
+        omap_features = OMAP3_HAS_NEON;
+        status = omap_ctrl_readl(AM33XX_DEV_FEATURE);
+        if (status & AM33XX_SGX_MASK)
+                omap_features |= OMAP3_HAS_SGX;
+        omap3_cpuinfo();
+}
 void __init omap3xxx_check_revision(void)
 {
        const char *cpu_rev;
@@ -405,11 +420,18 @@ void __init omap3xxx_check_revision(void)
                        cpu_rev = "1.0";
                        break;
                case 1:
-                /* FALLTHROUGH */
-                default:
                        omap_revision = TI8168_REV_ES1_1;
                        cpu_rev = "1.1";
                        break;
+                case 2:
+                        omap_revision = TI8168_REV_ES2_0;
+                        cpu_rev = "2.0";
+                        break;
+                case 3:
+                        /* FALLTHROUGH */
+                default:
+                        omap_revision = TI8168_REV_ES2_1;
+                        cpu_rev = "2.1";
                }
                break;
        case 0xb944:
@@ -430,6 +452,10 @@ void __init omap3xxx_check_revision(void)
                        break;
                }
                break;
+        case 0xb98c:
+                omap_revision = AM437X_REV_ES1_0;
+                cpu_rev = "1.0";
+                break;
        case 0xb8f2:
                switch (rev) {
                case 0:
@@ -601,7 +627,7 @@ void __init omap2_set_globals_tap(u32 class, void __iomem *tap)
 #ifdef CONFIG_SOC_BUS
-static const char const *omap_types[] = {
+static const char * const omap_types[] = {
        [OMAP2_DEVICE_TYPE_TEST]        = "TST",
        [OMAP2_DEVICE_TYPE_EMU]         = "EMU",
        [OMAP2_DEVICE_TYPE_SEC]         = "HS",
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 09abf99e9e57..4a3f06f02859 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -202,7 +202,7 @@ static struct map_desc omapti81xx_io_desc[] __initdata = {
 };
 #endif
-#ifdef CONFIG_SOC_AM33XX
+#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
 static struct map_desc omapam33xx_io_desc[] __initdata = {
        {
                .virtual        = L4_34XX_VIRT,
@@ -318,7 +318,7 @@ void __init ti81xx_map_io(void)
 }
 #endif
-#ifdef CONFIG_SOC_AM33XX
+#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
 void __init am33xx_map_io(void)
 {
        iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
@@ -394,7 +394,7 @@ static void __init omap_hwmod_init_postsetup(void)
        omap_pm_if_early_init();
 }
-static void __init omap_common_late_init(void)
+static void __init __maybe_unused omap_common_late_init(void)
 {
        omap_mux_late_init();
        omap2_common_pm_late_init();
@@ -576,8 +576,7 @@ void __init am33xx_init_early(void)
        omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
        omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
        omap3xxx_check_revision();
-        ti81xx_check_features();
+        am33xx_check_features();
-        am33xx_voltagedomains_init();
        am33xx_powerdomains_init();
        am33xx_clockdomains_init();
        am33xx_hwmod_init();
@@ -586,6 +585,19 @@ void __init am33xx_init_early(void)
 }
 #endif
+#ifdef CONFIG_SOC_AM43XX
+void __init am43xx_init_early(void)
+{
+        omap2_set_globals_tap(AM335X_CLASS,
+                              AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
+        omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
+                                  NULL);
+        omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE));
+        omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL);
+        omap3xxx_check_revision();
+}
+#endif
 #ifdef CONFIG_ARCH_OMAP4
 void __init omap4430_init_early(void)
 {
@@ -631,7 +643,13 @@ void __init omap5_init_early(void)
        omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
        omap_prm_base_init();
        omap_cm_base_init();
+        omap44xx_prm_init();
        omap5xxx_check_revision();
+        omap54xx_voltagedomains_init();
+        omap54xx_powerdomains_init();
+        omap54xx_clockdomains_init();
+        omap54xx_hwmod_init();
+        omap_hwmod_init_postsetup();
 }
 #endif
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
deleted file mode 100644
index 0b080267b7f6..000000000000
--- a/arch/arm/mach-omap2/mailbox.c
+++ /dev/null
@@ -1,430 +0,0 @@
-/*
- * Mailbox reservation modules for OMAP2/3
- *
- * Copyright (C) 2006-2009 Nokia Corporation
- * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
- *        and  Paul Mundt
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/module.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/pm_runtime.h>
-#include <plat/mailbox.h>
-#include "soc.h"
-#define MAILBOX_REVISION                0x000
-#define MAILBOX_MESSAGE(m)              (0x040 + 4 * (m))
-#define MAILBOX_FIFOSTATUS(m)           (0x080 + 4 * (m))
-#define MAILBOX_MSGSTATUS(m)            (0x0c0 + 4 * (m))
-#define MAILBOX_IRQSTATUS(u)            (0x100 + 8 * (u))
-#define MAILBOX_IRQENABLE(u)            (0x104 + 8 * (u))
-#define OMAP4_MAILBOX_IRQSTATUS(u)      (0x104 + 0x10 * (u))
-#define OMAP4_MAILBOX_IRQENABLE(u)      (0x108 + 0x10 * (u))
-#define OMAP4_MAILBOX_IRQENABLE_CLR(u)  (0x10c + 0x10 * (u))
-#define MAILBOX_IRQ_NEWMSG(m)           (1 << (2 * (m)))
-#define MAILBOX_IRQ_NOTFULL(m)          (1 << (2 * (m) + 1))
-#define MBOX_REG_SIZE                   0x120
-#define OMAP4_MBOX_REG_SIZE             0x130
-#define MBOX_NR_REGS                    (MBOX_REG_SIZE / sizeof(u32))
-#define OMAP4_MBOX_NR_REGS              (OMAP4_MBOX_REG_SIZE / sizeof(u32))
-static void __iomem *mbox_base;
-struct omap_mbox2_fifo {
-        unsigned long msg;
-        unsigned long fifo_stat;
-        unsigned long msg_stat;
-};
-struct omap_mbox2_priv {
-        struct omap_mbox2_fifo tx_fifo;
-        struct omap_mbox2_fifo rx_fifo;
-        unsigned long irqenable;
-        unsigned long irqstatus;
-        u32 newmsg_bit;
-        u32 notfull_bit;
-        u32 ctx[OMAP4_MBOX_NR_REGS];
-        unsigned long irqdisable;
-};
-static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
-                                  omap_mbox_type_t irq);
-static inline unsigned int mbox_read_reg(size_t ofs)
-{
-        return __raw_readl(mbox_base + ofs);
-}
-static inline void mbox_write_reg(u32 val, size_t ofs)
-{
-        __raw_writel(val, mbox_base + ofs);
-}
-/* Mailbox H/W preparations */
-static int omap2_mbox_startup(struct omap_mbox *mbox)
-{
-        u32 l;
-        pm_runtime_enable(mbox->dev->parent);
-        pm_runtime_get_sync(mbox->dev->parent);
-        l = mbox_read_reg(MAILBOX_REVISION);
-        pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
-        return 0;
-}
-static void omap2_mbox_shutdown(struct omap_mbox *mbox)
-{
-        pm_runtime_put_sync(mbox->dev->parent);
-        pm_runtime_disable(mbox->dev->parent);
-}
-/* Mailbox FIFO handle functions */
-static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
-{
-        struct omap_mbox2_fifo *fifo =
-                &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
-        return (mbox_msg_t) mbox_read_reg(fifo->msg);
-}
-static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
-{
-        struct omap_mbox2_fifo *fifo =
-                &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
-        mbox_write_reg(msg, fifo->msg);
-}
-static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
-{
-        struct omap_mbox2_fifo *fifo =
-                &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
-        return (mbox_read_reg(fifo->msg_stat) == 0);
-}
-static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
-{
-        struct omap_mbox2_fifo *fifo =
-                &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
-        return mbox_read_reg(fifo->fifo_stat);
-}
-/* Mailbox IRQ handle functions */
-static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
-                omap_mbox_type_t irq)
-{
-        struct omap_mbox2_priv *p = mbox->priv;
-        u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
-        l = mbox_read_reg(p->irqenable);
-        l |= bit;
-        mbox_write_reg(l, p->irqenable);
-}
-static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
-                omap_mbox_type_t irq)
-{
-        struct omap_mbox2_priv *p = mbox->priv;
-        u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
-        if (!cpu_is_omap44xx())
-                bit = mbox_read_reg(p->irqdisable) & ~bit;
-        mbox_write_reg(bit, p->irqdisable);
-}
-static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
-                omap_mbox_type_t irq)
-{
-        struct omap_mbox2_priv *p = mbox->priv;
-        u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
-        mbox_write_reg(bit, p->irqstatus);
-        /* Flush posted write for irq status to avoid spurious interrupts */
-        mbox_read_reg(p->irqstatus);
-}
-static int omap2_mbox_is_irq(struct omap_mbox *mbox,
-                omap_mbox_type_t irq)
-{
-        struct omap_mbox2_priv *p = mbox->priv;
-        u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
-        u32 enable = mbox_read_reg(p->irqenable);
-        u32 status = mbox_read_reg(p->irqstatus);
-        return (int)(enable & status & bit);
-}
-static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
-{
-        int i;
-        struct omap_mbox2_priv *p = mbox->priv;
-        int nr_regs;
-        if (cpu_is_omap44xx())
-                nr_regs = OMAP4_MBOX_NR_REGS;
-        else
-                nr_regs = MBOX_NR_REGS;
-        for (i = 0; i < nr_regs; i++) {
-                p->ctx[i] = mbox_read_reg(i * sizeof(u32));
-                dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
-                        i, p->ctx[i]);
-        }
-}
-static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
-{
-        int i;
-        struct omap_mbox2_priv *p = mbox->priv;
-        int nr_regs;
-        if (cpu_is_omap44xx())
-                nr_regs = OMAP4_MBOX_NR_REGS;
-        else
-                nr_regs = MBOX_NR_REGS;
-        for (i = 0; i < nr_regs; i++) {
-                mbox_write_reg(p->ctx[i], i * sizeof(u32));
-                dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
-                        i, p->ctx[i]);
-        }
-}
-static struct omap_mbox_ops omap2_mbox_ops = {
-        .type           = OMAP_MBOX_TYPE2,
-        .startup        = omap2_mbox_startup,
-        .shutdown       = omap2_mbox_shutdown,
-        .fifo_read      = omap2_mbox_fifo_read,
-        .fifo_write     = omap2_mbox_fifo_write,
-        .fifo_empty     = omap2_mbox_fifo_empty,
-        .fifo_full      = omap2_mbox_fifo_full,
-        .enable_irq     = omap2_mbox_enable_irq,
-        .disable_irq    = omap2_mbox_disable_irq,
-        .ack_irq        = omap2_mbox_ack_irq,
-        .is_irq         = omap2_mbox_is_irq,
-        .save_ctx       = omap2_mbox_save_ctx,
-        .restore_ctx    = omap2_mbox_restore_ctx,
-};
-/*
- * MAILBOX 0: ARM -> DSP,
- * MAILBOX 1: ARM <- DSP.
- * MAILBOX 2: ARM -> IVA,
- * MAILBOX 3: ARM <- IVA.
- */
-/* FIXME: the following structs should be filled automatically by the user id */
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP2)
-/* DSP */
-static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
-        .tx_fifo = {
-                .msg            = MAILBOX_MESSAGE(0),
-                .fifo_stat      = MAILBOX_FIFOSTATUS(0),
-        },
-        .rx_fifo = {
-                .msg            = MAILBOX_MESSAGE(1),
-                .msg_stat       = MAILBOX_MSGSTATUS(1),
-        },
-        .irqenable      = MAILBOX_IRQENABLE(0),
-        .irqstatus      = MAILBOX_IRQSTATUS(0),
-        .notfull_bit    = MAILBOX_IRQ_NOTFULL(0),
-        .newmsg_bit     = MAILBOX_IRQ_NEWMSG(1),
-        .irqdisable     = MAILBOX_IRQENABLE(0),
-};
-struct omap_mbox mbox_dsp_info = {
-        .name   = "dsp",
-        .ops    = &omap2_mbox_ops,
-        .priv   = &omap2_mbox_dsp_priv,
-};
-#endif
-#if defined(CONFIG_ARCH_OMAP3)
-struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL };
-#endif
-#if defined(CONFIG_SOC_OMAP2420)
-/* IVA */
-static struct omap_mbox2_priv omap2_mbox_iva_priv = {
-        .tx_fifo = {
-                .msg            = MAILBOX_MESSAGE(2),
-                .fifo_stat      = MAILBOX_FIFOSTATUS(2),
-        },
-        .rx_fifo = {
-                .msg            = MAILBOX_MESSAGE(3),
-                .msg_stat       = MAILBOX_MSGSTATUS(3),
-        },
-        .irqenable      = MAILBOX_IRQENABLE(3),
-        .irqstatus      = MAILBOX_IRQSTATUS(3),
-        .notfull_bit    = MAILBOX_IRQ_NOTFULL(2),
-        .newmsg_bit     = MAILBOX_IRQ_NEWMSG(3),
-        .irqdisable     = MAILBOX_IRQENABLE(3),
-};
-static struct omap_mbox mbox_iva_info = {
-        .name   = "iva",
-        .ops    = &omap2_mbox_ops,
-        .priv   = &omap2_mbox_iva_priv,
-};
-#endif
-#ifdef CONFIG_ARCH_OMAP2
-struct omap_mbox *omap2_mboxes[] = {
-        &mbox_dsp_info,
-#ifdef CONFIG_SOC_OMAP2420
-        &mbox_iva_info,
-#endif
-        NULL
-};
-#endif
-#if defined(CONFIG_ARCH_OMAP4)
-/* OMAP4 */
-static struct omap_mbox2_priv omap2_mbox_1_priv = {
-        .tx_fifo = {
-                .msg            = MAILBOX_MESSAGE(0),
-                .fifo_stat      = MAILBOX_FIFOSTATUS(0),
-        },
-        .rx_fifo = {
-                .msg            = MAILBOX_MESSAGE(1),
-                .msg_stat       = MAILBOX_MSGSTATUS(1),
-        },
-        .irqenable      = OMAP4_MAILBOX_IRQENABLE(0),
-        .irqstatus      = OMAP4_MAILBOX_IRQSTATUS(0),
-        .notfull_bit    = MAILBOX_IRQ_NOTFULL(0),
-        .newmsg_bit     = MAILBOX_IRQ_NEWMSG(1),
-        .irqdisable     = OMAP4_MAILBOX_IRQENABLE_CLR(0),
-};
-struct omap_mbox mbox_1_info = {
-        .name   = "mailbox-1",
-        .ops    = &omap2_mbox_ops,
-        .priv   = &omap2_mbox_1_priv,
-};
-static struct omap_mbox2_priv omap2_mbox_2_priv = {
-        .tx_fifo = {
-                .msg            = MAILBOX_MESSAGE(3),
-                .fifo_stat      = MAILBOX_FIFOSTATUS(3),
-        },
-        .rx_fifo = {
-                .msg            = MAILBOX_MESSAGE(2),
-                .msg_stat       = MAILBOX_MSGSTATUS(2),
-        },
-        .irqenable      = OMAP4_MAILBOX_IRQENABLE(0),
-        .irqstatus      = OMAP4_MAILBOX_IRQSTATUS(0),
-        .notfull_bit    = MAILBOX_IRQ_NOTFULL(3),
-        .newmsg_bit     = MAILBOX_IRQ_NEWMSG(2),
-        .irqdisable     = OMAP4_MAILBOX_IRQENABLE_CLR(0),
-};
-struct omap_mbox mbox_2_info = {
-        .name   = "mailbox-2",
-        .ops    = &omap2_mbox_ops,
-        .priv   = &omap2_mbox_2_priv,
-};
-struct omap_mbox *omap4_mboxes[] = { &mbox_1_info, &mbox_2_info, NULL };
-#endif
-static int omap2_mbox_probe(struct platform_device *pdev)
-{
-        struct resource *mem;
-        int ret;
-        struct omap_mbox **list;
-        if (false)
-                ;
-#if defined(CONFIG_ARCH_OMAP3)
-        else if (cpu_is_omap34xx()) {
-                list = omap3_mboxes;
-                list[0]->irq = platform_get_irq(pdev, 0);
-        }
-#endif
-#if defined(CONFIG_ARCH_OMAP2)
-        else if (cpu_is_omap2430()) {
-                list = omap2_mboxes;
-                list[0]->irq = platform_get_irq(pdev, 0);
-        } else if (cpu_is_omap2420()) {
-                list = omap2_mboxes;
-                list[0]->irq = platform_get_irq_byname(pdev, "dsp");
-                list[1]->irq = platform_get_irq_byname(pdev, "iva");
-        }
-#endif
-#if defined(CONFIG_ARCH_OMAP4)
-        else if (cpu_is_omap44xx()) {
-                list = omap4_mboxes;
-                list[0]->irq = list[1]->irq = platform_get_irq(pdev, 0);
-        }
-#endif
-        else {
-                pr_err("%s: platform not supported\n", __func__);
-                return -ENODEV;
-        }
-        mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        mbox_base = ioremap(mem->start, resource_size(mem));
-        if (!mbox_base)
-                return -ENOMEM;
-        ret = omap_mbox_register(&pdev->dev, list);
-        if (ret) {
-                iounmap(mbox_base);
-                return ret;
-        }
-        return 0;
-}
-static int omap2_mbox_remove(struct platform_device *pdev)
-{
-        omap_mbox_unregister();
-        iounmap(mbox_base);
-        return 0;
-}
-static struct platform_driver omap2_mbox_driver = {
-        .probe = omap2_mbox_probe,
-        .remove = omap2_mbox_remove,
-        .driver = {
-                .name = "omap-mailbox",
-        },
-};
-static int __init omap2_mbox_init(void)
-{
-        return platform_driver_register(&omap2_mbox_driver);
-}
-static void __exit omap2_mbox_exit(void)
-{
-        platform_driver_unregister(&omap2_mbox_driver);
-}
-module_init(omap2_mbox_init);
-module_exit(omap2_mbox_exit);
-MODULE_LICENSE("GPL v2");
-MODULE_DESCRIPTION("omap mailbox: omap2/3/4 architecture specific functions");
-MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>");
-MODULE_AUTHOR("Paul Mundt");
-MODULE_ALIAS("platform:omap2-mailbox");
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index fdb22f14021f..5d2080ef7923 100644
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -10,7 +10,6 @@
 #include "mux2420.h"
 #include "mux2430.h"
 #include "mux34xx.h"
-#include "mux44xx.h"
 #define OMAP_MUX_TERMINATOR     0xffff
@@ -64,8 +63,6 @@
 /* Flags for omapX_mux_init */
 #define OMAP_PACKAGE_MASK               0xffff
-#define OMAP_PACKAGE_CBS                8               /* 547-pin 0.40 0.40 */
-#define OMAP_PACKAGE_CBL                7               /* 547-pin 0.40 0.40 */
 #define OMAP_PACKAGE_CBP                6               /* 515-pin 0.40 0.50 */
 #define OMAP_PACKAGE_CUS                5               /* 423-pin 0.65 */
 #define OMAP_PACKAGE_CBB                4               /* 515-pin 0.40 0.50 */
diff --git a/arch/arm/mach-omap2/mux44xx.c b/arch/arm/mach-omap2/mux44xx.c
deleted file mode 100644
index f5a74daab2ff..000000000000
--- a/arch/arm/mach-omap2/mux44xx.c
+++ /dev/null
@@ -1,1356 +0,0 @@
-/*
- * OMAP44xx ES1.0 pin mux definition
- *
- * Copyright (C) 2010 Texas Instruments, Inc.
- *
- * Benoit Cousson (b-cousson@ti.com)
- *
- * - Based on mux34xx.c done by Tony Lindgren <tony@atomide.com>
- *
- * This file is automatically generated from the OMAP hardware databases.
- * We respectfully ask that any modifications to this file be coordinated
- * with the public linux-omap@vger.kernel.org mailing list and the
- * authors above to ensure that the autogeneration scripts are kept
- * up-to-date with the file contents.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/module.h>
-#include <linux/init.h>
-#include "mux.h"
-#ifdef CONFIG_OMAP_MUX
-#define _OMAP4_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7)  \
-{                                                                       \
-        .reg_offset     = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET),        \
-        .gpio           = (g),                                          \
-        .muxnames       = { m0, m1, m2, m3, m4, m5, m6, m7 },           \
-}
-#else
-#define _OMAP4_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7)  \
-{                                                                       \
-        .reg_offset     = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET),        \
-        .gpio           = (g),                                          \
-}
-#endif
-#define _OMAP4_BALLENTRY(M0, bb, bt)                            \
-{                                                                       \
-        .reg_offset     = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET),        \
-        .balls          = { bb, bt },                                   \
-}
-/*
- * Superset of all mux modes for omap4 ES1.0
- */
-static struct omap_mux __initdata omap4_core_muxmodes[] = {
-        _OMAP4_MUXENTRY(GPMC_AD0, 0, "gpmc_ad0", "sdmmc2_dat0", NULL, NULL,
-                        NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD1, 0, "gpmc_ad1", "sdmmc2_dat1", NULL, NULL,
-                        NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD2, 0, "gpmc_ad2", "sdmmc2_dat2", NULL, NULL,
-                        NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD3, 0, "gpmc_ad3", "sdmmc2_dat3", NULL, NULL,
-                        NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD4, 0, "gpmc_ad4", "sdmmc2_dat4",
-                        "sdmmc2_dir_dat0", NULL, NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD5, 0, "gpmc_ad5", "sdmmc2_dat5",
-                        "sdmmc2_dir_dat1", NULL, NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD6, 0, "gpmc_ad6", "sdmmc2_dat6",
-                        "sdmmc2_dir_cmd", NULL, NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD7, 0, "gpmc_ad7", "sdmmc2_dat7",
-                        "sdmmc2_clk_fdbk", NULL, NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD8, 32, "gpmc_ad8", "kpd_row0", "c2c_data15",
-                        "gpio_32", NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD9, 33, "gpmc_ad9", "kpd_row1", "c2c_data14",
-                        "gpio_33", NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD10, 34, "gpmc_ad10", "kpd_row2", "c2c_data13",
-                        "gpio_34", NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD11, 35, "gpmc_ad11", "kpd_row3", "c2c_data12",
-                        "gpio_35", NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD12, 36, "gpmc_ad12", "kpd_col0", "c2c_data11",
-                        "gpio_36", NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD13, 37, "gpmc_ad13", "kpd_col1", "c2c_data10",
-                        "gpio_37", NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD14, 38, "gpmc_ad14", "kpd_col2", "c2c_data9",
-                        "gpio_38", NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD15, 39, "gpmc_ad15", "kpd_col3", "c2c_data8",
-                        "gpio_39", NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_A16, 40, "gpmc_a16", "kpd_row4", "c2c_datain0",
-                        "gpio_40", "venc_656_data0", NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_A17, 41, "gpmc_a17", "kpd_row5", "c2c_datain1",
-                        "gpio_41", "venc_656_data1", NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_A18, 42, "gpmc_a18", "kpd_row6", "c2c_datain2",
-                        "gpio_42", "venc_656_data2", NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_A19, 43, "gpmc_a19", "kpd_row7", "c2c_datain3",
-                        "gpio_43", "venc_656_data3", NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_A20, 44, "gpmc_a20", "kpd_col4", "c2c_datain4",
-                        "gpio_44", "venc_656_data4", NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_A21, 45, "gpmc_a21", "kpd_col5", "c2c_datain5",
-                        "gpio_45", "venc_656_data5", NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_A22, 46, "gpmc_a22", "kpd_col6", "c2c_datain6",
-                        "gpio_46", "venc_656_data6", NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_A23, 47, "gpmc_a23", "kpd_col7", "c2c_datain7",
-                        "gpio_47", "venc_656_data7", NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_A24, 48, "gpmc_a24", NULL, "c2c_clkout0",
-                        "gpio_48", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_A25, 49, "gpmc_a25", NULL, "c2c_clkout1",
-                        "gpio_49", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_NCS0, 50, "gpmc_ncs0", NULL, NULL, "gpio_50",
-                        "sys_ndmareq0", NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_NCS1, 51, "gpmc_ncs1", NULL, "c2c_dataout6",
-                        "gpio_51", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_NCS2, 52, "gpmc_ncs2", NULL, "c2c_dataout7",
-                        "gpio_52", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_NCS3, 53, "gpmc_ncs3", "gpmc_dir",
-                        "c2c_dataout4", "gpio_53", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_NWP, 54, "gpmc_nwp", "dsi1_te0", NULL, "gpio_54",
-                        "sys_ndmareq1", NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_CLK, 55, "gpmc_clk", NULL, NULL, "gpio_55",
-                        "sys_ndmareq2", NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_NADV_ALE, 56, "gpmc_nadv_ale", "dsi1_te1", NULL,
-                        "gpio_56", "sys_ndmareq3", NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_NOE, 0, "gpmc_noe", "sdmmc2_clk", NULL, NULL,
-                        NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_NWE, 0, "gpmc_nwe", "sdmmc2_cmd", NULL, NULL,
-                        NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_NBE0_CLE, 59, "gpmc_nbe0_cle", "dsi2_te0", NULL,
-                        "gpio_59", NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_NBE1, 60, "gpmc_nbe1", NULL, "c2c_dataout5",
-                        "gpio_60", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_WAIT0, 61, "gpmc_wait0", "dsi2_te1", NULL,
-                        "gpio_61", NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_WAIT1, 62, "gpmc_wait1", NULL, "c2c_dataout2",
-                        "gpio_62", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(C2C_DATA11, 100, "c2c_data11", "usbc1_icusb_txen",
-                        "c2c_dataout3", "gpio_100", "sys_ndmareq0", NULL,
-                        NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(C2C_DATA12, 101, "c2c_data12", "dsi1_te0",
-                        "c2c_clkin0", "gpio_101", "sys_ndmareq1", NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(C2C_DATA13, 102, "c2c_data13", "dsi1_te1",
-                        "c2c_clkin1", "gpio_102", "sys_ndmareq2", NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(C2C_DATA14, 103, "c2c_data14", "dsi2_te0",
-                        "c2c_dataout0", "gpio_103", "sys_ndmareq3", NULL,
-                        NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(C2C_DATA15, 104, "c2c_data15", "dsi2_te1",
-                        "c2c_dataout1", "gpio_104", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(HDMI_HPD, 63, "hdmi_hpd", NULL, NULL, "gpio_63", NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(HDMI_CEC, 64, "hdmi_cec", NULL, NULL, "gpio_64", NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(HDMI_DDC_SCL, 65, "hdmi_ddc_scl", NULL, NULL,
-                        "gpio_65", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(HDMI_DDC_SDA, 66, "hdmi_ddc_sda", NULL, NULL,
-                        "gpio_66", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(CSI21_DX0, 0, "csi21_dx0", NULL, NULL, "gpi_67", NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(CSI21_DY0, 0, "csi21_dy0", NULL, NULL, "gpi_68", NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(CSI21_DX1, 0, "csi21_dx1", NULL, NULL, "gpi_69", NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(CSI21_DY1, 0, "csi21_dy1", NULL, NULL, "gpi_70", NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(CSI21_DX2, 0, "csi21_dx2", NULL, NULL, "gpi_71", NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(CSI21_DY2, 0, "csi21_dy2", NULL, NULL, "gpi_72", NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(CSI21_DX3, 0, "csi21_dx3", NULL, NULL, "gpi_73", NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(CSI21_DY3, 0, "csi21_dy3", NULL, NULL, "gpi_74", NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(CSI21_DX4, 0, "csi21_dx4", NULL, NULL, "gpi_75", NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(CSI21_DY4, 0, "csi21_dy4", NULL, NULL, "gpi_76", NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(CSI22_DX0, 0, "csi22_dx0", NULL, NULL, "gpi_77", NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(CSI22_DY0, 0, "csi22_dy0", NULL, NULL, "gpi_78", NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(CSI22_DX1, 0, "csi22_dx1", NULL, NULL, "gpi_79", NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(CSI22_DY1, 0, "csi22_dy1", NULL, NULL, "gpi_80", NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(CAM_SHUTTER, 81, "cam_shutter", NULL, NULL, "gpio_81",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(CAM_STROBE, 82, "cam_strobe", NULL, NULL, "gpio_82",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(CAM_GLOBALRESET, 83, "cam_globalreset", NULL, NULL,
-                        "gpio_83", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(USBB1_ULPITLL_CLK, 84, "usbb1_ulpitll_clk",
-                        "hsi1_cawake", NULL, "gpio_84", "usbb1_ulpiphy_clk",
-                        NULL, "hw_dbg20", "safe_mode"),
-        _OMAP4_MUXENTRY(USBB1_ULPITLL_STP, 85, "usbb1_ulpitll_stp",
-                        "hsi1_cadata", "mcbsp4_clkr", "gpio_85",
-                        "usbb1_ulpiphy_stp", "usbb1_mm_rxdp", "hw_dbg21",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(USBB1_ULPITLL_DIR, 86, "usbb1_ulpitll_dir",
-                        "hsi1_caflag", "mcbsp4_fsr", "gpio_86",
-                        "usbb1_ulpiphy_dir", NULL, "hw_dbg22", "safe_mode"),
-        _OMAP4_MUXENTRY(USBB1_ULPITLL_NXT, 87, "usbb1_ulpitll_nxt",
-                        "hsi1_acready", "mcbsp4_fsx", "gpio_87",
-                        "usbb1_ulpiphy_nxt", "usbb1_mm_rxdm", "hw_dbg23",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT0, 88, "usbb1_ulpitll_dat0",
-                        "hsi1_acwake", "mcbsp4_clkx", "gpio_88",
-                        "usbb1_ulpiphy_dat0", "usbb1_mm_rxrcv", "hw_dbg24",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT1, 89, "usbb1_ulpitll_dat1",
-                        "hsi1_acdata", "mcbsp4_dx", "gpio_89",
-                        "usbb1_ulpiphy_dat1", "usbb1_mm_txse0", "hw_dbg25",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT2, 90, "usbb1_ulpitll_dat2",
-                        "hsi1_acflag", "mcbsp4_dr", "gpio_90",
-                        "usbb1_ulpiphy_dat2", "usbb1_mm_txdat", "hw_dbg26",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT3, 91, "usbb1_ulpitll_dat3",
-                        "hsi1_caready", NULL, "gpio_91", "usbb1_ulpiphy_dat3",
-                        "usbb1_mm_txen", "hw_dbg27", "safe_mode"),
-        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT4, 92, "usbb1_ulpitll_dat4",
-                        "dmtimer8_pwm_evt", "abe_mcbsp3_dr", "gpio_92",
-                        "usbb1_ulpiphy_dat4", NULL, "hw_dbg28", "safe_mode"),
-        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT5, 93, "usbb1_ulpitll_dat5",
-                        "dmtimer9_pwm_evt", "abe_mcbsp3_dx", "gpio_93",
-                        "usbb1_ulpiphy_dat5", NULL, "hw_dbg29", "safe_mode"),
-        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT6, 94, "usbb1_ulpitll_dat6",
-                        "dmtimer10_pwm_evt", "abe_mcbsp3_clkx", "gpio_94",
-                        "usbb1_ulpiphy_dat6", "abe_dmic_din3", "hw_dbg30",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT7, 95, "usbb1_ulpitll_dat7",
-                        "dmtimer11_pwm_evt", "abe_mcbsp3_fsx", "gpio_95",
-                        "usbb1_ulpiphy_dat7", "abe_dmic_clk3", "hw_dbg31",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(USBB1_HSIC_DATA, 96, "usbb1_hsic_data", NULL, NULL,
-                        "gpio_96", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(USBB1_HSIC_STROBE, 97, "usbb1_hsic_strobe", NULL,
-                        NULL, "gpio_97", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(USBC1_ICUSB_DP, 98, "usbc1_icusb_dp", NULL, NULL,
-                        "gpio_98", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(USBC1_ICUSB_DM, 99, "usbc1_icusb_dm", NULL, NULL,
-                        "gpio_99", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC1_CLK, 100, "sdmmc1_clk", NULL, "dpm_emu19",
-                        "gpio_100", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC1_CMD, 101, "sdmmc1_cmd", NULL, "uart1_rx",
-                        "gpio_101", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC1_DAT0, 102, "sdmmc1_dat0", NULL, "dpm_emu18",
-                        "gpio_102", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC1_DAT1, 103, "sdmmc1_dat1", NULL, "dpm_emu17",
-                        "gpio_103", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC1_DAT2, 104, "sdmmc1_dat2", NULL, "dpm_emu16",
-                        "gpio_104", "jtag_tms_tmsc", NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC1_DAT3, 105, "sdmmc1_dat3", NULL, "dpm_emu15",
-                        "gpio_105", "jtag_tck", NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC1_DAT4, 106, "sdmmc1_dat4", NULL, NULL,
-                        "gpio_106", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC1_DAT5, 107, "sdmmc1_dat5", NULL, NULL,
-                        "gpio_107", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC1_DAT6, 108, "sdmmc1_dat6", NULL, NULL,
-                        "gpio_108", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC1_DAT7, 109, "sdmmc1_dat7", NULL, NULL,
-                        "gpio_109", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_MCBSP2_CLKX, 110, "abe_mcbsp2_clkx", "mcspi2_clk",
-                        "abe_mcasp_ahclkx", "gpio_110", "usbb2_mm_rxdm",
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_MCBSP2_DR, 111, "abe_mcbsp2_dr", "mcspi2_somi",
-                        "abe_mcasp_axr", "gpio_111", "usbb2_mm_rxdp", NULL,
-                        NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_MCBSP2_DX, 112, "abe_mcbsp2_dx", "mcspi2_simo",
-                        "abe_mcasp_amute", "gpio_112", "usbb2_mm_rxrcv", NULL,
-                        NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_MCBSP2_FSX, 113, "abe_mcbsp2_fsx", "mcspi2_cs0",
-                        "abe_mcasp_afsx", "gpio_113", "usbb2_mm_txen", NULL,
-                        NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_MCBSP1_CLKX, 114, "abe_mcbsp1_clkx",
-                        "abe_slimbus1_clock", NULL, "gpio_114", NULL, NULL,
-                        NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_MCBSP1_DR, 115, "abe_mcbsp1_dr",
-                        "abe_slimbus1_data", NULL, "gpio_115", NULL, NULL,
-                        NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_MCBSP1_DX, 116, "abe_mcbsp1_dx", "sdmmc3_dat2",
-                        "abe_mcasp_aclkx", "gpio_116", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_MCBSP1_FSX, 117, "abe_mcbsp1_fsx", "sdmmc3_dat3",
-                        "abe_mcasp_amutein", "gpio_117", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_PDM_UL_DATA, 0, "abe_pdm_ul_data",
-                        "abe_mcbsp3_dr", NULL, NULL, NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_PDM_DL_DATA, 0, "abe_pdm_dl_data",
-                        "abe_mcbsp3_dx", NULL, NULL, NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_PDM_FRAME, 0, "abe_pdm_frame", "abe_mcbsp3_clkx",
-                        NULL, NULL, NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_PDM_LB_CLK, 0, "abe_pdm_lb_clk", "abe_mcbsp3_fsx",
-                        NULL, NULL, NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_CLKS, 118, "abe_clks", NULL, NULL, "gpio_118",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_DMIC_CLK1, 119, "abe_dmic_clk1", NULL, NULL,
-                        "gpio_119", "usbb2_mm_txse0", NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_DMIC_DIN1, 120, "abe_dmic_din1", NULL, NULL,
-                        "gpio_120", "usbb2_mm_txdat", NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_DMIC_DIN2, 121, "abe_dmic_din2", "slimbus2_clock",
-                        NULL, "gpio_121", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_DMIC_DIN3, 122, "abe_dmic_din3", "slimbus2_data",
-                        "abe_dmic_clk2", "gpio_122", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(UART2_CTS, 123, "uart2_cts", "sdmmc3_clk", NULL,
-                        "gpio_123", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UART2_RTS, 124, "uart2_rts", "sdmmc3_cmd", NULL,
-                        "gpio_124", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UART2_RX, 125, "uart2_rx", "sdmmc3_dat0", NULL,
-                        "gpio_125", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UART2_TX, 126, "uart2_tx", "sdmmc3_dat1", NULL,
-                        "gpio_126", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(HDQ_SIO, 127, "hdq_sio", "i2c3_sccb", "i2c2_sccb",
-                        "gpio_127", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(I2C1_SCL, 0, "i2c1_scl", NULL, NULL, NULL, NULL, NULL,
-                        NULL, NULL),
-        _OMAP4_MUXENTRY(I2C1_SDA, 0, "i2c1_sda", NULL, NULL, NULL, NULL, NULL,
-                        NULL, NULL),
-        _OMAP4_MUXENTRY(I2C2_SCL, 128, "i2c2_scl", "uart1_rx", NULL,
-                        "gpio_128", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(I2C2_SDA, 129, "i2c2_sda", "uart1_tx", NULL,
-                        "gpio_129", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(I2C3_SCL, 130, "i2c3_scl", NULL, NULL, "gpio_130",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(I2C3_SDA, 131, "i2c3_sda", NULL, NULL, "gpio_131",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(I2C4_SCL, 132, "i2c4_scl", NULL, NULL, "gpio_132",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(I2C4_SDA, 133, "i2c4_sda", NULL, NULL, "gpio_133",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(MCSPI1_CLK, 134, "mcspi1_clk", NULL, NULL, "gpio_134",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(MCSPI1_SOMI, 135, "mcspi1_somi", NULL, NULL,
-                        "gpio_135", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(MCSPI1_SIMO, 136, "mcspi1_simo", NULL, NULL,
-                        "gpio_136", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(MCSPI1_CS0, 137, "mcspi1_cs0", NULL, NULL, "gpio_137",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(MCSPI1_CS1, 138, "mcspi1_cs1", "uart1_rx", NULL,
-                        "gpio_138", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(MCSPI1_CS2, 139, "mcspi1_cs2", "uart1_cts",
-                        "slimbus2_clock", "gpio_139", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(MCSPI1_CS3, 140, "mcspi1_cs3", "uart1_rts",
-                        "slimbus2_data", "gpio_140", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(UART3_CTS_RCTX, 141, "uart3_cts_rctx", "uart1_tx",
-                        NULL, "gpio_141", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UART3_RTS_SD, 142, "uart3_rts_sd", NULL, NULL,
-                        "gpio_142", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UART3_RX_IRRX, 143, "uart3_rx_irrx",
-                        "dmtimer8_pwm_evt", NULL, "gpio_143", NULL, NULL,
-                        NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UART3_TX_IRTX, 144, "uart3_tx_irtx",
-                        "dmtimer9_pwm_evt", NULL, "gpio_144", NULL, NULL,
-                        NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC5_CLK, 145, "sdmmc5_clk", "mcspi2_clk",
-                        "usbc1_icusb_dp", "gpio_145", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC5_CMD, 146, "sdmmc5_cmd", "mcspi2_simo",
-                        "usbc1_icusb_dm", "gpio_146", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC5_DAT0, 147, "sdmmc5_dat0", "mcspi2_somi",
-                        "usbc1_icusb_rcv", "gpio_147", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC5_DAT1, 148, "sdmmc5_dat1", NULL,
-                        "usbc1_icusb_txen", "gpio_148", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC5_DAT2, 149, "sdmmc5_dat2", "mcspi2_cs1", NULL,
-                        "gpio_149", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC5_DAT3, 150, "sdmmc5_dat3", "mcspi2_cs0", NULL,
-                        "gpio_150", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(MCSPI4_CLK, 151, "mcspi4_clk", "sdmmc4_clk", NULL,
-                        "gpio_151", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(MCSPI4_SIMO, 152, "mcspi4_simo", "sdmmc4_cmd", NULL,
-                        "gpio_152", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(MCSPI4_SOMI, 153, "mcspi4_somi", "sdmmc4_dat0", NULL,
-                        "gpio_153", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(MCSPI4_CS0, 154, "mcspi4_cs0", "sdmmc4_dat3", NULL,
-                        "gpio_154", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UART4_RX, 155, "uart4_rx", "sdmmc4_dat2", NULL,
-                        "gpio_155", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UART4_TX, 156, "uart4_tx", "sdmmc4_dat1", NULL,
-                        "gpio_156", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_CLK, 157, "usbb2_ulpitll_clk",
-                        "usbb2_ulpiphy_clk", "sdmmc4_cmd", "gpio_157",
-                        "hsi2_cawake", NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_STP, 158, "usbb2_ulpitll_stp",
-                        "usbb2_ulpiphy_stp", "sdmmc4_clk", "gpio_158",
-                        "hsi2_cadata", "dispc2_data23", NULL, "reserved"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_DIR, 159, "usbb2_ulpitll_dir",
-                        "usbb2_ulpiphy_dir", "sdmmc4_dat0", "gpio_159",
-                        "hsi2_caflag", "dispc2_data22", NULL, "reserved"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_NXT, 160, "usbb2_ulpitll_nxt",
-                        "usbb2_ulpiphy_nxt", "sdmmc4_dat1", "gpio_160",
-                        "hsi2_acready", "dispc2_data21", NULL, "reserved"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT0, 161, "usbb2_ulpitll_dat0",
-                        "usbb2_ulpiphy_dat0", "sdmmc4_dat2", "gpio_161",
-                        "hsi2_acwake", "dispc2_data20", NULL, "reserved"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT1, 162, "usbb2_ulpitll_dat1",
-                        "usbb2_ulpiphy_dat1", "sdmmc4_dat3", "gpio_162",
-                        "hsi2_acdata", "dispc2_data19", NULL, "reserved"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT2, 163, "usbb2_ulpitll_dat2",
-                        "usbb2_ulpiphy_dat2", "sdmmc3_dat2", "gpio_163",
-                        "hsi2_acflag", "dispc2_data18", NULL, "reserved"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT3, 164, "usbb2_ulpitll_dat3",
-                        "usbb2_ulpiphy_dat3", "sdmmc3_dat1", "gpio_164",
-                        "hsi2_caready", "dispc2_data15", NULL, "reserved"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT4, 165, "usbb2_ulpitll_dat4",
-                        "usbb2_ulpiphy_dat4", "sdmmc3_dat0", "gpio_165",
-                        "mcspi3_somi", "dispc2_data14", NULL, "reserved"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT5, 166, "usbb2_ulpitll_dat5",
-                        "usbb2_ulpiphy_dat5", "sdmmc3_dat3", "gpio_166",
-                        "mcspi3_cs0", "dispc2_data13", NULL, "reserved"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT6, 167, "usbb2_ulpitll_dat6",
-                        "usbb2_ulpiphy_dat6", "sdmmc3_cmd", "gpio_167",
-                        "mcspi3_simo", "dispc2_data12", NULL, "reserved"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT7, 168, "usbb2_ulpitll_dat7",
-                        "usbb2_ulpiphy_dat7", "sdmmc3_clk", "gpio_168",
-                        "mcspi3_clk", "dispc2_data11", NULL, "reserved"),
-        _OMAP4_MUXENTRY(USBB2_HSIC_DATA, 169, "usbb2_hsic_data", NULL, NULL,
-                        "gpio_169", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(USBB2_HSIC_STROBE, 170, "usbb2_hsic_strobe", NULL,
-                        NULL, "gpio_170", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UNIPRO_TX0, 171, "unipro_tx0", "kpd_col0", NULL,
-                        "gpio_171", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UNIPRO_TY0, 172, "unipro_ty0", "kpd_col1", NULL,
-                        "gpio_172", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UNIPRO_TX1, 173, "unipro_tx1", "kpd_col2", NULL,
-                        "gpio_173", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UNIPRO_TY1, 174, "unipro_ty1", "kpd_col3", NULL,
-                        "gpio_174", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UNIPRO_TX2, 0, "unipro_tx2", "kpd_col4", NULL,
-                        "gpio_0", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UNIPRO_TY2, 1, "unipro_ty2", "kpd_col5", NULL,
-                        "gpio_1", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UNIPRO_RX0, 0, "unipro_rx0", "kpd_row0", NULL,
-                        "gpi_175", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UNIPRO_RY0, 0, "unipro_ry0", "kpd_row1", NULL,
-                        "gpi_176", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UNIPRO_RX1, 0, "unipro_rx1", "kpd_row2", NULL,
-                        "gpi_177", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UNIPRO_RY1, 0, "unipro_ry1", "kpd_row3", NULL,
-                        "gpi_178", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UNIPRO_RX2, 0, "unipro_rx2", "kpd_row4", NULL,
-                        "gpi_2", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UNIPRO_RY2, 0, "unipro_ry2", "kpd_row5", NULL,
-                        "gpi_3", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(USBA0_OTG_CE, 0, "usba0_otg_ce", NULL, NULL, NULL,
-                        NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(USBA0_OTG_DP, 179, "usba0_otg_dp", "uart3_rx_irrx",
-                        "uart2_rx", "gpio_179", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(USBA0_OTG_DM, 180, "usba0_otg_dm", "uart3_tx_irtx",
-                        "uart2_tx", "gpio_180", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(FREF_CLK1_OUT, 181, "fref_clk1_out", NULL, NULL,
-                        "gpio_181", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(FREF_CLK2_OUT, 182, "fref_clk2_out", NULL, NULL,
-                        "gpio_182", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SYS_NIRQ1, 0, "sys_nirq1", NULL, NULL, NULL, NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SYS_NIRQ2, 183, "sys_nirq2", NULL, NULL, "gpio_183",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SYS_BOOT0, 184, "sys_boot0", NULL, NULL, "gpio_184",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SYS_BOOT1, 185, "sys_boot1", NULL, NULL, "gpio_185",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SYS_BOOT2, 186, "sys_boot2", NULL, NULL, "gpio_186",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SYS_BOOT3, 187, "sys_boot3", NULL, NULL, "gpio_187",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SYS_BOOT4, 188, "sys_boot4", NULL, NULL, "gpio_188",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SYS_BOOT5, 189, "sys_boot5", NULL, NULL, "gpio_189",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU0, 11, "dpm_emu0", NULL, NULL, "gpio_11", NULL,
-                        NULL, "hw_dbg0", "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU1, 12, "dpm_emu1", NULL, NULL, "gpio_12", NULL,
-                        NULL, "hw_dbg1", "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU2, 13, "dpm_emu2", "usba0_ulpiphy_clk", NULL,
-                        "gpio_13", NULL, "dispc2_fid", "hw_dbg2", "reserved"),
-        _OMAP4_MUXENTRY(DPM_EMU3, 14, "dpm_emu3", "usba0_ulpiphy_stp", NULL,
-                        "gpio_14", NULL, "dispc2_data10", "hw_dbg3",
-                        "reserved"),
-        _OMAP4_MUXENTRY(DPM_EMU4, 15, "dpm_emu4", "usba0_ulpiphy_dir", NULL,
-                        "gpio_15", NULL, "dispc2_data9", "hw_dbg4",
-                        "reserved"),
-        _OMAP4_MUXENTRY(DPM_EMU5, 16, "dpm_emu5", "usba0_ulpiphy_nxt", NULL,
-                        "gpio_16", "rfbi_te_vsync0", "dispc2_data16",
-                        "hw_dbg5", "reserved"),
-        _OMAP4_MUXENTRY(DPM_EMU6, 17, "dpm_emu6", "usba0_ulpiphy_dat0",
-                        "uart3_tx_irtx", "gpio_17", "rfbi_hsync0",
-                        "dispc2_data17", "hw_dbg6", "reserved"),
-        _OMAP4_MUXENTRY(DPM_EMU7, 18, "dpm_emu7", "usba0_ulpiphy_dat1",
-                        "uart3_rx_irrx", "gpio_18", "rfbi_cs0",
-                        "dispc2_hsync", "hw_dbg7", "reserved"),
-        _OMAP4_MUXENTRY(DPM_EMU8, 19, "dpm_emu8", "usba0_ulpiphy_dat2",
-                        "uart3_rts_sd", "gpio_19", "rfbi_re", "dispc2_pclk",
-                        "hw_dbg8", "reserved"),
-        _OMAP4_MUXENTRY(DPM_EMU9, 20, "dpm_emu9", "usba0_ulpiphy_dat3",
-                        "uart3_cts_rctx", "gpio_20", "rfbi_we",
-                        "dispc2_vsync", "hw_dbg9", "reserved"),
-        _OMAP4_MUXENTRY(DPM_EMU10, 21, "dpm_emu10", "usba0_ulpiphy_dat4",
-                        NULL, "gpio_21", "rfbi_a0", "dispc2_de", "hw_dbg10",
-                        "reserved"),
-        _OMAP4_MUXENTRY(DPM_EMU11, 22, "dpm_emu11", "usba0_ulpiphy_dat5",
-                        NULL, "gpio_22", "rfbi_data8", "dispc2_data8",
-                        "hw_dbg11", "reserved"),
-        _OMAP4_MUXENTRY(DPM_EMU12, 23, "dpm_emu12", "usba0_ulpiphy_dat6",
-                        NULL, "gpio_23", "rfbi_data7", "dispc2_data7",
-                        "hw_dbg12", "reserved"),
-        _OMAP4_MUXENTRY(DPM_EMU13, 24, "dpm_emu13", "usba0_ulpiphy_dat7",
-                        NULL, "gpio_24", "rfbi_data6", "dispc2_data6",
-                        "hw_dbg13", "reserved"),
-        _OMAP4_MUXENTRY(DPM_EMU14, 25, "dpm_emu14", "sys_drm_msecure",
-                        "uart1_rx", "gpio_25", "rfbi_data5", "dispc2_data5",
-                        "hw_dbg14", "reserved"),
-        _OMAP4_MUXENTRY(DPM_EMU15, 26, "dpm_emu15", "sys_secure_indicator",
-                        NULL, "gpio_26", "rfbi_data4", "dispc2_data4",
-                        "hw_dbg15", "reserved"),
-        _OMAP4_MUXENTRY(DPM_EMU16, 27, "dpm_emu16", "dmtimer8_pwm_evt",
-                        "dsi1_te0", "gpio_27", "rfbi_data3", "dispc2_data3",
-                        "hw_dbg16", "reserved"),
-        _OMAP4_MUXENTRY(DPM_EMU17, 28, "dpm_emu17", "dmtimer9_pwm_evt",
-                        "dsi1_te1", "gpio_28", "rfbi_data2", "dispc2_data2",
-                        "hw_dbg17", "reserved"),
-        _OMAP4_MUXENTRY(DPM_EMU18, 190, "dpm_emu18", "dmtimer10_pwm_evt",
-                        "dsi2_te0", "gpio_190", "rfbi_data1", "dispc2_data1",
-                        "hw_dbg18", "reserved"),
-        _OMAP4_MUXENTRY(DPM_EMU19, 191, "dpm_emu19", "dmtimer11_pwm_evt",
-                        "dsi2_te1", "gpio_191", "rfbi_data0", "dispc2_data0",
-                        "hw_dbg19", "reserved"),
-        { .reg_offset = OMAP_MUX_TERMINATOR },
-};
-/*
- * Balls for 44XX CBL package
- * 547-pin CBL ES1.0 S-FPGA-N547, 0.40mm Ball Pitch (Top),
- *                                0.40mm Ball Pitch (Bottom)
- */
-#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS)                \
-                && defined(CONFIG_OMAP_PACKAGE_CBL)
-static struct omap_ball __initdata omap4_core_cbl_ball[] = {
-        _OMAP4_BALLENTRY(GPMC_AD0, "c12", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD1, "d12", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD2, "c13", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD3, "d13", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD4, "c15", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD5, "d15", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD6, "a16", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD7, "b16", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD8, "c16", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD9, "d16", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD10, "c17", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD11, "d17", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD12, "c18", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD13, "d18", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD14, "c19", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD15, "d19", NULL),
-        _OMAP4_BALLENTRY(GPMC_A16, "b17", NULL),
-        _OMAP4_BALLENTRY(GPMC_A17, "a18", NULL),
-        _OMAP4_BALLENTRY(GPMC_A18, "b18", NULL),
-        _OMAP4_BALLENTRY(GPMC_A19, "a19", NULL),
-        _OMAP4_BALLENTRY(GPMC_A20, "b19", NULL),
-        _OMAP4_BALLENTRY(GPMC_A21, "b20", NULL),
-        _OMAP4_BALLENTRY(GPMC_A22, "a21", NULL),
-        _OMAP4_BALLENTRY(GPMC_A23, "b21", NULL),
-        _OMAP4_BALLENTRY(GPMC_A24, "c20", NULL),
-        _OMAP4_BALLENTRY(GPMC_A25, "d20", NULL),
-        _OMAP4_BALLENTRY(GPMC_NCS0, "b25", NULL),
-        _OMAP4_BALLENTRY(GPMC_NCS1, "c21", NULL),
-        _OMAP4_BALLENTRY(GPMC_NCS2, "d21", NULL),
-        _OMAP4_BALLENTRY(GPMC_NCS3, "c22", NULL),
-        _OMAP4_BALLENTRY(GPMC_NWP, "c25", NULL),
-        _OMAP4_BALLENTRY(GPMC_CLK, "b22", NULL),
-        _OMAP4_BALLENTRY(GPMC_NADV_ALE, "d25", NULL),
-        _OMAP4_BALLENTRY(GPMC_NOE, "b11", NULL),
-        _OMAP4_BALLENTRY(GPMC_NWE, "b12", NULL),
-        _OMAP4_BALLENTRY(GPMC_NBE0_CLE, "c23", NULL),
-        _OMAP4_BALLENTRY(GPMC_NBE1, "d22", NULL),
-        _OMAP4_BALLENTRY(GPMC_WAIT0, "b26", NULL),
-        _OMAP4_BALLENTRY(GPMC_WAIT1, "b23", NULL),
-        _OMAP4_BALLENTRY(C2C_DATA11, "d23", NULL),
-        _OMAP4_BALLENTRY(C2C_DATA12, "a24", NULL),
-        _OMAP4_BALLENTRY(C2C_DATA13, "b24", NULL),
-        _OMAP4_BALLENTRY(C2C_DATA14, "c24", NULL),
-        _OMAP4_BALLENTRY(C2C_DATA15, "d24", NULL),
-        _OMAP4_BALLENTRY(HDMI_HPD, "b9", NULL),
-        _OMAP4_BALLENTRY(HDMI_CEC, "b10", NULL),
-        _OMAP4_BALLENTRY(HDMI_DDC_SCL, "a8", NULL),
-        _OMAP4_BALLENTRY(HDMI_DDC_SDA, "b8", NULL),
-        _OMAP4_BALLENTRY(CSI21_DX0, "r26", NULL),
-        _OMAP4_BALLENTRY(CSI21_DY0, "r25", NULL),
-        _OMAP4_BALLENTRY(CSI21_DX1, "t26", NULL),
-        _OMAP4_BALLENTRY(CSI21_DY1, "t25", NULL),
-        _OMAP4_BALLENTRY(CSI21_DX2, "u26", NULL),
-        _OMAP4_BALLENTRY(CSI21_DY2, "u25", NULL),
-        _OMAP4_BALLENTRY(CSI21_DX3, "v26", NULL),
-        _OMAP4_BALLENTRY(CSI21_DY3, "v25", NULL),
-        _OMAP4_BALLENTRY(CSI21_DX4, "w26", NULL),
-        _OMAP4_BALLENTRY(CSI21_DY4, "w25", NULL),
-        _OMAP4_BALLENTRY(CSI22_DX0, "m26", NULL),
-        _OMAP4_BALLENTRY(CSI22_DY0, "m25", NULL),
-        _OMAP4_BALLENTRY(CSI22_DX1, "n26", NULL),
-        _OMAP4_BALLENTRY(CSI22_DY1, "n25", NULL),
-        _OMAP4_BALLENTRY(CAM_SHUTTER, "t27", NULL),
-        _OMAP4_BALLENTRY(CAM_STROBE, "u27", NULL),
-        _OMAP4_BALLENTRY(CAM_GLOBALRESET, "v27", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_CLK, "ae18", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_STP, "ag19", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_DIR, "af19", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_NXT, "ae19", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT0, "af18", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT1, "ag18", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT2, "ae17", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT3, "af17", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT4, "ah17", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT5, "ae16", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT6, "af16", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT7, "ag16", NULL),
-        _OMAP4_BALLENTRY(USBB1_HSIC_DATA, "af14", NULL),
-        _OMAP4_BALLENTRY(USBB1_HSIC_STROBE, "ae14", NULL),
-        _OMAP4_BALLENTRY(USBC1_ICUSB_DP, "h2", NULL),
-        _OMAP4_BALLENTRY(USBC1_ICUSB_DM, "h3", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_CLK, "d2", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_CMD, "e3", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_DAT0, "e4", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_DAT1, "e2", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_DAT2, "e1", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_DAT3, "f4", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_DAT4, "f3", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_DAT5, "f1", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_DAT6, "g4", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_DAT7, "g3", NULL),
-        _OMAP4_BALLENTRY(ABE_MCBSP2_CLKX, "ad27", NULL),
-        _OMAP4_BALLENTRY(ABE_MCBSP2_DR, "ad26", NULL),
-        _OMAP4_BALLENTRY(ABE_MCBSP2_DX, "ad25", NULL),
-        _OMAP4_BALLENTRY(ABE_MCBSP2_FSX, "ac28", NULL),
-        _OMAP4_BALLENTRY(ABE_MCBSP1_CLKX, "ac26", NULL),
-        _OMAP4_BALLENTRY(ABE_MCBSP1_DR, "ac25", NULL),
-        _OMAP4_BALLENTRY(ABE_MCBSP1_DX, "ab25", NULL),
-        _OMAP4_BALLENTRY(ABE_MCBSP1_FSX, "ac27", NULL),
-        _OMAP4_BALLENTRY(ABE_PDM_UL_DATA, "ag25", NULL),
-        _OMAP4_BALLENTRY(ABE_PDM_DL_DATA, "af25", NULL),
-        _OMAP4_BALLENTRY(ABE_PDM_FRAME, "ae25", NULL),
-        _OMAP4_BALLENTRY(ABE_PDM_LB_CLK, "af26", NULL),
-        _OMAP4_BALLENTRY(ABE_CLKS, "ah26", NULL),
-        _OMAP4_BALLENTRY(ABE_DMIC_CLK1, "ae24", NULL),
-        _OMAP4_BALLENTRY(ABE_DMIC_DIN1, "af24", NULL),
-        _OMAP4_BALLENTRY(ABE_DMIC_DIN2, "ag24", NULL),
-        _OMAP4_BALLENTRY(ABE_DMIC_DIN3, "ah24", NULL),
-        _OMAP4_BALLENTRY(UART2_CTS, "ab26", NULL),
-        _OMAP4_BALLENTRY(UART2_RTS, "ab27", NULL),
-        _OMAP4_BALLENTRY(UART2_RX, "aa25", NULL),
-        _OMAP4_BALLENTRY(UART2_TX, "aa26", NULL),
-        _OMAP4_BALLENTRY(HDQ_SIO, "aa27", NULL),
-        _OMAP4_BALLENTRY(I2C1_SCL, "ae28", NULL),
-        _OMAP4_BALLENTRY(I2C1_SDA, "ae26", NULL),
-        _OMAP4_BALLENTRY(I2C2_SCL, "c26", NULL),
-        _OMAP4_BALLENTRY(I2C2_SDA, "d26", NULL),
-        _OMAP4_BALLENTRY(I2C3_SCL, "w27", NULL),
-        _OMAP4_BALLENTRY(I2C3_SDA, "y27", NULL),
-        _OMAP4_BALLENTRY(I2C4_SCL, "ag21", NULL),
-        _OMAP4_BALLENTRY(I2C4_SDA, "ah22", NULL),
-        _OMAP4_BALLENTRY(MCSPI1_CLK, "af22", NULL),
-        _OMAP4_BALLENTRY(MCSPI1_SOMI, "ae22", NULL),
-        _OMAP4_BALLENTRY(MCSPI1_SIMO, "ag22", NULL),
-        _OMAP4_BALLENTRY(MCSPI1_CS0, "ae23", NULL),
-        _OMAP4_BALLENTRY(MCSPI1_CS1, "af23", NULL),
-        _OMAP4_BALLENTRY(MCSPI1_CS2, "ag23", NULL),
-        _OMAP4_BALLENTRY(MCSPI1_CS3, "ah23", NULL),
-        _OMAP4_BALLENTRY(UART3_CTS_RCTX, "f27", NULL),
-        _OMAP4_BALLENTRY(UART3_RTS_SD, "f28", NULL),
-        _OMAP4_BALLENTRY(UART3_RX_IRRX, "g27", NULL),
-        _OMAP4_BALLENTRY(UART3_TX_IRTX, "g28", NULL),
-        _OMAP4_BALLENTRY(SDMMC5_CLK, "ae5", NULL),
-        _OMAP4_BALLENTRY(SDMMC5_CMD, "af5", NULL),
-        _OMAP4_BALLENTRY(SDMMC5_DAT0, "ae4", NULL),
-        _OMAP4_BALLENTRY(SDMMC5_DAT1, "af4", NULL),
-        _OMAP4_BALLENTRY(SDMMC5_DAT2, "ag3", NULL),
-        _OMAP4_BALLENTRY(SDMMC5_DAT3, "af3", NULL),
-        _OMAP4_BALLENTRY(MCSPI4_CLK, "ae21", NULL),
-        _OMAP4_BALLENTRY(MCSPI4_SIMO, "af20", NULL),
-        _OMAP4_BALLENTRY(MCSPI4_SOMI, "af21", NULL),
-        _OMAP4_BALLENTRY(MCSPI4_CS0, "ae20", NULL),
-        _OMAP4_BALLENTRY(UART4_RX, "ag20", NULL),
-        _OMAP4_BALLENTRY(UART4_TX, "ah19", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_CLK, "ag12", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_STP, "af12", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_DIR, "ae12", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_NXT, "ag13", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT0, "ae11", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT1, "af11", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT2, "ag11", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT3, "ah11", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT4, "ae10", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT5, "af10", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT6, "ag10", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT7, "ae9", NULL),
-        _OMAP4_BALLENTRY(USBB2_HSIC_DATA, "af13", NULL),
-        _OMAP4_BALLENTRY(USBB2_HSIC_STROBE, "ae13", NULL),
-        _OMAP4_BALLENTRY(UNIPRO_TX0, "g26", NULL),
-        _OMAP4_BALLENTRY(UNIPRO_TY0, "g25", NULL),
-        _OMAP4_BALLENTRY(UNIPRO_TX1, "h26", NULL),
-        _OMAP4_BALLENTRY(UNIPRO_TY1, "h25", NULL),
-        _OMAP4_BALLENTRY(UNIPRO_TX2, "j27", NULL),
-        _OMAP4_BALLENTRY(UNIPRO_TY2, "h27", NULL),
-        _OMAP4_BALLENTRY(UNIPRO_RX0, "j26", NULL),
-        _OMAP4_BALLENTRY(UNIPRO_RY0, "j25", NULL),
-        _OMAP4_BALLENTRY(UNIPRO_RX1, "k26", NULL),
-        _OMAP4_BALLENTRY(UNIPRO_RY1, "k25", NULL),
-        _OMAP4_BALLENTRY(UNIPRO_RX2, "l27", NULL),
-        _OMAP4_BALLENTRY(UNIPRO_RY2, "k27", NULL),
-        _OMAP4_BALLENTRY(USBA0_OTG_CE, "c3", NULL),
-        _OMAP4_BALLENTRY(USBA0_OTG_DP, "b5", NULL),
-        _OMAP4_BALLENTRY(USBA0_OTG_DM, "b4", NULL),
-        _OMAP4_BALLENTRY(FREF_CLK1_OUT, "aa28", NULL),
-        _OMAP4_BALLENTRY(FREF_CLK2_OUT, "y28", NULL),
-        _OMAP4_BALLENTRY(SYS_NIRQ1, "ae6", NULL),
-        _OMAP4_BALLENTRY(SYS_NIRQ2, "af6", NULL),
-        _OMAP4_BALLENTRY(SYS_BOOT0, "f26", NULL),
-        _OMAP4_BALLENTRY(SYS_BOOT1, "e27", NULL),
-        _OMAP4_BALLENTRY(SYS_BOOT2, "e26", NULL),
-        _OMAP4_BALLENTRY(SYS_BOOT3, "e25", NULL),
-        _OMAP4_BALLENTRY(SYS_BOOT4, "d28", NULL),
-        _OMAP4_BALLENTRY(SYS_BOOT5, "d27", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU0, "m2", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU1, "n2", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU2, "p2", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU3, "v1", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU4, "v2", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU5, "w1", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU6, "w2", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU7, "w3", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU8, "w4", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU9, "y2", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU10, "y3", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU11, "y4", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU12, "aa1", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU13, "aa2", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU14, "aa3", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU15, "aa4", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU16, "ab2", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU17, "ab3", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU18, "ab4", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU19, "ac4", NULL),
-        { .reg_offset = OMAP_MUX_TERMINATOR },
-};
-#else
-#define omap4_core_cbl_ball  NULL
-#endif
-/*
- * Signals different on ES2.0 compared to superset
- */
-static struct omap_mux __initdata omap4_es2_core_subset[] = {
-        _OMAP4_MUXENTRY(GPMC_AD8, 32, "gpmc_ad8", "kpd_row0", "c2c_data15",
-                        "gpio_32", NULL, "sdmmc1_dat0", NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD9, 33, "gpmc_ad9", "kpd_row1", "c2c_data14",
-                        "gpio_33", NULL, "sdmmc1_dat1", NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD10, 34, "gpmc_ad10", "kpd_row2", "c2c_data13",
-                        "gpio_34", NULL, "sdmmc1_dat2", NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD11, 35, "gpmc_ad11", "kpd_row3", "c2c_data12",
-                        "gpio_35", NULL, "sdmmc1_dat3", NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD12, 36, "gpmc_ad12", "kpd_col0", "c2c_data11",
-                        "gpio_36", NULL, "sdmmc1_dat4", NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD13, 37, "gpmc_ad13", "kpd_col1", "c2c_data10",
-                        "gpio_37", NULL, "sdmmc1_dat5", NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD14, 38, "gpmc_ad14", "kpd_col2", "c2c_data9",
-                        "gpio_38", NULL, "sdmmc1_dat6", NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD15, 39, "gpmc_ad15", "kpd_col3", "c2c_data8",
-                        "gpio_39", NULL, "sdmmc1_dat7", NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_A16, 40, "gpmc_a16", "kpd_row4", "c2c_datain0",
-                        "gpio_40", "venc_656_data0", NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_A24, 48, "gpmc_a24", "kpd_col8", "c2c_clkout0",
-                        "gpio_48", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_NCS2, 52, "gpmc_ncs2", "kpd_row8",
-                        "c2c_dataout7", "gpio_52", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_CLK, 55, "gpmc_clk", NULL, NULL, "gpio_55",
-                        "sys_ndmareq2", "sdmmc1_cmd", NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_NADV_ALE, 56, "gpmc_nadv_ale", "dsi1_te1", NULL,
-                        "gpio_56", "sys_ndmareq3", "sdmmc1_clk", NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_WAIT2, 100, "gpmc_wait2", "usbc1_icusb_txen",
-                        "c2c_dataout3", "gpio_100", "sys_ndmareq0", NULL,
-                        NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_NCS4, 101, "gpmc_ncs4", "dsi1_te0", "c2c_clkin0",
-                        "gpio_101", "sys_ndmareq1", NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_NCS5, 102, "gpmc_ncs5", "dsi1_te1", "c2c_clkin1",
-                        "gpio_102", "sys_ndmareq2", NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_NCS6, 103, "gpmc_ncs6", "dsi2_te0",
-                        "c2c_dataout0", "gpio_103", "sys_ndmareq3", NULL,
-                        NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_NCS7, 104, "gpmc_ncs7", "dsi2_te1",
-                        "c2c_dataout1", "gpio_104", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT0, 88, "usbb1_ulpitll_dat0",
-                        "hsi1_acwake", "mcbsp4_clkx", "gpio_88",
-                        "usbb1_ulpiphy_dat0", "usbb1_mm_txen", "hw_dbg24",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT1, 89, "usbb1_ulpitll_dat1",
-                        "hsi1_acdata", "mcbsp4_dx", "gpio_89",
-                        "usbb1_ulpiphy_dat1", "usbb1_mm_txdat", "hw_dbg25",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT2, 90, "usbb1_ulpitll_dat2",
-                        "hsi1_acflag", "mcbsp4_dr", "gpio_90",
-                        "usbb1_ulpiphy_dat2", "usbb1_mm_txse0", "hw_dbg26",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT3, 91, "usbb1_ulpitll_dat3",
-                        "hsi1_caready", NULL, "gpio_91", "usbb1_ulpiphy_dat3",
-                        "usbb1_mm_rxrcv", "hw_dbg27", "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_DMIC_CLK1, 119, "abe_dmic_clk1", NULL, NULL,
-                        "gpio_119", "usbb2_mm_txse0", "uart4_cts", NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_DMIC_DIN1, 120, "abe_dmic_din1", NULL, NULL,
-                        "gpio_120", "usbb2_mm_txdat", "uart4_rts", NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_DMIC_DIN2, 121, "abe_dmic_din2", "slimbus2_clock",
-                        "abe_mcasp_axr", "gpio_121", NULL,
-                        "dmtimer11_pwm_evt", NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_DMIC_DIN3, 122, "abe_dmic_din3", "slimbus2_data",
-                        "abe_dmic_clk2", "gpio_122", NULL, "dmtimer9_pwm_evt",
-                        NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC5_CLK, 145, "sdmmc5_clk", "mcspi2_clk",
-                        "usbc1_icusb_dp", "gpio_145", NULL, "sdmmc2_clk",
-                        NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC5_CMD, 146, "sdmmc5_cmd", "mcspi2_simo",
-                        "usbc1_icusb_dm", "gpio_146", NULL, "sdmmc2_cmd",
-                        NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC5_DAT0, 147, "sdmmc5_dat0", "mcspi2_somi",
-                        "usbc1_icusb_rcv", "gpio_147", NULL, "sdmmc2_dat0",
-                        NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC5_DAT1, 148, "sdmmc5_dat1", NULL,
-                        "usbc1_icusb_txen", "gpio_148", NULL, "sdmmc2_dat1",
-                        NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC5_DAT2, 149, "sdmmc5_dat2", "mcspi2_cs1", NULL,
-                        "gpio_149", NULL, "sdmmc2_dat2", NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC5_DAT3, 150, "sdmmc5_dat3", "mcspi2_cs0", NULL,
-                        "gpio_150", NULL, "sdmmc2_dat3", NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(MCSPI4_CLK, 151, "mcspi4_clk", "sdmmc4_clk",
-                        "kpd_col6", "gpio_151", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(MCSPI4_SIMO, 152, "mcspi4_simo", "sdmmc4_cmd",
-                        "kpd_col7", "gpio_152", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(MCSPI4_SOMI, 153, "mcspi4_somi", "sdmmc4_dat0",
-                        "kpd_row6", "gpio_153", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(MCSPI4_CS0, 154, "mcspi4_cs0", "sdmmc4_dat3",
-                        "kpd_row7", "gpio_154", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(UART4_RX, 155, "uart4_rx", "sdmmc4_dat2", "kpd_row8",
-                        "gpio_155", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UART4_TX, 156, "uart4_tx", "sdmmc4_dat1", "kpd_col8",
-                        "gpio_156", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_STP, 158, "usbb2_ulpitll_stp",
-                        "usbb2_ulpiphy_stp", "sdmmc4_clk", "gpio_158",
-                        "hsi2_cadata", "dispc2_data23", NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_DIR, 159, "usbb2_ulpitll_dir",
-                        "usbb2_ulpiphy_dir", "sdmmc4_dat0", "gpio_159",
-                        "hsi2_caflag", "dispc2_data22", NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_NXT, 160, "usbb2_ulpitll_nxt",
-                        "usbb2_ulpiphy_nxt", "sdmmc4_dat1", "gpio_160",
-                        "hsi2_acready", "dispc2_data21", NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT0, 161, "usbb2_ulpitll_dat0",
-                        "usbb2_ulpiphy_dat0", "sdmmc4_dat2", "gpio_161",
-                        "hsi2_acwake", "dispc2_data20", "usbb2_mm_txen",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT1, 162, "usbb2_ulpitll_dat1",
-                        "usbb2_ulpiphy_dat1", "sdmmc4_dat3", "gpio_162",
-                        "hsi2_acdata", "dispc2_data19", "usbb2_mm_txdat",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT2, 163, "usbb2_ulpitll_dat2",
-                        "usbb2_ulpiphy_dat2", "sdmmc3_dat2", "gpio_163",
-                        "hsi2_acflag", "dispc2_data18", "usbb2_mm_txse0",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT3, 164, "usbb2_ulpitll_dat3",
-                        "usbb2_ulpiphy_dat3", "sdmmc3_dat1", "gpio_164",
-                        "hsi2_caready", "dispc2_data15", "rfbi_data15",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT4, 165, "usbb2_ulpitll_dat4",
-                        "usbb2_ulpiphy_dat4", "sdmmc3_dat0", "gpio_165",
-                        "mcspi3_somi", "dispc2_data14", "rfbi_data14",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT5, 166, "usbb2_ulpitll_dat5",
-                        "usbb2_ulpiphy_dat5", "sdmmc3_dat3", "gpio_166",
-                        "mcspi3_cs0", "dispc2_data13", "rfbi_data13",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT6, 167, "usbb2_ulpitll_dat6",
-                        "usbb2_ulpiphy_dat6", "sdmmc3_cmd", "gpio_167",
-                        "mcspi3_simo", "dispc2_data12", "rfbi_data12",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT7, 168, "usbb2_ulpitll_dat7",
-                        "usbb2_ulpiphy_dat7", "sdmmc3_clk", "gpio_168",
-                        "mcspi3_clk", "dispc2_data11", "rfbi_data11",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(KPD_COL3, 171, "kpd_col3", "kpd_col0", NULL,
-                        "gpio_171", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(KPD_COL4, 172, "kpd_col4", "kpd_col1", NULL,
-                        "gpio_172", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(KPD_COL5, 173, "kpd_col5", "kpd_col2", NULL,
-                        "gpio_173", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(KPD_COL0, 174, "kpd_col0", "kpd_col3", NULL,
-                        "gpio_174", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(KPD_COL1, 0, "kpd_col1", "kpd_col4", NULL, "gpio_0",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(KPD_COL2, 1, "kpd_col2", "kpd_col5", NULL, "gpio_1",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(KPD_ROW3, 175, "kpd_row3", "kpd_row0", NULL,
-                        "gpio_175", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(KPD_ROW4, 176, "kpd_row4", "kpd_row1", NULL,
-                        "gpio_176", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(KPD_ROW5, 177, "kpd_row5", "kpd_row2", NULL,
-                        "gpio_177", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(KPD_ROW0, 178, "kpd_row0", "kpd_row3", NULL,
-                        "gpio_178", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(KPD_ROW1, 2, "kpd_row1", "kpd_row4", NULL, "gpio_2",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(KPD_ROW2, 3, "kpd_row2", "kpd_row5", NULL, "gpio_3",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(USBA0_OTG_DP, 0, "usba0_otg_dp", "uart3_rx_irrx",
-                        "uart2_rx", NULL, NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(USBA0_OTG_DM, 0, "usba0_otg_dm", "uart3_tx_irtx",
-                        "uart2_tx", NULL, NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU2, 13, "dpm_emu2", "usba0_ulpiphy_clk", NULL,
-                        "gpio_13", NULL, "dispc2_fid", "hw_dbg2",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU3, 14, "dpm_emu3", "usba0_ulpiphy_stp", NULL,
-                        "gpio_14", "rfbi_data10", "dispc2_data10", "hw_dbg3",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU4, 15, "dpm_emu4", "usba0_ulpiphy_dir", NULL,
-                        "gpio_15", "rfbi_data9", "dispc2_data9", "hw_dbg4",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU5, 16, "dpm_emu5", "usba0_ulpiphy_nxt", NULL,
-                        "gpio_16", "rfbi_te_vsync0", "dispc2_data16",
-                        "hw_dbg5", "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU6, 17, "dpm_emu6", "usba0_ulpiphy_dat0",
-                        "uart3_tx_irtx", "gpio_17", "rfbi_hsync0",
-                        "dispc2_data17", "hw_dbg6", "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU7, 18, "dpm_emu7", "usba0_ulpiphy_dat1",
-                        "uart3_rx_irrx", "gpio_18", "rfbi_cs0",
-                        "dispc2_hsync", "hw_dbg7", "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU8, 19, "dpm_emu8", "usba0_ulpiphy_dat2",
-                        "uart3_rts_sd", "gpio_19", "rfbi_re", "dispc2_pclk",
-                        "hw_dbg8", "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU9, 20, "dpm_emu9", "usba0_ulpiphy_dat3",
-                        "uart3_cts_rctx", "gpio_20", "rfbi_we",
-                        "dispc2_vsync", "hw_dbg9", "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU10, 21, "dpm_emu10", "usba0_ulpiphy_dat4",
-                        NULL, "gpio_21", "rfbi_a0", "dispc2_de", "hw_dbg10",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU11, 22, "dpm_emu11", "usba0_ulpiphy_dat5",
-                        NULL, "gpio_22", "rfbi_data8", "dispc2_data8",
-                        "hw_dbg11", "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU12, 23, "dpm_emu12", "usba0_ulpiphy_dat6",
-                        NULL, "gpio_23", "rfbi_data7", "dispc2_data7",
-                        "hw_dbg12", "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU13, 24, "dpm_emu13", "usba0_ulpiphy_dat7",
-                        NULL, "gpio_24", "rfbi_data6", "dispc2_data6",
-                        "hw_dbg13", "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU14, 25, "dpm_emu14", "sys_drm_msecure",
-                        "uart1_rx", "gpio_25", "rfbi_data5", "dispc2_data5",
-                        "hw_dbg14", "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU15, 26, "dpm_emu15", "sys_secure_indicator",
-                        NULL, "gpio_26", "rfbi_data4", "dispc2_data4",
-                        "hw_dbg15", "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU16, 27, "dpm_emu16", "dmtimer8_pwm_evt",
-                        "dsi1_te0", "gpio_27", "rfbi_data3", "dispc2_data3",
-                        "hw_dbg16", "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU17, 28, "dpm_emu17", "dmtimer9_pwm_evt",
-                        "dsi1_te1", "gpio_28", "rfbi_data2", "dispc2_data2",
-                        "hw_dbg17", "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU18, 190, "dpm_emu18", "dmtimer10_pwm_evt",
-                        "dsi2_te0", "gpio_190", "rfbi_data1", "dispc2_data1",
-                        "hw_dbg18", "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU19, 191, "dpm_emu19", "dmtimer11_pwm_evt",
-                        "dsi2_te1", "gpio_191", "rfbi_data0", "dispc2_data0",
-                        "hw_dbg19", "safe_mode"),
-        { .reg_offset = OMAP_MUX_TERMINATOR },
-};
-/*
- * Balls for 44XX CBS package
- * 547-pin CBL ES2.0 S-FPGA-N547, 0.40mm Ball Pitch (Top),
- *                                0.40mm Ball Pitch (Bottom)
- */
-#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS)                \
-                && defined(CONFIG_OMAP_PACKAGE_CBS)
-static struct omap_ball __initdata omap4_core_cbs_ball[] = {
-        _OMAP4_BALLENTRY(GPMC_AD0, "c12", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD1, "d12", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD2, "c13", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD3, "d13", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD4, "c15", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD5, "d15", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD6, "a16", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD7, "b16", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD8, "c16", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD9, "d16", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD10, "c17", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD11, "d17", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD12, "c18", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD13, "d18", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD14, "c19", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD15, "d19", NULL),
-        _OMAP4_BALLENTRY(GPMC_A16, "b17", NULL),
-        _OMAP4_BALLENTRY(GPMC_A17, "a18", NULL),
-        _OMAP4_BALLENTRY(GPMC_A18, "b18", NULL),
-        _OMAP4_BALLENTRY(GPMC_A19, "a19", NULL),
-        _OMAP4_BALLENTRY(GPMC_A20, "b19", NULL),
-        _OMAP4_BALLENTRY(GPMC_A21, "b20", NULL),
-        _OMAP4_BALLENTRY(GPMC_A22, "a21", NULL),
-        _OMAP4_BALLENTRY(GPMC_A23, "b21", NULL),
-        _OMAP4_BALLENTRY(GPMC_A24, "c20", NULL),
-        _OMAP4_BALLENTRY(GPMC_A25, "d20", NULL),
-        _OMAP4_BALLENTRY(GPMC_NCS0, "b25", NULL),
-        _OMAP4_BALLENTRY(GPMC_NCS1, "c21", NULL),
-        _OMAP4_BALLENTRY(GPMC_NCS2, "d21", NULL),
-        _OMAP4_BALLENTRY(GPMC_NCS3, "c22", NULL),
-        _OMAP4_BALLENTRY(GPMC_NWP, "c25", NULL),
-        _OMAP4_BALLENTRY(GPMC_CLK, "b22", NULL),
-        _OMAP4_BALLENTRY(GPMC_NADV_ALE, "d25", NULL),
-        _OMAP4_BALLENTRY(GPMC_NOE, "b11", NULL),
-        _OMAP4_BALLENTRY(GPMC_NWE, "b12", NULL),
-        _OMAP4_BALLENTRY(GPMC_NBE0_CLE, "c23", NULL),
-        _OMAP4_BALLENTRY(GPMC_NBE1, "d22", NULL),
-        _OMAP4_BALLENTRY(GPMC_WAIT0, "b26", NULL),
-        _OMAP4_BALLENTRY(GPMC_WAIT1, "b23", NULL),
-        _OMAP4_BALLENTRY(GPMC_WAIT2, "d23", NULL),
-        _OMAP4_BALLENTRY(GPMC_NCS4, "a24", NULL),
-        _OMAP4_BALLENTRY(GPMC_NCS5, "b24", NULL),
-        _OMAP4_BALLENTRY(GPMC_NCS6, "c24", NULL),
-        _OMAP4_BALLENTRY(GPMC_NCS7, "d24", NULL),
-        _OMAP4_BALLENTRY(HDMI_HPD, "b9", NULL),
-        _OMAP4_BALLENTRY(HDMI_CEC, "b10", NULL),
-        _OMAP4_BALLENTRY(HDMI_DDC_SCL, "a8", NULL),
-        _OMAP4_BALLENTRY(HDMI_DDC_SDA, "b8", NULL),
-        _OMAP4_BALLENTRY(CSI21_DX0, "r26", NULL),
-        _OMAP4_BALLENTRY(CSI21_DY0, "r25", NULL),
-        _OMAP4_BALLENTRY(CSI21_DX1, "t26", NULL),
-        _OMAP4_BALLENTRY(CSI21_DY1, "t25", NULL),
-        _OMAP4_BALLENTRY(CSI21_DX2, "u26", NULL),
-        _OMAP4_BALLENTRY(CSI21_DY2, "u25", NULL),
-        _OMAP4_BALLENTRY(CSI21_DX3, "v26", NULL),
-        _OMAP4_BALLENTRY(CSI21_DY3, "v25", NULL),
-        _OMAP4_BALLENTRY(CSI21_DX4, "w26", NULL),
-        _OMAP4_BALLENTRY(CSI21_DY4, "w25", NULL),
-        _OMAP4_BALLENTRY(CSI22_DX0, "m26", NULL),
-        _OMAP4_BALLENTRY(CSI22_DY0, "m25", NULL),
-        _OMAP4_BALLENTRY(CSI22_DX1, "n26", NULL),
-        _OMAP4_BALLENTRY(CSI22_DY1, "n25", NULL),
-        _OMAP4_BALLENTRY(CAM_SHUTTER, "t27", NULL),
-        _OMAP4_BALLENTRY(CAM_STROBE, "u27", NULL),
-        _OMAP4_BALLENTRY(CAM_GLOBALRESET, "v27", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_CLK, "ae18", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_STP, "ag19", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_DIR, "af19", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_NXT, "ae19", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT0, "af18", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT1, "ag18", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT2, "ae17", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT3, "af17", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT4, "ah17", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT5, "ae16", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT6, "af16", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT7, "ag16", NULL),
-        _OMAP4_BALLENTRY(USBB1_HSIC_DATA, "af14", NULL),
-        _OMAP4_BALLENTRY(USBB1_HSIC_STROBE, "ae14", NULL),
-        _OMAP4_BALLENTRY(USBC1_ICUSB_DP, "h2", NULL),
-        _OMAP4_BALLENTRY(USBC1_ICUSB_DM, "h3", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_CLK, "d2", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_CMD, "e3", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_DAT0, "e4", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_DAT1, "e2", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_DAT2, "e1", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_DAT3, "f4", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_DAT4, "f3", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_DAT5, "f1", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_DAT6, "g4", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_DAT7, "g3", NULL),
-        _OMAP4_BALLENTRY(ABE_MCBSP2_CLKX, "ad27", NULL),
-        _OMAP4_BALLENTRY(ABE_MCBSP2_DR, "ad26", NULL),
-        _OMAP4_BALLENTRY(ABE_MCBSP2_DX, "ad25", NULL),
-        _OMAP4_BALLENTRY(ABE_MCBSP2_FSX, "ac28", NULL),
-        _OMAP4_BALLENTRY(ABE_MCBSP1_CLKX, "ac26", NULL),
-        _OMAP4_BALLENTRY(ABE_MCBSP1_DR, "ac25", NULL),
-        _OMAP4_BALLENTRY(ABE_MCBSP1_DX, "ab25", NULL),
-        _OMAP4_BALLENTRY(ABE_MCBSP1_FSX, "ac27", NULL),
-        _OMAP4_BALLENTRY(ABE_PDM_UL_DATA, "ag25", NULL),
-        _OMAP4_BALLENTRY(ABE_PDM_DL_DATA, "af25", NULL),
-        _OMAP4_BALLENTRY(ABE_PDM_FRAME, "ae25", NULL),
-        _OMAP4_BALLENTRY(ABE_PDM_LB_CLK, "af26", NULL),
-        _OMAP4_BALLENTRY(ABE_CLKS, "ah26", NULL),
-        _OMAP4_BALLENTRY(ABE_DMIC_CLK1, "ae24", NULL),
-        _OMAP4_BALLENTRY(ABE_DMIC_DIN1, "af24", NULL),
-        _OMAP4_BALLENTRY(ABE_DMIC_DIN2, "ag24", NULL),
-        _OMAP4_BALLENTRY(ABE_DMIC_DIN3, "ah24", NULL),
-        _OMAP4_BALLENTRY(UART2_CTS, "ab26", NULL),
-        _OMAP4_BALLENTRY(UART2_RTS, "ab27", NULL),
-        _OMAP4_BALLENTRY(UART2_RX, "aa25", NULL),
-        _OMAP4_BALLENTRY(UART2_TX, "aa26", NULL),
-        _OMAP4_BALLENTRY(HDQ_SIO, "aa27", NULL),
-        _OMAP4_BALLENTRY(I2C1_SCL, "ae28", NULL),
-        _OMAP4_BALLENTRY(I2C1_SDA, "ae26", NULL),
-        _OMAP4_BALLENTRY(I2C2_SCL, "c26", NULL),
-        _OMAP4_BALLENTRY(I2C2_SDA, "d26", NULL),
-        _OMAP4_BALLENTRY(I2C3_SCL, "w27", NULL),
-        _OMAP4_BALLENTRY(I2C3_SDA, "y27", NULL),
-        _OMAP4_BALLENTRY(I2C4_SCL, "ag21", NULL),
-        _OMAP4_BALLENTRY(I2C4_SDA, "ah22", NULL),
-        _OMAP4_BALLENTRY(MCSPI1_CLK, "af22", NULL),
-        _OMAP4_BALLENTRY(MCSPI1_SOMI, "ae22", NULL),
-        _OMAP4_BALLENTRY(MCSPI1_SIMO, "ag22", NULL),
-        _OMAP4_BALLENTRY(MCSPI1_CS0, "ae23", NULL),
-        _OMAP4_BALLENTRY(MCSPI1_CS1, "af23", NULL),
-        _OMAP4_BALLENTRY(MCSPI1_CS2, "ag23", NULL),
-        _OMAP4_BALLENTRY(MCSPI1_CS3, "ah23", NULL),
-        _OMAP4_BALLENTRY(UART3_CTS_RCTX, "f27", NULL),
-        _OMAP4_BALLENTRY(UART3_RTS_SD, "f28", NULL),
-        _OMAP4_BALLENTRY(UART3_RX_IRRX, "g27", NULL),
-        _OMAP4_BALLENTRY(UART3_TX_IRTX, "g28", NULL),
-        _OMAP4_BALLENTRY(SDMMC5_CLK, "ae5", NULL),
-        _OMAP4_BALLENTRY(SDMMC5_CMD, "af5", NULL),
-        _OMAP4_BALLENTRY(SDMMC5_DAT0, "ae4", NULL),
-        _OMAP4_BALLENTRY(SDMMC5_DAT1, "af4", NULL),
-        _OMAP4_BALLENTRY(SDMMC5_DAT2, "ag3", NULL),
-        _OMAP4_BALLENTRY(SDMMC5_DAT3, "af3", NULL),
-        _OMAP4_BALLENTRY(MCSPI4_CLK, "ae21", NULL),
-        _OMAP4_BALLENTRY(MCSPI4_SIMO, "af20", NULL),
-        _OMAP4_BALLENTRY(MCSPI4_SOMI, "af21", NULL),
-        _OMAP4_BALLENTRY(MCSPI4_CS0, "ae20", NULL),
-        _OMAP4_BALLENTRY(UART4_RX, "ag20", NULL),
-        _OMAP4_BALLENTRY(UART4_TX, "ah19", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_CLK, "ag12", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_STP, "af12", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_DIR, "ae12", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_NXT, "ag13", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT0, "ae11", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT1, "af11", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT2, "ag11", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT3, "ah11", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT4, "ae10", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT5, "af10", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT6, "ag10", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT7, "ae9", NULL),
-        _OMAP4_BALLENTRY(USBB2_HSIC_DATA, "af13", NULL),
-        _OMAP4_BALLENTRY(USBB2_HSIC_STROBE, "ae13", NULL),
-        _OMAP4_BALLENTRY(KPD_COL3, "g26", NULL),
-        _OMAP4_BALLENTRY(KPD_COL4, "g25", NULL),
-        _OMAP4_BALLENTRY(KPD_COL5, "h26", NULL),
-        _OMAP4_BALLENTRY(KPD_COL0, "h25", NULL),
-        _OMAP4_BALLENTRY(KPD_COL1, "j27", NULL),
-        _OMAP4_BALLENTRY(KPD_COL2, "h27", NULL),
-        _OMAP4_BALLENTRY(KPD_ROW3, "j26", NULL),
-        _OMAP4_BALLENTRY(KPD_ROW4, "j25", NULL),
-        _OMAP4_BALLENTRY(KPD_ROW5, "k26", NULL),
-        _OMAP4_BALLENTRY(KPD_ROW0, "k25", NULL),
-        _OMAP4_BALLENTRY(KPD_ROW1, "l27", NULL),
-        _OMAP4_BALLENTRY(KPD_ROW2, "k27", NULL),
-        _OMAP4_BALLENTRY(USBA0_OTG_CE, "c3", NULL),
-        _OMAP4_BALLENTRY(USBA0_OTG_DP, "b5", NULL),
-        _OMAP4_BALLENTRY(USBA0_OTG_DM, "b4", NULL),
-        _OMAP4_BALLENTRY(FREF_CLK1_OUT, "aa28", NULL),
-        _OMAP4_BALLENTRY(FREF_CLK2_OUT, "y28", NULL),
-        _OMAP4_BALLENTRY(SYS_NIRQ1, "ae6", NULL),
-        _OMAP4_BALLENTRY(SYS_NIRQ2, "af6", NULL),
-        _OMAP4_BALLENTRY(SYS_BOOT0, "f26", NULL),
-        _OMAP4_BALLENTRY(SYS_BOOT1, "e27", NULL),
-        _OMAP4_BALLENTRY(SYS_BOOT2, "e26", NULL),
-        _OMAP4_BALLENTRY(SYS_BOOT3, "e25", NULL),
-        _OMAP4_BALLENTRY(SYS_BOOT4, "d28", NULL),
-        _OMAP4_BALLENTRY(SYS_BOOT5, "d27", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU0, "m2", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU1, "n2", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU2, "p2", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU3, "v1", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU4, "v2", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU5, "w1", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU6, "w2", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU7, "w3", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU8, "w4", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU9, "y2", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU10, "y3", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU11, "y4", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU12, "aa1", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU13, "aa2", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU14, "aa3", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU15, "aa4", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU16, "ab2", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU17, "ab3", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU18, "ab4", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU19, "ac4", NULL),
-        { .reg_offset = OMAP_MUX_TERMINATOR },
-};
-#else
-#define omap4_core_cbs_ball  NULL
-#endif
-/*
- * Superset of all mux modes for omap4
- */
-static struct omap_mux __initdata omap4_wkup_muxmodes[] = {
-        _OMAP4_MUXENTRY(SIM_IO, 0, "sim_io", NULL, NULL, "gpio_wk0", NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SIM_CLK, 1, "sim_clk", NULL, NULL, "gpio_wk1", NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SIM_RESET, 2, "sim_reset", NULL, NULL, "gpio_wk2",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SIM_CD, 3, "sim_cd", NULL, NULL, "gpio_wk3", NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SIM_PWRCTRL, 4, "sim_pwrctrl", NULL, NULL, "gpio_wk4",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SR_SCL, 0, "sr_scl", NULL, NULL, NULL, NULL, NULL,
-                        NULL, NULL),
-        _OMAP4_MUXENTRY(SR_SDA, 0, "sr_sda", NULL, NULL, NULL, NULL, NULL,
-                        NULL, NULL),
-        _OMAP4_MUXENTRY(FREF_XTAL_IN, 0, "fref_xtal_in", NULL, NULL, NULL,
-                        "c2c_wakereqin", NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(FREF_SLICER_IN, 0, "fref_slicer_in", NULL, NULL,
-                        "gpi_wk5", "c2c_wakereqin", NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(FREF_CLK_IOREQ, 0, "fref_clk_ioreq", NULL, NULL, NULL,
-                        NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(FREF_CLK0_OUT, 6, "fref_clk0_out", "fref_clk1_req",
-                        "sys_drm_msecure", "gpio_wk6", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(FREF_CLK3_REQ, 30, "fref_clk3_req", "fref_clk1_req",
-                        "sys_drm_msecure", "gpio_wk30", "c2c_wakereqin", NULL,
-                        NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(FREF_CLK3_OUT, 31, "fref_clk3_out", "fref_clk2_req",
-                        "sys_secure_indicator", "gpio_wk31", "c2c_wakereqout",
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(FREF_CLK4_REQ, 7, "fref_clk4_req", "fref_clk5_out",
-                        NULL, "gpio_wk7", NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(FREF_CLK4_OUT, 8, "fref_clk4_out", NULL, NULL,
-                        "gpio_wk8", NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(SYS_32K, 0, "sys_32k", NULL, NULL, NULL, NULL, NULL,
-                        NULL, NULL),
-        _OMAP4_MUXENTRY(SYS_NRESPWRON, 0, "sys_nrespwron", NULL, NULL, NULL,
-                        NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(SYS_NRESWARM, 0, "sys_nreswarm", NULL, NULL, NULL,
-                        NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(SYS_PWR_REQ, 0, "sys_pwr_req", NULL, NULL, NULL, NULL,
-                        NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(SYS_PWRON_RESET_OUT, 29, "sys_pwron_reset_out", NULL,
-                        NULL, "gpio_wk29", NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(SYS_BOOT6, 9, "sys_boot6", "dpm_emu18", NULL,
-                        "gpio_wk9", "c2c_wakereqout", NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(SYS_BOOT7, 10, "sys_boot7", "dpm_emu19", NULL,
-                        "gpio_wk10", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(JTAG_NTRST, 0, "jtag_ntrst", NULL, NULL, NULL, NULL,
-                        NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(JTAG_TCK, 0, "jtag_tck", NULL, NULL, NULL, NULL, NULL,
-                        NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(JTAG_RTCK, 0, "jtag_rtck", NULL, NULL, NULL, NULL,
-                        NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(JTAG_TMS_TMSC, 0, "jtag_tms_tmsc", NULL, NULL, NULL,
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(JTAG_TDI, 0, "jtag_tdi", NULL, NULL, NULL, NULL, NULL,
-                        NULL, NULL),
-        _OMAP4_MUXENTRY(JTAG_TDO, 0, "jtag_tdo", NULL, NULL, NULL, NULL, NULL,
-                        NULL, NULL),
-        { .reg_offset = OMAP_MUX_TERMINATOR },
-};
-/*
- * Balls for 44XX CBL & CBS package - wakeup partition
- * 547-pin CBL ES1.0 S-FPGA-N547, 0.40mm Ball Pitch (Top),
- *                                0.40mm Ball Pitch (Bottom)
- */
-#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS)                \
-                && defined(CONFIG_OMAP_PACKAGE_CBL)
-static struct omap_ball __initdata omap4_wkup_cbl_cbs_ball[] = {
-        _OMAP4_BALLENTRY(SIM_IO, "h4", NULL),
-        _OMAP4_BALLENTRY(SIM_CLK, "j2", NULL),
-        _OMAP4_BALLENTRY(SIM_RESET, "g2", NULL),
-        _OMAP4_BALLENTRY(SIM_CD, "j1", NULL),
-        _OMAP4_BALLENTRY(SIM_PWRCTRL, "k1", NULL),
-        _OMAP4_BALLENTRY(SR_SCL, "ag9", NULL),
-        _OMAP4_BALLENTRY(SR_SDA, "af9", NULL),
-        _OMAP4_BALLENTRY(FREF_XTAL_IN, "ah6", NULL),
-        _OMAP4_BALLENTRY(FREF_SLICER_IN, "ag8", NULL),
-        _OMAP4_BALLENTRY(FREF_CLK_IOREQ, "ad1", NULL),
-        _OMAP4_BALLENTRY(FREF_CLK0_OUT, "ad2", NULL),
-        _OMAP4_BALLENTRY(FREF_CLK3_REQ, "ad3", NULL),
-        _OMAP4_BALLENTRY(FREF_CLK3_OUT, "ad4", NULL),
-        _OMAP4_BALLENTRY(FREF_CLK4_REQ, "ac2", NULL),
-        _OMAP4_BALLENTRY(FREF_CLK4_OUT, "ac3", NULL),
-        _OMAP4_BALLENTRY(SYS_32K, "ag7", NULL),
-        _OMAP4_BALLENTRY(SYS_NRESPWRON, "ae7", NULL),
-        _OMAP4_BALLENTRY(SYS_NRESWARM, "af7", NULL),
-        _OMAP4_BALLENTRY(SYS_PWR_REQ, "ah7", NULL),
-        _OMAP4_BALLENTRY(SYS_PWRON_RESET_OUT, "ag6", NULL),
-        _OMAP4_BALLENTRY(SYS_BOOT6, "af8", NULL),
-        _OMAP4_BALLENTRY(SYS_BOOT7, "ae8", NULL),
-        _OMAP4_BALLENTRY(JTAG_NTRST, "ah2", NULL),
-        _OMAP4_BALLENTRY(JTAG_TCK, "ag1", NULL),
-        _OMAP4_BALLENTRY(JTAG_RTCK, "ae3", NULL),
-        _OMAP4_BALLENTRY(JTAG_TMS_TMSC, "ah1", NULL),
-        _OMAP4_BALLENTRY(JTAG_TDI, "ae1", NULL),
-        _OMAP4_BALLENTRY(JTAG_TDO, "ae2", NULL),
-        { .reg_offset = OMAP_MUX_TERMINATOR },
-};
-#else
-#define omap4_wkup_cbl_cbs_ball  NULL
-#endif
-int __init omap4_mux_init(struct omap_board_mux *board_subset,
-        struct omap_board_mux *board_wkup_subset, int flags)
-{
-        struct omap_ball *package_balls_core;
-        struct omap_ball *package_balls_wkup = omap4_wkup_cbl_cbs_ball;
-        struct omap_mux *core_muxmodes;
-        struct omap_mux *core_subset = NULL;
-        int ret;
-        switch (flags & OMAP_PACKAGE_MASK) {
-        case OMAP_PACKAGE_CBL:
-                pr_debug("%s: OMAP4430 ES1.0 -> OMAP_PACKAGE_CBL\n", __func__);
-                package_balls_core = omap4_core_cbl_ball;
-                core_muxmodes = omap4_core_muxmodes;
-                break;
-        case OMAP_PACKAGE_CBS:
-                pr_debug("%s: OMAP4430 ES2.X -> OMAP_PACKAGE_CBS\n", __func__);
-                package_balls_core = omap4_core_cbs_ball;
-                core_muxmodes = omap4_core_muxmodes;
-                core_subset = omap4_es2_core_subset;
-                break;
-        default:
-                pr_err("%s: Unknown omap package, mux disabled\n", __func__);
-                return -EINVAL;
-        }
-        ret = omap_mux_init("core",
-                            OMAP_MUX_GPIO_IN_MODE3,
-                            OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE,
-                            OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE,
-                            core_muxmodes, core_subset, board_subset,
-                            package_balls_core);
-        if (ret)
-                return ret;
-        ret = omap_mux_init("wkup",
-                            OMAP_MUX_GPIO_IN_MODE3,
-                            OMAP4_CTRL_MODULE_PAD_WKUP_MUX_PBASE,
-                            OMAP4_CTRL_MODULE_PAD_WKUP_MUX_SIZE,
-                            omap4_wkup_muxmodes, NULL, board_wkup_subset,
-                            package_balls_wkup);
-        return ret;
-}
diff --git a/arch/arm/mach-omap2/mux44xx.h b/arch/arm/mach-omap2/mux44xx.h
deleted file mode 100644
index c635026cd7e9..000000000000
--- a/arch/arm/mach-omap2/mux44xx.h
+++ /dev/null
@@ -1,298 +0,0 @@
-/*
- * OMAP44xx MUX registers and bitfields
- *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
- *
- * Benoit Cousson (b-cousson@ti.com)
- *
- * This file is automatically generated from the OMAP hardware databases.
- * We respectfully ask that any modifications to this file be coordinated
- * with the public linux-omap@vger.kernel.org mailing list and the
- * authors above to ensure that the autogeneration scripts are kept
- * up-to-date with the file contents.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ARCH_ARM_MACH_OMAP2_MUX_44XX_H
-#define __ARCH_ARM_MACH_OMAP2_MUX_44XX_H
-#define OMAP4_MUX(M0, mux_value)                                        \
-{                                                                       \
-        .reg_offset     = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET),        \
-        .value          = (mux_value),                                  \
-}
-/* ctrl_module_pad_core base address */
-#define OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE                    0x4a100000
-/* ctrl_module_pad_core registers offset */
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET                   0x0040
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD1_OFFSET                   0x0042
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD2_OFFSET                   0x0044
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD3_OFFSET                   0x0046
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD4_OFFSET                   0x0048
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD5_OFFSET                   0x004a
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD6_OFFSET                   0x004c
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD7_OFFSET                   0x004e
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD8_OFFSET                   0x0050
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD9_OFFSET                   0x0052
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD10_OFFSET                  0x0054
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD11_OFFSET                  0x0056
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD12_OFFSET                  0x0058
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD13_OFFSET                  0x005a
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD14_OFFSET                  0x005c
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD15_OFFSET                  0x005e
-#define OMAP4_CTRL_MODULE_PAD_GPMC_A16_OFFSET                   0x0060
-#define OMAP4_CTRL_MODULE_PAD_GPMC_A17_OFFSET                   0x0062
-#define OMAP4_CTRL_MODULE_PAD_GPMC_A18_OFFSET                   0x0064
-#define OMAP4_CTRL_MODULE_PAD_GPMC_A19_OFFSET                   0x0066
-#define OMAP4_CTRL_MODULE_PAD_GPMC_A20_OFFSET                   0x0068
-#define OMAP4_CTRL_MODULE_PAD_GPMC_A21_OFFSET                   0x006a
-#define OMAP4_CTRL_MODULE_PAD_GPMC_A22_OFFSET                   0x006c
-#define OMAP4_CTRL_MODULE_PAD_GPMC_A23_OFFSET                   0x006e
-#define OMAP4_CTRL_MODULE_PAD_GPMC_A24_OFFSET                   0x0070
-#define OMAP4_CTRL_MODULE_PAD_GPMC_A25_OFFSET                   0x0072
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS0_OFFSET                  0x0074
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS1_OFFSET                  0x0076
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS2_OFFSET                  0x0078
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS3_OFFSET                  0x007a
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NWP_OFFSET                   0x007c
-#define OMAP4_CTRL_MODULE_PAD_GPMC_CLK_OFFSET                   0x007e
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NADV_ALE_OFFSET              0x0080
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NOE_OFFSET                   0x0082
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NWE_OFFSET                   0x0084
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NBE0_CLE_OFFSET              0x0086
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NBE1_OFFSET                  0x0088
-#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT0_OFFSET                 0x008a
-#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT1_OFFSET                 0x008c
-#define OMAP4_CTRL_MODULE_PAD_C2C_DATA11_OFFSET                 0x008e
-#define OMAP4_CTRL_MODULE_PAD_C2C_DATA12_OFFSET                 0x0090
-#define OMAP4_CTRL_MODULE_PAD_C2C_DATA13_OFFSET                 0x0092
-#define OMAP4_CTRL_MODULE_PAD_C2C_DATA14_OFFSET                 0x0094
-#define OMAP4_CTRL_MODULE_PAD_C2C_DATA15_OFFSET                 0x0096
-#define OMAP4_CTRL_MODULE_PAD_HDMI_HPD_OFFSET                   0x0098
-#define OMAP4_CTRL_MODULE_PAD_HDMI_CEC_OFFSET                   0x009a
-#define OMAP4_CTRL_MODULE_PAD_HDMI_DDC_SCL_OFFSET               0x009c
-#define OMAP4_CTRL_MODULE_PAD_HDMI_DDC_SDA_OFFSET               0x009e
-#define OMAP4_CTRL_MODULE_PAD_CSI21_DX0_OFFSET                  0x00a0
-#define OMAP4_CTRL_MODULE_PAD_CSI21_DY0_OFFSET                  0x00a2
-#define OMAP4_CTRL_MODULE_PAD_CSI21_DX1_OFFSET                  0x00a4
-#define OMAP4_CTRL_MODULE_PAD_CSI21_DY1_OFFSET                  0x00a6
-#define OMAP4_CTRL_MODULE_PAD_CSI21_DX2_OFFSET                  0x00a8
-#define OMAP4_CTRL_MODULE_PAD_CSI21_DY2_OFFSET                  0x00aa
-#define OMAP4_CTRL_MODULE_PAD_CSI21_DX3_OFFSET                  0x00ac
-#define OMAP4_CTRL_MODULE_PAD_CSI21_DY3_OFFSET                  0x00ae
-#define OMAP4_CTRL_MODULE_PAD_CSI21_DX4_OFFSET                  0x00b0
-#define OMAP4_CTRL_MODULE_PAD_CSI21_DY4_OFFSET                  0x00b2
-#define OMAP4_CTRL_MODULE_PAD_CSI22_DX0_OFFSET                  0x00b4
-#define OMAP4_CTRL_MODULE_PAD_CSI22_DY0_OFFSET                  0x00b6
-#define OMAP4_CTRL_MODULE_PAD_CSI22_DX1_OFFSET                  0x00b8
-#define OMAP4_CTRL_MODULE_PAD_CSI22_DY1_OFFSET                  0x00ba
-#define OMAP4_CTRL_MODULE_PAD_CAM_SHUTTER_OFFSET                0x00bc
-#define OMAP4_CTRL_MODULE_PAD_CAM_STROBE_OFFSET                 0x00be
-#define OMAP4_CTRL_MODULE_PAD_CAM_GLOBALRESET_OFFSET            0x00c0
-#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_CLK_OFFSET          0x00c2
-#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_STP_OFFSET          0x00c4
-#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DIR_OFFSET          0x00c6
-#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_NXT_OFFSET          0x00c8
-#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT0_OFFSET         0x00ca
-#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT1_OFFSET         0x00cc
-#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT2_OFFSET         0x00ce
-#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT3_OFFSET         0x00d0
-#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT4_OFFSET         0x00d2
-#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT5_OFFSET         0x00d4
-#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT6_OFFSET         0x00d6
-#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT7_OFFSET         0x00d8
-#define OMAP4_CTRL_MODULE_PAD_USBB1_HSIC_DATA_OFFSET            0x00da
-#define OMAP4_CTRL_MODULE_PAD_USBB1_HSIC_STROBE_OFFSET          0x00dc
-#define OMAP4_CTRL_MODULE_PAD_USBC1_ICUSB_DP_OFFSET             0x00de
-#define OMAP4_CTRL_MODULE_PAD_USBC1_ICUSB_DM_OFFSET             0x00e0
-#define OMAP4_CTRL_MODULE_PAD_SDMMC1_CLK_OFFSET                 0x00e2
-#define OMAP4_CTRL_MODULE_PAD_SDMMC1_CMD_OFFSET                 0x00e4
-#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT0_OFFSET                0x00e6
-#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT1_OFFSET                0x00e8
-#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT2_OFFSET                0x00ea
-#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT3_OFFSET                0x00ec
-#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT4_OFFSET                0x00ee
-#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT5_OFFSET                0x00f0
-#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT6_OFFSET                0x00f2
-#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT7_OFFSET                0x00f4
-#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_CLKX_OFFSET            0x00f6
-#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_DR_OFFSET              0x00f8
-#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_DX_OFFSET              0x00fa
-#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_FSX_OFFSET             0x00fc
-#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_CLKX_OFFSET            0x00fe
-#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_DR_OFFSET              0x0100
-#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_DX_OFFSET              0x0102
-#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_FSX_OFFSET             0x0104
-#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_UL_DATA_OFFSET            0x0106
-#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_DL_DATA_OFFSET            0x0108
-#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_FRAME_OFFSET              0x010a
-#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_LB_CLK_OFFSET             0x010c
-#define OMAP4_CTRL_MODULE_PAD_ABE_CLKS_OFFSET                   0x010e
-#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_CLK1_OFFSET              0x0110
-#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN1_OFFSET              0x0112
-#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN2_OFFSET              0x0114
-#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN3_OFFSET              0x0116
-#define OMAP4_CTRL_MODULE_PAD_UART2_CTS_OFFSET                  0x0118
-#define OMAP4_CTRL_MODULE_PAD_UART2_RTS_OFFSET                  0x011a
-#define OMAP4_CTRL_MODULE_PAD_UART2_RX_OFFSET                   0x011c
-#define OMAP4_CTRL_MODULE_PAD_UART2_TX_OFFSET                   0x011e
-#define OMAP4_CTRL_MODULE_PAD_HDQ_SIO_OFFSET                    0x0120
-#define OMAP4_CTRL_MODULE_PAD_I2C1_SCL_OFFSET                   0x0122
-#define OMAP4_CTRL_MODULE_PAD_I2C1_SDA_OFFSET                   0x0124
-#define OMAP4_CTRL_MODULE_PAD_I2C2_SCL_OFFSET                   0x0126
-#define OMAP4_CTRL_MODULE_PAD_I2C2_SDA_OFFSET                   0x0128
-#define OMAP4_CTRL_MODULE_PAD_I2C3_SCL_OFFSET                   0x012a
-#define OMAP4_CTRL_MODULE_PAD_I2C3_SDA_OFFSET                   0x012c
-#define OMAP4_CTRL_MODULE_PAD_I2C4_SCL_OFFSET                   0x012e
-#define OMAP4_CTRL_MODULE_PAD_I2C4_SDA_OFFSET                   0x0130
-#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CLK_OFFSET                 0x0132
-#define OMAP4_CTRL_MODULE_PAD_MCSPI1_SOMI_OFFSET                0x0134
-#define OMAP4_CTRL_MODULE_PAD_MCSPI1_SIMO_OFFSET                0x0136
-#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS0_OFFSET                 0x0138
-#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS1_OFFSET                 0x013a
-#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS2_OFFSET                 0x013c
-#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS3_OFFSET                 0x013e
-#define OMAP4_CTRL_MODULE_PAD_UART3_CTS_RCTX_OFFSET             0x0140
-#define OMAP4_CTRL_MODULE_PAD_UART3_RTS_SD_OFFSET               0x0142
-#define OMAP4_CTRL_MODULE_PAD_UART3_RX_IRRX_OFFSET              0x0144
-#define OMAP4_CTRL_MODULE_PAD_UART3_TX_IRTX_OFFSET              0x0146
-#define OMAP4_CTRL_MODULE_PAD_SDMMC5_CLK_OFFSET                 0x0148
-#define OMAP4_CTRL_MODULE_PAD_SDMMC5_CMD_OFFSET                 0x014a
-#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT0_OFFSET                0x014c
-#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT1_OFFSET                0x014e
-#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT2_OFFSET                0x0150
-#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT3_OFFSET                0x0152
-#define OMAP4_CTRL_MODULE_PAD_MCSPI4_CLK_OFFSET                 0x0154
-#define OMAP4_CTRL_MODULE_PAD_MCSPI4_SIMO_OFFSET                0x0156
-#define OMAP4_CTRL_MODULE_PAD_MCSPI4_SOMI_OFFSET                0x0158
-#define OMAP4_CTRL_MODULE_PAD_MCSPI4_CS0_OFFSET                 0x015a
-#define OMAP4_CTRL_MODULE_PAD_UART4_RX_OFFSET                   0x015c
-#define OMAP4_CTRL_MODULE_PAD_UART4_TX_OFFSET                   0x015e
-#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_CLK_OFFSET          0x0160
-#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_STP_OFFSET          0x0162
-#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DIR_OFFSET          0x0164
-#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_NXT_OFFSET          0x0166
-#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT0_OFFSET         0x0168
-#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT1_OFFSET         0x016a
-#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT2_OFFSET         0x016c
-#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT3_OFFSET         0x016e
-#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT4_OFFSET         0x0170
-#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT5_OFFSET         0x0172
-#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT6_OFFSET         0x0174
-#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT7_OFFSET         0x0176
-#define OMAP4_CTRL_MODULE_PAD_USBB2_HSIC_DATA_OFFSET            0x0178
-#define OMAP4_CTRL_MODULE_PAD_USBB2_HSIC_STROBE_OFFSET          0x017a
-#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX0_OFFSET                 0x017c
-#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY0_OFFSET                 0x017e
-#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX1_OFFSET                 0x0180
-#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY1_OFFSET                 0x0182
-#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX2_OFFSET                 0x0184
-#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY2_OFFSET                 0x0186
-#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX0_OFFSET                 0x0188
-#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY0_OFFSET                 0x018a
-#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX1_OFFSET                 0x018c
-#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY1_OFFSET                 0x018e
-#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX2_OFFSET                 0x0190
-#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY2_OFFSET                 0x0192
-#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_CE_OFFSET               0x0194
-#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_DP_OFFSET               0x0196
-#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_DM_OFFSET               0x0198
-#define OMAP4_CTRL_MODULE_PAD_FREF_CLK1_OUT_OFFSET              0x019a
-#define OMAP4_CTRL_MODULE_PAD_FREF_CLK2_OUT_OFFSET              0x019c
-#define OMAP4_CTRL_MODULE_PAD_SYS_NIRQ1_OFFSET                  0x019e
-#define OMAP4_CTRL_MODULE_PAD_SYS_NIRQ2_OFFSET                  0x01a0
-#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT0_OFFSET                  0x01a2
-#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT1_OFFSET                  0x01a4
-#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT2_OFFSET                  0x01a6
-#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT3_OFFSET                  0x01a8
-#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT4_OFFSET                  0x01aa
-#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT5_OFFSET                  0x01ac
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU0_OFFSET                   0x01ae
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU1_OFFSET                   0x01b0
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU2_OFFSET                   0x01b2
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU3_OFFSET                   0x01b4
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU4_OFFSET                   0x01b6
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU5_OFFSET                   0x01b8
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU6_OFFSET                   0x01ba
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU7_OFFSET                   0x01bc
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU8_OFFSET                   0x01be
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU9_OFFSET                   0x01c0
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU10_OFFSET                  0x01c2
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU11_OFFSET                  0x01c4
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU12_OFFSET                  0x01c6
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU13_OFFSET                  0x01c8
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU14_OFFSET                  0x01ca
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU15_OFFSET                  0x01cc
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU16_OFFSET                  0x01ce
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU17_OFFSET                  0x01d0
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU18_OFFSET                  0x01d2
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET                  0x01d4
-/* ES2.0 only */
-#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT2_OFFSET                 0x008e
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS4_OFFSET                  0x0090
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS5_OFFSET                  0x0092
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS6_OFFSET                  0x0094
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS7_OFFSET                  0x0096
-#define OMAP4_CTRL_MODULE_PAD_KPD_COL3_OFFSET                   0x017c
-#define OMAP4_CTRL_MODULE_PAD_KPD_COL4_OFFSET                   0x017e
-#define OMAP4_CTRL_MODULE_PAD_KPD_COL5_OFFSET                   0x0180
-#define OMAP4_CTRL_MODULE_PAD_KPD_COL0_OFFSET                   0x0182
-#define OMAP4_CTRL_MODULE_PAD_KPD_COL1_OFFSET                   0x0184
-#define OMAP4_CTRL_MODULE_PAD_KPD_COL2_OFFSET                   0x0186
-#define OMAP4_CTRL_MODULE_PAD_KPD_ROW3_OFFSET                   0x0188
-#define OMAP4_CTRL_MODULE_PAD_KPD_ROW4_OFFSET                   0x018a
-#define OMAP4_CTRL_MODULE_PAD_KPD_ROW5_OFFSET                   0x018c
-#define OMAP4_CTRL_MODULE_PAD_KPD_ROW0_OFFSET                   0x018e
-#define OMAP4_CTRL_MODULE_PAD_KPD_ROW1_OFFSET                   0x0190
-#define OMAP4_CTRL_MODULE_PAD_KPD_ROW2_OFFSET                   0x0192
-#define OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE                     \
-                (OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET         \
-                 - OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET + 2)
-/* ctrl_module_pad_wkup base address */
-#define OMAP4_CTRL_MODULE_PAD_WKUP_MUX_PBASE                    0x4a31e000
-/* ctrl_module_pad_wkup registers offset */
-#define OMAP4_CTRL_MODULE_PAD_SIM_IO_OFFSET                     0x0040
-#define OMAP4_CTRL_MODULE_PAD_SIM_CLK_OFFSET                    0x0042
-#define OMAP4_CTRL_MODULE_PAD_SIM_RESET_OFFSET                  0x0044
-#define OMAP4_CTRL_MODULE_PAD_SIM_CD_OFFSET                     0x0046
-#define OMAP4_CTRL_MODULE_PAD_SIM_PWRCTRL_OFFSET                0x0048
-#define OMAP4_CTRL_MODULE_PAD_SR_SCL_OFFSET                     0x004a
-#define OMAP4_CTRL_MODULE_PAD_SR_SDA_OFFSET                     0x004c
-#define OMAP4_CTRL_MODULE_PAD_FREF_XTAL_IN_OFFSET               0x004e
-#define OMAP4_CTRL_MODULE_PAD_FREF_SLICER_IN_OFFSET             0x0050
-#define OMAP4_CTRL_MODULE_PAD_FREF_CLK_IOREQ_OFFSET             0x0052
-#define OMAP4_CTRL_MODULE_PAD_FREF_CLK0_OUT_OFFSET              0x0054
-#define OMAP4_CTRL_MODULE_PAD_FREF_CLK3_REQ_OFFSET              0x0056
-#define OMAP4_CTRL_MODULE_PAD_FREF_CLK3_OUT_OFFSET              0x0058
-#define OMAP4_CTRL_MODULE_PAD_FREF_CLK4_REQ_OFFSET              0x005a
-#define OMAP4_CTRL_MODULE_PAD_FREF_CLK4_OUT_OFFSET              0x005c
-#define OMAP4_CTRL_MODULE_PAD_SYS_32K_OFFSET                    0x005e
-#define OMAP4_CTRL_MODULE_PAD_SYS_NRESPWRON_OFFSET              0x0060
-#define OMAP4_CTRL_MODULE_PAD_SYS_NRESWARM_OFFSET               0x0062
-#define OMAP4_CTRL_MODULE_PAD_SYS_PWR_REQ_OFFSET                0x0064
-#define OMAP4_CTRL_MODULE_PAD_SYS_PWRON_RESET_OUT_OFFSET        0x0066
-#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT6_OFFSET                  0x0068
-#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT7_OFFSET                  0x006a
-#define OMAP4_CTRL_MODULE_PAD_JTAG_NTRST_OFFSET                 0x006c
-#define OMAP4_CTRL_MODULE_PAD_JTAG_TCK_OFFSET                   0x006e
-#define OMAP4_CTRL_MODULE_PAD_JTAG_RTCK_OFFSET                  0x0070
-#define OMAP4_CTRL_MODULE_PAD_JTAG_TMS_TMSC_OFFSET              0x0072
-#define OMAP4_CTRL_MODULE_PAD_JTAG_TDI_OFFSET                   0x0074
-#define OMAP4_CTRL_MODULE_PAD_JTAG_TDO_OFFSET                   0x0076
-#define OMAP4_CTRL_MODULE_PAD_WKUP_MUX_SIZE                     \
-                (OMAP4_CTRL_MODULE_PAD_JTAG_TDO_OFFSET          \
-                 - OMAP4_CTRL_MODULE_PAD_SIM_IO_OFFSET + 2)
-#endif
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index 0ea09faf327b..75e92952c18e 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -20,8 +20,6 @@
 #include "omap44xx.h"
-        __CPUINIT
 /* Physical address needed since MMU not enabled yet on secondary core */
 #define AUX_CORE_BOOT0_PA                       0x48281800
@@ -49,7 +47,7 @@ END(omap5_secondary_startup)
 * The primary core will update this flag using a hardware
 * register AuxCoreBoot0.
 */
-ENTRY(omap_secondary_startup)
+ENTRY(omap4_secondary_startup)
 hold:   ldr     r12,=0x103
        dsb
        smc     #0                      @ read from AuxCoreBoot0
@@ -64,9 +62,9 @@ hold:	ldr	r12,=0x103
         * should now contain the SVC stack for this core
         */
        b       secondary_startup
-ENDPROC(omap_secondary_startup)
+ENDPROC(omap4_secondary_startup)
-ENTRY(omap_secondary_startup_4460)
+ENTRY(omap4460_secondary_startup)
 hold_2: ldr     r12,=0x103
        dsb
        smc     #0                      @ read from AuxCoreBoot0
@@ -101,4 +99,4 @@ hold_2:	ldr	r12,=0x103
         * should now contain the SVC stack for this core
         */
        b       secondary_startup
-ENDPROC(omap_secondary_startup_4460)
+ENDPROC(omap4460_secondary_startup)
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index e80327b6c81f..f991016e2a6a 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -71,10 +71,43 @@ struct omap4_cpu_pm_info {
        void (*secondary_startup)(void);
 };
+/**
+ * struct cpu_pm_ops - CPU pm operations
+ * @finish_suspend:     CPU suspend finisher function pointer
+ * @resume:             CPU resume function pointer
+ * @scu_prepare:        CPU Snoop Control program function pointer
+ *
+ * Structure holds functions pointer for CPU low power operations like
+ * suspend, resume and scu programming.
+ */
+struct cpu_pm_ops {
+        int (*finish_suspend)(unsigned long cpu_state);
+        void (*resume)(void);
+        void (*scu_prepare)(unsigned int cpu_id, unsigned int cpu_state);
+};
 static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
 static struct powerdomain *mpuss_pd;
 static void __iomem *sar_base;
+static int default_finish_suspend(unsigned long cpu_state)
+{
+        omap_do_wfi();
+        return 0;
+}
+static void dummy_cpu_resume(void)
+{}
+static void dummy_scu_prepare(unsigned int cpu_id, unsigned int cpu_state)
+{}
+struct cpu_pm_ops omap_pm_ops = {
+        .finish_suspend         = default_finish_suspend,
+        .resume                 = dummy_cpu_resume,
+        .scu_prepare            = dummy_scu_prepare,
+};
 /*
 * Program the wakeup routine address for the CPU0 and CPU1
 * used for OFF or DORMANT wakeup.
@@ -158,11 +191,12 @@ static void save_l2x0_context(void)
 {
        u32 val;
        void __iomem *l2x0_base = omap4_get_l2cache_base();
+        if (l2x0_base) {
-        val = __raw_readl(l2x0_base + L2X0_AUX_CTRL);
+                val = __raw_readl(l2x0_base + L2X0_AUX_CTRL);
-        __raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET);
+                __raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET);
-        val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL);
+                val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL);
-        __raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET);
+                __raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET);
+        }
 }
 #else
 static void save_l2x0_context(void)
@@ -225,14 +259,17 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
        cpu_clear_prev_logic_pwrst(cpu);
        pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
-        set_cpu_wakeup_addr(cpu, virt_to_phys(omap4_cpu_resume));
+        set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.resume));
-        scu_pwrst_prepare(cpu, power_state);
+        omap_pm_ops.scu_prepare(cpu, power_state);
        l2x0_pwrst_prepare(cpu, save_state);
        /*
         * Call low level function  with targeted low power state.
         */
-        cpu_suspend(save_state, omap4_finish_suspend);
+        if (save_state)
+                cpu_suspend(save_state, omap_pm_ops.finish_suspend);
+        else
+                omap_pm_ops.finish_suspend(save_state);
        /*
         * Restore the CPUx power state to ON otherwise CPUx
@@ -254,7 +291,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
 * @cpu : CPU ID
 * @power_state: CPU low power state.
 */
-int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
+int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
 {
        struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
        unsigned int cpu_state = 0;
@@ -268,14 +305,14 @@ int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
        pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
        pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
        set_cpu_wakeup_addr(cpu, virt_to_phys(pm_info->secondary_startup));
-        scu_pwrst_prepare(cpu, power_state);
+        omap_pm_ops.scu_prepare(cpu, power_state);
        /*
         * CPU never retuns back if targeted power state is OFF mode.
         * CPU ONLINE follows normal CPU ONLINE ptah via
-         * omap_secondary_startup().
+         * omap4_secondary_startup().
         */
-        omap4_finish_suspend(cpu_state);
+        omap_pm_ops.finish_suspend(cpu_state);
        pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
        return 0;
@@ -319,9 +356,9 @@ int __init omap4_mpuss_init(void)
        pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
        pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
        if (cpu_is_omap446x())
-                pm_info->secondary_startup = omap_secondary_startup_4460;
+                pm_info->secondary_startup = omap4460_secondary_startup;
        else
-                pm_info->secondary_startup = omap_secondary_startup;
+                pm_info->secondary_startup = omap4_secondary_startup;
        pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
        if (!pm_info->pwrdm) {
@@ -352,6 +389,12 @@ int __init omap4_mpuss_init(void)
        save_l2x0_context();
+        if (cpu_is_omap44xx()) {
+                omap_pm_ops.finish_suspend = omap4_finish_suspend;
+                omap_pm_ops.resume = omap4_cpu_resume;
+                omap_pm_ops.scu_prepare = scu_pwrst_prepare;
+        }
        return 0;
 }
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 2a551f997aea..8708b2a9da45 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -51,7 +51,7 @@ void __iomem *omap4_get_scu_base(void)
        return scu_base;
 }
-static void __cpuinit omap4_secondary_init(unsigned int cpu)
+static void omap4_secondary_init(unsigned int cpu)
 {
        /*
         * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
@@ -72,7 +72,7 @@ static void __cpuinit omap4_secondary_init(unsigned int cpu)
        spin_unlock(&boot_lock);
 }
-static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
        static struct clockdomain *cpu1_clkdm;
        static bool booted;
@@ -87,7 +87,7 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
        /*
         * Update the AuxCoreBoot0 with boot state for secondary core.
-         * omap_secondary_startup() routine will hold the secondary core till
+         * omap4_secondary_startup() routine will hold the secondary core till
         * the AuxCoreBoot1 register is updated with cpu state
         * A barrier is added to ensure that write buffer is drained
         */
@@ -200,7 +200,7 @@ static void __init omap4_smp_init_cpus(void)
 static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
 {
-        void *startup_addr = omap_secondary_startup;
+        void *startup_addr = omap4_secondary_startup;
        void __iomem *base = omap_get_wakeupgen_base();
        /*
@@ -211,7 +211,7 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
                scu_enable(scu_base);
        if (cpu_is_omap446x()) {
-                startup_addr = omap_secondary_startup_4460;
+                startup_addr = omap4460_secondary_startup;
                pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
        }
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index f8bb3b9b6a76..813c61558a5f 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -323,8 +323,8 @@ static void irq_save_secure_context(void)
 #endif
 #ifdef CONFIG_HOTPLUG_CPU
-static int __cpuinit irq_cpu_hotplug_notify(struct notifier_block *self,
+static int irq_cpu_hotplug_notify(struct notifier_block *self,
-                                         unsigned long action, void *hcpu)
+                                  unsigned long action, void *hcpu)
 {
        unsigned int cpu = (unsigned int)hcpu;
diff --git a/arch/arm/mach-omap2/omap2-restart.c b/arch/arm/mach-omap2/omap2-restart.c
index 719b716a4494..68423e26399d 100644
--- a/arch/arm/mach-omap2/omap2-restart.c
+++ b/arch/arm/mach-omap2/omap2-restart.c
@@ -31,7 +31,7 @@ static struct clk *reset_virt_prcm_set_ck, *reset_sys_ck;
 * Set the DPLL to bypass so that reboot completes successfully.  No
 * return value.
 */
-void omap2xxx_restart(char mode, const char *cmd)
+void omap2xxx_restart(enum reboot_mode mode, const char *cmd)
 {
        u32 rate;
diff --git a/arch/arm/mach-omap2/omap3-restart.c b/arch/arm/mach-omap2/omap3-restart.c
index 923c582189e5..5de2a0c2979d 100644
--- a/arch/arm/mach-omap2/omap3-restart.c
+++ b/arch/arm/mach-omap2/omap3-restart.c
@@ -12,6 +12,7 @@
 */
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/reboot.h>
 #include "iomap.h"
 #include "common.h"
@@ -28,7 +29,7 @@
 * Resets the SoC.  For @cmd, see the 'reboot' syscall in
 * kernel/sys.c.  No return value.
 */
-void omap3xxx_restart(char mode, const char *cmd)
+void omap3xxx_restart(enum reboot_mode mode, const char *cmd)
 {
        omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
        omap3xxx_prm_dpll3_reset(); /* never returns */
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 13b27ffaf45e..57911430324e 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -23,6 +23,7 @@
 #include <linux/export.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/of_address.h>
+#include <linux/reboot.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/map.h>
@@ -339,19 +340,3 @@ int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
        return 0;
 }
 #endif
-/**
- * omap44xx_restart - trigger a software restart of the SoC
- * @mode: the "reboot mode", see arch/arm/kernel/{setup,process}.c
- * @cmd: passed from the userspace program rebooting the system (if provided)
- *
- * Resets the SoC.  For @cmd, see the 'reboot' syscall in
- * kernel/sys.c.  No return value.
- */
-void omap44xx_restart(char mode, const char *cmd)
-{
-        /* XXX Should save 'cmd' into scratchpad for use after reboot */
-        omap4_prminst_global_warm_sw_reset(); /* never returns */
-        while (1);
-}
diff --git a/arch/arm/mach-omap2/omap4-restart.c b/arch/arm/mach-omap2/omap4-restart.c
new file mode 100644
index 000000000000..41dfd7da8170
--- /dev/null
+++ b/arch/arm/mach-omap2/omap4-restart.c
@@ -0,0 +1,28 @@
+/*
+ * omap4-restart.c - Common to OMAP4 and OMAP5
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/types.h>
+#include <linux/reboot.h>
+#include "prminst44xx.h"
+/**
+ * omap44xx_restart - trigger a software restart of the SoC
+ * @mode: the "reboot mode", see arch/arm/kernel/{setup,process}.c
+ * @cmd: passed from the userspace program rebooting the system (if provided)
+ *
+ * Resets the SoC.  For @cmd, see the 'reboot' syscall in
+ * kernel/sys.c.  No return value.
+ */
+void omap44xx_restart(enum reboot_mode mode, const char *cmd)
+{
+        /* XXX Should save 'cmd' into scratchpad for use after reboot */
+        omap4_prminst_global_warm_sw_reset(); /* never returns */
+        while (1)
+                ;
+}
diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c
index e6d230700b2b..f99f68e1e85b 100644
--- a/arch/arm/mach-omap2/omap_device.c
+++ b/arch/arm/mach-omap2/omap_device.c
@@ -129,6 +129,7 @@ static int omap_device_build_from_dt(struct platform_device *pdev)
        struct device_node *node = pdev->dev.of_node;
        const char *oh_name;
        int oh_cnt, i, ret = 0;
+        bool device_active = false;
        oh_cnt = of_property_count_strings(node, "ti,hwmods");
        if (oh_cnt <= 0) {
@@ -152,6 +153,8 @@ static int omap_device_build_from_dt(struct platform_device *pdev)
                        goto odbfd_exit1;
                }
                hwmods[i] = oh;
+                if (oh->flags & HWMOD_INIT_NO_IDLE)
+                        device_active = true;
        }
        od = omap_device_alloc(pdev, hwmods, oh_cnt);
@@ -170,11 +173,13 @@ static int omap_device_build_from_dt(struct platform_device *pdev)
                        r->name = dev_name(&pdev->dev);
        }
-        if (of_get_property(node, "ti,no_idle_on_suspend", NULL))
-                omap_device_disable_idle_on_suspend(pdev);
        pdev->dev.pm_domain = &omap_device_pm_domain;
+        if (device_active) {
+                omap_device_enable(pdev);
+                pm_runtime_set_active(&pdev->dev);
+        }
 odbfd_exit1:
        kfree(hwmods);
 odbfd_exit:
@@ -591,11 +596,6 @@ static int _od_runtime_suspend(struct device *dev)
        return ret;
 }
-static int _od_runtime_idle(struct device *dev)
-{
-        return pm_generic_runtime_idle(dev);
-}
 static int _od_runtime_resume(struct device *dev)
 {
        struct platform_device *pdev = to_platform_device(dev);
@@ -621,8 +621,7 @@ static int _od_suspend_noirq(struct device *dev)
        if (!ret && !pm_runtime_status_suspended(dev)) {
                if (pm_generic_runtime_suspend(dev) == 0) {
-                        if (!(od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND))
+                        omap_device_idle(pdev);
-                                omap_device_idle(pdev);
                        od->flags |= OMAP_DEVICE_SUSPENDED;
                }
        }
@@ -638,8 +637,7 @@ static int _od_resume_noirq(struct device *dev)
        if ((od->flags & OMAP_DEVICE_SUSPENDED) &&
            !pm_runtime_status_suspended(dev)) {
                od->flags &= ~OMAP_DEVICE_SUSPENDED;
-                if (!(od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND))
+                omap_device_enable(pdev);
-                        omap_device_enable(pdev);
                pm_generic_runtime_resume(dev);
        }
@@ -653,7 +651,7 @@ static int _od_resume_noirq(struct device *dev)
 struct dev_pm_domain omap_device_pm_domain = {
        .ops = {
                SET_RUNTIME_PM_OPS(_od_runtime_suspend, _od_runtime_resume,
-                                   _od_runtime_idle)
+                                   NULL)
                USE_PLATFORM_PM_SLEEP_OPS
                .suspend_noirq = _od_suspend_noirq,
                .resume_noirq = _od_resume_noirq,
@@ -852,6 +850,7 @@ static int __init omap_device_late_idle(struct device *dev, void *data)
 {
        struct platform_device *pdev = to_platform_device(dev);
        struct omap_device *od = to_omap_device(pdev);
+        int i;
        if (!od)
                return 0;
@@ -860,6 +859,15 @@ static int __init omap_device_late_idle(struct device *dev, void *data)
         * If omap_device state is enabled, but has no driver bound,
         * idle it.
         */
+        /*
+         * Some devices (like memory controllers) are always kept
+         * enabled, and should not be idled even with no drivers.
+         */
+        for (i = 0; i < od->hwmods_cnt; i++)
+                if (od->hwmods[i]->flags & HWMOD_INIT_NO_IDLE)
+                        return 0;
        if (od->_driver_status != BUS_NOTIFY_BOUND_DRIVER) {
                if (od->_state == OMAP_DEVICE_STATE_ENABLED) {
                        dev_warn(dev, "%s: enabled but no driver.  Idling\n",
diff --git a/arch/arm/mach-omap2/omap_device.h b/arch/arm/mach-omap2/omap_device.h
index 044c31d50e5b..17ca1aec2710 100644
--- a/arch/arm/mach-omap2/omap_device.h
+++ b/arch/arm/mach-omap2/omap_device.h
@@ -38,7 +38,6 @@ extern struct dev_pm_domain omap_device_pm_domain;
 /* omap_device.flags values */
 #define OMAP_DEVICE_SUSPENDED           BIT(0)
-#define OMAP_DEVICE_NO_IDLE_ON_SUSPEND  BIT(1)
 /**
 * struct omap_device - omap_device wrapper for platform_devices
@@ -101,13 +100,4 @@ static inline struct omap_device *to_omap_device(struct platform_device *pdev)
 {
        return pdev ? pdev->archdata.od : NULL;
 }
-static inline
-void omap_device_disable_idle_on_suspend(struct platform_device *pdev)
-{
-        struct omap_device *od = to_omap_device(pdev);
-        od->flags |= OMAP_DEVICE_NO_IDLE_ON_SUSPEND;
-}
 #endif
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 7341eff63f56..7f4db12b1459 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -2386,7 +2386,7 @@ static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data)
                np = of_dev_hwmod_lookup(of_find_node_by_name(NULL, "ocp"), oh);
                if (np)
-                        va_start = of_iomap(np, 0);
+                        va_start = of_iomap(np, oh->mpu_rt_idx);
        } else {
                va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
        }
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index 0c898f58ac9b..e1482a9b3bc2 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -95,6 +95,54 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3;
 #define MODULEMODE_HWCTRL               1
 #define MODULEMODE_SWCTRL               2
+#define DEBUG_OMAP2UART1_FLAGS  0
+#define DEBUG_OMAP2UART2_FLAGS  0
+#define DEBUG_OMAP2UART3_FLAGS  0
+#define DEBUG_OMAP3UART3_FLAGS  0
+#define DEBUG_OMAP3UART4_FLAGS  0
+#define DEBUG_OMAP4UART3_FLAGS  0
+#define DEBUG_OMAP4UART4_FLAGS  0
+#define DEBUG_TI81XXUART1_FLAGS 0
+#define DEBUG_TI81XXUART2_FLAGS 0
+#define DEBUG_TI81XXUART3_FLAGS 0
+#define DEBUG_AM33XXUART1_FLAGS 0
+#define DEBUG_OMAPUART_FLAGS    (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET)
+#if defined(CONFIG_DEBUG_OMAP2UART1)
+#undef DEBUG_OMAP2UART1_FLAGS
+#define DEBUG_OMAP2UART1_FLAGS DEBUG_OMAPUART_FLAGS
+#elif defined(CONFIG_DEBUG_OMAP2UART2)
+#undef DEBUG_OMAP2UART2_FLAGS
+#define DEBUG_OMAP2UART2_FLAGS DEBUG_OMAPUART_FLAGS
+#elif defined(CONFIG_DEBUG_OMAP2UART3)
+#undef DEBUG_OMAP2UART3_FLAGS
+#define DEBUG_OMAP2UART3_FLAGS DEBUG_OMAPUART_FLAGS
+#elif defined(CONFIG_DEBUG_OMAP3UART3)
+#undef DEBUG_OMAP3UART3_FLAGS
+#define DEBUG_OMAP3UART3_FLAGS DEBUG_OMAPUART_FLAGS
+#elif defined(CONFIG_DEBUG_OMAP3UART4)
+#undef DEBUG_OMAP3UART4_FLAGS
+#define DEBUG_OMAP3UART4_FLAGS DEBUG_OMAPUART_FLAGS
+#elif defined(CONFIG_DEBUG_OMAP4UART3)
+#undef DEBUG_OMAP4UART3_FLAGS
+#define DEBUG_OMAP4UART3_FLAGS DEBUG_OMAPUART_FLAGS
+#elif defined(CONFIG_DEBUG_OMAP4UART4)
+#undef DEBUG_OMAP4UART4_FLAGS
+#define DEBUG_OMAP4UART4_FLAGS DEBUG_OMAPUART_FLAGS
+#elif defined(CONFIG_DEBUG_TI81XXUART1)
+#undef DEBUG_TI81XXUART1_FLAGS
+#define DEBUG_TI81XXUART1_FLAGS DEBUG_OMAPUART_FLAGS
+#elif defined(CONFIG_DEBUG_TI81XXUART2)
+#undef DEBUG_TI81XXUART2_FLAGS
+#define DEBUG_TI81XXUART2_FLAGS DEBUG_OMAPUART_FLAGS
+#elif defined(CONFIG_DEBUG_TI81XXUART3)
+#undef DEBUG_TI81XXUART3_FLAGS
+#define DEBUG_TI81XXUART3_FLAGS DEBUG_OMAPUART_FLAGS
+#elif defined(CONFIG_DEBUG_AM33XXUART1)
+#undef DEBUG_AM33XXUART1_FLAGS
+#define DEBUG_AM33XXUART1_FLAGS DEBUG_OMAPUART_FLAGS
+#endif
 /**
 * struct omap_hwmod_mux_info - hwmod specific mux configuration
@@ -568,6 +616,7 @@ struct omap_hwmod_link {
 * @voltdm: pointer to voltage domain (filled in at runtime)
 * @dev_attr: arbitrary device attributes that can be passed to the driver
 * @_sysc_cache: internal-use hwmod flags
+ * @mpu_rt_idx: index of device address space for register target (for DT boot)
 * @_mpu_rt_va: cached register target start address (internal use)
 * @_mpu_port: cached MPU register target slave (internal use)
 * @opt_clks_cnt: number of @opt_clks
@@ -617,6 +666,7 @@ struct omap_hwmod {
        struct list_head                node;
        struct omap_hwmod_ocp_if        *_mpu_port;
        u16                             flags;
+        u8                              mpu_rt_idx;
        u8                              response_lat;
        u8                              rst_lines_cnt;
        u8                              opt_clks_cnt;
@@ -699,6 +749,7 @@ extern int omap2420_hwmod_init(void);
 extern int omap2430_hwmod_init(void);
 extern int omap3xxx_hwmod_init(void);
 extern int omap44xx_hwmod_init(void);
+extern int omap54xx_hwmod_init(void);
 extern int am33xx_hwmod_init(void);
 extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 5137cc84b504..d8b9d60f854f 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -16,6 +16,7 @@
 #include <linux/i2c-omap.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <linux/omap-dma.h>
+#include <linux/platform_data/mailbox-omap.h>
 #include <plat/dmtimer.h>
 #include "omap_hwmod.h"
@@ -166,6 +167,18 @@ static struct omap_hwmod omap2420_dma_system_hwmod = {
 };
 /* mailbox */
+static struct omap_mbox_dev_info omap2420_mailbox_info[] = {
+        { .name = "dsp", .tx_id = 0, .rx_id = 1, .irq_id = 0, .usr_id = 0 },
+        { .name = "iva", .tx_id = 2, .rx_id = 3, .irq_id = 1, .usr_id = 3 },
+};
+static struct omap_mbox_pdata omap2420_mailbox_attrs = {
+        .num_users      = 4,
+        .num_fifos      = 6,
+        .info_cnt       = ARRAY_SIZE(omap2420_mailbox_info),
+        .info           = omap2420_mailbox_info,
+};
 static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
        { .name = "dsp", .irq = 26 + OMAP_INTC_START, },
        { .name = "iva", .irq = 34 + OMAP_INTC_START, },
@@ -186,6 +199,7 @@ static struct omap_hwmod omap2420_mailbox_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
                },
        },
+        .dev_attr       = &omap2420_mailbox_attrs,
 };
 /*
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 4ce999ee3ee9..5b9083461dc5 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -17,6 +17,7 @@
 #include <linux/platform_data/asoc-ti-mcbsp.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <linux/omap-dma.h>
+#include <linux/platform_data/mailbox-omap.h>
 #include <plat/dmtimer.h>
 #include "omap_hwmod.h"
@@ -170,6 +171,17 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
 };
 /* mailbox */
+static struct omap_mbox_dev_info omap2430_mailbox_info[] = {
+        { .name = "dsp", .tx_id = 0, .rx_id = 1 },
+};
+static struct omap_mbox_pdata omap2430_mailbox_attrs = {
+        .num_users      = 4,
+        .num_fifos      = 6,
+        .info_cnt       = ARRAY_SIZE(omap2430_mailbox_info),
+        .info           = omap2430_mailbox_info,
+};
 static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
        { .irq = 26 + OMAP_INTC_START, },
        { .irq = -1 },
@@ -189,6 +201,7 @@ static struct omap_hwmod omap2430_mailbox_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
                },
        },
+        .dev_attr       = &omap2430_mailbox_attrs,
 };
 /* mcspi3 */
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
index 534974e08add..5da7a42a6d90 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
@@ -17,7 +17,6 @@
 #include "hdq1w.h"
 #include "omap_hwmod_common_data.h"
-#include "dma.h"
 /* UART */
@@ -89,32 +88,32 @@ struct omap_hwmod_class omap2_venc_hwmod_class = {
 /* Common DMA request line data */
 struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {
-        { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
+        { .name = "rx", .dma_req = 50, },
-        { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
+        { .name = "tx", .dma_req = 49, },
        { .dma_req = -1 }
 };
 struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {
-        { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
+        { .name = "rx", .dma_req = 52, },
-        { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
+        { .name = "tx", .dma_req = 51, },
        { .dma_req = -1 }
 };
 struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {
-        { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
+        { .name = "rx", .dma_req = 54, },
-        { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
+        { .name = "tx", .dma_req = 53, },
        { .dma_req = -1 }
 };
 struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {
-        { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
+        { .name = "tx", .dma_req = 27 },
-        { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
+        { .name = "rx", .dma_req = 28 },
        { .dma_req = -1 }
 };
 struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {
-        { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
+        { .name = "tx", .dma_req = 29 },
-        { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
+        { .name = "rx", .dma_req = 30 },
        { .dma_req = -1 }
 };
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index d05fc7b54567..56cebb05509e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -512,7 +512,7 @@ struct omap_hwmod omap2xxx_uart1_hwmod = {
        .mpu_irqs       = omap2_uart1_mpu_irqs,
        .sdma_reqs      = omap2_uart1_sdma_reqs,
        .main_clk       = "uart1_fck",
-        .flags          = HWMOD_SWSUP_SIDLE_ACT,
+        .flags          = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
        .prcm           = {
                .omap2 = {
                        .module_offs = CORE_MOD,
@@ -532,7 +532,7 @@ struct omap_hwmod omap2xxx_uart2_hwmod = {
        .mpu_irqs       = omap2_uart2_mpu_irqs,
        .sdma_reqs      = omap2_uart2_sdma_reqs,
        .main_clk       = "uart2_fck",
-        .flags          = HWMOD_SWSUP_SIDLE_ACT,
+        .flags          = DEBUG_OMAP2UART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
        .prcm           = {
                .omap2 = {
                        .module_offs = CORE_MOD,
@@ -552,7 +552,7 @@ struct omap_hwmod omap2xxx_uart3_hwmod = {
        .mpu_irqs       = omap2_uart3_mpu_irqs,
        .sdma_reqs      = omap2_uart3_sdma_reqs,
        .main_clk       = "uart3_fck",
-        .flags          = HWMOD_SWSUP_SIDLE_ACT,
+        .flags          = DEBUG_OMAP2UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
        .prcm           = {
                .omap2 = {
                        .module_offs = CORE_MOD,
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 69337af748cc..eb2f3b93b51c 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -35,29 +35,6 @@
 */
 /*
- * 'emif_fw' class
- * instance(s): emif_fw
- */
-static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
-        .name           = "emif_fw",
-};
-/* emif_fw */
-static struct omap_hwmod am33xx_emif_fw_hwmod = {
-        .name           = "emif_fw",
-        .class          = &am33xx_emif_fw_hwmod_class,
-        .clkdm_name     = "l4fw_clkdm",
-        .main_clk       = "l4fw_gclk",
-        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-/*
 * 'emif' class
 * instance(s): emif
 */
@@ -70,18 +47,12 @@ static struct omap_hwmod_class am33xx_emif_hwmod_class = {
        .sysc           = &am33xx_emif_sysc,
 };
-static struct omap_hwmod_irq_info am33xx_emif_irqs[] = {
-        { .name = "ddrerr0", .irq = 101 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 /* emif */
 static struct omap_hwmod am33xx_emif_hwmod = {
        .name           = "emif",
        .class          = &am33xx_emif_hwmod_class,
        .clkdm_name     = "l3_clkdm",
        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-        .mpu_irqs       = am33xx_emif_irqs,
        .main_clk       = "dpll_ddr_m2_div2_ck",
        .prcm           = {
                .omap4  = {
@@ -99,19 +70,11 @@ static struct omap_hwmod_class am33xx_l3_hwmod_class = {
        .name           = "l3",
 };
-/* l3_main (l3_fast) */
-static struct omap_hwmod_irq_info am33xx_l3_main_irqs[] = {
-        { .name = "l3debug", .irq = 9 + OMAP_INTC_START, },
-        { .name = "l3appint", .irq = 10 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_l3_main_hwmod = {
        .name           = "l3_main",
        .class          = &am33xx_l3_hwmod_class,
        .clkdm_name     = "l3_clkdm",
        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-        .mpu_irqs       = am33xx_l3_main_irqs,
        .main_clk       = "l3_gclk",
        .prcm           = {
                .omap4  = {
@@ -196,20 +159,6 @@ static struct omap_hwmod am33xx_l4_wkup_hwmod = {
        },
 };
-/* l4_fw */
-static struct omap_hwmod am33xx_l4_fw_hwmod = {
-        .name           = "l4_fw",
-        .class          = &am33xx_l4_hwmod_class,
-        .clkdm_name     = "l4fw_clkdm",
-        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
 /*
 * 'mpu' class
 */
@@ -217,21 +166,11 @@ static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
        .name   = "mpu",
 };
-/* mpu */
-static struct omap_hwmod_irq_info am33xx_mpu_irqs[] = {
-        { .name = "emuint", .irq = 0 + OMAP_INTC_START, },
-        { .name = "commtx", .irq = 1 + OMAP_INTC_START, },
-        { .name = "commrx", .irq = 2 + OMAP_INTC_START, },
-        { .name = "bench", .irq = 3 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_mpu_hwmod = {
        .name           = "mpu",
        .class          = &am33xx_mpu_hwmod_class,
        .clkdm_name     = "mpu_clkdm",
        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-        .mpu_irqs       = am33xx_mpu_irqs,
        .main_clk       = "dpll_mpu_m2_ck",
        .prcm           = {
                .omap4  = {
@@ -253,11 +192,6 @@ static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
        { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
 };
-static struct omap_hwmod_irq_info am33xx_wkup_m3_irqs[] = {
-        { .name = "txev", .irq = 78 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 /* wkup_m3  */
 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
        .name           = "wkup_m3",
@@ -265,7 +199,6 @@ static struct omap_hwmod am33xx_wkup_m3_hwmod = {
        .clkdm_name     = "l4_wkup_aon_clkdm",
        /* Keep hardreset asserted */
        .flags          = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
-        .mpu_irqs       = am33xx_wkup_m3_irqs,
        .main_clk       = "dpll_core_m4_div2_ck",
        .prcm           = {
                .omap4  = {
@@ -291,25 +224,12 @@ static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
        { .name = "pruss", .rst_shift = 1 },
 };
-static struct omap_hwmod_irq_info am33xx_pruss_irqs[] = {
-        { .name = "evtout0", .irq = 20 + OMAP_INTC_START, },
-        { .name = "evtout1", .irq = 21 + OMAP_INTC_START, },
-        { .name = "evtout2", .irq = 22 + OMAP_INTC_START, },
-        { .name = "evtout3", .irq = 23 + OMAP_INTC_START, },
-        { .name = "evtout4", .irq = 24 + OMAP_INTC_START, },
-        { .name = "evtout5", .irq = 25 + OMAP_INTC_START, },
-        { .name = "evtout6", .irq = 26 + OMAP_INTC_START, },
-        { .name = "evtout7", .irq = 27 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 /* pru-icss */
 /* Pseudo hwmod for reset control purpose only */
 static struct omap_hwmod am33xx_pruss_hwmod = {
        .name           = "pruss",
        .class          = &am33xx_pruss_hwmod_class,
        .clkdm_name     = "pruss_ocp_clkdm",
-        .mpu_irqs       = am33xx_pruss_irqs,
        .main_clk       = "pruss_ocp_gclk",
        .prcm           = {
                .omap4  = {
@@ -329,24 +249,19 @@ static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
 };
 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
-        { .name = "gfx", .rst_shift = 0 },
+        { .name = "gfx", .rst_shift = 0, .st_shift = 0},
-};
-static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
-        { .name = "gfxint", .irq = 37 + OMAP_INTC_START, },
-        { .irq = -1 },
 };
 static struct omap_hwmod am33xx_gfx_hwmod = {
        .name           = "gfx",
        .class          = &am33xx_gfx_hwmod_class,
        .clkdm_name     = "gfx_l3_clkdm",
-        .mpu_irqs       = am33xx_gfx_irqs,
        .main_clk       = "gfx_fck_div_ck",
        .prcm           = {
                .omap4  = {
                        .clkctrl_offs   = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
                        .rstctrl_offs   = AM33XX_RM_GFX_RSTCTRL_OFFSET,
+                        .rstst_offs     = AM33XX_RM_GFX_RSTST_OFFSET,
                        .modulemode     = MODULEMODE_SWCTRL,
                },
        },
@@ -387,16 +302,10 @@ static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
        .sysc           = &am33xx_adc_tsc_sysc,
 };
-static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
-        { .irq = 16 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
        .name           = "adc_tsc",
        .class          = &am33xx_adc_tsc_hwmod_class,
        .clkdm_name     = "l4_wkup_clkdm",
-        .mpu_irqs       = am33xx_adc_tsc_irqs,
        .main_clk       = "adc_tsc_fck",
        .prcm           = {
                .omap4  = {
@@ -515,23 +424,10 @@ static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
        .sysc           = &am33xx_aes0_sysc,
 };
-static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
-        { .irq = 103 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-static struct omap_hwmod_dma_info am33xx_aes0_edma_reqs[] = {
-        { .name = "tx", .dma_req = 6, },
-        { .name = "rx", .dma_req = 5, },
-        { .dma_req = -1 }
-};
 static struct omap_hwmod am33xx_aes0_hwmod = {
        .name           = "aes",
        .class          = &am33xx_aes0_hwmod_class,
        .clkdm_name     = "l3_clkdm",
-        .mpu_irqs       = am33xx_aes0_irqs,
-        .sdma_reqs      = am33xx_aes0_edma_reqs,
        .main_clk       = "aes0_fck",
        .prcm           = {
                .omap4  = {
@@ -554,22 +450,10 @@ static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
        .sysc           = &am33xx_sha0_sysc,
 };
-static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
-        { .irq = 109 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-static struct omap_hwmod_dma_info am33xx_sha0_edma_reqs[] = {
-        { .name = "rx", .dma_req = 36, },
-        { .dma_req = -1 }
-};
 static struct omap_hwmod am33xx_sha0_hwmod = {
        .name           = "sham",
        .class          = &am33xx_sha0_hwmod_class,
        .clkdm_name     = "l3_clkdm",
-        .mpu_irqs       = am33xx_sha0_irqs,
-        .sdma_reqs      = am33xx_sha0_edma_reqs,
        .main_clk       = "l3_gclk",
        .prcm           = {
                .omap4  = {
@@ -604,16 +488,10 @@ static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
 };
 /* smartreflex0 */
-static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
-        { .irq = 120 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_smartreflex0_hwmod = {
        .name           = "smartreflex0",
        .class          = &am33xx_smartreflex_hwmod_class,
        .clkdm_name     = "l4_wkup_clkdm",
-        .mpu_irqs       = am33xx_smartreflex0_irqs,
        .main_clk       = "smartreflex0_fck",
        .prcm           = {
                .omap4  = {
@@ -624,16 +502,10 @@ static struct omap_hwmod am33xx_smartreflex0_hwmod = {
 };
 /* smartreflex1 */
-static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
-        { .irq = 121 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_smartreflex1_hwmod = {
        .name           = "smartreflex1",
        .class          = &am33xx_smartreflex_hwmod_class,
        .clkdm_name     = "l4_wkup_clkdm",
-        .mpu_irqs       = am33xx_smartreflex1_irqs,
        .main_clk       = "smartreflex1_fck",
        .prcm           = {
                .omap4  = {
@@ -650,17 +522,11 @@ static struct omap_hwmod_class am33xx_control_hwmod_class = {
        .name           = "control",
 };
-static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
-        { .irq = 8 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_control_hwmod = {
        .name           = "control",
        .class          = &am33xx_control_hwmod_class,
        .clkdm_name     = "l4_wkup_clkdm",
        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-        .mpu_irqs       = am33xx_control_irqs,
        .main_clk       = "dpll_core_m4_div2_ck",
        .prcm           = {
                .omap4  = {
@@ -690,21 +556,13 @@ static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
        .sysc           = &am33xx_cpgmac_sysc,
 };
-static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
-        { .name = "c0_rx_thresh_pend", .irq = 40 + OMAP_INTC_START, },
-        { .name = "c0_rx_pend", .irq = 41 + OMAP_INTC_START, },
-        { .name = "c0_tx_pend", .irq = 42 + OMAP_INTC_START, },
-        { .name = "c0_misc_pend", .irq = 43 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_cpgmac0_hwmod = {
        .name           = "cpgmac0",
        .class          = &am33xx_cpgmac0_hwmod_class,
        .clkdm_name     = "cpsw_125mhz_clkdm",
        .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
-        .mpu_irqs       = am33xx_cpgmac0_irqs,
        .main_clk       = "cpsw_125mhz_gclk",
+        .mpu_rt_idx     = 1,
        .prcm           = {
                .omap4  = {
                        .clkctrl_offs   = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
@@ -735,17 +593,10 @@ static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
 };
 /* dcan0 */
-static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
-        { .name = "d_can_ms", .irq = 52 + OMAP_INTC_START, },
-        { .name = "d_can_mo", .irq = 53 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_dcan0_hwmod = {
        .name           = "d_can0",
        .class          = &am33xx_dcan_hwmod_class,
        .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_dcan0_irqs,
        .main_clk       = "dcan0_fck",
        .prcm           = {
                .omap4  = {
@@ -756,16 +607,10 @@ static struct omap_hwmod am33xx_dcan0_hwmod = {
 };
 /* dcan1 */
-static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
-        { .name = "d_can_ms", .irq = 55 + OMAP_INTC_START, },
-        { .name = "d_can_mo", .irq = 56 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_dcan1_hwmod = {
        .name           = "d_can1",
        .class          = &am33xx_dcan_hwmod_class,
        .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_dcan1_irqs,
        .main_clk       = "dcan1_fck",
        .prcm           = {
                .omap4  = {
@@ -792,16 +637,10 @@ static struct omap_hwmod_class am33xx_elm_hwmod_class = {
        .sysc           = &am33xx_elm_sysc,
 };
-static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
-        { .irq = 4 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_elm_hwmod = {
        .name           = "elm",
        .class          = &am33xx_elm_hwmod_class,
        .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_elm_irqs,
        .main_clk       = "l4ls_gclk",
        .prcm           = {
                .omap4  = {
@@ -854,45 +693,26 @@ static struct omap_hwmod am33xx_epwmss0_hwmod = {
 };
 /* ecap0 */
-static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
-        { .irq = 31 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_ecap0_hwmod = {
        .name           = "ecap0",
        .class          = &am33xx_ecap_hwmod_class,
        .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_ecap0_irqs,
        .main_clk       = "l4ls_gclk",
 };
 /* eqep0 */
-static struct omap_hwmod_irq_info am33xx_eqep0_irqs[] = {
-        { .irq = 79 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_eqep0_hwmod = {
        .name           = "eqep0",
        .class          = &am33xx_eqep_hwmod_class,
        .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_eqep0_irqs,
        .main_clk       = "l4ls_gclk",
 };
 /* ehrpwm0 */
-static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
-        { .name = "int", .irq = 86 + OMAP_INTC_START, },
-        { .name = "tzint", .irq = 58 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
        .name           = "ehrpwm0",
        .class          = &am33xx_ehrpwm_hwmod_class,
        .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_ehrpwm0_irqs,
        .main_clk       = "l4ls_gclk",
 };
@@ -911,45 +731,26 @@ static struct omap_hwmod am33xx_epwmss1_hwmod = {
 };
 /* ecap1 */
-static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
-        { .irq = 47 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_ecap1_hwmod = {
        .name           = "ecap1",
        .class          = &am33xx_ecap_hwmod_class,
        .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_ecap1_irqs,
        .main_clk       = "l4ls_gclk",
 };
 /* eqep1 */
-static struct omap_hwmod_irq_info am33xx_eqep1_irqs[] = {
-        { .irq = 88 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_eqep1_hwmod = {
        .name           = "eqep1",
        .class          = &am33xx_eqep_hwmod_class,
        .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_eqep1_irqs,
        .main_clk       = "l4ls_gclk",
 };
 /* ehrpwm1 */
-static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
-        { .name = "int", .irq = 87 + OMAP_INTC_START, },
-        { .name = "tzint", .irq = 59 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
        .name           = "ehrpwm1",
        .class          = &am33xx_ehrpwm_hwmod_class,
        .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_ehrpwm1_irqs,
        .main_clk       = "l4ls_gclk",
 };
@@ -968,45 +769,26 @@ static struct omap_hwmod am33xx_epwmss2_hwmod = {
 };
 /* ecap2 */
-static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
-        { .irq = 61 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_ecap2_hwmod = {
        .name           = "ecap2",
        .class          = &am33xx_ecap_hwmod_class,
        .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_ecap2_irqs,
        .main_clk       = "l4ls_gclk",
 };
 /* eqep2 */
-static struct omap_hwmod_irq_info am33xx_eqep2_irqs[] = {
-        { .irq = 89 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_eqep2_hwmod = {
        .name           = "eqep2",
        .class          = &am33xx_eqep_hwmod_class,
        .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_eqep2_irqs,
        .main_clk       = "l4ls_gclk",
 };
 /* ehrpwm2 */
-static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
-        { .name = "int", .irq = 39 + OMAP_INTC_START, },
-        { .name = "tzint", .irq = 60 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
        .name           = "ehrpwm2",
        .class          = &am33xx_ehrpwm_hwmod_class,
        .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_ehrpwm2_irqs,
        .main_clk       = "l4ls_gclk",
 };
@@ -1041,17 +823,11 @@ static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
        { .role = "dbclk", .clk = "gpio0_dbclk" },
 };
-static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
-        { .irq = 96 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_gpio0_hwmod = {
        .name           = "gpio1",
        .class          = &am33xx_gpio_hwmod_class,
        .clkdm_name     = "l4_wkup_clkdm",
        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = am33xx_gpio0_irqs,
        .main_clk       = "dpll_core_m4_div2_ck",
        .prcm           = {
                .omap4  = {
@@ -1065,11 +841,6 @@ static struct omap_hwmod am33xx_gpio0_hwmod = {
 };
 /* gpio1 */
-static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
-        { .irq = 98 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
        { .role = "dbclk", .clk = "gpio1_dbclk" },
 };
@@ -1079,7 +850,6 @@ static struct omap_hwmod am33xx_gpio1_hwmod = {
        .class          = &am33xx_gpio_hwmod_class,
        .clkdm_name     = "l4ls_clkdm",
        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = am33xx_gpio1_irqs,
        .main_clk       = "l4ls_gclk",
        .prcm           = {
                .omap4  = {
@@ -1093,11 +863,6 @@ static struct omap_hwmod am33xx_gpio1_hwmod = {
 };
 /* gpio2 */
-static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
-        { .irq = 32 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
        { .role = "dbclk", .clk = "gpio2_dbclk" },
 };
@@ -1107,7 +872,6 @@ static struct omap_hwmod am33xx_gpio2_hwmod = {
        .class          = &am33xx_gpio_hwmod_class,
        .clkdm_name     = "l4ls_clkdm",
        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = am33xx_gpio2_irqs,
        .main_clk       = "l4ls_gclk",
        .prcm           = {
                .omap4  = {
@@ -1121,11 +885,6 @@ static struct omap_hwmod am33xx_gpio2_hwmod = {
 };
 /* gpio3 */
-static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
-        { .irq = 62 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
        { .role = "dbclk", .clk = "gpio3_dbclk" },
 };
@@ -1135,7 +894,6 @@ static struct omap_hwmod am33xx_gpio3_hwmod = {
        .class          = &am33xx_gpio_hwmod_class,
        .clkdm_name     = "l4ls_clkdm",
        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = am33xx_gpio3_irqs,
        .main_clk       = "l4ls_gclk",
        .prcm           = {
                .omap4  = {
@@ -1164,17 +922,11 @@ static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
        .sysc           = &gpmc_sysc,
 };
-static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = {
-        { .irq = 100 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_gpmc_hwmod = {
        .name           = "gpmc",
        .class          = &am33xx_gpmc_hwmod_class,
        .clkdm_name     = "l3s_clkdm",
        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-        .mpu_irqs       = am33xx_gpmc_irqs,
        .main_clk       = "l3s_gclk",
        .prcm           = {
                .omap4  = {
@@ -1208,23 +960,10 @@ static struct omap_i2c_dev_attr i2c_dev_attr = {
 };
 /* i2c1 */
-static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
-        { .irq = 70 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
-        { .name = "tx", .dma_req = 0, },
-        { .name = "rx", .dma_req = 0, },
-        { .dma_req = -1 }
-};
 static struct omap_hwmod am33xx_i2c1_hwmod = {
        .name           = "i2c1",
        .class          = &i2c_class,
        .clkdm_name     = "l4_wkup_clkdm",
-        .mpu_irqs       = i2c1_mpu_irqs,
-        .sdma_reqs      = i2c1_edma_reqs,
        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
        .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
        .prcm           = {
@@ -1237,23 +976,10 @@ static struct omap_hwmod am33xx_i2c1_hwmod = {
 };
 /* i2c1 */
-static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
-        { .irq = 71 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
-        { .name = "tx", .dma_req = 0, },
-        { .name = "rx", .dma_req = 0, },
-        { .dma_req = -1 }
-};
 static struct omap_hwmod am33xx_i2c2_hwmod = {
        .name           = "i2c2",
        .class          = &i2c_class,
        .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = i2c2_mpu_irqs,
-        .sdma_reqs      = i2c2_edma_reqs,
        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
        .main_clk       = "dpll_per_m2_div4_ck",
        .prcm           = {
@@ -1266,23 +992,10 @@ static struct omap_hwmod am33xx_i2c2_hwmod = {
 };
 /* i2c3 */
-static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
-        { .name = "tx", .dma_req = 0, },
-        { .name = "rx", .dma_req = 0, },
-        { .dma_req = -1 }
-};
-static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
-        { .irq = 30 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_i2c3_hwmod = {
        .name           = "i2c3",
        .class          = &i2c_class,
        .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = i2c3_mpu_irqs,
-        .sdma_reqs      = i2c3_edma_reqs,
        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
        .main_clk       = "dpll_per_m2_div4_ck",
        .prcm           = {
@@ -1309,16 +1022,10 @@ static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
        .sysc           = &lcdc_sysc,
 };
-static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
-        { .irq = 36 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_lcdc_hwmod = {
        .name           = "lcdc",
        .class          = &am33xx_lcdc_hwmod_class,
        .clkdm_name     = "lcdc_clkdm",
-        .mpu_irqs       = am33xx_lcdc_irqs,
        .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
        .main_clk       = "lcd_gclk",
        .prcm           = {
@@ -1348,16 +1055,10 @@ static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
        .sysc   = &am33xx_mailbox_sysc,
 };
-static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
-        { .irq = 77 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_mailbox_hwmod = {
        .name           = "mailbox",
        .class          = &am33xx_mailbox_hwmod_class,
        .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_mailbox_irqs,
        .main_clk       = "l4ls_gclk",
        .prcm = {
                .omap4 = {
@@ -1384,24 +1085,10 @@ static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
 };
 /* mcasp0 */
-static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
-        { .name = "ax", .irq = 80 + OMAP_INTC_START, },
-        { .name = "ar", .irq = 81 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = {
-        { .name = "tx", .dma_req = 8, },
-        { .name = "rx", .dma_req = 9, },
-        { .dma_req = -1 }
-};
 static struct omap_hwmod am33xx_mcasp0_hwmod = {
        .name           = "mcasp0",
        .class          = &am33xx_mcasp_hwmod_class,
        .clkdm_name     = "l3s_clkdm",
-        .mpu_irqs       = am33xx_mcasp0_irqs,
-        .sdma_reqs      = am33xx_mcasp0_edma_reqs,
        .main_clk       = "mcasp0_fck",
        .prcm           = {
                .omap4  = {
@@ -1412,24 +1099,10 @@ static struct omap_hwmod am33xx_mcasp0_hwmod = {
 };
 /* mcasp1 */
-static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
-        { .name = "ax", .irq = 82 + OMAP_INTC_START, },
-        { .name = "ar", .irq = 83 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = {
-        { .name = "tx", .dma_req = 10, },
-        { .name = "rx", .dma_req = 11, },
-        { .dma_req = -1 }
-};
 static struct omap_hwmod am33xx_mcasp1_hwmod = {
        .name           = "mcasp1",
        .class          = &am33xx_mcasp_hwmod_class,
        .clkdm_name     = "l3s_clkdm",
-        .mpu_irqs       = am33xx_mcasp1_irqs,
-        .sdma_reqs      = am33xx_mcasp1_edma_reqs,
        .main_clk       = "mcasp1_fck",
        .prcm           = {
                .omap4  = {
@@ -1457,17 +1130,6 @@ static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
 };
 /* mmc0 */
-static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
-        { .irq = 64 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
-        { .name = "tx", .dma_req = 24, },
-        { .name = "rx", .dma_req = 25, },
-        { .dma_req = -1 }
-};
 static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
        .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 };
@@ -1476,8 +1138,6 @@ static struct omap_hwmod am33xx_mmc0_hwmod = {
        .name           = "mmc1",
        .class          = &am33xx_mmc_hwmod_class,
        .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_mmc0_irqs,
-        .sdma_reqs      = am33xx_mmc0_edma_reqs,
        .main_clk       = "mmc_clk",
        .prcm           = {
                .omap4  = {
@@ -1489,17 +1149,6 @@ static struct omap_hwmod am33xx_mmc0_hwmod = {
 };
 /* mmc1 */
-static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
-        { .irq = 28 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
-        { .name = "tx", .dma_req = 2, },
-        { .name = "rx", .dma_req = 3, },
-        { .dma_req = -1 }
-};
 static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
        .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 };
@@ -1508,8 +1157,6 @@ static struct omap_hwmod am33xx_mmc1_hwmod = {
        .name           = "mmc2",
        .class          = &am33xx_mmc_hwmod_class,
        .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_mmc1_irqs,
-        .sdma_reqs      = am33xx_mmc1_edma_reqs,
        .main_clk       = "mmc_clk",
        .prcm           = {
                .omap4  = {
@@ -1521,17 +1168,6 @@ static struct omap_hwmod am33xx_mmc1_hwmod = {
 };
 /* mmc2 */
-static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
-        { .irq = 29 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
-        { .name = "tx", .dma_req = 64, },
-        { .name = "rx", .dma_req = 65, },
-        { .dma_req = -1 }
-};
 static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
        .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 };
@@ -1539,8 +1175,6 @@ static struct omap_hwmod am33xx_mmc2_hwmod = {
        .name           = "mmc3",
        .class          = &am33xx_mmc_hwmod_class,
        .clkdm_name     = "l3s_clkdm",
-        .mpu_irqs       = am33xx_mmc2_irqs,
-        .sdma_reqs      = am33xx_mmc2_edma_reqs,
        .main_clk       = "mmc_clk",
        .prcm           = {
                .omap4  = {
@@ -1569,17 +1203,10 @@ static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
        .sysc           = &am33xx_rtc_sysc,
 };
-static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
-        { .name = "rtcint", .irq = 75 + OMAP_INTC_START, },
-        { .name = "rtcalarmint", .irq = 76 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_rtc_hwmod = {
        .name           = "rtc",
        .class          = &am33xx_rtc_hwmod_class,
        .clkdm_name     = "l4_rtc_clkdm",
-        .mpu_irqs       = am33xx_rtc_irqs,
        .main_clk       = "clk_32768_ck",
        .prcm           = {
                .omap4  = {
@@ -1608,19 +1235,6 @@ static struct omap_hwmod_class am33xx_spi_hwmod_class = {
 };
 /* spi0 */
-static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
-        { .irq = 65 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-static struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = {
-        { .name = "rx0", .dma_req = 17 },
-        { .name = "tx0", .dma_req = 16 },
-        { .name = "rx1", .dma_req = 19 },
-        { .name = "tx1", .dma_req = 18 },
-        { .dma_req = -1 }
-};
 static struct omap2_mcspi_dev_attr mcspi_attrib = {
        .num_chipselect = 2,
 };
@@ -1628,8 +1242,6 @@ static struct omap_hwmod am33xx_spi0_hwmod = {
        .name           = "spi0",
        .class          = &am33xx_spi_hwmod_class,
        .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_spi0_irqs,
-        .sdma_reqs      = am33xx_mcspi0_edma_reqs,
        .main_clk       = "dpll_per_m2_div4_ck",
        .prcm           = {
                .omap4  = {
@@ -1641,25 +1253,10 @@ static struct omap_hwmod am33xx_spi0_hwmod = {
 };
 /* spi1 */
-static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
-        { .irq = 125 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-static struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = {
-        { .name = "rx0", .dma_req = 43 },
-        { .name = "tx0", .dma_req = 42 },
-        { .name = "rx1", .dma_req = 45 },
-        { .name = "tx1", .dma_req = 44 },
-        { .dma_req = -1 }
-};
 static struct omap_hwmod am33xx_spi1_hwmod = {
        .name           = "spi1",
        .class          = &am33xx_spi_hwmod_class,
        .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_spi1_irqs,
-        .sdma_reqs      = am33xx_mcspi1_edma_reqs,
        .main_clk       = "dpll_per_m2_div4_ck",
        .prcm           = {
                .omap4  = {
@@ -1725,16 +1322,10 @@ static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
        .sysc           = &am33xx_timer1ms_sysc,
 };
-static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
-        { .irq = 67 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_timer1_hwmod = {
        .name           = "timer1",
        .class          = &am33xx_timer1ms_hwmod_class,
        .clkdm_name     = "l4_wkup_clkdm",
-        .mpu_irqs       = am33xx_timer1_irqs,
        .main_clk       = "timer1_fck",
        .prcm           = {
                .omap4  = {
@@ -1744,16 +1335,10 @@ static struct omap_hwmod am33xx_timer1_hwmod = {
        },
 };
-static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
-        { .irq = 68 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_timer2_hwmod = {
        .name           = "timer2",
        .class          = &am33xx_timer_hwmod_class,
        .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_timer2_irqs,
        .main_clk       = "timer2_fck",
        .prcm           = {
                .omap4  = {
@@ -1763,16 +1348,10 @@ static struct omap_hwmod am33xx_timer2_hwmod = {
        },
 };
-static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
-        { .irq = 69 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_timer3_hwmod = {
        .name           = "timer3",
        .class          = &am33xx_timer_hwmod_class,
        .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_timer3_irqs,
        .main_clk       = "timer3_fck",
        .prcm           = {
                .omap4  = {
@@ -1782,16 +1361,10 @@ static struct omap_hwmod am33xx_timer3_hwmod = {
        },
 };
-static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
-        { .irq = 92 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_timer4_hwmod = {
        .name           = "timer4",
        .class          = &am33xx_timer_hwmod_class,
        .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_timer4_irqs,
        .main_clk       = "timer4_fck",
        .prcm           = {
                .omap4  = {
@@ -1801,16 +1374,10 @@ static struct omap_hwmod am33xx_timer4_hwmod = {
        },
 };
-static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
-        { .irq = 93 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_timer5_hwmod = {
        .name           = "timer5",
        .class          = &am33xx_timer_hwmod_class,
        .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_timer5_irqs,
        .main_clk       = "timer5_fck",
        .prcm           = {
                .omap4  = {
@@ -1820,16 +1387,10 @@ static struct omap_hwmod am33xx_timer5_hwmod = {
        },
 };
-static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
-        { .irq = 94 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_timer6_hwmod = {
        .name           = "timer6",
        .class          = &am33xx_timer_hwmod_class,
        .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_timer6_irqs,
        .main_clk       = "timer6_fck",
        .prcm           = {
                .omap4  = {
@@ -1839,16 +1400,10 @@ static struct omap_hwmod am33xx_timer6_hwmod = {
        },
 };
-static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
-        { .irq = 95 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_timer7_hwmod = {
        .name           = "timer7",
        .class          = &am33xx_timer_hwmod_class,
        .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_timer7_irqs,
        .main_clk       = "timer7_fck",
        .prcm           = {
                .omap4  = {
@@ -1863,18 +1418,10 @@ static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
        .name           = "tpcc",
 };
-static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
-        { .name = "edma0", .irq = 12 + OMAP_INTC_START, },
-        { .name = "edma0_mperr", .irq = 13 + OMAP_INTC_START, },
-        { .name = "edma0_err", .irq = 14 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_tpcc_hwmod = {
        .name           = "tpcc",
        .class          = &am33xx_tpcc_hwmod_class,
        .clkdm_name     = "l3_clkdm",
-        .mpu_irqs       = am33xx_tpcc_irqs,
        .main_clk       = "l3_gclk",
        .prcm           = {
                .omap4  = {
@@ -1900,16 +1447,10 @@ static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
 };
 /* tptc0 */
-static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
-        { .irq = 112 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_tptc0_hwmod = {
        .name           = "tptc0",
        .class          = &am33xx_tptc_hwmod_class,
        .clkdm_name     = "l3_clkdm",
-        .mpu_irqs       = am33xx_tptc0_irqs,
        .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
        .main_clk       = "l3_gclk",
        .prcm           = {
@@ -1921,16 +1462,10 @@ static struct omap_hwmod am33xx_tptc0_hwmod = {
 };
 /* tptc1 */
-static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
-        { .irq = 113 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_tptc1_hwmod = {
        .name           = "tptc1",
        .class          = &am33xx_tptc_hwmod_class,
        .clkdm_name     = "l3_clkdm",
-        .mpu_irqs       = am33xx_tptc1_irqs,
        .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
        .main_clk       = "l3_gclk",
        .prcm           = {
@@ -1942,16 +1477,10 @@ static struct omap_hwmod am33xx_tptc1_hwmod = {
 };
 /* tptc2 */
-static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
-        { .irq = 114 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_tptc2_hwmod = {
        .name           = "tptc2",
        .class          = &am33xx_tptc_hwmod_class,
        .clkdm_name     = "l3_clkdm",
-        .mpu_irqs       = am33xx_tptc2_irqs,
        .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
        .main_clk       = "l3_gclk",
        .prcm           = {
@@ -1980,24 +1509,11 @@ static struct omap_hwmod_class uart_class = {
 };
 /* uart1 */
-static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
-        { .name = "tx", .dma_req = 26, },
-        { .name = "rx", .dma_req = 27, },
-        { .dma_req = -1 }
-};
-static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
-        { .irq = 72 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_uart1_hwmod = {
        .name           = "uart1",
        .class          = &uart_class,
        .clkdm_name     = "l4_wkup_clkdm",
-        .flags          = HWMOD_SWSUP_SIDLE_ACT,
+        .flags          = DEBUG_AM33XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
-        .mpu_irqs       = am33xx_uart1_irqs,
-        .sdma_reqs      = uart1_edma_reqs,
        .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
        .prcm           = {
                .omap4  = {
@@ -2007,25 +1523,11 @@ static struct omap_hwmod am33xx_uart1_hwmod = {
        },
 };
-/* uart2 */
-static struct omap_hwmod_dma_info uart2_edma_reqs[] = {
-        { .name = "tx", .dma_req = 28, },
-        { .name = "rx", .dma_req = 29, },
-        { .dma_req = -1 }
-};
-static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
-        { .irq = 73 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_uart2_hwmod = {
        .name           = "uart2",
        .class          = &uart_class,
        .clkdm_name     = "l4ls_clkdm",
        .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .mpu_irqs       = am33xx_uart2_irqs,
-        .sdma_reqs      = uart2_edma_reqs,
        .main_clk       = "dpll_per_m2_div4_ck",
        .prcm           = {
                .omap4  = {
@@ -2036,24 +1538,11 @@ static struct omap_hwmod am33xx_uart2_hwmod = {
 };
 /* uart3 */
-static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
-        { .name = "tx", .dma_req = 30, },
-        { .name = "rx", .dma_req = 31, },
-        { .dma_req = -1 }
-};
-static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
-        { .irq = 74 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_uart3_hwmod = {
        .name           = "uart3",
        .class          = &uart_class,
        .clkdm_name     = "l4ls_clkdm",
        .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .mpu_irqs       = am33xx_uart3_irqs,
-        .sdma_reqs      = uart3_edma_reqs,
        .main_clk       = "dpll_per_m2_div4_ck",
        .prcm           = {
                .omap4  = {
@@ -2063,18 +1552,11 @@ static struct omap_hwmod am33xx_uart3_hwmod = {
        },
 };
-static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
-        { .irq = 44 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_uart4_hwmod = {
        .name           = "uart4",
        .class          = &uart_class,
        .clkdm_name     = "l4ls_clkdm",
        .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .mpu_irqs       = am33xx_uart4_irqs,
-        .sdma_reqs      = uart1_edma_reqs,
        .main_clk       = "dpll_per_m2_div4_ck",
        .prcm           = {
                .omap4  = {
@@ -2084,18 +1566,11 @@ static struct omap_hwmod am33xx_uart4_hwmod = {
        },
 };
-static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
-        { .irq = 45 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_uart5_hwmod = {
        .name           = "uart5",
        .class          = &uart_class,
        .clkdm_name     = "l4ls_clkdm",
        .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .mpu_irqs       = am33xx_uart5_irqs,
-        .sdma_reqs      = uart1_edma_reqs,
        .main_clk       = "dpll_per_m2_div4_ck",
        .prcm           = {
                .omap4  = {
@@ -2105,18 +1580,11 @@ static struct omap_hwmod am33xx_uart5_hwmod = {
        },
 };
-static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
-        { .irq = 46 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_uart6_hwmod = {
        .name           = "uart6",
        .class          = &uart_class,
        .clkdm_name     = "l4ls_clkdm",
        .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .mpu_irqs       = am33xx_uart6_irqs,
-        .sdma_reqs      = uart1_edma_reqs,
        .main_clk       = "dpll_per_m2_div4_ck",
        .prcm           = {
                .omap4  = {
@@ -2180,18 +1648,10 @@ static struct omap_hwmod_class am33xx_usbotg_class = {
        .sysc           = &am33xx_usbhsotg_sysc,
 };
-static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
-        { .name = "usbss-irq", .irq = 17 + OMAP_INTC_START, },
-        { .name = "musb0-irq", .irq = 18 + OMAP_INTC_START, },
-        { .name = "musb1-irq", .irq = 19 + OMAP_INTC_START, },
-        { .irq = -1, },
-};
 static struct omap_hwmod am33xx_usbss_hwmod = {
        .name           = "usb_otg_hs",
        .class          = &am33xx_usbotg_class,
        .clkdm_name     = "l3s_clkdm",
-        .mpu_irqs       = am33xx_usbss_mpu_irqs,
        .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
        .main_clk       = "usbotg_fck",
        .prcm           = {
@@ -2207,14 +1667,6 @@ static struct omap_hwmod am33xx_usbss_hwmod = {
 * Interfaces
 */
-/* l4 fw -> emif fw */
-static struct omap_hwmod_ocp_if am33xx_l4_fw__emif_fw = {
-        .master         = &am33xx_l4_fw_hwmod,
-        .slave          = &am33xx_emif_fw_hwmod,
-        .clk            = "l4fw_gclk",
-        .user           = OCP_USER_MPU,
-};
 static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
        {
                .pa_start       = 0x4c000000,
@@ -2272,14 +1724,6 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-/* l3 s -> l4 fw */
-static struct omap_hwmod_ocp_if am33xx_l3_s__l4_fw = {
-        .master         = &am33xx_l3_s_hwmod,
-        .slave          = &am33xx_l4_fw_hwmod,
-        .clk            = "l3s_gclk",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
 /* l3 main -> l3 instr */
 static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
        .master         = &am33xx_l3_main_hwmod,
@@ -2329,261 +1773,114 @@ static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
 };
 /* l4 wkup -> wkup m3 */
-static struct omap_hwmod_addr_space am33xx_wkup_m3_addrs[] = {
-        {
-                .name           = "umem",
-                .pa_start       = 0x44d00000,
-                .pa_end         = 0x44d00000 + SZ_16K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        {
-                .name           = "dmem",
-                .pa_start       = 0x44d80000,
-                .pa_end         = 0x44d80000 + SZ_8K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
        .master         = &am33xx_l4_wkup_hwmod,
        .slave          = &am33xx_wkup_m3_hwmod,
        .clk            = "dpll_core_m4_div2_ck",
-        .addr           = am33xx_wkup_m3_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 /* l4 hs -> pru-icss */
-static struct omap_hwmod_addr_space am33xx_pruss_addrs[] = {
-        {
-                .pa_start       = 0x4a300000,
-                .pa_end         = 0x4a300000 + SZ_512K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
        .master         = &am33xx_l4_hs_hwmod,
        .slave          = &am33xx_pruss_hwmod,
        .clk            = "dpll_core_m4_ck",
-        .addr           = am33xx_pruss_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 /* l3 main -> gfx */
-static struct omap_hwmod_addr_space am33xx_gfx_addrs[] = {
-        {
-                .pa_start       = 0x56000000,
-                .pa_end         = 0x56000000 + SZ_16M - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
        .master         = &am33xx_l3_main_hwmod,
        .slave          = &am33xx_gfx_hwmod,
        .clk            = "dpll_core_m4_ck",
-        .addr           = am33xx_gfx_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 /* l4 wkup -> smartreflex0 */
-static struct omap_hwmod_addr_space am33xx_smartreflex0_addrs[] = {
-        {
-                .pa_start       = 0x44e37000,
-                .pa_end         = 0x44e37000 + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
        .master         = &am33xx_l4_wkup_hwmod,
        .slave          = &am33xx_smartreflex0_hwmod,
        .clk            = "dpll_core_m4_div2_ck",
-        .addr           = am33xx_smartreflex0_addrs,
        .user           = OCP_USER_MPU,
 };
 /* l4 wkup -> smartreflex1 */
-static struct omap_hwmod_addr_space am33xx_smartreflex1_addrs[] = {
-        {
-                .pa_start       = 0x44e39000,
-                .pa_end         = 0x44e39000 + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
        .master         = &am33xx_l4_wkup_hwmod,
        .slave          = &am33xx_smartreflex1_hwmod,
        .clk            = "dpll_core_m4_div2_ck",
-        .addr           = am33xx_smartreflex1_addrs,
        .user           = OCP_USER_MPU,
 };
 /* l4 wkup -> control */
-static struct omap_hwmod_addr_space am33xx_control_addrs[] = {
-        {
-                .pa_start       = 0x44e10000,
-                .pa_end         = 0x44e10000 + SZ_8K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
        .master         = &am33xx_l4_wkup_hwmod,
        .slave          = &am33xx_control_hwmod,
        .clk            = "dpll_core_m4_div2_ck",
-        .addr           = am33xx_control_addrs,
        .user           = OCP_USER_MPU,
 };
 /* l4 wkup -> rtc */
-static struct omap_hwmod_addr_space am33xx_rtc_addrs[] = {
-        {
-                .pa_start       = 0x44e3e000,
-                .pa_end         = 0x44e3e000 + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
        .master         = &am33xx_l4_wkup_hwmod,
        .slave          = &am33xx_rtc_hwmod,
        .clk            = "clkdiv32k_ick",
-        .addr           = am33xx_rtc_addrs,
        .user           = OCP_USER_MPU,
 };
 /* l4 per/ls -> DCAN0 */
-static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = {
-        {
-                .pa_start       = 0x481CC000,
-                .pa_end         = 0x481CC000 + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
        .master         = &am33xx_l4_ls_hwmod,
        .slave          = &am33xx_dcan0_hwmod,
        .clk            = "l4ls_gclk",
-        .addr           = am33xx_dcan0_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 /* l4 per/ls -> DCAN1 */
-static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = {
-        {
-                .pa_start       = 0x481D0000,
-                .pa_end         = 0x481D0000 + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
        .master         = &am33xx_l4_ls_hwmod,
        .slave          = &am33xx_dcan1_hwmod,
        .clk            = "l4ls_gclk",
-        .addr           = am33xx_dcan1_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 /* l4 per/ls -> GPIO2 */
-static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
-        {
-                .pa_start       = 0x4804C000,
-                .pa_end         = 0x4804C000 + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
        .master         = &am33xx_l4_ls_hwmod,
        .slave          = &am33xx_gpio1_hwmod,
        .clk            = "l4ls_gclk",
-        .addr           = am33xx_gpio1_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 /* l4 per/ls -> gpio3 */
-static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
-        {
-                .pa_start       = 0x481AC000,
-                .pa_end         = 0x481AC000 + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
        .master         = &am33xx_l4_ls_hwmod,
        .slave          = &am33xx_gpio2_hwmod,
        .clk            = "l4ls_gclk",
-        .addr           = am33xx_gpio2_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 /* l4 per/ls -> gpio4 */
-static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
-        {
-                .pa_start       = 0x481AE000,
-                .pa_end         = 0x481AE000 + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
        .master         = &am33xx_l4_ls_hwmod,
        .slave          = &am33xx_gpio3_hwmod,
        .clk            = "l4ls_gclk",
-        .addr           = am33xx_gpio3_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 /* L4 WKUP -> I2C1 */
-static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
-        {
-                .pa_start       = 0x44E0B000,
-                .pa_end         = 0x44E0B000 + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
        .master         = &am33xx_l4_wkup_hwmod,
        .slave          = &am33xx_i2c1_hwmod,
        .clk            = "dpll_core_m4_div2_ck",
-        .addr           = am33xx_i2c1_addr_space,
        .user           = OCP_USER_MPU,
 };
 /* L4 WKUP -> GPIO1 */
-static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
-        {
-                .pa_start       = 0x44E07000,
-                .pa_end         = 0x44E07000 + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
        .master         = &am33xx_l4_wkup_hwmod,
        .slave          = &am33xx_gpio0_hwmod,
        .clk            = "dpll_core_m4_div2_ck",
-        .addr           = am33xx_gpio0_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
@@ -2605,41 +1902,16 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
        .user           = OCP_USER_MPU,
 };
-static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
-        /* cpsw ss */
-        {
-                .pa_start       = 0x4a100000,
-                .pa_end         = 0x4a100000 + SZ_2K - 1,
-        },
-        /* cpsw wr */
-        {
-                .pa_start       = 0x4a101200,
-                .pa_end         = 0x4a101200 + SZ_256 - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
        .master         = &am33xx_l4_hs_hwmod,
        .slave          = &am33xx_cpgmac0_hwmod,
        .clk            = "cpsw_125mhz_gclk",
-        .addr           = am33xx_cpgmac0_addr_space,
        .user           = OCP_USER_MPU,
 };
-static struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
-        {
-                .pa_start       = 0x4A101000,
-                .pa_end         = 0x4A101000 + SZ_256 - 1,
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
        .master         = &am33xx_cpgmac0_hwmod,
        .slave          = &am33xx_mdio_hwmod,
-        .addr           = am33xx_mdio_addr_space,
        .user           = OCP_USER_MPU,
 };
@@ -2677,51 +1949,24 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = {
        .user           = OCP_USER_MPU,
 };
-static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
-        {
-                .pa_start       = 0x48300100,
-                .pa_end         = 0x48300100 + SZ_128 - 1,
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = {
        .master         = &am33xx_epwmss0_hwmod,
        .slave          = &am33xx_ecap0_hwmod,
        .clk            = "l4ls_gclk",
-        .addr           = am33xx_ecap0_addr_space,
        .user           = OCP_USER_MPU,
 };
-static struct omap_hwmod_addr_space am33xx_eqep0_addr_space[] = {
-        {
-                .pa_start       = 0x48300180,
-                .pa_end         = 0x48300180 + SZ_128 - 1,
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = {
        .master         = &am33xx_epwmss0_hwmod,
        .slave          = &am33xx_eqep0_hwmod,
        .clk            = "l4ls_gclk",
-        .addr           = am33xx_eqep0_addr_space,
        .user           = OCP_USER_MPU,
 };
-static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
-        {
-                .pa_start       = 0x48300200,
-                .pa_end         = 0x48300200 + SZ_128 - 1,
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = {
        .master         = &am33xx_epwmss0_hwmod,
        .slave          = &am33xx_ehrpwm0_hwmod,
        .clk            = "l4ls_gclk",
-        .addr           = am33xx_ehrpwm0_addr_space,
        .user           = OCP_USER_MPU,
 };
@@ -2743,51 +1988,24 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = {
        .user           = OCP_USER_MPU,
 };
-static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
-        {
-                .pa_start       = 0x48302100,
-                .pa_end         = 0x48302100 + SZ_128 - 1,
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = {
        .master         = &am33xx_epwmss1_hwmod,
        .slave          = &am33xx_ecap1_hwmod,
        .clk            = "l4ls_gclk",
-        .addr           = am33xx_ecap1_addr_space,
        .user           = OCP_USER_MPU,
 };
-static struct omap_hwmod_addr_space am33xx_eqep1_addr_space[] = {
-        {
-                .pa_start       = 0x48302180,
-                .pa_end         = 0x48302180 + SZ_128 - 1,
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = {
        .master         = &am33xx_epwmss1_hwmod,
        .slave          = &am33xx_eqep1_hwmod,
        .clk            = "l4ls_gclk",
-        .addr           = am33xx_eqep1_addr_space,
        .user           = OCP_USER_MPU,
 };
-static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
-        {
-                .pa_start       = 0x48302200,
-                .pa_end         = 0x48302200 + SZ_128 - 1,
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = {
        .master         = &am33xx_epwmss1_hwmod,
        .slave          = &am33xx_ehrpwm1_hwmod,
        .clk            = "l4ls_gclk",
-        .addr           = am33xx_ehrpwm1_addr_space,
        .user           = OCP_USER_MPU,
 };
@@ -2808,51 +2026,24 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = {
        .user           = OCP_USER_MPU,
 };
-static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
-        {
-                .pa_start       = 0x48304100,
-                .pa_end         = 0x48304100 + SZ_128 - 1,
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = {
        .master         = &am33xx_epwmss2_hwmod,
        .slave          = &am33xx_ecap2_hwmod,
        .clk            = "l4ls_gclk",
-        .addr           = am33xx_ecap2_addr_space,
        .user           = OCP_USER_MPU,
 };
-static struct omap_hwmod_addr_space am33xx_eqep2_addr_space[] = {
-        {
-                .pa_start       = 0x48304180,
-                .pa_end         = 0x48304180 + SZ_128 - 1,
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = {
        .master         = &am33xx_epwmss2_hwmod,
        .slave          = &am33xx_eqep2_hwmod,
        .clk            = "l4ls_gclk",
-        .addr           = am33xx_eqep2_addr_space,
        .user           = OCP_USER_MPU,
 };
-static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
-        {
-                .pa_start       = 0x48304200,
-                .pa_end         = 0x48304200 + SZ_128 - 1,
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = {
        .master         = &am33xx_epwmss2_hwmod,
        .slave          = &am33xx_ehrpwm2_hwmod,
        .clk            = "l4ls_gclk",
-        .addr           = am33xx_ehrpwm2_addr_space,
        .user           = OCP_USER_MPU,
 };
@@ -2875,37 +2066,17 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
 };
 /* i2c2 */
-static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
-        {
-                .pa_start       = 0x4802A000,
-                .pa_end         = 0x4802A000 + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
        .master         = &am33xx_l4_ls_hwmod,
        .slave          = &am33xx_i2c2_hwmod,
        .clk            = "l4ls_gclk",
-        .addr           = am33xx_i2c2_addr_space,
        .user           = OCP_USER_MPU,
 };
-static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
-        {
-                .pa_start       = 0x4819C000,
-                .pa_end         = 0x4819C000 + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
        .master         = &am33xx_l4_ls_hwmod,
        .slave          = &am33xx_i2c3_hwmod,
        .clk            = "l4ls_gclk",
-        .addr           = am33xx_i2c3_addr_space,
        .user           = OCP_USER_MPU,
 };
@@ -2945,20 +2116,10 @@ static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
 };
 /* l4 ls -> spinlock */
-static struct omap_hwmod_addr_space am33xx_spinlock_addrs[] = {
-        {
-                .pa_start       = 0x480Ca000,
-                .pa_end         = 0x480Ca000 + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
        .master         = &am33xx_l4_ls_hwmod,
        .slave          = &am33xx_spinlock_hwmod,
        .clk            = "l4ls_gclk",
-        .addr           = am33xx_spinlock_addrs,
        .user           = OCP_USER_MPU,
 };
@@ -2980,24 +2141,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
        .user           = OCP_USER_MPU,
 };
-/* l3 s -> mcasp0 data */
-static struct omap_hwmod_addr_space am33xx_mcasp0_data_addr_space[] = {
-        {
-                .pa_start       = 0x46000000,
-                .pa_end         = 0x46000000 + SZ_4M - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp0_data = {
-        .master         = &am33xx_l3_s_hwmod,
-        .slave          = &am33xx_mcasp0_hwmod,
-        .clk            = "l3s_gclk",
-        .addr           = am33xx_mcasp0_data_addr_space,
-        .user           = OCP_USER_SDMA,
-};
 /* l4 ls -> mcasp1 */
 static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
        {
@@ -3016,24 +2159,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
        .user           = OCP_USER_MPU,
 };
-/* l3 s -> mcasp1 data */
-static struct omap_hwmod_addr_space am33xx_mcasp1_data_addr_space[] = {
-        {
-                .pa_start       = 0x46400000,
-                .pa_end         = 0x46400000 + SZ_4M - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp1_data = {
-        .master         = &am33xx_l3_s_hwmod,
-        .slave          = &am33xx_mcasp1_hwmod,
-        .clk            = "l3s_gclk",
-        .addr           = am33xx_mcasp1_data_addr_space,
-        .user           = OCP_USER_SDMA,
-};
 /* l4 ls -> mmc0 */
 static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
        {
@@ -3089,182 +2214,82 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
 };
 /* l4 ls -> mcspi0 */
-static struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
-        {
-                .pa_start       = 0x48030000,
-                .pa_end         = 0x48030000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
        .master         = &am33xx_l4_ls_hwmod,
        .slave          = &am33xx_spi0_hwmod,
        .clk            = "l4ls_gclk",
-        .addr           = am33xx_mcspi0_addr_space,
        .user           = OCP_USER_MPU,
 };
 /* l4 ls -> mcspi1 */
-static struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
-        {
-                .pa_start       = 0x481A0000,
-                .pa_end         = 0x481A0000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
        .master         = &am33xx_l4_ls_hwmod,
        .slave          = &am33xx_spi1_hwmod,
        .clk            = "l4ls_gclk",
-        .addr           = am33xx_mcspi1_addr_space,
        .user           = OCP_USER_MPU,
 };
 /* l4 wkup -> timer1 */
-static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
-        {
-                .pa_start       = 0x44E31000,
-                .pa_end         = 0x44E31000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
        .master         = &am33xx_l4_wkup_hwmod,
        .slave          = &am33xx_timer1_hwmod,
        .clk            = "dpll_core_m4_div2_ck",
-        .addr           = am33xx_timer1_addr_space,
        .user           = OCP_USER_MPU,
 };
 /* l4 per -> timer2 */
-static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
-        {
-                .pa_start       = 0x48040000,
-                .pa_end         = 0x48040000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
        .master         = &am33xx_l4_ls_hwmod,
        .slave          = &am33xx_timer2_hwmod,
        .clk            = "l4ls_gclk",
-        .addr           = am33xx_timer2_addr_space,
        .user           = OCP_USER_MPU,
 };
 /* l4 per -> timer3 */
-static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
-        {
-                .pa_start       = 0x48042000,
-                .pa_end         = 0x48042000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
        .master         = &am33xx_l4_ls_hwmod,
        .slave          = &am33xx_timer3_hwmod,
        .clk            = "l4ls_gclk",
-        .addr           = am33xx_timer3_addr_space,
        .user           = OCP_USER_MPU,
 };
 /* l4 per -> timer4 */
-static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
-        {
-                .pa_start       = 0x48044000,
-                .pa_end         = 0x48044000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
        .master         = &am33xx_l4_ls_hwmod,
        .slave          = &am33xx_timer4_hwmod,
        .clk            = "l4ls_gclk",
-        .addr           = am33xx_timer4_addr_space,
        .user           = OCP_USER_MPU,
 };
 /* l4 per -> timer5 */
-static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
-        {
-                .pa_start       = 0x48046000,
-                .pa_end         = 0x48046000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
        .master         = &am33xx_l4_ls_hwmod,
        .slave          = &am33xx_timer5_hwmod,
        .clk            = "l4ls_gclk",
-        .addr           = am33xx_timer5_addr_space,
        .user           = OCP_USER_MPU,
 };
 /* l4 per -> timer6 */
-static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
-        {
-                .pa_start       = 0x48048000,
-                .pa_end         = 0x48048000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
        .master         = &am33xx_l4_ls_hwmod,
        .slave          = &am33xx_timer6_hwmod,
        .clk            = "l4ls_gclk",
-        .addr           = am33xx_timer6_addr_space,
        .user           = OCP_USER_MPU,
 };
 /* l4 per -> timer7 */
-static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
-        {
-                .pa_start       = 0x4804A000,
-                .pa_end         = 0x4804A000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
        .master         = &am33xx_l4_ls_hwmod,
        .slave          = &am33xx_timer7_hwmod,
        .clk            = "l4ls_gclk",
-        .addr           = am33xx_timer7_addr_space,
        .user           = OCP_USER_MPU,
 };
 /* l3 main -> tpcc */
-static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
-        {
-                .pa_start       = 0x49000000,
-                .pa_end         = 0x49000000 + SZ_32K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
        .master         = &am33xx_l3_main_hwmod,
        .slave          = &am33xx_tpcc_hwmod,
        .clk            = "l3_gclk",
-        .addr           = am33xx_tpcc_addr_space,
        .user           = OCP_USER_MPU,
 };
@@ -3323,160 +2348,67 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
 };
 /* l4 wkup -> uart1 */
-static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
-        {
-                .pa_start       = 0x44E09000,
-                .pa_end         = 0x44E09000 + SZ_8K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
        .master         = &am33xx_l4_wkup_hwmod,
        .slave          = &am33xx_uart1_hwmod,
        .clk            = "dpll_core_m4_div2_ck",
-        .addr           = am33xx_uart1_addr_space,
        .user           = OCP_USER_MPU,
 };
 /* l4 ls -> uart2 */
-static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
-        {
-                .pa_start       = 0x48022000,
-                .pa_end         = 0x48022000 + SZ_8K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
        .master         = &am33xx_l4_ls_hwmod,
        .slave          = &am33xx_uart2_hwmod,
        .clk            = "l4ls_gclk",
-        .addr           = am33xx_uart2_addr_space,
        .user           = OCP_USER_MPU,
 };
 /* l4 ls -> uart3 */
-static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
-        {
-                .pa_start       = 0x48024000,
-                .pa_end         = 0x48024000 + SZ_8K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
        .master         = &am33xx_l4_ls_hwmod,
        .slave          = &am33xx_uart3_hwmod,
        .clk            = "l4ls_gclk",
-        .addr           = am33xx_uart3_addr_space,
        .user           = OCP_USER_MPU,
 };
 /* l4 ls -> uart4 */
-static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
-        {
-                .pa_start       = 0x481A6000,
-                .pa_end         = 0x481A6000 + SZ_8K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
        .master         = &am33xx_l4_ls_hwmod,
        .slave          = &am33xx_uart4_hwmod,
        .clk            = "l4ls_gclk",
-        .addr           = am33xx_uart4_addr_space,
        .user           = OCP_USER_MPU,
 };
 /* l4 ls -> uart5 */
-static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
-        {
-                .pa_start       = 0x481A8000,
-                .pa_end         = 0x481A8000 + SZ_8K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
        .master         = &am33xx_l4_ls_hwmod,
        .slave          = &am33xx_uart5_hwmod,
        .clk            = "l4ls_gclk",
-        .addr           = am33xx_uart5_addr_space,
        .user           = OCP_USER_MPU,
 };
 /* l4 ls -> uart6 */
-static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
-        {
-                .pa_start       = 0x481aa000,
-                .pa_end         = 0x481aa000 + SZ_8K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
        .master         = &am33xx_l4_ls_hwmod,
        .slave          = &am33xx_uart6_hwmod,
        .clk            = "l4ls_gclk",
-        .addr           = am33xx_uart6_addr_space,
        .user           = OCP_USER_MPU,
 };
 /* l4 wkup -> wd_timer1 */
-static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
-        {
-                .pa_start       = 0x44e35000,
-                .pa_end         = 0x44e35000 + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
        .master         = &am33xx_l4_wkup_hwmod,
        .slave          = &am33xx_wd_timer1_hwmod,
        .clk            = "dpll_core_m4_div2_ck",
-        .addr           = am33xx_wd_timer1_addrs,
        .user           = OCP_USER_MPU,
 };
 /* usbss */
 /* l3 s -> USBSS interface */
-static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
-        {
-                .name           = "usbss",
-                .pa_start       = 0x47400000,
-                .pa_end         = 0x47400000 + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        {
-                .name           = "musb0",
-                .pa_start       = 0x47401000,
-                .pa_end         = 0x47401000 + SZ_2K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        {
-                .name           = "musb1",
-                .pa_start       = 0x47401800,
-                .pa_end         = 0x47401800 + SZ_2K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
        .master         = &am33xx_l3_s_hwmod,
        .slave          = &am33xx_usbss_hwmod,
        .clk            = "l3s_gclk",
-        .addr           = am33xx_usbss_addr_space,
        .user           = OCP_USER_MPU,
        .flags          = OCPIF_SWSUP_IDLE,
 };
@@ -3525,13 +2457,11 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
 };
 static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
-        &am33xx_l4_fw__emif_fw,
        &am33xx_l3_main__emif,
        &am33xx_mpu__l3_main,
        &am33xx_mpu__prcm,
        &am33xx_l3_s__l4_ls,
        &am33xx_l3_s__l4_wkup,
-        &am33xx_l3_s__l4_fw,
        &am33xx_l3_main__l4_hs,
        &am33xx_l3_main__l3_s,
        &am33xx_l3_main__l3_instr,
@@ -3561,9 +2491,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
        &am33xx_l4_per__i2c3,
        &am33xx_l4_per__mailbox,
        &am33xx_l4_ls__mcasp0,
-        &am33xx_l3_s__mcasp0_data,
        &am33xx_l4_ls__mcasp1,
-        &am33xx_l3_s__mcasp1_data,
        &am33xx_l4_ls__mmc0,
        &am33xx_l4_ls__mmc1,
        &am33xx_l3_s__mmc2,
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 31c7126eb3bb..0c3a427da544 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -25,6 +25,7 @@
 #include <linux/platform_data/asoc-ti-mcbsp.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <linux/platform_data/iommu-omap.h>
+#include <linux/platform_data/mailbox-omap.h>
 #include <plat/dmtimer.h>
 #include "am35xx.h"
@@ -35,7 +36,6 @@
 #include "prm-regbits-34xx.h"
 #include "cm-regbits-34xx.h"
-#include "dma.h"
 #include "i2c.h"
 #include "mmc.h"
 #include "wd_timer.h"
@@ -490,7 +490,7 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = {
        .mpu_irqs       = omap2_uart1_mpu_irqs,
        .sdma_reqs      = omap2_uart1_sdma_reqs,
        .main_clk       = "uart1_fck",
-        .flags          = HWMOD_SWSUP_SIDLE_ACT,
+        .flags          = DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
        .prcm           = {
                .omap2 = {
                        .module_offs = CORE_MOD,
@@ -509,7 +509,7 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = {
        .mpu_irqs       = omap2_uart2_mpu_irqs,
        .sdma_reqs      = omap2_uart2_sdma_reqs,
        .main_clk       = "uart2_fck",
-        .flags          = HWMOD_SWSUP_SIDLE_ACT,
+        .flags          = DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
        .prcm           = {
                .omap2 = {
                        .module_offs = CORE_MOD,
@@ -528,7 +528,8 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
        .mpu_irqs       = omap2_uart3_mpu_irqs,
        .sdma_reqs      = omap2_uart3_sdma_reqs,
        .main_clk       = "uart3_fck",
-        .flags          = HWMOD_SWSUP_SIDLE_ACT,
+        .flags          = DEBUG_OMAP3UART3_FLAGS | DEBUG_TI81XXUART3_FLAGS |
+                                HWMOD_SWSUP_SIDLE_ACT,
        .prcm           = {
                .omap2 = {
                        .module_offs = OMAP3430_PER_MOD,
@@ -548,8 +549,8 @@ static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
 };
 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
-        { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
+        { .name = "rx", .dma_req = 82, },
-        { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
+        { .name = "tx", .dma_req = 81, },
        { .dma_req = -1 }
 };
@@ -558,7 +559,7 @@ static struct omap_hwmod omap36xx_uart4_hwmod = {
        .mpu_irqs       = uart4_mpu_irqs,
        .sdma_reqs      = uart4_sdma_reqs,
        .main_clk       = "uart4_fck",
-        .flags          = HWMOD_SWSUP_SIDLE_ACT,
+        .flags          = DEBUG_OMAP3UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
        .prcm           = {
                .omap2 = {
                        .module_offs = OMAP3430_PER_MOD,
@@ -577,8 +578,8 @@ static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
 };
 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
-        { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, },
+        { .name = "rx", .dma_req = 55, },
-        { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
+        { .name = "tx", .dma_req = 54, },
        { .dma_req = -1 }
 };
@@ -857,8 +858,8 @@ static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
 };
 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
-        { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
+        { .name = "tx", .dma_req = 25 },
-        { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
+        { .name = "rx", .dma_req = 26 },
        { .dma_req = -1 }
 };
@@ -1505,6 +1506,17 @@ static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
        .sysc = &omap3xxx_mailbox_sysc,
 };
+static struct omap_mbox_dev_info omap3xxx_mailbox_info[] = {
+        { .name = "dsp", .tx_id = 0, .rx_id = 1 },
+};
+static struct omap_mbox_pdata omap3xxx_mailbox_attrs = {
+        .num_users      = 2,
+        .num_fifos      = 2,
+        .info_cnt       = ARRAY_SIZE(omap3xxx_mailbox_info),
+        .info           = omap3xxx_mailbox_info,
+};
 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
        { .irq = 26 + OMAP_INTC_START, },
        { .irq = -1 },
@@ -1524,6 +1536,7 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
                },
        },
+        .dev_attr       = &omap3xxx_mailbox_attrs,
 };
 /*
@@ -3581,7 +3594,7 @@ static struct omap_hwmod_irq_info omap3_sham_mpu_irqs[] = {
 };
 static struct omap_hwmod_dma_info omap3_sham_sdma_reqs[] = {
-        { .name = "rx", .dma_req = OMAP34XX_DMA_SHA1MD5_RX, },
+        { .name = "rx", .dma_req = 69, },
        { .dma_req = -1 }
 };
@@ -3642,8 +3655,8 @@ static struct omap_hwmod_class omap3xxx_aes_class = {
 };
 static struct omap_hwmod_dma_info omap3_aes_sdma_reqs[] = {
-        { .name = "tx", .dma_req = OMAP34XX_DMA_AES2_TX, },
+        { .name = "tx", .dma_req = 65, },
-        { .name = "rx", .dma_req = OMAP34XX_DMA_AES2_RX, },
+        { .name = "rx", .dma_req = 66, },
        { .dma_req = -1 }
 };
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 848b6dc67590..9c3b504477d7 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -12,6 +12,8 @@
 * with the public linux-omap@vger.kernel.org mailing list and the
 * authors above to ensure that the autogeneration scripts are kept
 * up-to-date with the file contents.
+ * Note that this file is currently not in sync with autogeneration scripts.
+ * The above note to be removed, once it is synced up.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
@@ -21,7 +23,6 @@
 #include <linux/io.h>
 #include <linux/platform_data/gpio-omap.h>
 #include <linux/power/smartreflex.h>
-#include <linux/platform_data/omap_ocp2scp.h>
 #include <linux/i2c-omap.h>
 #include <linux/omap-dma.h>
@@ -52,27 +53,6 @@
 */
 /*
- * 'c2c_target_fw' class
- * instance(s): c2c_target_fw
- */
-static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
-        .name   = "c2c_target_fw",
-};
-/* c2c_target_fw */
-static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
-        .name           = "c2c_target_fw",
-        .class          = &omap44xx_c2c_target_fw_hwmod_class,
-        .clkdm_name     = "d2d_clkdm",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
-                        .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
-                },
-        },
-};
-/*
 * 'dmm' class
 * instance(s): dmm
 */
@@ -81,16 +61,10 @@ static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
 };
 /* dmm */
-static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
-        { .irq = 113 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod omap44xx_dmm_hwmod = {
        .name           = "dmm",
        .class          = &omap44xx_dmm_hwmod_class,
        .clkdm_name     = "l3_emif_clkdm",
-        .mpu_irqs       = omap44xx_dmm_irqs,
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
@@ -100,27 +74,6 @@ static struct omap_hwmod omap44xx_dmm_hwmod = {
 };
 /*
- * 'emif_fw' class
- * instance(s): emif_fw
- */
-static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
-        .name   = "emif_fw",
-};
-/* emif_fw */
-static struct omap_hwmod omap44xx_emif_fw_hwmod = {
-        .name           = "emif_fw",
-        .class          = &omap44xx_emif_fw_hwmod_class,
-        .clkdm_name     = "l3_emif_clkdm",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
-                        .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
-                },
-        },
-};
-/*
 * 'l3' class
 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 */
@@ -143,17 +96,10 @@ static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 };
 /* l3_main_1 */
-static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
-        { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
-        { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
        .name           = "l3_main_1",
        .class          = &omap44xx_l3_hwmod_class,
        .clkdm_name     = "l3_1_clkdm",
-        .mpu_irqs       = omap44xx_l3_main_1_irqs,
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
@@ -326,29 +272,10 @@ static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 };
 /* aess */
-static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
-        { .irq = 99 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
-        { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
-        { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
-        { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
-        { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
-        { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
-        { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
-        { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
-        { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
 static struct omap_hwmod omap44xx_aess_hwmod = {
        .name           = "aess",
        .class          = &omap44xx_aess_hwmod_class,
        .clkdm_name     = "abe_clkdm",
-        .mpu_irqs       = omap44xx_aess_irqs,
-        .sdma_reqs      = omap44xx_aess_sdma_reqs,
        .main_clk       = "aess_fclk",
        .prcm = {
                .omap4 = {
@@ -371,22 +298,10 @@ static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
 };
 /* c2c */
-static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
-        { .irq = 88 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
-        { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
 static struct omap_hwmod omap44xx_c2c_hwmod = {
        .name           = "c2c",
        .class          = &omap44xx_c2c_hwmod_class,
        .clkdm_name     = "d2d_clkdm",
-        .mpu_irqs       = omap44xx_c2c_irqs,
-        .sdma_reqs      = omap44xx_c2c_sdma_reqs,
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
@@ -449,16 +364,10 @@ static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 };
 /* ctrl_module_core */
-static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
-        { .irq = 8 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
        .name           = "ctrl_module_core",
        .class          = &omap44xx_ctrl_module_hwmod_class,
        .clkdm_name     = "l4_cfg_clkdm",
-        .mpu_irqs       = omap44xx_ctrl_module_core_irqs,
        .prcm = {
                .omap4 = {
                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
@@ -601,22 +510,10 @@ static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 };
 /* dmic */
-static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
-        { .irq = 114 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
-        { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
 static struct omap_hwmod omap44xx_dmic_hwmod = {
        .name           = "dmic",
        .class          = &omap44xx_dmic_hwmod_class,
        .clkdm_name     = "abe_clkdm",
-        .mpu_irqs       = omap44xx_dmic_irqs,
-        .sdma_reqs      = omap44xx_dmic_sdma_reqs,
        .main_clk       = "func_dmic_abe_gfclk",
        .prcm = {
                .omap4 = {
@@ -637,11 +534,6 @@ static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 };
 /* dsp */
-static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
-        { .irq = 28 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
        { .name = "dsp", .rst_shift = 0 },
 };
@@ -650,7 +542,6 @@ static struct omap_hwmod omap44xx_dsp_hwmod = {
        .name           = "dsp",
        .class          = &omap44xx_dsp_hwmod_class,
        .clkdm_name     = "tesla_clkdm",
-        .mpu_irqs       = omap44xx_dsp_irqs,
        .rst_lines      = omap44xx_dsp_resets,
        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
        .main_clk       = "dpll_iva_m4x2_ck",
@@ -992,16 +883,10 @@ static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 };
 /* elm */
-static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
-        { .irq = 4 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod omap44xx_elm_hwmod = {
        .name           = "elm",
        .class          = &omap44xx_elm_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
-        .mpu_irqs       = omap44xx_elm_irqs,
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
@@ -1025,17 +910,11 @@ static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
 };
 /* emif1 */
-static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
-        { .irq = 110 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod omap44xx_emif1_hwmod = {
        .name           = "emif1",
        .class          = &omap44xx_emif_hwmod_class,
        .clkdm_name     = "l3_emif_clkdm",
        .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
-        .mpu_irqs       = omap44xx_emif1_irqs,
        .main_clk       = "ddrphy_ck",
        .prcm = {
                .omap4 = {
@@ -1047,17 +926,11 @@ static struct omap_hwmod omap44xx_emif1_hwmod = {
 };
 /* emif2 */
-static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
-        { .irq = 111 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod omap44xx_emif2_hwmod = {
        .name           = "emif2",
        .class          = &omap44xx_emif_hwmod_class,
        .clkdm_name     = "l3_emif_clkdm",
        .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
-        .mpu_irqs       = omap44xx_emif2_irqs,
        .main_clk       = "ddrphy_ck",
        .prcm = {
                .omap4 = {
@@ -1098,16 +971,10 @@ static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
 };
 /* fdif */
-static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
-        { .irq = 69 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod omap44xx_fdif_hwmod = {
        .name           = "fdif",
        .class          = &omap44xx_fdif_hwmod_class,
        .clkdm_name     = "iss_clkdm",
-        .mpu_irqs       = omap44xx_fdif_irqs,
        .main_clk       = "fdif_fck",
        .prcm = {
                .omap4 = {
@@ -1148,11 +1015,6 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
 };
 /* gpio1 */
-static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
-        { .irq = 29 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
        { .role = "dbclk", .clk = "gpio1_dbclk" },
 };
@@ -1161,7 +1023,6 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
        .name           = "gpio1",
        .class          = &omap44xx_gpio_hwmod_class,
        .clkdm_name     = "l4_wkup_clkdm",
-        .mpu_irqs       = omap44xx_gpio1_irqs,
        .main_clk       = "l4_wkup_clk_mux_ck",
        .prcm = {
                .omap4 = {
@@ -1176,11 +1037,6 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
 };
 /* gpio2 */
-static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
-        { .irq = 30 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
        { .role = "dbclk", .clk = "gpio2_dbclk" },
 };
@@ -1190,7 +1046,6 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
        .class          = &omap44xx_gpio_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap44xx_gpio2_irqs,
        .main_clk       = "l4_div_ck",
        .prcm = {
                .omap4 = {
@@ -1205,11 +1060,6 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
 };
 /* gpio3 */
-static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
-        { .irq = 31 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
        { .role = "dbclk", .clk = "gpio3_dbclk" },
 };
@@ -1219,7 +1069,6 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
        .class          = &omap44xx_gpio_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap44xx_gpio3_irqs,
        .main_clk       = "l4_div_ck",
        .prcm = {
                .omap4 = {
@@ -1234,11 +1083,6 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
 };
 /* gpio4 */
-static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
-        { .irq = 32 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
        { .role = "dbclk", .clk = "gpio4_dbclk" },
 };
@@ -1248,7 +1092,6 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
        .class          = &omap44xx_gpio_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap44xx_gpio4_irqs,
        .main_clk       = "l4_div_ck",
        .prcm = {
                .omap4 = {
@@ -1263,11 +1106,6 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
 };
 /* gpio5 */
-static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
-        { .irq = 33 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
        { .role = "dbclk", .clk = "gpio5_dbclk" },
 };
@@ -1277,7 +1115,6 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
        .class          = &omap44xx_gpio_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap44xx_gpio5_irqs,
        .main_clk       = "l4_div_ck",
        .prcm = {
                .omap4 = {
@@ -1292,11 +1129,6 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
 };
 /* gpio6 */
-static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
-        { .irq = 34 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
        { .role = "dbclk", .clk = "gpio6_dbclk" },
 };
@@ -1306,7 +1138,6 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
        .class          = &omap44xx_gpio_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap44xx_gpio6_irqs,
        .main_clk       = "l4_div_ck",
        .prcm = {
                .omap4 = {
@@ -1341,16 +1172,6 @@ static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
 };
 /* gpmc */
-static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
-        { .irq = 20 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
-        { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
 static struct omap_hwmod omap44xx_gpmc_hwmod = {
        .name           = "gpmc",
        .class          = &omap44xx_gpmc_hwmod_class,
@@ -1364,8 +1185,6 @@ static struct omap_hwmod omap44xx_gpmc_hwmod = {
         * HWMOD_INIT_NO_RESET should be removed ASAP.
         */
        .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
-        .mpu_irqs       = omap44xx_gpmc_irqs,
-        .sdma_reqs      = omap44xx_gpmc_sdma_reqs,
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
@@ -1396,16 +1215,10 @@ static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
 };
 /* gpu */
-static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
-        { .irq = 21 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod omap44xx_gpu_hwmod = {
        .name           = "gpu",
        .class          = &omap44xx_gpu_hwmod_class,
        .clkdm_name     = "l3_gfx_clkdm",
-        .mpu_irqs       = omap44xx_gpu_irqs,
        .main_clk       = "sgx_clk_mux",
        .prcm = {
                .omap4 = {
@@ -1436,17 +1249,11 @@ static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
 };
 /* hdq1w */
-static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
-        { .irq = 58 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
        .name           = "hdq1w",
        .class          = &omap44xx_hdq1w_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
        .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
-        .mpu_irqs       = omap44xx_hdq1w_irqs,
        .main_clk       = "func_12m_fclk",
        .prcm = {
                .omap4 = {
@@ -1482,18 +1289,10 @@ static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
 };
 /* hsi */
-static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
-        { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
-        { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
-        { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod omap44xx_hsi_hwmod = {
        .name           = "hsi",
        .class          = &omap44xx_hsi_hwmod_class,
        .clkdm_name     = "l3_init_clkdm",
-        .mpu_irqs       = omap44xx_hsi_irqs,
        .main_clk       = "hsi_fck",
        .prcm = {
                .omap4 = {
@@ -1533,24 +1332,11 @@ static struct omap_i2c_dev_attr i2c_dev_attr = {
 };
 /* i2c1 */
-static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
-        { .irq = 56 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
-        { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
 static struct omap_hwmod omap44xx_i2c1_hwmod = {
        .name           = "i2c1",
        .class          = &omap44xx_i2c_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
-        .mpu_irqs       = omap44xx_i2c1_irqs,
-        .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
        .main_clk       = "func_96m_fclk",
        .prcm = {
                .omap4 = {
@@ -1563,24 +1349,11 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
 };
 /* i2c2 */
-static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
-        { .irq = 57 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
-        { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
 static struct omap_hwmod omap44xx_i2c2_hwmod = {
        .name           = "i2c2",
        .class          = &omap44xx_i2c_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
-        .mpu_irqs       = omap44xx_i2c2_irqs,
-        .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
        .main_clk       = "func_96m_fclk",
        .prcm = {
                .omap4 = {
@@ -1593,24 +1366,11 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
 };
 /* i2c3 */
-static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
-        { .irq = 61 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
-        { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
 static struct omap_hwmod omap44xx_i2c3_hwmod = {
        .name           = "i2c3",
        .class          = &omap44xx_i2c_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
-        .mpu_irqs       = omap44xx_i2c3_irqs,
-        .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
        .main_clk       = "func_96m_fclk",
        .prcm = {
                .omap4 = {
@@ -1623,24 +1383,11 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
 };
 /* i2c4 */
-static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
-        { .irq = 62 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
-        { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
 static struct omap_hwmod omap44xx_i2c4_hwmod = {
        .name           = "i2c4",
        .class          = &omap44xx_i2c_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
-        .mpu_irqs       = omap44xx_i2c4_irqs,
-        .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
        .main_clk       = "func_96m_fclk",
        .prcm = {
                .omap4 = {
@@ -1662,11 +1409,6 @@ static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
 };
 /* ipu */
-static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
-        { .irq = 100 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
        { .name = "cpu0", .rst_shift = 0 },
        { .name = "cpu1", .rst_shift = 1 },
@@ -1676,7 +1418,6 @@ static struct omap_hwmod omap44xx_ipu_hwmod = {
        .name           = "ipu",
        .class          = &omap44xx_ipu_hwmod_class,
        .clkdm_name     = "ducati_clkdm",
-        .mpu_irqs       = omap44xx_ipu_irqs,
        .rst_lines      = omap44xx_ipu_resets,
        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
        .main_clk       = "ducati_clk_mux_ck",
@@ -1721,19 +1462,6 @@ static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
 };
 /* iss */
-static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
-        { .irq = 24 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
-        { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
-        { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
-        { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
-        { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
        { .role = "ctrlclk", .clk = "iss_ctrlclk" },
 };
@@ -1742,8 +1470,6 @@ static struct omap_hwmod omap44xx_iss_hwmod = {
        .name           = "iss",
        .class          = &omap44xx_iss_hwmod_class,
        .clkdm_name     = "iss_clkdm",
-        .mpu_irqs       = omap44xx_iss_irqs,
-        .sdma_reqs      = omap44xx_iss_sdma_reqs,
        .main_clk       = "ducati_clk_mux_ck",
        .prcm = {
                .omap4 = {
@@ -1766,13 +1492,6 @@ static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
 };
 /* iva */
-static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
-        { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
-        { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
-        { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
        { .name = "seq0", .rst_shift = 0 },
        { .name = "seq1", .rst_shift = 1 },
@@ -1783,7 +1502,6 @@ static struct omap_hwmod omap44xx_iva_hwmod = {
        .name           = "iva",
        .class          = &omap44xx_iva_hwmod_class,
        .clkdm_name     = "ivahd_clkdm",
-        .mpu_irqs       = omap44xx_iva_irqs,
        .rst_lines      = omap44xx_iva_resets,
        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
        .main_clk       = "dpll_iva_m5x2_ck",
@@ -1820,16 +1538,10 @@ static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
 };
 /* kbd */
-static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
-        { .irq = 120 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod omap44xx_kbd_hwmod = {
        .name           = "kbd",
        .class          = &omap44xx_kbd_hwmod_class,
        .clkdm_name     = "l4_wkup_clkdm",
-        .mpu_irqs       = omap44xx_kbd_irqs,
        .main_clk       = "sys_32k_ck",
        .prcm = {
                .omap4 = {
@@ -1861,16 +1573,10 @@ static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
 };
 /* mailbox */
-static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
-        { .irq = 26 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod omap44xx_mailbox_hwmod = {
        .name           = "mailbox",
        .class          = &omap44xx_mailbox_hwmod_class,
        .clkdm_name     = "l4_cfg_clkdm",
-        .mpu_irqs       = omap44xx_mailbox_irqs,
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
@@ -1903,24 +1609,10 @@ static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
 };
 /* mcasp */
-static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
-        { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
-        { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
-        { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
-        { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
 static struct omap_hwmod omap44xx_mcasp_hwmod = {
        .name           = "mcasp",
        .class          = &omap44xx_mcasp_hwmod_class,
        .clkdm_name     = "abe_clkdm",
-        .mpu_irqs       = omap44xx_mcasp_irqs,
-        .sdma_reqs      = omap44xx_mcasp_sdma_reqs,
        .main_clk       = "func_mcasp_abe_gfclk",
        .prcm = {
                .omap4 = {
@@ -1951,17 +1643,6 @@ static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
 };
 /* mcbsp1 */
-static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
-        { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
-        { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
        { .role = "pad_fck", .clk = "pad_clks_ck" },
        { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
@@ -1971,8 +1652,6 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
        .name           = "mcbsp1",
        .class          = &omap44xx_mcbsp_hwmod_class,
        .clkdm_name     = "abe_clkdm",
-        .mpu_irqs       = omap44xx_mcbsp1_irqs,
-        .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
        .main_clk       = "func_mcbsp1_gfclk",
        .prcm = {
                .omap4 = {
@@ -1986,17 +1665,6 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
 };
 /* mcbsp2 */
-static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
-        { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
-        { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
        { .role = "pad_fck", .clk = "pad_clks_ck" },
        { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
@@ -2006,8 +1674,6 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
        .name           = "mcbsp2",
        .class          = &omap44xx_mcbsp_hwmod_class,
        .clkdm_name     = "abe_clkdm",
-        .mpu_irqs       = omap44xx_mcbsp2_irqs,
-        .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
        .main_clk       = "func_mcbsp2_gfclk",
        .prcm = {
                .omap4 = {
@@ -2021,17 +1687,6 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
 };
 /* mcbsp3 */
-static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
-        { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
-        { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
        { .role = "pad_fck", .clk = "pad_clks_ck" },
        { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
@@ -2041,8 +1696,6 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
        .name           = "mcbsp3",
        .class          = &omap44xx_mcbsp_hwmod_class,
        .clkdm_name     = "abe_clkdm",
-        .mpu_irqs       = omap44xx_mcbsp3_irqs,
-        .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
        .main_clk       = "func_mcbsp3_gfclk",
        .prcm = {
                .omap4 = {
@@ -2056,17 +1709,6 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
 };
 /* mcbsp4 */
-static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
-        { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
-        { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
        { .role = "pad_fck", .clk = "pad_clks_ck" },
        { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
@@ -2076,8 +1718,6 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
        .name           = "mcbsp4",
        .class          = &omap44xx_mcbsp_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
-        .mpu_irqs       = omap44xx_mcbsp4_irqs,
-        .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
        .main_clk       = "per_mcbsp4_gfclk",
        .prcm = {
                .omap4 = {
@@ -2112,17 +1752,6 @@ static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
 };
 /* mcpdm */
-static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
-        { .irq = 112 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
-        { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
-        { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
        .name           = "mcpdm",
        .class          = &omap44xx_mcpdm_hwmod_class,
@@ -2139,8 +1768,6 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = {
         * results 'slow motion' audio playback.
         */
        .flags          = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
-        .mpu_irqs       = omap44xx_mcpdm_irqs,
-        .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
        .main_clk       = "pad_clks_ck",
        .prcm = {
                .omap4 = {
@@ -2174,11 +1801,6 @@ static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
 };
 /* mcspi1 */
-static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
-        { .irq = 65 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
        { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
        { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
@@ -2200,7 +1822,6 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
        .name           = "mcspi1",
        .class          = &omap44xx_mcspi_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
-        .mpu_irqs       = omap44xx_mcspi1_irqs,
        .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
        .main_clk       = "func_48m_fclk",
        .prcm = {
@@ -2214,11 +1835,6 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
 };
 /* mcspi2 */
-static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
-        { .irq = 66 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
        { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
        { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
@@ -2236,7 +1852,6 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
        .name           = "mcspi2",
        .class          = &omap44xx_mcspi_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
-        .mpu_irqs       = omap44xx_mcspi2_irqs,
        .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
        .main_clk       = "func_48m_fclk",
        .prcm = {
@@ -2250,11 +1865,6 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
 };
 /* mcspi3 */
-static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
-        { .irq = 91 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
        { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
        { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
@@ -2272,7 +1882,6 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
        .name           = "mcspi3",
        .class          = &omap44xx_mcspi_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
-        .mpu_irqs       = omap44xx_mcspi3_irqs,
        .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
        .main_clk       = "func_48m_fclk",
        .prcm = {
@@ -2286,11 +1895,6 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
 };
 /* mcspi4 */
-static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
-        { .irq = 48 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
        { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
        { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
@@ -2306,7 +1910,6 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = {
        .name           = "mcspi4",
        .class          = &omap44xx_mcspi_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
-        .mpu_irqs       = omap44xx_mcspi4_irqs,
        .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
        .main_clk       = "func_48m_fclk",
        .prcm = {
@@ -2342,11 +1945,6 @@ static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
 };
 /* mmc1 */
-static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
-        { .irq = 83 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
        { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
        { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
@@ -2362,7 +1960,6 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
        .name           = "mmc1",
        .class          = &omap44xx_mmc_hwmod_class,
        .clkdm_name     = "l3_init_clkdm",
-        .mpu_irqs       = omap44xx_mmc1_irqs,
        .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
        .main_clk       = "hsmmc1_fclk",
        .prcm = {
@@ -2376,11 +1973,6 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
 };
 /* mmc2 */
-static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
-        { .irq = 86 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
        { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
        { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
@@ -2391,7 +1983,6 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
        .name           = "mmc2",
        .class          = &omap44xx_mmc_hwmod_class,
        .clkdm_name     = "l3_init_clkdm",
-        .mpu_irqs       = omap44xx_mmc2_irqs,
        .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
        .main_clk       = "hsmmc2_fclk",
        .prcm = {
@@ -2404,11 +1995,6 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
 };
 /* mmc3 */
-static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
-        { .irq = 94 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
        { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
        { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
@@ -2419,7 +2005,6 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
        .name           = "mmc3",
        .class          = &omap44xx_mmc_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
-        .mpu_irqs       = omap44xx_mmc3_irqs,
        .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
        .main_clk       = "func_48m_fclk",
        .prcm = {
@@ -2432,11 +2017,6 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
 };
 /* mmc4 */
-static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
-        { .irq = 96 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
        { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
        { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
@@ -2447,7 +2027,6 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
        .name           = "mmc4",
        .class          = &omap44xx_mmc_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
-        .mpu_irqs       = omap44xx_mmc4_irqs,
        .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
        .main_clk       = "func_48m_fclk",
        .prcm = {
@@ -2460,11 +2039,6 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
 };
 /* mmc5 */
-static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
-        { .irq = 59 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
        { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
        { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
@@ -2475,7 +2049,6 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = {
        .name           = "mmc5",
        .class          = &omap44xx_mmc_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
-        .mpu_irqs       = omap44xx_mmc5_irqs,
        .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
        .main_clk       = "func_48m_fclk",
        .prcm = {
@@ -2517,11 +2090,6 @@ static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
 };
 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
-static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = {
-        { .irq = 100 + OMAP44XX_IRQ_GIC_START, },
-        { .irq = -1 }
-};
 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
        { .name = "mmu_cache", .rst_shift = 2 },
 };
@@ -2548,7 +2116,6 @@ static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
        .name           = "mmu_ipu",
        .class          = &omap44xx_mmu_hwmod_class,
        .clkdm_name     = "ducati_clkdm",
-        .mpu_irqs       = omap44xx_mmu_ipu_irqs,
        .rst_lines      = omap44xx_mmu_ipu_resets,
        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
        .main_clk       = "ducati_clk_mux_ck",
@@ -2572,11 +2139,6 @@ static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
 };
 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
-static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = {
-        { .irq = 28 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
        { .name = "mmu_cache", .rst_shift = 1 },
 };
@@ -2603,7 +2165,6 @@ static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
        .name           = "mmu_dsp",
        .class          = &omap44xx_mmu_hwmod_class,
        .clkdm_name     = "tesla_clkdm",
-        .mpu_irqs       = omap44xx_mmu_dsp_irqs,
        .rst_lines      = omap44xx_mmu_dsp_resets,
        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
        .main_clk       = "dpll_iva_m4x2_ck",
@@ -2628,21 +2189,11 @@ static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
 };
 /* mpu */
-static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
-        { .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START },
-        { .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START },
-        { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
-        { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
-        { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod omap44xx_mpu_hwmod = {
        .name           = "mpu",
        .class          = &omap44xx_mpu_hwmod_class,
        .clkdm_name     = "mpuss_clkdm",
        .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
-        .mpu_irqs       = omap44xx_mpu_irqs,
        .main_clk       = "dpll_mpu_m2_ck",
        .prcm = {
                .omap4 = {
@@ -2695,25 +2246,6 @@ static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
        .sysc   = &omap44xx_ocp2scp_sysc,
 };
-/* ocp2scp dev_attr */
-static struct resource omap44xx_usb_phy_and_pll_addrs[] = {
-        {
-                .name           = "usb_phy",
-                .start          = 0x4a0ad080,
-                .end            = 0x4a0ae000,
-                .flags          = IORESOURCE_MEM,
-        },
-        { }
-};
-static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = {
-        {
-                .drv_name       = "omap-usb2",
-                .res            = omap44xx_usb_phy_and_pll_addrs,
-        },
-        { }
-};
 /* ocp2scp_usb_phy */
 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
        .name           = "ocp2scp_usb_phy",
@@ -2737,7 +2269,6 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
                        .modulemode   = MODULEMODE_HWCTRL,
                },
        },
-        .dev_attr       = ocp2scp_dev_attr,
 };
 /*
@@ -2788,11 +2319,6 @@ static struct omap_hwmod omap44xx_cm_core_hwmod = {
 };
 /* prm */
-static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
-        { .irq = 11 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
        { .name = "rst_global_warm_sw", .rst_shift = 0 },
        { .name = "rst_global_cold_sw", .rst_shift = 1 },
@@ -2801,7 +2327,6 @@ static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
 static struct omap_hwmod omap44xx_prm_hwmod = {
        .name           = "prm",
        .class          = &omap44xx_prcm_hwmod_class,
-        .mpu_irqs       = omap44xx_prm_irqs,
        .rst_lines      = omap44xx_prm_resets,
        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
 };
@@ -2872,23 +2397,6 @@ static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
 };
 /* slimbus1 */
-static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
-        { .irq = 97 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
-        { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
-        { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
-        { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
-        { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
        { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
        { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
@@ -2900,8 +2408,6 @@ static struct omap_hwmod omap44xx_slimbus1_hwmod = {
        .name           = "slimbus1",
        .class          = &omap44xx_slimbus_hwmod_class,
        .clkdm_name     = "abe_clkdm",
-        .mpu_irqs       = omap44xx_slimbus1_irqs,
-        .sdma_reqs      = omap44xx_slimbus1_sdma_reqs,
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
@@ -2914,23 +2420,6 @@ static struct omap_hwmod omap44xx_slimbus1_hwmod = {
 };
 /* slimbus2 */
-static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
-        { .irq = 98 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
-        { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
-        { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
-        { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
-        { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
        { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
        { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
@@ -2941,8 +2430,6 @@ static struct omap_hwmod omap44xx_slimbus2_hwmod = {
        .name           = "slimbus2",
        .class          = &omap44xx_slimbus_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
-        .mpu_irqs       = omap44xx_slimbus2_irqs,
-        .sdma_reqs      = omap44xx_slimbus2_sdma_reqs,
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
@@ -2985,16 +2472,10 @@ static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
        .sensor_voltdm_name   = "core",
 };
-static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
-        { .irq = 19 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
        .name           = "smartreflex_core",
        .class          = &omap44xx_smartreflex_hwmod_class,
        .clkdm_name     = "l4_ao_clkdm",
-        .mpu_irqs       = omap44xx_smartreflex_core_irqs,
        .main_clk       = "smartreflex_core_fck",
        .prcm = {
@@ -3012,16 +2493,10 @@ static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
        .sensor_voltdm_name     = "iva",
 };
-static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
-        { .irq = 102 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
        .name           = "smartreflex_iva",
        .class          = &omap44xx_smartreflex_hwmod_class,
        .clkdm_name     = "l4_ao_clkdm",
-        .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
        .main_clk       = "smartreflex_iva_fck",
        .prcm = {
                .omap4 = {
@@ -3038,16 +2513,10 @@ static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
        .sensor_voltdm_name     = "mpu",
 };
-static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
-        { .irq = 18 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
        .name           = "smartreflex_mpu",
        .class          = &omap44xx_smartreflex_hwmod_class,
        .clkdm_name     = "l4_ao_clkdm",
-        .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
        .main_clk       = "smartreflex_mpu_fck",
        .prcm = {
                .omap4 = {
@@ -3155,17 +2624,11 @@ static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
 };
 /* timer1 */
-static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
-        { .irq = 37 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod omap44xx_timer1_hwmod = {
        .name           = "timer1",
        .class          = &omap44xx_timer_1ms_hwmod_class,
        .clkdm_name     = "l4_wkup_clkdm",
        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
-        .mpu_irqs       = omap44xx_timer1_irqs,
        .main_clk       = "dmt1_clk_mux",
        .prcm = {
                .omap4 = {
@@ -3178,17 +2641,11 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
 };
 /* timer2 */
-static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
-        { .irq = 38 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod omap44xx_timer2_hwmod = {
        .name           = "timer2",
        .class          = &omap44xx_timer_1ms_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
-        .mpu_irqs       = omap44xx_timer2_irqs,
        .main_clk       = "cm2_dm2_mux",
        .prcm = {
                .omap4 = {
@@ -3200,16 +2657,10 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
 };
 /* timer3 */
-static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
-        { .irq = 39 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod omap44xx_timer3_hwmod = {
        .name           = "timer3",
        .class          = &omap44xx_timer_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
-        .mpu_irqs       = omap44xx_timer3_irqs,
        .main_clk       = "cm2_dm3_mux",
        .prcm = {
                .omap4 = {
@@ -3221,16 +2672,10 @@ static struct omap_hwmod omap44xx_timer3_hwmod = {
 };
 /* timer4 */
-static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
-        { .irq = 40 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod omap44xx_timer4_hwmod = {
        .name           = "timer4",
        .class          = &omap44xx_timer_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
-        .mpu_irqs       = omap44xx_timer4_irqs,
        .main_clk       = "cm2_dm4_mux",
        .prcm = {
                .omap4 = {
@@ -3242,16 +2687,10 @@ static struct omap_hwmod omap44xx_timer4_hwmod = {
 };
 /* timer5 */
-static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
-        { .irq = 41 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod omap44xx_timer5_hwmod = {
        .name           = "timer5",
        .class          = &omap44xx_timer_hwmod_class,
        .clkdm_name     = "abe_clkdm",
-        .mpu_irqs       = omap44xx_timer5_irqs,
        .main_clk       = "timer5_sync_mux",
        .prcm = {
                .omap4 = {
@@ -3264,16 +2703,10 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
 };
 /* timer6 */
-static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
-        { .irq = 42 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod omap44xx_timer6_hwmod = {
        .name           = "timer6",
        .class          = &omap44xx_timer_hwmod_class,
        .clkdm_name     = "abe_clkdm",
-        .mpu_irqs       = omap44xx_timer6_irqs,
        .main_clk       = "timer6_sync_mux",
        .prcm = {
                .omap4 = {
@@ -3286,16 +2719,10 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
 };
 /* timer7 */
-static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
-        { .irq = 43 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod omap44xx_timer7_hwmod = {
        .name           = "timer7",
        .class          = &omap44xx_timer_hwmod_class,
        .clkdm_name     = "abe_clkdm",
-        .mpu_irqs       = omap44xx_timer7_irqs,
        .main_clk       = "timer7_sync_mux",
        .prcm = {
                .omap4 = {
@@ -3308,16 +2735,10 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
 };
 /* timer8 */
-static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
-        { .irq = 44 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod omap44xx_timer8_hwmod = {
        .name           = "timer8",
        .class          = &omap44xx_timer_hwmod_class,
        .clkdm_name     = "abe_clkdm",
-        .mpu_irqs       = omap44xx_timer8_irqs,
        .main_clk       = "timer8_sync_mux",
        .prcm = {
                .omap4 = {
@@ -3330,16 +2751,10 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
 };
 /* timer9 */
-static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
-        { .irq = 45 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod omap44xx_timer9_hwmod = {
        .name           = "timer9",
        .class          = &omap44xx_timer_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
-        .mpu_irqs       = omap44xx_timer9_irqs,
        .main_clk       = "cm2_dm9_mux",
        .prcm = {
                .omap4 = {
@@ -3352,17 +2767,11 @@ static struct omap_hwmod omap44xx_timer9_hwmod = {
 };
 /* timer10 */
-static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
-        { .irq = 46 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod omap44xx_timer10_hwmod = {
        .name           = "timer10",
        .class          = &omap44xx_timer_1ms_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
-        .mpu_irqs       = omap44xx_timer10_irqs,
        .main_clk       = "cm2_dm10_mux",
        .prcm = {
                .omap4 = {
@@ -3375,16 +2784,10 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
 };
 /* timer11 */
-static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
-        { .irq = 47 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod omap44xx_timer11_hwmod = {
        .name           = "timer11",
        .class          = &omap44xx_timer_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
-        .mpu_irqs       = omap44xx_timer11_irqs,
        .main_clk       = "cm2_dm11_mux",
        .prcm = {
                .omap4 = {
@@ -3419,24 +2822,11 @@ static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
 };
 /* uart1 */
-static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
-        { .irq = 72 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
-        { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
 static struct omap_hwmod omap44xx_uart1_hwmod = {
        .name           = "uart1",
        .class          = &omap44xx_uart_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
        .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .mpu_irqs       = omap44xx_uart1_irqs,
-        .sdma_reqs      = omap44xx_uart1_sdma_reqs,
        .main_clk       = "func_48m_fclk",
        .prcm = {
                .omap4 = {
@@ -3448,24 +2838,11 @@ static struct omap_hwmod omap44xx_uart1_hwmod = {
 };
 /* uart2 */
-static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
-        { .irq = 73 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
-        { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
 static struct omap_hwmod omap44xx_uart2_hwmod = {
        .name           = "uart2",
        .class          = &omap44xx_uart_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
        .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .mpu_irqs       = omap44xx_uart2_irqs,
-        .sdma_reqs      = omap44xx_uart2_sdma_reqs,
        .main_clk       = "func_48m_fclk",
        .prcm = {
                .omap4 = {
@@ -3477,25 +2854,11 @@ static struct omap_hwmod omap44xx_uart2_hwmod = {
 };
 /* uart3 */
-static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
-        { .irq = 74 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
-        { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
 static struct omap_hwmod omap44xx_uart3_hwmod = {
        .name           = "uart3",
        .class          = &omap44xx_uart_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
-        .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
+        .flags          = DEBUG_OMAP4UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
-                                HWMOD_SWSUP_SIDLE_ACT,
-        .mpu_irqs       = omap44xx_uart3_irqs,
-        .sdma_reqs      = omap44xx_uart3_sdma_reqs,
        .main_clk       = "func_48m_fclk",
        .prcm = {
                .omap4 = {
@@ -3507,24 +2870,11 @@ static struct omap_hwmod omap44xx_uart3_hwmod = {
 };
 /* uart4 */
-static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
-        { .irq = 70 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
-        { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
 static struct omap_hwmod omap44xx_uart4_hwmod = {
        .name           = "uart4",
        .class          = &omap44xx_uart_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
-        .flags          = HWMOD_SWSUP_SIDLE_ACT,
+        .flags          = DEBUG_OMAP4UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
-        .mpu_irqs       = omap44xx_uart4_irqs,
-        .sdma_reqs      = omap44xx_uart4_sdma_reqs,
        .main_clk       = "func_48m_fclk",
        .prcm = {
                .omap4 = {
@@ -3563,17 +2913,10 @@ static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
 };
 /* usb_host_fs */
-static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
-        { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
-        { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
        .name           = "usb_host_fs",
        .class          = &omap44xx_usb_host_fs_hwmod_class,
        .clkdm_name     = "l3_init_clkdm",
-        .mpu_irqs       = omap44xx_usb_host_fs_irqs,
        .main_clk       = "usb_host_fs_fck",
        .prcm = {
                .omap4 = {
@@ -3607,12 +2950,6 @@ static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
 };
 /* usb_host_hs */
-static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
-        { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
-        { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
        .name           = "usb_host_hs",
        .class          = &omap44xx_usb_host_hs_hwmod_class,
@@ -3625,7 +2962,6 @@ static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
-        .mpu_irqs       = omap44xx_usb_host_hs_irqs,
        /*
         * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
@@ -3700,12 +3036,6 @@ static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
 };
 /* usb_otg_hs */
-static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
-        { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
-        { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
        { .role = "xclk", .clk = "usb_otg_hs_xclk" },
 };
@@ -3715,7 +3045,6 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
        .class          = &omap44xx_usb_otg_hs_hwmod_class,
        .clkdm_name     = "l3_init_clkdm",
        .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
-        .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
        .main_clk       = "usb_otg_hs_ick",
        .prcm = {
                .omap4 = {
@@ -3749,16 +3078,10 @@ static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
        .sysc   = &omap44xx_usb_tll_hs_sysc,
 };
-static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
-        { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
        .name           = "usb_tll_hs",
        .class          = &omap44xx_usb_tll_hs_hwmod_class,
        .clkdm_name     = "l3_init_clkdm",
-        .mpu_irqs       = omap44xx_usb_tll_hs_irqs,
        .main_clk       = "usb_tll_hs_ick",
        .prcm = {
                .omap4 = {
@@ -3794,16 +3117,10 @@ static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
 };
 /* wd_timer2 */
-static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
-        { .irq = 80 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
        .name           = "wd_timer2",
        .class          = &omap44xx_wd_timer_hwmod_class,
        .clkdm_name     = "l4_wkup_clkdm",
-        .mpu_irqs       = omap44xx_wd_timer2_irqs,
        .main_clk       = "sys_32k_ck",
        .prcm = {
                .omap4 = {
@@ -3815,16 +3132,10 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
 };
 /* wd_timer3 */
-static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
-        { .irq = 36 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
        .name           = "wd_timer3",
        .class          = &omap44xx_wd_timer_hwmod_class,
        .clkdm_name     = "abe_clkdm",
-        .mpu_irqs       = omap44xx_wd_timer3_irqs,
        .main_clk       = "sys_32k_ck",
        .prcm = {
                .omap4 = {
@@ -3840,32 +3151,6 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
 * interfaces
 */
-static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
-        {
-                .pa_start       = 0x4a204000,
-                .pa_end         = 0x4a2040ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* c2c -> c2c_target_fw */
-static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
-        .master         = &omap44xx_c2c_hwmod,
-        .slave          = &omap44xx_c2c_target_fw_hwmod,
-        .clk            = "div_core_ck",
-        .addr           = omap44xx_c2c_target_fw_addrs,
-        .user           = OCP_USER_MPU,
-};
-/* l4_cfg -> c2c_target_fw */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
-        .master         = &omap44xx_l4_cfg_hwmod,
-        .slave          = &omap44xx_c2c_target_fw_hwmod,
-        .clk            = "l4_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
 /* l3_main_1 -> dmm */
 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
        .master         = &omap44xx_l3_main_1_hwmod,
@@ -3874,55 +3159,11 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
        .user           = OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
-        {
-                .pa_start       = 0x4e000000,
-                .pa_end         = 0x4e0007ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* mpu -> dmm */
 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
        .master         = &omap44xx_mpu_hwmod,
        .slave          = &omap44xx_dmm_hwmod,
        .clk            = "l3_div_ck",
-        .addr           = omap44xx_dmm_addrs,
-        .user           = OCP_USER_MPU,
-};
-/* c2c -> emif_fw */
-static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
-        .master         = &omap44xx_c2c_hwmod,
-        .slave          = &omap44xx_emif_fw_hwmod,
-        .clk            = "div_core_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* dmm -> emif_fw */
-static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
-        .master         = &omap44xx_dmm_hwmod,
-        .slave          = &omap44xx_emif_fw_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
-        {
-                .pa_start       = 0x4a20c000,
-                .pa_end         = 0x4a20c0ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_cfg -> emif_fw */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
-        .master         = &omap44xx_l4_cfg_hwmod,
-        .slave          = &omap44xx_emif_fw_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_emif_fw_addrs,
        .user           = OCP_USER_MPU,
 };
@@ -3998,32 +3239,14 @@ static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
-        {
-                .pa_start       = 0x44000000,
-                .pa_end         = 0x44000fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* mpu -> l3_main_1 */
 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
        .master         = &omap44xx_mpu_hwmod,
        .slave          = &omap44xx_l3_main_1_hwmod,
        .clk            = "l3_div_ck",
-        .addr           = omap44xx_l3_main_1_addrs,
        .user           = OCP_USER_MPU,
 };
-/* c2c_target_fw -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
-        .master         = &omap44xx_c2c_target_fw_hwmod,
-        .slave          = &omap44xx_l3_main_2_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
 /* debugss -> l3_main_2 */
 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
        .master         = &omap44xx_debugss_hwmod,
@@ -4088,21 +3311,11 @@ static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
-        {
-                .pa_start       = 0x44800000,
-                .pa_end         = 0x44801fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l3_main_1 -> l3_main_2 */
 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
        .master         = &omap44xx_l3_main_1_hwmod,
        .slave          = &omap44xx_l3_main_2_hwmod,
        .clk            = "l3_div_ck",
-        .addr           = omap44xx_l3_main_2_addrs,
        .user           = OCP_USER_MPU,
 };
@@ -4138,21 +3351,11 @@ static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
-        {
-                .pa_start       = 0x45000000,
-                .pa_end         = 0x45000fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l3_main_1 -> l3_main_3 */
 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
        .master         = &omap44xx_l3_main_1_hwmod,
        .slave          = &omap44xx_l3_main_3_hwmod,
        .clk            = "l3_div_ck",
-        .addr           = omap44xx_l3_main_3_addrs,
        .user           = OCP_USER_MPU,
 };
@@ -4236,21 +3439,11 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
-        {
-                .pa_start       = 0x4a102000,
-                .pa_end         = 0x4a10207f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_cfg -> ocp_wp_noc */
 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
        .master         = &omap44xx_l4_cfg_hwmod,
        .slave          = &omap44xx_ocp_wp_noc_hwmod,
        .clk            = "l4_div_ck",
-        .addr           = omap44xx_ocp_wp_noc_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
@@ -4340,21 +3533,11 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
-        {
-                .pa_start       = 0x4a304000,
-                .pa_end         = 0x4a30401f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_wkup -> counter_32k */
 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
        .master         = &omap44xx_l4_wkup_hwmod,
        .slave          = &omap44xx_counter_32k_hwmod,
        .clk            = "l4_wkup_clk_mux_ck",
-        .addr           = omap44xx_counter_32k_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
@@ -4430,21 +3613,11 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
-        {
-                .pa_start       = 0x54160000,
-                .pa_end         = 0x54167fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l3_instr -> debugss */
 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
        .master         = &omap44xx_l3_instr_hwmod,
        .slave          = &omap44xx_debugss_hwmod,
        .clk            = "l3_div_ck",
-        .addr           = omap44xx_debugss_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
@@ -4466,41 +3639,19 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x4012e000,
-                .pa_end         = 0x4012e07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_abe -> dmic */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
        .master         = &omap44xx_l4_abe_hwmod,
        .slave          = &omap44xx_dmic_hwmod,
        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_dmic_addrs,
        .user           = OCP_USER_MPU,
 };
-static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
-        {
-                .name           = "dma",
-                .pa_start       = 0x4902e000,
-                .pa_end         = 0x4902e07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_abe -> dmic (dma) */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
        .master         = &omap44xx_l4_abe_hwmod,
        .slave          = &omap44xx_dmic_hwmod,
        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_dmic_dma_addrs,
        .user           = OCP_USER_SDMA,
 };
@@ -4798,42 +3949,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
-        {
-                .pa_start       = 0x4c000000,
-                .pa_end         = 0x4c0000ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* emif_fw -> emif1 */
-static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
-        .master         = &omap44xx_emif_fw_hwmod,
-        .slave          = &omap44xx_emif1_hwmod,
-        .clk            = "l3_div_ck",
-        .addr           = omap44xx_emif1_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
-        {
-                .pa_start       = 0x4d000000,
-                .pa_end         = 0x4d0000ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* emif_fw -> emif2 */
-static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
-        .master         = &omap44xx_emif_fw_hwmod,
-        .slave          = &omap44xx_emif2_hwmod,
-        .clk            = "l3_div_ck",
-        .addr           = omap44xx_emif2_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
        {
                .pa_start       = 0x4a10a000,
@@ -4852,129 +3967,59 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
-        {
-                .pa_start       = 0x4a310000,
-                .pa_end         = 0x4a3101ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_wkup -> gpio1 */
 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
        .master         = &omap44xx_l4_wkup_hwmod,
        .slave          = &omap44xx_gpio1_hwmod,
        .clk            = "l4_wkup_clk_mux_ck",
-        .addr           = omap44xx_gpio1_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
-        {
-                .pa_start       = 0x48055000,
-                .pa_end         = 0x480551ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_per -> gpio2 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
        .master         = &omap44xx_l4_per_hwmod,
        .slave          = &omap44xx_gpio2_hwmod,
        .clk            = "l4_div_ck",
-        .addr           = omap44xx_gpio2_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
-        {
-                .pa_start       = 0x48057000,
-                .pa_end         = 0x480571ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_per -> gpio3 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
        .master         = &omap44xx_l4_per_hwmod,
        .slave          = &omap44xx_gpio3_hwmod,
        .clk            = "l4_div_ck",
-        .addr           = omap44xx_gpio3_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
-        {
-                .pa_start       = 0x48059000,
-                .pa_end         = 0x480591ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_per -> gpio4 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
        .master         = &omap44xx_l4_per_hwmod,
        .slave          = &omap44xx_gpio4_hwmod,
        .clk            = "l4_div_ck",
-        .addr           = omap44xx_gpio4_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
-        {
-                .pa_start       = 0x4805b000,
-                .pa_end         = 0x4805b1ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_per -> gpio5 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
        .master         = &omap44xx_l4_per_hwmod,
        .slave          = &omap44xx_gpio5_hwmod,
        .clk            = "l4_div_ck",
-        .addr           = omap44xx_gpio5_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
-        {
-                .pa_start       = 0x4805d000,
-                .pa_end         = 0x4805d1ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_per -> gpio6 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
        .master         = &omap44xx_l4_per_hwmod,
        .slave          = &omap44xx_gpio6_hwmod,
        .clk            = "l4_div_ck",
-        .addr           = omap44xx_gpio6_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
-        {
-                .pa_start       = 0x50000000,
-                .pa_end         = 0x500003ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l3_main_2 -> gpmc */
 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
        .master         = &omap44xx_l3_main_2_hwmod,
        .slave          = &omap44xx_gpmc_hwmod,
        .clk            = "l3_div_ck",
-        .addr           = omap44xx_gpmc_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
@@ -5032,75 +4077,35 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
-        {
-                .pa_start       = 0x48070000,
-                .pa_end         = 0x480700ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_per -> i2c1 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
        .master         = &omap44xx_l4_per_hwmod,
        .slave          = &omap44xx_i2c1_hwmod,
        .clk            = "l4_div_ck",
-        .addr           = omap44xx_i2c1_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
-        {
-                .pa_start       = 0x48072000,
-                .pa_end         = 0x480720ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_per -> i2c2 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
        .master         = &omap44xx_l4_per_hwmod,
        .slave          = &omap44xx_i2c2_hwmod,
        .clk            = "l4_div_ck",
-        .addr           = omap44xx_i2c2_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
-        {
-                .pa_start       = 0x48060000,
-                .pa_end         = 0x480600ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_per -> i2c3 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
        .master         = &omap44xx_l4_per_hwmod,
        .slave          = &omap44xx_i2c3_hwmod,
        .clk            = "l4_div_ck",
-        .addr           = omap44xx_i2c3_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
-        {
-                .pa_start       = 0x48350000,
-                .pa_end         = 0x483500ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_per -> i2c4 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
        .master         = &omap44xx_l4_per_hwmod,
        .slave          = &omap44xx_i2c4_hwmod,
        .clk            = "l4_div_ck",
-        .addr           = omap44xx_i2c4_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
@@ -5138,39 +4143,19 @@ static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
        .user           = OCP_USER_IVA,
 };
-static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
-        {
-                .pa_start       = 0x5a000000,
-                .pa_end         = 0x5a07ffff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l3_main_2 -> iva */
 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
        .master         = &omap44xx_l3_main_2_hwmod,
        .slave          = &omap44xx_iva_hwmod,
        .clk            = "l3_div_ck",
-        .addr           = omap44xx_iva_addrs,
        .user           = OCP_USER_MPU,
 };
-static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
-        {
-                .pa_start       = 0x4a31c000,
-                .pa_end         = 0x4a31c07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_wkup -> kbd */
 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
        .master         = &omap44xx_l4_wkup_hwmod,
        .slave          = &omap44xx_kbd_hwmod,
        .clk            = "l4_wkup_clk_mux_ck",
-        .addr           = omap44xx_kbd_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
@@ -5228,335 +4213,147 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
        .user           = OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x40122000,
-                .pa_end         = 0x401220ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_abe -> mcbsp1 */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
        .master         = &omap44xx_l4_abe_hwmod,
        .slave          = &omap44xx_mcbsp1_hwmod,
        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_mcbsp1_addrs,
        .user           = OCP_USER_MPU,
 };
-static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
-        {
-                .name           = "dma",
-                .pa_start       = 0x49022000,
-                .pa_end         = 0x490220ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_abe -> mcbsp1 (dma) */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
        .master         = &omap44xx_l4_abe_hwmod,
        .slave          = &omap44xx_mcbsp1_hwmod,
        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_mcbsp1_dma_addrs,
        .user           = OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x40124000,
-                .pa_end         = 0x401240ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_abe -> mcbsp2 */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
        .master         = &omap44xx_l4_abe_hwmod,
        .slave          = &omap44xx_mcbsp2_hwmod,
        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_mcbsp2_addrs,
        .user           = OCP_USER_MPU,
 };
-static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
-        {
-                .name           = "dma",
-                .pa_start       = 0x49024000,
-                .pa_end         = 0x490240ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_abe -> mcbsp2 (dma) */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
        .master         = &omap44xx_l4_abe_hwmod,
        .slave          = &omap44xx_mcbsp2_hwmod,
        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_mcbsp2_dma_addrs,
        .user           = OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x40126000,
-                .pa_end         = 0x401260ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_abe -> mcbsp3 */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
        .master         = &omap44xx_l4_abe_hwmod,
        .slave          = &omap44xx_mcbsp3_hwmod,
        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_mcbsp3_addrs,
        .user           = OCP_USER_MPU,
 };
-static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
-        {
-                .name           = "dma",
-                .pa_start       = 0x49026000,
-                .pa_end         = 0x490260ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_abe -> mcbsp3 (dma) */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
        .master         = &omap44xx_l4_abe_hwmod,
        .slave          = &omap44xx_mcbsp3_hwmod,
        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_mcbsp3_dma_addrs,
        .user           = OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
-        {
-                .pa_start       = 0x48096000,
-                .pa_end         = 0x480960ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_per -> mcbsp4 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
        .master         = &omap44xx_l4_per_hwmod,
        .slave          = &omap44xx_mcbsp4_hwmod,
        .clk            = "l4_div_ck",
-        .addr           = omap44xx_mcbsp4_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x40132000,
-                .pa_end         = 0x4013207f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_abe -> mcpdm */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
        .master         = &omap44xx_l4_abe_hwmod,
        .slave          = &omap44xx_mcpdm_hwmod,
        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_mcpdm_addrs,
        .user           = OCP_USER_MPU,
 };
-static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
-        {
-                .name           = "dma",
-                .pa_start       = 0x49032000,
-                .pa_end         = 0x4903207f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_abe -> mcpdm (dma) */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
        .master         = &omap44xx_l4_abe_hwmod,
        .slave          = &omap44xx_mcpdm_hwmod,
        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_mcpdm_dma_addrs,
        .user           = OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
-        {
-                .pa_start       = 0x48098000,
-                .pa_end         = 0x480981ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_per -> mcspi1 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
        .master         = &omap44xx_l4_per_hwmod,
        .slave          = &omap44xx_mcspi1_hwmod,
        .clk            = "l4_div_ck",
-        .addr           = omap44xx_mcspi1_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
-        {
-                .pa_start       = 0x4809a000,
-                .pa_end         = 0x4809a1ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_per -> mcspi2 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
        .master         = &omap44xx_l4_per_hwmod,
        .slave          = &omap44xx_mcspi2_hwmod,
        .clk            = "l4_div_ck",
-        .addr           = omap44xx_mcspi2_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
-        {
-                .pa_start       = 0x480b8000,
-                .pa_end         = 0x480b81ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_per -> mcspi3 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
        .master         = &omap44xx_l4_per_hwmod,
        .slave          = &omap44xx_mcspi3_hwmod,
        .clk            = "l4_div_ck",
-        .addr           = omap44xx_mcspi3_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
-        {
-                .pa_start       = 0x480ba000,
-                .pa_end         = 0x480ba1ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_per -> mcspi4 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
        .master         = &omap44xx_l4_per_hwmod,
        .slave          = &omap44xx_mcspi4_hwmod,
        .clk            = "l4_div_ck",
-        .addr           = omap44xx_mcspi4_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
-        {
-                .pa_start       = 0x4809c000,
-                .pa_end         = 0x4809c3ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_per -> mmc1 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
        .master         = &omap44xx_l4_per_hwmod,
        .slave          = &omap44xx_mmc1_hwmod,
        .clk            = "l4_div_ck",
-        .addr           = omap44xx_mmc1_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
-        {
-                .pa_start       = 0x480b4000,
-                .pa_end         = 0x480b43ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_per -> mmc2 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
        .master         = &omap44xx_l4_per_hwmod,
        .slave          = &omap44xx_mmc2_hwmod,
        .clk            = "l4_div_ck",
-        .addr           = omap44xx_mmc2_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
-        {
-                .pa_start       = 0x480ad000,
-                .pa_end         = 0x480ad3ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_per -> mmc3 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
        .master         = &omap44xx_l4_per_hwmod,
        .slave          = &omap44xx_mmc3_hwmod,
        .clk            = "l4_div_ck",
-        .addr           = omap44xx_mmc3_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
-        {
-                .pa_start       = 0x480d1000,
-                .pa_end         = 0x480d13ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_per -> mmc4 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
        .master         = &omap44xx_l4_per_hwmod,
        .slave          = &omap44xx_mmc4_hwmod,
        .clk            = "l4_div_ck",
-        .addr           = omap44xx_mmc4_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
-        {
-                .pa_start       = 0x480d5000,
-                .pa_end         = 0x480d53ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_per -> mmc5 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
        .master         = &omap44xx_l4_per_hwmod,
        .slave          = &omap44xx_mmc5_hwmod,
        .clk            = "l4_div_ck",
-        .addr           = omap44xx_mmc5_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
@@ -5568,111 +4365,51 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = {
-        {
-                .pa_start       = 0x4a0ad000,
-                .pa_end         = 0x4a0ad01f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_cfg -> ocp2scp_usb_phy */
 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
        .master         = &omap44xx_l4_cfg_hwmod,
        .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
        .clk            = "l4_div_ck",
-        .addr           = omap44xx_ocp2scp_usb_phy_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
-        {
-                .pa_start       = 0x48243000,
-                .pa_end         = 0x48243fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* mpu_private -> prcm_mpu */
 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
        .master         = &omap44xx_mpu_private_hwmod,
        .slave          = &omap44xx_prcm_mpu_hwmod,
        .clk            = "l3_div_ck",
-        .addr           = omap44xx_prcm_mpu_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
-        {
-                .pa_start       = 0x4a004000,
-                .pa_end         = 0x4a004fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_wkup -> cm_core_aon */
 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
        .master         = &omap44xx_l4_wkup_hwmod,
        .slave          = &omap44xx_cm_core_aon_hwmod,
        .clk            = "l4_wkup_clk_mux_ck",
-        .addr           = omap44xx_cm_core_aon_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
-        {
-                .pa_start       = 0x4a008000,
-                .pa_end         = 0x4a009fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_cfg -> cm_core */
 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
        .master         = &omap44xx_l4_cfg_hwmod,
        .slave          = &omap44xx_cm_core_hwmod,
        .clk            = "l4_div_ck",
-        .addr           = omap44xx_cm_core_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
-        {
-                .pa_start       = 0x4a306000,
-                .pa_end         = 0x4a307fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_wkup -> prm */
 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
        .master         = &omap44xx_l4_wkup_hwmod,
        .slave          = &omap44xx_prm_hwmod,
        .clk            = "l4_wkup_clk_mux_ck",
-        .addr           = omap44xx_prm_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
-        {
-                .pa_start       = 0x4a30a000,
-                .pa_end         = 0x4a30a7ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_wkup -> scrm */
 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
        .master         = &omap44xx_l4_wkup_hwmod,
        .slave          = &omap44xx_scrm_hwmod,
        .clk            = "l4_wkup_clk_mux_ck",
-        .addr           = omap44xx_scrm_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
@@ -5810,447 +4547,195 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
-        {
-                .pa_start       = 0x4a318000,
-                .pa_end         = 0x4a31807f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_wkup -> timer1 */
 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
        .master         = &omap44xx_l4_wkup_hwmod,
        .slave          = &omap44xx_timer1_hwmod,
        .clk            = "l4_wkup_clk_mux_ck",
-        .addr           = omap44xx_timer1_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
-        {
-                .pa_start       = 0x48032000,
-                .pa_end         = 0x4803207f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_per -> timer2 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
        .master         = &omap44xx_l4_per_hwmod,
        .slave          = &omap44xx_timer2_hwmod,
        .clk            = "l4_div_ck",
-        .addr           = omap44xx_timer2_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
-        {
-                .pa_start       = 0x48034000,
-                .pa_end         = 0x4803407f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_per -> timer3 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
        .master         = &omap44xx_l4_per_hwmod,
        .slave          = &omap44xx_timer3_hwmod,
        .clk            = "l4_div_ck",
-        .addr           = omap44xx_timer3_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
-        {
-                .pa_start       = 0x48036000,
-                .pa_end         = 0x4803607f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_per -> timer4 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
        .master         = &omap44xx_l4_per_hwmod,
        .slave          = &omap44xx_timer4_hwmod,
        .clk            = "l4_div_ck",
-        .addr           = omap44xx_timer4_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
-        {
-                .pa_start       = 0x40138000,
-                .pa_end         = 0x4013807f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_abe -> timer5 */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
        .master         = &omap44xx_l4_abe_hwmod,
        .slave          = &omap44xx_timer5_hwmod,
        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_timer5_addrs,
        .user           = OCP_USER_MPU,
 };
-static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
-        {
-                .pa_start       = 0x49038000,
-                .pa_end         = 0x4903807f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_abe -> timer5 (dma) */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
        .master         = &omap44xx_l4_abe_hwmod,
        .slave          = &omap44xx_timer5_hwmod,
        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_timer5_dma_addrs,
        .user           = OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
-        {
-                .pa_start       = 0x4013a000,
-                .pa_end         = 0x4013a07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_abe -> timer6 */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
        .master         = &omap44xx_l4_abe_hwmod,
        .slave          = &omap44xx_timer6_hwmod,
        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_timer6_addrs,
        .user           = OCP_USER_MPU,
 };
-static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
-        {
-                .pa_start       = 0x4903a000,
-                .pa_end         = 0x4903a07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_abe -> timer6 (dma) */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
        .master         = &omap44xx_l4_abe_hwmod,
        .slave          = &omap44xx_timer6_hwmod,
        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_timer6_dma_addrs,
        .user           = OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
-        {
-                .pa_start       = 0x4013c000,
-                .pa_end         = 0x4013c07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_abe -> timer7 */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
        .master         = &omap44xx_l4_abe_hwmod,
        .slave          = &omap44xx_timer7_hwmod,
        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_timer7_addrs,
        .user           = OCP_USER_MPU,
 };
-static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
-        {
-                .pa_start       = 0x4903c000,
-                .pa_end         = 0x4903c07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_abe -> timer7 (dma) */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
        .master         = &omap44xx_l4_abe_hwmod,
        .slave          = &omap44xx_timer7_hwmod,
        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_timer7_dma_addrs,
        .user           = OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
-        {
-                .pa_start       = 0x4013e000,
-                .pa_end         = 0x4013e07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_abe -> timer8 */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
        .master         = &omap44xx_l4_abe_hwmod,
        .slave          = &omap44xx_timer8_hwmod,
        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_timer8_addrs,
        .user           = OCP_USER_MPU,
 };
-static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
-        {
-                .pa_start       = 0x4903e000,
-                .pa_end         = 0x4903e07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_abe -> timer8 (dma) */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
        .master         = &omap44xx_l4_abe_hwmod,
        .slave          = &omap44xx_timer8_hwmod,
        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_timer8_dma_addrs,
        .user           = OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
-        {
-                .pa_start       = 0x4803e000,
-                .pa_end         = 0x4803e07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_per -> timer9 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
        .master         = &omap44xx_l4_per_hwmod,
        .slave          = &omap44xx_timer9_hwmod,
        .clk            = "l4_div_ck",
-        .addr           = omap44xx_timer9_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
-        {
-                .pa_start       = 0x48086000,
-                .pa_end         = 0x4808607f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_per -> timer10 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
        .master         = &omap44xx_l4_per_hwmod,
        .slave          = &omap44xx_timer10_hwmod,
        .clk            = "l4_div_ck",
-        .addr           = omap44xx_timer10_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
-        {
-                .pa_start       = 0x48088000,
-                .pa_end         = 0x4808807f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_per -> timer11 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
        .master         = &omap44xx_l4_per_hwmod,
        .slave          = &omap44xx_timer11_hwmod,
        .clk            = "l4_div_ck",
-        .addr           = omap44xx_timer11_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
-        {
-                .pa_start       = 0x4806a000,
-                .pa_end         = 0x4806a0ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_per -> uart1 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
        .master         = &omap44xx_l4_per_hwmod,
        .slave          = &omap44xx_uart1_hwmod,
        .clk            = "l4_div_ck",
-        .addr           = omap44xx_uart1_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
-        {
-                .pa_start       = 0x4806c000,
-                .pa_end         = 0x4806c0ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_per -> uart2 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
        .master         = &omap44xx_l4_per_hwmod,
        .slave          = &omap44xx_uart2_hwmod,
        .clk            = "l4_div_ck",
-        .addr           = omap44xx_uart2_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
-        {
-                .pa_start       = 0x48020000,
-                .pa_end         = 0x480200ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_per -> uart3 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
        .master         = &omap44xx_l4_per_hwmod,
        .slave          = &omap44xx_uart3_hwmod,
        .clk            = "l4_div_ck",
-        .addr           = omap44xx_uart3_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
-        {
-                .pa_start       = 0x4806e000,
-                .pa_end         = 0x4806e0ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_per -> uart4 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
        .master         = &omap44xx_l4_per_hwmod,
        .slave          = &omap44xx_uart4_hwmod,
        .clk            = "l4_div_ck",
-        .addr           = omap44xx_uart4_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
-        {
-                .pa_start       = 0x4a0a9000,
-                .pa_end         = 0x4a0a93ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_cfg -> usb_host_fs */
 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
        .master         = &omap44xx_l4_cfg_hwmod,
        .slave          = &omap44xx_usb_host_fs_hwmod,
        .clk            = "l4_div_ck",
-        .addr           = omap44xx_usb_host_fs_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
-        {
-                .name           = "uhh",
-                .pa_start       = 0x4a064000,
-                .pa_end         = 0x4a0647ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        {
-                .name           = "ohci",
-                .pa_start       = 0x4a064800,
-                .pa_end         = 0x4a064bff,
-        },
-        {
-                .name           = "ehci",
-                .pa_start       = 0x4a064c00,
-                .pa_end         = 0x4a064fff,
-        },
-        {}
-};
 /* l4_cfg -> usb_host_hs */
 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
        .master         = &omap44xx_l4_cfg_hwmod,
        .slave          = &omap44xx_usb_host_hs_hwmod,
        .clk            = "l4_div_ck",
-        .addr           = omap44xx_usb_host_hs_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
-        {
-                .pa_start       = 0x4a0ab000,
-                .pa_end         = 0x4a0ab7ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_cfg -> usb_otg_hs */
 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
        .master         = &omap44xx_l4_cfg_hwmod,
        .slave          = &omap44xx_usb_otg_hs_hwmod,
        .clk            = "l4_div_ck",
-        .addr           = omap44xx_usb_otg_hs_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
-        {
-                .name           = "tll",
-                .pa_start       = 0x4a062000,
-                .pa_end         = 0x4a063fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        {}
-};
 /* l4_cfg -> usb_tll_hs */
 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
        .master         = &omap44xx_l4_cfg_hwmod,
        .slave          = &omap44xx_usb_tll_hs_hwmod,
        .clk            = "l4_div_ck",
-        .addr           = omap44xx_usb_tll_hs_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
-        {
-                .pa_start       = 0x4a314000,
-                .pa_end         = 0x4a31407f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_wkup -> wd_timer2 */
 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
        .master         = &omap44xx_l4_wkup_hwmod,
        .slave          = &omap44xx_wd_timer2_hwmod,
        .clk            = "l4_wkup_clk_mux_ck",
-        .addr           = omap44xx_wd_timer2_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
@@ -6290,14 +4775,25 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
        .user           = OCP_USER_SDMA,
 };
+/* mpu -> emif1 */
+static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
+        .master         = &omap44xx_mpu_hwmod,
+        .slave          = &omap44xx_emif1_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* mpu -> emif2 */
+static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
+        .master         = &omap44xx_mpu_hwmod,
+        .slave          = &omap44xx_emif2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
-        &omap44xx_c2c__c2c_target_fw,
-        &omap44xx_l4_cfg__c2c_target_fw,
        &omap44xx_l3_main_1__dmm,
        &omap44xx_mpu__dmm,
-        &omap44xx_c2c__emif_fw,
-        &omap44xx_dmm__emif_fw,
-        &omap44xx_l4_cfg__emif_fw,
        &omap44xx_iva__l3_instr,
        &omap44xx_l3_main_3__l3_instr,
        &omap44xx_ocp_wp_noc__l3_instr,
@@ -6308,7 +4804,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
        &omap44xx_mmc1__l3_main_1,
        &omap44xx_mmc2__l3_main_1,
        &omap44xx_mpu__l3_main_1,
-        &omap44xx_c2c_target_fw__l3_main_2,
        &omap44xx_debugss__l3_main_2,
        &omap44xx_dma_system__l3_main_2,
        &omap44xx_fdif__l3_main_2,
@@ -6364,8 +4859,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
        &omap44xx_l3_main_2__dss_venc,
        &omap44xx_l4_per__dss_venc,
        &omap44xx_l4_per__elm,
-        &omap44xx_emif_fw__emif1,
-        &omap44xx_emif_fw__emif2,
        &omap44xx_l4_cfg__fdif,
        &omap44xx_l4_wkup__gpio1,
        &omap44xx_l4_per__gpio2,
@@ -6450,6 +4943,8 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
        &omap44xx_l4_wkup__wd_timer2,
        &omap44xx_l4_abe__wd_timer3,
        &omap44xx_l4_abe__wd_timer3_dma,
+        &omap44xx_mpu__emif1,
+        &omap44xx_mpu__emif2,
        NULL,
 };
diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
new file mode 100644
index 000000000000..3c70f5c1860f
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
@@ -0,0 +1,2151 @@
+/*
+ * Hardware modules present on the OMAP54xx chips
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley
+ * Benoit Cousson
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/io.h>
+#include <linux/platform_data/gpio-omap.h>
+#include <linux/power/smartreflex.h>
+#include <linux/i2c-omap.h>
+#include <linux/omap-dma.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
+#include <plat/dmtimer.h>
+#include "omap_hwmod.h"
+#include "omap_hwmod_common_data.h"
+#include "cm1_54xx.h"
+#include "cm2_54xx.h"
+#include "prm54xx.h"
+#include "prm-regbits-54xx.h"
+#include "i2c.h"
+#include "mmc.h"
+#include "wd_timer.h"
+/* Base offset for all OMAP5 interrupts external to MPUSS */
+#define OMAP54XX_IRQ_GIC_START  32
+/* Base offset for all OMAP5 dma requests */
+#define OMAP54XX_DMA_REQ_START  1
+/*
+ * IP blocks
+ */
+/*
+ * 'dmm' class
+ * instance(s): dmm
+ */
+static struct omap_hwmod_class omap54xx_dmm_hwmod_class = {
+        .name   = "dmm",
+};
+/* dmm */
+static struct omap_hwmod omap54xx_dmm_hwmod = {
+        .name           = "dmm",
+        .class          = &omap54xx_dmm_hwmod_class,
+        .clkdm_name     = "emif_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET,
+                },
+        },
+};
+/*
+ * 'l3' class
+ * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
+ */
+static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
+        .name   = "l3",
+};
+/* l3_instr */
+static struct omap_hwmod omap54xx_l3_instr_hwmod = {
+        .name           = "l3_instr",
+        .class          = &omap54xx_l3_hwmod_class,
+        .clkdm_name     = "l3instr_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+};
+/* l3_main_1 */
+static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
+        .name           = "l3_main_1",
+        .class          = &omap54xx_l3_hwmod_class,
+        .clkdm_name     = "l3main1_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
+                },
+        },
+};
+/* l3_main_2 */
+static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
+        .name           = "l3_main_2",
+        .class          = &omap54xx_l3_hwmod_class,
+        .clkdm_name     = "l3main2_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
+                },
+        },
+};
+/* l3_main_3 */
+static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
+        .name           = "l3_main_3",
+        .class          = &omap54xx_l3_hwmod_class,
+        .clkdm_name     = "l3instr_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+};
+/*
+ * 'l4' class
+ * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
+ */
+static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
+        .name   = "l4",
+};
+/* l4_abe */
+static struct omap_hwmod omap54xx_l4_abe_hwmod = {
+        .name           = "l4_abe",
+        .class          = &omap54xx_l4_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET,
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
+};
+/* l4_cfg */
+static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
+        .name           = "l4_cfg",
+        .class          = &omap54xx_l4_hwmod_class,
+        .clkdm_name     = "l4cfg_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
+                },
+        },
+};
+/* l4_per */
+static struct omap_hwmod omap54xx_l4_per_hwmod = {
+        .name           = "l4_per",
+        .class          = &omap54xx_l4_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
+                },
+        },
+};
+/* l4_wkup */
+static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
+        .name           = "l4_wkup",
+        .class          = &omap54xx_l4_hwmod_class,
+        .clkdm_name     = "wkupaon_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
+                },
+        },
+};
+/*
+ * 'mpu_bus' class
+ * instance(s): mpu_private
+ */
+static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
+        .name   = "mpu_bus",
+};
+/* mpu_private */
+static struct omap_hwmod omap54xx_mpu_private_hwmod = {
+        .name           = "mpu_private",
+        .class          = &omap54xx_mpu_bus_hwmod_class,
+        .clkdm_name     = "mpu_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
+};
+/*
+ * 'counter' class
+ * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
+ */
+static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = SYSC_HAS_SIDLEMODE,
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+static struct omap_hwmod_class omap54xx_counter_hwmod_class = {
+        .name   = "counter",
+        .sysc   = &omap54xx_counter_sysc,
+};
+/* counter_32k */
+static struct omap_hwmod omap54xx_counter_32k_hwmod = {
+        .name           = "counter_32k",
+        .class          = &omap54xx_counter_hwmod_class,
+        .clkdm_name     = "wkupaon_clkdm",
+        .flags          = HWMOD_SWSUP_SIDLE,
+        .main_clk       = "wkupaon_iclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
+                },
+        },
+};
+/*
+ * 'dma' class
+ * dma controller for data exchange between memory to memory (i.e. internal or
+ * external memory) and gp peripherals to memory or memory to gp peripherals
+ */
+static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x002c,
+        .syss_offs      = 0x0028,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+static struct omap_hwmod_class omap54xx_dma_hwmod_class = {
+        .name   = "dma",
+        .sysc   = &omap54xx_dma_sysc,
+};
+/* dma dev_attr */
+static struct omap_dma_dev_attr dma_dev_attr = {
+        .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
+                          IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
+        .lch_count      = 32,
+};
+/* dma_system */
+static struct omap_hwmod_irq_info omap54xx_dma_system_irqs[] = {
+        { .name = "0", .irq = 12 + OMAP54XX_IRQ_GIC_START },
+        { .name = "1", .irq = 13 + OMAP54XX_IRQ_GIC_START },
+        { .name = "2", .irq = 14 + OMAP54XX_IRQ_GIC_START },
+        { .name = "3", .irq = 15 + OMAP54XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+static struct omap_hwmod omap54xx_dma_system_hwmod = {
+        .name           = "dma_system",
+        .class          = &omap54xx_dma_hwmod_class,
+        .clkdm_name     = "dma_clkdm",
+        .mpu_irqs       = omap54xx_dma_system_irqs,
+        .main_clk       = "l3_iclk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
+                },
+        },
+        .dev_attr       = &dma_dev_attr,
+};
+/*
+ * 'dmic' class
+ * digital microphone controller
+ */
+static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+static struct omap_hwmod_class omap54xx_dmic_hwmod_class = {
+        .name   = "dmic",
+        .sysc   = &omap54xx_dmic_sysc,
+};
+/* dmic */
+static struct omap_hwmod omap54xx_dmic_hwmod = {
+        .name           = "dmic",
+        .class          = &omap54xx_dmic_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
+        .main_clk       = "dmic_gfclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/*
+ * 'emif' class
+ * external memory interface no1 (wrapper)
+ */
+static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
+        .rev_offs       = 0x0000,
+};
+static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
+        .name   = "emif",
+        .sysc   = &omap54xx_emif_sysc,
+};
+/* emif1 */
+static struct omap_hwmod omap54xx_emif1_hwmod = {
+        .name           = "emif1",
+        .class          = &omap54xx_emif_hwmod_class,
+        .clkdm_name     = "emif_clkdm",
+        .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+        .main_clk       = "dpll_core_h11x2_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+};
+/* emif2 */
+static struct omap_hwmod omap54xx_emif2_hwmod = {
+        .name           = "emif2",
+        .class          = &omap54xx_emif_hwmod_class,
+        .clkdm_name     = "emif_clkdm",
+        .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+        .main_clk       = "dpll_core_h11x2_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+};
+/*
+ * 'gpio' class
+ * general purpose io module
+ */
+static struct omap_hwmod_class_sysconfig omap54xx_gpio_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0114,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+static struct omap_hwmod_class omap54xx_gpio_hwmod_class = {
+        .name   = "gpio",
+        .sysc   = &omap54xx_gpio_sysc,
+        .rev    = 2,
+};
+/* gpio dev_attr */
+static struct omap_gpio_dev_attr gpio_dev_attr = {
+        .bank_width     = 32,
+        .dbck_flag      = true,
+};
+/* gpio1 */
+static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio1_dbclk" },
+};
+static struct omap_hwmod omap54xx_gpio1_hwmod = {
+        .name           = "gpio1",
+        .class          = &omap54xx_gpio_hwmod_class,
+        .clkdm_name     = "wkupaon_clkdm",
+        .main_clk       = "wkupaon_iclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = gpio1_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+/* gpio2 */
+static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio2_dbclk" },
+};
+static struct omap_hwmod omap54xx_gpio2_hwmod = {
+        .name           = "gpio2",
+        .class          = &omap54xx_gpio_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .main_clk       = "l4_root_clk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = gpio2_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+/* gpio3 */
+static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio3_dbclk" },
+};
+static struct omap_hwmod omap54xx_gpio3_hwmod = {
+        .name           = "gpio3",
+        .class          = &omap54xx_gpio_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .main_clk       = "l4_root_clk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = gpio3_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+/* gpio4 */
+static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio4_dbclk" },
+};
+static struct omap_hwmod omap54xx_gpio4_hwmod = {
+        .name           = "gpio4",
+        .class          = &omap54xx_gpio_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .main_clk       = "l4_root_clk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = gpio4_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+/* gpio5 */
+static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio5_dbclk" },
+};
+static struct omap_hwmod omap54xx_gpio5_hwmod = {
+        .name           = "gpio5",
+        .class          = &omap54xx_gpio_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .main_clk       = "l4_root_clk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = gpio5_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+/* gpio6 */
+static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio6_dbclk" },
+};
+static struct omap_hwmod omap54xx_gpio6_hwmod = {
+        .name           = "gpio6",
+        .class          = &omap54xx_gpio_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .main_clk       = "l4_root_clk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = gpio6_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+/* gpio7 */
+static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio7_dbclk" },
+};
+static struct omap_hwmod omap54xx_gpio7_hwmod = {
+        .name           = "gpio7",
+        .class          = &omap54xx_gpio_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .main_clk       = "l4_root_clk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = gpio7_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio7_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+/* gpio8 */
+static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio8_dbclk" },
+};
+static struct omap_hwmod omap54xx_gpio8_hwmod = {
+        .name           = "gpio8",
+        .class          = &omap54xx_gpio_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .main_clk       = "l4_root_clk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = gpio8_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio8_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+/*
+ * 'i2c' class
+ * multimaster high-speed i2c controller
+ */
+static struct omap_hwmod_class_sysconfig omap54xx_i2c_sysc = {
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0090,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .clockact       = CLOCKACT_TEST_ICLK,
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+static struct omap_hwmod_class omap54xx_i2c_hwmod_class = {
+        .name   = "i2c",
+        .sysc   = &omap54xx_i2c_sysc,
+        .reset  = &omap_i2c_reset,
+        .rev    = OMAP_I2C_IP_VERSION_2,
+};
+/* i2c dev_attr */
+static struct omap_i2c_dev_attr i2c_dev_attr = {
+        .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
+};
+/* i2c1 */
+static struct omap_hwmod omap54xx_i2c1_hwmod = {
+        .name           = "i2c1",
+        .class          = &omap54xx_i2c_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+        .main_clk       = "func_96m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &i2c_dev_attr,
+};
+/* i2c2 */
+static struct omap_hwmod omap54xx_i2c2_hwmod = {
+        .name           = "i2c2",
+        .class          = &omap54xx_i2c_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+        .main_clk       = "func_96m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &i2c_dev_attr,
+};
+/* i2c3 */
+static struct omap_hwmod omap54xx_i2c3_hwmod = {
+        .name           = "i2c3",
+        .class          = &omap54xx_i2c_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+        .main_clk       = "func_96m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &i2c_dev_attr,
+};
+/* i2c4 */
+static struct omap_hwmod omap54xx_i2c4_hwmod = {
+        .name           = "i2c4",
+        .class          = &omap54xx_i2c_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+        .main_clk       = "func_96m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &i2c_dev_attr,
+};
+/* i2c5 */
+static struct omap_hwmod omap54xx_i2c5_hwmod = {
+        .name           = "i2c5",
+        .class          = &omap54xx_i2c_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+        .main_clk       = "func_96m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &i2c_dev_attr,
+};
+/*
+ * 'kbd' class
+ * keyboard controller
+ */
+static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+static struct omap_hwmod_class omap54xx_kbd_hwmod_class = {
+        .name   = "kbd",
+        .sysc   = &omap54xx_kbd_sysc,
+};
+/* kbd */
+static struct omap_hwmod omap54xx_kbd_hwmod = {
+        .name           = "kbd",
+        .class          = &omap54xx_kbd_hwmod_class,
+        .clkdm_name     = "wkupaon_clkdm",
+        .main_clk       = "sys_32k_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/*
+ * 'mcbsp' class
+ * multi channel buffered serial port controller
+ */
+static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc = {
+        .sysc_offs      = 0x008c,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = {
+        .name   = "mcbsp",
+        .sysc   = &omap54xx_mcbsp_sysc,
+        .rev    = MCBSP_CONFIG_TYPE4,
+};
+/* mcbsp1 */
+static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
+        { .role = "pad_fck", .clk = "pad_clks_ck" },
+        { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
+};
+static struct omap_hwmod omap54xx_mcbsp1_hwmod = {
+        .name           = "mcbsp1",
+        .class          = &omap54xx_mcbsp_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
+        .main_clk       = "mcbsp1_gfclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = mcbsp1_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
+};
+/* mcbsp2 */
+static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
+        { .role = "pad_fck", .clk = "pad_clks_ck" },
+        { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
+};
+static struct omap_hwmod omap54xx_mcbsp2_hwmod = {
+        .name           = "mcbsp2",
+        .class          = &omap54xx_mcbsp_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
+        .main_clk       = "mcbsp2_gfclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = mcbsp2_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
+};
+/* mcbsp3 */
+static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
+        { .role = "pad_fck", .clk = "pad_clks_ck" },
+        { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
+};
+static struct omap_hwmod omap54xx_mcbsp3_hwmod = {
+        .name           = "mcbsp3",
+        .class          = &omap54xx_mcbsp_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
+        .main_clk       = "mcbsp3_gfclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = mcbsp3_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
+};
+/*
+ * 'mcpdm' class
+ * multi channel pdm controller (proprietary interface with phoenix power
+ * ic)
+ */
+static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class = {
+        .name   = "mcpdm",
+        .sysc   = &omap54xx_mcpdm_sysc,
+};
+/* mcpdm */
+static struct omap_hwmod omap54xx_mcpdm_hwmod = {
+        .name           = "mcpdm",
+        .class          = &omap54xx_mcpdm_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
+        /*
+         * It's suspected that the McPDM requires an off-chip main
+         * functional clock, controlled via I2C.  This IP block is
+         * currently reset very early during boot, before I2C is
+         * available, so it doesn't seem that we have any choice in
+         * the kernel other than to avoid resetting it.  XXX This is
+         * really a hardware issue workaround: every IP block should
+         * be able to source its main functional clock from either
+         * on-chip or off-chip sources.  McPDM seems to be the only
+         * current exception.
+         */
+        .flags          = HWMOD_EXT_OPT_MAIN_CLK,
+        .main_clk       = "pad_clks_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/*
+ * 'mcspi' class
+ * multichannel serial port interface (mcspi) / master/slave synchronous serial
+ * bus
+ */
+static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+static struct omap_hwmod_class omap54xx_mcspi_hwmod_class = {
+        .name   = "mcspi",
+        .sysc   = &omap54xx_mcspi_sysc,
+        .rev    = OMAP4_MCSPI_REV,
+};
+/* mcspi1 */
+/* mcspi1 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
+        .num_chipselect = 4,
+};
+static struct omap_hwmod omap54xx_mcspi1_hwmod = {
+        .name           = "mcspi1",
+        .class          = &omap54xx_mcspi_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &mcspi1_dev_attr,
+};
+/* mcspi2 */
+/* mcspi2 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
+        .num_chipselect = 2,
+};
+static struct omap_hwmod omap54xx_mcspi2_hwmod = {
+        .name           = "mcspi2",
+        .class          = &omap54xx_mcspi_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &mcspi2_dev_attr,
+};
+/* mcspi3 */
+/* mcspi3 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
+        .num_chipselect = 2,
+};
+static struct omap_hwmod omap54xx_mcspi3_hwmod = {
+        .name           = "mcspi3",
+        .class          = &omap54xx_mcspi_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &mcspi3_dev_attr,
+};
+/* mcspi4 */
+/* mcspi4 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
+        .num_chipselect = 1,
+};
+static struct omap_hwmod omap54xx_mcspi4_hwmod = {
+        .name           = "mcspi4",
+        .class          = &omap54xx_mcspi_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &mcspi4_dev_attr,
+};
+/*
+ * 'mmc' class
+ * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
+ */
+static struct omap_hwmod_class_sysconfig omap54xx_mmc_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
+                           SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+                           MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+static struct omap_hwmod_class omap54xx_mmc_hwmod_class = {
+        .name   = "mmc",
+        .sysc   = &omap54xx_mmc_sysc,
+};
+/* mmc1 */
+static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
+        { .role = "32khz_clk", .clk = "mmc1_32khz_clk" },
+};
+/* mmc1 dev_attr */
+static struct omap_mmc_dev_attr mmc1_dev_attr = {
+        .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+static struct omap_hwmod omap54xx_mmc1_hwmod = {
+        .name           = "mmc1",
+        .class          = &omap54xx_mmc_hwmod_class,
+        .clkdm_name     = "l3init_clkdm",
+        .main_clk       = "mmc1_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = mmc1_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mmc1_opt_clks),
+        .dev_attr       = &mmc1_dev_attr,
+};
+/* mmc2 */
+static struct omap_hwmod omap54xx_mmc2_hwmod = {
+        .name           = "mmc2",
+        .class          = &omap54xx_mmc_hwmod_class,
+        .clkdm_name     = "l3init_clkdm",
+        .main_clk       = "mmc2_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* mmc3 */
+static struct omap_hwmod omap54xx_mmc3_hwmod = {
+        .name           = "mmc3",
+        .class          = &omap54xx_mmc_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* mmc4 */
+static struct omap_hwmod omap54xx_mmc4_hwmod = {
+        .name           = "mmc4",
+        .class          = &omap54xx_mmc_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* mmc5 */
+static struct omap_hwmod omap54xx_mmc5_hwmod = {
+        .name           = "mmc5",
+        .class          = &omap54xx_mmc_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_96m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/*
+ * 'mpu' class
+ * mpu sub-system
+ */
+static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
+        .name   = "mpu",
+};
+/* mpu */
+static struct omap_hwmod omap54xx_mpu_hwmod = {
+        .name           = "mpu",
+        .class          = &omap54xx_mpu_hwmod_class,
+        .clkdm_name     = "mpu_clkdm",
+        .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+        .main_clk       = "dpll_mpu_m2_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
+                },
+        },
+};
+/*
+ * 'timer' class
+ * general purpose timer module with accurate 1ms tick
+ * This class contains several variants: ['timer_1ms', 'timer']
+ */
+static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+        .clockact       = CLOCKACT_TEST_ICLK,
+};
+static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = {
+        .name   = "timer",
+        .sysc   = &omap54xx_timer_1ms_sysc,
+};
+static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+static struct omap_hwmod_class omap54xx_timer_hwmod_class = {
+        .name   = "timer",
+        .sysc   = &omap54xx_timer_sysc,
+};
+/* timer1 */
+static struct omap_hwmod omap54xx_timer1_hwmod = {
+        .name           = "timer1",
+        .class          = &omap54xx_timer_1ms_hwmod_class,
+        .clkdm_name     = "wkupaon_clkdm",
+        .main_clk       = "timer1_gfclk_mux",
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* timer2 */
+static struct omap_hwmod omap54xx_timer2_hwmod = {
+        .name           = "timer2",
+        .class          = &omap54xx_timer_1ms_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "timer2_gfclk_mux",
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* timer3 */
+static struct omap_hwmod omap54xx_timer3_hwmod = {
+        .name           = "timer3",
+        .class          = &omap54xx_timer_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "timer3_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* timer4 */
+static struct omap_hwmod omap54xx_timer4_hwmod = {
+        .name           = "timer4",
+        .class          = &omap54xx_timer_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "timer4_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* timer5 */
+static struct omap_hwmod omap54xx_timer5_hwmod = {
+        .name           = "timer5",
+        .class          = &omap54xx_timer_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
+        .main_clk       = "timer5_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* timer6 */
+static struct omap_hwmod omap54xx_timer6_hwmod = {
+        .name           = "timer6",
+        .class          = &omap54xx_timer_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
+        .main_clk       = "timer6_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* timer7 */
+static struct omap_hwmod omap54xx_timer7_hwmod = {
+        .name           = "timer7",
+        .class          = &omap54xx_timer_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
+        .main_clk       = "timer7_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* timer8 */
+static struct omap_hwmod omap54xx_timer8_hwmod = {
+        .name           = "timer8",
+        .class          = &omap54xx_timer_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
+        .main_clk       = "timer8_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* timer9 */
+static struct omap_hwmod omap54xx_timer9_hwmod = {
+        .name           = "timer9",
+        .class          = &omap54xx_timer_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "timer9_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* timer10 */
+static struct omap_hwmod omap54xx_timer10_hwmod = {
+        .name           = "timer10",
+        .class          = &omap54xx_timer_1ms_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "timer10_gfclk_mux",
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* timer11 */
+static struct omap_hwmod omap54xx_timer11_hwmod = {
+        .name           = "timer11",
+        .class          = &omap54xx_timer_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "timer11_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/*
+ * 'uart' class
+ * universal asynchronous receiver/transmitter (uart)
+ */
+static struct omap_hwmod_class_sysconfig omap54xx_uart_sysc = {
+        .rev_offs       = 0x0050,
+        .sysc_offs      = 0x0054,
+        .syss_offs      = 0x0058,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+static struct omap_hwmod_class omap54xx_uart_hwmod_class = {
+        .name   = "uart",
+        .sysc   = &omap54xx_uart_sysc,
+};
+/* uart1 */
+static struct omap_hwmod omap54xx_uart1_hwmod = {
+        .name           = "uart1",
+        .class          = &omap54xx_uart_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* uart2 */
+static struct omap_hwmod omap54xx_uart2_hwmod = {
+        .name           = "uart2",
+        .class          = &omap54xx_uart_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* uart3 */
+static struct omap_hwmod omap54xx_uart3_hwmod = {
+        .name           = "uart3",
+        .class          = &omap54xx_uart_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = DEBUG_OMAP4UART3_FLAGS,
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* uart4 */
+static struct omap_hwmod omap54xx_uart4_hwmod = {
+        .name           = "uart4",
+        .class          = &omap54xx_uart_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = DEBUG_OMAP4UART4_FLAGS,
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* uart5 */
+static struct omap_hwmod omap54xx_uart5_hwmod = {
+        .name           = "uart5",
+        .class          = &omap54xx_uart_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* uart6 */
+static struct omap_hwmod omap54xx_uart6_hwmod = {
+        .name           = "uart6",
+        .class          = &omap54xx_uart_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/*
+ * 'usb_otg_ss' class
+ * 2.0 super speed (usb_otg_ss) controller
+ */
+static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
+                           SYSC_HAS_SIDLEMODE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+                           MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = {
+        .name   = "usb_otg_ss",
+        .sysc   = &omap54xx_usb_otg_ss_sysc,
+};
+/* usb_otg_ss */
+static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = {
+        { .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" },
+};
+static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = {
+        .name           = "usb_otg_ss",
+        .class          = &omap54xx_usb_otg_ss_hwmod_class,
+        .clkdm_name     = "l3init_clkdm",
+        .flags          = HWMOD_SWSUP_SIDLE,
+        .main_clk       = "dpll_core_h13x2_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = usb_otg_ss_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss_opt_clks),
+};
+/*
+ * 'wd_timer' class
+ * 32-bit watchdog upward counter that generates a pulse on the reset pin on
+ * overflow condition
+ */
+static struct omap_hwmod_class_sysconfig omap54xx_wd_timer_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+static struct omap_hwmod_class omap54xx_wd_timer_hwmod_class = {
+        .name           = "wd_timer",
+        .sysc           = &omap54xx_wd_timer_sysc,
+        .pre_shutdown   = &omap2_wd_timer_disable,
+};
+/* wd_timer2 */
+static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
+        .name           = "wd_timer2",
+        .class          = &omap54xx_wd_timer_hwmod_class,
+        .clkdm_name     = "wkupaon_clkdm",
+        .main_clk       = "sys_32k_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/*
+ * Interfaces
+ */
+/* l3_main_1 -> dmm */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = {
+        .master         = &omap54xx_l3_main_1_hwmod,
+        .slave          = &omap54xx_dmm_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_SDMA,
+};
+/* l3_main_3 -> l3_instr */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
+        .master         = &omap54xx_l3_main_3_hwmod,
+        .slave          = &omap54xx_l3_instr_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l3_main_2 -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
+        .master         = &omap54xx_l3_main_2_hwmod,
+        .slave          = &omap54xx_l3_main_1_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_cfg -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
+        .master         = &omap54xx_l4_cfg_hwmod,
+        .slave          = &omap54xx_l3_main_1_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* mpu -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
+        .master         = &omap54xx_mpu_hwmod,
+        .slave          = &omap54xx_l3_main_1_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU,
+};
+/* l3_main_1 -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
+        .master         = &omap54xx_l3_main_1_hwmod,
+        .slave          = &omap54xx_l3_main_2_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU,
+};
+/* l4_cfg -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
+        .master         = &omap54xx_l4_cfg_hwmod,
+        .slave          = &omap54xx_l3_main_2_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l3_main_1 -> l3_main_3 */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
+        .master         = &omap54xx_l3_main_1_hwmod,
+        .slave          = &omap54xx_l3_main_3_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU,
+};
+/* l3_main_2 -> l3_main_3 */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
+        .master         = &omap54xx_l3_main_2_hwmod,
+        .slave          = &omap54xx_l3_main_3_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_cfg -> l3_main_3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
+        .master         = &omap54xx_l4_cfg_hwmod,
+        .slave          = &omap54xx_l3_main_3_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l3_main_1 -> l4_abe */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = {
+        .master         = &omap54xx_l3_main_1_hwmod,
+        .slave          = &omap54xx_l4_abe_hwmod,
+        .clk            = "abe_iclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* mpu -> l4_abe */
+static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = {
+        .master         = &omap54xx_mpu_hwmod,
+        .slave          = &omap54xx_l4_abe_hwmod,
+        .clk            = "abe_iclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l3_main_1 -> l4_cfg */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
+        .master         = &omap54xx_l3_main_1_hwmod,
+        .slave          = &omap54xx_l4_cfg_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l3_main_2 -> l4_per */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
+        .master         = &omap54xx_l3_main_2_hwmod,
+        .slave          = &omap54xx_l4_per_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l3_main_1 -> l4_wkup */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
+        .master         = &omap54xx_l3_main_1_hwmod,
+        .slave          = &omap54xx_l4_wkup_hwmod,
+        .clk            = "wkupaon_iclk_mux",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* mpu -> mpu_private */
+static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
+        .master         = &omap54xx_mpu_hwmod,
+        .slave          = &omap54xx_mpu_private_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_wkup -> counter_32k */
+static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = {
+        .master         = &omap54xx_l4_wkup_hwmod,
+        .slave          = &omap54xx_counter_32k_hwmod,
+        .clk            = "wkupaon_iclk_mux",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap54xx_dma_system_addrs[] = {
+        {
+                .pa_start       = 0x4a056000,
+                .pa_end         = 0x4a056fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_cfg -> dma_system */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system = {
+        .master         = &omap54xx_l4_cfg_hwmod,
+        .slave          = &omap54xx_dma_system_hwmod,
+        .clk            = "l4_root_clk_div",
+        .addr           = omap54xx_dma_system_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_abe -> dmic */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic = {
+        .master         = &omap54xx_l4_abe_hwmod,
+        .slave          = &omap54xx_dmic_hwmod,
+        .clk            = "abe_iclk",
+        .user           = OCP_USER_MPU,
+};
+/* mpu -> emif1 */
+static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
+        .master         = &omap54xx_mpu_hwmod,
+        .slave          = &omap54xx_emif1_hwmod,
+        .clk            = "dpll_core_h11x2_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* mpu -> emif2 */
+static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
+        .master         = &omap54xx_mpu_hwmod,
+        .slave          = &omap54xx_emif2_hwmod,
+        .clk            = "dpll_core_h11x2_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_wkup -> gpio1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_wkup__gpio1 = {
+        .master         = &omap54xx_l4_wkup_hwmod,
+        .slave          = &omap54xx_gpio1_hwmod,
+        .clk            = "wkupaon_iclk_mux",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per -> gpio2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio2 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_gpio2_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per -> gpio3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio3 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_gpio3_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per -> gpio4 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio4 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_gpio4_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per -> gpio5 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio5 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_gpio5_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per -> gpio6 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio6 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_gpio6_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per -> gpio7 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio7 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_gpio7_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per -> gpio8 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio8 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_gpio8_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per -> i2c1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c1 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_i2c1_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per -> i2c2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c2 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_i2c2_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per -> i2c3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c3 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_i2c3_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per -> i2c4 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c4 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_i2c4_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per -> i2c5 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c5 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_i2c5_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_wkup -> kbd */
+static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = {
+        .master         = &omap54xx_l4_wkup_hwmod,
+        .slave          = &omap54xx_kbd_hwmod,
+        .clk            = "wkupaon_iclk_mux",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_abe -> mcbsp1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = {
+        .master         = &omap54xx_l4_abe_hwmod,
+        .slave          = &omap54xx_mcbsp1_hwmod,
+        .clk            = "abe_iclk",
+        .user           = OCP_USER_MPU,
+};
+/* l4_abe -> mcbsp2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp2 = {
+        .master         = &omap54xx_l4_abe_hwmod,
+        .slave          = &omap54xx_mcbsp2_hwmod,
+        .clk            = "abe_iclk",
+        .user           = OCP_USER_MPU,
+};
+/* l4_abe -> mcbsp3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp3 = {
+        .master         = &omap54xx_l4_abe_hwmod,
+        .slave          = &omap54xx_mcbsp3_hwmod,
+        .clk            = "abe_iclk",
+        .user           = OCP_USER_MPU,
+};
+/* l4_abe -> mcpdm */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm = {
+        .master         = &omap54xx_l4_abe_hwmod,
+        .slave          = &omap54xx_mcpdm_hwmod,
+        .clk            = "abe_iclk",
+        .user           = OCP_USER_MPU,
+};
+/* l4_per -> mcspi1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi1 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_mcspi1_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per -> mcspi2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi2 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_mcspi2_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per -> mcspi3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi3 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_mcspi3_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per -> mcspi4 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi4 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_mcspi4_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per -> mmc1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc1 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_mmc1_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per -> mmc2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc2 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_mmc2_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per -> mmc3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc3 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_mmc3_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per -> mmc4 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc4 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_mmc4_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per -> mmc5 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc5 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_mmc5_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_cfg -> mpu */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
+        .master         = &omap54xx_l4_cfg_hwmod,
+        .slave          = &omap54xx_mpu_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_wkup -> timer1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
+        .master         = &omap54xx_l4_wkup_hwmod,
+        .slave          = &omap54xx_timer1_hwmod,
+        .clk            = "wkupaon_iclk_mux",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per -> timer2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__timer2 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_timer2_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per -> timer3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__timer3 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_timer3_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per -> timer4 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__timer4 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_timer4_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_abe -> timer5 */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5 = {
+        .master         = &omap54xx_l4_abe_hwmod,
+        .slave          = &omap54xx_timer5_hwmod,
+        .clk            = "abe_iclk",
+        .user           = OCP_USER_MPU,
+};
+/* l4_abe -> timer6 */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6 = {
+        .master         = &omap54xx_l4_abe_hwmod,
+        .slave          = &omap54xx_timer6_hwmod,
+        .clk            = "abe_iclk",
+        .user           = OCP_USER_MPU,
+};
+/* l4_abe -> timer7 */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7 = {
+        .master         = &omap54xx_l4_abe_hwmod,
+        .slave          = &omap54xx_timer7_hwmod,
+        .clk            = "abe_iclk",
+        .user           = OCP_USER_MPU,
+};
+/* l4_abe -> timer8 */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8 = {
+        .master         = &omap54xx_l4_abe_hwmod,
+        .slave          = &omap54xx_timer8_hwmod,
+        .clk            = "abe_iclk",
+        .user           = OCP_USER_MPU,
+};
+/* l4_per -> timer9 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__timer9 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_timer9_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per -> timer10 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__timer10 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_timer10_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per -> timer11 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_timer11_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per -> uart1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__uart1 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_uart1_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per -> uart2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__uart2 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_uart2_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per -> uart3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__uart3 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_uart3_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per -> uart4 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__uart4 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_uart4_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per -> uart5 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__uart5 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_uart5_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per -> uart6 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__uart6 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_uart6_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_cfg -> usb_otg_ss */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = {
+        .master         = &omap54xx_l4_cfg_hwmod,
+        .slave          = &omap54xx_usb_otg_ss_hwmod,
+        .clk            = "dpll_core_h13x2_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_wkup -> wd_timer2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_wkup__wd_timer2 = {
+        .master         = &omap54xx_l4_wkup_hwmod,
+        .slave          = &omap54xx_wd_timer2_hwmod,
+        .clk            = "wkupaon_iclk_mux",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
+        &omap54xx_l3_main_1__dmm,
+        &omap54xx_l3_main_3__l3_instr,
+        &omap54xx_l3_main_2__l3_main_1,
+        &omap54xx_l4_cfg__l3_main_1,
+        &omap54xx_mpu__l3_main_1,
+        &omap54xx_l3_main_1__l3_main_2,
+        &omap54xx_l4_cfg__l3_main_2,
+        &omap54xx_l3_main_1__l3_main_3,
+        &omap54xx_l3_main_2__l3_main_3,
+        &omap54xx_l4_cfg__l3_main_3,
+        &omap54xx_l3_main_1__l4_abe,
+        &omap54xx_mpu__l4_abe,
+        &omap54xx_l3_main_1__l4_cfg,
+        &omap54xx_l3_main_2__l4_per,
+        &omap54xx_l3_main_1__l4_wkup,
+        &omap54xx_mpu__mpu_private,
+        &omap54xx_l4_wkup__counter_32k,
+        &omap54xx_l4_cfg__dma_system,
+        &omap54xx_l4_abe__dmic,
+        &omap54xx_mpu__emif1,
+        &omap54xx_mpu__emif2,
+        &omap54xx_l4_wkup__gpio1,
+        &omap54xx_l4_per__gpio2,
+        &omap54xx_l4_per__gpio3,
+        &omap54xx_l4_per__gpio4,
+        &omap54xx_l4_per__gpio5,
+        &omap54xx_l4_per__gpio6,
+        &omap54xx_l4_per__gpio7,
+        &omap54xx_l4_per__gpio8,
+        &omap54xx_l4_per__i2c1,
+        &omap54xx_l4_per__i2c2,
+        &omap54xx_l4_per__i2c3,
+        &omap54xx_l4_per__i2c4,
+        &omap54xx_l4_per__i2c5,
+        &omap54xx_l4_wkup__kbd,
+        &omap54xx_l4_abe__mcbsp1,
+        &omap54xx_l4_abe__mcbsp2,
+        &omap54xx_l4_abe__mcbsp3,
+        &omap54xx_l4_abe__mcpdm,
+        &omap54xx_l4_per__mcspi1,
+        &omap54xx_l4_per__mcspi2,
+        &omap54xx_l4_per__mcspi3,
+        &omap54xx_l4_per__mcspi4,
+        &omap54xx_l4_per__mmc1,
+        &omap54xx_l4_per__mmc2,
+        &omap54xx_l4_per__mmc3,
+        &omap54xx_l4_per__mmc4,
+        &omap54xx_l4_per__mmc5,
+        &omap54xx_l4_cfg__mpu,
+        &omap54xx_l4_wkup__timer1,
+        &omap54xx_l4_per__timer2,
+        &omap54xx_l4_per__timer3,
+        &omap54xx_l4_per__timer4,
+        &omap54xx_l4_abe__timer5,
+        &omap54xx_l4_abe__timer6,
+        &omap54xx_l4_abe__timer7,
+        &omap54xx_l4_abe__timer8,
+        &omap54xx_l4_per__timer9,
+        &omap54xx_l4_per__timer10,
+        &omap54xx_l4_per__timer11,
+        &omap54xx_l4_per__uart1,
+        &omap54xx_l4_per__uart2,
+        &omap54xx_l4_per__uart3,
+        &omap54xx_l4_per__uart4,
+        &omap54xx_l4_per__uart5,
+        &omap54xx_l4_per__uart6,
+        &omap54xx_l4_cfg__usb_otg_ss,
+        &omap54xx_l4_wkup__wd_timer2,
+        NULL,
+};
+int __init omap54xx_hwmod_init(void)
+{
+        omap_hwmod_init();
+        return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);
+}
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index a251f87fa2a2..82f0698933d8 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -1,7 +1,7 @@
 /*
- * OMAP4 Power Management Routines
+ * OMAP4+ Power Management Routines
 *
- * Copyright (C) 2010-2011 Texas Instruments, Inc.
+ * Copyright (C) 2010-2013 Texas Instruments, Inc.
 * Rajendra Nayak <rnayak@ti.com>
 * Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
@@ -135,16 +135,16 @@ static void omap_default_idle(void)
 }
 /**
- * omap4_pm_init - Init routine for OMAP4 PM
+ * omap4_init_static_deps - Add OMAP4 static dependencies
 *
- * Initializes all powerdomain and clockdomain target states
+ * Add needed static clockdomain dependencies on OMAP4 devices.
- * and all PRCM settings.
+ * Return: 0 on success or 'err' on failures
 */
-int __init omap4_pm_init(void)
+static inline int omap4_init_static_deps(void)
 {
-        int ret;
        struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm;
        struct clockdomain *ducati_clkdm, *l3_2_clkdm;
+        int ret = 0;
        if (omap_rev() == OMAP4430_REV_ES1_0) {
                WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
@@ -163,7 +163,7 @@ int __init omap4_pm_init(void)
        ret = pwrdm_for_each(pwrdms_setup, NULL);
        if (ret) {
                pr_err("Failed to setup powerdomains\n");
-                goto err2;
+                return ret;
        }
        /*
@@ -171,6 +171,10 @@ int __init omap4_pm_init(void)
         * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
         * expected. The hardware recommendation is to enable static
         * dependencies for these to avoid system lock ups or random crashes.
+         * The L4 wakeup depedency is added to workaround the OCP sync hardware
+         * BUG with 32K synctimer which lead to incorrect timer value read
+         * from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which
+         * are part of L4 wakeup clockdomain.
         */
        mpuss_clkdm = clkdm_lookup("mpuss_clkdm");
        emif_clkdm = clkdm_lookup("l3_emif_clkdm");
@@ -179,7 +183,7 @@ int __init omap4_pm_init(void)
        ducati_clkdm = clkdm_lookup("ducati_clkdm");
        if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) ||
                (!l3_2_clkdm) || (!ducati_clkdm))
-                goto err2;
+                return -EINVAL;
        ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
        ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm);
@@ -188,9 +192,42 @@ int __init omap4_pm_init(void)
        ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
        if (ret) {
                pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 wakeup dependency\n");
+                return -EINVAL;
+        }
+        return ret;
+}
+/**
+ * omap4_pm_init - Init routine for OMAP4+ devices
+ *
+ * Initializes all powerdomain and clockdomain target states
+ * and all PRCM settings.
+ * Return: Returns the error code returned by called functions.
+ */
+int __init omap4_pm_init(void)
+{
+        int ret = 0;
+        if (omap_rev() == OMAP4430_REV_ES1_0) {
+                WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
+                return -ENODEV;
+        }
+        pr_info("Power Management for TI OMAP4+ devices.\n");
+        ret = pwrdm_for_each(pwrdms_setup, NULL);
+        if (ret) {
+                pr_err("Failed to setup powerdomains.\n");
                goto err2;
        }
+        if (cpu_is_omap44xx()) {
+                ret = omap4_init_static_deps();
+                if (ret)
+                        goto err2;
+        }
        ret = omap4_mpuss_init();
        if (ret) {
                pr_err("Failed to initialise OMAP4 MPUSS\n");
@@ -206,7 +243,8 @@ int __init omap4_pm_init(void)
        /* Overwrite the default cpu_do_idle() */
        arm_pm_idle = omap_default_idle;
-        omap4_idle_init();
+        if (cpu_is_omap44xx())
+                omap4_idle_init();
 err2:
        return ret;
diff --git a/arch/arm/mach-omap2/pmu.c b/arch/arm/mach-omap2/pmu.c
index 9ace8eae7ee8..33c8846b4193 100644
--- a/arch/arm/mach-omap2/pmu.c
+++ b/arch/arm/mach-omap2/pmu.c
@@ -54,10 +54,7 @@ static int __init omap2_init_pmu(unsigned oh_num, char *oh_names[])
        WARN(IS_ERR(omap_pmu_dev), "Can't build omap_device for %s.\n",
             dev_name);
-        if (IS_ERR(omap_pmu_dev))
+        return PTR_RET(omap_pmu_dev);
-                return PTR_ERR(omap_pmu_dev);
-        return 0;
 }
 static int __init omap_init_pmu(void)
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 86babd740d41..e233dfcbc186 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -102,6 +102,10 @@ static int _pwrdm_register(struct powerdomain *pwrdm)
        if (_pwrdm_lookup(pwrdm->name))
                return -EEXIST;
+        if (arch_pwrdm && arch_pwrdm->pwrdm_has_voltdm)
+                if (!arch_pwrdm->pwrdm_has_voltdm())
+                        goto skip_voltdm;
        voltdm = voltdm_lookup(pwrdm->voltdm.name);
        if (!voltdm) {
                pr_err("powerdomain: %s: voltagedomain %s does not exist\n",
@@ -111,6 +115,7 @@ static int _pwrdm_register(struct powerdomain *pwrdm)
        pwrdm->voltdm.ptr = voltdm;
        INIT_LIST_HEAD(&pwrdm->voltdm_node);
        voltdm_add_pwrdm(voltdm, pwrdm);
+skip_voltdm:
        spin_lock_init(&pwrdm->_lock);
        list_add(&pwrdm->node, &pwrdm_list);
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index 140c36074fed..e4d7bd6f94b8 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -166,6 +166,7 @@ struct powerdomain {
 * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd
 * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep
 * @pwrdm_wait_transition: Wait for a pd state transition to complete
+ * @pwrdm_has_voltdm: Check if a voltdm association is needed
 *
 * Regarding @pwrdm_set_lowpwrstchange: On the OMAP2 and 3-family
 * chips, a powerdomain's power state is not allowed to directly
@@ -196,6 +197,7 @@ struct pwrdm_ops {
        int     (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm);
        int     (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm);
        int     (*pwrdm_wait_transition)(struct powerdomain *pwrdm);
+        int     (*pwrdm_has_voltdm)(void);
 };
 int pwrdm_register_platform_funcs(struct pwrdm_ops *custom_funcs);
@@ -253,6 +255,7 @@ extern void omap243x_powerdomains_init(void);
 extern void omap3xxx_powerdomains_init(void);
 extern void am33xx_powerdomains_init(void);
 extern void omap44xx_powerdomains_init(void);
+extern void omap54xx_powerdomains_init(void);
 extern struct pwrdm_ops omap2_pwrdm_operations;
 extern struct pwrdm_ops omap3_pwrdm_operations;
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index f0e14e9efe5a..e2d4bd804523 100644
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -336,6 +336,54 @@ static struct powerdomain dpll5_pwrdm = {
        .voltdm           = { .name = "core" },
 };
+static struct powerdomain device_81xx_pwrdm = {
+        .name             = "device_pwrdm",
+        .prcm_offs        = TI81XX_PRM_DEVICE_MOD,
+        .voltdm           = { .name = "core" },
+};
+static struct powerdomain active_816x_pwrdm = {
+        .name             = "active_pwrdm",
+        .prcm_offs        = TI816X_PRM_ACTIVE_MOD,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .voltdm           = { .name = "core" },
+};
+static struct powerdomain default_816x_pwrdm = {
+        .name             = "default_pwrdm",
+        .prcm_offs        = TI81XX_PRM_DEFAULT_MOD,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .voltdm           = { .name = "core" },
+};
+static struct powerdomain ivahd0_816x_pwrdm = {
+        .name             = "ivahd0_pwrdm",
+        .prcm_offs        = TI816X_PRM_IVAHD0_MOD,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .voltdm           = { .name = "mpu_iva" },
+};
+static struct powerdomain ivahd1_816x_pwrdm = {
+        .name             = "ivahd1_pwrdm",
+        .prcm_offs        = TI816X_PRM_IVAHD1_MOD,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .voltdm           = { .name = "mpu_iva" },
+};
+static struct powerdomain ivahd2_816x_pwrdm = {
+        .name             = "ivahd2_pwrdm",
+        .prcm_offs        = TI816X_PRM_IVAHD2_MOD,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .voltdm           = { .name = "mpu_iva" },
+};
+static struct powerdomain sgx_816x_pwrdm = {
+        .name             = "sgx_pwrdm",
+        .prcm_offs        = TI816X_PRM_SGX_MOD,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .voltdm           = { .name = "core" },
+};
 /* As powerdomains are added or removed above, this list must also be changed */
 static struct powerdomain *powerdomains_omap3430_common[] __initdata = {
        &wkup_omap2_pwrdm,
@@ -393,6 +441,17 @@ static struct powerdomain *powerdomains_am35x[] __initdata = {
        NULL
 };
+static struct powerdomain *powerdomains_ti81xx[] __initdata = {
+        &device_81xx_pwrdm,
+        &active_816x_pwrdm,
+        &default_816x_pwrdm,
+        &ivahd0_816x_pwrdm,
+        &ivahd1_816x_pwrdm,
+        &ivahd2_816x_pwrdm,
+        &sgx_816x_pwrdm,
+        NULL
+};
 void __init omap3xxx_powerdomains_init(void)
 {
        unsigned int rev;
@@ -406,6 +465,9 @@ void __init omap3xxx_powerdomains_init(void)
        if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
                pwrdm_register_pwrdms(powerdomains_am35x);
+        } else if (rev == TI8168_REV_ES1_0 || rev == TI8168_REV_ES1_1
+                        || rev == TI8168_REV_ES2_0 || rev == TI8168_REV_ES2_1) {
+                pwrdm_register_pwrdms(powerdomains_ti81xx);
        } else {
                pwrdm_register_pwrdms(powerdomains_omap3430_common);
diff --git a/arch/arm/mach-omap2/powerdomains54xx_data.c b/arch/arm/mach-omap2/powerdomains54xx_data.c
new file mode 100644
index 000000000000..81f8a7cc26ee
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomains54xx_data.c
@@ -0,0 +1,331 @@
+/*
+ * OMAP54XX Power domains framework
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Abhijit Pagare (abhijitpagare@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ * Paul Walmsley (paul@pwsan.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include "powerdomain.h"
+#include "prcm-common.h"
+#include "prcm44xx.h"
+#include "prm-regbits-54xx.h"
+#include "prm54xx.h"
+#include "prcm_mpu54xx.h"
+/* core_54xx_pwrdm: CORE power domain */
+static struct powerdomain core_54xx_pwrdm = {
+        .name             = "core_pwrdm",
+        .voltdm           = { .name = "core" },
+        .prcm_offs        = OMAP54XX_PRM_CORE_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .banks            = 5,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* core_nret_bank */
+                [1] = PWRSTS_OFF_RET,   /* core_ocmram */
+                [2] = PWRSTS_OFF_RET,   /* core_other_bank */
+                [3] = PWRSTS_OFF_RET,   /* ipu_l2ram */
+                [4] = PWRSTS_OFF_RET,   /* ipu_unicache */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* core_nret_bank */
+                [1] = PWRSTS_OFF_RET,   /* core_ocmram */
+                [2] = PWRSTS_OFF_RET,   /* core_other_bank */
+                [3] = PWRSTS_OFF_RET,   /* ipu_l2ram */
+                [4] = PWRSTS_OFF_RET,   /* ipu_unicache */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+/* abe_54xx_pwrdm: Audio back end power domain */
+static struct powerdomain abe_54xx_pwrdm = {
+        .name             = "abe_pwrdm",
+        .voltdm           = { .name = "core" },
+        .prcm_offs        = OMAP54XX_PRM_ABE_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF,
+        .banks            = 2,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* aessmem */
+                [1] = PWRSTS_OFF_RET,   /* periphmem */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* aessmem */
+                [1] = PWRSTS_OFF_RET,   /* periphmem */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+/* coreaon_54xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
+static struct powerdomain coreaon_54xx_pwrdm = {
+        .name             = "coreaon_pwrdm",
+        .voltdm           = { .name = "core" },
+        .prcm_offs        = OMAP54XX_PRM_COREAON_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_ON,
+};
+/* dss_54xx_pwrdm: Display subsystem power domain */
+static struct powerdomain dss_54xx_pwrdm = {
+        .name             = "dss_pwrdm",
+        .voltdm           = { .name = "core" },
+        .prcm_offs        = OMAP54XX_PRM_DSS_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* dss_mem */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* dss_mem */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+/* cpu0_54xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
+static struct powerdomain cpu0_54xx_pwrdm = {
+        .name             = "cpu0_pwrdm",
+        .voltdm           = { .name = "mpu" },
+        .prcm_offs        = OMAP54XX_PRCM_MPU_PRM_C0_INST,
+        .prcm_partition   = OMAP54XX_PRCM_MPU_PARTITION,
+        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* cpu0_l1 */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_ON,        /* cpu0_l1 */
+        },
+};
+/* cpu1_54xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
+static struct powerdomain cpu1_54xx_pwrdm = {
+        .name             = "cpu1_pwrdm",
+        .voltdm           = { .name = "mpu" },
+        .prcm_offs        = OMAP54XX_PRCM_MPU_PRM_C1_INST,
+        .prcm_partition   = OMAP54XX_PRCM_MPU_PARTITION,
+        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* cpu1_l1 */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_ON,        /* cpu1_l1 */
+        },
+};
+/* emu_54xx_pwrdm: Emulation power domain */
+static struct powerdomain emu_54xx_pwrdm = {
+        .name             = "emu_pwrdm",
+        .voltdm           = { .name = "wkup" },
+        .prcm_offs        = OMAP54XX_PRM_EMU_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* emu_bank */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* emu_bank */
+        },
+};
+/* mpu_54xx_pwrdm: Modena processor and the Neon coprocessor power domain */
+static struct powerdomain mpu_54xx_pwrdm = {
+        .name             = "mpu_pwrdm",
+        .voltdm           = { .name = "mpu" },
+        .prcm_offs        = OMAP54XX_PRM_MPU_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .banks            = 2,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* mpu_l2 */
+                [1] = PWRSTS_RET,       /* mpu_ram */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* mpu_l2 */
+                [1] = PWRSTS_OFF_RET,   /* mpu_ram */
+        },
+};
+/* custefuse_54xx_pwrdm: Customer efuse controller power domain */
+static struct powerdomain custefuse_54xx_pwrdm = {
+        .name             = "custefuse_pwrdm",
+        .voltdm           = { .name = "core" },
+        .prcm_offs        = OMAP54XX_PRM_CUSTEFUSE_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+/* dsp_54xx_pwrdm: Tesla processor power domain */
+static struct powerdomain dsp_54xx_pwrdm = {
+        .name             = "dsp_pwrdm",
+        .voltdm           = { .name = "mm" },
+        .prcm_offs        = OMAP54XX_PRM_DSP_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .banks            = 3,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* dsp_edma */
+                [1] = PWRSTS_OFF_RET,   /* dsp_l1 */
+                [2] = PWRSTS_OFF_RET,   /* dsp_l2 */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* dsp_edma */
+                [1] = PWRSTS_OFF_RET,   /* dsp_l1 */
+                [2] = PWRSTS_OFF_RET,   /* dsp_l2 */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+/* cam_54xx_pwrdm: Camera subsystem power domain */
+static struct powerdomain cam_54xx_pwrdm = {
+        .name             = "cam_pwrdm",
+        .voltdm           = { .name = "core" },
+        .prcm_offs        = OMAP54XX_PRM_CAM_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* cam_mem */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* cam_mem */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+/* l3init_54xx_pwrdm: L3 initators pheripherals power domain  */
+static struct powerdomain l3init_54xx_pwrdm = {
+        .name             = "l3init_pwrdm",
+        .voltdm           = { .name = "core" },
+        .prcm_offs        = OMAP54XX_PRM_L3INIT_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .banks            = 2,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* l3init_bank1 */
+                [1] = PWRSTS_OFF_RET,   /* l3init_bank2 */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* l3init_bank1 */
+                [1] = PWRSTS_OFF_RET,   /* l3init_bank2 */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+/* gpu_54xx_pwrdm: 3D accelerator power domain */
+static struct powerdomain gpu_54xx_pwrdm = {
+        .name             = "gpu_pwrdm",
+        .voltdm           = { .name = "mm" },
+        .prcm_offs        = OMAP54XX_PRM_GPU_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* gpu_mem */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* gpu_mem */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+/* wkupaon_54xx_pwrdm: Wake-up power domain */
+static struct powerdomain wkupaon_54xx_pwrdm = {
+        .name             = "wkupaon_pwrdm",
+        .voltdm           = { .name = "wkup" },
+        .prcm_offs        = OMAP54XX_PRM_WKUPAON_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_ON,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_ON,        /* wkup_bank */
+        },
+};
+/* iva_54xx_pwrdm: IVA-HD power domain */
+static struct powerdomain iva_54xx_pwrdm = {
+        .name             = "iva_pwrdm",
+        .voltdm           = { .name = "mm" },
+        .prcm_offs        = OMAP54XX_PRM_IVA_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF,
+        .banks            = 4,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* hwa_mem */
+                [1] = PWRSTS_OFF_RET,   /* sl2_mem */
+                [2] = PWRSTS_OFF_RET,   /* tcm1_mem */
+                [3] = PWRSTS_OFF_RET,   /* tcm2_mem */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* hwa_mem */
+                [1] = PWRSTS_OFF_RET,   /* sl2_mem */
+                [2] = PWRSTS_OFF_RET,   /* tcm1_mem */
+                [3] = PWRSTS_OFF_RET,   /* tcm2_mem */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+/*
+ * The following power domains are not under SW control
+ *
+ * mpuaon
+ * mmaon
+ */
+/* As powerdomains are added or removed above, this list must also be changed */
+static struct powerdomain *powerdomains_omap54xx[] __initdata = {
+        &core_54xx_pwrdm,
+        &abe_54xx_pwrdm,
+        &coreaon_54xx_pwrdm,
+        &dss_54xx_pwrdm,
+        &cpu0_54xx_pwrdm,
+        &cpu1_54xx_pwrdm,
+        &emu_54xx_pwrdm,
+        &mpu_54xx_pwrdm,
+        &custefuse_54xx_pwrdm,
+        &dsp_54xx_pwrdm,
+        &cam_54xx_pwrdm,
+        &l3init_54xx_pwrdm,
+        &gpu_54xx_pwrdm,
+        &wkupaon_54xx_pwrdm,
+        &iva_54xx_pwrdm,
+        NULL
+};
+void __init omap54xx_powerdomains_init(void)
+{
+        pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
+        pwrdm_register_pwrdms(powerdomains_omap54xx);
+        pwrdm_complete_init();
+}
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index c7d355fafd24..ff1ac4a82a04 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -48,6 +48,17 @@
 #define OMAP3430_NEON_MOD                               0xb00
 #define OMAP3430ES2_USBHOST_MOD                         0xc00
+/*
+ * TI81XX PRM module offsets
+ */
+#define TI81XX_PRM_DEVICE_MOD                   0x0000
+#define TI816X_PRM_ACTIVE_MOD                   0x0a00
+#define TI81XX_PRM_DEFAULT_MOD                  0x0b00
+#define TI816X_PRM_IVAHD0_MOD                   0x0c00
+#define TI816X_PRM_IVAHD1_MOD                   0x0d00
+#define TI816X_PRM_IVAHD2_MOD                   0x0e00
+#define TI816X_PRM_SGX_MOD                              0x0f00
 /* 24XX register bits shared between CM & PRM registers */
 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
diff --git a/arch/arm/mach-omap2/prcm44xx.h b/arch/arm/mach-omap2/prcm44xx.h
index 7334ffb9d2c1..f429cdd5a118 100644
--- a/arch/arm/mach-omap2/prcm44xx.h
+++ b/arch/arm/mach-omap2/prcm44xx.h
@@ -32,6 +32,12 @@
 #define OMAP4430_SCRM_PARTITION                 4
 #define OMAP4430_PRCM_MPU_PARTITION             5
+#define OMAP54XX_PRM_PARTITION                  1
+#define OMAP54XX_CM_CORE_AON_PARTITION          2
+#define OMAP54XX_CM_CORE_PARTITION              3
+#define OMAP54XX_SCRM_PARTITION                 4
+#define OMAP54XX_PRCM_MPU_PARTITION             5
 /*
 * OMAP4_MAX_PRCM_PARTITIONS: set to the highest value of the PRCM partition
 * IDs, plus one
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h
index 884af7bb4afd..059bd4f49035 100644
--- a/arch/arm/mach-omap2/prcm_mpu44xx.h
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.h
@@ -25,12 +25,9 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
 #define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
+#include "prcm_mpu_44xx_54xx.h"
 #include "common.h"
-# ifndef __ASSEMBLER__
-extern void __iomem *prcm_mpu_base;
-# endif
 #define OMAP4430_PRCM_MPU_BASE                  0x48243000
 #define OMAP44XX_PRCM_MPU_REGADDR(inst, reg)                            \
@@ -98,13 +95,4 @@ extern void __iomem *prcm_mpu_base;
 #define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET          0x0018
 #define OMAP4430_CM_CPU1_CLKSTCTRL              OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)
-/* Function prototypes */
-# ifndef __ASSEMBLER__
-extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx);
-extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx);
-extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst,
-                                            s16 idx);
-extern void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu);
-# endif
 #endif
diff --git a/arch/arm/mach-omap2/prcm_mpu54xx.h b/arch/arm/mach-omap2/prcm_mpu54xx.h
new file mode 100644
index 000000000000..bc2ce3288315
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm_mpu54xx.h
@@ -0,0 +1,87 @@
+/*
+ * OMAP54xx PRCM MPU instance offset macros
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU54XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU54XX_H
+#include "prcm_mpu_44xx_54xx.h"
+#include "common.h"
+#define OMAP54XX_PRCM_MPU_BASE                  0x48243000
+#define OMAP54XX_PRCM_MPU_REGADDR(inst, reg)                            \
+        OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE + (inst) + (reg))
+/* PRCM_MPU instances */
+#define OMAP54XX_PRCM_MPU_OCP_SOCKET_INST       0x0000
+#define OMAP54XX_PRCM_MPU_DEVICE_INST           0x0200
+#define OMAP54XX_PRCM_MPU_PRM_C0_INST           0x0400
+#define OMAP54XX_PRCM_MPU_CM_C0_INST            0x0600
+#define OMAP54XX_PRCM_MPU_PRM_C1_INST           0x0800
+#define OMAP54XX_PRCM_MPU_CM_C1_INST            0x0a00
+/* PRCM_MPU clockdomain register offsets (from instance start) */
+#define OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS     0x0000
+#define OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS     0x0000
+/*
+ * PRCM_MPU
+ *
+ * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global)
+ * point of view the PRCM_MPU is a single entity. It shares the same
+ * programming model as the global PRCM and thus can be assimilate as two new
+ * MOD inside the PRCM
+ */
+/* PRCM_MPU.PRCM_MPU_OCP_SOCKET register offsets */
+#define OMAP54XX_REVISION_PRCM_MPU_OFFSET                       0x0000
+/* PRCM_MPU.PRCM_MPU_DEVICE register offsets */
+#define OMAP54XX_PRCM_MPU_PRM_RSTST_OFFSET                      0x0000
+#define OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET                0x0004
+#define OMAP54XX_PRM_FRAC_INCREMENTER_NUMERATOR_OFFSET          0x0010
+#define OMAP54XX_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x0014
+/* PRCM_MPU.PRCM_MPU_PRM_C0 register offsets */
+#define OMAP54XX_PM_CPU0_PWRSTCTRL_OFFSET                       0x0000
+#define OMAP54XX_PM_CPU0_PWRSTST_OFFSET                         0x0004
+#define OMAP54XX_RM_CPU0_CPU0_RSTCTRL_OFFSET                    0x0010
+#define OMAP54XX_RM_CPU0_CPU0_RSTST_OFFSET                      0x0014
+#define OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET                    0x0024
+/* PRCM_MPU.PRCM_MPU_CM_C0 register offsets */
+#define OMAP54XX_CM_CPU0_CLKSTCTRL_OFFSET                       0x0000
+#define OMAP54XX_CM_CPU0_CPU0_CLKCTRL_OFFSET                    0x0020
+#define OMAP54XX_CM_CPU0_CPU0_CLKCTRL                           OMAP54XX_PRCM_MPU_REGADDR(OMAP54XX_PRCM_MPU_CM_C0_INST, 0x0020)
+/* PRCM_MPU.PRCM_MPU_PRM_C1 register offsets */
+#define OMAP54XX_PM_CPU1_PWRSTCTRL_OFFSET                       0x0000
+#define OMAP54XX_PM_CPU1_PWRSTST_OFFSET                         0x0004
+#define OMAP54XX_RM_CPU1_CPU1_RSTCTRL_OFFSET                    0x0010
+#define OMAP54XX_RM_CPU1_CPU1_RSTST_OFFSET                      0x0014
+#define OMAP54XX_RM_CPU1_CPU1_CONTEXT_OFFSET                    0x0024
+/* PRCM_MPU.PRCM_MPU_CM_C1 register offsets */
+#define OMAP54XX_CM_CPU1_CLKSTCTRL_OFFSET                       0x0000
+#define OMAP54XX_CM_CPU1_CPU1_CLKCTRL_OFFSET                    0x0020
+#define OMAP54XX_CM_CPU1_CPU1_CLKCTRL                           OMAP54XX_PRCM_MPU_REGADDR(OMAP54XX_PRCM_MPU_CM_C1_INST, 0x0020)
+#endif
diff --git a/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h b/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h
new file mode 100644
index 000000000000..ca149e70bed0
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h
@@ -0,0 +1,36 @@
+/*
+ * OMAP44xx and OMAP54xx PRCM MPU function prototypes
+ *
+ * Copyright (C) 2010, 2013 Texas Instruments, Inc.
+ * Copyright (C) 2010 Nokia Corporation
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU_44XX_54XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU_44XX_54XX_H
+#ifndef __ASSEMBLER__
+extern void __iomem *prcm_mpu_base;
+extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx);
+extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst,
+                                            s16 idx);
+extern void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu);
+#endif
+#endif
diff --git a/arch/arm/mach-omap2/prm-regbits-54xx.h b/arch/arm/mach-omap2/prm-regbits-54xx.h
new file mode 100644
index 000000000000..be31b21aa9c6
--- /dev/null
+++ b/arch/arm/mach-omap2/prm-regbits-54xx.h
@@ -0,0 +1,2701 @@
+/*
+ * OMAP54xx Power Management register bits
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_54XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_54XX_H
+/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
+#define OMAP54XX_ABBOFF_ACT_SHIFT                                               1
+#define OMAP54XX_ABBOFF_ACT_WIDTH                                               0x1
+#define OMAP54XX_ABBOFF_ACT_MASK                                                (1 << 1)
+/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
+#define OMAP54XX_ABBOFF_SLEEP_SHIFT                                             2
+#define OMAP54XX_ABBOFF_SLEEP_WIDTH                                             0x1
+#define OMAP54XX_ABBOFF_SLEEP_MASK                                              (1 << 2)
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_ABB_MM_DONE_EN_SHIFT                                           31
+#define OMAP54XX_ABB_MM_DONE_EN_WIDTH                                           0x1
+#define OMAP54XX_ABB_MM_DONE_EN_MASK                                            (1 << 31)
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_ABB_MM_DONE_ST_SHIFT                                           31
+#define OMAP54XX_ABB_MM_DONE_ST_WIDTH                                           0x1
+#define OMAP54XX_ABB_MM_DONE_ST_MASK                                            (1 << 31)
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP54XX_ABB_MPU_DONE_EN_SHIFT                                          7
+#define OMAP54XX_ABB_MPU_DONE_EN_WIDTH                                          0x1
+#define OMAP54XX_ABB_MPU_DONE_EN_MASK                                           (1 << 7)
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP54XX_ABB_MPU_DONE_ST_SHIFT                                          7
+#define OMAP54XX_ABB_MPU_DONE_ST_WIDTH                                          0x1
+#define OMAP54XX_ABB_MPU_DONE_ST_MASK                                           (1 << 7)
+/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */
+#define OMAP54XX_ACTIVE_FBB_SEL_SHIFT                                           2
+#define OMAP54XX_ACTIVE_FBB_SEL_WIDTH                                           0x1
+#define OMAP54XX_ACTIVE_FBB_SEL_MASK                                            (1 << 2)
+/* Used by PM_ABE_PWRSTCTRL */
+#define OMAP54XX_AESSMEM_ONSTATE_SHIFT                                          16
+#define OMAP54XX_AESSMEM_ONSTATE_WIDTH                                          0x2
+#define OMAP54XX_AESSMEM_ONSTATE_MASK                                           (0x3 << 16)
+/* Used by PM_ABE_PWRSTCTRL */
+#define OMAP54XX_AESSMEM_RETSTATE_SHIFT                                         8
+#define OMAP54XX_AESSMEM_RETSTATE_WIDTH                                         0x1
+#define OMAP54XX_AESSMEM_RETSTATE_MASK                                          (1 << 8)
+/* Used by PM_ABE_PWRSTST */
+#define OMAP54XX_AESSMEM_STATEST_SHIFT                                          4
+#define OMAP54XX_AESSMEM_STATEST_WIDTH                                          0x2
+#define OMAP54XX_AESSMEM_STATEST_MASK                                           (0x3 << 4)
+/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
+#define OMAP54XX_AIPOFF_SHIFT                                                   8
+#define OMAP54XX_AIPOFF_WIDTH                                                   0x1
+#define OMAP54XX_AIPOFF_MASK                                                    (1 << 8)
+/* Used by PRM_VOLTCTRL */
+#define OMAP54XX_AUTO_CTRL_VDD_CORE_L_SHIFT                                     0
+#define OMAP54XX_AUTO_CTRL_VDD_CORE_L_WIDTH                                     0x2
+#define OMAP54XX_AUTO_CTRL_VDD_CORE_L_MASK                                      (0x3 << 0)
+/* Used by PRM_VOLTCTRL */
+#define OMAP54XX_AUTO_CTRL_VDD_MM_L_SHIFT                                       4
+#define OMAP54XX_AUTO_CTRL_VDD_MM_L_WIDTH                                       0x2
+#define OMAP54XX_AUTO_CTRL_VDD_MM_L_MASK                                        (0x3 << 4)
+/* Used by PRM_VOLTCTRL */
+#define OMAP54XX_AUTO_CTRL_VDD_MPU_L_SHIFT                                      2
+#define OMAP54XX_AUTO_CTRL_VDD_MPU_L_WIDTH                                      0x2
+#define OMAP54XX_AUTO_CTRL_VDD_MPU_L_MASK                                       (0x3 << 2)
+/* Used by PRM_VC_BYPASS_ERRST */
+#define OMAP54XX_BYPS_RA_ERR_SHIFT                                              1
+#define OMAP54XX_BYPS_RA_ERR_WIDTH                                              0x1
+#define OMAP54XX_BYPS_RA_ERR_MASK                                               (1 << 1)
+/* Used by PRM_VC_BYPASS_ERRST */
+#define OMAP54XX_BYPS_SA_ERR_SHIFT                                              0
+#define OMAP54XX_BYPS_SA_ERR_WIDTH                                              0x1
+#define OMAP54XX_BYPS_SA_ERR_MASK                                               (1 << 0)
+/* Used by PRM_VC_BYPASS_ERRST */
+#define OMAP54XX_BYPS_TIMEOUT_ERR_SHIFT                                         2
+#define OMAP54XX_BYPS_TIMEOUT_ERR_WIDTH                                         0x1
+#define OMAP54XX_BYPS_TIMEOUT_ERR_MASK                                          (1 << 2)
+/* Used by PRM_RSTST */
+#define OMAP54XX_C2C_RST_SHIFT                                                  10
+#define OMAP54XX_C2C_RST_WIDTH                                                  0x1
+#define OMAP54XX_C2C_RST_MASK                                                   (1 << 10)
+/* Used by PM_CAM_PWRSTCTRL */
+#define OMAP54XX_CAM_MEM_ONSTATE_SHIFT                                          16
+#define OMAP54XX_CAM_MEM_ONSTATE_WIDTH                                          0x2
+#define OMAP54XX_CAM_MEM_ONSTATE_MASK                                           (0x3 << 16)
+/* Used by PM_CAM_PWRSTST */
+#define OMAP54XX_CAM_MEM_STATEST_SHIFT                                          4
+#define OMAP54XX_CAM_MEM_STATEST_WIDTH                                          0x2
+#define OMAP54XX_CAM_MEM_STATEST_MASK                                           (0x3 << 4)
+/* Used by PRM_CLKREQCTRL */
+#define OMAP54XX_CLKREQ_COND_SHIFT                                              0
+#define OMAP54XX_CLKREQ_COND_WIDTH                                              0x3
+#define OMAP54XX_CLKREQ_COND_MASK                                               (0x7 << 0)
+/* Used by PRM_VC_SMPS_CORE_CONFIG */
+#define OMAP54XX_CMDRA_VDD_CORE_L_SHIFT                                         16
+#define OMAP54XX_CMDRA_VDD_CORE_L_WIDTH                                         0x8
+#define OMAP54XX_CMDRA_VDD_CORE_L_MASK                                          (0xff << 16)
+/* Used by PRM_VC_SMPS_MM_CONFIG */
+#define OMAP54XX_CMDRA_VDD_MM_L_SHIFT                                           16
+#define OMAP54XX_CMDRA_VDD_MM_L_WIDTH                                           0x8
+#define OMAP54XX_CMDRA_VDD_MM_L_MASK                                            (0xff << 16)
+/* Used by PRM_VC_SMPS_MPU_CONFIG */
+#define OMAP54XX_CMDRA_VDD_MPU_L_SHIFT                                          16
+#define OMAP54XX_CMDRA_VDD_MPU_L_WIDTH                                          0x8
+#define OMAP54XX_CMDRA_VDD_MPU_L_MASK                                           (0xff << 16)
+/* Used by PRM_VC_SMPS_CORE_CONFIG */
+#define OMAP54XX_CMD_VDD_CORE_L_SHIFT                                           28
+#define OMAP54XX_CMD_VDD_CORE_L_WIDTH                                           0x1
+#define OMAP54XX_CMD_VDD_CORE_L_MASK                                            (1 << 28)
+/* Used by PRM_VC_SMPS_MM_CONFIG */
+#define OMAP54XX_CMD_VDD_MM_L_SHIFT                                             28
+#define OMAP54XX_CMD_VDD_MM_L_WIDTH                                             0x1
+#define OMAP54XX_CMD_VDD_MM_L_MASK                                              (1 << 28)
+/* Used by PRM_VC_SMPS_MPU_CONFIG */
+#define OMAP54XX_CMD_VDD_MPU_L_SHIFT                                            28
+#define OMAP54XX_CMD_VDD_MPU_L_WIDTH                                            0x1
+#define OMAP54XX_CMD_VDD_MPU_L_MASK                                             (1 << 28)
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP54XX_CORE_OCMRAM_ONSTATE_SHIFT                                      18
+#define OMAP54XX_CORE_OCMRAM_ONSTATE_WIDTH                                      0x2
+#define OMAP54XX_CORE_OCMRAM_ONSTATE_MASK                                       (0x3 << 18)
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP54XX_CORE_OCMRAM_RETSTATE_SHIFT                                     9
+#define OMAP54XX_CORE_OCMRAM_RETSTATE_WIDTH                                     0x1
+#define OMAP54XX_CORE_OCMRAM_RETSTATE_MASK                                      (1 << 9)
+/* Used by PM_CORE_PWRSTST */
+#define OMAP54XX_CORE_OCMRAM_STATEST_SHIFT                                      6
+#define OMAP54XX_CORE_OCMRAM_STATEST_WIDTH                                      0x2
+#define OMAP54XX_CORE_OCMRAM_STATEST_MASK                                       (0x3 << 6)
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP54XX_CORE_OTHER_BANK_ONSTATE_SHIFT                                  16
+#define OMAP54XX_CORE_OTHER_BANK_ONSTATE_WIDTH                                  0x2
+#define OMAP54XX_CORE_OTHER_BANK_ONSTATE_MASK                                   (0x3 << 16)
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP54XX_CORE_OTHER_BANK_RETSTATE_SHIFT                                 8
+#define OMAP54XX_CORE_OTHER_BANK_RETSTATE_WIDTH                                 0x1
+#define OMAP54XX_CORE_OTHER_BANK_RETSTATE_MASK                                  (1 << 8)
+/* Used by PM_CORE_PWRSTST */
+#define OMAP54XX_CORE_OTHER_BANK_STATEST_SHIFT                                  4
+#define OMAP54XX_CORE_OTHER_BANK_STATEST_WIDTH                                  0x2
+#define OMAP54XX_CORE_OTHER_BANK_STATEST_MASK                                   (0x3 << 4)
+/* Used by REVISION_PRM */
+#define OMAP54XX_CUSTOM_SHIFT                                                   6
+#define OMAP54XX_CUSTOM_WIDTH                                                   0x2
+#define OMAP54XX_CUSTOM_MASK                                                    (0x3 << 6)
+/* Used by PRM_VC_VAL_BYPASS */
+#define OMAP54XX_DATA_SHIFT                                                     16
+#define OMAP54XX_DATA_WIDTH                                                     0x8
+#define OMAP54XX_DATA_MASK                                                      (0xff << 16)
+/* Used by PRM_DEBUG_CORE_RET_TRANS */
+#define OMAP54XX_PRM_DEBUG_OUT_SHIFT                                            0
+#define OMAP54XX_PRM_DEBUG_OUT_WIDTH                                            0x1c
+#define OMAP54XX_PRM_DEBUG_OUT_MASK                                             (0xfffffff << 0)
+/* Renamed from DEBUG_OUT Used by PRM_DEBUG_MM_RET_TRANS */
+#define OMAP54XX_DEBUG_OUT_0_9_SHIFT                                            0
+#define OMAP54XX_DEBUG_OUT_0_9_WIDTH                                            0xa
+#define OMAP54XX_DEBUG_OUT_0_9_MASK                                             (0x3ff << 0)
+/* Renamed from DEBUG_OUT Used by PRM_DEBUG_MPU_RET_TRANS */
+#define OMAP54XX_DEBUG_OUT_0_6_SHIFT                                            0
+#define OMAP54XX_DEBUG_OUT_0_6_WIDTH                                            0x7
+#define OMAP54XX_DEBUG_OUT_0_6_MASK                                             (0x7f << 0)
+/* Renamed from DEBUG_OUT Used by PRM_DEBUG_OFF_TRANS */
+#define OMAP54XX_DEBUG_OUT_0_31_SHIFT                                           0
+#define OMAP54XX_DEBUG_OUT_0_31_WIDTH                                           0x20
+#define OMAP54XX_DEBUG_OUT_0_31_MASK                                            (0xffffffff << 0)
+/* Renamed from DEBUG_OUT Used by PRM_DEBUG_WKUPAON_FD_TRANS */
+#define OMAP54XX_DEBUG_OUT_0_11_SHIFT                                           0
+#define OMAP54XX_DEBUG_OUT_0_11_WIDTH                                           0xc
+#define OMAP54XX_DEBUG_OUT_0_11_MASK                                            (0xfff << 0)
+/* Used by PRM_DEVICE_OFF_CTRL */
+#define OMAP54XX_DEVICE_OFF_ENABLE_SHIFT                                        0
+#define OMAP54XX_DEVICE_OFF_ENABLE_WIDTH                                        0x1
+#define OMAP54XX_DEVICE_OFF_ENABLE_MASK                                         (1 << 0)
+/* Used by PRM_VC_CFG_I2C_MODE */
+#define OMAP54XX_DFILTEREN_SHIFT                                                6
+#define OMAP54XX_DFILTEREN_WIDTH                                                0x1
+#define OMAP54XX_DFILTEREN_MASK                                                 (1 << 6)
+/* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_DPLL_ABE_RECAL_EN_SHIFT                                        4
+#define OMAP54XX_DPLL_ABE_RECAL_EN_WIDTH                                        0x1
+#define OMAP54XX_DPLL_ABE_RECAL_EN_MASK                                         (1 << 4)
+/* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_DPLL_ABE_RECAL_ST_SHIFT                                        4
+#define OMAP54XX_DPLL_ABE_RECAL_ST_WIDTH                                        0x1
+#define OMAP54XX_DPLL_ABE_RECAL_ST_MASK                                         (1 << 4)
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_DPLL_CORE_RECAL_EN_SHIFT                                       0
+#define OMAP54XX_DPLL_CORE_RECAL_EN_WIDTH                                       0x1
+#define OMAP54XX_DPLL_CORE_RECAL_EN_MASK                                        (1 << 0)
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_DPLL_CORE_RECAL_ST_SHIFT                                       0
+#define OMAP54XX_DPLL_CORE_RECAL_ST_WIDTH                                       0x1
+#define OMAP54XX_DPLL_CORE_RECAL_ST_MASK                                        (1 << 0)
+/* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_DPLL_IVA_RECAL_EN_SHIFT                                        2
+#define OMAP54XX_DPLL_IVA_RECAL_EN_WIDTH                                        0x1
+#define OMAP54XX_DPLL_IVA_RECAL_EN_MASK                                         (1 << 2)
+/* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_DPLL_IVA_RECAL_ST_SHIFT                                        2
+#define OMAP54XX_DPLL_IVA_RECAL_ST_WIDTH                                        0x1
+#define OMAP54XX_DPLL_IVA_RECAL_ST_MASK                                         (1 << 2)
+/* Used by PRM_IRQENABLE_MPU */
+#define OMAP54XX_DPLL_MPU_RECAL_EN_SHIFT                                        1
+#define OMAP54XX_DPLL_MPU_RECAL_EN_WIDTH                                        0x1
+#define OMAP54XX_DPLL_MPU_RECAL_EN_MASK                                         (1 << 1)
+/* Used by PRM_IRQSTATUS_MPU */
+#define OMAP54XX_DPLL_MPU_RECAL_ST_SHIFT                                        1
+#define OMAP54XX_DPLL_MPU_RECAL_ST_WIDTH                                        0x1
+#define OMAP54XX_DPLL_MPU_RECAL_ST_MASK                                         (1 << 1)
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_DPLL_PER_RECAL_EN_SHIFT                                        3
+#define OMAP54XX_DPLL_PER_RECAL_EN_WIDTH                                        0x1
+#define OMAP54XX_DPLL_PER_RECAL_EN_MASK                                         (1 << 3)
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_DPLL_PER_RECAL_ST_SHIFT                                        3
+#define OMAP54XX_DPLL_PER_RECAL_ST_WIDTH                                        0x1
+#define OMAP54XX_DPLL_PER_RECAL_ST_MASK                                         (1 << 3)
+/* Used by PM_DSP_PWRSTCTRL */
+#define OMAP54XX_DSP_EDMA_ONSTATE_SHIFT                                         20
+#define OMAP54XX_DSP_EDMA_ONSTATE_WIDTH                                         0x2
+#define OMAP54XX_DSP_EDMA_ONSTATE_MASK                                          (0x3 << 20)
+/* Used by PM_DSP_PWRSTCTRL */
+#define OMAP54XX_DSP_EDMA_RETSTATE_SHIFT                                        10
+#define OMAP54XX_DSP_EDMA_RETSTATE_WIDTH                                        0x1
+#define OMAP54XX_DSP_EDMA_RETSTATE_MASK                                         (1 << 10)
+/* Used by PM_DSP_PWRSTST */
+#define OMAP54XX_DSP_EDMA_STATEST_SHIFT                                         8
+#define OMAP54XX_DSP_EDMA_STATEST_WIDTH                                         0x2
+#define OMAP54XX_DSP_EDMA_STATEST_MASK                                          (0x3 << 8)
+/* Used by PM_DSP_PWRSTCTRL */
+#define OMAP54XX_DSP_L1_ONSTATE_SHIFT                                           16
+#define OMAP54XX_DSP_L1_ONSTATE_WIDTH                                           0x2
+#define OMAP54XX_DSP_L1_ONSTATE_MASK                                            (0x3 << 16)
+/* Used by PM_DSP_PWRSTCTRL */
+#define OMAP54XX_DSP_L1_RETSTATE_SHIFT                                          8
+#define OMAP54XX_DSP_L1_RETSTATE_WIDTH                                          0x1
+#define OMAP54XX_DSP_L1_RETSTATE_MASK                                           (1 << 8)
+/* Used by PM_DSP_PWRSTST */
+#define OMAP54XX_DSP_L1_STATEST_SHIFT                                           4
+#define OMAP54XX_DSP_L1_STATEST_WIDTH                                           0x2
+#define OMAP54XX_DSP_L1_STATEST_MASK                                            (0x3 << 4)
+/* Used by PM_DSP_PWRSTCTRL */
+#define OMAP54XX_DSP_L2_ONSTATE_SHIFT                                           18
+#define OMAP54XX_DSP_L2_ONSTATE_WIDTH                                           0x2
+#define OMAP54XX_DSP_L2_ONSTATE_MASK                                            (0x3 << 18)
+/* Used by PM_DSP_PWRSTCTRL */
+#define OMAP54XX_DSP_L2_RETSTATE_SHIFT                                          9
+#define OMAP54XX_DSP_L2_RETSTATE_WIDTH                                          0x1
+#define OMAP54XX_DSP_L2_RETSTATE_MASK                                           (1 << 9)
+/* Used by PM_DSP_PWRSTST */
+#define OMAP54XX_DSP_L2_STATEST_SHIFT                                           6
+#define OMAP54XX_DSP_L2_STATEST_WIDTH                                           0x2
+#define OMAP54XX_DSP_L2_STATEST_MASK                                            (0x3 << 6)
+/* Used by PM_DSS_PWRSTCTRL */
+#define OMAP54XX_DSS_MEM_ONSTATE_SHIFT                                          16
+#define OMAP54XX_DSS_MEM_ONSTATE_WIDTH                                          0x2
+#define OMAP54XX_DSS_MEM_ONSTATE_MASK                                           (0x3 << 16)
+/* Used by PM_DSS_PWRSTCTRL */
+#define OMAP54XX_DSS_MEM_RETSTATE_SHIFT                                         8
+#define OMAP54XX_DSS_MEM_RETSTATE_WIDTH                                         0x1
+#define OMAP54XX_DSS_MEM_RETSTATE_MASK                                          (1 << 8)
+/* Used by PM_DSS_PWRSTST */
+#define OMAP54XX_DSS_MEM_STATEST_SHIFT                                          4
+#define OMAP54XX_DSS_MEM_STATEST_WIDTH                                          0x2
+#define OMAP54XX_DSS_MEM_STATEST_MASK                                           (0x3 << 4)
+/* Used by PRM_DEVICE_OFF_CTRL */
+#define OMAP54XX_EMIF1_OFFWKUP_DISABLE_SHIFT                                    8
+#define OMAP54XX_EMIF1_OFFWKUP_DISABLE_WIDTH                                    0x1
+#define OMAP54XX_EMIF1_OFFWKUP_DISABLE_MASK                                     (1 << 8)
+/* Used by PRM_DEVICE_OFF_CTRL */
+#define OMAP54XX_EMIF2_OFFWKUP_DISABLE_SHIFT                                    9
+#define OMAP54XX_EMIF2_OFFWKUP_DISABLE_WIDTH                                    0x1
+#define OMAP54XX_EMIF2_OFFWKUP_DISABLE_MASK                                     (1 << 9)
+/* Used by PM_EMU_PWRSTCTRL */
+#define OMAP54XX_EMU_BANK_ONSTATE_SHIFT                                         16
+#define OMAP54XX_EMU_BANK_ONSTATE_WIDTH                                         0x2
+#define OMAP54XX_EMU_BANK_ONSTATE_MASK                                          (0x3 << 16)
+/* Used by PM_EMU_PWRSTST */
+#define OMAP54XX_EMU_BANK_STATEST_SHIFT                                         4
+#define OMAP54XX_EMU_BANK_STATEST_WIDTH                                         0x2
+#define OMAP54XX_EMU_BANK_STATEST_MASK                                          (0x3 << 4)
+/*
+ * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP,
+ * PRM_SRAM_WKUP_SETUP
+ */
+#define OMAP54XX_ENABLE_RTA_SHIFT                                               0
+#define OMAP54XX_ENABLE_RTA_WIDTH                                               0x1
+#define OMAP54XX_ENABLE_RTA_MASK                                                (1 << 0)
+/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
+#define OMAP54XX_ENFUNC1_SHIFT                                                  3
+#define OMAP54XX_ENFUNC1_WIDTH                                                  0x1
+#define OMAP54XX_ENFUNC1_MASK                                                   (1 << 3)
+/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
+#define OMAP54XX_ENFUNC2_SHIFT                                                  4
+#define OMAP54XX_ENFUNC2_WIDTH                                                  0x1
+#define OMAP54XX_ENFUNC2_MASK                                                   (1 << 4)
+/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
+#define OMAP54XX_ENFUNC3_SHIFT                                                  5
+#define OMAP54XX_ENFUNC3_WIDTH                                                  0x1
+#define OMAP54XX_ENFUNC3_MASK                                                   (1 << 5)
+/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
+#define OMAP54XX_ENFUNC4_SHIFT                                                  6
+#define OMAP54XX_ENFUNC4_WIDTH                                                  0x1
+#define OMAP54XX_ENFUNC4_MASK                                                   (1 << 6)
+/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
+#define OMAP54XX_ENFUNC5_SHIFT                                                  7
+#define OMAP54XX_ENFUNC5_WIDTH                                                  0x1
+#define OMAP54XX_ENFUNC5_MASK                                                   (1 << 7)
+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
+#define OMAP54XX_ERRORGAIN_SHIFT                                                16
+#define OMAP54XX_ERRORGAIN_WIDTH                                                0x8
+#define OMAP54XX_ERRORGAIN_MASK                                                 (0xff << 16)
+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
+#define OMAP54XX_ERROROFFSET_SHIFT                                              24
+#define OMAP54XX_ERROROFFSET_WIDTH                                              0x8
+#define OMAP54XX_ERROROFFSET_MASK                                               (0xff << 24)
+/* Used by PRM_RSTST */
+#define OMAP54XX_EXTERNAL_WARM_RST_SHIFT                                        5
+#define OMAP54XX_EXTERNAL_WARM_RST_WIDTH                                        0x1
+#define OMAP54XX_EXTERNAL_WARM_RST_MASK                                         (1 << 5)
+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
+#define OMAP54XX_FORCEUPDATE_SHIFT                                              1
+#define OMAP54XX_FORCEUPDATE_WIDTH                                              0x1
+#define OMAP54XX_FORCEUPDATE_MASK                                               (1 << 1)
+/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_MM_VOLTAGE, PRM_VP_MPU_VOLTAGE */
+#define OMAP54XX_FORCEUPDATEWAIT_SHIFT                                          8
+#define OMAP54XX_FORCEUPDATEWAIT_WIDTH                                          0x18
+#define OMAP54XX_FORCEUPDATEWAIT_MASK                                           (0xffffff << 8)
+/* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU */
+#define OMAP54XX_FORCEWKUP_EN_SHIFT                                             10
+#define OMAP54XX_FORCEWKUP_EN_WIDTH                                             0x1
+#define OMAP54XX_FORCEWKUP_EN_MASK                                              (1 << 10)
+/* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU */
+#define OMAP54XX_FORCEWKUP_ST_SHIFT                                             10
+#define OMAP54XX_FORCEWKUP_ST_WIDTH                                             0x1
+#define OMAP54XX_FORCEWKUP_ST_MASK                                              (1 << 10)
+/* Used by REVISION_PRM */
+#define OMAP54XX_FUNC_SHIFT                                                     16
+#define OMAP54XX_FUNC_WIDTH                                                     0xc
+#define OMAP54XX_FUNC_MASK                                                      (0xfff << 16)
+/* Used by PRM_RSTST */
+#define OMAP54XX_GLOBAL_COLD_RST_SHIFT                                          0
+#define OMAP54XX_GLOBAL_COLD_RST_WIDTH                                          0x1
+#define OMAP54XX_GLOBAL_COLD_RST_MASK                                           (1 << 0)
+/* Used by PRM_RSTST */
+#define OMAP54XX_GLOBAL_WARM_SW_RST_SHIFT                                       1
+#define OMAP54XX_GLOBAL_WARM_SW_RST_WIDTH                                       0x1
+#define OMAP54XX_GLOBAL_WARM_SW_RST_MASK                                        (1 << 1)
+/* Used by PRM_IO_PMCTRL */
+#define OMAP54XX_GLOBAL_WUEN_SHIFT                                              16
+#define OMAP54XX_GLOBAL_WUEN_WIDTH                                              0x1
+#define OMAP54XX_GLOBAL_WUEN_MASK                                               (1 << 16)
+/* Used by PM_GPU_PWRSTCTRL */
+#define OMAP54XX_GPU_MEM_ONSTATE_SHIFT                                          16
+#define OMAP54XX_GPU_MEM_ONSTATE_WIDTH                                          0x2
+#define OMAP54XX_GPU_MEM_ONSTATE_MASK                                           (0x3 << 16)
+/* Used by PM_GPU_PWRSTST */
+#define OMAP54XX_GPU_MEM_STATEST_SHIFT                                          4
+#define OMAP54XX_GPU_MEM_STATEST_WIDTH                                          0x2
+#define OMAP54XX_GPU_MEM_STATEST_MASK                                           (0x3 << 4)
+/* Used by PRM_VC_CFG_I2C_MODE */
+#define OMAP54XX_HSMCODE_SHIFT                                                  0
+#define OMAP54XX_HSMCODE_WIDTH                                                  0x3
+#define OMAP54XX_HSMCODE_MASK                                                   (0x7 << 0)
+/* Used by PRM_VC_CFG_I2C_MODE */
+#define OMAP54XX_HSMODEEN_SHIFT                                                 3
+#define OMAP54XX_HSMODEEN_WIDTH                                                 0x1
+#define OMAP54XX_HSMODEEN_MASK                                                  (1 << 3)
+/* Used by PRM_VC_CFG_I2C_CLK */
+#define OMAP54XX_HSSCLH_SHIFT                                                   16
+#define OMAP54XX_HSSCLH_WIDTH                                                   0x8
+#define OMAP54XX_HSSCLH_MASK                                                    (0xff << 16)
+/* Used by PRM_VC_CFG_I2C_CLK */
+#define OMAP54XX_HSSCLL_SHIFT                                                   24
+#define OMAP54XX_HSSCLL_WIDTH                                                   0x8
+#define OMAP54XX_HSSCLL_MASK                                                    (0xff << 24)
+/* Used by PM_IVA_PWRSTCTRL */
+#define OMAP54XX_HWA_MEM_ONSTATE_SHIFT                                          16
+#define OMAP54XX_HWA_MEM_ONSTATE_WIDTH                                          0x2
+#define OMAP54XX_HWA_MEM_ONSTATE_MASK                                           (0x3 << 16)
+/* Used by PM_IVA_PWRSTCTRL */
+#define OMAP54XX_HWA_MEM_RETSTATE_SHIFT                                         8
+#define OMAP54XX_HWA_MEM_RETSTATE_WIDTH                                         0x1
+#define OMAP54XX_HWA_MEM_RETSTATE_MASK                                          (1 << 8)
+/* Used by PM_IVA_PWRSTST */
+#define OMAP54XX_HWA_MEM_STATEST_SHIFT                                          4
+#define OMAP54XX_HWA_MEM_STATEST_WIDTH                                          0x2
+#define OMAP54XX_HWA_MEM_STATEST_MASK                                           (0x3 << 4)
+/* Used by PRM_RSTST */
+#define OMAP54XX_ICEPICK_RST_SHIFT                                              9
+#define OMAP54XX_ICEPICK_RST_WIDTH                                              0x1
+#define OMAP54XX_ICEPICK_RST_MASK                                               (1 << 9)
+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
+#define OMAP54XX_INITVDD_SHIFT                                                  2
+#define OMAP54XX_INITVDD_WIDTH                                                  0x1
+#define OMAP54XX_INITVDD_MASK                                                   (1 << 2)
+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
+#define OMAP54XX_INITVOLTAGE_SHIFT                                              8
+#define OMAP54XX_INITVOLTAGE_WIDTH                                              0x8
+#define OMAP54XX_INITVOLTAGE_MASK                                               (0xff << 8)
+/*
+ * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST,
+ * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
+ * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST,
+ * PRM_VOLTST_MM, PRM_VOLTST_MPU
+ */
+#define OMAP54XX_INTRANSITION_SHIFT                                             20
+#define OMAP54XX_INTRANSITION_WIDTH                                             0x1
+#define OMAP54XX_INTRANSITION_MASK                                              (1 << 20)
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_IO_EN_SHIFT                                                    9
+#define OMAP54XX_IO_EN_WIDTH                                                    0x1
+#define OMAP54XX_IO_EN_MASK                                                     (1 << 9)
+/* Used by PRM_IO_PMCTRL */
+#define OMAP54XX_IO_ON_STATUS_SHIFT                                             5
+#define OMAP54XX_IO_ON_STATUS_WIDTH                                             0x1
+#define OMAP54XX_IO_ON_STATUS_MASK                                              (1 << 5)
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_IO_ST_SHIFT                                                    9
+#define OMAP54XX_IO_ST_WIDTH                                                    0x1
+#define OMAP54XX_IO_ST_MASK                                                     (1 << 9)
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP54XX_IPU_L2RAM_ONSTATE_SHIFT                                        20
+#define OMAP54XX_IPU_L2RAM_ONSTATE_WIDTH                                        0x2
+#define OMAP54XX_IPU_L2RAM_ONSTATE_MASK                                         (0x3 << 20)
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP54XX_IPU_L2RAM_RETSTATE_SHIFT                                       10
+#define OMAP54XX_IPU_L2RAM_RETSTATE_WIDTH                                       0x1
+#define OMAP54XX_IPU_L2RAM_RETSTATE_MASK                                        (1 << 10)
+/* Used by PM_CORE_PWRSTST */
+#define OMAP54XX_IPU_L2RAM_STATEST_SHIFT                                        8
+#define OMAP54XX_IPU_L2RAM_STATEST_WIDTH                                        0x2
+#define OMAP54XX_IPU_L2RAM_STATEST_MASK                                         (0x3 << 8)
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP54XX_IPU_UNICACHE_ONSTATE_SHIFT                                     22
+#define OMAP54XX_IPU_UNICACHE_ONSTATE_WIDTH                                     0x2
+#define OMAP54XX_IPU_UNICACHE_ONSTATE_MASK                                      (0x3 << 22)
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP54XX_IPU_UNICACHE_RETSTATE_SHIFT                                    11
+#define OMAP54XX_IPU_UNICACHE_RETSTATE_WIDTH                                    0x1
+#define OMAP54XX_IPU_UNICACHE_RETSTATE_MASK                                     (1 << 11)
+/* Used by PM_CORE_PWRSTST */
+#define OMAP54XX_IPU_UNICACHE_STATEST_SHIFT                                     10
+#define OMAP54XX_IPU_UNICACHE_STATEST_WIDTH                                     0x2
+#define OMAP54XX_IPU_UNICACHE_STATEST_MASK                                      (0x3 << 10)
+/* Used by PRM_IO_PMCTRL */
+#define OMAP54XX_ISOCLK_OVERRIDE_SHIFT                                          0
+#define OMAP54XX_ISOCLK_OVERRIDE_WIDTH                                          0x1
+#define OMAP54XX_ISOCLK_OVERRIDE_MASK                                           (1 << 0)
+/* Used by PRM_IO_PMCTRL */
+#define OMAP54XX_ISOCLK_STATUS_SHIFT                                            1
+#define OMAP54XX_ISOCLK_STATUS_WIDTH                                            0x1
+#define OMAP54XX_ISOCLK_STATUS_MASK                                             (1 << 1)
+/* Used by PRM_IO_PMCTRL */
+#define OMAP54XX_ISOOVR_EXTEND_SHIFT                                            4
+#define OMAP54XX_ISOOVR_EXTEND_WIDTH                                            0x1
+#define OMAP54XX_ISOOVR_EXTEND_MASK                                             (1 << 4)
+/* Used by PRM_IO_COUNT */
+#define OMAP54XX_ISO_2_ON_TIME_SHIFT                                            0
+#define OMAP54XX_ISO_2_ON_TIME_WIDTH                                            0x8
+#define OMAP54XX_ISO_2_ON_TIME_MASK                                             (0xff << 0)
+/* Used by PM_L3INIT_PWRSTCTRL */
+#define OMAP54XX_L3INIT_BANK1_ONSTATE_SHIFT                                     16
+#define OMAP54XX_L3INIT_BANK1_ONSTATE_WIDTH                                     0x2
+#define OMAP54XX_L3INIT_BANK1_ONSTATE_MASK                                      (0x3 << 16)
+/* Used by PM_L3INIT_PWRSTCTRL */
+#define OMAP54XX_L3INIT_BANK1_RETSTATE_SHIFT                                    8
+#define OMAP54XX_L3INIT_BANK1_RETSTATE_WIDTH                                    0x1
+#define OMAP54XX_L3INIT_BANK1_RETSTATE_MASK                                     (1 << 8)
+/* Used by PM_L3INIT_PWRSTST */
+#define OMAP54XX_L3INIT_BANK1_STATEST_SHIFT                                     4
+#define OMAP54XX_L3INIT_BANK1_STATEST_WIDTH                                     0x2
+#define OMAP54XX_L3INIT_BANK1_STATEST_MASK                                      (0x3 << 4)
+/* Used by PM_L3INIT_PWRSTCTRL */
+#define OMAP54XX_L3INIT_BANK2_ONSTATE_SHIFT                                     18
+#define OMAP54XX_L3INIT_BANK2_ONSTATE_WIDTH                                     0x2
+#define OMAP54XX_L3INIT_BANK2_ONSTATE_MASK                                      (0x3 << 18)
+/* Used by PM_L3INIT_PWRSTCTRL */
+#define OMAP54XX_L3INIT_BANK2_RETSTATE_SHIFT                                    9
+#define OMAP54XX_L3INIT_BANK2_RETSTATE_WIDTH                                    0x1
+#define OMAP54XX_L3INIT_BANK2_RETSTATE_MASK                                     (1 << 9)
+/* Used by PM_L3INIT_PWRSTST */
+#define OMAP54XX_L3INIT_BANK2_STATEST_SHIFT                                     6
+#define OMAP54XX_L3INIT_BANK2_STATEST_WIDTH                                     0x2
+#define OMAP54XX_L3INIT_BANK2_STATEST_MASK                                      (0x3 << 6)
+/*
+ * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST,
+ * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
+ * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST
+ */
+#define OMAP54XX_LASTPOWERSTATEENTERED_SHIFT                                    24
+#define OMAP54XX_LASTPOWERSTATEENTERED_WIDTH                                    0x2
+#define OMAP54XX_LASTPOWERSTATEENTERED_MASK                                     (0x3 << 24)
+/* Used by PRM_RSTST */
+#define OMAP54XX_LLI_RST_SHIFT                                                  14
+#define OMAP54XX_LLI_RST_WIDTH                                                  0x1
+#define OMAP54XX_LLI_RST_MASK                                                   (1 << 14)
+/*
+ * Used by PM_ABE_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_DSP_PWRSTCTRL,
+ * PM_DSS_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_MPU_PWRSTCTRL
+ */
+#define OMAP54XX_LOGICRETSTATE_SHIFT                                            2
+#define OMAP54XX_LOGICRETSTATE_WIDTH                                            0x1
+#define OMAP54XX_LOGICRETSTATE_MASK                                             (1 << 2)
+/*
+ * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST,
+ * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
+ * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST
+ */
+#define OMAP54XX_LOGICSTATEST_SHIFT                                             2
+#define OMAP54XX_LOGICSTATEST_WIDTH                                             0x1
+#define OMAP54XX_LOGICSTATEST_MASK                                              (1 << 2)
+/*
+ * Used by RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT,
+ * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT,
+ * RM_ABE_MCPDM_CONTEXT, RM_ABE_SLIMBUS1_CONTEXT, RM_ABE_TIMER5_CONTEXT,
+ * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT,
+ * RM_ABE_WD_TIMER3_CONTEXT, RM_C2C_C2C_CONTEXT, RM_C2C_C2C_OCP_FW_CONTEXT,
+ * RM_CAM_CAL_CONTEXT, RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT,
+ * RM_COREAON_SMARTREFLEX_CORE_CONTEXT, RM_COREAON_SMARTREFLEX_MM_CONTEXT,
+ * RM_COREAON_SMARTREFLEX_MPU_CONTEXT, RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT,
+ * RM_DSP_DSP_CONTEXT, RM_DSS_BB2D_CONTEXT, RM_DSS_DSS_CONTEXT,
+ * RM_EMIF_DMM_CONTEXT, RM_EMIF_EMIF1_CONTEXT, RM_EMIF_EMIF2_CONTEXT,
+ * RM_EMIF_EMIF_DLL_CONTEXT, RM_EMIF_EMIF_OCP_FW_CONTEXT,
+ * RM_EMU_DEBUGSS_CONTEXT, RM_GPU_GPU_CONTEXT, RM_IPU_IPU_CONTEXT,
+ * RM_IVA_IVA_CONTEXT, RM_IVA_SL2_CONTEXT, RM_L3INIT_IEEE1500_2_OCP_CONTEXT,
+ * RM_L3INIT_OCP2SCP1_CONTEXT, RM_L3INIT_OCP2SCP3_CONTEXT,
+ * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_UNIPRO2_CONTEXT,
+ * RM_L3INSTR_L3_INSTR_CONTEXT, RM_L3INSTR_L3_MAIN_3_CONTEXT,
+ * RM_L3INSTR_OCP_WP_NOC_CONTEXT, RM_L3MAIN1_L3_MAIN_1_CONTEXT,
+ * RM_L3MAIN2_L3_MAIN_2_CONTEXT, RM_L3MAIN2_OCMC_RAM_CONTEXT,
+ * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_OCP2SCP2_CONTEXT,
+ * RM_L4CFG_SAR_ROM_CONTEXT, RM_L4PER_ELM_CONTEXT, RM_L4PER_HDQ1W_CONTEXT,
+ * RM_L4PER_I2C2_CONTEXT, RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT,
+ * RM_L4PER_I2C5_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCSPI1_CONTEXT,
+ * RM_L4PER_MCSPI2_CONTEXT, RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT,
+ * RM_L4PER_MMC3_CONTEXT, RM_L4PER_MMC4_CONTEXT, RM_L4PER_MMC5_CONTEXT,
+ * RM_L4PER_TIMER10_CONTEXT, RM_L4PER_TIMER11_CONTEXT, RM_L4PER_TIMER2_CONTEXT,
+ * RM_L4PER_TIMER3_CONTEXT, RM_L4PER_TIMER4_CONTEXT, RM_L4PER_TIMER9_CONTEXT,
+ * RM_L4SEC_FPKA_CONTEXT, RM_MIPIEXT_LLI_CONTEXT,
+ * RM_MIPIEXT_LLI_OCP_FW_CONTEXT, RM_MIPIEXT_MPHY_CONTEXT, RM_MPU_MPU_CONTEXT,
+ * RM_WKUPAON_COUNTER_32K_CONTEXT, RM_WKUPAON_GPIO1_CONTEXT,
+ * RM_WKUPAON_KBD_CONTEXT, RM_WKUPAON_L4_WKUP_CONTEXT,
+ * RM_WKUPAON_SAR_RAM_CONTEXT, RM_WKUPAON_TIMER12_CONTEXT,
+ * RM_WKUPAON_TIMER1_CONTEXT, RM_WKUPAON_WD_TIMER1_CONTEXT,
+ * RM_WKUPAON_WD_TIMER2_CONTEXT
+ */
+#define OMAP54XX_LOSTCONTEXT_DFF_SHIFT                                          0
+#define OMAP54XX_LOSTCONTEXT_DFF_WIDTH                                          0x1
+#define OMAP54XX_LOSTCONTEXT_DFF_MASK                                           (1 << 0)
+/*
+ * Used by RM_C2C_C2C_CONTEXT, RM_C2C_C2C_OCP_FW_CONTEXT,
+ * RM_C2C_MODEM_ICR_CONTEXT, RM_DMA_DMA_SYSTEM_CONTEXT, RM_DSP_DSP_CONTEXT,
+ * RM_DSS_DSS_CONTEXT, RM_EMIF_DMM_CONTEXT, RM_EMIF_EMIF1_CONTEXT,
+ * RM_EMIF_EMIF2_CONTEXT, RM_EMIF_EMIF_OCP_FW_CONTEXT, RM_IPU_IPU_CONTEXT,
+ * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT,
+ * RM_L3INIT_USB_HOST_HS_CONTEXT, RM_L3INIT_USB_OTG_SS_CONTEXT,
+ * RM_L3INIT_USB_TLL_HS_CONTEXT, RM_L3INSTR_L3_MAIN_3_CONTEXT,
+ * RM_L3INSTR_OCP_WP_NOC_CONTEXT, RM_L3MAIN1_L3_MAIN_1_CONTEXT,
+ * RM_L3MAIN2_GPMC_CONTEXT, RM_L3MAIN2_L3_MAIN_2_CONTEXT,
+ * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_MAILBOX_CONTEXT,
+ * RM_L4CFG_SPINLOCK_CONTEXT, RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT,
+ * RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT,
+ * RM_L4PER_GPIO7_CONTEXT, RM_L4PER_GPIO8_CONTEXT, RM_L4PER_I2C1_CONTEXT,
+ * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT,
+ * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4PER_UART5_CONTEXT,
+ * RM_L4PER_UART6_CONTEXT, RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT,
+ * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_DMA_CRYPTO_CONTEXT, RM_L4SEC_RNG_CONTEXT,
+ * RM_L4SEC_SHA2MD5_CONTEXT, RM_MIPIEXT_LLI_CONTEXT,
+ * RM_MIPIEXT_LLI_OCP_FW_CONTEXT, RM_MIPIEXT_MPHY_CONTEXT, RM_MPU_MPU_CONTEXT
+ */
+#define OMAP54XX_LOSTCONTEXT_RFF_SHIFT                                          1
+#define OMAP54XX_LOSTCONTEXT_RFF_WIDTH                                          0x1
+#define OMAP54XX_LOSTCONTEXT_RFF_MASK                                           (1 << 1)
+/* Used by RM_ABE_AESS_CONTEXT */
+#define OMAP54XX_LOSTMEM_AESSMEM_SHIFT                                          8
+#define OMAP54XX_LOSTMEM_AESSMEM_WIDTH                                          0x1
+#define OMAP54XX_LOSTMEM_AESSMEM_MASK                                           (1 << 8)
+/* Used by RM_CAM_CAL_CONTEXT */
+#define OMAP54XX_LOSTMEM_CAL_MEM_SHIFT                                          8
+#define OMAP54XX_LOSTMEM_CAL_MEM_WIDTH                                          0x1
+#define OMAP54XX_LOSTMEM_CAL_MEM_MASK                                           (1 << 8)
+/* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */
+#define OMAP54XX_LOSTMEM_CAM_MEM_SHIFT                                          8
+#define OMAP54XX_LOSTMEM_CAM_MEM_WIDTH                                          0x1
+#define OMAP54XX_LOSTMEM_CAM_MEM_MASK                                           (1 << 8)
+/* Used by RM_EMIF_DMM_CONTEXT */
+#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_SHIFT                                   9
+#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_WIDTH                                   0x1
+#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_MASK                                    (1 << 9)
+/* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_L3INSTR_OCP_WP_NOC_CONTEXT */
+#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_SHIFT                               8
+#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_WIDTH                               0x1
+#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_MASK                                (1 << 8)
+/* Used by RM_L3MAIN2_OCMC_RAM_CONTEXT */
+#define OMAP54XX_LOSTMEM_CORE_OCMRAM_SHIFT                                      8
+#define OMAP54XX_LOSTMEM_CORE_OCMRAM_WIDTH                                      0x1
+#define OMAP54XX_LOSTMEM_CORE_OCMRAM_MASK                                       (1 << 8)
+/* Used by RM_DMA_DMA_SYSTEM_CONTEXT, RM_EMIF_DMM_CONTEXT */
+#define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_SHIFT                                  8
+#define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_WIDTH                                  0x1
+#define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_MASK                                   (1 << 8)
+/* Used by RM_DSP_DSP_CONTEXT */
+#define OMAP54XX_LOSTMEM_DSP_EDMA_SHIFT                                         10
+#define OMAP54XX_LOSTMEM_DSP_EDMA_WIDTH                                         0x1
+#define OMAP54XX_LOSTMEM_DSP_EDMA_MASK                                          (1 << 10)
+/* Used by RM_DSP_DSP_CONTEXT */
+#define OMAP54XX_LOSTMEM_DSP_L1_SHIFT                                           8
+#define OMAP54XX_LOSTMEM_DSP_L1_WIDTH                                           0x1
+#define OMAP54XX_LOSTMEM_DSP_L1_MASK                                            (1 << 8)
+/* Used by RM_DSP_DSP_CONTEXT */
+#define OMAP54XX_LOSTMEM_DSP_L2_SHIFT                                           9
+#define OMAP54XX_LOSTMEM_DSP_L2_WIDTH                                           0x1
+#define OMAP54XX_LOSTMEM_DSP_L2_MASK                                            (1 << 9)
+/* Used by RM_DSS_BB2D_CONTEXT, RM_DSS_DSS_CONTEXT */
+#define OMAP54XX_LOSTMEM_DSS_MEM_SHIFT                                          8
+#define OMAP54XX_LOSTMEM_DSS_MEM_WIDTH                                          0x1
+#define OMAP54XX_LOSTMEM_DSS_MEM_MASK                                           (1 << 8)
+/* Used by RM_EMU_DEBUGSS_CONTEXT */
+#define OMAP54XX_LOSTMEM_EMU_BANK_SHIFT                                         8
+#define OMAP54XX_LOSTMEM_EMU_BANK_WIDTH                                         0x1
+#define OMAP54XX_LOSTMEM_EMU_BANK_MASK                                          (1 << 8)
+/* Used by RM_GPU_GPU_CONTEXT */
+#define OMAP54XX_LOSTMEM_GPU_MEM_SHIFT                                          8
+#define OMAP54XX_LOSTMEM_GPU_MEM_WIDTH                                          0x1
+#define OMAP54XX_LOSTMEM_GPU_MEM_MASK                                           (1 << 8)
+/* Used by RM_IVA_IVA_CONTEXT */
+#define OMAP54XX_LOSTMEM_HWA_MEM_SHIFT                                          10
+#define OMAP54XX_LOSTMEM_HWA_MEM_WIDTH                                          0x1
+#define OMAP54XX_LOSTMEM_HWA_MEM_MASK                                           (1 << 10)
+/* Used by RM_IPU_IPU_CONTEXT */
+#define OMAP54XX_LOSTMEM_IPU_L2RAM_SHIFT                                        9
+#define OMAP54XX_LOSTMEM_IPU_L2RAM_WIDTH                                        0x1
+#define OMAP54XX_LOSTMEM_IPU_L2RAM_MASK                                         (1 << 9)
+/* Used by RM_IPU_IPU_CONTEXT */
+#define OMAP54XX_LOSTMEM_IPU_UNICACHE_SHIFT                                     8
+#define OMAP54XX_LOSTMEM_IPU_UNICACHE_WIDTH                                     0x1
+#define OMAP54XX_LOSTMEM_IPU_UNICACHE_MASK                                      (1 << 8)
+/*
+ * Used by RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT,
+ * RM_L3INIT_MMC2_CONTEXT, RM_L3INIT_SATA_CONTEXT, RM_L3INIT_UNIPRO2_CONTEXT,
+ * RM_L3INIT_USB_OTG_SS_CONTEXT
+ */
+#define OMAP54XX_LOSTMEM_L3INIT_BANK1_SHIFT                                     8
+#define OMAP54XX_LOSTMEM_L3INIT_BANK1_WIDTH                                     0x1
+#define OMAP54XX_LOSTMEM_L3INIT_BANK1_MASK                                      (1 << 8)
+/* Used by RM_MPU_MPU_CONTEXT */
+#define OMAP54XX_LOSTMEM_MPU_L2_SHIFT                                           9
+#define OMAP54XX_LOSTMEM_MPU_L2_WIDTH                                           0x1
+#define OMAP54XX_LOSTMEM_MPU_L2_MASK                                            (1 << 9)
+/* Used by RM_MPU_MPU_CONTEXT */
+#define OMAP54XX_LOSTMEM_MPU_RAM_SHIFT                                          10
+#define OMAP54XX_LOSTMEM_MPU_RAM_WIDTH                                          0x1
+#define OMAP54XX_LOSTMEM_MPU_RAM_MASK                                           (1 << 10)
+/*
+ * Used by RM_L4PER_MMC3_CONTEXT, RM_L4PER_MMC4_CONTEXT, RM_L4PER_MMC5_CONTEXT,
+ * RM_L4SEC_FPKA_CONTEXT
+ */
+#define OMAP54XX_LOSTMEM_NONRETAINED_BANK_SHIFT                                 8
+#define OMAP54XX_LOSTMEM_NONRETAINED_BANK_WIDTH                                 0x1
+#define OMAP54XX_LOSTMEM_NONRETAINED_BANK_MASK                                  (1 << 8)
+/*
+ * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT,
+ * RM_ABE_MCBSP3_CONTEXT, RM_ABE_MCPDM_CONTEXT, RM_ABE_SLIMBUS1_CONTEXT
+ */
+#define OMAP54XX_LOSTMEM_PERIHPMEM_SHIFT                                        8
+#define OMAP54XX_LOSTMEM_PERIHPMEM_WIDTH                                        0x1
+#define OMAP54XX_LOSTMEM_PERIHPMEM_MASK                                         (1 << 8)
+/*
+ * Used by RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT,
+ * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4PER_UART5_CONTEXT,
+ * RM_L4PER_UART6_CONTEXT, RM_L4SEC_DMA_CRYPTO_CONTEXT
+ */
+#define OMAP54XX_LOSTMEM_RETAINED_BANK_SHIFT                                    8
+#define OMAP54XX_LOSTMEM_RETAINED_BANK_WIDTH                                    0x1
+#define OMAP54XX_LOSTMEM_RETAINED_BANK_MASK                                     (1 << 8)
+/* Used by RM_IVA_SL2_CONTEXT */
+#define OMAP54XX_LOSTMEM_SL2_MEM_SHIFT                                          8
+#define OMAP54XX_LOSTMEM_SL2_MEM_WIDTH                                          0x1
+#define OMAP54XX_LOSTMEM_SL2_MEM_MASK                                           (1 << 8)
+/* Used by RM_IVA_IVA_CONTEXT */
+#define OMAP54XX_LOSTMEM_TCM1_MEM_SHIFT                                         8
+#define OMAP54XX_LOSTMEM_TCM1_MEM_WIDTH                                         0x1
+#define OMAP54XX_LOSTMEM_TCM1_MEM_MASK                                          (1 << 8)
+/* Used by RM_IVA_IVA_CONTEXT */
+#define OMAP54XX_LOSTMEM_TCM2_MEM_SHIFT                                         9
+#define OMAP54XX_LOSTMEM_TCM2_MEM_WIDTH                                         0x1
+#define OMAP54XX_LOSTMEM_TCM2_MEM_MASK                                          (1 << 9)
+/* Used by RM_WKUPAON_SAR_RAM_CONTEXT */
+#define OMAP54XX_LOSTMEM_WKUP_BANK_SHIFT                                        8
+#define OMAP54XX_LOSTMEM_WKUP_BANK_WIDTH                                        0x1
+#define OMAP54XX_LOSTMEM_WKUP_BANK_MASK                                         (1 << 8)
+/*
+ * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CORE_PWRSTCTRL,
+ * PM_CUSTEFUSE_PWRSTCTRL, PM_DSP_PWRSTCTRL, PM_DSS_PWRSTCTRL,
+ * PM_GPU_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_MPU_PWRSTCTRL
+ */
+#define OMAP54XX_LOWPOWERSTATECHANGE_SHIFT                                      4
+#define OMAP54XX_LOWPOWERSTATECHANGE_WIDTH                                      0x1
+#define OMAP54XX_LOWPOWERSTATECHANGE_MASK                                       (1 << 4)
+/* Used by PRM_DEBUG_TRANS_CFG */
+#define OMAP54XX_MODE_SHIFT                                                     0
+#define OMAP54XX_MODE_WIDTH                                                     0x2
+#define OMAP54XX_MODE_MASK                                                      (0x3 << 0)
+/* Used by PRM_MODEM_IF_CTRL */
+#define OMAP54XX_MODEM_SHUTDOWN_IRQ_SHIFT                                       9
+#define OMAP54XX_MODEM_SHUTDOWN_IRQ_WIDTH                                       0x1
+#define OMAP54XX_MODEM_SHUTDOWN_IRQ_MASK                                        (1 << 9)
+/* Used by PRM_MODEM_IF_CTRL */
+#define OMAP54XX_MODEM_WAKE_IRQ_SHIFT                                           8
+#define OMAP54XX_MODEM_WAKE_IRQ_WIDTH                                           0x1
+#define OMAP54XX_MODEM_WAKE_IRQ_MASK                                            (1 << 8)
+/* Used by PM_MPU_PWRSTCTRL */
+#define OMAP54XX_MPU_L2_ONSTATE_SHIFT                                           18
+#define OMAP54XX_MPU_L2_ONSTATE_WIDTH                                           0x2
+#define OMAP54XX_MPU_L2_ONSTATE_MASK                                            (0x3 << 18)
+/* Used by PM_MPU_PWRSTCTRL */
+#define OMAP54XX_MPU_L2_RETSTATE_SHIFT                                          9
+#define OMAP54XX_MPU_L2_RETSTATE_WIDTH                                          0x1
+#define OMAP54XX_MPU_L2_RETSTATE_MASK                                           (1 << 9)
+/* Used by PM_MPU_PWRSTST */
+#define OMAP54XX_MPU_L2_STATEST_SHIFT                                           6
+#define OMAP54XX_MPU_L2_STATEST_WIDTH                                           0x2
+#define OMAP54XX_MPU_L2_STATEST_MASK                                            (0x3 << 6)
+/* Used by PM_MPU_PWRSTCTRL */
+#define OMAP54XX_MPU_RAM_ONSTATE_SHIFT                                          20
+#define OMAP54XX_MPU_RAM_ONSTATE_WIDTH                                          0x2
+#define OMAP54XX_MPU_RAM_ONSTATE_MASK                                           (0x3 << 20)
+/* Used by PM_MPU_PWRSTCTRL */
+#define OMAP54XX_MPU_RAM_RETSTATE_SHIFT                                         10
+#define OMAP54XX_MPU_RAM_RETSTATE_WIDTH                                         0x1
+#define OMAP54XX_MPU_RAM_RETSTATE_MASK                                          (1 << 10)
+/* Used by PM_MPU_PWRSTST */
+#define OMAP54XX_MPU_RAM_STATEST_SHIFT                                          8
+#define OMAP54XX_MPU_RAM_STATEST_WIDTH                                          0x2
+#define OMAP54XX_MPU_RAM_STATEST_MASK                                           (0x3 << 8)
+/* Used by PRM_RSTST */
+#define OMAP54XX_MPU_SECURITY_VIOL_RST_SHIFT                                    2
+#define OMAP54XX_MPU_SECURITY_VIOL_RST_WIDTH                                    0x1
+#define OMAP54XX_MPU_SECURITY_VIOL_RST_MASK                                     (1 << 2)
+/* Used by PRM_RSTST */
+#define OMAP54XX_MPU_WDT_RST_SHIFT                                              3
+#define OMAP54XX_MPU_WDT_RST_WIDTH                                              0x1
+#define OMAP54XX_MPU_WDT_RST_MASK                                               (1 << 3)
+/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */
+#define OMAP54XX_NOCAP_SHIFT                                                    4
+#define OMAP54XX_NOCAP_WIDTH                                                    0x1
+#define OMAP54XX_NOCAP_MASK                                                     (1 << 4)
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP54XX_OCP_NRET_BANK_ONSTATE_SHIFT                                    24
+#define OMAP54XX_OCP_NRET_BANK_ONSTATE_WIDTH                                    0x2
+#define OMAP54XX_OCP_NRET_BANK_ONSTATE_MASK                                     (0x3 << 24)
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP54XX_OCP_NRET_BANK_RETSTATE_SHIFT                                   12
+#define OMAP54XX_OCP_NRET_BANK_RETSTATE_WIDTH                                   0x1
+#define OMAP54XX_OCP_NRET_BANK_RETSTATE_MASK                                    (1 << 12)
+/* Used by PM_CORE_PWRSTST */
+#define OMAP54XX_OCP_NRET_BANK_STATEST_SHIFT                                    12
+#define OMAP54XX_OCP_NRET_BANK_STATEST_WIDTH                                    0x2
+#define OMAP54XX_OCP_NRET_BANK_STATEST_MASK                                     (0x3 << 12)
+/*
+ * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L,
+ * PRM_VC_VAL_CMD_VDD_MPU_L
+ */
+#define OMAP54XX_OFF_SHIFT                                                      0
+#define OMAP54XX_OFF_WIDTH                                                      0x8
+#define OMAP54XX_OFF_MASK                                                       (0xff << 0)
+/*
+ * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L,
+ * PRM_VC_VAL_CMD_VDD_MPU_L
+ */
+#define OMAP54XX_ON_SHIFT                                                       24
+#define OMAP54XX_ON_WIDTH                                                       0x8
+#define OMAP54XX_ON_MASK                                                        (0xff << 24)
+/*
+ * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L,
+ * PRM_VC_VAL_CMD_VDD_MPU_L
+ */
+#define OMAP54XX_ONLP_SHIFT                                                     16
+#define OMAP54XX_ONLP_WIDTH                                                     0x8
+#define OMAP54XX_ONLP_MASK                                                      (0xff << 16)
+/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */
+#define OMAP54XX_OPP_CHANGE_SHIFT                                               2
+#define OMAP54XX_OPP_CHANGE_WIDTH                                               0x1
+#define OMAP54XX_OPP_CHANGE_MASK                                                (1 << 2)
+/* Used by PRM_VC_VAL_BYPASS */
+#define OMAP54XX_OPP_CHANGE_EMIF_LVL_SHIFT                                      25
+#define OMAP54XX_OPP_CHANGE_EMIF_LVL_WIDTH                                      0x1
+#define OMAP54XX_OPP_CHANGE_EMIF_LVL_MASK                                       (1 << 25)
+/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */
+#define OMAP54XX_OPP_SEL_SHIFT                                                  0
+#define OMAP54XX_OPP_SEL_WIDTH                                                  0x2
+#define OMAP54XX_OPP_SEL_MASK                                                   (0x3 << 0)
+/* Used by PRM_DEBUG_OUT */
+#define OMAP54XX_OUTPUT_SHIFT                                                   0
+#define OMAP54XX_OUTPUT_WIDTH                                                   0x20
+#define OMAP54XX_OUTPUT_MASK                                                    (0xffffffff << 0)
+/* Used by PRM_SRAM_COUNT */
+#define OMAP54XX_PCHARGECNT_VALUE_SHIFT                                         0
+#define OMAP54XX_PCHARGECNT_VALUE_WIDTH                                         0x6
+#define OMAP54XX_PCHARGECNT_VALUE_MASK                                          (0x3f << 0)
+/* Used by PRM_PSCON_COUNT */
+#define OMAP54XX_PCHARGE_TIME_SHIFT                                             0
+#define OMAP54XX_PCHARGE_TIME_WIDTH                                             0x8
+#define OMAP54XX_PCHARGE_TIME_MASK                                              (0xff << 0)
+/* Used by PM_ABE_PWRSTCTRL */
+#define OMAP54XX_PERIPHMEM_ONSTATE_SHIFT                                        20
+#define OMAP54XX_PERIPHMEM_ONSTATE_WIDTH                                        0x2
+#define OMAP54XX_PERIPHMEM_ONSTATE_MASK                                         (0x3 << 20)
+/* Used by PM_ABE_PWRSTCTRL */
+#define OMAP54XX_PERIPHMEM_RETSTATE_SHIFT                                       10
+#define OMAP54XX_PERIPHMEM_RETSTATE_WIDTH                                       0x1
+#define OMAP54XX_PERIPHMEM_RETSTATE_MASK                                        (1 << 10)
+/* Used by PM_ABE_PWRSTST */
+#define OMAP54XX_PERIPHMEM_STATEST_SHIFT                                        8
+#define OMAP54XX_PERIPHMEM_STATEST_WIDTH                                        0x2
+#define OMAP54XX_PERIPHMEM_STATEST_MASK                                         (0x3 << 8)
+/* Used by PRM_PHASE1_CNDP */
+#define OMAP54XX_PHASE1_CNDP_SHIFT                                              0
+#define OMAP54XX_PHASE1_CNDP_WIDTH                                              0x20
+#define OMAP54XX_PHASE1_CNDP_MASK                                               (0xffffffff << 0)
+/* Used by PRM_PHASE2A_CNDP */
+#define OMAP54XX_PHASE2A_CNDP_SHIFT                                             0
+#define OMAP54XX_PHASE2A_CNDP_WIDTH                                             0x20
+#define OMAP54XX_PHASE2A_CNDP_MASK                                              (0xffffffff << 0)
+/* Used by PRM_PHASE2B_CNDP */
+#define OMAP54XX_PHASE2B_CNDP_SHIFT                                             0
+#define OMAP54XX_PHASE2B_CNDP_WIDTH                                             0x20
+#define OMAP54XX_PHASE2B_CNDP_MASK                                              (0xffffffff << 0)
+/* Used by PRM_PSCON_COUNT */
+#define OMAP54XX_PONOUT_2_PGOODIN_TIME_SHIFT                                    8
+#define OMAP54XX_PONOUT_2_PGOODIN_TIME_WIDTH                                    0x8
+#define OMAP54XX_PONOUT_2_PGOODIN_TIME_MASK                                     (0xff << 8)
+/*
+ * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CORE_PWRSTCTRL,
+ * PM_CUSTEFUSE_PWRSTCTRL, PM_DSP_PWRSTCTRL, PM_DSS_PWRSTCTRL,
+ * PM_EMU_PWRSTCTRL, PM_GPU_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL,
+ * PM_MPU_PWRSTCTRL
+ */
+#define OMAP54XX_POWERSTATE_SHIFT                                               0
+#define OMAP54XX_POWERSTATE_WIDTH                                               0x2
+#define OMAP54XX_POWERSTATE_MASK                                                (0x3 << 0)
+/*
+ * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST,
+ * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
+ * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST
+ */
+#define OMAP54XX_POWERSTATEST_SHIFT                                             0
+#define OMAP54XX_POWERSTATEST_WIDTH                                             0x2
+#define OMAP54XX_POWERSTATEST_MASK                                              (0x3 << 0)
+/* Used by PRM_PWRREQCTRL */
+#define OMAP54XX_PWRREQ_COND_SHIFT                                              0
+#define OMAP54XX_PWRREQ_COND_WIDTH                                              0x2
+#define OMAP54XX_PWRREQ_COND_MASK                                               (0x3 << 0)
+/* Used by PRM_VC_SMPS_CORE_CONFIG */
+#define OMAP54XX_RACEN_VDD_CORE_L_SHIFT                                         27
+#define OMAP54XX_RACEN_VDD_CORE_L_WIDTH                                         0x1
+#define OMAP54XX_RACEN_VDD_CORE_L_MASK                                          (1 << 27)
+/* Used by PRM_VC_SMPS_MM_CONFIG */
+#define OMAP54XX_RACEN_VDD_MM_L_SHIFT                                           27
+#define OMAP54XX_RACEN_VDD_MM_L_WIDTH                                           0x1
+#define OMAP54XX_RACEN_VDD_MM_L_MASK                                            (1 << 27)
+/* Used by PRM_VC_SMPS_MPU_CONFIG */
+#define OMAP54XX_RACEN_VDD_MPU_L_SHIFT                                          27
+#define OMAP54XX_RACEN_VDD_MPU_L_WIDTH                                          0x1
+#define OMAP54XX_RACEN_VDD_MPU_L_MASK                                           (1 << 27)
+/* Used by PRM_VC_SMPS_CORE_CONFIG */
+#define OMAP54XX_RAC_VDD_CORE_L_SHIFT                                           26
+#define OMAP54XX_RAC_VDD_CORE_L_WIDTH                                           0x1
+#define OMAP54XX_RAC_VDD_CORE_L_MASK                                            (1 << 26)
+/* Used by PRM_VC_SMPS_MM_CONFIG */
+#define OMAP54XX_RAC_VDD_MM_L_SHIFT                                             26
+#define OMAP54XX_RAC_VDD_MM_L_WIDTH                                             0x1
+#define OMAP54XX_RAC_VDD_MM_L_MASK                                              (1 << 26)
+/* Used by PRM_VC_SMPS_MPU_CONFIG */
+#define OMAP54XX_RAC_VDD_MPU_L_SHIFT                                            26
+#define OMAP54XX_RAC_VDD_MPU_L_WIDTH                                            0x1
+#define OMAP54XX_RAC_VDD_MPU_L_MASK                                             (1 << 26)
+/*
+ * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
+ * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
+ * PRM_VOLTSETUP_MPU_RET_SLEEP
+ */
+#define OMAP54XX_RAMP_DOWN_COUNT_SHIFT                                          16
+#define OMAP54XX_RAMP_DOWN_COUNT_WIDTH                                          0x6
+#define OMAP54XX_RAMP_DOWN_COUNT_MASK                                           (0x3f << 16)
+/*
+ * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
+ * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
+ * PRM_VOLTSETUP_MPU_RET_SLEEP
+ */
+#define OMAP54XX_RAMP_DOWN_PRESCAL_SHIFT                                        24
+#define OMAP54XX_RAMP_DOWN_PRESCAL_WIDTH                                        0x2
+#define OMAP54XX_RAMP_DOWN_PRESCAL_MASK                                         (0x3 << 24)
+/*
+ * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
+ * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
+ * PRM_VOLTSETUP_MPU_RET_SLEEP
+ */
+#define OMAP54XX_RAMP_UP_COUNT_SHIFT                                            0
+#define OMAP54XX_RAMP_UP_COUNT_WIDTH                                            0x6
+#define OMAP54XX_RAMP_UP_COUNT_MASK                                             (0x3f << 0)
+/*
+ * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
+ * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
+ * PRM_VOLTSETUP_MPU_RET_SLEEP
+ */
+#define OMAP54XX_RAMP_UP_PRESCAL_SHIFT                                          8
+#define OMAP54XX_RAMP_UP_PRESCAL_WIDTH                                          0x2
+#define OMAP54XX_RAMP_UP_PRESCAL_MASK                                           (0x3 << 8)
+/* Used by PRM_VC_SMPS_CORE_CONFIG */
+#define OMAP54XX_RAV_VDD_CORE_L_SHIFT                                           25
+#define OMAP54XX_RAV_VDD_CORE_L_WIDTH                                           0x1
+#define OMAP54XX_RAV_VDD_CORE_L_MASK                                            (1 << 25)
+/* Used by PRM_VC_SMPS_MM_CONFIG */
+#define OMAP54XX_RAV_VDD_MM_L_SHIFT                                             25
+#define OMAP54XX_RAV_VDD_MM_L_WIDTH                                             0x1
+#define OMAP54XX_RAV_VDD_MM_L_MASK                                              (1 << 25)
+/* Used by PRM_VC_SMPS_MPU_CONFIG */
+#define OMAP54XX_RAV_VDD_MPU_L_SHIFT                                            25
+#define OMAP54XX_RAV_VDD_MPU_L_WIDTH                                            0x1
+#define OMAP54XX_RAV_VDD_MPU_L_MASK                                             (1 << 25)
+/* Used by PRM_VC_VAL_BYPASS */
+#define OMAP54XX_REGADDR_SHIFT                                                  8
+#define OMAP54XX_REGADDR_WIDTH                                                  0x8
+#define OMAP54XX_REGADDR_MASK                                                   (0xff << 8)
+/*
+ * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L,
+ * PRM_VC_VAL_CMD_VDD_MPU_L
+ */
+#define OMAP54XX_RET_SHIFT                                                      8
+#define OMAP54XX_RET_WIDTH                                                      0x8
+#define OMAP54XX_RET_MASK                                                       (0xff << 8)
+/* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */
+#define OMAP54XX_RETMODE_ENABLE_SHIFT                                           0
+#define OMAP54XX_RETMODE_ENABLE_WIDTH                                           0x1
+#define OMAP54XX_RETMODE_ENABLE_MASK                                            (1 << 0)
+/* Used by PRM_RSTTIME */
+#define OMAP54XX_RSTTIME1_SHIFT                                                 0
+#define OMAP54XX_RSTTIME1_WIDTH                                                 0xa
+#define OMAP54XX_RSTTIME1_MASK                                                  (0x3ff << 0)
+/* Used by PRM_RSTTIME */
+#define OMAP54XX_RSTTIME2_SHIFT                                                 10
+#define OMAP54XX_RSTTIME2_WIDTH                                                 0x5
+#define OMAP54XX_RSTTIME2_MASK                                                  (0x1f << 10)
+/* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */
+#define OMAP54XX_RST_CPU0_SHIFT                                                 0
+#define OMAP54XX_RST_CPU0_WIDTH                                                 0x1
+#define OMAP54XX_RST_CPU0_MASK                                                  (1 << 0)
+/* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */
+#define OMAP54XX_RST_CPU1_SHIFT                                                 1
+#define OMAP54XX_RST_CPU1_WIDTH                                                 0x1
+#define OMAP54XX_RST_CPU1_MASK                                                  (1 << 1)
+/* Used by RM_DSP_RSTCTRL, RM_DSP_RSTST */
+#define OMAP54XX_RST_DSP_SHIFT                                                  0
+#define OMAP54XX_RST_DSP_WIDTH                                                  0x1
+#define OMAP54XX_RST_DSP_MASK                                                   (1 << 0)
+/* Used by RM_DSP_RSTST */
+#define OMAP54XX_RST_DSP_EMU_SHIFT                                              2
+#define OMAP54XX_RST_DSP_EMU_WIDTH                                              0x1
+#define OMAP54XX_RST_DSP_EMU_MASK                                               (1 << 2)
+/* Used by RM_DSP_RSTST */
+#define OMAP54XX_RST_DSP_EMU_REQ_SHIFT                                          3
+#define OMAP54XX_RST_DSP_EMU_REQ_WIDTH                                          0x1
+#define OMAP54XX_RST_DSP_EMU_REQ_MASK                                           (1 << 3)
+/* Used by RM_DSP_RSTCTRL, RM_DSP_RSTST */
+#define OMAP54XX_RST_DSP_MMU_CACHE_SHIFT                                        1
+#define OMAP54XX_RST_DSP_MMU_CACHE_WIDTH                                        0x1
+#define OMAP54XX_RST_DSP_MMU_CACHE_MASK                                         (1 << 1)
+/* Used by RM_IPU_RSTST */
+#define OMAP54XX_RST_EMULATION_CPU0_SHIFT                                       3
+#define OMAP54XX_RST_EMULATION_CPU0_WIDTH                                       0x1
+#define OMAP54XX_RST_EMULATION_CPU0_MASK                                        (1 << 3)
+/* Used by RM_IPU_RSTST */
+#define OMAP54XX_RST_EMULATION_CPU1_SHIFT                                       4
+#define OMAP54XX_RST_EMULATION_CPU1_WIDTH                                       0x1
+#define OMAP54XX_RST_EMULATION_CPU1_MASK                                        (1 << 4)
+/* Used by RM_IVA_RSTST */
+#define OMAP54XX_RST_EMULATION_SEQ1_SHIFT                                       3
+#define OMAP54XX_RST_EMULATION_SEQ1_WIDTH                                       0x1
+#define OMAP54XX_RST_EMULATION_SEQ1_MASK                                        (1 << 3)
+/* Used by RM_IVA_RSTST */
+#define OMAP54XX_RST_EMULATION_SEQ2_SHIFT                                       4
+#define OMAP54XX_RST_EMULATION_SEQ2_WIDTH                                       0x1
+#define OMAP54XX_RST_EMULATION_SEQ2_MASK                                        (1 << 4)
+/* Used by PRM_RSTCTRL */
+#define OMAP54XX_RST_GLOBAL_COLD_SW_SHIFT                                       1
+#define OMAP54XX_RST_GLOBAL_COLD_SW_WIDTH                                       0x1
+#define OMAP54XX_RST_GLOBAL_COLD_SW_MASK                                        (1 << 1)
+/* Used by PRM_RSTCTRL */
+#define OMAP54XX_RST_GLOBAL_WARM_SW_SHIFT                                       0
+#define OMAP54XX_RST_GLOBAL_WARM_SW_WIDTH                                       0x1
+#define OMAP54XX_RST_GLOBAL_WARM_SW_MASK                                        (1 << 0)
+/* Used by RM_IPU_RSTST */
+#define OMAP54XX_RST_ICECRUSHER_CPU0_SHIFT                                      5
+#define OMAP54XX_RST_ICECRUSHER_CPU0_WIDTH                                      0x1
+#define OMAP54XX_RST_ICECRUSHER_CPU0_MASK                                       (1 << 5)
+/* Used by RM_IPU_RSTST */
+#define OMAP54XX_RST_ICECRUSHER_CPU1_SHIFT                                      6
+#define OMAP54XX_RST_ICECRUSHER_CPU1_WIDTH                                      0x1
+#define OMAP54XX_RST_ICECRUSHER_CPU1_MASK                                       (1 << 6)
+/* Used by RM_IVA_RSTST */
+#define OMAP54XX_RST_ICECRUSHER_SEQ1_SHIFT                                      5
+#define OMAP54XX_RST_ICECRUSHER_SEQ1_WIDTH                                      0x1
+#define OMAP54XX_RST_ICECRUSHER_SEQ1_MASK                                       (1 << 5)
+/* Used by RM_IVA_RSTST */
+#define OMAP54XX_RST_ICECRUSHER_SEQ2_SHIFT                                      6
+#define OMAP54XX_RST_ICECRUSHER_SEQ2_WIDTH                                      0x1
+#define OMAP54XX_RST_ICECRUSHER_SEQ2_MASK                                       (1 << 6)
+/* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */
+#define OMAP54XX_RST_IPU_MMU_CACHE_SHIFT                                        2
+#define OMAP54XX_RST_IPU_MMU_CACHE_WIDTH                                        0x1
+#define OMAP54XX_RST_IPU_MMU_CACHE_MASK                                         (1 << 2)
+/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */
+#define OMAP54XX_RST_LOGIC_SHIFT                                                2
+#define OMAP54XX_RST_LOGIC_WIDTH                                                0x1
+#define OMAP54XX_RST_LOGIC_MASK                                                 (1 << 2)
+/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */
+#define OMAP54XX_RST_SEQ1_SHIFT                                                 0
+#define OMAP54XX_RST_SEQ1_WIDTH                                                 0x1
+#define OMAP54XX_RST_SEQ1_MASK                                                  (1 << 0)
+/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */
+#define OMAP54XX_RST_SEQ2_SHIFT                                                 1
+#define OMAP54XX_RST_SEQ2_WIDTH                                                 0x1
+#define OMAP54XX_RST_SEQ2_MASK                                                  (1 << 1)
+/* Used by REVISION_PRM */
+#define OMAP54XX_R_RTL_SHIFT                                                    11
+#define OMAP54XX_R_RTL_WIDTH                                                    0x5
+#define OMAP54XX_R_RTL_MASK                                                     (0x1f << 11)
+/* Used by PRM_VC_SMPS_CORE_CONFIG */
+#define OMAP54XX_SA_VDD_CORE_L_SHIFT                                            0
+#define OMAP54XX_SA_VDD_CORE_L_WIDTH                                            0x7
+#define OMAP54XX_SA_VDD_CORE_L_MASK                                             (0x7f << 0)
+/* Used by PRM_VC_SMPS_MM_CONFIG */
+#define OMAP54XX_SA_VDD_MM_L_SHIFT                                              0
+#define OMAP54XX_SA_VDD_MM_L_WIDTH                                              0x7
+#define OMAP54XX_SA_VDD_MM_L_MASK                                               (0x7f << 0)
+/* Used by PRM_VC_SMPS_MPU_CONFIG */
+#define OMAP54XX_SA_VDD_MPU_L_SHIFT                                             0
+#define OMAP54XX_SA_VDD_MPU_L_WIDTH                                             0x7
+#define OMAP54XX_SA_VDD_MPU_L_MASK                                              (0x7f << 0)
+/* Used by REVISION_PRM */
+#define OMAP54XX_SCHEME_SHIFT                                                   30
+#define OMAP54XX_SCHEME_WIDTH                                                   0x2
+#define OMAP54XX_SCHEME_MASK                                                    (0x3 << 30)
+/* Used by PRM_VC_CFG_I2C_CLK */
+#define OMAP54XX_SCLH_SHIFT                                                     0
+#define OMAP54XX_SCLH_WIDTH                                                     0x8
+#define OMAP54XX_SCLH_MASK                                                      (0xff << 0)
+/* Used by PRM_VC_CFG_I2C_CLK */
+#define OMAP54XX_SCLL_SHIFT                                                     8
+#define OMAP54XX_SCLL_WIDTH                                                     0x8
+#define OMAP54XX_SCLL_MASK                                                      (0xff << 8)
+/* Used by PRM_RSTST */
+#define OMAP54XX_SECURE_WDT_RST_SHIFT                                           4
+#define OMAP54XX_SECURE_WDT_RST_WIDTH                                           0x1
+#define OMAP54XX_SECURE_WDT_RST_MASK                                            (1 << 4)
+/* Used by PRM_VC_SMPS_CORE_CONFIG */
+#define OMAP54XX_SEL_SA_VDD_CORE_L_SHIFT                                        24
+#define OMAP54XX_SEL_SA_VDD_CORE_L_WIDTH                                        0x1
+#define OMAP54XX_SEL_SA_VDD_CORE_L_MASK                                         (1 << 24)
+/* Used by PRM_VC_SMPS_MM_CONFIG */
+#define OMAP54XX_SEL_SA_VDD_MM_L_SHIFT                                          24
+#define OMAP54XX_SEL_SA_VDD_MM_L_WIDTH                                          0x1
+#define OMAP54XX_SEL_SA_VDD_MM_L_MASK                                           (1 << 24)
+/* Used by PRM_VC_SMPS_MPU_CONFIG */
+#define OMAP54XX_SEL_SA_VDD_MPU_L_SHIFT                                         24
+#define OMAP54XX_SEL_SA_VDD_MPU_L_WIDTH                                         0x1
+#define OMAP54XX_SEL_SA_VDD_MPU_L_MASK                                          (1 << 24)
+/* Used by PM_IVA_PWRSTCTRL */
+#define OMAP54XX_SL2_MEM_ONSTATE_SHIFT                                          18
+#define OMAP54XX_SL2_MEM_ONSTATE_WIDTH                                          0x2
+#define OMAP54XX_SL2_MEM_ONSTATE_MASK                                           (0x3 << 18)
+/* Used by PM_IVA_PWRSTCTRL */
+#define OMAP54XX_SL2_MEM_RETSTATE_SHIFT                                         9
+#define OMAP54XX_SL2_MEM_RETSTATE_WIDTH                                         0x1
+#define OMAP54XX_SL2_MEM_RETSTATE_MASK                                          (1 << 9)
+/* Used by PM_IVA_PWRSTST */
+#define OMAP54XX_SL2_MEM_STATEST_SHIFT                                          6
+#define OMAP54XX_SL2_MEM_STATEST_WIDTH                                          0x2
+#define OMAP54XX_SL2_MEM_STATEST_MASK                                           (0x3 << 6)
+/* Used by PRM_VC_VAL_BYPASS */
+#define OMAP54XX_SLAVEADDR_SHIFT                                                0
+#define OMAP54XX_SLAVEADDR_WIDTH                                                0x7
+#define OMAP54XX_SLAVEADDR_MASK                                                 (0x7f << 0)
+/* Used by PRM_SRAM_COUNT */
+#define OMAP54XX_SLPCNT_VALUE_SHIFT                                             16
+#define OMAP54XX_SLPCNT_VALUE_WIDTH                                             0x8
+#define OMAP54XX_SLPCNT_VALUE_MASK                                              (0xff << 16)
+/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_MM_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
+#define OMAP54XX_SMPSWAITTIMEMAX_SHIFT                                          8
+#define OMAP54XX_SMPSWAITTIMEMAX_WIDTH                                          0x10
+#define OMAP54XX_SMPSWAITTIMEMAX_MASK                                           (0xffff << 8)
+/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_MM_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
+#define OMAP54XX_SMPSWAITTIMEMIN_SHIFT                                          8
+#define OMAP54XX_SMPSWAITTIMEMIN_WIDTH                                          0x10
+#define OMAP54XX_SMPSWAITTIMEMIN_MASK                                           (0xffff << 8)
+/* Used by PRM_VC_CORE_ERRST */
+#define OMAP54XX_SMPS_RA_ERR_CORE_SHIFT                                         1
+#define OMAP54XX_SMPS_RA_ERR_CORE_WIDTH                                         0x1
+#define OMAP54XX_SMPS_RA_ERR_CORE_MASK                                          (1 << 1)
+/* Used by PRM_VC_MM_ERRST */
+#define OMAP54XX_SMPS_RA_ERR_MM_SHIFT                                           1
+#define OMAP54XX_SMPS_RA_ERR_MM_WIDTH                                           0x1
+#define OMAP54XX_SMPS_RA_ERR_MM_MASK                                            (1 << 1)
+/* Used by PRM_VC_MPU_ERRST */
+#define OMAP54XX_SMPS_RA_ERR_MPU_SHIFT                                          1
+#define OMAP54XX_SMPS_RA_ERR_MPU_WIDTH                                          0x1
+#define OMAP54XX_SMPS_RA_ERR_MPU_MASK                                           (1 << 1)
+/* Used by PRM_VC_CORE_ERRST */
+#define OMAP54XX_SMPS_SA_ERR_CORE_SHIFT                                         0
+#define OMAP54XX_SMPS_SA_ERR_CORE_WIDTH                                         0x1
+#define OMAP54XX_SMPS_SA_ERR_CORE_MASK                                          (1 << 0)
+/* Used by PRM_VC_MM_ERRST */
+#define OMAP54XX_SMPS_SA_ERR_MM_SHIFT                                           0
+#define OMAP54XX_SMPS_SA_ERR_MM_WIDTH                                           0x1
+#define OMAP54XX_SMPS_SA_ERR_MM_MASK                                            (1 << 0)
+/* Used by PRM_VC_MPU_ERRST */
+#define OMAP54XX_SMPS_SA_ERR_MPU_SHIFT                                          0
+#define OMAP54XX_SMPS_SA_ERR_MPU_WIDTH                                          0x1
+#define OMAP54XX_SMPS_SA_ERR_MPU_MASK                                           (1 << 0)
+/* Used by PRM_VC_CORE_ERRST */
+#define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_SHIFT                                    2
+#define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_WIDTH                                    0x1
+#define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_MASK                                     (1 << 2)
+/* Used by PRM_VC_MM_ERRST */
+#define OMAP54XX_SMPS_TIMEOUT_ERR_MM_SHIFT                                      2
+#define OMAP54XX_SMPS_TIMEOUT_ERR_MM_WIDTH                                      0x1
+#define OMAP54XX_SMPS_TIMEOUT_ERR_MM_MASK                                       (1 << 2)
+/* Used by PRM_VC_MPU_ERRST */
+#define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_SHIFT                                     2
+#define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_WIDTH                                     0x1
+#define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_MASK                                      (1 << 2)
+/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */
+#define OMAP54XX_SR2EN_SHIFT                                                    0
+#define OMAP54XX_SR2EN_WIDTH                                                    0x1
+#define OMAP54XX_SR2EN_MASK                                                     (1 << 0)
+/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */
+#define OMAP54XX_SR2_IN_TRANSITION_SHIFT                                        6
+#define OMAP54XX_SR2_IN_TRANSITION_WIDTH                                        0x1
+#define OMAP54XX_SR2_IN_TRANSITION_MASK                                         (1 << 6)
+/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */
+#define OMAP54XX_SR2_STATUS_SHIFT                                               3
+#define OMAP54XX_SR2_STATUS_WIDTH                                               0x2
+#define OMAP54XX_SR2_STATUS_MASK                                                (0x3 << 3)
+/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */
+#define OMAP54XX_SR2_WTCNT_VALUE_SHIFT                                          8
+#define OMAP54XX_SR2_WTCNT_VALUE_WIDTH                                          0x8
+#define OMAP54XX_SR2_WTCNT_VALUE_MASK                                           (0xff << 8)
+/* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */
+#define OMAP54XX_SRAMLDO_STATUS_SHIFT                                           8
+#define OMAP54XX_SRAMLDO_STATUS_WIDTH                                           0x1
+#define OMAP54XX_SRAMLDO_STATUS_MASK                                            (1 << 8)
+/* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */
+#define OMAP54XX_SRAM_IN_TRANSITION_SHIFT                                       9
+#define OMAP54XX_SRAM_IN_TRANSITION_WIDTH                                       0x1
+#define OMAP54XX_SRAM_IN_TRANSITION_MASK                                        (1 << 9)
+/* Used by PRM_VC_CFG_I2C_MODE */
+#define OMAP54XX_SRMODEEN_SHIFT                                                 4
+#define OMAP54XX_SRMODEEN_WIDTH                                                 0x1
+#define OMAP54XX_SRMODEEN_MASK                                                  (1 << 4)
+/* Used by PRM_VOLTSETUP_WARMRESET */
+#define OMAP54XX_STABLE_COUNT_SHIFT                                             0
+#define OMAP54XX_STABLE_COUNT_WIDTH                                             0x6
+#define OMAP54XX_STABLE_COUNT_MASK                                              (0x3f << 0)
+/* Used by PRM_VOLTSETUP_WARMRESET */
+#define OMAP54XX_STABLE_PRESCAL_SHIFT                                           8
+#define OMAP54XX_STABLE_PRESCAL_WIDTH                                           0x2
+#define OMAP54XX_STABLE_PRESCAL_MASK                                            (0x3 << 8)
+/* Used by PRM_BANDGAP_SETUP */
+#define OMAP54XX_STARTUP_COUNT_SHIFT                                            0
+#define OMAP54XX_STARTUP_COUNT_WIDTH                                            0x8
+#define OMAP54XX_STARTUP_COUNT_MASK                                             (0xff << 0)
+/* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */
+#define OMAP54XX_STARTUP_COUNT_24_31_SHIFT                                      24
+#define OMAP54XX_STARTUP_COUNT_24_31_WIDTH                                      0x8
+#define OMAP54XX_STARTUP_COUNT_24_31_MASK                                       (0xff << 24)
+/* Used by PM_IVA_PWRSTCTRL */
+#define OMAP54XX_TCM1_MEM_ONSTATE_SHIFT                                         20
+#define OMAP54XX_TCM1_MEM_ONSTATE_WIDTH                                         0x2
+#define OMAP54XX_TCM1_MEM_ONSTATE_MASK                                          (0x3 << 20)
+/* Used by PM_IVA_PWRSTCTRL */
+#define OMAP54XX_TCM1_MEM_RETSTATE_SHIFT                                        10
+#define OMAP54XX_TCM1_MEM_RETSTATE_WIDTH                                        0x1
+#define OMAP54XX_TCM1_MEM_RETSTATE_MASK                                         (1 << 10)
+/* Used by PM_IVA_PWRSTST */
+#define OMAP54XX_TCM1_MEM_STATEST_SHIFT                                         8
+#define OMAP54XX_TCM1_MEM_STATEST_WIDTH                                         0x2
+#define OMAP54XX_TCM1_MEM_STATEST_MASK                                          (0x3 << 8)
+/* Used by PM_IVA_PWRSTCTRL */
+#define OMAP54XX_TCM2_MEM_ONSTATE_SHIFT                                         22
+#define OMAP54XX_TCM2_MEM_ONSTATE_WIDTH                                         0x2
+#define OMAP54XX_TCM2_MEM_ONSTATE_MASK                                          (0x3 << 22)
+/* Used by PM_IVA_PWRSTCTRL */
+#define OMAP54XX_TCM2_MEM_RETSTATE_SHIFT                                        11
+#define OMAP54XX_TCM2_MEM_RETSTATE_WIDTH                                        0x1
+#define OMAP54XX_TCM2_MEM_RETSTATE_MASK                                         (1 << 11)
+/* Used by PM_IVA_PWRSTST */
+#define OMAP54XX_TCM2_MEM_STATEST_SHIFT                                         10
+#define OMAP54XX_TCM2_MEM_STATEST_WIDTH                                         0x2
+#define OMAP54XX_TCM2_MEM_STATEST_MASK                                          (0x3 << 10)
+/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */
+#define OMAP54XX_TIMEOUT_SHIFT                                                  0
+#define OMAP54XX_TIMEOUT_WIDTH                                                  0x10
+#define OMAP54XX_TIMEOUT_MASK                                                   (0xffff << 0)
+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
+#define OMAP54XX_TIMEOUTEN_SHIFT                                                3
+#define OMAP54XX_TIMEOUTEN_WIDTH                                                0x1
+#define OMAP54XX_TIMEOUTEN_MASK                                                 (1 << 3)
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_TRANSITION_EN_SHIFT                                            8
+#define OMAP54XX_TRANSITION_EN_WIDTH                                            0x1
+#define OMAP54XX_TRANSITION_EN_MASK                                             (1 << 8)
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_TRANSITION_ST_SHIFT                                            8
+#define OMAP54XX_TRANSITION_ST_WIDTH                                            0x1
+#define OMAP54XX_TRANSITION_ST_MASK                                             (1 << 8)
+/* Used by PRM_DEBUG_TRANS_CFG */
+#define OMAP54XX_TRIGGER_CLEAR_SHIFT                                            2
+#define OMAP54XX_TRIGGER_CLEAR_WIDTH                                            0x1
+#define OMAP54XX_TRIGGER_CLEAR_MASK                                             (1 << 2)
+/* Used by PRM_RSTST */
+#define OMAP54XX_TSHUT_CORE_RST_SHIFT                                           13
+#define OMAP54XX_TSHUT_CORE_RST_WIDTH                                           0x1
+#define OMAP54XX_TSHUT_CORE_RST_MASK                                            (1 << 13)
+/* Used by PRM_RSTST */
+#define OMAP54XX_TSHUT_MM_RST_SHIFT                                             12
+#define OMAP54XX_TSHUT_MM_RST_WIDTH                                             0x1
+#define OMAP54XX_TSHUT_MM_RST_MASK                                              (1 << 12)
+/* Used by PRM_RSTST */
+#define OMAP54XX_TSHUT_MPU_RST_SHIFT                                            11
+#define OMAP54XX_TSHUT_MPU_RST_WIDTH                                            0x1
+#define OMAP54XX_TSHUT_MPU_RST_MASK                                             (1 << 11)
+/* Used by PRM_VC_VAL_BYPASS */
+#define OMAP54XX_VALID_SHIFT                                                    24
+#define OMAP54XX_VALID_WIDTH                                                    0x1
+#define OMAP54XX_VALID_MASK                                                     (1 << 24)
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VC_BYPASSACK_EN_SHIFT                                          14
+#define OMAP54XX_VC_BYPASSACK_EN_WIDTH                                          0x1
+#define OMAP54XX_VC_BYPASSACK_EN_MASK                                           (1 << 14)
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VC_BYPASSACK_ST_SHIFT                                          14
+#define OMAP54XX_VC_BYPASSACK_ST_WIDTH                                          0x1
+#define OMAP54XX_VC_BYPASSACK_ST_MASK                                           (1 << 14)
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VC_CORE_VPACK_EN_SHIFT                                         22
+#define OMAP54XX_VC_CORE_VPACK_EN_WIDTH                                         0x1
+#define OMAP54XX_VC_CORE_VPACK_EN_MASK                                          (1 << 22)
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VC_CORE_VPACK_ST_SHIFT                                         22
+#define OMAP54XX_VC_CORE_VPACK_ST_WIDTH                                         0x1
+#define OMAP54XX_VC_CORE_VPACK_ST_MASK                                          (1 << 22)
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VC_MM_VPACK_EN_SHIFT                                           30
+#define OMAP54XX_VC_MM_VPACK_EN_WIDTH                                           0x1
+#define OMAP54XX_VC_MM_VPACK_EN_MASK                                            (1 << 30)
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VC_MM_VPACK_ST_SHIFT                                           30
+#define OMAP54XX_VC_MM_VPACK_ST_WIDTH                                           0x1
+#define OMAP54XX_VC_MM_VPACK_ST_MASK                                            (1 << 30)
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP54XX_VC_MPU_VPACK_EN_SHIFT                                          6
+#define OMAP54XX_VC_MPU_VPACK_EN_WIDTH                                          0x1
+#define OMAP54XX_VC_MPU_VPACK_EN_MASK                                           (1 << 6)
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP54XX_VC_MPU_VPACK_ST_SHIFT                                          6
+#define OMAP54XX_VC_MPU_VPACK_ST_WIDTH                                          0x1
+#define OMAP54XX_VC_MPU_VPACK_ST_MASK                                           (1 << 6)
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VC_RAERR_EN_SHIFT                                              12
+#define OMAP54XX_VC_RAERR_EN_WIDTH                                              0x1
+#define OMAP54XX_VC_RAERR_EN_MASK                                               (1 << 12)
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VC_RAERR_ST_SHIFT                                              12
+#define OMAP54XX_VC_RAERR_ST_WIDTH                                              0x1
+#define OMAP54XX_VC_RAERR_ST_MASK                                               (1 << 12)
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VC_SAERR_EN_SHIFT                                              11
+#define OMAP54XX_VC_SAERR_EN_WIDTH                                              0x1
+#define OMAP54XX_VC_SAERR_EN_MASK                                               (1 << 11)
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VC_SAERR_ST_SHIFT                                              11
+#define OMAP54XX_VC_SAERR_ST_WIDTH                                              0x1
+#define OMAP54XX_VC_SAERR_ST_MASK                                               (1 << 11)
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VC_TOERR_EN_SHIFT                                              13
+#define OMAP54XX_VC_TOERR_EN_WIDTH                                              0x1
+#define OMAP54XX_VC_TOERR_EN_MASK                                               (1 << 13)
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VC_TOERR_ST_SHIFT                                              13
+#define OMAP54XX_VC_TOERR_ST_WIDTH                                              0x1
+#define OMAP54XX_VC_TOERR_ST_MASK                                               (1 << 13)
+/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */
+#define OMAP54XX_VDDMAX_SHIFT                                                   24
+#define OMAP54XX_VDDMAX_WIDTH                                                   0x8
+#define OMAP54XX_VDDMAX_MASK                                                    (0xff << 24)
+/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */
+#define OMAP54XX_VDDMIN_SHIFT                                                   16
+#define OMAP54XX_VDDMIN_WIDTH                                                   0x8
+#define OMAP54XX_VDDMIN_MASK                                                    (0xff << 16)
+/* Used by PRM_VOLTCTRL */
+#define OMAP54XX_VDD_CORE_I2C_DISABLE_SHIFT                                     12
+#define OMAP54XX_VDD_CORE_I2C_DISABLE_WIDTH                                     0x1
+#define OMAP54XX_VDD_CORE_I2C_DISABLE_MASK                                      (1 << 12)
+/* Used by PRM_RSTST */
+#define OMAP54XX_VDD_CORE_VOLT_MGR_RST_SHIFT                                    8
+#define OMAP54XX_VDD_CORE_VOLT_MGR_RST_WIDTH                                    0x1
+#define OMAP54XX_VDD_CORE_VOLT_MGR_RST_MASK                                     (1 << 8)
+/* Used by PRM_VOLTCTRL */
+#define OMAP54XX_VDD_MM_I2C_DISABLE_SHIFT                                       14
+#define OMAP54XX_VDD_MM_I2C_DISABLE_WIDTH                                       0x1
+#define OMAP54XX_VDD_MM_I2C_DISABLE_MASK                                        (1 << 14)
+/* Used by PRM_VOLTCTRL */
+#define OMAP54XX_VDD_MM_PRESENCE_SHIFT                                          9
+#define OMAP54XX_VDD_MM_PRESENCE_WIDTH                                          0x1
+#define OMAP54XX_VDD_MM_PRESENCE_MASK                                           (1 << 9)
+/* Used by PRM_RSTST */
+#define OMAP54XX_VDD_MM_VOLT_MGR_RST_SHIFT                                      7
+#define OMAP54XX_VDD_MM_VOLT_MGR_RST_WIDTH                                      0x1
+#define OMAP54XX_VDD_MM_VOLT_MGR_RST_MASK                                       (1 << 7)
+/* Used by PRM_VOLTCTRL */
+#define OMAP54XX_VDD_MPU_I2C_DISABLE_SHIFT                                      13
+#define OMAP54XX_VDD_MPU_I2C_DISABLE_WIDTH                                      0x1
+#define OMAP54XX_VDD_MPU_I2C_DISABLE_MASK                                       (1 << 13)
+/* Used by PRM_VOLTCTRL */
+#define OMAP54XX_VDD_MPU_PRESENCE_SHIFT                                         8
+#define OMAP54XX_VDD_MPU_PRESENCE_WIDTH                                         0x1
+#define OMAP54XX_VDD_MPU_PRESENCE_MASK                                          (1 << 8)
+/* Used by PRM_RSTST */
+#define OMAP54XX_VDD_MPU_VOLT_MGR_RST_SHIFT                                     6
+#define OMAP54XX_VDD_MPU_VOLT_MGR_RST_WIDTH                                     0x1
+#define OMAP54XX_VDD_MPU_VOLT_MGR_RST_MASK                                      (1 << 6)
+/* Used by PRM_VC_CORE_ERRST */
+#define OMAP54XX_VFSM_RA_ERR_CORE_SHIFT                                         4
+#define OMAP54XX_VFSM_RA_ERR_CORE_WIDTH                                         0x1
+#define OMAP54XX_VFSM_RA_ERR_CORE_MASK                                          (1 << 4)
+/* Used by PRM_VC_MM_ERRST */
+#define OMAP54XX_VFSM_RA_ERR_MM_SHIFT                                           4
+#define OMAP54XX_VFSM_RA_ERR_MM_WIDTH                                           0x1
+#define OMAP54XX_VFSM_RA_ERR_MM_MASK                                            (1 << 4)
+/* Used by PRM_VC_MPU_ERRST */
+#define OMAP54XX_VFSM_RA_ERR_MPU_SHIFT                                          4
+#define OMAP54XX_VFSM_RA_ERR_MPU_WIDTH                                          0x1
+#define OMAP54XX_VFSM_RA_ERR_MPU_MASK                                           (1 << 4)
+/* Used by PRM_VC_CORE_ERRST */
+#define OMAP54XX_VFSM_SA_ERR_CORE_SHIFT                                         3
+#define OMAP54XX_VFSM_SA_ERR_CORE_WIDTH                                         0x1
+#define OMAP54XX_VFSM_SA_ERR_CORE_MASK                                          (1 << 3)
+/* Used by PRM_VC_MM_ERRST */
+#define OMAP54XX_VFSM_SA_ERR_MM_SHIFT                                           3
+#define OMAP54XX_VFSM_SA_ERR_MM_WIDTH                                           0x1
+#define OMAP54XX_VFSM_SA_ERR_MM_MASK                                            (1 << 3)
+/* Used by PRM_VC_MPU_ERRST */
+#define OMAP54XX_VFSM_SA_ERR_MPU_SHIFT                                          3
+#define OMAP54XX_VFSM_SA_ERR_MPU_WIDTH                                          0x1
+#define OMAP54XX_VFSM_SA_ERR_MPU_MASK                                           (1 << 3)
+/* Used by PRM_VC_CORE_ERRST */
+#define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_SHIFT                                    5
+#define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_WIDTH                                    0x1
+#define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_MASK                                     (1 << 5)
+/* Used by PRM_VC_MM_ERRST */
+#define OMAP54XX_VFSM_TIMEOUT_ERR_MM_SHIFT                                      5
+#define OMAP54XX_VFSM_TIMEOUT_ERR_MM_WIDTH                                      0x1
+#define OMAP54XX_VFSM_TIMEOUT_ERR_MM_MASK                                       (1 << 5)
+/* Used by PRM_VC_MPU_ERRST */
+#define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_SHIFT                                     5
+#define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_WIDTH                                     0x1
+#define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_MASK                                      (1 << 5)
+/* Used by PRM_VC_SMPS_CORE_CONFIG */
+#define OMAP54XX_VOLRA_VDD_CORE_L_SHIFT                                         8
+#define OMAP54XX_VOLRA_VDD_CORE_L_WIDTH                                         0x8
+#define OMAP54XX_VOLRA_VDD_CORE_L_MASK                                          (0xff << 8)
+/* Used by PRM_VC_SMPS_MM_CONFIG */
+#define OMAP54XX_VOLRA_VDD_MM_L_SHIFT                                           8
+#define OMAP54XX_VOLRA_VDD_MM_L_WIDTH                                           0x8
+#define OMAP54XX_VOLRA_VDD_MM_L_MASK                                            (0xff << 8)
+/* Used by PRM_VC_SMPS_MPU_CONFIG */
+#define OMAP54XX_VOLRA_VDD_MPU_L_SHIFT                                          8
+#define OMAP54XX_VOLRA_VDD_MPU_L_WIDTH                                          0x8
+#define OMAP54XX_VOLRA_VDD_MPU_L_MASK                                           (0xff << 8)
+/* Used by PRM_VOLTST_MM, PRM_VOLTST_MPU */
+#define OMAP54XX_VOLTSTATEST_SHIFT                                              0
+#define OMAP54XX_VOLTSTATEST_WIDTH                                              0x2
+#define OMAP54XX_VOLTSTATEST_MASK                                               (0x3 << 0)
+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
+#define OMAP54XX_VPENABLE_SHIFT                                                 0
+#define OMAP54XX_VPENABLE_WIDTH                                                 0x1
+#define OMAP54XX_VPENABLE_MASK                                                  (1 << 0)
+/* Used by PRM_VP_CORE_STATUS, PRM_VP_MM_STATUS, PRM_VP_MPU_STATUS */
+#define OMAP54XX_VPINIDLE_SHIFT                                                 0
+#define OMAP54XX_VPINIDLE_WIDTH                                                 0x1
+#define OMAP54XX_VPINIDLE_MASK                                                  (1 << 0)
+/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_MM_VOLTAGE, PRM_VP_MPU_VOLTAGE */
+#define OMAP54XX_VPVOLTAGE_SHIFT                                                0
+#define OMAP54XX_VPVOLTAGE_WIDTH                                                0x8
+#define OMAP54XX_VPVOLTAGE_MASK                                                 (0xff << 0)
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VP_CORE_EQVALUE_EN_SHIFT                                       20
+#define OMAP54XX_VP_CORE_EQVALUE_EN_WIDTH                                       0x1
+#define OMAP54XX_VP_CORE_EQVALUE_EN_MASK                                        (1 << 20)
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VP_CORE_EQVALUE_ST_SHIFT                                       20
+#define OMAP54XX_VP_CORE_EQVALUE_ST_WIDTH                                       0x1
+#define OMAP54XX_VP_CORE_EQVALUE_ST_MASK                                        (1 << 20)
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VP_CORE_MAXVDD_EN_SHIFT                                        18
+#define OMAP54XX_VP_CORE_MAXVDD_EN_WIDTH                                        0x1
+#define OMAP54XX_VP_CORE_MAXVDD_EN_MASK                                         (1 << 18)
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VP_CORE_MAXVDD_ST_SHIFT                                        18
+#define OMAP54XX_VP_CORE_MAXVDD_ST_WIDTH                                        0x1
+#define OMAP54XX_VP_CORE_MAXVDD_ST_MASK                                         (1 << 18)
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VP_CORE_MINVDD_EN_SHIFT                                        17
+#define OMAP54XX_VP_CORE_MINVDD_EN_WIDTH                                        0x1
+#define OMAP54XX_VP_CORE_MINVDD_EN_MASK                                         (1 << 17)
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VP_CORE_MINVDD_ST_SHIFT                                        17
+#define OMAP54XX_VP_CORE_MINVDD_ST_WIDTH                                        0x1
+#define OMAP54XX_VP_CORE_MINVDD_ST_MASK                                         (1 << 17)
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VP_CORE_NOSMPSACK_EN_SHIFT                                     19
+#define OMAP54XX_VP_CORE_NOSMPSACK_EN_WIDTH                                     0x1
+#define OMAP54XX_VP_CORE_NOSMPSACK_EN_MASK                                      (1 << 19)
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VP_CORE_NOSMPSACK_ST_SHIFT                                     19
+#define OMAP54XX_VP_CORE_NOSMPSACK_ST_WIDTH                                     0x1
+#define OMAP54XX_VP_CORE_NOSMPSACK_ST_MASK                                      (1 << 19)
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_SHIFT                                 16
+#define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_WIDTH                                 0x1
+#define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_MASK                                  (1 << 16)
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_SHIFT                                 16
+#define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_WIDTH                                 0x1
+#define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_MASK                                  (1 << 16)
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VP_CORE_TRANXDONE_EN_SHIFT                                     21
+#define OMAP54XX_VP_CORE_TRANXDONE_EN_WIDTH                                     0x1
+#define OMAP54XX_VP_CORE_TRANXDONE_EN_MASK                                      (1 << 21)
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VP_CORE_TRANXDONE_ST_SHIFT                                     21
+#define OMAP54XX_VP_CORE_TRANXDONE_ST_WIDTH                                     0x1
+#define OMAP54XX_VP_CORE_TRANXDONE_ST_MASK                                      (1 << 21)
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VP_MM_EQVALUE_EN_SHIFT                                         28
+#define OMAP54XX_VP_MM_EQVALUE_EN_WIDTH                                         0x1
+#define OMAP54XX_VP_MM_EQVALUE_EN_MASK                                          (1 << 28)
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VP_MM_EQVALUE_ST_SHIFT                                         28
+#define OMAP54XX_VP_MM_EQVALUE_ST_WIDTH                                         0x1
+#define OMAP54XX_VP_MM_EQVALUE_ST_MASK                                          (1 << 28)
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VP_MM_MAXVDD_EN_SHIFT                                          26
+#define OMAP54XX_VP_MM_MAXVDD_EN_WIDTH                                          0x1
+#define OMAP54XX_VP_MM_MAXVDD_EN_MASK                                           (1 << 26)
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VP_MM_MAXVDD_ST_SHIFT                                          26
+#define OMAP54XX_VP_MM_MAXVDD_ST_WIDTH                                          0x1
+#define OMAP54XX_VP_MM_MAXVDD_ST_MASK                                           (1 << 26)
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VP_MM_MINVDD_EN_SHIFT                                          25
+#define OMAP54XX_VP_MM_MINVDD_EN_WIDTH                                          0x1
+#define OMAP54XX_VP_MM_MINVDD_EN_MASK                                           (1 << 25)
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VP_MM_MINVDD_ST_SHIFT                                          25
+#define OMAP54XX_VP_MM_MINVDD_ST_WIDTH                                          0x1
+#define OMAP54XX_VP_MM_MINVDD_ST_MASK                                           (1 << 25)
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VP_MM_NOSMPSACK_EN_SHIFT                                       27
+#define OMAP54XX_VP_MM_NOSMPSACK_EN_WIDTH                                       0x1
+#define OMAP54XX_VP_MM_NOSMPSACK_EN_MASK                                        (1 << 27)
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VP_MM_NOSMPSACK_ST_SHIFT                                       27
+#define OMAP54XX_VP_MM_NOSMPSACK_ST_WIDTH                                       0x1
+#define OMAP54XX_VP_MM_NOSMPSACK_ST_MASK                                        (1 << 27)
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_SHIFT                                   24
+#define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_WIDTH                                   0x1
+#define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_MASK                                    (1 << 24)
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_SHIFT                                   24
+#define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_WIDTH                                   0x1
+#define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_MASK                                    (1 << 24)
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VP_MM_TRANXDONE_EN_SHIFT                                       29
+#define OMAP54XX_VP_MM_TRANXDONE_EN_WIDTH                                       0x1
+#define OMAP54XX_VP_MM_TRANXDONE_EN_MASK                                        (1 << 29)
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VP_MM_TRANXDONE_ST_SHIFT                                       29
+#define OMAP54XX_VP_MM_TRANXDONE_ST_WIDTH                                       0x1
+#define OMAP54XX_VP_MM_TRANXDONE_ST_MASK                                        (1 << 29)
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP54XX_VP_MPU_EQVALUE_EN_SHIFT                                        4
+#define OMAP54XX_VP_MPU_EQVALUE_EN_WIDTH                                        0x1
+#define OMAP54XX_VP_MPU_EQVALUE_EN_MASK                                         (1 << 4)
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP54XX_VP_MPU_EQVALUE_ST_SHIFT                                        4
+#define OMAP54XX_VP_MPU_EQVALUE_ST_WIDTH                                        0x1
+#define OMAP54XX_VP_MPU_EQVALUE_ST_MASK                                         (1 << 4)
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP54XX_VP_MPU_MAXVDD_EN_SHIFT                                         2
+#define OMAP54XX_VP_MPU_MAXVDD_EN_WIDTH                                         0x1
+#define OMAP54XX_VP_MPU_MAXVDD_EN_MASK                                          (1 << 2)
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP54XX_VP_MPU_MAXVDD_ST_SHIFT                                         2
+#define OMAP54XX_VP_MPU_MAXVDD_ST_WIDTH                                         0x1
+#define OMAP54XX_VP_MPU_MAXVDD_ST_MASK                                          (1 << 2)
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP54XX_VP_MPU_MINVDD_EN_SHIFT                                         1
+#define OMAP54XX_VP_MPU_MINVDD_EN_WIDTH                                         0x1
+#define OMAP54XX_VP_MPU_MINVDD_EN_MASK                                          (1 << 1)
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP54XX_VP_MPU_MINVDD_ST_SHIFT                                         1
+#define OMAP54XX_VP_MPU_MINVDD_ST_WIDTH                                         0x1
+#define OMAP54XX_VP_MPU_MINVDD_ST_MASK                                          (1 << 1)
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP54XX_VP_MPU_NOSMPSACK_EN_SHIFT                                      3
+#define OMAP54XX_VP_MPU_NOSMPSACK_EN_WIDTH                                      0x1
+#define OMAP54XX_VP_MPU_NOSMPSACK_EN_MASK                                       (1 << 3)
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP54XX_VP_MPU_NOSMPSACK_ST_SHIFT                                      3
+#define OMAP54XX_VP_MPU_NOSMPSACK_ST_WIDTH                                      0x1
+#define OMAP54XX_VP_MPU_NOSMPSACK_ST_MASK                                       (1 << 3)
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_SHIFT                                  0
+#define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_WIDTH                                  0x1
+#define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_MASK                                   (1 << 0)
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_SHIFT                                  0
+#define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_WIDTH                                  0x1
+#define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_MASK                                   (1 << 0)
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP54XX_VP_MPU_TRANXDONE_EN_SHIFT                                      5
+#define OMAP54XX_VP_MPU_TRANXDONE_EN_WIDTH                                      0x1
+#define OMAP54XX_VP_MPU_TRANXDONE_EN_MASK                                       (1 << 5)
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP54XX_VP_MPU_TRANXDONE_ST_SHIFT                                      5
+#define OMAP54XX_VP_MPU_TRANXDONE_ST_WIDTH                                      0x1
+#define OMAP54XX_VP_MPU_TRANXDONE_ST_MASK                                       (1 << 5)
+/* Used by PRM_SRAM_COUNT */
+#define OMAP54XX_VSETUPCNT_VALUE_SHIFT                                          8
+#define OMAP54XX_VSETUPCNT_VALUE_WIDTH                                          0x8
+#define OMAP54XX_VSETUPCNT_VALUE_MASK                                           (0xff << 8)
+/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_MM_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
+#define OMAP54XX_VSTEPMAX_SHIFT                                                 0
+#define OMAP54XX_VSTEPMAX_WIDTH                                                 0x8
+#define OMAP54XX_VSTEPMAX_MASK                                                  (0xff << 0)
+/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_MM_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
+#define OMAP54XX_VSTEPMIN_SHIFT                                                 0
+#define OMAP54XX_VSTEPMIN_WIDTH                                                 0x8
+#define OMAP54XX_VSTEPMIN_MASK                                                  (0xff << 0)
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DISPC_DSP_SHIFT                                        2
+#define OMAP54XX_WKUPDEP_DISPC_DSP_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_DISPC_DSP_MASK                                         (1 << 2)
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DISPC_IPU_SHIFT                                        1
+#define OMAP54XX_WKUPDEP_DISPC_IPU_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_DISPC_IPU_MASK                                         (1 << 1)
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DISPC_MPU_SHIFT                                        0
+#define OMAP54XX_WKUPDEP_DISPC_MPU_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_DISPC_MPU_MASK                                         (1 << 0)
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DISPC_SDMA_SHIFT                                       3
+#define OMAP54XX_WKUPDEP_DISPC_SDMA_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_DISPC_SDMA_MASK                                        (1 << 3)
+/* Used by PM_ABE_DMIC_WKDEP */
+#define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_SHIFT                                     6
+#define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_MASK                                      (1 << 6)
+/* Used by PM_ABE_DMIC_WKDEP */
+#define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_SHIFT                                    7
+#define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_MASK                                     (1 << 7)
+/* Used by PM_ABE_DMIC_WKDEP */
+#define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_SHIFT                                     2
+#define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_MASK                                      (1 << 2)
+/* Used by PM_ABE_DMIC_WKDEP */
+#define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_SHIFT                                     0
+#define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_MASK                                      (1 << 0)
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DSI1_A_DSP_SHIFT                                       6
+#define OMAP54XX_WKUPDEP_DSI1_A_DSP_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_DSI1_A_DSP_MASK                                        (1 << 6)
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DSI1_A_IPU_SHIFT                                       5
+#define OMAP54XX_WKUPDEP_DSI1_A_IPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_DSI1_A_IPU_MASK                                        (1 << 5)
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DSI1_A_MPU_SHIFT                                       4
+#define OMAP54XX_WKUPDEP_DSI1_A_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_DSI1_A_MPU_MASK                                        (1 << 4)
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DSI1_A_SDMA_SHIFT                                      7
+#define OMAP54XX_WKUPDEP_DSI1_A_SDMA_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_DSI1_A_SDMA_MASK                                       (1 << 7)
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DSI1_B_DSP_SHIFT                                       10
+#define OMAP54XX_WKUPDEP_DSI1_B_DSP_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_DSI1_B_DSP_MASK                                        (1 << 10)
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DSI1_B_IPU_SHIFT                                       9
+#define OMAP54XX_WKUPDEP_DSI1_B_IPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_DSI1_B_IPU_MASK                                        (1 << 9)
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DSI1_B_MPU_SHIFT                                       8
+#define OMAP54XX_WKUPDEP_DSI1_B_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_DSI1_B_MPU_MASK                                        (1 << 8)
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DSI1_B_SDMA_SHIFT                                      11
+#define OMAP54XX_WKUPDEP_DSI1_B_SDMA_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_DSI1_B_SDMA_MASK                                       (1 << 11)
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DSI1_C_DSP_SHIFT                                       17
+#define OMAP54XX_WKUPDEP_DSI1_C_DSP_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_DSI1_C_DSP_MASK                                        (1 << 17)
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DSI1_C_IPU_SHIFT                                       16
+#define OMAP54XX_WKUPDEP_DSI1_C_IPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_DSI1_C_IPU_MASK                                        (1 << 16)
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DSI1_C_MPU_SHIFT                                       15
+#define OMAP54XX_WKUPDEP_DSI1_C_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_DSI1_C_MPU_MASK                                        (1 << 15)
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DSI1_C_SDMA_SHIFT                                      18
+#define OMAP54XX_WKUPDEP_DSI1_C_SDMA_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_DSI1_C_SDMA_MASK                                       (1 << 18)
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_SHIFT                                   1
+#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_MASK                                    (1 << 1)
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT                                   0
+#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_MASK                                    (1 << 0)
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_SHIFT                                   6
+#define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_MASK                                    (1 << 6)
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_SHIFT                                   1
+#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_MASK                                    (1 << 1)
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT                                   0
+#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_MASK                                    (1 << 0)
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_SHIFT                                   6
+#define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_MASK                                    (1 << 6)
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT                                   0
+#define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_MASK                                    (1 << 0)
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_SHIFT                                   6
+#define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_MASK                                    (1 << 6)
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT                                   0
+#define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_MASK                                    (1 << 0)
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_SHIFT                                   6
+#define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_MASK                                    (1 << 6)
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT                                   0
+#define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_MASK                                    (1 << 0)
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_SHIFT                                   6
+#define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_MASK                                    (1 << 6)
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT                                   0
+#define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_MASK                                    (1 << 0)
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_SHIFT                                   6
+#define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_MASK                                    (1 << 6)
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_SHIFT                                   0
+#define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_MASK                                    (1 << 0)
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_SHIFT                                   0
+#define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_MASK                                    (1 << 0)
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_SHIFT                                     19
+#define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_MASK                                      (1 << 19)
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_SHIFT                                      14
+#define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_MASK                                       (1 << 14)
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_SHIFT                                      13
+#define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_MASK                                       (1 << 13)
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_SHIFT                                      12
+#define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_MASK                                       (1 << 12)
+/* Used by PM_L3INIT_HSI_WKDEP */
+#define OMAP54XX_WKUPDEP_HSI_DSP_DSP_SHIFT                                      6
+#define OMAP54XX_WKUPDEP_HSI_DSP_DSP_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_HSI_DSP_DSP_MASK                                       (1 << 6)
+/* Used by PM_L3INIT_HSI_WKDEP */
+#define OMAP54XX_WKUPDEP_HSI_MCU_IPU_SHIFT                                      1
+#define OMAP54XX_WKUPDEP_HSI_MCU_IPU_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_HSI_MCU_IPU_MASK                                       (1 << 1)
+/* Used by PM_L3INIT_HSI_WKDEP */
+#define OMAP54XX_WKUPDEP_HSI_MCU_MPU_SHIFT                                      0
+#define OMAP54XX_WKUPDEP_HSI_MCU_MPU_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_HSI_MCU_MPU_MASK                                       (1 << 0)
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_SHIFT                                    7
+#define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_MASK                                     (1 << 7)
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_SHIFT                                     1
+#define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_MASK                                      (1 << 1)
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_SHIFT                                     0
+#define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_MASK                                      (1 << 0)
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_SHIFT                                    7
+#define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_MASK                                     (1 << 7)
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_SHIFT                                     1
+#define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_MASK                                      (1 << 1)
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_SHIFT                                     0
+#define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_MASK                                      (1 << 0)
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_SHIFT                                    7
+#define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_MASK                                     (1 << 7)
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_SHIFT                                     1
+#define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_MASK                                      (1 << 1)
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_SHIFT                                     0
+#define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_MASK                                      (1 << 0)
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_SHIFT                                    7
+#define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_MASK                                     (1 << 7)
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_SHIFT                                     1
+#define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_MASK                                      (1 << 1)
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_SHIFT                                     0
+#define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_MASK                                      (1 << 0)
+/* Used by PM_L4PER_I2C5_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_SHIFT                                     0
+#define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_MASK                                      (1 << 0)
+/* Used by PM_WKUPAON_KBD_WKDEP */
+#define OMAP54XX_WKUPDEP_KBD_MPU_SHIFT                                          0
+#define OMAP54XX_WKUPDEP_KBD_MPU_WIDTH                                          0x1
+#define OMAP54XX_WKUPDEP_KBD_MPU_MASK                                           (1 << 0)
+/* Used by PM_ABE_MCASP_WKDEP */
+#define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_SHIFT                                    6
+#define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_MASK                                     (1 << 6)
+/* Used by PM_ABE_MCASP_WKDEP */
+#define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_SHIFT                                   7
+#define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_MASK                                    (1 << 7)
+/* Used by PM_ABE_MCASP_WKDEP */
+#define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_SHIFT                                    2
+#define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_MASK                                     (1 << 2)
+/* Used by PM_ABE_MCASP_WKDEP */
+#define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_SHIFT                                    0
+#define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_MASK                                     (1 << 0)
+/* Used by PM_ABE_MCBSP1_WKDEP */
+#define OMAP54XX_WKUPDEP_MCBSP1_DSP_SHIFT                                       2
+#define OMAP54XX_WKUPDEP_MCBSP1_DSP_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCBSP1_DSP_MASK                                        (1 << 2)
+/* Used by PM_ABE_MCBSP1_WKDEP */
+#define OMAP54XX_WKUPDEP_MCBSP1_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_MCBSP1_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCBSP1_MPU_MASK                                        (1 << 0)
+/* Used by PM_ABE_MCBSP1_WKDEP */
+#define OMAP54XX_WKUPDEP_MCBSP1_SDMA_SHIFT                                      3
+#define OMAP54XX_WKUPDEP_MCBSP1_SDMA_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_MCBSP1_SDMA_MASK                                       (1 << 3)
+/* Used by PM_ABE_MCBSP2_WKDEP */
+#define OMAP54XX_WKUPDEP_MCBSP2_DSP_SHIFT                                       2
+#define OMAP54XX_WKUPDEP_MCBSP2_DSP_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCBSP2_DSP_MASK                                        (1 << 2)
+/* Used by PM_ABE_MCBSP2_WKDEP */
+#define OMAP54XX_WKUPDEP_MCBSP2_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_MCBSP2_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCBSP2_MPU_MASK                                        (1 << 0)
+/* Used by PM_ABE_MCBSP2_WKDEP */
+#define OMAP54XX_WKUPDEP_MCBSP2_SDMA_SHIFT                                      3
+#define OMAP54XX_WKUPDEP_MCBSP2_SDMA_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_MCBSP2_SDMA_MASK                                       (1 << 3)
+/* Used by PM_ABE_MCBSP3_WKDEP */
+#define OMAP54XX_WKUPDEP_MCBSP3_DSP_SHIFT                                       2
+#define OMAP54XX_WKUPDEP_MCBSP3_DSP_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCBSP3_DSP_MASK                                        (1 << 2)
+/* Used by PM_ABE_MCBSP3_WKDEP */
+#define OMAP54XX_WKUPDEP_MCBSP3_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_MCBSP3_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCBSP3_MPU_MASK                                        (1 << 0)
+/* Used by PM_ABE_MCBSP3_WKDEP */
+#define OMAP54XX_WKUPDEP_MCBSP3_SDMA_SHIFT                                      3
+#define OMAP54XX_WKUPDEP_MCBSP3_SDMA_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_MCBSP3_SDMA_MASK                                       (1 << 3)
+/* Used by PM_ABE_MCPDM_WKDEP */
+#define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_SHIFT                                    6
+#define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_MASK                                     (1 << 6)
+/* Used by PM_ABE_MCPDM_WKDEP */
+#define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_SHIFT                                   7
+#define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_MASK                                    (1 << 7)
+/* Used by PM_ABE_MCPDM_WKDEP */
+#define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_SHIFT                                    2
+#define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_MASK                                     (1 << 2)
+/* Used by PM_ABE_MCPDM_WKDEP */
+#define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_SHIFT                                    0
+#define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_MASK                                     (1 << 0)
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define OMAP54XX_WKUPDEP_MCSPI1_DSP_SHIFT                                       2
+#define OMAP54XX_WKUPDEP_MCSPI1_DSP_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCSPI1_DSP_MASK                                        (1 << 2)
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define OMAP54XX_WKUPDEP_MCSPI1_IPU_SHIFT                                       1
+#define OMAP54XX_WKUPDEP_MCSPI1_IPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCSPI1_IPU_MASK                                        (1 << 1)
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define OMAP54XX_WKUPDEP_MCSPI1_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_MCSPI1_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCSPI1_MPU_MASK                                        (1 << 0)
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define OMAP54XX_WKUPDEP_MCSPI1_SDMA_SHIFT                                      3
+#define OMAP54XX_WKUPDEP_MCSPI1_SDMA_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_MCSPI1_SDMA_MASK                                       (1 << 3)
+/* Used by PM_L4PER_MCSPI2_WKDEP */
+#define OMAP54XX_WKUPDEP_MCSPI2_IPU_SHIFT                                       1
+#define OMAP54XX_WKUPDEP_MCSPI2_IPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCSPI2_IPU_MASK                                        (1 << 1)
+/* Used by PM_L4PER_MCSPI2_WKDEP */
+#define OMAP54XX_WKUPDEP_MCSPI2_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_MCSPI2_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCSPI2_MPU_MASK                                        (1 << 0)
+/* Used by PM_L4PER_MCSPI2_WKDEP */
+#define OMAP54XX_WKUPDEP_MCSPI2_SDMA_SHIFT                                      3
+#define OMAP54XX_WKUPDEP_MCSPI2_SDMA_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_MCSPI2_SDMA_MASK                                       (1 << 3)
+/* Used by PM_L4PER_MCSPI3_WKDEP */
+#define OMAP54XX_WKUPDEP_MCSPI3_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_MCSPI3_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCSPI3_MPU_MASK                                        (1 << 0)
+/* Used by PM_L4PER_MCSPI3_WKDEP */
+#define OMAP54XX_WKUPDEP_MCSPI3_SDMA_SHIFT                                      3
+#define OMAP54XX_WKUPDEP_MCSPI3_SDMA_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_MCSPI3_SDMA_MASK                                       (1 << 3)
+/* Used by PM_L4PER_MCSPI4_WKDEP */
+#define OMAP54XX_WKUPDEP_MCSPI4_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_MCSPI4_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCSPI4_MPU_MASK                                        (1 << 0)
+/* Used by PM_L4PER_MCSPI4_WKDEP */
+#define OMAP54XX_WKUPDEP_MCSPI4_SDMA_SHIFT                                      3
+#define OMAP54XX_WKUPDEP_MCSPI4_SDMA_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_MCSPI4_SDMA_MASK                                       (1 << 3)
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC1_DSP_SHIFT                                         2
+#define OMAP54XX_WKUPDEP_MMC1_DSP_WIDTH                                         0x1
+#define OMAP54XX_WKUPDEP_MMC1_DSP_MASK                                          (1 << 2)
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC1_IPU_SHIFT                                         1
+#define OMAP54XX_WKUPDEP_MMC1_IPU_WIDTH                                         0x1
+#define OMAP54XX_WKUPDEP_MMC1_IPU_MASK                                          (1 << 1)
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC1_MPU_SHIFT                                         0
+#define OMAP54XX_WKUPDEP_MMC1_MPU_WIDTH                                         0x1
+#define OMAP54XX_WKUPDEP_MMC1_MPU_MASK                                          (1 << 0)
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC1_SDMA_SHIFT                                        3
+#define OMAP54XX_WKUPDEP_MMC1_SDMA_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_MMC1_SDMA_MASK                                         (1 << 3)
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC2_DSP_SHIFT                                         2
+#define OMAP54XX_WKUPDEP_MMC2_DSP_WIDTH                                         0x1
+#define OMAP54XX_WKUPDEP_MMC2_DSP_MASK                                          (1 << 2)
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC2_IPU_SHIFT                                         1
+#define OMAP54XX_WKUPDEP_MMC2_IPU_WIDTH                                         0x1
+#define OMAP54XX_WKUPDEP_MMC2_IPU_MASK                                          (1 << 1)
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC2_MPU_SHIFT                                         0
+#define OMAP54XX_WKUPDEP_MMC2_MPU_WIDTH                                         0x1
+#define OMAP54XX_WKUPDEP_MMC2_MPU_MASK                                          (1 << 0)
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC2_SDMA_SHIFT                                        3
+#define OMAP54XX_WKUPDEP_MMC2_SDMA_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_MMC2_SDMA_MASK                                         (1 << 3)
+/* Used by PM_L4PER_MMC3_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC3_IPU_SHIFT                                         1
+#define OMAP54XX_WKUPDEP_MMC3_IPU_WIDTH                                         0x1
+#define OMAP54XX_WKUPDEP_MMC3_IPU_MASK                                          (1 << 1)
+/* Used by PM_L4PER_MMC3_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC3_MPU_SHIFT                                         0
+#define OMAP54XX_WKUPDEP_MMC3_MPU_WIDTH                                         0x1
+#define OMAP54XX_WKUPDEP_MMC3_MPU_MASK                                          (1 << 0)
+/* Used by PM_L4PER_MMC3_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC3_SDMA_SHIFT                                        3
+#define OMAP54XX_WKUPDEP_MMC3_SDMA_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_MMC3_SDMA_MASK                                         (1 << 3)
+/* Used by PM_L4PER_MMC4_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC4_MPU_SHIFT                                         0
+#define OMAP54XX_WKUPDEP_MMC4_MPU_WIDTH                                         0x1
+#define OMAP54XX_WKUPDEP_MMC4_MPU_MASK                                          (1 << 0)
+/* Used by PM_L4PER_MMC4_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC4_SDMA_SHIFT                                        3
+#define OMAP54XX_WKUPDEP_MMC4_SDMA_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_MMC4_SDMA_MASK                                         (1 << 3)
+/* Used by PM_L4PER_MMC5_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC5_MPU_SHIFT                                         0
+#define OMAP54XX_WKUPDEP_MMC5_MPU_WIDTH                                         0x1
+#define OMAP54XX_WKUPDEP_MMC5_MPU_MASK                                          (1 << 0)
+/* Used by PM_L4PER_MMC5_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC5_SDMA_SHIFT                                        3
+#define OMAP54XX_WKUPDEP_MMC5_SDMA_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_MMC5_SDMA_MASK                                         (1 << 3)
+/* Used by PM_L3INIT_SATA_WKDEP */
+#define OMAP54XX_WKUPDEP_SATA_MPU_SHIFT                                         0
+#define OMAP54XX_WKUPDEP_SATA_MPU_WIDTH                                         0x1
+#define OMAP54XX_WKUPDEP_SATA_MPU_MASK                                          (1 << 0)
+/* Used by PM_ABE_SLIMBUS1_WKDEP */
+#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_SHIFT                                 6
+#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_WIDTH                                 0x1
+#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_MASK                                  (1 << 6)
+/* Used by PM_ABE_SLIMBUS1_WKDEP */
+#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT                                7
+#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_WIDTH                                0x1
+#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK                                 (1 << 7)
+/* Used by PM_ABE_SLIMBUS1_WKDEP */
+#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_SHIFT                                 2
+#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_WIDTH                                 0x1
+#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_MASK                                  (1 << 2)
+/* Used by PM_ABE_SLIMBUS1_WKDEP */
+#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT                                 0
+#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_WIDTH                                 0x1
+#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK                                  (1 << 0)
+/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
+#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_SHIFT                             1
+#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_WIDTH                             0x1
+#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_MASK                              (1 << 1)
+/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
+#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_SHIFT                             0
+#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_WIDTH                             0x1
+#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_MASK                              (1 << 0)
+/* Used by PM_COREAON_SMARTREFLEX_MM_WKDEP */
+#define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_SHIFT                               0
+#define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_WIDTH                               0x1
+#define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_MASK                                (1 << 0)
+/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */
+#define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_SHIFT                              0
+#define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_WIDTH                              0x1
+#define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_MASK                               (1 << 0)
+/* Used by PM_L4PER_TIMER10_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER10_MPU_SHIFT                                      0
+#define OMAP54XX_WKUPDEP_TIMER10_MPU_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_TIMER10_MPU_MASK                                       (1 << 0)
+/* Used by PM_L4PER_TIMER11_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER11_IPU_SHIFT                                      1
+#define OMAP54XX_WKUPDEP_TIMER11_IPU_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_TIMER11_IPU_MASK                                       (1 << 1)
+/* Used by PM_L4PER_TIMER11_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER11_MPU_SHIFT                                      0
+#define OMAP54XX_WKUPDEP_TIMER11_MPU_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_TIMER11_MPU_MASK                                       (1 << 0)
+/* Used by PM_WKUPAON_TIMER12_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER12_MPU_SHIFT                                      0
+#define OMAP54XX_WKUPDEP_TIMER12_MPU_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_TIMER12_MPU_MASK                                       (1 << 0)
+/* Used by PM_WKUPAON_TIMER1_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER1_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_TIMER1_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER1_MPU_MASK                                        (1 << 0)
+/* Used by PM_L4PER_TIMER2_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER2_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_TIMER2_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER2_MPU_MASK                                        (1 << 0)
+/* Used by PM_L4PER_TIMER3_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER3_IPU_SHIFT                                       1
+#define OMAP54XX_WKUPDEP_TIMER3_IPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER3_IPU_MASK                                        (1 << 1)
+/* Used by PM_L4PER_TIMER3_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER3_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_TIMER3_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER3_MPU_MASK                                        (1 << 0)
+/* Used by PM_L4PER_TIMER4_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER4_IPU_SHIFT                                       1
+#define OMAP54XX_WKUPDEP_TIMER4_IPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER4_IPU_MASK                                        (1 << 1)
+/* Used by PM_L4PER_TIMER4_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER4_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_TIMER4_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER4_MPU_MASK                                        (1 << 0)
+/* Used by PM_ABE_TIMER5_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER5_DSP_SHIFT                                       2
+#define OMAP54XX_WKUPDEP_TIMER5_DSP_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER5_DSP_MASK                                        (1 << 2)
+/* Used by PM_ABE_TIMER5_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER5_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_TIMER5_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER5_MPU_MASK                                        (1 << 0)
+/* Used by PM_ABE_TIMER6_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER6_DSP_SHIFT                                       2
+#define OMAP54XX_WKUPDEP_TIMER6_DSP_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER6_DSP_MASK                                        (1 << 2)
+/* Used by PM_ABE_TIMER6_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER6_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_TIMER6_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER6_MPU_MASK                                        (1 << 0)
+/* Used by PM_ABE_TIMER7_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER7_DSP_SHIFT                                       2
+#define OMAP54XX_WKUPDEP_TIMER7_DSP_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER7_DSP_MASK                                        (1 << 2)
+/* Used by PM_ABE_TIMER7_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER7_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_TIMER7_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER7_MPU_MASK                                        (1 << 0)
+/* Used by PM_ABE_TIMER8_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER8_DSP_SHIFT                                       2
+#define OMAP54XX_WKUPDEP_TIMER8_DSP_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER8_DSP_MASK                                        (1 << 2)
+/* Used by PM_ABE_TIMER8_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER8_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_TIMER8_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER8_MPU_MASK                                        (1 << 0)
+/* Used by PM_L4PER_TIMER9_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER9_IPU_SHIFT                                       1
+#define OMAP54XX_WKUPDEP_TIMER9_IPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER9_IPU_MASK                                        (1 << 1)
+/* Used by PM_L4PER_TIMER9_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER9_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_TIMER9_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER9_MPU_MASK                                        (1 << 0)
+/* Used by PM_L4PER_UART1_WKDEP */
+#define OMAP54XX_WKUPDEP_UART1_MPU_SHIFT                                        0
+#define OMAP54XX_WKUPDEP_UART1_MPU_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_UART1_MPU_MASK                                         (1 << 0)
+/* Used by PM_L4PER_UART1_WKDEP */
+#define OMAP54XX_WKUPDEP_UART1_SDMA_SHIFT                                       3
+#define OMAP54XX_WKUPDEP_UART1_SDMA_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_UART1_SDMA_MASK                                        (1 << 3)
+/* Used by PM_L4PER_UART2_WKDEP */
+#define OMAP54XX_WKUPDEP_UART2_MPU_SHIFT                                        0
+#define OMAP54XX_WKUPDEP_UART2_MPU_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_UART2_MPU_MASK                                         (1 << 0)
+/* Used by PM_L4PER_UART2_WKDEP */
+#define OMAP54XX_WKUPDEP_UART2_SDMA_SHIFT                                       3
+#define OMAP54XX_WKUPDEP_UART2_SDMA_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_UART2_SDMA_MASK                                        (1 << 3)
+/* Used by PM_L4PER_UART3_WKDEP */
+#define OMAP54XX_WKUPDEP_UART3_DSP_SHIFT                                        2
+#define OMAP54XX_WKUPDEP_UART3_DSP_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_UART3_DSP_MASK                                         (1 << 2)
+/* Used by PM_L4PER_UART3_WKDEP */
+#define OMAP54XX_WKUPDEP_UART3_IPU_SHIFT                                        1
+#define OMAP54XX_WKUPDEP_UART3_IPU_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_UART3_IPU_MASK                                         (1 << 1)
+/* Used by PM_L4PER_UART3_WKDEP */
+#define OMAP54XX_WKUPDEP_UART3_MPU_SHIFT                                        0
+#define OMAP54XX_WKUPDEP_UART3_MPU_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_UART3_MPU_MASK                                         (1 << 0)
+/* Used by PM_L4PER_UART3_WKDEP */
+#define OMAP54XX_WKUPDEP_UART3_SDMA_SHIFT                                       3
+#define OMAP54XX_WKUPDEP_UART3_SDMA_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_UART3_SDMA_MASK                                        (1 << 3)
+/* Used by PM_L4PER_UART4_WKDEP */
+#define OMAP54XX_WKUPDEP_UART4_MPU_SHIFT                                        0
+#define OMAP54XX_WKUPDEP_UART4_MPU_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_UART4_MPU_MASK                                         (1 << 0)
+/* Used by PM_L4PER_UART4_WKDEP */
+#define OMAP54XX_WKUPDEP_UART4_SDMA_SHIFT                                       3
+#define OMAP54XX_WKUPDEP_UART4_SDMA_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_UART4_SDMA_MASK                                        (1 << 3)
+/* Used by PM_L4PER_UART5_WKDEP */
+#define OMAP54XX_WKUPDEP_UART5_MPU_SHIFT                                        0
+#define OMAP54XX_WKUPDEP_UART5_MPU_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_UART5_MPU_MASK                                         (1 << 0)
+/* Used by PM_L4PER_UART5_WKDEP */
+#define OMAP54XX_WKUPDEP_UART5_SDMA_SHIFT                                       3
+#define OMAP54XX_WKUPDEP_UART5_SDMA_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_UART5_SDMA_MASK                                        (1 << 3)
+/* Used by PM_L4PER_UART6_WKDEP */
+#define OMAP54XX_WKUPDEP_UART6_MPU_SHIFT                                        0
+#define OMAP54XX_WKUPDEP_UART6_MPU_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_UART6_MPU_MASK                                         (1 << 0)
+/* Used by PM_L4PER_UART6_WKDEP */
+#define OMAP54XX_WKUPDEP_UART6_SDMA_SHIFT                                       3
+#define OMAP54XX_WKUPDEP_UART6_SDMA_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_UART6_SDMA_MASK                                        (1 << 3)
+/* Used by PM_L3INIT_UNIPRO2_WKDEP */
+#define OMAP54XX_WKUPDEP_UNIPRO2_MPU_SHIFT                                      0
+#define OMAP54XX_WKUPDEP_UNIPRO2_MPU_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_UNIPRO2_MPU_MASK                                       (1 << 0)
+/* Used by PM_L3INIT_USB_HOST_HS_WKDEP */
+#define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_SHIFT                                  1
+#define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_WIDTH                                  0x1
+#define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_MASK                                   (1 << 1)
+/* Used by PM_L3INIT_USB_HOST_HS_WKDEP */
+#define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_SHIFT                                  0
+#define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_WIDTH                                  0x1
+#define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_MASK                                   (1 << 0)
+/* Used by PM_L3INIT_USB_OTG_SS_WKDEP */
+#define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_SHIFT                                   1
+#define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_MASK                                    (1 << 1)
+/* Used by PM_L3INIT_USB_OTG_SS_WKDEP */
+#define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_SHIFT                                   0
+#define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_MASK                                    (1 << 0)
+/* Used by PM_L3INIT_USB_TLL_HS_WKDEP */
+#define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_SHIFT                                   1
+#define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_MASK                                    (1 << 1)
+/* Used by PM_L3INIT_USB_TLL_HS_WKDEP */
+#define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_SHIFT                                   0
+#define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_MASK                                    (1 << 0)
+/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */
+#define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_SHIFT                                    0
+#define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_MASK                                     (1 << 0)
+/* Used by PM_ABE_WD_TIMER3_WKDEP */
+#define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_SHIFT                                    0
+#define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_MASK                                     (1 << 0)
+/* Used by PRM_IO_PMCTRL */
+#define OMAP54XX_WUCLK_CTRL_SHIFT                                               8
+#define OMAP54XX_WUCLK_CTRL_WIDTH                                               0x1
+#define OMAP54XX_WUCLK_CTRL_MASK                                                (1 << 8)
+/* Used by PRM_IO_PMCTRL */
+#define OMAP54XX_WUCLK_STATUS_SHIFT                                             9
+#define OMAP54XX_WUCLK_STATUS_WIDTH                                             0x1
+#define OMAP54XX_WUCLK_STATUS_MASK                                              (1 << 9)
+/* Used by REVISION_PRM */
+#define OMAP54XX_X_MAJOR_SHIFT                                                  8
+#define OMAP54XX_X_MAJOR_WIDTH                                                  0x3
+#define OMAP54XX_X_MAJOR_MASK                                                   (0x7 << 8)
+/* Used by REVISION_PRM */
+#define OMAP54XX_Y_MINOR_SHIFT                                                  0
+#define OMAP54XX_Y_MINOR_WIDTH                                                  0x6
+#define OMAP54XX_Y_MINOR_MASK                                                   (0x3f << 0)
+#endif
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
index 44c0d7216aa7..720440737744 100644
--- a/arch/arm/mach-omap2/prm33xx.c
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -320,6 +320,12 @@ static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm)
        return 0;
 }
+static int am33xx_check_vcvp(void)
+{
+        /* No VC/VP on am33xx devices */
+        return 0;
+}
 struct pwrdm_ops am33xx_pwrdm_operations = {
        .pwrdm_set_next_pwrst           = am33xx_pwrdm_set_next_pwrst,
        .pwrdm_read_next_pwrst          = am33xx_pwrdm_read_next_pwrst,
@@ -335,4 +341,5 @@ struct pwrdm_ops am33xx_pwrdm_operations = {
        .pwrdm_set_mem_onst             = am33xx_pwrdm_set_mem_onst,
        .pwrdm_set_mem_retst            = am33xx_pwrdm_set_mem_retst,
        .pwrdm_wait_transition          = am33xx_pwrdm_wait_transition,
+        .pwrdm_has_voltdm               = am33xx_check_vcvp,
 };
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 8ee1fbdec561..7db2422faa16 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -25,6 +25,7 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H
 #define __ARCH_ARM_MACH_OMAP2_PRM44XX_H
+#include "prm44xx_54xx.h"
 #include "prcm-common.h"
 #include "prm.h"
@@ -744,36 +745,4 @@
 #define OMAP4_PRM_VC_ERRST_OFFSET                       0x00f8
 #define OMAP4430_PRM_VC_ERRST                           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8)
-/* Function prototypes */
-# ifndef __ASSEMBLER__
-extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx);
-extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx);
-extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
-/* OMAP4-specific VP functions */
-u32 omap4_prm_vp_check_txdone(u8 vp_id);
-void omap4_prm_vp_clear_txdone(u8 vp_id);
-/*
- * OMAP4 access functions for voltage controller (VC) and
- * voltage proccessor (VP) in the PRM.
- */
-extern u32 omap4_prm_vcvp_read(u8 offset);
-extern void omap4_prm_vcvp_write(u32 val, u8 offset);
-extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
-extern void omap44xx_prm_reconfigure_io_chain(void);
-/* PRM interrupt-related functions */
-extern void omap44xx_prm_read_pending_irqs(unsigned long *events);
-extern void omap44xx_prm_ocp_barrier(void);
-extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
-extern void omap44xx_prm_restore_irqen(u32 *saved_mask);
-extern int __init omap44xx_prm_init(void);
-extern u32 omap44xx_prm_get_reset_sources(void);
-# endif
 #endif
diff --git a/arch/arm/mach-omap2/prm44xx_54xx.h b/arch/arm/mach-omap2/prm44xx_54xx.h
new file mode 100644
index 000000000000..7cd22abb8f15
--- /dev/null
+++ b/arch/arm/mach-omap2/prm44xx_54xx.h
@@ -0,0 +1,58 @@
+/*
+ * OMAP44xx and 54xx PRM common functions
+ *
+ * Copyright (C) 2009-2013 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H
+/* Function prototypes */
+#ifndef __ASSEMBLER__
+extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx);
+extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
+/* OMAP4/OMAP5-specific VP functions */
+u32 omap4_prm_vp_check_txdone(u8 vp_id);
+void omap4_prm_vp_clear_txdone(u8 vp_id);
+/*
+ * OMAP4/OMAP5 access functions for voltage controller (VC) and
+ * voltage proccessor (VP) in the PRM.
+ */
+extern u32 omap4_prm_vcvp_read(u8 offset);
+extern void omap4_prm_vcvp_write(u32 val, u8 offset);
+extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
+extern void omap44xx_prm_reconfigure_io_chain(void);
+/* PRM interrupt-related functions */
+extern void omap44xx_prm_read_pending_irqs(unsigned long *events);
+extern void omap44xx_prm_ocp_barrier(void);
+extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
+extern void omap44xx_prm_restore_irqen(u32 *saved_mask);
+extern int __init omap44xx_prm_init(void);
+extern u32 omap44xx_prm_get_reset_sources(void);
+#endif
+#endif
diff --git a/arch/arm/mach-omap2/prm54xx.h b/arch/arm/mach-omap2/prm54xx.h
new file mode 100644
index 000000000000..e4411010309c
--- /dev/null
+++ b/arch/arm/mach-omap2/prm54xx.h
@@ -0,0 +1,421 @@
+/*
+ * OMAP54xx PRM instance offset macros
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM54XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM54XX_H
+#include "prm44xx_54xx.h"
+#include "prcm-common.h"
+#include "prm.h"
+#define OMAP54XX_PRM_BASE               0x4ae06000
+#define OMAP54XX_PRM_REGADDR(inst, reg)                         \
+        OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE + (inst) + (reg))
+/* PRM instances */
+#define OMAP54XX_PRM_OCP_SOCKET_INST    0x0000
+#define OMAP54XX_PRM_CKGEN_INST         0x0100
+#define OMAP54XX_PRM_MPU_INST           0x0300
+#define OMAP54XX_PRM_DSP_INST           0x0400
+#define OMAP54XX_PRM_ABE_INST           0x0500
+#define OMAP54XX_PRM_COREAON_INST       0x0600
+#define OMAP54XX_PRM_CORE_INST          0x0700
+#define OMAP54XX_PRM_IVA_INST           0x1200
+#define OMAP54XX_PRM_CAM_INST           0x1300
+#define OMAP54XX_PRM_DSS_INST           0x1400
+#define OMAP54XX_PRM_GPU_INST           0x1500
+#define OMAP54XX_PRM_L3INIT_INST        0x1600
+#define OMAP54XX_PRM_CUSTEFUSE_INST     0x1700
+#define OMAP54XX_PRM_WKUPAON_INST       0x1800
+#define OMAP54XX_PRM_WKUPAON_CM_INST    0x1900
+#define OMAP54XX_PRM_EMU_INST           0x1a00
+#define OMAP54XX_PRM_EMU_CM_INST        0x1b00
+#define OMAP54XX_PRM_DEVICE_INST        0x1c00
+#define OMAP54XX_PRM_INSTR_INST         0x1f00
+/* PRM clockdomain register offsets (from instance start) */
+#define OMAP54XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS  0x0000
+#define OMAP54XX_PRM_EMU_CM_EMU_CDOFFS          0x0000
+/* PRM */
+/* PRM.OCP_SOCKET_PRM register offsets */
+#define OMAP54XX_REVISION_PRM_OFFSET                            0x0000
+#define OMAP54XX_PRM_IRQSTATUS_MPU_OFFSET                       0x0010
+#define OMAP54XX_PRM_IRQSTATUS_MPU_2_OFFSET                     0x0014
+#define OMAP54XX_PRM_IRQENABLE_MPU_OFFSET                       0x0018
+#define OMAP54XX_PRM_IRQENABLE_MPU_2_OFFSET                     0x001c
+#define OMAP54XX_PRM_IRQSTATUS_IPU_OFFSET                       0x0020
+#define OMAP54XX_PRM_IRQENABLE_IPU_OFFSET                       0x0028
+#define OMAP54XX_PRM_IRQSTATUS_DSP_OFFSET                       0x0030
+#define OMAP54XX_PRM_IRQENABLE_DSP_OFFSET                       0x0038
+#define OMAP54XX_CM_PRM_PROFILING_CLKCTRL_OFFSET                0x0040
+#define OMAP54XX_CM_PRM_PROFILING_CLKCTRL                       OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_OCP_SOCKET_INST, 0x0040)
+#define OMAP54XX_PRM_DEBUG_OUT_OFFSET                           0x0084
+#define OMAP54XX_PRM_DEBUG_TRANS_CFG_OFFSET                     0x0090
+#define OMAP54XX_PRM_DEBUG_OFF_TRANS_OFFSET                     0x0094
+#define OMAP54XX_PRM_DEBUG_CORE_RET_TRANS_OFFSET                0x0098
+#define OMAP54XX_PRM_DEBUG_MPU_RET_TRANS_OFFSET                 0x009c
+#define OMAP54XX_PRM_DEBUG_MM_RET_TRANS_OFFSET                  0x00a0
+#define OMAP54XX_PRM_DEBUG_WKUPAON_FD_TRANS_OFFSET              0x00a4
+/* PRM.CKGEN_PRM register offsets */
+#define OMAP54XX_CM_CLKSEL_ABE_DSS_SYS_OFFSET                   0x0000
+#define OMAP54XX_CM_CLKSEL_ABE_DSS_SYS                          OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0000)
+#define OMAP54XX_CM_CLKSEL_WKUPAON_OFFSET                       0x0008
+#define OMAP54XX_CM_CLKSEL_WKUPAON                              OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0008)
+#define OMAP54XX_CM_CLKSEL_ABE_PLL_REF_OFFSET                   0x000c
+#define OMAP54XX_CM_CLKSEL_ABE_PLL_REF                          OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x000c)
+#define OMAP54XX_CM_CLKSEL_SYS_OFFSET                           0x0010
+#define OMAP54XX_CM_CLKSEL_SYS                                  OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0010)
+/* PRM.MPU_PRM register offsets */
+#define OMAP54XX_PM_MPU_PWRSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_PM_MPU_PWRSTST_OFFSET                          0x0004
+#define OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET                      0x0024
+/* PRM.DSP_PRM register offsets */
+#define OMAP54XX_PM_DSP_PWRSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_PM_DSP_PWRSTST_OFFSET                          0x0004
+#define OMAP54XX_RM_DSP_RSTCTRL_OFFSET                          0x0010
+#define OMAP54XX_RM_DSP_RSTST_OFFSET                            0x0014
+#define OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET                      0x0024
+/* PRM.ABE_PRM register offsets */
+#define OMAP54XX_PM_ABE_PWRSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_PM_ABE_PWRSTST_OFFSET                          0x0004
+#define OMAP54XX_RM_ABE_AESS_CONTEXT_OFFSET                     0x002c
+#define OMAP54XX_PM_ABE_MCPDM_WKDEP_OFFSET                      0x0030
+#define OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET                    0x0034
+#define OMAP54XX_PM_ABE_DMIC_WKDEP_OFFSET                       0x0038
+#define OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET                     0x003c
+#define OMAP54XX_PM_ABE_MCASP_WKDEP_OFFSET                      0x0040
+#define OMAP54XX_RM_ABE_MCASP_CONTEXT_OFFSET                    0x0044
+#define OMAP54XX_PM_ABE_MCBSP1_WKDEP_OFFSET                     0x0048
+#define OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET                   0x004c
+#define OMAP54XX_PM_ABE_MCBSP2_WKDEP_OFFSET                     0x0050
+#define OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET                   0x0054
+#define OMAP54XX_PM_ABE_MCBSP3_WKDEP_OFFSET                     0x0058
+#define OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET                   0x005c
+#define OMAP54XX_PM_ABE_SLIMBUS1_WKDEP_OFFSET                   0x0060
+#define OMAP54XX_RM_ABE_SLIMBUS1_CONTEXT_OFFSET                 0x0064
+#define OMAP54XX_PM_ABE_TIMER5_WKDEP_OFFSET                     0x0068
+#define OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET                   0x006c
+#define OMAP54XX_PM_ABE_TIMER6_WKDEP_OFFSET                     0x0070
+#define OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET                   0x0074
+#define OMAP54XX_PM_ABE_TIMER7_WKDEP_OFFSET                     0x0078
+#define OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET                   0x007c
+#define OMAP54XX_PM_ABE_TIMER8_WKDEP_OFFSET                     0x0080
+#define OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET                   0x0084
+#define OMAP54XX_PM_ABE_WD_TIMER3_WKDEP_OFFSET                  0x0088
+#define OMAP54XX_RM_ABE_WD_TIMER3_CONTEXT_OFFSET                0x008c
+/* PRM.COREAON_PRM register offsets */
+#define OMAP54XX_PM_COREAON_SMARTREFLEX_MPU_WKDEP_OFFSET        0x0028
+#define OMAP54XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET      0x002c
+#define OMAP54XX_PM_COREAON_SMARTREFLEX_MM_WKDEP_OFFSET         0x0030
+#define OMAP54XX_RM_COREAON_SMARTREFLEX_MM_CONTEXT_OFFSET       0x0034
+#define OMAP54XX_PM_COREAON_SMARTREFLEX_CORE_WKDEP_OFFSET       0x0038
+#define OMAP54XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET     0x003c
+/* PRM.CORE_PRM register offsets */
+#define OMAP54XX_PM_CORE_PWRSTCTRL_OFFSET                       0x0000
+#define OMAP54XX_PM_CORE_PWRSTST_OFFSET                         0x0004
+#define OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET            0x0024
+#define OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET            0x0124
+#define OMAP54XX_RM_L3MAIN2_GPMC_CONTEXT_OFFSET                 0x012c
+#define OMAP54XX_RM_L3MAIN2_OCMC_RAM_CONTEXT_OFFSET             0x0134
+#define OMAP54XX_RM_IPU_RSTCTRL_OFFSET                          0x0210
+#define OMAP54XX_RM_IPU_RSTST_OFFSET                            0x0214
+#define OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET                      0x0224
+#define OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET               0x0324
+#define OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET                     0x0424
+#define OMAP54XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET             0x042c
+#define OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET                   0x0434
+#define OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET                   0x043c
+#define OMAP54XX_RM_EMIF_EMIF_DLL_CONTEXT_OFFSET                0x0444
+#define OMAP54XX_RM_C2C_C2C_CONTEXT_OFFSET                      0x0524
+#define OMAP54XX_RM_C2C_MODEM_ICR_CONTEXT_OFFSET                0x052c
+#define OMAP54XX_RM_C2C_C2C_OCP_FW_CONTEXT_OFFSET               0x0534
+#define OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET                 0x0624
+#define OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET               0x062c
+#define OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET                0x0634
+#define OMAP54XX_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET                0x063c
+#define OMAP54XX_RM_L4CFG_OCP2SCP2_CONTEXT_OFFSET               0x0644
+#define OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET            0x0724
+#define OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET             0x072c
+#define OMAP54XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET           0x0744
+#define OMAP54XX_RM_MIPIEXT_LLI_CONTEXT_OFFSET                  0x0824
+#define OMAP54XX_RM_MIPIEXT_LLI_OCP_FW_CONTEXT_OFFSET           0x082c
+#define OMAP54XX_RM_MIPIEXT_MPHY_CONTEXT_OFFSET                 0x0834
+#define OMAP54XX_PM_L4PER_TIMER10_WKDEP_OFFSET                  0x0928
+#define OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET                0x092c
+#define OMAP54XX_PM_L4PER_TIMER11_WKDEP_OFFSET                  0x0930
+#define OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET                0x0934
+#define OMAP54XX_PM_L4PER_TIMER2_WKDEP_OFFSET                   0x0938
+#define OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET                 0x093c
+#define OMAP54XX_PM_L4PER_TIMER3_WKDEP_OFFSET                   0x0940
+#define OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET                 0x0944
+#define OMAP54XX_PM_L4PER_TIMER4_WKDEP_OFFSET                   0x0948
+#define OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET                 0x094c
+#define OMAP54XX_PM_L4PER_TIMER9_WKDEP_OFFSET                   0x0950
+#define OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET                 0x0954
+#define OMAP54XX_RM_L4PER_ELM_CONTEXT_OFFSET                    0x095c
+#define OMAP54XX_PM_L4PER_GPIO2_WKDEP_OFFSET                    0x0960
+#define OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET                  0x0964
+#define OMAP54XX_PM_L4PER_GPIO3_WKDEP_OFFSET                    0x0968
+#define OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET                  0x096c
+#define OMAP54XX_PM_L4PER_GPIO4_WKDEP_OFFSET                    0x0970
+#define OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET                  0x0974
+#define OMAP54XX_PM_L4PER_GPIO5_WKDEP_OFFSET                    0x0978
+#define OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET                  0x097c
+#define OMAP54XX_PM_L4PER_GPIO6_WKDEP_OFFSET                    0x0980
+#define OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET                  0x0984
+#define OMAP54XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET                  0x098c
+#define OMAP54XX_PM_L4PER_I2C1_WKDEP_OFFSET                     0x09a0
+#define OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET                   0x09a4
+#define OMAP54XX_PM_L4PER_I2C2_WKDEP_OFFSET                     0x09a8
+#define OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET                   0x09ac
+#define OMAP54XX_PM_L4PER_I2C3_WKDEP_OFFSET                     0x09b0
+#define OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET                   0x09b4
+#define OMAP54XX_PM_L4PER_I2C4_WKDEP_OFFSET                     0x09b8
+#define OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET                   0x09bc
+#define OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET                 0x09c0
+#define OMAP54XX_PM_L4PER_MCSPI1_WKDEP_OFFSET                   0x09f0
+#define OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET                 0x09f4
+#define OMAP54XX_PM_L4PER_MCSPI2_WKDEP_OFFSET                   0x09f8
+#define OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET                 0x09fc
+#define OMAP54XX_PM_L4PER_MCSPI3_WKDEP_OFFSET                   0x0a00
+#define OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET                 0x0a04
+#define OMAP54XX_PM_L4PER_MCSPI4_WKDEP_OFFSET                   0x0a08
+#define OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET                 0x0a0c
+#define OMAP54XX_PM_L4PER_GPIO7_WKDEP_OFFSET                    0x0a10
+#define OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET                  0x0a14
+#define OMAP54XX_PM_L4PER_GPIO8_WKDEP_OFFSET                    0x0a18
+#define OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET                  0x0a1c
+#define OMAP54XX_PM_L4PER_MMC3_WKDEP_OFFSET                     0x0a20
+#define OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET                   0x0a24
+#define OMAP54XX_PM_L4PER_MMC4_WKDEP_OFFSET                     0x0a28
+#define OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET                   0x0a2c
+#define OMAP54XX_PM_L4PER_UART1_WKDEP_OFFSET                    0x0a40
+#define OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET                  0x0a44
+#define OMAP54XX_PM_L4PER_UART2_WKDEP_OFFSET                    0x0a48
+#define OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET                  0x0a4c
+#define OMAP54XX_PM_L4PER_UART3_WKDEP_OFFSET                    0x0a50
+#define OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET                  0x0a54
+#define OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET                  0x0a58
+#define OMAP54XX_PM_L4PER_UART4_WKDEP_OFFSET                    0x0a5c
+#define OMAP54XX_PM_L4PER_MMC5_WKDEP_OFFSET                     0x0a60
+#define OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET                   0x0a64
+#define OMAP54XX_PM_L4PER_I2C5_WKDEP_OFFSET                     0x0a68
+#define OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET                   0x0a6c
+#define OMAP54XX_PM_L4PER_UART5_WKDEP_OFFSET                    0x0a70
+#define OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET                  0x0a74
+#define OMAP54XX_PM_L4PER_UART6_WKDEP_OFFSET                    0x0a78
+#define OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET                  0x0a7c
+#define OMAP54XX_RM_L4SEC_AES1_CONTEXT_OFFSET                   0x0aa4
+#define OMAP54XX_RM_L4SEC_AES2_CONTEXT_OFFSET                   0x0aac
+#define OMAP54XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET                0x0ab4
+#define OMAP54XX_RM_L4SEC_FPKA_CONTEXT_OFFSET                   0x0abc
+#define OMAP54XX_RM_L4SEC_RNG_CONTEXT_OFFSET                    0x0ac4
+#define OMAP54XX_RM_L4SEC_SHA2MD5_CONTEXT_OFFSET                0x0acc
+#define OMAP54XX_RM_L4SEC_DMA_CRYPTO_CONTEXT_OFFSET             0x0adc
+/* PRM.IVA_PRM register offsets */
+#define OMAP54XX_PM_IVA_PWRSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_PM_IVA_PWRSTST_OFFSET                          0x0004
+#define OMAP54XX_RM_IVA_RSTCTRL_OFFSET                          0x0010
+#define OMAP54XX_RM_IVA_RSTST_OFFSET                            0x0014
+#define OMAP54XX_RM_IVA_IVA_CONTEXT_OFFSET                      0x0024
+#define OMAP54XX_RM_IVA_SL2_CONTEXT_OFFSET                      0x002c
+/* PRM.CAM_PRM register offsets */
+#define OMAP54XX_PM_CAM_PWRSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_PM_CAM_PWRSTST_OFFSET                          0x0004
+#define OMAP54XX_RM_CAM_ISS_CONTEXT_OFFSET                      0x0024
+#define OMAP54XX_RM_CAM_FDIF_CONTEXT_OFFSET                     0x002c
+#define OMAP54XX_RM_CAM_CAL_CONTEXT_OFFSET                      0x0034
+/* PRM.DSS_PRM register offsets */
+#define OMAP54XX_PM_DSS_PWRSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_PM_DSS_PWRSTST_OFFSET                          0x0004
+#define OMAP54XX_PM_DSS_DSS_WKDEP_OFFSET                        0x0020
+#define OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET                      0x0024
+#define OMAP54XX_RM_DSS_BB2D_CONTEXT_OFFSET                     0x0034
+/* PRM.GPU_PRM register offsets */
+#define OMAP54XX_PM_GPU_PWRSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_PM_GPU_PWRSTST_OFFSET                          0x0004
+#define OMAP54XX_RM_GPU_GPU_CONTEXT_OFFSET                      0x0024
+/* PRM.L3INIT_PRM register offsets */
+#define OMAP54XX_PM_L3INIT_PWRSTCTRL_OFFSET                     0x0000
+#define OMAP54XX_PM_L3INIT_PWRSTST_OFFSET                       0x0004
+#define OMAP54XX_PM_L3INIT_MMC1_WKDEP_OFFSET                    0x0028
+#define OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET                  0x002c
+#define OMAP54XX_PM_L3INIT_MMC2_WKDEP_OFFSET                    0x0030
+#define OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET                  0x0034
+#define OMAP54XX_PM_L3INIT_HSI_WKDEP_OFFSET                     0x0038
+#define OMAP54XX_RM_L3INIT_HSI_CONTEXT_OFFSET                   0x003c
+#define OMAP54XX_PM_L3INIT_UNIPRO2_WKDEP_OFFSET                 0x0040
+#define OMAP54XX_RM_L3INIT_UNIPRO2_CONTEXT_OFFSET               0x0044
+#define OMAP54XX_PM_L3INIT_USB_HOST_HS_WKDEP_OFFSET             0x0058
+#define OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET           0x005c
+#define OMAP54XX_PM_L3INIT_USB_TLL_HS_WKDEP_OFFSET              0x0068
+#define OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET            0x006c
+#define OMAP54XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET        0x007c
+#define OMAP54XX_PM_L3INIT_SATA_WKDEP_OFFSET                    0x0088
+#define OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET                  0x008c
+#define OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET              0x00e4
+#define OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET              0x00ec
+#define OMAP54XX_PM_L3INIT_USB_OTG_SS_WKDEP_OFFSET              0x00f0
+#define OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET            0x00f4
+/* PRM.CUSTEFUSE_PRM register offsets */
+#define OMAP54XX_PM_CUSTEFUSE_PWRSTCTRL_OFFSET                  0x0000
+#define OMAP54XX_PM_CUSTEFUSE_PWRSTST_OFFSET                    0x0004
+#define OMAP54XX_RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT_OFFSET    0x0024
+/* PRM.WKUPAON_PRM register offsets */
+#define OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET              0x0024
+#define OMAP54XX_RM_WKUPAON_WD_TIMER1_CONTEXT_OFFSET            0x002c
+#define OMAP54XX_PM_WKUPAON_WD_TIMER2_WKDEP_OFFSET              0x0030
+#define OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET            0x0034
+#define OMAP54XX_PM_WKUPAON_GPIO1_WKDEP_OFFSET                  0x0038
+#define OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET                0x003c
+#define OMAP54XX_PM_WKUPAON_TIMER1_WKDEP_OFFSET                 0x0040
+#define OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET               0x0044
+#define OMAP54XX_PM_WKUPAON_TIMER12_WKDEP_OFFSET                0x0048
+#define OMAP54XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET              0x004c
+#define OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET          0x0054
+#define OMAP54XX_RM_WKUPAON_SAR_RAM_CONTEXT_OFFSET              0x0064
+#define OMAP54XX_PM_WKUPAON_KBD_WKDEP_OFFSET                    0x0078
+#define OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET                  0x007c
+/* PRM.WKUPAON_CM register offsets */
+#define OMAP54XX_CM_WKUPAON_CLKSTCTRL_OFFSET                    0x0000
+#define OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET              0x0020
+#define OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL                     OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0020)
+#define OMAP54XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET            0x0028
+#define OMAP54XX_CM_WKUPAON_WD_TIMER1_CLKCTRL                   OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0028)
+#define OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET            0x0030
+#define OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL                   OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0030)
+#define OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET                0x0038
+#define OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL                       OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0038)
+#define OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET               0x0040
+#define OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL                      OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0040)
+#define OMAP54XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET              0x0048
+#define OMAP54XX_CM_WKUPAON_TIMER12_CLKCTRL                     OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0048)
+#define OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET          0x0050
+#define OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL                 OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0050)
+#define OMAP54XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET              0x0060
+#define OMAP54XX_CM_WKUPAON_SAR_RAM_CLKCTRL                     OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0060)
+#define OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET                  0x0078
+#define OMAP54XX_CM_WKUPAON_KBD_CLKCTRL                         OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0078)
+#define OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET                 0x0090
+#define OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL                        OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0090)
+#define OMAP54XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET            0x0098
+#define OMAP54XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL                   OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0098)
+/* PRM.EMU_PRM register offsets */
+#define OMAP54XX_PM_EMU_PWRSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_PM_EMU_PWRSTST_OFFSET                          0x0004
+#define OMAP54XX_RM_EMU_DEBUGSS_CONTEXT_OFFSET                  0x0024
+/* PRM.EMU_CM register offsets */
+#define OMAP54XX_CM_EMU_CLKSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_CM_EMU_DYNAMICDEP_OFFSET                       0x0008
+#define OMAP54XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET                  0x0020
+#define OMAP54XX_CM_EMU_DEBUGSS_CLKCTRL                         OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_EMU_CM_INST, 0x0020)
+#define OMAP54XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET              0x0028
+#define OMAP54XX_CM_EMU_MPU_EMU_DBG_CLKCTRL                     OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_EMU_CM_INST, 0x0028)
+/* PRM.DEVICE_PRM register offsets */
+#define OMAP54XX_PRM_RSTCTRL_OFFSET                             0x0000
+#define OMAP54XX_PRM_RSTST_OFFSET                               0x0004
+#define OMAP54XX_PRM_RSTTIME_OFFSET                             0x0008
+#define OMAP54XX_PRM_CLKREQCTRL_OFFSET                          0x000c
+#define OMAP54XX_PRM_VOLTCTRL_OFFSET                            0x0010
+#define OMAP54XX_PRM_PWRREQCTRL_OFFSET                          0x0014
+#define OMAP54XX_PRM_PSCON_COUNT_OFFSET                         0x0018
+#define OMAP54XX_PRM_IO_COUNT_OFFSET                            0x001c
+#define OMAP54XX_PRM_IO_PMCTRL_OFFSET                           0x0020
+#define OMAP54XX_PRM_VOLTSETUP_WARMRESET_OFFSET                 0x0024
+#define OMAP54XX_PRM_VOLTSETUP_CORE_OFF_OFFSET                  0x0028
+#define OMAP54XX_PRM_VOLTSETUP_MPU_OFF_OFFSET                   0x002c
+#define OMAP54XX_PRM_VOLTSETUP_MM_OFF_OFFSET                    0x0030
+#define OMAP54XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET            0x0034
+#define OMAP54XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET             0x0038
+#define OMAP54XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET              0x003c
+#define OMAP54XX_PRM_VP_CORE_CONFIG_OFFSET                      0x0040
+#define OMAP54XX_PRM_VP_CORE_STATUS_OFFSET                      0x0044
+#define OMAP54XX_PRM_VP_CORE_VLIMITTO_OFFSET                    0x0048
+#define OMAP54XX_PRM_VP_CORE_VOLTAGE_OFFSET                     0x004c
+#define OMAP54XX_PRM_VP_CORE_VSTEPMAX_OFFSET                    0x0050
+#define OMAP54XX_PRM_VP_CORE_VSTEPMIN_OFFSET                    0x0054
+#define OMAP54XX_PRM_VP_MPU_CONFIG_OFFSET                       0x0058
+#define OMAP54XX_PRM_VP_MPU_STATUS_OFFSET                       0x005c
+#define OMAP54XX_PRM_VP_MPU_VLIMITTO_OFFSET                     0x0060
+#define OMAP54XX_PRM_VP_MPU_VOLTAGE_OFFSET                      0x0064
+#define OMAP54XX_PRM_VP_MPU_VSTEPMAX_OFFSET                     0x0068
+#define OMAP54XX_PRM_VP_MPU_VSTEPMIN_OFFSET                     0x006c
+#define OMAP54XX_PRM_VP_MM_CONFIG_OFFSET                        0x0070
+#define OMAP54XX_PRM_VP_MM_STATUS_OFFSET                        0x0074
+#define OMAP54XX_PRM_VP_MM_VLIMITTO_OFFSET                      0x0078
+#define OMAP54XX_PRM_VP_MM_VOLTAGE_OFFSET                       0x007c
+#define OMAP54XX_PRM_VP_MM_VSTEPMAX_OFFSET                      0x0080
+#define OMAP54XX_PRM_VP_MM_VSTEPMIN_OFFSET                      0x0084
+#define OMAP54XX_PRM_VC_SMPS_CORE_CONFIG_OFFSET                 0x0088
+#define OMAP54XX_PRM_VC_SMPS_MM_CONFIG_OFFSET                   0x008c
+#define OMAP54XX_PRM_VC_SMPS_MPU_CONFIG_OFFSET                  0x0090
+#define OMAP54XX_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET               0x0094
+#define OMAP54XX_PRM_VC_VAL_CMD_VDD_MM_L_OFFSET                 0x0098
+#define OMAP54XX_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET                0x009c
+#define OMAP54XX_PRM_VC_VAL_BYPASS_OFFSET                       0x00a0
+#define OMAP54XX_PRM_VC_CORE_ERRST_OFFSET                       0x00a4
+#define OMAP54XX_PRM_VC_MM_ERRST_OFFSET                         0x00a8
+#define OMAP54XX_PRM_VC_MPU_ERRST_OFFSET                        0x00ac
+#define OMAP54XX_PRM_VC_BYPASS_ERRST_OFFSET                     0x00b0
+#define OMAP54XX_PRM_VC_CFG_I2C_MODE_OFFSET                     0x00b4
+#define OMAP54XX_PRM_VC_CFG_I2C_CLK_OFFSET                      0x00b8
+#define OMAP54XX_PRM_SRAM_COUNT_OFFSET                          0x00bc
+#define OMAP54XX_PRM_SRAM_WKUP_SETUP_OFFSET                     0x00c0
+#define OMAP54XX_PRM_SLDO_CORE_SETUP_OFFSET                     0x00c4
+#define OMAP54XX_PRM_SLDO_CORE_CTRL_OFFSET                      0x00c8
+#define OMAP54XX_PRM_SLDO_MPU_SETUP_OFFSET                      0x00cc
+#define OMAP54XX_PRM_SLDO_MPU_CTRL_OFFSET                       0x00d0
+#define OMAP54XX_PRM_SLDO_MM_SETUP_OFFSET                       0x00d4
+#define OMAP54XX_PRM_SLDO_MM_CTRL_OFFSET                        0x00d8
+#define OMAP54XX_PRM_ABBLDO_MPU_SETUP_OFFSET                    0x00dc
+#define OMAP54XX_PRM_ABBLDO_MPU_CTRL_OFFSET                     0x00e0
+#define OMAP54XX_PRM_ABBLDO_MM_SETUP_OFFSET                     0x00e4
+#define OMAP54XX_PRM_ABBLDO_MM_CTRL_OFFSET                      0x00e8
+#define OMAP54XX_PRM_BANDGAP_SETUP_OFFSET                       0x00ec
+#define OMAP54XX_PRM_DEVICE_OFF_CTRL_OFFSET                     0x00f0
+#define OMAP54XX_PRM_PHASE1_CNDP_OFFSET                         0x00f4
+#define OMAP54XX_PRM_PHASE2A_CNDP_OFFSET                        0x00f8
+#define OMAP54XX_PRM_PHASE2B_CNDP_OFFSET                        0x00fc
+#define OMAP54XX_PRM_MODEM_IF_CTRL_OFFSET                       0x0100
+#define OMAP54XX_PRM_VOLTST_MPU_OFFSET                          0x0110
+#define OMAP54XX_PRM_VOLTST_MM_OFFSET                           0x0114
+#endif
diff --git a/arch/arm/mach-omap2/scrm54xx.h b/arch/arm/mach-omap2/scrm54xx.h
new file mode 100644
index 000000000000..57e86c8f8239
--- /dev/null
+++ b/arch/arm/mach-omap2/scrm54xx.h
@@ -0,0 +1,231 @@
+/*
+ * OMAP54XX SCRM registers and bitfields
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H
+#define __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H
+#define OMAP5_SCRM_BASE         0x4ae0a000
+#define OMAP54XX_SCRM_REGADDR(reg)                              \
+        OMAP2_L4_IO_ADDRESS(OMAP5_SCRM_BASE + (reg))
+/* SCRM */
+/* SCRM.SCRM register offsets */
+#define OMAP5_SCRM_REVISION_SCRM_OFFSET         0x0000
+#define OMAP5_SCRM_REVISION_SCRM                OMAP54XX_SCRM_REGADDR(0x0000)
+#define OMAP5_SCRM_CLKSETUPTIME_OFFSET          0x0100
+#define OMAP5_SCRM_CLKSETUPTIME                 OMAP54XX_SCRM_REGADDR(0x0100)
+#define OMAP5_SCRM_PMICSETUPTIME_OFFSET         0x0104
+#define OMAP5_SCRM_PMICSETUPTIME                OMAP54XX_SCRM_REGADDR(0x0104)
+#define OMAP5_SCRM_ALTCLKSRC_OFFSET             0x0110
+#define OMAP5_SCRM_ALTCLKSRC                    OMAP54XX_SCRM_REGADDR(0x0110)
+#define OMAP5_SCRM_MODEMCLKM_OFFSET             0x0118
+#define OMAP5_SCRM_MODEMCLKM                    OMAP54XX_SCRM_REGADDR(0x0118)
+#define OMAP5_SCRM_D2DCLKM_OFFSET               0x011c
+#define OMAP5_SCRM_D2DCLKM                      OMAP54XX_SCRM_REGADDR(0x011c)
+#define OMAP5_SCRM_EXTCLKREQ_OFFSET             0x0200
+#define OMAP5_SCRM_EXTCLKREQ                    OMAP54XX_SCRM_REGADDR(0x0200)
+#define OMAP5_SCRM_ACCCLKREQ_OFFSET             0x0204
+#define OMAP5_SCRM_ACCCLKREQ                    OMAP54XX_SCRM_REGADDR(0x0204)
+#define OMAP5_SCRM_PWRREQ_OFFSET                0x0208
+#define OMAP5_SCRM_PWRREQ                       OMAP54XX_SCRM_REGADDR(0x0208)
+#define OMAP5_SCRM_AUXCLKREQ0_OFFSET            0x0210
+#define OMAP5_SCRM_AUXCLKREQ0                   OMAP54XX_SCRM_REGADDR(0x0210)
+#define OMAP5_SCRM_AUXCLKREQ1_OFFSET            0x0214
+#define OMAP5_SCRM_AUXCLKREQ1                   OMAP54XX_SCRM_REGADDR(0x0214)
+#define OMAP5_SCRM_AUXCLKREQ2_OFFSET            0x0218
+#define OMAP5_SCRM_AUXCLKREQ2                   OMAP54XX_SCRM_REGADDR(0x0218)
+#define OMAP5_SCRM_AUXCLKREQ3_OFFSET            0x021c
+#define OMAP5_SCRM_AUXCLKREQ3                   OMAP54XX_SCRM_REGADDR(0x021c)
+#define OMAP5_SCRM_AUXCLKREQ4_OFFSET            0x0220
+#define OMAP5_SCRM_AUXCLKREQ4                   OMAP54XX_SCRM_REGADDR(0x0220)
+#define OMAP5_SCRM_AUXCLKREQ5_OFFSET            0x0224
+#define OMAP5_SCRM_AUXCLKREQ5                   OMAP54XX_SCRM_REGADDR(0x0224)
+#define OMAP5_SCRM_D2DCLKREQ_OFFSET             0x0234
+#define OMAP5_SCRM_D2DCLKREQ                    OMAP54XX_SCRM_REGADDR(0x0234)
+#define OMAP5_SCRM_AUXCLK0_OFFSET               0x0310
+#define OMAP5_SCRM_AUXCLK0                      OMAP54XX_SCRM_REGADDR(0x0310)
+#define OMAP5_SCRM_AUXCLK1_OFFSET               0x0314
+#define OMAP5_SCRM_AUXCLK1                      OMAP54XX_SCRM_REGADDR(0x0314)
+#define OMAP5_SCRM_AUXCLK2_OFFSET               0x0318
+#define OMAP5_SCRM_AUXCLK2                      OMAP54XX_SCRM_REGADDR(0x0318)
+#define OMAP5_SCRM_AUXCLK3_OFFSET               0x031c
+#define OMAP5_SCRM_AUXCLK3                      OMAP54XX_SCRM_REGADDR(0x031c)
+#define OMAP5_SCRM_AUXCLK4_OFFSET               0x0320
+#define OMAP5_SCRM_AUXCLK4                      OMAP54XX_SCRM_REGADDR(0x0320)
+#define OMAP5_SCRM_AUXCLK5_OFFSET               0x0324
+#define OMAP5_SCRM_AUXCLK5                      OMAP54XX_SCRM_REGADDR(0x0324)
+#define OMAP5_SCRM_RSTTIME_OFFSET               0x0400
+#define OMAP5_SCRM_RSTTIME                      OMAP54XX_SCRM_REGADDR(0x0400)
+#define OMAP5_SCRM_MODEMRSTCTRL_OFFSET          0x0418
+#define OMAP5_SCRM_MODEMRSTCTRL                 OMAP54XX_SCRM_REGADDR(0x0418)
+#define OMAP5_SCRM_D2DRSTCTRL_OFFSET            0x041c
+#define OMAP5_SCRM_D2DRSTCTRL                   OMAP54XX_SCRM_REGADDR(0x041c)
+#define OMAP5_SCRM_EXTPWRONRSTCTRL_OFFSET       0x0420
+#define OMAP5_SCRM_EXTPWRONRSTCTRL              OMAP54XX_SCRM_REGADDR(0x0420)
+#define OMAP5_SCRM_EXTWARMRSTST_OFFSET          0x0510
+#define OMAP5_SCRM_EXTWARMRSTST                 OMAP54XX_SCRM_REGADDR(0x0510)
+#define OMAP5_SCRM_APEWARMRSTST_OFFSET          0x0514
+#define OMAP5_SCRM_APEWARMRSTST                 OMAP54XX_SCRM_REGADDR(0x0514)
+#define OMAP5_SCRM_MODEMWARMRSTST_OFFSET        0x0518
+#define OMAP5_SCRM_MODEMWARMRSTST               OMAP54XX_SCRM_REGADDR(0x0518)
+#define OMAP5_SCRM_D2DWARMRSTST_OFFSET          0x051c
+#define OMAP5_SCRM_D2DWARMRSTST                 OMAP54XX_SCRM_REGADDR(0x051c)
+/*
+ * Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4,
+ * AUXCLKREQ5, D2DCLKREQ
+ */
+#define OMAP5_ACCURACY_SHIFT                    1
+#define OMAP5_ACCURACY_WIDTH                    0x1
+#define OMAP5_ACCURACY_MASK                     (1 << 1)
+/* Used by APEWARMRSTST */
+#define OMAP5_APEWARMRSTST_SHIFT                1
+#define OMAP5_APEWARMRSTST_WIDTH                0x1
+#define OMAP5_APEWARMRSTST_MASK                 (1 << 1)
+/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
+#define OMAP5_CLKDIV_SHIFT                      16
+#define OMAP5_CLKDIV_WIDTH                      0x4
+#define OMAP5_CLKDIV_MASK                       (0xf << 16)
+/* Used by D2DCLKM, MODEMCLKM */
+#define OMAP5_CLK_32KHZ_SHIFT                   0
+#define OMAP5_CLK_32KHZ_WIDTH                   0x1
+#define OMAP5_CLK_32KHZ_MASK                    (1 << 0)
+/* Used by D2DRSTCTRL, MODEMRSTCTRL */
+#define OMAP5_COLDRST_SHIFT                     0
+#define OMAP5_COLDRST_WIDTH                     0x1
+#define OMAP5_COLDRST_MASK                      (1 << 0)
+/* Used by D2DWARMRSTST */
+#define OMAP5_D2DWARMRSTST_SHIFT                3
+#define OMAP5_D2DWARMRSTST_WIDTH                0x1
+#define OMAP5_D2DWARMRSTST_MASK                 (1 << 3)
+/* Used by AUXCLK0 */
+#define OMAP5_DISABLECLK_SHIFT                  9
+#define OMAP5_DISABLECLK_WIDTH                  0x1
+#define OMAP5_DISABLECLK_MASK                   (1 << 9)
+/* Used by CLKSETUPTIME */
+#define OMAP5_DOWNTIME_SHIFT                    16
+#define OMAP5_DOWNTIME_WIDTH                    0x6
+#define OMAP5_DOWNTIME_MASK                     (0x3f << 16)
+/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
+#define OMAP5_ENABLE_SHIFT                      8
+#define OMAP5_ENABLE_WIDTH                      0x1
+#define OMAP5_ENABLE_MASK                       (1 << 8)
+/* Renamed from ENABLE Used by EXTPWRONRSTCTRL */
+#define OMAP5_ENABLE_0_0_SHIFT                  0
+#define OMAP5_ENABLE_0_0_WIDTH                  0x1
+#define OMAP5_ENABLE_0_0_MASK                   (1 << 0)
+/* Used by ALTCLKSRC */
+#define OMAP5_ENABLE_EXT_SHIFT                  3
+#define OMAP5_ENABLE_EXT_WIDTH                  0x1
+#define OMAP5_ENABLE_EXT_MASK                   (1 << 3)
+/* Used by ALTCLKSRC */
+#define OMAP5_ENABLE_INT_SHIFT                  2
+#define OMAP5_ENABLE_INT_WIDTH                  0x1
+#define OMAP5_ENABLE_INT_MASK                   (1 << 2)
+/* Used by EXTWARMRSTST */
+#define OMAP5_EXTWARMRSTST_SHIFT                0
+#define OMAP5_EXTWARMRSTST_WIDTH                0x1
+#define OMAP5_EXTWARMRSTST_MASK                 (1 << 0)
+/*
+ * Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4,
+ * AUXCLKREQ5
+ */
+#define OMAP5_MAPPING_SHIFT                     2
+#define OMAP5_MAPPING_WIDTH                     0x3
+#define OMAP5_MAPPING_MASK                      (0x7 << 2)
+/* Used by ALTCLKSRC */
+#define OMAP5_MODE_SHIFT                        0
+#define OMAP5_MODE_WIDTH                        0x2
+#define OMAP5_MODE_MASK                         (0x3 << 0)
+/* Used by MODEMWARMRSTST */
+#define OMAP5_MODEMWARMRSTST_SHIFT              2
+#define OMAP5_MODEMWARMRSTST_WIDTH              0x1
+#define OMAP5_MODEMWARMRSTST_MASK               (1 << 2)
+/*
+ * Used by ACCCLKREQ, AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5,
+ * AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4, AUXCLKREQ5,
+ * D2DCLKREQ, EXTCLKREQ, PWRREQ
+ */
+#define OMAP5_POLARITY_SHIFT                    0
+#define OMAP5_POLARITY_WIDTH                    0x1
+#define OMAP5_POLARITY_MASK                     (1 << 0)
+/* Used by EXTPWRONRSTCTRL */
+#define OMAP5_PWRONRST_SHIFT                    1
+#define OMAP5_PWRONRST_WIDTH                    0x1
+#define OMAP5_PWRONRST_MASK                     (1 << 1)
+/* Used by REVISION_SCRM */
+#define OMAP5_REV_SHIFT                         0
+#define OMAP5_REV_WIDTH                         0x8
+#define OMAP5_REV_MASK                          (0xff << 0)
+/* Used by RSTTIME */
+#define OMAP5_RSTTIME_SHIFT                     0
+#define OMAP5_RSTTIME_WIDTH                     0x4
+#define OMAP5_RSTTIME_MASK                      (0xf << 0)
+/* Used by CLKSETUPTIME */
+#define OMAP5_SETUPTIME_SHIFT                   0
+#define OMAP5_SETUPTIME_WIDTH                   0xc
+#define OMAP5_SETUPTIME_MASK                    (0xfff << 0)
+/* Used by PMICSETUPTIME */
+#define OMAP5_SLEEPTIME_SHIFT                   0
+#define OMAP5_SLEEPTIME_WIDTH                   0x6
+#define OMAP5_SLEEPTIME_MASK                    (0x3f << 0)
+/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
+#define OMAP5_SRCSELECT_SHIFT                   1
+#define OMAP5_SRCSELECT_WIDTH                   0x2
+#define OMAP5_SRCSELECT_MASK                    (0x3 << 1)
+/* Used by D2DCLKM */
+#define OMAP5_SYSCLK_SHIFT                      1
+#define OMAP5_SYSCLK_WIDTH                      0x1
+#define OMAP5_SYSCLK_MASK                       (1 << 1)
+/* Used by PMICSETUPTIME */
+#define OMAP5_WAKEUPTIME_SHIFT                  16
+#define OMAP5_WAKEUPTIME_WIDTH                  0x6
+#define OMAP5_WAKEUPTIME_MASK                   (0x3f << 16)
+/* Used by D2DRSTCTRL, MODEMRSTCTRL */
+#define OMAP5_WARMRST_SHIFT                     1
+#define OMAP5_WARMRST_WIDTH                     0x1
+#define OMAP5_WARMRST_MASK                      (1 << 1)
+#endif
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index f6601563aa69..a388f8c1bcb3 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -63,7 +63,6 @@ struct omap_uart_state {
 static LIST_HEAD(uart_list);
 static u8 num_uarts;
 static u8 console_uart_id = -1;
-static u8 no_console_suspend;
 static u8 uart_debug;
 #define DEFAULT_RXDMA_POLLRATE          1       /* RX DMA polling rate (us) */
@@ -176,6 +175,9 @@ static char *cmdline_find_option(char *str)
 static int __init omap_serial_early_init(void)
 {
+        if (of_have_populated_dt())
+                return -ENODEV;
        do {
                char oh_name[MAX_UART_HWMOD_NAME_LEN];
                struct omap_hwmod *oh;
@@ -206,20 +208,6 @@ static int __init omap_serial_early_init(void)
                                pr_info("%s used as console in debug mode: uart%d clocks will not be gated",
                                        uart_name, uart->num);
                        }
-                        if (cmdline_find_option("no_console_suspend"))
-                                no_console_suspend = true;
-                        /*
-                         * omap-uart can be used for earlyprintk logs
-                         * So if omap-uart is used as console then prevent
-                         * uart reset and idle to get logs from omap-uart
-                         * until uart console driver is available to take
-                         * care for console messages.
-                         * Idling or resetting omap-uart while printing logs
-                         * early boot logs can stall the boot-up.
-                         */
-                        oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET;
                }
        } while (1);
@@ -292,9 +280,6 @@ void __init omap_serial_init_port(struct omap_board_data *bdata,
                return;
        }
-        if ((console_uart_id == bdata->id) && no_console_suspend)
-                omap_device_disable_idle_on_suspend(pdev);
        oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
        if (console_uart_id == bdata->id) {
diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S
index 88ff83a0942e..9086ce03ae12 100644
--- a/arch/arm/mach-omap2/sleep44xx.S
+++ b/arch/arm/mach-omap2/sleep44xx.S
@@ -34,6 +34,8 @@ ppa_zero_params:
 ppa_por_params:
        .word           1, 0
+#ifdef CONFIG_ARCH_OMAP4
 /*
 * =============================
 * == CPU suspend finisher ==
@@ -326,7 +328,9 @@ skip_l2en:
        b       cpu_resume                      @ Jump to generic resume
 ENDPROC(omap4_cpu_resume)
-#endif
+#endif  /* CONFIG_ARCH_OMAP4 */
+#endif  /* defined(CONFIG_SMP) && defined(CONFIG_PM) */
 #ifndef CONFIG_OMAP4_ERRATA_I688
 ENTRY(omap_bus_sync)
diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c
index aee3c8940a30..7a42e1960c3b 100644
--- a/arch/arm/mach-omap2/smartreflex-class3.c
+++ b/arch/arm/mach-omap2/smartreflex-class3.c
@@ -26,14 +26,14 @@ static int sr_class3_enable(struct omap_sr *sr)
        }
        omap_vp_enable(sr->voltdm);
-        return sr_enable(sr->voltdm, volt);
+        return sr_enable(sr, volt);
 }
 static int sr_class3_disable(struct omap_sr *sr, int is_volt_reset)
 {
-        sr_disable_errgen(sr->voltdm);
+        sr_disable_errgen(sr);
        omap_vp_disable(sr->voltdm);
-        sr_disable(sr->voltdm);
+        sr_disable(sr);
        if (is_volt_reset)
                voltdm_reset(sr->voltdm);
@@ -42,7 +42,7 @@ static int sr_class3_disable(struct omap_sr *sr, int is_volt_reset)
 static int sr_class3_configure(struct omap_sr *sr)
 {
-        return sr_configure_errgen(sr->voltdm);
+        return sr_configure_errgen(sr);
 }
 /* SR class3 structure */
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index 197cc16870d9..8c616e436bc7 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -96,6 +96,15 @@
 # endif
 #endif
+#ifdef CONFIG_SOC_AM43XX
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP2
+#  define MULTI_OMAP2
+# else
+#  define OMAP_NAME am43xx
+# endif
+#endif
 /*
 * Omap device type i.e. EMU/HS/TST/GP/BAD
 */
@@ -187,6 +196,7 @@ IS_OMAP_CLASS(44xx, 0x44)
 IS_AM_CLASS(35xx, 0x35)
 IS_OMAP_CLASS(54xx, 0x54)
 IS_AM_CLASS(33xx, 0x33)
+IS_AM_CLASS(43xx, 0x43)
 IS_TI_CLASS(81xx, 0x81)
@@ -202,6 +212,7 @@ IS_OMAP_SUBCLASS(543x, 0x543)
 IS_TI_SUBCLASS(816x, 0x816)
 IS_TI_SUBCLASS(814x, 0x814)
 IS_AM_SUBCLASS(335x, 0x335)
+IS_AM_SUBCLASS(437x, 0x437)
 #define cpu_is_omap24xx()               0
 #define cpu_is_omap242x()               0
@@ -214,6 +225,8 @@ IS_AM_SUBCLASS(335x, 0x335)
 #define soc_is_am35xx()                 0
 #define soc_is_am33xx()                 0
 #define soc_is_am335x()                 0
+#define soc_is_am43xx()                 0
+#define soc_is_am437x()                 0
 #define cpu_is_omap44xx()               0
 #define cpu_is_omap443x()               0
 #define cpu_is_omap446x()               0
@@ -341,6 +354,13 @@ IS_OMAP_TYPE(3430, 0x3430)
 # define soc_is_am335x()                is_am335x()
 #endif
+#ifdef  CONFIG_SOC_AM43XX
+# undef soc_is_am43xx
+# undef soc_is_am437x
+# define soc_is_am43xx()                is_am43xx()
+# define soc_is_am437x()                is_am437x()
+#endif
 # if defined(CONFIG_ARCH_OMAP4)
 # undef cpu_is_omap44xx
 # undef cpu_is_omap443x
@@ -383,6 +403,8 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define TI816X_CLASS            0x81600034
 #define TI8168_REV_ES1_0        TI816X_CLASS
 #define TI8168_REV_ES1_1        (TI816X_CLASS | (0x1 << 8))
+#define TI8168_REV_ES2_0        (TI816X_CLASS | (0x2 << 8))
+#define TI8168_REV_ES2_1        (TI816X_CLASS | (0x3 << 8))
 #define TI814X_CLASS            0x81400034
 #define TI8148_REV_ES1_0        TI814X_CLASS
@@ -398,6 +420,9 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define AM335X_REV_ES2_0        (AM335X_CLASS | (0x1 << 8))
 #define AM335X_REV_ES2_1        (AM335X_CLASS | (0x2 << 8))
+#define AM437X_CLASS            0x43700000
+#define AM437X_REV_ES1_0        AM437X_CLASS
 #define OMAP443X_CLASS          0x44300044
 #define OMAP4430_REV_ES1_0      (OMAP443X_CLASS | (0x10 << 8))
 #define OMAP4430_REV_ES2_0      (OMAP443X_CLASS | (0x20 << 8))
@@ -424,6 +449,7 @@ void omap4xxx_check_revision(void);
 void omap5xxx_check_revision(void);
 void omap3xxx_check_features(void);
 void ti81xx_check_features(void);
+void am33xx_check_features(void);
 void omap4xxx_check_features(void);
 /*
diff --git a/arch/arm/mach-omap2/sram.c b/arch/arm/mach-omap2/sram.c
index 0ff0f068bea8..4bd096836235 100644
--- a/arch/arm/mach-omap2/sram.c
+++ b/arch/arm/mach-omap2/sram.c
@@ -119,6 +119,9 @@ static void __init omap_detect_sram(void)
                if (soc_is_am33xx()) {
                        omap_sram_start = AM33XX_SRAM_PA;
                        omap_sram_size = 0x10000; /* 64K */
+                } else if (soc_is_am43xx()) {
+                        omap_sram_start = AM33XX_SRAM_PA;
+                        omap_sram_size = SZ_256K;
                } else if (cpu_is_omap34xx()) {
                        omap_sram_start = OMAP3_SRAM_PA;
                        omap_sram_size = 0x10000; /* 64K */
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index f8b23b8040d9..b37e1fcbad56 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -41,10 +41,10 @@
 #include <linux/of_irq.h>
 #include <linux/platform_device.h>
 #include <linux/platform_data/dmtimer-omap.h>
+#include <linux/sched_clock.h>
 #include <asm/mach/time.h>
 #include <asm/smp_twd.h>
-#include <asm/sched_clock.h>
 #include "omap_hwmod.h"
 #include "omap_device.h"
@@ -220,7 +220,7 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
                                         int posted)
 {
        char name[10]; /* 10 = sizeof("gptXX_Xck0") */
-        const char *oh_name;
+        const char *oh_name = NULL;
        struct device_node *np;
        struct omap_hwmod *oh;
        struct resource irq, mem;
@@ -582,7 +582,7 @@ OMAP_SYS_32K_TIMER_INIT(2, 1, "timer_32k_ck", "ti,timer-alwon",
                        2, "timer_sys_ck", NULL);
 #endif /* CONFIG_ARCH_OMAP2 */
-#ifdef CONFIG_ARCH_OMAP3
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
 OMAP_SYS_32K_TIMER_INIT(3, 1, "timer_32k_ck", "ti,timer-alwon",
                        2, "timer_sys_ck", NULL);
 OMAP_SYS_32K_TIMER_INIT(3_secure, 12, "secure_32k_fck", "ti,timer-secure",
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index 51e138cc5398..c05898fbd634 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -140,6 +140,7 @@ static struct regulator_init_data omap3_vdac_idata = {
 static struct regulator_consumer_supply omap3_vpll2_supplies[] = {
        REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dpi.0"),
        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"),
 };
diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
index aa27d7f5cbb7..2eb19d4d0aa1 100644
--- a/arch/arm/mach-omap2/usb-host.c
+++ b/arch/arm/mach-omap2/usb-host.c
@@ -28,6 +28,7 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/usb/phy.h>
+#include <linux/usb/nop-usb-xceiv.h>
 #include "soc.h"
 #include "omap_device.h"
@@ -188,125 +189,6 @@ static void __init setup_ehci_io_mux(const enum usbhs_omap_port_mode *port_mode)
        return;
 }
-static
-void __init setup_4430ehci_io_mux(const enum usbhs_omap_port_mode *port_mode)
-{
-        switch (port_mode[0]) {
-        case OMAP_EHCI_PORT_MODE_PHY:
-                omap_mux_init_signal("usbb1_ulpiphy_stp",
-                        OMAP_PIN_OUTPUT);
-                omap_mux_init_signal("usbb1_ulpiphy_clk",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpiphy_dir",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpiphy_nxt",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpiphy_dat0",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpiphy_dat1",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpiphy_dat2",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpiphy_dat3",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpiphy_dat4",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpiphy_dat5",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpiphy_dat6",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpiphy_dat7",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                        break;
-        case OMAP_EHCI_PORT_MODE_TLL:
-                omap_mux_init_signal("usbb1_ulpitll_stp",
-                        OMAP_PIN_INPUT_PULLUP);
-                omap_mux_init_signal("usbb1_ulpitll_clk",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpitll_dir",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpitll_nxt",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpitll_dat0",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpitll_dat1",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpitll_dat2",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpitll_dat3",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpitll_dat4",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpitll_dat5",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpitll_dat6",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpitll_dat7",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                        break;
-        case OMAP_USBHS_PORT_MODE_UNUSED:
-        default:
-                        break;
-        }
-        switch (port_mode[1]) {
-        case OMAP_EHCI_PORT_MODE_PHY:
-                omap_mux_init_signal("usbb2_ulpiphy_stp",
-                        OMAP_PIN_OUTPUT);
-                omap_mux_init_signal("usbb2_ulpiphy_clk",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpiphy_dir",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpiphy_nxt",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpiphy_dat0",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpiphy_dat1",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpiphy_dat2",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpiphy_dat3",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpiphy_dat4",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpiphy_dat5",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpiphy_dat6",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpiphy_dat7",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                        break;
-        case OMAP_EHCI_PORT_MODE_TLL:
-                omap_mux_init_signal("usbb2_ulpitll_stp",
-                        OMAP_PIN_INPUT_PULLUP);
-                omap_mux_init_signal("usbb2_ulpitll_clk",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpitll_dir",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpitll_nxt",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpitll_dat0",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpitll_dat1",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpitll_dat2",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpitll_dat3",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpitll_dat4",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpitll_dat5",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpitll_dat6",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpitll_dat7",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                        break;
-        case OMAP_USBHS_PORT_MODE_UNUSED:
-        default:
-                        break;
-        }
-}
 static void __init setup_ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
 {
        switch (port_mode[0]) {
@@ -404,78 +286,6 @@ static void __init setup_ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
        }
 }
-static
-void __init setup_4430ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
-{
-        switch (port_mode[0]) {
-        case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
-        case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
-        case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
-        case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
-                omap_mux_init_signal("usbb1_mm_rxdp",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_mm_rxdm",
-                        OMAP_PIN_INPUT_PULLDOWN);
-        case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
-        case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
-                omap_mux_init_signal("usbb1_mm_rxrcv",
-                        OMAP_PIN_INPUT_PULLDOWN);
-        case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
-        case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
-                omap_mux_init_signal("usbb1_mm_txen",
-                        OMAP_PIN_INPUT_PULLDOWN);
-        case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
-        case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
-                omap_mux_init_signal("usbb1_mm_txdat",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_mm_txse0",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                break;
-        case OMAP_USBHS_PORT_MODE_UNUSED:
-        default:
-                break;
-        }
-        switch (port_mode[1]) {
-        case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
-        case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
-        case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
-        case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
-                omap_mux_init_signal("usbb2_mm_rxdp",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_mm_rxdm",
-                        OMAP_PIN_INPUT_PULLDOWN);
-        case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
-        case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
-                omap_mux_init_signal("usbb2_mm_rxrcv",
-                        OMAP_PIN_INPUT_PULLDOWN);
-        case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
-        case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
-                omap_mux_init_signal("usbb2_mm_txen",
-                        OMAP_PIN_INPUT_PULLDOWN);
-        case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
-        case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
-                omap_mux_init_signal("usbb2_mm_txdat",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_mm_txse0",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                break;
-        case OMAP_USBHS_PORT_MODE_UNUSED:
-        default:
-                break;
-        }
-}
 void __init usbhs_init(struct usbhs_omap_platform_data *pdata)
 {
        struct omap_hwmod       *uhh_hwm, *tll_hwm;
@@ -489,9 +299,6 @@ void __init usbhs_init(struct usbhs_omap_platform_data *pdata)
                if (omap_rev() <= OMAP3430_REV_ES2_1)
                        pdata->single_ulpi_bypass = true;
-        } else if (cpu_is_omap44xx()) {
-                setup_4430ehci_io_mux(pdata->port_mode);
-                setup_4430ohci_io_mux(pdata->port_mode);
        }
        uhh_hwm = omap_hwmod_lookup(USBHS_UHH_HWMODNAME);
@@ -560,7 +367,8 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
        struct regulator_init_data *reg_data;
        struct fixed_voltage_config *config;
        struct platform_device *pdev;
-        int ret;
+        struct platform_device_info pdevinfo;
+        int ret = -ENOMEM;
        supplies = kzalloc(sizeof(*supplies), GFP_KERNEL);
        if (!supplies)
@@ -571,7 +379,7 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
        reg_data = kzalloc(sizeof(*reg_data), GFP_KERNEL);
        if (!reg_data)
-                return -ENOMEM;
+                goto err_data;
        reg_data->constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS;
        reg_data->consumer_supplies = supplies;
@@ -580,39 +388,53 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
        config = kmemdup(&hsusb_reg_config, sizeof(hsusb_reg_config),
                        GFP_KERNEL);
        if (!config)
-                return -ENOMEM;
+                goto err_config;
+        config->supply_name = kstrdup(name, GFP_KERNEL);
+        if (!config->supply_name)
+                goto err_supplyname;
-        config->supply_name = name;
        config->gpio = gpio;
        config->enable_high = polarity;
        config->init_data = reg_data;
        /* create a regulator device */
-        pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
+        memset(&pdevinfo, 0, sizeof(pdevinfo));
-        if (!pdev)
+        pdevinfo.name = reg_name;
-                return -ENOMEM;
+        pdevinfo.id = PLATFORM_DEVID_AUTO;
+        pdevinfo.data = config;
+        pdevinfo.size_data = sizeof(*config);
-        pdev->id = PLATFORM_DEVID_AUTO;
+        pdev = platform_device_register_full(&pdevinfo);
-        pdev->name = reg_name;
+        if (IS_ERR(pdev)) {
-        pdev->dev.platform_data = config;
+                ret = PTR_ERR(pdev);
+                pr_err("%s: Failed registering regulator %s for %s : %d\n",
+                                __func__, name, dev_id, ret);
+                goto err_register;
+        }
-        ret = platform_device_register(pdev);
+        return 0;
-        if (ret)
-                pr_err("%s: Failed registering regulator %s for %s\n",
-                                __func__, name, dev_id);
+err_register:
+        kfree(config->supply_name);
+err_supplyname:
+        kfree(config);
+err_config:
+        kfree(reg_data);
+err_data:
+        kfree(supplies);
        return ret;
 }
+#define MAX_STR 20
 int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys)
 {
-        char *rail_name;
+        char rail_name[MAX_STR];
-        int i, len;
+        int i;
        struct platform_device *pdev;
        char *phy_id;
+        struct platform_device_info pdevinfo;
-        /* the phy_id will be something like "nop_usb_xceiv.1" */
-        len = strlen(nop_name) + 3; /* 3 -> ".1" and NULL terminator */
        for (i = 0; i < num_phys; i++) {
@@ -627,25 +449,26 @@ int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys)
                        !gpio_is_valid(phy->vcc_gpio))
                        continue;
-                /* create a NOP PHY device */
+                phy_id = kmalloc(MAX_STR, GFP_KERNEL);
-                pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
+                if (!phy_id) {
-                if (!pdev)
+                        pr_err("%s: kmalloc() failed\n", __func__);
                        return -ENOMEM;
+                }
-                pdev->id = phy->port;
+                /* create a NOP PHY device */
-                pdev->name = nop_name;
+                memset(&pdevinfo, 0, sizeof(pdevinfo));
-                pdev->dev.platform_data = phy->platform_data;
+                pdevinfo.name = nop_name;
+                pdevinfo.id = phy->port;
-                phy_id = kmalloc(len, GFP_KERNEL);
+                pdevinfo.data = phy->platform_data;
-                if (!phy_id)
+                pdevinfo.size_data = sizeof(struct nop_usb_xceiv_platform_data);
-                        return -ENOMEM;
+                scnprintf(phy_id, MAX_STR, "nop_usb_xceiv.%d",
-                scnprintf(phy_id, len, "nop_usb_xceiv.%d\n",
+                                        phy->port);
-                                        pdev->id);
+                pdev = platform_device_register_full(&pdevinfo);
+                if (IS_ERR(pdev)) {
-                if (platform_device_register(pdev)) {
+                        pr_err("%s: Failed to register device %s : %ld\n",
-                        pr_err("%s: Failed to register device %s\n",
+                                __func__,  phy_id, PTR_ERR(pdev));
-                                __func__,  phy_id);
+                        kfree(phy_id);
                        continue;
                }
@@ -653,26 +476,15 @@ int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys)
                /* Do we need RESET regulator ? */
                if (gpio_is_valid(phy->reset_gpio)) {
+                        scnprintf(rail_name, MAX_STR,
-                        rail_name = kmalloc(13, GFP_KERNEL);
+                                        "hsusb%d_reset", phy->port);
-                        if (!rail_name)
-                                return -ENOMEM;
-                        scnprintf(rail_name, 13, "hsusb%d_reset", phy->port);
                        usbhs_add_regulator(rail_name, phy_id, "reset",
                                                phy->reset_gpio, 1);
                }
                /* Do we need VCC regulator ? */
                if (gpio_is_valid(phy->vcc_gpio)) {
+                        scnprintf(rail_name, MAX_STR, "hsusb%d_vcc", phy->port);
-                        rail_name = kmalloc(13, GFP_KERNEL);
-                        if (!rail_name)
-                                return -ENOMEM;
-                        scnprintf(rail_name, 13, "hsusb%d_vcc", phy->port);
                        usbhs_add_regulator(rail_name, phy_id, "vcc",
                                        phy->vcc_gpio, phy->vcc_polarity);
                }
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index 3242a554ad6b..8c4de2708cf2 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -85,9 +85,6 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
        musb_plat.mode = board_data->mode;
        musb_plat.extvbus = board_data->extvbus;
-        if (cpu_is_omap44xx())
-                musb_plat.has_mailbox = true;
        if (soc_is_am35xx()) {
                oh_name = "am35x_otg_hs";
                name = "musb-am35x";
diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
index a0ce4f10ff13..f7f2879b31b0 100644
--- a/arch/arm/mach-omap2/voltage.h
+++ b/arch/arm/mach-omap2/voltage.h
@@ -169,8 +169,8 @@ int omap_voltage_late_init(void);
 extern void omap2xxx_voltagedomains_init(void);
 extern void omap3xxx_voltagedomains_init(void);
-extern void am33xx_voltagedomains_init(void);
 extern void omap44xx_voltagedomains_init(void);
+extern void omap54xx_voltagedomains_init(void);
 struct voltagedomain *voltdm_lookup(const char *name);
 void voltdm_init(struct voltagedomain **voltdm_list);
diff --git a/arch/arm/mach-omap2/voltagedomains33xx_data.c b/arch/arm/mach-omap2/voltagedomains33xx_data.c
deleted file mode 100644
index 965458dc0cb9..000000000000
--- a/arch/arm/mach-omap2/voltagedomains33xx_data.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * AM33XX voltage domain data
- *
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include "voltage.h"
-static struct voltagedomain am33xx_voltdm_mpu = {
-        .name           = "mpu",
-};
-static struct voltagedomain am33xx_voltdm_core = {
-        .name           = "core",
-};
-static struct voltagedomain am33xx_voltdm_rtc = {
-        .name           = "rtc",
-};
-static struct voltagedomain *voltagedomains_am33xx[] __initdata = {
-        &am33xx_voltdm_mpu,
-        &am33xx_voltdm_core,
-        &am33xx_voltdm_rtc,
-        NULL,
-};
-void __init am33xx_voltagedomains_init(void)
-{
-        voltdm_init(voltagedomains_am33xx);
-}
diff --git a/arch/arm/mach-omap2/voltagedomains54xx_data.c b/arch/arm/mach-omap2/voltagedomains54xx_data.c
new file mode 100644
index 000000000000..33d22b87252d
--- /dev/null
+++ b/arch/arm/mach-omap2/voltagedomains54xx_data.c
@@ -0,0 +1,92 @@
+/*
+ * OMAP5 Voltage Management Routines
+ *
+ * Based on voltagedomains44xx_data.c
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include "common.h"
+#include "prm54xx.h"
+#include "voltage.h"
+#include "omap_opp_data.h"
+#include "vc.h"
+#include "vp.h"
+static const struct omap_vfsm_instance omap5_vdd_mpu_vfsm = {
+        .voltsetup_reg = OMAP54XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET,
+};
+static const struct omap_vfsm_instance omap5_vdd_mm_vfsm = {
+        .voltsetup_reg = OMAP54XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET,
+};
+static const struct omap_vfsm_instance omap5_vdd_core_vfsm = {
+        .voltsetup_reg = OMAP54XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET,
+};
+static struct voltagedomain omap5_voltdm_mpu = {
+        .name = "mpu",
+        .scalable = true,
+        .read = omap4_prm_vcvp_read,
+        .write = omap4_prm_vcvp_write,
+        .rmw = omap4_prm_vcvp_rmw,
+        .vc = &omap4_vc_mpu,
+        .vfsm = &omap5_vdd_mpu_vfsm,
+        .vp = &omap4_vp_mpu,
+};
+static struct voltagedomain omap5_voltdm_mm = {
+        .name = "mm",
+        .scalable = true,
+        .read = omap4_prm_vcvp_read,
+        .write = omap4_prm_vcvp_write,
+        .rmw = omap4_prm_vcvp_rmw,
+        .vc = &omap4_vc_iva,
+        .vfsm = &omap5_vdd_mm_vfsm,
+        .vp = &omap4_vp_iva,
+};
+static struct voltagedomain omap5_voltdm_core = {
+        .name = "core",
+        .scalable = true,
+        .read = omap4_prm_vcvp_read,
+        .write = omap4_prm_vcvp_write,
+        .rmw = omap4_prm_vcvp_rmw,
+        .vc = &omap4_vc_core,
+        .vfsm = &omap5_vdd_core_vfsm,
+        .vp = &omap4_vp_core,
+};
+static struct voltagedomain omap5_voltdm_wkup = {
+        .name = "wkup",
+};
+static struct voltagedomain *voltagedomains_omap5[] __initdata = {
+        &omap5_voltdm_mpu,
+        &omap5_voltdm_mm,
+        &omap5_voltdm_core,
+        &omap5_voltdm_wkup,
+        NULL,
+};
+static const char *sys_clk_name __initdata = "sys_clkin";
+void __init omap54xx_voltagedomains_init(void)
+{
+        struct voltagedomain *voltdm;
+        int i;
+        for (i = 0; voltdm = voltagedomains_omap5[i], voltdm; i++)
+                voltdm->sys_clk.name = sys_clk_name;
+        voltdm_init(voltagedomains_omap5);
+};
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index f8a6db9239bf..b41599f98a8e 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -347,7 +347,7 @@ void __init orion5x_init(void)
        orion5x_wdt_init();
 }
-void orion5x_restart(char mode, const char *cmd)
+void orion5x_restart(enum reboot_mode mode, const char *cmd)
 {
        /*
         * Enable and issue soft reset
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index cdaa01f3d186..a909afb384fb 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -1,6 +1,8 @@
 #ifndef __ARCH_ORION5X_COMMON_H
 #define __ARCH_ORION5X_COMMON_H
+#include <linux/reboot.h>
 struct dsa_platform_data;
 struct mv643xx_eth_platform_data;
 struct mv_sata_platform_data;
@@ -29,7 +31,7 @@ void orion5x_spi_init(void);
 void orion5x_uart0_init(void);
 void orion5x_uart1_init(void);
 void orion5x_xor_init(void);
-void orion5x_restart(char, const char *);
+void orion5x_restart(enum reboot_mode, const char *);
 /*
 * PCIe/PCI functions.
diff --git a/arch/arm/mach-orion5x/include/mach/bridge-regs.h b/arch/arm/mach-orion5x/include/mach/bridge-regs.h
index 461fd69a10ae..f727d03f1688 100644
--- a/arch/arm/mach-orion5x/include/mach/bridge-regs.h
+++ b/arch/arm/mach-orion5x/include/mach/bridge-regs.h
@@ -18,7 +18,6 @@
 #define CPU_CTRL                (ORION5X_BRIDGE_VIRT_BASE + 0x104)
 #define RSTOUTn_MASK            (ORION5X_BRIDGE_VIRT_BASE + 0x108)
-#define WDT_RESET_OUT_EN        0x0002
 #define CPU_SOFT_RESET          (ORION5X_BRIDGE_VIRT_BASE + 0x10c)
@@ -26,8 +25,6 @@
 #define POWER_MNG_CTRL_REG      (ORION5X_BRIDGE_VIRT_BASE + 0x11C)
-#define WDT_INT_REQ             0x0008
 #define BRIDGE_INT_TIMER1_CLR   (~0x0004)
 #define MAIN_IRQ_CAUSE          (ORION5X_BRIDGE_VIRT_BASE + 0x200)
diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c
index 24f4e14e5893..6234977b5aea 100644
--- a/arch/arm/mach-orion5x/ls-chl-setup.c
+++ b/arch/arm/mach-orion5x/ls-chl-setup.c
@@ -139,7 +139,7 @@ static struct mv_sata_platform_data lschl_sata_data = {
 static void lschl_power_off(void)
 {
-        orion5x_restart('h', NULL);
+        orion5x_restart(REBOOT_HARD, NULL);
 }
 /*****************************************************************************
diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c
index fc653bb41e78..fe04c4b64569 100644
--- a/arch/arm/mach-orion5x/ls_hgl-setup.c
+++ b/arch/arm/mach-orion5x/ls_hgl-setup.c
@@ -185,7 +185,7 @@ static struct mv_sata_platform_data ls_hgl_sata_data = {
 static void ls_hgl_power_off(void)
 {
-        orion5x_restart('h', NULL);
+        orion5x_restart(REBOOT_HARD, NULL);
 }
diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c
index 18e66e617dc2..ca4dbe973daf 100644
--- a/arch/arm/mach-orion5x/lsmini-setup.c
+++ b/arch/arm/mach-orion5x/lsmini-setup.c
@@ -185,7 +185,7 @@ static struct mv_sata_platform_data lsmini_sata_data = {
 static void lsmini_power_off(void)
 {
-        orion5x_restart('h', NULL);
+        orion5x_restart(REBOOT_HARD, NULL);
 }
diff --git a/arch/arm/mach-picoxcell/Kconfig b/arch/arm/mach-picoxcell/Kconfig
index 13bae78b215a..b1022f4315f7 100644
--- a/arch/arm/mach-picoxcell/Kconfig
+++ b/arch/arm/mach-picoxcell/Kconfig
@@ -4,7 +4,6 @@ config ARCH_PICOXCELL
        select ARM_PATCH_PHYS_VIRT
        select ARM_VIC
        select CPU_V6K
-        select DW_APB_TIMER
        select DW_APB_TIMER_OF
        select GENERIC_CLOCKEVENTS
        select HAVE_TCM
diff --git a/arch/arm/mach-picoxcell/common.c b/arch/arm/mach-picoxcell/common.c
index 70b441ad1d18..ec79fea82704 100644
--- a/arch/arm/mach-picoxcell/common.c
+++ b/arch/arm/mach-picoxcell/common.c
@@ -8,20 +8,14 @@
 * All enquiries to support@picochip.com
 */
 #include <linux/delay.h>
-#include <linux/irq.h>
-#include <linux/irqchip.h>
-#include <linux/irqdomain.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
-#include <linux/of_irq.h>
 #include <linux/of_platform.h>
-#include <linux/dw_apb_timer.h>
+#include <linux/reboot.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include "common.h"
 #define PHYS_TO_IO(x)                   (((x) & 0x00ffffff) | 0xfe000000)
 #define PICOXCELL_PERIPH_BASE           0x80000000
 #define PICOXCELL_PERIPH_LENGTH         SZ_4M
@@ -70,7 +64,7 @@ static const char *picoxcell_dt_match[] = {
        NULL
 };
-static void picoxcell_wdt_restart(char mode, const char *cmd)
+static void picoxcell_wdt_restart(enum reboot_mode mode, const char *cmd)
 {
        /*
         * Configure the watchdog to reset with the shortest possible timeout
@@ -86,9 +80,6 @@ static void picoxcell_wdt_restart(char mode, const char *cmd)
 DT_MACHINE_START(PICOXCELL, "Picochip picoXcell")
        .map_io         = picoxcell_map_io,
-        .nr_irqs        = NR_IRQS_LEGACY,
-        .init_irq       = irqchip_init,
-        .init_time      = dw_apb_timer_init,
        .init_machine   = picoxcell_init_machine,
        .dt_compat      = picoxcell_dt_match,
        .restart        = picoxcell_wdt_restart,
diff --git a/arch/arm/mach-picoxcell/common.h b/arch/arm/mach-picoxcell/common.h
deleted file mode 100644
index 481b42a4ef15..000000000000
--- a/arch/arm/mach-picoxcell/common.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright (c) 2011 Picochip Ltd., Jamie Iles
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * All enquiries to support@picochip.com
- */
-#ifndef __PICOXCELL_COMMON_H__
-#define __PICOXCELL_COMMON_H__
-#include <asm/mach/time.h>
-extern void dw_apb_timer_init(void);
-#endif /* __PICOXCELL_COMMON_H__ */
diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c
index 4f94cd87972a..2c70f74fed5d 100644
--- a/arch/arm/mach-prima2/common.c
+++ b/arch/arm/mach-prima2/common.c
@@ -9,7 +9,6 @@
 #include <linux/clocksource.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
-#include <linux/irqchip.h>
 #include <asm/sizes.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -17,16 +16,6 @@
 #include <linux/of_platform.h>
 #include "common.h"
-static struct of_device_id sirfsoc_of_bus_ids[] __initdata = {
-        { .compatible = "simple-bus", },
-        {},
-};
-void __init sirfsoc_mach_init(void)
-{
-        of_platform_bus_probe(NULL, sirfsoc_of_bus_ids, NULL);
-}
 void __init sirfsoc_init_late(void)
 {
        sirfsoc_pm_init();
@@ -55,9 +44,7 @@ DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)")
        /* Maintainer: Barry Song <baohua.song@csr.com> */
        .nr_irqs        = 128,
        .map_io         = sirfsoc_map_io,
-        .init_irq       = irqchip_init,
        .init_time      = sirfsoc_init_time,
-        .init_machine   = sirfsoc_mach_init,
        .init_late      = sirfsoc_init_late,
        .dt_compat      = atlas6_dt_match,
        .restart        = sirfsoc_restart,
@@ -66,18 +53,16 @@ MACHINE_END
 #ifdef CONFIG_ARCH_PRIMA2
 static const char *prima2_dt_match[] __initdata = {
-       "sirf,prima2",
+        "sirf,prima2",
-       NULL
+        NULL
 };
 DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
        /* Maintainer: Barry Song <baohua.song@csr.com> */
        .nr_irqs        = 128,
        .map_io         = sirfsoc_map_io,
-        .init_irq       = irqchip_init,
        .init_time      = sirfsoc_init_time,
        .dma_zone_size  = SZ_256M,
-        .init_machine   = sirfsoc_mach_init,
        .init_late      = sirfsoc_init_late,
        .dt_compat      = prima2_dt_match,
        .restart        = sirfsoc_restart,
@@ -94,9 +79,7 @@ DT_MACHINE_START(MARCO_DT, "Generic MARCO (Flattened Device Tree)")
        /* Maintainer: Barry Song <baohua.song@csr.com> */
        .smp            = smp_ops(sirfsoc_smp_ops),
        .map_io         = sirfsoc_map_io,
-        .init_irq       = irqchip_init,
        .init_time      = sirfsoc_init_time,
-        .init_machine   = sirfsoc_mach_init,
        .init_late      = sirfsoc_init_late,
        .dt_compat      = marco_dt_match,
        .restart        = sirfsoc_restart,
diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h
index 81135cd88e54..a6304858474a 100644
--- a/arch/arm/mach-prima2/common.h
+++ b/arch/arm/mach-prima2/common.h
@@ -10,6 +10,8 @@
 #define __MACH_PRIMA2_COMMON_H__
 #include <linux/init.h>
+#include <linux/reboot.h>
 #include <asm/mach/time.h>
 #include <asm/exception.h>
@@ -22,7 +24,7 @@ extern void sirfsoc_cpu_die(unsigned int cpu);
 extern void __init sirfsoc_of_irq_init(void);
 extern void __init sirfsoc_of_clk_init(void);
-extern void sirfsoc_restart(char, const char *);
+extern void sirfsoc_restart(enum reboot_mode, const char *);
 extern asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs);
 #ifndef CONFIG_DEBUG_LL
diff --git a/arch/arm/mach-prima2/headsmp.S b/arch/arm/mach-prima2/headsmp.S
index 5b8a408d8921..d86fe33c5f53 100644
--- a/arch/arm/mach-prima2/headsmp.S
+++ b/arch/arm/mach-prima2/headsmp.S
@@ -9,8 +9,6 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
-        __CPUINIT
 /*
 * SIRFSOC specific entry point for secondary CPUs.  This provides
 * a "holding pen" into which all secondary cores are held until we're
diff --git a/arch/arm/mach-prima2/platsmp.c b/arch/arm/mach-prima2/platsmp.c
index 1c3de7bed841..3dbcb1ab6e37 100644
--- a/arch/arm/mach-prima2/platsmp.c
+++ b/arch/arm/mach-prima2/platsmp.c
@@ -44,7 +44,7 @@ void __init sirfsoc_map_scu(void)
        scu_base = (void __iomem *)SIRFSOC_VA(base);
 }
-static void __cpuinit sirfsoc_secondary_init(unsigned int cpu)
+static void sirfsoc_secondary_init(unsigned int cpu)
 {
        /*
         * let the primary processor know we're out of the
@@ -65,7 +65,7 @@ static struct of_device_id rsc_ids[]  = {
        {},
 };
-static int __cpuinit sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
        unsigned long timeout;
        struct device_node *np;
diff --git a/arch/arm/mach-prima2/pm.c b/arch/arm/mach-prima2/pm.c
index 8f595c0cc8d9..02cc34388b05 100644
--- a/arch/arm/mach-prima2/pm.c
+++ b/arch/arm/mach-prima2/pm.c
@@ -9,7 +9,7 @@
 #include <linux/kernel.h>
 #include <linux/suspend.h>
 #include <linux/slab.h>
-#include <linux/module.h>
+#include <linux/export.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_device.h>
diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach-prima2/rstc.c
index d5e0cbc934c0..ccb53391147a 100644
--- a/arch/arm/mach-prima2/rstc.c
+++ b/arch/arm/mach-prima2/rstc.c
@@ -13,6 +13,7 @@
 #include <linux/device.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/reboot.h>
 void __iomem *sirfsoc_rstc_base;
 static DEFINE_MUTEX(rstc_lock);
@@ -84,7 +85,7 @@ int sirfsoc_reset_device(struct device *dev)
 #define SIRFSOC_SYS_RST_BIT  BIT(31)
-void sirfsoc_restart(char mode, const char *cmd)
+void sirfsoc_restart(enum reboot_mode mode, const char *cmd)
 {
        writel(SIRFSOC_SYS_RST_BIT, sirfsoc_rstc_base);
 }
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 96100dbf5a2e..a8427115ee07 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -615,12 +615,14 @@ endmenu
 config PXA25x
        bool
        select CPU_XSCALE
+        select CPU_FREQ_TABLE if CPU_FREQ
        help
          Select code specific to PXA21x/25x/26x variants
 config PXA27x
        bool
        select CPU_XSCALE
+        select CPU_FREQ_TABLE if CPU_FREQ
        help
          Select code specific to PXA27x variants
@@ -633,6 +635,7 @@ config CPU_PXA26x
 config PXA3xx
        bool
        select CPU_XSC3
+        select CPU_FREQ_TABLE if CPU_FREQ
        help
          Select code specific to PXA3xx variants
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index a5b8fead7d61..f162f1b77cd2 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -663,16 +663,16 @@ static void corgi_poweroff(void)
                /* Green LED off tells the bootloader to halt */
                gpio_set_value(CORGI_GPIO_LED_GREEN, 0);
-        pxa_restart('h', NULL);
+        pxa_restart(REBOOT_HARD, NULL);
 }
-static void corgi_restart(char mode, const char *cmd)
+static void corgi_restart(enum reboot_mode mode, const char *cmd)
 {
        if (!machine_is_corgi())
                /* Green LED on tells the bootloader to reboot */
                gpio_set_value(CORGI_GPIO_LED_GREEN, 1);
-        pxa_restart('h', cmd);
+        pxa_restart(REBOOT_HARD, cmd);
 }
 static void __init corgi_init(void)
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index 446563a7d1ad..3a3362fa793e 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -477,16 +477,24 @@ static int em_x270_usb_hub_init(void)
        /* USB Hub power-on and reset */
        gpio_direction_output(usb_hub_reset, 1);
        gpio_direction_output(GPIO9_USB_VBUS_EN, 0);
-        regulator_enable(em_x270_usb_ldo);
+        err = regulator_enable(em_x270_usb_ldo);
+        if (err)
+                goto err_free_rst_gpio;
        gpio_set_value(usb_hub_reset, 0);
        gpio_set_value(usb_hub_reset, 1);
        regulator_disable(em_x270_usb_ldo);
-        regulator_enable(em_x270_usb_ldo);
+        err = regulator_enable(em_x270_usb_ldo);
+        if (err)
+                goto err_free_rst_gpio;
        gpio_set_value(usb_hub_reset, 0);
        gpio_set_value(GPIO9_USB_VBUS_EN, 1);
        return 0;
+err_free_rst_gpio:
+        gpio_free(usb_hub_reset);
 err_free_vbus_gpio:
        gpio_free(GPIO9_USB_VBUS_EN);
 err_free_usb_ldo:
@@ -592,7 +600,7 @@ err_irq:
        return err;
 }
-static void em_x270_mci_setpower(struct device *dev, unsigned int vdd)
+static int em_x270_mci_setpower(struct device *dev, unsigned int vdd)
 {
        struct pxamci_platform_data* p_d = dev->platform_data;
@@ -600,10 +608,11 @@ static void em_x270_mci_setpower(struct device *dev, unsigned int vdd)
                int vdd_uV = (2000 + (vdd - __ffs(MMC_VDD_20_21)) * 100) * 1000;
                regulator_set_voltage(em_x270_sdio_ldo, vdd_uV, vdd_uV);
-                regulator_enable(em_x270_sdio_ldo);
+                return regulator_enable(em_x270_sdio_ldo);
        } else {
                regulator_disable(em_x270_sdio_ldo);
        }
+        return 0;
 }
 static void em_x270_mci_exit(struct device *dev, void *data)
@@ -833,21 +842,25 @@ static inline void em_x270_init_ac97(void) {}
 #endif
 #if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
-static unsigned int em_x270_module_matrix_keys[] = {
+static const unsigned int em_x270_module_matrix_keys[] = {
        KEY(0, 0, KEY_A), KEY(1, 0, KEY_UP), KEY(2, 1, KEY_B),
        KEY(0, 2, KEY_LEFT), KEY(1, 1, KEY_ENTER), KEY(2, 0, KEY_RIGHT),
        KEY(0, 1, KEY_C), KEY(1, 2, KEY_DOWN), KEY(2, 2, KEY_D),
 };
+static struct matrix_keymap_data em_x270_matrix_keymap_data = {
+        .keymap                 = em_x270_module_matrix_keys,
+        .keymap_size            = ARRAY_SIZE(em_x270_module_matrix_keys),
+};
 struct pxa27x_keypad_platform_data em_x270_module_keypad_info = {
        /* code map for the matrix keys */
        .matrix_key_rows        = 3,
        .matrix_key_cols        = 3,
-        .matrix_key_map         = em_x270_module_matrix_keys,
+        .matrix_keymap_data     = &em_x270_matrix_keymap_data,
-        .matrix_key_map_size    = ARRAY_SIZE(em_x270_module_matrix_keys),
 };
-static unsigned int em_x270_exeda_matrix_keys[] = {
+static const unsigned int em_x270_exeda_matrix_keys[] = {
        KEY(0, 0, KEY_RIGHTSHIFT), KEY(0, 1, KEY_RIGHTCTRL),
        KEY(0, 2, KEY_RIGHTALT), KEY(0, 3, KEY_SPACE),
        KEY(0, 4, KEY_LEFTALT), KEY(0, 5, KEY_LEFTCTRL),
@@ -889,12 +902,16 @@ static unsigned int em_x270_exeda_matrix_keys[] = {
        KEY(7, 6, 0), KEY(7, 7, 0),
 };
+static struct matrix_keymap_data em_x270_exeda_matrix_keymap_data = {
+        .keymap                 = em_x270_exeda_matrix_keys,
+        .keymap_size            = ARRAY_SIZE(em_x270_exeda_matrix_keys),
+};
 struct pxa27x_keypad_platform_data em_x270_exeda_keypad_info = {
        /* code map for the matrix keys */
        .matrix_key_rows        = 8,
        .matrix_key_cols        = 8,
-        .matrix_key_map         = em_x270_exeda_matrix_keys,
+        .matrix_keymap_data     = &em_x270_exeda_matrix_keymap_data,
-        .matrix_key_map_size    = ARRAY_SIZE(em_x270_exeda_matrix_keys),
 };
 static void __init em_x270_init_keypad(void)
diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c
index dca10709be8f..fe2eb8394dff 100644
--- a/arch/arm/mach-pxa/ezx.c
+++ b/arch/arm/mach-pxa/ezx.c
@@ -392,7 +392,7 @@ static unsigned long e6_pin_config[] __initdata = {
 /* KEYPAD */
 #ifdef CONFIG_MACH_EZX_A780
-static unsigned int a780_key_map[] = {
+static const unsigned int a780_key_map[] = {
        KEY(0, 0, KEY_SEND),
        KEY(0, 1, KEY_BACK),
        KEY(0, 2, KEY_END),
@@ -424,11 +424,15 @@ static unsigned int a780_key_map[] = {
        KEY(4, 4, KEY_DOWN),
 };
+static struct matrix_keymap_data a780_matrix_keymap_data = {
+        .keymap                 = a780_key_map,
+        .keymap_size            = ARRAY_SIZE(a780_key_map),
+};
 static struct pxa27x_keypad_platform_data a780_keypad_platform_data = {
        .matrix_key_rows = 5,
        .matrix_key_cols = 5,
-        .matrix_key_map = a780_key_map,
+        .matrix_keymap_data = &a780_matrix_keymap_data,
-        .matrix_key_map_size = ARRAY_SIZE(a780_key_map),
        .direct_key_map = { KEY_CAMERA },
        .direct_key_num = 1,
@@ -438,7 +442,7 @@ static struct pxa27x_keypad_platform_data a780_keypad_platform_data = {
 #endif /* CONFIG_MACH_EZX_A780 */
 #ifdef CONFIG_MACH_EZX_E680
-static unsigned int e680_key_map[] = {
+static const unsigned int e680_key_map[] = {
        KEY(0, 0, KEY_UP),
        KEY(0, 1, KEY_RIGHT),
        KEY(0, 2, KEY_RESERVED),
@@ -455,11 +459,15 @@ static unsigned int e680_key_map[] = {
        KEY(2, 3, KEY_KPENTER),
 };
+static struct matrix_keymap_data e680_matrix_keymap_data = {
+        .keymap                 = e680_key_map,
+        .keymap_size            = ARRAY_SIZE(e680_key_map),
+};
 static struct pxa27x_keypad_platform_data e680_keypad_platform_data = {
        .matrix_key_rows = 3,
        .matrix_key_cols = 4,
-        .matrix_key_map = e680_key_map,
+        .matrix_keymap_data = &e680_matrix_keymap_data,
-        .matrix_key_map_size = ARRAY_SIZE(e680_key_map),
        .direct_key_map = {
                KEY_CAMERA,
@@ -476,7 +484,7 @@ static struct pxa27x_keypad_platform_data e680_keypad_platform_data = {
 #endif /* CONFIG_MACH_EZX_E680 */
 #ifdef CONFIG_MACH_EZX_A1200
-static unsigned int a1200_key_map[] = {
+static const unsigned int a1200_key_map[] = {
        KEY(0, 0, KEY_RESERVED),
        KEY(0, 1, KEY_RIGHT),
        KEY(0, 2, KEY_PAGEDOWN),
@@ -513,18 +521,22 @@ static unsigned int a1200_key_map[] = {
        KEY(4, 5, KEY_RESERVED),
 };
+static struct matrix_keymap_data a1200_matrix_keymap_data = {
+        .keymap                 = a1200_key_map,
+        .keymap_size            = ARRAY_SIZE(a1200_key_map),
+};
 static struct pxa27x_keypad_platform_data a1200_keypad_platform_data = {
        .matrix_key_rows = 5,
        .matrix_key_cols = 6,
-        .matrix_key_map = a1200_key_map,
+        .matrix_keymap_data = &a1200_matrix_keymap_data,
-        .matrix_key_map_size = ARRAY_SIZE(a1200_key_map),
        .debounce_interval = 30,
 };
 #endif /* CONFIG_MACH_EZX_A1200 */
 #ifdef CONFIG_MACH_EZX_E6
-static unsigned int e6_key_map[] = {
+static const unsigned int e6_key_map[] = {
        KEY(0, 0, KEY_RESERVED),
        KEY(0, 1, KEY_RIGHT),
        KEY(0, 2, KEY_PAGEDOWN),
@@ -561,18 +573,22 @@ static unsigned int e6_key_map[] = {
        KEY(4, 5, KEY_PREVIOUSSONG),
 };
+static struct matrix_keymap_data e6_keymap_data = {
+        .keymap                 = e6_key_map,
+        .keymap_size            = ARRAY_SIZE(e6_key_map),
+};
 static struct pxa27x_keypad_platform_data e6_keypad_platform_data = {
        .matrix_key_rows = 5,
        .matrix_key_cols = 6,
-        .matrix_key_map = e6_key_map,
+        .matrix_keymap_data = &e6_keymap_data,
-        .matrix_key_map_size = ARRAY_SIZE(e6_key_map),
        .debounce_interval = 30,
 };
 #endif /* CONFIG_MACH_EZX_E6 */
 #ifdef CONFIG_MACH_EZX_A910
-static unsigned int a910_key_map[] = {
+static const unsigned int a910_key_map[] = {
        KEY(0, 0, KEY_NUMERIC_6),
        KEY(0, 1, KEY_RIGHT),
        KEY(0, 2, KEY_PAGEDOWN),
@@ -609,18 +625,22 @@ static unsigned int a910_key_map[] = {
        KEY(4, 5, KEY_RESERVED),
 };
+static struct matrix_keymap_data a910_matrix_keymap_data = {
+        .keymap                 = a910_key_map,
+        .keymap_size            = ARRAY_SIZE(a910_key_map),
+};
 static struct pxa27x_keypad_platform_data a910_keypad_platform_data = {
        .matrix_key_rows = 5,
        .matrix_key_cols = 6,
-        .matrix_key_map = a910_key_map,
+        .matrix_keymap_data = &a910_matrix_keymap_data,
-        .matrix_key_map_size = ARRAY_SIZE(a910_key_map),
        .debounce_interval = 30,
 };
 #endif /* CONFIG_MACH_EZX_A910 */
 #ifdef CONFIG_MACH_EZX_E2
-static unsigned int e2_key_map[] = {
+static const unsigned int e2_key_map[] = {
        KEY(0, 0, KEY_NUMERIC_6),
        KEY(0, 1, KEY_RIGHT),
        KEY(0, 2, KEY_NUMERIC_9),
@@ -657,11 +677,15 @@ static unsigned int e2_key_map[] = {
        KEY(4, 5, KEY_RESERVED),
 };
+static struct matrix_keymap_data e2_matrix_keymap_data = {
+        .keymap                 = e2_key_map,
+        .keymap_size            = ARRAY_SIZE(e2_key_map),
+};
 static struct pxa27x_keypad_platform_data e2_keypad_platform_data = {
        .matrix_key_rows = 5,
        .matrix_key_cols = 6,
-        .matrix_key_map = e2_key_map,
+        .matrix_keymap_data = &e2_matrix_keymap_data,
-        .matrix_key_map_size = ARRAY_SIZE(e2_key_map),
        .debounce_interval = 30,
 };
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h
index fd7ea39b78c0..8963984d1f43 100644
--- a/arch/arm/mach-pxa/generic.h
+++ b/arch/arm/mach-pxa/generic.h
@@ -9,6 +9,8 @@
 * published by the Free Software Foundation.
 */
+#include <linux/reboot.h>
 struct irq_data;
 extern void pxa_timer_init(void);
@@ -56,4 +58,4 @@ void __init pxa_set_btuart_info(void *info);
 void __init pxa_set_stuart_info(void *info);
 void __init pxa_set_hwuart_info(void *info);
-void pxa_restart(char, const char *);
+void pxa_restart(enum reboot_mode, const char *);
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
index e848c4607baf..5d665588c7eb 100644
--- a/arch/arm/mach-pxa/littleton.c
+++ b/arch/arm/mach-pxa/littleton.c
@@ -222,7 +222,7 @@ static inline void littleton_init_spi(void) {}
 #endif
 #if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
-static unsigned int littleton_matrix_key_map[] = {
+static const unsigned int littleton_matrix_key_map[] = {
        /* KEY(row, col, key_code) */
        KEY(1, 3, KEY_0), KEY(0, 0, KEY_1), KEY(1, 0, KEY_2), KEY(2, 0, KEY_3),
        KEY(0, 1, KEY_4), KEY(1, 1, KEY_5), KEY(2, 1, KEY_6), KEY(0, 2, KEY_7),
@@ -249,11 +249,15 @@ static unsigned int littleton_matrix_key_map[] = {
        KEY(3, 1, KEY_F23),     /* soft2 */
 };
+static struct matrix_keymap_data littleton_matrix_keymap_data = {
+        .keymap                 = littleton_matrix_key_map,
+        .keymap_size            = ARRAY_SIZE(littleton_matrix_key_map),
+};
 static struct pxa27x_keypad_platform_data littleton_keypad_info = {
        .matrix_key_rows        = 6,
        .matrix_key_cols        = 5,
-        .matrix_key_map         = littleton_matrix_key_map,
+        .matrix_keymap_data     = &littleton_matrix_keymap_data,
-        .matrix_key_map_size    = ARRAY_SIZE(littleton_matrix_key_map),
        .enable_rotary0         = 1,
        .rotary0_up_key         = KEY_UP,
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 7a12c1ba90ff..dd70343c8708 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -408,7 +408,7 @@ static int mainstone_mci_init(struct device *dev, irq_handler_t mstone_detect_in
        return err;
 }
-static void mainstone_mci_setpower(struct device *dev, unsigned int vdd)
+static int mainstone_mci_setpower(struct device *dev, unsigned int vdd)
 {
        struct pxamci_platform_data* p_d = dev->platform_data;
@@ -420,6 +420,7 @@ static void mainstone_mci_setpower(struct device *dev, unsigned int vdd)
                printk(KERN_DEBUG "%s: off\n", __func__);
                MST_MSCWR1 &= ~MST_MSCWR1_MMC_ON;
        }
+        return 0;
 }
 static void mainstone_mci_exit(struct device *dev, void *data)
@@ -498,7 +499,7 @@ static struct pxaohci_platform_data mainstone_ohci_platform_data = {
 };
 #if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
-static unsigned int mainstone_matrix_keys[] = {
+static const unsigned int mainstone_matrix_keys[] = {
        KEY(0, 0, KEY_A), KEY(1, 0, KEY_B), KEY(2, 0, KEY_C),
        KEY(3, 0, KEY_D), KEY(4, 0, KEY_E), KEY(5, 0, KEY_F),
        KEY(0, 1, KEY_G), KEY(1, 1, KEY_H), KEY(2, 1, KEY_I),
@@ -527,11 +528,15 @@ static unsigned int mainstone_matrix_keys[] = {
        KEY(4, 6, KEY_SELECT),
 };
+static struct matrix_keymap_data mainstone_matrix_keymap_data = {
+        .keymap                 = mainstone_matrix_keys,
+        .keymap_size            = ARRAY_SIZE(mainstone_matrix_keys),
+};
 struct pxa27x_keypad_platform_data mainstone_keypad_info = {
        .matrix_key_rows        = 6,
        .matrix_key_cols        = 7,
-        .matrix_key_map         = mainstone_matrix_keys,
+        .matrix_keymap_data     = &mainstone_matrix_keymap_data,
-        .matrix_key_map_size    = ARRAY_SIZE(mainstone_matrix_keys),
        .enable_rotary0         = 1,
        .rotary0_up_key         = KEY_UP,
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index f8979b943cbf..acc9d3cc0762 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -37,6 +37,7 @@
 #include <linux/wm97xx.h>
 #include <linux/mtd/physmap.h>
 #include <linux/usb/gpio_vbus.h>
+#include <linux/reboot.h>
 #include <linux/regulator/max1586.h>
 #include <linux/slab.h>
 #include <linux/i2c/pxa-i2c.h>
@@ -222,7 +223,7 @@ static struct pxafb_mach_info mioa701_pxafb_info = {
 /*
 * Keyboard configuration
 */
-static unsigned int mioa701_matrix_keys[] = {
+static const unsigned int mioa701_matrix_keys[] = {
        KEY(0, 0, KEY_UP),
        KEY(0, 1, KEY_RIGHT),
        KEY(0, 2, KEY_MEDIA),
@@ -233,11 +234,16 @@ static unsigned int mioa701_matrix_keys[] = {
        KEY(2, 1, KEY_PHONE),   /* Phone Green key */
        KEY(2, 2, KEY_CAMERA)   /* Camera key */
 };
+static struct matrix_keymap_data mioa701_matrix_keymap_data = {
+        .keymap                 = mioa701_matrix_keys,
+        .keymap_size            = ARRAY_SIZE(mioa701_matrix_keys),
+};
 static struct pxa27x_keypad_platform_data mioa701_keypad_info = {
        .matrix_key_rows = 3,
        .matrix_key_cols = 3,
-        .matrix_key_map = mioa701_matrix_keys,
+        .matrix_keymap_data = &mioa701_matrix_keymap_data,
-        .matrix_key_map_size = ARRAY_SIZE(mioa701_matrix_keys),
 };
 /*
@@ -691,13 +697,13 @@ static void mioa701_machine_exit(void);
 static void mioa701_poweroff(void)
 {
        mioa701_machine_exit();
-        pxa_restart('s', NULL);
+        pxa_restart(REBOOT_SOFT, NULL);
 }
-static void mioa701_restart(char c, const char *cmd)
+static void mioa701_restart(enum reboot_mode c, const char *cmd)
 {
        mioa701_machine_exit();
-        pxa_restart('s', cmd);
+        pxa_restart(REBOOT_SOFT, cmd);
 }
 static struct gpio global_gpios[] = {
@@ -756,7 +762,6 @@ static void mioa701_machine_exit(void)
 MACHINE_START(MIOA701, "MIO A701")
        .atag_offset    = 0x100,
-        .restart_mode   = 's',
        .map_io         = &pxa27x_map_io,
        .nr_irqs        = PXA_NR_IRQS,
        .init_irq       = &pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c
index 909b713e5789..cf210b11ffcc 100644
--- a/arch/arm/mach-pxa/palmld.c
+++ b/arch/arm/mach-pxa/palmld.c
@@ -173,7 +173,7 @@ static inline void palmld_nor_init(void) {}
 * GPIO keyboard
 ******************************************************************************/
 #if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
-static unsigned int palmld_matrix_keys[] = {
+static const unsigned int palmld_matrix_keys[] = {
        KEY(0, 1, KEY_F2),
        KEY(0, 2, KEY_UP),
@@ -190,11 +190,15 @@ static unsigned int palmld_matrix_keys[] = {
        KEY(3, 2, KEY_LEFT),
 };
+static struct matrix_keymap_data palmld_matrix_keymap_data = {
+        .keymap                 = palmld_matrix_keys,
+        .keymap_size            = ARRAY_SIZE(palmld_matrix_keys),
+};
 static struct pxa27x_keypad_platform_data palmld_keypad_platform_data = {
        .matrix_key_rows        = 4,
        .matrix_key_cols        = 3,
-        .matrix_key_map         = palmld_matrix_keys,
+        .matrix_keymap_data     = &palmld_matrix_keymap_data,
-        .matrix_key_map_size    = ARRAY_SIZE(palmld_matrix_keys),
        .debounce_interval      = 30,
 };
diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c
index 5033fd07968f..3ed9b029428b 100644
--- a/arch/arm/mach-pxa/palmt5.c
+++ b/arch/arm/mach-pxa/palmt5.c
@@ -108,7 +108,7 @@ static unsigned long palmt5_pin_config[] __initdata = {
 * GPIO keyboard
 ******************************************************************************/
 #if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
-static unsigned int palmt5_matrix_keys[] = {
+static const unsigned int palmt5_matrix_keys[] = {
        KEY(0, 0, KEY_POWER),
        KEY(0, 1, KEY_F1),
        KEY(0, 2, KEY_ENTER),
@@ -124,11 +124,15 @@ static unsigned int palmt5_matrix_keys[] = {
        KEY(3, 2, KEY_LEFT),
 };
+static struct matrix_keymap_data palmt5_matrix_keymap_data = {
+        .keymap                 = palmt5_matrix_keys,
+        .keymap_size            = ARRAY_SIZE(palmt5_matrix_keys),
+};
 static struct pxa27x_keypad_platform_data palmt5_keypad_platform_data = {
        .matrix_key_rows        = 4,
        .matrix_key_cols        = 3,
-        .matrix_key_map         = palmt5_matrix_keys,
+        .matrix_keymap_data     = &palmt5_matrix_keymap_data,
-        .matrix_key_map_size    = ARRAY_SIZE(palmt5_matrix_keys),
        .debounce_interval      = 30,
 };
diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c
index d82a50b4a803..d8b937c870de 100644
--- a/arch/arm/mach-pxa/palmtreo.c
+++ b/arch/arm/mach-pxa/palmtreo.c
@@ -168,7 +168,7 @@ static unsigned long centro685_pin_config[] __initdata = {
 * GPIO keyboard
 ******************************************************************************/
 #if IS_ENABLED(CONFIG_KEYBOARD_PXA27x)
-static unsigned int treo680_matrix_keys[] = {
+static const unsigned int treo680_matrix_keys[] = {
        KEY(0, 0, KEY_F8),              /* Red/Off/Power */
        KEY(0, 1, KEY_LEFT),
        KEY(0, 2, KEY_LEFTCTRL),        /* Alternate */
@@ -227,7 +227,7 @@ static unsigned int treo680_matrix_keys[] = {
        KEY(7, 5, KEY_I),
 };
-static unsigned int centro_matrix_keys[] = {
+static const unsigned int centro_matrix_keys[] = {
        KEY(0, 0, KEY_F9),              /* Home */
        KEY(0, 1, KEY_LEFT),
        KEY(0, 2, KEY_LEFTCTRL),        /* Alternate */
@@ -286,11 +286,20 @@ static unsigned int centro_matrix_keys[] = {
        KEY(7, 5, KEY_I),
 };
+static struct matrix_keymap_data treo680_matrix_keymap_data = {
+        .keymap                 = treo680_matrix_keys,
+        .keymap_size            = ARRAY_SIZE(treo680_matrix_keys),
+};
+static struct matrix_keymap_data centro_matrix_keymap_data = {
+        .keymap                 = centro_matrix_keys,
+        .keymap_size            = ARRAY_SIZE(centro_matrix_keys),
+};
 static struct pxa27x_keypad_platform_data treo680_keypad_pdata = {
        .matrix_key_rows        = 8,
        .matrix_key_cols        = 7,
-        .matrix_key_map         = treo680_matrix_keys,
+        .matrix_keymap_data     = &treo680_matrix_keymap_data,
-        .matrix_key_map_size    = ARRAY_SIZE(treo680_matrix_keys),
        .direct_key_map         = { KEY_CONNECT },
        .direct_key_num         = 1,
@@ -301,10 +310,8 @@ static void __init palmtreo_kpc_init(void)
 {
        static struct pxa27x_keypad_platform_data *data = &treo680_keypad_pdata;
-        if (machine_is_centro()) {
+        if (machine_is_centro())
-                data->matrix_key_map = centro_matrix_keys;
+                data->matrix_keymap_data = &centro_matrix_keymap_data;
-                data->matrix_key_map_size = ARRAY_SIZE(centro_matrix_keys);
-        }
        pxa_set_keypad_info(&treo680_keypad_pdata);
 }
diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c
index 627c93a7364c..83f830dd8ad8 100644
--- a/arch/arm/mach-pxa/palmtx.c
+++ b/arch/arm/mach-pxa/palmtx.c
@@ -176,7 +176,7 @@ static inline void palmtx_nor_init(void) {}
 * GPIO keyboard
 ******************************************************************************/
 #if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
-static unsigned int palmtx_matrix_keys[] = {
+static const unsigned int palmtx_matrix_keys[] = {
        KEY(0, 0, KEY_POWER),
        KEY(0, 1, KEY_F1),
        KEY(0, 2, KEY_ENTER),
@@ -192,11 +192,15 @@ static unsigned int palmtx_matrix_keys[] = {
        KEY(3, 2, KEY_LEFT),
 };
+static struct matrix_keymap_data palmtx_matrix_keymap_data = {
+        .keymap                 = palmtx_matrix_keys,
+        .keymap_size            = ARRAY_SIZE(palmtx_matrix_keys),
+};
 static struct pxa27x_keypad_platform_data palmtx_keypad_platform_data = {
        .matrix_key_rows        = 4,
        .matrix_key_cols        = 3,
-        .matrix_key_map         = palmtx_matrix_keys,
+        .matrix_keymap_data     = &palmtx_matrix_keymap_data,
-        .matrix_key_map_size    = ARRAY_SIZE(palmtx_matrix_keys),
        .debounce_interval      = 30,
 };
diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c
index 18b7fcd98592..1a35ddf218da 100644
--- a/arch/arm/mach-pxa/palmz72.c
+++ b/arch/arm/mach-pxa/palmz72.c
@@ -140,7 +140,7 @@ static unsigned long palmz72_pin_config[] __initdata = {
 * GPIO keyboard
 ******************************************************************************/
 #if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
-static unsigned int palmz72_matrix_keys[] = {
+static const unsigned int palmz72_matrix_keys[] = {
        KEY(0, 0, KEY_POWER),
        KEY(0, 1, KEY_F1),
        KEY(0, 2, KEY_ENTER),
@@ -156,11 +156,15 @@ static unsigned int palmz72_matrix_keys[] = {
        KEY(3, 2, KEY_LEFT),
 };
+static struct matrix_keymap_data almz72_matrix_keymap_data = {
+        .keymap                 = palmz72_matrix_keys,
+        .keymap_size            = ARRAY_SIZE(palmz72_matrix_keys),
+};
 static struct pxa27x_keypad_platform_data palmz72_keypad_platform_data = {
        .matrix_key_rows        = 4,
        .matrix_key_cols        = 3,
-        .matrix_key_map         = palmz72_matrix_keys,
+        .matrix_keymap_data     = &almz72_matrix_keymap_data,
-        .matrix_key_map_size    = ARRAY_SIZE(palmz72_matrix_keys),
        .debounce_interval      = 30,
 };
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c
index fb7f1d1627dc..13e5b00eae90 100644
--- a/arch/arm/mach-pxa/pcm990-baseboard.c
+++ b/arch/arm/mach-pxa/pcm990-baseboard.c
@@ -335,7 +335,7 @@ static int pcm990_mci_init(struct device *dev, irq_handler_t mci_detect_int,
        return err;
 }
-static void pcm990_mci_setpower(struct device *dev, unsigned int vdd)
+static int pcm990_mci_setpower(struct device *dev, unsigned int vdd)
 {
        struct pxamci_platform_data *p_d = dev->platform_data;
        u8 val;
@@ -348,6 +348,7 @@ static void pcm990_mci_setpower(struct device *dev, unsigned int vdd)
                val &= ~PCM990_CTRL_MMC2PWR;
        pcm990_cpld_writeb(PCM990_CTRL_MMC2PWR, PCM990_CTRL_REG5);
+        return 0;
 }
 static void pcm990_mci_exit(struct device *dev, void *data)
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 50ccd5f1d560..aedf053a1de5 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -258,7 +258,7 @@ err_free_2:
        return err;
 }
-static void poodle_mci_setpower(struct device *dev, unsigned int vdd)
+static int poodle_mci_setpower(struct device *dev, unsigned int vdd)
 {
        struct pxamci_platform_data* p_d = dev->platform_data;
@@ -270,6 +270,8 @@ static void poodle_mci_setpower(struct device *dev, unsigned int vdd)
                gpio_set_value(POODLE_GPIO_SD_PWR1, 0);
                gpio_set_value(POODLE_GPIO_SD_PWR, 0);
        }
+        return 0;
 }
 static void poodle_mci_exit(struct device *dev, void *data)
@@ -422,7 +424,7 @@ static struct i2c_board_info __initdata poodle_i2c_devices[] = {
 static void poodle_poweroff(void)
 {
-        pxa_restart('h', NULL);
+        pxa_restart(REBOOT_HARD, NULL);
 }
 static void __init poodle_init(void)
diff --git a/arch/arm/mach-pxa/reset.c b/arch/arm/mach-pxa/reset.c
index 3fab583755d4..0d5dd646f61f 100644
--- a/arch/arm/mach-pxa/reset.c
+++ b/arch/arm/mach-pxa/reset.c
@@ -83,7 +83,7 @@ static void do_hw_reset(void)
        writel_relaxed(readl_relaxed(OSCR) + 368640, OSMR3);
 }
-void pxa_restart(char mode, const char *cmd)
+void pxa_restart(enum reboot_mode mode, const char *cmd)
 {
        local_irq_disable();
        local_fiq_disable();
@@ -91,14 +91,14 @@ void pxa_restart(char mode, const char *cmd)
        clear_reset_status(RESET_STATUS_ALL);
        switch (mode) {
-        case 's':
+        case REBOOT_SOFT:
                /* Jump into ROM at address 0 */
                soft_restart(0);
                break;
-        case 'g':
+        case REBOOT_GPIO:
                do_gpio_reset();
                break;
-        case 'h':
+        case REBOOT_HARD:
        default:
                do_hw_reset();
                break;
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 362726c49c70..4c29173026e8 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -31,6 +31,7 @@
 #include <linux/regulator/machine.h>
 #include <linux/io.h>
 #include <linux/module.h>
+#include <linux/reboot.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -597,7 +598,7 @@ static inline void spitz_spi_init(void) {}
 * NOTE: The card detect interrupt isn't debounced so we delay it by 250ms to
 * give the card a chance to fully insert/eject.
 */
-static void spitz_mci_setpower(struct device *dev, unsigned int vdd)
+static int spitz_mci_setpower(struct device *dev, unsigned int vdd)
 {
        struct pxamci_platform_data* p_d = dev->platform_data;
@@ -605,6 +606,8 @@ static void spitz_mci_setpower(struct device *dev, unsigned int vdd)
                spitz_card_pwr_ctrl(SCOOP_CPR_SD_3V, SCOOP_CPR_SD_3V);
        else
                spitz_card_pwr_ctrl(SCOOP_CPR_SD_3V, 0x0);
+        return 0;
 }
 static struct pxamci_platform_data spitz_mci_platform_data = {
@@ -924,10 +927,10 @@ static inline void spitz_i2c_init(void) {}
 ******************************************************************************/
 static void spitz_poweroff(void)
 {
-        pxa_restart('g', NULL);
+        pxa_restart(REBOOT_GPIO, NULL);
 }
-static void spitz_restart(char mode, const char *cmd)
+static void spitz_restart(enum reboot_mode mode, const char *cmd)
 {
        uint32_t msc0 = __raw_readl(MSC0);
        /* Bootloader magic for a reboot */
@@ -979,7 +982,6 @@ static void __init spitz_fixup(struct tag *tags, char **cmdline,
 #ifdef CONFIG_MACH_SPITZ
 MACHINE_START(SPITZ, "SHARP Spitz")
-        .restart_mode   = 'g',
        .fixup          = spitz_fixup,
        .map_io         = pxa27x_map_io,
        .nr_irqs        = PXA_NR_IRQS,
@@ -993,7 +995,6 @@ MACHINE_END
 #ifdef CONFIG_MACH_BORZOI
 MACHINE_START(BORZOI, "SHARP Borzoi")
-        .restart_mode   = 'g',
        .fixup          = spitz_fixup,
        .map_io         = pxa27x_map_io,
        .nr_irqs        = PXA_NR_IRQS,
@@ -1007,7 +1008,6 @@ MACHINE_END
 #ifdef CONFIG_MACH_AKITA
 MACHINE_START(AKITA, "SHARP Akita")
-        .restart_mode   = 'g',
        .fixup          = spitz_fixup,
        .map_io         = pxa27x_map_io,
        .nr_irqs        = PXA_NR_IRQS,
diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c
index 88fde43c948c..62aea3e835f3 100644
--- a/arch/arm/mach-pxa/stargate2.c
+++ b/arch/arm/mach-pxa/stargate2.c
@@ -734,9 +734,10 @@ static int stargate2_mci_init(struct device *dev,
 *
 * Very simple control. Either it is on or off and is controlled by
 * a gpio pin */
-static void stargate2_mci_setpower(struct device *dev, unsigned int vdd)
+static int stargate2_mci_setpower(struct device *dev, unsigned int vdd)
 {
        gpio_set_value(SG2_SD_POWER_ENABLE, !!vdd);
+        return 0;
 }
 static void stargate2_mci_exit(struct device *dev, void *data)
diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c
index f55979c09a5f..4680efe55345 100644
--- a/arch/arm/mach-pxa/tavorevb.c
+++ b/arch/arm/mach-pxa/tavorevb.c
@@ -106,7 +106,7 @@ static struct platform_device smc91x_device = {
 };
 #if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
-static unsigned int tavorevb_matrix_key_map[] = {
+static const unsigned int tavorevb_matrix_key_map[] = {
        /* KEY(row, col, key_code) */
        KEY(0, 4, KEY_A), KEY(0, 5, KEY_B), KEY(0, 6, KEY_C),
        KEY(1, 4, KEY_E), KEY(1, 5, KEY_F), KEY(1, 6, KEY_G),
@@ -147,11 +147,15 @@ static unsigned int tavorevb_matrix_key_map[] = {
        KEY(3, 3, KEY_F23),     /* soft2 */
 };
+static struct matrix_keymap_data tavorevb_matrix_keymap_data = {
+        .keymap         = tavorevb_matrix_key_map,
+        .keymap_size    = ARRAY_SIZE(tavorevb_matrix_key_map),
+};
 static struct pxa27x_keypad_platform_data tavorevb_keypad_info = {
        .matrix_key_rows        = 7,
        .matrix_key_cols        = 7,
-        .matrix_key_map         = tavorevb_matrix_key_map,
+        .matrix_keymap_data     = &tavorevb_matrix_keymap_data,
-        .matrix_key_map_size    = ARRAY_SIZE(tavorevb_matrix_key_map),
        .debounce_interval      = 30,
 };
diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c
index 8f1ee92aea30..9aa852a8fab9 100644
--- a/arch/arm/mach-pxa/time.c
+++ b/arch/arm/mach-pxa/time.c
@@ -16,11 +16,11 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/clockchips.h>
+#include <linux/sched_clock.h>
 #include <asm/div64.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
-#include <asm/sched_clock.h>
 #include <mach/regs-ost.h>
 #include <mach/irqs.h>
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index 3d91d2e5bf3a..0206b915a6f6 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -36,6 +36,7 @@
 #include <linux/input/matrix_keypad.h>
 #include <linux/i2c/pxa-i2c.h>
 #include <linux/usb/gpio_vbus.h>
+#include <linux/reboot.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -911,10 +912,10 @@ static struct platform_device *devices[] __initdata = {
 static void tosa_poweroff(void)
 {
-        pxa_restart('g', NULL);
+        pxa_restart(REBOOT_GPIO, NULL);
 }
-static void tosa_restart(char mode, const char *cmd)
+static void tosa_restart(enum reboot_mode mode, const char *cmd)
 {
        uint32_t msc0 = __raw_readl(MSC0);
@@ -969,7 +970,6 @@ static void __init fixup_tosa(struct tag *tags, char **cmdline,
 }
 MACHINE_START(TOSA, "SHARP Tosa")
-        .restart_mode   = 'g',
        .fixup          = fixup_tosa,
        .map_io         = pxa25x_map_io,
        .nr_irqs        = TOSA_NR_IRQS,
diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c
index 989903a7e467..2513d8f4931f 100644
--- a/arch/arm/mach-pxa/z2.c
+++ b/arch/arm/mach-pxa/z2.c
@@ -345,7 +345,7 @@ static inline void z2_leds_init(void) {}
 * GPIO keyboard
 ******************************************************************************/
 #if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
-static unsigned int z2_matrix_keys[] = {
+static const unsigned int z2_matrix_keys[] = {
        KEY(0, 0, KEY_OPTION),
        KEY(1, 0, KEY_UP),
        KEY(2, 0, KEY_DOWN),
@@ -405,11 +405,15 @@ static unsigned int z2_matrix_keys[] = {
        KEY(5, 7, KEY_DOT),
 };
+static struct matrix_keymap_data z2_matrix_keymap_data = {
+        .keymap                 = z2_matrix_keys,
+        .keymap_size            = ARRAY_SIZE(z2_matrix_keys),
+};
 static struct pxa27x_keypad_platform_data z2_keypad_platform_data = {
        .matrix_key_rows        = 7,
        .matrix_key_cols        = 8,
-        .matrix_key_map         = z2_matrix_keys,
+        .matrix_keymap_data     = &z2_matrix_keymap_data,
-        .matrix_key_map_size    = ARRAY_SIZE(z2_matrix_keys),
        .debounce_interval      = 30,
 };
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index 1f00d650ac27..36cf7cf95ec1 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -263,7 +263,7 @@ static inline void zylonite_init_mmc(void) {}
 #endif
 #if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
-static unsigned int zylonite_matrix_key_map[] = {
+static const unsigned int zylonite_matrix_key_map[] = {
        /* KEY(row, col, key_code) */
        KEY(0, 0, KEY_A), KEY(0, 1, KEY_B), KEY(0, 2, KEY_C), KEY(0, 5, KEY_D),
        KEY(1, 0, KEY_E), KEY(1, 1, KEY_F), KEY(1, 2, KEY_G), KEY(1, 5, KEY_H),
@@ -306,11 +306,15 @@ static unsigned int zylonite_matrix_key_map[] = {
        KEY(0, 3, KEY_AUX),     /* contact */
 };
+static struct matrix_keymap_data zylonite_matrix_keymap_data = {
+        .keymap                 = zylonite_matrix_key_map,
+        .keymap_size            = ARRAY_SIZE(zylonite_matrix_key_map),
+};
 static struct pxa27x_keypad_platform_data zylonite_keypad_info = {
        .matrix_key_rows        = 8,
        .matrix_key_cols        = 8,
-        .matrix_key_map         = zylonite_matrix_key_map,
+        .matrix_keymap_data     = &zylonite_matrix_keymap_data,
-        .matrix_key_map_size    = ARRAY_SIZE(zylonite_matrix_key_map),
        .enable_rotary0         = 1,
        .rotary0_up_key         = KEY_UP,
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 5b1c8bfe6fa9..c85ddb2a0ad0 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -29,6 +29,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
+#include <linux/reboot.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -418,7 +419,7 @@ static void __init realview_eb_timer_init(void)
        realview_eb_twd_init();
 }
-static void realview_eb_restart(char mode, const char *cmd)
+static void realview_eb_restart(enum reboot_mode mode, const char *cmd)
 {
        void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
        void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index d5e83a1f6982..c5eade76461b 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -31,6 +31,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
+#include <linux/reboot.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -329,7 +330,7 @@ static void __init realview_pb1176_timer_init(void)
        realview_timer_init(IRQ_DC1176_TIMER0);
 }
-static void realview_pb1176_restart(char mode, const char *cmd)
+static void realview_pb1176_restart(enum reboot_mode mode, const char *cmd)
 {
        void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
        void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index c3cfe213b5e6..f4b0962578fe 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -29,6 +29,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
+#include <linux/reboot.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -316,7 +317,7 @@ static void __init realview_pb11mp_timer_init(void)
        realview_pb11mp_twd_init();
 }
-static void realview_pb11mp_restart(char mode, const char *cmd)
+static void realview_pb11mp_restart(enum reboot_mode mode, const char *cmd)
 {
        void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
        void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index dde652a59620..10a3e1d76891 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -29,6 +29,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
+#include <linux/reboot.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
@@ -264,7 +265,7 @@ static void __init realview_pba8_timer_init(void)
        realview_timer_init(IRQ_PBA8_TIMER0_1);
 }
-static void realview_pba8_restart(char mode, const char *cmd)
+static void realview_pba8_restart(enum reboot_mode mode, const char *cmd)
 {
        void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
        void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index 54f0185b01e3..9d75493e3f0c 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -28,6 +28,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
+#include <linux/reboot.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
@@ -344,7 +345,7 @@ static void realview_pbx_fixup(struct tag *tags, char **from,
 #endif
 }
-static void realview_pbx_restart(char mode, const char *cmd)
+static void realview_pbx_restart(enum reboot_mode mode, const char *cmd)
 {
        void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
        void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
new file mode 100644
index 000000000000..25ee12b21f01
--- /dev/null
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -0,0 +1,16 @@
+config ARCH_ROCKCHIP
+        bool "Rockchip RK2928 and RK3xxx SOCs" if ARCH_MULTI_V7
+        select PINCTRL
+        select PINCTRL_ROCKCHIP
+        select ARCH_REQUIRE_GPIOLIB
+        select ARM_GIC
+        select CACHE_L2X0
+        select HAVE_ARM_TWD if LOCAL_TIMERS
+        select HAVE_SMP
+        select LOCAL_TIMERS if SMP
+        select COMMON_CLK
+        select GENERIC_CLOCKEVENTS
+        select DW_APB_TIMER_OF
+        help
+          Support for Rockchip's Cortex-A9 Single-to-Quad-Core-SoCs
+          containing the RK2928, RK30xx and RK31xx series.
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
new file mode 100644
index 000000000000..1547d4fc920a
--- /dev/null
+++ b/arch/arm/mach-rockchip/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip.o
diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c
new file mode 100644
index 000000000000..724d2d81f976
--- /dev/null
+++ b/arch/arm/mach-rockchip/rockchip.c
@@ -0,0 +1,52 @@
+/*
+ * Device Tree support for Rockchip SoCs
+ *
+ * Copyright (c) 2013 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of_platform.h>
+#include <linux/irqchip.h>
+#include <linux/dw_apb_timer.h>
+#include <linux/clk-provider.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/hardware/cache-l2x0.h>
+static void __init rockchip_timer_init(void)
+{
+        of_clk_init(NULL);
+        clocksource_of_init();
+}
+static void __init rockchip_dt_init(void)
+{
+        l2x0_of_init(0, ~0UL);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+static const char * const rockchip_board_dt_compat[] = {
+        "rockchip,rk2928",
+        "rockchip,rk3066a",
+        "rockchip,rk3066b",
+        "rockchip,rk3188",
+        NULL,
+};
+DT_MACHINE_START(ROCKCHIP_DT, "Rockchip Cortex-A9 (Device Tree)")
+        .init_machine   = rockchip_dt_init,
+        .init_time      = rockchip_timer_init,
+        .dt_compat      = rockchip_board_dt_compat,
+MACHINE_END
diff --git a/arch/arm/mach-rpc/riscpc.c b/arch/arm/mach-rpc/riscpc.c
index a302cf5e0fc7..09d602b10d57 100644
--- a/arch/arm/mach-rpc/riscpc.c
+++ b/arch/arm/mach-rpc/riscpc.c
@@ -20,6 +20,7 @@
 #include <linux/ata_platform.h>
 #include <linux/io.h>
 #include <linux/i2c.h>
+#include <linux/reboot.h>
 #include <asm/elf.h>
 #include <asm/mach-types.h>
@@ -201,7 +202,7 @@ static int __init rpc_init(void)
 arch_initcall(rpc_init);
-static void rpc_restart(char mode, const char *cmd)
+static void rpc_restart(enum reboot_mode mode, const char *cmd)
 {
        iomd_writeb(0, IOMD_ROMCR0);
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index f2f7088bfd22..7791ac76f945 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -28,9 +28,10 @@ config CPU_S3C2410
        select CPU_ARM920T
        select CPU_LLSERIAL_S3C2410
        select S3C2410_CLOCK
-        select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX
+        select ARM_S3C2410_CPUFREQ if ARM_S3C24XX_CPUFREQ
        select S3C2410_PM if PM
        select SAMSUNG_HRT
+        select SAMSUNG_WDT_RESET
        help
          Support for S3C2410 and S3C2410A family from the S3C24XX line
          of Samsung Mobile CPUs.
@@ -81,6 +82,7 @@ config CPU_S3C2442
 config CPU_S3C244X
        def_bool y
        depends on CPU_S3C2440 || CPU_S3C2442
+        select SAMSUNG_WDT_RESET
 config CPU_S3C2443
        bool "SAMSUNG S3C2443"
@@ -204,27 +206,38 @@ config S3C24XX_GPIO_EXTRA128
          Add an extra 128 gpio numbers to the available GPIO pool. This is
          available for boards that need extra gpios for external devices.
+config S3C24XX_PLL
+        bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
+        depends on ARM_S3C24XX_CPUFREQ
+        help
+          Compile in support for changing the PLL frequency from the
+          S3C24XX series CPUfreq driver. The PLL takes time to settle
+          after a frequency change, so by default it is not enabled.
+          This also means that the PLL tables for the selected CPU(s) will
+          be built which may increase the size of the kernel image.
 # cpu frequency items common between s3c2410 and s3c2440/s3c2442
 config S3C2410_IOTIMING
        bool
-        depends on CPU_FREQ_S3C24XX
+        depends on ARM_S3C24XX_CPUFREQ
        help
          Internal node to select io timing code that is common to the s3c2410
          and s3c2440/s3c2442 cpu frequency support.
 config S3C2410_CPUFREQ_UTILS
-        bool
+       bool
-        depends on CPU_FREQ_S3C24XX
+       depends on ARM_S3C24XX_CPUFREQ
-        help
+       help
-          Internal node to select timing code that is common to the s3c2410
+         Internal node to select timing code that is common to the s3c2410
-          and s3c2440/s3c244 cpu frequency support.
+         and s3c2440/s3c244 cpu frequency support.
 # cpu frequency support common to s3c2412, s3c2413 and s3c2442
 config S3C2412_IOTIMING
        bool
-        depends on CPU_FREQ_S3C24XX && (CPU_S3C2412 || CPU_S3C2443)
+        depends on ARM_S3C24XX_CPUFREQ && (CPU_S3C2412 || CPU_S3C2443)
        help
          Intel node to select io timing code that is common to the s3c2412
          and the s3c2443.
@@ -233,16 +246,9 @@ config S3C2412_IOTIMING
 if CPU_S3C2410
-config S3C2410_CPUFREQ
-        bool
-        depends on CPU_FREQ_S3C24XX
-        select S3C2410_CPUFREQ_UTILS
-        help
-          CPU Frequency scaling support for S3C2410
 config S3C2410_PLL
        bool
-        depends on S3C2410_CPUFREQ && CPU_FREQ_S3C24XX_PLL
+        depends on ARM_S3C2410_CPUFREQ && S3C24XX_PLL
        default y
        help
          Select the PLL table for the S3C2410
@@ -278,7 +284,7 @@ config ARCH_BAST
        bool "Simtec Electronics BAST (EB2410ITX)"
        select ISA
        select MACH_BAST_IDE
-        select S3C2410_IOTIMING if S3C2410_CPUFREQ
+        select S3C2410_IOTIMING if ARM_S3C2410_CPUFREQ
        select S3C24XX_DCLK
        select S3C24XX_SIMTEC_NOR
        select S3C24XX_SIMTEC_PM if PM
@@ -385,14 +391,6 @@ config CPU_S3C2412_ONLY
                   !CPU_S3C2442 && !CPU_S3C2443
        default y
-config S3C2412_CPUFREQ
-        bool
-        depends on CPU_FREQ_S3C24XX
-        default y
-        select S3C2412_IOTIMING
-        help
-          CPU Frequency scaling support for S3C2412 and S3C2413 SoC CPUs.
 config S3C2412_DMA
        bool
        help
@@ -490,18 +488,22 @@ config MACH_SMDK2416
        help
          Say Y here if you are using an SMDK2416
+config MACH_S3C2416_DT
+        bool "Samsung S3C2416 machine using devicetree"
+        select CLKSRC_OF
+        select USE_OF
+        select PINCTRL
+        select PINCTRL_S3C24XX
+        help
+          Machine support for Samsung S3C2416 machines with device tree enabled.
+          Select this if a fdt blob is available for the S3C2416 SoC based board.
+          Note: This is under development and not all peripherals can be supported
+          with this machine file.
 endif   # CPU_S3C2416
 if CPU_S3C2440
-config S3C2440_CPUFREQ
-        bool "S3C2440/S3C2442 CPU Frequency scaling support"
-        depends on CPU_FREQ_S3C24XX && (CPU_S3C2440 || CPU_S3C2442)
-        default y
-        select S3C2410_CPUFREQ_UTILS
-        help
-          CPU Frequency scaling support for S3C2440 and S3C2442 SoC CPUs.
 config S3C2440_DMA
        bool
        help
@@ -521,15 +523,15 @@ config S3C2440_XTAL_16934400
 config S3C2440_PLL_12000000
        bool
-        depends on S3C2440_CPUFREQ && S3C2440_XTAL_12000000
+        depends on ARM_S3C2440_CPUFREQ && S3C2440_XTAL_12000000
-        default y if CPU_FREQ_S3C24XX_PLL
+        default y if S3C24XX_PLL
        help
          PLL tables for S3C2440 or S3C2442 CPUs with 12MHz crystals.
 config S3C2440_PLL_16934400
        bool
-        depends on S3C2440_CPUFREQ && S3C2440_XTAL_16934400
+        depends on ARM_S3C2440_CPUFREQ && S3C2440_XTAL_16934400
-        default y if CPU_FREQ_S3C24XX_PLL
+        default y if S3C24XX_PLL
        help
          PLL tables for S3C2440 or S3C2442 CPUs with 16.934MHz crystals.
@@ -583,7 +585,7 @@ config MACH_NEXCODER_2440
 config MACH_OSIRIS
        bool "Simtec IM2440D20 (OSIRIS) module"
-        select S3C2410_IOTIMING if S3C2440_CPUFREQ
+        select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ
        select S3C2440_XTAL_12000000
        select S3C24XX_DCLK
        select S3C24XX_GPIO_EXTRA128
@@ -655,7 +657,7 @@ config MACH_RX1950
        bool "HP iPAQ rx1950"
        select I2C
        select PM_H1940 if PM
-        select S3C2410_IOTIMING if S3C2440_CPUFREQ
+        select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ
        select S3C2440_XTAL_16934400
        select S3C24XX_DCLK
        select S3C24XX_PWM
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index 6f46ecfc8396..7f54e5b954ca 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -17,13 +17,11 @@ obj-				:=
 obj-y                           += common.o
 obj-$(CONFIG_CPU_S3C2410)       += s3c2410.o
-obj-$(CONFIG_S3C2410_CPUFREQ)   += cpufreq-s3c2410.o
 obj-$(CONFIG_S3C2410_DMA)       += dma-s3c2410.o
 obj-$(CONFIG_S3C2410_PLL)       += pll-s3c2410.o
 obj-$(CONFIG_S3C2410_PM)        += pm-s3c2410.o sleep-s3c2410.o
 obj-$(CONFIG_CPU_S3C2412)       += s3c2412.o clock-s3c2412.o
-obj-$(CONFIG_S3C2412_CPUFREQ)   += cpufreq-s3c2412.o
 obj-$(CONFIG_S3C2412_DMA)       += dma-s3c2412.o
 obj-$(CONFIG_S3C2412_PM)        += pm-s3c2412.o
 obj-$(CONFIG_S3C2412_PM_SLEEP)  += sleep-s3c2412.o
@@ -34,7 +32,6 @@ obj-$(CONFIG_S3C2416_PM)	+= pm-s3c2416.o
 obj-$(CONFIG_CPU_S3C2440)       += s3c2440.o clock-s3c2440.o
 obj-$(CONFIG_CPU_S3C2442)       += s3c2442.o
 obj-$(CONFIG_CPU_S3C244X)       += s3c244x.o clock-s3c244x.o
-obj-$(CONFIG_S3C2440_CPUFREQ)   += cpufreq-s3c2440.o
 obj-$(CONFIG_S3C2440_DMA)       += dma-s3c2440.o
 obj-$(CONFIG_S3C2440_PLL_12000000) += pll-s3c2440-12000000.o
 obj-$(CONFIG_S3C2440_PLL_16934400) += pll-s3c2440-16934400.o
@@ -59,9 +56,6 @@ obj-$(CONFIG_S3C2412_IOTIMING)	+= iotiming-s3c2412.o
 obj-$(CONFIG_S3C2443_COMMON)    += common-s3c2443.o
 obj-$(CONFIG_S3C2443_DMA)       += dma-s3c2443.o
-obj-$(CONFIG_CPU_FREQ_S3C24XX)  += cpufreq.o
-obj-$(CONFIG_CPU_FREQ_S3C24XX_DEBUGFS) += cpufreq-debugfs.o
 #
 # machine support
 # following is ordered alphabetically by option text.
@@ -85,6 +79,7 @@ obj-$(CONFIG_MACH_SMDK2413)		+= mach-smdk2413.o
 obj-$(CONFIG_MACH_VSTMS)                += mach-vstms.o
 obj-$(CONFIG_MACH_SMDK2416)             += mach-smdk2416.o
+obj-$(CONFIG_MACH_S3C2416_DT)           += mach-s3c2416-dt.o
 obj-$(CONFIG_MACH_ANUBIS)               += mach-anubis.o
 obj-$(CONFIG_MACH_AT2440EVB)            += mach-at2440evb.o
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2410.c b/arch/arm/mach-s3c24xx/clock-s3c2410.c
index 34fffdf6fc1d..564553694b54 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2410.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2410.c
@@ -119,66 +119,101 @@ static struct clk init_clocks_off[] = {
        }
 };
-static struct clk init_clocks[] = {
+static struct clk clk_lcd = {
-        {
+        .name           = "lcd",
-                .name           = "lcd",
+        .parent         = &clk_h,
-                .parent         = &clk_h,
+        .enable         = s3c2410_clkcon_enable,
-                .enable         = s3c2410_clkcon_enable,
+        .ctrlbit        = S3C2410_CLKCON_LCDC,
-                .ctrlbit        = S3C2410_CLKCON_LCDC,
+};
-        }, {
-                .name           = "gpio",
+static struct clk clk_gpio = {
-                .parent         = &clk_p,
+        .name           = "gpio",
-                .enable         = s3c2410_clkcon_enable,
+        .parent         = &clk_p,
-                .ctrlbit        = S3C2410_CLKCON_GPIO,
+        .enable         = s3c2410_clkcon_enable,
-        }, {
+        .ctrlbit        = S3C2410_CLKCON_GPIO,
-                .name           = "usb-host",
+};
-                .parent         = &clk_h,
-                .enable         = s3c2410_clkcon_enable,
+static struct clk clk_usb_host = {
-                .ctrlbit        = S3C2410_CLKCON_USBH,
+        .name           = "usb-host",
-        }, {
+        .parent         = &clk_h,
-                .name           = "usb-device",
+        .enable         = s3c2410_clkcon_enable,
-                .parent         = &clk_h,
+        .ctrlbit        = S3C2410_CLKCON_USBH,
-                .enable         = s3c2410_clkcon_enable,
+};
-                .ctrlbit        = S3C2410_CLKCON_USBD,
-        }, {
+static struct clk clk_usb_device = {
-                .name           = "timers",
+        .name           = "usb-device",
-                .parent         = &clk_p,
+        .parent         = &clk_h,
-                .enable         = s3c2410_clkcon_enable,
+        .enable         = s3c2410_clkcon_enable,
-                .ctrlbit        = S3C2410_CLKCON_PWMT,
+        .ctrlbit        = S3C2410_CLKCON_USBD,
-        }, {
+};
-                .name           = "uart",
-                .devname        = "s3c2410-uart.0",
+static struct clk clk_timers = {
-                .parent         = &clk_p,
+        .name           = "timers",
-                .enable         = s3c2410_clkcon_enable,
+        .parent         = &clk_p,
-                .ctrlbit        = S3C2410_CLKCON_UART0,
+        .enable         = s3c2410_clkcon_enable,
-        }, {
+        .ctrlbit        = S3C2410_CLKCON_PWMT,
-                .name           = "uart",
+};
-                .devname        = "s3c2410-uart.1",
-                .parent         = &clk_p,
+struct clk s3c24xx_clk_uart0 = {
-                .enable         = s3c2410_clkcon_enable,
+        .name           = "uart",
-                .ctrlbit        = S3C2410_CLKCON_UART1,
+        .devname        = "s3c2410-uart.0",
-        }, {
+        .parent         = &clk_p,
-                .name           = "uart",
+        .enable         = s3c2410_clkcon_enable,
-                .devname        = "s3c2410-uart.2",
+        .ctrlbit        = S3C2410_CLKCON_UART0,
-                .parent         = &clk_p,
+};
-                .enable         = s3c2410_clkcon_enable,
-                .ctrlbit        = S3C2410_CLKCON_UART2,
+struct clk s3c24xx_clk_uart1 = {
-        }, {
+        .name           = "uart",
-                .name           = "rtc",
+        .devname        = "s3c2410-uart.1",
-                .parent         = &clk_p,
+        .parent         = &clk_p,
-                .enable         = s3c2410_clkcon_enable,
+        .enable         = s3c2410_clkcon_enable,
-                .ctrlbit        = S3C2410_CLKCON_RTC,
+        .ctrlbit        = S3C2410_CLKCON_UART1,
-        }, {
+};
-                .name           = "watchdog",
-                .parent         = &clk_p,
+struct clk s3c24xx_clk_uart2 = {
-                .ctrlbit        = 0,
+        .name           = "uart",
-        }, {
+        .devname        = "s3c2410-uart.2",
-                .name           = "usb-bus-host",
+        .parent         = &clk_p,
-                .parent         = &clk_usb_bus,
+        .enable         = s3c2410_clkcon_enable,
-        }, {
+        .ctrlbit        = S3C2410_CLKCON_UART2,
-                .name           = "usb-bus-gadget",
+};
-                .parent         = &clk_usb_bus,
-        },
+static struct clk clk_rtc = {
+        .name           = "rtc",
+        .parent         = &clk_p,
+        .enable         = s3c2410_clkcon_enable,
+        .ctrlbit        = S3C2410_CLKCON_RTC,
+};
+static struct clk clk_watchdog = {
+        .name           = "watchdog",
+        .parent         = &clk_p,
+        .ctrlbit        = 0,
+};
+static struct clk clk_usb_bus_host = {
+        .name           = "usb-bus-host",
+        .parent         = &clk_usb_bus,
+};
+static struct clk clk_usb_bus_gadget = {
+        .name           = "usb-bus-gadget",
+        .parent         = &clk_usb_bus,
+};
+static struct clk *init_clocks[] = {
+        &clk_lcd,
+        &clk_gpio,
+        &clk_usb_host,
+        &clk_usb_device,
+        &clk_timers,
+        &s3c24xx_clk_uart0,
+        &s3c24xx_clk_uart1,
+        &s3c24xx_clk_uart2,
+        &clk_rtc,
+        &clk_watchdog,
+        &clk_usb_bus_host,
+        &clk_usb_bus_gadget,
 };
 /* s3c2410_baseclk_add()
@@ -195,7 +230,6 @@ int __init s3c2410_baseclk_add(void)
 {
        unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
        unsigned long clkcon  = __raw_readl(S3C2410_CLKCON);
-        struct clk *clkp;
        struct clk *xtal;
        int ret;
        int ptr;
@@ -207,8 +241,9 @@ int __init s3c2410_baseclk_add(void)
        /* register clocks from clock array */
-        clkp = init_clocks;
+        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++) {
-        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
+                struct clk *clkp = init_clocks[ptr];
                /* ensure that we note the clock state */
                clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2440.c b/arch/arm/mach-s3c24xx/clock-s3c2440.c
index 1069b5680826..aaf006d1d6dc 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2440.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2440.c
@@ -166,6 +166,9 @@ static struct clk_lookup s3c2440_clk_lookup[] = {
        CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
        CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
        CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n),
+        CLKDEV_INIT("s3c2440-uart.0", "uart", &s3c24xx_clk_uart0),
+        CLKDEV_INIT("s3c2440-uart.1", "uart", &s3c24xx_clk_uart1),
+        CLKDEV_INIT("s3c2440-uart.2", "uart", &s3c24xx_clk_uart2),
        CLKDEV_INIT("s3c2440-camif", "camera", &s3c2440_clk_cam_upll),
 };
diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h
index 307c3714be55..84b280654f4c 100644
--- a/arch/arm/mach-s3c24xx/common.h
+++ b/arch/arm/mach-s3c24xx/common.h
@@ -12,6 +12,8 @@
 #ifndef __ARCH_ARM_MACH_S3C24XX_COMMON_H
 #define __ARCH_ARM_MACH_S3C24XX_COMMON_H __FILE__
+#include <linux/reboot.h>
 struct s3c2410_uartcfg;
 #ifdef CONFIG_CPU_S3C2410
@@ -20,7 +22,7 @@ extern  int s3c2410a_init(void);
 extern void s3c2410_map_io(void);
 extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c2410_init_clocks(int xtal);
-extern void s3c2410_restart(char mode, const char *cmd);
+extern void s3c2410_restart(enum reboot_mode mode, const char *cmd);
 extern void s3c2410_init_irq(void);
 #else
 #define s3c2410_init_clocks NULL
@@ -36,7 +38,7 @@ extern void s3c2412_map_io(void);
 extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c2412_init_clocks(int xtal);
 extern  int s3c2412_baseclk_add(void);
-extern void s3c2412_restart(char mode, const char *cmd);
+extern void s3c2412_restart(enum reboot_mode mode, const char *cmd);
 extern void s3c2412_init_irq(void);
 #else
 #define s3c2412_init_clocks NULL
@@ -51,7 +53,7 @@ extern void s3c2416_map_io(void);
 extern void s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c2416_init_clocks(int xtal);
 extern  int s3c2416_baseclk_add(void);
-extern void s3c2416_restart(char mode, const char *cmd);
+extern void s3c2416_restart(enum reboot_mode mode, const char *cmd);
 extern void s3c2416_init_irq(void);
 extern struct syscore_ops s3c2416_irq_syscore_ops;
@@ -66,7 +68,7 @@ extern struct syscore_ops s3c2416_irq_syscore_ops;
 extern void s3c244x_map_io(void);
 extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c244x_init_clocks(int xtal);
-extern void s3c244x_restart(char mode, const char *cmd);
+extern void s3c244x_restart(enum reboot_mode mode, const char *cmd);
 #else
 #define s3c244x_init_clocks NULL
 #define s3c244x_init_uarts NULL
@@ -96,7 +98,7 @@ extern void s3c2443_map_io(void);
 extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c2443_init_clocks(int xtal);
 extern  int s3c2443_baseclk_add(void);
-extern void s3c2443_restart(char mode, const char *cmd);
+extern void s3c2443_restart(enum reboot_mode mode, const char *cmd);
 extern void s3c2443_init_irq(void);
 #else
 #define s3c2443_init_clocks NULL
diff --git a/arch/arm/mach-s3c24xx/cpufreq-debugfs.c b/arch/arm/mach-s3c24xx/cpufreq-debugfs.c
deleted file mode 100644
index 9b7b4289d66c..000000000000
--- a/arch/arm/mach-s3c24xx/cpufreq-debugfs.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
- * Copyright (c) 2009 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C24XX CPU Frequency scaling - debugfs status support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/init.h>
-#include <linux/export.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/cpufreq.h>
-#include <linux/debugfs.h>
-#include <linux/seq_file.h>
-#include <linux/err.h>
-#include <plat/cpu-freq-core.h>
-static struct dentry *dbgfs_root;
-static struct dentry *dbgfs_file_io;
-static struct dentry *dbgfs_file_info;
-static struct dentry *dbgfs_file_board;
-#define print_ns(x) ((x) / 10), ((x) % 10)
-static void show_max(struct seq_file *seq, struct s3c_freq *f)
-{
-        seq_printf(seq, "MAX: F=%lu, H=%lu, P=%lu, A=%lu\n",
-                   f->fclk, f->hclk, f->pclk, f->armclk);
-}
-static int board_show(struct seq_file *seq, void *p)
-{
-        struct s3c_cpufreq_config *cfg;
-        struct s3c_cpufreq_board *brd;
-        cfg = s3c_cpufreq_getconfig();
-        if (!cfg) {
-                seq_printf(seq, "no configuration registered\n");
-                return 0;
-        }
-        brd = cfg->board;
-        if (!brd) {
-                seq_printf(seq, "no board definition set?\n");
-                return 0;
-        }
-        seq_printf(seq, "SDRAM refresh %u ns\n", brd->refresh);
-        seq_printf(seq, "auto_io=%u\n", brd->auto_io);
-        seq_printf(seq, "need_io=%u\n", brd->need_io);
-        show_max(seq, &brd->max);
-        return 0;
-}
-static int fops_board_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, board_show, NULL);
-}
-static const struct file_operations fops_board = {
-        .open           = fops_board_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-        .owner          = THIS_MODULE,
-};
-static int info_show(struct seq_file *seq, void *p)
-{
-        struct s3c_cpufreq_config *cfg;
-        cfg = s3c_cpufreq_getconfig();
-        if (!cfg) {
-                seq_printf(seq, "no configuration registered\n");
-                return 0;
-        }
-        seq_printf(seq, "  FCLK %ld Hz\n", cfg->freq.fclk);
-        seq_printf(seq, "  HCLK %ld Hz (%lu.%lu ns)\n",
-                   cfg->freq.hclk, print_ns(cfg->freq.hclk_tns));
-        seq_printf(seq, "  PCLK %ld Hz\n", cfg->freq.hclk);
-        seq_printf(seq, "ARMCLK %ld Hz\n", cfg->freq.armclk);
-        seq_printf(seq, "\n");
-        show_max(seq, &cfg->max);
-        seq_printf(seq, "Divisors: P=%d, H=%d, A=%d, dvs=%s\n",
-                   cfg->divs.h_divisor, cfg->divs.p_divisor,
-                   cfg->divs.arm_divisor, cfg->divs.dvs ? "on" : "off");
-        seq_printf(seq, "\n");
-        seq_printf(seq, "lock_pll=%u\n", cfg->lock_pll);
-        return 0;
-}
-static int fops_info_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, info_show, NULL);
-}
-static const struct file_operations fops_info = {
-        .open           = fops_info_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-        .owner          = THIS_MODULE,
-};
-static int io_show(struct seq_file *seq, void *p)
-{
-        void (*show_bank)(struct seq_file *, struct s3c_cpufreq_config *, union s3c_iobank *);
-        struct s3c_cpufreq_config *cfg;
-        struct s3c_iotimings *iot;
-        union s3c_iobank *iob;
-        int bank;
-        cfg = s3c_cpufreq_getconfig();
-        if (!cfg) {
-                seq_printf(seq, "no configuration registered\n");
-                return 0;
-        }
-        show_bank = cfg->info->debug_io_show;
-        if (!show_bank) {
-                seq_printf(seq, "no code to show bank timing\n");
-                return 0;
-        }
-        iot = s3c_cpufreq_getiotimings();
-        if (!iot) {
-                seq_printf(seq, "no io timings registered\n");
-                return 0;
-        }
-        seq_printf(seq, "hclk period is %lu.%lu ns\n", print_ns(cfg->freq.hclk_tns));
-        for (bank = 0; bank < MAX_BANKS; bank++) {
-                iob = &iot->bank[bank];
-                seq_printf(seq, "bank %d: ", bank);
-                if (!iob->io_2410) {
-                        seq_printf(seq, "nothing set\n");
-                        continue;
-                }
-                show_bank(seq, cfg, iob);
-        }
-        return 0;
-}
-static int fops_io_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, io_show, NULL);
-}
-static const struct file_operations fops_io = {
-        .open           = fops_io_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-        .owner          = THIS_MODULE,
-};
-static int __init s3c_freq_debugfs_init(void)
-{
-        dbgfs_root = debugfs_create_dir("s3c-cpufreq", NULL);
-        if (IS_ERR(dbgfs_root)) {
-                printk(KERN_ERR "%s: error creating debugfs root\n", __func__);
-                return PTR_ERR(dbgfs_root);
-        }
-        dbgfs_file_io = debugfs_create_file("io-timing", S_IRUGO, dbgfs_root,
-                                            NULL, &fops_io);
-        dbgfs_file_info = debugfs_create_file("info", S_IRUGO, dbgfs_root,
-                                              NULL, &fops_info);
-        dbgfs_file_board = debugfs_create_file("board", S_IRUGO, dbgfs_root,
-                                               NULL, &fops_board);
-        return 0;
-}
-late_initcall(s3c_freq_debugfs_init);
diff --git a/arch/arm/mach-s3c24xx/cpufreq-s3c2410.c b/arch/arm/mach-s3c24xx/cpufreq-s3c2410.c
deleted file mode 100644
index cfa0dd8723ec..000000000000
--- a/arch/arm/mach-s3c24xx/cpufreq-s3c2410.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * Copyright (c) 2006-2008 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 CPU Frequency scaling
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/cpufreq.h>
-#include <linux/device.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <mach/regs-clock.h>
-#include <plat/cpu.h>
-#include <plat/clock.h>
-#include <plat/cpu-freq-core.h>
-/* Note, 2410A has an extra mode for 1:4:4 ratio, bit 2 of CLKDIV */
-static void s3c2410_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
-{
-        u32 clkdiv = 0;
-        if (cfg->divs.h_divisor == 2)
-                clkdiv |= S3C2410_CLKDIVN_HDIVN;
-        if (cfg->divs.p_divisor != cfg->divs.h_divisor)
-                clkdiv |= S3C2410_CLKDIVN_PDIVN;
-        __raw_writel(clkdiv, S3C2410_CLKDIVN);
-}
-static int s3c2410_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
-{
-        unsigned long hclk, fclk, pclk;
-        unsigned int hdiv, pdiv;
-        unsigned long hclk_max;
-        fclk = cfg->freq.fclk;
-        hclk_max = cfg->max.hclk;
-        cfg->freq.armclk = fclk;
-        s3c_freq_dbg("%s: fclk is %lu, max hclk %lu\n",
-                      __func__, fclk, hclk_max);
-        hdiv = (fclk > cfg->max.hclk) ? 2 : 1;
-        hclk = fclk / hdiv;
-        if (hclk > cfg->max.hclk) {
-                s3c_freq_dbg("%s: hclk too big\n", __func__);
-                return -EINVAL;
-        }
-        pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
-        pclk = hclk / pdiv;
-        if (pclk > cfg->max.pclk) {
-                s3c_freq_dbg("%s: pclk too big\n", __func__);
-                return -EINVAL;
-        }
-        pdiv *= hdiv;
-        /* record the result */
-        cfg->divs.p_divisor = pdiv;
-        cfg->divs.h_divisor = hdiv;
-        return 0;
-}
-static struct s3c_cpufreq_info s3c2410_cpufreq_info = {
-        .max            = {
-                .fclk   = 200000000,
-                .hclk   = 100000000,
-                .pclk   =  50000000,
-        },
-        /* transition latency is about 5ms worst-case, so
-         * set 10ms to be sure */
-        .latency        = 10000000,
-        .locktime_m     = 150,
-        .locktime_u     = 150,
-        .locktime_bits  = 12,
-        .need_pll       = 1,
-        .name           = "s3c2410",
-        .calc_iotiming  = s3c2410_iotiming_calc,
-        .set_iotiming   = s3c2410_iotiming_set,
-        .get_iotiming   = s3c2410_iotiming_get,
-        .resume_clocks  = s3c2410_setup_clocks,
-        .set_fvco       = s3c2410_set_fvco,
-        .set_refresh    = s3c2410_cpufreq_setrefresh,
-        .set_divs       = s3c2410_cpufreq_setdivs,
-        .calc_divs      = s3c2410_cpufreq_calcdivs,
-        .debug_io_show  = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),
-};
-static int s3c2410_cpufreq_add(struct device *dev,
-                               struct subsys_interface *sif)
-{
-        return s3c_cpufreq_register(&s3c2410_cpufreq_info);
-}
-static struct subsys_interface s3c2410_cpufreq_interface = {
-        .name           = "s3c2410_cpufreq",
-        .subsys         = &s3c2410_subsys,
-        .add_dev        = s3c2410_cpufreq_add,
-};
-static int __init s3c2410_cpufreq_init(void)
-{
-        return subsys_interface_register(&s3c2410_cpufreq_interface);
-}
-arch_initcall(s3c2410_cpufreq_init);
-static int s3c2410a_cpufreq_add(struct device *dev,
-                                struct subsys_interface *sif)
-{
-        /* alter the maximum freq settings for S3C2410A. If a board knows
-         * it only has a maximum of 200, then it should register its own
-         * limits. */
-        s3c2410_cpufreq_info.max.fclk = 266000000;
-        s3c2410_cpufreq_info.max.hclk = 133000000;
-        s3c2410_cpufreq_info.max.pclk =  66500000;
-        s3c2410_cpufreq_info.name = "s3c2410a";
-        return s3c2410_cpufreq_add(dev, sif);
-}
-static struct subsys_interface s3c2410a_cpufreq_interface = {
-        .name           = "s3c2410a_cpufreq",
-        .subsys         = &s3c2410a_subsys,
-        .add_dev        = s3c2410a_cpufreq_add,
-};
-static int __init s3c2410a_cpufreq_init(void)
-{
-        return subsys_interface_register(&s3c2410a_cpufreq_interface);
-}
-arch_initcall(s3c2410a_cpufreq_init);
diff --git a/arch/arm/mach-s3c24xx/cpufreq-s3c2412.c b/arch/arm/mach-s3c24xx/cpufreq-s3c2412.c
deleted file mode 100644
index 8bf0f3a77476..000000000000
--- a/arch/arm/mach-s3c24xx/cpufreq-s3c2412.c
+++ /dev/null
@@ -1,258 +0,0 @@
-/*
- * Copyright 2008 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2412 CPU Frequency scalling
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/cpufreq.h>
-#include <linux/device.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <mach/regs-clock.h>
-#include <plat/cpu.h>
-#include <plat/clock.h>
-#include <plat/cpu-freq-core.h>
-#include "s3c2412.h"
-/* our clock resources. */
-static struct clk *xtal;
-static struct clk *fclk;
-static struct clk *hclk;
-static struct clk *armclk;
-/* HDIV: 1, 2, 3, 4, 6, 8 */
-static int s3c2412_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
-{
-        unsigned int hdiv, pdiv, armdiv, dvs;
-        unsigned long hclk, fclk, armclk, armdiv_clk;
-        unsigned long hclk_max;
-        fclk = cfg->freq.fclk;
-        armclk = cfg->freq.armclk;
-        hclk_max = cfg->max.hclk;
-        /* We can't run hclk above armclk as at the best we have to
-         * have armclk and hclk in dvs mode. */
-        if (hclk_max > armclk)
-                hclk_max = armclk;
-        s3c_freq_dbg("%s: fclk=%lu, armclk=%lu, hclk_max=%lu\n",
-                     __func__, fclk, armclk, hclk_max);
-        s3c_freq_dbg("%s: want f=%lu, arm=%lu, h=%lu, p=%lu\n",
-                     __func__, cfg->freq.fclk, cfg->freq.armclk,
-                     cfg->freq.hclk, cfg->freq.pclk);
-        armdiv = fclk / armclk;
-        if (armdiv < 1)
-                armdiv = 1;
-        if (armdiv > 2)
-                armdiv = 2;
-        cfg->divs.arm_divisor = armdiv;
-        armdiv_clk = fclk / armdiv;
-        hdiv = armdiv_clk / hclk_max;
-        if (hdiv < 1)
-                hdiv = 1;
-        cfg->freq.hclk = hclk = armdiv_clk / hdiv;
-        /* set dvs depending on whether we reached armclk or not. */
-        cfg->divs.dvs = dvs = armclk < armdiv_clk;
-        /* update the actual armclk we achieved. */
-        cfg->freq.armclk = dvs ? hclk : armdiv_clk;
-        s3c_freq_dbg("%s: armclk %lu, hclk %lu, armdiv %d, hdiv %d, dvs %d\n",
-                     __func__, armclk, hclk, armdiv, hdiv, cfg->divs.dvs);
-        if (hdiv > 4)
-                goto invalid;
-        pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
-        if ((hclk / pdiv) > cfg->max.pclk)
-                pdiv++;
-        cfg->freq.pclk = hclk / pdiv;
-        s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv);
-        if (pdiv > 2)
-                goto invalid;
-        pdiv *= hdiv;
-        /* store the result, and then return */
-        cfg->divs.h_divisor = hdiv * armdiv;
-        cfg->divs.p_divisor = pdiv * armdiv;
-        return 0;
-invalid:
-        return -EINVAL;
-}
-static void s3c2412_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
-{
-        unsigned long clkdiv;
-        unsigned long olddiv;
-        olddiv = clkdiv = __raw_readl(S3C2410_CLKDIVN);
-        /* clear off current clock info */
-        clkdiv &= ~S3C2412_CLKDIVN_ARMDIVN;
-        clkdiv &= ~S3C2412_CLKDIVN_HDIVN_MASK;
-        clkdiv &= ~S3C2412_CLKDIVN_PDIVN;
-        if (cfg->divs.arm_divisor == 2)
-                clkdiv |= S3C2412_CLKDIVN_ARMDIVN;
-        clkdiv |= ((cfg->divs.h_divisor / cfg->divs.arm_divisor) - 1);
-        if (cfg->divs.p_divisor != cfg->divs.h_divisor)
-                clkdiv |= S3C2412_CLKDIVN_PDIVN;
-        s3c_freq_dbg("%s: div %08lx => %08lx\n", __func__, olddiv, clkdiv);
-        __raw_writel(clkdiv, S3C2410_CLKDIVN);
-        clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk);
-}
-static void s3c2412_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
-{
-        struct s3c_cpufreq_board *board = cfg->board;
-        unsigned long refresh;
-        s3c_freq_dbg("%s: refresh %u ns, hclk %lu\n", __func__,
-                     board->refresh, cfg->freq.hclk);
-        /* Reduce both the refresh time (in ns) and the frequency (in MHz)
-         * by 10 each to ensure that we do not overflow 32 bit numbers. This
-         * should work for HCLK up to 133MHz and refresh period up to 30usec.
-         */
-        refresh = (board->refresh / 10);
-        refresh *= (cfg->freq.hclk / 100);
-        refresh /= (1 * 1000 * 1000);   /* 10^6 */
-        s3c_freq_dbg("%s: setting refresh 0x%08lx\n", __func__, refresh);
-        __raw_writel(refresh, S3C2412_REFRESH);
-}
-/* set the default cpu frequency information, based on an 200MHz part
- * as we have no other way of detecting the speed rating in software.
- */
-static struct s3c_cpufreq_info s3c2412_cpufreq_info = {
-        .max            = {
-                .fclk   = 200000000,
-                .hclk   = 100000000,
-                .pclk   =  50000000,
-        },
-        .latency        = 5000000, /* 5ms */
-        .locktime_m     = 150,
-        .locktime_u     = 150,
-        .locktime_bits  = 16,
-        .name           = "s3c2412",
-        .set_refresh    = s3c2412_cpufreq_setrefresh,
-        .set_divs       = s3c2412_cpufreq_setdivs,
-        .calc_divs      = s3c2412_cpufreq_calcdivs,
-        .calc_iotiming  = s3c2412_iotiming_calc,
-        .set_iotiming   = s3c2412_iotiming_set,
-        .get_iotiming   = s3c2412_iotiming_get,
-        .resume_clocks  = s3c2412_setup_clocks,
-        .debug_io_show  = s3c_cpufreq_debugfs_call(s3c2412_iotiming_debugfs),
-};
-static int s3c2412_cpufreq_add(struct device *dev,
-                               struct subsys_interface *sif)
-{
-        unsigned long fclk_rate;
-        hclk = clk_get(NULL, "hclk");
-        if (IS_ERR(hclk)) {
-                printk(KERN_ERR "%s: cannot find hclk clock\n", __func__);
-                return -ENOENT;
-        }
-        fclk = clk_get(NULL, "fclk");
-        if (IS_ERR(fclk)) {
-                printk(KERN_ERR "%s: cannot find fclk clock\n", __func__);
-                goto err_fclk;
-        }
-        fclk_rate = clk_get_rate(fclk);
-        if (fclk_rate > 200000000) {
-                printk(KERN_INFO
-                       "%s: fclk %ld MHz, assuming 266MHz capable part\n",
-                       __func__, fclk_rate / 1000000);
-                s3c2412_cpufreq_info.max.fclk = 266000000;
-                s3c2412_cpufreq_info.max.hclk = 133000000;
-                s3c2412_cpufreq_info.max.pclk =  66000000;
-        }
-        armclk = clk_get(NULL, "armclk");
-        if (IS_ERR(armclk)) {
-                printk(KERN_ERR "%s: cannot find arm clock\n", __func__);
-                goto err_armclk;
-        }
-        xtal = clk_get(NULL, "xtal");
-        if (IS_ERR(xtal)) {
-                printk(KERN_ERR "%s: cannot find xtal clock\n", __func__);
-                goto err_xtal;
-        }
-        return s3c_cpufreq_register(&s3c2412_cpufreq_info);
-err_xtal:
-        clk_put(armclk);
-err_armclk:
-        clk_put(fclk);
-err_fclk:
-        clk_put(hclk);
-        return -ENOENT;
-}
-static struct subsys_interface s3c2412_cpufreq_interface = {
-        .name           = "s3c2412_cpufreq",
-        .subsys         = &s3c2412_subsys,
-        .add_dev        = s3c2412_cpufreq_add,
-};
-static int s3c2412_cpufreq_init(void)
-{
-        return subsys_interface_register(&s3c2412_cpufreq_interface);
-}
-arch_initcall(s3c2412_cpufreq_init);
diff --git a/arch/arm/mach-s3c24xx/cpufreq-s3c2440.c b/arch/arm/mach-s3c24xx/cpufreq-s3c2440.c
deleted file mode 100644
index 72b2cc8a5a85..000000000000
--- a/arch/arm/mach-s3c24xx/cpufreq-s3c2440.c
+++ /dev/null
@@ -1,312 +0,0 @@
-/*
- * Copyright (c) 2006-2009 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *      Vincent Sanders <vince@simtec.co.uk>
- *
- * S3C2440/S3C2442 CPU Frequency scaling
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/cpufreq.h>
-#include <linux/device.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <mach/regs-clock.h>
-#include <plat/cpu.h>
-#include <plat/cpu-freq-core.h>
-#include <plat/clock.h>
-static struct clk *xtal;
-static struct clk *fclk;
-static struct clk *hclk;
-static struct clk *armclk;
-/* HDIV: 1, 2, 3, 4, 6, 8 */
-static inline int within_khz(unsigned long a, unsigned long b)
-{
-        long diff = a - b;
-        return (diff >= -1000 && diff <= 1000);
-}
-/**
- * s3c2440_cpufreq_calcdivs - calculate divider settings
- * @cfg: The cpu frequency settings.
- *
- * Calcualte the divider values for the given frequency settings
- * specified in @cfg. The values are stored in @cfg for later use
- * by the relevant set routine if the request settings can be reached.
- */
-int s3c2440_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
-{
-        unsigned int hdiv, pdiv;
-        unsigned long hclk, fclk, armclk;
-        unsigned long hclk_max;
-        fclk = cfg->freq.fclk;
-        armclk = cfg->freq.armclk;
-        hclk_max = cfg->max.hclk;
-        s3c_freq_dbg("%s: fclk is %lu, armclk %lu, max hclk %lu\n",
-                     __func__, fclk, armclk, hclk_max);
-        if (armclk > fclk) {
-                printk(KERN_WARNING "%s: armclk > fclk\n", __func__);
-                armclk = fclk;
-        }
-        /* if we are in DVS, we need HCLK to be <= ARMCLK */
-        if (armclk < fclk && armclk < hclk_max)
-                hclk_max = armclk;
-        for (hdiv = 1; hdiv < 9; hdiv++) {
-                if (hdiv == 5 || hdiv == 7)
-                        hdiv++;
-                hclk = (fclk / hdiv);
-                if (hclk <= hclk_max || within_khz(hclk, hclk_max))
-                        break;
-        }
-        s3c_freq_dbg("%s: hclk %lu, div %d\n", __func__, hclk, hdiv);
-        if (hdiv > 8)
-                goto invalid;
-        pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
-        if ((hclk / pdiv) > cfg->max.pclk)
-                pdiv++;
-        s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv);
-        if (pdiv > 2)
-                goto invalid;
-        pdiv *= hdiv;
-        /* calculate a valid armclk */
-        if (armclk < hclk)
-                armclk = hclk;
-        /* if we're running armclk lower than fclk, this really means
-         * that the system should go into dvs mode, which means that
-         * armclk is connected to hclk. */
-        if (armclk < fclk) {
-                cfg->divs.dvs = 1;
-                armclk = hclk;
-        } else
-                cfg->divs.dvs = 0;
-        cfg->freq.armclk = armclk;
-        /* store the result, and then return */
-        cfg->divs.h_divisor = hdiv;
-        cfg->divs.p_divisor = pdiv;
-        return 0;
- invalid:
-        return -EINVAL;
-}
-#define CAMDIVN_HCLK_HALF (S3C2440_CAMDIVN_HCLK3_HALF | \
-                           S3C2440_CAMDIVN_HCLK4_HALF)
-/**
- * s3c2440_cpufreq_setdivs - set the cpu frequency divider settings
- * @cfg: The cpu frequency settings.
- *
- * Set the divisors from the settings in @cfg, which where generated
- * during the calculation phase by s3c2440_cpufreq_calcdivs().
- */
-static void s3c2440_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
-{
-        unsigned long clkdiv, camdiv;
-        s3c_freq_dbg("%s: divsiors: h=%d, p=%d\n", __func__,
-                     cfg->divs.h_divisor, cfg->divs.p_divisor);
-        clkdiv = __raw_readl(S3C2410_CLKDIVN);
-        camdiv = __raw_readl(S3C2440_CAMDIVN);
-        clkdiv &= ~(S3C2440_CLKDIVN_HDIVN_MASK | S3C2440_CLKDIVN_PDIVN);
-        camdiv &= ~CAMDIVN_HCLK_HALF;
-        switch (cfg->divs.h_divisor) {
-        case 1:
-                clkdiv |= S3C2440_CLKDIVN_HDIVN_1;
-                break;
-        case 2:
-                clkdiv |= S3C2440_CLKDIVN_HDIVN_2;
-                break;
-        case 6:
-                camdiv |= S3C2440_CAMDIVN_HCLK3_HALF;
-        case 3:
-                clkdiv |= S3C2440_CLKDIVN_HDIVN_3_6;
-                break;
-        case 8:
-                camdiv |= S3C2440_CAMDIVN_HCLK4_HALF;
-        case 4:
-                clkdiv |= S3C2440_CLKDIVN_HDIVN_4_8;
-                break;
-        default:
-                BUG();  /* we don't expect to get here. */
-        }
-        if (cfg->divs.p_divisor != cfg->divs.h_divisor)
-                clkdiv |= S3C2440_CLKDIVN_PDIVN;
-        /* todo - set pclk. */
-        /* Write the divisors first with hclk intentionally halved so that
-         * when we write clkdiv we will under-frequency instead of over. We
-         * then make a short delay and remove the hclk halving if necessary.
-         */
-        __raw_writel(camdiv | CAMDIVN_HCLK_HALF, S3C2440_CAMDIVN);
-        __raw_writel(clkdiv, S3C2410_CLKDIVN);
-        ndelay(20);
-        __raw_writel(camdiv, S3C2440_CAMDIVN);
-        clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk);
-}
-static int run_freq_for(unsigned long max_hclk, unsigned long fclk,
-                        int *divs,
-                        struct cpufreq_frequency_table *table,
-                        size_t table_size)
-{
-        unsigned long freq;
-        int index = 0;
-        int div;
-        for (div = *divs; div > 0; div = *divs++) {
-                freq = fclk / div;
-                if (freq > max_hclk && div != 1)
-                        continue;
-                freq /= 1000; /* table is in kHz */
-                index = s3c_cpufreq_addfreq(table, index, table_size, freq);
-                if (index < 0)
-                        break;
-        }
-        return index;
-}
-static int hclk_divs[] = { 1, 2, 3, 4, 6, 8, -1 };
-static int s3c2440_cpufreq_calctable(struct s3c_cpufreq_config *cfg,
-                                     struct cpufreq_frequency_table *table,
-                                     size_t table_size)
-{
-        int ret;
-        WARN_ON(cfg->info == NULL);
-        WARN_ON(cfg->board == NULL);
-        ret = run_freq_for(cfg->info->max.hclk,
-                           cfg->info->max.fclk,
-                           hclk_divs,
-                           table, table_size);
-        s3c_freq_dbg("%s: returning %d\n", __func__, ret);
-        return ret;
-}
-struct s3c_cpufreq_info s3c2440_cpufreq_info = {
-        .max            = {
-                .fclk   = 400000000,
-                .hclk   = 133333333,
-                .pclk   =  66666666,
-        },
-        .locktime_m     = 300,
-        .locktime_u     = 300,
-        .locktime_bits  = 16,
-        .name           = "s3c244x",
-        .calc_iotiming  = s3c2410_iotiming_calc,
-        .set_iotiming   = s3c2410_iotiming_set,
-        .get_iotiming   = s3c2410_iotiming_get,
-        .set_fvco       = s3c2410_set_fvco,
-        .set_refresh    = s3c2410_cpufreq_setrefresh,
-        .set_divs       = s3c2440_cpufreq_setdivs,
-        .calc_divs      = s3c2440_cpufreq_calcdivs,
-        .calc_freqtable = s3c2440_cpufreq_calctable,
-        .resume_clocks  = s3c244x_setup_clocks,
-        .debug_io_show  = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),
-};
-static int s3c2440_cpufreq_add(struct device *dev,
-                               struct subsys_interface *sif)
-{
-        xtal = s3c_cpufreq_clk_get(NULL, "xtal");
-        hclk = s3c_cpufreq_clk_get(NULL, "hclk");
-        fclk = s3c_cpufreq_clk_get(NULL, "fclk");
-        armclk = s3c_cpufreq_clk_get(NULL, "armclk");
-        if (IS_ERR(xtal) || IS_ERR(hclk) || IS_ERR(fclk) || IS_ERR(armclk)) {
-                printk(KERN_ERR "%s: failed to get clocks\n", __func__);
-                return -ENOENT;
-        }
-        return s3c_cpufreq_register(&s3c2440_cpufreq_info);
-}
-static struct subsys_interface s3c2440_cpufreq_interface = {
-        .name           = "s3c2440_cpufreq",
-        .subsys         = &s3c2440_subsys,
-        .add_dev        = s3c2440_cpufreq_add,
-};
-static int s3c2440_cpufreq_init(void)
-{
-        return subsys_interface_register(&s3c2440_cpufreq_interface);
-}
-/* arch_initcall adds the clocks we need, so use subsys_initcall. */
-subsys_initcall(s3c2440_cpufreq_init);
-static struct subsys_interface s3c2442_cpufreq_interface = {
-        .name           = "s3c2442_cpufreq",
-        .subsys         = &s3c2442_subsys,
-        .add_dev        = s3c2440_cpufreq_add,
-};
-static int s3c2442_cpufreq_init(void)
-{
-        return subsys_interface_register(&s3c2442_cpufreq_interface);
-}
-subsys_initcall(s3c2442_cpufreq_init);
diff --git a/arch/arm/mach-s3c24xx/cpufreq-utils.c b/arch/arm/mach-s3c24xx/cpufreq-utils.c
index ddd8280e3875..2a0aa5684e72 100644
--- a/arch/arm/mach-s3c24xx/cpufreq-utils.c
+++ b/arch/arm/mach-s3c24xx/cpufreq-utils.c
@@ -60,5 +60,5 @@ void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
 */
 void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg)
 {
-        __raw_writel(cfg->pll.index, S3C2410_MPLLCON);
+        __raw_writel(cfg->pll.driver_data, S3C2410_MPLLCON);
 }
diff --git a/arch/arm/mach-s3c24xx/cpufreq.c b/arch/arm/mach-s3c24xx/cpufreq.c
deleted file mode 100644
index 3c0e78ede0da..000000000000
--- a/arch/arm/mach-s3c24xx/cpufreq.c
+++ /dev/null
@@ -1,711 +0,0 @@
-/*
- * Copyright (c) 2006-2008 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C24XX CPU Frequency scaling
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/cpufreq.h>
-#include <linux/cpu.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/device.h>
-#include <linux/sysfs.h>
-#include <linux/slab.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <plat/cpu.h>
-#include <plat/clock.h>
-#include <plat/cpu-freq-core.h>
-#include <mach/regs-clock.h>
-/* note, cpufreq support deals in kHz, no Hz */
-static struct cpufreq_driver s3c24xx_driver;
-static struct s3c_cpufreq_config cpu_cur;
-static struct s3c_iotimings s3c24xx_iotiming;
-static struct cpufreq_frequency_table *pll_reg;
-static unsigned int last_target = ~0;
-static unsigned int ftab_size;
-static struct cpufreq_frequency_table *ftab;
-static struct clk *_clk_mpll;
-static struct clk *_clk_xtal;
-static struct clk *clk_fclk;
-static struct clk *clk_hclk;
-static struct clk *clk_pclk;
-static struct clk *clk_arm;
-#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUGFS
-struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void)
-{
-        return &cpu_cur;
-}
-struct s3c_iotimings *s3c_cpufreq_getiotimings(void)
-{
-        return &s3c24xx_iotiming;
-}
-#endif /* CONFIG_CPU_FREQ_S3C24XX_DEBUGFS */
-static void s3c_cpufreq_getcur(struct s3c_cpufreq_config *cfg)
-{
-        unsigned long fclk, pclk, hclk, armclk;
-        cfg->freq.fclk = fclk = clk_get_rate(clk_fclk);
-        cfg->freq.hclk = hclk = clk_get_rate(clk_hclk);
-        cfg->freq.pclk = pclk = clk_get_rate(clk_pclk);
-        cfg->freq.armclk = armclk = clk_get_rate(clk_arm);
-        cfg->pll.index = __raw_readl(S3C2410_MPLLCON);
-        cfg->pll.frequency = fclk;
-        cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10);
-        cfg->divs.h_divisor = fclk / hclk;
-        cfg->divs.p_divisor = fclk / pclk;
-}
-static inline void s3c_cpufreq_calc(struct s3c_cpufreq_config *cfg)
-{
-        unsigned long pll = cfg->pll.frequency;
-        cfg->freq.fclk = pll;
-        cfg->freq.hclk = pll / cfg->divs.h_divisor;
-        cfg->freq.pclk = pll / cfg->divs.p_divisor;
-        /* convert hclk into 10ths of nanoseconds for io calcs */
-        cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10);
-}
-static inline int closer(unsigned int target, unsigned int n, unsigned int c)
-{
-        int diff_cur = abs(target - c);
-        int diff_new = abs(target - n);
-        return (diff_new < diff_cur);
-}
-static void s3c_cpufreq_show(const char *pfx,
-                                 struct s3c_cpufreq_config *cfg)
-{
-        s3c_freq_dbg("%s: Fvco=%u, F=%lu, A=%lu, H=%lu (%u), P=%lu (%u)\n",
-                     pfx, cfg->pll.frequency, cfg->freq.fclk, cfg->freq.armclk,
-                     cfg->freq.hclk, cfg->divs.h_divisor,
-                     cfg->freq.pclk, cfg->divs.p_divisor);
-}
-/* functions to wrapper the driver info calls to do the cpu specific work */
-static void s3c_cpufreq_setio(struct s3c_cpufreq_config *cfg)
-{
-        if (cfg->info->set_iotiming)
-                (cfg->info->set_iotiming)(cfg, &s3c24xx_iotiming);
-}
-static int s3c_cpufreq_calcio(struct s3c_cpufreq_config *cfg)
-{
-        if (cfg->info->calc_iotiming)
-                return (cfg->info->calc_iotiming)(cfg, &s3c24xx_iotiming);
-        return 0;
-}
-static void s3c_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
-{
-        (cfg->info->set_refresh)(cfg);
-}
-static void s3c_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
-{
-        (cfg->info->set_divs)(cfg);
-}
-static int s3c_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
-{
-        return (cfg->info->calc_divs)(cfg);
-}
-static void s3c_cpufreq_setfvco(struct s3c_cpufreq_config *cfg)
-{
-        (cfg->info->set_fvco)(cfg);
-}
-static inline void s3c_cpufreq_resume_clocks(void)
-{
-        cpu_cur.info->resume_clocks();
-}
-static inline void s3c_cpufreq_updateclk(struct clk *clk,
-                                         unsigned int freq)
-{
-        clk_set_rate(clk, freq);
-}
-static int s3c_cpufreq_settarget(struct cpufreq_policy *policy,
-                                 unsigned int target_freq,
-                                 struct cpufreq_frequency_table *pll)
-{
-        struct s3c_cpufreq_freqs freqs;
-        struct s3c_cpufreq_config cpu_new;
-        unsigned long flags;
-        cpu_new = cpu_cur;  /* copy new from current */
-        s3c_cpufreq_show("cur", &cpu_cur);
-        /* TODO - check for DMA currently outstanding */
-        cpu_new.pll = pll ? *pll : cpu_cur.pll;
-        if (pll)
-                freqs.pll_changing = 1;
-        /* update our frequencies */
-        cpu_new.freq.armclk = target_freq;
-        cpu_new.freq.fclk = cpu_new.pll.frequency;
-        if (s3c_cpufreq_calcdivs(&cpu_new) < 0) {
-                printk(KERN_ERR "no divisors for %d\n", target_freq);
-                goto err_notpossible;
-        }
-        s3c_freq_dbg("%s: got divs\n", __func__);
-        s3c_cpufreq_calc(&cpu_new);
-        s3c_freq_dbg("%s: calculated frequencies for new\n", __func__);
-        if (cpu_new.freq.hclk != cpu_cur.freq.hclk) {
-                if (s3c_cpufreq_calcio(&cpu_new) < 0) {
-                        printk(KERN_ERR "%s: no IO timings\n", __func__);
-                        goto err_notpossible;
-                }
-        }
-        s3c_cpufreq_show("new", &cpu_new);
-        /* setup our cpufreq parameters */
-        freqs.old = cpu_cur.freq;
-        freqs.new = cpu_new.freq;
-        freqs.freqs.old = cpu_cur.freq.armclk / 1000;
-        freqs.freqs.new = cpu_new.freq.armclk / 1000;
-        /* update f/h/p clock settings before we issue the change
-         * notification, so that drivers do not need to do anything
-         * special if they want to recalculate on CPUFREQ_PRECHANGE. */
-        s3c_cpufreq_updateclk(_clk_mpll, cpu_new.pll.frequency);
-        s3c_cpufreq_updateclk(clk_fclk, cpu_new.freq.fclk);
-        s3c_cpufreq_updateclk(clk_hclk, cpu_new.freq.hclk);
-        s3c_cpufreq_updateclk(clk_pclk, cpu_new.freq.pclk);
-        /* start the frequency change */
-        cpufreq_notify_transition(policy, &freqs.freqs, CPUFREQ_PRECHANGE);
-        /* If hclk is staying the same, then we do not need to
-         * re-write the IO or the refresh timings whilst we are changing
-         * speed. */
-        local_irq_save(flags);
-        /* is our memory clock slowing down? */
-        if (cpu_new.freq.hclk < cpu_cur.freq.hclk) {
-                s3c_cpufreq_setrefresh(&cpu_new);
-                s3c_cpufreq_setio(&cpu_new);
-        }
-        if (cpu_new.freq.fclk == cpu_cur.freq.fclk) {
-                /* not changing PLL, just set the divisors */
-                s3c_cpufreq_setdivs(&cpu_new);
-        } else {
-                if (cpu_new.freq.fclk < cpu_cur.freq.fclk) {
-                        /* slow the cpu down, then set divisors */
-                        s3c_cpufreq_setfvco(&cpu_new);
-                        s3c_cpufreq_setdivs(&cpu_new);
-                } else {
-                        /* set the divisors, then speed up */
-                        s3c_cpufreq_setdivs(&cpu_new);
-                        s3c_cpufreq_setfvco(&cpu_new);
-                }
-        }
-        /* did our memory clock speed up */
-        if (cpu_new.freq.hclk > cpu_cur.freq.hclk) {
-                s3c_cpufreq_setrefresh(&cpu_new);
-                s3c_cpufreq_setio(&cpu_new);
-        }
-        /* update our current settings */
-        cpu_cur = cpu_new;
-        local_irq_restore(flags);
-        /* notify everyone we've done this */
-        cpufreq_notify_transition(policy, &freqs.freqs, CPUFREQ_POSTCHANGE);
-        s3c_freq_dbg("%s: finished\n", __func__);
-        return 0;
- err_notpossible:
-        printk(KERN_ERR "no compatible settings for %d\n", target_freq);
-        return -EINVAL;
-}
-/* s3c_cpufreq_target
- *
- * called by the cpufreq core to adjust the frequency that the CPU
- * is currently running at.
- */
-static int s3c_cpufreq_target(struct cpufreq_policy *policy,
-                              unsigned int target_freq,
-                              unsigned int relation)
-{
-        struct cpufreq_frequency_table *pll;
-        unsigned int index;
-        /* avoid repeated calls which cause a needless amout of duplicated
-         * logging output (and CPU time as the calculation process is
-         * done) */
-        if (target_freq == last_target)
-                return 0;
-        last_target = target_freq;
-        s3c_freq_dbg("%s: policy %p, target %u, relation %u\n",
-                     __func__, policy, target_freq, relation);
-        if (ftab) {
-                if (cpufreq_frequency_table_target(policy, ftab,
-                                                   target_freq, relation,
-                                                   &index)) {
-                        s3c_freq_dbg("%s: table failed\n", __func__);
-                        return -EINVAL;
-                }
-                s3c_freq_dbg("%s: adjust %d to entry %d (%u)\n", __func__,
-                             target_freq, index, ftab[index].frequency);
-                target_freq = ftab[index].frequency;
-        }
-        target_freq *= 1000;  /* convert target to Hz */
-        /* find the settings for our new frequency */
-        if (!pll_reg || cpu_cur.lock_pll) {
-                /* either we've not got any PLL values, or we've locked
-                 * to the current one. */
-                pll = NULL;
-        } else {
-                struct cpufreq_policy tmp_policy;
-                int ret;
-                /* we keep the cpu pll table in Hz, to ensure we get an
-                 * accurate value for the PLL output. */
-                tmp_policy.min = policy->min * 1000;
-                tmp_policy.max = policy->max * 1000;
-                tmp_policy.cpu = policy->cpu;
-                /* cpufreq_frequency_table_target uses a pointer to 'index'
-                 * which is the number of the table entry, not the value of
-                 * the table entry's index field. */
-                ret = cpufreq_frequency_table_target(&tmp_policy, pll_reg,
-                                                     target_freq, relation,
-                                                     &index);
-                if (ret < 0) {
-                        printk(KERN_ERR "%s: no PLL available\n", __func__);
-                        goto err_notpossible;
-                }
-                pll = pll_reg + index;
-                s3c_freq_dbg("%s: target %u => %u\n",
-                             __func__, target_freq, pll->frequency);
-                target_freq = pll->frequency;
-        }
-        return s3c_cpufreq_settarget(policy, target_freq, pll);
- err_notpossible:
-        printk(KERN_ERR "no compatible settings for %d\n", target_freq);
-        return -EINVAL;
-}
-static unsigned int s3c_cpufreq_get(unsigned int cpu)
-{
-        return clk_get_rate(clk_arm) / 1000;
-}
-struct clk *s3c_cpufreq_clk_get(struct device *dev, const char *name)
-{
-        struct clk *clk;
-        clk = clk_get(dev, name);
-        if (IS_ERR(clk))
-                printk(KERN_ERR "cpufreq: failed to get clock '%s'\n", name);
-        return clk;
-}
-static int s3c_cpufreq_init(struct cpufreq_policy *policy)
-{
-        printk(KERN_INFO "%s: initialising policy %p\n", __func__, policy);
-        if (policy->cpu != 0)
-                return -EINVAL;
-        policy->cur = s3c_cpufreq_get(0);
-        policy->min = policy->cpuinfo.min_freq = 0;
-        policy->max = policy->cpuinfo.max_freq = cpu_cur.info->max.fclk / 1000;
-        policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
-        /* feed the latency information from the cpu driver */
-        policy->cpuinfo.transition_latency = cpu_cur.info->latency;
-        if (ftab)
-                cpufreq_frequency_table_cpuinfo(policy, ftab);
-        return 0;
-}
-static __init int s3c_cpufreq_initclks(void)
-{
-        _clk_mpll = s3c_cpufreq_clk_get(NULL, "mpll");
-        _clk_xtal = s3c_cpufreq_clk_get(NULL, "xtal");
-        clk_fclk = s3c_cpufreq_clk_get(NULL, "fclk");
-        clk_hclk = s3c_cpufreq_clk_get(NULL, "hclk");
-        clk_pclk = s3c_cpufreq_clk_get(NULL, "pclk");
-        clk_arm = s3c_cpufreq_clk_get(NULL, "armclk");
-        if (IS_ERR(clk_fclk) || IS_ERR(clk_hclk) || IS_ERR(clk_pclk) ||
-            IS_ERR(_clk_mpll) || IS_ERR(clk_arm) || IS_ERR(_clk_xtal)) {
-                printk(KERN_ERR "%s: could not get clock(s)\n", __func__);
-                return -ENOENT;
-        }
-        printk(KERN_INFO "%s: clocks f=%lu,h=%lu,p=%lu,a=%lu\n", __func__,
-               clk_get_rate(clk_fclk) / 1000,
-               clk_get_rate(clk_hclk) / 1000,
-               clk_get_rate(clk_pclk) / 1000,
-               clk_get_rate(clk_arm) / 1000);
-        return 0;
-}
-static int s3c_cpufreq_verify(struct cpufreq_policy *policy)
-{
-        if (policy->cpu != 0)
-                return -EINVAL;
-        return 0;
-}
-#ifdef CONFIG_PM
-static struct cpufreq_frequency_table suspend_pll;
-static unsigned int suspend_freq;
-static int s3c_cpufreq_suspend(struct cpufreq_policy *policy)
-{
-        suspend_pll.frequency = clk_get_rate(_clk_mpll);
-        suspend_pll.index = __raw_readl(S3C2410_MPLLCON);
-        suspend_freq = s3c_cpufreq_get(0) * 1000;
-        return 0;
-}
-static int s3c_cpufreq_resume(struct cpufreq_policy *policy)
-{
-        int ret;
-        s3c_freq_dbg("%s: resuming with policy %p\n", __func__, policy);
-        last_target = ~0;       /* invalidate last_target setting */
-        /* first, find out what speed we resumed at. */
-        s3c_cpufreq_resume_clocks();
-        /* whilst we will be called later on, we try and re-set the
-         * cpu frequencies as soon as possible so that we do not end
-         * up resuming devices and then immediately having to re-set
-         * a number of settings once these devices have restarted.
-         *
-         * as a note, it is expected devices are not used until they
-         * have been un-suspended and at that time they should have
-         * used the updated clock settings.
-         */
-        ret = s3c_cpufreq_settarget(NULL, suspend_freq, &suspend_pll);
-        if (ret) {
-                printk(KERN_ERR "%s: failed to reset pll/freq\n", __func__);
-                return ret;
-        }
-        return 0;
-}
-#else
-#define s3c_cpufreq_resume NULL
-#define s3c_cpufreq_suspend NULL
-#endif
-static struct cpufreq_driver s3c24xx_driver = {
-        .flags          = CPUFREQ_STICKY,
-        .verify         = s3c_cpufreq_verify,
-        .target         = s3c_cpufreq_target,
-        .get            = s3c_cpufreq_get,
-        .init           = s3c_cpufreq_init,
-        .suspend        = s3c_cpufreq_suspend,
-        .resume         = s3c_cpufreq_resume,
-        .name           = "s3c24xx",
-};
-int __init s3c_cpufreq_register(struct s3c_cpufreq_info *info)
-{
-        if (!info || !info->name) {
-                printk(KERN_ERR "%s: failed to pass valid information\n",
-                       __func__);
-                return -EINVAL;
-        }
-        printk(KERN_INFO "S3C24XX CPU Frequency driver, %s cpu support\n",
-               info->name);
-        /* check our driver info has valid data */
-        BUG_ON(info->set_refresh == NULL);
-        BUG_ON(info->set_divs == NULL);
-        BUG_ON(info->calc_divs == NULL);
-        /* info->set_fvco is optional, depending on whether there
-         * is a need to set the clock code. */
-        cpu_cur.info = info;
-        /* Note, driver registering should probably update locktime */
-        return 0;
-}
-int __init s3c_cpufreq_setboard(struct s3c_cpufreq_board *board)
-{
-        struct s3c_cpufreq_board *ours;
-        if (!board) {
-                printk(KERN_INFO "%s: no board data\n", __func__);
-                return -EINVAL;
-        }
-        /* Copy the board information so that each board can make this
-         * initdata. */
-        ours = kzalloc(sizeof(struct s3c_cpufreq_board), GFP_KERNEL);
-        if (ours == NULL) {
-                printk(KERN_ERR "%s: no memory\n", __func__);
-                return -ENOMEM;
-        }
-        *ours = *board;
-        cpu_cur.board = ours;
-        return 0;
-}
-int __init s3c_cpufreq_auto_io(void)
-{
-        int ret;
-        if (!cpu_cur.info->get_iotiming) {
-                printk(KERN_ERR "%s: get_iotiming undefined\n", __func__);
-                return -ENOENT;
-        }
-        printk(KERN_INFO "%s: working out IO settings\n", __func__);
-        ret = (cpu_cur.info->get_iotiming)(&cpu_cur, &s3c24xx_iotiming);
-        if (ret)
-                printk(KERN_ERR "%s: failed to get timings\n", __func__);
-        return ret;
-}
-/* if one or is zero, then return the other, otherwise return the min */
-#define do_min(_a, _b) ((_a) == 0 ? (_b) : (_b) == 0 ? (_a) : min(_a, _b))
-/**
- * s3c_cpufreq_freq_min - find the minimum settings for the given freq.
- * @dst: The destination structure
- * @a: One argument.
- * @b: The other argument.
- *
- * Create a minimum of each frequency entry in the 'struct s3c_freq',
- * unless the entry is zero when it is ignored and the non-zero argument
- * used.
- */
-static void s3c_cpufreq_freq_min(struct s3c_freq *dst,
-                                 struct s3c_freq *a, struct s3c_freq *b)
-{
-        dst->fclk = do_min(a->fclk, b->fclk);
-        dst->hclk = do_min(a->hclk, b->hclk);
-        dst->pclk = do_min(a->pclk, b->pclk);
-        dst->armclk = do_min(a->armclk, b->armclk);
-}
-static inline u32 calc_locktime(u32 freq, u32 time_us)
-{
-        u32 result;
-        result = freq * time_us;
-        result = DIV_ROUND_UP(result, 1000 * 1000);
-        return result;
-}
-static void s3c_cpufreq_update_loctkime(void)
-{
-        unsigned int bits = cpu_cur.info->locktime_bits;
-        u32 rate = (u32)clk_get_rate(_clk_xtal);
-        u32 val;
-        if (bits == 0) {
-                WARN_ON(1);
-                return;
-        }
-        val = calc_locktime(rate, cpu_cur.info->locktime_u) << bits;
-        val |= calc_locktime(rate, cpu_cur.info->locktime_m);
-        printk(KERN_INFO "%s: new locktime is 0x%08x\n", __func__, val);
-        __raw_writel(val, S3C2410_LOCKTIME);
-}
-static int s3c_cpufreq_build_freq(void)
-{
-        int size, ret;
-        if (!cpu_cur.info->calc_freqtable)
-                return -EINVAL;
-        kfree(ftab);
-        ftab = NULL;
-        size = cpu_cur.info->calc_freqtable(&cpu_cur, NULL, 0);
-        size++;
-        ftab = kmalloc(sizeof(struct cpufreq_frequency_table) * size, GFP_KERNEL);
-        if (!ftab) {
-                printk(KERN_ERR "%s: no memory for tables\n", __func__);
-                return -ENOMEM;
-        }
-        ftab_size = size;
-        ret = cpu_cur.info->calc_freqtable(&cpu_cur, ftab, size);
-        s3c_cpufreq_addfreq(ftab, ret, size, CPUFREQ_TABLE_END);
-        return 0;
-}
-static int __init s3c_cpufreq_initcall(void)
-{
-        int ret = 0;
-        if (cpu_cur.info && cpu_cur.board) {
-                ret = s3c_cpufreq_initclks();
-                if (ret)
-                        goto out;
-                /* get current settings */
-                s3c_cpufreq_getcur(&cpu_cur);
-                s3c_cpufreq_show("cur", &cpu_cur);
-                if (cpu_cur.board->auto_io) {
-                        ret = s3c_cpufreq_auto_io();
-                        if (ret) {
-                                printk(KERN_ERR "%s: failed to get io timing\n",
-                                       __func__);
-                                goto out;
-                        }
-                }
-                if (cpu_cur.board->need_io && !cpu_cur.info->set_iotiming) {
-                        printk(KERN_ERR "%s: no IO support registered\n",
-                               __func__);
-                        ret = -EINVAL;
-                        goto out;
-                }
-                if (!cpu_cur.info->need_pll)
-                        cpu_cur.lock_pll = 1;
-                s3c_cpufreq_update_loctkime();
-                s3c_cpufreq_freq_min(&cpu_cur.max, &cpu_cur.board->max,
-                                     &cpu_cur.info->max);
-                if (cpu_cur.info->calc_freqtable)
-                        s3c_cpufreq_build_freq();
-                ret = cpufreq_register_driver(&s3c24xx_driver);
-        }
- out:
-        return ret;
-}
-late_initcall(s3c_cpufreq_initcall);
-/**
- * s3c_plltab_register - register CPU PLL table.
- * @plls: The list of PLL entries.
- * @plls_no: The size of the PLL entries @plls.
- *
- * Register the given set of PLLs with the system.
- */
-int __init s3c_plltab_register(struct cpufreq_frequency_table *plls,
-                               unsigned int plls_no)
-{
-        struct cpufreq_frequency_table *vals;
-        unsigned int size;
-        size = sizeof(struct cpufreq_frequency_table) * (plls_no + 1);
-        vals = kmalloc(size, GFP_KERNEL);
-        if (vals) {
-                memcpy(vals, plls, size);
-                pll_reg = vals;
-                /* write a terminating entry, we don't store it in the
-                 * table that is stored in the kernel */
-                vals += plls_no;
-                vals->frequency = CPUFREQ_TABLE_END;
-                printk(KERN_INFO "cpufreq: %d PLL entries\n", plls_no);
-        } else
-                printk(KERN_ERR "cpufreq: no memory for PLL tables\n");
-        return vals ? 0 : -ENOMEM;
-}
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2412.c b/arch/arm/mach-s3c24xx/dma-s3c2412.c
index ab1700ec8e64..b7e094671522 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2412.c
@@ -35,121 +35,95 @@ static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = {
        [DMACH_XD0] = {
                .name           = "xdreq0",
                .channels       = MAP(S3C2412_DMAREQSEL_XDREQ0),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_XDREQ0),
        },
        [DMACH_XD1] = {
                .name           = "xdreq1",
                .channels       = MAP(S3C2412_DMAREQSEL_XDREQ1),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_XDREQ1),
        },
        [DMACH_SDI] = {
                .name           = "sdi",
                .channels       = MAP(S3C2412_DMAREQSEL_SDI),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_SDI),
        },
-        [DMACH_SPI0] = {
+        [DMACH_SPI0_RX] = {
-                .name           = "spi0",
+                .name           = "spi0-rx",
+                .channels       = MAP(S3C2412_DMAREQSEL_SPI0RX),
+        },
+        [DMACH_SPI0_TX] = {
+                .name           = "spi0-tx",
                .channels       = MAP(S3C2412_DMAREQSEL_SPI0TX),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_SPI0RX),
        },
-        [DMACH_SPI1] = {
+        [DMACH_SPI1_RX] = {
-                .name           = "spi1",
+                .name           = "spi1-rx",
+                .channels       = MAP(S3C2412_DMAREQSEL_SPI1RX),
+        },
+        [DMACH_SPI1_TX] = {
+                .name           = "spi1-tx",
                .channels       = MAP(S3C2412_DMAREQSEL_SPI1TX),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_SPI1RX),
        },
        [DMACH_UART0] = {
                .name           = "uart0",
                .channels       = MAP(S3C2412_DMAREQSEL_UART0_0),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_UART0_0),
        },
        [DMACH_UART1] = {
                .name           = "uart1",
                .channels       = MAP(S3C2412_DMAREQSEL_UART1_0),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_UART1_0),
        },
        [DMACH_UART2] = {
                .name           = "uart2",
                .channels       = MAP(S3C2412_DMAREQSEL_UART2_0),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_UART2_0),
        },
        [DMACH_UART0_SRC2] = {
                .name           = "uart0",
                .channels       = MAP(S3C2412_DMAREQSEL_UART0_1),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_UART0_1),
        },
        [DMACH_UART1_SRC2] = {
                .name           = "uart1",
                .channels       = MAP(S3C2412_DMAREQSEL_UART1_1),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_UART1_1),
        },
        [DMACH_UART2_SRC2] = {
                .name           = "uart2",
                .channels       = MAP(S3C2412_DMAREQSEL_UART2_1),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_UART2_1),
        },
        [DMACH_TIMER] = {
                .name           = "timer",
                .channels       = MAP(S3C2412_DMAREQSEL_TIMER),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_TIMER),
        },
        [DMACH_I2S_IN] = {
                .name           = "i2s-sdi",
                .channels       = MAP(S3C2412_DMAREQSEL_I2SRX),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_I2SRX),
        },
        [DMACH_I2S_OUT] = {
                .name           = "i2s-sdo",
                .channels       = MAP(S3C2412_DMAREQSEL_I2STX),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_I2STX),
        },
        [DMACH_USB_EP1] = {
                .name           = "usb-ep1",
                .channels       = MAP(S3C2412_DMAREQSEL_USBEP1),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_USBEP1),
        },
        [DMACH_USB_EP2] = {
                .name           = "usb-ep2",
                .channels       = MAP(S3C2412_DMAREQSEL_USBEP2),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_USBEP2),
        },
        [DMACH_USB_EP3] = {
                .name           = "usb-ep3",
                .channels       = MAP(S3C2412_DMAREQSEL_USBEP3),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_USBEP3),
        },
        [DMACH_USB_EP4] = {
                .name           = "usb-ep4",
                .channels       = MAP(S3C2412_DMAREQSEL_USBEP4),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_USBEP4),
        },
 };
-static void s3c2412_dma_direction(struct s3c2410_dma_chan *chan,
-                                  struct s3c24xx_dma_map *map,
-                                  enum dma_data_direction dir)
-{
-        unsigned long chsel;
-        if (dir == DMA_FROM_DEVICE)
-                chsel = map->channels_rx[0];
-        else
-                chsel = map->channels[0];
-        chsel &= ~DMA_CH_VALID;
-        chsel |= S3C2412_DMAREQSEL_HW;
-        writel(chsel, chan->regs + S3C2412_DMA_DMAREQSEL);
-}
 static void s3c2412_dma_select(struct s3c2410_dma_chan *chan,
                               struct s3c24xx_dma_map *map)
 {
-        s3c2412_dma_direction(chan, map, chan->source);
+        unsigned long chsel = map->channels[0] & (~DMA_CH_VALID);
+        writel(chsel | S3C2412_DMAREQSEL_HW,
+               chan->regs + S3C2412_DMA_DMAREQSEL);
 }
 static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = {
        .select         = s3c2412_dma_select,
-        .direction      = s3c2412_dma_direction,
        .dcon_mask      = 0,
        .map            = s3c2412_dma_mappings,
        .map_size       = ARRAY_SIZE(s3c2412_dma_mappings),
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2443.c b/arch/arm/mach-s3c24xx/dma-s3c2443.c
index 5fe3539dc2b5..95b9f759fe97 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2443.c
@@ -128,7 +128,8 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
 static void s3c2443_dma_select(struct s3c2410_dma_chan *chan,
                               struct s3c24xx_dma_map *map)
 {
-        writel(map->channels[0] | S3C2443_DMAREQSEL_HW,
+        unsigned long chsel = map->channels[0] & (~DMA_CH_VALID);
+        writel(chsel | S3C2443_DMAREQSEL_HW,
               chan->regs + S3C2443_DMA_DMAREQSEL);
 }
diff --git a/arch/arm/mach-s3c24xx/dma.c b/arch/arm/mach-s3c24xx/dma.c
index aab64909e9a3..4a65cba3295d 100644
--- a/arch/arm/mach-s3c24xx/dma.c
+++ b/arch/arm/mach-s3c24xx/dma.c
@@ -1159,9 +1159,6 @@ int s3c2410_dma_devconfig(enum dma_ch channel,
                return -EINVAL;
        }
-        if (dma_sel.direction != NULL)
-                (dma_sel.direction)(chan, chan->map, source);
        return 0;
 }
diff --git a/arch/arm/mach-s3c24xx/s3c2412.h b/arch/arm/mach-s3c24xx/include/mach/s3c2412.h
index 548ced42cbb7..548ced42cbb7 100644
--- a/arch/arm/mach-s3c24xx/s3c2412.h
+++ b/arch/arm/mach-s3c24xx/include/mach/s3c2412.h
diff --git a/arch/arm/mach-s3c24xx/include/mach/uncompress.h b/arch/arm/mach-s3c24xx/include/mach/uncompress.h
index 8b283f847daa..7d2ce205dce8 100644
--- a/arch/arm/mach-s3c24xx/include/mach/uncompress.h
+++ b/arch/arm/mach-s3c24xx/include/mach/uncompress.h
@@ -49,6 +49,9 @@ static void arch_detect_cpu(void)
                fifo_mask = S3C2410_UFSTAT_TXMASK;
                fifo_max = 15 << S3C2410_UFSTAT_TXSHIFT;
        }
+        uart_base = (volatile u8 *) S3C_PA_UART +
+                (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
 }
 #endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s3c24xx/iotiming-s3c2412.c b/arch/arm/mach-s3c24xx/iotiming-s3c2412.c
index 663436d9db01..bd064c05c473 100644
--- a/arch/arm/mach-s3c24xx/iotiming-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/iotiming-s3c2412.c
@@ -31,7 +31,7 @@
 #include <plat/cpu-freq-core.h>
 #include <plat/clock.h>
-#include "s3c2412.h"
+#include <mach/s3c2412.h>
 #define print_ns(x) ((x) / 10), ((x) % 10)
diff --git a/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c b/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c
new file mode 100644
index 000000000000..f50454a34f72
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c
@@ -0,0 +1,91 @@
+/*
+ * Samsung's S3C2416 flattened device tree enabled machine
+ *
+ * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de>
+ *
+ * based on mach-exynos/mach-exynos4-dt.c
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ * Copyright (c) 2010-2011 Linaro Ltd.
+ *              www.linaro.org
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/clocksource.h>
+#include <linux/irqchip.h>
+#include <linux/of_platform.h>
+#include <linux/serial_core.h>
+#include <asm/mach/arch.h>
+#include <mach/map.h>
+#include <plat/cpu.h>
+#include <plat/pm.h>
+#include <plat/regs-serial.h>
+#include "common.h"
+/*
+ * The following lookup table is used to override device names when devices
+ * are registered from device tree. This is temporarily added to enable
+ * device tree support addition for the S3C2416 architecture.
+ *
+ * For drivers that require platform data to be provided from the machine
+ * file, a platform data pointer can also be supplied along with the
+ * devices names. Usually, the platform data elements that cannot be parsed
+ * from the device tree by the drivers (example: function pointers) are
+ * supplied. But it should be noted that this is a temporary mechanism and
+ * at some point, the drivers should be capable of parsing all the platform
+ * data from the device tree.
+ */
+static const struct of_dev_auxdata s3c2416_auxdata_lookup[] __initconst = {
+        OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART,
+                                "s3c2440-uart.0", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART + 0x4000,
+                                "s3c2440-uart.1", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART + 0x8000,
+                                "s3c2440-uart.2", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART + 0xC000,
+                                "s3c2440-uart.3", NULL),
+        OF_DEV_AUXDATA("samsung,s3c6410-sdhci", S3C_PA_HSMMC0,
+                                "s3c-sdhci.0", NULL),
+        OF_DEV_AUXDATA("samsung,s3c6410-sdhci", S3C_PA_HSMMC1,
+                                "s3c-sdhci.1", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-i2c", S3C_PA_IIC,
+                                "s3c2440-i2c.0", NULL),
+        {},
+};
+static void __init s3c2416_dt_map_io(void)
+{
+        s3c24xx_init_io(NULL, 0);
+        s3c24xx_init_clocks(12000000);
+}
+static void __init s3c2416_dt_machine_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table,
+                                s3c2416_auxdata_lookup, NULL);
+        s3c_pm_init();
+}
+static char const *s3c2416_dt_compat[] __initdata = {
+        "samsung,s3c2416",
+        "samsung,s3c2450",
+        NULL
+};
+DT_MACHINE_START(S3C2416_DT, "Samsung S3C2416 (Flattened Device Tree)")
+        /* Maintainer: Heiko Stuebner <heiko@sntech.de> */
+        .dt_compat      = s3c2416_dt_compat,
+        .map_io         = s3c2416_dt_map_io,
+        .init_irq       = irqchip_init,
+        .init_machine   = s3c2416_dt_machine_init,
+         .init_time     = clocksource_of_init,
+        .restart        = s3c2416_restart,
+MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/pll-s3c2410.c b/arch/arm/mach-s3c24xx/pll-s3c2410.c
index dcf3420a3271..5e37d368594b 100644
--- a/arch/arm/mach-s3c24xx/pll-s3c2410.c
+++ b/arch/arm/mach-s3c24xx/pll-s3c2410.c
@@ -33,36 +33,36 @@
 #include <plat/cpu-freq-core.h>
 static struct cpufreq_frequency_table pll_vals_12MHz[] = {
-    { .frequency = 34000000,  .index = PLLVAL(82, 2, 3),   },
+    { .frequency = 34000000,  .driver_data = PLLVAL(82, 2, 3),   },
-    { .frequency = 45000000,  .index = PLLVAL(82, 1, 3),   },
+    { .frequency = 45000000,  .driver_data = PLLVAL(82, 1, 3),   },
-    { .frequency = 51000000,  .index = PLLVAL(161, 3, 3),  },
+    { .frequency = 51000000,  .driver_data = PLLVAL(161, 3, 3),  },
-    { .frequency = 48000000,  .index = PLLVAL(120, 2, 3),  },
+    { .frequency = 48000000,  .driver_data = PLLVAL(120, 2, 3),  },
-    { .frequency = 56000000,  .index = PLLVAL(142, 2, 3),  },
+    { .frequency = 56000000,  .driver_data = PLLVAL(142, 2, 3),  },
-    { .frequency = 68000000,  .index = PLLVAL(82, 2, 2),   },
+    { .frequency = 68000000,  .driver_data = PLLVAL(82, 2, 2),   },
-    { .frequency = 79000000,  .index = PLLVAL(71, 1, 2),   },
+    { .frequency = 79000000,  .driver_data = PLLVAL(71, 1, 2),   },
-    { .frequency = 85000000,  .index = PLLVAL(105, 2, 2),  },
+    { .frequency = 85000000,  .driver_data = PLLVAL(105, 2, 2),  },
-    { .frequency = 90000000,  .index = PLLVAL(112, 2, 2),  },
+    { .frequency = 90000000,  .driver_data = PLLVAL(112, 2, 2),  },
-    { .frequency = 101000000, .index = PLLVAL(127, 2, 2),  },
+    { .frequency = 101000000, .driver_data = PLLVAL(127, 2, 2),  },
-    { .frequency = 113000000, .index = PLLVAL(105, 1, 2),  },
+    { .frequency = 113000000, .driver_data = PLLVAL(105, 1, 2),  },
-    { .frequency = 118000000, .index = PLLVAL(150, 2, 2),  },
+    { .frequency = 118000000, .driver_data = PLLVAL(150, 2, 2),  },
-    { .frequency = 124000000, .index = PLLVAL(116, 1, 2),  },
+    { .frequency = 124000000, .driver_data = PLLVAL(116, 1, 2),  },
-    { .frequency = 135000000, .index = PLLVAL(82, 2, 1),   },
+    { .frequency = 135000000, .driver_data = PLLVAL(82, 2, 1),   },
-    { .frequency = 147000000, .index = PLLVAL(90, 2, 1),   },
+    { .frequency = 147000000, .driver_data = PLLVAL(90, 2, 1),   },
-    { .frequency = 152000000, .index = PLLVAL(68, 1, 1),   },
+    { .frequency = 152000000, .driver_data = PLLVAL(68, 1, 1),   },
-    { .frequency = 158000000, .index = PLLVAL(71, 1, 1),   },
+    { .frequency = 158000000, .driver_data = PLLVAL(71, 1, 1),   },
-    { .frequency = 170000000, .index = PLLVAL(77, 1, 1),   },
+    { .frequency = 170000000, .driver_data = PLLVAL(77, 1, 1),   },
-    { .frequency = 180000000, .index = PLLVAL(82, 1, 1),   },
+    { .frequency = 180000000, .driver_data = PLLVAL(82, 1, 1),   },
-    { .frequency = 186000000, .index = PLLVAL(85, 1, 1),   },
+    { .frequency = 186000000, .driver_data = PLLVAL(85, 1, 1),   },
-    { .frequency = 192000000, .index = PLLVAL(88, 1, 1),   },
+    { .frequency = 192000000, .driver_data = PLLVAL(88, 1, 1),   },
-    { .frequency = 203000000, .index = PLLVAL(161, 3, 1),  },
+    { .frequency = 203000000, .driver_data = PLLVAL(161, 3, 1),  },
    /* 2410A extras */
-    { .frequency = 210000000, .index = PLLVAL(132, 2, 1),  },
+    { .frequency = 210000000, .driver_data = PLLVAL(132, 2, 1),  },
-    { .frequency = 226000000, .index = PLLVAL(105, 1, 1),  },
+    { .frequency = 226000000, .driver_data = PLLVAL(105, 1, 1),  },
-    { .frequency = 266000000, .index = PLLVAL(125, 1, 1),  },
+    { .frequency = 266000000, .driver_data = PLLVAL(125, 1, 1),  },
-    { .frequency = 268000000, .index = PLLVAL(126, 1, 1),  },
+    { .frequency = 268000000, .driver_data = PLLVAL(126, 1, 1),  },
-    { .frequency = 270000000, .index = PLLVAL(127, 1, 1),  },
+    { .frequency = 270000000, .driver_data = PLLVAL(127, 1, 1),  },
 };
 static int s3c2410_plls_add(struct device *dev, struct subsys_interface *sif)
diff --git a/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c b/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c
index 673781758319..a19460e6e7b0 100644
--- a/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c
+++ b/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c
@@ -21,33 +21,33 @@
 #include <plat/cpu-freq-core.h>
 static struct cpufreq_frequency_table s3c2440_plls_12[] __initdata = {
-        { .frequency = 75000000,        .index = PLLVAL(0x75, 3, 3),  },        /* FVco 600.000000 */
+        { .frequency = 75000000,        .driver_data = PLLVAL(0x75, 3, 3),  },  /* FVco 600.000000 */
-        { .frequency = 80000000,        .index = PLLVAL(0x98, 4, 3),  },        /* FVco 640.000000 */
+        { .frequency = 80000000,        .driver_data = PLLVAL(0x98, 4, 3),  },  /* FVco 640.000000 */
-        { .frequency = 90000000,        .index = PLLVAL(0x70, 2, 3),  },        /* FVco 720.000000 */
+        { .frequency = 90000000,        .driver_data = PLLVAL(0x70, 2, 3),  },  /* FVco 720.000000 */
-        { .frequency = 100000000,       .index = PLLVAL(0x5c, 1, 3),  },        /* FVco 800.000000 */
+        { .frequency = 100000000,       .driver_data = PLLVAL(0x5c, 1, 3),  },  /* FVco 800.000000 */
-        { .frequency = 110000000,       .index = PLLVAL(0x66, 1, 3),  },        /* FVco 880.000000 */
+        { .frequency = 110000000,       .driver_data = PLLVAL(0x66, 1, 3),  },  /* FVco 880.000000 */
-        { .frequency = 120000000,       .index = PLLVAL(0x70, 1, 3),  },        /* FVco 960.000000 */
+        { .frequency = 120000000,       .driver_data = PLLVAL(0x70, 1, 3),  },  /* FVco 960.000000 */
-        { .frequency = 150000000,       .index = PLLVAL(0x75, 3, 2),  },        /* FVco 600.000000 */
+        { .frequency = 150000000,       .driver_data = PLLVAL(0x75, 3, 2),  },  /* FVco 600.000000 */
-        { .frequency = 160000000,       .index = PLLVAL(0x98, 4, 2),  },        /* FVco 640.000000 */
+        { .frequency = 160000000,       .driver_data = PLLVAL(0x98, 4, 2),  },  /* FVco 640.000000 */
-        { .frequency = 170000000,       .index = PLLVAL(0x4d, 1, 2),  },        /* FVco 680.000000 */
+        { .frequency = 170000000,       .driver_data = PLLVAL(0x4d, 1, 2),  },  /* FVco 680.000000 */
-        { .frequency = 180000000,       .index = PLLVAL(0x70, 2, 2),  },        /* FVco 720.000000 */
+        { .frequency = 180000000,       .driver_data = PLLVAL(0x70, 2, 2),  },  /* FVco 720.000000 */
-        { .frequency = 190000000,       .index = PLLVAL(0x57, 1, 2),  },        /* FVco 760.000000 */
+        { .frequency = 190000000,       .driver_data = PLLVAL(0x57, 1, 2),  },  /* FVco 760.000000 */
-        { .frequency = 200000000,       .index = PLLVAL(0x5c, 1, 2),  },        /* FVco 800.000000 */
+        { .frequency = 200000000,       .driver_data = PLLVAL(0x5c, 1, 2),  },  /* FVco 800.000000 */
-        { .frequency = 210000000,       .index = PLLVAL(0x84, 2, 2),  },        /* FVco 840.000000 */
+        { .frequency = 210000000,       .driver_data = PLLVAL(0x84, 2, 2),  },  /* FVco 840.000000 */
-        { .frequency = 220000000,       .index = PLLVAL(0x66, 1, 2),  },        /* FVco 880.000000 */
+        { .frequency = 220000000,       .driver_data = PLLVAL(0x66, 1, 2),  },  /* FVco 880.000000 */
-        { .frequency = 230000000,       .index = PLLVAL(0x6b, 1, 2),  },        /* FVco 920.000000 */
+        { .frequency = 230000000,       .driver_data = PLLVAL(0x6b, 1, 2),  },  /* FVco 920.000000 */
-        { .frequency = 240000000,       .index = PLLVAL(0x70, 1, 2),  },        /* FVco 960.000000 */
+        { .frequency = 240000000,       .driver_data = PLLVAL(0x70, 1, 2),  },  /* FVco 960.000000 */
-        { .frequency = 300000000,       .index = PLLVAL(0x75, 3, 1),  },        /* FVco 600.000000 */
+        { .frequency = 300000000,       .driver_data = PLLVAL(0x75, 3, 1),  },  /* FVco 600.000000 */
-        { .frequency = 310000000,       .index = PLLVAL(0x93, 4, 1),  },        /* FVco 620.000000 */
+        { .frequency = 310000000,       .driver_data = PLLVAL(0x93, 4, 1),  },  /* FVco 620.000000 */
-        { .frequency = 320000000,       .index = PLLVAL(0x98, 4, 1),  },        /* FVco 640.000000 */
+        { .frequency = 320000000,       .driver_data = PLLVAL(0x98, 4, 1),  },  /* FVco 640.000000 */
-        { .frequency = 330000000,       .index = PLLVAL(0x66, 2, 1),  },        /* FVco 660.000000 */
+        { .frequency = 330000000,       .driver_data = PLLVAL(0x66, 2, 1),  },  /* FVco 660.000000 */
-        { .frequency = 340000000,       .index = PLLVAL(0x4d, 1, 1),  },        /* FVco 680.000000 */
+        { .frequency = 340000000,       .driver_data = PLLVAL(0x4d, 1, 1),  },  /* FVco 680.000000 */
-        { .frequency = 350000000,       .index = PLLVAL(0xa7, 4, 1),  },        /* FVco 700.000000 */
+        { .frequency = 350000000,       .driver_data = PLLVAL(0xa7, 4, 1),  },  /* FVco 700.000000 */
-        { .frequency = 360000000,       .index = PLLVAL(0x70, 2, 1),  },        /* FVco 720.000000 */
+        { .frequency = 360000000,       .driver_data = PLLVAL(0x70, 2, 1),  },  /* FVco 720.000000 */
-        { .frequency = 370000000,       .index = PLLVAL(0xb1, 4, 1),  },        /* FVco 740.000000 */
+        { .frequency = 370000000,       .driver_data = PLLVAL(0xb1, 4, 1),  },  /* FVco 740.000000 */
-        { .frequency = 380000000,       .index = PLLVAL(0x57, 1, 1),  },        /* FVco 760.000000 */
+        { .frequency = 380000000,       .driver_data = PLLVAL(0x57, 1, 1),  },  /* FVco 760.000000 */
-        { .frequency = 390000000,       .index = PLLVAL(0x7a, 2, 1),  },        /* FVco 780.000000 */
+        { .frequency = 390000000,       .driver_data = PLLVAL(0x7a, 2, 1),  },  /* FVco 780.000000 */
-        { .frequency = 400000000,       .index = PLLVAL(0x5c, 1, 1),  },        /* FVco 800.000000 */
+        { .frequency = 400000000,       .driver_data = PLLVAL(0x5c, 1, 1),  },  /* FVco 800.000000 */
 };
 static int s3c2440_plls12_add(struct device *dev, struct subsys_interface *sif)
diff --git a/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c b/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c
index debfa106289b..1191b2905625 100644
--- a/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c
+++ b/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c
@@ -21,61 +21,61 @@
 #include <plat/cpu-freq-core.h>
 static struct cpufreq_frequency_table s3c2440_plls_169344[] __initdata = {
-        { .frequency = 78019200,        .index = PLLVAL(121, 5, 3),     },      /* FVco 624.153600 */
+        { .frequency = 78019200,        .driver_data = PLLVAL(121, 5, 3),       },      /* FVco 624.153600 */
-        { .frequency = 84067200,        .index = PLLVAL(131, 5, 3),     },      /* FVco 672.537600 */
+        { .frequency = 84067200,        .driver_data = PLLVAL(131, 5, 3),       },      /* FVco 672.537600 */
-        { .frequency = 90115200,        .index = PLLVAL(141, 5, 3),     },      /* FVco 720.921600 */
+        { .frequency = 90115200,        .driver_data = PLLVAL(141, 5, 3),       },      /* FVco 720.921600 */
-        { .frequency = 96163200,        .index = PLLVAL(151, 5, 3),     },      /* FVco 769.305600 */
+        { .frequency = 96163200,        .driver_data = PLLVAL(151, 5, 3),       },      /* FVco 769.305600 */
-        { .frequency = 102135600,       .index = PLLVAL(185, 6, 3),     },      /* FVco 817.084800 */
+        { .frequency = 102135600,       .driver_data = PLLVAL(185, 6, 3),       },      /* FVco 817.084800 */
-        { .frequency = 108259200,       .index = PLLVAL(171, 5, 3),     },      /* FVco 866.073600 */
+        { .frequency = 108259200,       .driver_data = PLLVAL(171, 5, 3),       },      /* FVco 866.073600 */
-        { .frequency = 114307200,       .index = PLLVAL(127, 3, 3),     },      /* FVco 914.457600 */
+        { .frequency = 114307200,       .driver_data = PLLVAL(127, 3, 3),       },      /* FVco 914.457600 */
-        { .frequency = 120234240,       .index = PLLVAL(134, 3, 3),     },      /* FVco 961.873920 */
+        { .frequency = 120234240,       .driver_data = PLLVAL(134, 3, 3),       },      /* FVco 961.873920 */
-        { .frequency = 126161280,       .index = PLLVAL(141, 3, 3),     },      /* FVco 1009.290240 */
+        { .frequency = 126161280,       .driver_data = PLLVAL(141, 3, 3),       },      /* FVco 1009.290240 */
-        { .frequency = 132088320,       .index = PLLVAL(148, 3, 3),     },      /* FVco 1056.706560 */
+        { .frequency = 132088320,       .driver_data = PLLVAL(148, 3, 3),       },      /* FVco 1056.706560 */
-        { .frequency = 138015360,       .index = PLLVAL(155, 3, 3),     },      /* FVco 1104.122880 */
+        { .frequency = 138015360,       .driver_data = PLLVAL(155, 3, 3),       },      /* FVco 1104.122880 */
-        { .frequency = 144789120,       .index = PLLVAL(163, 3, 3),     },      /* FVco 1158.312960 */
+        { .frequency = 144789120,       .driver_data = PLLVAL(163, 3, 3),       },      /* FVco 1158.312960 */
-        { .frequency = 150100363,       .index = PLLVAL(187, 9, 2),     },      /* FVco 600.401454 */
+        { .frequency = 150100363,       .driver_data = PLLVAL(187, 9, 2),       },      /* FVco 600.401454 */
-        { .frequency = 156038400,       .index = PLLVAL(121, 5, 2),     },      /* FVco 624.153600 */
+        { .frequency = 156038400,       .driver_data = PLLVAL(121, 5, 2),       },      /* FVco 624.153600 */
-        { .frequency = 162086400,       .index = PLLVAL(126, 5, 2),     },      /* FVco 648.345600 */
+        { .frequency = 162086400,       .driver_data = PLLVAL(126, 5, 2),       },      /* FVco 648.345600 */
-        { .frequency = 168134400,       .index = PLLVAL(131, 5, 2),     },      /* FVco 672.537600 */
+        { .frequency = 168134400,       .driver_data = PLLVAL(131, 5, 2),       },      /* FVco 672.537600 */
-        { .frequency = 174048000,       .index = PLLVAL(177, 7, 2),     },      /* FVco 696.192000 */
+        { .frequency = 174048000,       .driver_data = PLLVAL(177, 7, 2),       },      /* FVco 696.192000 */
-        { .frequency = 180230400,       .index = PLLVAL(141, 5, 2),     },      /* FVco 720.921600 */
+        { .frequency = 180230400,       .driver_data = PLLVAL(141, 5, 2),       },      /* FVco 720.921600 */
-        { .frequency = 186278400,       .index = PLLVAL(124, 4, 2),     },      /* FVco 745.113600 */
+        { .frequency = 186278400,       .driver_data = PLLVAL(124, 4, 2),       },      /* FVco 745.113600 */
-        { .frequency = 192326400,       .index = PLLVAL(151, 5, 2),     },      /* FVco 769.305600 */
+        { .frequency = 192326400,       .driver_data = PLLVAL(151, 5, 2),       },      /* FVco 769.305600 */
-        { .frequency = 198132480,       .index = PLLVAL(109, 3, 2),     },      /* FVco 792.529920 */
+        { .frequency = 198132480,       .driver_data = PLLVAL(109, 3, 2),       },      /* FVco 792.529920 */
-        { .frequency = 204271200,       .index = PLLVAL(185, 6, 2),     },      /* FVco 817.084800 */
+        { .frequency = 204271200,       .driver_data = PLLVAL(185, 6, 2),       },      /* FVco 817.084800 */
-        { .frequency = 210268800,       .index = PLLVAL(141, 4, 2),     },      /* FVco 841.075200 */
+        { .frequency = 210268800,       .driver_data = PLLVAL(141, 4, 2),       },      /* FVco 841.075200 */
-        { .frequency = 216518400,       .index = PLLVAL(171, 5, 2),     },      /* FVco 866.073600 */
+        { .frequency = 216518400,       .driver_data = PLLVAL(171, 5, 2),       },      /* FVco 866.073600 */
-        { .frequency = 222264000,       .index = PLLVAL(97, 2, 2),      },      /* FVco 889.056000 */
+        { .frequency = 222264000,       .driver_data = PLLVAL(97, 2, 2),        },      /* FVco 889.056000 */
-        { .frequency = 228614400,       .index = PLLVAL(127, 3, 2),     },      /* FVco 914.457600 */
+        { .frequency = 228614400,       .driver_data = PLLVAL(127, 3, 2),       },      /* FVco 914.457600 */
-        { .frequency = 234259200,       .index = PLLVAL(158, 4, 2),     },      /* FVco 937.036800 */
+        { .frequency = 234259200,       .driver_data = PLLVAL(158, 4, 2),       },      /* FVco 937.036800 */
-        { .frequency = 240468480,       .index = PLLVAL(134, 3, 2),     },      /* FVco 961.873920 */
+        { .frequency = 240468480,       .driver_data = PLLVAL(134, 3, 2),       },      /* FVco 961.873920 */
-        { .frequency = 246960000,       .index = PLLVAL(167, 4, 2),     },      /* FVco 987.840000 */
+        { .frequency = 246960000,       .driver_data = PLLVAL(167, 4, 2),       },      /* FVco 987.840000 */
-        { .frequency = 252322560,       .index = PLLVAL(141, 3, 2),     },      /* FVco 1009.290240 */
+        { .frequency = 252322560,       .driver_data = PLLVAL(141, 3, 2),       },      /* FVco 1009.290240 */
-        { .frequency = 258249600,       .index = PLLVAL(114, 2, 2),     },      /* FVco 1032.998400 */
+        { .frequency = 258249600,       .driver_data = PLLVAL(114, 2, 2),       },      /* FVco 1032.998400 */
-        { .frequency = 264176640,       .index = PLLVAL(148, 3, 2),     },      /* FVco 1056.706560 */
+        { .frequency = 264176640,       .driver_data = PLLVAL(148, 3, 2),       },      /* FVco 1056.706560 */
-        { .frequency = 270950400,       .index = PLLVAL(120, 2, 2),     },      /* FVco 1083.801600 */
+        { .frequency = 270950400,       .driver_data = PLLVAL(120, 2, 2),       },      /* FVco 1083.801600 */
-        { .frequency = 276030720,       .index = PLLVAL(155, 3, 2),     },      /* FVco 1104.122880 */
+        { .frequency = 276030720,       .driver_data = PLLVAL(155, 3, 2),       },      /* FVco 1104.122880 */
-        { .frequency = 282240000,       .index = PLLVAL(92, 1, 2),      },      /* FVco 1128.960000 */
+        { .frequency = 282240000,       .driver_data = PLLVAL(92, 1, 2),        },      /* FVco 1128.960000 */
-        { .frequency = 289578240,       .index = PLLVAL(163, 3, 2),     },      /* FVco 1158.312960 */
+        { .frequency = 289578240,       .driver_data = PLLVAL(163, 3, 2),       },      /* FVco 1158.312960 */
-        { .frequency = 294235200,       .index = PLLVAL(131, 2, 2),     },      /* FVco 1176.940800 */
+        { .frequency = 294235200,       .driver_data = PLLVAL(131, 2, 2),       },      /* FVco 1176.940800 */
-        { .frequency = 300200727,       .index = PLLVAL(187, 9, 1),     },      /* FVco 600.401454 */
+        { .frequency = 300200727,       .driver_data = PLLVAL(187, 9, 1),       },      /* FVco 600.401454 */
-        { .frequency = 306358690,       .index = PLLVAL(191, 9, 1),     },      /* FVco 612.717380 */
+        { .frequency = 306358690,       .driver_data = PLLVAL(191, 9, 1),       },      /* FVco 612.717380 */
-        { .frequency = 312076800,       .index = PLLVAL(121, 5, 1),     },      /* FVco 624.153600 */
+        { .frequency = 312076800,       .driver_data = PLLVAL(121, 5, 1),       },      /* FVco 624.153600 */
-        { .frequency = 318366720,       .index = PLLVAL(86, 3, 1),      },      /* FVco 636.733440 */
+        { .frequency = 318366720,       .driver_data = PLLVAL(86, 3, 1),        },      /* FVco 636.733440 */
-        { .frequency = 324172800,       .index = PLLVAL(126, 5, 1),     },      /* FVco 648.345600 */
+        { .frequency = 324172800,       .driver_data = PLLVAL(126, 5, 1),       },      /* FVco 648.345600 */
-        { .frequency = 330220800,       .index = PLLVAL(109, 4, 1),     },      /* FVco 660.441600 */
+        { .frequency = 330220800,       .driver_data = PLLVAL(109, 4, 1),       },      /* FVco 660.441600 */
-        { .frequency = 336268800,       .index = PLLVAL(131, 5, 1),     },      /* FVco 672.537600 */
+        { .frequency = 336268800,       .driver_data = PLLVAL(131, 5, 1),       },      /* FVco 672.537600 */
-        { .frequency = 342074880,       .index = PLLVAL(93, 3, 1),      },      /* FVco 684.149760 */
+        { .frequency = 342074880,       .driver_data = PLLVAL(93, 3, 1),        },      /* FVco 684.149760 */
-        { .frequency = 348096000,       .index = PLLVAL(177, 7, 1),     },      /* FVco 696.192000 */
+        { .frequency = 348096000,       .driver_data = PLLVAL(177, 7, 1),       },      /* FVco 696.192000 */
-        { .frequency = 355622400,       .index = PLLVAL(118, 4, 1),     },      /* FVco 711.244800 */
+        { .frequency = 355622400,       .driver_data = PLLVAL(118, 4, 1),       },      /* FVco 711.244800 */
-        { .frequency = 360460800,       .index = PLLVAL(141, 5, 1),     },      /* FVco 720.921600 */
+        { .frequency = 360460800,       .driver_data = PLLVAL(141, 5, 1),       },      /* FVco 720.921600 */
-        { .frequency = 366206400,       .index = PLLVAL(165, 6, 1),     },      /* FVco 732.412800 */
+        { .frequency = 366206400,       .driver_data = PLLVAL(165, 6, 1),       },      /* FVco 732.412800 */
-        { .frequency = 372556800,       .index = PLLVAL(124, 4, 1),     },      /* FVco 745.113600 */
+        { .frequency = 372556800,       .driver_data = PLLVAL(124, 4, 1),       },      /* FVco 745.113600 */
-        { .frequency = 378201600,       .index = PLLVAL(126, 4, 1),     },      /* FVco 756.403200 */
+        { .frequency = 378201600,       .driver_data = PLLVAL(126, 4, 1),       },      /* FVco 756.403200 */
-        { .frequency = 384652800,       .index = PLLVAL(151, 5, 1),     },      /* FVco 769.305600 */
+        { .frequency = 384652800,       .driver_data = PLLVAL(151, 5, 1),       },      /* FVco 769.305600 */
-        { .frequency = 391608000,       .index = PLLVAL(177, 6, 1),     },      /* FVco 783.216000 */
+        { .frequency = 391608000,       .driver_data = PLLVAL(177, 6, 1),       },      /* FVco 783.216000 */
-        { .frequency = 396264960,       .index = PLLVAL(109, 3, 1),     },      /* FVco 792.529920 */
+        { .frequency = 396264960,       .driver_data = PLLVAL(109, 3, 1),       },      /* FVco 792.529920 */
-        { .frequency = 402192000,       .index = PLLVAL(87, 2, 1),      },      /* FVco 804.384000 */
+        { .frequency = 402192000,       .driver_data = PLLVAL(87, 2, 1),        },      /* FVco 804.384000 */
 };
 static int s3c2440_plls169344_add(struct device *dev,
diff --git a/arch/arm/mach-s3c24xx/s3c2410.c b/arch/arm/mach-s3c24xx/s3c2410.c
index d850ea5adac2..34676d1d5fec 100644
--- a/arch/arm/mach-s3c24xx/s3c2410.c
+++ b/arch/arm/mach-s3c24xx/s3c2410.c
@@ -22,6 +22,7 @@
 #include <linux/syscore_ops.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 #include <linux/io.h>
 #include <asm/mach/arch.h>
@@ -138,6 +139,7 @@ void __init s3c2410_init_clocks(int xtal)
        s3c2410_baseclk_add();
        s3c24xx_register_clock(&s3c2410_armclk);
        clkdev_add_table(s3c2410_clk_lookup, ARRAY_SIZE(s3c2410_clk_lookup));
+        samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
 }
 struct bus_type s3c2410_subsys = {
@@ -195,13 +197,13 @@ int __init s3c2410a_init(void)
        return s3c2410_init();
 }
-void s3c2410_restart(char mode, const char *cmd)
+void s3c2410_restart(enum reboot_mode mode, const char *cmd)
 {
-        if (mode == 's') {
+        if (mode == REBOOT_SOFT) {
                soft_restart(0);
        }
-        arch_wdt_reset();
+        samsung_wdt_reset();
        /* we'll take a jump through zero as a poor second */
        soft_restart(0);
diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c
index 0f864d4c97de..0251650cbf80 100644
--- a/arch/arm/mach-s3c24xx/s3c2412.c
+++ b/arch/arm/mach-s3c24xx/s3c2412.c
@@ -22,6 +22,7 @@
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -129,9 +130,9 @@ static void s3c2412_idle(void)
        cpu_do_idle();
 }
-void s3c2412_restart(char mode, const char *cmd)
+void s3c2412_restart(enum reboot_mode mode, const char *cmd)
 {
-        if (mode == 's')
+        if (mode == REBOOT_SOFT)
                soft_restart(0);
        /* errata "Watch-dog/Software Reset Problem" specifies that
diff --git a/arch/arm/mach-s3c24xx/s3c2416.c b/arch/arm/mach-s3c24xx/s3c2416.c
index b9c5d382dafb..9ef3ccfbe196 100644
--- a/arch/arm/mach-s3c24xx/s3c2416.c
+++ b/arch/arm/mach-s3c24xx/s3c2416.c
@@ -35,6 +35,7 @@
 #include <linux/syscore_ops.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -79,9 +80,9 @@ static struct device s3c2416_dev = {
        .bus            = &s3c2416_subsys,
 };
-void s3c2416_restart(char mode, const char *cmd)
+void s3c2416_restart(enum reboot_mode mode, const char *cmd)
 {
-        if (mode == 's')
+        if (mode == REBOOT_SOFT)
                soft_restart(0);
        __raw_writel(S3C2443_SWRST_RESET, S3C2443_SWRST);
diff --git a/arch/arm/mach-s3c24xx/s3c2443.c b/arch/arm/mach-s3c24xx/s3c2443.c
index 8328cd65bf3d..b6c71918b25c 100644
--- a/arch/arm/mach-s3c24xx/s3c2443.c
+++ b/arch/arm/mach-s3c24xx/s3c2443.c
@@ -22,6 +22,7 @@
 #include <linux/device.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -59,9 +60,9 @@ static struct device s3c2443_dev = {
        .bus            = &s3c2443_subsys,
 };
-void s3c2443_restart(char mode, const char *cmd)
+void s3c2443_restart(enum reboot_mode mode, const char *cmd)
 {
-        if (mode == 's')
+        if (mode == REBOOT_SOFT)
                soft_restart(0);
        __raw_writel(S3C2443_SWRST_RESET, S3C2443_SWRST);
diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c
index 2a35edb67354..911b555029fc 100644
--- a/arch/arm/mach-s3c24xx/s3c244x.c
+++ b/arch/arm/mach-s3c24xx/s3c244x.c
@@ -18,6 +18,7 @@
 #include <linux/init.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 #include <linux/device.h>
 #include <linux/syscore_ops.h>
 #include <linux/clk.h>
@@ -133,6 +134,7 @@ void __init s3c244x_init_clocks(int xtal)
        s3c24xx_register_baseclocks(xtal);
        s3c244x_setup_clocks();
        s3c2410_baseclk_add();
+        samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
 }
 /* Since the S3C2442 and S3C2440 share items, put both subsystems here */
@@ -197,12 +199,12 @@ struct syscore_ops s3c244x_pm_syscore_ops = {
        .resume         = s3c244x_resume,
 };
-void s3c244x_restart(char mode, const char *cmd)
+void s3c244x_restart(enum reboot_mode mode, const char *cmd)
 {
-        if (mode == 's')
+        if (mode == REBOOT_SOFT)
                soft_restart(0);
-        arch_wdt_reset();
+        samsung_wdt_reset();
        /* we'll take a jump through zero as a poor second */
        soft_restart(0);
diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c
index 0b9c0ba44834..3f62e467b129 100644
--- a/arch/arm/mach-s3c64xx/common.c
+++ b/arch/arm/mach-s3c64xx/common.c
@@ -21,6 +21,7 @@
 #include <linux/ioport.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 #include <linux/io.h>
 #include <linux/dma-mapping.h>
 #include <linux/irq.h>
@@ -183,6 +184,12 @@ core_initcall(s3c64xx_dev_init);
 void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
 {
+        /*
+         * FIXME: there is no better place to put this at the moment
+         * (samsung_wdt_reset_init needs clocks)
+         */
+        samsung_wdt_reset_init(S3C_VA_WATCHDOG);
        printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
        /* initialise the pair of VICs */
@@ -375,10 +382,10 @@ static int __init s3c64xx_init_irq_eint(void)
 }
 arch_initcall(s3c64xx_init_irq_eint);
-void s3c64xx_restart(char mode, const char *cmd)
+void s3c64xx_restart(enum reboot_mode mode, const char *cmd)
 {
-        if (mode != 's')
+        if (mode != REBOOT_SOFT)
-                arch_wdt_reset();
+                samsung_wdt_reset();
        /* if all else fails, or mode was for soft, jump to 0 */
        soft_restart(0);
diff --git a/arch/arm/mach-s3c64xx/common.h b/arch/arm/mach-s3c64xx/common.h
index 6cfc99bdfb37..e8f990b37665 100644
--- a/arch/arm/mach-s3c64xx/common.h
+++ b/arch/arm/mach-s3c64xx/common.h
@@ -17,13 +17,15 @@
 #ifndef __ARCH_ARM_MACH_S3C64XX_COMMON_H
 #define __ARCH_ARM_MACH_S3C64XX_COMMON_H
+#include <linux/reboot.h>
 void s3c64xx_init_irq(u32 vic0, u32 vic1);
 void s3c64xx_init_io(struct map_desc *mach_desc, int size);
 void s3c64xx_register_clocks(unsigned long xtal, unsigned armclk_limit);
 void s3c64xx_setup_clocks(void);
-void s3c64xx_restart(char mode, const char *cmd);
+void s3c64xx_restart(enum reboot_mode mode, const char *cmd);
 void s3c64xx_init_late(void);
 #ifdef CONFIG_CPU_S3C6400
diff --git a/arch/arm/mach-s3c64xx/include/mach/uncompress.h b/arch/arm/mach-s3c64xx/include/mach/uncompress.h
index c6a82a20bf2a..1c956738b42d 100644
--- a/arch/arm/mach-s3c64xx/include/mach/uncompress.h
+++ b/arch/arm/mach-s3c64xx/include/mach/uncompress.h
@@ -23,6 +23,9 @@ static void arch_detect_cpu(void)
        /* we do not need to do any cpu detection here at the moment. */
        fifo_mask = S3C2440_UFSTAT_TXMASK;
        fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
+        uart_base = (volatile u8 *)S3C_PA_UART +
+                (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
 }
 #endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s5p64x0/common.c b/arch/arm/mach-s5p64x0/common.c
index 8ae5800e807f..dfdfdc320ce7 100644
--- a/arch/arm/mach-s5p64x0/common.c
+++ b/arch/arm/mach-s5p64x0/common.c
@@ -24,6 +24,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/gpio.h>
 #include <linux/irq.h>
+#include <linux/reboot.h>
 #include <asm/irq.h>
 #include <asm/proc-fns.h>
@@ -173,6 +174,8 @@ void __init s5p64x0_init_io(struct map_desc *mach_desc, int size)
        s5p_init_cpu(S5P64X0_SYS_ID);
        s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
+        samsung_wdt_reset_init(S3C_VA_WATCHDOG);
 }
 void __init s5p6440_map_io(void)
@@ -437,10 +440,10 @@ static int __init s5p64x0_init_irq_eint(void)
 }
 arch_initcall(s5p64x0_init_irq_eint);
-void s5p64x0_restart(char mode, const char *cmd)
+void s5p64x0_restart(enum reboot_mode mode, const char *cmd)
 {
-        if (mode != 's')
+        if (mode != REBOOT_SOFT)
-                arch_wdt_reset();
+                samsung_wdt_reset();
        soft_restart(0);
 }
diff --git a/arch/arm/mach-s5p64x0/common.h b/arch/arm/mach-s5p64x0/common.h
index f8a60fdc5884..f3a9b43cba4a 100644
--- a/arch/arm/mach-s5p64x0/common.h
+++ b/arch/arm/mach-s5p64x0/common.h
@@ -12,6 +12,8 @@
 #ifndef __ARCH_ARM_MACH_S5P64X0_COMMON_H
 #define __ARCH_ARM_MACH_S5P64X0_COMMON_H
+#include <linux/reboot.h>
 void s5p6440_init_irq(void);
 void s5p6450_init_irq(void);
 void s5p64x0_init_io(struct map_desc *mach_desc, int size);
@@ -22,7 +24,7 @@ void s5p6440_setup_clocks(void);
 void s5p6450_register_clocks(void);
 void s5p6450_setup_clocks(void);
-void s5p64x0_restart(char mode, const char *cmd);
+void s5p64x0_restart(enum reboot_mode mode, const char *cmd);
 #ifdef CONFIG_CPU_S5P6440
diff --git a/arch/arm/mach-s5p64x0/include/mach/uncompress.h b/arch/arm/mach-s5p64x0/include/mach/uncompress.h
index 19e0d64d78c5..bbcc3f669ee3 100644
--- a/arch/arm/mach-s5p64x0/include/mach/uncompress.h
+++ b/arch/arm/mach-s5p64x0/include/mach/uncompress.h
@@ -14,171 +14,21 @@
 #define __ASM_ARCH_UNCOMPRESS_H
 #include <mach/map.h>
+#include <plat/uncompress.h>
-/*
+static void arch_detect_cpu(void)
- * cannot use commonly <plat/uncompress.h>
- * because uart base of S5P6440 and S5P6450 is different
- */
-typedef unsigned int upf_t;     /* cannot include linux/serial_core.h */
-/* uart setup */
-unsigned int fifo_mask;
-unsigned int fifo_max;
-/* forward declerations */
-static void arch_detect_cpu(void);
-/* defines for UART registers */
-#include <plat/regs-serial.h>
-#include <plat/regs-watchdog.h>
-/* working in physical space... */
-#undef S3C2410_WDOGREG
-#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
-/* how many bytes we allow into the FIFO at a time in FIFO mode */
-#define FIFO_MAX         (14)
-unsigned long uart_base;
-static __inline__ void get_uart_base(void)
 {
        unsigned int chipid;
        chipid = *(const volatile unsigned int __force *) 0xE0100118;
-        uart_base = S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT;
        if ((chipid & 0xff000) == 0x50000)
-                uart_base += 0xEC800000;
+                uart_base = (volatile u8 *)S5P6450_PA_UART(CONFIG_S3C_LOWLEVEL_UART_PORT);
        else
-                uart_base += 0xEC000000;
+                uart_base = (volatile u8 *)S5P6440_PA_UART(CONFIG_S3C_LOWLEVEL_UART_PORT);
-}
-static __inline__ void uart_wr(unsigned int reg, unsigned int val)
-{
-        volatile unsigned int *ptr;
-        get_uart_base();
-        ptr = (volatile unsigned int *)(reg + uart_base);
-        *ptr = val;
-}
-static __inline__ unsigned int uart_rd(unsigned int reg)
-{
-        volatile unsigned int *ptr;
-        get_uart_base();
-        ptr = (volatile unsigned int *)(reg + uart_base);
-        return *ptr;
-}
-/*
- * we can deal with the case the UARTs are being run
- * in FIFO mode, so that we don't hold up our execution
- * waiting for tx to happen...
- */
-static void putc(int ch)
-{
-        if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
-                int level;
-                while (1) {
-                        level = uart_rd(S3C2410_UFSTAT);
-                        level &= fifo_mask;
-                        if (level < fifo_max)
-                                break;
-                }
-        } else {
-                /* not using fifos */
-                while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
-                        barrier();
-        }
-        /* write byte to transmission register */
+        fifo_mask = S3C2440_UFSTAT_TXMASK;
-        uart_wr(S3C2410_UTXH, ch);
+        fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
-}
-static inline void flush(void)
-{
-}
-#define __raw_writel(d, ad)                     \
-        do {                                                    \
-                *((volatile unsigned int __force *)(ad)) = (d); \
-        } while (0)
-#ifdef CONFIG_S3C_BOOT_ERROR_RESET
-static void arch_decomp_error(const char *x)
-{
-        putstr("\n\n");
-        putstr(x);
-        putstr("\n\n -- System resetting\n");
-        __raw_writel(0x4000, S3C2410_WTDAT);
-        __raw_writel(0x4000, S3C2410_WTCNT);
-        __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
-        while(1);
-}
-#define arch_error arch_decomp_error
-#endif
-#ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO
-static inline void arch_enable_uart_fifo(void)
-{
-        u32 fifocon = uart_rd(S3C2410_UFCON);
-        if (!(fifocon & S3C2410_UFCON_FIFOMODE)) {
-                fifocon |= S3C2410_UFCON_RESETBOTH;
-                uart_wr(S3C2410_UFCON, fifocon);
-                /* wait for fifo reset to complete */
-                while (1) {
-                        fifocon = uart_rd(S3C2410_UFCON);
-                        if (!(fifocon & S3C2410_UFCON_RESETBOTH))
-                                break;
-                }
-        }
-}
-#else
-#define arch_enable_uart_fifo() do { } while(0)
-#endif
-static void arch_decomp_setup(void)
-{
-        /*
-         * we may need to setup the uart(s) here if we are not running
-         * on an BAST... the BAST will have left the uarts configured
-         * after calling linux.
-         */
-        arch_detect_cpu();
-        /*
-         * Enable the UART FIFOs if they where not enabled and our
-         * configuration says we should turn them on.
-         */
-        arch_enable_uart_fifo();
-}
-static void arch_detect_cpu(void)
-{
-        /* we do not need to do any cpu detection here at the moment. */
 }
 #endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s5pc100/common.c b/arch/arm/mach-s5pc100/common.c
index cc6e561c9958..4bdfecf6d024 100644
--- a/arch/arm/mach-s5pc100/common.c
+++ b/arch/arm/mach-s5pc100/common.c
@@ -24,6 +24,7 @@
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
 #include <linux/sched.h>
+#include <linux/reboot.h>
 #include <asm/irq.h>
 #include <asm/proc-fns.h>
@@ -178,6 +179,7 @@ void __init s5pc100_init_clocks(int xtal)
        s5p_register_clocks(xtal);
        s5pc100_register_clocks();
        s5pc100_setup_clocks();
+        samsung_wdt_reset_init(S3C_VA_WATCHDOG);
 }
 void __init s5pc100_init_irq(void)
@@ -216,10 +218,10 @@ void __init s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no)
        s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
 }
-void s5pc100_restart(char mode, const char *cmd)
+void s5pc100_restart(enum reboot_mode mode, const char *cmd)
 {
-        if (mode != 's')
+        if (mode != REBOOT_SOFT)
-                arch_wdt_reset();
+                samsung_wdt_reset();
        soft_restart(0);
 }
diff --git a/arch/arm/mach-s5pc100/common.h b/arch/arm/mach-s5pc100/common.h
index c41f912e9e1f..08d782d65d7b 100644
--- a/arch/arm/mach-s5pc100/common.h
+++ b/arch/arm/mach-s5pc100/common.h
@@ -12,13 +12,15 @@
 #ifndef __ARCH_ARM_MACH_S5PC100_COMMON_H
 #define __ARCH_ARM_MACH_S5PC100_COMMON_H
+#include <linux/reboot.h>
 void s5pc100_init_io(struct map_desc *mach_desc, int size);
 void s5pc100_init_irq(void);
 void s5pc100_register_clocks(void);
 void s5pc100_setup_clocks(void);
-void s5pc100_restart(char mode, const char *cmd);
+void s5pc100_restart(enum reboot_mode mode, const char *cmd);
 extern  int s5pc100_init(void);
 extern void s5pc100_map_io(void);
diff --git a/arch/arm/mach-s5pc100/include/mach/uncompress.h b/arch/arm/mach-s5pc100/include/mach/uncompress.h
index 01ccf535e76c..720e1339425c 100644
--- a/arch/arm/mach-s5pc100/include/mach/uncompress.h
+++ b/arch/arm/mach-s5pc100/include/mach/uncompress.h
@@ -23,6 +23,8 @@ static void arch_detect_cpu(void)
        /* we do not need to do any cpu detection here at the moment. */
        fifo_mask = S3C2440_UFSTAT_TXMASK;
        fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
+        uart_base = (volatile u8 *)S5P_PA_UART(CONFIG_S3C_LOWLEVEL_UART_PORT);
 }
 #endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s5pv210/common.c b/arch/arm/mach-s5pv210/common.c
index 9dfe93e2624d..023f1a796a9c 100644
--- a/arch/arm/mach-s5pv210/common.c
+++ b/arch/arm/mach-s5pv210/common.c
@@ -143,7 +143,7 @@ static struct map_desc s5pv210_iodesc[] __initdata = {
        }
 };
-void s5pv210_restart(char mode, const char *cmd)
+void s5pv210_restart(enum reboot_mode mode, const char *cmd)
 {
        __raw_writel(0x1, S5P_SWRESET);
 }
diff --git a/arch/arm/mach-s5pv210/common.h b/arch/arm/mach-s5pv210/common.h
index 0a1cc0aef720..fe1beb54e548 100644
--- a/arch/arm/mach-s5pv210/common.h
+++ b/arch/arm/mach-s5pv210/common.h
@@ -12,13 +12,15 @@
 #ifndef __ARCH_ARM_MACH_S5PV210_COMMON_H
 #define __ARCH_ARM_MACH_S5PV210_COMMON_H
+#include <linux/reboot.h>
 void s5pv210_init_io(struct map_desc *mach_desc, int size);
 void s5pv210_init_irq(void);
 void s5pv210_register_clocks(void);
 void s5pv210_setup_clocks(void);
-void s5pv210_restart(char mode, const char *cmd);
+void s5pv210_restart(enum reboot_mode mode, const char *cmd);
 extern  int s5pv210_init(void);
 extern void s5pv210_map_io(void);
diff --git a/arch/arm/mach-s5pv210/include/mach/uncompress.h b/arch/arm/mach-s5pv210/include/mach/uncompress.h
index ef977ea8546d..231cb07de058 100644
--- a/arch/arm/mach-s5pv210/include/mach/uncompress.h
+++ b/arch/arm/mach-s5pv210/include/mach/uncompress.h
@@ -21,6 +21,8 @@ static void arch_detect_cpu(void)
        /* we do not need to do any cpu detection here at the moment. */
        fifo_mask = S5PV210_UFSTAT_TXMASK;
        fifo_max = 63 << S5PV210_UFSTAT_TXSHIFT;
+        uart_base = (volatile u8 *)S5P_PA_UART(CONFIG_S3C_LOWLEVEL_UART_PORT);
 }
 #endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index ed2b85485b9d..ad40ab0f5dbd 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -377,12 +377,8 @@ static struct max8998_platform_data aquila_max8998_pdata = {
        .buck1_set1     = S5PV210_GPH0(3),
        .buck1_set2     = S5PV210_GPH0(4),
        .buck2_set3     = S5PV210_GPH0(5),
-        .buck1_voltage1 = 1200000,
+        .buck1_voltage  = { 1200000, 1200000, 1200000, 1200000 },
-        .buck1_voltage2 = 1200000,
+        .buck2_voltage  = { 1200000, 1200000 },
-        .buck1_voltage3 = 1200000,
-        .buck1_voltage4 = 1200000,
-        .buck2_voltage1 = 1200000,
-        .buck2_voltage2 = 1200000,
 };
 #endif
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index 30b24ad84f49..e5cd9fbf19e9 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -580,12 +580,8 @@ static struct max8998_platform_data goni_max8998_pdata = {
        .buck1_set1     = S5PV210_GPH0(3),
        .buck1_set2     = S5PV210_GPH0(4),
        .buck2_set3     = S5PV210_GPH0(5),
-        .buck1_voltage1 = 1200000,
+        .buck1_voltage  = { 1200000, 1200000, 1200000, 1200000 },
-        .buck1_voltage2 = 1200000,
+        .buck2_voltage  = { 1200000, 1200000 },
-        .buck1_voltage3 = 1200000,
-        .buck1_voltage4 = 1200000,
-        .buck2_voltage1 = 1200000,
-        .buck2_voltage2 = 1200000,
 };
 #endif
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index 9db3e98e8b85..f25b6119e028 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -19,6 +19,7 @@
 #include <linux/cpufreq.h>
 #include <linux/ioport.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 #include <video/sa1100fb.h>
@@ -131,9 +132,9 @@ static void sa1100_power_off(void)
        PMCR = PMCR_SF;
 }
-void sa11x0_restart(char mode, const char *cmd)
+void sa11x0_restart(enum reboot_mode mode, const char *cmd)
 {
-        if (mode == 's') {
+        if (mode == REBOOT_SOFT) {
                /* Jump into ROM at address 0 */
                soft_restart(0);
        } else {
diff --git a/arch/arm/mach-sa1100/generic.h b/arch/arm/mach-sa1100/generic.h
index 2abc6a1f6e86..9a33695c9492 100644
--- a/arch/arm/mach-sa1100/generic.h
+++ b/arch/arm/mach-sa1100/generic.h
@@ -3,12 +3,13 @@
 *
 * Author: Nicolas Pitre
 */
+#include <linux/reboot.h>
 extern void sa1100_timer_init(void);
 extern void __init sa1100_map_io(void);
 extern void __init sa1100_init_irq(void);
 extern void __init sa1100_init_gpio(void);
-extern void sa11x0_restart(char, const char *);
+extern void sa11x0_restart(enum reboot_mode, const char *);
 extern void sa11x0_init_late(void);
 #define SET_BANK(__nr,__start,__size) \
diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c
index a59a13a665a6..713c86cd3d64 100644
--- a/arch/arm/mach-sa1100/time.c
+++ b/arch/arm/mach-sa1100/time.c
@@ -14,9 +14,9 @@
 #include <linux/irq.h>
 #include <linux/timex.h>
 #include <linux/clockchips.h>
+#include <linux/sched_clock.h>
 #include <asm/mach/time.h>
-#include <asm/sched_clock.h>
 #include <mach/hardware.h>
 #include <mach/irqs.h>
diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c
index 153555724988..1d32c5e8eab6 100644
--- a/arch/arm/mach-shark/core.c
+++ b/arch/arm/mach-shark/core.c
@@ -11,6 +11,7 @@
 #include <linux/serial_8250.h>
 #include <linux/io.h>
 #include <linux/cpu.h>
+#include <linux/reboot.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -24,7 +25,7 @@
 #define ROMCARD_SIZE            0x08000000
 #define ROMCARD_START           0x10000000
-static void shark_restart(char mode, const char *cmd)
+static void shark_restart(enum reboot_mode mode, const char *cmd)
 {
        short temp;
        /* Reset the Machine via pc[3] of the sequoia chipset */
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 1a517e2fe449..3912ce91fee4 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -23,7 +23,7 @@ config ARCH_R8A73A4
        select ARCH_WANT_OPTIONAL_GPIOLIB
        select ARM_GIC
        select CPU_V7
-        select ARM_ARCH_TIMER
+        select HAVE_ARM_ARCH_TIMER
        select SH_CLK_CPG
        select RENESAS_IRQC
@@ -36,10 +36,13 @@ config ARCH_R8A7740
        select RENESAS_INTC_IRQPIN
 config ARCH_R8A7778
-        bool "R-Car M1 (R8A77780)"
+        bool "R-Car M1A (R8A77781)"
+        select ARCH_WANT_OPTIONAL_GPIOLIB
        select CPU_V7
        select SH_CLK_CPG
        select ARM_GIC
+        select USB_ARCH_HAS_EHCI
+        select USB_ARCH_HAS_OHCI
 config ARCH_R8A7779
        bool "R-Car H1 (R8A77790)"
@@ -56,7 +59,7 @@ config ARCH_R8A7790
        select ARCH_WANT_OPTIONAL_GPIOLIB
        select ARM_GIC
        select CPU_V7
-        select ARM_ARCH_TIMER
+        select HAVE_ARM_ARCH_TIMER
        select SH_CLK_CPG
        select RENESAS_IRQC
@@ -68,27 +71,6 @@ config ARCH_EMEV2
 comment "SH-Mobile Board Type"
-config MACH_AP4EVB
-        bool "AP4EVB board"
-        depends on ARCH_SH7372
-        select ARCH_REQUIRE_GPIOLIB
-        select REGULATOR_FIXED_VOLTAGE if REGULATOR
-        select SH_LCD_MIPI_DSI
-        select SND_SOC_AK4642 if SND_SIMPLE_CARD
-choice
-        prompt "AP4EVB LCD panel selection"
-        default AP4EVB_QHD
-        depends on MACH_AP4EVB
-config AP4EVB_QHD
-        bool "MIPI-DSI QHD (960x540)"
-config AP4EVB_WVGA
-        bool "Parallel WVGA (800x480)"
-endchoice
 config MACH_AG5EVM
        bool "AG5EVM board"
        depends on ARCH_SH73A0
@@ -115,19 +97,27 @@ config MACH_KOTA2
        select ARCH_REQUIRE_GPIOLIB
        select REGULATOR_FIXED_VOLTAGE if REGULATOR
-config MACH_BONITO
+config MACH_ARMADILLO800EVA
-        bool "bonito board"
+        bool "Armadillo-800 EVA board"
        depends on ARCH_R8A7740
        select ARCH_REQUIRE_GPIOLIB
        select REGULATOR_FIXED_VOLTAGE if REGULATOR
+        select SND_SOC_WM8978 if SND_SIMPLE_CARD
+        select USE_OF
-config MACH_ARMADILLO800EVA
+config MACH_ARMADILLO800EVA_REFERENCE
-        bool "Armadillo-800 EVA board"
+        bool "Armadillo-800 EVA board - Reference Device Tree Implementation"
        depends on ARCH_R8A7740
        select ARCH_REQUIRE_GPIOLIB
        select REGULATOR_FIXED_VOLTAGE if REGULATOR
        select SND_SOC_WM8978 if SND_SIMPLE_CARD
        select USE_OF
+        ---help---
+           Use reference implementation of Aramdillo800 EVA board support
+           which makes a greater use of device tree at the expense
+           of not supporting a number of devices.
+           This is intended to aid developers
 config MACH_BOCKW
        bool "BOCK-W platform"
@@ -169,6 +159,8 @@ config MACH_KZM9D
 config MACH_KZM9G
        bool "KZM-A9-GT board"
        depends on ARCH_SH73A0
+        select ARCH_HAS_CPUFREQ
+        select ARCH_HAS_OPP
        select ARCH_REQUIRE_GPIOLIB
        select REGULATOR_FIXED_VOLTAGE if REGULATOR
        select SND_SOC_AK4642 if SND_SIMPLE_CARD
@@ -194,37 +186,6 @@ config CPU_HAS_INTEVT
        bool
        default y
-menu "Memory configuration"
-config MEMORY_START
-        hex "Physical memory start address"
-        default "0x40000000" if MACH_AP4EVB || MACH_AG5EVM || \
-                                MACH_MACKEREL || MACH_BONITO || \
-                                MACH_ARMADILLO800EVA || MACH_APE6EVM || \
-                                MACH_LAGER
-        default "0x41000000" if MACH_KOTA2
-        default "0x00000000"
-        ---help---
-          Tweak this only when porting to a new machine which does not
-          already have a defconfig. Changing it from the known correct
-          value on any of the known systems will only lead to disaster.
-config MEMORY_SIZE
-        hex "Physical memory size"
-        default "0x80000000" if MACH_LAGER
-        default "0x40000000" if MACH_APE6EVM
-        default "0x20000000" if MACH_AG5EVM || MACH_BONITO || \
-                                MACH_ARMADILLO800EVA
-        default "0x1e000000" if MACH_KOTA2
-        default "0x10000000" if MACH_AP4EVB || MACH_MACKEREL
-        default "0x04000000"
-        help
-          This sets the default memory size assumed by your kernel. It can
-          be overridden as normal by the 'mem=' argument on the kernel command
-          line.
-endmenu
 menu "Timer and clock configuration"
 config SHMOBILE_TIMER_HZ
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 068f1dadc46b..6165a517f580 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -35,17 +35,16 @@ obj-$(CONFIG_ARCH_R8A7779)	+= pm-r8a7779.o
 obj-$(CONFIG_ARCH_SH73A0)       += pm-sh73a0.o
 # Board objects
-obj-$(CONFIG_MACH_AP4EVB)       += board-ap4evb.o
 obj-$(CONFIG_MACH_AG5EVM)       += board-ag5evm.o
 obj-$(CONFIG_MACH_APE6EVM)      += board-ape6evm.o
 obj-$(CONFIG_MACH_MACKEREL)     += board-mackerel.o
 obj-$(CONFIG_MACH_KOTA2)        += board-kota2.o
-obj-$(CONFIG_MACH_BONITO)       += board-bonito.o
 obj-$(CONFIG_MACH_BOCKW)        += board-bockw.o
 obj-$(CONFIG_MACH_MARZEN)       += board-marzen.o
 obj-$(CONFIG_MACH_MARZEN_REFERENCE)     += board-marzen-reference.o
 obj-$(CONFIG_MACH_LAGER)        += board-lager.o
 obj-$(CONFIG_MACH_ARMADILLO800EVA)      += board-armadillo800eva.o
+obj-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE)    += board-armadillo800eva-reference.o
 obj-$(CONFIG_MACH_KZM9D)        += board-kzm9d.o
 obj-$(CONFIG_MACH_KZM9G)        += board-kzm9g.o
 obj-$(CONFIG_MACH_KZM9G_REFERENCE)      += board-kzm9g-reference.o
diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot
index 498efd99338d..84c6868580f0 100644
--- a/arch/arm/mach-shmobile/Makefile.boot
+++ b/arch/arm/mach-shmobile/Makefile.boot
@@ -1,6 +1,20 @@
-__ZRELADDR      := $(shell /bin/bash -c 'printf "0x%08x" \
+# per-board load address for uImage
-                     $$[$(CONFIG_MEMORY_START) + 0x8000]')
+loadaddr-y      :=
+loadaddr-$(CONFIG_MACH_AG5EVM) += 0x40008000
+loadaddr-$(CONFIG_MACH_APE6EVM) += 0x40008000
+loadaddr-$(CONFIG_MACH_ARMADILLO800EVA) += 0x40008000
+loadaddr-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += 0x40008000
+loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000
+loadaddr-$(CONFIG_MACH_KOTA2) += 0x41008000
+loadaddr-$(CONFIG_MACH_KZM9D) += 0x40008000
+loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000
+loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000
+loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000
+loadaddr-$(CONFIG_MACH_MACKEREL) += 0x40008000
+loadaddr-$(CONFIG_MACH_MARZEN) += 0x60008000
+loadaddr-$(CONFIG_MACH_MARZEN_REFERENCE) += 0x60008000
+__ZRELADDR      := $(sort $(loadaddr-y))
   zreladdr-y   += $(__ZRELADDR)
 # Unsupported legacy stuff
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
deleted file mode 100644
index 45f78cadec1d..000000000000
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ /dev/null
@@ -1,1332 +0,0 @@
-/*
- * AP4EVB board support
- *
- * Copyright (C) 2010  Magnus Damm
- * Copyright (C) 2008  Yoshihiro Shimoda
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#include <linux/clk.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/mfd/tmio.h>
-#include <linux/mmc/host.h>
-#include <linux/mmc/sh_mobile_sdhi.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mmc/sh_mmcif.h>
-#include <linux/i2c.h>
-#include <linux/i2c/tsc2007.h>
-#include <linux/io.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/machine.h>
-#include <linux/smsc911x.h>
-#include <linux/sh_intc.h>
-#include <linux/sh_clk.h>
-#include <linux/gpio.h>
-#include <linux/input.h>
-#include <linux/leds.h>
-#include <linux/input/sh_keysc.h>
-#include <linux/usb/r8a66597.h>
-#include <linux/pm_clock.h>
-#include <linux/dma-mapping.h>
-#include <media/sh_mobile_ceu.h>
-#include <media/sh_mobile_csi2.h>
-#include <media/soc_camera.h>
-#include <sound/sh_fsi.h>
-#include <sound/simple_card.h>
-#include <video/sh_mobile_hdmi.h>
-#include <video/sh_mobile_lcdc.h>
-#include <video/sh_mipi_dsi.h>
-#include <mach/common.h>
-#include <mach/irqs.h>
-#include <mach/sh7372.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/setup.h>
-#include "sh-gpio.h"
-/*
- * Address      Interface               BusWidth        note
- * ------------------------------------------------------------------
- * 0x0000_0000  NOR Flash ROM (MCP)     16bit           SW7 : bit1 = ON
- * 0x0800_0000  user area               -
- * 0x1000_0000  NOR Flash ROM (MCP)     16bit           SW7 : bit1 = OFF
- * 0x1400_0000  Ether (LAN9220)         16bit
- * 0x1600_0000  user area               -               cannot use with NAND
- * 0x1800_0000  user area               -
- * 0x1A00_0000  -
- * 0x4000_0000  LPDDR2-SDRAM (POP)      32bit
- */
-/*
- * NOR Flash ROM
- *
- *  SW1  |     SW2    | SW7  | NOR Flash ROM
- *  bit1 | bit1  bit2 | bit1 | Memory allocation
- * ------+------------+------+------------------
- *  OFF  | ON     OFF | ON   |    Area 0
- *  OFF  | ON     OFF | OFF  |    Area 4
- */
-/*
- * NAND Flash ROM
- *
- *  SW1  |     SW2    | SW7  | NAND Flash ROM
- *  bit1 | bit1  bit2 | bit2 | Memory allocation
- * ------+------------+------+------------------
- *  OFF  | ON     OFF | ON   |    FCE 0
- *  OFF  | ON     OFF | OFF  |    FCE 1
- */
-/*
- * SMSC 9220
- *
- *  SW1         SMSC 9220
- * -----------------------
- *  ON          access disable
- *  OFF         access enable
- */
-/*
- * LCD / IRQ / KEYSC / IrDA
- *
- * IRQ = IRQ26 (TS), IRQ27 (VIO), IRQ28 (QHD-TouchScreen)
- * LCD = 2nd LCDC (WVGA)
- *
- *              |               SW43                    |
- * SW3          |       ON              |       OFF     |
- * -------------+-----------------------+---------------+
- * ON           | KEY / IrDA            | LCD           |
- * OFF          | KEY / IrDA / IRQ      | IRQ           |
- *
- *
- * QHD / WVGA display
- *
- * You can choice display type on menuconfig.
- * Then, check above dip-switch.
- */
-/*
- * USB
- *
- * J7 : 1-2  MAX3355E VBUS
- *      2-3  DC 5.0V
- *
- * S39: bit2: off
- */
-/*
- * FSI/FSMI
- *
- * SW41 :  ON : SH-Mobile AP4 Audio Mode
- *      : OFF : Bluetooth Audio Mode
- *
- * it needs amixer settings for playing
- *
- * amixer set "Headphone Enable" on
- */
-/*
- * MMC0/SDHI1 (CN7)
- *
- * J22 : select card voltage
- *       1-2 pin : 1.8v
- *       2-3 pin : 3.3v
- *
- *        SW1  |             SW33
- *             | bit1 | bit2 | bit3 | bit4
- * ------------+------+------+------+-------
- * MMC0   OFF  |  OFF |  ON  |  ON  |  X
- * SDHI1  OFF  |  ON  |   X  |  OFF | ON
- *
- * voltage lebel
- * CN7 : 1.8v
- * CN12: 3.3v
- */
-/* Dummy supplies, where voltage doesn't matter */
-static struct regulator_consumer_supply fixed1v8_power_consumers[] =
-{
-        /* J22 default position: 1.8V */
-        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
-        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
-        REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"),
-        REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"),
-};
-static struct regulator_consumer_supply fixed3v3_power_consumers[] =
-{
-        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
-        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
-};
-static struct regulator_consumer_supply dummy_supplies[] = {
-        REGULATOR_SUPPLY("vddvario", "smsc911x"),
-        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
-};
-/* MTD */
-static struct mtd_partition nor_flash_partitions[] = {
-        {
-                .name           = "loader",
-                .offset         = 0x00000000,
-                .size           = 512 * 1024,
-                .mask_flags     = MTD_WRITEABLE,
-        },
-        {
-                .name           = "bootenv",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = 512 * 1024,
-                .mask_flags     = MTD_WRITEABLE,
-        },
-        {
-                .name           = "kernel_ro",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = 8 * 1024 * 1024,
-                .mask_flags     = MTD_WRITEABLE,
-        },
-        {
-                .name           = "kernel",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = 8 * 1024 * 1024,
-        },
-        {
-                .name           = "data",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = MTDPART_SIZ_FULL,
-        },
-};
-static struct physmap_flash_data nor_flash_data = {
-        .width          = 2,
-        .parts          = nor_flash_partitions,
-        .nr_parts       = ARRAY_SIZE(nor_flash_partitions),
-};
-static struct resource nor_flash_resources[] = {
-        [0]     = {
-                .start  = 0x20000000, /* CS0 shadow instead of regular CS0 */
-                .end    = 0x28000000 - 1, /* needed by USB MASK ROM boot */
-                .flags  = IORESOURCE_MEM,
-        }
-};
-static struct platform_device nor_flash_device = {
-        .name           = "physmap-flash",
-        .dev            = {
-                .platform_data  = &nor_flash_data,
-        },
-        .num_resources  = ARRAY_SIZE(nor_flash_resources),
-        .resource       = nor_flash_resources,
-};
-/* SMSC 9220 */
-static struct resource smc911x_resources[] = {
-        {
-                .start  = 0x14000000,
-                .end    = 0x16000000 - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = evt2irq(0x02c0) /* IRQ6A */,
-                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
-        },
-};
-static struct smsc911x_platform_config smsc911x_info = {
-        .flags          = SMSC911X_USE_16BIT | SMSC911X_SAVE_MAC_ADDRESS,
-        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
-};
-static struct platform_device smc911x_device = {
-        .name           = "smsc911x",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(smc911x_resources),
-        .resource       = smc911x_resources,
-        .dev            = {
-                .platform_data = &smsc911x_info,
-        },
-};
-/*
- * The card detect pin of the top SD/MMC slot (CN7) is active low and is
- * connected to GPIO A22 of SH7372 (GPIO 41).
- */
-static int slot_cn7_get_cd(struct platform_device *pdev)
-{
-        return !gpio_get_value(41);
-}
-/* MERAM */
-static struct sh_mobile_meram_info meram_info = {
-        .addr_mode      = SH_MOBILE_MERAM_MODE1,
-};
-static struct resource meram_resources[] = {
-        [0] = {
-                .name   = "regs",
-                .start  = 0xe8000000,
-                .end    = 0xe807ffff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .name   = "meram",
-                .start  = 0xe8080000,
-                .end    = 0xe81fffff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device meram_device = {
-        .name           = "sh_mobile_meram",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(meram_resources),
-        .resource       = meram_resources,
-        .dev            = {
-                .platform_data = &meram_info,
-        },
-};
-/* SH_MMCIF */
-static struct resource sh_mmcif_resources[] = {
-        [0] = {
-                .name   = "MMCIF",
-                .start  = 0xE6BD0000,
-                .end    = 0xE6BD00FF,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                /* MMC ERR */
-                .start  = evt2irq(0x1ac0),
-                .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
-                /* MMC NOR */
-                .start  = evt2irq(0x1ae0),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct sh_mmcif_plat_data sh_mmcif_plat = {
-        .sup_pclk       = 0,
-        .ocr            = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
-        .caps           = MMC_CAP_4_BIT_DATA |
-                          MMC_CAP_8_BIT_DATA |
-                          MMC_CAP_NEEDS_POLL,
-        .get_cd         = slot_cn7_get_cd,
-        .slave_id_tx    = SHDMA_SLAVE_MMCIF_TX,
-        .slave_id_rx    = SHDMA_SLAVE_MMCIF_RX,
-};
-static struct platform_device sh_mmcif_device = {
-        .name           = "sh_mmcif",
-        .id             = 0,
-        .dev            = {
-                .dma_mask               = NULL,
-                .coherent_dma_mask      = 0xffffffff,
-                .platform_data          = &sh_mmcif_plat,
-        },
-        .num_resources  = ARRAY_SIZE(sh_mmcif_resources),
-        .resource       = sh_mmcif_resources,
-};
-/* SDHI0 */
-static struct sh_mobile_sdhi_info sdhi0_info = {
-        .dma_slave_tx   = SHDMA_SLAVE_SDHI0_TX,
-        .dma_slave_rx   = SHDMA_SLAVE_SDHI0_RX,
-        .tmio_caps      = MMC_CAP_SDIO_IRQ,
-};
-static struct resource sdhi0_resources[] = {
-        [0] = {
-                .name   = "SDHI0",
-                .start  = 0xe6850000,
-                .end    = 0xe68500ff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = evt2irq(0x0e00) /* SDHI0_SDHI0I0 */,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
-                .start  = evt2irq(0x0e20) /* SDHI0_SDHI0I1 */,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [3] = {
-                .start  = evt2irq(0x0e40) /* SDHI0_SDHI0I2 */,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device sdhi0_device = {
-        .name           = "sh_mobile_sdhi",
-        .num_resources  = ARRAY_SIZE(sdhi0_resources),
-        .resource       = sdhi0_resources,
-        .id             = 0,
-        .dev    = {
-                .platform_data  = &sdhi0_info,
-        },
-};
-/* SDHI1 */
-static struct sh_mobile_sdhi_info sdhi1_info = {
-        .dma_slave_tx   = SHDMA_SLAVE_SDHI1_TX,
-        .dma_slave_rx   = SHDMA_SLAVE_SDHI1_RX,
-        .tmio_ocr_mask  = MMC_VDD_165_195,
-        .tmio_flags     = TMIO_MMC_WRPROTECT_DISABLE,
-        .tmio_caps      = MMC_CAP_NEEDS_POLL | MMC_CAP_SDIO_IRQ,
-        .get_cd         = slot_cn7_get_cd,
-};
-static struct resource sdhi1_resources[] = {
-        [0] = {
-                .name   = "SDHI1",
-                .start  = 0xe6860000,
-                .end    = 0xe68600ff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = evt2irq(0x0e80), /* SDHI1_SDHI1I0 */
-                .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
-                .start  = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */
-                .flags  = IORESOURCE_IRQ,
-        },
-        [3] = {
-                .start  = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device sdhi1_device = {
-        .name           = "sh_mobile_sdhi",
-        .num_resources  = ARRAY_SIZE(sdhi1_resources),
-        .resource       = sdhi1_resources,
-        .id             = 1,
-        .dev    = {
-                .platform_data  = &sdhi1_info,
-        },
-};
-/* USB1 */
-static void usb1_host_port_power(int port, int power)
-{
-        if (!power) /* only power-on supported for now */
-                return;
-        /* set VBOUT/PWEN and EXTLP1 in DVSTCTR */
-        __raw_writew(__raw_readw(IOMEM(0xE68B0008)) | 0x600, IOMEM(0xE68B0008));
-}
-static struct r8a66597_platdata usb1_host_data = {
-        .on_chip        = 1,
-        .port_power     = usb1_host_port_power,
-};
-static struct resource usb1_host_resources[] = {
-        [0] = {
-                .name   = "USBHS",
-                .start  = 0xE68B0000,
-                .end    = 0xE68B00E6 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = evt2irq(0x1ce0) /* USB1_USB1I0 */,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device usb1_host_device = {
-        .name   = "r8a66597_hcd",
-        .id     = 1,
-        .dev = {
-                .dma_mask               = NULL,         /*  not use dma */
-                .coherent_dma_mask      = 0xffffffff,
-                .platform_data          = &usb1_host_data,
-        },
-        .num_resources  = ARRAY_SIZE(usb1_host_resources),
-        .resource       = usb1_host_resources,
-};
-/*
- * QHD display
- */
-#ifdef CONFIG_AP4EVB_QHD
-/* KEYSC (Needs SW43 set to ON) */
-static struct sh_keysc_info keysc_info = {
-        .mode           = SH_KEYSC_MODE_1,
-        .scan_timing    = 3,
-        .delay          = 2500,
-        .keycodes = {
-                KEY_0, KEY_1, KEY_2, KEY_3, KEY_4,
-                KEY_5, KEY_6, KEY_7, KEY_8, KEY_9,
-                KEY_A, KEY_B, KEY_C, KEY_D, KEY_E,
-                KEY_F, KEY_G, KEY_H, KEY_I, KEY_J,
-                KEY_K, KEY_L, KEY_M, KEY_N, KEY_O,
-        },
-};
-static struct resource keysc_resources[] = {
-        [0] = {
-                .name   = "KEYSC",
-                .start  = 0xe61b0000,
-                .end    = 0xe61b0063,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = evt2irq(0x0be0), /* KEYSC_KEY */
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device keysc_device = {
-        .name           = "sh_keysc",
-        .id             = 0, /* "keysc0" clock */
-        .num_resources  = ARRAY_SIZE(keysc_resources),
-        .resource       = keysc_resources,
-        .dev    = {
-                .platform_data  = &keysc_info,
-        },
-};
-/* MIPI-DSI */
-static int sh_mipi_set_dot_clock(struct platform_device *pdev,
-                                 void __iomem *base,
-                                 int enable)
-{
-        struct clk *pck = clk_get(&pdev->dev, "dsip_clk");
-        if (IS_ERR(pck))
-                return PTR_ERR(pck);
-        if (enable) {
-                /*
-                 * DSIPCLK      = 24MHz
-                 * D-PHY        = DSIPCLK * ((0x6*2)+1) = 312MHz (see .phyctrl)
-                 * HsByteCLK    = D-PHY/8 = 39MHz
-                 *
-                 *  X * Y * FPS =
-                 * (544+72+600+16) * (961+8+8+2) * 30 = 36.1MHz
-                 */
-                clk_set_rate(pck, clk_round_rate(pck, 24000000));
-                clk_enable(pck);
-        } else {
-                clk_disable(pck);
-        }
-        clk_put(pck);
-        return 0;
-}
-static struct resource mipidsi0_resources[] = {
-        [0] = {
-                .start  = 0xffc60000,
-                .end    = 0xffc63073,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = 0xffc68000,
-                .end    = 0xffc680ef,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct sh_mipi_dsi_info mipidsi0_info = {
-        .data_format    = MIPI_RGB888,
-        .channel        = LCDC_CHAN_MAINLCD,
-        .lane           = 2,
-        .vsynw_offset   = 17,
-        .phyctrl        = 0x6 << 8,
-        .flags          = SH_MIPI_DSI_SYNC_PULSES_MODE |
-                          SH_MIPI_DSI_HSbyteCLK,
-        .set_dot_clock  = sh_mipi_set_dot_clock,
-};
-static struct platform_device mipidsi0_device = {
-        .name           = "sh-mipi-dsi",
-        .num_resources  = ARRAY_SIZE(mipidsi0_resources),
-        .resource       = mipidsi0_resources,
-        .id             = 0,
-        .dev    = {
-                .platform_data  = &mipidsi0_info,
-        },
-};
-static struct platform_device *qhd_devices[] __initdata = {
-        &mipidsi0_device,
-        &keysc_device,
-};
-#endif /* CONFIG_AP4EVB_QHD */
-/* LCDC0 */
-static const struct fb_videomode ap4evb_lcdc_modes[] = {
-        {
-#ifdef CONFIG_AP4EVB_QHD
-                .name           = "R63302(QHD)",
-                .xres           = 544,
-                .yres           = 961,
-                .left_margin    = 72,
-                .right_margin   = 600,
-                .hsync_len      = 16,
-                .upper_margin   = 8,
-                .lower_margin   = 8,
-                .vsync_len      = 2,
-                .sync           = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
-#else
-                .name           = "WVGA Panel",
-                .xres           = 800,
-                .yres           = 480,
-                .left_margin    = 220,
-                .right_margin   = 110,
-                .hsync_len      = 70,
-                .upper_margin   = 20,
-                .lower_margin   = 5,
-                .vsync_len      = 5,
-                .sync           = 0,
-#endif
-        },
-};
-static const struct sh_mobile_meram_cfg lcd_meram_cfg = {
-        .icb[0] = {
-                .meram_size     = 0x40,
-        },
-        .icb[1] = {
-                .meram_size     = 0x40,
-        },
-};
-static struct sh_mobile_lcdc_info lcdc_info = {
-        .meram_dev = &meram_info,
-        .ch[0] = {
-                .chan = LCDC_CHAN_MAINLCD,
-                .fourcc = V4L2_PIX_FMT_RGB565,
-                .lcd_modes = ap4evb_lcdc_modes,
-                .num_modes = ARRAY_SIZE(ap4evb_lcdc_modes),
-                .meram_cfg = &lcd_meram_cfg,
-#ifdef CONFIG_AP4EVB_QHD
-                .tx_dev = &mipidsi0_device,
-#endif
-        }
-};
-static struct resource lcdc_resources[] = {
-        [0] = {
-                .name   = "LCDC",
-                .start  = 0xfe940000, /* P4-only space */
-                .end    = 0xfe943fff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = intcs_evt2irq(0x580),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device lcdc_device = {
-        .name           = "sh_mobile_lcdc_fb",
-        .num_resources  = ARRAY_SIZE(lcdc_resources),
-        .resource       = lcdc_resources,
-        .dev    = {
-                .platform_data  = &lcdc_info,
-                .coherent_dma_mask = ~0,
-        },
-};
-/* FSI */
-#define IRQ_FSI         evt2irq(0x1840)
-static struct sh_fsi_platform_info fsi_info = {
-        .port_b = {
-                .flags          = SH_FSI_CLK_CPG |
-                                  SH_FSI_FMT_SPDIF,
-        },
-};
-static struct resource fsi_resources[] = {
-        [0] = {
-                .name   = "FSI",
-                .start  = 0xFE3C0000,
-                .end    = 0xFE3C0400 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_FSI,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device fsi_device = {
-        .name           = "sh_fsi2",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(fsi_resources),
-        .resource       = fsi_resources,
-        .dev    = {
-                .platform_data  = &fsi_info,
-        },
-};
-static struct asoc_simple_card_info fsi2_ak4643_info = {
-        .name           = "AK4643",
-        .card           = "FSI2A-AK4643",
-        .codec          = "ak4642-codec.0-0013",
-        .platform       = "sh_fsi2",
-        .daifmt         = SND_SOC_DAIFMT_LEFT_J,
-        .cpu_dai = {
-                .name   = "fsia-dai",
-                .fmt    = SND_SOC_DAIFMT_CBS_CFS,
-        },
-        .codec_dai = {
-                .name   = "ak4642-hifi",
-                .fmt    = SND_SOC_DAIFMT_CBM_CFM,
-                .sysclk = 11289600,
-        },
-};
-static struct platform_device fsi_ak4643_device = {
-        .name   = "asoc-simple-card",
-        .dev    = {
-                .platform_data  = &fsi2_ak4643_info,
-        },
-};
-/* LCDC1 */
-static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
-                                unsigned long *parent_freq);
-static struct sh_mobile_hdmi_info hdmi_info = {
-        .flags = HDMI_SND_SRC_SPDIF,
-        .clk_optimize_parent = ap4evb_clk_optimize,
-};
-static struct resource hdmi_resources[] = {
-        [0] = {
-                .name   = "HDMI",
-                .start  = 0xe6be0000,
-                .end    = 0xe6be00ff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                /* There's also an HDMI interrupt on INTCS @ 0x18e0 */
-                .start  = evt2irq(0x17e0),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device hdmi_device = {
-        .name           = "sh-mobile-hdmi",
-        .num_resources  = ARRAY_SIZE(hdmi_resources),
-        .resource       = hdmi_resources,
-        .id             = -1,
-        .dev    = {
-                .platform_data  = &hdmi_info,
-        },
-};
-static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
-                                unsigned long *parent_freq)
-{
-        struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick");
-        long error;
-        if (IS_ERR(hdmi_ick)) {
-                int ret = PTR_ERR(hdmi_ick);
-                pr_err("Cannot get HDMI ICK: %d\n", ret);
-                return ret;
-        }
-        error = clk_round_parent(hdmi_ick, target, best_freq, parent_freq, 1, 64);
-        clk_put(hdmi_ick);
-        return error;
-}
-static const struct sh_mobile_meram_cfg hdmi_meram_cfg = {
-        .icb[0] = {
-                .meram_size     = 0x100,
-        },
-        .icb[1] = {
-                .meram_size     = 0x100,
-        },
-};
-static struct sh_mobile_lcdc_info sh_mobile_lcdc1_info = {
-        .clock_source = LCDC_CLK_EXTERNAL,
-        .meram_dev = &meram_info,
-        .ch[0] = {
-                .chan = LCDC_CHAN_MAINLCD,
-                .fourcc = V4L2_PIX_FMT_RGB565,
-                .interface_type = RGB24,
-                .clock_divider = 1,
-                .flags = LCDC_FLAGS_DWPOL,
-                .meram_cfg = &hdmi_meram_cfg,
-                .tx_dev = &hdmi_device,
-        }
-};
-static struct resource lcdc1_resources[] = {
-        [0] = {
-                .name   = "LCDC1",
-                .start  = 0xfe944000,
-                .end    = 0xfe947fff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = intcs_evt2irq(0x1780),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device lcdc1_device = {
-        .name           = "sh_mobile_lcdc_fb",
-        .num_resources  = ARRAY_SIZE(lcdc1_resources),
-        .resource       = lcdc1_resources,
-        .id             = 1,
-        .dev    = {
-                .platform_data  = &sh_mobile_lcdc1_info,
-                .coherent_dma_mask = ~0,
-        },
-};
-static struct asoc_simple_card_info fsi2_hdmi_info = {
-        .name           = "HDMI",
-        .card           = "FSI2B-HDMI",
-        .codec          = "sh-mobile-hdmi",
-        .platform       = "sh_fsi2",
-        .cpu_dai = {
-                .name   = "fsib-dai",
-                .fmt    = SND_SOC_DAIFMT_CBM_CFM | SND_SOC_DAIFMT_IB_NF,
-        },
-        .codec_dai = {
-                .name   = "sh_mobile_hdmi-hifi",
-        },
-};
-static struct platform_device fsi_hdmi_device = {
-        .name   = "asoc-simple-card",
-        .id     = 1,
-        .dev    = {
-                .platform_data  = &fsi2_hdmi_info,
-        },
-};
-static struct gpio_led ap4evb_leds[] = {
-        {
-                .name                   = "led4",
-                .gpio                   = 185,
-                .default_state  = LEDS_GPIO_DEFSTATE_ON,
-        },
-        {
-                .name                   = "led2",
-                .gpio                   = 186,
-                .default_state  = LEDS_GPIO_DEFSTATE_ON,
-        },
-        {
-                .name                   = "led3",
-                .gpio                   = 187,
-                .default_state  = LEDS_GPIO_DEFSTATE_ON,
-        },
-        {
-                .name                   = "led1",
-                .gpio                   = 188,
-                .default_state  = LEDS_GPIO_DEFSTATE_ON,
-        }
-};
-static struct gpio_led_platform_data ap4evb_leds_pdata = {
-        .num_leds = ARRAY_SIZE(ap4evb_leds),
-        .leds = ap4evb_leds,
-};
-static struct platform_device leds_device = {
-        .name = "leds-gpio",
-        .id = 0,
-        .dev = {
-                .platform_data  = &ap4evb_leds_pdata,
-        },
-};
-static struct i2c_board_info imx074_info = {
-        I2C_BOARD_INFO("imx074", 0x1a),
-};
-static struct soc_camera_link imx074_link = {
-        .bus_id         = 0,
-        .board_info     = &imx074_info,
-        .i2c_adapter_id = 0,
-        .module_name    = "imx074",
-};
-static struct platform_device ap4evb_camera = {
-        .name   = "soc-camera-pdrv",
-        .id     = 0,
-        .dev    = {
-                .platform_data = &imx074_link,
-        },
-};
-static struct sh_csi2_client_config csi2_clients[] = {
-        {
-                .phy            = SH_CSI2_PHY_MAIN,
-                .lanes          = 0,            /* default: 2 lanes */
-                .channel        = 0,
-                .pdev           = &ap4evb_camera,
-        },
-};
-static struct sh_csi2_pdata csi2_info = {
-        .type           = SH_CSI2C,
-        .clients        = csi2_clients,
-        .num_clients    = ARRAY_SIZE(csi2_clients),
-        .flags          = SH_CSI2_ECC | SH_CSI2_CRC,
-};
-static struct resource csi2_resources[] = {
-        [0] = {
-                .name   = "CSI2",
-                .start  = 0xffc90000,
-                .end    = 0xffc90fff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = intcs_evt2irq(0x17a0),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct sh_mobile_ceu_companion csi2 = {
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(csi2_resources),
-        .resource       = csi2_resources,
-        .platform_data  = &csi2_info,
-};
-static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
-        .flags = SH_CEU_FLAG_USE_8BIT_BUS,
-        .max_width = 8188,
-        .max_height = 8188,
-        .csi2 = &csi2,
-};
-static struct resource ceu_resources[] = {
-        [0] = {
-                .name   = "CEU",
-                .start  = 0xfe910000,
-                .end    = 0xfe91009f,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = intcs_evt2irq(0x880),
-                .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
-                /* place holder for contiguous memory */
-        },
-};
-static struct platform_device ceu_device = {
-        .name           = "sh_mobile_ceu",
-        .id             = 0, /* "ceu0" clock */
-        .num_resources  = ARRAY_SIZE(ceu_resources),
-        .resource       = ceu_resources,
-        .dev    = {
-                .platform_data          = &sh_mobile_ceu_info,
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-static struct platform_device *ap4evb_devices[] __initdata = {
-        &leds_device,
-        &nor_flash_device,
-        &smc911x_device,
-        &sdhi0_device,
-        &sdhi1_device,
-        &usb1_host_device,
-        &fsi_device,
-        &fsi_ak4643_device,
-        &fsi_hdmi_device,
-        &sh_mmcif_device,
-        &hdmi_device,
-        &lcdc_device,
-        &lcdc1_device,
-        &ceu_device,
-        &ap4evb_camera,
-        &meram_device,
-};
-static void __init hdmi_init_pm_clock(void)
-{
-        struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick");
-        int ret;
-        long rate;
-        if (IS_ERR(hdmi_ick)) {
-                ret = PTR_ERR(hdmi_ick);
-                pr_err("Cannot get HDMI ICK: %d\n", ret);
-                goto out;
-        }
-        ret = clk_set_parent(&sh7372_pllc2_clk, &sh7372_dv_clki_div2_clk);
-        if (ret < 0) {
-                pr_err("Cannot set PLLC2 parent: %d, %d users\n", ret, sh7372_pllc2_clk.usecount);
-                goto out;
-        }
-        pr_debug("PLLC2 initial frequency %lu\n", clk_get_rate(&sh7372_pllc2_clk));
-        rate = clk_round_rate(&sh7372_pllc2_clk, 594000000);
-        if (rate < 0) {
-                pr_err("Cannot get suitable rate: %ld\n", rate);
-                ret = rate;
-                goto out;
-        }
-        ret = clk_set_rate(&sh7372_pllc2_clk, rate);
-        if (ret < 0) {
-                pr_err("Cannot set rate %ld: %d\n", rate, ret);
-                goto out;
-        }
-        pr_debug("PLLC2 set frequency %lu\n", rate);
-        ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk);
-        if (ret < 0)
-                pr_err("Cannot set HDMI parent: %d\n", ret);
-out:
-        if (!IS_ERR(hdmi_ick))
-                clk_put(hdmi_ick);
-}
-/* TouchScreen */
-#ifdef CONFIG_AP4EVB_QHD
-# define GPIO_TSC_IRQ   GPIO_FN_IRQ28_123
-# define GPIO_TSC_PORT  123
-#else /* WVGA */
-# define GPIO_TSC_IRQ   GPIO_FN_IRQ7_40
-# define GPIO_TSC_PORT  40
-#endif
-#define IRQ28   evt2irq(0x3380) /* IRQ28A */
-#define IRQ7    evt2irq(0x02e0) /* IRQ7A */
-static int ts_get_pendown_state(void)
-{
-        int val;
-        gpio_free(GPIO_TSC_IRQ);
-        gpio_request_one(GPIO_TSC_PORT, GPIOF_IN, NULL);
-        val = gpio_get_value(GPIO_TSC_PORT);
-        gpio_request(GPIO_TSC_IRQ, NULL);
-        return !val;
-}
-static int ts_init(void)
-{
-        gpio_request(GPIO_TSC_IRQ, NULL);
-        return 0;
-}
-static struct tsc2007_platform_data tsc2007_info = {
-        .model                  = 2007,
-        .x_plate_ohms           = 180,
-        .get_pendown_state      = ts_get_pendown_state,
-        .init_platform_hw       = ts_init,
-};
-static struct i2c_board_info tsc_device = {
-        I2C_BOARD_INFO("tsc2007", 0x48),
-        .type           = "tsc2007",
-        .platform_data  = &tsc2007_info,
-        /*.irq is selected on ap4evb_init */
-};
-/* I2C */
-static struct i2c_board_info i2c0_devices[] = {
-        {
-                I2C_BOARD_INFO("ak4643", 0x13),
-        },
-};
-static struct i2c_board_info i2c1_devices[] = {
-        {
-                I2C_BOARD_INFO("r2025sd", 0x32),
-        },
-};
-static const struct pinctrl_map ap4evb_pinctrl_map[] = {
-        /* MMCIF */
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
-                                  "mmc0_data8_0", "mmc0"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
-                                  "mmc0_ctrl_0", "mmc0"),
-        /* SDHI0 */
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
-                                  "sdhi0_data4", "sdhi0"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
-                                  "sdhi0_ctrl", "sdhi0"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
-                                  "sdhi0_cd", "sdhi0"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
-                                  "sdhi0_wp", "sdhi0"),
-        /* SDHI1 */
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
-                                  "sdhi1_data4", "sdhi1"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
-                                  "sdhi1_ctrl", "sdhi1"),
-};
-#define GPIO_PORT9CR    IOMEM(0xE6051009)
-#define GPIO_PORT10CR   IOMEM(0xE605100A)
-#define USCCR1          IOMEM(0xE6058144)
-static void __init ap4evb_init(void)
-{
-        struct pm_domain_device domain_devices[] = {
-                { "A4LC", &lcdc1_device, },
-                { "A4LC", &lcdc_device, },
-                { "A4MP", &fsi_device, },
-                { "A3SP", &sh_mmcif_device, },
-                { "A3SP", &sdhi0_device, },
-                { "A3SP", &sdhi1_device, },
-                { "A4R", &ceu_device, },
-        };
-        u32 srcr4;
-        struct clk *clk;
-        regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
-                                     ARRAY_SIZE(fixed1v8_power_consumers), 1800000);
-        regulator_register_always_on(1, "fixed-3.3V", fixed3v3_power_consumers,
-                                     ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
-        regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies));
-        /* External clock source */
-        clk_set_rate(&sh7372_dv_clki_clk, 27000000);
-        pinctrl_register_mappings(ap4evb_pinctrl_map,
-                                  ARRAY_SIZE(ap4evb_pinctrl_map));
-        sh7372_pinmux_init();
-        /* enable SCIFA0 */
-        gpio_request(GPIO_FN_SCIFA0_TXD, NULL);
-        gpio_request(GPIO_FN_SCIFA0_RXD, NULL);
-        /* enable SMSC911X */
-        gpio_request(GPIO_FN_CS5A,      NULL);
-        gpio_request(GPIO_FN_IRQ6_39,   NULL);
-        /* enable Debug switch (S6) */
-        gpio_request_one(32, GPIOF_IN | GPIOF_EXPORT, NULL);
-        gpio_request_one(33, GPIOF_IN | GPIOF_EXPORT, NULL);
-        gpio_request_one(34, GPIOF_IN | GPIOF_EXPORT, NULL);
-        gpio_request_one(35, GPIOF_IN | GPIOF_EXPORT, NULL);
-        /* USB enable */
-        gpio_request(GPIO_FN_VBUS0_1,    NULL);
-        gpio_request(GPIO_FN_IDIN_1_18,  NULL);
-        gpio_request(GPIO_FN_PWEN_1_115, NULL);
-        gpio_request(GPIO_FN_OVCN_1_114, NULL);
-        gpio_request(GPIO_FN_EXTLP_1,    NULL);
-        gpio_request(GPIO_FN_OVCN2_1,    NULL);
-        /* setup USB phy */
-        __raw_writew(0x8a0a, IOMEM(0xE6058130));        /* USBCR4 */
-        /* enable FSI2 port A (ak4643) */
-        gpio_request(GPIO_FN_FSIAIBT,   NULL);
-        gpio_request(GPIO_FN_FSIAILR,   NULL);
-        gpio_request(GPIO_FN_FSIAISLD,  NULL);
-        gpio_request(GPIO_FN_FSIAOSLD,  NULL);
-        gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
-        gpio_request(9, NULL);
-        gpio_request(10, NULL);
-        gpio_direction_none(GPIO_PORT9CR);  /* FSIAOBT needs no direction */
-        gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */
-        /* card detect pin for MMC slot (CN7) */
-        gpio_request_one(41, GPIOF_IN, NULL);
-        /* setup FSI2 port B (HDMI) */
-        gpio_request(GPIO_FN_FSIBCK, NULL);
-        __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */
-        /* set SPU2 clock to 119.6 MHz */
-        clk = clk_get(NULL, "spu_clk");
-        if (!IS_ERR(clk)) {
-                clk_set_rate(clk, clk_round_rate(clk, 119600000));
-                clk_put(clk);
-        }
-        /*
-         * set irq priority, to avoid sound chopping
-         * when NFS rootfs is used
-         *  FSI(3) > SMSC911X(2)
-         */
-        intc_set_priority(IRQ_FSI, 3);
-        i2c_register_board_info(0, i2c0_devices,
-                                ARRAY_SIZE(i2c0_devices));
-        i2c_register_board_info(1, i2c1_devices,
-                                ARRAY_SIZE(i2c1_devices));
-#ifdef CONFIG_AP4EVB_QHD
-        /*
-         * For QHD Panel (MIPI-DSI, CONFIG_AP4EVB_QHD=y) and
-         * IRQ28 for Touch Panel, set dip switches S3, S43 as OFF, ON.
-         */
-        /* enable KEYSC */
-        gpio_request(GPIO_FN_KEYOUT0, NULL);
-        gpio_request(GPIO_FN_KEYOUT1, NULL);
-        gpio_request(GPIO_FN_KEYOUT2, NULL);
-        gpio_request(GPIO_FN_KEYOUT3, NULL);
-        gpio_request(GPIO_FN_KEYOUT4, NULL);
-        gpio_request(GPIO_FN_KEYIN0_136, NULL);
-        gpio_request(GPIO_FN_KEYIN1_135, NULL);
-        gpio_request(GPIO_FN_KEYIN2_134, NULL);
-        gpio_request(GPIO_FN_KEYIN3_133, NULL);
-        gpio_request(GPIO_FN_KEYIN4,     NULL);
-        /* enable TouchScreen */
-        irq_set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW);
-        tsc_device.irq = IRQ28;
-        i2c_register_board_info(1, &tsc_device, 1);
-        /* LCDC0 */
-        lcdc_info.clock_source                  = LCDC_CLK_PERIPHERAL;
-        lcdc_info.ch[0].interface_type          = RGB24;
-        lcdc_info.ch[0].clock_divider           = 1;
-        lcdc_info.ch[0].flags                   = LCDC_FLAGS_DWPOL;
-        lcdc_info.ch[0].panel_cfg.width         = 44;
-        lcdc_info.ch[0].panel_cfg.height        = 79;
-        platform_add_devices(qhd_devices, ARRAY_SIZE(qhd_devices));
-#else
-        /*
-         * For WVGA Panel (18-bit RGB, CONFIG_AP4EVB_WVGA=y) and
-         * IRQ7 for Touch Panel, set dip switches S3, S43 to ON, OFF.
-         */
-        gpio_request(GPIO_FN_LCDD17,   NULL);
-        gpio_request(GPIO_FN_LCDD16,   NULL);
-        gpio_request(GPIO_FN_LCDD15,   NULL);
-        gpio_request(GPIO_FN_LCDD14,   NULL);
-        gpio_request(GPIO_FN_LCDD13,   NULL);
-        gpio_request(GPIO_FN_LCDD12,   NULL);
-        gpio_request(GPIO_FN_LCDD11,   NULL);
-        gpio_request(GPIO_FN_LCDD10,   NULL);
-        gpio_request(GPIO_FN_LCDD9,    NULL);
-        gpio_request(GPIO_FN_LCDD8,    NULL);
-        gpio_request(GPIO_FN_LCDD7,    NULL);
-        gpio_request(GPIO_FN_LCDD6,    NULL);
-        gpio_request(GPIO_FN_LCDD5,    NULL);
-        gpio_request(GPIO_FN_LCDD4,    NULL);
-        gpio_request(GPIO_FN_LCDD3,    NULL);
-        gpio_request(GPIO_FN_LCDD2,    NULL);
-        gpio_request(GPIO_FN_LCDD1,    NULL);
-        gpio_request(GPIO_FN_LCDD0,    NULL);
-        gpio_request(GPIO_FN_LCDDISP,  NULL);
-        gpio_request(GPIO_FN_LCDDCK,   NULL);
-        gpio_request_one(189, GPIOF_OUT_INIT_HIGH, NULL); /* backlight */
-        gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
-        lcdc_info.clock_source                  = LCDC_CLK_BUS;
-        lcdc_info.ch[0].interface_type          = RGB18;
-        lcdc_info.ch[0].clock_divider           = 3;
-        lcdc_info.ch[0].flags                   = 0;
-        lcdc_info.ch[0].panel_cfg.width         = 152;
-        lcdc_info.ch[0].panel_cfg.height        = 91;
-        /* enable TouchScreen */
-        irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW);
-        tsc_device.irq = IRQ7;
-        i2c_register_board_info(0, &tsc_device, 1);
-#endif /* CONFIG_AP4EVB_QHD */
-        /* CEU */
-        /*
-         * TODO: reserve memory for V4L2 DMA buffers, when a suitable API
-         * becomes available
-         */
-        /* MIPI-CSI stuff */
-        gpio_request(GPIO_FN_VIO_CKO, NULL);
-        clk = clk_get(NULL, "vck1_clk");
-        if (!IS_ERR(clk)) {
-                clk_set_rate(clk, clk_round_rate(clk, 13000000));
-                clk_enable(clk);
-                clk_put(clk);
-        }
-        sh7372_add_standard_devices();
-        /* HDMI */
-        gpio_request(GPIO_FN_HDMI_HPD, NULL);
-        gpio_request(GPIO_FN_HDMI_CEC, NULL);
-        /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
-#define SRCR4 IOMEM(0xe61580bc)
-        srcr4 = __raw_readl(SRCR4);
-        __raw_writel(srcr4 | (1 << 13), SRCR4);
-        udelay(50);
-        __raw_writel(srcr4 & ~(1 << 13), SRCR4);
-        platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices));
-        rmobile_add_devices_to_domains(domain_devices,
-                                       ARRAY_SIZE(domain_devices));
-        hdmi_init_pm_clock();
-        sh7372_pm_init();
-        pm_clk_add(&fsi_device.dev, "spu2");
-        pm_clk_add(&lcdc1_device.dev, "hdmi");
-}
-MACHINE_START(AP4EVB, "ap4evb")
-        .map_io         = sh7372_map_io,
-        .init_early     = sh7372_add_early_devices,
-        .init_irq       = sh7372_init_irq,
-        .handle_irq     = shmobile_handle_irq_intc,
-        .init_machine   = ap4evb_init,
-        .init_late      = sh7372_pm_init_late,
-        .init_time      = sh7372_earlytimer_init,
-MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c
index 55b8c9fef954..5eb0caa6a7d0 100644
--- a/arch/arm/mach-shmobile/board-ape6evm.c
+++ b/arch/arm/mach-shmobile/board-ape6evm.c
@@ -26,6 +26,7 @@
 #include <linux/platform_device.h>
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
+#include <linux/sh_clk.h>
 #include <linux/smsc911x.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
@@ -65,7 +66,21 @@ static const struct pinctrl_map ape6evm_pinctrl_map[] = {
 static void __init ape6evm_add_standard_devices(void)
 {
+        struct clk *parent;
+        struct clk *mp;
        r8a73a4_clock_init();
+        /* MP clock parent = extal2 */
+        parent      = clk_get(NULL, "extal2");
+        mp          = clk_get(NULL, "mp");
+        BUG_ON(IS_ERR(parent) || IS_ERR(mp));
+        clk_set_parent(mp, parent);
+        clk_put(parent);
+        clk_put(mp);
        pinctrl_register_mappings(ape6evm_pinctrl_map,
                                  ARRAY_SIZE(ape6evm_pinctrl_map));
        r8a73a4_pinmux_init();
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
new file mode 100644
index 000000000000..03b85fec2ddb
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
@@ -0,0 +1,213 @@
+/*
+ * armadillo 800 eva board support
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ *
+ */
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+#include <linux/pinctrl/machine.h>
+#include <mach/common.h>
+#include <mach/r8a7740.h>
+#include <asm/mach/arch.h>
+#include <asm/hardware/cache-l2x0.h>
+/*
+ * CON1         Camera Module
+ * CON2         Extension Bus
+ * CON3         HDMI Output
+ * CON4         Composite Video Output
+ * CON5         H-UDI JTAG
+ * CON6         ARM JTAG
+ * CON7         SD1
+ * CON8         SD2
+ * CON9         RTC BackUp
+ * CON10        Monaural Mic Input
+ * CON11        Stereo Headphone Output
+ * CON12        Audio Line Output(L)
+ * CON13        Audio Line Output(R)
+ * CON14        AWL13 Module
+ * CON15        Extension
+ * CON16        LCD1
+ * CON17        LCD2
+ * CON19        Power Input
+ * CON20        USB1
+ * CON21        USB2
+ * CON22        Serial
+ * CON23        LAN
+ * CON24        USB3
+ * LED1         Camera LED(Yellow)
+ * LED2         Power LED (Green)
+ * ED3-LED6     User LED(Yellow)
+ * LED7         LAN link LED(Green)
+ * LED8         LAN activity LED(Yellow)
+ */
+/*
+ * DipSwitch
+ *
+ *                    SW1
+ *
+ * -12345678-+---------------+----------------------------
+ *  1        | boot          | hermit
+ *  0        | boot          | OS auto boot
+ * -12345678-+---------------+----------------------------
+ *   00      | boot device   | eMMC
+ *   10      | boot device   | SDHI0 (CON7)
+ *   01      | boot device   | -
+ *   11      | boot device   | Extension Buss (CS0)
+ * -12345678-+---------------+----------------------------
+ *     0     | Extension Bus | D8-D15 disable, eMMC enable
+ *     1     | Extension Bus | D8-D15 enable,  eMMC disable
+ * -12345678-+---------------+----------------------------
+ *      0    | SDHI1         | COM8 disable, COM14 enable
+ *      1    | SDHI1         | COM8 enable,  COM14 disable
+ * -12345678-+---------------+----------------------------
+ *       0   | USB0          | COM20 enable,  COM24 disable
+ *       1   | USB0          | COM20 disable, COM24 enable
+ * -12345678-+---------------+----------------------------
+ *        00 | JTAG          | SH-X2
+ *        10 | JTAG          | ARM
+ *        01 | JTAG          | -
+ *        11 | JTAG          | Boundary Scan
+ *-----------+---------------+----------------------------
+ */
+/*
+ * FSI-WM8978
+ *
+ * this command is required when playback.
+ *
+ * # amixer set "Headphone" 50
+ *
+ * this command is required when capture.
+ *
+ * # amixer set "Input PGA" 15
+ * # amixer set "Left Input Mixer MicP" on
+ * # amixer set "Left Input Mixer MicN" on
+ * # amixer set "Right Input Mixer MicN" on
+ * # amixer set "Right Input Mixer MicP" on
+ */
+/*
+ * USB function
+ *
+ * When you use USB Function,
+ * set SW1.6 ON, and connect cable to CN24.
+ *
+ * USBF needs workaround on R8A7740 chip.
+ * These are a little bit complex.
+ * see
+ *      usbhsf_power_ctrl()
+ */
+static const struct pinctrl_map eva_pinctrl_map[] = {
+        /* SCIFA1 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.1", "pfc-r8a7740",
+                                  "scifa1_data", "scifa1"),
+};
+static void __init eva_clock_init(void)
+{
+        struct clk *system      = clk_get(NULL, "system_clk");
+        struct clk *xtal1       = clk_get(NULL, "extal1");
+        struct clk *usb24s      = clk_get(NULL, "usb24s");
+        struct clk *fsibck      = clk_get(NULL, "fsibck");
+        if (IS_ERR(system)      ||
+            IS_ERR(xtal1)       ||
+            IS_ERR(usb24s)      ||
+            IS_ERR(fsibck)) {
+                pr_err("armadillo800eva board clock init failed\n");
+                goto clock_error;
+        }
+        /* armadillo 800 eva extal1 is 24MHz */
+        clk_set_rate(xtal1, 24000000);
+        /* usb24s use extal1 (= system) clock (= 24MHz) */
+        clk_set_parent(usb24s, system);
+        /* FSIBCK is 12.288MHz, and it is parent of FSI-B */
+        clk_set_rate(fsibck, 12288000);
+clock_error:
+        if (!IS_ERR(system))
+                clk_put(system);
+        if (!IS_ERR(xtal1))
+                clk_put(xtal1);
+        if (!IS_ERR(usb24s))
+                clk_put(usb24s);
+        if (!IS_ERR(fsibck))
+                clk_put(fsibck);
+}
+/*
+ * board init
+ */
+static void __init eva_init(void)
+{
+        r8a7740_clock_init(MD_CK0 | MD_CK2);
+        eva_clock_init();
+        pinctrl_register_mappings(eva_pinctrl_map, ARRAY_SIZE(eva_pinctrl_map));
+        r8a7740_pinmux_init();
+        r8a7740_meram_workaround();
+        /*
+         * Touchscreen
+         * TODO: Move reset GPIO over to .dts when we can reference it
+         */
+        gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */
+#ifdef CONFIG_CACHE_L2X0
+        /* Early BRESP enable, Shared attribute override enable, 32K*8way */
+        l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff);
+#endif
+        r8a7740_add_standard_devices_dt();
+        r8a7740_pm_init();
+}
+#define RESCNT2 IOMEM(0xe6188020)
+static void eva_restart(char mode, const char *cmd)
+{
+        /* Do soft power on reset */
+        writel((1 << 31), RESCNT2);
+}
+static const char *eva_boards_compat_dt[] __initdata = {
+        "renesas,armadillo800eva-reference",
+        NULL,
+};
+DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva-reference")
+        .map_io         = r8a7740_map_io,
+        .init_early     = r8a7740_init_delay,
+        .init_irq       = r8a7740_init_irq_of,
+        .init_machine   = eva_init,
+        .init_time      = shmobile_timer_init,
+        .init_late      = shmobile_init_late,
+        .dt_compat      = eva_boards_compat_dt,
+        .restart        = eva_restart,
+MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index b85b2882dbd0..c5be60d85e4b 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -42,6 +42,7 @@
 #include <linux/mmc/sh_mmcif.h>
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/i2c-gpio.h>
+#include <linux/reboot.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/r8a7740.h>
@@ -377,7 +378,7 @@ static struct resource sh_eth_resources[] = {
 };
 static struct platform_device sh_eth_device = {
-        .name = "sh-eth",
+        .name = "r8a7740-gether",
        .id = -1,
        .dev = {
                .platform_data = &sh_eth_platdata,
@@ -584,7 +585,7 @@ static struct regulator_init_data vcc_sdhi0_init_data = {
 static struct fixed_voltage_config vcc_sdhi0_info = {
        .supply_name = "SDHI0 Vcc",
        .microvolts = 3300000,
-        .gpio = GPIO_PORT75,
+        .gpio = 75,
        .enable_high = 1,
        .init_data = &vcc_sdhi0_init_data,
 };
@@ -615,7 +616,7 @@ static struct regulator_init_data vccq_sdhi0_init_data = {
 };
 static struct gpio vccq_sdhi0_gpios[] = {
-        {GPIO_PORT17, GPIOF_OUT_INIT_LOW, "vccq-sdhi0" },
+        {17, GPIOF_OUT_INIT_LOW, "vccq-sdhi0" },
 };
 static struct gpio_regulator_state vccq_sdhi0_states[] = {
@@ -626,7 +627,7 @@ static struct gpio_regulator_state vccq_sdhi0_states[] = {
 static struct gpio_regulator_config vccq_sdhi0_info = {
        .supply_name = "vqmmc",
-        .enable_gpio = GPIO_PORT74,
+        .enable_gpio = 74,
        .enable_high = 1,
        .enabled_at_boot = 0,
@@ -664,7 +665,7 @@ static struct regulator_init_data vcc_sdhi1_init_data = {
 static struct fixed_voltage_config vcc_sdhi1_info = {
        .supply_name = "SDHI1 Vcc",
        .microvolts = 3300000,
-        .gpio = GPIO_PORT16,
+        .gpio = 16,
        .enable_high = 1,
        .init_data = &vcc_sdhi1_init_data,
 };
@@ -693,7 +694,7 @@ static struct sh_mobile_sdhi_info sdhi0_info = {
        .tmio_caps      = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
                          MMC_CAP_POWER_OFF_CARD,
        .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
-        .cd_gpio        = GPIO_PORT167,
+        .cd_gpio        = 167,
 };
 static struct resource sdhi0_resources[] = {
@@ -736,7 +737,7 @@ static struct sh_mobile_sdhi_info sdhi1_info = {
                          MMC_CAP_POWER_OFF_CARD,
        .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
        /* Port72 cannot generate IRQs, will be used in polling mode. */
-        .cd_gpio        = GPIO_PORT72,
+        .cd_gpio        = 72,
 };
 static struct resource sdhi1_resources[] = {
@@ -1046,6 +1047,35 @@ static struct platform_device *eva_devices[] __initdata = {
 };
 static const struct pinctrl_map eva_pinctrl_map[] = {
+        /* CEU0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740",
+                                  "ceu0_data_0_7", "ceu0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740",
+                                  "ceu0_clk_0", "ceu0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740",
+                                  "ceu0_sync", "ceu0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740",
+                                  "ceu0_field", "ceu0"),
+        /* FSIA */
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740",
+                                  "fsia_sclk_in", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740",
+                                  "fsia_mclk_out", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740",
+                                  "fsia_data_in_1", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740",
+                                  "fsia_data_out_0", "fsia"),
+        /* FSIB */
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-r8a7740",
+                                  "fsib_mclk_in", "fsib"),
+        /* GETHER */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7740",
+                                  "gether_mii", "gether"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7740",
+                                  "gether_int", "gether"),
+        /* HDMI */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-r8a7740",
+                                  "hdmi", "hdmi"),
        /* LCD0 */
        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
                                  "lcd0_data24_0", "lcd0"),
@@ -1058,6 +1088,9 @@ static const struct pinctrl_map eva_pinctrl_map[] = {
                                  "mmc0_data8_1", "mmc0"),
        PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a7740",
                                  "mmc0_ctrl_1", "mmc0"),
+        /* SCIFA1 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.1", "pfc-r8a7740",
+                                  "scifa1_data", "scifa1"),
        /* SDHI0 */
        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740",
                                  "sdhi0_data4", "sdhi0"),
@@ -1065,6 +1098,12 @@ static const struct pinctrl_map eva_pinctrl_map[] = {
                                  "sdhi0_ctrl", "sdhi0"),
        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740",
                                  "sdhi0_wp", "sdhi0"),
+        /* ST1232 */
+        PIN_MAP_MUX_GROUP_DEFAULT("0-0055", "pfc-r8a7740",
+                                  "intc_irq10", "intc"),
+        /* USBHS */
+        PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-r8a7740",
+                                  "intc_irq7_1", "intc"),
 };
 static void __init eva_clock_init(void)
@@ -1119,40 +1158,11 @@ static void __init eva_init(void)
        r8a7740_pinmux_init();
        r8a7740_meram_workaround();
-        /* SCIFA1 */
-        gpio_request(GPIO_FN_SCIFA1_RXD, NULL);
-        gpio_request(GPIO_FN_SCIFA1_TXD, NULL);
        /* LCDC0 */
-        gpio_request(GPIO_FN_LCDC0_SELECT,      NULL);
        gpio_request_one(61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
        gpio_request_one(202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */
-        /* Touchscreen */
-        gpio_request(GPIO_FN_IRQ10,     NULL); /* TP_INT */
        /* GETHER */
-        gpio_request(GPIO_FN_ET_CRS,            NULL);
-        gpio_request(GPIO_FN_ET_MDC,            NULL);
-        gpio_request(GPIO_FN_ET_MDIO,           NULL);
-        gpio_request(GPIO_FN_ET_TX_ER,          NULL);
-        gpio_request(GPIO_FN_ET_RX_ER,          NULL);
-        gpio_request(GPIO_FN_ET_ERXD0,          NULL);
-        gpio_request(GPIO_FN_ET_ERXD1,          NULL);
-        gpio_request(GPIO_FN_ET_ERXD2,          NULL);
-        gpio_request(GPIO_FN_ET_ERXD3,          NULL);
-        gpio_request(GPIO_FN_ET_TX_CLK,         NULL);
-        gpio_request(GPIO_FN_ET_TX_EN,          NULL);
-        gpio_request(GPIO_FN_ET_ETXD0,          NULL);
-        gpio_request(GPIO_FN_ET_ETXD1,          NULL);
-        gpio_request(GPIO_FN_ET_ETXD2,          NULL);
-        gpio_request(GPIO_FN_ET_ETXD3,          NULL);
-        gpio_request(GPIO_FN_ET_PHY_INT,        NULL);
-        gpio_request(GPIO_FN_ET_COL,            NULL);
-        gpio_request(GPIO_FN_ET_RX_DV,          NULL);
-        gpio_request(GPIO_FN_ET_RX_CLK,         NULL);
        gpio_request_one(18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */
        /* USB */
@@ -1163,34 +1173,17 @@ static void __init eva_init(void)
        } else {
                /* USB Func */
                /*
-                 * A1 chip has 2 IRQ7 pin and it was controled by MSEL register.
+                 * The USBHS interrupt handlers needs to read the IRQ pin value
-                 * OTOH, usbhs interrupt needs its value (HI/LOW) to decide
+                 * (HI/LOW) to diffentiate USB connection and disconnection
-                 * USB connection/disconnection (usbhsf_get_vbus()).
+                 * events (usbhsf_get_vbus()). We thus need to select both the
-                 * This means we needs to select GPIO_FN_IRQ7_PORT209 first,
+                 * intc_irq7_1 pin group and GPIO 209 here.
-                 * and select GPIO 209 here
                 */
-                gpio_request(GPIO_FN_IRQ7_PORT209, NULL);
                gpio_request_one(209, GPIOF_IN, NULL);
                platform_device_register(&usbhsf_device);
                usb = &usbhsf_device;
        }
-        /* CEU0 */
-        gpio_request(GPIO_FN_VIO0_D7,           NULL);
-        gpio_request(GPIO_FN_VIO0_D6,           NULL);
-        gpio_request(GPIO_FN_VIO0_D5,           NULL);
-        gpio_request(GPIO_FN_VIO0_D4,           NULL);
-        gpio_request(GPIO_FN_VIO0_D3,           NULL);
-        gpio_request(GPIO_FN_VIO0_D2,           NULL);
-        gpio_request(GPIO_FN_VIO0_D1,           NULL);
-        gpio_request(GPIO_FN_VIO0_D0,           NULL);
-        gpio_request(GPIO_FN_VIO0_CLK,          NULL);
-        gpio_request(GPIO_FN_VIO0_HD,           NULL);
-        gpio_request(GPIO_FN_VIO0_VD,           NULL);
-        gpio_request(GPIO_FN_VIO0_FIELD,        NULL);
-        gpio_request(GPIO_FN_VIO_CKO,           NULL);
        /* CON1/CON15 Camera */
        gpio_request_one(173, GPIOF_OUT_INIT_LOW, NULL);  /* STANDBY */
        gpio_request_one(172, GPIOF_OUT_INIT_HIGH, NULL); /* RST */
@@ -1198,24 +1191,11 @@ static void __init eva_init(void)
        gpio_request_one(158, GPIOF_OUT_INIT_LOW, NULL);  /* CAM_PON */
        /* FSI-WM8978 */
-        gpio_request(GPIO_FN_FSIAIBT,           NULL);
-        gpio_request(GPIO_FN_FSIAILR,           NULL);
-        gpio_request(GPIO_FN_FSIAOMC,           NULL);
-        gpio_request(GPIO_FN_FSIAOSLD,          NULL);
-        gpio_request(GPIO_FN_FSIAISLD_PORT5,    NULL);
        gpio_request(7, NULL);
        gpio_request(8, NULL);
        gpio_direction_none(GPIO_PORT7CR); /* FSIAOBT needs no direction */
        gpio_direction_none(GPIO_PORT8CR); /* FSIAOLR needs no direction */
-        /* FSI-HDMI */
-        gpio_request(GPIO_FN_FSIBCK,            NULL);
-        /* HDMI */
-        gpio_request(GPIO_FN_HDMI_HPD,          NULL);
-        gpio_request(GPIO_FN_HDMI_CEC,          NULL);
        /*
         * CAUTION
         *
@@ -1277,7 +1257,7 @@ static void __init eva_add_early_devices(void)
 }
 #define RESCNT2 IOMEM(0xe6188020)
-static void eva_restart(char mode, const char *cmd)
+static void eva_restart(enum reboot_mode mode, const char *cmd)
 {
        /* Do soft power on reset */
        writel((1 << 31), RESCNT2);
diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c
index 38e5e50fb318..3354a85c90f7 100644
--- a/arch/arm/mach-shmobile/board-bockw.c
+++ b/arch/arm/mach-shmobile/board-bockw.c
@@ -18,13 +18,52 @@
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
+#include <linux/mfd/tmio.h>
+#include <linux/mmc/host.h>
+#include <linux/mtd/partitions.h>
+#include <linux/pinctrl/machine.h>
 #include <linux/platform_device.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/r8a7778.h>
 #include <asm/mach/arch.h>
+/*
+ *      CN9(Upper side) SCIF/RCAN selection
+ *
+ *              1,4     3,6
+ * SW40         SCIF    RCAN
+ * SW41         SCIF    RCAN
+ */
+/*
+ * MMC (CN26) pin
+ *
+ * SW6  (D2)    3 pin
+ * SW7  (D5)    ON
+ * SW8  (D3)    3 pin
+ * SW10 (D4)    1 pin
+ * SW12 (CLK)   1 pin
+ * SW13 (D6)    3 pin
+ * SW14 (CMD)   ON
+ * SW15 (D6)    1 pin
+ * SW16 (D0)    ON
+ * SW17 (D1)    ON
+ * SW18 (D7)    3 pin
+ * SW19 (MMC)   1 pin
+ */
+/* Dummy supplies, where voltage doesn't matter */
+static struct regulator_consumer_supply dummy_supplies[] = {
+        REGULATOR_SUPPLY("vddvario", "smsc911x"),
+        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
+};
 static struct smsc911x_platform_config smsc911x_data = {
        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
@@ -37,17 +76,134 @@ static struct resource smsc911x_resources[] = {
        DEFINE_RES_IRQ(irq_pin(0)), /* IRQ 0 */
 };
+/* USB */
+static struct rcar_phy_platform_data usb_phy_platform_data __initdata;
+/* SDHI */
+static struct sh_mobile_sdhi_info sdhi0_info = {
+        .tmio_caps      = MMC_CAP_SD_HIGHSPEED,
+        .tmio_ocr_mask  = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
+        .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT,
+};
+static struct sh_eth_plat_data ether_platform_data __initdata = {
+        .phy            = 0x01,
+        .edmac_endian   = EDMAC_LITTLE_ENDIAN,
+        .register_type  = SH_ETH_REG_FAST_RCAR,
+        .phy_interface  = PHY_INTERFACE_MODE_RMII,
+        /*
+         * Although the LINK signal is available on the board, it's connected to
+         * the link/activity LED output of the PHY, thus the link disappears and
+         * reappears after each packet.  We'd be better off ignoring such signal
+         * and getting the link state from the PHY indirectly.
+         */
+        .no_ether_link  = 1,
+};
+/* I2C */
+static struct i2c_board_info i2c0_devices[] = {
+        {
+                I2C_BOARD_INFO("rx8581", 0x51),
+        },
+};
+/* HSPI*/
+static struct mtd_partition m25p80_spi_flash_partitions[] = {
+        {
+                .name   = "data(spi)",
+                .size   = 0x0100000,
+                .offset = 0,
+        },
+};
+static struct flash_platform_data spi_flash_data = {
+        .name           = "m25p80",
+        .type           = "s25fl008k",
+        .parts          = m25p80_spi_flash_partitions,
+        .nr_parts       = ARRAY_SIZE(m25p80_spi_flash_partitions),
+};
+static struct spi_board_info spi_board_info[] __initdata = {
+        {
+                .modalias       = "m25p80",
+                .max_speed_hz   = 104000000,
+                .chip_select    = 0,
+                .bus_num        = 0,
+                .mode           = SPI_MODE_0,
+                .platform_data  = &spi_flash_data,
+        },
+};
+/* MMC */
+static struct sh_mmcif_plat_data sh_mmcif_plat = {
+        .sup_pclk       = 0,
+        .ocr            = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
+        .caps           = MMC_CAP_4_BIT_DATA |
+                          MMC_CAP_8_BIT_DATA |
+                          MMC_CAP_NEEDS_POLL,
+};
+static const struct pinctrl_map bockw_pinctrl_map[] = {
+        /* Ether */
+        PIN_MAP_MUX_GROUP_DEFAULT("r8a777x-ether", "pfc-r8a7778",
+                                  "ether_rmii", "ether"),
+        /* HSPI0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-hspi.0", "pfc-r8a7778",
+                                  "hspi0_a", "hspi0"),
+        /* MMC */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif", "pfc-r8a7778",
+                                  "mmc_data8", "mmc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif", "pfc-r8a7778",
+                                  "mmc_ctrl", "mmc"),
+        /* SCIF0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
+                                  "scif0_data_a", "scif0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
+                                  "scif0_ctrl", "scif0"),
+        /* USB */
+        PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform", "pfc-r8a7778",
+                                  "usb0", "usb0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform", "pfc-r8a7778",
+                                  "usb1", "usb1"),
+        /* SDHI0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778",
+                                  "sdhi0_data4", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778",
+                                  "sdhi0_ctrl", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778",
+                                  "sdhi0_cd", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778",
+                                  "sdhi0_wp", "sdhi0"),
+};
+#define FPGA    0x18200000
 #define IRQ0MR  0x30
+#define PFC     0xfffc0000
+#define PUPR4   0x110
 static void __init bockw_init(void)
 {
-        void __iomem *fpga;
+        void __iomem *base;
        r8a7778_clock_init();
        r8a7778_init_irq_extpin(1);
        r8a7778_add_standard_devices();
+        r8a7778_add_usb_phy_device(&usb_phy_platform_data);
+        r8a7778_add_ether_device(&ether_platform_data);
+        r8a7778_add_i2c_device(0);
+        r8a7778_add_hspi_device(0);
+        r8a7778_add_mmc_device(&sh_mmcif_plat);
-        fpga = ioremap_nocache(0x18200000, SZ_1M);
+        i2c_register_board_info(0, i2c0_devices,
-        if (fpga) {
+                                ARRAY_SIZE(i2c0_devices));
+        spi_register_board_info(spi_board_info,
+                                ARRAY_SIZE(spi_board_info));
+        pinctrl_register_mappings(bockw_pinctrl_map,
+                                  ARRAY_SIZE(bockw_pinctrl_map));
+        r8a7778_pinmux_init();
+        /* for SMSC */
+        base = ioremap_nocache(FPGA, SZ_1M);
+        if (base) {
                /*
                 * CAUTION
                 *
@@ -55,16 +211,33 @@ static void __init bockw_init(void)
                 * it should be cared in the future
                 * Now, it is assuming IRQ0 was used only from SMSC.
                 */
-                u16 val = ioread16(fpga + IRQ0MR);
+                u16 val = ioread16(base + IRQ0MR);
                val &= ~(1 << 4); /* enable SMSC911x */
-                iowrite16(val, fpga + IRQ0MR);
+                iowrite16(val, base + IRQ0MR);
-                iounmap(fpga);
+                iounmap(base);
+                regulator_register_fixed(0, dummy_supplies,
+                                         ARRAY_SIZE(dummy_supplies));
                platform_device_register_resndata(
                        &platform_bus, "smsc911x", -1,
                        smsc911x_resources, ARRAY_SIZE(smsc911x_resources),
                        &smsc911x_data, sizeof(smsc911x_data));
        }
+        /* for SDHI */
+        base = ioremap_nocache(PFC, 0x200);
+        if (base) {
+                /*
+                 * FIXME
+                 *
+                 * SDHI CD/WP pin needs pull-up
+                 */
+                iowrite32(ioread32(base + PUPR4) | (3 << 26), base + PUPR4);
+                iounmap(base);
+                r8a7778_sdhi_init(0, &sdhi0_info);
+        }
 }
 static const char *bockw_boards_compat_dt[] __initdata = {
@@ -78,4 +251,5 @@ DT_MACHINE_START(BOCKW_DT, "bockw")
        .init_machine   = bockw_init,
        .init_time      = shmobile_timer_init,
        .dt_compat      = bockw_boards_compat_dt,
+        .init_late      = r8a7778_init_late,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c
deleted file mode 100644
index 70d992c540ae..000000000000
--- a/arch/arm/mach-shmobile/board-bonito.c
+++ /dev/null
@@ -1,495 +0,0 @@
-/*
- * bonito board support
- *
- * Copyright (C) 2011 Renesas Solutions Corp.
- * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
- */
-#include <linux/kernel.h>
-#include <linux/i2c.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/machine.h>
-#include <linux/smsc911x.h>
-#include <linux/videodev2.h>
-#include <mach/common.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
-#include <asm/hardware/cache-l2x0.h>
-#include <mach/r8a7740.h>
-#include <mach/irqs.h>
-#include <video/sh_mobile_lcdc.h>
-/*
- * CS   Address         device                  note
- *----------------------------------------------------------------
- * 0    0x0000_0000     NOR Flash (64MB)        SW12 : bit3 = OFF
- * 2    0x0800_0000     ExtNOR (64MB)           SW12 : bit3 = OFF
- * 4                    -
- * 5A                   -
- * 5B   0x1600_0000     SRAM (8MB)
- * 6    0x1800_0000     FPGA (64K)
- *      0x1801_0000     Ether (4KB)
- *      0x1801_1000     USB (4KB)
- */
-/*
- * SW12
- *
- *      bit1                    bit2                    bit3
- *----------------------------------------------------------------------------
- * ON   NOR WriteProtect        NAND WriteProtect       CS0 ExtNOR / CS2 NOR
- * OFF  NOR Not WriteProtect    NAND Not WriteProtect   CS0 NOR    / CS2 ExtNOR
- */
-/*
- * SCIFA5 (CN42)
- *
- * S38.3 = ON
- * S39.6 = ON
- * S43.1 = ON
- */
-/*
- * LCDC0 (CN3/CN4/CN7)
- *
- * S38.1 = OFF
- * S38.2 = OFF
- */
-/* Dummy supplies, where voltage doesn't matter */
-static struct regulator_consumer_supply dummy_supplies[] = {
-        REGULATOR_SUPPLY("vddvario", "smsc911x"),
-        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
-};
-/*
- * FPGA
- */
-#define IRQSR0          0x0020
-#define IRQSR1          0x0022
-#define IRQMR0          0x0030
-#define IRQMR1          0x0032
-#define BUSSWMR1        0x0070
-#define BUSSWMR2        0x0072
-#define BUSSWMR3        0x0074
-#define BUSSWMR4        0x0076
-#define LCDCR           0x10B4
-#define DEVRSTCR1       0x10D0
-#define DEVRSTCR2       0x10D2
-#define A1MDSR          0x10E0
-#define BVERR           0x1100
-/* FPGA IRQ */
-#define FPGA_IRQ_BASE           (512)
-#define FPGA_IRQ0               (FPGA_IRQ_BASE)
-#define FPGA_IRQ1               (FPGA_IRQ_BASE + 16)
-#define FPGA_ETH_IRQ            (FPGA_IRQ0 + 15)
-static u16 bonito_fpga_read(u32 offset)
-{
-        return __raw_readw(IOMEM(0xf0003000) + offset);
-}
-static void bonito_fpga_write(u32 offset, u16 val)
-{
-        __raw_writew(val, IOMEM(0xf0003000) + offset);
-}
-static void bonito_fpga_irq_disable(struct irq_data *data)
-{
-        unsigned int irq = data->irq;
-        u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
-        int shift = irq % 16;
-        bonito_fpga_write(addr, bonito_fpga_read(addr) | (1 << shift));
-}
-static void bonito_fpga_irq_enable(struct irq_data *data)
-{
-        unsigned int irq = data->irq;
-        u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
-        int shift = irq % 16;
-        bonito_fpga_write(addr, bonito_fpga_read(addr) & ~(1 << shift));
-}
-static struct irq_chip bonito_fpga_irq_chip __read_mostly = {
-        .name           = "bonito FPGA",
-        .irq_mask       = bonito_fpga_irq_disable,
-        .irq_unmask     = bonito_fpga_irq_enable,
-};
-static void bonito_fpga_irq_demux(unsigned int irq, struct irq_desc *desc)
-{
-        u32 val =  bonito_fpga_read(IRQSR1) << 16 |
-                   bonito_fpga_read(IRQSR0);
-        u32 mask = bonito_fpga_read(IRQMR1) << 16 |
-                   bonito_fpga_read(IRQMR0);
-        int i;
-        val &= ~mask;
-        for (i = 0; i < 32; i++) {
-                if (!(val & (1 << i)))
-                        continue;
-                generic_handle_irq(FPGA_IRQ_BASE + i);
-        }
-}
-static void bonito_fpga_init(void)
-{
-        int i;
-        bonito_fpga_write(IRQMR0, 0xffff); /* mask all */
-        bonito_fpga_write(IRQMR1, 0xffff); /* mask all */
-        /* Device reset */
-        bonito_fpga_write(DEVRSTCR1,
-                   (1 << 2));   /* Eth */
-        /* FPGA irq require special handling */
-        for (i = FPGA_IRQ_BASE; i < FPGA_IRQ_BASE + 32; i++) {
-                irq_set_chip_and_handler_name(i, &bonito_fpga_irq_chip,
-                                              handle_level_irq, "level");
-                set_irq_flags(i, IRQF_VALID); /* yuck */
-        }
-        irq_set_chained_handler(evt2irq(0x0340), bonito_fpga_irq_demux);
-        irq_set_irq_type(evt2irq(0x0340), IRQ_TYPE_LEVEL_LOW);
-}
-/*
-* PMIC settings
-*
-* FIXME
-*
-* bonito board needs some settings by pmic which use i2c access.
-* pmic settings use device_initcall() here for use it.
-*/
-static __u8 *pmic_settings = NULL;
-static __u8 pmic_do_2A[] = {
-        0x1C, 0x09,
-        0x1A, 0x80,
-        0xff, 0xff,
-};
-static int __init pmic_init(void)
-{
-        struct i2c_adapter *a = i2c_get_adapter(0);
-        struct i2c_msg msg;
-        __u8 buf[2];
-        int i, ret;
-        if (!pmic_settings)
-                return 0;
-        if (!a)
-                return 0;
-        msg.addr        = 0x46;
-        msg.buf         = buf;
-        msg.len         = 2;
-        msg.flags       = 0;
-        for (i = 0; ; i += 2) {
-                buf[0] = pmic_settings[i + 0];
-                buf[1] = pmic_settings[i + 1];
-                if ((0xff == buf[0]) && (0xff == buf[1]))
-                        break;
-                ret = i2c_transfer(a, &msg, 1);
-                if (ret < 0) {
-                        pr_err("i2c transfer fail\n");
-                        break;
-                }
-        }
-        return 0;
-}
-device_initcall(pmic_init);
-/*
- * LCDC0
- */
-static const struct fb_videomode lcdc0_mode = {
-        .name           = "WVGA Panel",
-        .xres           = 800,
-        .yres           = 480,
-        .left_margin    = 88,
-        .right_margin   = 40,
-        .hsync_len      = 128,
-        .upper_margin   = 20,
-        .lower_margin   = 5,
-        .vsync_len      = 5,
-        .sync           = 0,
-};
-static struct sh_mobile_lcdc_info lcdc0_info = {
-        .clock_source   = LCDC_CLK_BUS,
-        .ch[0] = {
-                .chan                   = LCDC_CHAN_MAINLCD,
-                .fourcc = V4L2_PIX_FMT_RGB565,
-                .interface_type         = RGB24,
-                .clock_divider          = 5,
-                .flags                  = 0,
-                .lcd_modes              = &lcdc0_mode,
-                .num_modes              = 1,
-                .panel_cfg = {
-                        .width  = 152,
-                        .height = 91,
-                },
-        },
-};
-static struct resource lcdc0_resources[] = {
-        [0] = {
-                .name   = "LCDC0",
-                .start  = 0xfe940000,
-                .end    = 0xfe943fff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = intcs_evt2irq(0x0580),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device lcdc0_device = {
-        .name           = "sh_mobile_lcdc_fb",
-        .id             = 0,
-        .resource       = lcdc0_resources,
-        .num_resources  = ARRAY_SIZE(lcdc0_resources),
-        .dev    = {
-                .platform_data  = &lcdc0_info,
-                .coherent_dma_mask = ~0,
-        },
-};
-static const struct pinctrl_map lcdc0_pinctrl_map[] = {
-        /* LCD0 */
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
-                                  "lcd0_data24_1", "lcd0"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
-                                  "lcd0_lclk_1", "lcd0"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
-                                  "lcd0_sync", "lcd0"),
-};
-/*
- * SMSC 9221
- */
-static struct resource smsc_resources[] = {
-        [0] = {
-                .start          = 0x18010000,
-                .end            = 0x18011000 - 1,
-                .flags          = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start          = FPGA_ETH_IRQ,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-static struct smsc911x_platform_config smsc_platdata = {
-        .flags          = SMSC911X_USE_16BIT,
-        .phy_interface  = PHY_INTERFACE_MODE_MII,
-        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
-};
-static struct platform_device smsc_device = {
-        .name           = "smsc911x",
-        .dev  = {
-                .platform_data = &smsc_platdata,
-        },
-        .resource       = smsc_resources,
-        .num_resources  = ARRAY_SIZE(smsc_resources),
-};
-/*
- * core board devices
- */
-static struct platform_device *bonito_core_devices[] __initdata = {
-};
-/*
- * base board devices
- */
-static struct platform_device *bonito_base_devices[] __initdata = {
-        &lcdc0_device,
-        &smsc_device,
-};
-/*
- * map I/O
- */
-static struct map_desc bonito_io_desc[] __initdata = {
-        /*
-         * for FPGA (0x1800000-0x19ffffff)
-         * 0x18000000-0x18002000 -> 0xf0003000-0xf0005000
-         */
-        {
-                .virtual        = 0xf0003000,
-                .pfn            = __phys_to_pfn(0x18000000),
-                .length         = PAGE_SIZE * 2,
-                .type           = MT_DEVICE_NONSHARED
-        }
-};
-static void __init bonito_map_io(void)
-{
-        r8a7740_map_io();
-        iotable_init(bonito_io_desc, ARRAY_SIZE(bonito_io_desc));
-}
-/*
- * board init
- */
-#define BIT_ON(sw, bit)         (sw & (1 << bit))
-#define BIT_OFF(sw, bit)        (!(sw & (1 << bit)))
-#define VCCQ1CR         IOMEM(0xE6058140)
-#define VCCQ1LCDCR      IOMEM(0xE6058186)
-static void __init bonito_init(void)
-{
-        u16 val;
-        regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
-        r8a7740_pinmux_init();
-        bonito_fpga_init();
-        pmic_settings = pmic_do_2A;
-        /*
-         * core board settings
-         */
-#ifdef CONFIG_CACHE_L2X0
-        /* Early BRESP enable, Shared attribute override enable, 32K*8way */
-        l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff);
-#endif
-        r8a7740_add_standard_devices();
-        platform_add_devices(bonito_core_devices,
-                             ARRAY_SIZE(bonito_core_devices));
-        /*
-         * base board settings
-         */
-        gpio_request_one(176, GPIOF_IN, NULL);
-        if (!gpio_get_value(176)) {
-                u16 bsw2;
-                u16 bsw3;
-                u16 bsw4;
-                /*
-                 * FPGA
-                 */
-                gpio_request(GPIO_FN_CS5B,              NULL);
-                gpio_request(GPIO_FN_CS6A,              NULL);
-                gpio_request(GPIO_FN_CS5A_PORT105,      NULL);
-                gpio_request(GPIO_FN_IRQ10,             NULL);
-                val = bonito_fpga_read(BVERR);
-                pr_info("bonito version: cpu %02x, base %02x\n",
-                        ((val >> 8) & 0xFF),
-                        ((val >> 0) & 0xFF));
-                bsw2 = bonito_fpga_read(BUSSWMR2);
-                bsw3 = bonito_fpga_read(BUSSWMR3);
-                bsw4 = bonito_fpga_read(BUSSWMR4);
-                /*
-                 * SCIFA5 (CN42)
-                 */
-                if (BIT_OFF(bsw2, 1) && /* S38.3 = ON */
-                    BIT_OFF(bsw3, 9) && /* S39.6 = ON */
-                    BIT_OFF(bsw4, 4)) { /* S43.1 = ON */
-                        gpio_request(GPIO_FN_SCIFA5_TXD_PORT91, NULL);
-                        gpio_request(GPIO_FN_SCIFA5_RXD_PORT92, NULL);
-                }
-                /*
-                 * LCDC0 (CN3)
-                 */
-                if (BIT_ON(bsw2, 3) &&  /* S38.1 = OFF */
-                    BIT_ON(bsw2, 2)) {  /* S38.2 = OFF */
-                        pinctrl_register_mappings(lcdc0_pinctrl_map,
-                                                  ARRAY_SIZE(lcdc0_pinctrl_map));
-                        gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
-                        gpio_request_one(61, GPIOF_OUT_INIT_HIGH,
-                                         NULL); /* LCDDON */
-                        /* backlight on */
-                        bonito_fpga_write(LCDCR, 1);
-                        /*  drivability Max */
-                        __raw_writew(0x00FF , VCCQ1LCDCR);
-                        __raw_writew(0xFFFF , VCCQ1CR);
-                }
-                platform_add_devices(bonito_base_devices,
-                                     ARRAY_SIZE(bonito_base_devices));
-        }
-}
-static void __init bonito_earlytimer_init(void)
-{
-        u16 val;
-        u8 md_ck = 0;
-        /* read MD_CK value */
-        val = bonito_fpga_read(A1MDSR);
-        if (val & (1 << 10))
-                md_ck |= MD_CK2;
-        if (val & (1 << 9))
-                md_ck |= MD_CK1;
-        if (val & (1 << 8))
-                md_ck |= MD_CK0;
-        r8a7740_clock_init(md_ck);
-        shmobile_earlytimer_init();
-}
-static void __init bonito_add_early_devices(void)
-{
-        r8a7740_add_early_devices();
-}
-MACHINE_START(BONITO, "bonito")
-        .map_io         = bonito_map_io,
-        .init_early     = bonito_add_early_devices,
-        .init_irq       = r8a7740_init_irq,
-        .handle_irq     = shmobile_handle_irq_intc,
-        .init_machine   = bonito_init,
-        .init_late      = shmobile_init_late,
-        .init_time      = bonito_earlytimer_init,
-MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-kzm9d.c b/arch/arm/mach-shmobile/board-kzm9d.c
index c016ccd92433..4368000e1127 100644
--- a/arch/arm/mach-shmobile/board-kzm9d.c
+++ b/arch/arm/mach-shmobile/board-kzm9d.c
@@ -56,7 +56,7 @@ static struct smsc911x_platform_config smsc911x_platdata = {
 static struct platform_device smsc91x_device = {
        .name   = "smsc911x",
-        .id     = 0,
+        .id     = -1,
        .dev    = {
                  .platform_data = &smsc911x_platdata,
                },
diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c
index aefa50d385b7..44055fe8a45c 100644
--- a/arch/arm/mach-shmobile/board-kzm9g-reference.c
+++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c
@@ -79,7 +79,6 @@ static void __init kzm_init(void)
        sh73a0_pinmux_init();
        /* enable SD */
-        gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
        gpio_request_one(15, GPIOF_OUT_INIT_HIGH, NULL); /* power */
        gpio_request_one(14, GPIOF_OUT_INIT_HIGH, NULL); /* power */
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index e6b775a10aad..1068120d339f 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -29,10 +29,12 @@
 #include <linux/mmc/host.h>
 #include <linux/mmc/sh_mmcif.h>
 #include <linux/mmc/sh_mobile_sdhi.h>
+#include <linux/mfd/as3711.h>
 #include <linux/mfd/tmio.h>
 #include <linux/pinctrl/machine.h>
 #include <linux/pinctrl/pinconf-generic.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
@@ -606,6 +608,140 @@ static struct platform_device fsi_ak4648_device = {
 };
 /* I2C */
+/* StepDown1 is used to supply 1.315V to the CPU */
+static struct regulator_init_data as3711_sd1 = {
+        .constraints = {
+                .name = "1.315V CPU",
+                .boot_on = 1,
+                .always_on = 1,
+                .min_uV = 1315000,
+                .max_uV = 1335000,
+        },
+};
+/* StepDown2 is used to supply 1.8V to the CPU and to the board */
+static struct regulator_init_data as3711_sd2 = {
+        .constraints = {
+                .name = "1.8V",
+                .boot_on = 1,
+                .always_on = 1,
+                .min_uV = 1800000,
+                .max_uV = 1800000,
+        },
+};
+/*
+ * StepDown3 is switched in parallel with StepDown2, seems to be off,
+ * according to read-back pre-set register values
+ */
+/* StepDown4 is used to supply 1.215V to the CPU and to the board */
+static struct regulator_init_data as3711_sd4 = {
+        .constraints = {
+                .name = "1.215V",
+                .boot_on = 1,
+                .always_on = 1,
+                .min_uV = 1215000,
+                .max_uV = 1235000,
+        },
+};
+/* LDO1 is unused and unconnected */
+/* LDO2 is used to supply 2.8V to the CPU */
+static struct regulator_init_data as3711_ldo2 = {
+        .constraints = {
+                .name = "2.8V CPU",
+                .boot_on = 1,
+                .always_on = 1,
+                .min_uV = 2800000,
+                .max_uV = 2800000,
+        },
+};
+/* LDO3 is used to supply 3.0V to the CPU */
+static struct regulator_init_data as3711_ldo3 = {
+        .constraints = {
+                .name = "3.0V CPU",
+                .boot_on = 1,
+                .always_on = 1,
+                .min_uV = 3000000,
+                .max_uV = 3000000,
+        },
+};
+/* LDO4 is used to supply 2.8V to the board */
+static struct regulator_init_data as3711_ldo4 = {
+        .constraints = {
+                .name = "2.8V",
+                .boot_on = 1,
+                .always_on = 1,
+                .min_uV = 2800000,
+                .max_uV = 2800000,
+        },
+};
+/* LDO5 is switched parallel to LDO4, also set to 2.8V */
+static struct regulator_init_data as3711_ldo5 = {
+        .constraints = {
+                .name = "2.8V #2",
+                .boot_on = 1,
+                .always_on = 1,
+                .min_uV = 2800000,
+                .max_uV = 2800000,
+        },
+};
+/* LDO6 is unused and unconnected */
+/* LDO7 is used to supply 1.15V to the CPU */
+static struct regulator_init_data as3711_ldo7 = {
+        .constraints = {
+                .name = "1.15V CPU",
+                .boot_on = 1,
+                .always_on = 1,
+                .min_uV = 1150000,
+                .max_uV = 1150000,
+        },
+};
+/* LDO8 is switched parallel to LDO7, also set to 1.15V */
+static struct regulator_init_data as3711_ldo8 = {
+        .constraints = {
+                .name = "1.15V CPU #2",
+                .boot_on = 1,
+                .always_on = 1,
+                .min_uV = 1150000,
+                .max_uV = 1150000,
+        },
+};
+static struct as3711_platform_data as3711_pdata = {
+        .regulator      = {
+                .init_data      = {
+                        [AS3711_REGULATOR_SD_1] = &as3711_sd1,
+                        [AS3711_REGULATOR_SD_2] = &as3711_sd2,
+                        [AS3711_REGULATOR_SD_4] = &as3711_sd4,
+                        [AS3711_REGULATOR_LDO_2] = &as3711_ldo2,
+                        [AS3711_REGULATOR_LDO_3] = &as3711_ldo3,
+                        [AS3711_REGULATOR_LDO_4] = &as3711_ldo4,
+                        [AS3711_REGULATOR_LDO_5] = &as3711_ldo5,
+                        [AS3711_REGULATOR_LDO_7] = &as3711_ldo7,
+                        [AS3711_REGULATOR_LDO_8] = &as3711_ldo8,
+                },
+        },
+        .backlight      = {
+                .su2_fb = "sh_mobile_lcdc_fb.0",
+                .su2_max_uA = 36000,
+                .su2_feedback = AS3711_SU2_CURR_AUTO,
+                .su2_fbprot = AS3711_SU2_GPIO4,
+                .su2_auto_curr1 = true,
+                .su2_auto_curr2 = true,
+                .su2_auto_curr3 = true,
+        },
+};
 static struct pcf857x_platform_data pcf8575_pdata = {
        .gpio_base      = GPIO_PCF8575_BASE,
 };
@@ -625,6 +761,11 @@ static struct i2c_board_info i2c0_devices[] = {
                I2C_BOARD_INFO("adxl34x", 0x1d),
                .irq = irq_pin(26), /* IRQ26 */
        },
+        {
+                I2C_BOARD_INFO("as3711", 0x40),
+                .irq = intcs_evt2irq(0x3300), /* IRQ24 */
+                .platform_data = &as3711_pdata,
+        },
 };
 static struct i2c_board_info i2c1_devices[] = {
@@ -663,13 +804,13 @@ static unsigned long pin_pullup_conf[] = {
 static const struct pinctrl_map kzm_pinctrl_map[] = {
        /* FSIA (AK4648) */
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0",
                                  "fsia_mclk_in", "fsia"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0",
                                  "fsia_sclk_in", "fsia"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0",
                                  "fsia_data_in", "fsia"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0",
                                  "fsia_data_out", "fsia"),
        /* I2C3 */
        PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0",
@@ -715,59 +856,6 @@ static const struct pinctrl_map kzm_pinctrl_map[] = {
                                  "usb_vbus", "usb"),
 };
-/*
- * FIXME
- *
- * This is quick hack for enabling LCDC backlight
- */
-static int __init as3711_enable_lcdc_backlight(void)
-{
-        struct i2c_adapter *a = i2c_get_adapter(0);
-        struct i2c_msg msg;
-        int i, ret;
-        __u8 magic[] = {
-                0x40, 0x2a,
-                0x43, 0x3c,
-                0x44, 0x3c,
-                0x45, 0x3c,
-                0x54, 0x03,
-                0x51, 0x00,
-                0x51, 0x01,
-                0xff, 0x00, /* wait */
-                0x43, 0xf0,
-                0x44, 0xf0,
-                0x45, 0xf0,
-        };
-        if (!of_machine_is_compatible("renesas,kzm9g"))
-                return 0;
-        if (!a)
-                return 0;
-        msg.addr        = 0x40;
-        msg.len         = 2;
-        msg.flags       = 0;
-        for (i = 0; i < ARRAY_SIZE(magic); i += 2) {
-                msg.buf = magic + i;
-                if (0xff == msg.buf[0]) {
-                        udelay(500);
-                        continue;
-                }
-                ret = i2c_transfer(a, &msg, 1);
-                if (ret < 0) {
-                        pr_err("i2c transfer fail\n");
-                        break;
-                }
-        }
-        return 0;
-}
-device_initcall(as3711_enable_lcdc_backlight);
 static void __init kzm_init(void)
 {
        regulator_register_always_on(2, "fixed-1.8V", fixed1v8_power_consumers,
@@ -788,9 +876,6 @@ static void __init kzm_init(void)
        /* Touchscreen */
        gpio_request_one(223, GPIOF_IN, NULL); /* IRQ8 */
-        /* enable SD */
-        gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
 #ifdef CONFIG_CACHE_L2X0
        /* Early BRESP enable, Shared attribute override enable, 64K*8way */
        l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff);
@@ -806,7 +891,7 @@ static void __init kzm_init(void)
        sh73a0_pm_init();
 }
-static void kzm9g_restart(char mode, const char *cmd)
+static void kzm9g_restart(enum reboot_mode mode, const char *cmd)
 {
 #define RESCNT2 IOMEM(0xe6188020)
        /* Do soft power on reset */
diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
index f587187a8603..8d6bd5c5efb9 100644
--- a/arch/arm/mach-shmobile/board-lager.c
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -18,19 +18,83 @@
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
 #include <linux/interrupt.h>
 #include <linux/irqchip.h>
 #include <linux/kernel.h>
+#include <linux/leds.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/platform_data/gpio-rcar.h>
 #include <linux/platform_device.h>
 #include <mach/common.h>
 #include <mach/r8a7790.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+/* LEDS */
+static struct gpio_led lager_leds[] = {
+        {
+                .name           = "led8",
+                .gpio           = RCAR_GP_PIN(5, 17),
+                .default_state  = LEDS_GPIO_DEFSTATE_ON,
+        }, {
+                .name           = "led7",
+                .gpio           = RCAR_GP_PIN(4, 23),
+                .default_state  = LEDS_GPIO_DEFSTATE_ON,
+        }, {
+                .name           = "led6",
+                .gpio           = RCAR_GP_PIN(4, 22),
+                .default_state  = LEDS_GPIO_DEFSTATE_ON,
+        },
+};
+static __initdata struct gpio_led_platform_data lager_leds_pdata = {
+        .leds           = lager_leds,
+        .num_leds       = ARRAY_SIZE(lager_leds),
+};
+/* GPIO KEY */
+#define GPIO_KEY(c, g, d, ...) \
+        { .code = c, .gpio = g, .desc = d, .active_low = 1 }
+static struct gpio_keys_button gpio_buttons[] = {
+        GPIO_KEY(KEY_4,         RCAR_GP_PIN(1, 28),     "SW2-pin4"),
+        GPIO_KEY(KEY_3,         RCAR_GP_PIN(1, 26),     "SW2-pin3"),
+        GPIO_KEY(KEY_2,         RCAR_GP_PIN(1, 24),     "SW2-pin2"),
+        GPIO_KEY(KEY_1,         RCAR_GP_PIN(1, 14),     "SW2-pin1"),
+};
+static __initdata struct gpio_keys_platform_data lager_keys_pdata = {
+        .buttons        = gpio_buttons,
+        .nbuttons       = ARRAY_SIZE(gpio_buttons),
+};
+static const struct pinctrl_map lager_pinctrl_map[] = {
+        /* SCIF0 (CN19: DEBUG SERIAL0) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790",
+                                  "scif0_data", "scif0"),
+        /* SCIF1 (CN20: DEBUG SERIAL1) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.7", "pfc-r8a7790",
+                                  "scif1_data", "scif1"),
+};
 static void __init lager_add_standard_devices(void)
 {
        r8a7790_clock_init();
+        pinctrl_register_mappings(lager_pinctrl_map,
+                                  ARRAY_SIZE(lager_pinctrl_map));
+        r8a7790_pinmux_init();
        r8a7790_add_standard_devices();
+        platform_device_register_data(&platform_bus, "leds-gpio", -1,
+                                      &lager_leds_pdata,
+                                      sizeof(lager_leds_pdata));
+        platform_device_register_data(&platform_bus, "gpio-keys", -1,
+                                      &lager_keys_pdata,
+                                      sizeof(lager_keys_pdata));
 }
 static const char *lager_boards_compat_dt[] __initdata = {
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index fa3407da682a..85f51a849a50 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -1309,6 +1309,49 @@ static struct i2c_board_info i2c1_devices[] = {
 };
 static const struct pinctrl_map mackerel_pinctrl_map[] = {
+        /* ADXL34X */
+        PIN_MAP_MUX_GROUP_DEFAULT("1-0053", "pfc-sh7372",
+                                  "intc_irq21", "intc"),
+        /* CEU */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
+                                  "ceu_data_0_7", "ceu"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
+                                  "ceu_clk_0", "ceu"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
+                                  "ceu_sync", "ceu"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
+                                  "ceu_field", "ceu"),
+        /* FLCTL */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372",
+                                  "flctl_data", "flctl"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372",
+                                  "flctl_ce0", "flctl"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372",
+                                  "flctl_ctrl", "flctl"),
+        /* FSIA (AK4643) */
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
+                                  "fsia_sclk_in", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
+                                  "fsia_data_in", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
+                                  "fsia_data_out", "fsia"),
+        /* FSIB (HDMI) */
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-sh7372",
+                                  "fsib_mclk_in", "fsib"),
+        /* HDMI */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-sh7372",
+                                  "hdmi", "hdmi"),
+        /* LCDC */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372",
+                                  "lcd_data24", "lcd"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372",
+                                  "lcd_sync", "lcd"),
+        /* SCIFA0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-sh7372",
+                                  "scifa0_data", "scifa0"),
+        /* SCIFA2 (GT-720F GPS module) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh7372",
+                                  "scifa2_data", "scifa2"),
        /* SDHI0 */
        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
                                  "sdhi0_data4", "sdhi0"),
@@ -1316,6 +1359,8 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = {
                                  "sdhi0_ctrl", "sdhi0"),
        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
                                  "sdhi0_wp", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
+                                  "intc_irq26_1", "intc"),
        /* SDHI1 */
 #if !IS_ENABLED(CONFIG_MMC_SH_MMCIF)
        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
@@ -1334,6 +1379,25 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = {
                                  "sdhi2_data4", "sdhi2"),
        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372",
                                  "sdhi2_ctrl", "sdhi2"),
+        /* SMSC911X */
+        PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372",
+                                  "bsc_cs5a", "bsc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372",
+                                  "intc_irq6_0", "intc"),
+        /* ST1232 */
+        PIN_MAP_MUX_GROUP_DEFAULT("0-0055", "pfc-sh7372",
+                                  "intc_irq7_0", "intc"),
+        /* TCA6416 */
+        PIN_MAP_MUX_GROUP_DEFAULT("0-0020", "pfc-sh7372",
+                                  "intc_irq9_0", "intc"),
+        /* USBHS0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.0", "pfc-sh7372",
+                                  "usb0_vbus", "usb0"),
+        /* USBHS1 */
+        PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.1", "pfc-sh7372",
+                                  "usb1_vbus", "usb1"),
+        PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.1", "pfc-sh7372",
+                                  "usb1_otg_id_0", "usb1"),
 };
 #define GPIO_PORT9CR    IOMEM(0xE6051009)
@@ -1377,61 +1441,18 @@ static void __init mackerel_init(void)
                                  ARRAY_SIZE(mackerel_pinctrl_map));
        sh7372_pinmux_init();
-        /* enable SCIFA0 */
-        gpio_request(GPIO_FN_SCIFA0_TXD, NULL);
-        gpio_request(GPIO_FN_SCIFA0_RXD, NULL);
-        /* enable SMSC911X */
-        gpio_request(GPIO_FN_CS5A,      NULL);
-        gpio_request(GPIO_FN_IRQ6_39,   NULL);
-        /* LCDC */
-        gpio_request(GPIO_FN_LCDD23,   NULL);
-        gpio_request(GPIO_FN_LCDD22,   NULL);
-        gpio_request(GPIO_FN_LCDD21,   NULL);
-        gpio_request(GPIO_FN_LCDD20,   NULL);
-        gpio_request(GPIO_FN_LCDD19,   NULL);
-        gpio_request(GPIO_FN_LCDD18,   NULL);
-        gpio_request(GPIO_FN_LCDD17,   NULL);
-        gpio_request(GPIO_FN_LCDD16,   NULL);
-        gpio_request(GPIO_FN_LCDD15,   NULL);
-        gpio_request(GPIO_FN_LCDD14,   NULL);
-        gpio_request(GPIO_FN_LCDD13,   NULL);
-        gpio_request(GPIO_FN_LCDD12,   NULL);
-        gpio_request(GPIO_FN_LCDD11,   NULL);
-        gpio_request(GPIO_FN_LCDD10,   NULL);
-        gpio_request(GPIO_FN_LCDD9,    NULL);
-        gpio_request(GPIO_FN_LCDD8,    NULL);
-        gpio_request(GPIO_FN_LCDD7,    NULL);
-        gpio_request(GPIO_FN_LCDD6,    NULL);
-        gpio_request(GPIO_FN_LCDD5,    NULL);
-        gpio_request(GPIO_FN_LCDD4,    NULL);
-        gpio_request(GPIO_FN_LCDD3,    NULL);
-        gpio_request(GPIO_FN_LCDD2,    NULL);
-        gpio_request(GPIO_FN_LCDD1,    NULL);
-        gpio_request(GPIO_FN_LCDD0,    NULL);
-        gpio_request(GPIO_FN_LCDDISP,  NULL);
-        gpio_request(GPIO_FN_LCDDCK,   NULL);
        /* backlight, off by default */
        gpio_request_one(31, GPIOF_OUT_INIT_LOW, NULL);
        gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
        /* USBHS0 */
-        gpio_request(GPIO_FN_VBUS0_0, NULL);
        gpio_request_pulldown(GPIO_PORT168CR); /* VBUS0_0 pull down */
        /* USBHS1 */
-        gpio_request(GPIO_FN_VBUS0_1, NULL);
        gpio_request_pulldown(GPIO_PORT167CR); /* VBUS0_1 pull down */
-        gpio_request(GPIO_FN_IDIN_1_113, NULL);
-        /* enable FSI2 port A (ak4643) */
+        /* FSI2 port A (ak4643) */
-        gpio_request(GPIO_FN_FSIAIBT,   NULL);
-        gpio_request(GPIO_FN_FSIAILR,   NULL);
-        gpio_request(GPIO_FN_FSIAISLD,  NULL);
-        gpio_request(GPIO_FN_FSIAOSLD,  NULL);
        gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
        gpio_request(9,  NULL);
@@ -1441,8 +1462,7 @@ static void __init mackerel_init(void)
        intc_set_priority(IRQ_FSI, 3); /* irq priority FSI(3) > SMSC911X(2) */
-        /* setup FSI2 port B (HDMI) */
+        /* FSI2 port B (HDMI) */
-        gpio_request(GPIO_FN_FSIBCK, NULL);
        __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */
        /* set SPU2 clock to 119.6 MHz */
@@ -1452,68 +1472,15 @@ static void __init mackerel_init(void)
                clk_put(clk);
        }
-        /* enable Keypad */
+        /* Keypad */
-        gpio_request(GPIO_FN_IRQ9_42,   NULL);
        irq_set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH);
-        /* enable Touchscreen */
+        /* Touchscreen */
-        gpio_request(GPIO_FN_IRQ7_40,   NULL);
        irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW);
-        /* enable Accelerometer */
+        /* Accelerometer */
-        gpio_request(GPIO_FN_IRQ21,     NULL);
        irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH);
-        /* SDHI0 PORT172 card-detect IRQ26 */
-        gpio_request(GPIO_FN_IRQ26_172, NULL);
-        /* FLCTL */
-        gpio_request(GPIO_FN_D0_NAF0, NULL);
-        gpio_request(GPIO_FN_D1_NAF1, NULL);
-        gpio_request(GPIO_FN_D2_NAF2, NULL);
-        gpio_request(GPIO_FN_D3_NAF3, NULL);
-        gpio_request(GPIO_FN_D4_NAF4, NULL);
-        gpio_request(GPIO_FN_D5_NAF5, NULL);
-        gpio_request(GPIO_FN_D6_NAF6, NULL);
-        gpio_request(GPIO_FN_D7_NAF7, NULL);
-        gpio_request(GPIO_FN_D8_NAF8, NULL);
-        gpio_request(GPIO_FN_D9_NAF9, NULL);
-        gpio_request(GPIO_FN_D10_NAF10, NULL);
-        gpio_request(GPIO_FN_D11_NAF11, NULL);
-        gpio_request(GPIO_FN_D12_NAF12, NULL);
-        gpio_request(GPIO_FN_D13_NAF13, NULL);
-        gpio_request(GPIO_FN_D14_NAF14, NULL);
-        gpio_request(GPIO_FN_D15_NAF15, NULL);
-        gpio_request(GPIO_FN_FCE0, NULL);
-        gpio_request(GPIO_FN_WE0_FWE, NULL);
-        gpio_request(GPIO_FN_FRB, NULL);
-        gpio_request(GPIO_FN_A4_FOE, NULL);
-        gpio_request(GPIO_FN_A5_FCDE, NULL);
-        gpio_request(GPIO_FN_RD_FSC, NULL);
-        /* enable GPS module (GT-720F) */
-        gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
-        gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
-        /* CEU */
-        gpio_request(GPIO_FN_VIO_CLK, NULL);
-        gpio_request(GPIO_FN_VIO_VD, NULL);
-        gpio_request(GPIO_FN_VIO_HD, NULL);
-        gpio_request(GPIO_FN_VIO_FIELD, NULL);
-        gpio_request(GPIO_FN_VIO_CKO, NULL);
-        gpio_request(GPIO_FN_VIO_D7, NULL);
-        gpio_request(GPIO_FN_VIO_D6, NULL);
-        gpio_request(GPIO_FN_VIO_D5, NULL);
-        gpio_request(GPIO_FN_VIO_D4, NULL);
-        gpio_request(GPIO_FN_VIO_D3, NULL);
-        gpio_request(GPIO_FN_VIO_D2, NULL);
-        gpio_request(GPIO_FN_VIO_D1, NULL);
-        gpio_request(GPIO_FN_VIO_D0, NULL);
-        /* HDMI */
-        gpio_request(GPIO_FN_HDMI_HPD, NULL);
-        gpio_request(GPIO_FN_HDMI_CEC, NULL);
        /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
        srcr4 = __raw_readl(SRCR4);
        __raw_writel(srcr4 | (1 << 13), SRCR4);
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index b9594e911ce7..a7d1010505bf 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -28,6 +28,7 @@
 #include <linux/leds.h>
 #include <linux/dma-mapping.h>
 #include <linux/pinctrl/machine.h>
+#include <linux/platform_data/gpio-rcar.h>
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
@@ -36,10 +37,6 @@
 #include <linux/mmc/host.h>
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/mfd/tmio.h>
-#include <linux/usb/otg.h>
-#include <linux/usb/ehci_pdriver.h>
-#include <linux/usb/ohci_pdriver.h>
-#include <linux/pm_runtime.h>
 #include <mach/hardware.h>
 #include <mach/r8a7779.h>
 #include <mach/common.h>
@@ -60,6 +57,8 @@ static struct regulator_consumer_supply dummy_supplies[] = {
        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
 };
+static struct rcar_phy_platform_data usb_phy_platform_data __initdata;
 /* SMSC LAN89218 */
 static struct resource smsc911x_resources[] = {
        [0] = {
@@ -68,7 +67,7 @@ static struct resource smsc911x_resources[] = {
                .flags          = IORESOURCE_MEM,
        },
        [1] = {
-                .start          = gic_iid(0x3c), /* IRQ 1 */
+                .start          = irq_pin(1), /* IRQ 1 */
                .flags          = IORESOURCE_IRQ,
        },
 };
@@ -149,39 +148,19 @@ static struct platform_device hspi_device = {
        .num_resources  = ARRAY_SIZE(hspi_resources),
 };
-/* USB PHY */
-static struct resource usb_phy_resources[] = {
-        [0] = {
-                .start          = 0xffe70000,
-                .end            = 0xffe70900 - 1,
-                .flags          = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start          = 0xfff70000,
-                .end            = 0xfff70900 - 1,
-                .flags          = IORESOURCE_MEM,
-        },
-};
-static struct platform_device usb_phy_device = {
-        .name           = "rcar_usb_phy",
-        .resource       = usb_phy_resources,
-        .num_resources  = ARRAY_SIZE(usb_phy_resources),
-};
 /* LEDS */
 static struct gpio_led marzen_leds[] = {
        {
                .name           = "led2",
-                .gpio           = 157,
+                .gpio           = RCAR_GP_PIN(4, 29),
                .default_state  = LEDS_GPIO_DEFSTATE_ON,
        }, {
                .name           = "led3",
-                .gpio           = 158,
+                .gpio           = RCAR_GP_PIN(4, 30),
                .default_state  = LEDS_GPIO_DEFSTATE_ON,
        }, {
                .name           = "led4",
-                .gpio           = 159,
+                .gpio           = RCAR_GP_PIN(4, 31),
                .default_state  = LEDS_GPIO_DEFSTATE_ON,
        },
 };
@@ -204,161 +183,9 @@ static struct platform_device *marzen_devices[] __initdata = {
        &sdhi0_device,
        &thermal_device,
        &hspi_device,
-        &usb_phy_device,
        &leds_device,
 };
-/* USB */
-static struct usb_phy *phy;
-static int usb_power_on(struct platform_device *pdev)
-{
-        if (IS_ERR(phy))
-                return PTR_ERR(phy);
-        pm_runtime_enable(&pdev->dev);
-        pm_runtime_get_sync(&pdev->dev);
-        usb_phy_init(phy);
-        return 0;
-}
-static void usb_power_off(struct platform_device *pdev)
-{
-        if (IS_ERR(phy))
-                return;
-        usb_phy_shutdown(phy);
-        pm_runtime_put_sync(&pdev->dev);
-        pm_runtime_disable(&pdev->dev);
-}
-static struct usb_ehci_pdata ehcix_pdata = {
-        .power_on       = usb_power_on,
-        .power_off      = usb_power_off,
-        .power_suspend  = usb_power_off,
-};
-static struct resource ehci0_resources[] = {
-        [0] = {
-                .start  = 0xffe70000,
-                .end    = 0xffe70400 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = gic_iid(0x4c),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device ehci0_device = {
-        .name   = "ehci-platform",
-        .id     = 0,
-        .dev    = {
-                .dma_mask               = &ehci0_device.dev.coherent_dma_mask,
-                .coherent_dma_mask      = 0xffffffff,
-                .platform_data          = &ehcix_pdata,
-        },
-        .num_resources  = ARRAY_SIZE(ehci0_resources),
-        .resource       = ehci0_resources,
-};
-static struct resource ehci1_resources[] = {
-        [0] = {
-                .start  = 0xfff70000,
-                .end    = 0xfff70400 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = gic_iid(0x4d),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device ehci1_device = {
-        .name   = "ehci-platform",
-        .id     = 1,
-        .dev    = {
-                .dma_mask               = &ehci1_device.dev.coherent_dma_mask,
-                .coherent_dma_mask      = 0xffffffff,
-                .platform_data          = &ehcix_pdata,
-        },
-        .num_resources  = ARRAY_SIZE(ehci1_resources),
-        .resource       = ehci1_resources,
-};
-static struct usb_ohci_pdata ohcix_pdata = {
-        .power_on       = usb_power_on,
-        .power_off      = usb_power_off,
-        .power_suspend  = usb_power_off,
-};
-static struct resource ohci0_resources[] = {
-        [0] = {
-                .start  = 0xffe70400,
-                .end    = 0xffe70800 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = gic_iid(0x4c),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device ohci0_device = {
-        .name   = "ohci-platform",
-        .id     = 0,
-        .dev    = {
-                .dma_mask               = &ohci0_device.dev.coherent_dma_mask,
-                .coherent_dma_mask      = 0xffffffff,
-                .platform_data          = &ohcix_pdata,
-        },
-        .num_resources  = ARRAY_SIZE(ohci0_resources),
-        .resource       = ohci0_resources,
-};
-static struct resource ohci1_resources[] = {
-        [0] = {
-                .start  = 0xfff70400,
-                .end    = 0xfff70800 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = gic_iid(0x4d),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device ohci1_device = {
-        .name   = "ohci-platform",
-        .id     = 1,
-        .dev    = {
-                .dma_mask               = &ohci1_device.dev.coherent_dma_mask,
-                .coherent_dma_mask      = 0xffffffff,
-                .platform_data          = &ohcix_pdata,
-        },
-        .num_resources  = ARRAY_SIZE(ohci1_resources),
-        .resource       = ohci1_resources,
-};
-static struct platform_device *marzen_late_devices[] __initdata = {
-        &ehci0_device,
-        &ehci1_device,
-        &ohci0_device,
-        &ohci1_device,
-};
-void __init marzen_init_late(void)
-{
-        /* get usb phy */
-        phy = usb_get_phy(USB_PHY_TYPE_USB2);
-        shmobile_init_late();
-        platform_add_devices(marzen_late_devices,
-                             ARRAY_SIZE(marzen_late_devices));
-}
 static const struct pinctrl_map marzen_pinctrl_map[] = {
        /* HSPI0 */
        PIN_MAP_MUX_GROUP_DEFAULT("sh-hspi.0", "pfc-r8a7779",
@@ -404,8 +231,10 @@ static void __init marzen_init(void)
        pinctrl_register_mappings(marzen_pinctrl_map,
                                  ARRAY_SIZE(marzen_pinctrl_map));
        r8a7779_pinmux_init();
+        r8a7779_init_irq_extpin(1); /* IRQ1 as individual interrupt */
        r8a7779_add_standard_devices();
+        r8a7779_add_usb_phy_device(&usb_phy_platform_data);
        platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
 }
@@ -416,6 +245,6 @@ MACHINE_START(MARZEN, "marzen")
        .nr_irqs        = NR_IRQS_LEGACY,
        .init_irq       = r8a7779_init_irq,
        .init_machine   = marzen_init,
-        .init_late      = marzen_init_late,
+        .init_late      = r8a7779_init_late,
        .init_time      = r8a7779_earlytimer_init,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
index e710c00c3822..5f7fe628b8a1 100644
--- a/arch/arm/mach-shmobile/clock-r8a73a4.c
+++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
@@ -22,15 +22,44 @@
 #include <linux/kernel.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
+#include <mach/clock.h>
 #include <mach/common.h>
 #define CPG_BASE 0xe6150000
 #define CPG_LEN 0x270
-#define MPCKCR 0xe6150080
 #define SMSTPCR2 0xe6150138
+#define SMSTPCR3 0xe615013c
 #define SMSTPCR5 0xe6150144
+#define FRQCRA          0xE6150000
+#define FRQCRB          0xE6150004
+#define VCLKCR1         0xE6150008
+#define VCLKCR2         0xE615000C
+#define VCLKCR3         0xE615001C
+#define VCLKCR4         0xE6150014
+#define VCLKCR5         0xE6150034
+#define ZBCKCR          0xE6150010
+#define SD0CKCR         0xE6150074
+#define SD1CKCR         0xE6150078
+#define SD2CKCR         0xE615007C
+#define MMC0CKCR        0xE6150240
+#define MMC1CKCR        0xE6150244
+#define FSIACKCR        0xE6150018
+#define FSIBCKCR        0xE6150090
+#define MPCKCR          0xe6150080
+#define SPUVCKCR        0xE6150094
+#define HSICKCR         0xE615026C
+#define M4CKCR          0xE6150098
+#define PLLECR          0xE61500D0
+#define PLL1CR          0xE6150028
+#define PLL2CR          0xE615002C
+#define PLL2SCR         0xE61501F4
+#define PLL2HCR         0xE61501E4
+#define CKSCR           0xE61500C0
+#define CPG_MAP(o) ((o - CPG_BASE) + cpg_mapping.base)
 static struct clk_mapping cpg_mapping = {
        .phys   = CPG_BASE,
        .len    = CPG_LEN,
@@ -51,29 +80,327 @@ static struct clk extal2_clk = {
        .mapping        = &cpg_mapping,
 };
+static struct sh_clk_ops followparent_clk_ops = {
+        .recalc = followparent_recalc,
+};
+static struct clk main_clk = {
+        /* .parent will be set r8a73a4_clock_init */
+        .ops    = &followparent_clk_ops,
+};
+SH_CLK_RATIO(div2,      1, 2);
+SH_CLK_RATIO(div4,      1, 4);
+SH_FIXED_RATIO_CLK(main_div2_clk,       main_clk,               div2);
+SH_FIXED_RATIO_CLK(extal1_div2_clk,     extal1_clk,             div2);
+SH_FIXED_RATIO_CLK(extal2_div2_clk,     extal2_clk,             div2);
+SH_FIXED_RATIO_CLK(extal2_div4_clk,     extal2_clk,             div4);
+/* External FSIACK/FSIBCK clock */
+static struct clk fsiack_clk = {
+};
+static struct clk fsibck_clk = {
+};
+/*
+ *              PLL clocks
+ */
+static struct clk *pll_parent_main[] = {
+        [0] = &main_clk,
+        [1] = &main_div2_clk
+};
+static struct clk *pll_parent_main_extal[8] = {
+        [0] = &main_div2_clk,
+        [1] = &extal2_div2_clk,
+        [3] = &extal2_div4_clk,
+        [4] = &main_clk,
+        [5] = &extal2_clk,
+};
+static unsigned long pll_recalc(struct clk *clk)
+{
+        unsigned long mult = 1;
+        if (ioread32(CPG_MAP(PLLECR)) & (1 << clk->enable_bit))
+                mult = (((ioread32(clk->mapped_reg) >> 24) & 0x7f) + 1);
+        return clk->parent->rate * mult;
+}
+static int pll_set_parent(struct clk *clk, struct clk *parent)
+{
+        u32 val;
+        int i, ret;
+        if (!clk->parent_table || !clk->parent_num)
+                return -EINVAL;
+        /* Search the parent */
+        for (i = 0; i < clk->parent_num; i++)
+                if (clk->parent_table[i] == parent)
+                        break;
+        if (i == clk->parent_num)
+                return -ENODEV;
+        ret = clk_reparent(clk, parent);
+        if (ret < 0)
+                return ret;
+        val = ioread32(clk->mapped_reg) &
+                ~(((1 << clk->src_width) - 1) << clk->src_shift);
+        iowrite32(val | i << clk->src_shift, clk->mapped_reg);
+        return 0;
+}
+static struct sh_clk_ops pll_clk_ops = {
+        .recalc         = pll_recalc,
+        .set_parent     = pll_set_parent,
+};
+#define PLL_CLOCK(name, p, pt, w, s, reg, e)            \
+        static struct clk name = {                      \
+                .ops            = &pll_clk_ops,         \
+                .flags          = CLK_ENABLE_ON_INIT,   \
+                .parent         = p,                    \
+                .parent_table   = pt,                   \
+                .parent_num     = ARRAY_SIZE(pt),       \
+                .src_width      = w,                    \
+                .src_shift      = s,                    \
+                .enable_reg     = (void __iomem *)reg,  \
+                .enable_bit     = e,                    \
+                .mapping        = &cpg_mapping,         \
+        }
+PLL_CLOCK(pll1_clk,  &main_clk,      pll_parent_main,       1, 7, PLL1CR,  1);
+PLL_CLOCK(pll2_clk,  &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2CR,  2);
+PLL_CLOCK(pll2s_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2SCR, 4);
+PLL_CLOCK(pll2h_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2HCR, 5);
+SH_FIXED_RATIO_CLK(pll1_div2_clk,       pll1_clk,       div2);
 static struct clk *main_clks[] = {
        &extalr_clk,
        &extal1_clk,
+        &extal1_div2_clk,
        &extal2_clk,
+        &extal2_div2_clk,
+        &extal2_div4_clk,
+        &main_clk,
+        &main_div2_clk,
+        &fsiack_clk,
+        &fsibck_clk,
+        &pll1_clk,
+        &pll1_div2_clk,
+        &pll2_clk,
+        &pll2s_clk,
+        &pll2h_clk,
+};
+/* DIV4 */
+static void div4_kick(struct clk *clk)
+{
+        unsigned long value;
+        /* set KICK bit in FRQCRB to update hardware setting */
+        value = ioread32(CPG_MAP(FRQCRB));
+        value |= (1 << 31);
+        iowrite32(value, CPG_MAP(FRQCRB));
+}
+static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10};
+static struct clk_div_mult_table div4_div_mult_table = {
+        .divisors       = divisors,
+        .nr_divisors    = ARRAY_SIZE(divisors),
+};
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+        .kick           = div4_kick,
+};
+enum {
+        DIV4_I, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
+        DIV4_ZX, DIV4_ZS, DIV4_HP,
+        DIV4_NR };
+static struct clk div4_clks[DIV4_NR] = {
+        [DIV4_I]        = SH_CLK_DIV4(&pll1_clk, FRQCRA, 20, 0x0dff, CLK_ENABLE_ON_INIT),
+        [DIV4_M3]       = SH_CLK_DIV4(&pll1_clk, FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
+        [DIV4_B]        = SH_CLK_DIV4(&pll1_clk, FRQCRA,  8, 0x0dff, CLK_ENABLE_ON_INIT),
+        [DIV4_M1]       = SH_CLK_DIV4(&pll1_clk, FRQCRA,  4, 0x1dff, 0),
+        [DIV4_M2]       = SH_CLK_DIV4(&pll1_clk, FRQCRA,  0, 0x1dff, 0),
+        [DIV4_ZX]       = SH_CLK_DIV4(&pll1_clk, FRQCRB, 12, 0x0dff, 0),
+        [DIV4_ZS]       = SH_CLK_DIV4(&pll1_clk, FRQCRB,  8, 0x0dff, 0),
+        [DIV4_HP]       = SH_CLK_DIV4(&pll1_clk, FRQCRB,  4, 0x0dff, 0),
 };
 enum {
+        DIV6_ZB,
+        DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
+        DIV6_MMC0, DIV6_MMC1,
+        DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_VCK4, DIV6_VCK5,
+        DIV6_FSIA, DIV6_FSIB,
+        DIV6_MP, DIV6_M4, DIV6_HSI, DIV6_SPUV,
+        DIV6_NR };
+static struct clk *div6_parents[8] = {
+        [0] = &pll1_div2_clk,
+        [1] = &pll2s_clk,
+        [3] = &extal2_clk,
+        [4] = &main_div2_clk,
+        [6] = &extalr_clk,
+};
+static struct clk *fsia_parents[4] = {
+        [0] = &pll1_div2_clk,
+        [1] = &pll2s_clk,
+        [2] = &fsiack_clk,
+};
+static struct clk *fsib_parents[4] = {
+        [0] = &pll1_div2_clk,
+        [1] = &pll2s_clk,
+        [2] = &fsibck_clk,
+};
+static struct clk *mp_parents[4] = {
+        [0] = &pll1_div2_clk,
+        [1] = &pll2s_clk,
+        [2] = &extal2_clk,
+        [3] = &extal2_clk,
+};
+static struct clk *m4_parents[2] = {
+        [0] = &pll2s_clk,
+};
+static struct clk *hsi_parents[4] = {
+        [0] = &pll2h_clk,
+        [1] = &pll1_div2_clk,
+        [3] = &pll2s_clk,
+};
+/*** FIXME ***
+ * SH_CLK_DIV6_EXT() macro doesn't care .mapping
+ * but, it is necessary on R-Car (= ioremap() base CPG)
+ * The difference between
+ * SH_CLK_DIV6_EXT() <--> SH_CLK_MAP_DIV6_EXT()
+ * is only .mapping
+ */
+#define SH_CLK_MAP_DIV6_EXT(_reg, _flags, _parents,                     \
+                            _num_parents, _src_shift, _src_width)       \
+{                                                                       \
+        .enable_reg     = (void __iomem *)_reg,                         \
+        .enable_bit     = 0, /* unused */                               \
+        .flags          = _flags | CLK_MASK_DIV_ON_DISABLE,             \
+        .div_mask       = SH_CLK_DIV6_MSK,                              \
+        .parent_table   = _parents,                                     \
+        .parent_num     = _num_parents,                                 \
+        .src_shift      = _src_shift,                                   \
+        .src_width      = _src_width,                                   \
+        .mapping        = &cpg_mapping,                                 \
+}
+static struct clk div6_clks[DIV6_NR] = {
+        [DIV6_ZB] = SH_CLK_MAP_DIV6_EXT(ZBCKCR, CLK_ENABLE_ON_INIT,
+                                div6_parents, 2, 7, 1),
+        [DIV6_SDHI0] = SH_CLK_MAP_DIV6_EXT(SD0CKCR, 0,
+                                div6_parents, 2, 6, 2),
+        [DIV6_SDHI1] = SH_CLK_MAP_DIV6_EXT(SD1CKCR, 0,
+                                div6_parents, 2, 6, 2),
+        [DIV6_SDHI2] = SH_CLK_MAP_DIV6_EXT(SD2CKCR, 0,
+                                div6_parents, 2, 6, 2),
+        [DIV6_MMC0] = SH_CLK_MAP_DIV6_EXT(MMC0CKCR, 0,
+                                div6_parents, 2, 6, 2),
+        [DIV6_MMC1] = SH_CLK_MAP_DIV6_EXT(MMC1CKCR, 0,
+                                div6_parents, 2, 6, 2),
+        [DIV6_VCK1] = SH_CLK_MAP_DIV6_EXT(VCLKCR1, 0, /* didn't care bit[6-7] */
+                                div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
+        [DIV6_VCK2] = SH_CLK_MAP_DIV6_EXT(VCLKCR2, 0, /* didn't care bit[6-7] */
+                                div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
+        [DIV6_VCK3] = SH_CLK_MAP_DIV6_EXT(VCLKCR3, 0, /* didn't care bit[6-7] */
+                                div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
+        [DIV6_VCK4] = SH_CLK_MAP_DIV6_EXT(VCLKCR4, 0, /* didn't care bit[6-7] */
+                                div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
+        [DIV6_VCK5] = SH_CLK_MAP_DIV6_EXT(VCLKCR5, 0, /* didn't care bit[6-7] */
+                                div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
+        [DIV6_FSIA] = SH_CLK_MAP_DIV6_EXT(FSIACKCR, 0,
+                                fsia_parents, ARRAY_SIZE(fsia_parents), 6, 2),
+        [DIV6_FSIB] = SH_CLK_MAP_DIV6_EXT(FSIBCKCR, 0,
+                                fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2),
+        [DIV6_MP] = SH_CLK_MAP_DIV6_EXT(MPCKCR, 0, /* it needs bit[9-11] control */
+                                mp_parents, ARRAY_SIZE(mp_parents), 6, 2),
+        /* pll2s will be selected always for M4 */
+        [DIV6_M4] = SH_CLK_MAP_DIV6_EXT(M4CKCR, 0, /* it needs bit[9] control */
+                                m4_parents, ARRAY_SIZE(m4_parents), 6, 1),
+        [DIV6_HSI] = SH_CLK_MAP_DIV6_EXT(HSICKCR, 0, /* it needs bit[9] control */
+                                hsi_parents, ARRAY_SIZE(hsi_parents), 6, 2),
+        [DIV6_SPUV] = SH_CLK_MAP_DIV6_EXT(SPUVCKCR, 0,
+                                mp_parents, ARRAY_SIZE(mp_parents), 6, 2),
+};
+/* MSTP */
+enum {
        MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
+        MSTP315, MSTP314, MSTP313, MSTP312, MSTP305,
        MSTP522,
        MSTP_NR
 };
 static struct clk mstp_clks[MSTP_NR] = {
-        [MSTP204] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
+        [MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 4, 0), /* SCIFA0 */
-        [MSTP203] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
+        [MSTP203] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 3, 0), /* SCIFA1 */
-        [MSTP206] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
+        [MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 6, 0), /* SCIFB0 */
-        [MSTP207] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
+        [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 7, 0), /* SCIFB1 */
-        [MSTP216] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
+        [MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 16, 0), /* SCIFB2 */
-        [MSTP217] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 17, 0), /* SCIFB3 */
+        [MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 17, 0), /* SCIFB3 */
+        [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1],SMSTPCR3, 5, 0), /* MMCIF1 */
+        [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI2],SMSTPCR3, 12, 0), /* SDHI2 */
+        [MSTP313] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI1],SMSTPCR3, 13, 0), /* SDHI1 */
+        [MSTP314] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI0],SMSTPCR3, 14, 0), /* SDHI0 */
+        [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0],SMSTPCR3, 15, 0), /* MMCIF0 */
        [MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */
 };
 static struct clk_lookup lookups[] = {
+        /* main clock */
+        CLKDEV_CON_ID("extal1",                 &extal1_clk),
+        CLKDEV_CON_ID("extal1_div2",            &extal1_div2_clk),
+        CLKDEV_CON_ID("extal2",                 &extal2_clk),
+        CLKDEV_CON_ID("extal2_div2",            &extal2_div2_clk),
+        CLKDEV_CON_ID("extal2_div4",            &extal2_div4_clk),
+        CLKDEV_CON_ID("fsiack",                 &fsiack_clk),
+        CLKDEV_CON_ID("fsibck",                 &fsibck_clk),
+        /* pll clock */
+        CLKDEV_CON_ID("pll1",                   &pll1_clk),
+        CLKDEV_CON_ID("pll1_div2",              &pll1_div2_clk),
+        CLKDEV_CON_ID("pll2",                   &pll2_clk),
+        CLKDEV_CON_ID("pll2s",                  &pll2s_clk),
+        CLKDEV_CON_ID("pll2h",                  &pll2h_clk),
+        /* DIV6 */
+        CLKDEV_CON_ID("zb",                     &div6_clks[DIV6_ZB]),
+        CLKDEV_CON_ID("vck1",                   &div6_clks[DIV6_VCK1]),
+        CLKDEV_CON_ID("vck2",                   &div6_clks[DIV6_VCK2]),
+        CLKDEV_CON_ID("vck3",                   &div6_clks[DIV6_VCK3]),
+        CLKDEV_CON_ID("vck4",                   &div6_clks[DIV6_VCK4]),
+        CLKDEV_CON_ID("vck5",                   &div6_clks[DIV6_VCK5]),
+        CLKDEV_CON_ID("fsia",                   &div6_clks[DIV6_FSIA]),
+        CLKDEV_CON_ID("fsib",                   &div6_clks[DIV6_FSIB]),
+        CLKDEV_CON_ID("mp",                     &div6_clks[DIV6_MP]),
+        CLKDEV_CON_ID("m4",                     &div6_clks[DIV6_M4]),
+        CLKDEV_CON_ID("hsi",                    &div6_clks[DIV6_HSI]),
+        CLKDEV_CON_ID("spuv",                   &div6_clks[DIV6_SPUV]),
+        /* MSTP */
        CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
        CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
        CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
@@ -81,6 +408,16 @@ static struct clk_lookup lookups[] = {
        CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
        CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]),
        CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
+        CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
+        CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]),
+        CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
+        CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP312]),
+        CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
+        CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]),
+        CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
+        CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]),
+        CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
+        CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]),
        /* for DT */
        CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
@@ -88,22 +425,40 @@ static struct clk_lookup lookups[] = {
 void __init r8a73a4_clock_init(void)
 {
-        void __iomem *cpg_base, *reg;
+        void __iomem *reg;
        int k, ret = 0;
+        u32 ckscr;
+        reg = ioremap_nocache(CKSCR, PAGE_SIZE);
+        BUG_ON(!reg);
+        ckscr = ioread32(reg);
+        iounmap(reg);
-        /* fix MPCLK to EXTAL2 for now.
+        switch ((ckscr >> 28) & 0x3) {
-         * this is needed until more detailed clock topology is supported
+        case 0:
-         */
+                main_clk.parent = &extal1_clk;
-        cpg_base = ioremap_nocache(CPG_BASE, CPG_LEN);
+                break;
-        BUG_ON(!cpg_base);
+        case 1:
-        reg = cpg_base + (MPCKCR - CPG_BASE);
+                main_clk.parent = &extal1_div2_clk;
-        iowrite32(ioread32(reg) | 1 << 7 | 0x0c, reg); /* set CKSEL */
+                break;
-        iounmap(cpg_base);
+        case 2:
+                main_clk.parent = &extal2_clk;
+                break;
+        case 3:
+                main_clk.parent = &extal2_div2_clk;
+                break;
+        }
        for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
                ret = clk_register(main_clks[k]);
        if (!ret)
+                ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+        if (!ret)
+                ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
+        if (!ret)
                ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index c0d39aa6de50..de10fd78bf2b 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -266,7 +266,7 @@ static struct clk fsiack_clk = {
 static struct clk fsibck_clk = {
 };
-struct clk *main_clks[] = {
+static struct clk *main_clks[] = {
        &extalr_clk,
        &extal1_clk,
        &extal2_clk,
@@ -317,7 +317,7 @@ enum {
        DIV4_NR
 };
-struct clk div4_clks[DIV4_NR] = {
+static struct clk div4_clks[DIV4_NR] = {
        [DIV4_I]        = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
        [DIV4_ZG]       = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
        [DIV4_B]        = SH_CLK_DIV4(&pllc1_clk, FRQCRA,  8, 0x6fff, CLK_ENABLE_ON_INIT),
@@ -461,7 +461,7 @@ enum {
        MSTP329, MSTP328, MSTP323, MSTP320,
        MSTP314, MSTP313, MSTP312,
-        MSTP309,
+        MSTP309, MSTP304,
        MSTP416, MSTP415, MSTP407, MSTP406,
@@ -499,6 +499,7 @@ static struct clk mstp_clks[MSTP_NR] = {
        [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 13, 0), /* SDHI1 */
        [MSTP312] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 12, 0), /* MMC */
        [MSTP309] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3,  9, 0), /* GEther */
+        [MSTP304] = SH_CLK_MSTP32(&div4_clks[DIV4_CP],  SMSTPCR3,  4, 0), /* TPU0 */
        [MSTP416] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR4, 16, 0), /* USBHOST */
        [MSTP415] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR4, 15, 0), /* SDHI2 */
@@ -551,6 +552,7 @@ static struct clk_lookup lookups[] = {
        CLKDEV_DEV_ID("sh_tmu.4",               &mstp_clks[MSTP111]),
        CLKDEV_DEV_ID("sh_tmu.5",               &mstp_clks[MSTP111]),
        CLKDEV_DEV_ID("i2c-sh_mobile.0",        &mstp_clks[MSTP116]),
+        CLKDEV_DEV_ID("fff20000.i2c",           &mstp_clks[MSTP116]),
        CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1",    &mstp_clks[MSTP117]),
        CLKDEV_DEV_ID("sh_tmu.0",               &mstp_clks[MSTP125]),
        CLKDEV_DEV_ID("sh_tmu.1",               &mstp_clks[MSTP125]),
@@ -584,6 +586,7 @@ static struct clk_lookup lookups[] = {
        CLKDEV_DEV_ID("sh_cmt.10",              &mstp_clks[MSTP329]),
        CLKDEV_DEV_ID("sh_fsi2",                &mstp_clks[MSTP328]),
        CLKDEV_DEV_ID("i2c-sh_mobile.1",        &mstp_clks[MSTP323]),
+        CLKDEV_DEV_ID("e6c20000.i2c",           &mstp_clks[MSTP323]),
        CLKDEV_DEV_ID("renesas_usbhs",          &mstp_clks[MSTP320]),
        CLKDEV_DEV_ID("sh_mobile_sdhi.0",       &mstp_clks[MSTP314]),
        CLKDEV_DEV_ID("e6850000.sdhi",          &mstp_clks[MSTP314]),
@@ -591,7 +594,9 @@ static struct clk_lookup lookups[] = {
        CLKDEV_DEV_ID("e6860000.sdhi",          &mstp_clks[MSTP313]),
        CLKDEV_DEV_ID("sh_mmcif",               &mstp_clks[MSTP312]),
        CLKDEV_DEV_ID("e6bd0000.mmcif",         &mstp_clks[MSTP312]),
-        CLKDEV_DEV_ID("sh-eth",                 &mstp_clks[MSTP309]),
+        CLKDEV_DEV_ID("r8a7740-gether",         &mstp_clks[MSTP309]),
+        CLKDEV_DEV_ID("e9a00000.sh-eth",        &mstp_clks[MSTP309]),
+        CLKDEV_DEV_ID("renesas_tpu_pwm",        &mstp_clks[MSTP304]),
        CLKDEV_DEV_ID("sh_mobile_sdhi.2",       &mstp_clks[MSTP415]),
        CLKDEV_DEV_ID("e6870000.sdhi",          &mstp_clks[MSTP415]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c
index cd6855290b1f..a0e9eb72e46d 100644
--- a/arch/arm/mach-shmobile/clock-r8a7778.c
+++ b/arch/arm/mach-shmobile/clock-r8a7778.c
@@ -23,9 +23,23 @@
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
+/*
+ *     MD      MD      MD      MD       PLLA   PLLB    EXTAL   clki    clkz
+ *     19      18      12      11                      (HMz)   (MHz)   (MHz)
+ *----------------------------------------------------------------------------
+ *     1       0       0       0       x21     x21     38.00   800     800
+ *     1       0       0       1       x24     x24     33.33   800     800
+ *     1       0       1       0       x28     x28     28.50   800     800
+ *     1       0       1       1       x32     x32     25.00   800     800
+ *     1       1       0       1       x24     x21     33.33   800     700
+ *     1       1       1       0       x28     x21     28.50   800     600
+ *     1       1       1       1       x32     x24     25.00   800     600
+ */
 #include <linux/io.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
+#include <mach/clock.h>
 #include <mach/common.h>
 #define MSTPCR0         IOMEM(0xffc80030)
@@ -37,6 +51,9 @@
 #define MSTPCR4         IOMEM(0xffc80050)
 #define MSTPCR5         IOMEM(0xffc80054)
 #define MSTPCR6         IOMEM(0xffc80058)
+#define MODEMR          0xFFCC0020
+#define MD(nr)  BIT(nr)
 /* ioremap() through clock mapping mandatory to avoid
 * collision with ARM coherent DMA virtual memory range.
@@ -47,37 +64,94 @@ static struct clk_mapping cpg_mapping = {
        .len    = 0x80,
 };
-static struct clk clkp = {
+static struct clk extal_clk = {
-        .rate   = 62500000, /* FIXME: shortcut */
+        /* .rate will be updated on r8a7778_clock_init() */
-        .flags  = CLK_ENABLE_ON_INIT,
        .mapping = &cpg_mapping,
 };
+/*
+ * clock ratio of these clock will be updated
+ * on r8a7778_clock_init()
+ */
+SH_FIXED_RATIO_CLK_SET(plla_clk,        extal_clk, 1, 1);
+SH_FIXED_RATIO_CLK_SET(pllb_clk,        extal_clk, 1, 1);
+SH_FIXED_RATIO_CLK_SET(i_clk,           plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(s_clk,           plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(s1_clk,          plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(s3_clk,          plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(s4_clk,          plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(b_clk,           plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(out_clk,         plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(p_clk,           plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(g_clk,           plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(z_clk,           pllb_clk,  1, 1);
 static struct clk *main_clks[] = {
-        &clkp,
+        &extal_clk,
+        &plla_clk,
+        &pllb_clk,
+        &i_clk,
+        &s_clk,
+        &s1_clk,
+        &s3_clk,
+        &s4_clk,
+        &b_clk,
+        &out_clk,
+        &p_clk,
+        &g_clk,
+        &z_clk,
 };
 enum {
+        MSTP331,
+        MSTP323, MSTP322, MSTP321,
        MSTP114,
-        MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
+        MSTP100,
+        MSTP030,
+        MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
        MSTP016, MSTP015,
+        MSTP007,
        MSTP_NR };
 static struct clk mstp_clks[MSTP_NR] = {
-        [MSTP114] = SH_CLK_MSTP32(&clkp, MSTPCR1, 14, 0), /* Ether */
+        [MSTP331] = SH_CLK_MSTP32(&s4_clk, MSTPCR3, 31, 0), /* MMC */
-        [MSTP026] = SH_CLK_MSTP32(&clkp, MSTPCR0, 26, 0), /* SCIF0 */
+        [MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */
-        [MSTP025] = SH_CLK_MSTP32(&clkp, MSTPCR0, 25, 0), /* SCIF1 */
+        [MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */
-        [MSTP024] = SH_CLK_MSTP32(&clkp, MSTPCR0, 24, 0), /* SCIF2 */
+        [MSTP321] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 21, 0), /* SDHI2 */
-        [MSTP023] = SH_CLK_MSTP32(&clkp, MSTPCR0, 23, 0), /* SCIF3 */
+        [MSTP114] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 14, 0), /* Ether */
-        [MSTP022] = SH_CLK_MSTP32(&clkp, MSTPCR0, 22, 0), /* SCIF4 */
+        [MSTP100] = SH_CLK_MSTP32(&p_clk, MSTPCR1,  0, 0), /* USB0/1 */
-        [MSTP021] = SH_CLK_MSTP32(&clkp, MSTPCR0, 21, 0), /* SCIF5 */
+        [MSTP030] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 30, 0), /* I2C0 */
-        [MSTP016] = SH_CLK_MSTP32(&clkp, MSTPCR0, 16, 0), /* TMU0 */
+        [MSTP029] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 29, 0), /* I2C1 */
-        [MSTP015] = SH_CLK_MSTP32(&clkp, MSTPCR0, 15, 0), /* TMU1 */
+        [MSTP028] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 28, 0), /* I2C2 */
+        [MSTP027] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 27, 0), /* I2C3 */
+        [MSTP026] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 26, 0), /* SCIF0 */
+        [MSTP025] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 25, 0), /* SCIF1 */
+        [MSTP024] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 24, 0), /* SCIF2 */
+        [MSTP023] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 23, 0), /* SCIF3 */
+        [MSTP022] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 22, 0), /* SCIF4 */
+        [MSTP021] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 21, 0), /* SCIF5 */
+        [MSTP016] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 16, 0), /* TMU0 */
+        [MSTP015] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 15, 0), /* TMU1 */
+        [MSTP007] = SH_CLK_MSTP32(&p_clk, MSTPCR0,  7, 0), /* HSPI */
 };
 static struct clk_lookup lookups[] = {
+        /* main */
+        CLKDEV_CON_ID("shyway_clk",     &s_clk),
+        CLKDEV_CON_ID("peripheral_clk", &p_clk),
        /* MSTP32 clocks */
-        CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */
+        CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP331]), /* MMC */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
+        CLKDEV_DEV_ID("r8a777x-ether", &mstp_clks[MSTP114]), /* Ether */
+        CLKDEV_DEV_ID("ehci-platform", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */
+        CLKDEV_DEV_ID("ohci-platform", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */
+        CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */
+        CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */
+        CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */
+        CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */
        CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
        CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
        CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
@@ -86,12 +160,93 @@ static struct clk_lookup lookups[] = {
        CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
        CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */
        CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP015]), /* TMU01 */
+        CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */
+        CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */
+        CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */
 };
 void __init r8a7778_clock_init(void)
 {
+        void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
+        u32 mode;
        int k, ret = 0;
+        BUG_ON(!modemr);
+        mode = ioread32(modemr);
+        iounmap(modemr);
+        switch (mode & (MD(19) | MD(18) | MD(12) | MD(11))) {
+        case MD(19):
+                extal_clk.rate = 38000000;
+                SH_CLK_SET_RATIO(&plla_clk_ratio,       21, 1);
+                SH_CLK_SET_RATIO(&pllb_clk_ratio,       21, 1);
+                break;
+        case MD(19) | MD(11):
+                extal_clk.rate = 33333333;
+                SH_CLK_SET_RATIO(&plla_clk_ratio,       24, 1);
+                SH_CLK_SET_RATIO(&pllb_clk_ratio,       24, 1);
+                break;
+        case MD(19) | MD(12):
+                extal_clk.rate = 28500000;
+                SH_CLK_SET_RATIO(&plla_clk_ratio,       28, 1);
+                SH_CLK_SET_RATIO(&pllb_clk_ratio,       28, 1);
+                break;
+        case MD(19) | MD(12) | MD(11):
+                extal_clk.rate = 25000000;
+                SH_CLK_SET_RATIO(&plla_clk_ratio,       32, 1);
+                SH_CLK_SET_RATIO(&pllb_clk_ratio,       32, 1);
+                break;
+        case MD(19) | MD(18) | MD(11):
+                extal_clk.rate = 33333333;
+                SH_CLK_SET_RATIO(&plla_clk_ratio,       24, 1);
+                SH_CLK_SET_RATIO(&pllb_clk_ratio,       21, 1);
+                break;
+        case MD(19) | MD(18) | MD(12):
+                extal_clk.rate = 28500000;
+                SH_CLK_SET_RATIO(&plla_clk_ratio,       28, 1);
+                SH_CLK_SET_RATIO(&pllb_clk_ratio,       21, 1);
+                break;
+        case MD(19) | MD(18) | MD(12) | MD(11):
+                extal_clk.rate = 25000000;
+                SH_CLK_SET_RATIO(&plla_clk_ratio,       32, 1);
+                SH_CLK_SET_RATIO(&pllb_clk_ratio,       24, 1);
+                break;
+        default:
+                BUG();
+        }
+        if (mode & MD(1)) {
+                SH_CLK_SET_RATIO(&i_clk_ratio,  1, 1);
+                SH_CLK_SET_RATIO(&s_clk_ratio,  1, 3);
+                SH_CLK_SET_RATIO(&s1_clk_ratio, 1, 6);
+                SH_CLK_SET_RATIO(&s3_clk_ratio, 1, 4);
+                SH_CLK_SET_RATIO(&s4_clk_ratio, 1, 8);
+                SH_CLK_SET_RATIO(&p_clk_ratio,  1, 12);
+                SH_CLK_SET_RATIO(&g_clk_ratio,  1, 12);
+                if (mode & MD(2)) {
+                        SH_CLK_SET_RATIO(&b_clk_ratio,          1, 18);
+                        SH_CLK_SET_RATIO(&out_clk_ratio,        1, 18);
+                } else {
+                        SH_CLK_SET_RATIO(&b_clk_ratio,          1, 12);
+                        SH_CLK_SET_RATIO(&out_clk_ratio,        1, 12);
+                }
+        } else {
+                SH_CLK_SET_RATIO(&i_clk_ratio,  1, 1);
+                SH_CLK_SET_RATIO(&s_clk_ratio,  1, 4);
+                SH_CLK_SET_RATIO(&s1_clk_ratio, 1, 8);
+                SH_CLK_SET_RATIO(&s3_clk_ratio, 1, 4);
+                SH_CLK_SET_RATIO(&s4_clk_ratio, 1, 8);
+                SH_CLK_SET_RATIO(&p_clk_ratio,  1, 16);
+                SH_CLK_SET_RATIO(&g_clk_ratio,  1, 12);
+                if (mode & MD(2)) {
+                        SH_CLK_SET_RATIO(&b_clk_ratio,          1, 16);
+                        SH_CLK_SET_RATIO(&out_clk_ratio,        1, 16);
+                } else {
+                        SH_CLK_SET_RATIO(&b_clk_ratio,          1, 12);
+                        SH_CLK_SET_RATIO(&out_clk_ratio,        1, 12);
+                }
+        }
        for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
                ret = clk_register(main_clks[k]);
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index 31d5cd4d9787..10340f5becbb 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -112,7 +112,7 @@ static struct clk *main_clks[] = {
 };
 enum { MSTP323, MSTP322, MSTP321, MSTP320,
-        MSTP115, MSTP114,
+        MSTP116, MSTP115, MSTP114,
        MSTP103, MSTP101, MSTP100,
        MSTP030,
        MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
@@ -125,6 +125,7 @@ static struct clk mstp_clks[MSTP_NR] = {
        [MSTP322] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 22, 0), /* SDHI1 */
        [MSTP321] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 21, 0), /* SDHI2 */
        [MSTP320] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 20, 0), /* SDHI3 */
+        [MSTP116] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 16, 0), /* PCIe */
        [MSTP115] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 15, 0), /* SATA */
        [MSTP114] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 14, 0), /* Ether */
        [MSTP103] = SH_CLK_MSTP32(&clks_clk, MSTPCR1,  3, 0), /* DU */
@@ -161,9 +162,10 @@ static struct clk_lookup lookups[] = {
        CLKDEV_CON_ID("peripheral_clk", &clkp_clk),
        /* MSTP32 clocks */
+        CLKDEV_DEV_ID("rcar-pcie", &mstp_clks[MSTP116]), /* PCIe */
        CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */
        CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */
-        CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */
+        CLKDEV_DEV_ID("r8a777x-ether", &mstp_clks[MSTP114]), /* Ether */
        CLKDEV_DEV_ID("ehci-platform.1", &mstp_clks[MSTP101]), /* USB EHCI port2 */
        CLKDEV_DEV_ID("ohci-platform.1", &mstp_clks[MSTP101]), /* USB OHCI port2 */
        CLKDEV_DEV_ID("ehci-platform.0", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index bad9bf2e34d6..5d71313df52d 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -22,48 +22,228 @@
 #include <linux/kernel.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
+#include <mach/clock.h>
 #include <mach/common.h>
+/*
+ *   MD         EXTAL           PLL0    PLL1    PLL3
+ * 14 13 19     (MHz)           *1      *1
+ *---------------------------------------------------
+ * 0  0  0      15 x 1          x172/2  x208/2  x106
+ * 0  0  1      15 x 1          x172/2  x208/2  x88
+ * 0  1  0      20 x 1          x130/2  x156/2  x80
+ * 0  1  1      20 x 1          x130/2  x156/2  x66
+ * 1  0  0      26 / 2          x200/2  x240/2  x122
+ * 1  0  1      26 / 2          x200/2  x240/2  x102
+ * 1  1  0      30 / 2          x172/2  x208/2  x106
+ * 1  1  1      30 / 2          x172/2  x208/2  x88
+ *
+ * *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2)
+ *      see "p1 / 2" on R8A7790_CLOCK_ROOT() below
+ */
+#define MD(nr)  (1 << nr)
 #define CPG_BASE 0xe6150000
 #define CPG_LEN 0x1000
 #define SMSTPCR2 0xe6150138
+#define SMSTPCR3 0xe615013c
 #define SMSTPCR7 0xe615014c
+#define MODEMR          0xE6160060
+#define SDCKCR          0xE6150074
+#define SD2CKCR         0xE6150078
+#define SD3CKCR         0xE615007C
+#define MMC0CKCR        0xE6150240
+#define MMC1CKCR        0xE6150244
+#define SSPCKCR         0xE6150248
+#define SSPRSCKCR       0xE615024C
 static struct clk_mapping cpg_mapping = {
        .phys   = CPG_BASE,
        .len    = CPG_LEN,
 };
-static struct clk p_clk = {
+static struct clk extal_clk = {
-        .rate   = 65000000, /* shortcut for now */
+        /* .rate will be updated on r8a7790_clock_init() */
        .mapping        = &cpg_mapping,
 };
-static struct clk mp_clk = {
+static struct sh_clk_ops followparent_clk_ops = {
-        .rate   = 52000000,  /* shortcut for now */
+        .recalc = followparent_recalc,
-        .mapping        = &cpg_mapping,
+};
+static struct clk main_clk = {
+        /* .parent will be set r8a73a4_clock_init */
+        .ops    = &followparent_clk_ops,
 };
+/*
+ * clock ratio of these clock will be updated
+ * on r8a7790_clock_init()
+ */
+SH_FIXED_RATIO_CLK_SET(pll1_clk,                main_clk,       1, 1);
+SH_FIXED_RATIO_CLK_SET(pll3_clk,                main_clk,       1, 1);
+SH_FIXED_RATIO_CLK_SET(lb_clk,                  pll1_clk,       1, 1);
+SH_FIXED_RATIO_CLK_SET(qspi_clk,                pll1_clk,       1, 1);
+/* fixed ratio clock */
+SH_FIXED_RATIO_CLK_SET(extal_div2_clk,          extal_clk,      1, 2);
+SH_FIXED_RATIO_CLK_SET(cp_clk,                  extal_clk,      1, 2);
+SH_FIXED_RATIO_CLK_SET(pll1_div2_clk,           pll1_clk,       1, 2);
+SH_FIXED_RATIO_CLK_SET(zg_clk,                  pll1_clk,       1, 3);
+SH_FIXED_RATIO_CLK_SET(zx_clk,                  pll1_clk,       1, 3);
+SH_FIXED_RATIO_CLK_SET(zs_clk,                  pll1_clk,       1, 6);
+SH_FIXED_RATIO_CLK_SET(hp_clk,                  pll1_clk,       1, 12);
+SH_FIXED_RATIO_CLK_SET(i_clk,                   pll1_clk,       1, 2);
+SH_FIXED_RATIO_CLK_SET(b_clk,                   pll1_clk,       1, 12);
+SH_FIXED_RATIO_CLK_SET(p_clk,                   pll1_clk,       1, 24);
+SH_FIXED_RATIO_CLK_SET(cl_clk,                  pll1_clk,       1, 48);
+SH_FIXED_RATIO_CLK_SET(m2_clk,                  pll1_clk,       1, 8);
+SH_FIXED_RATIO_CLK_SET(imp_clk,                 pll1_clk,       1, 4);
+SH_FIXED_RATIO_CLK_SET(rclk_clk,                pll1_clk,       1, (48 * 1024));
+SH_FIXED_RATIO_CLK_SET(oscclk_clk,              pll1_clk,       1, (12 * 1024));
+SH_FIXED_RATIO_CLK_SET(zb3_clk,                 pll3_clk,       1, 4);
+SH_FIXED_RATIO_CLK_SET(zb3d2_clk,               pll3_clk,       1, 8);
+SH_FIXED_RATIO_CLK_SET(ddr_clk,                 pll3_clk,       1, 8);
+SH_FIXED_RATIO_CLK_SET(mp_clk,                  pll1_div2_clk,  1, 15);
 static struct clk *main_clks[] = {
+        &extal_clk,
+        &extal_div2_clk,
+        &main_clk,
+        &pll1_clk,
+        &pll1_div2_clk,
+        &pll3_clk,
+        &lb_clk,
+        &qspi_clk,
+        &zg_clk,
+        &zx_clk,
+        &zs_clk,
+        &hp_clk,
+        &i_clk,
+        &b_clk,
        &p_clk,
+        &cl_clk,
+        &m2_clk,
+        &imp_clk,
+        &rclk_clk,
+        &oscclk_clk,
+        &zb3_clk,
+        &zb3d2_clk,
+        &ddr_clk,
        &mp_clk,
+        &cp_clk,
+};
+/* SDHI (DIV4) clock */
+static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10 };
+static struct clk_div_mult_table div4_div_mult_table = {
+        .divisors = divisors,
+        .nr_divisors = ARRAY_SIZE(divisors),
+};
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+};
+enum {
+        DIV4_SDH, DIV4_SD0, DIV4_SD1, DIV4_NR
+};
+static struct clk div4_clks[DIV4_NR] = {
+        [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
+        [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT),
+        [DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1de0, CLK_ENABLE_ON_INIT),
+};
+/* DIV6 clocks */
+enum {
+        DIV6_SD2, DIV6_SD3,
+        DIV6_MMC0, DIV6_MMC1,
+        DIV6_SSP, DIV6_SSPRS,
+        DIV6_NR
+};
+static struct clk div6_clks[DIV6_NR] = {
+        [DIV6_SD2]      = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
+        [DIV6_SD3]      = SH_CLK_DIV6(&pll1_div2_clk, SD3CKCR, 0),
+        [DIV6_MMC0]     = SH_CLK_DIV6(&pll1_div2_clk, MMC0CKCR, 0),
+        [DIV6_MMC1]     = SH_CLK_DIV6(&pll1_div2_clk, MMC1CKCR, 0),
+        [DIV6_SSP]      = SH_CLK_DIV6(&pll1_div2_clk, SSPCKCR, 0),
+        [DIV6_SSPRS]    = SH_CLK_DIV6(&pll1_div2_clk, SSPRSCKCR, 0),
+};
+/* MSTP */
+enum {
+        MSTP721, MSTP720,
+        MSTP717, MSTP716,
+        MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304,
+        MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
+        MSTP_NR
 };
-enum { MSTP721, MSTP720,
-        MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP_NR };
 static struct clk mstp_clks[MSTP_NR] = {
        [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
        [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
+        [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, 0), /* MMC0 */
+        [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_SD0], SMSTPCR3, 14, 0), /* SDHI0 */
+        [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_SD1], SMSTPCR3, 13, 0), /* SDHI1 */
+        [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SD2], SMSTPCR3, 12, 0), /* SDHI2 */
+        [MSTP311] = SH_CLK_MSTP32(&div6_clks[DIV6_SD3], SMSTPCR3, 11, 0), /* SDHI3 */
+        [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1], SMSTPCR3, 5, 0), /* MMC1 */
+        [MSTP304] = SH_CLK_MSTP32(&cp_clk, SMSTPCR3, 4, 0), /* TPU0 */
        [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
        [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
        [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
        [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
        [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
        [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */
+        [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */
+        [MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */
 };
 static struct clk_lookup lookups[] = {
+        /* main clocks */
+        CLKDEV_CON_ID("extal",          &extal_clk),
+        CLKDEV_CON_ID("extal_div2",     &extal_div2_clk),
+        CLKDEV_CON_ID("main",           &main_clk),
+        CLKDEV_CON_ID("pll1",           &pll1_clk),
+        CLKDEV_CON_ID("pll1_div2",      &pll1_div2_clk),
+        CLKDEV_CON_ID("pll3",           &pll3_clk),
+        CLKDEV_CON_ID("zg",             &zg_clk),
+        CLKDEV_CON_ID("zx",             &zx_clk),
+        CLKDEV_CON_ID("zs",             &zs_clk),
+        CLKDEV_CON_ID("hp",             &hp_clk),
+        CLKDEV_CON_ID("i",              &i_clk),
+        CLKDEV_CON_ID("b",              &b_clk),
+        CLKDEV_CON_ID("lb",             &lb_clk),
+        CLKDEV_CON_ID("p",              &p_clk),
+        CLKDEV_CON_ID("cl",             &cl_clk),
+        CLKDEV_CON_ID("m2",             &m2_clk),
+        CLKDEV_CON_ID("imp",            &imp_clk),
+        CLKDEV_CON_ID("rclk",           &rclk_clk),
+        CLKDEV_CON_ID("oscclk",         &oscclk_clk),
+        CLKDEV_CON_ID("zb3",            &zb3_clk),
+        CLKDEV_CON_ID("zb3d2",          &zb3d2_clk),
+        CLKDEV_CON_ID("ddr",            &ddr_clk),
+        CLKDEV_CON_ID("mp",             &mp_clk),
+        CLKDEV_CON_ID("qspi",           &qspi_clk),
+        CLKDEV_CON_ID("cp",             &cp_clk),
+        /* DIV4 */
+        CLKDEV_CON_ID("sdh",            &div4_clks[DIV4_SDH]),
+        /* DIV6 */
+        CLKDEV_CON_ID("ssp",            &div6_clks[DIV6_SSP]),
+        CLKDEV_CON_ID("ssprs",          &div6_clks[DIV6_SSPRS]),
+        /* MSTP */
        CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
        CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
        CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
@@ -72,16 +252,77 @@ static struct clk_lookup lookups[] = {
        CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]),
        CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]),
        CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
+        CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]),
+        CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]),
+        CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]),
+        CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
+        CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]),
+        CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
+        CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]),
+        CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
+        CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP312]),
+        CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
+        CLKDEV_DEV_ID("ee160000.sdhi", &mstp_clks[MSTP311]),
+        CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]),
+        CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]),
+        CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
 };
+#define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31)              \
+        extal_clk.rate  = e * 1000 * 1000;                      \
+        main_clk.parent = m;                                    \
+        SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1);           \
+        if (mode & MD(19))                                      \
+                SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1);      \
+        else                                                    \
+                SH_CLK_SET_RATIO(&pll3_clk_ratio, p30, 1)
 void __init r8a7790_clock_init(void)
 {
+        void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
+        u32 mode;
        int k, ret = 0;
+        BUG_ON(!modemr);
+        mode = ioread32(modemr);
+        iounmap(modemr);
+        switch (mode & (MD(14) | MD(13))) {
+        case 0:
+                R8A7790_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
+                break;
+        case MD(13):
+                R8A7790_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66);
+                break;
+        case MD(14):
+                R8A7790_CLOCK_ROOT(26, &extal_div2_clk, 200, 240, 122, 102);
+                break;
+        case MD(13) | MD(14):
+                R8A7790_CLOCK_ROOT(30, &extal_div2_clk, 172, 208, 106, 88);
+                break;
+        }
+        if (mode & (MD(18)))
+                SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 36);
+        else
+                SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 24);
+        if ((mode & (MD(3) | MD(2) | MD(1))) == MD(2))
+                SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16);
+        else
+                SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20);
        for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
                ret = clk_register(main_clks[k]);
        if (!ret)
+                ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+        if (!ret)
+                ret = sh_clk_div6_register(div6_clks, DIV6_NR);
+        if (!ret)
                ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 7e105932c09d..5390c6bbbc02 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -142,15 +142,15 @@ static void pllc2_table_rebuild(struct clk *clk)
        /* Initialise PLLC2 frequency table */
        for (i = 0; i < ARRAY_SIZE(pllc2_freq_table) - 2; i++) {
                pllc2_freq_table[i].frequency = clk->parent->rate * (i + 20) * 2;
-                pllc2_freq_table[i].index = i;
+                pllc2_freq_table[i].driver_data = i;
        }
        /* This is a special entry - switching PLL off makes it a repeater */
        pllc2_freq_table[i].frequency = clk->parent->rate;
-        pllc2_freq_table[i].index = i;
+        pllc2_freq_table[i].driver_data = i;
        pllc2_freq_table[++i].frequency = CPUFREQ_TABLE_END;
-        pllc2_freq_table[i].index = i;
+        pllc2_freq_table[i].driver_data = i;
 }
 static unsigned long pllc2_recalc(struct clk *clk)
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 784fbaa4cc55..d9fd0336b910 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -228,6 +228,11 @@ enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
 static struct clk div4_clks[DIV4_NR] = {
        [DIV4_I] = DIV4(FRQCRA, 20, 0xdff, CLK_ENABLE_ON_INIT),
+        /*
+         * ZG clock is dividing PLL0 frequency to supply SGX. Make sure not to
+         * exceed maximum frequencies of 201.5MHz for VDD_DVFS=1.175 and
+         * 239.2MHz for VDD_DVFS=1.315V.
+         */
        [DIV4_ZG] = SH_CLK_DIV4(&pll0_clk, FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT),
        [DIV4_M3] = DIV4(FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
        [DIV4_B] = DIV4(FRQCRA, 8, 0xdff, CLK_ENABLE_ON_INIT),
@@ -252,6 +257,101 @@ static struct clk twd_clk = {
        .ops = &twd_clk_ops,
 };
+static struct sh_clk_ops zclk_ops, kicker_ops;
+static const struct sh_clk_ops *div4_clk_ops;
+static int zclk_set_rate(struct clk *clk, unsigned long rate)
+{
+        int ret;
+        if (!clk->parent || !__clk_get(clk->parent))
+                return -ENODEV;
+        if (readl(FRQCRB) & (1 << 31))
+                return -EBUSY;
+        if (rate == clk_get_rate(clk->parent)) {
+                /* 1:1 - switch off divider */
+                __raw_writel(__raw_readl(FRQCRB) & ~(1 << 28), FRQCRB);
+                /* nullify the divider to prepare for the next time */
+                ret = div4_clk_ops->set_rate(clk, rate / 2);
+                if (!ret)
+                        ret = frqcr_kick();
+                if (ret > 0)
+                        ret = 0;
+        } else {
+                /* Enable the divider */
+                __raw_writel(__raw_readl(FRQCRB) | (1 << 28), FRQCRB);
+                ret = frqcr_kick();
+                if (ret >= 0)
+                        /*
+                         * set the divider - call the DIV4 method, it will kick
+                         * FRQCRB too
+                         */
+                        ret = div4_clk_ops->set_rate(clk, rate);
+                if (ret < 0)
+                        goto esetrate;
+        }
+esetrate:
+        __clk_put(clk->parent);
+        return ret;
+}
+static long zclk_round_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned long div_freq = div4_clk_ops->round_rate(clk, rate),
+                parent_freq = clk_get_rate(clk->parent);
+        if (rate > div_freq && abs(parent_freq - rate) < rate - div_freq)
+                return parent_freq;
+        return div_freq;
+}
+static unsigned long zclk_recalc(struct clk *clk)
+{
+        /*
+         * Must recalculate frequencies in case PLL0 has been changed, even if
+         * the divisor is unused ATM!
+         */
+        unsigned long div_freq = div4_clk_ops->recalc(clk);
+        if (__raw_readl(FRQCRB) & (1 << 28))
+                return div_freq;
+        return clk_get_rate(clk->parent);
+}
+static int kicker_set_rate(struct clk *clk, unsigned long rate)
+{
+        if (__raw_readl(FRQCRB) & (1 << 31))
+                return -EBUSY;
+        return div4_clk_ops->set_rate(clk, rate);
+}
+static void div4_clk_extend(void)
+{
+        int i;
+        div4_clk_ops = div4_clks[0].ops;
+        /* Add a kicker-busy check before changing the rate */
+        kicker_ops = *div4_clk_ops;
+        /* We extend the DIV4 clock with a 1:1 pass-through case */
+        zclk_ops = *div4_clk_ops;
+        kicker_ops.set_rate = kicker_set_rate;
+        zclk_ops.set_rate = zclk_set_rate;
+        zclk_ops.round_rate = zclk_round_rate;
+        zclk_ops.recalc = zclk_recalc;
+        for (i = 0; i < DIV4_NR; i++)
+                div4_clks[i].ops = i == DIV4_Z ? &zclk_ops : &kicker_ops;
+}
 enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,
        DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
        DIV6_FSIA, DIV6_FSIB, DIV6_SUB,
@@ -450,7 +550,7 @@ static struct clk *late_main_clks[] = {
 };
 enum { MSTP001,
-        MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100,
+        MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP112, MSTP100,
        MSTP219, MSTP218, MSTP217,
        MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
        MSTP331, MSTP329, MSTP328, MSTP325, MSTP323, MSTP322,
@@ -471,6 +571,7 @@ static struct clk mstp_clks[MSTP_NR] = {
        [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
        [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX0 */
        [MSTP116] = MSTP(&div4_clks[DIV4_HP], SMSTPCR1, 16, 0), /* IIC0 */
+        [MSTP112] = MSTP(&div4_clks[DIV4_ZG], SMSTPCR1, 12, 0), /* SGX */
        [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
        [MSTP219] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 19, 0), /* SCIFA7 */
        [MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* SY-DMAC */
@@ -513,6 +614,9 @@ static struct clk_lookup lookups[] = {
        CLKDEV_CON_ID("r_clk", &r_clk),
        CLKDEV_DEV_ID("smp_twd", &twd_clk), /* smp_twd */
+        /* DIV4 clocks */
+        CLKDEV_DEV_ID("cpufreq-cpu0", &div4_clks[DIV4_Z]),
        /* DIV6 clocks */
        CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
        CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
@@ -604,8 +708,11 @@ void __init sh73a0_clock_init(void)
        for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
                ret = clk_register(main_clks[k]);
-        if (!ret)
+        if (!ret) {
                ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+                if (!ret)
+                        div4_clk_extend();
+        }
        if (!ret)
                ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
diff --git a/arch/arm/mach-shmobile/headsmp-scu.S b/arch/arm/mach-shmobile/headsmp-scu.S
index 7d113f898e7f..bfd920083a3b 100644
--- a/arch/arm/mach-shmobile/headsmp-scu.S
+++ b/arch/arm/mach-shmobile/headsmp-scu.S
@@ -23,33 +23,25 @@
 #include <linux/init.h>
 #include <asm/memory.h>
-        __CPUINIT
 /*
- * Reset vector for secondary CPUs.
+ * Boot code for secondary CPUs.
 *
 * First we turn on L1 cache coherency for our CPU. Then we jump to
 * shmobile_invalidate_start that invalidates the cache and hands over control
 * to the common ARM startup code.
- * This function will be mapped to address 0 by the SBAR register.
- * A normal branch is out of range here so we need a long jump. We jump to
- * the physical address as the MMU is still turned off.
 */
-        .align  12
+ENTRY(shmobile_boot_scu)
-ENTRY(shmobile_secondary_vector_scu)
+                                        @ r0 = SCU base address
-        mrc     p15, 0, r0, c0, c0, 5   @ read MIPDR
+        mrc     p15, 0, r1, c0, c0, 5   @ read MIPDR
-        and     r0, r0, #3              @ mask out cpu ID
+        and     r1, r1, #3              @ mask out cpu ID
-        lsl     r0, r0, #3              @ we will shift by cpu_id * 8 bits
+        lsl     r1, r1, #3              @ we will shift by cpu_id * 8 bits
-        ldr     r1, 2f
+        ldr     r2, [r0, #8]            @ SCU Power Status Register
-        ldr     r1, [r1]                @ SCU base address
-        ldr     r2, [r1, #8]            @ SCU Power Status Register
        mov     r3, #3
-        bic     r2, r2, r3, lsl r0      @ Clear bits of our CPU (Run Mode)
+        bic     r2, r2, r3, lsl r1      @ Clear bits of our CPU (Run Mode)
-        str     r2, [r1, #8]            @ write back
+        str     r2, [r0, #8]            @ write back
-        ldr     pc, 1f
+        b       shmobile_invalidate_start
-1:      .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET
+ENDPROC(shmobile_boot_scu)
-2:      .long shmobile_scu_base - PAGE_OFFSET + PLAT_PHYS_OFFSET
-ENDPROC(shmobile_secondary_vector_scu)
        .text
        .globl  shmobile_scu_base
diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S
index 96001fd49b6c..a9d212498987 100644
--- a/arch/arm/mach-shmobile/headsmp.S
+++ b/arch/arm/mach-shmobile/headsmp.S
@@ -14,8 +14,6 @@
 #include <linux/init.h>
 #include <asm/memory.h>
-        __CPUINIT
 ENTRY(shmobile_invalidate_start)
        bl      v7_invalidate_l1
        b       secondary_startup
@@ -27,7 +25,14 @@ ENDPROC(shmobile_invalidate_start)
 * We need _long_ jump to the physical address.
 */
        .align  12
-ENTRY(shmobile_secondary_vector)
+ENTRY(shmobile_boot_vector)
+        ldr     r0, 2f
        ldr     pc, 1f
-1:      .long   shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET
+ENDPROC(shmobile_boot_vector)
-ENDPROC(shmobile_secondary_vector)
+        .globl  shmobile_boot_fn
+shmobile_boot_fn:
+1:      .space  4
+        .globl  shmobile_boot_arg
+shmobile_boot_arg:
+2:      .space  4
diff --git a/arch/arm/mach-shmobile/include/mach/clock.h b/arch/arm/mach-shmobile/include/mach/clock.h
index 76ac61292e48..03e56074928c 100644
--- a/arch/arm/mach-shmobile/include/mach/clock.h
+++ b/arch/arm/mach-shmobile/include/mach/clock.h
@@ -24,16 +24,16 @@ struct clk name = {			\
 }
 #define SH_FIXED_RATIO_CLK(name, p, r)          \
-static SH_FIXED_RATIO_CLKg(name, p, r);
+static SH_FIXED_RATIO_CLKg(name, p, r)
 #define SH_FIXED_RATIO_CLK_SET(name, p, m, d)   \
        SH_CLK_RATIO(name, m, d);               \
-        SH_FIXED_RATIO_CLK(name, p, name);
+        SH_FIXED_RATIO_CLK(name, p, name)
 #define SH_CLK_SET_RATIO(p, m, d)       \
-{                       \
+do {                    \
        (p)->mul = m;   \
        (p)->div = d;   \
-}
+} while (0)
 #endif
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index 4634a5d4b63f..e818f029d8e3 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -7,8 +7,10 @@ extern void shmobile_setup_delay(unsigned int max_cpu_core_mhz,
                         unsigned int mult, unsigned int div);
 struct twd_local_timer;
 extern void shmobile_setup_console(void);
-extern void shmobile_secondary_vector(void);
+extern void shmobile_boot_vector(void);
-extern void shmobile_secondary_vector_scu(void);
+extern unsigned long shmobile_boot_fn;
+extern unsigned long shmobile_boot_arg;
+extern void shmobile_boot_scu(void);
 struct clk;
 extern int shmobile_clk_init(void);
 extern void shmobile_handle_irq_intc(struct pt_regs *);
diff --git a/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt b/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt
deleted file mode 100644
index 9f134dfeffdc..000000000000
--- a/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt
+++ /dev/null
@@ -1,93 +0,0 @@
-LIST "partner-jet-setup.txt"
-LIST "(C) Copyright 2010 Renesas Solutions Corp"
-LIST "Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"
-LIST "RWT Setting"
-EW 0xE6020004, 0xA500
-EW 0xE6030004, 0xA500
-LIST "GPIO Setting"
-EB 0xE6051013, 0xA2
-LIST "CPG"
-ED 0xE61500C0, 0x00000002
-WAIT 1, 0xFE40009C
-LIST "FRQCR"
-ED 0xE6150000, 0x2D1305C3
-ED 0xE61500E0, 0x9E40358E
-ED 0xE6150004, 0x80331050
-WAIT 1, 0xFE40009C
-ED 0xE61500E4, 0x00002000
-WAIT 1, 0xFE40009C
-LIST "PLL"
-ED 0xE6150028, 0x00004000
-WAIT 1, 0xFE40009C
-ED 0xE615002C, 0x93000040
-WAIT 1, 0xFE40009C
-LIST "SUB/USBClk"
-ED 0xE6150080, 0x00000180
-LIST "BSC"
-ED 0xFEC10000, 0x00E0001B
-LIST "SBSC1"
-ED 0xFE400354, 0x01AD8000
-ED 0xFE400354, 0x01AD8001
-WAIT 5, 0xFE40009C
-ED 0xFE400008, 0xBCC90151
-ED 0xFE400040, 0x41774113
-ED 0xFE400044, 0x2712E229
-ED 0xFE400048, 0x20C18505
-ED 0xFE40004C, 0x00110209
-ED 0xFE400010, 0x00000087
-WAIT 30, 0xFE40009C
-ED 0xFE400084, 0x0000003F
-EB 0xFE500000, 0x00
-WAIT 5, 0xFE40009C
-ED 0xFE400084, 0x0000FF0A
-EB 0xFE500000, 0x00
-WAIT 1, 0xFE40009C
-ED 0xFE400084, 0x00002201
-EB 0xFE500000, 0x00
-ED 0xFE400084, 0x00000302
-EB 0xFE500000, 0x00
-EB 0xFE5C0000, 0x00
-ED 0xFE400008, 0xBCC90159
-ED 0xFE40008C, 0x88800004
-ED 0xFE400094, 0x00000004
-ED 0xFE400028, 0xA55A0032
-ED 0xFE40002C, 0xA55A000C
-ED 0xFE400020, 0xA55A2048
-ED 0xFE400008, 0xBCC90959
-LIST "Change CPGA setting"
-ED 0xE61500E0, 0x9E40352E
-ED 0xE6150004, 0x80331050
-WAIT 1, 0xFE40009C
-ED 0xFE400354, 0x01AD8002
-LIST "SCIF0 - Serial port for earlyprintk"
-EB 0xE6053098, 0xe1
-EW 0xE6C40000, 0x0000
-EB 0xE6C40004, 0x19
-EW 0xE6C40008, 0x0030
diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h
index b2074e2acb15..d241bfd6926d 100644
--- a/arch/arm/mach-shmobile/include/mach/irqs.h
+++ b/arch/arm/mach-shmobile/include/mach/irqs.h
@@ -16,4 +16,9 @@
 #define IRQPIN_BASE             2000
 #define irq_pin(nr)             ((nr) + IRQPIN_BASE)
+/* GPIO IRQ */
+#define _GPIO_IRQ_BASE          2500
+#define GPIO_IRQ_BASE(x)        (_GPIO_IRQ_BASE + (32 * x))
+#define GPIO_IRQ(x, y)          (_GPIO_IRQ_BASE + (32 * x) + y)
 #endif /* __ASM_MACH_IRQS_H */
diff --git a/arch/arm/mach-shmobile/include/mach/memory.h b/arch/arm/mach-shmobile/include/mach/memory.h
deleted file mode 100644
index 0ffbe8155c76..000000000000
--- a/arch/arm/mach-shmobile/include/mach/memory.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __ASM_MACH_MEMORY_H
-#define __ASM_MACH_MEMORY_H
-#define PLAT_PHYS_OFFSET        UL(CONFIG_MEMORY_START)
-#define MEM_SIZE        UL(CONFIG_MEMORY_SIZE)
-#endif /* __ASM_MACH_MEMORY_H */
diff --git a/arch/arm/mach-shmobile/include/mach/mmc-ap4eb.h b/arch/arm/mach-shmobile/include/mach/mmc-ap4eb.h
deleted file mode 100644
index db59fdbda860..000000000000
--- a/arch/arm/mach-shmobile/include/mach/mmc-ap4eb.h
+++ /dev/null
@@ -1,29 +0,0 @@
-#ifndef MMC_AP4EB_H
-#define MMC_AP4EB_H
-#define PORT185CR      (void __iomem *)0xe60520b9
-#define PORT186CR      (void __iomem *)0xe60520ba
-#define PORT187CR      (void __iomem *)0xe60520bb
-#define PORT188CR      (void __iomem *)0xe60520bc
-#define PORTR191_160DR (void __iomem *)0xe6056014
-static inline void mmc_init_progress(void)
-{
-       /* Initialise LEDS1-4
-        * registers: PORT185CR-PORT188CR (LED1-LED4 Control)
-        * value:     0x10 - enable output
-        */
-       __raw_writeb(0x10, PORT185CR);
-       __raw_writeb(0x10, PORT186CR);
-       __raw_writeb(0x10, PORT187CR);
-       __raw_writeb(0x10, PORT188CR);
-}
-static inline void mmc_update_progress(int n)
-{
-        __raw_writel((__raw_readl(PORTR191_160DR) & ~(0xf << 25)) |
-                     (1 << (25 + n)), PORTR191_160DR);
-}
-#endif /* MMC_AP4EB_H */
diff --git a/arch/arm/mach-shmobile/include/mach/mmc.h b/arch/arm/mach-shmobile/include/mach/mmc.h
index 21a59db638bb..e979b8fc1da2 100644
--- a/arch/arm/mach-shmobile/include/mach/mmc.h
+++ b/arch/arm/mach-shmobile/include/mach/mmc.h
@@ -7,9 +7,7 @@
 *
 **************************************************/
-#ifdef CONFIG_MACH_AP4EVB
+#ifdef CONFIG_MACH_MACKEREL
-#include "mach/mmc-ap4eb.h"
-#elif defined(CONFIG_MACH_MACKEREL)
 #include "mach/mmc-mackerel.h"
 #else
 #error "unsupported board."
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
index abdc4d4efa28..b34d19b5ca5c 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -28,494 +28,6 @@
 #define MD_CK1  (1 << 1)
 #define MD_CK0  (1 << 0)
-/*
- * Pin Function Controller:
- *      GPIO_FN_xx - GPIO used to select pin function
- *      GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
- */
-enum {
-        /* PORT */
-        GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
-        GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
-        GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
-        GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
-        GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
-        GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
-        GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
-        GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
-        GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
-        GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
-        GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
-        GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
-        GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
-        GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
-        GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
-        GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
-        GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
-        GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
-        GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
-        GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
-        GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
-        GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
-        GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
-        GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
-        GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
-        GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129,
-        GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
-        GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
-        GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
-        GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
-        GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
-        GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
-        GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
-        GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
-        GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
-        GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179,
-        GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184,
-        GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189,
-        GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
-        GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
-        GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
-        GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
-        GPIO_PORT210, GPIO_PORT211,
-        /* IRQ */
-        GPIO_FN_IRQ0_PORT2,     GPIO_FN_IRQ0_PORT13,
-        GPIO_FN_IRQ1,
-        GPIO_FN_IRQ2_PORT11,    GPIO_FN_IRQ2_PORT12,
-        GPIO_FN_IRQ3_PORT10,    GPIO_FN_IRQ3_PORT14,
-        GPIO_FN_IRQ4_PORT15,    GPIO_FN_IRQ4_PORT172,
-        GPIO_FN_IRQ5_PORT0,     GPIO_FN_IRQ5_PORT1,
-        GPIO_FN_IRQ6_PORT121,   GPIO_FN_IRQ6_PORT173,
-        GPIO_FN_IRQ7_PORT120,   GPIO_FN_IRQ7_PORT209,
-        GPIO_FN_IRQ8,
-        GPIO_FN_IRQ9_PORT118,   GPIO_FN_IRQ9_PORT210,
-        GPIO_FN_IRQ10,
-        GPIO_FN_IRQ11,
-        GPIO_FN_IRQ12_PORT42,   GPIO_FN_IRQ12_PORT97,
-        GPIO_FN_IRQ13_PORT64,   GPIO_FN_IRQ13_PORT98,
-        GPIO_FN_IRQ14_PORT63,   GPIO_FN_IRQ14_PORT99,
-        GPIO_FN_IRQ15_PORT62,   GPIO_FN_IRQ15_PORT100,
-        GPIO_FN_IRQ16_PORT68,   GPIO_FN_IRQ16_PORT211,
-        GPIO_FN_IRQ17,
-        GPIO_FN_IRQ18,
-        GPIO_FN_IRQ19,
-        GPIO_FN_IRQ20,
-        GPIO_FN_IRQ21,
-        GPIO_FN_IRQ22,
-        GPIO_FN_IRQ23,
-        GPIO_FN_IRQ24,
-        GPIO_FN_IRQ25,
-        GPIO_FN_IRQ26_PORT58,   GPIO_FN_IRQ26_PORT81,
-        GPIO_FN_IRQ27_PORT57,   GPIO_FN_IRQ27_PORT168,
-        GPIO_FN_IRQ28_PORT56,   GPIO_FN_IRQ28_PORT169,
-        GPIO_FN_IRQ29_PORT50,   GPIO_FN_IRQ29_PORT170,
-        GPIO_FN_IRQ30_PORT49,   GPIO_FN_IRQ30_PORT171,
-        GPIO_FN_IRQ31_PORT41,   GPIO_FN_IRQ31_PORT167,
-        /* Function */
-        /* DBGT */
-        GPIO_FN_DBGMDT2,        GPIO_FN_DBGMDT1,        GPIO_FN_DBGMDT0,
-        GPIO_FN_DBGMD10,        GPIO_FN_DBGMD11,        GPIO_FN_DBGMD20,
-        GPIO_FN_DBGMD21,
-        /* FSI-A */
-        GPIO_FN_FSIAISLD_PORT0,         /* FSIAISLD Port 0/5 */
-        GPIO_FN_FSIAISLD_PORT5,
-        GPIO_FN_FSIASPDIF_PORT9,        /* FSIASPDIF Port 9/18 */
-        GPIO_FN_FSIASPDIF_PORT18,
-        GPIO_FN_FSIAOSLD1,      GPIO_FN_FSIAOSLD2,
-        GPIO_FN_FSIAOLR,        GPIO_FN_FSIAOBT,
-        GPIO_FN_FSIAOSLD,       GPIO_FN_FSIAOMC,
-        GPIO_FN_FSIACK,         GPIO_FN_FSIAILR,
-        GPIO_FN_FSIAIBT,
-        /* FSI-B */
-        GPIO_FN_FSIBCK,
-        /* FMSI */
-        GPIO_FN_FMSISLD_PORT1, /* FMSISLD Port 1/6 */
-        GPIO_FN_FMSISLD_PORT6,
-        GPIO_FN_FMSIILR,        GPIO_FN_FMSIIBT,
-        GPIO_FN_FMSIOLR,        GPIO_FN_FMSIOBT,
-        GPIO_FN_FMSICK,         GPIO_FN_FMSOILR,
-        GPIO_FN_FMSOIBT,        GPIO_FN_FMSOOLR,
-        GPIO_FN_FMSOOBT,        GPIO_FN_FMSOSLD,
-        GPIO_FN_FMSOCK,
-        /* SCIFA0 */
-        GPIO_FN_SCIFA0_SCK,     GPIO_FN_SCIFA0_CTS,
-        GPIO_FN_SCIFA0_RTS,     GPIO_FN_SCIFA0_RXD,
-        GPIO_FN_SCIFA0_TXD,
-        /* SCIFA1 */
-        GPIO_FN_SCIFA1_CTS,     GPIO_FN_SCIFA1_SCK,
-        GPIO_FN_SCIFA1_RXD,     GPIO_FN_SCIFA1_TXD,
-        GPIO_FN_SCIFA1_RTS,
-        /* SCIFA2 */
-        GPIO_FN_SCIFA2_SCK_PORT22, /* SCIFA2_SCK Port 22/199 */
-        GPIO_FN_SCIFA2_SCK_PORT199,
-        GPIO_FN_SCIFA2_RXD,     GPIO_FN_SCIFA2_TXD,
-        GPIO_FN_SCIFA2_CTS,     GPIO_FN_SCIFA2_RTS,
-        /* SCIFA3 */
-        GPIO_FN_SCIFA3_RTS_PORT105, /* MSEL5CR_8_0 */
-        GPIO_FN_SCIFA3_SCK_PORT116,
-        GPIO_FN_SCIFA3_CTS_PORT117,
-        GPIO_FN_SCIFA3_RXD_PORT174,
-        GPIO_FN_SCIFA3_TXD_PORT175,
-        GPIO_FN_SCIFA3_RTS_PORT161, /* MSEL5CR_8_1 */
-        GPIO_FN_SCIFA3_SCK_PORT158,
-        GPIO_FN_SCIFA3_CTS_PORT162,
-        GPIO_FN_SCIFA3_RXD_PORT159,
-        GPIO_FN_SCIFA3_TXD_PORT160,
-        /* SCIFA4 */
-        GPIO_FN_SCIFA4_RXD_PORT12, /* MSEL5CR[12:11] = 00 */
-        GPIO_FN_SCIFA4_TXD_PORT13,
-        GPIO_FN_SCIFA4_RXD_PORT204, /* MSEL5CR[12:11] = 01 */
-        GPIO_FN_SCIFA4_TXD_PORT203,
-        GPIO_FN_SCIFA4_RXD_PORT94, /* MSEL5CR[12:11] = 10 */
-        GPIO_FN_SCIFA4_TXD_PORT93,
-        GPIO_FN_SCIFA4_SCK_PORT21, /* SCIFA4_SCK Port 21/205 */
-        GPIO_FN_SCIFA4_SCK_PORT205,
-        /* SCIFA5 */
-        GPIO_FN_SCIFA5_TXD_PORT20, /* MSEL5CR[15:14] = 00 */
-        GPIO_FN_SCIFA5_RXD_PORT10,
-        GPIO_FN_SCIFA5_RXD_PORT207, /* MSEL5CR[15:14] = 01 */
-        GPIO_FN_SCIFA5_TXD_PORT208,
-        GPIO_FN_SCIFA5_TXD_PORT91, /* MSEL5CR[15:14] = 10 */
-        GPIO_FN_SCIFA5_RXD_PORT92,
-        GPIO_FN_SCIFA5_SCK_PORT23, /* SCIFA5_SCK Port 23/206 */
-        GPIO_FN_SCIFA5_SCK_PORT206,
-        /* SCIFA6 */
-        GPIO_FN_SCIFA6_SCK,     GPIO_FN_SCIFA6_RXD,     GPIO_FN_SCIFA6_TXD,
-        /* SCIFA7 */
-        GPIO_FN_SCIFA7_TXD,     GPIO_FN_SCIFA7_RXD,
-        /* SCIFAB */
-        GPIO_FN_SCIFB_SCK_PORT190, /* MSEL5CR_17_0 */
-        GPIO_FN_SCIFB_RXD_PORT191,
-        GPIO_FN_SCIFB_TXD_PORT192,
-        GPIO_FN_SCIFB_RTS_PORT186,
-        GPIO_FN_SCIFB_CTS_PORT187,
-        GPIO_FN_SCIFB_SCK_PORT2, /* MSEL5CR_17_1 */
-        GPIO_FN_SCIFB_RXD_PORT3,
-        GPIO_FN_SCIFB_TXD_PORT4,
-        GPIO_FN_SCIFB_RTS_PORT172,
-        GPIO_FN_SCIFB_CTS_PORT173,
-        /* LCD0 */
-        GPIO_FN_LCDC0_SELECT,
-        /* LCD1 */
-        GPIO_FN_LCDC1_SELECT,
-        /* RSPI */
-        GPIO_FN_RSPI_SSL0_A,    GPIO_FN_RSPI_SSL1_A,
-        GPIO_FN_RSPI_SSL2_A,    GPIO_FN_RSPI_SSL3_A,
-        GPIO_FN_RSPI_MOSI_A,    GPIO_FN_RSPI_MISO_A,
-        GPIO_FN_RSPI_CK_A,
-        /* VIO CKO */
-        GPIO_FN_VIO_CKO1,
-        GPIO_FN_VIO_CKO2,
-        GPIO_FN_VIO_CKO_1,
-        GPIO_FN_VIO_CKO,
-        /* VIO0 */
-        GPIO_FN_VIO0_D0,        GPIO_FN_VIO0_D1,        GPIO_FN_VIO0_D2,
-        GPIO_FN_VIO0_D3,        GPIO_FN_VIO0_D4,        GPIO_FN_VIO0_D5,
-        GPIO_FN_VIO0_D6,        GPIO_FN_VIO0_D7,        GPIO_FN_VIO0_D8,
-        GPIO_FN_VIO0_D9,        GPIO_FN_VIO0_D10,       GPIO_FN_VIO0_D11,
-        GPIO_FN_VIO0_D12,       GPIO_FN_VIO0_VD,        GPIO_FN_VIO0_HD,
-        GPIO_FN_VIO0_CLK,       GPIO_FN_VIO0_FIELD,
-        GPIO_FN_VIO0_D13_PORT26, /* MSEL5CR_27_0 */
-        GPIO_FN_VIO0_D14_PORT25,
-        GPIO_FN_VIO0_D15_PORT24,
-        GPIO_FN_VIO0_D13_PORT22, /* MSEL5CR_27_1 */
-        GPIO_FN_VIO0_D14_PORT95,
-        GPIO_FN_VIO0_D15_PORT96,
-        /* VIO1 */
-        GPIO_FN_VIO1_D0,        GPIO_FN_VIO1_D1,        GPIO_FN_VIO1_D2,
-        GPIO_FN_VIO1_D3,        GPIO_FN_VIO1_D4,        GPIO_FN_VIO1_D5,
-        GPIO_FN_VIO1_D6,        GPIO_FN_VIO1_D7,        GPIO_FN_VIO1_VD,
-        GPIO_FN_VIO1_HD,        GPIO_FN_VIO1_CLK,       GPIO_FN_VIO1_FIELD,
-        /* TPU0 */
-        GPIO_FN_TPU0TO0,        GPIO_FN_TPU0TO1,
-        GPIO_FN_TPU0TO3,
-        GPIO_FN_TPU0TO2_PORT66, /* TPU0TO2 Port 66/202 */
-        GPIO_FN_TPU0TO2_PORT202,
-        /* SSP1 0 */
-        GPIO_FN_STP0_IPD0,      GPIO_FN_STP0_IPD1,      GPIO_FN_STP0_IPD2,
-        GPIO_FN_STP0_IPD3,      GPIO_FN_STP0_IPD4,      GPIO_FN_STP0_IPD5,
-        GPIO_FN_STP0_IPD6,      GPIO_FN_STP0_IPD7,      GPIO_FN_STP0_IPEN,
-        GPIO_FN_STP0_IPCLK,     GPIO_FN_STP0_IPSYNC,
-        /* SSP1 1 */
-        GPIO_FN_STP1_IPD1,      GPIO_FN_STP1_IPD2,      GPIO_FN_STP1_IPD3,
-        GPIO_FN_STP1_IPD4,      GPIO_FN_STP1_IPD5,      GPIO_FN_STP1_IPD6,
-        GPIO_FN_STP1_IPD7,      GPIO_FN_STP1_IPCLK,     GPIO_FN_STP1_IPSYNC,
-        GPIO_FN_STP1_IPD0_PORT186, /* MSEL5CR_23_0 */
-        GPIO_FN_STP1_IPEN_PORT187,
-        GPIO_FN_STP1_IPD0_PORT194, /* MSEL5CR_23_1 */
-        GPIO_FN_STP1_IPEN_PORT193,
-        /* SIM */
-        GPIO_FN_SIM_RST,        GPIO_FN_SIM_CLK,
-        GPIO_FN_SIM_D_PORT22, /* SIM_D  Port 22/199 */
-        GPIO_FN_SIM_D_PORT199,
-        /* MSIOF2 */
-        GPIO_FN_MSIOF2_TXD,     GPIO_FN_MSIOF2_RXD,     GPIO_FN_MSIOF2_TSCK,
-        GPIO_FN_MSIOF2_SS2,     GPIO_FN_MSIOF2_TSYNC,   GPIO_FN_MSIOF2_SS1,
-        GPIO_FN_MSIOF2_MCK1,    GPIO_FN_MSIOF2_MCK0,    GPIO_FN_MSIOF2_RSYNC,
-        GPIO_FN_MSIOF2_RSCK,
-        /* KEYSC */
-        GPIO_FN_KEYIN4,         GPIO_FN_KEYIN5,
-        GPIO_FN_KEYIN6,         GPIO_FN_KEYIN7,
-        GPIO_FN_KEYOUT0,        GPIO_FN_KEYOUT1,        GPIO_FN_KEYOUT2,
-        GPIO_FN_KEYOUT3,        GPIO_FN_KEYOUT4,        GPIO_FN_KEYOUT5,
-        GPIO_FN_KEYOUT6,        GPIO_FN_KEYOUT7,
-        GPIO_FN_KEYIN0_PORT43, /* MSEL4CR_18_0 */
-        GPIO_FN_KEYIN1_PORT44,
-        GPIO_FN_KEYIN2_PORT45,
-        GPIO_FN_KEYIN3_PORT46,
-        GPIO_FN_KEYIN0_PORT58, /* MSEL4CR_18_1 */
-        GPIO_FN_KEYIN1_PORT57,
-        GPIO_FN_KEYIN2_PORT56,
-        GPIO_FN_KEYIN3_PORT55,
-        /* VOU */
-        GPIO_FN_DV_D0,  GPIO_FN_DV_D1,  GPIO_FN_DV_D2,  GPIO_FN_DV_D3,
-        GPIO_FN_DV_D4,  GPIO_FN_DV_D5,  GPIO_FN_DV_D6,  GPIO_FN_DV_D7,
-        GPIO_FN_DV_D8,  GPIO_FN_DV_D9,  GPIO_FN_DV_D10, GPIO_FN_DV_D11,
-        GPIO_FN_DV_D12, GPIO_FN_DV_D13, GPIO_FN_DV_D14, GPIO_FN_DV_D15,
-        GPIO_FN_DV_CLK,
-        GPIO_FN_DV_VSYNC,
-        GPIO_FN_DV_HSYNC,
-        /* MEMC */
-        GPIO_FN_MEMC_AD0,       GPIO_FN_MEMC_AD1,       GPIO_FN_MEMC_AD2,
-        GPIO_FN_MEMC_AD3,       GPIO_FN_MEMC_AD4,       GPIO_FN_MEMC_AD5,
-        GPIO_FN_MEMC_AD6,       GPIO_FN_MEMC_AD7,       GPIO_FN_MEMC_AD8,
-        GPIO_FN_MEMC_AD9,       GPIO_FN_MEMC_AD10,      GPIO_FN_MEMC_AD11,
-        GPIO_FN_MEMC_AD12,      GPIO_FN_MEMC_AD13,      GPIO_FN_MEMC_AD14,
-        GPIO_FN_MEMC_AD15,      GPIO_FN_MEMC_CS0,       GPIO_FN_MEMC_INT,
-        GPIO_FN_MEMC_NWE,       GPIO_FN_MEMC_NOE,
-        GPIO_FN_MEMC_CS1, /* MSEL4CR_6_0 */
-        GPIO_FN_MEMC_ADV,
-        GPIO_FN_MEMC_WAIT,
-        GPIO_FN_MEMC_BUSCLK,
-        GPIO_FN_MEMC_A1, /* MSEL4CR_6_1 */
-        GPIO_FN_MEMC_DREQ0,
-        GPIO_FN_MEMC_DREQ1,
-        GPIO_FN_MEMC_A0,
-        /* MSIOF0 */
-        GPIO_FN_MSIOF0_SS1,     GPIO_FN_MSIOF0_SS2,
-        GPIO_FN_MSIOF0_RXD,     GPIO_FN_MSIOF0_TXD,
-        GPIO_FN_MSIOF0_MCK0,    GPIO_FN_MSIOF0_MCK1,
-        GPIO_FN_MSIOF0_RSYNC,   GPIO_FN_MSIOF0_RSCK,
-        GPIO_FN_MSIOF0_TSCK,    GPIO_FN_MSIOF0_TSYNC,
-        /* MSIOF1 */
-        GPIO_FN_MSIOF1_RSCK,    GPIO_FN_MSIOF1_RSYNC,
-        GPIO_FN_MSIOF1_MCK0,    GPIO_FN_MSIOF1_MCK1,
-        GPIO_FN_MSIOF1_SS2_PORT116,     GPIO_FN_MSIOF1_SS1_PORT117,
-        GPIO_FN_MSIOF1_RXD_PORT118,     GPIO_FN_MSIOF1_TXD_PORT119,
-        GPIO_FN_MSIOF1_TSYNC_PORT120,
-        GPIO_FN_MSIOF1_TSCK_PORT121,    /* MSEL4CR_10_0 */
-        GPIO_FN_MSIOF1_SS1_PORT67,      GPIO_FN_MSIOF1_TSCK_PORT72,
-        GPIO_FN_MSIOF1_TSYNC_PORT73,    GPIO_FN_MSIOF1_TXD_PORT74,
-        GPIO_FN_MSIOF1_RXD_PORT75,
-        GPIO_FN_MSIOF1_SS2_PORT202,     /* MSEL4CR_10_1 */
-        /* GPIO */
-        GPIO_FN_GPO0,   GPIO_FN_GPI0,
-        GPIO_FN_GPO1,   GPIO_FN_GPI1,
-        /* USB0 */
-        GPIO_FN_USB0_OCI,       GPIO_FN_USB0_PPON,      GPIO_FN_VBUS,
-        /* USB1 */
-        GPIO_FN_USB1_OCI,       GPIO_FN_USB1_PPON,
-        /* BBIF1 */
-        GPIO_FN_BBIF1_RXD,      GPIO_FN_BBIF1_TXD,      GPIO_FN_BBIF1_TSYNC,
-        GPIO_FN_BBIF1_TSCK,     GPIO_FN_BBIF1_RSCK,     GPIO_FN_BBIF1_RSYNC,
-        GPIO_FN_BBIF1_FLOW,     GPIO_FN_BBIF1_RX_FLOW_N,
-        /* BBIF2 */
-        GPIO_FN_BBIF2_TXD2_PORT5, /* MSEL5CR_0_0 */
-        GPIO_FN_BBIF2_RXD2_PORT60,
-        GPIO_FN_BBIF2_TSYNC2_PORT6,
-        GPIO_FN_BBIF2_TSCK2_PORT59,
-        GPIO_FN_BBIF2_RXD2_PORT90, /* MSEL5CR_0_1 */
-        GPIO_FN_BBIF2_TXD2_PORT183,
-        GPIO_FN_BBIF2_TSCK2_PORT89,
-        GPIO_FN_BBIF2_TSYNC2_PORT184,
-        /* BSC / FLCTL / PCMCIA */
-        GPIO_FN_CS0,    GPIO_FN_CS2,    GPIO_FN_CS4,
-        GPIO_FN_CS5B,   GPIO_FN_CS6A,
-        GPIO_FN_CS5A_PORT105, /* CS5A PORT 19/105 */
-        GPIO_FN_CS5A_PORT19,
-        GPIO_FN_IOIS16, /* ? */
-        GPIO_FN_A0,     GPIO_FN_A1,     GPIO_FN_A2,     GPIO_FN_A3,
-        GPIO_FN_A4_FOE,         /* share with FLCTL */
-        GPIO_FN_A5_FCDE,        /* share with FLCTL */
-        GPIO_FN_A6,     GPIO_FN_A7,     GPIO_FN_A8,     GPIO_FN_A9,
-        GPIO_FN_A10,    GPIO_FN_A11,    GPIO_FN_A12,    GPIO_FN_A13,
-        GPIO_FN_A14,    GPIO_FN_A15,    GPIO_FN_A16,    GPIO_FN_A17,
-        GPIO_FN_A18,    GPIO_FN_A19,    GPIO_FN_A20,    GPIO_FN_A21,
-        GPIO_FN_A22,    GPIO_FN_A23,    GPIO_FN_A24,    GPIO_FN_A25,
-        GPIO_FN_A26,
-        GPIO_FN_D0_NAF0,        GPIO_FN_D1_NAF1,        /* share with FLCTL */
-        GPIO_FN_D2_NAF2,        GPIO_FN_D3_NAF3,        /* share with FLCTL */
-        GPIO_FN_D4_NAF4,        GPIO_FN_D5_NAF5,        /* share with FLCTL */
-        GPIO_FN_D6_NAF6,        GPIO_FN_D7_NAF7,        /* share with FLCTL */
-        GPIO_FN_D8_NAF8,        GPIO_FN_D9_NAF9,        /* share with FLCTL */
-        GPIO_FN_D10_NAF10,      GPIO_FN_D11_NAF11,      /* share with FLCTL */
-        GPIO_FN_D12_NAF12,      GPIO_FN_D13_NAF13,      /* share with FLCTL */
-        GPIO_FN_D14_NAF14,      GPIO_FN_D15_NAF15,      /* share with FLCTL */
-        GPIO_FN_D16,    GPIO_FN_D17,    GPIO_FN_D18,    GPIO_FN_D19,
-        GPIO_FN_D20,    GPIO_FN_D21,    GPIO_FN_D22,    GPIO_FN_D23,
-        GPIO_FN_D24,    GPIO_FN_D25,    GPIO_FN_D26,    GPIO_FN_D27,
-        GPIO_FN_D28,    GPIO_FN_D29,    GPIO_FN_D30,    GPIO_FN_D31,
-        GPIO_FN_WE0_FWE,        /* share with FLCTL */
-        GPIO_FN_WE1,
-        GPIO_FN_WE2_ICIORD,     /* share with PCMCIA */
-        GPIO_FN_WE3_ICIOWR,     /* share with PCMCIA */
-        GPIO_FN_CKO,    GPIO_FN_BS,     GPIO_FN_RDWR,
-        GPIO_FN_RD_FSC,         /* share with FLCTL */
-        GPIO_FN_WAIT_PORT177,   /* WAIT Port 90/177 */
-        GPIO_FN_WAIT_PORT90,
-        GPIO_FN_FCE0,   GPIO_FN_FCE1,   GPIO_FN_FRB, /* FLCTL */
-        /* IRDA */
-        GPIO_FN_IRDA_FIRSEL,    GPIO_FN_IRDA_IN,        GPIO_FN_IRDA_OUT,
-        /* ATAPI */
-        GPIO_FN_IDE_D0,         GPIO_FN_IDE_D1,         GPIO_FN_IDE_D2,
-        GPIO_FN_IDE_D3,         GPIO_FN_IDE_D4,         GPIO_FN_IDE_D5,
-        GPIO_FN_IDE_D6,         GPIO_FN_IDE_D7,         GPIO_FN_IDE_D8,
-        GPIO_FN_IDE_D9,         GPIO_FN_IDE_D10,        GPIO_FN_IDE_D11,
-        GPIO_FN_IDE_D12,        GPIO_FN_IDE_D13,        GPIO_FN_IDE_D14,
-        GPIO_FN_IDE_D15,        GPIO_FN_IDE_A0,         GPIO_FN_IDE_A1,
-        GPIO_FN_IDE_A2,         GPIO_FN_IDE_CS0,        GPIO_FN_IDE_CS1,
-        GPIO_FN_IDE_IOWR,       GPIO_FN_IDE_IORD,       GPIO_FN_IDE_IORDY,
-        GPIO_FN_IDE_INT,        GPIO_FN_IDE_RST,        GPIO_FN_IDE_DIRECTION,
-        GPIO_FN_IDE_EXBUF_ENB,  GPIO_FN_IDE_IODACK,     GPIO_FN_IDE_IODREQ,
-        /* RMII */
-        GPIO_FN_RMII_CRS_DV,    GPIO_FN_RMII_RX_ER,     GPIO_FN_RMII_RXD0,
-        GPIO_FN_RMII_RXD1,      GPIO_FN_RMII_TX_EN,     GPIO_FN_RMII_TXD0,
-        GPIO_FN_RMII_MDC,       GPIO_FN_RMII_TXD1,      GPIO_FN_RMII_MDIO,
-        GPIO_FN_RMII_REF50CK,   /* for RMII */
-        GPIO_FN_RMII_REF125CK,  /* for GMII */
-        /* GEther */
-        GPIO_FN_ET_TX_CLK,      GPIO_FN_ET_TX_EN,       GPIO_FN_ET_ETXD0,
-        GPIO_FN_ET_ETXD1,       GPIO_FN_ET_ETXD2,       GPIO_FN_ET_ETXD3,
-        GPIO_FN_ET_ETXD4,       GPIO_FN_ET_ETXD5, /* for GEther */
-        GPIO_FN_ET_ETXD6,       GPIO_FN_ET_ETXD7, /* for GEther */
-        GPIO_FN_ET_COL,         GPIO_FN_ET_TX_ER,
-        GPIO_FN_ET_RX_CLK,      GPIO_FN_ET_RX_DV,
-        GPIO_FN_ET_ERXD0,       GPIO_FN_ET_ERXD1,
-        GPIO_FN_ET_ERXD2,       GPIO_FN_ET_ERXD3,
-        GPIO_FN_ET_ERXD4,       GPIO_FN_ET_ERXD5, /* for GEther */
-        GPIO_FN_ET_ERXD6,       GPIO_FN_ET_ERXD7, /* for GEther */
-        GPIO_FN_ET_RX_ER,       GPIO_FN_ET_CRS,
-        GPIO_FN_ET_MDC,         GPIO_FN_ET_MDIO,
-        GPIO_FN_ET_LINK,        GPIO_FN_ET_PHY_INT,
-        GPIO_FN_ET_WOL,         GPIO_FN_ET_GTX_CLK,
-        /* DMA0 */
-        GPIO_FN_DREQ0,          GPIO_FN_DACK0,
-        /* DMA1 */
-        GPIO_FN_DREQ1,          GPIO_FN_DACK1,
-        /* SYSC */
-        GPIO_FN_RESETOUTS,
-        GPIO_FN_RESETP_PULLUP,
-        GPIO_FN_RESETP_PLAIN,
-        /* HDMI */
-        GPIO_FN_HDMI_HPD,
-        GPIO_FN_HDMI_CEC,
-        /* SDENC */
-        GPIO_FN_SDENC_CPG,
-        GPIO_FN_SDENC_DV_CLKI,
-        /* IRREM */
-        GPIO_FN_IROUT,
-        /* DEBUG */
-        GPIO_FN_EDEBGREQ_PULLDOWN,
-        GPIO_FN_EDEBGREQ_PULLUP,
-        GPIO_FN_TRACEAUD_FROM_VIO,
-        GPIO_FN_TRACEAUD_FROM_LCDC0,
-        GPIO_FN_TRACEAUD_FROM_MEMC,
-};
 /* DMA slave IDs */
 enum {
        SHDMA_SLAVE_INVALID,
@@ -533,10 +45,13 @@ enum {
 };
 extern void r8a7740_meram_workaround(void);
+extern void r8a7740_init_delay(void);
 extern void r8a7740_init_irq(void);
+extern void r8a7740_init_irq_of(void);
 extern void r8a7740_map_io(void);
 extern void r8a7740_add_early_devices(void);
 extern void r8a7740_add_standard_devices(void);
+extern void r8a7740_add_standard_devices_dt(void);
 extern void r8a7740_clock_init(u8 md_ck);
 extern void r8a7740_pinmux_init(void);
 extern void r8a7740_pm_init(void);
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h
index 951149e6bcca..851d027a2f06 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7778.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h
@@ -18,15 +18,26 @@
 #ifndef __ASM_R8A7778_H__
 #define __ASM_R8A7778_H__
+#include <linux/mmc/sh_mmcif.h>
+#include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/sh_eth.h>
+#include <linux/platform_data/usb-rcar-phy.h>
 extern void r8a7778_add_standard_devices(void);
 extern void r8a7778_add_standard_devices_dt(void);
 extern void r8a7778_add_ether_device(struct sh_eth_plat_data *pdata);
+extern void r8a7778_add_usb_phy_device(struct rcar_phy_platform_data *pdata);
+extern void r8a7778_add_i2c_device(int id);
+extern void r8a7778_add_hspi_device(int id);
+extern void r8a7778_add_mmc_device(struct sh_mmcif_plat_data *info);
+extern void r8a7778_init_late(void);
 extern void r8a7778_init_delay(void);
 extern void r8a7778_init_irq(void);
 extern void r8a7778_init_irq_dt(void);
 extern void r8a7778_clock_init(void);
 extern void r8a7778_init_irq_extpin(int irlm);
+extern void r8a7778_pinmux_init(void);
+extern void r8a7778_sdhi_init(int id, struct sh_mobile_sdhi_info *info);
 #endif /* __ASM_R8A7778_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index 188b295938a5..fc47073c7ba9 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -4,6 +4,7 @@
 #include <linux/sh_clk.h>
 #include <linux/pm_domain.h>
 #include <linux/sh_eth.h>
+#include <linux/platform_data/usb-rcar-phy.h>
 struct platform_device;
@@ -33,6 +34,8 @@ extern void r8a7779_add_early_devices(void);
 extern void r8a7779_add_standard_devices(void);
 extern void r8a7779_add_standard_devices_dt(void);
 extern void r8a7779_add_ether_device(struct sh_eth_plat_data *pdata);
+extern void r8a7779_add_usb_phy_device(struct rcar_phy_platform_data *pdata);
+extern void r8a7779_init_late(void);
 extern void r8a7779_clock_init(void);
 extern void r8a7779_pinmux_init(void);
 extern void r8a7779_pm_init(void);
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h
index fd7cba024c39..854a9f0ca040 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -15,397 +15,6 @@
 #include <linux/pm_domain.h>
 #include <mach/pm-rmobile.h>
-/*
- * Pin Function Controller:
- *      GPIO_FN_xx - GPIO used to select pin function
- *      GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
- */
-enum {
-        /* PORT */
-        GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
-        GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
-        GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
-        GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
-        GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
-        GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
-        GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
-        GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
-        GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
-        GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
-        GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
-        GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
-        GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
-        GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
-        GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
-        GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
-        GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
-        GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
-        GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
-        GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
-        GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
-        GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
-        GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
-        GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
-        GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
-        GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129,
-        GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
-        GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
-        GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
-        GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
-        GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
-        GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
-        GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
-        GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
-        GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
-        GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179,
-        GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184,
-        GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189,
-        GPIO_PORT190,
-        /* IRQ */
-        GPIO_FN_IRQ0_6,         /* PORT   6 */
-        GPIO_FN_IRQ0_162,       /* PORT 162 */
-        GPIO_FN_IRQ1,           /* PORT  12 */
-        GPIO_FN_IRQ2_4,         /* PORT   4 */
-        GPIO_FN_IRQ2_5,         /* PORT   5 */
-        GPIO_FN_IRQ3_8,         /* PORT   8 */
-        GPIO_FN_IRQ3_16,        /* PORT  16 */
-        GPIO_FN_IRQ4_17,        /* PORT  17 */
-        GPIO_FN_IRQ4_163,       /* PORT 163 */
-        GPIO_FN_IRQ5,           /* PORT  18 */
-        GPIO_FN_IRQ6_39,        /* PORT  39 */
-        GPIO_FN_IRQ6_164,       /* PORT 164 */
-        GPIO_FN_IRQ7_40,        /* PORT  40 */
-        GPIO_FN_IRQ7_167,       /* PORT 167 */
-        GPIO_FN_IRQ8_41,        /* PORT  41 */
-        GPIO_FN_IRQ8_168,       /* PORT 168 */
-        GPIO_FN_IRQ9_42,        /* PORT  42 */
-        GPIO_FN_IRQ9_169,       /* PORT 169 */
-        GPIO_FN_IRQ10,          /* PORT  65 */
-        GPIO_FN_IRQ11,          /* PORT  67 */
-        GPIO_FN_IRQ12_80,       /* PORT  80 */
-        GPIO_FN_IRQ12_137,      /* PORT 137 */
-        GPIO_FN_IRQ13_81,       /* PORT  81 */
-        GPIO_FN_IRQ13_145,      /* PORT 145 */
-        GPIO_FN_IRQ14_82,       /* PORT  82 */
-        GPIO_FN_IRQ14_146,      /* PORT 146 */
-        GPIO_FN_IRQ15_83,       /* PORT  83 */
-        GPIO_FN_IRQ15_147,      /* PORT 147 */
-        GPIO_FN_IRQ16_84,       /* PORT  84 */
-        GPIO_FN_IRQ16_170,      /* PORT 170 */
-        GPIO_FN_IRQ17,          /* PORT  85 */
-        GPIO_FN_IRQ18,          /* PORT  86 */
-        GPIO_FN_IRQ19,          /* PORT  87 */
-        GPIO_FN_IRQ20,          /* PORT  92 */
-        GPIO_FN_IRQ21,          /* PORT  93 */
-        GPIO_FN_IRQ22,          /* PORT  94 */
-        GPIO_FN_IRQ23,          /* PORT  95 */
-        GPIO_FN_IRQ24,          /* PORT 112 */
-        GPIO_FN_IRQ25,          /* PORT 119 */
-        GPIO_FN_IRQ26_121,      /* PORT 121 */
-        GPIO_FN_IRQ26_172,      /* PORT 172 */
-        GPIO_FN_IRQ27_122,      /* PORT 122 */
-        GPIO_FN_IRQ27_180,      /* PORT 180 */
-        GPIO_FN_IRQ28_123,      /* PORT 123 */
-        GPIO_FN_IRQ28_181,      /* PORT 181 */
-        GPIO_FN_IRQ29_129,      /* PORT 129 */
-        GPIO_FN_IRQ29_182,      /* PORT 182 */
-        GPIO_FN_IRQ30_130,      /* PORT 130 */
-        GPIO_FN_IRQ30_183,      /* PORT 183 */
-        GPIO_FN_IRQ31_138,      /* PORT 138 */
-        GPIO_FN_IRQ31_184,      /* PORT 184 */
-        /*
-         * MSIOF0       (PORT 36, 37, 38, 39
-         *                    40, 41, 42, 43, 44, 45)
-         */
-        GPIO_FN_MSIOF0_TSYNC,   GPIO_FN_MSIOF0_TSCK,
-        GPIO_FN_MSIOF0_RXD,     GPIO_FN_MSIOF0_RSCK,
-        GPIO_FN_MSIOF0_RSYNC,   GPIO_FN_MSIOF0_MCK0,
-        GPIO_FN_MSIOF0_MCK1,    GPIO_FN_MSIOF0_SS1,
-        GPIO_FN_MSIOF0_SS2,     GPIO_FN_MSIOF0_TXD,
-        /*
-         * MSIOF1       (PORT 39, 40, 41, 42, 43, 44
-         *                    84, 85, 86, 87, 88, 89, 90, 91, 92, 93)
-         */
-        GPIO_FN_MSIOF1_TSCK_39, GPIO_FN_MSIOF1_TSYNC_40,
-        GPIO_FN_MSIOF1_TSCK_88, GPIO_FN_MSIOF1_TSYNC_89,
-        GPIO_FN_MSIOF1_TXD_41,  GPIO_FN_MSIOF1_RXD_42,
-        GPIO_FN_MSIOF1_TXD_90,  GPIO_FN_MSIOF1_RXD_91,
-        GPIO_FN_MSIOF1_SS1_43,  GPIO_FN_MSIOF1_SS2_44,
-        GPIO_FN_MSIOF1_SS1_92,  GPIO_FN_MSIOF1_SS2_93,
-        GPIO_FN_MSIOF1_RSCK,    GPIO_FN_MSIOF1_RSYNC,
-        GPIO_FN_MSIOF1_MCK0,    GPIO_FN_MSIOF1_MCK1,
-        /*
-         * MSIOF2       (PORT 134, 135, 136, 137, 138, 139
-         *                    148, 149, 150, 151)
-         */
-        GPIO_FN_MSIOF2_RSCK,    GPIO_FN_MSIOF2_RSYNC,
-        GPIO_FN_MSIOF2_MCK0,    GPIO_FN_MSIOF2_MCK1,
-        GPIO_FN_MSIOF2_SS1,     GPIO_FN_MSIOF2_SS2,
-        GPIO_FN_MSIOF2_TSYNC,   GPIO_FN_MSIOF2_TSCK,
-        GPIO_FN_MSIOF2_RXD,     GPIO_FN_MSIOF2_TXD,
-        /* MSIOF3       (PORT 76, 77, 78, 79, 80, 81, 82, 83) */
-        GPIO_FN_BBIF1_RXD,      GPIO_FN_BBIF1_TSYNC,
-        GPIO_FN_BBIF1_TSCK,     GPIO_FN_BBIF1_TXD,
-        GPIO_FN_BBIF1_RSCK,     GPIO_FN_BBIF1_RSYNC,
-        GPIO_FN_BBIF1_FLOW,     GPIO_FN_BB_RX_FLOW_N,
-        /* MSIOF4       (PORT 0, 1, 2, 3) */
-        GPIO_FN_BBIF2_TSCK1,    GPIO_FN_BBIF2_TSYNC1,
-        GPIO_FN_BBIF2_TXD1,     GPIO_FN_BBIF2_RXD,
-        /* FSI          (PORT 4, 5, 6, 7, 8, 9, 10, 11, 15) */
-        GPIO_FN_FSIACK,         GPIO_FN_FSIBCK,
-        GPIO_FN_FSIAILR,        GPIO_FN_FSIAIBT,
-        GPIO_FN_FSIAISLD,       GPIO_FN_FSIAOMC,
-        GPIO_FN_FSIAOLR,        GPIO_FN_FSIAOBT,
-        GPIO_FN_FSIAOSLD,       GPIO_FN_FSIASPDIF_11,
-        GPIO_FN_FSIASPDIF_15,
-        /* FMSI         (PORT 12, 13, 14, 15, 16, 17, 18, 65) */
-        GPIO_FN_FMSOCK,         GPIO_FN_FMSOOLR,
-        GPIO_FN_FMSIOLR,        GPIO_FN_FMSOOBT,
-        GPIO_FN_FMSIOBT,        GPIO_FN_FMSOSLD,
-        GPIO_FN_FMSOILR,        GPIO_FN_FMSIILR,
-        GPIO_FN_FMSOIBT,        GPIO_FN_FMSIIBT,
-        GPIO_FN_FMSISLD,        GPIO_FN_FMSICK,
-        /* SCIFA0       (PORT 152, 153, 156, 157, 158) */
-        GPIO_FN_SCIFA0_TXD,     GPIO_FN_SCIFA0_RXD,
-        GPIO_FN_SCIFA0_SCK,     GPIO_FN_SCIFA0_RTS,
-        GPIO_FN_SCIFA0_CTS,
-        /* SCIFA1       (PORT 154, 155, 159, 160, 161) */
-        GPIO_FN_SCIFA1_TXD,     GPIO_FN_SCIFA1_RXD,
-        GPIO_FN_SCIFA1_SCK,     GPIO_FN_SCIFA1_RTS,
-        GPIO_FN_SCIFA1_CTS,
-        /* SCIFA2       (PORT 94, 95, 96, 97, 98) */
-        GPIO_FN_SCIFA2_CTS1,    GPIO_FN_SCIFA2_RTS1,
-        GPIO_FN_SCIFA2_TXD1,    GPIO_FN_SCIFA2_RXD1,
-        GPIO_FN_SCIFA2_SCK1,
-        /* SCIFA3       (PORT 43, 44,
-                             140, 141, 142, 143, 144) */
-        GPIO_FN_SCIFA3_CTS_43,  GPIO_FN_SCIFA3_CTS_140,
-        GPIO_FN_SCIFA3_RTS_44,  GPIO_FN_SCIFA3_RTS_141,
-        GPIO_FN_SCIFA3_SCK,     GPIO_FN_SCIFA3_TXD,
-        GPIO_FN_SCIFA3_RXD,
-        /* SCIFA4       (PORT 5, 6) */
-        GPIO_FN_SCIFA4_RXD,     GPIO_FN_SCIFA4_TXD,
-        /* SCIFA5       (PORT 8, 12) */
-        GPIO_FN_SCIFA5_RXD,     GPIO_FN_SCIFA5_TXD,
-        /* SCIFB        (PORT 162, 163, 164, 165, 166) */
-        GPIO_FN_SCIFB_SCK,      GPIO_FN_SCIFB_RTS,
-        GPIO_FN_SCIFB_CTS,      GPIO_FN_SCIFB_TXD,
-        GPIO_FN_SCIFB_RXD,
-        /*
-         * CEU          (PORT 16, 17,
-         *                    100, 101, 102, 103, 104, 105, 106, 107, 108, 109,
-         *                    110, 111, 112, 113, 114, 115, 116, 117, 118, 119,
-         *                    120)
-         */
-        GPIO_FN_VIO_HD,         GPIO_FN_VIO_CKO1,       GPIO_FN_VIO_CKO2,
-        GPIO_FN_VIO_VD,         GPIO_FN_VIO_CLK,        GPIO_FN_VIO_FIELD,
-        GPIO_FN_VIO_CKO,
-        GPIO_FN_VIO_D0,         GPIO_FN_VIO_D1,         GPIO_FN_VIO_D2,
-        GPIO_FN_VIO_D3,         GPIO_FN_VIO_D4,         GPIO_FN_VIO_D5,
-        GPIO_FN_VIO_D6,         GPIO_FN_VIO_D7,         GPIO_FN_VIO_D8,
-        GPIO_FN_VIO_D9,         GPIO_FN_VIO_D10,        GPIO_FN_VIO_D11,
-        GPIO_FN_VIO_D12,        GPIO_FN_VIO_D13,        GPIO_FN_VIO_D14,
-        GPIO_FN_VIO_D15,
-        /* USB0         (PORT 113, 114, 115, 116, 117, 167) */
-        GPIO_FN_IDIN_0,         GPIO_FN_EXTLP_0,
-        GPIO_FN_OVCN2_0,        GPIO_FN_PWEN_0,
-        GPIO_FN_OVCN_0,         GPIO_FN_VBUS0_0,
-        /* USB1         (PORT 18, 113, 114, 115, 116, 117, 138, 162, 168) */
-        GPIO_FN_IDIN_1_18,      GPIO_FN_IDIN_1_113,
-        GPIO_FN_PWEN_1_115,     GPIO_FN_PWEN_1_138,
-        GPIO_FN_OVCN_1_114,     GPIO_FN_OVCN_1_162,
-        GPIO_FN_EXTLP_1,        GPIO_FN_OVCN2_1,
-        GPIO_FN_VBUS0_1,
-        /* GPIO         (PORT 41, 42, 43, 44) */
-        GPIO_FN_GPI0,   GPIO_FN_GPI1,   GPIO_FN_GPO0,   GPIO_FN_GPO1,
-        /*
-         * BSC          (PORT 19,
-         *                    20, 21, 22, 25, 26, 27, 28, 29,
-         *                    30, 31, 32, 33, 34, 35, 36, 37, 38, 39,
-         *                    40, 41, 42, 43, 44, 45,
-         *                    62, 63, 64, 65, 66, 67,
-         *                    71, 72, 74, 75)
-         */
-        GPIO_FN_BS,     GPIO_FN_WE1,
-        GPIO_FN_CKO,    GPIO_FN_WAIT,   GPIO_FN_RDWR,
-        GPIO_FN_A0,     GPIO_FN_A1,     GPIO_FN_A2,     GPIO_FN_A3,
-        GPIO_FN_A6,     GPIO_FN_A7,     GPIO_FN_A8,     GPIO_FN_A9,
-        GPIO_FN_A10,    GPIO_FN_A11,    GPIO_FN_A12,    GPIO_FN_A13,
-        GPIO_FN_A14,    GPIO_FN_A15,    GPIO_FN_A16,    GPIO_FN_A17,
-        GPIO_FN_A18,    GPIO_FN_A19,    GPIO_FN_A20,    GPIO_FN_A21,
-        GPIO_FN_A22,    GPIO_FN_A23,    GPIO_FN_A24,    GPIO_FN_A25,
-        GPIO_FN_A26,
-        GPIO_FN_CS0,    GPIO_FN_CS2,    GPIO_FN_CS4,
-        GPIO_FN_CS5A,   GPIO_FN_CS5B,   GPIO_FN_CS6A,
-        /*
-         * BSC/FLCTL            (PORT 23, 24,
-         *                            46, 47, 48, 49,
-         *                            50, 51, 52, 53, 54, 55, 56, 57, 58, 59,
-         *                            60, 61, 69, 70)
-         */
-        GPIO_FN_RD_FSC,         GPIO_FN_WE0_FWE,
-        GPIO_FN_A4_FOE,         GPIO_FN_A5_FCDE,
-        GPIO_FN_D0_NAF0,        GPIO_FN_D1_NAF1,        GPIO_FN_D2_NAF2,
-        GPIO_FN_D3_NAF3,        GPIO_FN_D4_NAF4,        GPIO_FN_D5_NAF5,
-        GPIO_FN_D6_NAF6,        GPIO_FN_D7_NAF7,        GPIO_FN_D8_NAF8,
-        GPIO_FN_D9_NAF9,        GPIO_FN_D10_NAF10,      GPIO_FN_D11_NAF11,
-        GPIO_FN_D12_NAF12,      GPIO_FN_D13_NAF13,      GPIO_FN_D14_NAF14,
-        GPIO_FN_D15_NAF15,
-        /* SPU2         (PORT 65) */
-        GPIO_FN_VINT_I,
-        /* FLCTL        (PORT 66, 68, 73) */
-        GPIO_FN_FCE1,   GPIO_FN_FCE0,   GPIO_FN_FRB,
-        /* HSI          (PORT 76, 77, 78, 79, 80, 81, 82, 83) */
-        GPIO_FN_GP_RX_FLAG,     GPIO_FN_GP_RX_DATA,     GPIO_FN_GP_TX_READY,
-        GPIO_FN_GP_RX_WAKE,     GPIO_FN_MP_TX_FLAG,     GPIO_FN_MP_TX_DATA,
-        GPIO_FN_MP_RX_READY,    GPIO_FN_MP_TX_WAKE,
-        /*
-         * MFI          (PORT 76, 77, 78, 79,
-         *                    80, 81, 82, 83, 84, 85, 86, 87, 88, 89,
-         *                    90, 91, 92, 93, 94, 95, 96, 97, 98, 99)
-         */
-        GPIO_FN_MFIv6,  /* see MSEL4CR 6 */
-        GPIO_FN_MFIv4,  /* see MSEL4CR 6 */
-        GPIO_FN_MEMC_CS0,               GPIO_FN_MEMC_BUSCLK_MEMC_A0,
-        GPIO_FN_MEMC_CS1_MEMC_A1,       GPIO_FN_MEMC_ADV_MEMC_DREQ0,
-        GPIO_FN_MEMC_WAIT_MEMC_DREQ1,   GPIO_FN_MEMC_NOE,
-        GPIO_FN_MEMC_NWE,               GPIO_FN_MEMC_INT,
-        GPIO_FN_MEMC_AD0,       GPIO_FN_MEMC_AD1,       GPIO_FN_MEMC_AD2,
-        GPIO_FN_MEMC_AD3,       GPIO_FN_MEMC_AD4,       GPIO_FN_MEMC_AD5,
-        GPIO_FN_MEMC_AD6,       GPIO_FN_MEMC_AD7,       GPIO_FN_MEMC_AD8,
-        GPIO_FN_MEMC_AD9,       GPIO_FN_MEMC_AD10,      GPIO_FN_MEMC_AD11,
-        GPIO_FN_MEMC_AD12,      GPIO_FN_MEMC_AD13,      GPIO_FN_MEMC_AD14,
-        GPIO_FN_MEMC_AD15,
-        /* SIM          (PORT 94, 95, 98) */
-        GPIO_FN_SIM_RST,        GPIO_FN_SIM_CLK,        GPIO_FN_SIM_D,
-        /* TPU          (PORT 93, 99, 112, 160, 161) */
-        GPIO_FN_TPU0TO0,        GPIO_FN_TPU0TO1,
-        GPIO_FN_TPU0TO2_93,     GPIO_FN_TPU0TO2_99,
-        GPIO_FN_TPU0TO3,
-        /* I2C2         (PORT 110, 111) */
-        GPIO_FN_I2C_SCL2,       GPIO_FN_I2C_SDA2,
-        /* I2C3(1)      (PORT 114, 115) */
-        GPIO_FN_I2C_SCL3,       GPIO_FN_I2C_SDA3,
-        /* I2C3(2)      (PORT 137, 145) */
-        GPIO_FN_I2C_SCL3S,      GPIO_FN_I2C_SDA3S,
-        /* I2C4(2)      (PORT 116, 117) */
-        GPIO_FN_I2C_SCL4,       GPIO_FN_I2C_SDA4,
-        /* I2C4(2)      (PORT 146, 147) */
-        GPIO_FN_I2C_SCL4S,      GPIO_FN_I2C_SDA4S,
-        /*
-         * KEYSC        (PORT 121, 122, 123, 124, 125, 126, 127, 128, 129,
-         *                    130, 131, 132, 133, 134, 135, 136)
-         */
-        GPIO_FN_KEYOUT0,        GPIO_FN_KEYIN0_121,     GPIO_FN_KEYIN0_136,
-        GPIO_FN_KEYOUT1,        GPIO_FN_KEYIN1_122,     GPIO_FN_KEYIN1_135,
-        GPIO_FN_KEYOUT2,        GPIO_FN_KEYIN2_123,     GPIO_FN_KEYIN2_134,
-        GPIO_FN_KEYOUT3,        GPIO_FN_KEYIN3_124,     GPIO_FN_KEYIN3_133,
-        GPIO_FN_KEYOUT4,        GPIO_FN_KEYIN4,
-        GPIO_FN_KEYOUT5,        GPIO_FN_KEYIN5,
-        GPIO_FN_KEYOUT6,        GPIO_FN_KEYIN6,
-        GPIO_FN_KEYOUT7,        GPIO_FN_KEYIN7,
-        /*
-         * LCDC         (PORT      121, 122, 123, 124, 125, 126, 127, 128, 129,
-         *                    130, 131, 132, 133, 134, 135, 136, 137, 138, 139,
-         *                    140, 141, 142, 143, 144, 145, 146, 147, 148, 149,
-         *                    150, 151)
-         */
-        GPIO_FN_LCDC0_SELECT, /* LCDC 0 */
-        GPIO_FN_LCDC1_SELECT, /* LCDC 1 */
-        GPIO_FN_LCDHSYN,        GPIO_FN_LCDCS,  GPIO_FN_LCDVSYN,
-        GPIO_FN_LCDDCK,         GPIO_FN_LCDWR,  GPIO_FN_LCDRD,
-        GPIO_FN_LCDDISP,        GPIO_FN_LCDRS,  GPIO_FN_LCDLCLK,
-        GPIO_FN_LCDDON,
-        GPIO_FN_LCDD0,  GPIO_FN_LCDD1,  GPIO_FN_LCDD2,  GPIO_FN_LCDD3,
-        GPIO_FN_LCDD4,  GPIO_FN_LCDD5,  GPIO_FN_LCDD6,  GPIO_FN_LCDD7,
-        GPIO_FN_LCDD8,  GPIO_FN_LCDD9,  GPIO_FN_LCDD10, GPIO_FN_LCDD11,
-        GPIO_FN_LCDD12, GPIO_FN_LCDD13, GPIO_FN_LCDD14, GPIO_FN_LCDD15,
-        GPIO_FN_LCDD16, GPIO_FN_LCDD17, GPIO_FN_LCDD18, GPIO_FN_LCDD19,
-        GPIO_FN_LCDD20, GPIO_FN_LCDD21, GPIO_FN_LCDD22, GPIO_FN_LCDD23,
-        /* IRDA         (PORT 139, 140, 141, 142) */
-        GPIO_FN_IRDA_OUT,       GPIO_FN_IRDA_IN,        GPIO_FN_IRDA_FIRSEL,
-        GPIO_FN_IROUT_139,      GPIO_FN_IROUT_140,
-        /* TSIF1        (PORT 156, 157, 158, 159) */
-        GPIO_FN_TS0_1SELECT, /* TSIF0 - 1 select */
-        GPIO_FN_TS0_2SELECT, /* TSIF0 - 2 select */
-        GPIO_FN_TS1_1SELECT, /* TSIF1 - 1 select */
-        GPIO_FN_TS1_2SELECT, /* TSIF1 - 2 select */
-        GPIO_FN_TS_SPSYNC1,     GPIO_FN_TS_SDAT1,
-        GPIO_FN_TS_SDEN1,       GPIO_FN_TS_SCK1,
-        /* TSIF2        (PORT 137, 145, 146, 147) */
-        GPIO_FN_TS_SPSYNC2,     GPIO_FN_TS_SDAT2,
-        GPIO_FN_TS_SDEN2,       GPIO_FN_TS_SCK2,
-        /* HDMI         (PORT 169, 170) */
-        GPIO_FN_HDMI_HPD,       GPIO_FN_HDMI_CEC,
-        /* SDENC        see MSEL4CR 19 */
-        GPIO_FN_SDENC_CPG,
-        GPIO_FN_SDENC_DV_CLKI,
-};
 /* DMA slave IDs */
 enum {
        SHDMA_SLAVE_INVALID,
@@ -466,6 +75,8 @@ extern void sh7372_intcs_resume(void);
 extern void sh7372_intca_suspend(void);
 extern void sh7372_intca_resume(void);
+extern unsigned long sh7372_cpu_resume;
 #ifdef CONFIG_PM
 extern void __init sh7372_init_pm_domains(void);
 #else
diff --git a/arch/arm/mach-shmobile/include/mach/zboot.h b/arch/arm/mach-shmobile/include/mach/zboot.h
index 9320aff0a20f..f2d8744c1f14 100644
--- a/arch/arm/mach-shmobile/include/mach/zboot.h
+++ b/arch/arm/mach-shmobile/include/mach/zboot.h
@@ -10,11 +10,9 @@
 *
 **************************************************/
-#ifdef CONFIG_MACH_AP4EVB
+#ifdef CONFIG_MACH_MACKEREL
-#define MACH_TYPE       MACH_TYPE_AP4EVB
-#include "mach/head-ap4evb.txt"
-#elif defined(CONFIG_MACH_MACKEREL)
 #define MACH_TYPE       MACH_TYPE_MACKEREL
+#define MEMORY_START    0x40000000
 #include "mach/head-mackerel.txt"
 #else
 #error "unsupported board."
diff --git a/arch/arm/mach-shmobile/intc-r8a7740.c b/arch/arm/mach-shmobile/intc-r8a7740.c
index b741c8409a5a..8871f7717dc8 100644
--- a/arch/arm/mach-shmobile/intc-r8a7740.c
+++ b/arch/arm/mach-shmobile/intc-r8a7740.c
@@ -20,19 +20,15 @@
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/irqchip.h>
 #include <linux/irqchip/arm-gic.h>
-void __init r8a7740_init_irq(void)
+static void __init r8a7740_init_irq_common(void)
 {
-        void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000);
-        void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000);
        void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10);
        void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10);
        void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4);
-        /* initialize the Generic Interrupt Controller PL390 r0p0 */
-        gic_init(0, 29, gic_dist_base, gic_cpu_base);
        /* route signals to GIC */
        iowrite32(0x0, pfc_inta_ctrl);
@@ -54,3 +50,19 @@ void __init r8a7740_init_irq(void)
        iounmap(intc_msk_base);
        iounmap(pfc_inta_ctrl);
 }
+void __init r8a7740_init_irq_of(void)
+{
+        irqchip_init();
+        r8a7740_init_irq_common();
+}
+void __init r8a7740_init_irq(void)
+{
+        void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000);
+        void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000);
+        /* initialize the Generic Interrupt Controller PL390 r0p0 */
+        gic_init(0, 29, gic_dist_base, gic_cpu_base);
+        r8a7740_init_irq_common();
+}
diff --git a/arch/arm/mach-shmobile/pm-sh7372.c b/arch/arm/mach-shmobile/pm-sh7372.c
index dec9293bb90d..0de75fd394b9 100644
--- a/arch/arm/mach-shmobile/pm-sh7372.c
+++ b/arch/arm/mach-shmobile/pm-sh7372.c
@@ -351,6 +351,9 @@ static void sh7372_enter_a4s_common(int pllc0_on)
 static void sh7372_pm_setup_smfram(void)
 {
+        /* pass physical address of cpu_resume() to assembly resume code */
+        sh7372_cpu_resume = virt_to_phys(cpu_resume);
        memcpy((void *)SMFRAM, sh7372_resume_core_standby_sysc, 0x100);
 }
 #else
diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c
index 899a86c31ec9..1ccddd228112 100644
--- a/arch/arm/mach-shmobile/setup-emev2.c
+++ b/arch/arm/mach-shmobile/setup-emev2.c
@@ -287,14 +287,14 @@ static struct gpio_em_config gio3_config = {
 static struct resource gio3_resources[] = {
        [0] = {
                .name   = "GIO_096",
-                .start  = 0xe0050100,
+                .start  = 0xe0050180,
-                .end    = 0xe005012b,
+                .end    = 0xe00501ab,
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
                .name   = "GIO_096",
-                .start  = 0xe0050140,
+                .start  = 0xe00501c0,
-                .end    = 0xe005015f,
+                .end    = 0xe00501df,
                .flags  = IORESOURCE_MEM,
        },
        [2] = {
diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
index c5a75a7a508f..7f45c2edbca9 100644
--- a/arch/arm/mach-shmobile/setup-r8a73a4.c
+++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
@@ -62,7 +62,7 @@ enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFB3 };
 static const struct plat_sci_port scif[] = {
        SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
        SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
-        SCIFB_DATA(SCIFB0, 0xe6c50000, gic_spi(145)), /* SCIFB0 */
+        SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
        SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
        SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
        SCIFB_DATA(SCIFB3, 0xe6cf0000, gic_spi(151)), /* SCIFB3 */
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 326a4ab0bd5f..00c5a707238b 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -70,29 +70,15 @@ void __init r8a7740_map_io(void)
 }
 /* PFC */
-static struct resource r8a7740_pfc_resources[] = {
+static const struct resource pfc_resources[] = {
-        [0] = {
+        DEFINE_RES_MEM(0xe6050000, 0x8000),
-                .start  = 0xe6050000,
+        DEFINE_RES_MEM(0xe605800c, 0x0020),
-                .end    = 0xe6057fff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = 0xe605800c,
-                .end    = 0xe605802b,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-static struct platform_device r8a7740_pfc_device = {
-        .name           = "pfc-r8a7740",
-        .id             = -1,
-        .resource       = r8a7740_pfc_resources,
-        .num_resources  = ARRAY_SIZE(r8a7740_pfc_resources),
 };
 void __init r8a7740_pinmux_init(void)
 {
-        platform_device_register(&r8a7740_pfc_device);
+        platform_device_register_simple("pfc-r8a7740", -1, pfc_resources,
+                                        ARRAY_SIZE(pfc_resources));
 }
 static struct renesas_intc_irqpin_config irqpin0_platform_data = {
@@ -531,11 +517,7 @@ static struct platform_device ipmmu_device = {
        .num_resources  = ARRAY_SIZE(ipmmu_resources),
 };
-static struct platform_device *r8a7740_early_devices[] __initdata = {
+static struct platform_device *r8a7740_devices_dt[] __initdata = {
-        &irqpin0_device,
-        &irqpin1_device,
-        &irqpin2_device,
-        &irqpin3_device,
        &scif0_device,
        &scif1_device,
        &scif2_device,
@@ -546,6 +528,13 @@ static struct platform_device *r8a7740_early_devices[] __initdata = {
        &scif7_device,
        &scifb_device,
        &cmt10_device,
+};
+static struct platform_device *r8a7740_early_devices[] __initdata = {
+        &irqpin0_device,
+        &irqpin1_device,
+        &irqpin2_device,
+        &irqpin3_device,
        &tmu00_device,
        &tmu01_device,
        &tmu02_device,
@@ -965,6 +954,8 @@ void __init r8a7740_add_standard_devices(void)
        /* add devices */
        platform_add_devices(r8a7740_early_devices,
                            ARRAY_SIZE(r8a7740_early_devices));
+        platform_add_devices(r8a7740_devices_dt,
+                            ARRAY_SIZE(r8a7740_devices_dt));
        platform_add_devices(r8a7740_late_devices,
                             ARRAY_SIZE(r8a7740_late_devices));
@@ -986,6 +977,8 @@ void __init r8a7740_add_early_devices(void)
 {
        early_platform_add_devices(r8a7740_early_devices,
                                   ARRAY_SIZE(r8a7740_early_devices));
+        early_platform_add_devices(r8a7740_devices_dt,
+                                   ARRAY_SIZE(r8a7740_devices_dt));
        /* setup early console here as well */
        shmobile_setup_console();
@@ -993,33 +986,29 @@ void __init r8a7740_add_early_devices(void)
 #ifdef CONFIG_USE_OF
-void __init r8a7740_add_early_devices_dt(void)
-{
-        shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
-        early_platform_add_devices(r8a7740_early_devices,
-                                   ARRAY_SIZE(r8a7740_early_devices));
-        /* setup early console here as well */
-        shmobile_setup_console();
-}
 static const struct of_dev_auxdata r8a7740_auxdata_lookup[] __initconst = {
        { }
 };
 void __init r8a7740_add_standard_devices_dt(void)
 {
-        /* clocks are setup late during boot in the case of DT */
+        platform_add_devices(r8a7740_devices_dt,
-        r8a7740_clock_init(0);
+                            ARRAY_SIZE(r8a7740_devices_dt));
-        platform_add_devices(r8a7740_early_devices,
-                            ARRAY_SIZE(r8a7740_early_devices));
        of_platform_populate(NULL, of_default_bus_match_table,
                             r8a7740_auxdata_lookup, NULL);
 }
+void __init r8a7740_init_delay(void)
+{
+        shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
+};
+static void __init r8a7740_generic_init(void)
+{
+        r8a7740_clock_init(0);
+        r8a7740_add_standard_devices_dt();
+}
 static const char *r8a7740_boards_compat_dt[] __initdata = {
        "renesas,r8a7740",
        NULL,
@@ -1027,9 +1016,10 @@ static const char *r8a7740_boards_compat_dt[] __initdata = {
 DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
        .map_io         = r8a7740_map_io,
-        .init_early     = r8a7740_add_early_devices_dt,
+        .init_early     = r8a7740_init_delay,
-        .init_irq       = r8a7740_init_irq,
+        .init_irq       = r8a7740_init_irq_of,
-        .init_machine   = r8a7740_add_standard_devices_dt,
+        .init_machine   = r8a7740_generic_init,
+        .init_time      = shmobile_timer_init,
        .dt_compat      = r8a7740_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index 30b4a336308f..80c20392ad7c 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -24,11 +24,18 @@
 #include <linux/irqchip/arm-gic.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
+#include <linux/platform_data/gpio-rcar.h>
 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
 #include <linux/platform_device.h>
 #include <linux/irqchip.h>
 #include <linux/serial_sci.h>
 #include <linux/sh_timer.h>
+#include <linux/pm_runtime.h>
+#include <linux/usb/phy.h>
+#include <linux/usb/hcd.h>
+#include <linux/usb/ehci_pdriver.h>
+#include <linux/usb/ohci_pdriver.h>
+#include <linux/dma-mapping.h>
 #include <mach/irqs.h>
 #include <mach/r8a7778.h>
 #include <mach/common.h>
@@ -80,12 +87,6 @@ static struct sh_timer_config sh_tmu1_platform_data = {
        .clocksource_rating     = 200,
 };
-/* Ether */
-static struct resource ether_resources[] = {
-        DEFINE_RES_MEM(0xfde00000, 0x400),
-        DEFINE_RES_IRQ(gic_iid(0x89)),
-};
 #define r8a7778_register_tmu(idx)                       \
        platform_device_register_resndata(              \
                &platform_bus, "sh_tmu", idx,           \
@@ -94,6 +95,244 @@ static struct resource ether_resources[] = {
                &sh_tmu##idx##_platform_data,           \
                sizeof(sh_tmu##idx##_platform_data))
+/* USB PHY */
+static struct resource usb_phy_resources[] __initdata = {
+        DEFINE_RES_MEM(0xffe70800, 0x100),
+        DEFINE_RES_MEM(0xffe76000, 0x100),
+};
+void __init r8a7778_add_usb_phy_device(struct rcar_phy_platform_data *pdata)
+{
+        platform_device_register_resndata(&platform_bus, "rcar_usb_phy", -1,
+                                          usb_phy_resources,
+                                          ARRAY_SIZE(usb_phy_resources),
+                                          pdata, sizeof(*pdata));
+}
+/* USB */
+static struct usb_phy *phy;
+static int usb_power_on(struct platform_device *pdev)
+{
+        if (IS_ERR(phy))
+                return PTR_ERR(phy);
+        pm_runtime_enable(&pdev->dev);
+        pm_runtime_get_sync(&pdev->dev);
+        usb_phy_init(phy);
+        return 0;
+}
+static void usb_power_off(struct platform_device *pdev)
+{
+        if (IS_ERR(phy))
+                return;
+        usb_phy_shutdown(phy);
+        pm_runtime_put_sync(&pdev->dev);
+        pm_runtime_disable(&pdev->dev);
+}
+static int ehci_init_internal_buffer(struct usb_hcd *hcd)
+{
+        /*
+         * Below are recommended values from the datasheet;
+         * see [USB :: Setting of EHCI Internal Buffer].
+         */
+        /* EHCI IP internal buffer setting */
+        iowrite32(0x00ff0040, hcd->regs + 0x0094);
+        /* EHCI IP internal buffer enable */
+        iowrite32(0x00000001, hcd->regs + 0x009C);
+        return 0;
+}
+static struct usb_ehci_pdata ehci_pdata __initdata = {
+        .power_on       = usb_power_on,
+        .power_off      = usb_power_off,
+        .power_suspend  = usb_power_off,
+        .pre_setup      = ehci_init_internal_buffer,
+};
+static struct resource ehci_resources[] __initdata = {
+        DEFINE_RES_MEM(0xffe70000, 0x400),
+        DEFINE_RES_IRQ(gic_iid(0x4c)),
+};
+static struct usb_ohci_pdata ohci_pdata __initdata = {
+        .power_on       = usb_power_on,
+        .power_off      = usb_power_off,
+        .power_suspend  = usb_power_off,
+};
+static struct resource ohci_resources[] __initdata = {
+        DEFINE_RES_MEM(0xffe70400, 0x400),
+        DEFINE_RES_IRQ(gic_iid(0x4c)),
+};
+#define USB_PLATFORM_INFO(hci)                                  \
+static struct platform_device_info hci##_info __initdata = {    \
+        .parent         = &platform_bus,                        \
+        .name           = #hci "-platform",                     \
+        .id             = -1,                                   \
+        .res            = hci##_resources,                      \
+        .num_res        = ARRAY_SIZE(hci##_resources),          \
+        .data           = &hci##_pdata,                         \
+        .size_data      = sizeof(hci##_pdata),                  \
+        .dma_mask       = DMA_BIT_MASK(32),                     \
+}
+USB_PLATFORM_INFO(ehci);
+USB_PLATFORM_INFO(ohci);
+/* Ether */
+static struct resource ether_resources[] = {
+        DEFINE_RES_MEM(0xfde00000, 0x400),
+        DEFINE_RES_IRQ(gic_iid(0x89)),
+};
+void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata)
+{
+        platform_device_register_resndata(&platform_bus, "r8a777x-ether", -1,
+                                          ether_resources,
+                                          ARRAY_SIZE(ether_resources),
+                                          pdata, sizeof(*pdata));
+}
+/* PFC/GPIO */
+static struct resource pfc_resources[] = {
+        DEFINE_RES_MEM(0xfffc0000, 0x118),
+};
+#define R8A7778_GPIO(idx)                                               \
+static struct resource r8a7778_gpio##idx##_resources[] = {              \
+        DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30),              \
+        DEFINE_RES_IRQ(gic_iid(0x87)),                                  \
+};                                                                      \
+                                                                        \
+static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data = {    \
+        .gpio_base      = 32 * (idx),                                   \
+        .irq_base       = GPIO_IRQ_BASE(idx),                           \
+        .number_of_pins = 32,                                           \
+        .pctl_name      = "pfc-r8a7778",                                \
+}
+R8A7778_GPIO(0);
+R8A7778_GPIO(1);
+R8A7778_GPIO(2);
+R8A7778_GPIO(3);
+R8A7778_GPIO(4);
+#define r8a7778_register_gpio(idx)                              \
+        platform_device_register_resndata(                      \
+                &platform_bus, "gpio_rcar", idx,                \
+                r8a7778_gpio##idx##_resources,                  \
+                ARRAY_SIZE(r8a7778_gpio##idx##_resources),      \
+                &r8a7778_gpio##idx##_platform_data,             \
+                sizeof(r8a7778_gpio##idx##_platform_data))
+void __init r8a7778_pinmux_init(void)
+{
+        platform_device_register_simple(
+                "pfc-r8a7778", -1,
+                pfc_resources,
+                ARRAY_SIZE(pfc_resources));
+        r8a7778_register_gpio(0);
+        r8a7778_register_gpio(1);
+        r8a7778_register_gpio(2);
+        r8a7778_register_gpio(3);
+        r8a7778_register_gpio(4);
+};
+/* SDHI */
+static struct resource sdhi_resources[] = {
+        /* SDHI0 */
+        DEFINE_RES_MEM(0xFFE4C000, 0x100),
+        DEFINE_RES_IRQ(gic_iid(0x77)),
+        /* SDHI1 */
+        DEFINE_RES_MEM(0xFFE4D000, 0x100),
+        DEFINE_RES_IRQ(gic_iid(0x78)),
+        /* SDHI2 */
+        DEFINE_RES_MEM(0xFFE4F000, 0x100),
+        DEFINE_RES_IRQ(gic_iid(0x76)),
+};
+void __init r8a7778_sdhi_init(int id,
+                              struct sh_mobile_sdhi_info *info)
+{
+        BUG_ON(id < 0 || id > 2);
+        platform_device_register_resndata(
+                &platform_bus, "sh_mobile_sdhi", id,
+                sdhi_resources + (2 * id), 2,
+                info, sizeof(*info));
+}
+/* I2C */
+static struct resource i2c_resources[] __initdata = {
+        /* I2C0 */
+        DEFINE_RES_MEM(0xffc70000, 0x1000),
+        DEFINE_RES_IRQ(gic_iid(0x63)),
+        /* I2C1 */
+        DEFINE_RES_MEM(0xffc71000, 0x1000),
+        DEFINE_RES_IRQ(gic_iid(0x6e)),
+        /* I2C2 */
+        DEFINE_RES_MEM(0xffc72000, 0x1000),
+        DEFINE_RES_IRQ(gic_iid(0x6c)),
+        /* I2C3 */
+        DEFINE_RES_MEM(0xffc73000, 0x1000),
+        DEFINE_RES_IRQ(gic_iid(0x6d)),
+};
+void __init r8a7778_add_i2c_device(int id)
+{
+        BUG_ON(id < 0 || id > 3);
+        platform_device_register_simple(
+                "i2c-rcar", id,
+                i2c_resources + (2 * id), 2);
+}
+/* HSPI */
+static struct resource hspi_resources[] __initdata = {
+        /* HSPI0 */
+        DEFINE_RES_MEM(0xfffc7000, 0x18),
+        DEFINE_RES_IRQ(gic_iid(0x5f)),
+        /* HSPI1 */
+        DEFINE_RES_MEM(0xfffc8000, 0x18),
+        DEFINE_RES_IRQ(gic_iid(0x74)),
+        /* HSPI2 */
+        DEFINE_RES_MEM(0xfffc6000, 0x18),
+        DEFINE_RES_IRQ(gic_iid(0x75)),
+};
+void __init r8a7778_add_hspi_device(int id)
+{
+        BUG_ON(id < 0 || id > 2);
+        platform_device_register_simple(
+                "sh-hspi", id,
+                hspi_resources + (2 * id), 2);
+}
+/* MMC */
+static struct resource mmc_resources[] __initdata = {
+        DEFINE_RES_MEM(0xffe4e000, 0x100),
+        DEFINE_RES_IRQ(gic_iid(0x5d)),
+};
+void __init r8a7778_add_mmc_device(struct sh_mmcif_plat_data *info)
+{
+        platform_device_register_resndata(
+                &platform_bus, "sh_mmcif", -1,
+                mmc_resources, ARRAY_SIZE(mmc_resources),
+                info, sizeof(*info));
+}
 void __init r8a7778_add_standard_devices(void)
 {
        int i;
@@ -118,12 +357,12 @@ void __init r8a7778_add_standard_devices(void)
        r8a7778_register_tmu(1);
 }
-void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata)
+void __init r8a7778_init_late(void)
 {
-        platform_device_register_resndata(&platform_bus, "sh_eth", -1,
+        phy = usb_get_phy(USB_PHY_TYPE_USB2);
-                                          ether_resources,
-                                          ARRAY_SIZE(ether_resources),
+        platform_device_register_full(&ehci_info);
-                                          pdata, sizeof(*pdata));
+        platform_device_register_full(&ohci_info);
 }
 static struct renesas_intc_irqpin_config irqpin_platform_data = {
@@ -239,6 +478,7 @@ DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
        .init_machine   = r8a7778_add_standard_devices_dt,
        .init_time      = shmobile_timer_init,
        .dt_compat      = r8a7778_compat_dt,
+        .init_late      = r8a7778_init_late,
 MACHINE_END
 #endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index b0b394842ea5..398687761f50 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -32,6 +32,11 @@
 #include <linux/sh_intc.h>
 #include <linux/sh_timer.h>
 #include <linux/dma-mapping.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/hcd.h>
+#include <linux/usb/ehci_pdriver.h>
+#include <linux/usb/ohci_pdriver.h>
+#include <linux/pm_runtime.h>
 #include <mach/hardware.h>
 #include <mach/irqs.h>
 #include <mach/r8a7779.h>
@@ -65,11 +70,7 @@ void __init r8a7779_map_io(void)
 }
 static struct resource r8a7779_pfc_resources[] = {
-        [0] = {
+        DEFINE_RES_MEM(0xfffc0000, 0x023c),
-                .start  = 0xfffc0000,
-                .end    = 0xfffc023b,
-                .flags  = IORESOURCE_MEM,
-        },
 };
 static struct platform_device r8a7779_pfc_device = {
@@ -81,15 +82,8 @@ static struct platform_device r8a7779_pfc_device = {
 #define R8A7779_GPIO(idx, npins) \
 static struct resource r8a7779_gpio##idx##_resources[] = {              \
-        [0] = {                                                         \
+        DEFINE_RES_MEM(0xffc40000 + (0x1000 * (idx)), 0x002c),          \
-                .start  = 0xffc40000 + 0x1000 * (idx),                  \
+        DEFINE_RES_IRQ(gic_iid(0xad + (idx))),                          \
-                .end    = 0xffc4002b + 0x1000 * (idx),                  \
-                .flags  = IORESOURCE_MEM,                               \
-        },                                                              \
-        [1] = {                                                         \
-                .start  = gic_iid(0xad + (idx)),                        \
-                .flags  = IORESOURCE_IRQ,                               \
-        }                                                               \
 };                                                                      \
                                                                        \
 static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = {    \
@@ -394,6 +388,165 @@ static struct platform_device sata_device = {
        },
 };
+/* USB PHY */
+static struct resource usb_phy_resources[] __initdata = {
+        [0] = {
+                .start          = 0xffe70800,
+                .end            = 0xffe70900 - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+/* USB */
+static struct usb_phy *phy;
+static int usb_power_on(struct platform_device *pdev)
+{
+        if (IS_ERR(phy))
+                return PTR_ERR(phy);
+        pm_runtime_enable(&pdev->dev);
+        pm_runtime_get_sync(&pdev->dev);
+        usb_phy_init(phy);
+        return 0;
+}
+static void usb_power_off(struct platform_device *pdev)
+{
+        if (IS_ERR(phy))
+                return;
+        usb_phy_shutdown(phy);
+        pm_runtime_put_sync(&pdev->dev);
+        pm_runtime_disable(&pdev->dev);
+}
+static int ehci_init_internal_buffer(struct usb_hcd *hcd)
+{
+        /*
+         * Below are recommended values from the datasheet;
+         * see [USB :: Setting of EHCI Internal Buffer].
+         */
+        /* EHCI IP internal buffer setting */
+        iowrite32(0x00ff0040, hcd->regs + 0x0094);
+        /* EHCI IP internal buffer enable */
+        iowrite32(0x00000001, hcd->regs + 0x009C);
+        return 0;
+}
+static struct usb_ehci_pdata ehcix_pdata = {
+        .power_on       = usb_power_on,
+        .power_off      = usb_power_off,
+        .power_suspend  = usb_power_off,
+        .pre_setup      = ehci_init_internal_buffer,
+};
+static struct resource ehci0_resources[] = {
+        [0] = {
+                .start  = 0xffe70000,
+                .end    = 0xffe70400 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_iid(0x4c),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device ehci0_device = {
+        .name   = "ehci-platform",
+        .id     = 0,
+        .dev    = {
+                .dma_mask               = &ehci0_device.dev.coherent_dma_mask,
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &ehcix_pdata,
+        },
+        .num_resources  = ARRAY_SIZE(ehci0_resources),
+        .resource       = ehci0_resources,
+};
+static struct resource ehci1_resources[] = {
+        [0] = {
+                .start  = 0xfff70000,
+                .end    = 0xfff70400 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_iid(0x4d),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device ehci1_device = {
+        .name   = "ehci-platform",
+        .id     = 1,
+        .dev    = {
+                .dma_mask               = &ehci1_device.dev.coherent_dma_mask,
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &ehcix_pdata,
+        },
+        .num_resources  = ARRAY_SIZE(ehci1_resources),
+        .resource       = ehci1_resources,
+};
+static struct usb_ohci_pdata ohcix_pdata = {
+        .power_on       = usb_power_on,
+        .power_off      = usb_power_off,
+        .power_suspend  = usb_power_off,
+};
+static struct resource ohci0_resources[] = {
+        [0] = {
+                .start  = 0xffe70400,
+                .end    = 0xffe70800 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_iid(0x4c),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device ohci0_device = {
+        .name   = "ohci-platform",
+        .id     = 0,
+        .dev    = {
+                .dma_mask               = &ohci0_device.dev.coherent_dma_mask,
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &ohcix_pdata,
+        },
+        .num_resources  = ARRAY_SIZE(ohci0_resources),
+        .resource       = ohci0_resources,
+};
+static struct resource ohci1_resources[] = {
+        [0] = {
+                .start  = 0xfff70400,
+                .end    = 0xfff70800 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_iid(0x4d),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device ohci1_device = {
+        .name   = "ohci-platform",
+        .id     = 1,
+        .dev    = {
+                .dma_mask               = &ohci1_device.dev.coherent_dma_mask,
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &ohcix_pdata,
+        },
+        .num_resources  = ARRAY_SIZE(ohci1_resources),
+        .resource       = ohci1_resources,
+};
 /* Ether */
 static struct resource ether_resources[] = {
        {
@@ -417,7 +570,7 @@ static struct platform_device *r8a7779_devices_dt[] __initdata = {
        &tmu01_device,
 };
-static struct platform_device *r8a7779_late_devices[] __initdata = {
+static struct platform_device *r8a7779_standard_devices[] __initdata = {
        &i2c0_device,
        &i2c1_device,
        &i2c2_device,
@@ -437,18 +590,26 @@ void __init r8a7779_add_standard_devices(void)
        platform_add_devices(r8a7779_devices_dt,
                            ARRAY_SIZE(r8a7779_devices_dt));
-        platform_add_devices(r8a7779_late_devices,
+        platform_add_devices(r8a7779_standard_devices,
-                            ARRAY_SIZE(r8a7779_late_devices));
+                            ARRAY_SIZE(r8a7779_standard_devices));
 }
 void __init r8a7779_add_ether_device(struct sh_eth_plat_data *pdata)
 {
-        platform_device_register_resndata(&platform_bus, "sh_eth", -1,
+        platform_device_register_resndata(&platform_bus, "r8a777x-ether", -1,
                                          ether_resources,
                                          ARRAY_SIZE(ether_resources),
                                          pdata, sizeof(*pdata));
 }
+void __init r8a7779_add_usb_phy_device(struct rcar_phy_platform_data *pdata)
+{
+        platform_device_register_resndata(&platform_bus, "rcar_usb_phy", -1,
+                                          usb_phy_resources,
+                                          ARRAY_SIZE(usb_phy_resources),
+                                          pdata, sizeof(*pdata));
+}
 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
 void __init __weak r8a7779_register_twd(void) { }
@@ -481,6 +642,23 @@ void __init r8a7779_add_early_devices(void)
         */
 }
+static struct platform_device *r8a7779_late_devices[] __initdata = {
+        &ehci0_device,
+        &ehci1_device,
+        &ohci0_device,
+        &ohci1_device,
+};
+void __init r8a7779_init_late(void)
+{
+        /* get USB PHY */
+        phy = usb_get_phy(USB_PHY_TYPE_USB2);
+        shmobile_init_late();
+        platform_add_devices(r8a7779_late_devices,
+                             ARRAY_SIZE(r8a7779_late_devices));
+}
 #ifdef CONFIG_USE_OF
 void __init r8a7779_init_delay(void)
 {
@@ -514,6 +692,7 @@ DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
        .init_irq       = r8a7779_init_irq_dt,
        .init_machine   = r8a7779_add_standard_devices_dt,
        .init_time      = shmobile_timer_init,
+        .init_late      = r8a7779_init_late,
        .dt_compat      = r8a7779_compat_dt,
 MACHINE_END
 #endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index 49de2d56f86d..28f94752b8ff 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -23,21 +23,55 @@
 #include <linux/kernel.h>
 #include <linux/of_platform.h>
 #include <linux/serial_sci.h>
+#include <linux/platform_data/gpio-rcar.h>
 #include <linux/platform_data/irq-renesas-irqc.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/r8a7790.h>
 #include <asm/mach/arch.h>
-static const struct resource pfc_resources[] = {
+static struct resource pfc_resources[] __initdata = {
        DEFINE_RES_MEM(0xe6060000, 0x250),
-        DEFINE_RES_MEM(0xe6050000, 0x5050),
 };
+#define R8A7790_GPIO(idx)                                               \
+static struct resource r8a7790_gpio##idx##_resources[] __initdata = {   \
+        DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50),              \
+        DEFINE_RES_IRQ(gic_spi(4 + (idx))),                             \
+};                                                                      \
+                                                                        \
+static struct gpio_rcar_config r8a7790_gpio##idx##_platform_data __initdata = { \
+        .gpio_base      = 32 * (idx),                                   \
+        .irq_base       = 0,                                            \
+        .number_of_pins = 32,                                           \
+        .pctl_name      = "pfc-r8a7790",                                \
+        .has_both_edge_trigger = 1,                                     \
+};                                                                      \
+R8A7790_GPIO(0);
+R8A7790_GPIO(1);
+R8A7790_GPIO(2);
+R8A7790_GPIO(3);
+R8A7790_GPIO(4);
+R8A7790_GPIO(5);
+#define r8a7790_register_gpio(idx)                                      \
+        platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \
+                r8a7790_gpio##idx##_resources,                          \
+                ARRAY_SIZE(r8a7790_gpio##idx##_resources),              \
+                &r8a7790_gpio##idx##_platform_data,                     \
+                sizeof(r8a7790_gpio##idx##_platform_data))
 void __init r8a7790_pinmux_init(void)
 {
        platform_device_register_simple("pfc-r8a7790", -1, pfc_resources,
                                        ARRAY_SIZE(pfc_resources));
+        r8a7790_register_gpio(0);
+        r8a7790_register_gpio(1);
+        r8a7790_register_gpio(2);
+        r8a7790_register_gpio(3);
+        r8a7790_register_gpio(4);
+        r8a7790_register_gpio(5);
 }
 #define SCIF_COMMON(scif_type, baseaddr, irq)                   \
@@ -64,12 +98,20 @@ void __init r8a7790_pinmux_init(void)
 [index] = {                                             \
        SCIF_COMMON(PORT_SCIF, baseaddr, irq),          \
        .scbrr_algo_id  = SCBRR_ALGO_2,                 \
-        .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,      \
+        .scscr = SCSCR_RE | SCSCR_TE,   \
+}
+#define HSCIF_DATA(index, baseaddr, irq)                \
+[index] = {                                             \
+        SCIF_COMMON(PORT_HSCIF, baseaddr, irq),         \
+        .scbrr_algo_id  = SCBRR_ALGO_6,                 \
+        .scscr = SCSCR_RE | SCSCR_TE,   \
 }
-enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1 };
+enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1,
+       HSCIF0, HSCIF1 };
-static const struct plat_sci_port scif[] = {
+static struct plat_sci_port scif[] __initdata = {
        SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
        SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
        SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
@@ -78,6 +120,8 @@ static const struct plat_sci_port scif[] = {
        SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */
        SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */
        SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */
+        HSCIF_DATA(HSCIF0, 0xe62c0000, gic_spi(154)), /* HSCIF0 */
+        HSCIF_DATA(HSCIF1, 0xe62c8000, gic_spi(155)), /* HSCIF1 */
 };
 static inline void r8a7790_register_scif(int idx)
@@ -86,11 +130,11 @@ static inline void r8a7790_register_scif(int idx)
                                      sizeof(struct plat_sci_port));
 }
-static struct renesas_irqc_config irqc0_data = {
+static struct renesas_irqc_config irqc0_data __initdata = {
        .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
 };
-static struct resource irqc0_resources[] = {
+static struct resource irqc0_resources[] __initdata = {
        DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
        DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
        DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
@@ -115,6 +159,8 @@ void __init r8a7790_add_standard_devices(void)
        r8a7790_register_scif(SCIFA2);
        r8a7790_register_scif(SCIF0);
        r8a7790_register_scif(SCIF1);
+        r8a7790_register_scif(HSCIF0);
+        r8a7790_register_scif(HSCIF1);
        r8a7790_register_irqc(0);
 }
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index 9696f3646864..96e7ca1e4e11 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -288,12 +288,7 @@ static struct sh_timer_config tmu00_platform_data = {
 };
 static struct resource tmu00_resources[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM_NAMED(0xfff60008, 0xc, "TMU00"),
-                .name   = "TMU00",
-                .start  = 0xfff60008,
-                .end    = 0xfff60013,
-                .flags  = IORESOURCE_MEM,
-        },
        [1] = {
                .start  = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */
                .flags  = IORESOURCE_IRQ,
@@ -318,12 +313,7 @@ static struct sh_timer_config tmu01_platform_data = {
 };
 static struct resource tmu01_resources[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM_NAMED(0xfff60014, 0xc, "TMU00"),
-                .name   = "TMU01",
-                .start  = 0xfff60014,
-                .end    = 0xfff6001f,
-                .flags  = IORESOURCE_MEM,
-        },
        [1] = {
                .start  = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */
                .flags  = IORESOURCE_IRQ,
@@ -341,12 +331,7 @@ static struct platform_device tmu01_device = {
 };
 static struct resource i2c0_resources[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM_NAMED(0xe6820000, 0x426, "IIC0"),
-                .name   = "IIC0",
-                .start  = 0xe6820000,
-                .end    = 0xe6820425 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
        [1] = {
                .start  = gic_spi(167),
                .end    = gic_spi(170),
@@ -355,12 +340,7 @@ static struct resource i2c0_resources[] = {
 };
 static struct resource i2c1_resources[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM_NAMED(0xe6822000, 0x426, "IIC1"),
-                .name   = "IIC1",
-                .start  = 0xe6822000,
-                .end    = 0xe6822425 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
        [1] = {
                .start  = gic_spi(51),
                .end    = gic_spi(54),
@@ -369,12 +349,7 @@ static struct resource i2c1_resources[] = {
 };
 static struct resource i2c2_resources[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM_NAMED(0xe6824000, 0x426, "IIC2"),
-                .name   = "IIC2",
-                .start  = 0xe6824000,
-                .end    = 0xe6824425 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
        [1] = {
                .start  = gic_spi(171),
                .end    = gic_spi(174),
@@ -383,12 +358,7 @@ static struct resource i2c2_resources[] = {
 };
 static struct resource i2c3_resources[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM_NAMED(0xe6826000, 0x426, "IIC3"),
-                .name   = "IIC3",
-                .start  = 0xe6826000,
-                .end    = 0xe6826425 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
        [1] = {
                .start  = gic_spi(183),
                .end    = gic_spi(186),
@@ -397,12 +367,7 @@ static struct resource i2c3_resources[] = {
 };
 static struct resource i2c4_resources[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM_NAMED(0xe6828000, 0x426, "IIC4"),
-                .name   = "IIC4",
-                .start  = 0xe6828000,
-                .end    = 0xe6828425 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
        [1] = {
                .start  = gic_spi(187),
                .end    = gic_spi(190),
@@ -623,12 +588,7 @@ static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
 };
 static struct resource sh73a0_dmae_resources[] = {
-        {
+        DEFINE_RES_MEM(0xfe000020, 0x89e0),
-                /* Registers including DMAOR and channels including DMARSx */
-                .start  = 0xfe000020,
-                .end    = 0xfe008a00 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
        {
                .name   = "error_irq",
                .start  = gic_spi(129),
@@ -727,18 +687,10 @@ static struct sh_dmae_pdata sh73a0_mpdma_platform_data = {
 /* Resource order important! */
 static struct resource sh73a0_mpdma_resources[] = {
-        {
+        /* Channel registers and DMAOR */
-                /* Channel registers and DMAOR */
+        DEFINE_RES_MEM(0xec618020, 0x270),
-                .start  = 0xec618020,
+        /* DMARSx */
-                .end    = 0xec61828f,
+        DEFINE_RES_MEM(0xec619000, 0xc),
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                /* DMARSx */
-                .start  = 0xec619000,
-                .end    = 0xec61900b,
-                .flags  = IORESOURCE_MEM,
-        },
        {
                .name   = "error_irq",
                .start  = gic_spi(181),
@@ -785,12 +737,7 @@ static struct platform_device pmu_device = {
 /* an IPMMU module for ICB */
 static struct resource ipmmu_resources[] = {
-        [0] = {
+        DEFINE_RES_MEM_NAMED(0xfe951000, 0x100, "IPMMU"),
-                .name   = "IPMMU",
-                .start  = 0xfe951000,
-                .end    = 0xfe9510ff,
-                .flags  = IORESOURCE_MEM,
-        },
 };
 static const char * const ipmmu_dev_names[] = {
@@ -982,11 +929,17 @@ void __init sh73a0_add_standard_devices(void)
                            ARRAY_SIZE(sh73a0_late_devices));
 }
+void __init sh73a0_init_delay(void)
+{
+        shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */
+}
 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
 void __init __weak sh73a0_register_twd(void) { }
 void __init sh73a0_earlytimer_init(void)
 {
+        sh73a0_init_delay();
        sh73a0_clock_init();
        shmobile_earlytimer_init();
        sh73a0_register_twd();
@@ -1005,17 +958,14 @@ void __init sh73a0_add_early_devices(void)
 #ifdef CONFIG_USE_OF
-void __init sh73a0_init_delay(void)
-{
-        shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */
-}
 static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = {
        {},
 };
 void __init sh73a0_add_standard_devices_dt(void)
 {
+        struct platform_device_info devinfo = { .name = "cpufreq-cpu0", .id = -1, };
        /* clocks are setup late during boot in the case of DT */
        sh73a0_clock_init();
@@ -1023,6 +973,9 @@ void __init sh73a0_add_standard_devices_dt(void)
                             ARRAY_SIZE(sh73a0_devices_dt));
        of_platform_populate(NULL, of_default_bus_match_table,
                             sh73a0_auxdata_lookup, NULL);
+        /* Instantiate cpufreq-cpu0 */
+        platform_device_register_full(&devinfo);
 }
 static const char *sh73a0_boards_compat_dt[] __initdata = {
diff --git a/arch/arm/mach-shmobile/sleep-sh7372.S b/arch/arm/mach-shmobile/sleep-sh7372.S
index a9df53b69ab8..53f4840e4949 100644
--- a/arch/arm/mach-shmobile/sleep-sh7372.S
+++ b/arch/arm/mach-shmobile/sleep-sh7372.S
@@ -40,7 +40,10 @@
        .global sh7372_resume_core_standby_sysc
 sh7372_resume_core_standby_sysc:
        ldr     pc, 1f
-1:      .long   cpu_resume - PAGE_OFFSET + PLAT_PHYS_OFFSET
+        .globl  sh7372_cpu_resume
+sh7372_cpu_resume:
+1:      .space  4
 #define SPDCR 0xe6180008
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
index e38691b4d0dd..22a05a869d25 100644
--- a/arch/arm/mach-shmobile/smp-emev2.c
+++ b/arch/arm/mach-shmobile/smp-emev2.c
@@ -30,7 +30,7 @@
 #define EMEV2_SCU_BASE 0x1e000000
-static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
        arch_send_wakeup_ipi_mask(cpumask_of(cpu_logical_map(cpu)));
        return 0;
@@ -40,8 +40,10 @@ static void __init emev2_smp_prepare_cpus(unsigned int max_cpus)
 {
        scu_enable(shmobile_scu_base);
-        /* Tell ROM loader about our vector (in headsmp-scu.S) */
+        /* Tell ROM loader about our vector (in headsmp-scu.S, headsmp.S) */
-        emev2_set_boot_vector(__pa(shmobile_secondary_vector_scu));
+        emev2_set_boot_vector(__pa(shmobile_boot_vector));
+        shmobile_boot_fn = virt_to_phys(shmobile_boot_scu);
+        shmobile_boot_arg = (unsigned long)shmobile_scu_base;
        /* enable cache coherency on booting CPU */
        scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
index a853bf182ed5..9bdf810f2a87 100644
--- a/arch/arm/mach-shmobile/smp-r8a7779.c
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -81,7 +81,7 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu)
        return ret ? ret : 1;
 }
-static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
        struct r8a7779_pm_ch *ch = NULL;
        int ret = -EIO;
@@ -101,8 +101,10 @@ static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus)
 {
        scu_enable(shmobile_scu_base);
-        /* Map the reset vector (in headsmp-scu.S) */
+        /* Map the reset vector (in headsmp-scu.S, headsmp.S) */
-        __raw_writel(__pa(shmobile_secondary_vector_scu), AVECR);
+        __raw_writel(__pa(shmobile_boot_vector), AVECR);
+        shmobile_boot_fn = virt_to_phys(shmobile_boot_scu);
+        shmobile_boot_arg = (unsigned long)shmobile_scu_base;
        /* enable cache coherency on booting CPU */
        scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index 496592b6c763..d5fc3ed4e315 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -48,7 +48,7 @@ void __init sh73a0_register_twd(void)
 }
 #endif
-static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
        cpu = cpu_logical_map(cpu);
@@ -64,9 +64,11 @@ static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
 {
        scu_enable(shmobile_scu_base);
-        /* Map the reset vector (in headsmp-scu.S) */
+        /* Map the reset vector (in headsmp-scu.S, headsmp.S) */
        __raw_writel(0, APARMBAREA);      /* 4k */
-        __raw_writel(__pa(shmobile_secondary_vector_scu), SBAR);
+        __raw_writel(__pa(shmobile_boot_vector), SBAR);
+        shmobile_boot_fn = virt_to_phys(shmobile_boot_scu);
+        shmobile_boot_arg = (unsigned long)shmobile_scu_base;
        /* enable cache coherency on booting CPU */
        scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 566e804d4036..dd86db467521 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -7,11 +7,11 @@ config ARCH_SOCFPGA
        select CLKDEV_LOOKUP
        select COMMON_CLK
        select CPU_V7
-        select DW_APB_TIMER
        select DW_APB_TIMER_OF
        select GENERIC_CLOCKEVENTS
        select GPIO_PL061 if GPIOLIB
        select HAVE_ARM_SCU
        select HAVE_SMP
+        select MFD_SYSCON
        select SPARSE_IRQ
        select USE_OF
diff --git a/arch/arm/mach-socfpga/headsmp.S b/arch/arm/mach-socfpga/headsmp.S
index 9004bfb1756e..95c115d8b5ee 100644
--- a/arch/arm/mach-socfpga/headsmp.S
+++ b/arch/arm/mach-socfpga/headsmp.S
@@ -10,7 +10,6 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
-        __CPUINIT
        .arch   armv7-a
 ENTRY(secondary_trampoline)
diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
index b51ce8c7929d..5356a72bc8ce 100644
--- a/arch/arm/mach-socfpga/platsmp.c
+++ b/arch/arm/mach-socfpga/platsmp.c
@@ -29,7 +29,7 @@
 #include "core.h"
-static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
        int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index 46a051359f02..bfce9641e32f 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -14,12 +14,12 @@
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
-#include <linux/dw_apb_timer.h>
 #include <linux/clk-provider.h>
 #include <linux/irqchip.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/reboot.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/arch.h>
@@ -90,13 +90,13 @@ static void __init socfpga_init_irq(void)
        socfpga_sysmgr_init();
 }
-static void socfpga_cyclone5_restart(char mode, const char *cmd)
+static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
 {
        u32 temp;
        temp = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
-        if (mode == 'h')
+        if (mode == REBOOT_HARD)
                temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
        else
                temp |= RSTMGR_CTRL_SWWARMRSTREQ;
@@ -120,7 +120,6 @@ DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
        .smp            = smp_ops(socfpga_smp_ops),
        .map_io         = socfpga_map_io,
        .init_irq       = socfpga_init_irq,
-        .init_time      = dw_apb_timer_init,
        .init_machine   = socfpga_cyclone5_init,
        .restart        = socfpga_cyclone5_restart,
        .dt_compat      = altera_dt_match,
diff --git a/arch/arm/mach-spear/generic.h b/arch/arm/mach-spear/generic.h
index a9fd45362fee..a99d90a4d09c 100644
--- a/arch/arm/mach-spear/generic.h
+++ b/arch/arm/mach-spear/generic.h
@@ -16,6 +16,8 @@
 #include <linux/dmaengine.h>
 #include <linux/amba/pl08x.h>
 #include <linux/init.h>
+#include <linux/reboot.h>
 #include <asm/mach/time.h>
 extern void spear13xx_timer_init(void);
@@ -32,10 +34,10 @@ void __init spear6xx_clk_init(void __iomem *misc_base);
 void __init spear13xx_map_io(void);
 void __init spear13xx_l2x0_init(void);
-void spear_restart(char, const char *);
+void spear_restart(enum reboot_mode, const char *);
 void spear13xx_secondary_startup(void);
-void __cpuinit spear13xx_cpu_die(unsigned int cpu);
+void spear13xx_cpu_die(unsigned int cpu);
 extern struct smp_operations spear13xx_smp_ops;
diff --git a/arch/arm/mach-spear/platsmp.c b/arch/arm/mach-spear/platsmp.c
index 9c4c722c954e..5c4a19887b2b 100644
--- a/arch/arm/mach-spear/platsmp.c
+++ b/arch/arm/mach-spear/platsmp.c
@@ -24,7 +24,7 @@ static DEFINE_SPINLOCK(boot_lock);
 static void __iomem *scu_base = IOMEM(VA_SCU_BASE);
-static void __cpuinit spear13xx_secondary_init(unsigned int cpu)
+static void spear13xx_secondary_init(unsigned int cpu)
 {
        /*
         * let the primary processor know we're out of the
@@ -40,7 +40,7 @@ static void __cpuinit spear13xx_secondary_init(unsigned int cpu)
        spin_unlock(&boot_lock);
 }
-static int __cpuinit spear13xx_boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int spear13xx_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
        unsigned long timeout;
diff --git a/arch/arm/mach-spear/restart.c b/arch/arm/mach-spear/restart.c
index 2b44500bb718..ce5e098c4888 100644
--- a/arch/arm/mach-spear/restart.c
+++ b/arch/arm/mach-spear/restart.c
@@ -12,14 +12,15 @@
 */
 #include <linux/io.h>
 #include <linux/amba/sp810.h>
+#include <linux/reboot.h>
 #include <asm/system_misc.h>
 #include <mach/spear.h>
 #include "generic.h"
 #define SPEAR13XX_SYS_SW_RES                    (VA_MISC_BASE + 0x204)
-void spear_restart(char mode, const char *cmd)
+void spear_restart(enum reboot_mode mode, const char *cmd)
 {
-        if (mode == 's') {
+        if (mode == REBOOT_SOFT) {
                /* software reset, Jump into ROM at address 0 */
                soft_restart(0);
        } else {
diff --git a/arch/arm/mach-spear/spear1310.c b/arch/arm/mach-spear/spear1310.c
index 9eaac2c881ea..7ad003001ab7 100644
--- a/arch/arm/mach-spear/spear1310.c
+++ b/arch/arm/mach-spear/spear1310.c
@@ -14,7 +14,6 @@
 #define pr_fmt(fmt) "SPEAr1310: " fmt
 #include <linux/amba/pl022.h>
-#include <linux/irqchip.h>
 #include <linux/of_platform.h>
 #include <linux/pata_arasan_cf_data.h>
 #include <asm/mach/arch.h>
@@ -60,7 +59,6 @@ static void __init spear1310_map_io(void)
 DT_MACHINE_START(SPEAR1310_DT, "ST SPEAr1310 SoC with Flattened Device Tree")
        .smp            =       smp_ops(spear13xx_smp_ops),
        .map_io         =       spear1310_map_io,
-        .init_irq       =       irqchip_init,
        .init_time      =       spear13xx_timer_init,
        .init_machine   =       spear1310_dt_init,
        .restart        =       spear_restart,
diff --git a/arch/arm/mach-spear/spear1340.c b/arch/arm/mach-spear/spear1340.c
index a04a7fe76f71..3fb683424729 100644
--- a/arch/arm/mach-spear/spear1340.c
+++ b/arch/arm/mach-spear/spear1340.c
@@ -17,7 +17,6 @@
 #include <linux/amba/serial.h>
 #include <linux/delay.h>
 #include <linux/of_platform.h>
-#include <linux/irqchip.h>
 #include <asm/mach/arch.h>
 #include "generic.h"
 #include <mach/spear.h>
@@ -155,7 +154,6 @@ static const char * const spear1340_dt_board_compat[] = {
 DT_MACHINE_START(SPEAR1340_DT, "ST SPEAr1340 SoC with Flattened Device Tree")
        .smp            =       smp_ops(spear13xx_smp_ops),
        .map_io         =       spear13xx_map_io,
-        .init_irq       =       irqchip_init,
        .init_time      =       spear13xx_timer_init,
        .init_machine   =       spear1340_dt_init,
        .restart        =       spear_restart,
diff --git a/arch/arm/mach-spear/spear300.c b/arch/arm/mach-spear/spear300.c
index bac56e845f7a..b52e48f342f4 100644
--- a/arch/arm/mach-spear/spear300.c
+++ b/arch/arm/mach-spear/spear300.c
@@ -14,7 +14,6 @@
 #define pr_fmt(fmt) "SPEAr300: " fmt
 #include <linux/amba/pl08x.h>
-#include <linux/irqchip.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
 #include "generic.h"
@@ -212,7 +211,6 @@ static void __init spear300_map_io(void)
 DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree")
        .map_io         =       spear300_map_io,
-        .init_irq       =       irqchip_init,
        .init_time      =       spear3xx_timer_init,
        .init_machine   =       spear300_dt_init,
        .restart        =       spear_restart,
diff --git a/arch/arm/mach-spear/spear310.c b/arch/arm/mach-spear/spear310.c
index 6ffbc63d516d..ed2029db391f 100644
--- a/arch/arm/mach-spear/spear310.c
+++ b/arch/arm/mach-spear/spear310.c
@@ -15,7 +15,6 @@
 #include <linux/amba/pl08x.h>
 #include <linux/amba/serial.h>
-#include <linux/irqchip.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
 #include "generic.h"
@@ -254,7 +253,6 @@ static void __init spear310_map_io(void)
 DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree")
        .map_io         =       spear310_map_io,
-        .init_irq       =       irqchip_init,
        .init_time      =       spear3xx_timer_init,
        .init_machine   =       spear310_dt_init,
        .restart        =       spear_restart,
diff --git a/arch/arm/mach-spear/spear320.c b/arch/arm/mach-spear/spear320.c
index 6eb3eec65f96..bf634b32a930 100644
--- a/arch/arm/mach-spear/spear320.c
+++ b/arch/arm/mach-spear/spear320.c
@@ -16,7 +16,6 @@
 #include <linux/amba/pl022.h>
 #include <linux/amba/pl08x.h>
 #include <linux/amba/serial.h>
-#include <linux/irqchip.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -269,7 +268,6 @@ static void __init spear320_map_io(void)
 DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree")
        .map_io         =       spear320_map_io,
-        .init_irq       =       irqchip_init,
        .init_time      =       spear3xx_timer_init,
        .init_machine   =       spear320_dt_init,
        .restart        =       spear_restart,
diff --git a/arch/arm/mach-spear/spear3xx.c b/arch/arm/mach-spear/spear3xx.c
index 0227c97797cd..bf3b1fd8cb23 100644
--- a/arch/arm/mach-spear/spear3xx.c
+++ b/arch/arm/mach-spear/spear3xx.c
@@ -56,8 +56,8 @@ struct pl08x_platform_data pl080_plat_data = {
        },
        .lli_buses = PL08X_AHB1,
        .mem_buses = PL08X_AHB1,
-        .get_signal = pl080_get_signal,
+        .get_xfer_signal = pl080_get_signal,
-        .put_signal = pl080_put_signal,
+        .put_xfer_signal = pl080_put_signal,
 };
 /*
diff --git a/arch/arm/mach-spear/spear6xx.c b/arch/arm/mach-spear/spear6xx.c
index ec8eefbbdfad..da26fa5b68d7 100644
--- a/arch/arm/mach-spear/spear6xx.c
+++ b/arch/arm/mach-spear/spear6xx.c
@@ -16,7 +16,6 @@
 #include <linux/amba/pl08x.h>
 #include <linux/clk.h>
 #include <linux/err.h>
-#include <linux/irqchip.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_platform.h>
@@ -335,8 +334,8 @@ static struct pl08x_platform_data spear6xx_pl080_plat_data = {
        },
        .lli_buses = PL08X_AHB1,
        .mem_buses = PL08X_AHB1,
-        .get_signal = pl080_get_signal,
+        .get_xfer_signal = pl080_get_signal,
-        .put_signal = pl080_put_signal,
+        .put_xfer_signal = pl080_put_signal,
        .slave_channels = spear600_dma_info,
        .num_slave_channels = ARRAY_SIZE(spear600_dma_info),
 };
@@ -423,7 +422,6 @@ static const char *spear600_dt_board_compat[] = {
 DT_MACHINE_START(SPEAR600_DT, "ST SPEAr600 (Flattened Device Tree)")
        .map_io         =       spear6xx_map_io,
-        .init_irq       =       irqchip_init,
        .init_time      =       spear6xx_timer_init,
        .init_machine   =       spear600_dt_init,
        .restart        =       spear_restart,
diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig
new file mode 100644
index 000000000000..835833e3c4f8
--- /dev/null
+++ b/arch/arm/mach-sti/Kconfig
@@ -0,0 +1,46 @@
+menuconfig ARCH_STI
+        bool "STMicroelectronics Consumer Electronics SOCs with Device Trees" if ARCH_MULTI_V7
+        select GENERIC_CLOCKEVENTS
+        select CLKDEV_LOOKUP
+        select ARM_GIC
+        select ARM_GLOBAL_TIMER
+        select PINCTRL
+        select PINCTRL_ST
+        select MFD_SYSCON
+        select MIGHT_HAVE_CACHE_L2X0
+        select HAVE_SMP
+        select HAVE_ARM_SCU if SMP
+        select ARCH_REQUIRE_GPIOLIB
+        select ARM_ERRATA_754322
+        select ARM_ERRATA_764369
+        select ARM_ERRATA_775420
+        select PL310_ERRATA_753970 if CACHE_PL310
+        select PL310_ERRATA_769419 if CACHE_PL310
+        help
+          Include support for STiH41x SOCs like STiH415/416 using the device tree
+          for discovery
+          More information at Documentation/arm/STiH41x and
+          at Documentation/devicetree
+if ARCH_STI
+config SOC_STIH415
+        bool "STiH415 STMicroelectronics Consumer Electronics family"
+        default y
+        help
+          This enables support for STMicroelectronics Digital Consumer
+          Electronics family StiH415 parts, primarily targetted at set-top-box
+          and other digital audio/video applications using Flattned Device
+          Trees.
+config SOC_STIH416
+        bool "STiH416 STMicroelectronics Consumer Electronics family"
+        default y
+        help
+          This enables support for STMicroelectronics Digital Consumer
+          Electronics family StiH416 parts, primarily targetted at set-top-box
+          and other digital audio/video applications using Flattened Device
+          Trees.
+endif
diff --git a/arch/arm/mach-sti/Makefile b/arch/arm/mach-sti/Makefile
new file mode 100644
index 000000000000..acb330916333
--- /dev/null
+++ b/arch/arm/mach-sti/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
+obj-$(CONFIG_ARCH_STI)          += board-dt.o
diff --git a/arch/arm/mach-sti/board-dt.c b/arch/arm/mach-sti/board-dt.c
new file mode 100644
index 000000000000..8fe6f0c46480
--- /dev/null
+++ b/arch/arm/mach-sti/board-dt.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ * Author(s): Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/clk-provider.h>
+#include <linux/clocksource.h>
+#include <linux/irq.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/mach/arch.h>
+#include "smp.h"
+void __init stih41x_l2x0_init(void)
+{
+        u32 way_size = 0x4;
+        u32 aux_ctrl;
+        /* may be this can be encoded in macros like BIT*() */
+        aux_ctrl = (0x1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
+                (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
+                (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
+                (way_size << L2X0_AUX_CTRL_WAY_SIZE_SHIFT);
+        l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
+}
+static void __init stih41x_timer_init(void)
+{
+        of_clk_init(NULL);
+        clocksource_of_init();
+        stih41x_l2x0_init();
+}
+static const char *stih41x_dt_match[] __initdata = {
+        "st,stih415",
+        "st,stih416",
+        NULL
+};
+DT_MACHINE_START(STM, "STiH415/416 SoC with Flattened Device Tree")
+        .init_time      = stih41x_timer_init,
+        .smp            = smp_ops(sti_smp_ops),
+        .dt_compat      = stih41x_dt_match,
+MACHINE_END
diff --git a/arch/arm/mach-sti/headsmp.S b/arch/arm/mach-sti/headsmp.S
new file mode 100644
index 000000000000..4c09bae86edf
--- /dev/null
+++ b/arch/arm/mach-sti/headsmp.S
@@ -0,0 +1,42 @@
+/*
+ *  arch/arm/mach-sti/headsmp.S
+ *
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ *              http://www.st.com
+ *
+ * Cloned from linux/arch/arm/mach-vexpress/headsmp.S
+ *
+ *  Copyright (c) 2003 ARM Limited
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+/*
+ * ST specific entry point for secondary CPUs.  This provides
+ * a "holding pen" into which all secondary cores are held until we're
+ * ready for them to initialise.
+ */
+ENTRY(sti_secondary_startup)
+        mrc     p15, 0, r0, c0, c0, 5
+        and     r0, r0, #15
+        adr     r4, 1f
+        ldmia   r4, {r5, r6}
+        sub     r4, r4, r5
+        add     r6, r6, r4
+pen:    ldr     r7, [r6]
+        cmp     r7, r0
+        bne     pen
+        /*
+         * we've been released from the holding pen: secondary_stack
+         * should now contain the SVC stack for this core
+         */
+        b       secondary_startup
+1:      .long   .
+        .long   pen_release
diff --git a/arch/arm/mach-sti/platsmp.c b/arch/arm/mach-sti/platsmp.c
new file mode 100644
index 000000000000..dce50d983a8e
--- /dev/null
+++ b/arch/arm/mach-sti/platsmp.c
@@ -0,0 +1,117 @@
+/*
+ *  arch/arm/mach-sti/platsmp.c
+ *
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ *              http://www.st.com
+ *
+ * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
+ *
+ *  Copyright (C) 2002 ARM Ltd.
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <asm/cacheflush.h>
+#include <asm/smp_plat.h>
+#include <asm/smp_scu.h>
+#include "smp.h"
+static void write_pen_release(int val)
+{
+        pen_release = val;
+        smp_wmb();
+        __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
+        outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
+}
+static DEFINE_SPINLOCK(boot_lock);
+void sti_secondary_init(unsigned int cpu)
+{
+        trace_hardirqs_off();
+        /*
+         * let the primary processor know we're out of the
+         * pen, then head off into the C entry point
+         */
+        write_pen_release(-1);
+        /*
+         * Synchronise with the boot thread.
+         */
+        spin_lock(&boot_lock);
+        spin_unlock(&boot_lock);
+}
+int sti_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        unsigned long timeout;
+        /*
+         * set synchronisation state between this boot processor
+         * and the secondary one
+         */
+        spin_lock(&boot_lock);
+        /*
+         * The secondary processor is waiting to be released from
+         * the holding pen - release it, then wait for it to flag
+         * that it has been released by resetting pen_release.
+         *
+         * Note that "pen_release" is the hardware CPU ID, whereas
+         * "cpu" is Linux's internal ID.
+         */
+        write_pen_release(cpu_logical_map(cpu));
+        /*
+         * Send the secondary CPU a soft interrupt, thereby causing
+         * it to jump to the secondary entrypoint.
+         */
+        arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+        timeout = jiffies + (1 * HZ);
+        while (time_before(jiffies, timeout)) {
+                smp_rmb();
+                if (pen_release == -1)
+                        break;
+                udelay(10);
+        }
+        /*
+         * now the secondary core is starting up let it run its
+         * calibrations, then wait for it to finish
+         */
+        spin_unlock(&boot_lock);
+        return pen_release != -1 ? -ENOSYS : 0;
+}
+void __init sti_smp_prepare_cpus(unsigned int max_cpus)
+{
+        void __iomem *scu_base = NULL;
+        struct device_node *np = of_find_compatible_node(
+                                        NULL, NULL, "arm,cortex-a9-scu");
+        if (np) {
+                scu_base = of_iomap(np, 0);
+                scu_enable(scu_base);
+                of_node_put(np);
+        }
+}
+struct smp_operations __initdata sti_smp_ops = {
+        .smp_prepare_cpus       = sti_smp_prepare_cpus,
+        .smp_secondary_init     = sti_secondary_init,
+        .smp_boot_secondary     = sti_boot_secondary,
+};
diff --git a/arch/arm/mach-sti/smp.h b/arch/arm/mach-sti/smp.h
new file mode 100644
index 000000000000..1871b72b1a7e
--- /dev/null
+++ b/arch/arm/mach-sti/smp.h
@@ -0,0 +1,17 @@
+/*
+ *  arch/arm/mach-sti/smp.h
+ *
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ *              http://www.st.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __MACH_STI_SMP_H
+#define __MACH_STI_SMP_H
+extern struct smp_operations    sti_smp_ops;
+#endif
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 706ce35396b8..38a3c55527c8 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -14,11 +14,11 @@
 #include <linux/delay.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/irqchip.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/io.h>
+#include <linux/reboot.h>
 #include <linux/clk/sunxi.h>
@@ -26,8 +26,6 @@
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
-#include "sunxi.h"
 #define SUN4I_WATCHDOG_CTRL_REG         0x00
 #define SUN4I_WATCHDOG_CTRL_RESTART             (1 << 0)
 #define SUN4I_WATCHDOG_MODE_REG         0x04
@@ -36,7 +34,7 @@
 static void __iomem *wdt_base;
-static void sun4i_restart(char mode, const char *cmd)
+static void sun4i_restart(enum reboot_mode mode, const char *cmd)
 {
        if (!wdt_base)
                return;
@@ -81,20 +79,6 @@ static void sunxi_setup_restart(void)
        arm_pm_restart = of_id->data;
 }
-static struct map_desc sunxi_io_desc[] __initdata = {
-        {
-                .virtual        = (unsigned long) SUNXI_REGS_VIRT_BASE,
-                .pfn            = __phys_to_pfn(SUNXI_REGS_PHYS_BASE),
-                .length         = SUNXI_REGS_SIZE,
-                .type           = MT_DEVICE,
-        },
-};
-void __init sunxi_map_io(void)
-{
-        iotable_init(sunxi_io_desc, ARRAY_SIZE(sunxi_io_desc));
-}
 static void __init sunxi_timer_init(void)
 {
        sunxi_init_clocks();
@@ -110,14 +94,13 @@ static void __init sunxi_dt_init(void)
 static const char * const sunxi_board_dt_compat[] = {
        "allwinner,sun4i-a10",
+        "allwinner,sun5i-a10s",
        "allwinner,sun5i-a13",
        NULL,
 };
 DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
        .init_machine   = sunxi_dt_init,
-        .map_io         = sunxi_map_io,
-        .init_irq       = irqchip_init,
        .init_time      = sunxi_timer_init,
        .dt_compat      = sunxi_board_dt_compat,
 MACHINE_END
diff --git a/arch/arm/mach-sunxi/sunxi.h b/arch/arm/mach-sunxi/sunxi.h
deleted file mode 100644
index 33b58712adea..000000000000
--- a/arch/arm/mach-sunxi/sunxi.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * Generic definitions for Allwinner SunXi SoCs
- *
- * Copyright (C) 2012 Maxime Ripard
- *
- * Maxime Ripard <maxime.ripard@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __MACH_SUNXI_H
-#define __MACH_SUNXI_H
-#define SUNXI_REGS_PHYS_BASE    0x01c00000
-#define SUNXI_REGS_VIRT_BASE    IOMEM(0xf1c00000)
-#define SUNXI_REGS_SIZE         (SZ_2M + SZ_1M)
-#endif /* __MACH_SUNXI_H */
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 84d72fc36dfe..ef3a8da49b2d 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -28,7 +28,6 @@ config ARCH_TEGRA_2x_SOC
        select ARM_ERRATA_754327 if SMP
        select ARM_ERRATA_764369 if SMP
        select ARM_GIC
-        select CPU_FREQ_TABLE if CPU_FREQ
        select CPU_V7
        select PINCTRL
        select PINCTRL_TEGRA20
@@ -46,7 +45,6 @@ config ARCH_TEGRA_3x_SOC
        select ARM_ERRATA_754322
        select ARM_ERRATA_764369 if SMP
        select ARM_GIC
-        select CPU_FREQ_TABLE if CPU_FREQ
        select CPU_V7
        select PINCTRL
        select PINCTRL_TEGRA30
@@ -60,10 +58,9 @@ config ARCH_TEGRA_3x_SOC
 config ARCH_TEGRA_114_SOC
        bool "Enable support for Tegra114 family"
-        select ARM_ARCH_TIMER
+        select HAVE_ARM_ARCH_TIMER
        select ARM_GIC
        select ARM_L1_CACHE_SHIFT_6
-        select CPU_FREQ_TABLE if CPU_FREQ
        select CPU_V7
        select PINCTRL
        select PINCTRL_TEGRA114
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index d011f0ad49c4..98b184efc110 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
 obj-$(CONFIG_TEGRA_PCI)                 += pcie.o
 obj-$(CONFIG_ARCH_TEGRA_114_SOC)        += tegra114_speedo.o
+obj-$(CONFIG_ARCH_TEGRA_114_SOC)        += sleep-tegra30.o
 ifeq ($(CONFIG_CPU_IDLE),y)
 obj-$(CONFIG_ARCH_TEGRA_114_SOC)        += cpuidle-tegra114.o
 endif
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
index 1787327fae3a..9a6659fe2dc2 100644
--- a/arch/arm/mach-tegra/board.h
+++ b/arch/arm/mach-tegra/board.h
@@ -23,8 +23,9 @@
 #define __MACH_TEGRA_BOARD_H
 #include <linux/types.h>
+#include <linux/reboot.h>
-void tegra_assert_system_reset(char mode, const char *cmd);
+void tegra_assert_system_reset(enum reboot_mode mode, const char *cmd);
 void __init tegra_init_early(void);
 void __init tegra_map_common_io(void);
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 9f852c6fe5b9..94a119a35af8 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -22,13 +22,15 @@
 #include <linux/io.h>
 #include <linux/clk.h>
 #include <linux/delay.h>
+#include <linux/reboot.h>
 #include <linux/irqchip.h>
-#include <linux/clk/tegra.h>
+#include <linux/clk-provider.h>
 #include <asm/hardware/cache-l2x0.h>
 #include "board.h"
 #include "common.h"
+#include "cpuidle.h"
 #include "fuse.h"
 #include "iomap.h"
 #include "irq.h"
@@ -59,7 +61,7 @@ u32 tegra_uart_config[4] = {
 #ifdef CONFIG_OF
 void __init tegra_dt_init_irq(void)
 {
-        tegra_clocks_init();
+        of_clk_init(NULL);
        tegra_pmc_init();
        tegra_init_irq();
        irqchip_init();
@@ -67,7 +69,7 @@ void __init tegra_dt_init_irq(void)
 }
 #endif
-void tegra_assert_system_reset(char mode, const char *cmd)
+void tegra_assert_system_reset(enum reboot_mode mode, const char *cmd)
 {
        void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
        u32 reg;
@@ -108,5 +110,6 @@ void __init tegra_init_early(void)
 void __init tegra_init_late(void)
 {
        tegra_init_suspend();
+        tegra_cpuidle_init();
        tegra_powergate_debugfs_init();
 }
diff --git a/arch/arm/mach-tegra/common.h b/arch/arm/mach-tegra/common.h
index 5900cc44f780..32f8eb3fe344 100644
--- a/arch/arm/mach-tegra/common.h
+++ b/arch/arm/mach-tegra/common.h
@@ -2,3 +2,4 @@ extern struct smp_operations tegra_smp_ops;
 extern int tegra_cpu_kill(unsigned int cpu);
 extern void tegra_cpu_die(unsigned int cpu);
+extern int tegra_cpu_disable(unsigned int cpu);
diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
index 0cdba8de8c77..706aa4215c36 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra20.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra20.c
@@ -177,7 +177,6 @@ static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
                                    struct cpuidle_driver *drv,
                                    int index)
 {
-        u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;
        bool entered_lp2 = false;
        if (tegra_pending_sgi())
@@ -193,16 +192,16 @@ static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
        local_fiq_disable();
-        tegra_set_cpu_in_lp2(cpu);
+        tegra_set_cpu_in_lp2();
        cpu_pm_enter();
-        if (cpu == 0)
+        if (dev->cpu == 0)
                entered_lp2 = tegra20_cpu_cluster_power_down(dev, drv, index);
        else
                entered_lp2 = tegra20_idle_enter_lp2_cpu_1(dev, drv, index);
        cpu_pm_exit();
-        tegra_clear_cpu_in_lp2(cpu);
+        tegra_clear_cpu_in_lp2();
        local_fiq_enable();
@@ -214,8 +213,5 @@ static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
 int __init tegra20_cpuidle_init(void)
 {
-#ifdef CONFIG_PM_SLEEP
-        tegra_tear_down_cpu = tegra20_tear_down_cpu;
-#endif
        return cpuidle_register(&tegra_idle_driver, cpu_possible_mask);
 }
diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c
index 3cf9aca5f3ea..ed2a2a7bae4d 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra30.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra30.c
@@ -114,16 +114,15 @@ static int tegra30_idle_lp2(struct cpuidle_device *dev,
                            struct cpuidle_driver *drv,
                            int index)
 {
-        u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;
        bool entered_lp2 = false;
        bool last_cpu;
        local_fiq_disable();
-        last_cpu = tegra_set_cpu_in_lp2(cpu);
+        last_cpu = tegra_set_cpu_in_lp2();
        cpu_pm_enter();
-        if (cpu == 0) {
+        if (dev->cpu == 0) {
                if (last_cpu)
                        entered_lp2 = tegra30_cpu_cluster_power_down(dev, drv,
                                                                     index);
@@ -134,7 +133,7 @@ static int tegra30_idle_lp2(struct cpuidle_device *dev,
        }
        cpu_pm_exit();
-        tegra_clear_cpu_in_lp2(cpu);
+        tegra_clear_cpu_in_lp2();
        local_fiq_enable();
@@ -146,8 +145,5 @@ static int tegra30_idle_lp2(struct cpuidle_device *dev,
 int __init tegra30_cpuidle_init(void)
 {
-#ifdef CONFIG_PM_SLEEP
-        tegra_tear_down_cpu = tegra30_tear_down_cpu;
-#endif
        return cpuidle_register(&tegra_idle_driver, NULL);
 }
diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c
index 4b744c4661e2..e85973cef037 100644
--- a/arch/arm/mach-tegra/cpuidle.c
+++ b/arch/arm/mach-tegra/cpuidle.c
@@ -27,25 +27,20 @@
 #include "fuse.h"
 #include "cpuidle.h"
-static int __init tegra_cpuidle_init(void)
+void __init tegra_cpuidle_init(void)
 {
-        int ret;
        switch (tegra_chip_id) {
        case TEGRA20:
-                ret = tegra20_cpuidle_init();
+                if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
+                        tegra20_cpuidle_init();
                break;
        case TEGRA30:
-                ret = tegra30_cpuidle_init();
+                if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC))
+                        tegra30_cpuidle_init();
                break;
        case TEGRA114:
-                ret = tegra114_cpuidle_init();
+                if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
-                break;
+                        tegra114_cpuidle_init();
-        default:
-                ret = -ENODEV;
                break;
        }
-        return ret;
 }
-device_initcall(tegra_cpuidle_init);
diff --git a/arch/arm/mach-tegra/cpuidle.h b/arch/arm/mach-tegra/cpuidle.h
index d733f75d0208..9ec2c1ab0fa4 100644
--- a/arch/arm/mach-tegra/cpuidle.h
+++ b/arch/arm/mach-tegra/cpuidle.h
@@ -17,22 +17,13 @@
 #ifndef __MACH_TEGRA_CPUIDLE_H
 #define __MACH_TEGRA_CPUIDLE_H
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+#ifdef CONFIG_CPU_IDLE
 int tegra20_cpuidle_init(void);
-#else
-static inline int tegra20_cpuidle_init(void) { return -ENODEV; }
-#endif
-#ifdef CONFIG_ARCH_TEGRA_3x_SOC
 int tegra30_cpuidle_init(void);
-#else
-static inline int tegra30_cpuidle_init(void) { return -ENODEV; }
-#endif
-#ifdef CONFIG_ARCH_TEGRA_114_SOC
 int tegra114_cpuidle_init(void);
+void tegra_cpuidle_init(void);
 #else
-static inline int tegra114_cpuidle_init(void) { return -ENODEV; }
+static inline void tegra_cpuidle_init(void) {}
 #endif
 #endif
diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h
index 67eab56699bd..7a29bae799a7 100644
--- a/arch/arm/mach-tegra/flowctrl.h
+++ b/arch/arm/mach-tegra/flowctrl.h
@@ -25,6 +25,7 @@
 #define FLOW_CTRL_WAITEVENT             (2 << 29)
 #define FLOW_CTRL_WAIT_FOR_INTERRUPT    (4 << 29)
 #define FLOW_CTRL_JTAG_RESUME           (1 << 28)
+#define FLOW_CTRL_SCLK_RESUME           (1 << 27)
 #define FLOW_CTRL_HALT_CPU_IRQ          (1 << 10)
 #define FLOW_CTRL_HALT_CPU_FIQ          (1 << 8)
 #define FLOW_CTRL_CPU0_CSR              0x8
diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h
index aacc00d05980..def79683bef6 100644
--- a/arch/arm/mach-tegra/fuse.h
+++ b/arch/arm/mach-tegra/fuse.h
@@ -19,16 +19,6 @@
 #ifndef __MACH_TEGRA_FUSE_H
 #define __MACH_TEGRA_FUSE_H
-enum tegra_revision {
-        TEGRA_REVISION_UNKNOWN = 0,
-        TEGRA_REVISION_A01,
-        TEGRA_REVISION_A02,
-        TEGRA_REVISION_A03,
-        TEGRA_REVISION_A03p,
-        TEGRA_REVISION_A04,
-        TEGRA_REVISION_MAX,
-};
 #define SKU_ID_T20      8
 #define SKU_ID_T25SE    20
 #define SKU_ID_AP25     23
@@ -40,6 +30,17 @@ enum tegra_revision {
 #define TEGRA30         0x30
 #define TEGRA114        0x35
+#ifndef __ASSEMBLY__
+enum tegra_revision {
+        TEGRA_REVISION_UNKNOWN = 0,
+        TEGRA_REVISION_A01,
+        TEGRA_REVISION_A02,
+        TEGRA_REVISION_A03,
+        TEGRA_REVISION_A03p,
+        TEGRA_REVISION_A04,
+        TEGRA_REVISION_MAX,
+};
 extern int tegra_sku_id;
 extern int tegra_cpu_process_id;
 extern int tegra_core_process_id;
@@ -72,5 +73,6 @@ void tegra114_init_speedo_data(void);
 #else
 static inline void tegra114_init_speedo_data(void) {}
 #endif
+#endif /* __ASSEMBLY__ */
 #endif
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
index 184914a68d73..a52c10e0a857 100644
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -46,6 +46,17 @@ void __ref tegra_cpu_die(unsigned int cpu)
        BUG();
 }
+int tegra_cpu_disable(unsigned int cpu)
+{
+        switch (tegra_chip_id) {
+        case TEGRA20:
+        case TEGRA30:
+                return cpu == 0 ? -EPERM : 0;
+        default:
+                return 0;
+        }
+}
 void __init tegra_hotplug_init(void)
 {
        if (!IS_ENABLED(CONFIG_HOTPLUG_CPU))
@@ -55,4 +66,6 @@ void __init tegra_hotplug_init(void)
                tegra_hotplug_shutdown = tegra20_hotplug_shutdown;
        if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_chip_id == TEGRA30)
                tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
+        if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_chip_id == TEGRA114)
+                tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
 }
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index fad4226ef710..97b33a2a2d75 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -35,7 +35,7 @@
 static cpumask_t tegra_cpu_init_mask;
-static void __cpuinit tegra_secondary_init(unsigned int cpu)
+static void tegra_secondary_init(unsigned int cpu)
 {
        cpumask_set_cpu(cpu, &tegra_cpu_init_mask);
 }
@@ -140,11 +140,34 @@ remove_clamps:
 static int tegra114_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
+        int ret = 0;
        cpu = cpu_logical_map(cpu);
-        return tegra_pmc_cpu_power_on(cpu);
+        if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) {
+                /*
+                 * Warm boot flow
+                 * The flow controller in charge of the power state and
+                 * control for each CPU.
+                 */
+                /* set SCLK as event trigger for flow controller */
+                flowctrl_write_cpu_csr(cpu, 1);
+                flowctrl_write_cpu_halt(cpu,
+                                FLOW_CTRL_WAITEVENT | FLOW_CTRL_SCLK_RESUME);
+        } else {
+                /*
+                 * Cold boot flow
+                 * The CPU is powered up by toggling PMC directly. It will
+                 * also initial power state in flow controller. After that,
+                 * the CPU's power state is maintained by flow controller.
+                 */
+                ret = tegra_pmc_cpu_power_on(cpu);
+        }
+        return ret;
 }
-static int __cpuinit tegra_boot_secondary(unsigned int cpu,
+static int tegra_boot_secondary(unsigned int cpu,
                                          struct task_struct *idle)
 {
        if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && tegra_chip_id == TEGRA20)
@@ -173,5 +196,6 @@ struct smp_operations tegra_smp_ops __initdata = {
 #ifdef CONFIG_HOTPLUG_CPU
        .cpu_kill               = tegra_cpu_kill,
        .cpu_die                = tegra_cpu_die,
+        .cpu_disable            = tegra_cpu_disable,
 #endif
 };
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 45cf52c7e528..261fec140c06 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -44,6 +44,20 @@
 static DEFINE_SPINLOCK(tegra_lp2_lock);
 void (*tegra_tear_down_cpu)(void);
+static void tegra_tear_down_cpu_init(void)
+{
+        switch (tegra_chip_id) {
+        case TEGRA20:
+                if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
+                        tegra_tear_down_cpu = tegra20_tear_down_cpu;
+                break;
+        case TEGRA30:
+                if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC))
+                        tegra_tear_down_cpu = tegra30_tear_down_cpu;
+                break;
+        }
+}
 /*
 * restore_cpu_complex
 *
@@ -91,8 +105,9 @@ static void suspend_cpu_complex(void)
        flowctrl_cpu_suspend_enter(cpu);
 }
-void tegra_clear_cpu_in_lp2(int phy_cpu_id)
+void tegra_clear_cpu_in_lp2(void)
 {
+        int phy_cpu_id = cpu_logical_map(smp_processor_id());
        u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
        spin_lock(&tegra_lp2_lock);
@@ -103,8 +118,9 @@ void tegra_clear_cpu_in_lp2(int phy_cpu_id)
        spin_unlock(&tegra_lp2_lock);
 }
-bool tegra_set_cpu_in_lp2(int phy_cpu_id)
+bool tegra_set_cpu_in_lp2(void)
 {
+        int phy_cpu_id = cpu_logical_map(smp_processor_id());
        bool last_cpu = false;
        cpumask_t *cpu_lp2_mask = tegra_cpu_lp2_mask;
        u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
@@ -175,7 +191,7 @@ static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = {
        [TEGRA_SUSPEND_LP0] = "LP0",
 };
-static int __cpuinit tegra_suspend_enter(suspend_state_t state)
+static int tegra_suspend_enter(suspend_state_t state)
 {
        enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();
@@ -192,7 +208,7 @@ static int __cpuinit tegra_suspend_enter(suspend_state_t state)
        suspend_cpu_complex();
        switch (mode) {
        case TEGRA_SUSPEND_LP2:
-                tegra_set_cpu_in_lp2(0);
+                tegra_set_cpu_in_lp2();
                break;
        default:
                break;
@@ -202,7 +218,7 @@ static int __cpuinit tegra_suspend_enter(suspend_state_t state)
        switch (mode) {
        case TEGRA_SUSPEND_LP2:
-                tegra_clear_cpu_in_lp2(0);
+                tegra_clear_cpu_in_lp2();
                break;
        default:
                break;
@@ -224,6 +240,7 @@ void __init tegra_init_suspend(void)
        if (tegra_pmc_get_suspend_mode() == TEGRA_SUSPEND_NONE)
                return;
+        tegra_tear_down_cpu_init();
        tegra_pmc_suspend_init();
        suspend_set_ops(&tegra_suspend_ops);
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h
index 778a4aa7c3fa..94c4b9d9077c 100644
--- a/arch/arm/mach-tegra/pm.h
+++ b/arch/arm/mach-tegra/pm.h
@@ -28,8 +28,8 @@ extern unsigned long l2x0_saved_regs_addr;
 void save_cpu_arch_register(void);
 void restore_cpu_arch_register(void);
-void tegra_clear_cpu_in_lp2(int phy_cpu_id);
+void tegra_clear_cpu_in_lp2(void);
-bool tegra_set_cpu_in_lp2(int phy_cpu_id);
+bool tegra_set_cpu_in_lp2(void);
 void tegra_idle_lp2_last(void);
 extern void (*tegra_tear_down_cpu)(void);
diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c
index 32360e540ce6..eb3fa4aee0e4 100644
--- a/arch/arm/mach-tegra/pmc.c
+++ b/arch/arm/mach-tegra/pmc.c
@@ -234,7 +234,7 @@ static const struct of_device_id matches[] __initconst = {
        { }
 };
-static void tegra_pmc_parse_dt(void)
+static void __init tegra_pmc_parse_dt(void)
 {
        struct device_node *np;
        u32 prop;
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index e6de88a2ea06..39dc9e7834f3 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -22,11 +22,11 @@
 #include <asm/hardware/cache-l2x0.h>
 #include "flowctrl.h"
+#include "fuse.h"
 #include "iomap.h"
 #include "reset.h"
 #include "sleep.h"
-#define APB_MISC_GP_HIDREV      0x804
 #define PMC_SCRATCH41   0x140
 #define RESET_DATA(x)   ((TEGRA_RESET_##x)*4)
@@ -38,34 +38,40 @@
 *        CPU boot vector when restarting the a CPU following
 *        an LP2 transition. Also branched to by LP0 and LP1 resume after
 *        re-enabling sdram.
+ *
+ *      r6: SoC ID
 */
 ENTRY(tegra_resume)
        bl      v7_invalidate_l1
        cpu_id  r0
+        tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
+        cmp     r6, #TEGRA114
+        beq     no_cpu0_chk
        cmp     r0, #0                          @ CPU0?
 THUMB( it      ne )
        bne     cpu_resume                      @ no
+no_cpu0_chk:
-#ifdef CONFIG_ARCH_TEGRA_3x_SOC
        /* Are we on Tegra20? */
-        mov32   r6, TEGRA_APB_MISC_BASE
+        cmp     r6, #TEGRA20
-        ldr     r0, [r6, #APB_MISC_GP_HIDREV]
-        and     r0, r0, #0xff00
-        cmp     r0, #(0x20 << 8)
        beq     1f                              @ Yes
        /* Clear the flow controller flags for this CPU. */
-        mov32   r2, TEGRA_FLOW_CTRL_BASE + FLOW_CTRL_CPU0_CSR   @ CPU0 CSR
+        cpu_to_csr_reg r1, r0
-        ldr     r1, [r2]
+        mov32   r2, TEGRA_FLOW_CTRL_BASE
+        ldr     r1, [r2, r1]
        /* Clear event & intr flag */
        orr     r1, r1, \
                #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
-        movw    r0, #0x0FFD     @ enable, cluster_switch, immed, & bitmaps
+        movw    r0, #0x3FFD     @ enable, cluster_switch, immed, bitmaps
+                                @ & ext flags for CPU power mgnt
        bic     r1, r1, r0
        str     r1, [r2]
 1:
-#endif
+        check_cpu_part_num 0xc09, r8, r9
+        bne     not_ca9
 #ifdef CONFIG_HAVE_ARM_SCU
        /* enable SCU */
        mov32   r0, TEGRA_ARM_PERIF_BASE
@@ -76,6 +82,7 @@ ENTRY(tegra_resume)
        /* L2 cache resume & re-enable */
        l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr
+not_ca9:
        b       cpu_resume
 ENDPROC(tegra_resume)
@@ -98,7 +105,7 @@ ENTRY(__tegra_cpu_reset_handler_start)
 * Register usage within the reset handler:
 *
 *      Others: scratch
- *      R6  = SoC ID << 8
+ *      R6  = SoC ID
 *      R7  = CPU present (to the OS) mask
 *      R8  = CPU in LP1 state mask
 *      R9  = CPU in LP2 state mask
@@ -115,12 +122,10 @@ ENTRY(__tegra_cpu_reset_handler)
        cpsid   aif, 0x13                       @ SVC mode, interrupts disabled
-        mov32   r6, TEGRA_APB_MISC_BASE
+        tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
-        ldr     r6, [r6, #APB_MISC_GP_HIDREV]
-        and     r6, r6, #0xff00
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
 t20_check:
-        cmp     r6, #(0x20 << 8)
+        cmp     r6, #TEGRA20
        bne     after_t20_check
 t20_errata:
        # Tegra20 is a Cortex-A9 r1p1
@@ -136,7 +141,7 @@ after_t20_check:
 #endif
 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
 t30_check:
-        cmp     r6, #(0x30 << 8)
+        cmp     r6, #TEGRA30
        bne     after_t30_check
 t30_errata:
        # Tegra30 is a Cortex-A9 r2p9
@@ -163,7 +168,7 @@ after_errata:
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
        /* Are we on Tegra20? */
-        cmp     r6, #(0x20 << 8)
+        cmp     r6, #TEGRA20
        bne     1f
        /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
        mov32   r5, TEGRA_PMC_BASE
@@ -186,11 +191,14 @@ __is_not_lp2:
 #ifdef CONFIG_SMP
        /*
-         * Can only be secondary boot (initial or hotplug) but CPU 0
+         * Can only be secondary boot (initial or hotplug)
-         * cannot be here.
+         * CPU0 can't be here for Tegra20/30
         */
+        cmp     r6, #TEGRA114
+        beq     __no_cpu0_chk
        cmp     r10, #0
        bleq    __die                           @ CPU0 cannot be here
+__no_cpu0_chk:
        ldr     lr, [r12, #RESET_DATA(STARTUP_SECONDARY)]
        cmp     lr, #0
        bleq    __die                           @ no secondary startup handler
@@ -210,10 +218,7 @@ __die:
        mov32   r7, TEGRA_CLK_RESET_BASE
        /* Are we on Tegra20? */
-        mov32   r6, TEGRA_APB_MISC_BASE
+        cmp     r6, #TEGRA20
-        ldr     r0, [r6, #APB_MISC_GP_HIDREV]
-        and     r0, r0, #0xff00
-        cmp     r0, #(0x20 << 8)
        bne     1f
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index d29dfcce948d..ada8821b48be 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -19,6 +19,7 @@
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
+#include "fuse.h"
 #include "sleep.h"
 #include "flowctrl.h"
@@ -43,14 +44,19 @@ ENDPROC(tegra30_hotplug_shutdown)
 *
 * Puts the current CPU in wait-for-event mode on the flow controller
 * and powergates it -- flags (in R0) indicate the request type.
- * Must never be called for CPU 0.
 *
- * corrupts r0-r4, r12
+ * r10 = SoC ID
+ * corrupts r0-r4, r10-r12
 */
 ENTRY(tegra30_cpu_shutdown)
        cpu_id  r3
+        tegra_get_soc_id TEGRA_APB_MISC_VIRT, r10
+        cmp     r10, #TEGRA30
+        bne     _no_cpu0_chk    @ It's not Tegra30
        cmp     r3, #0
        moveq   pc, lr          @ Must never be called for CPU 0
+_no_cpu0_chk:
        ldr     r12, =TEGRA_FLOW_CTRL_VIRT
        cpu_to_csr_reg r1, r3
@@ -65,7 +71,9 @@ ENTRY(tegra30_cpu_shutdown)
        movw    r12, \
                FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \
                FLOW_CTRL_CSR_ENABLE
-        mov     r4, #(1 << 4)
+        cmp     r10, #TEGRA30
+        moveq   r4, #(1 << 4)                   @ wfe bitmap
+        movne   r4, #(1 << 8)                   @ wfi bitmap
 ARM(   orr     r12, r12, r4, lsl r3    )
 THUMB( lsl     r4, r4, r3              )
 THUMB( orr     r12, r12, r4            )
@@ -79,9 +87,20 @@ delay_1:
        cpsid   a                               @ disable imprecise aborts.
        ldr     r3, [r1]                        @ read CSR
        str     r3, [r1]                        @ clear CSR
        tst     r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
+        beq     flow_ctrl_setting_for_lp2
+        /* flow controller set up for hotplug */
+        mov     r3, #FLOW_CTRL_WAITEVENT                @ For hotplug
+        b       flow_ctrl_done
+flow_ctrl_setting_for_lp2:
+        /* flow controller set up for LP2 */
+        cmp     r10, #TEGRA30
        moveq   r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT       @ For LP2
-        movne   r3, #FLOW_CTRL_WAITEVENT                @ For hotplug
+        movne   r3, #FLOW_CTRL_WAITEVENT
+flow_ctrl_done:
+        cmp     r10, #TEGRA30
        str     r3, [r2]
        ldr     r0, [r2]
        b       wfe_war
@@ -89,7 +108,8 @@ delay_1:
 __cpu_reset_again:
        dsb
        .align 5
-        wfe                                     @ CPU should be power gated here
+        wfeeq                                   @ CPU should be power gated here
+        wfine
 wfe_war:
        b       __cpu_reset_again
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index 364d84523fba..9daaef26b0f6 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -106,9 +106,11 @@ ENTRY(tegra_shut_off_mmu)
        isb
 #ifdef CONFIG_CACHE_L2X0
        /* Disable L2 cache */
-        mov32   r4, TEGRA_ARM_PERIF_BASE + 0x3000
+        check_cpu_part_num 0xc09, r9, r10
-        mov     r5, #0
+        movweq  r4, #:lower16:(TEGRA_ARM_PERIF_BASE + 0x3000)
-        str     r5, [r4, #L2X0_CTRL]
+        movteq  r4, #:upper16:(TEGRA_ARM_PERIF_BASE + 0x3000)
+        moveq   r5, #0
+        streq   r5, [r4, #L2X0_CTRL]
 #endif
        mov     pc, r0
 ENDPROC(tegra_shut_off_mmu)
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index 2080fb12ce26..98b7da698f2b 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -25,6 +25,8 @@
                                        + IO_PPSB_VIRT)
 #define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \
                                        + IO_PPSB_VIRT)
+#define TEGRA_APB_MISC_VIRT (TEGRA_APB_MISC_BASE - IO_APB_PHYS \
+                                        + IO_APB_VIRT)
 #define TEGRA_PMC_VIRT  (TEGRA_PMC_BASE - IO_APB_PHYS + IO_APB_VIRT)
 /* PMC_SCRATCH37-39 and 41 are used for tegra_pen_lock and idle */
@@ -70,19 +72,40 @@
        movt    \reg, #:upper16:\val
 .endm
+/* Marco to check CPU part num */
+.macro check_cpu_part_num part_num, tmp1, tmp2
+        mrc     p15, 0, \tmp1, c0, c0, 0
+        ubfx    \tmp1, \tmp1, #4, #12
+        mov32   \tmp2, \part_num
+        cmp     \tmp1, \tmp2
+.endm
 /* Macro to exit SMP coherency. */
 .macro exit_smp, tmp1, tmp2
        mrc     p15, 0, \tmp1, c1, c0, 1        @ ACTLR
        bic     \tmp1, \tmp1, #(1<<6) | (1<<0)  @ clear ACTLR.SMP | ACTLR.FW
        mcr     p15, 0, \tmp1, c1, c0, 1        @ ACTLR
        isb
-        cpu_id  \tmp1
+#ifdef CONFIG_HAVE_ARM_SCU
-        mov     \tmp1, \tmp1, lsl #2
+        check_cpu_part_num 0xc09, \tmp1, \tmp2
-        mov     \tmp2, #0xf
+        mrceq   p15, 0, \tmp1, c0, c0, 5
-        mov     \tmp2, \tmp2, lsl \tmp1
+        andeq   \tmp1, \tmp1, #0xF
-        mov32   \tmp1, TEGRA_ARM_PERIF_VIRT + 0xC
+        moveq   \tmp1, \tmp1, lsl #2
-        str     \tmp2, [\tmp1]                  @ invalidate SCU tags for CPU
+        moveq   \tmp2, #0xf
+        moveq   \tmp2, \tmp2, lsl \tmp1
+        ldreq   \tmp1, =(TEGRA_ARM_PERIF_VIRT + 0xC)
+        streq   \tmp2, [\tmp1]                  @ invalidate SCU tags for CPU
        dsb
+#endif
+.endm
+/* Macro to check Tegra revision */
+#define APB_MISC_GP_HIDREV      0x804
+.macro tegra_get_soc_id base, tmp1
+        mov32   \tmp1, \base
+        ldr     \tmp1, [\tmp1, #APB_MISC_GP_HIDREV]
+        and     \tmp1, \tmp1, #0xff00
+        mov     \tmp1, \tmp1, lsr #8
 .endm
 /* Macro to resume & re-enable L2 cache */
diff --git a/arch/arm/mach-tegra/tegra2_emc.c b/arch/arm/mach-tegra/tegra2_emc.c
index 31e69a019bdd..3ae4a7f1a2fb 100644
--- a/arch/arm/mach-tegra/tegra2_emc.c
+++ b/arch/arm/mach-tegra/tegra2_emc.c
@@ -183,7 +183,7 @@ static struct device_node *tegra_emc_ramcode_devnode(struct device_node *np)
        u32 reg;
        for_each_child_of_node(np, iter) {
-                if (of_property_read_u32(np, "nvidia,ram-code", &reg))
+                if (of_property_read_u32(iter, "nvidia,ram-code", &reg))
                        continue;
                if (reg == tegra_bct_strapping)
                        return of_node_get(iter);
diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig
index 1f597647d431..a85adcd00882 100644
--- a/arch/arm/mach-u300/Kconfig
+++ b/arch/arm/mach-u300/Kconfig
@@ -1,24 +1,46 @@
-if ARCH_U300
 menu "ST-Ericsson AB U300/U335 Platform"
 comment "ST-Ericsson Mobile Platform Products"
-config MACH_U300
+config ARCH_U300
-        bool "U300"
+        bool "ST-Ericsson U300 Series" if ARCH_MULTI_V5
+        depends on MMU
+        select ARCH_REQUIRE_GPIOLIB
+        select ARM_AMBA
+        select ARM_PATCH_PHYS_VIRT
+        select ARM_VIC
+        select CLKDEV_LOOKUP
+        select CLKSRC_MMIO
+        select CLKSRC_OF
+        select COMMON_CLK
+        select CPU_ARM926T
+        select GENERIC_CLOCKEVENTS
+        select HAVE_TCM
        select PINCTRL
        select PINCTRL_COH901
        select PINCTRL_U300
+        select SPARSE_IRQ
+        select MFD_SYSCON
+        select USE_OF
+        help
+          Support for ST-Ericsson U300 series mobile platforms.
 comment "ST-Ericsson U300/U335 Feature Selections"
+config MACH_U300
+        depends on ARCH_U300
+        bool "U300"
+        default y
 config U300_DEBUG
+        depends on ARCH_U300
        bool "Debug support for U300"
        depends on PM
        help
                Debug support for U300 in sysfs, procfs etc.
 config MACH_U300_SPIDUMMY
+        depends on ARCH_U300
        bool "SSP/SPI dummy chip"
        select SPI
        select SPI_MASTER
@@ -31,5 +53,3 @@ config MACH_U300_SPIDUMMY
                SPI framework and ARM PL022 support.
 endmenu
-endif
diff --git a/arch/arm/mach-u300/Makefile b/arch/arm/mach-u300/Makefile
index 5a86c58da396..0f362b64fb87 100644
--- a/arch/arm/mach-u300/Makefile
+++ b/arch/arm/mach-u300/Makefile
@@ -7,7 +7,5 @@ obj-m		:=
 obj-n           :=
 obj-            :=
-obj-$(CONFIG_SPI_PL022)           += spi.o
 obj-$(CONFIG_MACH_U300_SPIDUMMY)  += dummyspichip.o
-obj-$(CONFIG_I2C_STU300)          += i2c.o
 obj-$(CONFIG_REGULATOR_AB3100)    += regulator.o
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index a683d17b2ce4..35670b15f281 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -9,46 +9,157 @@
 * Author: Linus Walleij <linus.walleij@stericsson.com>
 */
 #include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/interrupt.h>
-#include <linux/bitops.h>
-#include <linux/device.h>
-#include <linux/mm.h>
-#include <linux/termios.h>
-#include <linux/dmaengine.h>
-#include <linux/amba/bus.h>
-#include <linux/amba/mmci.h>
-#include <linux/amba/serial.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/mtd/nand.h>
-#include <linux/mtd/fsmc.h>
 #include <linux/pinctrl/machine.h>
 #include <linux/pinctrl/pinconf-generic.h>
-#include <linux/dma-mapping.h>
 #include <linux/platform_data/clk-u300.h>
-#include <linux/platform_data/pinctrl-coh901.h>
+#include <linux/irqchip.h>
-#include <linux/platform_data/dma-coh901318.h>
+#include <linux/of_address.h>
-#include <linux/irqchip/arm-vic.h>
+#include <linux/of_platform.h>
+#include <linux/clocksource.h>
+#include <linux/clk.h>
-#include <asm/types.h>
-#include <asm/setup.h>
-#include <asm/memory.h>
 #include <asm/mach/map.h>
-#include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <mach/hardware.h>
+/*
-#include <mach/syscon.h>
+ * These are the large blocks of memory allocated for I/O.
-#include <mach/irqs.h>
+ * the defines are used for setting up the I/O memory mapping.
+ */
+/* NAND Flash CS0 */
+#define U300_NAND_CS0_PHYS_BASE         0x80000000
+/* NFIF */
+#define U300_NAND_IF_PHYS_BASE          0x9f800000
+/* ALE, CLE offset for FSMC NAND */
+#define PLAT_NAND_CLE                   (1 << 16)
+#define PLAT_NAND_ALE                   (1 << 17)
+/* AHB Peripherals */
+#define U300_AHB_PER_PHYS_BASE          0xa0000000
+#define U300_AHB_PER_VIRT_BASE          0xff010000
+/* FAST Peripherals */
+#define U300_FAST_PER_PHYS_BASE         0xc0000000
+#define U300_FAST_PER_VIRT_BASE         0xff020000
+/* SLOW Peripherals */
+#define U300_SLOW_PER_PHYS_BASE         0xc0010000
+#define U300_SLOW_PER_VIRT_BASE         0xff000000
+/* Boot ROM */
+#define U300_BOOTROM_PHYS_BASE          0xffff0000
+#define U300_BOOTROM_VIRT_BASE          0xffff0000
+/* SEMI config base */
+#define U300_SEMI_CONFIG_BASE           0x2FFE0000
+/*
+ * AHB peripherals
+ */
+/* AHB Peripherals Bridge Controller */
+#define U300_AHB_BRIDGE_BASE            (U300_AHB_PER_PHYS_BASE+0x0000)
+/* Vectored Interrupt Controller 0, servicing 32 interrupts */
+#define U300_INTCON0_BASE               (U300_AHB_PER_PHYS_BASE+0x1000)
+#define U300_INTCON0_VBASE              IOMEM(U300_AHB_PER_VIRT_BASE+0x1000)
+/* Vectored Interrupt Controller 1, servicing 32 interrupts */
+#define U300_INTCON1_BASE               (U300_AHB_PER_PHYS_BASE+0x2000)
+#define U300_INTCON1_VBASE              IOMEM(U300_AHB_PER_VIRT_BASE+0x2000)
+/* Memory Stick Pro (MSPRO) controller */
+#define U300_MSPRO_BASE                 (U300_AHB_PER_PHYS_BASE+0x3000)
+/* EMIF Configuration Area */
+#define U300_EMIF_CFG_BASE              (U300_AHB_PER_PHYS_BASE+0x4000)
+/*
+ * FAST peripherals
+ */
+/* FAST bridge control */
+#define U300_FAST_BRIDGE_BASE           (U300_FAST_PER_PHYS_BASE+0x0000)
+/* MMC/SD controller */
+#define U300_MMCSD_BASE                 (U300_FAST_PER_PHYS_BASE+0x1000)
+/* PCM I2S0 controller */
+#define U300_PCM_I2S0_BASE              (U300_FAST_PER_PHYS_BASE+0x2000)
+/* PCM I2S1 controller */
+#define U300_PCM_I2S1_BASE              (U300_FAST_PER_PHYS_BASE+0x3000)
+/* I2C0 controller */
+#define U300_I2C0_BASE                  (U300_FAST_PER_PHYS_BASE+0x4000)
+/* I2C1 controller */
+#define U300_I2C1_BASE                  (U300_FAST_PER_PHYS_BASE+0x5000)
+/* SPI controller */
+#define U300_SPI_BASE                   (U300_FAST_PER_PHYS_BASE+0x6000)
+/* Fast UART1 on U335 only */
+#define U300_UART1_BASE                 (U300_FAST_PER_PHYS_BASE+0x7000)
+/*
+ * SLOW peripherals
+ */
-#include "timer.h"
+/* SLOW bridge control */
-#include "spi.h"
+#define U300_SLOW_BRIDGE_BASE           (U300_SLOW_PER_PHYS_BASE)
-#include "i2c.h"
+/* SYSCON */
-#include "u300-gpio.h"
+#define U300_SYSCON_BASE                (U300_SLOW_PER_PHYS_BASE+0x1000)
+#define U300_SYSCON_VBASE               IOMEM(U300_SLOW_PER_VIRT_BASE+0x1000)
+/* Watchdog */
+#define U300_WDOG_BASE                  (U300_SLOW_PER_PHYS_BASE+0x2000)
+/* UART0 */
+#define U300_UART0_BASE                 (U300_SLOW_PER_PHYS_BASE+0x3000)
+/* APP side special timer */
+#define U300_TIMER_APP_BASE             (U300_SLOW_PER_PHYS_BASE+0x4000)
+#define U300_TIMER_APP_VBASE            IOMEM(U300_SLOW_PER_VIRT_BASE+0x4000)
+/* Keypad */
+#define U300_KEYPAD_BASE                (U300_SLOW_PER_PHYS_BASE+0x5000)
+/* GPIO */
+#define U300_GPIO_BASE                  (U300_SLOW_PER_PHYS_BASE+0x6000)
+/* RTC */
+#define U300_RTC_BASE                   (U300_SLOW_PER_PHYS_BASE+0x7000)
+/* Bus tracer */
+#define U300_BUSTR_BASE                 (U300_SLOW_PER_PHYS_BASE+0x8000)
+/* Event handler (hardware queue) */
+#define U300_EVHIST_BASE                (U300_SLOW_PER_PHYS_BASE+0x9000)
+/* Genric Timer */
+#define U300_TIMER_BASE                 (U300_SLOW_PER_PHYS_BASE+0xa000)
+/* PPM */
+#define U300_PPM_BASE                   (U300_SLOW_PER_PHYS_BASE+0xb000)
+/*
+ * REST peripherals
+ */
+/* ISP (image signal processor) */
+#define U300_ISP_BASE                   (0xA0008000)
+/* DMA Controller base */
+#define U300_DMAC_BASE                  (0xC0020000)
+/* MSL Base */
+#define U300_MSL_BASE                   (0xc0022000)
+/* APEX Base */
+#define U300_APEX_BASE                  (0xc0030000)
+/* Video Encoder Base */
+#define U300_VIDEOENC_BASE              (0xc0080000)
+/* XGAM Base */
+#define U300_XGAM_BASE                  (0xd0000000)
+/*
+ * SYSCON addresses applicable to the core machine.
+ */
+/* Chip ID register 16bit (R/-) */
+#define U300_SYSCON_CIDR                                        (0x400)
+/* SMCR */
+#define U300_SYSCON_SMCR                                        (0x4d0)
+#define U300_SYSCON_SMCR_FIELD_MASK                             (0x000e)
+#define U300_SYSCON_SMCR_SEMI_SREFACK_IND                       (0x0008)
+#define U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE                    (0x0004)
+#define U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE              (0x0002)
+/* CPU_SW_DBGEN Software Debug Enable 16bit (R/W) */
+#define U300_SYSCON_CSDR                                        (0x4f0)
+#define U300_SYSCON_CSDR_SW_DEBUG_ENABLE                        (0x0001)
+/* PRINT_CONTROL Print Control 16bit (R/-) */
+#define U300_SYSCON_PCR                                         (0x4f8)
+#define U300_SYSCON_PCR_SERV_IND                                (0x0001)
+/* BOOT_CONTROL 16bit (R/-) */
+#define U300_SYSCON_BCR                                         (0x4fc)
+#define U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND              (0x0400)
+#define U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND              (0x0200)
+#define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK                  (0x01FC)
+#define U300_SYSCON_BCR_APP_BOOT_SERV_MASK                      (0x0003)
+static void __iomem *syscon_base;
 /*
 * Static I/O mappings that are needed for booting the U300 platforms. The
@@ -82,365 +193,6 @@ static void __init u300_map_io(void)
        iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
 }
-/*
- * Declaration of devices found on the U300 board and
- * their respective memory locations.
- */
-static struct amba_pl011_data uart0_plat_data = {
-#ifdef CONFIG_COH901318
-        .dma_filter = coh901318_filter_id,
-        .dma_rx_param = (void *) U300_DMA_UART0_RX,
-        .dma_tx_param = (void *) U300_DMA_UART0_TX,
-#endif
-};
-/* Slow device at 0x3000 offset */
-static AMBA_APB_DEVICE(uart0, "uart0", 0, U300_UART0_BASE,
-        { IRQ_U300_UART0 }, &uart0_plat_data);
-/* The U335 have an additional UART1 on the APP CPU */
-static struct amba_pl011_data uart1_plat_data = {
-#ifdef CONFIG_COH901318
-        .dma_filter = coh901318_filter_id,
-        .dma_rx_param = (void *) U300_DMA_UART1_RX,
-        .dma_tx_param = (void *) U300_DMA_UART1_TX,
-#endif
-};
-/* Fast device at 0x7000 offset */
-static AMBA_APB_DEVICE(uart1, "uart1", 0, U300_UART1_BASE,
-        { IRQ_U300_UART1 }, &uart1_plat_data);
-/* AHB device at 0x4000 offset */
-static AMBA_APB_DEVICE(pl172, "pl172", 0, U300_EMIF_CFG_BASE, { }, NULL);
-/* Fast device at 0x6000 offset */
-static AMBA_APB_DEVICE(pl022, "pl022", 0, U300_SPI_BASE,
-        { IRQ_U300_SPI }, NULL);
-/* Fast device at 0x1000 offset */
-#define U300_MMCSD_IRQS { IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 }
-static struct mmci_platform_data mmcsd_platform_data = {
-        /*
-         * Do not set ocr_mask or voltage translation function,
-         * we have a regulator we can control instead.
-         */
-        .f_max = 24000000,
-        .gpio_wp = -1,
-        .gpio_cd = U300_GPIO_PIN_MMC_CD,
-        .cd_invert = true,
-        .capabilities = MMC_CAP_MMC_HIGHSPEED |
-        MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
-#ifdef CONFIG_COH901318
-        .dma_filter = coh901318_filter_id,
-        .dma_rx_param = (void *) U300_DMA_MMCSD_RX_TX,
-        /* Don't specify a TX channel, this RX channel is bidirectional */
-#endif
-};
-static AMBA_APB_DEVICE(mmcsd, "mmci", 0, U300_MMCSD_BASE,
-        U300_MMCSD_IRQS, &mmcsd_platform_data);
-/*
- * The order of device declaration may be important, since some devices
- * have dependencies on other devices being initialized first.
- */
-static struct amba_device *amba_devs[] __initdata = {
-        &uart0_device,
-        &uart1_device,
-        &pl022_device,
-        &pl172_device,
-        &mmcsd_device,
-};
-/* Here follows a list of all hw resources that the platform devices
- * allocate. Note, clock dependencies are not included
- */
-static struct resource gpio_resources[] = {
-        {
-                .start = U300_GPIO_BASE,
-                .end   = (U300_GPIO_BASE + SZ_4K - 1),
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .name  = "gpio0",
-                .start = IRQ_U300_GPIO_PORT0,
-                .end   = IRQ_U300_GPIO_PORT0,
-                .flags = IORESOURCE_IRQ,
-        },
-        {
-                .name  = "gpio1",
-                .start = IRQ_U300_GPIO_PORT1,
-                .end   = IRQ_U300_GPIO_PORT1,
-                .flags = IORESOURCE_IRQ,
-        },
-        {
-                .name  = "gpio2",
-                .start = IRQ_U300_GPIO_PORT2,
-                .end   = IRQ_U300_GPIO_PORT2,
-                .flags = IORESOURCE_IRQ,
-        },
-        {
-                .name  = "gpio3",
-                .start = IRQ_U300_GPIO_PORT3,
-                .end   = IRQ_U300_GPIO_PORT3,
-                .flags = IORESOURCE_IRQ,
-        },
-        {
-                .name  = "gpio4",
-                .start = IRQ_U300_GPIO_PORT4,
-                .end   = IRQ_U300_GPIO_PORT4,
-                .flags = IORESOURCE_IRQ,
-        },
-        {
-                .name  = "gpio5",
-                .start = IRQ_U300_GPIO_PORT5,
-                .end   = IRQ_U300_GPIO_PORT5,
-                .flags = IORESOURCE_IRQ,
-        },
-        {
-                .name  = "gpio6",
-                .start = IRQ_U300_GPIO_PORT6,
-                .end   = IRQ_U300_GPIO_PORT6,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-static struct resource keypad_resources[] = {
-        {
-                .start = U300_KEYPAD_BASE,
-                .end   = U300_KEYPAD_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .name  = "coh901461-press",
-                .start = IRQ_U300_KEYPAD_KEYBF,
-                .end   = IRQ_U300_KEYPAD_KEYBF,
-                .flags = IORESOURCE_IRQ,
-        },
-        {
-                .name  = "coh901461-release",
-                .start = IRQ_U300_KEYPAD_KEYBR,
-                .end   = IRQ_U300_KEYPAD_KEYBR,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-static struct resource rtc_resources[] = {
-        {
-                .start = U300_RTC_BASE,
-                .end   = U300_RTC_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .start = IRQ_U300_RTC,
-                .end   = IRQ_U300_RTC,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-/*
- * Fsmc does have IRQs: #43 and #44 (NFIF and NFIF2)
- * but these are not yet used by the driver.
- */
-static struct resource fsmc_resources[] = {
-        {
-                .name  = "nand_addr",
-                .start = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_ALE,
-                .end   = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_ALE + SZ_16K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .name  = "nand_cmd",
-                .start = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_CLE,
-                .end   = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_CLE + SZ_16K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .name  = "nand_data",
-                .start = U300_NAND_CS0_PHYS_BASE,
-                .end   = U300_NAND_CS0_PHYS_BASE + SZ_16K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .name  = "fsmc_regs",
-                .start = U300_NAND_IF_PHYS_BASE,
-                .end   = U300_NAND_IF_PHYS_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-};
-static struct resource i2c0_resources[] = {
-        {
-                .start = U300_I2C0_BASE,
-                .end   = U300_I2C0_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .start = IRQ_U300_I2C0,
-                .end   = IRQ_U300_I2C0,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-static struct resource i2c1_resources[] = {
-        {
-                .start = U300_I2C1_BASE,
-                .end   = U300_I2C1_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .start = IRQ_U300_I2C1,
-                .end   = IRQ_U300_I2C1,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-static struct resource wdog_resources[] = {
-        {
-                .start = U300_WDOG_BASE,
-                .end   = U300_WDOG_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .start = IRQ_U300_WDOG,
-                .end   = IRQ_U300_WDOG,
-                .flags = IORESOURCE_IRQ,
-        }
-};
-static struct resource dma_resource[] = {
-        {
-                .start = U300_DMAC_BASE,
-                .end = U300_DMAC_BASE + PAGE_SIZE - 1,
-                .flags =  IORESOURCE_MEM,
-        },
-        {
-                .start = IRQ_U300_DMA,
-                .end = IRQ_U300_DMA,
-                .flags =  IORESOURCE_IRQ,
-        }
-};
-static struct resource pinctrl_resources[] = {
-        {
-                .start = U300_SYSCON_BASE,
-                .end   = U300_SYSCON_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-};
-static struct platform_device wdog_device = {
-        .name = "coh901327_wdog",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(wdog_resources),
-        .resource = wdog_resources,
-};
-static struct platform_device i2c0_device = {
-        .name = "stu300",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(i2c0_resources),
-        .resource = i2c0_resources,
-};
-static struct platform_device i2c1_device = {
-        .name = "stu300",
-        .id = 1,
-        .num_resources = ARRAY_SIZE(i2c1_resources),
-        .resource = i2c1_resources,
-};
-static struct platform_device pinctrl_device = {
-        .name = "pinctrl-u300",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(pinctrl_resources),
-        .resource = pinctrl_resources,
-};
-/*
- * The different variants have a few different versions of the
- * GPIO block, with different number of ports.
- */
-static struct u300_gpio_platform u300_gpio_plat = {
-        .ports = 7,
-        .gpio_base = 0,
-};
-static struct platform_device gpio_device = {
-        .name = "u300-gpio",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(gpio_resources),
-        .resource = gpio_resources,
-        .dev = {
-                .platform_data = &u300_gpio_plat,
-        },
-};
-static struct platform_device keypad_device = {
-        .name = "keypad",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(keypad_resources),
-        .resource = keypad_resources,
-};
-static struct platform_device rtc_device = {
-        .name = "rtc-coh901331",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(rtc_resources),
-        .resource = rtc_resources,
-};
-static struct mtd_partition u300_partitions[] = {
-        {
-                .name = "bootrecords",
-                .offset = 0,
-                .size = SZ_128K,
-        },
-        {
-                .name = "free",
-                .offset = SZ_128K,
-                .size = 8064 * SZ_1K,
-        },
-        {
-                .name = "platform",
-                .offset = 8192 * SZ_1K,
-                .size = 253952 * SZ_1K,
-        },
-};
-static struct fsmc_nand_platform_data nand_platform_data = {
-        .partitions = u300_partitions,
-        .nr_partitions = ARRAY_SIZE(u300_partitions),
-        .options = NAND_SKIP_BBTSCAN,
-        .width = FSMC_NAND_BW8,
-};
-static struct platform_device nand_device = {
-        .name = "fsmc-nand",
-        .id = -1,
-        .resource = fsmc_resources,
-        .num_resources = ARRAY_SIZE(fsmc_resources),
-        .dev = {
-                .platform_data = &nand_platform_data,
-        },
-};
-static struct platform_device dma_device = {
-        .name           = "coh901318",
-        .id             = -1,
-        .resource       = dma_resource,
-        .num_resources  = ARRAY_SIZE(dma_resource),
-        .dev = {
-                .coherent_dma_mask = ~0,
-        },
-};
 static unsigned long pin_pullup_conf[] = {
        PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 1),
 };
@@ -467,61 +219,6 @@ static struct pinctrl_map __initdata u300_pinmux_map[] = {
                                    pin_highz_conf),
 };
-/*
- * Notice that AMBA devices are initialized before platform devices.
- *
- */
-static struct platform_device *platform_devs[] __initdata = {
-        &dma_device,
-        &i2c0_device,
-        &i2c1_device,
-        &keypad_device,
-        &rtc_device,
-        &pinctrl_device,
-        &gpio_device,
-        &nand_device,
-        &wdog_device,
-};
-/*
- * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected
- * together so some interrupts are connected to the first one and some
- * to the second one.
- */
-static void __init u300_init_irq(void)
-{
-        u32 mask[2] = {0, 0};
-        struct clk *clk;
-        int i;
-        /* initialize clocking early, we want to clock the INTCON */
-        u300_clk_init(U300_SYSCON_VBASE);
-        /* Bootstrap EMIF and SEMI clocks */
-        clk = clk_get_sys("pl172", NULL);
-        BUG_ON(IS_ERR(clk));
-        clk_prepare_enable(clk);
-        clk = clk_get_sys("semi", NULL);
-        BUG_ON(IS_ERR(clk));
-        clk_prepare_enable(clk);
-        /* Clock the interrupt controller */
-        clk = clk_get_sys("intcon", NULL);
-        BUG_ON(IS_ERR(clk));
-        clk_prepare_enable(clk);
-        for (i = 0; i < U300_VIC_IRQS_END; i++)
-                set_bit(i, (unsigned long *) &mask[0]);
-        vic_init((void __iomem *) U300_INTCON0_VBASE, IRQ_U300_INTCON0_START,
-                 mask[0], mask[0]);
-        vic_init((void __iomem *) U300_INTCON1_VBASE, IRQ_U300_INTCON1_START,
-                 mask[1], mask[1]);
-}
-/*
- * U300 platforms peripheral handling
- */
 struct db_chip {
        u16 chipid;
        const char *name;
@@ -578,7 +275,7 @@ static void __init u300_init_check_chip(void)
        const char unknown[] = "UNKNOWN";
        /* Read out and print chip ID */
-        val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR);
+        val = readw(syscon_base + U300_SYSCON_CIDR);
        /* This is in funky bigendian order... */
        val = (val & 0xFFU) << 8 | (val >> 8);
        chip = db_chips;
@@ -600,101 +297,119 @@ static void __init u300_init_check_chip(void)
        }
 }
-/*
+/* Forward declare this function from the watchdog */
- * Some devices and their resources require reserved physical memory from
+void coh901327_watchdog_reset(void);
- * the end of the available RAM. This function traverses the list of devices
- * and assigns actual addresses to these.
+static void u300_restart(enum reboot_mode mode, const char *cmd)
- */
-static void __init u300_assign_physmem(void)
 {
-        unsigned long curr_start = __pa(high_memory);
+        switch (mode) {
-        int i, j;
+        case REBOOT_SOFT:
+        case REBOOT_HARD:
-        for (i = 0; i < ARRAY_SIZE(platform_devs); i++) {
+#ifdef CONFIG_COH901327_WATCHDOG
-                for (j = 0; j < platform_devs[i]->num_resources; j++) {
+                coh901327_watchdog_reset();
-                        struct resource *const res =
+#endif
-                          &platform_devs[i]->resource[j];
+                break;
+        default:
-                        if (IORESOURCE_MEM == res->flags &&
+                /* Do nothing */
-                                     0 == res->start) {
+                break;
-                                res->start  = curr_start;
-                                res->end   += curr_start;
-                                curr_start += resource_size(res);
-                                printk(KERN_INFO "core.c: Mapping RAM " \
-                                       "%#x-%#x to device %s:%s\n",
-                                        res->start, res->end,
-                                       platform_devs[i]->name, res->name);
-                        }
-                }
        }
+        /* Wait for system do die/reset. */
+        while (1);
 }
-static void __init u300_init_machine(void)
+/* These are mostly to get the right device names for the clock lookups */
+static struct of_dev_auxdata u300_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("stericsson,pinctrl-u300", U300_SYSCON_BASE,
+                "pinctrl-u300", NULL),
+        OF_DEV_AUXDATA("stericsson,gpio-coh901", U300_GPIO_BASE,
+                "u300-gpio", NULL),
+        OF_DEV_AUXDATA("stericsson,coh901327", U300_WDOG_BASE,
+                "coh901327_wdog", NULL),
+        OF_DEV_AUXDATA("stericsson,coh901331", U300_RTC_BASE,
+                "rtc-coh901331", NULL),
+        OF_DEV_AUXDATA("stericsson,coh901318", U300_DMAC_BASE,
+                "coh901318", NULL),
+        OF_DEV_AUXDATA("stericsson,fsmc-nand", U300_NAND_IF_PHYS_BASE,
+                "fsmc-nand", NULL),
+        OF_DEV_AUXDATA("arm,primecell", U300_UART0_BASE,
+                "uart0", NULL),
+        OF_DEV_AUXDATA("arm,primecell", U300_UART1_BASE,
+                "uart1", NULL),
+        OF_DEV_AUXDATA("arm,primecell", U300_SPI_BASE,
+                "pl022", NULL),
+        OF_DEV_AUXDATA("st,ddci2c", U300_I2C0_BASE,
+                "stu300.0", NULL),
+        OF_DEV_AUXDATA("st,ddci2c", U300_I2C1_BASE,
+                "stu300.1", NULL),
+        OF_DEV_AUXDATA("arm,primecell", U300_MMCSD_BASE,
+                "mmci", NULL),
+        { /* sentinel */ },
+};
+static void __init u300_init_irq_dt(void)
 {
-        int i;
+        struct device_node *syscon;
-        u16 val;
+        struct clk *clk;
-        /* Check what platform we run and print some status information */
+        syscon = of_find_node_by_path("/syscon@c0011000");
-        u300_init_check_chip();
+        if (!syscon) {
+                pr_crit("could not find syscon node\n");
+                return;
+        }
+        syscon_base = of_iomap(syscon, 0);
+        if (!syscon_base) {
+                pr_crit("could not remap syscon\n");
+                return;
+        }
+        /* initialize clocking early, we want to clock the INTCON */
+        u300_clk_init(syscon_base);
-        /* Initialize SPI device with some board specifics */
+        /* Bootstrap EMIF and SEMI clocks */
-        u300_spi_init(&pl022_device);
+        clk = clk_get_sys("pl172", NULL);
+        BUG_ON(IS_ERR(clk));
+        clk_prepare_enable(clk);
+        clk = clk_get_sys("semi", NULL);
+        BUG_ON(IS_ERR(clk));
+        clk_prepare_enable(clk);
-        /* Register the AMBA devices in the AMBA bus abstraction layer */
+        /* Clock the interrupt controller */
-        for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
+        clk = clk_get_sys("intcon", NULL);
-                struct amba_device *d = amba_devs[i];
+        BUG_ON(IS_ERR(clk));
-                amba_device_register(d, &iomem_resource);
+        clk_prepare_enable(clk);
-        }
-        u300_assign_physmem();
+        irqchip_init();
+}
+static void __init u300_init_machine_dt(void)
+{
+        u16 val;
+        /* Check what platform we run and print some status information */
+        u300_init_check_chip();
        /* Initialize pinmuxing */
        pinctrl_register_mappings(u300_pinmux_map,
                                  ARRAY_SIZE(u300_pinmux_map));
-        /* Register subdevices on the I2C buses */
+        of_platform_populate(NULL, of_default_bus_match_table,
-        u300_i2c_register_board_devices();
+                        u300_auxdata_lookup, NULL);
-        /* Register the platform devices */
-        platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
-        /* Register subdevices on the SPI bus */
-        u300_spi_register_board_devices();
        /* Enable SEMI self refresh */
-        val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
+        val = readw(syscon_base + U300_SYSCON_SMCR) |
                U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
-        writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
+        writew(val, syscon_base + U300_SYSCON_SMCR);
 }
-/* Forward declare this function from the watchdog */
+static const char * u300_board_compat[] = {
-void coh901327_watchdog_reset(void);
+        "stericsson,u300",
+        NULL,
-static void u300_restart(char mode, const char *cmd)
+};
-{
-        switch (mode) {
-        case 's':
-        case 'h':
-#ifdef CONFIG_COH901327_WATCHDOG
-                coh901327_watchdog_reset();
-#endif
-                break;
-        default:
-                /* Do nothing */
-                break;
-        }
-        /* Wait for system do die/reset. */
-        while (1);
-}
-MACHINE_START(U300, "Ericsson AB U335 S335/B335 Prototype Board")
+DT_MACHINE_START(U300_DT, "U300 S335/B335 (Device Tree)")
-        /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */
-        .atag_offset    = 0x100,
        .map_io         = u300_map_io,
-        .nr_irqs        = 0,
+        .init_irq       = u300_init_irq_dt,
-        .init_irq       = u300_init_irq,
+        .init_time      = clocksource_of_init,
-        .init_time      = u300_timer_init,
+        .init_machine   = u300_init_machine_dt,
-        .init_machine   = u300_init_machine,
        .restart        = u300_restart,
+        .dt_compat      = u300_board_compat,
 MACHINE_END
diff --git a/arch/arm/mach-u300/dummyspichip.c b/arch/arm/mach-u300/dummyspichip.c
index 2785cb67b5e8..ec0283cf9a32 100644
--- a/arch/arm/mach-u300/dummyspichip.c
+++ b/arch/arm/mach-u300/dummyspichip.c
@@ -263,28 +263,22 @@ static int pl022_dummy_remove(struct spi_device *spi)
        return 0;
 }
+static const struct of_device_id pl022_dummy_dt_match[] = {
+        { .compatible = "arm,pl022-dummy" },
+        {},
+};
 static struct spi_driver pl022_dummy_driver = {
        .driver = {
                .name   = "spi-dummy",
                .owner  = THIS_MODULE,
+                .of_match_table = pl022_dummy_dt_match,
        },
        .probe  = pl022_dummy_probe,
        .remove = pl022_dummy_remove,
 };
-static int __init pl022_init_dummy(void)
+module_spi_driver(pl022_dummy_driver);
-{
-        return spi_register_driver(&pl022_dummy_driver);
-}
-static void __exit pl022_exit_dummy(void)
-{
-        spi_unregister_driver(&pl022_dummy_driver);
-}
-module_init(pl022_init_dummy);
-module_exit(pl022_exit_dummy);
 MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
 MODULE_DESCRIPTION("PL022 SSP/SPI DUMMY Linux driver");
 MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-u300/i2c.c b/arch/arm/mach-u300/i2c.c
deleted file mode 100644
index 96800aa1316d..000000000000
--- a/arch/arm/mach-u300/i2c.c
+++ /dev/null
@@ -1,285 +0,0 @@
-/*
- * arch/arm/mach-u300/i2c.c
- *
- * Copyright (C) 2009-2012 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- *
- * Register board i2c devices
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-#include <linux/kernel.h>
-#include <linux/i2c.h>
-#include <linux/mfd/ab3100.h>
-#include <linux/regulator/machine.h>
-#include <linux/amba/bus.h>
-#include <mach/irqs.h>
-/*
- * Initial settings of ab3100 registers.
- * Common for below LDO regulator settings are that
- * bit 7-5 controls voltage. Bit 4 turns regulator ON(1) or OFF(0).
- * Bit 3-2 controls sleep enable and bit 1-0 controls sleep mode.
- */
-/* LDO_A 0x16: 2.75V, ON, SLEEP_A, SLEEP OFF GND */
-#define LDO_A_SETTING           0x16
-/* LDO_C 0x10: 2.65V, ON, SLEEP_A or B, SLEEP full power */
-#define LDO_C_SETTING           0x10
-/* LDO_D 0x10: 2.65V, ON, sleep mode not used */
-#define LDO_D_SETTING           0x10
-/* LDO_E 0x10: 1.8V, ON, SLEEP_A or B, SLEEP full power */
-#define LDO_E_SETTING           0x10
-/* LDO_E SLEEP 0x00: 1.8V, not used, SLEEP_A or B, not used */
-#define LDO_E_SLEEP_SETTING     0x00
-/* LDO_F 0xD0: 2.5V, ON, SLEEP_A or B, SLEEP full power */
-#define LDO_F_SETTING           0xD0
-/* LDO_G 0x00: 2.85V, OFF, SLEEP_A or B, SLEEP full power */
-#define LDO_G_SETTING           0x00
-/* LDO_H 0x18: 2.75V, ON, SLEEP_B, SLEEP full power */
-#define LDO_H_SETTING           0x18
-/* LDO_K 0x00: 2.75V, OFF, SLEEP_A or B, SLEEP full power */
-#define LDO_K_SETTING           0x00
-/* LDO_EXT 0x00: Voltage not set, OFF, not used, not used */
-#define LDO_EXT_SETTING         0x00
-/* BUCK 0x7D: 1.2V, ON, SLEEP_A and B, SLEEP low power */
-#define BUCK_SETTING    0x7D
-/* BUCK SLEEP 0xAC: 1.05V, Not used, SLEEP_A and B, Not used */
-#define BUCK_SLEEP_SETTING      0xAC
-#ifdef CONFIG_AB3100_CORE
-static struct regulator_consumer_supply supply_ldo_c[] = {
-        {
-                .dev_name = "ab3100-codec",
-                .supply = "vaudio", /* Powers the codec */
-        },
-};
-/*
- * This one needs to be a supply so we can turn it off
- * in order to shut down the system.
- */
-static struct regulator_consumer_supply supply_ldo_d[] = {
-        {
-                .supply = "vana15", /* Powers the SoC (CPU etc) */
-        },
-};
-static struct regulator_consumer_supply supply_ldo_g[] = {
-        {
-                .dev_name = "mmci",
-                .supply = "vmmc", /* Powers MMC/SD card */
-        },
-};
-static struct regulator_consumer_supply supply_ldo_h[] = {
-        {
-                .dev_name = "xgam_pdi",
-                .supply = "vdisp", /* Powers camera, display etc */
-        },
-};
-static struct regulator_consumer_supply supply_ldo_k[] = {
-        {
-                .dev_name = "irda",
-                .supply = "vir", /* Power IrDA */
-        },
-};
-/*
- * This is a placeholder for whoever wish to use the
- * external power.
- */
-static struct regulator_consumer_supply supply_ldo_ext[] = {
-        {
-                .supply = "vext", /* External power */
-        },
-};
-/* Preset (hardware defined) voltages for these regulators */
-#define LDO_A_VOLTAGE 2750000
-#define LDO_C_VOLTAGE 2650000
-#define LDO_D_VOLTAGE 2650000
-static struct ab3100_platform_data ab3100_plf_data = {
-        .reg_constraints = {
-                /* LDO A routing and constraints */
-                {
-                        .constraints = {
-                                .name = "vrad",
-                                .min_uV = LDO_A_VOLTAGE,
-                                .max_uV = LDO_A_VOLTAGE,
-                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                                .always_on = 1,
-                                .boot_on = 1,
-                        },
-                },
-                /* LDO C routing and constraints */
-                {
-                        .constraints = {
-                                .min_uV = LDO_C_VOLTAGE,
-                                .max_uV = LDO_C_VOLTAGE,
-                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                        },
-                        .num_consumer_supplies = ARRAY_SIZE(supply_ldo_c),
-                        .consumer_supplies = supply_ldo_c,
-                },
-                /* LDO D routing and constraints */
-                {
-                        .constraints = {
-                                .min_uV = LDO_D_VOLTAGE,
-                                .max_uV = LDO_D_VOLTAGE,
-                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                                /*
-                                 * Actually this is boot_on but we need
-                                 * to reference count it externally to
-                                 * be able to shut down the system.
-                                 */
-                        },
-                        .num_consumer_supplies = ARRAY_SIZE(supply_ldo_d),
-                        .consumer_supplies = supply_ldo_d,
-                },
-                /* LDO E routing and constraints */
-                {
-                        .constraints = {
-                                .name = "vio",
-                                .min_uV = 1800000,
-                                .max_uV = 1800000,
-                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                                .always_on = 1,
-                                .boot_on = 1,
-                        },
-                },
-                /* LDO F routing and constraints */
-                {
-                        .constraints = {
-                                .name = "vana25",
-                                .min_uV = 2500000,
-                                .max_uV = 2500000,
-                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                                .always_on = 1,
-                                .boot_on = 1,
-                        },
-                },
-                /* LDO G routing and constraints */
-                {
-                        .constraints = {
-                                .min_uV = 1500000,
-                                .max_uV = 2850000,
-                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                                .valid_ops_mask =
-                                REGULATOR_CHANGE_VOLTAGE |
-                                REGULATOR_CHANGE_STATUS,
-                        },
-                        .num_consumer_supplies = ARRAY_SIZE(supply_ldo_g),
-                        .consumer_supplies = supply_ldo_g,
-                },
-                /* LDO H routing and constraints */
-                {
-                        .constraints = {
-                                .min_uV = 1200000,
-                                .max_uV = 2750000,
-                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                                .valid_ops_mask =
-                                REGULATOR_CHANGE_VOLTAGE |
-                                REGULATOR_CHANGE_STATUS,
-                        },
-                        .num_consumer_supplies = ARRAY_SIZE(supply_ldo_h),
-                        .consumer_supplies = supply_ldo_h,
-                },
-                /* LDO K routing and constraints */
-                {
-                        .constraints = {
-                                .min_uV = 1800000,
-                                .max_uV = 2750000,
-                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                                .valid_ops_mask =
-                                REGULATOR_CHANGE_VOLTAGE |
-                                REGULATOR_CHANGE_STATUS,
-                        },
-                        .num_consumer_supplies = ARRAY_SIZE(supply_ldo_k),
-                        .consumer_supplies = supply_ldo_k,
-                },
-                /* External regulator interface. No fixed voltage specified.
-                 * If we knew the voltage of the external regulator and it
-                 * was connected on the board, we could add the (fixed)
-                 * voltage for it here.
-                 */
-                {
-                        .constraints = {
-                                .min_uV = 0,
-                                .max_uV = 0,
-                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                                .valid_ops_mask =
-                                REGULATOR_CHANGE_STATUS,
-                        },
-                        .num_consumer_supplies = ARRAY_SIZE(supply_ldo_ext),
-                        .consumer_supplies = supply_ldo_ext,
-                },
-                /* Buck converter routing and constraints */
-                {
-                        .constraints = {
-                                .name = "vcore",
-                                .min_uV = 1200000,
-                                .max_uV = 1800000,
-                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                                .valid_ops_mask =
-                                REGULATOR_CHANGE_VOLTAGE,
-                                .always_on = 1,
-                                .boot_on = 1,
-                        },
-                },
-        },
-        .reg_initvals = {
-                LDO_A_SETTING,
-                LDO_C_SETTING,
-                LDO_E_SETTING,
-                LDO_E_SLEEP_SETTING,
-                LDO_F_SETTING,
-                LDO_G_SETTING,
-                LDO_H_SETTING,
-                LDO_K_SETTING,
-                LDO_EXT_SETTING,
-                BUCK_SETTING,
-                BUCK_SLEEP_SETTING,
-                LDO_D_SETTING,
-        },
-};
-#endif
-static struct i2c_board_info __initdata bus0_i2c_board_info[] = {
-#ifdef CONFIG_AB3100_CORE
-        {
-                .type = "ab3100",
-                .addr = 0x48,
-                .irq = IRQ_U300_IRQ0_EXT,
-                .platform_data = &ab3100_plf_data,
-        },
-#else
-        { },
-#endif
-};
-static struct i2c_board_info __initdata bus1_i2c_board_info[] = {
-        {
-                .type = "fwcam",
-                .addr = 0x10,
-        },
-        {
-                .type = "fwcam",
-                .addr = 0x5d,
-        },
-};
-void __init u300_i2c_register_board_devices(void)
-{
-        i2c_register_board_info(0, bus0_i2c_board_info,
-                                ARRAY_SIZE(bus0_i2c_board_info));
-        /*
-         * This makes the core shut down all unused regulators
-         * after all the initcalls have completed.
-         */
-        regulator_has_full_constraints();
-        i2c_register_board_info(1, bus1_i2c_board_info,
-                                ARRAY_SIZE(bus1_i2c_board_info));
-}
diff --git a/arch/arm/mach-u300/i2c.h b/arch/arm/mach-u300/i2c.h
deleted file mode 100644
index 485c02e5c06d..000000000000
--- a/arch/arm/mach-u300/i2c.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * arch/arm/mach-u300/i2c.h
- *
- * Copyright (C) 2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- *
- * Register board i2c devices
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-#ifndef MACH_U300_I2C_H
-#define MACH_U300_I2C_H
-#ifdef CONFIG_I2C_STU300
-void __init u300_i2c_register_board_devices(void);
-#else
-/* Compile out this stuff if no I2C adapter is available */
-static inline void __init u300_i2c_register_board_devices(void)
-{
-}
-#endif
-#endif
diff --git a/arch/arm/mach-u300/include/mach/hardware.h b/arch/arm/mach-u300/include/mach/hardware.h
deleted file mode 100644
index b99d4ce0ac2b..000000000000
--- a/arch/arm/mach-u300/include/mach/hardware.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-u300/include/mach/hardware.h
- */
-#include <asm/sizes.h>
-#include <mach/u300-regs.h>
diff --git a/arch/arm/mach-u300/include/mach/irqs.h b/arch/arm/mach-u300/include/mach/irqs.h
deleted file mode 100644
index 21d5e76a6cd3..000000000000
--- a/arch/arm/mach-u300/include/mach/irqs.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/irqs.h
- *
- *
- * Copyright (C) 2006-2012 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * IRQ channel definitions for the U300 platforms.
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-#ifndef __MACH_IRQS_H
-#define __MACH_IRQS_H
-#define IRQ_U300_INTCON0_START          32
-#define IRQ_U300_INTCON1_START          64
-/* These are on INTCON0 - 30 lines */
-#define IRQ_U300_IRQ0_EXT               32
-#define IRQ_U300_IRQ1_EXT               33
-#define IRQ_U300_DMA                    34
-#define IRQ_U300_VIDEO_ENC_0            35
-#define IRQ_U300_VIDEO_ENC_1            36
-#define IRQ_U300_AAIF_RX                37
-#define IRQ_U300_AAIF_TX                38
-#define IRQ_U300_AAIF_VGPIO             39
-#define IRQ_U300_AAIF_WAKEUP            40
-#define IRQ_U300_PCM_I2S0_FRAME         41
-#define IRQ_U300_PCM_I2S0_FIFO          42
-#define IRQ_U300_PCM_I2S1_FRAME         43
-#define IRQ_U300_PCM_I2S1_FIFO          44
-#define IRQ_U300_XGAM_GAMCON            45
-#define IRQ_U300_XGAM_CDI               46
-#define IRQ_U300_XGAM_CDICON            47
-#define IRQ_U300_XGAM_PDI               49
-#define IRQ_U300_XGAM_PDICON            50
-#define IRQ_U300_XGAM_GAMEACC           51
-#define IRQ_U300_XGAM_MCIDCT            52
-#define IRQ_U300_APEX                   53
-#define IRQ_U300_UART0                  54
-#define IRQ_U300_SPI                    55
-#define IRQ_U300_TIMER_APP_OS           56
-#define IRQ_U300_TIMER_APP_DD           57
-#define IRQ_U300_TIMER_APP_GP1          58
-#define IRQ_U300_TIMER_APP_GP2          59
-#define IRQ_U300_TIMER_OS               60
-#define IRQ_U300_TIMER_MS               61
-#define IRQ_U300_KEYPAD_KEYBF           62
-#define IRQ_U300_KEYPAD_KEYBR           63
-/* These are on INTCON1 - 32 lines */
-#define IRQ_U300_GPIO_PORT0             64
-#define IRQ_U300_GPIO_PORT1             65
-#define IRQ_U300_GPIO_PORT2             66
-/* These are for DB3150, DB3200 and DB3350 */
-#define IRQ_U300_WDOG                   67
-#define IRQ_U300_EVHIST                 68
-#define IRQ_U300_MSPRO                  69
-#define IRQ_U300_MMCSD_MCIINTR0         70
-#define IRQ_U300_MMCSD_MCIINTR1         71
-#define IRQ_U300_I2C0                   72
-#define IRQ_U300_I2C1                   73
-#define IRQ_U300_RTC                    74
-#define IRQ_U300_NFIF                   75
-#define IRQ_U300_NFIF2                  76
-/* The DB3350-specific interrupt lines */
-#define IRQ_U300_ISP_F0                 77
-#define IRQ_U300_ISP_F1                 78
-#define IRQ_U300_ISP_F2                 79
-#define IRQ_U300_ISP_F3                 80
-#define IRQ_U300_ISP_F4                 81
-#define IRQ_U300_GPIO_PORT3             82
-#define IRQ_U300_SYSCON_PLL_LOCK        83
-#define IRQ_U300_UART1                  84
-#define IRQ_U300_GPIO_PORT4             85
-#define IRQ_U300_GPIO_PORT5             86
-#define IRQ_U300_GPIO_PORT6             87
-#define U300_VIC_IRQS_END               88
-#endif
diff --git a/arch/arm/mach-u300/include/mach/syscon.h b/arch/arm/mach-u300/include/mach/syscon.h
deleted file mode 100644
index 10bdd0be9774..000000000000
--- a/arch/arm/mach-u300/include/mach/syscon.h
+++ /dev/null
@@ -1,592 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/syscon.h
- *
- *
- * Copyright (C) 2008-2012 ST-Ericsson AB
- *
- * Author: Rickard Andersson <rickard.andersson@stericsson.com>
- */
-#ifndef __MACH_SYSCON_H
-#define __MACH_SYSCON_H
-/*
- * All register defines for SYSCON registers that concerns individual
- * block clocks and reset lines are registered here. This is because
- * we don't want any other file to try to fool around with this stuff.
- */
-/* APP side SYSCON registers */
-/* TODO: this is incomplete. Add all from asic_syscon_map.h eventually. */
-/* CLK Control Register 16bit (R/W) */
-#define U300_SYSCON_CCR                                         (0x0000)
-#define U300_SYSCON_CCR_I2S1_USE_VCXO                           (0x0040)
-#define U300_SYSCON_CCR_I2S0_USE_VCXO                           (0x0020)
-#define U300_SYSCON_CCR_TURN_VCXO_ON                            (0x0008)
-#define U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK                 (0x0007)
-#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER            (0x04)
-#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW                  (0x03)
-#define U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE         (0x02)
-#define U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH                 (0x01)
-#define U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST                 (0x00)
-/* CLK Status Register 16bit (R/W) */
-#define U300_SYSCON_CSR                                         (0x0004)
-#define U300_SYSCON_CSR_PLL208_LOCK_IND                         (0x0002)
-#define U300_SYSCON_CSR_PLL13_LOCK_IND                          (0x0001)
-/* Reset lines for SLOW devices 16bit (R/W) */
-#define U300_SYSCON_RSR                                         (0x0014)
-#define U300_SYSCON_RSR_PPM_RESET_EN                            (0x0200)
-#define U300_SYSCON_RSR_ACC_TMR_RESET_EN                        (0x0100)
-#define U300_SYSCON_RSR_APP_TMR_RESET_EN                        (0x0080)
-#define U300_SYSCON_RSR_RTC_RESET_EN                            (0x0040)
-#define U300_SYSCON_RSR_KEYPAD_RESET_EN                         (0x0020)
-#define U300_SYSCON_RSR_GPIO_RESET_EN                           (0x0010)
-#define U300_SYSCON_RSR_EH_RESET_EN                             (0x0008)
-#define U300_SYSCON_RSR_BTR_RESET_EN                            (0x0004)
-#define U300_SYSCON_RSR_UART_RESET_EN                           (0x0002)
-#define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN                    (0x0001)
-/* Reset lines for FAST devices 16bit (R/W) */
-#define U300_SYSCON_RFR                                         (0x0018)
-#define U300_SYSCON_RFR_UART1_RESET_ENABLE                      (0x0080)
-#define U300_SYSCON_RFR_SPI_RESET_ENABLE                        (0x0040)
-#define U300_SYSCON_RFR_MMC_RESET_ENABLE                        (0x0020)
-#define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE                   (0x0010)
-#define U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE                   (0x0008)
-#define U300_SYSCON_RFR_I2C1_RESET_ENABLE                       (0x0004)
-#define U300_SYSCON_RFR_I2C0_RESET_ENABLE                       (0x0002)
-#define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE                (0x0001)
-/* Reset lines for the rest of the peripherals 16bit (R/W) */
-#define U300_SYSCON_RRR                                         (0x001c)
-#define U300_SYSCON_RRR_CDS_RESET_EN                            (0x4000)
-#define U300_SYSCON_RRR_ISP_RESET_EN                            (0x2000)
-#define U300_SYSCON_RRR_INTCON_RESET_EN                         (0x1000)
-#define U300_SYSCON_RRR_MSPRO_RESET_EN                          (0x0800)
-#define U300_SYSCON_RRR_XGAM_RESET_EN                           (0x0100)
-#define U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN                   (0x0080)
-#define U300_SYSCON_RRR_NANDIF_RESET_EN                         (0x0040)
-#define U300_SYSCON_RRR_EMIF_RESET_EN                           (0x0020)
-#define U300_SYSCON_RRR_DMAC_RESET_EN                           (0x0010)
-#define U300_SYSCON_RRR_CPU_RESET_EN                            (0x0008)
-#define U300_SYSCON_RRR_APEX_RESET_EN                           (0x0004)
-#define U300_SYSCON_RRR_AHB_RESET_EN                            (0x0002)
-#define U300_SYSCON_RRR_AAIF_RESET_EN                           (0x0001)
-/* Clock enable for SLOW peripherals 16bit (R/W) */
-#define U300_SYSCON_CESR                                        (0x0020)
-#define U300_SYSCON_CESR_PPM_CLK_EN                             (0x0200)
-#define U300_SYSCON_CESR_ACC_TMR_CLK_EN                         (0x0100)
-#define U300_SYSCON_CESR_APP_TMR_CLK_EN                         (0x0080)
-#define U300_SYSCON_CESR_KEYPAD_CLK_EN                          (0x0040)
-#define U300_SYSCON_CESR_GPIO_CLK_EN                            (0x0010)
-#define U300_SYSCON_CESR_EH_CLK_EN                              (0x0008)
-#define U300_SYSCON_CESR_BTR_CLK_EN                             (0x0004)
-#define U300_SYSCON_CESR_UART_CLK_EN                            (0x0002)
-#define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN                     (0x0001)
-/* Clock enable for FAST peripherals 16bit (R/W) */
-#define U300_SYSCON_CEFR                                        (0x0024)
-#define U300_SYSCON_CEFR_UART1_CLK_EN                           (0x0200)
-#define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN                       (0x0100)
-#define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN                       (0x0080)
-#define U300_SYSCON_CEFR_SPI_CLK_EN                             (0x0040)
-#define U300_SYSCON_CEFR_MMC_CLK_EN                             (0x0020)
-#define U300_SYSCON_CEFR_I2S1_CLK_EN                            (0x0010)
-#define U300_SYSCON_CEFR_I2S0_CLK_EN                            (0x0008)
-#define U300_SYSCON_CEFR_I2C1_CLK_EN                            (0x0004)
-#define U300_SYSCON_CEFR_I2C0_CLK_EN                            (0x0002)
-#define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN                     (0x0001)
-/* Clock enable for the rest of the peripherals 16bit (R/W) */
-#define U300_SYSCON_CERR                                        (0x0028)
-#define U300_SYSCON_CERR_CDS_CLK_EN                             (0x2000)
-#define U300_SYSCON_CERR_ISP_CLK_EN                             (0x1000)
-#define U300_SYSCON_CERR_MSPRO_CLK_EN                           (0x0800)
-#define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN               (0x0400)
-#define U300_SYSCON_CERR_SEMI_CLK_EN                            (0x0200)
-#define U300_SYSCON_CERR_XGAM_CLK_EN                            (0x0100)
-#define U300_SYSCON_CERR_VIDEO_ENC_CLK_EN                       (0x0080)
-#define U300_SYSCON_CERR_NANDIF_CLK_EN                          (0x0040)
-#define U300_SYSCON_CERR_EMIF_CLK_EN                            (0x0020)
-#define U300_SYSCON_CERR_DMAC_CLK_EN                            (0x0010)
-#define U300_SYSCON_CERR_CPU_CLK_EN                             (0x0008)
-#define U300_SYSCON_CERR_APEX_CLK_EN                            (0x0004)
-#define U300_SYSCON_CERR_AHB_CLK_EN                             (0x0002)
-#define U300_SYSCON_CERR_AAIF_CLK_EN                            (0x0001)
-/* Single block clock enable 16bit (-/W) */
-#define U300_SYSCON_SBCER                                       (0x002c)
-#define U300_SYSCON_SBCER_PPM_CLK_EN                            (0x0009)
-#define U300_SYSCON_SBCER_ACC_TMR_CLK_EN                        (0x0008)
-#define U300_SYSCON_SBCER_APP_TMR_CLK_EN                        (0x0007)
-#define U300_SYSCON_SBCER_KEYPAD_CLK_EN                         (0x0006)
-#define U300_SYSCON_SBCER_GPIO_CLK_EN                           (0x0004)
-#define U300_SYSCON_SBCER_EH_CLK_EN                             (0x0003)
-#define U300_SYSCON_SBCER_BTR_CLK_EN                            (0x0002)
-#define U300_SYSCON_SBCER_UART_CLK_EN                           (0x0001)
-#define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN                    (0x0000)
-#define U300_SYSCON_SBCER_UART1_CLK_EN                          (0x0019)
-#define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN                      (0x0018)
-#define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN                      (0x0017)
-#define U300_SYSCON_SBCER_SPI_CLK_EN                            (0x0016)
-#define U300_SYSCON_SBCER_MMC_CLK_EN                            (0x0015)
-#define U300_SYSCON_SBCER_I2S1_CLK_EN                           (0x0014)
-#define U300_SYSCON_SBCER_I2S0_CLK_EN                           (0x0013)
-#define U300_SYSCON_SBCER_I2C1_CLK_EN                           (0x0012)
-#define U300_SYSCON_SBCER_I2C0_CLK_EN                           (0x0011)
-#define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN                    (0x0010)
-#define U300_SYSCON_SBCER_CDS_CLK_EN                            (0x002D)
-#define U300_SYSCON_SBCER_ISP_CLK_EN                            (0x002C)
-#define U300_SYSCON_SBCER_MSPRO_CLK_EN                          (0x002B)
-#define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN              (0x002A)
-#define U300_SYSCON_SBCER_SEMI_CLK_EN                           (0x0029)
-#define U300_SYSCON_SBCER_XGAM_CLK_EN                           (0x0028)
-#define U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN                      (0x0027)
-#define U300_SYSCON_SBCER_NANDIF_CLK_EN                         (0x0026)
-#define U300_SYSCON_SBCER_EMIF_CLK_EN                           (0x0025)
-#define U300_SYSCON_SBCER_DMAC_CLK_EN                           (0x0024)
-#define U300_SYSCON_SBCER_CPU_CLK_EN                            (0x0023)
-#define U300_SYSCON_SBCER_APEX_CLK_EN                           (0x0022)
-#define U300_SYSCON_SBCER_AHB_CLK_EN                            (0x0021)
-#define U300_SYSCON_SBCER_AAIF_CLK_EN                           (0x0020)
-/* Single block clock disable 16bit (-/W) */
-#define U300_SYSCON_SBCDR                                       (0x0030)
-/* Same values as above for SBCER */
-/* Clock force SLOW peripherals 16bit (R/W) */
-#define U300_SYSCON_CFSR                                        (0x003c)
-#define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN                       (0x0200)
-#define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN                   (0x0100)
-#define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN                   (0x0080)
-#define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN                    (0x0020)
-#define U300_SYSCON_CFSR_GPIO_CLK_FORCE_EN                      (0x0010)
-#define U300_SYSCON_CFSR_EH_CLK_FORCE_EN                        (0x0008)
-#define U300_SYSCON_CFSR_BTR_CLK_FORCE_EN                       (0x0004)
-#define U300_SYSCON_CFSR_UART_CLK_FORCE_EN                      (0x0002)
-#define U300_SYSCON_CFSR_SLOW_BRIDGE_CLK_FORCE_EN               (0x0001)
-/* Clock force FAST peripherals 16bit (R/W) */
-#define U300_SYSCON_CFFR                                        (0x40)
-/* Values not defined. Define if you want to use them. */
-/* Clock force the rest of the peripherals 16bit (R/W) */
-#define U300_SYSCON_CFRR                                        (0x44)
-#define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN                       (0x2000)
-#define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN                       (0x1000)
-#define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN                     (0x0800)
-#define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN         (0x0400)
-#define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN                      (0x0200)
-#define U300_SYSCON_CFRR_XGAM_CLK_FORCE_EN                      (0x0100)
-#define U300_SYSCON_CFRR_VIDEO_ENC_CLK_FORCE_EN                 (0x0080)
-#define U300_SYSCON_CFRR_NANDIF_CLK_FORCE_EN                    (0x0040)
-#define U300_SYSCON_CFRR_EMIF_CLK_FORCE_EN                      (0x0020)
-#define U300_SYSCON_CFRR_DMAC_CLK_FORCE_EN                      (0x0010)
-#define U300_SYSCON_CFRR_CPU_CLK_FORCE_EN                       (0x0008)
-#define U300_SYSCON_CFRR_APEX_CLK_FORCE_EN                      (0x0004)
-#define U300_SYSCON_CFRR_AHB_CLK_FORCE_EN                       (0x0002)
-#define U300_SYSCON_CFRR_AAIF_CLK_FORCE_EN                      (0x0001)
-/* PLL208 Frequency Control 16bit (R/W) */
-#define U300_SYSCON_PFCR                                        (0x48)
-#define U300_SYSCON_PFCR_DPLL_MULT_NUM                          (0x000F)
-/* Power Management Control 16bit (R/W) */
-#define U300_SYSCON_PMCR                                        (0x50)
-#define U300_SYSCON_PMCR_DCON_ENABLE                            (0x0002)
-#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE                        (0x0001)
-/*
- * All other clocking registers moved to clock.c!
- */
-/* Reset Out 16bit (R/W) */
-#define U300_SYSCON_RCR                                         (0x6c)
-#define U300_SYSCON_RCR_RESOUT0_RST_N_DISABLE                   (0x0001)
-/* EMIF Slew Rate Control 16bit (R/W) */
-#define U300_SYSCON_SRCLR                                       (0x70)
-#define U300_SYSCON_SRCLR_MASK                                  (0x03FF)
-#define U300_SYSCON_SRCLR_VALUE                                 (0x03FF)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_B                       (0x0200)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_A                       (0x0100)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_B                       (0x0080)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_A                       (0x0040)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_B                       (0x0020)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_A                       (0x0010)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_B                       (0x0008)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_A                       (0x0004)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_B                       (0x0002)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_A                       (0x0001)
-/* EMIF Clock Control Register 16bit (R/W) */
-#define U300_SYSCON_ECCR                                        (0x0078)
-#define U300_SYSCON_ECCR_MASK                                   (0x000F)
-#define U300_SYSCON_ECCR_EMIF_1_STATIC_CLK_EN_N_DISABLE         (0x0008)
-#define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE        (0x0004)
-#define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE           (0x0002)
-#define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE           (0x0001)
-/* Step one for killing the applications system 16bit (-/W) */
-#define U300_SYSCON_KA1R                                        (0x0080)
-#define U300_SYSCON_KA1R_MASK                                   (0xFFFF)
-#define U300_SYSCON_KA1R_VALUE                                  (0xFFFF)
-/* Step two for killing the application system 16bit (-/W) */
-#define U300_SYSCON_KA2R                                        (0x0084)
-#define U300_SYSCON_KA2R_MASK                                   (0xFFFF)
-#define U300_SYSCON_KA2R_VALUE                                  (0xFFFF)
-/* MMC/MSPRO frequency divider register 0 16bit (R/W) */
-#define U300_SYSCON_MMF0R                                       (0x90)
-#define U300_SYSCON_MMF0R_MASK                                  (0x00FF)
-#define U300_SYSCON_MMF0R_FREQ_0_HIGH_MASK                      (0x00F0)
-#define U300_SYSCON_MMF0R_FREQ_0_LOW_MASK                       (0x000F)
-/* MMC/MSPRO frequency divider register 1 16bit (R/W) */
-#define U300_SYSCON_MMF1R                                       (0x94)
-#define U300_SYSCON_MMF1R_MASK                                  (0x00FF)
-#define U300_SYSCON_MMF1R_FREQ_1_HIGH_MASK                      (0x00F0)
-#define U300_SYSCON_MMF1R_FREQ_1_LOW_MASK                       (0x000F)
-/* AAIF control register 16 bit (R/W) */
-#define U300_SYSCON_AAIFCR                                      (0x98)
-#define U300_SYSCON_AAIFCR_MASK                                 (0x0003)
-#define U300_SYSCON_AAIFCR_AASW_CTRL_MASK                       (0x0003)
-#define U300_SYSCON_AAIFCR_AASW_CTRL_FUNCTIONAL                 (0x0000)
-#define U300_SYSCON_AAIFCR_AASW_CTRL_MONITORING                 (0x0001)
-#define U300_SYSCON_AAIFCR_AASW_CTRL_ACC_TO_EXT                 (0x0002)
-#define U300_SYSCON_AAIFCR_AASW_CTRL_APP_TO_EXT                 (0x0003)
-/* Clock control for the MMC and MSPRO blocks 16bit (R/W) */
-#define U300_SYSCON_MMCR                                        (0x9C)
-#define U300_SYSCON_MMCR_MASK                                   (0x0003)
-#define U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE                  (0x0002)
-#define U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE                   (0x0001)
-/* Pull up/down control (R/W) */
-#define U300_SYSCON_PUCR                                        (0x104)
-#define U300_SYSCON_PUCR_EMIF_1_WAIT_N_PU_ENABLE                (0x0200)
-#define U300_SYSCON_PUCR_EMIF_1_NFIF_READY_PU_ENABLE            (0x0100)
-#define U300_SYSCON_PUCR_EMIF_1_16BIT_PU_ENABLE                 (0x0080)
-#define U300_SYSCON_PUCR_EMIF_1_8BIT_PU_ENABLE                  (0x0040)
-#define U300_SYSCON_PUCR_KEY_IN_PU_EN_MASK                      (0x003F)
-/* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */
-#define U300_SYSCON_S0CCR                                       (0x120)
-#define U300_SYSCON_S0CCR_FIELD_MASK                            (0x43FF)
-#define U300_SYSCON_S0CCR_CLOCK_REQ                             (0x4000)
-#define U300_SYSCON_S0CCR_CLOCK_REQ_MONITOR                     (0x2000)
-#define U300_SYSCON_S0CCR_CLOCK_INV                             (0x0200)
-#define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK                       (0x01E0)
-#define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK                     (0x001E)
-#define U300_SYSCON_S0CCR_CLOCK_ENABLE                          (0x0001)
-#define U300_SYSCON_S0CCR_SEL_MCLK                              (0x8<<1)
-#define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK                       (0xA<<1)
-#define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK                      (0xC<<1)
-#define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK                      (0xD<<1)
-#define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK                    (0xE<<1)
-#define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK                     (0x0<<1)
-#define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK                       (0x2<<1)
-#define U300_SYSCON_S0CCR_SEL_RTC_CLK                           (0x4<<1)
-#define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK                    (0x6<<1)
-/* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */
-#define U300_SYSCON_S1CCR                                       (0x124)
-#define U300_SYSCON_S1CCR_FIELD_MASK                            (0x43FF)
-#define U300_SYSCON_S1CCR_CLOCK_REQ                             (0x4000)
-#define U300_SYSCON_S1CCR_CLOCK_REQ_MONITOR                     (0x2000)
-#define U300_SYSCON_S1CCR_CLOCK_INV                             (0x0200)
-#define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK                       (0x01E0)
-#define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK                     (0x001E)
-#define U300_SYSCON_S1CCR_CLOCK_ENABLE                          (0x0001)
-#define U300_SYSCON_S1CCR_SEL_MCLK                              (0x8<<1)
-#define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK                       (0xA<<1)
-#define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK                      (0xC<<1)
-#define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK                      (0xD<<1)
-#define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK                    (0xE<<1)
-#define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK                     (0x0<<1)
-#define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK                       (0x2<<1)
-#define U300_SYSCON_S1CCR_SEL_RTC_CLK                           (0x4<<1)
-#define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK                    (0x6<<1)
-/* SYS_2_CLK_CONTROL third clock contol 16 bit (R/W) */
-#define U300_SYSCON_S2CCR                                       (0x128)
-#define U300_SYSCON_S2CCR_FIELD_MASK                            (0xC3FF)
-#define U300_SYSCON_S2CCR_CLK_STEAL                             (0x8000)
-#define U300_SYSCON_S2CCR_CLOCK_REQ                             (0x4000)
-#define U300_SYSCON_S2CCR_CLOCK_REQ_MONITOR                     (0x2000)
-#define U300_SYSCON_S2CCR_CLOCK_INV                             (0x0200)
-#define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK                       (0x01E0)
-#define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK                     (0x001E)
-#define U300_SYSCON_S2CCR_CLOCK_ENABLE                          (0x0001)
-#define U300_SYSCON_S2CCR_SEL_MCLK                              (0x8<<1)
-#define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK                       (0xA<<1)
-#define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK                      (0xC<<1)
-#define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK                      (0xD<<1)
-#define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK                    (0xE<<1)
-#define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK                     (0x0<<1)
-#define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK                       (0x2<<1)
-#define U300_SYSCON_S2CCR_SEL_RTC_CLK                           (0x4<<1)
-#define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK                    (0x6<<1)
-/* SYS_MISC_CONTROL, miscellaneous 16bit (R/W) */
-#define U300_SYSCON_MCR                                         (0x12c)
-#define U300_SYSCON_MCR_FIELD_MASK                              (0x00FF)
-#define U300_SYSCON_MCR_PMGEN_CR_4_MASK                         (0x00C0)
-#define U300_SYSCON_MCR_PMGEN_CR_4_GPIO                         (0x0000)
-#define U300_SYSCON_MCR_PMGEN_CR_4_SPI                          (0x0040)
-#define U300_SYSCON_MCR_PMGEN_CR_4_AAIF                         (0x00C0)
-#define U300_SYSCON_MCR_PMGEN_CR_2_MASK                         (0x0030)
-#define U300_SYSCON_MCR_PMGEN_CR_2_GPIO                         (0x0000)
-#define U300_SYSCON_MCR_PMGEN_CR_2_EMIF_1_STATIC                (0x0010)
-#define U300_SYSCON_MCR_PMGEN_CR_2_DSP                          (0x0020)
-#define U300_SYSCON_MCR_PMGEN_CR_2_AAIF                         (0x0030)
-#define U300_SYSCON_MCR_PMGEN_CR_0_MASK                         (0x000C)
-#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M1              (0x0000)
-#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M2              (0x0004)
-#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M3              (0x0008)
-#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_0_SDRAM                 (0x000C)
-#define U300_SYSCON_MCR_PM1G_MODE_ENABLE                        (0x0002)
-#define U300_SYSCON_MCR_PMTG5_MODE_ENABLE                       (0x0001)
-/* SC_PLL_IRQ_CONTROL 16bit (R/W) */
-#define U300_SYSCON_PICR                                        (0x0130)
-#define U300_SYSCON_PICR_MASK                                   (0x00FF)
-#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_LOW_ENABLE           (0x0080)
-#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_HIGH_ENABLE          (0x0040)
-#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_LOW_ENABLE            (0x0020)
-#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_HIGH_ENABLE           (0x0010)
-#define U300_SYSCON_PICR_IRQMASK_PLL13_UNLOCK_ENABLE            (0x0008)
-#define U300_SYSCON_PICR_IRQMASK_PLL13_LOCK_ENABLE              (0x0004)
-#define U300_SYSCON_PICR_IRQMASK_PLL208_UNLOCK_ENABLE           (0x0002)
-#define U300_SYSCON_PICR_IRQMASK_PLL208_LOCK_ENABLE             (0x0001)
-/* SC_PLL_IRQ_STATUS 16 bit (R/-) */
-#define U300_SYSCON_PISR                                        (0x0134)
-#define U300_SYSCON_PISR_MASK                                   (0x000F)
-#define U300_SYSCON_PISR_PLL13_UNLOCK_IND                       (0x0008)
-#define U300_SYSCON_PISR_PLL13_LOCK_IND                         (0x0004)
-#define U300_SYSCON_PISR_PLL208_UNLOCK_IND                      (0x0002)
-#define U300_SYSCON_PISR_PLL208_LOCK_IND                        (0x0001)
-/* SC_PLL_IRQ_CLEAR 16 bit (-/W) */
-#define U300_SYSCON_PICLR                                       (0x0138)
-#define U300_SYSCON_PICLR_MASK                                  (0x000F)
-#define U300_SYSCON_PICLR_RWMASK                                (0x0000)
-#define U300_SYSCON_PICLR_PLL13_UNLOCK_SC                       (0x0008)
-#define U300_SYSCON_PICLR_PLL13_LOCK_SC                         (0x0004)
-#define U300_SYSCON_PICLR_PLL208_UNLOCK_SC                      (0x0002)
-#define U300_SYSCON_PICLR_PLL208_LOCK_SC                        (0x0001)
-/* CAMIF_CONTROL 16 bit (-/W) */
-#define U300_SYSCON_CICR                                        (0x013C)
-#define U300_SYSCON_CICR_MASK                                   (0x0FFF)
-#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_MASK              (0x0F00)
-#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_PORT1             (0x0C00)
-#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_PORT0             (0x0300)
-#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_MASK                (0x00F0)
-#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_PORT1               (0x00C0)
-#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_PORT0               (0x0030)
-#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_MASK             (0x000F)
-#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_PORT1            (0x000C)
-#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_PORT0            (0x0003)
-/* Clock activity observability register 0 */
-#define U300_SYSCON_C0OAR                                       (0x140)
-#define U300_SYSCON_C0OAR_MASK                                  (0xFFFF)
-#define U300_SYSCON_C0OAR_VALUE                                 (0xFFFF)
-#define U300_SYSCON_C0OAR_BT_H_CLK                              (0x8000)
-#define U300_SYSCON_C0OAR_ASPB_P_CLK                            (0x4000)
-#define U300_SYSCON_C0OAR_APP_SEMI_H_CLK                        (0x2000)
-#define U300_SYSCON_C0OAR_APP_SEMI_CLK                          (0x1000)
-#define U300_SYSCON_C0OAR_APP_MMC_MSPRO_CLK                     (0x0800)
-#define U300_SYSCON_C0OAR_APP_I2S1_CLK                          (0x0400)
-#define U300_SYSCON_C0OAR_APP_I2S0_CLK                          (0x0200)
-#define U300_SYSCON_C0OAR_APP_CPU_CLK                           (0x0100)
-#define U300_SYSCON_C0OAR_APP_52_CLK                            (0x0080)
-#define U300_SYSCON_C0OAR_APP_208_CLK                           (0x0040)
-#define U300_SYSCON_C0OAR_APP_104_CLK                           (0x0020)
-#define U300_SYSCON_C0OAR_APEX_CLK                              (0x0010)
-#define U300_SYSCON_C0OAR_AHPB_M_H_CLK                          (0x0008)
-#define U300_SYSCON_C0OAR_AHB_CLK                               (0x0004)
-#define U300_SYSCON_C0OAR_AFPB_P_CLK                            (0x0002)
-#define U300_SYSCON_C0OAR_AAIF_CLK                              (0x0001)
-/* Clock activity observability register 1 */
-#define U300_SYSCON_C1OAR                                       (0x144)
-#define U300_SYSCON_C1OAR_MASK                                  (0x3FFE)
-#define U300_SYSCON_C1OAR_VALUE                                 (0x3FFE)
-#define U300_SYSCON_C1OAR_NFIF_F_CLK                            (0x2000)
-#define U300_SYSCON_C1OAR_MSPRO_CLK                             (0x1000)
-#define U300_SYSCON_C1OAR_MMC_P_CLK                             (0x0800)
-#define U300_SYSCON_C1OAR_MMC_CLK                               (0x0400)
-#define U300_SYSCON_C1OAR_KP_P_CLK                              (0x0200)
-#define U300_SYSCON_C1OAR_I2C1_P_CLK                            (0x0100)
-#define U300_SYSCON_C1OAR_I2C0_P_CLK                            (0x0080)
-#define U300_SYSCON_C1OAR_GPIO_CLK                              (0x0040)
-#define U300_SYSCON_C1OAR_EMIF_MPMC_CLK                         (0x0020)
-#define U300_SYSCON_C1OAR_EMIF_H_CLK                            (0x0010)
-#define U300_SYSCON_C1OAR_EVHIST_CLK                            (0x0008)
-#define U300_SYSCON_C1OAR_PPM_CLK                               (0x0004)
-#define U300_SYSCON_C1OAR_DMA_CLK                               (0x0002)
-/* Clock activity observability register 2 */
-#define U300_SYSCON_C2OAR                                       (0x148)
-#define U300_SYSCON_C2OAR_MASK                                  (0x0FFF)
-#define U300_SYSCON_C2OAR_VALUE                                 (0x0FFF)
-#define U300_SYSCON_C2OAR_XGAM_CDI_CLK                          (0x0800)
-#define U300_SYSCON_C2OAR_XGAM_CLK                              (0x0400)
-#define U300_SYSCON_C2OAR_VC_H_CLK                              (0x0200)
-#define U300_SYSCON_C2OAR_VC_CLK                                (0x0100)
-#define U300_SYSCON_C2OAR_UA_P_CLK                              (0x0080)
-#define U300_SYSCON_C2OAR_TMR1_CLK                              (0x0040)
-#define U300_SYSCON_C2OAR_TMR0_CLK                              (0x0020)
-#define U300_SYSCON_C2OAR_SPI_P_CLK                             (0x0010)
-#define U300_SYSCON_C2OAR_PCM_I2S1_CORE_CLK                     (0x0008)
-#define U300_SYSCON_C2OAR_PCM_I2S1_CLK                          (0x0004)
-#define U300_SYSCON_C2OAR_PCM_I2S0_CORE_CLK                     (0x0002)
-#define U300_SYSCON_C2OAR_PCM_I2S0_CLK                          (0x0001)
-/* Chip ID register 16bit (R/-) */
-#define U300_SYSCON_CIDR                                        (0x400)
-/* Video IRQ clear 16bit (R/W) */
-#define U300_SYSCON_VICR                                        (0x404)
-#define U300_SYSCON_VICR_VIDEO1_IRQ_CLEAR_ENABLE                (0x0002)
-#define U300_SYSCON_VICR_VIDEO0_IRQ_CLEAR_ENABLE                (0x0001)
-/* SMCR */
-#define U300_SYSCON_SMCR                                        (0x4d0)
-#define U300_SYSCON_SMCR_FIELD_MASK                             (0x000e)
-#define U300_SYSCON_SMCR_SEMI_SREFACK_IND                       (0x0008)
-#define U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE                    (0x0004)
-#define U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE              (0x0002)
-/* CPU_SW_DBGEN Software Debug Enable 16bit (R/W) */
-#define U300_SYSCON_CSDR                                        (0x4f0)
-#define U300_SYSCON_CSDR_SW_DEBUG_ENABLE                        (0x0001)
-/* PRINT_CONTROL Print Control 16bit (R/-) */
-#define U300_SYSCON_PCR                                         (0x4f8)
-#define U300_SYSCON_PCR_SERV_IND                                (0x0001)
-/* BOOT_CONTROL 16bit (R/-) */
-#define U300_SYSCON_BCR                                         (0x4fc)
-#define U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND              (0x0400)
-#define U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND              (0x0200)
-#define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK                  (0x01FC)
-#define U300_SYSCON_BCR_APP_BOOT_SERV_MASK                      (0x0003)
-/* CPU clock defines */
-/**
- * CPU high frequency in MHz
- */
-#define SYSCON_CPU_CLOCK_HIGH    208
-/**
- * CPU medium frequency in MHz
- */
-#define SYSCON_CPU_CLOCK_MEDIUM   52
-/**
- * CPU low frequency in MHz
- */
-#define SYSCON_CPU_CLOCK_LOW      13
-/* EMIF clock defines */
-/**
- * EMIF high frequency in MHz
- */
-#define SYSCON_EMIF_CLOCK_HIGH   104
-/**
- * EMIF medium frequency in MHz
- */
-#define SYSCON_EMIF_CLOCK_MEDIUM  52
-/**
- * EMIF low frequency in MHz
- */
-#define SYSCON_EMIF_CLOCK_LOW     13
-/* AHB clock defines */
-/**
- * AHB high frequency in MHz
- */
-#define SYSCON_AHB_CLOCK_HIGH     52
-/**
- * AHB medium frequency in MHz
- */
-#define SYSCON_AHB_CLOCK_MEDIUM   26
-/**
- * AHB low frequency in MHz
- */
-#define SYSCON_AHB_CLOCK_LOW       7  /* i.e 13/2=6.5MHz */
-enum syscon_busmaster {
-  SYSCON_BM_DMAC,
-  SYSCON_BM_XGAM,
-  SYSCON_BM_VIDEO_ENC
-};
-/* Selectr a resistor or a set of resistors */
-enum syscon_pull_up_down {
-  SYSCON_PU_KEY_IN_EN,
-  SYSCON_PU_EMIF_1_8_BIT_EN,
-  SYSCON_PU_EMIF_1_16_BIT_EN,
-  SYSCON_PU_EMIF_1_NFIF_READY_EN,
-  SYSCON_PU_EMIF_1_NFIF_WAIT_N_EN,
-};
-/*
- * Note that this array must match the order of the array "clk_reg"
- * in syscon.c
- */
-enum syscon_clk {
-  SYSCON_CLKCONTROL_SLOW_BRIDGE,
-  SYSCON_CLKCONTROL_UART,
-  SYSCON_CLKCONTROL_BTR,
-  SYSCON_CLKCONTROL_EH,
-  SYSCON_CLKCONTROL_GPIO,
-  SYSCON_CLKCONTROL_KEYPAD,
-  SYSCON_CLKCONTROL_APP_TIMER,
-  SYSCON_CLKCONTROL_ACC_TIMER,
-  SYSCON_CLKCONTROL_FAST_BRIDGE,
-  SYSCON_CLKCONTROL_I2C0,
-  SYSCON_CLKCONTROL_I2C1,
-  SYSCON_CLKCONTROL_I2S0,
-  SYSCON_CLKCONTROL_I2S1,
-  SYSCON_CLKCONTROL_MMC,
-  SYSCON_CLKCONTROL_SPI,
-  SYSCON_CLKCONTROL_I2S0_CORE,
-  SYSCON_CLKCONTROL_I2S1_CORE,
-  SYSCON_CLKCONTROL_UART1,
-  SYSCON_CLKCONTROL_AAIF,
-  SYSCON_CLKCONTROL_AHB,
-  SYSCON_CLKCONTROL_APEX,
-  SYSCON_CLKCONTROL_CPU,
-  SYSCON_CLKCONTROL_DMA,
-  SYSCON_CLKCONTROL_EMIF,
-  SYSCON_CLKCONTROL_NAND_IF,
-  SYSCON_CLKCONTROL_VIDEO_ENC,
-  SYSCON_CLKCONTROL_XGAM,
-  SYSCON_CLKCONTROL_SEMI,
-  SYSCON_CLKCONTROL_AHB_SUBSYS,
-  SYSCON_CLKCONTROL_MSPRO
-};
-enum syscon_sysclk_mode {
-  SYSCON_SYSCLK_DISABLED,
-  SYSCON_SYSCLK_M_CLK,
-  SYSCON_SYSCLK_ACC_FSM,
-  SYSCON_SYSCLK_PLL60_48,
-  SYSCON_SYSCLK_PLL60_60,
-  SYSCON_SYSCLK_ACC_PLL208,
-  SYSCON_SYSCLK_APP_PLL13,
-  SYSCON_SYSCLK_APP_FSM,
-  SYSCON_SYSCLK_RTC,
-  SYSCON_SYSCLK_APP_PLL208
-};
-enum syscon_sysclk_req {
-  SYSCON_SYSCLKREQ_DISABLED,
-  SYSCON_SYSCLKREQ_ACTIVE_LOW,
-  SYSCON_SYSCLKREQ_MONITOR
-};
-enum syscon_clk_mode {
-  SYSCON_CLKMODE_OFF,
-  SYSCON_CLKMODE_DEFAULT,
-  SYSCON_CLKMODE_LOW,
-  SYSCON_CLKMODE_MEDIUM,
-  SYSCON_CLKMODE_HIGH,
-  SYSCON_CLKMODE_PERMANENT,
-  SYSCON_CLKMODE_ON,
-};
-enum syscon_call_mode {
-  SYSCON_CLKCALL_NOWAIT,
-  SYSCON_CLKCALL_WAIT,
-};
-int syscon_dc_on(bool keep_power_on);
-int syscon_set_busmaster_active_state(enum syscon_busmaster busmaster,
-                                      bool active);
-bool syscon_get_busmaster_active_state(void);
-int syscon_set_sleep_mask(enum syscon_clk,
-                          bool sleep_ctrl);
-int syscon_config_sysclk(u32 sysclk,
-                         enum syscon_sysclk_mode sysclkmode,
-                         bool inverse,
-                         u32 divisor,
-                         enum syscon_sysclk_req sysclkreq);
-bool syscon_can_turn_off_semi_clock(void);
-/* This function is restricted to core.c */
-int syscon_request_normal_power(bool req);
-/* This function is restricted to be used by platform_speed.c */
-int syscon_speed_request(enum syscon_call_mode wait_mode,
-                         enum syscon_clk_mode req_clk_mode);
-#endif /* __MACH_SYSCON_H */
diff --git a/arch/arm/mach-u300/include/mach/timex.h b/arch/arm/mach-u300/include/mach/timex.h
deleted file mode 100644
index f233b72633f6..000000000000
--- a/arch/arm/mach-u300/include/mach/timex.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/timex.h
- *
- *
- * Copyright (C) 2006-2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * Platform tick rate definition.
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-#ifndef __MACH_TIMEX_H
-#define __MACH_TIMEX_H
-/* This is for the APP OS GP1 (General Purpose 1) timer */
-#define CLOCK_TICK_RATE         1000000
-#endif
diff --git a/arch/arm/mach-u300/include/mach/u300-regs.h b/arch/arm/mach-u300/include/mach/u300-regs.h
deleted file mode 100644
index 0320495efc4d..000000000000
--- a/arch/arm/mach-u300/include/mach/u300-regs.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/u300-regs.h
- *
- *
- * Copyright (C) 2006-2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * Basic register address definitions in physical memory and
- * some block definitions for core devices like the timer.
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-#ifndef __MACH_U300_REGS_H
-#define __MACH_U300_REGS_H
-/*
- * These are the large blocks of memory allocated for I/O.
- * the defines are used for setting up the I/O memory mapping.
- */
-/* NAND Flash CS0 */
-#define U300_NAND_CS0_PHYS_BASE         0x80000000
-/* NFIF */
-#define U300_NAND_IF_PHYS_BASE          0x9f800000
-/* ALE, CLE offset for FSMC NAND */
-#define PLAT_NAND_CLE                   (1 << 16)
-#define PLAT_NAND_ALE                   (1 << 17)
-/* AHB Peripherals */
-#define U300_AHB_PER_PHYS_BASE          0xa0000000
-#define U300_AHB_PER_VIRT_BASE          0xff010000
-/* FAST Peripherals */
-#define U300_FAST_PER_PHYS_BASE         0xc0000000
-#define U300_FAST_PER_VIRT_BASE         0xff020000
-/* SLOW Peripherals */
-#define U300_SLOW_PER_PHYS_BASE         0xc0010000
-#define U300_SLOW_PER_VIRT_BASE         0xff000000
-/* Boot ROM */
-#define U300_BOOTROM_PHYS_BASE          0xffff0000
-#define U300_BOOTROM_VIRT_BASE          0xffff0000
-/* SEMI config base */
-#define U300_SEMI_CONFIG_BASE           0x2FFE0000
-/*
- * AHB peripherals
- */
-/* AHB Peripherals Bridge Controller */
-#define U300_AHB_BRIDGE_BASE            (U300_AHB_PER_PHYS_BASE+0x0000)
-/* Vectored Interrupt Controller 0, servicing 32 interrupts */
-#define U300_INTCON0_BASE               (U300_AHB_PER_PHYS_BASE+0x1000)
-#define U300_INTCON0_VBASE              IOMEM(U300_AHB_PER_VIRT_BASE+0x1000)
-/* Vectored Interrupt Controller 1, servicing 32 interrupts */
-#define U300_INTCON1_BASE               (U300_AHB_PER_PHYS_BASE+0x2000)
-#define U300_INTCON1_VBASE              IOMEM(U300_AHB_PER_VIRT_BASE+0x2000)
-/* Memory Stick Pro (MSPRO) controller */
-#define U300_MSPRO_BASE                 (U300_AHB_PER_PHYS_BASE+0x3000)
-/* EMIF Configuration Area */
-#define U300_EMIF_CFG_BASE              (U300_AHB_PER_PHYS_BASE+0x4000)
-/*
- * FAST peripherals
- */
-/* FAST bridge control */
-#define U300_FAST_BRIDGE_BASE           (U300_FAST_PER_PHYS_BASE+0x0000)
-/* MMC/SD controller */
-#define U300_MMCSD_BASE                 (U300_FAST_PER_PHYS_BASE+0x1000)
-/* PCM I2S0 controller */
-#define U300_PCM_I2S0_BASE              (U300_FAST_PER_PHYS_BASE+0x2000)
-/* PCM I2S1 controller */
-#define U300_PCM_I2S1_BASE              (U300_FAST_PER_PHYS_BASE+0x3000)
-/* I2C0 controller */
-#define U300_I2C0_BASE                  (U300_FAST_PER_PHYS_BASE+0x4000)
-/* I2C1 controller */
-#define U300_I2C1_BASE                  (U300_FAST_PER_PHYS_BASE+0x5000)
-/* SPI controller */
-#define U300_SPI_BASE                   (U300_FAST_PER_PHYS_BASE+0x6000)
-/* Fast UART1 on U335 only */
-#define U300_UART1_BASE                 (U300_FAST_PER_PHYS_BASE+0x7000)
-/*
- * SLOW peripherals
- */
-/* SLOW bridge control */
-#define U300_SLOW_BRIDGE_BASE           (U300_SLOW_PER_PHYS_BASE)
-/* SYSCON */
-#define U300_SYSCON_BASE                (U300_SLOW_PER_PHYS_BASE+0x1000)
-#define U300_SYSCON_VBASE               IOMEM(U300_SLOW_PER_VIRT_BASE+0x1000)
-/* Watchdog */
-#define U300_WDOG_BASE                  (U300_SLOW_PER_PHYS_BASE+0x2000)
-/* UART0 */
-#define U300_UART0_BASE                 (U300_SLOW_PER_PHYS_BASE+0x3000)
-/* APP side special timer */
-#define U300_TIMER_APP_BASE             (U300_SLOW_PER_PHYS_BASE+0x4000)
-#define U300_TIMER_APP_VBASE            IOMEM(U300_SLOW_PER_VIRT_BASE+0x4000)
-/* Keypad */
-#define U300_KEYPAD_BASE                (U300_SLOW_PER_PHYS_BASE+0x5000)
-/* GPIO */
-#define U300_GPIO_BASE                  (U300_SLOW_PER_PHYS_BASE+0x6000)
-/* RTC */
-#define U300_RTC_BASE                   (U300_SLOW_PER_PHYS_BASE+0x7000)
-/* Bus tracer */
-#define U300_BUSTR_BASE                 (U300_SLOW_PER_PHYS_BASE+0x8000)
-/* Event handler (hardware queue) */
-#define U300_EVHIST_BASE                (U300_SLOW_PER_PHYS_BASE+0x9000)
-/* Genric Timer */
-#define U300_TIMER_BASE                 (U300_SLOW_PER_PHYS_BASE+0xa000)
-/* PPM */
-#define U300_PPM_BASE                   (U300_SLOW_PER_PHYS_BASE+0xb000)
-/*
- * REST peripherals
- */
-/* ISP (image signal processor) */
-#define U300_ISP_BASE                   (0xA0008000)
-/* DMA Controller base */
-#define U300_DMAC_BASE                  (0xC0020000)
-/* MSL Base */
-#define U300_MSL_BASE                   (0xc0022000)
-/* APEX Base */
-#define U300_APEX_BASE                  (0xc0030000)
-/* Video Encoder Base */
-#define U300_VIDEOENC_BASE              (0xc0080000)
-/* XGAM Base */
-#define U300_XGAM_BASE                  (0xd0000000)
-#endif
diff --git a/arch/arm/mach-u300/include/mach/uncompress.h b/arch/arm/mach-u300/include/mach/uncompress.h
deleted file mode 100644
index 783e7e60101b..000000000000
--- a/arch/arm/mach-u300/include/mach/uncompress.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * arch/arm/mach-u300/include/mach/uncompress.h
- *
- * Copyright (C) 2003 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#define AMBA_UART_DR    (*(volatile unsigned char *)0xc0013000)
-#define AMBA_UART_LCRH  (*(volatile unsigned char *)0xc001302C)
-#define AMBA_UART_CR    (*(volatile unsigned char *)0xc0013030)
-#define AMBA_UART_FR    (*(volatile unsigned char *)0xc0013018)
-/*
- * This does not append a newline
- */
-static inline void putc(int c)
-{
-        while (AMBA_UART_FR & (1 << 5))
-                barrier();
-        AMBA_UART_DR = c;
-}
-static inline void flush(void)
-{
-        while (AMBA_UART_FR & (1 << 3))
-                barrier();
-}
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
diff --git a/arch/arm/mach-u300/regulator.c b/arch/arm/mach-u300/regulator.c
index 9c53f01c62eb..bf40cd478fe9 100644
--- a/arch/arm/mach-u300/regulator.c
+++ b/arch/arm/mach-u300/regulator.c
@@ -10,11 +10,18 @@
 #include <linux/device.h>
 #include <linux/signal.h>
 #include <linux/err.h>
+#include <linux/of.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/machine.h>
 #include <linux/regulator/consumer.h>
-/* Those are just for writing in syscon */
+#include <linux/mfd/syscon.h>
-#include <linux/io.h>
+#include <linux/regmap.h>
-#include <mach/hardware.h>
-#include <mach/syscon.h>
+/* Power Management Control 16bit (R/W) */
+#define U300_SYSCON_PMCR                                        (0x50)
+#define U300_SYSCON_PMCR_DCON_ENABLE                            (0x0002)
+#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE                        (0x0001)
 /*
 * Regulators that power the board and chip and which are
@@ -47,13 +54,28 @@ void u300_pm_poweroff(void)
 /*
 * Hog the regulators needed to power up the board.
 */
-static int __init u300_init_boardpower(void)
+static int __init __u300_init_boardpower(struct platform_device *pdev)
 {
+        struct device_node *np = pdev->dev.of_node;
+        struct device_node *syscon_np;
+        struct regmap *regmap;
        int err;
-        u32 val;
        pr_info("U300: setting up board power\n");
-        main_power_15 = regulator_get(NULL, "vana15");
+        syscon_np = of_parse_phandle(np, "syscon", 0);
+        if (!syscon_np) {
+                pr_crit("U300: no syscon node\n");
+                return -ENODEV;
+        }
+        regmap = syscon_node_to_regmap(syscon_np);
+        if (!regmap) {
+                pr_crit("U300: could not locate syscon regmap\n");
+                return -ENODEV;
+        }
+        main_power_15 = regulator_get(&pdev->dev, "vana15");
        if (IS_ERR(main_power_15)) {
                pr_err("could not get vana15");
                return PTR_ERR(main_power_15);
@@ -72,9 +94,8 @@ static int __init u300_init_boardpower(void)
         * the rest of the U300 power management is implemented.
         */
        pr_info("U300: disable system controller pull-up\n");
-        val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMCR);
+        regmap_update_bits(regmap, U300_SYSCON_PMCR,
-        val &= ~U300_SYSCON_PMCR_DCON_ENABLE;
+                           U300_SYSCON_PMCR_DCON_ENABLE, 0);
-        writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMCR);
        /* Register globally exported PM poweroff hook */
        pm_power_off = u300_pm_poweroff;
@@ -82,7 +103,31 @@ static int __init u300_init_boardpower(void)
        return 0;
 }
+static int __init s365_board_probe(struct platform_device *pdev)
+{
+        return __u300_init_boardpower(pdev);
+}
+static const struct of_device_id s365_board_match[] = {
+        { .compatible = "stericsson,s365" },
+        {},
+};
+static struct platform_driver s365_board_driver = {
+        .driver         = {
+                .name   = "s365-board",
+                .owner  = THIS_MODULE,
+                .of_match_table = s365_board_match,
+        },
+};
 /*
 * So at module init time we hog the regulator!
 */
-module_init(u300_init_boardpower);
+static int __init u300_init_boardpower(void)
+{
+        return platform_driver_probe(&s365_board_driver,
+                                     s365_board_probe);
+}
+device_initcall(u300_init_boardpower);
diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c
deleted file mode 100644
index 910698293d64..000000000000
--- a/arch/arm/mach-u300/spi.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * arch/arm/mach-u300/spi.c
- *
- * Copyright (C) 2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- *
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-#include <linux/device.h>
-#include <linux/amba/bus.h>
-#include <linux/spi/spi.h>
-#include <linux/amba/pl022.h>
-#include <linux/platform_data/dma-coh901318.h>
-#include <linux/err.h>
-/*
- * The following is for the actual devices on the SSP/SPI bus
- */
-#ifdef CONFIG_MACH_U300_SPIDUMMY
-static void select_dummy_chip(u32 chipselect)
-{
-        pr_debug("CORE: %s called with CS=0x%x (%s)\n",
-                 __func__,
-                 chipselect,
-                 chipselect ? "unselect chip" : "select chip");
-        /*
-         * Here you would write the chip select value to the GPIO pins if
-         * this was a real chip (but this is a loopback dummy).
-         */
-}
-struct pl022_config_chip dummy_chip_info = {
-        /* available POLLING_TRANSFER, INTERRUPT_TRANSFER, DMA_TRANSFER */
-        .com_mode = DMA_TRANSFER,
-        .iface = SSP_INTERFACE_MOTOROLA_SPI,
-        /* We can only act as master but SSP_SLAVE is possible in theory */
-        .hierarchy = SSP_MASTER,
-        /* 0 = drive TX even as slave, 1 = do not drive TX as slave */
-        .slave_tx_disable = 0,
-        .rx_lev_trig = SSP_RX_4_OR_MORE_ELEM,
-        .tx_lev_trig = SSP_TX_4_OR_MORE_EMPTY_LOC,
-        .ctrl_len = SSP_BITS_12,
-        .wait_state = SSP_MWIRE_WAIT_ZERO,
-        .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
-        /*
-         * This is where you insert a call to a function to enable CS
-         * (usually GPIO) for a certain chip.
-         */
-        .cs_control = select_dummy_chip,
-};
-#endif
-static struct spi_board_info u300_spi_devices[] = {
-#ifdef CONFIG_MACH_U300_SPIDUMMY
-        {
-                /* A dummy chip used for loopback tests */
-                .modalias       = "spi-dummy",
-                /* Really dummy, pass in additional chip config here */
-                .platform_data  = NULL,
-                /* This defines how the controller shall handle the device */
-                .controller_data = &dummy_chip_info,
-                /* .irq - no external IRQ routed from this device */
-                .max_speed_hz   = 1000000,
-                .bus_num        = 0, /* Only one bus on this chip */
-                .chip_select    = 0,
-                /* Means SPI_CS_HIGH, change if e.g low CS */
-                .mode           = SPI_MODE_1 | SPI_LOOP,
-        },
-#endif
-};
-static struct pl022_ssp_controller ssp_platform_data = {
-        /* If you have several SPI buses this varies, we have only bus 0 */
-        .bus_id = 0,
-        /*
-         * On the APP CPU GPIO 4, 5 and 6 are connected as generic
-         * chip selects for SPI. (Same on U330, U335 and U365.)
-         * TODO: make sure the GPIO driver can select these properly
-         * and do padmuxing accordingly too.
-         */
-        .num_chipselect = 3,
-#ifdef CONFIG_COH901318
-        .enable_dma = 1,
-        .dma_filter = coh901318_filter_id,
-        .dma_rx_param = (void *) U300_DMA_SPI_RX,
-        .dma_tx_param = (void *) U300_DMA_SPI_TX,
-#else
-        .enable_dma = 0,
-#endif
-};
-void __init u300_spi_init(struct amba_device *adev)
-{
-        adev->dev.platform_data = &ssp_platform_data;
-}
-void __init u300_spi_register_board_devices(void)
-{
-        /* Register any SPI devices */
-        spi_register_board_info(u300_spi_devices, ARRAY_SIZE(u300_spi_devices));
-}
diff --git a/arch/arm/mach-u300/spi.h b/arch/arm/mach-u300/spi.h
deleted file mode 100644
index bd3d867e240f..000000000000
--- a/arch/arm/mach-u300/spi.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * arch/arm/mach-u300/spi.h
- *
- * Copyright (C) 2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- *
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-#ifndef SPI_H
-#define SPI_H
-#include <linux/amba/bus.h>
-#ifdef CONFIG_SPI_PL022
-void __init u300_spi_init(struct amba_device *adev);
-void __init u300_spi_register_board_devices(void);
-#else
-/* Compile out SPI support if PL022 is not selected */
-static inline void __init u300_spi_init(struct amba_device *adev)
-{
-}
-static inline void __init u300_spi_register_board_devices(void)
-{
-}
-#endif
-#endif
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index d9e73209c9b8..b5db207dfd1e 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -18,17 +18,15 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/irq.h>
+#include <linux/delay.h>
-#include <mach/hardware.h>
+#include <linux/of_address.h>
-#include <mach/irqs.h>
+#include <linux/of_irq.h>
+#include <linux/sched_clock.h>
 /* Generic stuff */
-#include <asm/sched_clock.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
-#include "timer.h"
 /*
 * APP side special timer registers
 * This timer contains four timers which can fire an interrupt each.
@@ -189,6 +187,8 @@
 #define TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
 #define US_PER_TICK ((1000000 + (HZ/2)) / HZ)
+static void __iomem *u300_timer_base;
 /*
 * The u300_set_mode() function is always called first, if we
 * have oneshot timer active, the oneshot scheduling function
@@ -201,28 +201,28 @@ static void u300_set_mode(enum clock_event_mode mode,
        case CLOCK_EVT_MODE_PERIODIC:
                /* Disable interrupts on GPT1 */
                writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+                       u300_timer_base + U300_TIMER_APP_GPT1IE);
                /* Disable GP1 while we're reprogramming it. */
                writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
+                       u300_timer_base + U300_TIMER_APP_DGPT1);
                /*
                 * Set the periodic mode to a certain number of ticks per
                 * jiffy.
                 */
                writel(TICKS_PER_JIFFY,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
+                       u300_timer_base + U300_TIMER_APP_GPT1TC);
                /*
                 * Set continuous mode, so the timer keeps triggering
                 * interrupts.
                 */
                writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
+                       u300_timer_base + U300_TIMER_APP_SGPT1M);
                /* Enable timer interrupts */
                writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+                       u300_timer_base + U300_TIMER_APP_GPT1IE);
                /* Then enable the OS timer again */
                writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
+                       u300_timer_base + U300_TIMER_APP_EGPT1);
                break;
        case CLOCK_EVT_MODE_ONESHOT:
                /* Just break; here? */
@@ -233,33 +233,33 @@ static void u300_set_mode(enum clock_event_mode mode,
                 */
                /* Disable interrupts on GPT1 */
                writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+                       u300_timer_base + U300_TIMER_APP_GPT1IE);
                /* Disable GP1 while we're reprogramming it. */
                writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
+                       u300_timer_base + U300_TIMER_APP_DGPT1);
                /*
                 * Expire far in the future, u300_set_next_event() will be
                 * called soon...
                 */
-                writel(0xFFFFFFFF, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
+                writel(0xFFFFFFFF, u300_timer_base + U300_TIMER_APP_GPT1TC);
                /* We run one shot per tick here! */
                writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
+                       u300_timer_base + U300_TIMER_APP_SGPT1M);
                /* Enable interrupts for this timer */
                writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+                       u300_timer_base + U300_TIMER_APP_GPT1IE);
                /* Enable timer */
                writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
+                       u300_timer_base + U300_TIMER_APP_EGPT1);
                break;
        case CLOCK_EVT_MODE_UNUSED:
        case CLOCK_EVT_MODE_SHUTDOWN:
                /* Disable interrupts on GP1 */
                writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+                       u300_timer_base + U300_TIMER_APP_GPT1IE);
                /* Disable GP1 */
                writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
+                       u300_timer_base + U300_TIMER_APP_DGPT1);
                break;
        case CLOCK_EVT_MODE_RESUME:
                /* Ignore this call */
@@ -281,27 +281,27 @@ static int u300_set_next_event(unsigned long cycles,
 {
        /* Disable interrupts on GPT1 */
        writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
-               U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+               u300_timer_base + U300_TIMER_APP_GPT1IE);
        /* Disable GP1 while we're reprogramming it. */
        writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
-               U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
+               u300_timer_base + U300_TIMER_APP_DGPT1);
        /* Reset the General Purpose timer 1. */
        writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
-               U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1);
+               u300_timer_base + U300_TIMER_APP_RGPT1);
        /* IRQ in n * cycles */
-        writel(cycles, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
+        writel(cycles, u300_timer_base + U300_TIMER_APP_GPT1TC);
        /*
         * We run one shot per tick here! (This is necessary to reconfigure,
         * the timer will tilt if you don't!)
         */
        writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
-               U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
+               u300_timer_base + U300_TIMER_APP_SGPT1M);
        /* Enable timer interrupts */
        writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
-               U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+               u300_timer_base + U300_TIMER_APP_GPT1IE);
        /* Then enable the OS timer again */
        writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
-               U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
+               u300_timer_base + U300_TIMER_APP_EGPT1);
        return 0;
 }
@@ -320,8 +320,9 @@ static irqreturn_t u300_timer_interrupt(int irq, void *dev_id)
 {
        struct clock_event_device *evt = &clockevent_u300_1mhz;
        /* ACK/Clear timer IRQ for the APP GPT1 Timer */
        writel(U300_TIMER_APP_GPT1IA_IRQ_ACK,
-                U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IA);
+                u300_timer_base + U300_TIMER_APP_GPT1IA);
        evt->event_handler(evt);
        return IRQ_HANDLED;
 }
@@ -342,65 +343,88 @@ static struct irqaction u300_timer_irq = {
 static u32 notrace u300_read_sched_clock(void)
 {
-        return readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC);
+        return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
+}
+static unsigned long u300_read_current_timer(void)
+{
+        return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
 }
+static struct delay_timer u300_delay_timer;
 /*
 * This sets up the system timers, clock source and clock event.
 */
-void __init u300_timer_init(void)
+static void __init u300_timer_init_of(struct device_node *np)
 {
+        struct resource irq_res;
+        int irq;
        struct clk *clk;
        unsigned long rate;
+        u300_timer_base = of_iomap(np, 0);
+        if (!u300_timer_base)
+                panic("could not ioremap system timer\n");
+        /* Get the IRQ for the GP1 timer */
+        irq = of_irq_to_resource(np, 2, &irq_res);
+        if (irq <= 0)
+                panic("no IRQ for system timer\n");
+        pr_info("U300 GP1 timer @ base: %p, IRQ: %d\n", u300_timer_base, irq);
        /* Clock the interrupt controller */
-        clk = clk_get_sys("apptimer", NULL);
+        clk = of_clk_get(np, 0);
        BUG_ON(IS_ERR(clk));
        clk_prepare_enable(clk);
        rate = clk_get_rate(clk);
        setup_sched_clock(u300_read_sched_clock, 32, rate);
+        u300_delay_timer.read_current_timer = &u300_read_current_timer;
+        u300_delay_timer.freq = rate;
+        register_current_timer_delay(&u300_delay_timer);
        /*
         * Disable the "OS" and "DD" timers - these are designed for Symbian!
         * Example usage in cnh1601578 cpu subsystem pd_timer_app.c
         */
        writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE,
-                U300_TIMER_APP_VBASE + U300_TIMER_APP_CRC);
+                u300_timer_base + U300_TIMER_APP_CRC);
        writel(U300_TIMER_APP_ROST_TIMER_RESET,
-                U300_TIMER_APP_VBASE + U300_TIMER_APP_ROST);
+                u300_timer_base + U300_TIMER_APP_ROST);
        writel(U300_TIMER_APP_DOST_TIMER_DISABLE,
-                U300_TIMER_APP_VBASE + U300_TIMER_APP_DOST);
+                u300_timer_base + U300_TIMER_APP_DOST);
        writel(U300_TIMER_APP_RDDT_TIMER_RESET,
-                U300_TIMER_APP_VBASE + U300_TIMER_APP_RDDT);
+                u300_timer_base + U300_TIMER_APP_RDDT);
        writel(U300_TIMER_APP_DDDT_TIMER_DISABLE,
-                U300_TIMER_APP_VBASE + U300_TIMER_APP_DDDT);
+                u300_timer_base + U300_TIMER_APP_DDDT);
        /* Reset the General Purpose timer 1. */
        writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
-                U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1);
+                u300_timer_base + U300_TIMER_APP_RGPT1);
        /* Set up the IRQ handler */
-        setup_irq(IRQ_U300_TIMER_APP_GP1, &u300_timer_irq);
+        setup_irq(irq, &u300_timer_irq);
        /* Reset the General Purpose timer 2 */
        writel(U300_TIMER_APP_RGPT2_TIMER_RESET,
-                U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT2);
+                u300_timer_base + U300_TIMER_APP_RGPT2);
        /* Set this timer to run around forever */
-        writel(0xFFFFFFFFU, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2TC);
+        writel(0xFFFFFFFFU, u300_timer_base + U300_TIMER_APP_GPT2TC);
        /* Set continuous mode so it wraps around */
        writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS,
-               U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT2M);
+               u300_timer_base + U300_TIMER_APP_SGPT2M);
        /* Disable timer interrupts */
        writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE,
-                U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2IE);
+                u300_timer_base + U300_TIMER_APP_GPT2IE);
        /* Then enable the GP2 timer to use as a free running us counter */
        writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE,
-                U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT2);
+                u300_timer_base + U300_TIMER_APP_EGPT2);
        /* Use general purpose timer 2 as clock source */
-        if (clocksource_mmio_init(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC,
+        if (clocksource_mmio_init(u300_timer_base + U300_TIMER_APP_GPT2CC,
                        "GPT2", rate, 300, 32, clocksource_mmio_readl_up))
                pr_err("timer: failed to initialize U300 clock source\n");
@@ -413,3 +437,6 @@ void __init u300_timer_init(void)
         * used by hrtimers!
         */
 }
+CLOCKSOURCE_OF_DECLARE(u300_timer, "stericsson,u300-apptimer",
+                       u300_timer_init_of);
diff --git a/arch/arm/mach-u300/timer.h b/arch/arm/mach-u300/timer.h
deleted file mode 100644
index d34287bc34f5..000000000000
--- a/arch/arm/mach-u300/timer.h
+++ /dev/null
@@ -1 +0,0 @@
-extern void u300_timer_init(void);
diff --git a/arch/arm/mach-u300/u300-gpio.h b/arch/arm/mach-u300/u300-gpio.h
deleted file mode 100644
index 83f50772e169..000000000000
--- a/arch/arm/mach-u300/u300-gpio.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Individual pin assignments for the B335/S335.
- * Notice that the actual usage of these pins depends on the
- * PAD MUX settings, that is why the same number can potentially
- * appear several times. In the reference design each pin is only
- * used for one purpose. These were determined by inspecting the
- * S365 schematic.
- */
-#define U300_GPIO_PIN_UART_RX           0
-#define U300_GPIO_PIN_UART_TX           1
-#define U300_GPIO_PIN_UART_CTS          2
-#define U300_GPIO_PIN_UART_RTS          3
-#define U300_GPIO_PIN_CAM_MAIN_STANDBY  4 /* Camera MAIN standby */
-#define U300_GPIO_PIN_GPIO05            5 /* Unrouted */
-#define U300_GPIO_PIN_MS_CD             6 /* Memory Stick Card insertion */
-#define U300_GPIO_PIN_GPIO07            7 /* Test point TP2430 */
-#define U300_GPIO_PIN_GPIO08            8 /* Test point TP2437 */
-#define U300_GPIO_PIN_GPIO09            9 /* Test point TP2431 */
-#define U300_GPIO_PIN_GPIO10            10 /* Test point TP2432 */
-#define U300_GPIO_PIN_MMC_CLKRET        11 /* Clock return from MMC/SD card */
-#define U300_GPIO_PIN_MMC_CD            12 /* MMC Card insertion detection */
-#define U300_GPIO_PIN_CAM_SUB_STANDBY   13 /* Camera SUB standby */
-#define U300_GPIO_PIN_GPIO14            14 /* Test point TP2436 */
-#define U300_GPIO_PIN_GPIO15            15 /* Unrouted */
-#define U300_GPIO_PIN_GPIO16            16 /* Test point TP2438 */
-#define U300_GPIO_PIN_PHFSENSE          17 /* Headphone jack sensing */
-#define U300_GPIO_PIN_GPIO18            18 /* Test point TP2439 */
-#define U300_GPIO_PIN_GPIO19            19 /* Routed somewhere */
-#define U300_GPIO_PIN_GPIO20            20 /* Unrouted */
-#define U300_GPIO_PIN_GPIO21            21 /* Unrouted */
-#define U300_GPIO_PIN_GPIO22            22 /* Unrouted */
-#define U300_GPIO_PIN_GPIO23            23 /* Unrouted */
-#define U300_GPIO_PIN_GPIO24            24 /* Unrouted */
-#define U300_GPIO_PIN_GPIO25            25 /* Unrouted */
-#define U300_GPIO_PIN_GPIO26            26 /* Unrouted */
-#define U300_GPIO_PIN_GPIO27            27 /* Unrouted */
-#define U300_GPIO_PIN_GPIO28            28 /* Unrouted */
-#define U300_GPIO_PIN_GPIO29            29 /* Unrouted */
-#define U300_GPIO_PIN_GPIO30            30 /* Unrouted */
-#define U300_GPIO_PIN_GPIO31            31 /* Unrouted */
-#define U300_GPIO_PIN_GPIO32            32 /* Unrouted */
-#define U300_GPIO_PIN_GPIO33            33 /* Unrouted */
-#define U300_GPIO_PIN_GPIO34            34 /* Unrouted */
-#define U300_GPIO_PIN_GPIO35            35 /* Unrouted */
-#define U300_GPIO_PIN_GPIO36            36 /* Unrouted */
-#define U300_GPIO_PIN_GPIO37            37 /* Unrouted */
-#define U300_GPIO_PIN_GPIO38            38 /* Unrouted */
-#define U300_GPIO_PIN_GPIO39            39 /* Unrouted */
-#define U300_GPIO_PIN_GPIO40            40 /* Unrouted */
-#define U300_GPIO_PIN_GPIO41            41 /* Unrouted */
-#define U300_GPIO_PIN_GPIO42            42 /* Unrouted */
-#define U300_GPIO_PIN_GPIO43            43 /* Unrouted */
-#define U300_GPIO_PIN_GPIO44            44 /* Unrouted */
-#define U300_GPIO_PIN_GPIO45            45 /* Unrouted */
-#define U300_GPIO_PIN_GPIO46            46 /* Unrouted */
-#define U300_GPIO_PIN_GPIO47            47 /* Unrouted */
-#define U300_GPIO_PIN_GPIO48            48 /* Unrouted */
-#define U300_GPIO_PIN_GPIO49            49 /* Unrouted */
-#define U300_GPIO_PIN_GPIO50            50 /* Unrouted */
-#define U300_GPIO_PIN_GPIO51            51 /* Unrouted */
-#define U300_GPIO_PIN_GPIO52            52 /* Unrouted */
-#define U300_GPIO_PIN_GPIO53            53 /* Unrouted */
-#define U300_GPIO_PIN_GPIO54            54 /* Unrouted */
-#define U300_GPIO_PIN_GPIO55            55 /* Unrouted */
diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c
index aba9e5692958..bfe443daf4b0 100644
--- a/arch/arm/mach-ux500/board-mop500-audio.c
+++ b/arch/arm/mach-ux500/board-mop500-audio.c
@@ -21,28 +21,14 @@
 static struct stedma40_chan_cfg msp0_dma_rx = {
        .high_priority = true,
-        .dir = STEDMA40_PERIPH_TO_MEM,
+        .dir = DMA_DEV_TO_MEM,
+        .dev_type = DB8500_DMA_DEV31_MSP0_SLIM0_CH0,
-        .src_dev_type = DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX,
-        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-        .src_info.psize = STEDMA40_PSIZE_LOG_4,
-        .dst_info.psize = STEDMA40_PSIZE_LOG_4,
-        /* data_width is set during configuration */
 };
 static struct stedma40_chan_cfg msp0_dma_tx = {
        .high_priority = true,
-        .dir = STEDMA40_MEM_TO_PERIPH,
+        .dir = DMA_MEM_TO_DEV,
+        .dev_type = DB8500_DMA_DEV31_MSP0_SLIM0_CH0,
-        .src_dev_type = STEDMA40_DEV_DST_MEMORY,
-        .dst_dev_type = DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX,
-        .src_info.psize = STEDMA40_PSIZE_LOG_4,
-        .dst_info.psize = STEDMA40_PSIZE_LOG_4,
-        /* data_width is set during configuration */
 };
 struct msp_i2s_platform_data msp0_platform_data = {
@@ -53,28 +39,14 @@ struct msp_i2s_platform_data msp0_platform_data = {
 static struct stedma40_chan_cfg msp1_dma_rx = {
        .high_priority = true,
-        .dir = STEDMA40_PERIPH_TO_MEM,
+        .dir = DMA_DEV_TO_MEM,
+        .dev_type = DB8500_DMA_DEV30_MSP3,
-        .src_dev_type = DB8500_DMA_DEV30_MSP3_RX,
-        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-        .src_info.psize = STEDMA40_PSIZE_LOG_4,
-        .dst_info.psize = STEDMA40_PSIZE_LOG_4,
-        /* data_width is set during configuration */
 };
 static struct stedma40_chan_cfg msp1_dma_tx = {
        .high_priority = true,
-        .dir = STEDMA40_MEM_TO_PERIPH,
+        .dir = DMA_MEM_TO_DEV,
+        .dev_type = DB8500_DMA_DEV30_MSP1,
-        .src_dev_type = STEDMA40_DEV_DST_MEMORY,
-        .dst_dev_type = DB8500_DMA_DEV30_MSP1_TX,
-        .src_info.psize = STEDMA40_PSIZE_LOG_4,
-        .dst_info.psize = STEDMA40_PSIZE_LOG_4,
-        /* data_width is set during configuration */
 };
 struct msp_i2s_platform_data msp1_platform_data = {
@@ -85,32 +57,16 @@ struct msp_i2s_platform_data msp1_platform_data = {
 static struct stedma40_chan_cfg msp2_dma_rx = {
        .high_priority = true,
-        .dir = STEDMA40_PERIPH_TO_MEM,
+        .dir = DMA_DEV_TO_MEM,
+        .dev_type = DB8500_DMA_DEV14_MSP2,
-        .src_dev_type = DB8500_DMA_DEV14_MSP2_RX,
-        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-        /* MSP2 DMA doesn't work with PSIZE == 4 on DB8500v2 */
-        .src_info.psize = STEDMA40_PSIZE_LOG_1,
-        .dst_info.psize = STEDMA40_PSIZE_LOG_1,
-        /* data_width is set during configuration */
 };
 static struct stedma40_chan_cfg msp2_dma_tx = {
        .high_priority = true,
-        .dir = STEDMA40_MEM_TO_PERIPH,
+        .dir = DMA_MEM_TO_DEV,
+        .dev_type = DB8500_DMA_DEV14_MSP2,
-        .src_dev_type = STEDMA40_DEV_DST_MEMORY,
-        .dst_dev_type = DB8500_DMA_DEV14_MSP2_TX,
-        .src_info.psize = STEDMA40_PSIZE_LOG_4,
-        .dst_info.psize = STEDMA40_PSIZE_LOG_4,
        .use_fixed_channel = true,
        .phy_channel = 1,
-        /* data_width is set during configuration */
 };
 static struct platform_device *db8500_add_msp_i2s(struct device *parent,
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index 947bd9eca079..7936d40a5c37 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -9,6 +9,7 @@
 #include <linux/bug.h>
 #include <linux/string.h>
 #include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf-generic.h>
 #include <linux/platform_data/pinctrl-nomadik.h>
 #include <asm/mach-types.h>
@@ -34,6 +35,11 @@ BIAS(in_pd, PIN_INPUT_PULLDOWN);
 BIAS(out_hi, PIN_OUTPUT_HIGH);
 BIAS(out_lo, PIN_OUTPUT_LOW);
 BIAS(out_lo_slpm_nowkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE);
+BIAS(abx500_out_lo, PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0));
+BIAS(abx500_in_pd, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 1));
+BIAS(abx500_in_nopull, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 0));
 /* These also force them into GPIO mode */
 BIAS(gpio_in_pu, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED);
 BIAS(gpio_in_pd, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED);
@@ -42,8 +48,6 @@ BIAS(gpio_in_pd_slpm_gpio_nopull, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED|PIN_SL
 BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED);
 BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED);
 /* Sleep modes */
-BIAS(slpm_in_nopull_wkup, PIN_SLEEPMODE_ENABLED|
-        PIN_SLPM_DIR_INPUT|PIN_SLPM_PULL_NONE|PIN_SLPM_WAKEUP_ENABLE);
 BIAS(slpm_in_wkup_pdis, PIN_SLEEPMODE_ENABLED|
        PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
 BIAS(slpm_in_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|
@@ -54,8 +58,6 @@ BIAS(slpm_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|
        PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
 BIAS(slpm_out_lo_pdis, PIN_SLEEPMODE_ENABLED|
        PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE|PIN_SLPM_PDIS_DISABLED);
-BIAS(slpm_out_lo_wkup, PIN_SLEEPMODE_ENABLED|
-        PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE);
 BIAS(slpm_out_lo_wkup_pdis, PIN_SLEEPMODE_ENABLED|
        PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
 BIAS(slpm_out_hi_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_OUTPUT_HIGH|
@@ -97,6 +99,252 @@ BIAS(out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|
 #define DB8500_PIN_STATE(pin, conf, dev, state) \
        PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-db8500", pin, conf)
+#define AB8500_MUX_HOG(group, func) \
+        PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8500.0", group, func)
+#define AB8500_PIN_HOG(pin, conf) \
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-ab8500.0", pin, abx500_##conf)
+#define AB8500_MUX_STATE(group, func, dev, state) \
+        PIN_MAP_MUX_GROUP(dev, state, "pinctrl-ab8500.0", group, func)
+#define AB8500_PIN_STATE(pin, conf, dev, state) \
+        PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-ab8500.0", pin, abx500_##conf)
+#define AB8505_MUX_HOG(group, func) \
+        PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8505.0", group, func)
+#define AB8505_PIN_HOG(pin, conf) \
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-ab8505.0", pin, abx500_##conf)
+#define AB8505_MUX_STATE(group, func, dev, state) \
+        PIN_MAP_MUX_GROUP(dev, state, "pinctrl-ab8505.0", group, func)
+#define AB8505_PIN_STATE(pin, conf, dev, state) \
+        PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-ab8505.0", pin, abx500_##conf)
+static struct pinctrl_map __initdata ab8500_pinmap[] = {
+        /* Sysclkreq2 */
+        AB8500_MUX_STATE("sysclkreq2_d_1", "sysclkreq", "regulator.35", PINCTRL_STATE_DEFAULT),
+        AB8500_PIN_STATE("GPIO1_T10", in_nopull, "regulator.35", PINCTRL_STATE_DEFAULT),
+        /* sysclkreq2 disable, mux in gpio configured in input pulldown */
+        AB8500_MUX_STATE("gpio1_a_1", "gpio", "regulator.35", PINCTRL_STATE_SLEEP),
+        AB8500_PIN_STATE("GPIO1_T10", in_pd, "regulator.35", PINCTRL_STATE_SLEEP),
+        /* pins 2 is muxed in GPIO, configured in INPUT PULL DOWN */
+        AB8500_MUX_HOG("gpio2_a_1", "gpio"),
+        AB8500_PIN_HOG("GPIO2_T9", in_pd),
+        /* Sysclkreq4 */
+        AB8500_MUX_STATE("sysclkreq4_d_1", "sysclkreq", "regulator.36", PINCTRL_STATE_DEFAULT),
+        AB8500_PIN_STATE("GPIO3_U9", in_nopull, "regulator.36", PINCTRL_STATE_DEFAULT),
+        /* sysclkreq4 disable, mux in gpio configured in input pulldown */
+        AB8500_MUX_STATE("gpio3_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP),
+        AB8500_PIN_STATE("GPIO3_U9", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
+        /* pins 4 is muxed in GPIO, configured in INPUT PULL DOWN */
+        AB8500_MUX_HOG("gpio4_a_1", "gpio"),
+        AB8500_PIN_HOG("GPIO4_W2", in_pd),
+        /*
+         * pins 6,7,8 and 9 are muxed in YCBCR0123
+         * configured in INPUT PULL UP
+         */
+        AB8500_MUX_HOG("ycbcr0123_d_1", "ycbcr"),
+        AB8500_PIN_HOG("GPIO6_Y18", in_nopull),
+        AB8500_PIN_HOG("GPIO7_AA20", in_nopull),
+        AB8500_PIN_HOG("GPIO8_W18", in_nopull),
+        AB8500_PIN_HOG("GPIO9_AA19", in_nopull),
+        /*
+         * pins 10,11,12 and 13 are muxed in GPIO
+         * configured in INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("gpio10_d_1", "gpio"),
+        AB8500_PIN_HOG("GPIO10_U17", in_pd),
+        AB8500_MUX_HOG("gpio11_d_1", "gpio"),
+        AB8500_PIN_HOG("GPIO11_AA18", in_pd),
+        AB8500_MUX_HOG("gpio12_d_1", "gpio"),
+        AB8500_PIN_HOG("GPIO12_U16", in_pd),
+        AB8500_MUX_HOG("gpio13_d_1", "gpio"),
+        AB8500_PIN_HOG("GPIO13_W17", in_pd),
+        /*
+         * pins 14,15 are muxed in PWM1 and PWM2
+         * configured in INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("pwmout1_d_1", "pwmout"),
+        AB8500_PIN_HOG("GPIO14_F14", in_pd),
+        AB8500_MUX_HOG("pwmout2_d_1", "pwmout"),
+        AB8500_PIN_HOG("GPIO15_B17", in_pd),
+        /*
+         * pins 16 is muxed in GPIO
+         * configured in INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("gpio16_a_1", "gpio"),
+        AB8500_PIN_HOG("GPIO14_F14", in_pd),
+        /*
+         * pins 17,18,19 and 20 are muxed in AUDIO interface 1
+         * configured in INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("adi1_d_1", "adi1"),
+        AB8500_PIN_HOG("GPIO17_P5", in_pd),
+        AB8500_PIN_HOG("GPIO18_R5", in_pd),
+        AB8500_PIN_HOG("GPIO19_U5", in_pd),
+        AB8500_PIN_HOG("GPIO20_T5", in_pd),
+        /*
+         * pins 21,22 and 23 are muxed in USB UICC
+         * configured in INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("usbuicc_d_1", "usbuicc"),
+        AB8500_PIN_HOG("GPIO21_H19", in_pd),
+        AB8500_PIN_HOG("GPIO22_G20", in_pd),
+        AB8500_PIN_HOG("GPIO23_G19", in_pd),
+        /*
+         * pins 24,25 are muxed in GPIO
+         * configured in INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("gpio24_a_1", "gpio"),
+        AB8500_PIN_HOG("GPIO24_T14", in_pd),
+        AB8500_MUX_HOG("gpio25_a_1", "gpio"),
+        AB8500_PIN_HOG("GPIO25_R16", in_pd),
+        /*
+         * pins 26 is muxed in GPIO
+         * configured in OUTPUT LOW
+         */
+        AB8500_MUX_HOG("gpio26_d_1", "gpio"),
+        AB8500_PIN_HOG("GPIO26_M16", out_lo),
+        /*
+         * pins 27,28 are muxed in DMIC12
+         * configured in INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("dmic12_d_1", "dmic"),
+        AB8500_PIN_HOG("GPIO27_J6", in_pd),
+        AB8500_PIN_HOG("GPIO28_K6", in_pd),
+        /*
+         * pins 29,30 are muxed in DMIC34
+         * configured in INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("dmic34_d_1", "dmic"),
+        AB8500_PIN_HOG("GPIO29_G6", in_pd),
+        AB8500_PIN_HOG("GPIO30_H6", in_pd),
+        /*
+         * pins 31,32 are muxed in DMIC56
+         * configured in INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("dmic56_d_1", "dmic"),
+        AB8500_PIN_HOG("GPIO31_F5", in_pd),
+        AB8500_PIN_HOG("GPIO32_G5", in_pd),
+        /*
+         * pins 34 is muxed in EXTCPENA
+         * configured INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("extcpena_d_1", "extcpena"),
+        AB8500_PIN_HOG("GPIO34_R17", in_pd),
+        /*
+         * pins 35 is muxed in GPIO
+         * configured in OUTPUT LOW
+         */
+        AB8500_MUX_HOG("gpio35_d_1", "gpio"),
+        AB8500_PIN_HOG("GPIO35_W15", in_pd),
+        /*
+         * pins 36,37,38 and 39 are muxed in GPIO
+         * configured in INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("gpio36_a_1", "gpio"),
+        AB8500_PIN_HOG("GPIO36_A17", in_pd),
+        AB8500_MUX_HOG("gpio37_a_1", "gpio"),
+        AB8500_PIN_HOG("GPIO37_E15", in_pd),
+        AB8500_MUX_HOG("gpio38_a_1", "gpio"),
+        AB8500_PIN_HOG("GPIO38_C17", in_pd),
+        AB8500_MUX_HOG("gpio39_a_1", "gpio"),
+        AB8500_PIN_HOG("GPIO39_E16", in_pd),
+        /*
+         * pins 40 and 41 are muxed in MODCSLSDA
+         * configured INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("modsclsda_d_1", "modsclsda"),
+        AB8500_PIN_HOG("GPIO40_T19", in_pd),
+        AB8500_PIN_HOG("GPIO41_U19", in_pd),
+        /*
+         * pins 42 is muxed in GPIO
+         * configured INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("gpio42_a_1", "gpio"),
+        AB8500_PIN_HOG("GPIO42_U2", in_pd),
+};
+static struct pinctrl_map __initdata ab8505_pinmap[] = {
+        /* Sysclkreq2 */
+        AB8505_MUX_STATE("sysclkreq2_d_1", "sysclkreq", "regulator.36", PINCTRL_STATE_DEFAULT),
+        AB8505_PIN_STATE("GPIO1_N4", in_nopull, "regulator.36", PINCTRL_STATE_DEFAULT),
+        /* sysclkreq2 disable, mux in gpio configured in input pulldown */
+        AB8505_MUX_STATE("gpio1_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP),
+        AB8505_PIN_STATE("GPIO1_N4", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
+        /* pins 2 is muxed in GPIO, configured in INPUT PULL DOWN */
+        AB8505_MUX_HOG("gpio2_a_1", "gpio"),
+        AB8505_PIN_HOG("GPIO2_R5", in_pd),
+        /* Sysclkreq4 */
+        AB8505_MUX_STATE("sysclkreq4_d_1", "sysclkreq", "regulator.37", PINCTRL_STATE_DEFAULT),
+        AB8505_PIN_STATE("GPIO3_P5", in_nopull, "regulator.37", PINCTRL_STATE_DEFAULT),
+        /* sysclkreq4 disable, mux in gpio configured in input pulldown */
+        AB8505_MUX_STATE("gpio3_a_1", "gpio", "regulator.37", PINCTRL_STATE_SLEEP),
+        AB8505_PIN_STATE("GPIO3_P5", in_pd, "regulator.37", PINCTRL_STATE_SLEEP),
+        AB8505_MUX_HOG("gpio10_d_1", "gpio"),
+        AB8505_PIN_HOG("GPIO10_B16", in_pd),
+        AB8505_MUX_HOG("gpio11_d_1", "gpio"),
+        AB8505_PIN_HOG("GPIO11_B17", in_pd),
+        AB8505_MUX_HOG("gpio13_d_1", "gpio"),
+        AB8505_PIN_HOG("GPIO13_D17", in_nopull),
+        AB8505_MUX_HOG("pwmout1_d_1", "pwmout"),
+        AB8505_PIN_HOG("GPIO14_C16", in_pd),
+        AB8505_MUX_HOG("adi2_d_1", "adi2"),
+        AB8505_PIN_HOG("GPIO17_P2", in_pd),
+        AB8505_PIN_HOG("GPIO18_N3", in_pd),
+        AB8505_PIN_HOG("GPIO19_T1", in_pd),
+        AB8505_PIN_HOG("GPIO20_P3", in_pd),
+        AB8505_MUX_HOG("gpio34_a_1", "gpio"),
+        AB8505_PIN_HOG("GPIO34_H14", in_pd),
+        AB8505_MUX_HOG("modsclsda_d_1", "modsclsda"),
+        AB8505_PIN_HOG("GPIO40_J15", in_pd),
+        AB8505_PIN_HOG("GPIO41_J14", in_pd),
+        AB8505_MUX_HOG("gpio50_d_1", "gpio"),
+        AB8505_PIN_HOG("GPIO50_L4", in_nopull),
+        AB8505_MUX_HOG("resethw_d_1", "resethw"),
+        AB8505_PIN_HOG("GPIO52_D16", in_pd),
+        AB8505_MUX_HOG("service_d_1", "service"),
+        AB8505_PIN_HOG("GPIO53_D15", in_pd),
+};
 /* Pin control settings */
 static struct pinctrl_map __initdata mop500_family_pinmap[] = {
        /*
@@ -174,17 +422,12 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = {
        DB8500_PIN_SLEEP("GPIO4_AH6", slpm_in_wkup_pdis, "uart1"),
        DB8500_PIN_SLEEP("GPIO5_AG6", slpm_out_wkup_pdis, "uart1"),
        /* MSP1 for ALSA codec */
-        DB8500_MUX("msp1txrx_a_1", "msp1", "ux500-msp-i2s.1"),
+        DB8500_MUX_HOG("msp1txrx_a_1", "msp1"),
-        DB8500_MUX("msp1_a_1", "msp1", "ux500-msp-i2s.1"),
+        DB8500_MUX_HOG("msp1_a_1", "msp1"),
-        DB8500_PIN("GPIO33_AF2", out_lo_slpm_nowkup, "ux500-msp-i2s.1"),
+        DB8500_PIN_HOG("GPIO33_AF2", out_lo_slpm_nowkup),
-        DB8500_PIN("GPIO34_AE1", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
+        DB8500_PIN_HOG("GPIO34_AE1", in_nopull_slpm_nowkup),
-        DB8500_PIN("GPIO35_AE2", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
+        DB8500_PIN_HOG("GPIO35_AE2", in_nopull_slpm_nowkup),
-        DB8500_PIN("GPIO36_AG2", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
+        DB8500_PIN_HOG("GPIO36_AG2", in_nopull_slpm_nowkup),
-        /* MSP1 sleep state */
-        DB8500_PIN_SLEEP("GPIO33_AF2", slpm_out_lo_wkup, "ux500-msp-i2s.1"),
-        DB8500_PIN_SLEEP("GPIO34_AE1", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
-        DB8500_PIN_SLEEP("GPIO35_AE2", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
-        DB8500_PIN_SLEEP("GPIO36_AG2", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
        /* Mux in LCD data lines 8 thru 11 and LCDA CLK for MCDE TVOUT */
        DB8500_MUX("lcd_d8_d11_a_1", "lcd", "mcde-tvout"),
        DB8500_MUX("lcdaclk_b_1", "lcda", "mcde-tvout"),
@@ -821,6 +1064,12 @@ void __init mop500_pinmaps_init(void)
        pinctrl_register_mappings(mop500_pinmap,
                                  ARRAY_SIZE(mop500_pinmap));
        mop500_href_family_pinmaps_init();
+        if (machine_is_u8520())
+                pinctrl_register_mappings(ab8505_pinmap,
+                                          ARRAY_SIZE(ab8505_pinmap));
+        else
+                pinctrl_register_mappings(ab8500_pinmap,
+                                          ARRAY_SIZE(ab8500_pinmap));
 }
 void __init snowball_pinmaps_init(void)
@@ -831,6 +1080,8 @@ void __init snowball_pinmaps_init(void)
                                  ARRAY_SIZE(snowball_pinmap));
        pinctrl_register_mappings(u8500_pinmap,
                                  ARRAY_SIZE(u8500_pinmap));
+        pinctrl_register_mappings(ab8500_pinmap,
+                                  ARRAY_SIZE(ab8500_pinmap));
 }
 void __init hrefv60_pinmaps_init(void)
@@ -840,4 +1091,6 @@ void __init hrefv60_pinmaps_init(void)
        pinctrl_register_mappings(hrefv60_pinmap,
                                  ARRAY_SIZE(hrefv60_pinmap));
        mop500_href_family_pinmaps_init();
+        pinctrl_register_mappings(ab8500_pinmap,
+                                  ARRAY_SIZE(ab8500_pinmap));
 }
diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c
index d6b7c8556fa1..0dc44c683427 100644
--- a/arch/arm/mach-ux500/board-mop500-regulators.c
+++ b/arch/arm/mach-ux500/board-mop500-regulators.c
@@ -999,7 +999,6 @@ struct ab8500_regulator_platform_data ab8500_regulator_plat_data = {
        .num_ext_regulator      = ARRAY_SIZE(ab8500_ext_regulators),
 };
-/* Use the AB8500 init settings for AB8505 as they are the same right now */
 struct ab8500_regulator_platform_data ab8505_regulator_plat_data = {
        .reg_init               = ab8505_reg_init,
        .num_reg_init           = ARRAY_SIZE(ab8505_reg_init),
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 0ef38775a0c1..b3e61a38e5c8 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -34,29 +34,25 @@
 #ifdef CONFIG_STE_DMA40
 struct stedma40_chan_cfg mop500_sdi0_dma_cfg_rx = {
        .mode = STEDMA40_MODE_LOGICAL,
-        .dir = STEDMA40_PERIPH_TO_MEM,
+        .dir = DMA_DEV_TO_MEM,
-        .src_dev_type = DB8500_DMA_DEV29_SD_MM0_RX,
+        .dev_type = DB8500_DMA_DEV29_SD_MM0,
-        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-        .src_info.data_width = STEDMA40_WORD_WIDTH,
-        .dst_info.data_width = STEDMA40_WORD_WIDTH,
 };
 static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {
        .mode = STEDMA40_MODE_LOGICAL,
-        .dir = STEDMA40_MEM_TO_PERIPH,
+        .dir = DMA_MEM_TO_DEV,
-        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+        .dev_type = DB8500_DMA_DEV29_SD_MM0,
-        .dst_dev_type = DB8500_DMA_DEV29_SD_MM0_TX,
-        .src_info.data_width = STEDMA40_WORD_WIDTH,
-        .dst_info.data_width = STEDMA40_WORD_WIDTH,
 };
 #endif
 struct mmci_platform_data mop500_sdi0_data = {
-        .ocr_mask       = MMC_VDD_29_30,
+        .f_max          = 100000000,
-        .f_max          = 50000000,
        .capabilities   = MMC_CAP_4_BIT_DATA |
                                MMC_CAP_SD_HIGHSPEED |
-                                MMC_CAP_MMC_HIGHSPEED,
+                                MMC_CAP_MMC_HIGHSPEED |
+                                MMC_CAP_ERASE |
+                                MMC_CAP_UHS_SDR12 |
+                                MMC_CAP_UHS_SDR25,
        .gpio_wp        = -1,
        .sigdir         = MCI_ST_FBCLKEN |
                                MCI_ST_CMDDIREN |
@@ -87,27 +83,22 @@ void mop500_sdi_tc35892_init(struct device *parent)
 #ifdef CONFIG_STE_DMA40
 static struct stedma40_chan_cfg sdi1_dma_cfg_rx = {
        .mode = STEDMA40_MODE_LOGICAL,
-        .dir = STEDMA40_PERIPH_TO_MEM,
+        .dir = DMA_DEV_TO_MEM,
-        .src_dev_type = DB8500_DMA_DEV32_SD_MM1_RX,
+        .dev_type = DB8500_DMA_DEV32_SD_MM1,
-        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-        .src_info.data_width = STEDMA40_WORD_WIDTH,
-        .dst_info.data_width = STEDMA40_WORD_WIDTH,
 };
 static struct stedma40_chan_cfg sdi1_dma_cfg_tx = {
        .mode = STEDMA40_MODE_LOGICAL,
-        .dir = STEDMA40_MEM_TO_PERIPH,
+        .dir = DMA_MEM_TO_DEV,
-        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+        .dev_type = DB8500_DMA_DEV32_SD_MM1,
-        .dst_dev_type = DB8500_DMA_DEV32_SD_MM1_TX,
-        .src_info.data_width = STEDMA40_WORD_WIDTH,
-        .dst_info.data_width = STEDMA40_WORD_WIDTH,
 };
 #endif
 struct mmci_platform_data mop500_sdi1_data = {
        .ocr_mask       = MMC_VDD_29_30,
-        .f_max          = 50000000,
+        .f_max          = 100000000,
-        .capabilities   = MMC_CAP_4_BIT_DATA,
+        .capabilities   = MMC_CAP_4_BIT_DATA |
+                                MMC_CAP_NONREMOVABLE,
        .gpio_cd        = -1,
        .gpio_wp        = -1,
 #ifdef CONFIG_STE_DMA40
@@ -124,28 +115,26 @@ struct mmci_platform_data mop500_sdi1_data = {
 #ifdef CONFIG_STE_DMA40
 struct stedma40_chan_cfg mop500_sdi2_dma_cfg_rx = {
        .mode = STEDMA40_MODE_LOGICAL,
-        .dir = STEDMA40_PERIPH_TO_MEM,
+        .dir = DMA_DEV_TO_MEM,
-        .src_dev_type =  DB8500_DMA_DEV28_SD_MM2_RX,
+        .dev_type =  DB8500_DMA_DEV28_SD_MM2,
-        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-        .src_info.data_width = STEDMA40_WORD_WIDTH,
-        .dst_info.data_width = STEDMA40_WORD_WIDTH,
 };
 static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = {
        .mode = STEDMA40_MODE_LOGICAL,
-        .dir = STEDMA40_MEM_TO_PERIPH,
+        .dir = DMA_MEM_TO_DEV,
-        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+        .dev_type = DB8500_DMA_DEV28_SD_MM2,
-        .dst_dev_type = DB8500_DMA_DEV28_SD_MM2_TX,
-        .src_info.data_width = STEDMA40_WORD_WIDTH,
-        .dst_info.data_width = STEDMA40_WORD_WIDTH,
 };
 #endif
 struct mmci_platform_data mop500_sdi2_data = {
        .ocr_mask       = MMC_VDD_165_195,
-        .f_max          = 50000000,
+        .f_max          = 100000000,
-        .capabilities   = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
+        .capabilities   = MMC_CAP_4_BIT_DATA |
-                          MMC_CAP_MMC_HIGHSPEED,
+                                MMC_CAP_8_BIT_DATA |
+                                MMC_CAP_NONREMOVABLE |
+                                MMC_CAP_MMC_HIGHSPEED |
+                                MMC_CAP_ERASE |
+                                MMC_CAP_CMD23,
        .gpio_cd        = -1,
        .gpio_wp        = -1,
 #ifdef CONFIG_STE_DMA40
@@ -162,28 +151,25 @@ struct mmci_platform_data mop500_sdi2_data = {
 #ifdef CONFIG_STE_DMA40
 struct stedma40_chan_cfg mop500_sdi4_dma_cfg_rx = {
        .mode = STEDMA40_MODE_LOGICAL,
-        .dir = STEDMA40_PERIPH_TO_MEM,
+        .dir = DMA_DEV_TO_MEM,
-        .src_dev_type =  DB8500_DMA_DEV42_SD_MM4_RX,
+        .dev_type =  DB8500_DMA_DEV42_SD_MM4,
-        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-        .src_info.data_width = STEDMA40_WORD_WIDTH,
-        .dst_info.data_width = STEDMA40_WORD_WIDTH,
 };
 static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = {
        .mode = STEDMA40_MODE_LOGICAL,
-        .dir = STEDMA40_MEM_TO_PERIPH,
+        .dir = DMA_MEM_TO_DEV,
-        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+        .dev_type = DB8500_DMA_DEV42_SD_MM4,
-        .dst_dev_type = DB8500_DMA_DEV42_SD_MM4_TX,
-        .src_info.data_width = STEDMA40_WORD_WIDTH,
-        .dst_info.data_width = STEDMA40_WORD_WIDTH,
 };
 #endif
 struct mmci_platform_data mop500_sdi4_data = {
-        .ocr_mask       = MMC_VDD_29_30,
+        .f_max          = 100000000,
-        .f_max          = 50000000,
+        .capabilities   = MMC_CAP_4_BIT_DATA |
-        .capabilities   = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
+                                MMC_CAP_8_BIT_DATA |
-                          MMC_CAP_MMC_HIGHSPEED,
+                                MMC_CAP_NONREMOVABLE |
+                                MMC_CAP_MMC_HIGHSPEED |
+                                MMC_CAP_ERASE |
+                                MMC_CAP_CMD23,
        .gpio_cd        = -1,
        .gpio_wp        = -1,
 #ifdef CONFIG_STE_DMA40
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 78389de94dde..df5d27a532e9 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -413,47 +413,23 @@ static void mop500_prox_deactivate(struct device *dev)
        regulator_put(prox_regulator);
 }
-void mop500_snowball_ethernet_clock_enable(void)
-{
-        struct clk *clk;
-        clk = clk_get_sys("fsmc", NULL);
-        if (!IS_ERR(clk))
-                clk_prepare_enable(clk);
-}
 static struct cryp_platform_data u8500_cryp1_platform_data = {
                .mem_to_engine = {
-                                .dir = STEDMA40_MEM_TO_PERIPH,
+                                .dir = DMA_MEM_TO_DEV,
-                                .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+                                .dev_type = DB8500_DMA_DEV48_CAC1,
-                                .dst_dev_type = DB8500_DMA_DEV48_CAC1_TX,
-                                .src_info.data_width = STEDMA40_WORD_WIDTH,
-                                .dst_info.data_width = STEDMA40_WORD_WIDTH,
                                .mode = STEDMA40_MODE_LOGICAL,
-                                .src_info.psize = STEDMA40_PSIZE_LOG_4,
-                                .dst_info.psize = STEDMA40_PSIZE_LOG_4,
                },
                .engine_to_mem = {
-                                .dir = STEDMA40_PERIPH_TO_MEM,
+                                .dir = DMA_DEV_TO_MEM,
-                                .src_dev_type = DB8500_DMA_DEV48_CAC1_RX,
+                                .dev_type = DB8500_DMA_DEV48_CAC1,
-                                .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-                                .src_info.data_width = STEDMA40_WORD_WIDTH,
-                                .dst_info.data_width = STEDMA40_WORD_WIDTH,
                                .mode = STEDMA40_MODE_LOGICAL,
-                                .src_info.psize = STEDMA40_PSIZE_LOG_4,
-                                .dst_info.psize = STEDMA40_PSIZE_LOG_4,
                }
 };
 static struct stedma40_chan_cfg u8500_hash_dma_cfg_tx = {
-                .dir = STEDMA40_MEM_TO_PERIPH,
+                .dir = DMA_MEM_TO_DEV,
-                .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+                .dev_type = DB8500_DMA_DEV50_HAC1_TX,
-                .dst_dev_type = DB8500_DMA_DEV50_HAC1_TX,
-                .src_info.data_width = STEDMA40_WORD_WIDTH,
-                .dst_info.data_width = STEDMA40_WORD_WIDTH,
                .mode = STEDMA40_MODE_LOGICAL,
-                .src_info.psize = STEDMA40_PSIZE_LOG_16,
-                .dst_info.psize = STEDMA40_PSIZE_LOG_16,
 };
 static struct hash_platform_data u8500_hash1_platform_data = {
@@ -470,20 +446,14 @@ static struct platform_device *mop500_platform_devs[] __initdata = {
 #ifdef CONFIG_STE_DMA40
 static struct stedma40_chan_cfg ssp0_dma_cfg_rx = {
        .mode = STEDMA40_MODE_LOGICAL,
-        .dir = STEDMA40_PERIPH_TO_MEM,
+        .dir = DMA_DEV_TO_MEM,
-        .src_dev_type =  DB8500_DMA_DEV8_SSP0_RX,
+        .dev_type = DB8500_DMA_DEV8_SSP0,
-        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-        .src_info.data_width = STEDMA40_BYTE_WIDTH,
-        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
 };
 static struct stedma40_chan_cfg ssp0_dma_cfg_tx = {
        .mode = STEDMA40_MODE_LOGICAL,
-        .dir = STEDMA40_MEM_TO_PERIPH,
+        .dir = DMA_MEM_TO_DEV,
-        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+        .dev_type = DB8500_DMA_DEV8_SSP0,
-        .dst_dev_type = DB8500_DMA_DEV8_SSP0_TX,
-        .src_info.data_width = STEDMA40_BYTE_WIDTH,
-        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
 };
 #endif
@@ -511,56 +481,38 @@ static void __init mop500_spi_init(struct device *parent)
 #ifdef CONFIG_STE_DMA40
 static struct stedma40_chan_cfg uart0_dma_cfg_rx = {
        .mode = STEDMA40_MODE_LOGICAL,
-        .dir = STEDMA40_PERIPH_TO_MEM,
+        .dir = DMA_DEV_TO_MEM,
-        .src_dev_type =  DB8500_DMA_DEV13_UART0_RX,
+        .dev_type = DB8500_DMA_DEV13_UART0,
-        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-        .src_info.data_width = STEDMA40_BYTE_WIDTH,
-        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
 };
 static struct stedma40_chan_cfg uart0_dma_cfg_tx = {
        .mode = STEDMA40_MODE_LOGICAL,
-        .dir = STEDMA40_MEM_TO_PERIPH,
+        .dir = DMA_MEM_TO_DEV,
-        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+        .dev_type = DB8500_DMA_DEV13_UART0,
-        .dst_dev_type = DB8500_DMA_DEV13_UART0_TX,
-        .src_info.data_width = STEDMA40_BYTE_WIDTH,
-        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
 };
 static struct stedma40_chan_cfg uart1_dma_cfg_rx = {
        .mode = STEDMA40_MODE_LOGICAL,
-        .dir = STEDMA40_PERIPH_TO_MEM,
+        .dir = DMA_DEV_TO_MEM,
-        .src_dev_type =  DB8500_DMA_DEV12_UART1_RX,
+        .dev_type = DB8500_DMA_DEV12_UART1,
-        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-        .src_info.data_width = STEDMA40_BYTE_WIDTH,
-        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
 };
 static struct stedma40_chan_cfg uart1_dma_cfg_tx = {
        .mode = STEDMA40_MODE_LOGICAL,
-        .dir = STEDMA40_MEM_TO_PERIPH,
+        .dir = DMA_MEM_TO_DEV,
-        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+        .dev_type = DB8500_DMA_DEV12_UART1,
-        .dst_dev_type = DB8500_DMA_DEV12_UART1_TX,
-        .src_info.data_width = STEDMA40_BYTE_WIDTH,
-        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
 };
 static struct stedma40_chan_cfg uart2_dma_cfg_rx = {
        .mode = STEDMA40_MODE_LOGICAL,
-        .dir = STEDMA40_PERIPH_TO_MEM,
+        .dir = DMA_DEV_TO_MEM,
-        .src_dev_type =  DB8500_DMA_DEV11_UART2_RX,
+        .dev_type = DB8500_DMA_DEV11_UART2,
-        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-        .src_info.data_width = STEDMA40_BYTE_WIDTH,
-        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
 };
 static struct stedma40_chan_cfg uart2_dma_cfg_tx = {
        .mode = STEDMA40_MODE_LOGICAL,
-        .dir = STEDMA40_MEM_TO_PERIPH,
+        .dir = DMA_MEM_TO_DEV,
-        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+        .dev_type = DB8500_DMA_DEV11_UART2,
-        .dst_dev_type = DB8500_DMA_DEV11_UART2_TX,
-        .src_info.data_width = STEDMA40_BYTE_WIDTH,
-        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
 };
 #endif
@@ -674,7 +626,7 @@ static void __init snowball_init_machine(void)
        mop500_audio_init(parent);
        mop500_uart_init(parent);
-        mop500_snowball_ethernet_clock_enable();
+        u8500_cryp1_hash1_init(parent);
        /* This board has full regulator constraints */
        regulator_has_full_constraints();
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index 49514b825034..d6fab166cbf1 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -93,6 +93,7 @@ extern struct amba_pl011_data uart0_plat;
 extern struct amba_pl011_data uart1_plat;
 extern struct amba_pl011_data uart2_plat;
 extern struct pl022_ssp_controller ssp0_plat;
+extern struct stedma40_platform_data dma40_plat_data;
 extern void mop500_sdi_init(struct device *parent);
 extern void snowball_sdi_init(struct device *parent);
@@ -104,7 +105,6 @@ void __init mop500_pinmaps_init(void);
 void __init snowball_pinmaps_init(void);
 void __init hrefv60_pinmaps_init(void);
 void mop500_audio_init(struct device *parent);
-void mop500_snowball_ethernet_clock_enable(void);
 int __init mop500_uib_init(void);
 void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c
index f58615b5c601..82ccf1d98735 100644
--- a/arch/arm/mach-ux500/cache-l2x0.c
+++ b/arch/arm/mach-ux500/cache-l2x0.c
@@ -42,7 +42,8 @@ static int __init ux500_l2x0_init(void)
        if (cpu_is_u8500_family() || cpu_is_ux540_family())
                l2x0_base = __io_address(U8500_L2CC_BASE);
        else
-                ux500_unknown_soc();
+                /* Non-Ux500 platform */
+                return -ENODEV;
        /* Unlock before init */
        ux500_l2x0_unlock();
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 46cca52890bc..12eee8167525 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -162,26 +162,15 @@ static void __init db8500_add_gpios(struct device *parent)
        dbx500_add_pinctrl(parent, "pinctrl-db8500", U8500_PRCMU_BASE);
 }
-static int usb_db8500_rx_dma_cfg[] = {
+static int usb_db8500_dma_cfg[] = {
-        DB8500_DMA_DEV38_USB_OTG_IEP_1_9,
+        DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9,
-        DB8500_DMA_DEV37_USB_OTG_IEP_2_10,
+        DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10,
-        DB8500_DMA_DEV36_USB_OTG_IEP_3_11,
+        DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11,
-        DB8500_DMA_DEV19_USB_OTG_IEP_4_12,
+        DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12,
-        DB8500_DMA_DEV18_USB_OTG_IEP_5_13,
+        DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13,
-        DB8500_DMA_DEV17_USB_OTG_IEP_6_14,
+        DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14,
-        DB8500_DMA_DEV16_USB_OTG_IEP_7_15,
+        DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15,
-        DB8500_DMA_DEV39_USB_OTG_IEP_8
+        DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8
-};
-static int usb_db8500_tx_dma_cfg[] = {
-        DB8500_DMA_DEV38_USB_OTG_OEP_1_9,
-        DB8500_DMA_DEV37_USB_OTG_OEP_2_10,
-        DB8500_DMA_DEV36_USB_OTG_OEP_3_11,
-        DB8500_DMA_DEV19_USB_OTG_OEP_4_12,
-        DB8500_DMA_DEV18_USB_OTG_OEP_5_13,
-        DB8500_DMA_DEV17_USB_OTG_OEP_6_14,
-        DB8500_DMA_DEV16_USB_OTG_OEP_7_15,
-        DB8500_DMA_DEV39_USB_OTG_OEP_8
 };
 static const char *db8500_read_soc_id(void)
@@ -215,7 +204,7 @@ struct device * __init u8500_init_devices(void)
        db8500_add_rtc(parent);
        db8500_add_gpios(parent);
-        db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);
+        db8500_add_usb(parent, usb_db8500_dma_cfg, usb_db8500_dma_cfg);
        for (i = 0; i < ARRAY_SIZE(platform_devs); i++)
                platform_devs[i]->dev.parent = parent;
@@ -226,34 +215,13 @@ struct device * __init u8500_init_devices(void)
 }
 #ifdef CONFIG_MACH_UX500_DT
-/* TODO: Once all pieces are DT:ed, remove completely. */
-static struct device * __init u8500_of_init_devices(void)
-{
-        struct device *parent = db8500_soc_device_init();
-        db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);
-        u8500_dma40_device.dev.parent = parent;
-        /*
-         * Devices to be DT:ed:
-         *   u8500_dma40_device  = todo
-         *   db8500_pmu_device   = done
-         *   db8500_prcmu_device = done
-         */
-        platform_device_register(&u8500_dma40_device);
-        return parent;
-}
 static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
        /* Requires call-back bindings. */
        OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
        /* Requires DMA bindings. */
-        OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat),
+        OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", NULL),
-        OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat),
+        OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", NULL),
-        OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat),
+        OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", NULL),
        OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0",  &ssp0_plat),
        OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0",  &mop500_sdi0_data),
        OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1",  &mop500_sdi1_data),
@@ -274,11 +242,16 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
        OF_DEV_AUXDATA("st,nomadik-i2c", 0x80128000, "nmk-i2c.2", NULL),
        OF_DEV_AUXDATA("st,nomadik-i2c", 0x80110000, "nmk-i2c.3", NULL),
        OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL),
+        OF_DEV_AUXDATA("stericsson,db8500-musb", 0xa03e0000, "musb-ux500.0", NULL),
        OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu",
                        &db8500_prcmu_pdata),
        OF_DEV_AUXDATA("smsc,lan9115", 0x50000000, "smsc911x.0", NULL),
+        OF_DEV_AUXDATA("stericsson,ux500-cryp", 0xa03cb000, "cryp1", NULL),
+        OF_DEV_AUXDATA("stericsson,ux500-hash", 0xa03c2000, "hash1", NULL),
+        OF_DEV_AUXDATA("stericsson,snd-soc-mop500", 0, "snd-soc-mop500.0",
+                        NULL),
        /* Requires device name bindings. */
-        OF_DEV_AUXDATA("stericsson,nmk-pinctrl", U8500_PRCMU_BASE,
+        OF_DEV_AUXDATA("stericsson,db8500-pinctrl", U8500_PRCMU_BASE,
                "pinctrl-db8500", NULL),
        /* Requires clock name and DMA bindings. */
        OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000,
@@ -289,6 +262,18 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
                "ux500-msp-i2s.2", &msp2_platform_data),
        OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000,
                "ux500-msp-i2s.3", &msp3_platform_data),
+        /* Requires clock name bindings and channel address lookup table. */
+        OF_DEV_AUXDATA("stericsson,db8500-dma40", 0x801C0000, "dma40.0", NULL),
+        {},
+};
+static struct of_dev_auxdata u8540_auxdata_lookup[] __initdata = {
+        /* Requires DMA bindings. */
+        OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", NULL),
+        OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", NULL),
+        OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", NULL),
+        OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu",
+                        &db8500_prcmu_pdata),
        {},
 };
@@ -302,24 +287,25 @@ static const struct of_device_id u8500_local_bus_nodes[] = {
 static void __init u8500_init_machine(void)
 {
-        struct device *parent = NULL;
+        struct device *parent = db8500_soc_device_init();
        /* Pinmaps must be in place before devices register */
        if (of_machine_is_compatible("st-ericsson,mop500"))
                mop500_pinmaps_init();
        else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
                snowball_pinmaps_init();
-                mop500_snowball_ethernet_clock_enable();
        } else if (of_machine_is_compatible("st-ericsson,hrefv60+"))
                hrefv60_pinmaps_init();
        else if (of_machine_is_compatible("st-ericsson,ccu9540")) {}
                /* TODO: Add pinmaps for ccu9540 board. */
-        /* TODO: Export SoC, USB, cpu-freq and DMA40 */
+        /* automatically probe child nodes of dbx5x0 devices */
-        parent = u8500_of_init_devices();
+        if (of_machine_is_compatible("st-ericsson,u8540"))
+                of_platform_populate(NULL, u8500_local_bus_nodes,
-        /* automatically probe child nodes of db8500 device */
+                                     u8540_auxdata_lookup, parent);
-        of_platform_populate(NULL, u8500_local_bus_nodes, u8500_auxdata_lookup, parent);
+        else
+                of_platform_populate(NULL, u8500_local_bus_nodes,
+                                     u8500_auxdata_lookup, parent);
 }
 static const char * stericsson_dt_platform_compat[] = {
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index b6145ea51641..e6fb0239151b 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -76,13 +76,15 @@ void __init ux500_init_irq(void)
        } else if (cpu_is_u9540()) {
                prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1);
                ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1);
-                u8500_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
+                u9540_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
                               U8500_CLKRST3_BASE, U8500_CLKRST5_BASE,
                               U8500_CLKRST6_BASE);
        } else if (cpu_is_u8540()) {
                prcmu_early_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1);
                ux500_pm_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1);
-                u8540_clk_init();
+                u8540_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
+                               U8500_CLKRST3_BASE, U8500_CLKRST5_BASE,
+                               U8500_CLKRST6_BASE);
        }
 }
diff --git a/arch/arm/mach-ux500/db8500-regs.h b/arch/arm/mach-ux500/db8500-regs.h
index b2d7a0b98629..27399553c841 100644
--- a/arch/arm/mach-ux500/db8500-regs.h
+++ b/arch/arm/mach-ux500/db8500-regs.h
@@ -102,7 +102,6 @@
 #define U8500_PRCMU_BASE        (U8500_PER4_BASE + 0x07000)
 #define U9540_DMC1_BASE         (U8500_PER4_BASE + 0x0A000)
 #define U8500_PRCMU_TCDM_BASE   (U8500_PER4_BASE + 0x68000)
-#define U9540_PRCMU_TCDM_BASE   (U8500_PER4_BASE + 0x6A000)
 #define U8500_PRCMU_TCPM_BASE   (U8500_PER4_BASE + 0x60000)
 #define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338)
 #define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450)
@@ -184,7 +183,7 @@
 #define U8500_IO_VIRTUAL        0xf0000000
 #define U8500_IO_PHYSICAL       0xa0000000
 /* This is where we map in the ROM to check ASIC IDs */
-#define UX500_VIRT_ROM          0xf0000000
+#define UX500_VIRT_ROM          IOMEM(0xf0000000)
 /* This macro is used in assembly, so no cast */
 #define IO_ADDRESS(x)           \
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index 1cf94ce0feec..516a6f57d159 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -42,128 +42,7 @@ static struct resource dma40_resources[] = {
        }
 };
-/* Default configuration for physcial memcpy */
+struct stedma40_platform_data dma40_plat_data = {
-struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
-        .mode = STEDMA40_MODE_PHYSICAL,
-        .dir = STEDMA40_MEM_TO_MEM,
-        .src_info.data_width = STEDMA40_BYTE_WIDTH,
-        .src_info.psize = STEDMA40_PSIZE_PHY_1,
-        .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
-        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
-        .dst_info.psize = STEDMA40_PSIZE_PHY_1,
-        .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
-};
-/* Default configuration for logical memcpy */
-struct stedma40_chan_cfg dma40_memcpy_conf_log = {
-        .dir = STEDMA40_MEM_TO_MEM,
-        .src_info.data_width = STEDMA40_BYTE_WIDTH,
-        .src_info.psize = STEDMA40_PSIZE_LOG_1,
-        .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
-        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
-        .dst_info.psize = STEDMA40_PSIZE_LOG_1,
-        .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
-};
-/*
- * Mapping between destination event lines and physical device address.
- * The event line is tied to a device and therefore the address is constant.
- * When the address comes from a primecell it will be configured in runtime
- * and we set the address to -1 as a placeholder.
- */
-static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV] = {
-        /* MUSB - these will be runtime-reconfigured */
-        [DB8500_DMA_DEV39_USB_OTG_OEP_8] = -1,
-        [DB8500_DMA_DEV16_USB_OTG_OEP_7_15] = -1,
-        [DB8500_DMA_DEV17_USB_OTG_OEP_6_14] = -1,
-        [DB8500_DMA_DEV18_USB_OTG_OEP_5_13] = -1,
-        [DB8500_DMA_DEV19_USB_OTG_OEP_4_12] = -1,
-        [DB8500_DMA_DEV36_USB_OTG_OEP_3_11] = -1,
-        [DB8500_DMA_DEV37_USB_OTG_OEP_2_10] = -1,
-        [DB8500_DMA_DEV38_USB_OTG_OEP_1_9] = -1,
-        /* PrimeCells - run-time configured */
-        [DB8500_DMA_DEV0_SPI0_TX] = -1,
-        [DB8500_DMA_DEV1_SD_MMC0_TX] = -1,
-        [DB8500_DMA_DEV2_SD_MMC1_TX] = -1,
-        [DB8500_DMA_DEV3_SD_MMC2_TX] = -1,
-        [DB8500_DMA_DEV8_SSP0_TX] = -1,
-        [DB8500_DMA_DEV9_SSP1_TX] = -1,
-        [DB8500_DMA_DEV11_UART2_TX] = -1,
-        [DB8500_DMA_DEV12_UART1_TX] = -1,
-        [DB8500_DMA_DEV13_UART0_TX] = -1,
-        [DB8500_DMA_DEV28_SD_MM2_TX] = -1,
-        [DB8500_DMA_DEV29_SD_MM0_TX] = -1,
-        [DB8500_DMA_DEV32_SD_MM1_TX] = -1,
-        [DB8500_DMA_DEV33_SPI2_TX] = -1,
-        [DB8500_DMA_DEV35_SPI1_TX] = -1,
-        [DB8500_DMA_DEV40_SPI3_TX] = -1,
-        [DB8500_DMA_DEV41_SD_MM3_TX] = -1,
-        [DB8500_DMA_DEV42_SD_MM4_TX] = -1,
-        [DB8500_DMA_DEV43_SD_MM5_TX] = -1,
-        [DB8500_DMA_DEV14_MSP2_TX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
-        [DB8500_DMA_DEV30_MSP1_TX] = U8500_MSP1_BASE + MSP_TX_RX_REG_OFFSET,
-        [DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
-        [DB8500_DMA_DEV48_CAC1_TX] = U8500_CRYP1_BASE + CRYP1_TX_REG_OFFSET,
-        [DB8500_DMA_DEV50_HAC1_TX] = U8500_HASH1_BASE + HASH1_TX_REG_OFFSET,
-};
-/* Mapping between source event lines and physical device address */
-static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV] = {
-        /* MUSB - these will be runtime-reconfigured */
-        [DB8500_DMA_DEV39_USB_OTG_IEP_8] = -1,
-        [DB8500_DMA_DEV16_USB_OTG_IEP_7_15] = -1,
-        [DB8500_DMA_DEV17_USB_OTG_IEP_6_14] = -1,
-        [DB8500_DMA_DEV18_USB_OTG_IEP_5_13] = -1,
-        [DB8500_DMA_DEV19_USB_OTG_IEP_4_12] = -1,
-        [DB8500_DMA_DEV36_USB_OTG_IEP_3_11] = -1,
-        [DB8500_DMA_DEV37_USB_OTG_IEP_2_10] = -1,
-        [DB8500_DMA_DEV38_USB_OTG_IEP_1_9] = -1,
-        /* PrimeCells */
-        [DB8500_DMA_DEV0_SPI0_RX] = -1,
-        [DB8500_DMA_DEV1_SD_MMC0_RX] = -1,
-        [DB8500_DMA_DEV2_SD_MMC1_RX] = -1,
-        [DB8500_DMA_DEV3_SD_MMC2_RX] = -1,
-        [DB8500_DMA_DEV8_SSP0_RX] = -1,
-        [DB8500_DMA_DEV9_SSP1_RX] = -1,
-        [DB8500_DMA_DEV11_UART2_RX] = -1,
-        [DB8500_DMA_DEV12_UART1_RX] = -1,
-        [DB8500_DMA_DEV13_UART0_RX] = -1,
-        [DB8500_DMA_DEV28_SD_MM2_RX] = -1,
-        [DB8500_DMA_DEV29_SD_MM0_RX] = -1,
-        [DB8500_DMA_DEV32_SD_MM1_RX] = -1,
-        [DB8500_DMA_DEV33_SPI2_RX] = -1,
-        [DB8500_DMA_DEV35_SPI1_RX] = -1,
-        [DB8500_DMA_DEV40_SPI3_RX] = -1,
-        [DB8500_DMA_DEV41_SD_MM3_RX] = -1,
-        [DB8500_DMA_DEV42_SD_MM4_RX] = -1,
-        [DB8500_DMA_DEV43_SD_MM5_RX] = -1,
-        [DB8500_DMA_DEV14_MSP2_RX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
-        [DB8500_DMA_DEV30_MSP3_RX] = U8500_MSP3_BASE + MSP_TX_RX_REG_OFFSET,
-        [DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
-        [DB8500_DMA_DEV48_CAC1_RX] = U8500_CRYP1_BASE + CRYP1_RX_REG_OFFSET,
-};
-/* Reserved event lines for memcpy only */
-static int dma40_memcpy_event[] = {
-        DB8500_DMA_MEMCPY_TX_0,
-        DB8500_DMA_MEMCPY_TX_1,
-        DB8500_DMA_MEMCPY_TX_2,
-        DB8500_DMA_MEMCPY_TX_3,
-        DB8500_DMA_MEMCPY_TX_4,
-        DB8500_DMA_MEMCPY_TX_5,
-};
-static struct stedma40_platform_data dma40_plat_data = {
-        .dev_len = DB8500_DMA_NR_DEV,
-        .dev_rx = dma40_rx_map,
-        .dev_tx = dma40_tx_map,
-        .memcpy = dma40_memcpy_event,
-        .memcpy_len = ARRAY_SIZE(dma40_memcpy_event),
-        .memcpy_conf_phy = &dma40_memcpy_conf_phy,
-        .memcpy_conf_log = &dma40_memcpy_conf_log,
        .disabled_channels = {-1},
 };
@@ -227,7 +106,7 @@ static struct resource db8500_prcmu_res[] = {
        {
                .name  = "prcmu-tcpm",
                .start = U8500_PRCMU_TCPM_BASE,
-                .end   = U8500_PRCMU_TCPM_BASE + SZ_4K - 1,
+                .end   = U8500_PRCMU_TCPM_BASE + SZ_32K - 1,
                .flags = IORESOURCE_MEM,
        },
 };
diff --git a/arch/arm/mach-ux500/id.c b/arch/arm/mach-ux500/id.c
index 0d33d1a06955..392f2fdb37d0 100644
--- a/arch/arm/mach-ux500/id.c
+++ b/arch/arm/mach-ux500/id.c
@@ -21,11 +21,11 @@
 struct dbx500_asic_id dbx500_id;
-static unsigned int ux500_read_asicid(phys_addr_t addr)
+static unsigned int __init ux500_read_asicid(phys_addr_t addr)
 {
        phys_addr_t base = addr & ~0xfff;
        struct map_desc desc = {
-                .virtual        = UX500_VIRT_ROM,
+                .virtual        = (unsigned long)UX500_VIRT_ROM,
                .pfn            = __phys_to_pfn(base),
                .length         = SZ_16K,
                .type           = MT_DEVICE,
@@ -37,7 +37,7 @@ static unsigned int ux500_read_asicid(phys_addr_t addr)
        local_flush_tlb_all();
        flush_cache_all();
-        return readl(IOMEM(UX500_VIRT_ROM + (addr & 0xfff)));
+        return readl(UX500_VIRT_ROM + (addr & 0xfff));
 }
 static void ux500_print_soc_info(unsigned int asicid)
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index 14d90469392f..1f296e796a4f 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -54,7 +54,7 @@ static void __iomem *scu_base_addr(void)
 static DEFINE_SPINLOCK(boot_lock);
-static void __cpuinit ux500_secondary_init(unsigned int cpu)
+static void ux500_secondary_init(unsigned int cpu)
 {
        /*
         * let the primary processor know we're out of the
@@ -69,7 +69,7 @@ static void __cpuinit ux500_secondary_init(unsigned int cpu)
        spin_unlock(&boot_lock);
 }
-static int __cpuinit ux500_boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int ux500_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
        unsigned long timeout;
diff --git a/arch/arm/mach-ux500/ste-dma40-db8500.h b/arch/arm/mach-ux500/ste-dma40-db8500.h
index a616419bea76..0296ae5b0fd9 100644
--- a/arch/arm/mach-ux500/ste-dma40-db8500.h
+++ b/arch/arm/mach-ux500/ste-dma40-db8500.h
@@ -12,133 +12,74 @@
 #define DB8500_DMA_NR_DEV 64
-enum dma_src_dev_type {
+/*
-        DB8500_DMA_DEV0_SPI0_RX = 0,
+ * Unless otherwise specified, all channels numbers are used for
-        DB8500_DMA_DEV1_SD_MMC0_RX = 1,
+ * TX & RX, and can be used for either source or destination
-        DB8500_DMA_DEV2_SD_MMC1_RX = 2,
+ * channels.
-        DB8500_DMA_DEV3_SD_MMC2_RX = 3,
+ */
-        DB8500_DMA_DEV4_I2C1_RX = 4,
+enum dma_dev_type {
-        DB8500_DMA_DEV5_I2C3_RX = 5,
+        DB8500_DMA_DEV0_SPI0 = 0,
-        DB8500_DMA_DEV6_I2C2_RX = 6,
+        DB8500_DMA_DEV1_SD_MMC0 = 1,
-        DB8500_DMA_DEV7_I2C4_RX = 7, /* Only on V1 and later */
+        DB8500_DMA_DEV2_SD_MMC1 = 2,
-        DB8500_DMA_DEV8_SSP0_RX = 8,
+        DB8500_DMA_DEV3_SD_MMC2 = 3,
-        DB8500_DMA_DEV9_SSP1_RX = 9,
+        DB8500_DMA_DEV4_I2C1 = 4,
-        DB8500_DMA_DEV10_MCDE_RX = 10,
+        DB8500_DMA_DEV5_I2C3 = 5,
-        DB8500_DMA_DEV11_UART2_RX = 11,
+        DB8500_DMA_DEV6_I2C2 = 6,
-        DB8500_DMA_DEV12_UART1_RX = 12,
+        DB8500_DMA_DEV7_I2C4 = 7,                       /* Only on V1 and later */
-        DB8500_DMA_DEV13_UART0_RX = 13,
+        DB8500_DMA_DEV8_SSP0 = 8,
-        DB8500_DMA_DEV14_MSP2_RX = 14,
+        DB8500_DMA_DEV9_SSP1 = 9,
-        DB8500_DMA_DEV15_I2C0_RX = 15,
+        DB8500_DMA_DEV10_MCDE_RX = 10,                  /* RX only */
-        DB8500_DMA_DEV16_USB_OTG_IEP_7_15 = 16,
+        DB8500_DMA_DEV11_UART2 = 11,
-        DB8500_DMA_DEV17_USB_OTG_IEP_6_14 = 17,
+        DB8500_DMA_DEV12_UART1 = 12,
-        DB8500_DMA_DEV18_USB_OTG_IEP_5_13 = 18,
+        DB8500_DMA_DEV13_UART0 = 13,
-        DB8500_DMA_DEV19_USB_OTG_IEP_4_12 = 19,
+        DB8500_DMA_DEV14_MSP2 = 14,
-        DB8500_DMA_DEV20_SLIM0_CH0_RX_HSI_RX_CH0 = 20,
+        DB8500_DMA_DEV15_I2C0 = 15,
-        DB8500_DMA_DEV21_SLIM0_CH1_RX_HSI_RX_CH1 = 21,
+        DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15 = 16,
-        DB8500_DMA_DEV22_SLIM0_CH2_RX_HSI_RX_CH2 = 22,
+        DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14 = 17,
-        DB8500_DMA_DEV23_SLIM0_CH3_RX_HSI_RX_CH3 = 23,
+        DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13 = 18,
-        DB8500_DMA_DEV24_SRC_SXA0_RX_TX = 24,
+        DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12 = 19,
-        DB8500_DMA_DEV25_SRC_SXA1_RX_TX = 25,
+        DB8500_DMA_DEV20_SLIM0_CH0_HSI_CH0 = 20,
-        DB8500_DMA_DEV26_SRC_SXA2_RX_TX = 26,
+        DB8500_DMA_DEV21_SLIM0_CH1_HSI_CH1 = 21,
-        DB8500_DMA_DEV27_SRC_SXA3_RX_TX = 27,
+        DB8500_DMA_DEV22_SLIM0_CH2_HSI_CH2 = 22,
-        DB8500_DMA_DEV28_SD_MM2_RX = 28,
+        DB8500_DMA_DEV23_SLIM0_CH3_HSI_CH3 = 23,
-        DB8500_DMA_DEV29_SD_MM0_RX = 29,
+        DB8500_DMA_DEV24_SXA0 = 24,
-        DB8500_DMA_DEV30_MSP1_RX = 30,
+        DB8500_DMA_DEV25_SXA1 = 25,
+        DB8500_DMA_DEV26_SXA2 = 26,
+        DB8500_DMA_DEV27_SXA3 = 27,
+        DB8500_DMA_DEV28_SD_MM2 = 28,
+        DB8500_DMA_DEV29_SD_MM0 = 29,
+        DB8500_DMA_DEV30_MSP1 = 30,
        /* On DB8500v2, MSP3 RX replaces MSP1 RX */
-        DB8500_DMA_DEV30_MSP3_RX = 30,
+        DB8500_DMA_DEV30_MSP3 = 30,
-        DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX = 31,
+        DB8500_DMA_DEV31_MSP0_SLIM0_CH0 = 31,
-        DB8500_DMA_DEV32_SD_MM1_RX = 32,
+        DB8500_DMA_DEV32_SD_MM1 = 32,
-        DB8500_DMA_DEV33_SPI2_RX = 33,
+        DB8500_DMA_DEV33_SPI2 = 33,
-        DB8500_DMA_DEV34_I2C3_RX2 = 34,
+        DB8500_DMA_DEV34_I2C3_RX2_TX2 = 34,
-        DB8500_DMA_DEV35_SPI1_RX = 35,
+        DB8500_DMA_DEV35_SPI1 = 35,
-        DB8500_DMA_DEV36_USB_OTG_IEP_3_11 = 36,
+        DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11 = 36,
-        DB8500_DMA_DEV37_USB_OTG_IEP_2_10 = 37,
+        DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10 = 37,
-        DB8500_DMA_DEV38_USB_OTG_IEP_1_9 = 38,
+        DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9 = 38,
-        DB8500_DMA_DEV39_USB_OTG_IEP_8 = 39,
+        DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8 = 39,
-        DB8500_DMA_DEV40_SPI3_RX = 40,
+        DB8500_DMA_DEV40_SPI3 = 40,
-        DB8500_DMA_DEV41_SD_MM3_RX = 41,
+        DB8500_DMA_DEV41_SD_MM3 = 41,
-        DB8500_DMA_DEV42_SD_MM4_RX = 42,
+        DB8500_DMA_DEV42_SD_MM4 = 42,
-        DB8500_DMA_DEV43_SD_MM5_RX = 43,
+        DB8500_DMA_DEV43_SD_MM5 = 43,
-        DB8500_DMA_DEV44_SRC_SXA4_RX_TX = 44,
+        DB8500_DMA_DEV44_SXA4 = 44,
-        DB8500_DMA_DEV45_SRC_SXA5_RX_TX = 45,
+        DB8500_DMA_DEV45_SXA5 = 45,
-        DB8500_DMA_DEV46_SLIM0_CH8_RX_SRC_SXA6_RX_TX = 46,
+        DB8500_DMA_DEV46_SLIM0_CH8_SRC_SXA6 = 46,
-        DB8500_DMA_DEV47_SLIM0_CH9_RX_SRC_SXA7_RX_TX = 47,
+        DB8500_DMA_DEV47_SLIM0_CH9_SRC_SXA7 = 47,
-        DB8500_DMA_DEV48_CAC1_RX = 48,
+        DB8500_DMA_DEV48_CAC1 = 48,
-        /* 49, 50 and 51 are not used */
+        DB8500_DMA_DEV49_CAC1_TX_HAC1_TX = 49,          /* TX only */
-        DB8500_DMA_DEV52_SLIM0_CH4_RX_HSI_RX_CH4 = 52,
+        DB8500_DMA_DEV50_HAC1_TX = 50,                  /* TX only */
-        DB8500_DMA_DEV53_SLIM0_CH5_RX_HSI_RX_CH5 = 53,
+        DB8500_DMA_MEMCPY_TX_0 = 51,                    /* TX only */
-        DB8500_DMA_DEV54_SLIM0_CH6_RX_HSI_RX_CH6 = 54,
+        DB8500_DMA_DEV52_SLIM0_CH4_HSI_CH4 = 52,
-        DB8500_DMA_DEV55_SLIM0_CH7_RX_HSI_RX_CH7 = 55,
+        DB8500_DMA_DEV53_SLIM0_CH5_HSI_CH5 = 53,
-        /* 56, 57, 58, 59 and 60 are not used */
+        DB8500_DMA_DEV54_SLIM0_CH6_HSI_CH6 = 54,
-        DB8500_DMA_DEV61_CAC0_RX = 61,
+        DB8500_DMA_DEV55_SLIM0_CH7_HSI_CH7 = 55,
-        /* 62 and 63 are not used */
+        /* 56 -> 60 are channels reserved for memcpy only */
-};
+        DB8500_DMA_DEV61_CAC0 = 61,
+        DB8500_DMA_DEV62_CAC0_TX_HAC0_TX = 62,          /* TX only */
-enum dma_dest_dev_type {
+        DB8500_DMA_DEV63_HAC0_TX = 63,                  /* TX only */
-        DB8500_DMA_DEV0_SPI0_TX = 0,
-        DB8500_DMA_DEV1_SD_MMC0_TX = 1,
-        DB8500_DMA_DEV2_SD_MMC1_TX = 2,
-        DB8500_DMA_DEV3_SD_MMC2_TX = 3,
-        DB8500_DMA_DEV4_I2C1_TX = 4,
-        DB8500_DMA_DEV5_I2C3_TX = 5,
-        DB8500_DMA_DEV6_I2C2_TX = 6,
-        DB8500_DMA_DEV7_I2C4_TX = 7, /* Only on V1 and later */
-        DB8500_DMA_DEV8_SSP0_TX = 8,
-        DB8500_DMA_DEV9_SSP1_TX = 9,
-        /* 10 is not used*/
-        DB8500_DMA_DEV11_UART2_TX = 11,
-        DB8500_DMA_DEV12_UART1_TX = 12,
-        DB8500_DMA_DEV13_UART0_TX = 13,
-        DB8500_DMA_DEV14_MSP2_TX = 14,
-        DB8500_DMA_DEV15_I2C0_TX = 15,
-        DB8500_DMA_DEV16_USB_OTG_OEP_7_15 = 16,
-        DB8500_DMA_DEV17_USB_OTG_OEP_6_14 = 17,
-        DB8500_DMA_DEV18_USB_OTG_OEP_5_13 = 18,
-        DB8500_DMA_DEV19_USB_OTG_OEP_4_12 = 19,
-        DB8500_DMA_DEV20_SLIM0_CH0_TX_HSI_TX_CH0 = 20,
-        DB8500_DMA_DEV21_SLIM0_CH1_TX_HSI_TX_CH1 = 21,
-        DB8500_DMA_DEV22_SLIM0_CH2_TX_HSI_TX_CH2 = 22,
-        DB8500_DMA_DEV23_SLIM0_CH3_TX_HSI_TX_CH3 = 23,
-        DB8500_DMA_DEV24_DST_SXA0_RX_TX = 24,
-        DB8500_DMA_DEV25_DST_SXA1_RX_TX = 25,
-        DB8500_DMA_DEV26_DST_SXA2_RX_TX = 26,
-        DB8500_DMA_DEV27_DST_SXA3_RX_TX = 27,
-        DB8500_DMA_DEV28_SD_MM2_TX = 28,
-        DB8500_DMA_DEV29_SD_MM0_TX = 29,
-        DB8500_DMA_DEV30_MSP1_TX = 30,
-        DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX = 31,
-        DB8500_DMA_DEV32_SD_MM1_TX = 32,
-        DB8500_DMA_DEV33_SPI2_TX = 33,
-        DB8500_DMA_DEV34_I2C3_TX2 = 34,
-        DB8500_DMA_DEV35_SPI1_TX = 35,
-        DB8500_DMA_DEV36_USB_OTG_OEP_3_11 = 36,
-        DB8500_DMA_DEV37_USB_OTG_OEP_2_10 = 37,
-        DB8500_DMA_DEV38_USB_OTG_OEP_1_9 = 38,
-        DB8500_DMA_DEV39_USB_OTG_OEP_8 = 39,
-        DB8500_DMA_DEV40_SPI3_TX = 40,
-        DB8500_DMA_DEV41_SD_MM3_TX = 41,
-        DB8500_DMA_DEV42_SD_MM4_TX = 42,
-        DB8500_DMA_DEV43_SD_MM5_TX = 43,
-        DB8500_DMA_DEV44_DST_SXA4_RX_TX = 44,
-        DB8500_DMA_DEV45_DST_SXA5_RX_TX = 45,
-        DB8500_DMA_DEV46_SLIM0_CH8_TX_DST_SXA6_RX_TX = 46,
-        DB8500_DMA_DEV47_SLIM0_CH9_TX_DST_SXA7_RX_TX = 47,
-        DB8500_DMA_DEV48_CAC1_TX  = 48,
-        DB8500_DMA_DEV49_CAC1_TX_HAC1_TX = 49,
-        DB8500_DMA_DEV50_HAC1_TX = 50,
-        DB8500_DMA_MEMCPY_TX_0 = 51,
-        DB8500_DMA_DEV52_SLIM1_CH4_TX_HSI_TX_CH4 = 52,
-        DB8500_DMA_DEV53_SLIM1_CH5_TX_HSI_TX_CH5 = 53,
-        DB8500_DMA_DEV54_SLIM1_CH6_TX_HSI_TX_CH6 = 54,
-        DB8500_DMA_DEV55_SLIM1_CH7_TX_HSI_TX_CH7 = 55,
-        DB8500_DMA_MEMCPY_TX_1 = 56,
-        DB8500_DMA_MEMCPY_TX_2 = 57,
-        DB8500_DMA_MEMCPY_TX_3 = 58,
-        DB8500_DMA_MEMCPY_TX_4 = 59,
-        DB8500_DMA_MEMCPY_TX_5 = 60,
-        DB8500_DMA_DEV61_CAC0_TX = 61,
-        DB8500_DMA_DEV62_CAC0_TX_HAC0_TX = 62,
-        DB8500_DMA_DEV63_HAC0_TX = 63,
 };
 #endif
diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c
index 2dfc72f7cd8a..b7bd8d3a5507 100644
--- a/arch/arm/mach-ux500/usb.c
+++ b/arch/arm/mach-ux500/usb.c
@@ -14,25 +14,15 @@
 #define MUSB_DMA40_RX_CH { \
                .mode = STEDMA40_MODE_LOGICAL, \
-                .dir = STEDMA40_PERIPH_TO_MEM, \
+                .dir = DMA_DEV_TO_MEM, \
-                .dst_dev_type = STEDMA40_DEV_DST_MEMORY, \
-                .src_info.data_width = STEDMA40_WORD_WIDTH, \
-                .dst_info.data_width = STEDMA40_WORD_WIDTH, \
-                .src_info.psize = STEDMA40_PSIZE_LOG_16, \
-                .dst_info.psize = STEDMA40_PSIZE_LOG_16, \
        }
 #define MUSB_DMA40_TX_CH { \
                .mode = STEDMA40_MODE_LOGICAL, \
-                .dir = STEDMA40_MEM_TO_PERIPH, \
+                .dir = DMA_MEM_TO_DEV, \
-                .src_dev_type = STEDMA40_DEV_SRC_MEMORY, \
-                .src_info.data_width = STEDMA40_WORD_WIDTH, \
-                .dst_info.data_width = STEDMA40_WORD_WIDTH, \
-                .src_info.psize = STEDMA40_PSIZE_LOG_16, \
-                .dst_info.psize = STEDMA40_PSIZE_LOG_16, \
        }
-static struct stedma40_chan_cfg musb_dma_rx_ch[UX500_MUSB_DMA_NUM_RX_CHANNELS]
+static struct stedma40_chan_cfg musb_dma_rx_ch[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS]
        = {
        MUSB_DMA40_RX_CH,
        MUSB_DMA40_RX_CH,
@@ -44,7 +34,7 @@ static struct stedma40_chan_cfg musb_dma_rx_ch[UX500_MUSB_DMA_NUM_RX_CHANNELS]
        MUSB_DMA40_RX_CH
 };
-static struct stedma40_chan_cfg musb_dma_tx_ch[UX500_MUSB_DMA_NUM_TX_CHANNELS]
+static struct stedma40_chan_cfg musb_dma_tx_ch[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS]
        = {
        MUSB_DMA40_TX_CH,
        MUSB_DMA40_TX_CH,
@@ -56,7 +46,7 @@ static struct stedma40_chan_cfg musb_dma_tx_ch[UX500_MUSB_DMA_NUM_TX_CHANNELS]
        MUSB_DMA40_TX_CH,
 };
-static void *ux500_dma_rx_param_array[UX500_MUSB_DMA_NUM_RX_CHANNELS] = {
+static void *ux500_dma_rx_param_array[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS] = {
        &musb_dma_rx_ch[0],
        &musb_dma_rx_ch[1],
        &musb_dma_rx_ch[2],
@@ -67,7 +57,7 @@ static void *ux500_dma_rx_param_array[UX500_MUSB_DMA_NUM_RX_CHANNELS] = {
        &musb_dma_rx_ch[7]
 };
-static void *ux500_dma_tx_param_array[UX500_MUSB_DMA_NUM_TX_CHANNELS] = {
+static void *ux500_dma_tx_param_array[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS] = {
        &musb_dma_tx_ch[0],
        &musb_dma_tx_ch[1],
        &musb_dma_tx_ch[2],
@@ -81,23 +71,11 @@ static void *ux500_dma_tx_param_array[UX500_MUSB_DMA_NUM_TX_CHANNELS] = {
 static struct ux500_musb_board_data musb_board_data = {
        .dma_rx_param_array = ux500_dma_rx_param_array,
        .dma_tx_param_array = ux500_dma_tx_param_array,
-        .num_rx_channels = UX500_MUSB_DMA_NUM_RX_CHANNELS,
-        .num_tx_channels = UX500_MUSB_DMA_NUM_TX_CHANNELS,
        .dma_filter = stedma40_filter,
 };
-static u64 ux500_musb_dmamask = DMA_BIT_MASK(32);
-static struct musb_hdrc_config musb_hdrc_config = {
-        .multipoint     = true,
-        .dyn_fifo       = true,
-        .num_eps        = 16,
-        .ram_bits       = 16,
-};
 static struct musb_hdrc_platform_data musb_platform_data = {
        .mode = MUSB_OTG,
-        .config = &musb_hdrc_config,
        .board_data = &musb_board_data,
 };
@@ -118,27 +96,26 @@ struct platform_device ux500_musb_device = {
        .id = 0,
        .dev = {
                .platform_data = &musb_platform_data,
-                .dma_mask = &ux500_musb_dmamask,
                .coherent_dma_mask = DMA_BIT_MASK(32),
        },
        .num_resources = ARRAY_SIZE(usb_resources),
        .resource = usb_resources,
 };
-static inline void ux500_usb_dma_update_rx_ch_config(int *src_dev_type)
+static inline void ux500_usb_dma_update_rx_ch_config(int *dev_type)
 {
        u32 idx;
-        for (idx = 0; idx < UX500_MUSB_DMA_NUM_RX_CHANNELS; idx++)
+        for (idx = 0; idx < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; idx++)
-                musb_dma_rx_ch[idx].src_dev_type = src_dev_type[idx];
+                musb_dma_rx_ch[idx].dev_type = dev_type[idx];
 }
-static inline void ux500_usb_dma_update_tx_ch_config(int *dst_dev_type)
+static inline void ux500_usb_dma_update_tx_ch_config(int *dev_type)
 {
        u32 idx;
-        for (idx = 0; idx < UX500_MUSB_DMA_NUM_TX_CHANNELS; idx++)
+        for (idx = 0; idx < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; idx++)
-                musb_dma_tx_ch[idx].dst_dev_type = dst_dev_type[idx];
+                musb_dma_tx_ch[idx].dev_type = dev_type[idx];
 }
 void ux500_add_usb(struct device *parent, resource_size_t base, int irq,
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 54bb80b012ac..3b0572f30d56 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -38,6 +38,7 @@
 #include <linux/clkdev.h>
 #include <linux/mtd/physmap.h>
 #include <linux/bitops.h>
+#include <linux/reboot.h>
 #include <asm/irq.h>
 #include <asm/hardware/arm_timer.h>
@@ -733,7 +734,7 @@ static void versatile_leds_event(led_event_t ledevt)
 }
 #endif  /* CONFIG_LEDS */
-void versatile_restart(char mode, const char *cmd)
+void versatile_restart(enum reboot_mode mode, const char *cmd)
 {
        void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
        u32 val;
diff --git a/arch/arm/mach-versatile/core.h b/arch/arm/mach-versatile/core.h
index 5c1b87d1da6b..f06d5768e428 100644
--- a/arch/arm/mach-versatile/core.h
+++ b/arch/arm/mach-versatile/core.h
@@ -24,13 +24,14 @@
 #include <linux/amba/bus.h>
 #include <linux/of_platform.h>
+#include <linux/reboot.h>
 extern void __init versatile_init(void);
 extern void __init versatile_init_early(void);
 extern void __init versatile_init_irq(void);
 extern void __init versatile_map_io(void);
 extern void versatile_timer_init(void);
-extern void versatile_restart(char, const char *);
+extern void versatile_restart(enum reboot_mode, const char *);
 extern unsigned int mmc_status(struct device *dev);
 #ifdef CONFIG_OF
 extern struct of_dev_auxdata versatile_auxdata_lookup[];
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 5907e10c37fd..b8bbabec6310 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -57,4 +57,13 @@ config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
 config ARCH_VEXPRESS_CA9X4
        bool "Versatile Express Cortex-A9x4 tile"
+config ARCH_VEXPRESS_DCSCB
+        bool "Dual Cluster System Control Block (DCSCB) support"
+        depends on MCPM
+        select ARM_CCI
+        help
+          Support for the Dual Cluster System Configuration Block (DCSCB).
+          This is needed to provide CPU and cluster power management
+          on RTSM implementing big.LITTLE.
 endmenu
diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
index 42703e8b4d3b..48ba89a8149f 100644
--- a/arch/arm/mach-vexpress/Makefile
+++ b/arch/arm/mach-vexpress/Makefile
@@ -6,5 +6,6 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
 obj-y                                   := v2m.o
 obj-$(CONFIG_ARCH_VEXPRESS_CA9X4)       += ct-ca9x4.o
+obj-$(CONFIG_ARCH_VEXPRESS_DCSCB)       += dcscb.o      dcscb_setup.o
 obj-$(CONFIG_SMP)                       += platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h
index f134cd4a85f1..bde4374ab6d5 100644
--- a/arch/arm/mach-vexpress/core.h
+++ b/arch/arm/mach-vexpress/core.h
@@ -6,6 +6,8 @@
 void vexpress_dt_smp_map_io(void);
+bool vexpress_smp_init_ops(void);
 extern struct smp_operations    vexpress_smp_ops;
 extern void vexpress_cpu_die(unsigned int cpu);
diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c
new file mode 100644
index 000000000000..16d57a8a9d5a
--- /dev/null
+++ b/arch/arm/mach-vexpress/dcscb.c
@@ -0,0 +1,253 @@
+/*
+ * arch/arm/mach-vexpress/dcscb.c - Dual Cluster System Configuration Block
+ *
+ * Created by:  Nicolas Pitre, May 2012
+ * Copyright:   (C) 2012-2013  Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/spinlock.h>
+#include <linux/errno.h>
+#include <linux/of_address.h>
+#include <linux/vexpress.h>
+#include <linux/arm-cci.h>
+#include <asm/mcpm.h>
+#include <asm/proc-fns.h>
+#include <asm/cacheflush.h>
+#include <asm/cputype.h>
+#include <asm/cp15.h>
+#define RST_HOLD0       0x0
+#define RST_HOLD1       0x4
+#define SYS_SWRESET     0x8
+#define RST_STAT0       0xc
+#define RST_STAT1       0x10
+#define EAG_CFG_R       0x20
+#define EAG_CFG_W       0x24
+#define KFC_CFG_R       0x28
+#define KFC_CFG_W       0x2c
+#define DCS_CFG_R       0x30
+/*
+ * We can't use regular spinlocks. In the switcher case, it is possible
+ * for an outbound CPU to call power_down() while its inbound counterpart
+ * is already live using the same logical CPU number which trips lockdep
+ * debugging.
+ */
+static arch_spinlock_t dcscb_lock = __ARCH_SPIN_LOCK_UNLOCKED;
+static void __iomem *dcscb_base;
+static int dcscb_use_count[4][2];
+static int dcscb_allcpus_mask[2];
+static int dcscb_power_up(unsigned int cpu, unsigned int cluster)
+{
+        unsigned int rst_hold, cpumask = (1 << cpu);
+        unsigned int all_mask = dcscb_allcpus_mask[cluster];
+        pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+        if (cpu >= 4 || cluster >= 2)
+                return -EINVAL;
+        /*
+         * Since this is called with IRQs enabled, and no arch_spin_lock_irq
+         * variant exists, we need to disable IRQs manually here.
+         */
+        local_irq_disable();
+        arch_spin_lock(&dcscb_lock);
+        dcscb_use_count[cpu][cluster]++;
+        if (dcscb_use_count[cpu][cluster] == 1) {
+                rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
+                if (rst_hold & (1 << 8)) {
+                        /* remove cluster reset and add individual CPU's reset */
+                        rst_hold &= ~(1 << 8);
+                        rst_hold |= all_mask;
+                }
+                rst_hold &= ~(cpumask | (cpumask << 4));
+                writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
+        } else if (dcscb_use_count[cpu][cluster] != 2) {
+                /*
+                 * The only possible values are:
+                 * 0 = CPU down
+                 * 1 = CPU (still) up
+                 * 2 = CPU requested to be up before it had a chance
+                 *     to actually make itself down.
+                 * Any other value is a bug.
+                 */
+                BUG();
+        }
+        arch_spin_unlock(&dcscb_lock);
+        local_irq_enable();
+        return 0;
+}
+static void dcscb_power_down(void)
+{
+        unsigned int mpidr, cpu, cluster, rst_hold, cpumask, all_mask;
+        bool last_man = false, skip_wfi = false;
+        mpidr = read_cpuid_mpidr();
+        cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+        cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+        cpumask = (1 << cpu);
+        all_mask = dcscb_allcpus_mask[cluster];
+        pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+        BUG_ON(cpu >= 4 || cluster >= 2);
+        __mcpm_cpu_going_down(cpu, cluster);
+        arch_spin_lock(&dcscb_lock);
+        BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
+        dcscb_use_count[cpu][cluster]--;
+        if (dcscb_use_count[cpu][cluster] == 0) {
+                rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
+                rst_hold |= cpumask;
+                if (((rst_hold | (rst_hold >> 4)) & all_mask) == all_mask) {
+                        rst_hold |= (1 << 8);
+                        last_man = true;
+                }
+                writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
+        } else if (dcscb_use_count[cpu][cluster] == 1) {
+                /*
+                 * A power_up request went ahead of us.
+                 * Even if we do not want to shut this CPU down,
+                 * the caller expects a certain state as if the WFI
+                 * was aborted.  So let's continue with cache cleaning.
+                 */
+                skip_wfi = true;
+        } else
+                BUG();
+        if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
+                arch_spin_unlock(&dcscb_lock);
+                /*
+                 * Flush all cache levels for this cluster.
+                 *
+                 * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need
+                 * a preliminary flush here for those CPUs.  At least, that's
+                 * the theory -- without the extra flush, Linux explodes on
+                 * RTSM (to be investigated).
+                 */
+                flush_cache_all();
+                set_cr(get_cr() & ~CR_C);
+                flush_cache_all();
+                /*
+                 * This is a harmless no-op.  On platforms with a real
+                 * outer cache this might either be needed or not,
+                 * depending on where the outer cache sits.
+                 */
+                outer_flush_all();
+                /* Disable local coherency by clearing the ACTLR "SMP" bit: */
+                set_auxcr(get_auxcr() & ~(1 << 6));
+                /*
+                 * Disable cluster-level coherency by masking
+                 * incoming snoops and DVM messages:
+                 */
+                cci_disable_port_by_cpu(mpidr);
+                __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
+        } else {
+                arch_spin_unlock(&dcscb_lock);
+                /*
+                 * Flush the local CPU cache.
+                 *
+                 * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need
+                 * a preliminary flush here for those CPUs.  At least, that's
+                 * the theory -- without the extra flush, Linux explodes on
+                 * RTSM (to be investigated).
+                 */
+                flush_cache_louis();
+                set_cr(get_cr() & ~CR_C);
+                flush_cache_louis();
+                /* Disable local coherency by clearing the ACTLR "SMP" bit: */
+                set_auxcr(get_auxcr() & ~(1 << 6));
+        }
+        __mcpm_cpu_down(cpu, cluster);
+        /* Now we are prepared for power-down, do it: */
+        dsb();
+        if (!skip_wfi)
+                wfi();
+        /* Not dead at this point?  Let our caller cope. */
+}
+static const struct mcpm_platform_ops dcscb_power_ops = {
+        .power_up       = dcscb_power_up,
+        .power_down     = dcscb_power_down,
+};
+static void __init dcscb_usage_count_init(void)
+{
+        unsigned int mpidr, cpu, cluster;
+        mpidr = read_cpuid_mpidr();
+        cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+        cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+        pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+        BUG_ON(cpu >= 4 || cluster >= 2);
+        dcscb_use_count[cpu][cluster] = 1;
+}
+extern void dcscb_power_up_setup(unsigned int affinity_level);
+static int __init dcscb_init(void)
+{
+        struct device_node *node;
+        unsigned int cfg;
+        int ret;
+        if (!cci_probed())
+                return -ENODEV;
+        node = of_find_compatible_node(NULL, NULL, "arm,rtsm,dcscb");
+        if (!node)
+                return -ENODEV;
+        dcscb_base = of_iomap(node, 0);
+        if (!dcscb_base)
+                return -EADDRNOTAVAIL;
+        cfg = readl_relaxed(dcscb_base + DCS_CFG_R);
+        dcscb_allcpus_mask[0] = (1 << (((cfg >> 16) >> (0 << 2)) & 0xf)) - 1;
+        dcscb_allcpus_mask[1] = (1 << (((cfg >> 16) >> (1 << 2)) & 0xf)) - 1;
+        dcscb_usage_count_init();
+        ret = mcpm_platform_register(&dcscb_power_ops);
+        if (!ret)
+                ret = mcpm_sync_init(dcscb_power_up_setup);
+        if (ret) {
+                iounmap(dcscb_base);
+                return ret;
+        }
+        pr_info("VExpress DCSCB support installed\n");
+        /*
+         * Future entries into the kernel can now go
+         * through the cluster entry vectors.
+         */
+        vexpress_flags_set(virt_to_phys(mcpm_entry_point));
+        return 0;
+}
+early_initcall(dcscb_init);
diff --git a/arch/arm/mach-vexpress/dcscb_setup.S b/arch/arm/mach-vexpress/dcscb_setup.S
new file mode 100644
index 000000000000..4bb7fbe0f621
--- /dev/null
+++ b/arch/arm/mach-vexpress/dcscb_setup.S
@@ -0,0 +1,38 @@
+/*
+ * arch/arm/include/asm/dcscb_setup.S
+ *
+ * Created by:  Dave Martin, 2012-06-22
+ * Copyright:   (C) 2012-2013  Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+ENTRY(dcscb_power_up_setup)
+        cmp     r0, #0                  @ check affinity level
+        beq     2f
+/*
+ * Enable cluster-level coherency, in preparation for turning on the MMU.
+ * The ACTLR SMP bit does not need to be set here, because cpu_resume()
+ * already restores that.
+ *
+ * A15/A7 may not require explicit L2 invalidation on reset, dependent
+ * on hardware integration decisions.
+ * For now, this code assumes that L2 is either already invalidated,
+ * or invalidation is not required.
+ */
+        b       cci_enable_port_for_self
+2:      @ Implementation-specific local CPU setup operations should go here,
+        @ if any.  In this case, there is nothing to do.
+        bx      lr
+ENDPROC(dcscb_power_up_setup)
diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c
index dc1ace55d557..993c9ae5dc5e 100644
--- a/arch/arm/mach-vexpress/platsmp.c
+++ b/arch/arm/mach-vexpress/platsmp.c
@@ -12,9 +12,11 @@
 #include <linux/errno.h>
 #include <linux/smp.h>
 #include <linux/io.h>
+#include <linux/of.h>
 #include <linux/of_fdt.h>
 #include <linux/vexpress.h>
+#include <asm/mcpm.h>
 #include <asm/smp_scu.h>
 #include <asm/mach/map.h>
@@ -203,3 +205,21 @@ struct smp_operations __initdata vexpress_smp_ops = {
        .cpu_die                = vexpress_cpu_die,
 #endif
 };
+bool __init vexpress_smp_init_ops(void)
+{
+#ifdef CONFIG_MCPM
+        /*
+         * The best way to detect a multi-cluster configuration at the moment
+         * is to look for the presence of a CCI in the system.
+         * Override the default vexpress_smp_ops if so.
+         */
+        struct device_node *node;
+        node = of_find_compatible_node(NULL, NULL, "arm,cci-400");
+        if (node && of_device_is_available(node)) {
+                mcpm_smp_set_ops();
+                return true;
+        }
+#endif
+        return false;
+}
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 8802030df98d..95a469e23e37 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -9,7 +9,6 @@
 #include <linux/clocksource.h>
 #include <linux/smp.h>
 #include <linux/init.h>
-#include <linux/irqchip.h>
 #include <linux/of_address.h>
 #include <linux/of_fdt.h>
 #include <linux/of_irq.h>
@@ -456,9 +455,9 @@ static const char * const v2m_dt_match[] __initconst = {
 DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express")
        .dt_compat      = v2m_dt_match,
        .smp            = smp_ops(vexpress_smp_ops),
+        .smp_init       = smp_init_ops(vexpress_smp_init_ops),
        .map_io         = v2m_dt_map_io,
        .init_early     = v2m_dt_init_early,
-        .init_irq       = irqchip_init,
        .init_time      = v2m_dt_timer_init,
        .init_machine   = v2m_dt_init,
 MACHINE_END
diff --git a/arch/arm/mach-virt/Kconfig b/arch/arm/mach-virt/Kconfig
index 8958f0d896bc..081d46929436 100644
--- a/arch/arm/mach-virt/Kconfig
+++ b/arch/arm/mach-virt/Kconfig
@@ -2,7 +2,7 @@ config ARCH_VIRT
        bool "Dummy Virtual Machine" if ARCH_MULTI_V7
        select ARCH_WANT_OPTIONAL_GPIOLIB
        select ARM_GIC
-        select ARM_ARCH_TIMER
+        select HAVE_ARM_ARCH_TIMER
        select ARM_PSCI
        select HAVE_SMP
        select CPU_V7
diff --git a/arch/arm/mach-virt/Makefile b/arch/arm/mach-virt/Makefile
index 042afc1f8c44..7ddbfa60227f 100644
--- a/arch/arm/mach-virt/Makefile
+++ b/arch/arm/mach-virt/Makefile
@@ -3,4 +3,3 @@
 #
 obj-y                                   := virt.o
-obj-$(CONFIG_SMP)                       += platsmp.o
diff --git a/arch/arm/mach-virt/platsmp.c b/arch/arm/mach-virt/platsmp.c
deleted file mode 100644
index f4143f5bfa5b..000000000000
--- a/arch/arm/mach-virt/platsmp.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Dummy Virtual Machine - does what it says on the tin.
- *
- * Copyright (C) 2012 ARM Ltd
- * Author: Will Deacon <will.deacon@arm.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/of.h>
-#include <asm/psci.h>
-#include <asm/smp_plat.h>
-extern void secondary_startup(void);
-static void __init virt_smp_init_cpus(void)
-{
-}
-static void __init virt_smp_prepare_cpus(unsigned int max_cpus)
-{
-}
-static int __cpuinit virt_boot_secondary(unsigned int cpu,
-                                         struct task_struct *idle)
-{
-        if (psci_ops.cpu_on)
-                return psci_ops.cpu_on(cpu_logical_map(cpu),
-                                       __pa(secondary_startup));
-        return -ENODEV;
-}
-struct smp_operations __initdata virt_smp_ops = {
-        .smp_init_cpus          = virt_smp_init_cpus,
-        .smp_prepare_cpus       = virt_smp_prepare_cpus,
-        .smp_boot_secondary     = virt_boot_secondary,
-};
diff --git a/arch/arm/mach-virt/virt.c b/arch/arm/mach-virt/virt.c
index 061f283f579e..b184e57d1854 100644
--- a/arch/arm/mach-virt/virt.c
+++ b/arch/arm/mach-virt/virt.c
@@ -18,7 +18,6 @@
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
-#include <linux/irqchip.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/smp.h>
@@ -36,11 +35,7 @@ static const char *virt_dt_match[] = {
        NULL
 };
-extern struct smp_operations virt_smp_ops;
 DT_MACHINE_START(VIRT, "Dummy Virtual Machine")
-        .init_irq       = irqchip_init,
        .init_machine   = virt_init,
-        .smp            = smp_ops(virt_smp_ops),
        .dt_compat      = virt_dt_match,
 MACHINE_END
diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c
index f5c33df7a597..eefaa60d6614 100644
--- a/arch/arm/mach-vt8500/vt8500.c
+++ b/arch/arm/mach-vt8500/vt8500.c
@@ -20,8 +20,8 @@
 #include <linux/clocksource.h>
 #include <linux/io.h>
-#include <linux/irqchip.h>
 #include <linux/pm.h>
+#include <linux/reboot.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -47,7 +47,7 @@
 static void __iomem *pmc_base;
-void vt8500_restart(char mode, const char *cmd)
+void vt8500_restart(enum reboot_mode mode, const char *cmd)
 {
        if (pmc_base)
                writel(1, pmc_base + VT8500_PMSR_REG);
@@ -179,7 +179,6 @@ static const char * const vt8500_dt_compat[] = {
 DT_MACHINE_START(WMT_DT, "VIA/Wondermedia SoC (Device Tree Support)")
        .dt_compat      = vt8500_dt_compat,
        .map_io         = vt8500_map_io,
-        .init_irq       = irqchip_init,
        .init_machine   = vt8500_init,
        .init_time      = clocksource_of_init,
        .restart        = vt8500_restart,
diff --git a/arch/arm/mach-w90x900/cpu.c b/arch/arm/mach-w90x900/cpu.c
index 9e4dd8b63c4a..b1eabaad50a5 100644
--- a/arch/arm/mach-w90x900/cpu.c
+++ b/arch/arm/mach-w90x900/cpu.c
@@ -230,9 +230,9 @@ void __init nuc900_init_clocks(void)
 #define WTE     (1 << 7)
 #define WTRE    (1 << 1)
-void nuc9xx_restart(char mode, const char *cmd)
+void nuc9xx_restart(enum reboot_mode mode, const char *cmd)
 {
-        if (mode == 's') {
+        if (mode == REBOOT_SOFT) {
                /* Jump into ROM at address 0 */
                soft_restart(0);
        } else {
diff --git a/arch/arm/mach-w90x900/nuc9xx.h b/arch/arm/mach-w90x900/nuc9xx.h
index 88ef4b267089..e3ab1e1381f1 100644
--- a/arch/arm/mach-w90x900/nuc9xx.h
+++ b/arch/arm/mach-w90x900/nuc9xx.h
@@ -14,10 +14,13 @@
 * published by the Free Software Foundation.
 *
 */
+#include <linux/reboot.h>
 struct map_desc;
 /* core initialisation functions */
 extern void nuc900_init_irq(void);
 extern void nuc900_timer_init(void);
-extern void nuc9xx_restart(char, const char *);
+extern void nuc9xx_restart(enum reboot_mode, const char *);
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index 5bfe7035b73d..5f252569c689 100644
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -25,7 +25,6 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/of.h>
-#include <linux/irqchip.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -92,21 +91,19 @@ static void __init zynq_map_io(void)
        zynq_scu_map_io();
 }
-static void zynq_system_reset(char mode, const char *cmd)
+static void zynq_system_reset(enum reboot_mode mode, const char *cmd)
 {
        zynq_slcr_system_reset();
 }
 static const char * const zynq_dt_match[] = {
-        "xlnx,zynq-zc702",
        "xlnx,zynq-7000",
        NULL
 };
-MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")
+DT_MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")
        .smp            = smp_ops(zynq_smp_ops),
        .map_io         = zynq_map_io,
-        .init_irq       = irqchip_init,
        .init_machine   = zynq_init_machine,
        .init_time      = zynq_timer_init,
        .dt_compat      = zynq_dt_match,
diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h
index fbbd0e21c404..3040d219570f 100644
--- a/arch/arm/mach-zynq/common.h
+++ b/arch/arm/mach-zynq/common.h
@@ -27,7 +27,7 @@ extern void secondary_startup(void);
 extern char zynq_secondary_trampoline;
 extern char zynq_secondary_trampoline_jump;
 extern char zynq_secondary_trampoline_end;
-extern int __cpuinit zynq_cpun_start(u32 address, int cpu);
+extern int zynq_cpun_start(u32 address, int cpu);
 extern struct smp_operations zynq_smp_ops __initdata;
 #endif
diff --git a/arch/arm/mach-zynq/headsmp.S b/arch/arm/mach-zynq/headsmp.S
index d183cd234a9b..d4cd5f34fe5c 100644
--- a/arch/arm/mach-zynq/headsmp.S
+++ b/arch/arm/mach-zynq/headsmp.S
@@ -9,8 +9,6 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
-        __CPUINIT
 ENTRY(zynq_secondary_trampoline)
        ldr     r0, [pc]
        bx      r0
diff --git a/arch/arm/mach-zynq/platsmp.c b/arch/arm/mach-zynq/platsmp.c
index 5fc167e07619..689fbbc3d9c8 100644
--- a/arch/arm/mach-zynq/platsmp.c
+++ b/arch/arm/mach-zynq/platsmp.c
@@ -30,11 +30,11 @@
 /*
 * Store number of cores in the system
 * Because of scu_get_core_count() must be in __init section and can't
- * be called from zynq_cpun_start() because it is in __cpuinit section.
+ * be called from zynq_cpun_start() because it is not in __init section.
 */
 static int ncores;
-int __cpuinit zynq_cpun_start(u32 address, int cpu)
+int zynq_cpun_start(u32 address, int cpu)
 {
        u32 trampoline_code_size = &zynq_secondary_trampoline_end -
                                                &zynq_secondary_trampoline;
@@ -53,34 +53,34 @@ int __cpuinit zynq_cpun_start(u32 address, int cpu)
                                                &zynq_secondary_trampoline;
                zynq_slcr_cpu_stop(cpu);
+                if (address) {
-                if (__pa(PAGE_OFFSET)) {
+                        if (__pa(PAGE_OFFSET)) {
-                        zero = ioremap(0, trampoline_code_size);
+                                zero = ioremap(0, trampoline_code_size);
-                        if (!zero) {
+                                if (!zero) {
-                                pr_warn("BOOTUP jump vectors not accessible\n");
+                                        pr_warn("BOOTUP jump vectors not accessible\n");
-                                return -1;
+                                        return -1;
+                                }
+                        } else {
+                                zero = (__force u8 __iomem *)PAGE_OFFSET;
                        }
-                } else {
-                        zero = (__force u8 __iomem *)PAGE_OFFSET;
-                }
-                /*
-                 * This is elegant way how to jump to any address
-                 * 0x0: Load address at 0x8 to r0
-                 * 0x4: Jump by mov instruction
-                 * 0x8: Jumping address
-                 */
-                memcpy((__force void *)zero, &zynq_secondary_trampoline,
-                                                trampoline_size);
-                writel(address, zero + trampoline_size);
-                flush_cache_all();
-                outer_flush_range(0, trampoline_code_size);
-                smp_wmb();
-                if (__pa(PAGE_OFFSET))
-                        iounmap(zero);
+                        /*
+                        * This is elegant way how to jump to any address
+                        * 0x0: Load address at 0x8 to r0
+                        * 0x4: Jump by mov instruction
+                        * 0x8: Jumping address
+                        */
+                        memcpy((__force void *)zero, &zynq_secondary_trampoline,
+                                                        trampoline_size);
+                        writel(address, zero + trampoline_size);
+                        flush_cache_all();
+                        outer_flush_range(0, trampoline_code_size);
+                        smp_wmb();
+                        if (__pa(PAGE_OFFSET))
+                                iounmap(zero);
+                }
                zynq_slcr_cpu_start(cpu);
                return 0;
@@ -92,7 +92,7 @@ int __cpuinit zynq_cpun_start(u32 address, int cpu)
 }
 EXPORT_SYMBOL(zynq_cpun_start);
-static int __cpuinit zynq_boot_secondary(unsigned int cpu,
+static int zynq_boot_secondary(unsigned int cpu,
                                                struct task_struct *idle)
 {
        return zynq_cpun_start(virt_to_phys(secondary_startup), cpu);
diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c
index c70969b9c258..50d008d8f87f 100644
--- a/arch/arm/mach-zynq/slcr.c
+++ b/arch/arm/mach-zynq/slcr.c
@@ -117,7 +117,7 @@ int __init zynq_slcr_init(void)
        pr_info("%s mapped to %p\n", np->name, zynq_slcr_base);
-        xilinx_zynq_clocks_init(zynq_slcr_base);
+        zynq_clock_init(zynq_slcr_base);
        of_node_put(np);
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 35955b54944c..db5c2cab8fda 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -392,11 +392,21 @@ config CPU_V7
        select CPU_CACHE_V7
        select CPU_CACHE_VIPT
        select CPU_COPY_V6 if MMU
-        select CPU_CP15_MMU
+        select CPU_CP15_MMU if MMU
+        select CPU_CP15_MPU if !MMU
        select CPU_HAS_ASID if MMU
        select CPU_PABRT_V7
        select CPU_TLB_V7 if MMU
+# ARMv7M
+config CPU_V7M
+        bool
+        select CPU_32v7M
+        select CPU_ABRT_NOMMU
+        select CPU_CACHE_NOP
+        select CPU_PABRT_LEGACY
+        select CPU_THUMBONLY
 config CPU_THUMBONLY
        bool
        # There are no CPUs available with MMU that don't implement an ARM ISA:
@@ -411,24 +421,28 @@ config CPU_32v3
        select CPU_USE_DOMAINS if MMU
        select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
        select TLS_REG_EMUL if SMP || !MMU
+        select NEED_KUSER_HELPERS
 config CPU_32v4
        bool
        select CPU_USE_DOMAINS if MMU
        select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
        select TLS_REG_EMUL if SMP || !MMU
+        select NEED_KUSER_HELPERS
 config CPU_32v4T
        bool
        select CPU_USE_DOMAINS if MMU
        select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
        select TLS_REG_EMUL if SMP || !MMU
+        select NEED_KUSER_HELPERS
 config CPU_32v5
        bool
        select CPU_USE_DOMAINS if MMU
        select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
        select TLS_REG_EMUL if SMP || !MMU
+        select NEED_KUSER_HELPERS
 config CPU_32v6
        bool
@@ -441,6 +455,9 @@ config CPU_32v6K
 config CPU_32v7
        bool
+config CPU_32v7M
+        bool
 # The abort model
 config CPU_ABRT_NOMMU
        bool
@@ -491,6 +508,9 @@ config CPU_CACHE_V6
 config CPU_CACHE_V7
        bool
+config CPU_CACHE_NOP
+        bool
 config CPU_CACHE_VIVT
        bool
@@ -613,7 +633,11 @@ config ARCH_DMA_ADDR_T_64BIT
 config ARM_THUMB
        bool "Support Thumb user binaries" if !CPU_THUMBONLY
-        depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || CPU_V7 || CPU_FEROCEON
+        depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || \
+                CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || \
+                CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
+                CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || \
+                CPU_V7 || CPU_FEROCEON || CPU_V7M
        default y
        help
          Say Y if you want to include kernel support for running user space
@@ -756,6 +780,7 @@ config CPU_BPREDICT_DISABLE
 config TLS_REG_EMUL
        bool
+        select NEED_KUSER_HELPERS
        help
          An SMP system using a pre-ARMv6 processor (there are apparently
          a few prototypes like that in existence) and therefore access to
@@ -763,11 +788,40 @@ config TLS_REG_EMUL
 config NEEDS_SYSCALL_FOR_CMPXCHG
        bool
+        select NEED_KUSER_HELPERS
        help
          SMP on a pre-ARMv6 processor?  Well OK then.
          Forget about fast user space cmpxchg support.
          It is just not possible.
+config NEED_KUSER_HELPERS
+        bool
+config KUSER_HELPERS
+        bool "Enable kuser helpers in vector page" if !NEED_KUSER_HELPERS
+        default y
+        help
+          Warning: disabling this option may break user programs.
+          Provide kuser helpers in the vector page.  The kernel provides
+          helper code to userspace in read only form at a fixed location
+          in the high vector page to allow userspace to be independent of
+          the CPU type fitted to the system.  This permits binaries to be
+          run on ARMv4 through to ARMv7 without modification.
+          However, the fixed address nature of these helpers can be used
+          by ROP (return orientated programming) authors when creating
+          exploits.
+          If all of the binaries and libraries which run on your platform
+          are built specifically for your platform, and make no use of
+          these helpers, then you can turn this option off.  However,
+          when such an binary or library is run, it will receive a SIGILL
+          signal, which will terminate the program.
+          Say N here only if you are absolutely certain that you do not
+          need these helpers; otherwise, the safe option is to say Y.
 config DMA_CACHE_RWFO
        bool "Enable read/write for ownership DMA cache maintenance"
        depends on CPU_V6K && SMP
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index 9e51be96f635..ecfe6e53f6e0 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_MODULES)		+= proc-syms.o
 obj-$(CONFIG_ALIGNMENT_TRAP)    += alignment.o
 obj-$(CONFIG_HIGHMEM)           += highmem.o
+obj-$(CONFIG_HUGETLB_PAGE)      += hugetlbpage.o
 obj-$(CONFIG_CPU_ABRT_NOMMU)    += abort-nommu.o
 obj-$(CONFIG_CPU_ABRT_EV4)      += abort-ev4.o
@@ -39,6 +40,7 @@ obj-$(CONFIG_CPU_CACHE_V4WB)	+= cache-v4wb.o
 obj-$(CONFIG_CPU_CACHE_V6)      += cache-v6.o
 obj-$(CONFIG_CPU_CACHE_V7)      += cache-v7.o
 obj-$(CONFIG_CPU_CACHE_FA)      += cache-fa.o
+obj-$(CONFIG_CPU_CACHE_NOP)     += cache-nop.o
 AFLAGS_cache-v6.o       :=-Wa,-march=armv6
 AFLAGS_cache-v7.o       :=-Wa,-march=armv7-a
@@ -87,6 +89,7 @@ obj-$(CONFIG_CPU_FEROCEON)	+= proc-feroceon.o
 obj-$(CONFIG_CPU_V6)            += proc-v6.o
 obj-$(CONFIG_CPU_V6K)           += proc-v6.o
 obj-$(CONFIG_CPU_V7)            += proc-v7.o
+obj-$(CONFIG_CPU_V7M)           += proc-v7m.o
 AFLAGS_proc-v6.o        :=-Wa,-march=armv6
 AFLAGS_proc-v7.o        :=-Wa,-march=armv7-a
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index c465faca51b0..d70e0aba0c9d 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -523,6 +523,147 @@ static void aurora_flush_range(unsigned long start, unsigned long end)
        }
 }
+/*
+ * For certain Broadcom SoCs, depending on the address range, different offsets
+ * need to be added to the address before passing it to L2 for
+ * invalidation/clean/flush
+ *
+ * Section Address Range              Offset        EMI
+ *   1     0x00000000 - 0x3FFFFFFF    0x80000000    VC
+ *   2     0x40000000 - 0xBFFFFFFF    0x40000000    SYS
+ *   3     0xC0000000 - 0xFFFFFFFF    0x80000000    VC
+ *
+ * When the start and end addresses have crossed two different sections, we
+ * need to break the L2 operation into two, each within its own section.
+ * For example, if we need to invalidate addresses starts at 0xBFFF0000 and
+ * ends at 0xC0001000, we need do invalidate 1) 0xBFFF0000 - 0xBFFFFFFF and 2)
+ * 0xC0000000 - 0xC0001000
+ *
+ * Note 1:
+ * By breaking a single L2 operation into two, we may potentially suffer some
+ * performance hit, but keep in mind the cross section case is very rare
+ *
+ * Note 2:
+ * We do not need to handle the case when the start address is in
+ * Section 1 and the end address is in Section 3, since it is not a valid use
+ * case
+ *
+ * Note 3:
+ * Section 1 in practical terms can no longer be used on rev A2. Because of
+ * that the code does not need to handle section 1 at all.
+ *
+ */
+#define BCM_SYS_EMI_START_ADDR        0x40000000UL
+#define BCM_VC_EMI_SEC3_START_ADDR    0xC0000000UL
+#define BCM_SYS_EMI_OFFSET            0x40000000UL
+#define BCM_VC_EMI_OFFSET             0x80000000UL
+static inline int bcm_addr_is_sys_emi(unsigned long addr)
+{
+        return (addr >= BCM_SYS_EMI_START_ADDR) &&
+                (addr < BCM_VC_EMI_SEC3_START_ADDR);
+}
+static inline unsigned long bcm_l2_phys_addr(unsigned long addr)
+{
+        if (bcm_addr_is_sys_emi(addr))
+                return addr + BCM_SYS_EMI_OFFSET;
+        else
+                return addr + BCM_VC_EMI_OFFSET;
+}
+static void bcm_inv_range(unsigned long start, unsigned long end)
+{
+        unsigned long new_start, new_end;
+        BUG_ON(start < BCM_SYS_EMI_START_ADDR);
+        if (unlikely(end <= start))
+                return;
+        new_start = bcm_l2_phys_addr(start);
+        new_end = bcm_l2_phys_addr(end);
+        /* normal case, no cross section between start and end */
+        if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
+                l2x0_inv_range(new_start, new_end);
+                return;
+        }
+        /* They cross sections, so it can only be a cross from section
+         * 2 to section 3
+         */
+        l2x0_inv_range(new_start,
+                bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
+        l2x0_inv_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
+                new_end);
+}
+static void bcm_clean_range(unsigned long start, unsigned long end)
+{
+        unsigned long new_start, new_end;
+        BUG_ON(start < BCM_SYS_EMI_START_ADDR);
+        if (unlikely(end <= start))
+                return;
+        if ((end - start) >= l2x0_size) {
+                l2x0_clean_all();
+                return;
+        }
+        new_start = bcm_l2_phys_addr(start);
+        new_end = bcm_l2_phys_addr(end);
+        /* normal case, no cross section between start and end */
+        if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
+                l2x0_clean_range(new_start, new_end);
+                return;
+        }
+        /* They cross sections, so it can only be a cross from section
+         * 2 to section 3
+         */
+        l2x0_clean_range(new_start,
+                bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
+        l2x0_clean_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
+                new_end);
+}
+static void bcm_flush_range(unsigned long start, unsigned long end)
+{
+        unsigned long new_start, new_end;
+        BUG_ON(start < BCM_SYS_EMI_START_ADDR);
+        if (unlikely(end <= start))
+                return;
+        if ((end - start) >= l2x0_size) {
+                l2x0_flush_all();
+                return;
+        }
+        new_start = bcm_l2_phys_addr(start);
+        new_end = bcm_l2_phys_addr(end);
+        /* normal case, no cross section between start and end */
+        if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
+                l2x0_flush_range(new_start, new_end);
+                return;
+        }
+        /* They cross sections, so it can only be a cross from section
+         * 2 to section 3
+         */
+        l2x0_flush_range(new_start,
+                bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
+        l2x0_flush_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
+                new_end);
+}
 static void __init l2x0_of_setup(const struct device_node *np,
                                 u32 *aux_val, u32 *aux_mask)
 {
@@ -765,6 +906,21 @@ static const struct l2x0_of_data aurora_no_outer_data = {
        },
 };
+static const struct l2x0_of_data bcm_l2x0_data = {
+        .setup = pl310_of_setup,
+        .save  = pl310_save,
+        .outer_cache = {
+                .resume      = pl310_resume,
+                .inv_range   = bcm_inv_range,
+                .clean_range = bcm_clean_range,
+                .flush_range = bcm_flush_range,
+                .sync        = l2x0_cache_sync,
+                .flush_all   = l2x0_flush_all,
+                .inv_all     = l2x0_inv_all,
+                .disable     = l2x0_disable,
+        },
+};
 static const struct of_device_id l2x0_ids[] __initconst = {
        { .compatible = "arm,pl310-cache", .data = (void *)&pl310_data },
        { .compatible = "arm,l220-cache", .data = (void *)&l2x0_data },
@@ -773,6 +929,8 @@ static const struct of_device_id l2x0_ids[] __initconst = {
          .data = (void *)&aurora_no_outer_data},
        { .compatible = "marvell,aurora-outer-cache",
          .data = (void *)&aurora_with_outer_data},
+        { .compatible = "bcm,bcm11351-a2-pl310-cache",
+          .data = (void *)&bcm_l2x0_data},
        {}
 };
diff --git a/arch/arm/mm/cache-nop.S b/arch/arm/mm/cache-nop.S
new file mode 100644
index 000000000000..8e12ddca0031
--- /dev/null
+++ b/arch/arm/mm/cache-nop.S
@@ -0,0 +1,50 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include "proc-macros.S"
+ENTRY(nop_flush_icache_all)
+        mov     pc, lr
+ENDPROC(nop_flush_icache_all)
+        .globl nop_flush_kern_cache_all
+        .equ nop_flush_kern_cache_all, nop_flush_icache_all
+        .globl nop_flush_kern_cache_louis
+        .equ nop_flush_kern_cache_louis, nop_flush_icache_all
+        .globl nop_flush_user_cache_all
+        .equ nop_flush_user_cache_all, nop_flush_icache_all
+        .globl nop_flush_user_cache_range
+        .equ nop_flush_user_cache_range, nop_flush_icache_all
+        .globl nop_coherent_kern_range
+        .equ nop_coherent_kern_range, nop_flush_icache_all
+ENTRY(nop_coherent_user_range)
+        mov     r0, 0
+        mov     pc, lr
+ENDPROC(nop_coherent_user_range)
+        .globl nop_flush_kern_dcache_area
+        .equ nop_flush_kern_dcache_area, nop_flush_icache_all
+        .globl nop_dma_flush_range
+        .equ nop_dma_flush_range, nop_flush_icache_all
+        .globl nop_dma_map_area
+        .equ nop_dma_map_area, nop_flush_icache_all
+        .globl nop_dma_unmap_area
+        .equ nop_dma_unmap_area, nop_flush_icache_all
+        __INITDATA
+        @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
+        define_cache_functions nop
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index 2ac37372ef52..4a0544492f10 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -20,6 +20,7 @@
 #include <asm/smp_plat.h>
 #include <asm/thread_notify.h>
 #include <asm/tlbflush.h>
+#include <asm/proc-fns.h>
 /*
 * On ARMv6, we have the following structure in the Context ID:
@@ -39,33 +40,51 @@
 * non 64-bit operations.
 */
 #define ASID_FIRST_VERSION      (1ULL << ASID_BITS)
-#define NUM_USER_ASIDS          (ASID_FIRST_VERSION - 1)
+#define NUM_USER_ASIDS          ASID_FIRST_VERSION
-#define ASID_TO_IDX(asid)       ((asid & ~ASID_MASK) - 1)
-#define IDX_TO_ASID(idx)        ((idx + 1) & ~ASID_MASK)
 static DEFINE_RAW_SPINLOCK(cpu_asid_lock);
 static atomic64_t asid_generation = ATOMIC64_INIT(ASID_FIRST_VERSION);
 static DECLARE_BITMAP(asid_map, NUM_USER_ASIDS);
-DEFINE_PER_CPU(atomic64_t, active_asids);
+static DEFINE_PER_CPU(atomic64_t, active_asids);
 static DEFINE_PER_CPU(u64, reserved_asids);
 static cpumask_t tlb_flush_pending;
+#ifdef CONFIG_ARM_ERRATA_798181
+void a15_erratum_get_cpumask(int this_cpu, struct mm_struct *mm,
+                             cpumask_t *mask)
+{
+        int cpu;
+        unsigned long flags;
+        u64 context_id, asid;
+        raw_spin_lock_irqsave(&cpu_asid_lock, flags);
+        context_id = mm->context.id.counter;
+        for_each_online_cpu(cpu) {
+                if (cpu == this_cpu)
+                        continue;
+                /*
+                 * We only need to send an IPI if the other CPUs are
+                 * running the same ASID as the one being invalidated.
+                 */
+                asid = per_cpu(active_asids, cpu).counter;
+                if (asid == 0)
+                        asid = per_cpu(reserved_asids, cpu);
+                if (context_id == asid)
+                        cpumask_set_cpu(cpu, mask);
+        }
+        raw_spin_unlock_irqrestore(&cpu_asid_lock, flags);
+}
+#endif
 #ifdef CONFIG_ARM_LPAE
 static void cpu_set_reserved_ttbr0(void)
 {
-        unsigned long ttbl = __pa(swapper_pg_dir);
-        unsigned long ttbh = 0;
        /*
         * Set TTBR0 to swapper_pg_dir which contains only global entries. The
         * ASID is set to 0.
         */
-        asm volatile(
+        cpu_set_ttbr(0, __pa(swapper_pg_dir));
-        "       mcrr    p15, 0, %0, %1, c2              @ set TTBR0\n"
-        :
-        : "r" (ttbl), "r" (ttbh));
        isb();
 }
 #else
@@ -128,7 +147,16 @@ static void flush_context(unsigned int cpu)
                        asid = 0;
                } else {
                        asid = atomic64_xchg(&per_cpu(active_asids, i), 0);
-                        __set_bit(ASID_TO_IDX(asid), asid_map);
+                        /*
+                         * If this CPU has already been through a
+                         * rollover, but hasn't run another task in
+                         * the meantime, we must preserve its reserved
+                         * ASID, as this is the only trace we have of
+                         * the process it is still running.
+                         */
+                        if (asid == 0)
+                                asid = per_cpu(reserved_asids, i);
+                        __set_bit(asid & ~ASID_MASK, asid_map);
                }
                per_cpu(reserved_asids, i) = asid;
        }
@@ -167,17 +195,19 @@ static u64 new_context(struct mm_struct *mm, unsigned int cpu)
                /*
                 * Allocate a free ASID. If we can't find one, take a
                 * note of the currently active ASIDs and mark the TLBs
-                 * as requiring flushes.
+                 * as requiring flushes. We always count from ASID #1,
+                 * as we reserve ASID #0 to switch via TTBR0 and indicate
+                 * rollover events.
                 */
-                asid = find_first_zero_bit(asid_map, NUM_USER_ASIDS);
+                asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, 1);
                if (asid == NUM_USER_ASIDS) {
                        generation = atomic64_add_return(ASID_FIRST_VERSION,
                                                         &asid_generation);
                        flush_context(cpu);
-                        asid = find_first_zero_bit(asid_map, NUM_USER_ASIDS);
+                        asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, 1);
                }
                __set_bit(asid, asid_map);
-                asid = generation | IDX_TO_ASID(asid);
+                asid |= generation;
                cpumask_clear(mm_cpumask(mm));
        }
@@ -215,7 +245,8 @@ void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk)
        if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending)) {
                local_flush_bp_all();
                local_flush_tlb_all();
-                dummy_flush_tlb_a15_erratum();
+                if (erratum_a15_798181())
+                        dummy_flush_tlb_a15_erratum();
        }
        atomic64_set(&per_cpu(active_asids, cpu), asid);
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index ef3e0f3aac96..7f9b1798c6cf 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -250,7 +250,7 @@ static void __dma_free_buffer(struct page *page, size_t size)
 #ifdef CONFIG_MMU
 #ifdef CONFIG_HUGETLB_PAGE
-#error ARM Coherent DMA allocator does not (yet) support huge TLB
+#warning ARM Coherent DMA allocator does not (yet) support huge TLB
 #endif
 static void *__alloc_from_contiguous(struct device *dev, size_t size,
@@ -880,10 +880,24 @@ static void __dma_page_dev_to_cpu(struct page *page, unsigned long off,
        dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
        /*
-         * Mark the D-cache clean for this page to avoid extra flushing.
+         * Mark the D-cache clean for these pages to avoid extra flushing.
         */
-        if (dir != DMA_TO_DEVICE && off == 0 && size >= PAGE_SIZE)
+        if (dir != DMA_TO_DEVICE && size >= PAGE_SIZE) {
-                set_bit(PG_dcache_clean, &page->flags);
+                unsigned long pfn;
+                size_t left = size;
+                pfn = page_to_pfn(page) + off / PAGE_SIZE;
+                off %= PAGE_SIZE;
+                if (off) {
+                        pfn++;
+                        left -= PAGE_SIZE - off;
+                }
+                while (left >= PAGE_SIZE) {
+                        page = pfn_to_page(pfn++);
+                        set_bit(PG_dcache_clean, &page->flags);
+                        left -= PAGE_SIZE;
+                }
+        }
 }
 /**
@@ -1314,6 +1328,15 @@ static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
        if (gfp & GFP_ATOMIC)
                return __iommu_alloc_atomic(dev, size, handle);
+        /*
+         * Following is a work-around (a.k.a. hack) to prevent pages
+         * with __GFP_COMP being passed to split_page() which cannot
+         * handle them.  The real problem is that this flag probably
+         * should be 0 on ARM as it is not supported on this
+         * platform; see CONFIG_HUGETLBFS.
+         */
+        gfp &= ~(__GFP_COMP);
        pages = __iommu_alloc_buffer(dev, size, gfp, attrs);
        if (!pages)
                return NULL;
@@ -1372,16 +1395,17 @@ static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
 void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
                          dma_addr_t handle, struct dma_attrs *attrs)
 {
-        struct page **pages = __iommu_get_pages(cpu_addr, attrs);
+        struct page **pages;
        size = PAGE_ALIGN(size);
-        if (!pages) {
+        if (__in_atomic_pool(cpu_addr, size)) {
-                WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr);
+                __iommu_free_atomic(dev, cpu_addr, handle, size);
                return;
        }
-        if (__in_atomic_pool(cpu_addr, size)) {
+        pages = __iommu_get_pages(cpu_addr, attrs);
-                __iommu_free_atomic(dev, cpu_addr, handle, size);
+        if (!pages) {
+                WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr);
                return;
        }
@@ -1636,13 +1660,27 @@ static dma_addr_t arm_coherent_iommu_map_page(struct device *dev, struct page *p
 {
        struct dma_iommu_mapping *mapping = dev->archdata.mapping;
        dma_addr_t dma_addr;
-        int ret, len = PAGE_ALIGN(size + offset);
+        int ret, prot, len = PAGE_ALIGN(size + offset);
        dma_addr = __alloc_iova(mapping, len);
        if (dma_addr == DMA_ERROR_CODE)
                return dma_addr;
-        ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, 0);
+        switch (dir) {
+        case DMA_BIDIRECTIONAL:
+                prot = IOMMU_READ | IOMMU_WRITE;
+                break;
+        case DMA_TO_DEVICE:
+                prot = IOMMU_READ;
+                break;
+        case DMA_FROM_DEVICE:
+                prot = IOMMU_WRITE;
+                break;
+        default:
+                prot = 0;
+        }
+        ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, prot);
        if (ret < 0)
                goto fail;
@@ -1907,7 +1945,7 @@ void arm_iommu_detach_device(struct device *dev)
        iommu_detach_device(mapping->domain, dev);
        kref_put(&mapping->kref, release_iommu_mapping);
-        mapping = NULL;
+        dev->archdata.mapping = NULL;
        set_dma_ops(dev, NULL);
        pr_debug("Detached IOMMU controller from %s device.\n", dev_name(dev));
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index 5dbf13f954f6..c97f7940cb95 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -491,12 +491,14 @@ do_translation_fault(unsigned long addr, unsigned int fsr,
 * Some section permission faults need to be handled gracefully.
 * They can happen due to a __{get,put}_user during an oops.
 */
+#ifndef CONFIG_ARM_LPAE
 static int
 do_sect_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
 {
        do_bad_area(addr, fsr, regs);
        return 0;
 }
+#endif /* CONFIG_ARM_LPAE */
 /*
 * This abort handler always returns "fault".
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 32aa5861119f..6d5ba9afb16a 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -17,6 +17,7 @@
 #include <asm/highmem.h>
 #include <asm/smp_plat.h>
 #include <asm/tlbflush.h>
+#include <linux/hugetlb.h>
 #include "mm.h"
@@ -168,19 +169,23 @@ void __flush_dcache_page(struct address_space *mapping, struct page *page)
         * coherent with the kernels mapping.
         */
        if (!PageHighMem(page)) {
-                __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
+                size_t page_size = PAGE_SIZE << compound_order(page);
+                __cpuc_flush_dcache_area(page_address(page), page_size);
        } else {
-                void *addr;
+                unsigned long i;
                if (cache_is_vipt_nonaliasing()) {
-                        addr = kmap_atomic(page);
+                        for (i = 0; i < (1 << compound_order(page)); i++) {
-                        __cpuc_flush_dcache_area(addr, PAGE_SIZE);
+                                void *addr = kmap_atomic(page);
-                        kunmap_atomic(addr);
-                } else {
-                        addr = kmap_high_get(page);
-                        if (addr) {
                                __cpuc_flush_dcache_area(addr, PAGE_SIZE);
-                                kunmap_high(page);
+                                kunmap_atomic(addr);
+                        }
+                } else {
+                        for (i = 0; i < (1 << compound_order(page)); i++) {
+                                void *addr = kmap_high_get(page);
+                                if (addr) {
+                                        __cpuc_flush_dcache_area(addr, PAGE_SIZE);
+                                        kunmap_high(page);
+                                }
                        }
                }
        }
@@ -287,7 +292,7 @@ void flush_dcache_page(struct page *page)
        mapping = page_mapping(page);
        if (!cache_ops_need_broadcast() &&
-            mapping && !mapping_mapped(mapping))
+            mapping && !page_mapped(page))
                clear_bit(PG_dcache_clean, &page->flags);
        else {
                __flush_dcache_page(mapping, page);
diff --git a/arch/arm/mm/fsr-3level.c b/arch/arm/mm/fsr-3level.c
index 05a4e9431836..ab4409a2307e 100644
--- a/arch/arm/mm/fsr-3level.c
+++ b/arch/arm/mm/fsr-3level.c
@@ -9,11 +9,11 @@ static struct fsr_info fsr_info[] = {
        { do_page_fault,        SIGSEGV, SEGV_MAPERR,   "level 3 translation fault"     },
        { do_bad,               SIGBUS,  0,             "reserved access flag fault"    },
        { do_bad,               SIGSEGV, SEGV_ACCERR,   "level 1 access flag fault"     },
-        { do_bad,               SIGSEGV, SEGV_ACCERR,   "level 2 access flag fault"     },
+        { do_page_fault,        SIGSEGV, SEGV_ACCERR,   "level 2 access flag fault"     },
        { do_page_fault,        SIGSEGV, SEGV_ACCERR,   "level 3 access flag fault"     },
        { do_bad,               SIGBUS,  0,             "reserved permission fault"     },
        { do_bad,               SIGSEGV, SEGV_ACCERR,   "level 1 permission fault"      },
-        { do_sect_fault,        SIGSEGV, SEGV_ACCERR,   "level 2 permission fault"      },
+        { do_page_fault,        SIGSEGV, SEGV_ACCERR,   "level 2 permission fault"      },
        { do_page_fault,        SIGSEGV, SEGV_ACCERR,   "level 3 permission fault"      },
        { do_bad,               SIGBUS,  0,             "synchronous external abort"    },
        { do_bad,               SIGBUS,  0,             "asynchronous external abort"   },
diff --git a/arch/arm/mm/hugetlbpage.c b/arch/arm/mm/hugetlbpage.c
new file mode 100644
index 000000000000..3d1e4a205b0b
--- /dev/null
+++ b/arch/arm/mm/hugetlbpage.c
@@ -0,0 +1,101 @@
+/*
+ * arch/arm/mm/hugetlbpage.c
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * Based on arch/x86/include/asm/hugetlb.h and Bill Carson's patches
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <linux/init.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/hugetlb.h>
+#include <linux/pagemap.h>
+#include <linux/err.h>
+#include <linux/sysctl.h>
+#include <asm/mman.h>
+#include <asm/tlb.h>
+#include <asm/tlbflush.h>
+#include <asm/pgalloc.h>
+/*
+ * On ARM, huge pages are backed by pmd's rather than pte's, so we do a lot
+ * of type casting from pmd_t * to pte_t *.
+ */
+pte_t *huge_pte_offset(struct mm_struct *mm, unsigned long addr)
+{
+        pgd_t *pgd;
+        pud_t *pud;
+        pmd_t *pmd = NULL;
+        pgd = pgd_offset(mm, addr);
+        if (pgd_present(*pgd)) {
+                pud = pud_offset(pgd, addr);
+                if (pud_present(*pud))
+                        pmd = pmd_offset(pud, addr);
+        }
+        return (pte_t *)pmd;
+}
+struct page *follow_huge_addr(struct mm_struct *mm, unsigned long address,
+                              int write)
+{
+        return ERR_PTR(-EINVAL);
+}
+int pud_huge(pud_t pud)
+{
+        return 0;
+}
+int huge_pmd_unshare(struct mm_struct *mm, unsigned long *addr, pte_t *ptep)
+{
+        return 0;
+}
+pte_t *huge_pte_alloc(struct mm_struct *mm,
+                        unsigned long addr, unsigned long sz)
+{
+        pgd_t *pgd;
+        pud_t *pud;
+        pte_t *pte = NULL;
+        pgd = pgd_offset(mm, addr);
+        pud = pud_alloc(mm, pgd, addr);
+        if (pud)
+                pte = (pte_t *)pmd_alloc(mm, pud, addr);
+        return pte;
+}
+struct page *
+follow_huge_pmd(struct mm_struct *mm, unsigned long address,
+                pmd_t *pmd, int write)
+{
+        struct page *page;
+        page = pte_page(*(pte_t *)pmd);
+        if (page)
+                page += ((address & ~PMD_MASK) >> PAGE_SHIFT);
+        return page;
+}
+int pmd_huge(pmd_t pmd)
+{
+        return pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT);
+}
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 9a5cdc01fcdf..15225d829d71 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -36,12 +36,13 @@
 #include "mm.h"
-static unsigned long phys_initrd_start __initdata = 0;
+static phys_addr_t phys_initrd_start __initdata = 0;
 static unsigned long phys_initrd_size __initdata = 0;
 static int __init early_initrd(char *p)
 {
-        unsigned long start, size;
+        phys_addr_t start;
+        unsigned long size;
        char *endp;
        start = memparse(p, &endp);
@@ -350,14 +351,14 @@ void __init arm_memblock_init(struct meminfo *mi, struct machine_desc *mdesc)
 #ifdef CONFIG_BLK_DEV_INITRD
        if (phys_initrd_size &&
            !memblock_is_region_memory(phys_initrd_start, phys_initrd_size)) {
-                pr_err("INITRD: 0x%08lx+0x%08lx is not a memory region - disabling initrd\n",
+                pr_err("INITRD: 0x%08llx+0x%08lx is not a memory region - disabling initrd\n",
-                       phys_initrd_start, phys_initrd_size);
+                       (u64)phys_initrd_start, phys_initrd_size);
                phys_initrd_start = phys_initrd_size = 0;
        }
        if (phys_initrd_size &&
            memblock_is_region_reserved(phys_initrd_start, phys_initrd_size)) {
-                pr_err("INITRD: 0x%08lx+0x%08lx overlaps in-use memory region - disabling initrd\n",
+                pr_err("INITRD: 0x%08llx+0x%08lx overlaps in-use memory region - disabling initrd\n",
-                       phys_initrd_start, phys_initrd_size);
+                       (u64)phys_initrd_start, phys_initrd_size);
                phys_initrd_start = phys_initrd_size = 0;
        }
        if (phys_initrd_size) {
@@ -442,7 +443,7 @@ static inline void
 free_memmap(unsigned long start_pfn, unsigned long end_pfn)
 {
        struct page *start_pg, *end_pg;
-        unsigned long pg, pgend;
+        phys_addr_t pg, pgend;
        /*
         * Convert start_pfn/end_pfn to a struct page pointer.
@@ -454,8 +455,8 @@ free_memmap(unsigned long start_pfn, unsigned long end_pfn)
         * Convert to physical addresses, and
         * round start upwards and end downwards.
         */
-        pg = (unsigned long)PAGE_ALIGN(__pa(start_pg));
+        pg = PAGE_ALIGN(__pa(start_pg));
-        pgend = (unsigned long)__pa(end_pg) & PAGE_MASK;
+        pgend = __pa(end_pg) & PAGE_MASK;
        /*
         * If there are free pages between these,
@@ -582,9 +583,6 @@ static void __init free_highpages(void)
 */
 void __init mem_init(void)
 {
-        unsigned long reserved_pages, free_pages;
-        struct memblock_region *reg;
-        int i;
 #ifdef CONFIG_HAVE_TCM
        /* These pointers are filled in on TCM detection */
        extern u32 dtcm_end;
@@ -595,57 +593,16 @@ void __init mem_init(void)
        /* this will put all unused low memory onto the freelists */
        free_unused_memmap(&meminfo);
+        free_all_bootmem();
-        totalram_pages += free_all_bootmem();
 #ifdef CONFIG_SA1111
        /* now that our DMA memory is actually so designated, we can free it */
-        free_reserved_area(__va(PHYS_PFN_OFFSET), swapper_pg_dir, 0, NULL);
+        free_reserved_area(__va(PHYS_OFFSET), swapper_pg_dir, -1, NULL);
 #endif
        free_highpages();
-        reserved_pages = free_pages = 0;
+        mem_init_print_info(NULL);
-        for_each_bank(i, &meminfo) {
-                struct membank *bank = &meminfo.bank[i];
-                unsigned int pfn1, pfn2;
-                struct page *page, *end;
-                pfn1 = bank_pfn_start(bank);
-                pfn2 = bank_pfn_end(bank);
-                page = pfn_to_page(pfn1);
-                end  = pfn_to_page(pfn2 - 1) + 1;
-                do {
-                        if (PageReserved(page))
-                                reserved_pages++;
-                        else if (!page_count(page))
-                                free_pages++;
-                        page++;
-                } while (page < end);
-        }
-        /*
-         * Since our memory may not be contiguous, calculate the
-         * real number of pages we have in this system
-         */
-        printk(KERN_INFO "Memory:");
-        num_physpages = 0;
-        for_each_memblock(memory, reg) {
-                unsigned long pages = memblock_region_memory_end_pfn(reg) -
-                        memblock_region_memory_base_pfn(reg);
-                num_physpages += pages;
-                printk(" %ldMB", pages >> (20 - PAGE_SHIFT));
-        }
-        printk(" = %luMB total\n", num_physpages >> (20 - PAGE_SHIFT));
-        printk(KERN_NOTICE "Memory: %luk/%luk available, %luk reserved, %luK highmem\n",
-                nr_free_pages() << (PAGE_SHIFT-10),
-                free_pages << (PAGE_SHIFT-10),
-                reserved_pages << (PAGE_SHIFT-10),
-                totalhigh_pages << (PAGE_SHIFT-10));
 #define MLK(b, t) b, t, ((t) - (b)) >> 10
 #define MLM(b, t) b, t, ((t) - (b)) >> 20
@@ -711,7 +668,7 @@ void __init mem_init(void)
        BUG_ON(PKMAP_BASE + LAST_PKMAP * PAGE_SIZE      > PAGE_OFFSET);
 #endif
-        if (PAGE_SIZE >= 16384 && num_physpages <= 128) {
+        if (PAGE_SIZE >= 16384 && get_num_physpages() <= 128) {
                extern int sysctl_overcommit_memory;
                /*
                 * On a machine this small we won't get
@@ -728,12 +685,12 @@ void free_initmem(void)
        extern char __tcm_start, __tcm_end;
        poison_init_mem(&__tcm_start, &__tcm_end - &__tcm_start);
-        free_reserved_area(&__tcm_start, &__tcm_end, 0, "TCM link");
+        free_reserved_area(&__tcm_start, &__tcm_end, -1, "TCM link");
 #endif
        poison_init_mem(__init_begin, __init_end - __init_begin);
        if (!machine_is_integrator() && !machine_is_cintegrator())
-                free_initmem_default(0);
+                free_initmem_default(-1);
 }
 #ifdef CONFIG_BLK_DEV_INITRD
@@ -744,7 +701,7 @@ void free_initrd_mem(unsigned long start, unsigned long end)
 {
        if (!keep_initrd) {
                poison_init_mem((void *)start, PAGE_ALIGN(end) - start);
-                free_reserved_area(start, end, 0, "initrd");
+                free_reserved_area((void *)start, (void *)end, -1, "initrd");
        }
 }
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 04d9006eab1f..f123d6eb074b 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -331,10 +331,10 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
        return (void __iomem *) (offset + addr);
 }
-void __iomem *__arm_ioremap_caller(unsigned long phys_addr, size_t size,
+void __iomem *__arm_ioremap_caller(phys_addr_t phys_addr, size_t size,
        unsigned int mtype, void *caller)
 {
-        unsigned long last_addr;
+        phys_addr_t last_addr;
        unsigned long offset = phys_addr & ~PAGE_MASK;
        unsigned long pfn = __phys_to_pfn(phys_addr);
@@ -367,12 +367,12 @@ __arm_ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size,
 }
 EXPORT_SYMBOL(__arm_ioremap_pfn);
-void __iomem * (*arch_ioremap_caller)(unsigned long, size_t,
+void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t,
                                      unsigned int, void *) =
        __arm_ioremap_caller;
 void __iomem *
-__arm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
+__arm_ioremap(phys_addr_t phys_addr, size_t size, unsigned int mtype)
 {
        return arch_ioremap_caller(phys_addr, size, mtype,
                __builtin_return_address(0));
@@ -387,7 +387,7 @@ EXPORT_SYMBOL(__arm_ioremap);
 * CONFIG_GENERIC_ALLOCATOR for allocating external memory.
 */
 void __iomem *
-__arm_ioremap_exec(unsigned long phys_addr, size_t size, bool cached)
+__arm_ioremap_exec(phys_addr_t phys_addr, size_t size, bool cached)
 {
        unsigned int mtype;
diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c
index 10062ceadd1c..0c6356255fe3 100644
--- a/arch/arm/mm/mmap.c
+++ b/arch/arm/mm/mmap.c
@@ -181,11 +181,9 @@ void arch_pick_mmap_layout(struct mm_struct *mm)
        if (mmap_is_legacy()) {
                mm->mmap_base = TASK_UNMAPPED_BASE + random_factor;
                mm->get_unmapped_area = arch_get_unmapped_area;
-                mm->unmap_area = arch_unmap_area;
        } else {
                mm->mmap_base = mmap_base(random_factor);
                mm->get_unmapped_area = arch_get_unmapped_area_topdown;
-                mm->unmap_area = arch_unmap_area_topdown;
        }
 }
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 4d409e6a552d..53cdbd39ec8e 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -675,7 +675,8 @@ static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
 }
 static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
-        unsigned long end, unsigned long phys, const struct mem_type *type)
+                                  unsigned long end, phys_addr_t phys,
+                                  const struct mem_type *type)
 {
        pud_t *pud = pud_offset(pgd, addr);
        unsigned long next;
@@ -949,7 +950,7 @@ void __init debug_ll_io_init(void)
        map.virtual &= PAGE_MASK;
        map.length = PAGE_SIZE;
        map.type = MT_DEVICE;
-        create_mapping(&map);
+        iotable_init(&map, 1);
 }
 #endif
@@ -988,28 +989,30 @@ phys_addr_t arm_lowmem_limit __initdata = 0;
 void __init sanity_check_meminfo(void)
 {
+        phys_addr_t memblock_limit = 0;
        int i, j, highmem = 0;
+        phys_addr_t vmalloc_limit = __pa(vmalloc_min - 1) + 1;
        for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
                struct membank *bank = &meminfo.bank[j];
+                phys_addr_t size_limit;
                *bank = meminfo.bank[i];
+                size_limit = bank->size;
-                if (bank->start > ULONG_MAX)
+                if (bank->start >= vmalloc_limit)
-                        highmem = 1;
-#ifdef CONFIG_HIGHMEM
-                if (__va(bank->start) >= vmalloc_min ||
-                    __va(bank->start) < (void *)PAGE_OFFSET)
                        highmem = 1;
+                else
+                        size_limit = vmalloc_limit - bank->start;
                bank->highmem = highmem;
+#ifdef CONFIG_HIGHMEM
                /*
                 * Split those memory banks which are partially overlapping
                 * the vmalloc area greatly simplifying things later.
                 */
-                if (!highmem && __va(bank->start) < vmalloc_min &&
+                if (!highmem && bank->size > size_limit) {
-                    bank->size > vmalloc_min - __va(bank->start)) {
                        if (meminfo.nr_banks >= NR_BANKS) {
                                printk(KERN_CRIT "NR_BANKS too low, "
                                                 "ignoring high memory\n");
@@ -1018,16 +1021,14 @@ void __init sanity_check_meminfo(void)
                                        (meminfo.nr_banks - i) * sizeof(*bank));
                                meminfo.nr_banks++;
                                i++;
-                                bank[1].size -= vmalloc_min - __va(bank->start);
+                                bank[1].size -= size_limit;
-                                bank[1].start = __pa(vmalloc_min - 1) + 1;
+                                bank[1].start = vmalloc_limit;
                                bank[1].highmem = highmem = 1;
                                j++;
                        }
-                        bank->size = vmalloc_min - __va(bank->start);
+                        bank->size = size_limit;
                }
 #else
-                bank->highmem = highmem;
                /*
                 * Highmem banks not allowed with !CONFIG_HIGHMEM.
                 */
@@ -1040,36 +1041,44 @@ void __init sanity_check_meminfo(void)
                }
                /*
-                 * Check whether this memory bank would entirely overlap
-                 * the vmalloc area.
-                 */
-                if (__va(bank->start) >= vmalloc_min ||
-                    __va(bank->start) < (void *)PAGE_OFFSET) {
-                        printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
-                               "(vmalloc region overlap).\n",
-                               (unsigned long long)bank->start,
-                               (unsigned long long)bank->start + bank->size - 1);
-                        continue;
-                }
-                /*
                 * Check whether this memory bank would partially overlap
                 * the vmalloc area.
                 */
-                if (__va(bank->start + bank->size - 1) >= vmalloc_min ||
+                if (bank->size > size_limit) {
-                    __va(bank->start + bank->size - 1) <= __va(bank->start)) {
-                        unsigned long newsize = vmalloc_min - __va(bank->start);
                        printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
                               "to -%.8llx (vmalloc region overlap).\n",
                               (unsigned long long)bank->start,
                               (unsigned long long)bank->start + bank->size - 1,
-                               (unsigned long long)bank->start + newsize - 1);
+                               (unsigned long long)bank->start + size_limit - 1);
-                        bank->size = newsize;
+                        bank->size = size_limit;
                }
 #endif
-                if (!bank->highmem && bank->start + bank->size > arm_lowmem_limit)
+                if (!bank->highmem) {
-                        arm_lowmem_limit = bank->start + bank->size;
+                        phys_addr_t bank_end = bank->start + bank->size;
+                        if (bank_end > arm_lowmem_limit)
+                                arm_lowmem_limit = bank_end;
+                        /*
+                         * Find the first non-section-aligned page, and point
+                         * memblock_limit at it. This relies on rounding the
+                         * limit down to be section-aligned, which happens at
+                         * the end of this function.
+                         *
+                         * With this algorithm, the start or end of almost any
+                         * bank can be non-section-aligned. The only exception
+                         * is that the start of the bank 0 must be section-
+                         * aligned, since otherwise memory would need to be
+                         * allocated when mapping the start of bank 0, which
+                         * occurs before any free memory is mapped.
+                         */
+                        if (!memblock_limit) {
+                                if (!IS_ALIGNED(bank->start, SECTION_SIZE))
+                                        memblock_limit = bank->start;
+                                else if (!IS_ALIGNED(bank_end, SECTION_SIZE))
+                                        memblock_limit = bank_end;
+                        }
+                }
                j++;
        }
 #ifdef CONFIG_HIGHMEM
@@ -1094,7 +1103,18 @@ void __init sanity_check_meminfo(void)
 #endif
        meminfo.nr_banks = j;
        high_memory = __va(arm_lowmem_limit - 1) + 1;
-        memblock_set_current_limit(arm_lowmem_limit);
+        /*
+         * Round the memblock limit down to a section size.  This
+         * helps to ensure that we will allocate memory from the
+         * last full section, which should be mapped.
+         */
+        if (memblock_limit)
+                memblock_limit = round_down(memblock_limit, SECTION_SIZE);
+        if (!memblock_limit)
+                memblock_limit = arm_lowmem_limit;
+        memblock_set_current_limit(memblock_limit);
 }
 static inline void prepare_page_table(void)
@@ -1175,7 +1195,7 @@ static void __init devicemaps_init(struct machine_desc *mdesc)
        /*
         * Allocate the vector page early.
         */
-        vectors = early_alloc(PAGE_SIZE);
+        vectors = early_alloc(PAGE_SIZE * 2);
        early_trap_init(vectors);
@@ -1220,20 +1240,34 @@ static void __init devicemaps_init(struct machine_desc *mdesc)
        map.pfn = __phys_to_pfn(virt_to_phys(vectors));
        map.virtual = 0xffff0000;
        map.length = PAGE_SIZE;
+#ifdef CONFIG_KUSER_HELPERS
        map.type = MT_HIGH_VECTORS;
+#else
+        map.type = MT_LOW_VECTORS;
+#endif
        create_mapping(&map);
        if (!vectors_high()) {
                map.virtual = 0;
+                map.length = PAGE_SIZE * 2;
                map.type = MT_LOW_VECTORS;
                create_mapping(&map);
        }
+        /* Now create a kernel read-only mapping */
+        map.pfn += 1;
+        map.virtual = 0xffff0000 + PAGE_SIZE;
+        map.length = PAGE_SIZE;
+        map.type = MT_LOW_VECTORS;
+        create_mapping(&map);
        /*
         * Ask the machine support to map in the statically mapped devices.
         */
        if (mdesc->map_io)
                mdesc->map_io();
+        else
+                debug_ll_io_init();
        fill_pmd_gaps();
        /* Reserve fixed i/o space in VMALLOC region */
@@ -1289,8 +1323,6 @@ void __init paging_init(struct machine_desc *mdesc)
 {
        void *zero_page;
-        memblock_set_current_limit(arm_lowmem_limit);
        build_mem_type_table();
        prepare_page_table();
        map_lowmem();
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index eb5293a69a84..1fa50100ab6a 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -8,6 +8,7 @@
 #include <linux/pagemap.h>
 #include <linux/io.h>
 #include <linux/memblock.h>
+#include <linux/kernel.h>
 #include <asm/cacheflush.h>
 #include <asm/sections.h>
@@ -15,22 +16,282 @@
 #include <asm/setup.h>
 #include <asm/traps.h>
 #include <asm/mach/arch.h>
+#include <asm/cputype.h>
+#include <asm/mpu.h>
 #include "mm.h"
+#ifdef CONFIG_ARM_MPU
+struct mpu_rgn_info mpu_rgn_info;
+/* Region number */
+static void rgnr_write(u32 v)
+{
+        asm("mcr        p15, 0, %0, c6, c2, 0" : : "r" (v));
+}
+/* Data-side / unified region attributes */
+/* Region access control register */
+static void dracr_write(u32 v)
+{
+        asm("mcr        p15, 0, %0, c6, c1, 4" : : "r" (v));
+}
+/* Region size register */
+static void drsr_write(u32 v)
+{
+        asm("mcr        p15, 0, %0, c6, c1, 2" : : "r" (v));
+}
+/* Region base address register */
+static void drbar_write(u32 v)
+{
+        asm("mcr        p15, 0, %0, c6, c1, 0" : : "r" (v));
+}
+static u32 drbar_read(void)
+{
+        u32 v;
+        asm("mrc        p15, 0, %0, c6, c1, 0" : "=r" (v));
+        return v;
+}
+/* Optional instruction-side region attributes */
+/* I-side Region access control register */
+static void iracr_write(u32 v)
+{
+        asm("mcr        p15, 0, %0, c6, c1, 5" : : "r" (v));
+}
+/* I-side Region size register */
+static void irsr_write(u32 v)
+{
+        asm("mcr        p15, 0, %0, c6, c1, 3" : : "r" (v));
+}
+/* I-side Region base address register */
+static void irbar_write(u32 v)
+{
+        asm("mcr        p15, 0, %0, c6, c1, 1" : : "r" (v));
+}
+static unsigned long irbar_read(void)
+{
+        unsigned long v;
+        asm("mrc        p15, 0, %0, c6, c1, 1" : "=r" (v));
+        return v;
+}
+/* MPU initialisation functions */
+void __init sanity_check_meminfo_mpu(void)
+{
+        int i;
+        struct membank *bank = meminfo.bank;
+        phys_addr_t phys_offset = PHYS_OFFSET;
+        phys_addr_t aligned_region_size, specified_mem_size, rounded_mem_size;
+        /* Initially only use memory continuous from PHYS_OFFSET */
+        if (bank_phys_start(&bank[0]) != phys_offset)
+                panic("First memory bank must be contiguous from PHYS_OFFSET");
+        /* Banks have already been sorted by start address */
+        for (i = 1; i < meminfo.nr_banks; i++) {
+                if (bank[i].start <= bank_phys_end(&bank[0]) &&
+                    bank_phys_end(&bank[i]) > bank_phys_end(&bank[0])) {
+                        bank[0].size = bank_phys_end(&bank[i]) - bank[0].start;
+                } else {
+                        pr_notice("Ignoring RAM after 0x%.8lx. "
+                        "First non-contiguous (ignored) bank start: 0x%.8lx\n",
+                                (unsigned long)bank_phys_end(&bank[0]),
+                                (unsigned long)bank_phys_start(&bank[i]));
+                        break;
+                }
+        }
+        /* All contiguous banks are now merged in to the first bank */
+        meminfo.nr_banks = 1;
+        specified_mem_size = bank[0].size;
+        /*
+         * MPU has curious alignment requirements: Size must be power of 2, and
+         * region start must be aligned to the region size
+         */
+        if (phys_offset != 0)
+                pr_info("PHYS_OFFSET != 0 => MPU Region size constrained by alignment requirements\n");
+        /*
+         * Maximum aligned region might overflow phys_addr_t if phys_offset is
+         * 0. Hence we keep everything below 4G until we take the smaller of
+         * the aligned_region_size and rounded_mem_size, one of which is
+         * guaranteed to be smaller than the maximum physical address.
+         */
+        aligned_region_size = (phys_offset - 1) ^ (phys_offset);
+        /* Find the max power-of-two sized region that fits inside our bank */
+        rounded_mem_size = (1 <<  __fls(bank[0].size)) - 1;
+        /* The actual region size is the smaller of the two */
+        aligned_region_size = aligned_region_size < rounded_mem_size
+                                ? aligned_region_size + 1
+                                : rounded_mem_size + 1;
+        if (aligned_region_size != specified_mem_size)
+                pr_warn("Truncating memory from 0x%.8lx to 0x%.8lx (MPU region constraints)",
+                                (unsigned long)specified_mem_size,
+                                (unsigned long)aligned_region_size);
+        meminfo.bank[0].size = aligned_region_size;
+        pr_debug("MPU Region from 0x%.8lx size 0x%.8lx (end 0x%.8lx))\n",
+                (unsigned long)phys_offset,
+                (unsigned long)aligned_region_size,
+                (unsigned long)bank_phys_end(&bank[0]));
+}
+static int mpu_present(void)
+{
+        return ((read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA) == MMFR0_PMSAv7);
+}
+static int mpu_max_regions(void)
+{
+        /*
+         * We don't support a different number of I/D side regions so if we
+         * have separate instruction and data memory maps then return
+         * whichever side has a smaller number of supported regions.
+         */
+        u32 dregions, iregions, mpuir;
+        mpuir = read_cpuid(CPUID_MPUIR);
+        dregions = iregions = (mpuir & MPUIR_DREGION_SZMASK) >> MPUIR_DREGION;
+        /* Check for separate d-side and i-side memory maps */
+        if (mpuir & MPUIR_nU)
+                iregions = (mpuir & MPUIR_IREGION_SZMASK) >> MPUIR_IREGION;
+        /* Use the smallest of the two maxima */
+        return min(dregions, iregions);
+}
+static int mpu_iside_independent(void)
+{
+        /* MPUIR.nU specifies whether there is *not* a unified memory map */
+        return read_cpuid(CPUID_MPUIR) & MPUIR_nU;
+}
+static int mpu_min_region_order(void)
+{
+        u32 drbar_result, irbar_result;
+        /* We've kept a region free for this probing */
+        rgnr_write(MPU_PROBE_REGION);
+        isb();
+        /*
+         * As per ARM ARM, write 0xFFFFFFFC to DRBAR to find the minimum
+         * region order
+        */
+        drbar_write(0xFFFFFFFC);
+        drbar_result = irbar_result = drbar_read();
+        drbar_write(0x0);
+        /* If the MPU is non-unified, we use the larger of the two minima*/
+        if (mpu_iside_independent()) {
+                irbar_write(0xFFFFFFFC);
+                irbar_result = irbar_read();
+                irbar_write(0x0);
+        }
+        isb(); /* Ensure that MPU region operations have completed */
+        /* Return whichever result is larger */
+        return __ffs(max(drbar_result, irbar_result));
+}
+static int mpu_setup_region(unsigned int number, phys_addr_t start,
+                        unsigned int size_order, unsigned int properties)
+{
+        u32 size_data;
+        /* We kept a region free for probing resolution of MPU regions*/
+        if (number > mpu_max_regions() || number == MPU_PROBE_REGION)
+                return -ENOENT;
+        if (size_order > 32)
+                return -ENOMEM;
+        if (size_order < mpu_min_region_order())
+                return -ENOMEM;
+        /* Writing N to bits 5:1 (RSR_SZ)  specifies region size 2^N+1 */
+        size_data = ((size_order - 1) << MPU_RSR_SZ) | 1 << MPU_RSR_EN;
+        dsb(); /* Ensure all previous data accesses occur with old mappings */
+        rgnr_write(number);
+        isb();
+        drbar_write(start);
+        dracr_write(properties);
+        isb(); /* Propagate properties before enabling region */
+        drsr_write(size_data);
+        /* Check for independent I-side registers */
+        if (mpu_iside_independent()) {
+                irbar_write(start);
+                iracr_write(properties);
+                isb();
+                irsr_write(size_data);
+        }
+        isb();
+        /* Store region info (we treat i/d side the same, so only store d) */
+        mpu_rgn_info.rgns[number].dracr = properties;
+        mpu_rgn_info.rgns[number].drbar = start;
+        mpu_rgn_info.rgns[number].drsr = size_data;
+        return 0;
+}
+/*
+* Set up default MPU regions, doing nothing if there is no MPU
+*/
+void __init mpu_setup(void)
+{
+        int region_err;
+        if (!mpu_present())
+                return;
+        region_err = mpu_setup_region(MPU_RAM_REGION, PHYS_OFFSET,
+                                        ilog2(meminfo.bank[0].size),
+                                        MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL);
+        if (region_err) {
+                panic("MPU region initialization failure! %d", region_err);
+        } else {
+                pr_info("Using ARMv7 PMSA Compliant MPU. "
+                         "Region independence: %s, Max regions: %d\n",
+                        mpu_iside_independent() ? "Yes" : "No",
+                        mpu_max_regions());
+        }
+}
+#else
+static void sanity_check_meminfo_mpu(void) {}
+static void __init mpu_setup(void) {}
+#endif /* CONFIG_ARM_MPU */
 void __init arm_mm_memblock_reserve(void)
 {
+#ifndef CONFIG_CPU_V7M
        /*
         * Register the exception vector page.
         * some architectures which the DRAM is the exception vector to trap,
         * alloc_page breaks with error, although it is not NULL, but "0."
         */
        memblock_reserve(CONFIG_VECTORS_BASE, PAGE_SIZE);
+#else /* ifndef CONFIG_CPU_V7M */
+        /*
+         * There is no dedicated vector page on V7-M. So nothing needs to be
+         * reserved here.
+         */
+#endif
 }
 void __init sanity_check_meminfo(void)
 {
-        phys_addr_t end = bank_phys_end(&meminfo.bank[meminfo.nr_banks - 1]);
+        phys_addr_t end;
+        sanity_check_meminfo_mpu();
+        end = bank_phys_end(&meminfo.bank[meminfo.nr_banks - 1]);
        high_memory = __va(end - 1) + 1;
 }
@@ -41,6 +302,7 @@ void __init sanity_check_meminfo(void)
 void __init paging_init(struct machine_desc *mdesc)
 {
        early_trap_init((void *)CONFIG_VECTORS_BASE);
+        mpu_setup();
        bootmem_init();
 }
@@ -87,16 +349,16 @@ void __iomem *__arm_ioremap_pfn_caller(unsigned long pfn, unsigned long offset,
        return __arm_ioremap_pfn(pfn, offset, size, mtype);
 }
-void __iomem *__arm_ioremap(unsigned long phys_addr, size_t size,
+void __iomem *__arm_ioremap(phys_addr_t phys_addr, size_t size,
                            unsigned int mtype)
 {
        return (void __iomem *)phys_addr;
 }
 EXPORT_SYMBOL(__arm_ioremap);
-void __iomem * (*arch_ioremap_caller)(unsigned long, size_t, unsigned int, void *);
+void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t, unsigned int, void *);
-void __iomem *__arm_ioremap_caller(unsigned long phys_addr, size_t size,
+void __iomem *__arm_ioremap_caller(phys_addr_t phys_addr, size_t size,
                                   unsigned int mtype, void *caller)
 {
        return __arm_ioremap(phys_addr, size, mtype);
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 2bb61e703d6c..d1a2d05971e0 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -443,8 +443,6 @@ ENTRY(cpu_arm1020_set_pte_ext)
 #endif /* CONFIG_MMU */
        mov     pc, lr
-        __CPUINIT
        .type   __arm1020_setup, #function
 __arm1020_setup:
        mov     r0, #0
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index 8f96aa40f510..9d89405c3d03 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -425,8 +425,6 @@ ENTRY(cpu_arm1020e_set_pte_ext)
 #endif /* CONFIG_MMU */
        mov     pc, lr
-        __CPUINIT
        .type   __arm1020e_setup, #function
 __arm1020e_setup:
        mov     r0, #0
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index 8ebe4a469a22..6f01a0ae3b30 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -407,8 +407,6 @@ ENTRY(cpu_arm1022_set_pte_ext)
 #endif /* CONFIG_MMU */
        mov     pc, lr
-        __CPUINIT
        .type   __arm1022_setup, #function
 __arm1022_setup:
        mov     r0, #0
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 093fc7e520c3..4799a24b43e6 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -396,9 +396,6 @@ ENTRY(cpu_arm1026_set_pte_ext)
 #endif /* CONFIG_MMU */
        mov     pc, lr
-        __CPUINIT
        .type   __arm1026_setup, #function
 __arm1026_setup:
        mov     r0, #0
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index 0ac908c7ade1..d42c37f9f5bc 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -116,8 +116,6 @@ ENTRY(cpu_arm720_reset)
 ENDPROC(cpu_arm720_reset)
                .popsection
-        __CPUINIT
        .type   __arm710_setup, #function
 __arm710_setup:
        mov     r0, #0
diff --git a/arch/arm/mm/proc-arm740.S b/arch/arm/mm/proc-arm740.S
index fde2d2a794cf..9b0ae90cbf17 100644
--- a/arch/arm/mm/proc-arm740.S
+++ b/arch/arm/mm/proc-arm740.S
@@ -60,8 +60,6 @@ ENTRY(cpu_arm740_reset)
 ENDPROC(cpu_arm740_reset)
        .popsection
-        __CPUINIT
        .type   __arm740_setup, #function
 __arm740_setup:
        mov     r0, #0
diff --git a/arch/arm/mm/proc-arm7tdmi.S b/arch/arm/mm/proc-arm7tdmi.S
index 6ddea3e464bd..f6cc3f63ce39 100644
--- a/arch/arm/mm/proc-arm7tdmi.S
+++ b/arch/arm/mm/proc-arm7tdmi.S
@@ -51,8 +51,6 @@ ENTRY(cpu_arm7tdmi_reset)
 ENDPROC(cpu_arm7tdmi_reset)
                .popsection
-                __CPUINIT
                .type   __arm7tdmi_setup, #function
 __arm7tdmi_setup:
                mov     pc, lr
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 2556cf1c2da1..549557df6d57 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -410,8 +410,6 @@ ENTRY(cpu_arm920_do_resume)
 ENDPROC(cpu_arm920_do_resume)
 #endif
-        __CPUINIT
        .type   __arm920_setup, #function
 __arm920_setup:
        mov     r0, #0
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index 4464c49d7449..2a758b06c6f6 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -388,8 +388,6 @@ ENTRY(cpu_arm922_set_pte_ext)
 #endif /* CONFIG_MMU */
        mov     pc, lr
-        __CPUINIT
        .type   __arm922_setup, #function
 __arm922_setup:
        mov     r0, #0
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 281eb9b9c1d6..97448c3acf38 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -438,8 +438,6 @@ ENTRY(cpu_arm925_set_pte_ext)
 #endif /* CONFIG_MMU */
        mov     pc, lr
-        __CPUINIT
        .type   __arm925_setup, #function
 __arm925_setup:
        mov     r0, #0
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 344c8a548cc0..0f098f407c9f 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -425,8 +425,6 @@ ENTRY(cpu_arm926_do_resume)
 ENDPROC(cpu_arm926_do_resume)
 #endif
-        __CPUINIT
        .type   __arm926_setup, #function
 __arm926_setup:
        mov     r0, #0
diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
index 8da189d4a402..1c39a704ff6e 100644
--- a/arch/arm/mm/proc-arm940.S
+++ b/arch/arm/mm/proc-arm940.S
@@ -273,8 +273,6 @@ ENDPROC(arm940_dma_unmap_area)
        @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
        define_cache_functions arm940
-        __CPUINIT
        .type   __arm940_setup, #function
 __arm940_setup:
        mov     r0, #0
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
index f666cf34075a..0289cd905e73 100644
--- a/arch/arm/mm/proc-arm946.S
+++ b/arch/arm/mm/proc-arm946.S
@@ -326,8 +326,6 @@ ENTRY(cpu_arm946_dcache_clean_area)
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
        mov     pc, lr
-        __CPUINIT
        .type   __arm946_setup, #function
 __arm946_setup:
        mov     r0, #0
diff --git a/arch/arm/mm/proc-arm9tdmi.S b/arch/arm/mm/proc-arm9tdmi.S
index 8881391dfb9e..f51197ba754a 100644
--- a/arch/arm/mm/proc-arm9tdmi.S
+++ b/arch/arm/mm/proc-arm9tdmi.S
@@ -51,8 +51,6 @@ ENTRY(cpu_arm9tdmi_reset)
 ENDPROC(cpu_arm9tdmi_reset)
                .popsection
-                __CPUINIT
                .type   __arm9tdmi_setup, #function
 __arm9tdmi_setup:
                mov     pc, lr
diff --git a/arch/arm/mm/proc-fa526.S b/arch/arm/mm/proc-fa526.S
index aaeb6c127c7a..2dfc0f1d3bfd 100644
--- a/arch/arm/mm/proc-fa526.S
+++ b/arch/arm/mm/proc-fa526.S
@@ -135,8 +135,6 @@ ENTRY(cpu_fa526_set_pte_ext)
 #endif
        mov     pc, lr
-        __CPUINIT
        .type   __fa526_setup, #function
 __fa526_setup:
        /* On return of this routine, r0 must carry correct flags for CFG register */
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index 4106b09e0c29..d5146b98c8d1 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -514,8 +514,6 @@ ENTRY(cpu_feroceon_set_pte_ext)
 #endif
        mov     pc, lr
-        __CPUINIT
        .type   __feroceon_setup, #function
 __feroceon_setup:
        mov     r0, #0
diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S
index 0b60dd3d742a..40acba595731 100644
--- a/arch/arm/mm/proc-mohawk.S
+++ b/arch/arm/mm/proc-mohawk.S
@@ -383,8 +383,6 @@ ENTRY(cpu_mohawk_do_resume)
 ENDPROC(cpu_mohawk_do_resume)
 #endif
-        __CPUINIT
        .type   __mohawk_setup, #function
 __mohawk_setup:
        mov     r0, #0
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index 775d70fba937..c45319c8f1d9 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -159,8 +159,6 @@ ENTRY(cpu_sa110_set_pte_ext)
 #endif
        mov     pc, lr
-        __CPUINIT
        .type   __sa110_setup, #function
 __sa110_setup:
        mov     r10, #0
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index d92dfd081429..09d241ae2dbe 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -198,8 +198,6 @@ ENTRY(cpu_sa1100_do_resume)
 ENDPROC(cpu_sa1100_do_resume)
 #endif
-        __CPUINIT
        .type   __sa1100_setup, #function
 __sa1100_setup:
        mov     r0, #0
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 919405e20b80..1128064fddcb 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -140,8 +140,10 @@ ENTRY(cpu_v6_set_pte_ext)
 ENTRY(cpu_v6_do_suspend)
        stmfd   sp!, {r4 - r9, lr}
        mrc     p15, 0, r4, c13, c0, 0  @ FCSE/PID
+#ifdef CONFIG_MMU
        mrc     p15, 0, r5, c3, c0, 0   @ Domain ID
        mrc     p15, 0, r6, c2, c0, 1   @ Translation table base 1
+#endif
        mrc     p15, 0, r7, c1, c0, 1   @ auxiliary control register
        mrc     p15, 0, r8, c1, c0, 2   @ co-processor access control
        mrc     p15, 0, r9, c1, c0, 0   @ control register
@@ -158,14 +160,16 @@ ENTRY(cpu_v6_do_resume)
        mcr     p15, 0, ip, c13, c0, 1  @ set reserved context ID
        ldmia   r0, {r4 - r9}
        mcr     p15, 0, r4, c13, c0, 0  @ FCSE/PID
+#ifdef CONFIG_MMU
        mcr     p15, 0, r5, c3, c0, 0   @ Domain ID
        ALT_SMP(orr     r1, r1, #TTB_FLAGS_SMP)
        ALT_UP(orr      r1, r1, #TTB_FLAGS_UP)
        mcr     p15, 0, r1, c2, c0, 0   @ Translation table base 0
        mcr     p15, 0, r6, c2, c0, 1   @ Translation table base 1
+        mcr     p15, 0, ip, c2, c0, 2   @ TTB control register
+#endif
        mcr     p15, 0, r7, c1, c0, 1   @ auxiliary control register
        mcr     p15, 0, r8, c1, c0, 2   @ co-processor access control
-        mcr     p15, 0, ip, c2, c0, 2   @ TTB control register
        mcr     p15, 0, ip, c7, c5, 4   @ ISB
        mov     r0, r9                  @ control register
        b       cpu_resume_mmu
@@ -176,8 +180,6 @@ ENDPROC(cpu_v6_do_resume)
        .align
-        __CPUINIT
 /*
 *      __v6_setup
 *
diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S
index 9704097c450e..bdd3be4be77a 100644
--- a/arch/arm/mm/proc-v7-2level.S
+++ b/arch/arm/mm/proc-v7-2level.S
@@ -110,7 +110,7 @@ ENTRY(cpu_v7_set_pte_ext)
 ARM(   str     r3, [r0, #2048]! )
 THUMB( add     r0, r0, #2048 )
 THUMB( str     r3, [r0] )
-        ALT_SMP(mov     pc,lr)
+        ALT_SMP(W(nop))
        ALT_UP (mcr     p15, 0, r0, c7, c10, 1)         @ flush_pte
 #endif
        mov     pc, lr
@@ -160,8 +160,6 @@ ENDPROC(cpu_v7_set_pte_ext)
        mcr     p15, 0, \ttbr1, c2, c0, 1       @ load TTB1
        .endm
-        __CPUINIT
        /*   AT
         *  TFR   EV X F   I D LR    S
         * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
@@ -172,5 +170,3 @@ ENDPROC(cpu_v7_set_pte_ext)
        .type   v7_crval, #object
 v7_crval:
        crval   clear=0x2120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
-        .previous
diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
index 363027e811d6..01a719e18bb0 100644
--- a/arch/arm/mm/proc-v7-3level.S
+++ b/arch/arm/mm/proc-v7-3level.S
@@ -39,6 +39,14 @@
 #define TTB_FLAGS_SMP   (TTB_IRGN_WBWA|TTB_S|TTB_RGN_OC_WBWA)
 #define PMD_FLAGS_SMP   (PMD_SECT_WBWA|PMD_SECT_S)
+#ifndef __ARMEB__
+#  define rpgdl r0
+#  define rpgdh r1
+#else
+#  define rpgdl r1
+#  define rpgdh r0
+#endif
 /*
 * cpu_v7_switch_mm(pgd_phys, tsk)
 *
@@ -47,10 +55,10 @@
 */
 ENTRY(cpu_v7_switch_mm)
 #ifdef CONFIG_MMU
-        mmid    r1, r1                          @ get mm->context.id
+        mmid    r2, r2
-        asid    r3, r1
+        asid    r2, r2
-        mov     r3, r3, lsl #(48 - 32)          @ ASID
+        orr     rpgdh, rpgdh, r2, lsl #(48 - 32)        @ upper 32-bits of pgd
-        mcrr    p15, 0, r0, r3, c2              @ set TTB 0
+        mcrr    p15, 0, rpgdl, rpgdh, c2                @ set TTB 0
        isb
 #endif
        mov     pc, lr
@@ -73,7 +81,7 @@ ENTRY(cpu_v7_set_pte_ext)
        tst     r3, #1 << (55 - 32)             @ L_PTE_DIRTY
        orreq   r2, #L_PTE_RDONLY
 1:      strd    r2, r3, [r0]
-        ALT_SMP(mov     pc, lr)
+        ALT_SMP(W(nop))
        ALT_UP (mcr     p15, 0, r0, c7, c10, 1)         @ flush_pte
 #endif
        mov     pc, lr
@@ -106,7 +114,8 @@ ENDPROC(cpu_v7_set_pte_ext)
         */
        .macro  v7_ttb_setup, zero, ttbr0, ttbr1, tmp
        ldr     \tmp, =swapper_pg_dir           @ swapper_pg_dir virtual address
-        cmp     \ttbr1, \tmp                    @ PHYS_OFFSET > PAGE_OFFSET? (branch below)
+        mov     \tmp, \tmp, lsr #ARCH_PGD_SHIFT
+        cmp     \ttbr1, \tmp                    @ PHYS_OFFSET > PAGE_OFFSET?
        mrc     p15, 0, \tmp, c2, c0, 2         @ TTB control register
        orr     \tmp, \tmp, #TTB_EAE
        ALT_SMP(orr     \tmp, \tmp, #TTB_FLAGS_SMP)
@@ -114,31 +123,23 @@ ENDPROC(cpu_v7_set_pte_ext)
        ALT_SMP(orr     \tmp, \tmp, #TTB_FLAGS_SMP << 16)
        ALT_UP(orr      \tmp, \tmp, #TTB_FLAGS_UP << 16)
        /*
-         * TTBR0/TTBR1 split (PAGE_OFFSET):
+         * Only use split TTBRs if PHYS_OFFSET <= PAGE_OFFSET (cmp above),
-         *   0x40000000: T0SZ = 2, T1SZ = 0 (not used)
+         * otherwise booting secondary CPUs would end up using TTBR1 for the
-         *   0x80000000: T0SZ = 0, T1SZ = 1
+         * identity mapping set up in TTBR0.
-         *   0xc0000000: T0SZ = 0, T1SZ = 2
-         *
-         * Only use this feature if PHYS_OFFSET <= PAGE_OFFSET, otherwise
-         * booting secondary CPUs would end up using TTBR1 for the identity
-         * mapping set up in TTBR0.
         */
-        bhi     9001f                           @ PHYS_OFFSET > PAGE_OFFSET?
+        orrls   \tmp, \tmp, #TTBR1_SIZE                         @ TTBCR.T1SZ
-        orr     \tmp, \tmp, #(((PAGE_OFFSET >> 30) - 1) << 16) @ TTBCR.T1SZ
+        mcr     p15, 0, \tmp, c2, c0, 2                         @ TTBCR
-#if defined CONFIG_VMSPLIT_2G
+        mov     \tmp, \ttbr1, lsr #(32 - ARCH_PGD_SHIFT)        @ upper bits
-        /* PAGE_OFFSET == 0x80000000, T1SZ == 1 */
+        mov     \ttbr1, \ttbr1, lsl #ARCH_PGD_SHIFT             @ lower bits
-        add     \ttbr1, \ttbr1, #1 << 4         @ skip two L1 entries
+        addls   \ttbr1, \ttbr1, #TTBR1_OFFSET
-#elif defined CONFIG_VMSPLIT_3G
+        mcrr    p15, 1, \ttbr1, \zero, c2                       @ load TTBR1
-        /* PAGE_OFFSET == 0xc0000000, T1SZ == 2 */
+        mov     \tmp, \ttbr0, lsr #(32 - ARCH_PGD_SHIFT)        @ upper bits
-        add     \ttbr1, \ttbr1, #4096 * (1 + 3) @ only L2 used, skip pgd+3*pmd
+        mov     \ttbr0, \ttbr0, lsl #ARCH_PGD_SHIFT             @ lower bits
-#endif
+        mcrr    p15, 0, \ttbr0, \zero, c2                       @ load TTBR0
-        /* CONFIG_VMSPLIT_1G does not need TTBR1 adjustment */
+        mcrr    p15, 1, \ttbr1, \zero, c2                       @ load TTBR1
-9001:   mcr     p15, 0, \tmp, c2, c0, 2         @ TTB control register
+        mcrr    p15, 0, \ttbr0, \zero, c2                       @ load TTBR0
-        mcrr    p15, 1, \ttbr1, \zero, c2       @ load TTBR1
        .endm
-        __CPUINIT
        /*
         *   AT
         *  TFR   EV X F   IHD LR    S
@@ -150,5 +151,3 @@ ENDPROC(cpu_v7_set_pte_ext)
        .type   v7_crval, #object
 v7_crval:
        crval   clear=0x0120c302, mmuset=0x30c23c7d, ucset=0x00c01c7c
-        .previous
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index e35fec34453e..73398bcf9bd8 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -75,13 +75,14 @@ ENTRY(cpu_v7_do_idle)
 ENDPROC(cpu_v7_do_idle)
 ENTRY(cpu_v7_dcache_clean_area)
-        ALT_SMP(mov     pc, lr)                 @ MP extensions imply L1 PTW
+        ALT_SMP(W(nop))                 @ MP extensions imply L1 PTW
-        ALT_UP(W(nop))
+        ALT_UP_B(1f)
-        dcache_line_size r2, r3
+        mov     pc, lr
-1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
+1:      dcache_line_size r2, r3
+2:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
        add     r0, r0, r2
        subs    r1, r1, r2
-        bhi     1b
+        bhi     2b
        dsb
        mov     pc, lr
 ENDPROC(cpu_v7_dcache_clean_area)
@@ -98,9 +99,11 @@ ENTRY(cpu_v7_do_suspend)
        mrc     p15, 0, r4, c13, c0, 0  @ FCSE/PID
        mrc     p15, 0, r5, c13, c0, 3  @ User r/o thread ID
        stmia   r0!, {r4 - r5}
+#ifdef CONFIG_MMU
        mrc     p15, 0, r6, c3, c0, 0   @ Domain ID
        mrc     p15, 0, r7, c2, c0, 1   @ TTB 1
        mrc     p15, 0, r11, c2, c0, 2  @ TTB control register
+#endif
        mrc     p15, 0, r8, c1, c0, 0   @ Control register
        mrc     p15, 0, r9, c1, c0, 1   @ Auxiliary control register
        mrc     p15, 0, r10, c1, c0, 2  @ Co-processor access control
@@ -110,13 +113,14 @@ ENDPROC(cpu_v7_do_suspend)
 ENTRY(cpu_v7_do_resume)
        mov     ip, #0
-        mcr     p15, 0, ip, c8, c7, 0   @ invalidate TLBs
        mcr     p15, 0, ip, c7, c5, 0   @ invalidate I cache
        mcr     p15, 0, ip, c13, c0, 1  @ set reserved context ID
        ldmia   r0!, {r4 - r5}
        mcr     p15, 0, r4, c13, c0, 0  @ FCSE/PID
        mcr     p15, 0, r5, c13, c0, 3  @ User r/o thread ID
        ldmia   r0, {r6 - r11}
+#ifdef CONFIG_MMU
+        mcr     p15, 0, ip, c8, c7, 0   @ invalidate TLBs
        mcr     p15, 0, r6, c3, c0, 0   @ Domain ID
 #ifndef CONFIG_ARM_LPAE
        ALT_SMP(orr     r1, r1, #TTB_FLAGS_SMP)
@@ -125,14 +129,15 @@ ENTRY(cpu_v7_do_resume)
        mcr     p15, 0, r1, c2, c0, 0   @ TTB 0
        mcr     p15, 0, r7, c2, c0, 1   @ TTB 1
        mcr     p15, 0, r11, c2, c0, 2  @ TTB control register
-        mrc     p15, 0, r4, c1, c0, 1   @ Read Auxiliary control register
-        teq     r4, r9                  @ Is it already set?
-        mcrne   p15, 0, r9, c1, c0, 1   @ No, so write it
-        mcr     p15, 0, r10, c1, c0, 2  @ Co-processor access control
        ldr     r4, =PRRR               @ PRRR
        ldr     r5, =NMRR               @ NMRR
        mcr     p15, 0, r4, c10, c2, 0  @ write PRRR
        mcr     p15, 0, r5, c10, c2, 1  @ write NMRR
+#endif  /* CONFIG_MMU */
+        mrc     p15, 0, r4, c1, c0, 1   @ Read Auxiliary control register
+        teq     r4, r9                  @ Is it already set?
+        mcrne   p15, 0, r9, c1, c0, 1   @ No, so write it
+        mcr     p15, 0, r10, c1, c0, 2  @ Co-processor access control
        isb
        dsb
        mov     r0, r8                  @ control register
@@ -163,8 +168,6 @@ ENDPROC(cpu_pj4b_do_idle)
 #endif
-        __CPUINIT
 /*
 *      __v7_setup
 *
@@ -178,7 +181,8 @@ ENDPROC(cpu_pj4b_do_idle)
 */
 __v7_ca5mp_setup:
 __v7_ca9mp_setup:
-        mov     r10, #(1 << 0)                  @ TLB ops broadcasting
+__v7_cr7mp_setup:
+        mov     r10, #(1 << 0)                  @ Cache/TLB ops broadcasting
        b       1f
 __v7_ca7mp_setup:
 __v7_ca15mp_setup:
@@ -443,6 +447,16 @@ __v7_pj4b_proc_info:
 #endif
        /*
+         * ARM Ltd. Cortex R7 processor.
+         */
+        .type   __v7_cr7mp_proc_info, #object
+__v7_cr7mp_proc_info:
+        .long   0x410fc170
+        .long   0xff0ffff0
+        __v7_proc __v7_cr7mp_setup
+        .size   __v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info
+        /*
         * ARM Ltd. Cortex A7 processor.
         */
        .type   __v7_ca7mp_proc_info, #object
diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S
new file mode 100644
index 000000000000..0c93588fcb91
--- /dev/null
+++ b/arch/arm/mm/proc-v7m.S
@@ -0,0 +1,157 @@
+/*
+ *  linux/arch/arm/mm/proc-v7m.S
+ *
+ *  Copyright (C) 2008 ARM Ltd.
+ *  Copyright (C) 2001 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  This is the "shell" of the ARMv7-M processor support.
+ */
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/v7m.h>
+#include "proc-macros.S"
+ENTRY(cpu_v7m_proc_init)
+        mov     pc, lr
+ENDPROC(cpu_v7m_proc_init)
+ENTRY(cpu_v7m_proc_fin)
+        mov     pc, lr
+ENDPROC(cpu_v7m_proc_fin)
+/*
+ *      cpu_v7m_reset(loc)
+ *
+ *      Perform a soft reset of the system.  Put the CPU into the
+ *      same state as it would be if it had been reset, and branch
+ *      to what would be the reset vector.
+ *
+ *      - loc   - location to jump to for soft reset
+ */
+        .align  5
+ENTRY(cpu_v7m_reset)
+        mov     pc, r0
+ENDPROC(cpu_v7m_reset)
+/*
+ *      cpu_v7m_do_idle()
+ *
+ *      Idle the processor (eg, wait for interrupt).
+ *
+ *      IRQs are already disabled.
+ */
+ENTRY(cpu_v7m_do_idle)
+        wfi
+        mov     pc, lr
+ENDPROC(cpu_v7m_do_idle)
+ENTRY(cpu_v7m_dcache_clean_area)
+        mov     pc, lr
+ENDPROC(cpu_v7m_dcache_clean_area)
+/*
+ * There is no MMU, so here is nothing to do.
+ */
+ENTRY(cpu_v7m_switch_mm)
+        mov     pc, lr
+ENDPROC(cpu_v7m_switch_mm)
+.globl  cpu_v7m_suspend_size
+.equ    cpu_v7m_suspend_size, 0
+#ifdef CONFIG_ARM_CPU_SUSPEND
+ENTRY(cpu_v7m_do_suspend)
+        mov     pc, lr
+ENDPROC(cpu_v7m_do_suspend)
+ENTRY(cpu_v7m_do_resume)
+        mov     pc, lr
+ENDPROC(cpu_v7m_do_resume)
+#endif
+        .section ".text.init", #alloc, #execinstr
+/*
+ *      __v7m_setup
+ *
+ *      This should be able to cover all ARMv7-M cores.
+ */
+__v7m_setup:
+        @ Configure the vector table base address
+        ldr     r0, =BASEADDR_V7M_SCB
+        ldr     r12, =vector_table
+        str     r12, [r0, V7M_SCB_VTOR]
+        @ enable UsageFault, BusFault and MemManage fault.
+        ldr     r5, [r0, #V7M_SCB_SHCSR]
+        orr     r5, #(V7M_SCB_SHCSR_USGFAULTENA | V7M_SCB_SHCSR_BUSFAULTENA | V7M_SCB_SHCSR_MEMFAULTENA)
+        str     r5, [r0, #V7M_SCB_SHCSR]
+        @ Lower the priority of the SVC and PendSV exceptions
+        mov     r5, #0x80000000
+        str     r5, [r0, V7M_SCB_SHPR2] @ set SVC priority
+        mov     r5, #0x00800000
+        str     r5, [r0, V7M_SCB_SHPR3] @ set PendSV priority
+        @ SVC to run the kernel in this mode
+        adr     r1, BSYM(1f)
+        ldr     r5, [r12, #11 * 4]      @ read the SVC vector entry
+        str     r1, [r12, #11 * 4]      @ write the temporary SVC vector entry
+        mov     r6, lr                  @ save LR
+        mov     r7, sp                  @ save SP
+        ldr     sp, =__v7m_setup_stack_top
+        cpsie   i
+        svc     #0
+1:      cpsid   i
+        str     r5, [r12, #11 * 4]      @ restore the original SVC vector entry
+        mov     lr, r6                  @ restore LR
+        mov     sp, r7                  @ restore SP
+        @ Special-purpose control register
+        mov     r1, #1
+        msr     control, r1             @ Thread mode has unpriviledged access
+        @ Configure the System Control Register to ensure 8-byte stack alignment
+        @ Note the STKALIGN bit is either RW or RAO.
+        ldr     r12, [r0, V7M_SCB_CCR]  @ system control register
+        orr     r12, #V7M_SCB_CCR_STKALIGN
+        str     r12, [r0, V7M_SCB_CCR]
+        mov     pc, lr
+ENDPROC(__v7m_setup)
+        define_processor_functions v7m, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1
+        .section ".rodata"
+        string cpu_arch_name, "armv7m"
+        string cpu_elf_name "v7m"
+        string cpu_v7m_name "ARMv7-M"
+        .section ".proc.info.init", #alloc, #execinstr
+        /*
+         * Match any ARMv7-M processor core.
+         */
+        .type   __v7m_proc_info, #object
+__v7m_proc_info:
+        .long   0x000f0000              @ Required ID value
+        .long   0x000f0000              @ Mask for ID
+        .long   0                       @ proc_info_list.__cpu_mm_mmu_flags
+        .long   0                       @ proc_info_list.__cpu_io_mmu_flags
+        b       __v7m_setup             @ proc_info_list.__cpu_flush
+        .long   cpu_arch_name
+        .long   cpu_elf_name
+        .long   HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT
+        .long   cpu_v7m_name
+        .long   v7m_processor_functions @ proc_info_list.proc
+        .long   0                       @ proc_info_list.tlb
+        .long   0                       @ proc_info_list.user
+        .long   nop_cache_fns           @ proc_info_list.cache
+        .size   __v7m_proc_info, . - __v7m_proc_info
+__v7m_setup_stack:
+        .space  4 * 8                           @ 8 registers
+__v7m_setup_stack_top:
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index e8efd83b6f25..dc1645890042 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -446,8 +446,6 @@ ENTRY(cpu_xsc3_do_resume)
 ENDPROC(cpu_xsc3_do_resume)
 #endif
-        __CPUINIT
        .type   __xsc3_setup, #function
 __xsc3_setup:
        mov     r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index e766f889bfd6..d19b1cfcad91 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -558,8 +558,6 @@ ENTRY(cpu_xscale_do_resume)
 ENDPROC(cpu_xscale_do_resume)
 #endif
-        __CPUINIT
        .type   __xscale_setup, #function
 __xscale_setup:
        mcr     p15, 0, ip, c7, c7, 0           @ invalidate I, D caches & BTB
diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c
index 1a643ee8e082..f50d223a0bd3 100644
--- a/arch/arm/net/bpf_jit_32.c
+++ b/arch/arm/net/bpf_jit_32.c
@@ -900,8 +900,7 @@ void bpf_jit_compile(struct sk_filter *fp)
 #endif
        alloc_size = 4 * ctx.idx;
-        ctx.target = module_alloc(max(sizeof(struct work_struct),
+        ctx.target = module_alloc(alloc_size);
-                                      alloc_size));
        if (unlikely(ctx.target == NULL))
                goto out;
@@ -927,19 +926,8 @@ out:
        return;
 }
-static void bpf_jit_free_worker(struct work_struct *work)
-{
-        module_free(NULL, work);
-}
 void bpf_jit_free(struct sk_filter *fp)
 {
-        struct work_struct *work;
+        if (fp->bpf_func != sk_run_filter)
+                module_free(NULL, fp->bpf_func);
-        if (fp->bpf_func != sk_run_filter) {
-                work = (struct work_struct *)fp->bpf_func;
-                INIT_WORK(work, bpf_jit_free_worker);
-                schedule_work(work);
-        }
 }
diff --git a/arch/arm/plat-iop/adma.c b/arch/arm/plat-iop/adma.c
index 1ff6a37e893c..a4d1f8de3b5b 100644
--- a/arch/arm/plat-iop/adma.c
+++ b/arch/arm/plat-iop/adma.c
@@ -192,12 +192,10 @@ static int __init iop3xx_adma_cap_init(void)
        #ifdef CONFIG_ARCH_IOP32X /* the 32x AAU does not perform zero sum */
        dma_cap_set(DMA_XOR, iop3xx_aau_data.cap_mask);
-        dma_cap_set(DMA_MEMSET, iop3xx_aau_data.cap_mask);
        dma_cap_set(DMA_INTERRUPT, iop3xx_aau_data.cap_mask);
        #else
        dma_cap_set(DMA_XOR, iop3xx_aau_data.cap_mask);
        dma_cap_set(DMA_XOR_VAL, iop3xx_aau_data.cap_mask);
-        dma_cap_set(DMA_MEMSET, iop3xx_aau_data.cap_mask);
        dma_cap_set(DMA_INTERRUPT, iop3xx_aau_data.cap_mask);
        #endif
diff --git a/arch/arm/plat-iop/gpio.c b/arch/arm/plat-iop/gpio.c
index e4de9be78feb..697de6dc4936 100644
--- a/arch/arm/plat-iop/gpio.c
+++ b/arch/arm/plat-iop/gpio.c
@@ -17,6 +17,7 @@
 #include <linux/gpio.h>
 #include <linux/export.h>
 #include <asm/hardware/iop3xx.h>
+#include <mach/gpio.h>
 void gpio_line_config(int line, int direction)
 {
diff --git a/arch/arm/plat-iop/restart.c b/arch/arm/plat-iop/restart.c
index 33fa699a4d28..3a4d5e5fde52 100644
--- a/arch/arm/plat-iop/restart.c
+++ b/arch/arm/plat-iop/restart.c
@@ -11,7 +11,7 @@
 #include <asm/system_misc.h>
 #include <mach/hardware.h>
-void iop3xx_restart(char mode, const char *cmd)
+void iop3xx_restart(enum reboot_mode mode, const char *cmd)
 {
        *IOP3XX_PCSR = 0x30;
diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c
index 837a2d52e9db..29606bd75f3f 100644
--- a/arch/arm/plat-iop/time.c
+++ b/arch/arm/plat-iop/time.c
@@ -22,9 +22,9 @@
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
 #include <linux/export.h>
+#include <linux/sched_clock.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/sched_clock.h>
 #include <asm/uaccess.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index ce66eb9be481..f82bae2171eb 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -86,22 +86,6 @@ config OMAP_MUX_WARNINGS
          to change the pin multiplexing setup.  When there are no warnings
          printed, it's safe to deselect OMAP_MUX for your product.
-config OMAP_MBOX_FWK
-        tristate "Mailbox framework support"
-        depends on ARCH_OMAP && !ARCH_MULTIPLATFORM
-        help
-          Say Y here if you want to use OMAP Mailbox framework support for
-          DSP, IVA1.0 and IVA2 in OMAP1/2/3.
-config OMAP_MBOX_KFIFO_SIZE
-        int "Mailbox kfifo default buffer size (bytes)"
-        depends on OMAP_MBOX_FWK
-        default 256
-        help
-          Specify the default size of mailbox's kfifo buffers (bytes).
-          This can also be changed at runtime (via the mbox_kfifo_size
-          module parameter).
 config OMAP_IOMMU_IVA2
        bool
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 31199417b56a..0b01b68fd033 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -17,6 +17,3 @@ obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o
 i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o
 obj-y += $(i2c-omap-m) $(i2c-omap-y)
-# OMAP mailbox framework
-obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index 5b0b86bb34bb..d9bc98eb2a6b 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -18,9 +18,9 @@
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/clocksource.h>
+#include <linux/sched_clock.h>
 #include <asm/mach/time.h>
-#include <asm/sched_clock.h>
 #include <plat/counter-32k.h>
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index e06c34bdc34a..4d463ca6821f 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -701,8 +701,8 @@ int omap_request_dma(int dev_id, const char *dev_name,
        for (ch = 0; ch < dma_chan_count; ch++) {
                if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
                        free_ch = ch;
-                        if (dev_id == 0)
+                        /* Exit after first free channel found */
-                                break;
+                        break;
                }
        }
        if (free_ch == -1) {
@@ -894,11 +894,12 @@ void omap_start_dma(int lch)
                int next_lch, cur_lch;
                char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT];
-                dma_chan_link_map[lch] = 1;
                /* Set the link register of the first channel */
                enable_lnk(lch);
                memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
+                dma_chan_link_map[lch] = 1;
                cur_lch = dma_chan[lch].next_lch;
                do {
                        next_lch = dma_chan[cur_lch].next_lch;
@@ -2110,8 +2111,6 @@ exit_dma_irq_fail:
        }
 exit_dma_lch_fail:
-        kfree(p);
-        kfree(d);
        kfree(dma_chan);
        return ret;
 }
@@ -2132,8 +2131,6 @@ static int omap_system_dma_remove(struct platform_device *pdev)
                        free_irq(dma_irq, (void *)(irq_rel + 1));
                }
        }
-        kfree(p);
-        kfree(d);
        kfree(dma_chan);
        return 0;
 }
diff --git a/arch/arm/plat-omap/include/plat/mailbox.h b/arch/arm/plat-omap/include/plat/mailbox.h
deleted file mode 100644
index cc3921e9059c..000000000000
--- a/arch/arm/plat-omap/include/plat/mailbox.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/* mailbox.h */
-#ifndef MAILBOX_H
-#define MAILBOX_H
-#include <linux/spinlock.h>
-#include <linux/workqueue.h>
-#include <linux/interrupt.h>
-#include <linux/device.h>
-#include <linux/kfifo.h>
-typedef u32 mbox_msg_t;
-struct omap_mbox;
-typedef int __bitwise omap_mbox_irq_t;
-#define IRQ_TX ((__force omap_mbox_irq_t) 1)
-#define IRQ_RX ((__force omap_mbox_irq_t) 2)
-typedef int __bitwise omap_mbox_type_t;
-#define OMAP_MBOX_TYPE1 ((__force omap_mbox_type_t) 1)
-#define OMAP_MBOX_TYPE2 ((__force omap_mbox_type_t) 2)
-struct omap_mbox_ops {
-        omap_mbox_type_t        type;
-        int             (*startup)(struct omap_mbox *mbox);
-        void            (*shutdown)(struct omap_mbox *mbox);
-        /* fifo */
-        mbox_msg_t      (*fifo_read)(struct omap_mbox *mbox);
-        void            (*fifo_write)(struct omap_mbox *mbox, mbox_msg_t msg);
-        int             (*fifo_empty)(struct omap_mbox *mbox);
-        int             (*fifo_full)(struct omap_mbox *mbox);
-        /* irq */
-        void            (*enable_irq)(struct omap_mbox *mbox,
-                                                omap_mbox_irq_t irq);
-        void            (*disable_irq)(struct omap_mbox *mbox,
-                                                omap_mbox_irq_t irq);
-        void            (*ack_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
-        int             (*is_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
-        /* ctx */
-        void            (*save_ctx)(struct omap_mbox *mbox);
-        void            (*restore_ctx)(struct omap_mbox *mbox);
-};
-struct omap_mbox_queue {
-        spinlock_t              lock;
-        struct kfifo            fifo;
-        struct work_struct      work;
-        struct tasklet_struct   tasklet;
-        struct omap_mbox        *mbox;
-        bool full;
-};
-struct omap_mbox {
-        char                    *name;
-        unsigned int            irq;
-        struct omap_mbox_queue  *txq, *rxq;
-        struct omap_mbox_ops    *ops;
-        struct device           *dev;
-        void                    *priv;
-        int                     use_count;
-        struct blocking_notifier_head   notifier;
-};
-int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg);
-void omap_mbox_init_seq(struct omap_mbox *);
-struct omap_mbox *omap_mbox_get(const char *, struct notifier_block *nb);
-void omap_mbox_put(struct omap_mbox *mbox, struct notifier_block *nb);
-int omap_mbox_register(struct device *parent, struct omap_mbox **);
-int omap_mbox_unregister(void);
-static inline void omap_mbox_save_ctx(struct omap_mbox *mbox)
-{
-        if (!mbox->ops->save_ctx) {
-                dev_err(mbox->dev, "%s:\tno save\n", __func__);
-                return;
-        }
-        mbox->ops->save_ctx(mbox);
-}
-static inline void omap_mbox_restore_ctx(struct omap_mbox *mbox)
-{
-        if (!mbox->ops->restore_ctx) {
-                dev_err(mbox->dev, "%s:\tno restore\n", __func__);
-                return;
-        }
-        mbox->ops->restore_ctx(mbox);
-}
-static inline void omap_mbox_enable_irq(struct omap_mbox *mbox,
-                                        omap_mbox_irq_t irq)
-{
-        mbox->ops->enable_irq(mbox, irq);
-}
-static inline void omap_mbox_disable_irq(struct omap_mbox *mbox,
-                                         omap_mbox_irq_t irq)
-{
-        mbox->ops->disable_irq(mbox, irq);
-}
-#endif /* MAILBOX_H */
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
deleted file mode 100644
index 42377ef9ea3d..000000000000
--- a/arch/arm/plat-omap/mailbox.c
+++ /dev/null
@@ -1,435 +0,0 @@
-/*
- * OMAP mailbox driver
- *
- * Copyright (C) 2006-2009 Nokia Corporation. All rights reserved.
- *
- * Contact: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- */
-#include <linux/interrupt.h>
-#include <linux/spinlock.h>
-#include <linux/mutex.h>
-#include <linux/delay.h>
-#include <linux/slab.h>
-#include <linux/kfifo.h>
-#include <linux/err.h>
-#include <linux/notifier.h>
-#include <linux/module.h>
-#include <plat/mailbox.h>
-static struct omap_mbox **mboxes;
-static int mbox_configured;
-static DEFINE_MUTEX(mbox_configured_lock);
-static unsigned int mbox_kfifo_size = CONFIG_OMAP_MBOX_KFIFO_SIZE;
-module_param(mbox_kfifo_size, uint, S_IRUGO);
-MODULE_PARM_DESC(mbox_kfifo_size, "Size of omap's mailbox kfifo (bytes)");
-/* Mailbox FIFO handle functions */
-static inline mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox)
-{
-        return mbox->ops->fifo_read(mbox);
-}
-static inline void mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
-{
-        mbox->ops->fifo_write(mbox, msg);
-}
-static inline int mbox_fifo_empty(struct omap_mbox *mbox)
-{
-        return mbox->ops->fifo_empty(mbox);
-}
-static inline int mbox_fifo_full(struct omap_mbox *mbox)
-{
-        return mbox->ops->fifo_full(mbox);
-}
-/* Mailbox IRQ handle functions */
-static inline void ack_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
-{
-        if (mbox->ops->ack_irq)
-                mbox->ops->ack_irq(mbox, irq);
-}
-static inline int is_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
-{
-        return mbox->ops->is_irq(mbox, irq);
-}
-/*
- * message sender
- */
-static int __mbox_poll_for_space(struct omap_mbox *mbox)
-{
-        int ret = 0, i = 1000;
-        while (mbox_fifo_full(mbox)) {
-                if (mbox->ops->type == OMAP_MBOX_TYPE2)
-                        return -1;
-                if (--i == 0)
-                        return -1;
-                udelay(1);
-        }
-        return ret;
-}
-int omap_mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg)
-{
-        struct omap_mbox_queue *mq = mbox->txq;
-        int ret = 0, len;
-        spin_lock_bh(&mq->lock);
-        if (kfifo_avail(&mq->fifo) < sizeof(msg)) {
-                ret = -ENOMEM;
-                goto out;
-        }
-        if (kfifo_is_empty(&mq->fifo) && !__mbox_poll_for_space(mbox)) {
-                mbox_fifo_write(mbox, msg);
-                goto out;
-        }
-        len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
-        WARN_ON(len != sizeof(msg));
-        tasklet_schedule(&mbox->txq->tasklet);
-out:
-        spin_unlock_bh(&mq->lock);
-        return ret;
-}
-EXPORT_SYMBOL(omap_mbox_msg_send);
-static void mbox_tx_tasklet(unsigned long tx_data)
-{
-        struct omap_mbox *mbox = (struct omap_mbox *)tx_data;
-        struct omap_mbox_queue *mq = mbox->txq;
-        mbox_msg_t msg;
-        int ret;
-        while (kfifo_len(&mq->fifo)) {
-                if (__mbox_poll_for_space(mbox)) {
-                        omap_mbox_enable_irq(mbox, IRQ_TX);
-                        break;
-                }
-                ret = kfifo_out(&mq->fifo, (unsigned char *)&msg,
-                                                                sizeof(msg));
-                WARN_ON(ret != sizeof(msg));
-                mbox_fifo_write(mbox, msg);
-        }
-}
-/*
- * Message receiver(workqueue)
- */
-static void mbox_rx_work(struct work_struct *work)
-{
-        struct omap_mbox_queue *mq =
-                        container_of(work, struct omap_mbox_queue, work);
-        mbox_msg_t msg;
-        int len;
-        while (kfifo_len(&mq->fifo) >= sizeof(msg)) {
-                len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
-                WARN_ON(len != sizeof(msg));
-                blocking_notifier_call_chain(&mq->mbox->notifier, len,
-                                                                (void *)msg);
-                spin_lock_irq(&mq->lock);
-                if (mq->full) {
-                        mq->full = false;
-                        omap_mbox_enable_irq(mq->mbox, IRQ_RX);
-                }
-                spin_unlock_irq(&mq->lock);
-        }
-}
-/*
- * Mailbox interrupt handler
- */
-static void __mbox_tx_interrupt(struct omap_mbox *mbox)
-{
-        omap_mbox_disable_irq(mbox, IRQ_TX);
-        ack_mbox_irq(mbox, IRQ_TX);
-        tasklet_schedule(&mbox->txq->tasklet);
-}
-static void __mbox_rx_interrupt(struct omap_mbox *mbox)
-{
-        struct omap_mbox_queue *mq = mbox->rxq;
-        mbox_msg_t msg;
-        int len;
-        while (!mbox_fifo_empty(mbox)) {
-                if (unlikely(kfifo_avail(&mq->fifo) < sizeof(msg))) {
-                        omap_mbox_disable_irq(mbox, IRQ_RX);
-                        mq->full = true;
-                        goto nomem;
-                }
-                msg = mbox_fifo_read(mbox);
-                len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
-                WARN_ON(len != sizeof(msg));
-                if (mbox->ops->type == OMAP_MBOX_TYPE1)
-                        break;
-        }
-        /* no more messages in the fifo. clear IRQ source. */
-        ack_mbox_irq(mbox, IRQ_RX);
-nomem:
-        schedule_work(&mbox->rxq->work);
-}
-static irqreturn_t mbox_interrupt(int irq, void *p)
-{
-        struct omap_mbox *mbox = p;
-        if (is_mbox_irq(mbox, IRQ_TX))
-                __mbox_tx_interrupt(mbox);
-        if (is_mbox_irq(mbox, IRQ_RX))
-                __mbox_rx_interrupt(mbox);
-        return IRQ_HANDLED;
-}
-static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox,
-                                        void (*work) (struct work_struct *),
-                                        void (*tasklet)(unsigned long))
-{
-        struct omap_mbox_queue *mq;
-        mq = kzalloc(sizeof(struct omap_mbox_queue), GFP_KERNEL);
-        if (!mq)
-                return NULL;
-        spin_lock_init(&mq->lock);
-        if (kfifo_alloc(&mq->fifo, mbox_kfifo_size, GFP_KERNEL))
-                goto error;
-        if (work)
-                INIT_WORK(&mq->work, work);
-        if (tasklet)
-                tasklet_init(&mq->tasklet, tasklet, (unsigned long)mbox);
-        return mq;
-error:
-        kfree(mq);
-        return NULL;
-}
-static void mbox_queue_free(struct omap_mbox_queue *q)
-{
-        kfifo_free(&q->fifo);
-        kfree(q);
-}
-static int omap_mbox_startup(struct omap_mbox *mbox)
-{
-        int ret = 0;
-        struct omap_mbox_queue *mq;
-        mutex_lock(&mbox_configured_lock);
-        if (!mbox_configured++) {
-                if (likely(mbox->ops->startup)) {
-                        ret = mbox->ops->startup(mbox);
-                        if (unlikely(ret))
-                                goto fail_startup;
-                } else
-                        goto fail_startup;
-        }
-        if (!mbox->use_count++) {
-                ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED,
-                                                        mbox->name, mbox);
-                if (unlikely(ret)) {
-                        pr_err("failed to register mailbox interrupt:%d\n",
-                                                                        ret);
-                        goto fail_request_irq;
-                }
-                mq = mbox_queue_alloc(mbox, NULL, mbox_tx_tasklet);
-                if (!mq) {
-                        ret = -ENOMEM;
-                        goto fail_alloc_txq;
-                }
-                mbox->txq = mq;
-                mq = mbox_queue_alloc(mbox, mbox_rx_work, NULL);
-                if (!mq) {
-                        ret = -ENOMEM;
-                        goto fail_alloc_rxq;
-                }
-                mbox->rxq = mq;
-                mq->mbox = mbox;
-                omap_mbox_enable_irq(mbox, IRQ_RX);
-        }
-        mutex_unlock(&mbox_configured_lock);
-        return 0;
-fail_alloc_rxq:
-        mbox_queue_free(mbox->txq);
-fail_alloc_txq:
-        free_irq(mbox->irq, mbox);
-fail_request_irq:
-        if (mbox->ops->shutdown)
-                mbox->ops->shutdown(mbox);
-        mbox->use_count--;
-fail_startup:
-        mbox_configured--;
-        mutex_unlock(&mbox_configured_lock);
-        return ret;
-}
-static void omap_mbox_fini(struct omap_mbox *mbox)
-{
-        mutex_lock(&mbox_configured_lock);
-        if (!--mbox->use_count) {
-                omap_mbox_disable_irq(mbox, IRQ_RX);
-                free_irq(mbox->irq, mbox);
-                tasklet_kill(&mbox->txq->tasklet);
-                flush_work(&mbox->rxq->work);
-                mbox_queue_free(mbox->txq);
-                mbox_queue_free(mbox->rxq);
-        }
-        if (likely(mbox->ops->shutdown)) {
-                if (!--mbox_configured)
-                        mbox->ops->shutdown(mbox);
-        }
-        mutex_unlock(&mbox_configured_lock);
-}
-struct omap_mbox *omap_mbox_get(const char *name, struct notifier_block *nb)
-{
-        struct omap_mbox *_mbox, *mbox = NULL;
-        int i, ret;
-        if (!mboxes)
-                return ERR_PTR(-EINVAL);
-        for (i = 0; (_mbox = mboxes[i]); i++) {
-                if (!strcmp(_mbox->name, name)) {
-                        mbox = _mbox;
-                        break;
-                }
-        }
-        if (!mbox)
-                return ERR_PTR(-ENOENT);
-        if (nb)
-                blocking_notifier_chain_register(&mbox->notifier, nb);
-        ret = omap_mbox_startup(mbox);
-        if (ret) {
-                blocking_notifier_chain_unregister(&mbox->notifier, nb);
-                return ERR_PTR(-ENODEV);
-        }
-        return mbox;
-}
-EXPORT_SYMBOL(omap_mbox_get);
-void omap_mbox_put(struct omap_mbox *mbox, struct notifier_block *nb)
-{
-        blocking_notifier_chain_unregister(&mbox->notifier, nb);
-        omap_mbox_fini(mbox);
-}
-EXPORT_SYMBOL(omap_mbox_put);
-static struct class omap_mbox_class = { .name = "mbox", };
-int omap_mbox_register(struct device *parent, struct omap_mbox **list)
-{
-        int ret;
-        int i;
-        mboxes = list;
-        if (!mboxes)
-                return -EINVAL;
-        for (i = 0; mboxes[i]; i++) {
-                struct omap_mbox *mbox = mboxes[i];
-                mbox->dev = device_create(&omap_mbox_class,
-                                parent, 0, mbox, "%s", mbox->name);
-                if (IS_ERR(mbox->dev)) {
-                        ret = PTR_ERR(mbox->dev);
-                        goto err_out;
-                }
-                BLOCKING_INIT_NOTIFIER_HEAD(&mbox->notifier);
-        }
-        return 0;
-err_out:
-        while (i--)
-                device_unregister(mboxes[i]->dev);
-        return ret;
-}
-EXPORT_SYMBOL(omap_mbox_register);
-int omap_mbox_unregister(void)
-{
-        int i;
-        if (!mboxes)
-                return -EINVAL;
-        for (i = 0; mboxes[i]; i++)
-                device_unregister(mboxes[i]->dev);
-        mboxes = NULL;
-        return 0;
-}
-EXPORT_SYMBOL(omap_mbox_unregister);
-static int __init omap_mbox_init(void)
-{
-        int err;
-        err = class_register(&omap_mbox_class);
-        if (err)
-                return err;
-        /* kfifo size sanity check: alignment and minimal size */
-        mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(mbox_msg_t));
-        mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size,
-                                                        sizeof(mbox_msg_t));
-        return 0;
-}
-subsys_initcall(omap_mbox_init);
-static void __exit omap_mbox_exit(void)
-{
-        class_unregister(&omap_mbox_class);
-}
-module_exit(omap_mbox_exit);
-MODULE_LICENSE("GPL v2");
-MODULE_DESCRIPTION("omap mailbox: interrupt driven messaging");
-MODULE_AUTHOR("Toshihiro Kobayashi");
-MODULE_AUTHOR("Hiroshi DOYU");
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
index c019b7aaf776..c66d163d7a2a 100644
--- a/arch/arm/plat-orion/common.c
+++ b/arch/arm/plat-orion/common.c
@@ -666,14 +666,9 @@ void __init orion_xor0_init(unsigned long mapbase_low,
        orion_xor0_shared_resources[3].start = irq_1;
        orion_xor0_shared_resources[3].end = irq_1;
-        /*
-         * two engines can't do memset simultaneously, this limitation
-         * satisfied by removing memset support from one of the engines.
-         */
        dma_cap_set(DMA_MEMCPY, orion_xor0_channels_data[0].cap_mask);
        dma_cap_set(DMA_XOR, orion_xor0_channels_data[0].cap_mask);
-        dma_cap_set(DMA_MEMSET, orion_xor0_channels_data[1].cap_mask);
        dma_cap_set(DMA_MEMCPY, orion_xor0_channels_data[1].cap_mask);
        dma_cap_set(DMA_XOR, orion_xor0_channels_data[1].cap_mask);
@@ -732,14 +727,9 @@ void __init orion_xor1_init(unsigned long mapbase_low,
        orion_xor1_shared_resources[3].start = irq_1;
        orion_xor1_shared_resources[3].end = irq_1;
-        /*
-         * two engines can't do memset simultaneously, this limitation
-         * satisfied by removing memset support from one of the engines.
-         */
        dma_cap_set(DMA_MEMCPY, orion_xor1_channels_data[0].cap_mask);
        dma_cap_set(DMA_XOR, orion_xor1_channels_data[0].cap_mask);
-        dma_cap_set(DMA_MEMSET, orion_xor1_channels_data[1].cap_mask);
        dma_cap_set(DMA_MEMCPY, orion_xor1_channels_data[1].cap_mask);
        dma_cap_set(DMA_XOR, orion_xor1_channels_data[1].cap_mask);
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index 249fe6333e18..6816192a7561 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -426,7 +426,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
                if (!(cause & (1 << i)))
                        continue;
-                type = irqd_get_trigger_type(irq_get_irq_data(irq));
+                type = irq_get_trigger_type(irq);
                if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
                        /* Swap polarity (race with GPIO line) */
                        u32 polarity;
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c
index 5d5ac0f05422..9d2b2ac74938 100644
--- a/arch/arm/plat-orion/time.c
+++ b/arch/arm/plat-orion/time.c
@@ -16,7 +16,7 @@
 #include <linux/clockchips.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
-#include <asm/sched_clock.h>
+#include <linux/sched_clock.h>
 /*
 * MBus bridge block registers.
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index f8ed2de0a678..a5b5ff6e68d2 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -6,7 +6,7 @@
 config PLAT_SAMSUNG
        bool
-        depends on PLAT_S3C24XX || ARCH_S3C64XX || PLAT_S5P
+        depends on PLAT_S3C24XX || ARCH_S3C64XX || PLAT_S5P || ARCH_EXYNOS
        default y
        select GENERIC_IRQ_CHIP
        select NO_IOPORT
@@ -15,12 +15,10 @@ config PLAT_SAMSUNG
 config PLAT_S5P
        bool
-        depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
+        depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210)
        default y
        select ARCH_REQUIRE_GPIOLIB
-        select ARM_GIC if ARCH_EXYNOS
+        select ARM_VIC
-        select ARM_VIC if !ARCH_EXYNOS
-        select GIC_NON_BANKED if ARCH_EXYNOS4
        select NO_IOPORT
        select PLAT_SAMSUNG
        select S3C_GPIO_TRACK
@@ -31,6 +29,13 @@ config PLAT_S5P
        help
          Base platform code for Samsung's S5P series SoC.
+config SAMSUNG_PM
+        bool
+        depends on PM && (PLAT_S3C24XX || ARCH_S3C64XX || ARCH_S5P64X0 || S5P_PM)
+        default y
+        help
+          Base platform power management code for samsung code
 if PLAT_SAMSUNG
 # boot configurations
@@ -60,6 +65,20 @@ config S3C_LOWLEVEL_UART_PORT
          this configuration should be between zero and two. The port
          must have been initialised by the boot-loader before use.
+config SAMSUNG_ATAGS
+        def_bool n
+        depends on !ARCH_MULTIPLATFORM
+        depends on ATAGS
+        help
+           This option enables ATAGS based boot support code for
+           Samsung platforms, including static platform devices, legacy
+           clock, timer and interrupt initialization, etc.
+           Platforms that support only DT based boot need not to select
+           this option.
+if SAMSUNG_ATAGS
 # timer options
 config SAMSUNG_HRT
@@ -367,11 +386,6 @@ config S5P_DEV_JPEG
        help
          Compile in platform device definitions for JPEG codec
-config S5P_DEV_MFC
-        bool
-        help
-          Compile in setup memory (init) code for MFC
 config S5P_DEV_ONENAND
        bool
        help
@@ -412,6 +426,21 @@ config S3C_DMA
        help
          Internal configuration for S3C DMA core
+config S5P_IRQ_PM
+        bool
+        default y if S5P_PM
+        help
+          Legacy IRQ power management for S5P platforms
+config SAMSUNG_PM_GPIO
+        bool
+        default y if GPIO_SAMSUNG && PM
+        help
+          Include legacy GPIO power management code for platforms not using
+          pinctrl-samsung driver.
+endif
 config SAMSUNG_DMADEV
        bool
        select ARM_AMBA
@@ -421,6 +450,11 @@ config SAMSUNG_DMADEV
        help
          Use DMA device engine for PL330 DMAC.
+config S5P_DEV_MFC
+        bool
+        help
+          Compile in setup memory (init) code for MFC
 comment "Power management"
 config SAMSUNG_PM_DEBUG
@@ -475,6 +509,12 @@ config SAMSUNG_WAKEMASK
          and above. This code allows a set of interrupt to wakeup-mask
          mappings. See <plat/wakeup-mask.h>
+config SAMSUNG_WDT_RESET
+        bool
+        help
+          Compile support for system restart by triggering watchdog reset.
+          Used on SoCs that do not provide dedicated reset control.
 config S5P_PM
        bool
        help
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index a23c460299a1..199bbe304d02 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -31,10 +31,10 @@ obj-$(CONFIG_S3C_ADC)	+= adc.o
 # devices
-obj-y                           += platformdata.o
+obj-$(CONFIG_SAMSUNG_ATAGS)     += platformdata.o
-obj-y                           += devs.o
+obj-$(CONFIG_SAMSUNG_ATAGS)     += devs.o
-obj-y                           += dev-uart.o
+obj-$(CONFIG_SAMSUNG_ATAGS)     += dev-uart.o
 obj-$(CONFIG_S5P_DEV_MFC)       += s5p-dev-mfc.o
 obj-$(CONFIG_S5P_DEV_UART)      += s5p-dev-uart.o
@@ -51,11 +51,13 @@ obj-$(CONFIG_SAMSUNG_DMADEV)	+= dma-ops.o
 # PM support
-obj-$(CONFIG_PM)                += pm.o
+obj-$(CONFIG_SAMSUNG_PM)        += pm.o
-obj-$(CONFIG_PM)                += pm-gpio.o
+obj-$(CONFIG_SAMSUNG_PM_GPIO)   += pm-gpio.o
 obj-$(CONFIG_SAMSUNG_PM_CHECK)  += pm-check.o
 obj-$(CONFIG_SAMSUNG_WAKEMASK)  += wakeup-mask.o
+obj-$(CONFIG_SAMSUNG_WDT_RESET) += watchdog-reset.o
-obj-$(CONFIG_S5P_PM)            += s5p-pm.o s5p-irq-pm.o
+obj-$(CONFIG_S5P_PM)            += s5p-pm.o
+obj-$(CONFIG_S5P_IRQ_PM)        += s5p-irq-pm.o
 obj-$(CONFIG_S5P_SLEEP)         += s5p-sleep.o
diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h
index a62753dc15ba..df45d6edc98d 100644
--- a/arch/arm/plat-samsung/include/plat/clock.h
+++ b/arch/arm/plat-samsung/include/plat/clock.h
@@ -83,6 +83,11 @@ extern struct clk clk_ext;
 extern struct clksrc_clk clk_epllref;
 extern struct clksrc_clk clk_esysclk;
+/* S3C24XX UART clocks */
+extern struct clk s3c24xx_clk_uart0;
+extern struct clk s3c24xx_clk_uart1;
+extern struct clk s3c24xx_clk_uart2;
 /* S3C64XX specific clocks */
 extern struct clk clk_h2;
 extern struct clk clk_27m;
diff --git a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
index 95509d8eb140..7231c8e4975e 100644
--- a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
+++ b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
@@ -202,7 +202,7 @@ extern int s3c_plltab_register(struct cpufreq_frequency_table *plls,
 extern struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void);
 extern struct s3c_iotimings *s3c_cpufreq_getiotimings(void);
-#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUGFS
+#ifdef CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS
 #define s3c_cpufreq_debugfs_call(x) x
 #else
 #define s3c_cpufreq_debugfs_call(x) NULL
@@ -259,17 +259,17 @@ extern void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg,
 #define s3c2412_iotiming_set NULL
 #endif /* CONFIG_S3C2412_IOTIMING */
-#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUG
+#ifdef CONFIG_ARM_S3C24XX_CPUFREQ_DEBUG
 #define s3c_freq_dbg(x...) printk(KERN_INFO x)
 #else
 #define s3c_freq_dbg(x...) do { if (0) printk(x); } while (0)
-#endif /* CONFIG_CPU_FREQ_S3C24XX_DEBUG */
+#endif /* CONFIG_ARM_S3C24XX_CPUFREQ_DEBUG */
-#ifdef CONFIG_CPU_FREQ_S3C24XX_IODEBUG
+#ifdef CONFIG_ARM_S3C24XX_CPUFREQ_IODEBUG
 #define s3c_freq_iodbg(x...) printk(KERN_INFO x)
 #else
 #define s3c_freq_iodbg(x...) do { if (0) printk(x); } while (0)
-#endif /* CONFIG_CPU_FREQ_S3C24XX_IODEBUG */
+#endif /* CONFIG_ARM_S3C24XX_CPUFREQ_IODEBUG */
 static inline int s3c_cpufreq_addfreq(struct cpufreq_frequency_table *table,
                                      int index, size_t table_size,
@@ -285,7 +285,7 @@ static inline int s3c_cpufreq_addfreq(struct cpufreq_frequency_table *table,
                s3c_freq_dbg("%s: { %d = %u kHz }\n",
                             __func__, index, freq);
-                table[index].index = index;
+                table[index].driver_data = index;
                table[index].frequency = freq;
        }
diff --git a/arch/arm/plat-samsung/include/plat/cpu-freq.h b/arch/arm/plat-samsung/include/plat/cpu-freq.h
index 80c4a809c721..85517ab962ae 100644
--- a/arch/arm/plat-samsung/include/plat/cpu-freq.h
+++ b/arch/arm/plat-samsung/include/plat/cpu-freq.h
@@ -126,7 +126,7 @@ struct s3c_cpufreq_board {
 };
 /* Things depending on frequency scaling. */
-#ifdef CONFIG_CPU_FREQ_S3C
+#ifdef CONFIG_ARM_S3C_CPUFREQ
 #define __init_or_cpufreq
 #else
 #define __init_or_cpufreq __init
@@ -134,7 +134,7 @@ struct s3c_cpufreq_board {
 /* Board functions */
-#ifdef CONFIG_CPU_FREQ_S3C
+#ifdef CONFIG_ARM_S3C_CPUFREQ
 extern int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board);
 #else
@@ -142,4 +142,4 @@ static inline int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board)
 {
        return 0;
 }
-#endif  /* CONFIG_CPU_FREQ_S3C */
+#endif  /* CONFIG_ARM_S3C_CPUFREQ */
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 989fefe18be6..4fb1f03a10d1 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -46,6 +46,7 @@ extern unsigned long samsung_cpu_id;
 #define EXYNOS4_CPU_MASK        0xFFFE0000
 #define EXYNOS5250_SOC_ID       0x43520000
+#define EXYNOS5420_SOC_ID       0xE5420000
 #define EXYNOS5440_SOC_ID       0xE5440000
 #define EXYNOS5_SOC_MASK        0xFFFFF000
@@ -67,6 +68,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
+IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK)
 IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
 #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
@@ -142,6 +144,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
 # define soc_is_exynos5250()    0
 #endif
+#if defined(CONFIG_SOC_EXYNOS5420)
+# define soc_is_exynos5420()    is_samsung_exynos5420()
+#else
+# define soc_is_exynos5420()    0
+#endif
 #if defined(CONFIG_SOC_EXYNOS5440)
 # define soc_is_exynos5440()    is_samsung_exynos5440()
 #else
diff --git a/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h b/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
index d01576318b2c..bd3a6db14cbb 100644
--- a/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
+++ b/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
@@ -28,7 +28,6 @@ struct s3c24xx_dma_map {
        const char              *name;
        unsigned long            channels[S3C_DMA_CHANNELS];
-        unsigned long            channels_rx[S3C_DMA_CHANNELS];
 };
 struct s3c24xx_dma_selection {
@@ -38,10 +37,6 @@ struct s3c24xx_dma_selection {
        void    (*select)(struct s3c2410_dma_chan *chan,
                          struct s3c24xx_dma_map *map);
-        void    (*direction)(struct s3c2410_dma_chan *chan,
-                             struct s3c24xx_dma_map *map,
-                             enum dma_data_direction dir);
 };
 extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel);
diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h
index f6fcadeee969..6bc1a8f471e3 100644
--- a/arch/arm/plat-samsung/include/plat/pm.h
+++ b/arch/arm/plat-samsung/include/plat/pm.h
@@ -19,7 +19,7 @@
 struct device;
-#ifdef CONFIG_PM
+#ifdef CONFIG_SAMSUNG_PM
 extern __init int s3c_pm_init(void);
 extern __init int s3c64xx_pm_init(void);
@@ -58,8 +58,6 @@ extern unsigned char pm_uart_udivslot;  /* true to save UART UDIVSLOT */
 /* from sleep.S */
-extern void s3c_cpu_resume(void);
 extern int s3c2410_cpu_suspend(unsigned long);
 /* sleep save info */
@@ -106,12 +104,14 @@ extern void s3c_pm_do_save(struct sleep_save *ptr, int count);
 extern void s3c_pm_do_restore(struct sleep_save *ptr, int count);
 extern void s3c_pm_do_restore_core(struct sleep_save *ptr, int count);
-#ifdef CONFIG_PM
+#ifdef CONFIG_SAMSUNG_PM
 extern int s3c_irq_wake(struct irq_data *data, unsigned int state);
 extern int s3c_irqext_wake(struct irq_data *data, unsigned int state);
+extern void s3c_cpu_resume(void);
 #else
 #define s3c_irq_wake NULL
 #define s3c_irqext_wake NULL
+#define s3c_cpu_resume NULL
 #endif
 /* PM debug functions */
@@ -166,6 +166,7 @@ extern void s3c_pm_check_store(void);
 */
 extern void s3c_pm_configure_extint(void);
+#ifdef CONFIG_GPIO_SAMSUNG
 /**
 * samsung_pm_restore_gpios() - restore the state of the gpios after sleep.
 *
@@ -181,6 +182,10 @@ extern void samsung_pm_restore_gpios(void);
 * Save the GPIO states for resotration on resume. See samsung_pm_restore_gpios().
 */
 extern void samsung_pm_save_gpios(void);
+#else
+static inline void samsung_pm_restore_gpios(void) {}
+static inline void samsung_pm_save_gpios(void) {}
+#endif
 extern void s3c_pm_save_core(void);
 extern void s3c_pm_restore_core(void);
diff --git a/arch/arm/plat-samsung/include/plat/regs-watchdog.h b/arch/arm/plat-samsung/include/plat/regs-watchdog.h
deleted file mode 100644
index 4938492470f7..000000000000
--- a/arch/arm/plat-samsung/include/plat/regs-watchdog.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-watchdog.h
- *
- * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
- *                    http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 Watchdog timer control
-*/
-#ifndef __ASM_ARCH_REGS_WATCHDOG_H
-#define __ASM_ARCH_REGS_WATCHDOG_H
-#define S3C_WDOGREG(x) ((x) + S3C_VA_WATCHDOG)
-#define S3C2410_WTCON      S3C_WDOGREG(0x00)
-#define S3C2410_WTDAT      S3C_WDOGREG(0x04)
-#define S3C2410_WTCNT      S3C_WDOGREG(0x08)
-/* the watchdog can either generate a reset pulse, or an
- * interrupt.
- */
-#define S3C2410_WTCON_RSTEN   (0x01)
-#define S3C2410_WTCON_INTEN   (1<<2)
-#define S3C2410_WTCON_ENABLE  (1<<5)
-#define S3C2410_WTCON_DIV16   (0<<3)
-#define S3C2410_WTCON_DIV32   (1<<3)
-#define S3C2410_WTCON_DIV64   (2<<3)
-#define S3C2410_WTCON_DIV128  (3<<3)
-#define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
-#define S3C2410_WTCON_PRESCALE_MASK (0xff00)
-#endif /* __ASM_ARCH_REGS_WATCHDOG_H */
diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h
index 02b66d723d1a..4afc32f90b6d 100644
--- a/arch/arm/plat-samsung/include/plat/uncompress.h
+++ b/arch/arm/plat-samsung/include/plat/uncompress.h
@@ -21,6 +21,8 @@ typedef unsigned int upf_t;	/* cannot include linux/serial_core.h */
 unsigned int fifo_mask;
 unsigned int fifo_max;
+volatile u8 *uart_base;
 /* forward declerations */
 static void arch_detect_cpu(void);
@@ -28,19 +30,24 @@ static void arch_detect_cpu(void);
 /* defines for UART registers */
 #include <plat/regs-serial.h>
-#include <plat/regs-watchdog.h>
 /* working in physical space... */
-#undef S3C2410_WDOGREG
+#define S3C_WDOGREG(x)  ((S3C_PA_WDT + (x)))
-#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
+#define S3C2410_WTCON   S3C_WDOGREG(0x00)
+#define S3C2410_WTDAT   S3C_WDOGREG(0x04)
+#define S3C2410_WTCNT   S3C_WDOGREG(0x08)
+#define S3C2410_WTCON_RSTEN     (1 << 0)
+#define S3C2410_WTCON_ENABLE    (1 << 5)
+#define S3C2410_WTCON_DIV128    (3 << 3)
+#define S3C2410_WTCON_PRESCALE(x)       ((x) << 8)
 /* how many bytes we allow into the FIFO at a time in FIFO mode */
 #define FIFO_MAX         (14)
-#ifdef S3C_PA_UART
-#define uart_base S3C_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT)
-#endif
 static __inline__ void
 uart_wr(unsigned int reg, unsigned int val)
 {
diff --git a/arch/arm/plat-samsung/include/plat/watchdog-reset.h b/arch/arm/plat-samsung/include/plat/watchdog-reset.h
index bc4db9b04e36..0386b8f76623 100644
--- a/arch/arm/plat-samsung/include/plat/watchdog-reset.h
+++ b/arch/arm/plat-samsung/include/plat/watchdog-reset.h
@@ -10,37 +10,11 @@
 * published by the Free Software Foundation.
 */
-#include <plat/clock.h>
+#ifndef __PLAT_SAMSUNG_WATCHDOG_RESET_H
-#include <plat/regs-watchdog.h>
+#define __PLAT_SAMSUNG_WATCHDOG_RESET_H
-#include <mach/map.h>
-#include <linux/clk.h>
+extern void samsung_wdt_reset(void);
-#include <linux/err.h>
+extern void samsung_wdt_reset_of_init(void);
-#include <linux/io.h>
+extern void samsung_wdt_reset_init(void __iomem *base);
-#include <linux/delay.h>
-static inline void arch_wdt_reset(void)
+#endif /* __PLAT_SAMSUNG_WATCHDOG_RESET_H */
-{
-        printk("arch_reset: attempting watchdog reset\n");
-        __raw_writel(0, S3C2410_WTCON);   /* disable watchdog, to be safe  */
-        if (!IS_ERR(s3c2410_wdtclk))
-                clk_enable(s3c2410_wdtclk);
-        /* put initial values into count and data */
-        __raw_writel(0x80, S3C2410_WTCNT);
-        __raw_writel(0x80, S3C2410_WTDAT);
-        /* set the watchdog to go and reset... */
-        __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN |
-                     S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON);
-        /* wait for reset to assert... */
-        mdelay(500);
-        printk(KERN_ERR "Watchdog reset failed to assert reset\n");
-        /* delay to allow the serial port to show the message */
-        mdelay(50);
-}
diff --git a/arch/arm/plat-samsung/init.c b/arch/arm/plat-samsung/init.c
index 79d10fca9090..3e5c4619caa5 100644
--- a/arch/arm/plat-samsung/init.c
+++ b/arch/arm/plat-samsung/init.c
@@ -87,7 +87,7 @@ void __init s3c24xx_init_clocks(int xtal)
 }
 /* uart management */
+#if IS_ENABLED(CONFIG_SAMSUNG_ATAGS)
 static int nr_uarts __initdata = 0;
 static struct s3c2410_uartcfg uart_cfgs[CONFIG_SERIAL_SAMSUNG_UARTS];
@@ -134,11 +134,12 @@ void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
        if (cpu == NULL)
                return;
-        if (cpu->init_uarts == NULL) {
+        if (cpu->init_uarts == NULL && IS_ENABLED(CONFIG_SAMSUNG_ATAGS)) {
                printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n");
        } else
                (cpu->init_uarts)(cfg, no);
 }
+#endif
 static int __init s3c_arch_init(void)
 {
@@ -152,8 +153,9 @@ static int __init s3c_arch_init(void)
        ret = (cpu->init)();
        if (ret != 0)
                return ret;
+#if IS_ENABLED(CONFIG_SAMSUNG_ATAGS)
        ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts);
+#endif
        return ret;
 }
diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c
index c2ff92c30bdf..a8de3cfe2ee1 100644
--- a/arch/arm/plat-samsung/pm-gpio.c
+++ b/arch/arm/plat-samsung/pm-gpio.c
@@ -192,7 +192,8 @@ struct samsung_gpio_pm samsung_gpio_pm_2bit = {
        .resume = samsung_gpio_pm_2bit_resume,
 };
-#if defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_PLAT_S5P)
+#if defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_PLAT_S5P) \
+        || defined(CONFIG_ARCH_EXYNOS)
 static void samsung_gpio_pm_4bit_save(struct samsung_gpio_chip *chip)
 {
        chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON);
@@ -302,7 +303,7 @@ struct samsung_gpio_pm samsung_gpio_pm_4bit = {
        .save   = samsung_gpio_pm_4bit_save,
        .resume = samsung_gpio_pm_4bit_resume,
 };
-#endif /* CONFIG_ARCH_S3C64XX || CONFIG_PLAT_S5P */
+#endif /* CONFIG_ARCH_S3C64XX || CONFIG_PLAT_S5P || CONFIG_ARCH_EXYNOS */
 /**
 * samsung_pm_save_gpio() - save gpio chip data for suspend
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
index bd7124c87fea..d0c23010b693 100644
--- a/arch/arm/plat-samsung/pm.c
+++ b/arch/arm/plat-samsung/pm.c
@@ -22,13 +22,17 @@
 #include <asm/cacheflush.h>
 #include <asm/suspend.h>
-#include <mach/hardware.h>
-#include <mach/map.h>
 #include <plat/regs-serial.h>
+#ifdef CONFIG_SAMSUNG_ATAGS
+#include <mach/hardware.h>
+#include <mach/map.h>
 #include <mach/regs-clock.h>
 #include <mach/regs-irq.h>
 #include <mach/irqs.h>
+#endif
 #include <asm/irq.h>
 #include <plat/pm.h>
@@ -76,7 +80,7 @@ unsigned char pm_uart_udivslot;
 #ifdef CONFIG_SAMSUNG_PM_DEBUG
-static struct pm_uart_save uart_save[CONFIG_SERIAL_SAMSUNG_UARTS];
+static struct pm_uart_save uart_save;
 static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save)
 {
@@ -97,11 +101,7 @@ static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save)
 static void s3c_pm_save_uarts(void)
 {
-        struct pm_uart_save *save = uart_save;
+        s3c_pm_save_uart(CONFIG_DEBUG_S3C_UART, &uart_save);
-        unsigned int uart;
-        for (uart = 0; uart < CONFIG_SERIAL_SAMSUNG_UARTS; uart++, save++)
-                s3c_pm_save_uart(uart, save);
 }
 static void s3c_pm_restore_uart(unsigned int uart, struct pm_uart_save *save)
@@ -122,11 +122,7 @@ static void s3c_pm_restore_uart(unsigned int uart, struct pm_uart_save *save)
 static void s3c_pm_restore_uarts(void)
 {
-        struct pm_uart_save *save = uart_save;
+        s3c_pm_restore_uart(CONFIG_DEBUG_S3C_UART, &uart_save);
-        unsigned int uart;
-        for (uart = 0; uart < CONFIG_SERIAL_SAMSUNG_UARTS; uart++, save++)
-                s3c_pm_restore_uart(uart, save);
 }
 #else
 static void s3c_pm_save_uarts(void) { }
diff --git a/arch/arm/plat-samsung/s5p-dev-mfc.c b/arch/arm/plat-samsung/s5p-dev-mfc.c
index a93fb6fb6606..ad51f85fbd01 100644
--- a/arch/arm/plat-samsung/s5p-dev-mfc.c
+++ b/arch/arm/plat-samsung/s5p-dev-mfc.c
@@ -17,10 +17,12 @@
 #include <linux/of_fdt.h>
 #include <linux/of.h>
+#include <plat/mfc.h>
+#ifdef CONFIG_SAMSUNG_ATAGS
 #include <mach/map.h>
 #include <mach/irqs.h>
 #include <plat/devs.h>
-#include <plat/mfc.h>
 static struct resource s5p_mfc_resource[] = {
        [0] = DEFINE_RES_MEM(S5P_PA_MFC, SZ_64K),
@@ -61,6 +63,10 @@ struct platform_device s5p_device_mfc_r = {
                .coherent_dma_mask      = DMA_BIT_MASK(32),
        },
 };
+#else
+static struct platform_device s5p_device_mfc_l;
+static struct platform_device s5p_device_mfc_r;
+#endif
 struct s5p_mfc_reserved_mem {
        phys_addr_t     base;
@@ -70,6 +76,7 @@ struct s5p_mfc_reserved_mem {
 static struct s5p_mfc_reserved_mem s5p_mfc_mem[2] __initdata;
 void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
                                phys_addr_t lbase, unsigned int lsize)
 {
@@ -93,6 +100,7 @@ void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
        }
 }
+#ifdef CONFIG_SAMSUNG_ATAGS
 static int __init s5p_mfc_memory_init(void)
 {
        int i;
@@ -111,6 +119,7 @@ static int __init s5p_mfc_memory_init(void)
        return 0;
 }
 device_initcall(s5p_mfc_memory_init);
+#endif
 #ifdef CONFIG_OF
 int __init s5p_fdt_find_mfc_mem(unsigned long node, const char *uname,
diff --git a/arch/arm/plat-samsung/samsung-time.c b/arch/arm/plat-samsung/samsung-time.c
index f899cbc9b288..2957075ca836 100644
--- a/arch/arm/plat-samsung/samsung-time.c
+++ b/arch/arm/plat-samsung/samsung-time.c
@@ -15,12 +15,12 @@
 #include <linux/clk.h>
 #include <linux/clockchips.h>
 #include <linux/platform_device.h>
+#include <linux/sched_clock.h>
 #include <asm/smp_twd.h>
 #include <asm/mach/time.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <asm/sched_clock.h>
 #include <mach/map.h>
 #include <plat/devs.h>
diff --git a/arch/arm/plat-samsung/watchdog-reset.c b/arch/arm/plat-samsung/watchdog-reset.c
new file mode 100644
index 000000000000..2ecb50bea044
--- /dev/null
+++ b/arch/arm/plat-samsung/watchdog-reset.c
@@ -0,0 +1,97 @@
+/* arch/arm/plat-samsung/watchdog-reset.c
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * Coyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
+ *
+ * Watchdog reset support for Samsung SoCs.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#define S3C2410_WTCON                   0x00
+#define S3C2410_WTDAT                   0x04
+#define S3C2410_WTCNT                   0x08
+#define S3C2410_WTCON_ENABLE            (1 << 5)
+#define S3C2410_WTCON_DIV16             (0 << 3)
+#define S3C2410_WTCON_RSTEN             (1 << 0)
+#define S3C2410_WTCON_PRESCALE(x)       ((x) << 8)
+static void __iomem *wdt_base;
+static struct clk *wdt_clock;
+void samsung_wdt_reset(void)
+{
+        if (!wdt_base) {
+                pr_err("%s: wdt reset not initialized\n", __func__);
+                /* delay to allow the serial port to show the message */
+                mdelay(50);
+                return;
+        }
+        if (!IS_ERR(wdt_clock))
+                clk_prepare_enable(wdt_clock);
+        /* disable watchdog, to be safe  */
+        __raw_writel(0, wdt_base + S3C2410_WTCON);
+        /* put initial values into count and data */
+        __raw_writel(0x80, wdt_base + S3C2410_WTCNT);
+        __raw_writel(0x80, wdt_base + S3C2410_WTDAT);
+        /* set the watchdog to go and reset... */
+        __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV16 |
+                        S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x20),
+                        wdt_base + S3C2410_WTCON);
+        /* wait for reset to assert... */
+        mdelay(500);
+        pr_err("Watchdog reset failed to assert reset\n");
+        /* delay to allow the serial port to show the message */
+        mdelay(50);
+}
+#ifdef CONFIG_OF
+static const struct of_device_id s3c2410_wdt_match[] = {
+        { .compatible = "samsung,s3c2410-wdt" },
+        {},
+};
+void __init samsung_wdt_reset_of_init(void)
+{
+        struct device_node *np;
+        np = of_find_matching_node(NULL, s3c2410_wdt_match);
+        if (!np) {
+                pr_err("%s: failed to find watchdog node\n", __func__);
+                return;
+        }
+        wdt_base = of_iomap(np, 0);
+        if (!wdt_base) {
+                pr_err("%s: failed to map watchdog registers\n", __func__);
+                return;
+        }
+        wdt_clock = of_clk_get(np, 0);
+}
+#endif
+void __init samsung_wdt_reset_init(void __iomem *base)
+{
+        wdt_base = base;
+        wdt_clock = clk_get(NULL, "watchdog");
+}
diff --git a/arch/arm/plat-versatile/headsmp.S b/arch/arm/plat-versatile/headsmp.S
index b178d44e9eaa..2677bc3762d7 100644
--- a/arch/arm/plat-versatile/headsmp.S
+++ b/arch/arm/plat-versatile/headsmp.S
@@ -11,8 +11,6 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
-        __INIT
 /*
 * Realview/Versatile Express specific entry point for secondary CPUs.
 * This provides a "holding pen" into which all secondary cores are held
diff --git a/arch/arm/plat-versatile/platsmp.c b/arch/arm/plat-versatile/platsmp.c
index 1e1b2d769748..39895d892c3b 100644
--- a/arch/arm/plat-versatile/platsmp.c
+++ b/arch/arm/plat-versatile/platsmp.c
@@ -23,7 +23,7 @@
 * observers, irrespective of whether they're taking part in coherency
 * or not.  This is necessary for the hotplug code to work reliably.
 */
-static void __cpuinit write_pen_release(int val)
+static void write_pen_release(int val)
 {
        pen_release = val;
        smp_wmb();
@@ -33,7 +33,7 @@ static void __cpuinit write_pen_release(int val)
 static DEFINE_SPINLOCK(boot_lock);
-void __cpuinit versatile_secondary_init(unsigned int cpu)
+void versatile_secondary_init(unsigned int cpu)
 {
        /*
         * let the primary processor know we're out of the
@@ -48,7 +48,7 @@ void __cpuinit versatile_secondary_init(unsigned int cpu)
        spin_unlock(&boot_lock);
 }
-int __cpuinit versatile_boot_secondary(unsigned int cpu, struct task_struct *idle)
+int versatile_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
        unsigned long timeout;
diff --git a/arch/arm/plat-versatile/sched-clock.c b/arch/arm/plat-versatile/sched-clock.c
index b33b74c87232..51b109e3b6c3 100644
--- a/arch/arm/plat-versatile/sched-clock.c
+++ b/arch/arm/plat-versatile/sched-clock.c
@@ -20,8 +20,8 @@
 */
 #include <linux/kernel.h>
 #include <linux/io.h>
+#include <linux/sched_clock.h>
-#include <asm/sched_clock.h>
 #include <plat/sched_clock.h>
 static void __iomem *ctr;
diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
index 13609e01f4b7..c9770ba5c7df 100644
--- a/arch/arm/xen/enlighten.c
+++ b/arch/arm/xen/enlighten.c
@@ -172,7 +172,7 @@ static void __init xen_percpu_init(void *unused)
        enable_percpu_irq(xen_events_irq, 0);
 }
-static void xen_restart(char str, const char *cmd)
+static void xen_restart(enum reboot_mode reboot_mode, const char *cmd)
 {
        struct sched_shutdown r = { .reason = SHUTDOWN_reboot };
        int rc;
@@ -314,4 +314,5 @@ EXPORT_SYMBOL_GPL(HYPERVISOR_hvm_op);
 EXPORT_SYMBOL_GPL(HYPERVISOR_memory_op);
 EXPORT_SYMBOL_GPL(HYPERVISOR_physdev_op);
 EXPORT_SYMBOL_GPL(HYPERVISOR_vcpu_op);
+EXPORT_SYMBOL_GPL(HYPERVISOR_tmem_op);
 EXPORT_SYMBOL_GPL(privcmd_call);
diff --git a/arch/arm/xen/hypercall.S b/arch/arm/xen/hypercall.S
index 199cb2da7663..d1cf7b7c2200 100644
--- a/arch/arm/xen/hypercall.S
+++ b/arch/arm/xen/hypercall.S
@@ -88,6 +88,7 @@ HYPERCALL2(hvm_op);
 HYPERCALL2(memory_op);
 HYPERCALL2(physdev_op);
 HYPERCALL3(vcpu_op);
+HYPERCALL1(tmem_op);
 ENTRY(privcmd_call)
        stmdb sp!, {r4}
author	Sage Weil <sage@inktank.com>	2013-08-15 14:11:45 -0400
committer	Sage Weil <sage@inktank.com>	2013-08-15 14:11:45 -0400
commit	ee3e542fec6e69bc9fb668698889a37d93950ddf (patch)
tree	e74ee766a4764769ef1d3d45d266b4dea64101d3 /arch/arm
parent	fe2a801b50c0bb8039d627e5ae1fec249d10ff39 (diff)
parent	f1d6e17f540af37bb1891480143669ba7636c4cf (diff)