diff options
author | Paul Walmsley <paul@pwsan.com> | 2009-12-08 18:18:47 -0500 |
---|---|---|
committer | paul <paul@twilight.(none)> | 2009-12-11 18:12:11 -0500 |
commit | 55d8a65308a5099155683c5a9bba3b8577988111 (patch) | |
tree | d1bb1d93c4bafa2275b91b2b7379075ba72f1120 /arch/arm/mach-omap2 | |
parent | 06b16939a3d58aa128fee22b9aaf7dbc9a5b7c1c (diff) |
OMAP2/3: move SDRC macros to mach-omap2/sdrc.h
clock34xx.c contains some macros which probably belong in mach-omap2/sdrc.h.
Move those macros to mach-omap2/sdrc.h.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r-- | arch/arm/mach-omap2/clock34xx.c | 14 | ||||
-rw-r--r-- | arch/arm/mach-omap2/sdrc.h | 16 |
2 files changed, 16 insertions, 14 deletions
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index 523978a58d4e..3344809e5fe5 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c | |||
@@ -322,22 +322,8 @@ static struct omap_clk omap34xx_clks[] = { | |||
322 | 322 | ||
323 | #define MAX_DPLL_WAIT_TRIES 1000000 | 323 | #define MAX_DPLL_WAIT_TRIES 1000000 |
324 | 324 | ||
325 | #define MIN_SDRC_DLL_LOCK_FREQ 83000000 | ||
326 | |||
327 | #define CYCLES_PER_MHZ 1000000 | 325 | #define CYCLES_PER_MHZ 1000000 |
328 | 326 | ||
329 | /* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */ | ||
330 | #define SDRC_MPURATE_SCALE 8 | ||
331 | |||
332 | /* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */ | ||
333 | #define SDRC_MPURATE_BASE_SHIFT 9 | ||
334 | |||
335 | /* | ||
336 | * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at | ||
337 | * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize | ||
338 | */ | ||
339 | #define SDRC_MPURATE_LOOPS 96 | ||
340 | |||
341 | /* | 327 | /* |
342 | * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks | 328 | * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks |
343 | * that are sourced by DPLL5, and both of these require this clock | 329 | * that are sourced by DPLL5, and both of these require this clock |
diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h index 48207b018989..12fc7dafec2b 100644 --- a/arch/arm/mach-omap2/sdrc.h +++ b/arch/arm/mach-omap2/sdrc.h | |||
@@ -56,4 +56,20 @@ static inline u32 sms_read_reg(u16 reg) | |||
56 | OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg)) | 56 | OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg)) |
57 | #endif /* __ASSEMBLER__ */ | 57 | #endif /* __ASSEMBLER__ */ |
58 | 58 | ||
59 | /* Minimum frequency that the SDRC DLL can lock at */ | ||
60 | #define MIN_SDRC_DLL_LOCK_FREQ 83000000 | ||
61 | |||
62 | /* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */ | ||
63 | #define SDRC_MPURATE_SCALE 8 | ||
64 | |||
65 | /* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */ | ||
66 | #define SDRC_MPURATE_BASE_SHIFT 9 | ||
67 | |||
68 | /* | ||
69 | * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at | ||
70 | * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize | ||
71 | */ | ||
72 | #define SDRC_MPURATE_LOOPS 96 | ||
73 | |||
74 | |||
59 | #endif | 75 | #endif |