aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-omap2/prcm.c
diff options
context:
space:
mode:
authorPaul Walmsley <paul@pwsan.com>2010-12-21 23:05:14 -0500
committerPaul Walmsley <paul@pwsan.com>2010-12-21 23:05:14 -0500
commitdac9a77120e2724e22696f06f3ecb4838da1e3e4 (patch)
tree7f7d91166a35efcdd4daf3e161e6532892250ef1 /arch/arm/mach-omap2/prcm.c
parent2ace831ffc8feaffb8bc03da89ff43d948efdc97 (diff)
OMAP4: PRCM: move global reset function for OMAP4 to an OMAP4-specific file
Move the OMAP4 global software reset function to the OMAP4-specific prm44xx.c file, where it belongs. Part of the long-term process of moving all of the direct PRCM register writes into lower-layer code. Also add OCP barriers on OMAP2/3/4 to reduce the chance that the MPU will continue executing while the system is supposed to be resetting itself. Signed-off-by: Paul Walmsley <paul@pwsan.com> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Rajendra Nayak <rnayak@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/prcm.c')
-rw-r--r--arch/arm/mach-omap2/prcm.c17
1 files changed, 8 insertions, 9 deletions
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index fe0865bd64cf..68c541f98ad2 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -68,17 +68,16 @@ void omap_prcm_arch_reset(char mode, const char *cmd)
68 } else if (cpu_is_omap34xx()) { 68 } else if (cpu_is_omap34xx()) {
69 prcm_offs = OMAP3430_GR_MOD; 69 prcm_offs = OMAP3430_GR_MOD;
70 omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0)); 70 omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
71 } else if (cpu_is_omap44xx()) 71 } else if (cpu_is_omap44xx()) {
72 prcm_offs = OMAP4430_PRM_DEVICE_INST; 72 omap4_prm_global_warm_sw_reset(); /* never returns */
73 else 73 } else {
74 WARN_ON(1); 74 WARN_ON(1);
75 }
75 76
76 if (cpu_is_omap24xx() || cpu_is_omap34xx()) 77 /* XXX should be moved to some OMAP2/3 specific code */
77 prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs, 78 prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
78 OMAP2_RM_RSTCTRL); 79 OMAP2_RM_RSTCTRL);
79 if (cpu_is_omap44xx()) 80 prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */
80 prm_set_mod_reg_bits(OMAP4430_RST_GLOBAL_WARM_SW_MASK,
81 prcm_offs, OMAP4_RM_RSTCTRL);
82} 81}
83 82
84/** 83/**