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authorPaul Walmsley <paul@pwsan.com>2010-12-21 23:05:14 -0500
committerPaul Walmsley <paul@pwsan.com>2010-12-21 23:05:14 -0500
commit2ace831ffc8feaffb8bc03da89ff43d948efdc97 (patch)
tree4a75814c417ffe94dd2505585305378b7f04b40e /arch/arm/mach-omap2/prcm.c
parentf0611a5c220e50dec65041b10bd2fe9484f061a6 (diff)
OMAP4: PRCM: add OMAP4-specific accessor/mutator functions
In some ways, the OMAP4 PRCM register layout is quite different than the OMAP2/3 PRCM register layout. For example, on OMAP2/3, from a register layout point of view, all CM instances were located in the CM subsystem, and all PRM instances were located in the PRM subsystem. OMAP4 changes this. Now, for example, some CM instances, such as WKUP_CM and EMU_CM, are located in the system PRM subsystem. And a "local PRCM" exists for the MPU - this PRCM combines registers that would normally appear in both CM and PRM instances, but uses its own register layout which matches neither the OMAP2/3 PRCM layout nor the OMAP4 PRCM layout. To try to deal with this, introduce some new functions, omap4_cminst* and omap4_prminst*. The former is to be used when writing to a CM instance register (no matter what subsystem or hardware module it exists in), and the latter, similarly, with PRM instance registers. To determine which "PRCM partition" to write to, the functions take a PRCM instance ID argument. Subsequent patches add these partition IDs to the OMAP4 powerdomain and clockdomain definitions. As far as I can see, there's really no good way to handle these types of register access inconsistencies. This patch seemed like the least bad approach. Moving forward, the long-term goal is to remove all direct PRCM register access from the PM code. PRCM register access should go through layers such as the powerdomain and clockdomain code that can hide the details of how to interact with the specific hardware variant. While here, rename cm4xxx.c to cm44xx.c to match the naming convention of the other OMAP4 PRCM files. Thanks to Santosh Shilimkar <santosh.shilimkar@ti.com>, Rajendra Nayak <rnayak@ti.com>, and Benoît Cousson <b-cousson@ti.com> for some comments. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoît Cousson <b-cousson@ti.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/prcm.c')
-rw-r--r--arch/arm/mach-omap2/prcm.c26
1 files changed, 1 insertions, 25 deletions
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index dd95cbbdecc7..fe0865bd64cf 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -33,6 +33,7 @@
33#include "cm44xx.h" 33#include "cm44xx.h"
34#include "prm2xxx_3xxx.h" 34#include "prm2xxx_3xxx.h"
35#include "prm44xx.h" 35#include "prm44xx.h"
36#include "prcm44xx.h"
36#include "prm-regbits-24xx.h" 37#include "prm-regbits-24xx.h"
37#include "prm-regbits-44xx.h" 38#include "prm-regbits-44xx.h"
38#include "control.h" 39#include "control.h"
@@ -80,31 +81,6 @@ void omap_prcm_arch_reset(char mode, const char *cmd)
80 prcm_offs, OMAP4_RM_RSTCTRL); 81 prcm_offs, OMAP4_RM_RSTCTRL);
81} 82}
82 83
83/* Read a PRM register, AND it, and shift the result down to bit 0 */
84u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask)
85{
86 u32 v;
87
88 v = __raw_readl(reg);
89 v &= mask;
90 v >>= __ffs(mask);
91
92 return v;
93}
94
95/* Read-modify-write a register in a PRM module. Caller must lock */
96u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg)
97{
98 u32 v;
99
100 v = __raw_readl(reg);
101 v &= ~mask;
102 v |= bits;
103 __raw_writel(v, reg);
104
105 return v;
106}
107
108/** 84/**
109 * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness 85 * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
110 * @reg: physical address of module IDLEST register 86 * @reg: physical address of module IDLEST register