diff options
author | sricharan <r.sricharan@ti.com> | 2011-08-24 10:37:45 -0400 |
---|---|---|
committer | Santosh Shilimkar <santosh.shilimkar@ti.com> | 2011-09-24 03:58:57 -0400 |
commit | ed0e352073ff86c876ff7820ad0b6bac123082b5 (patch) | |
tree | b2a77f867ecdb97cc9ffbd8c956edd4090c048b9 /arch/arm/mach-omap2/omap_l3_noc.h | |
parent | c1df2dcc90dc6f5110726e9bdcd2353db989c29d (diff) |
OMAP: Fix indentation issues in l3 error handler.
The indentation problems in the l3 noc and smx
error handler files are fixed.
Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reported-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/omap_l3_noc.h')
-rw-r--r-- | arch/arm/mach-omap2/omap_l3_noc.h | 106 |
1 files changed, 53 insertions, 53 deletions
diff --git a/arch/arm/mach-omap2/omap_l3_noc.h b/arch/arm/mach-omap2/omap_l3_noc.h index 22c0d57ee3d9..9120e70aa08a 100644 --- a/arch/arm/mach-omap2/omap_l3_noc.h +++ b/arch/arm/mach-omap2/omap_l3_noc.h | |||
@@ -1,25 +1,25 @@ | |||
1 | /* | 1 | /* |
2 | * OMAP4XXX L3 Interconnect error handling driver header | 2 | * OMAP4XXX L3 Interconnect error handling driver header |
3 | * | 3 | * |
4 | * Copyright (C) 2011 Texas Corporation | 4 | * Copyright (C) 2011 Texas Corporation |
5 | * Santosh Shilimkar <santosh.shilimkar@ti.com> | 5 | * Santosh Shilimkar <santosh.shilimkar@ti.com> |
6 | * sricharan <r.sricharan@ti.com> | 6 | * sricharan <r.sricharan@ti.com> |
7 | * | 7 | * |
8 | * This program is free software; you can redistribute it and/or modify | 8 | * This program is free software; you can redistribute it and/or modify |
9 | * it under the terms of the GNU General Public License as published by | 9 | * it under the terms of the GNU General Public License as published by |
10 | * the Free Software Foundation; either version 2 of the License, or | 10 | * the Free Software Foundation; either version 2 of the License, or |
11 | * (at your option) any later version. | 11 | * (at your option) any later version. |
12 | * | 12 | * |
13 | * This program is distributed in the hope that it will be useful, | 13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
16 | * GNU General Public License for more details. | 16 | * GNU General Public License for more details. |
17 | * | 17 | * |
18 | * You should have received a copy of the GNU General Public License | 18 | * You should have received a copy of the GNU General Public License |
19 | * along with this program; if not, write to the Free Software | 19 | * along with this program; if not, write to the Free Software |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 | 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 |
21 | * USA | 21 | * USA |
22 | */ | 22 | */ |
23 | #ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H | 23 | #ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H |
24 | #define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H | 24 | #define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H |
25 | 25 | ||
@@ -32,9 +32,9 @@ | |||
32 | #define L3_DEBUG_ERROR 0x1 | 32 | #define L3_DEBUG_ERROR 0x1 |
33 | 33 | ||
34 | /* L3 TARG register offsets */ | 34 | /* L3 TARG register offsets */ |
35 | #define L3_TARG_STDERRLOG_MAIN 0x48 | 35 | #define L3_TARG_STDERRLOG_MAIN 0x48 |
36 | #define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c | 36 | #define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c |
37 | #define L3_FLAGMUX_REGERR0 0xc | 37 | #define L3_FLAGMUX_REGERR0 0xc |
38 | 38 | ||
39 | u32 l3_flagmux[L3_MODULES] = { | 39 | u32 l3_flagmux[L3_MODULES] = { |
40 | 0x500, | 40 | 0x500, |
@@ -78,34 +78,34 @@ u32 l3_targ_inst_clk3[] = { | |||
78 | 78 | ||
79 | char *l3_targ_inst_name[L3_MODULES][18] = { | 79 | char *l3_targ_inst_name[L3_MODULES][18] = { |
80 | { | 80 | { |
81 | "DMM1", | 81 | "DMM1", |
82 | "DMM2", | 82 | "DMM2", |
83 | "ABE", | 83 | "ABE", |
84 | "L4CFG", | 84 | "L4CFG", |
85 | "CLK2 PWR DISC", | 85 | "CLK2 PWR DISC", |
86 | }, | 86 | }, |
87 | { | 87 | { |
88 | "CORTEX M3" , | 88 | "CORTEX M3" , |
89 | "DSS ", | 89 | "DSS ", |
90 | "GPMC ", | 90 | "GPMC ", |
91 | "ISS ", | 91 | "ISS ", |
92 | "IVAHD ", | 92 | "IVAHD ", |
93 | "AES1", | 93 | "AES1", |
94 | "L4 PER0", | 94 | "L4 PER0", |
95 | "OCMRAM ", | 95 | "OCMRAM ", |
96 | "GPMC sERROR", | 96 | "GPMC sERROR", |
97 | "SGX ", | 97 | "SGX ", |
98 | "SL2 ", | 98 | "SL2 ", |
99 | "C2C ", | 99 | "C2C ", |
100 | "PWR DISC CLK1", | 100 | "PWR DISC CLK1", |
101 | "SHA1", | 101 | "SHA1", |
102 | "AES2", | 102 | "AES2", |
103 | "L4 PER3", | 103 | "L4 PER3", |
104 | "L4 PER1", | 104 | "L4 PER1", |
105 | "L4 PER2", | 105 | "L4 PER2", |
106 | }, | 106 | }, |
107 | { | 107 | { |
108 | "EMUSS", | 108 | "EMUSS", |
109 | }, | 109 | }, |
110 | }; | 110 | }; |
111 | 111 | ||
@@ -116,13 +116,13 @@ u32 *l3_targ[L3_MODULES] = { | |||
116 | }; | 116 | }; |
117 | 117 | ||
118 | struct omap4_l3 { | 118 | struct omap4_l3 { |
119 | struct device *dev; | 119 | struct device *dev; |
120 | struct clk *ick; | 120 | struct clk *ick; |
121 | 121 | ||
122 | /* memory base */ | 122 | /* memory base */ |
123 | void __iomem *l3_base[L3_MODULES]; | 123 | void __iomem *l3_base[L3_MODULES]; |
124 | 124 | ||
125 | int debug_irq; | 125 | int debug_irq; |
126 | int app_irq; | 126 | int app_irq; |
127 | }; | 127 | }; |
128 | #endif | 128 | #endif |