diff options
author | Jon Hunter <jon-hunter@ti.com> | 2012-07-11 14:00:13 -0400 |
---|---|---|
committer | Jon Hunter <jon-hunter@ti.com> | 2012-11-12 17:23:52 -0500 |
commit | 10759e823c83e6c88b58264daa791bb82c7ebad9 (patch) | |
tree | 4fd01b0d9871c5fdae96cff2efbd07b3b274ad75 /arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | |
parent | f3a13e7246f92e0cf4e9e3baee3145693ba41a8d (diff) |
ARM: OMAP2+: Don't use __omap_dm_timer_reset()
Currently OMAP2+ devices are using the function __omap_dm_timer_reset() to
configure the clock-activity, idle, wakeup-enable and auto-idle fields in the
timer OCP_CFG register. The name of the function is mis-leading because this
function does not actually perform a reset of the timer.
For OMAP2+ devices, HWMOD is responsible for reseting and configuring the
timer OCP_CFG register. Therefore, do not use __omap_dm_timer_reset() for
OMAP2+ devices and rely on HWMOD. Furthermore, some timer instances do not
have the fields clock-activity, wakeup-enable and auto-idle and so this
function could configure the OCP_CFG register incorrectly.
Currently HWMOD is not configuring the clock-activity field in the OCP_CFG
register for timers that have this field. Commit 0f0d080 (ARM: OMAP: DMTimer:
Use posted mode) configures the clock-activity field to keep the f-clk enabled
so that the wake-up capability is enabled. Therefore, add the appropriate flags
to the timer HWMOD structures to configure this field in the same way.
For OMAP2/3 devices all dmtimers have the clock-activity field, where as for
OMAP4 devices, only dmtimer 1, 2 and 10 have the clock-activity field.
Verified on OMAP2420 H4, OMAP3430 Beagle and OMAP4430 Panda that HWMOD is
configuring the dmtimer OCP_CFG register as expected for clock-events timer.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/omap_hwmod_3xxx_data.c')
-rw-r--r-- | arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index fcce693a1edc..addc1c24ca2e 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | |||
@@ -162,6 +162,7 @@ static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { | |||
162 | SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE | | 162 | SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE | |
163 | SYSS_HAS_RESET_STATUS), | 163 | SYSS_HAS_RESET_STATUS), |
164 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | 164 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
165 | .clockact = CLOCKACT_TEST_ICLK, | ||
165 | .sysc_fields = &omap_hwmod_sysc_type1, | 166 | .sysc_fields = &omap_hwmod_sysc_type1, |
166 | }; | 167 | }; |
167 | 168 | ||
@@ -211,6 +212,7 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = { | |||
211 | }, | 212 | }, |
212 | .dev_attr = &capability_alwon_dev_attr, | 213 | .dev_attr = &capability_alwon_dev_attr, |
213 | .class = &omap3xxx_timer_hwmod_class, | 214 | .class = &omap3xxx_timer_hwmod_class, |
215 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | ||
214 | }; | 216 | }; |
215 | 217 | ||
216 | /* timer2 */ | 218 | /* timer2 */ |
@@ -228,6 +230,7 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = { | |||
228 | }, | 230 | }, |
229 | }, | 231 | }, |
230 | .class = &omap3xxx_timer_hwmod_class, | 232 | .class = &omap3xxx_timer_hwmod_class, |
233 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | ||
231 | }; | 234 | }; |
232 | 235 | ||
233 | /* timer3 */ | 236 | /* timer3 */ |
@@ -245,6 +248,7 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = { | |||
245 | }, | 248 | }, |
246 | }, | 249 | }, |
247 | .class = &omap3xxx_timer_hwmod_class, | 250 | .class = &omap3xxx_timer_hwmod_class, |
251 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | ||
248 | }; | 252 | }; |
249 | 253 | ||
250 | /* timer4 */ | 254 | /* timer4 */ |
@@ -262,6 +266,7 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = { | |||
262 | }, | 266 | }, |
263 | }, | 267 | }, |
264 | .class = &omap3xxx_timer_hwmod_class, | 268 | .class = &omap3xxx_timer_hwmod_class, |
269 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | ||
265 | }; | 270 | }; |
266 | 271 | ||
267 | /* timer5 */ | 272 | /* timer5 */ |
@@ -280,6 +285,7 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = { | |||
280 | }, | 285 | }, |
281 | .dev_attr = &capability_dsp_dev_attr, | 286 | .dev_attr = &capability_dsp_dev_attr, |
282 | .class = &omap3xxx_timer_hwmod_class, | 287 | .class = &omap3xxx_timer_hwmod_class, |
288 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | ||
283 | }; | 289 | }; |
284 | 290 | ||
285 | /* timer6 */ | 291 | /* timer6 */ |
@@ -298,6 +304,7 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = { | |||
298 | }, | 304 | }, |
299 | .dev_attr = &capability_dsp_dev_attr, | 305 | .dev_attr = &capability_dsp_dev_attr, |
300 | .class = &omap3xxx_timer_hwmod_class, | 306 | .class = &omap3xxx_timer_hwmod_class, |
307 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | ||
301 | }; | 308 | }; |
302 | 309 | ||
303 | /* timer7 */ | 310 | /* timer7 */ |
@@ -316,6 +323,7 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = { | |||
316 | }, | 323 | }, |
317 | .dev_attr = &capability_dsp_dev_attr, | 324 | .dev_attr = &capability_dsp_dev_attr, |
318 | .class = &omap3xxx_timer_hwmod_class, | 325 | .class = &omap3xxx_timer_hwmod_class, |
326 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | ||
319 | }; | 327 | }; |
320 | 328 | ||
321 | /* timer8 */ | 329 | /* timer8 */ |
@@ -334,6 +342,7 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = { | |||
334 | }, | 342 | }, |
335 | .dev_attr = &capability_dsp_pwm_dev_attr, | 343 | .dev_attr = &capability_dsp_pwm_dev_attr, |
336 | .class = &omap3xxx_timer_hwmod_class, | 344 | .class = &omap3xxx_timer_hwmod_class, |
345 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | ||
337 | }; | 346 | }; |
338 | 347 | ||
339 | /* timer9 */ | 348 | /* timer9 */ |
@@ -352,6 +361,7 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = { | |||
352 | }, | 361 | }, |
353 | .dev_attr = &capability_pwm_dev_attr, | 362 | .dev_attr = &capability_pwm_dev_attr, |
354 | .class = &omap3xxx_timer_hwmod_class, | 363 | .class = &omap3xxx_timer_hwmod_class, |
364 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | ||
355 | }; | 365 | }; |
356 | 366 | ||
357 | /* timer10 */ | 367 | /* timer10 */ |
@@ -370,6 +380,7 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = { | |||
370 | }, | 380 | }, |
371 | .dev_attr = &capability_pwm_dev_attr, | 381 | .dev_attr = &capability_pwm_dev_attr, |
372 | .class = &omap3xxx_timer_hwmod_class, | 382 | .class = &omap3xxx_timer_hwmod_class, |
383 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | ||
373 | }; | 384 | }; |
374 | 385 | ||
375 | /* timer11 */ | 386 | /* timer11 */ |
@@ -388,6 +399,7 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = { | |||
388 | }, | 399 | }, |
389 | .dev_attr = &capability_pwm_dev_attr, | 400 | .dev_attr = &capability_pwm_dev_attr, |
390 | .class = &omap3xxx_timer_hwmod_class, | 401 | .class = &omap3xxx_timer_hwmod_class, |
402 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | ||
391 | }; | 403 | }; |
392 | 404 | ||
393 | /* timer12 */ | 405 | /* timer12 */ |
@@ -411,6 +423,7 @@ static struct omap_hwmod omap3xxx_timer12_hwmod = { | |||
411 | }, | 423 | }, |
412 | .dev_attr = &capability_secure_dev_attr, | 424 | .dev_attr = &capability_secure_dev_attr, |
413 | .class = &omap3xxx_timer_hwmod_class, | 425 | .class = &omap3xxx_timer_hwmod_class, |
426 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | ||
414 | }; | 427 | }; |
415 | 428 | ||
416 | /* | 429 | /* |