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authorJon Hunter <jon-hunter@ti.com>2012-07-11 14:00:13 -0400
committerJon Hunter <jon-hunter@ti.com>2012-11-12 17:23:52 -0500
commit10759e823c83e6c88b58264daa791bb82c7ebad9 (patch)
tree4fd01b0d9871c5fdae96cff2efbd07b3b274ad75
parentf3a13e7246f92e0cf4e9e3baee3145693ba41a8d (diff)
ARM: OMAP2+: Don't use __omap_dm_timer_reset()
Currently OMAP2+ devices are using the function __omap_dm_timer_reset() to configure the clock-activity, idle, wakeup-enable and auto-idle fields in the timer OCP_CFG register. The name of the function is mis-leading because this function does not actually perform a reset of the timer. For OMAP2+ devices, HWMOD is responsible for reseting and configuring the timer OCP_CFG register. Therefore, do not use __omap_dm_timer_reset() for OMAP2+ devices and rely on HWMOD. Furthermore, some timer instances do not have the fields clock-activity, wakeup-enable and auto-idle and so this function could configure the OCP_CFG register incorrectly. Currently HWMOD is not configuring the clock-activity field in the OCP_CFG register for timers that have this field. Commit 0f0d080 (ARM: OMAP: DMTimer: Use posted mode) configures the clock-activity field to keep the f-clk enabled so that the wake-up capability is enabled. Therefore, add the appropriate flags to the timer HWMOD structures to configure this field in the same way. For OMAP2/3 devices all dmtimers have the clock-activity field, where as for OMAP4 devices, only dmtimer 1, 2 and 10 have the clock-activity field. Verified on OMAP2420 H4, OMAP3430 Beagle and OMAP4430 Panda that HWMOD is configuring the dmtimer OCP_CFG register as expected for clock-events timer. Signed-off-by: Jon Hunter <jon-hunter@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c13
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c13
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c4
-rw-r--r--arch/arm/mach-omap2/timer.c1
4 files changed, 30 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index 067fd0ae4b07..0db8f450bad9 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -60,6 +60,7 @@ static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
60 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 60 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
61 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 61 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
62 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 62 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
63 .clockact = CLOCKACT_TEST_ICLK,
63 .sysc_fields = &omap_hwmod_sysc_type1, 64 .sysc_fields = &omap_hwmod_sysc_type1,
64}; 65};
65 66
@@ -268,6 +269,7 @@ struct omap_hwmod omap2xxx_timer1_hwmod = {
268 }, 269 },
269 .dev_attr = &capability_alwon_dev_attr, 270 .dev_attr = &capability_alwon_dev_attr,
270 .class = &omap2xxx_timer_hwmod_class, 271 .class = &omap2xxx_timer_hwmod_class,
272 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
271}; 273};
272 274
273/* timer2 */ 275/* timer2 */
@@ -286,6 +288,7 @@ struct omap_hwmod omap2xxx_timer2_hwmod = {
286 }, 288 },
287 }, 289 },
288 .class = &omap2xxx_timer_hwmod_class, 290 .class = &omap2xxx_timer_hwmod_class,
291 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
289}; 292};
290 293
291/* timer3 */ 294/* timer3 */
@@ -304,6 +307,7 @@ struct omap_hwmod omap2xxx_timer3_hwmod = {
304 }, 307 },
305 }, 308 },
306 .class = &omap2xxx_timer_hwmod_class, 309 .class = &omap2xxx_timer_hwmod_class,
310 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
307}; 311};
308 312
309/* timer4 */ 313/* timer4 */
@@ -322,6 +326,7 @@ struct omap_hwmod omap2xxx_timer4_hwmod = {
322 }, 326 },
323 }, 327 },
324 .class = &omap2xxx_timer_hwmod_class, 328 .class = &omap2xxx_timer_hwmod_class,
329 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
325}; 330};
326 331
327/* timer5 */ 332/* timer5 */
@@ -341,6 +346,7 @@ struct omap_hwmod omap2xxx_timer5_hwmod = {
341 }, 346 },
342 .dev_attr = &capability_dsp_dev_attr, 347 .dev_attr = &capability_dsp_dev_attr,
343 .class = &omap2xxx_timer_hwmod_class, 348 .class = &omap2xxx_timer_hwmod_class,
349 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
344}; 350};
345 351
346/* timer6 */ 352/* timer6 */
@@ -360,6 +366,7 @@ struct omap_hwmod omap2xxx_timer6_hwmod = {
360 }, 366 },
361 .dev_attr = &capability_dsp_dev_attr, 367 .dev_attr = &capability_dsp_dev_attr,
362 .class = &omap2xxx_timer_hwmod_class, 368 .class = &omap2xxx_timer_hwmod_class,
369 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
363}; 370};
364 371
365/* timer7 */ 372/* timer7 */
@@ -379,6 +386,7 @@ struct omap_hwmod omap2xxx_timer7_hwmod = {
379 }, 386 },
380 .dev_attr = &capability_dsp_dev_attr, 387 .dev_attr = &capability_dsp_dev_attr,
381 .class = &omap2xxx_timer_hwmod_class, 388 .class = &omap2xxx_timer_hwmod_class,
389 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
382}; 390};
383 391
384/* timer8 */ 392/* timer8 */
@@ -398,6 +406,7 @@ struct omap_hwmod omap2xxx_timer8_hwmod = {
398 }, 406 },
399 .dev_attr = &capability_dsp_dev_attr, 407 .dev_attr = &capability_dsp_dev_attr,
400 .class = &omap2xxx_timer_hwmod_class, 408 .class = &omap2xxx_timer_hwmod_class,
409 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
401}; 410};
402 411
403/* timer9 */ 412/* timer9 */
@@ -417,6 +426,7 @@ struct omap_hwmod omap2xxx_timer9_hwmod = {
417 }, 426 },
418 .dev_attr = &capability_pwm_dev_attr, 427 .dev_attr = &capability_pwm_dev_attr,
419 .class = &omap2xxx_timer_hwmod_class, 428 .class = &omap2xxx_timer_hwmod_class,
429 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
420}; 430};
421 431
422/* timer10 */ 432/* timer10 */
@@ -436,6 +446,7 @@ struct omap_hwmod omap2xxx_timer10_hwmod = {
436 }, 446 },
437 .dev_attr = &capability_pwm_dev_attr, 447 .dev_attr = &capability_pwm_dev_attr,
438 .class = &omap2xxx_timer_hwmod_class, 448 .class = &omap2xxx_timer_hwmod_class,
449 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
439}; 450};
440 451
441/* timer11 */ 452/* timer11 */
@@ -455,6 +466,7 @@ struct omap_hwmod omap2xxx_timer11_hwmod = {
455 }, 466 },
456 .dev_attr = &capability_pwm_dev_attr, 467 .dev_attr = &capability_pwm_dev_attr,
457 .class = &omap2xxx_timer_hwmod_class, 468 .class = &omap2xxx_timer_hwmod_class,
469 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
458}; 470};
459 471
460/* timer12 */ 472/* timer12 */
@@ -474,6 +486,7 @@ struct omap_hwmod omap2xxx_timer12_hwmod = {
474 }, 486 },
475 .dev_attr = &capability_pwm_dev_attr, 487 .dev_attr = &capability_pwm_dev_attr,
476 .class = &omap2xxx_timer_hwmod_class, 488 .class = &omap2xxx_timer_hwmod_class,
489 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
477}; 490};
478 491
479/* wd_timer2 */ 492/* wd_timer2 */
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index fcce693a1edc..addc1c24ca2e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -162,6 +162,7 @@ static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
162 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE | 162 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
163 SYSS_HAS_RESET_STATUS), 163 SYSS_HAS_RESET_STATUS),
164 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 164 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
165 .clockact = CLOCKACT_TEST_ICLK,
165 .sysc_fields = &omap_hwmod_sysc_type1, 166 .sysc_fields = &omap_hwmod_sysc_type1,
166}; 167};
167 168
@@ -211,6 +212,7 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = {
211 }, 212 },
212 .dev_attr = &capability_alwon_dev_attr, 213 .dev_attr = &capability_alwon_dev_attr,
213 .class = &omap3xxx_timer_hwmod_class, 214 .class = &omap3xxx_timer_hwmod_class,
215 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
214}; 216};
215 217
216/* timer2 */ 218/* timer2 */
@@ -228,6 +230,7 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = {
228 }, 230 },
229 }, 231 },
230 .class = &omap3xxx_timer_hwmod_class, 232 .class = &omap3xxx_timer_hwmod_class,
233 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
231}; 234};
232 235
233/* timer3 */ 236/* timer3 */
@@ -245,6 +248,7 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = {
245 }, 248 },
246 }, 249 },
247 .class = &omap3xxx_timer_hwmod_class, 250 .class = &omap3xxx_timer_hwmod_class,
251 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
248}; 252};
249 253
250/* timer4 */ 254/* timer4 */
@@ -262,6 +266,7 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = {
262 }, 266 },
263 }, 267 },
264 .class = &omap3xxx_timer_hwmod_class, 268 .class = &omap3xxx_timer_hwmod_class,
269 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
265}; 270};
266 271
267/* timer5 */ 272/* timer5 */
@@ -280,6 +285,7 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
280 }, 285 },
281 .dev_attr = &capability_dsp_dev_attr, 286 .dev_attr = &capability_dsp_dev_attr,
282 .class = &omap3xxx_timer_hwmod_class, 287 .class = &omap3xxx_timer_hwmod_class,
288 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
283}; 289};
284 290
285/* timer6 */ 291/* timer6 */
@@ -298,6 +304,7 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
298 }, 304 },
299 .dev_attr = &capability_dsp_dev_attr, 305 .dev_attr = &capability_dsp_dev_attr,
300 .class = &omap3xxx_timer_hwmod_class, 306 .class = &omap3xxx_timer_hwmod_class,
307 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
301}; 308};
302 309
303/* timer7 */ 310/* timer7 */
@@ -316,6 +323,7 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
316 }, 323 },
317 .dev_attr = &capability_dsp_dev_attr, 324 .dev_attr = &capability_dsp_dev_attr,
318 .class = &omap3xxx_timer_hwmod_class, 325 .class = &omap3xxx_timer_hwmod_class,
326 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
319}; 327};
320 328
321/* timer8 */ 329/* timer8 */
@@ -334,6 +342,7 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
334 }, 342 },
335 .dev_attr = &capability_dsp_pwm_dev_attr, 343 .dev_attr = &capability_dsp_pwm_dev_attr,
336 .class = &omap3xxx_timer_hwmod_class, 344 .class = &omap3xxx_timer_hwmod_class,
345 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
337}; 346};
338 347
339/* timer9 */ 348/* timer9 */
@@ -352,6 +361,7 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = {
352 }, 361 },
353 .dev_attr = &capability_pwm_dev_attr, 362 .dev_attr = &capability_pwm_dev_attr,
354 .class = &omap3xxx_timer_hwmod_class, 363 .class = &omap3xxx_timer_hwmod_class,
364 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
355}; 365};
356 366
357/* timer10 */ 367/* timer10 */
@@ -370,6 +380,7 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = {
370 }, 380 },
371 .dev_attr = &capability_pwm_dev_attr, 381 .dev_attr = &capability_pwm_dev_attr,
372 .class = &omap3xxx_timer_hwmod_class, 382 .class = &omap3xxx_timer_hwmod_class,
383 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
373}; 384};
374 385
375/* timer11 */ 386/* timer11 */
@@ -388,6 +399,7 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = {
388 }, 399 },
389 .dev_attr = &capability_pwm_dev_attr, 400 .dev_attr = &capability_pwm_dev_attr,
390 .class = &omap3xxx_timer_hwmod_class, 401 .class = &omap3xxx_timer_hwmod_class,
402 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
391}; 403};
392 404
393/* timer12 */ 405/* timer12 */
@@ -411,6 +423,7 @@ static struct omap_hwmod omap3xxx_timer12_hwmod = {
411 }, 423 },
412 .dev_attr = &capability_secure_dev_attr, 424 .dev_attr = &capability_secure_dev_attr,
413 .class = &omap3xxx_timer_hwmod_class, 425 .class = &omap3xxx_timer_hwmod_class,
426 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
414}; 427};
415 428
416/* 429/*
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 7a6132848f5d..399f4ce9cab1 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -3067,6 +3067,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
3067 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 3067 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3068 SYSS_HAS_RESET_STATUS), 3068 SYSS_HAS_RESET_STATUS),
3069 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 3069 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3070 .clockact = CLOCKACT_TEST_ICLK,
3070 .sysc_fields = &omap_hwmod_sysc_type1, 3071 .sysc_fields = &omap_hwmod_sysc_type1,
3071}; 3072};
3072 3073
@@ -3120,6 +3121,7 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
3120 .name = "timer1", 3121 .name = "timer1",
3121 .class = &omap44xx_timer_1ms_hwmod_class, 3122 .class = &omap44xx_timer_1ms_hwmod_class,
3122 .clkdm_name = "l4_wkup_clkdm", 3123 .clkdm_name = "l4_wkup_clkdm",
3124 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
3123 .mpu_irqs = omap44xx_timer1_irqs, 3125 .mpu_irqs = omap44xx_timer1_irqs,
3124 .main_clk = "timer1_fck", 3126 .main_clk = "timer1_fck",
3125 .prcm = { 3127 .prcm = {
@@ -3142,6 +3144,7 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
3142 .name = "timer2", 3144 .name = "timer2",
3143 .class = &omap44xx_timer_1ms_hwmod_class, 3145 .class = &omap44xx_timer_1ms_hwmod_class,
3144 .clkdm_name = "l4_per_clkdm", 3146 .clkdm_name = "l4_per_clkdm",
3147 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
3145 .mpu_irqs = omap44xx_timer2_irqs, 3148 .mpu_irqs = omap44xx_timer2_irqs,
3146 .main_clk = "timer2_fck", 3149 .main_clk = "timer2_fck",
3147 .prcm = { 3150 .prcm = {
@@ -3316,6 +3319,7 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
3316 .name = "timer10", 3319 .name = "timer10",
3317 .class = &omap44xx_timer_1ms_hwmod_class, 3320 .class = &omap44xx_timer_1ms_hwmod_class,
3318 .clkdm_name = "l4_per_clkdm", 3321 .clkdm_name = "l4_per_clkdm",
3322 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
3319 .mpu_irqs = omap44xx_timer10_irqs, 3323 .mpu_irqs = omap44xx_timer10_irqs,
3320 .main_clk = "timer10_fck", 3324 .main_clk = "timer10_fck",
3321 .prcm = { 3325 .prcm = {
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 63229c5287e6..19765bd96c8e 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -324,7 +324,6 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
324 } 324 }
325 } 325 }
326 __omap_dm_timer_init_regs(timer); 326 __omap_dm_timer_init_regs(timer);
327 __omap_dm_timer_reset(timer, 1, 1);
328 327
329 if (posted) 328 if (posted)
330 __omap_dm_timer_enable_posted(timer); 329 __omap_dm_timer_enable_posted(timer);