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authorPeter Ujfalusi <peter.ujfalusi@nokia.com>2010-06-03 00:39:33 -0400
committerLiam Girdwood <lrg@slimlogic.co.uk>2010-06-03 11:12:40 -0400
commit451fd82dc148bd5ac9ed5b19b6915a1afe32b9cb (patch)
tree0bd09462f284fbdef0ed98f7d05ed4018302f296 /arch/arm/mach-omap2/mcbsp.c
parent0acce82b3dd792c85079ca1f4f7ffd8c82427e0a (diff)
OMAP3: McBSP: Change the way how the FIFO is handled
Use the actual FIFO size in words as buffer_size on OMAP3. Change the threshold configuration to use 1 based numbering, when specifying the allowed threshold maximum or the McBSP threshold value. Set the default maximum threshold to (buffer_size - 0x10) intialy. >From users of McBSP, now it is expected to use this method. Asking for threshold 1 means that the value written to threshold registers are going to be 0, which means 1 word threshold. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com> Acked-by: Jarkko Nikula <jhnikula@gmail.com> Acked-by: Mark Brown <broonie@opensource.wolsfonmicro.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
Diffstat (limited to 'arch/arm/mach-omap2/mcbsp.c')
-rw-r--r--arch/arm/mach-omap2/mcbsp.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index c29337074ad3..8fb5e5345557 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -133,7 +133,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
133 .rx_irq = INT_24XX_MCBSP1_IRQ_RX, 133 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
134 .tx_irq = INT_24XX_MCBSP1_IRQ_TX, 134 .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
135 .ops = &omap2_mcbsp_ops, 135 .ops = &omap2_mcbsp_ops,
136 .buffer_size = 0x6F, 136 .buffer_size = 0x80, /* The FIFO has 128 locations */
137 }, 137 },
138 { 138 {
139 .phys_base = OMAP34XX_MCBSP2_BASE, 139 .phys_base = OMAP34XX_MCBSP2_BASE,
@@ -143,7 +143,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
143 .rx_irq = INT_24XX_MCBSP2_IRQ_RX, 143 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
144 .tx_irq = INT_24XX_MCBSP2_IRQ_TX, 144 .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
145 .ops = &omap2_mcbsp_ops, 145 .ops = &omap2_mcbsp_ops,
146 .buffer_size = 0x3FF, 146 .buffer_size = 0x500, /* The FIFO has 1024 + 256 locations */
147 }, 147 },
148 { 148 {
149 .phys_base = OMAP34XX_MCBSP3_BASE, 149 .phys_base = OMAP34XX_MCBSP3_BASE,
@@ -153,7 +153,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
153 .rx_irq = INT_24XX_MCBSP3_IRQ_RX, 153 .rx_irq = INT_24XX_MCBSP3_IRQ_RX,
154 .tx_irq = INT_24XX_MCBSP3_IRQ_TX, 154 .tx_irq = INT_24XX_MCBSP3_IRQ_TX,
155 .ops = &omap2_mcbsp_ops, 155 .ops = &omap2_mcbsp_ops,
156 .buffer_size = 0x6F, 156 .buffer_size = 0x80, /* The FIFO has 128 locations */
157 }, 157 },
158 { 158 {
159 .phys_base = OMAP34XX_MCBSP4_BASE, 159 .phys_base = OMAP34XX_MCBSP4_BASE,
@@ -162,7 +162,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
162 .rx_irq = INT_24XX_MCBSP4_IRQ_RX, 162 .rx_irq = INT_24XX_MCBSP4_IRQ_RX,
163 .tx_irq = INT_24XX_MCBSP4_IRQ_TX, 163 .tx_irq = INT_24XX_MCBSP4_IRQ_TX,
164 .ops = &omap2_mcbsp_ops, 164 .ops = &omap2_mcbsp_ops,
165 .buffer_size = 0x6F, 165 .buffer_size = 0x80, /* The FIFO has 128 locations */
166 }, 166 },
167 { 167 {
168 .phys_base = OMAP34XX_MCBSP5_BASE, 168 .phys_base = OMAP34XX_MCBSP5_BASE,
@@ -171,7 +171,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
171 .rx_irq = INT_24XX_MCBSP5_IRQ_RX, 171 .rx_irq = INT_24XX_MCBSP5_IRQ_RX,
172 .tx_irq = INT_24XX_MCBSP5_IRQ_TX, 172 .tx_irq = INT_24XX_MCBSP5_IRQ_TX,
173 .ops = &omap2_mcbsp_ops, 173 .ops = &omap2_mcbsp_ops,
174 .buffer_size = 0x6F, 174 .buffer_size = 0x80, /* The FIFO has 128 locations */
175 }, 175 },
176}; 176};
177#define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata) 177#define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata)