diff options
author | Peter Ujfalusi <peter.ujfalusi@nokia.com> | 2010-06-03 00:39:33 -0400 |
---|---|---|
committer | Liam Girdwood <lrg@slimlogic.co.uk> | 2010-06-03 11:12:40 -0400 |
commit | 451fd82dc148bd5ac9ed5b19b6915a1afe32b9cb (patch) | |
tree | 0bd09462f284fbdef0ed98f7d05ed4018302f296 | |
parent | 0acce82b3dd792c85079ca1f4f7ffd8c82427e0a (diff) |
OMAP3: McBSP: Change the way how the FIFO is handled
Use the actual FIFO size in words as buffer_size on OMAP3.
Change the threshold configuration to use 1 based numbering, when
specifying the allowed threshold maximum or the McBSP threshold value.
Set the default maximum threshold to (buffer_size - 0x10) intialy.
>From users of McBSP, now it is expected to use this method.
Asking for threshold 1 means that the value written to threshold registers
are going to be 0, which means 1 word threshold.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Jarkko Nikula <jhnikula@gmail.com>
Acked-by: Mark Brown <broonie@opensource.wolsfonmicro.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
-rw-r--r-- | arch/arm/mach-omap2/mcbsp.c | 10 | ||||
-rw-r--r-- | arch/arm/plat-omap/mcbsp.c | 30 |
2 files changed, 25 insertions, 15 deletions
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index c29337074ad3..8fb5e5345557 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c | |||
@@ -133,7 +133,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { | |||
133 | .rx_irq = INT_24XX_MCBSP1_IRQ_RX, | 133 | .rx_irq = INT_24XX_MCBSP1_IRQ_RX, |
134 | .tx_irq = INT_24XX_MCBSP1_IRQ_TX, | 134 | .tx_irq = INT_24XX_MCBSP1_IRQ_TX, |
135 | .ops = &omap2_mcbsp_ops, | 135 | .ops = &omap2_mcbsp_ops, |
136 | .buffer_size = 0x6F, | 136 | .buffer_size = 0x80, /* The FIFO has 128 locations */ |
137 | }, | 137 | }, |
138 | { | 138 | { |
139 | .phys_base = OMAP34XX_MCBSP2_BASE, | 139 | .phys_base = OMAP34XX_MCBSP2_BASE, |
@@ -143,7 +143,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { | |||
143 | .rx_irq = INT_24XX_MCBSP2_IRQ_RX, | 143 | .rx_irq = INT_24XX_MCBSP2_IRQ_RX, |
144 | .tx_irq = INT_24XX_MCBSP2_IRQ_TX, | 144 | .tx_irq = INT_24XX_MCBSP2_IRQ_TX, |
145 | .ops = &omap2_mcbsp_ops, | 145 | .ops = &omap2_mcbsp_ops, |
146 | .buffer_size = 0x3FF, | 146 | .buffer_size = 0x500, /* The FIFO has 1024 + 256 locations */ |
147 | }, | 147 | }, |
148 | { | 148 | { |
149 | .phys_base = OMAP34XX_MCBSP3_BASE, | 149 | .phys_base = OMAP34XX_MCBSP3_BASE, |
@@ -153,7 +153,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { | |||
153 | .rx_irq = INT_24XX_MCBSP3_IRQ_RX, | 153 | .rx_irq = INT_24XX_MCBSP3_IRQ_RX, |
154 | .tx_irq = INT_24XX_MCBSP3_IRQ_TX, | 154 | .tx_irq = INT_24XX_MCBSP3_IRQ_TX, |
155 | .ops = &omap2_mcbsp_ops, | 155 | .ops = &omap2_mcbsp_ops, |
156 | .buffer_size = 0x6F, | 156 | .buffer_size = 0x80, /* The FIFO has 128 locations */ |
157 | }, | 157 | }, |
158 | { | 158 | { |
159 | .phys_base = OMAP34XX_MCBSP4_BASE, | 159 | .phys_base = OMAP34XX_MCBSP4_BASE, |
@@ -162,7 +162,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { | |||
162 | .rx_irq = INT_24XX_MCBSP4_IRQ_RX, | 162 | .rx_irq = INT_24XX_MCBSP4_IRQ_RX, |
163 | .tx_irq = INT_24XX_MCBSP4_IRQ_TX, | 163 | .tx_irq = INT_24XX_MCBSP4_IRQ_TX, |
164 | .ops = &omap2_mcbsp_ops, | 164 | .ops = &omap2_mcbsp_ops, |
165 | .buffer_size = 0x6F, | 165 | .buffer_size = 0x80, /* The FIFO has 128 locations */ |
166 | }, | 166 | }, |
167 | { | 167 | { |
168 | .phys_base = OMAP34XX_MCBSP5_BASE, | 168 | .phys_base = OMAP34XX_MCBSP5_BASE, |
@@ -171,7 +171,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { | |||
171 | .rx_irq = INT_24XX_MCBSP5_IRQ_RX, | 171 | .rx_irq = INT_24XX_MCBSP5_IRQ_RX, |
172 | .tx_irq = INT_24XX_MCBSP5_IRQ_TX, | 172 | .tx_irq = INT_24XX_MCBSP5_IRQ_TX, |
173 | .ops = &omap2_mcbsp_ops, | 173 | .ops = &omap2_mcbsp_ops, |
174 | .buffer_size = 0x6F, | 174 | .buffer_size = 0x80, /* The FIFO has 128 locations */ |
175 | }, | 175 | }, |
176 | }; | 176 | }; |
177 | #define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata) | 177 | #define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata) |
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index 8bab0b28b7a3..4ef46047b787 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c | |||
@@ -481,9 +481,9 @@ int omap_st_is_enabled(unsigned int id) | |||
481 | EXPORT_SYMBOL(omap_st_is_enabled); | 481 | EXPORT_SYMBOL(omap_st_is_enabled); |
482 | 482 | ||
483 | /* | 483 | /* |
484 | * omap_mcbsp_set_tx_threshold configures how to deal | 484 | * omap_mcbsp_set_rx_threshold configures the transmit threshold in words. |
485 | * with transmit threshold. the threshold value and handler can be | 485 | * The threshold parameter is 1 based, and it is converted (threshold - 1) |
486 | * configure in here. | 486 | * for the THRSH2 register. |
487 | */ | 487 | */ |
488 | void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold) | 488 | void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold) |
489 | { | 489 | { |
@@ -498,14 +498,15 @@ void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold) | |||
498 | } | 498 | } |
499 | mcbsp = id_to_mcbsp_ptr(id); | 499 | mcbsp = id_to_mcbsp_ptr(id); |
500 | 500 | ||
501 | MCBSP_WRITE(mcbsp, THRSH2, threshold); | 501 | if (threshold && threshold <= mcbsp->max_tx_thres) |
502 | MCBSP_WRITE(mcbsp, THRSH2, threshold - 1); | ||
502 | } | 503 | } |
503 | EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold); | 504 | EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold); |
504 | 505 | ||
505 | /* | 506 | /* |
506 | * omap_mcbsp_set_rx_threshold configures how to deal | 507 | * omap_mcbsp_set_rx_threshold configures the receive threshold in words. |
507 | * with receive threshold. the threshold value and handler can be | 508 | * The threshold parameter is 1 based, and it is converted (threshold - 1) |
508 | * configure in here. | 509 | * for the THRSH1 register. |
509 | */ | 510 | */ |
510 | void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold) | 511 | void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold) |
511 | { | 512 | { |
@@ -520,7 +521,8 @@ void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold) | |||
520 | } | 521 | } |
521 | mcbsp = id_to_mcbsp_ptr(id); | 522 | mcbsp = id_to_mcbsp_ptr(id); |
522 | 523 | ||
523 | MCBSP_WRITE(mcbsp, THRSH1, threshold); | 524 | if (threshold && threshold <= mcbsp->max_rx_thres) |
525 | MCBSP_WRITE(mcbsp, THRSH1, threshold - 1); | ||
524 | } | 526 | } |
525 | EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold); | 527 | EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold); |
526 | 528 | ||
@@ -1697,8 +1699,16 @@ static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) | |||
1697 | { | 1699 | { |
1698 | mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT; | 1700 | mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT; |
1699 | if (cpu_is_omap34xx()) { | 1701 | if (cpu_is_omap34xx()) { |
1700 | mcbsp->max_tx_thres = max_thres(mcbsp); | 1702 | /* |
1701 | mcbsp->max_rx_thres = max_thres(mcbsp); | 1703 | * Initially configure the maximum thresholds to a safe value. |
1704 | * The McBSP FIFO usage with these values should not go under | ||
1705 | * 16 locations. | ||
1706 | * If the whole FIFO without safety buffer is used, than there | ||
1707 | * is a possibility that the DMA will be not able to push the | ||
1708 | * new data on time, causing channel shifts in runtime. | ||
1709 | */ | ||
1710 | mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10; | ||
1711 | mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10; | ||
1702 | /* | 1712 | /* |
1703 | * REVISIT: Set dmap_op_mode to THRESHOLD as default | 1713 | * REVISIT: Set dmap_op_mode to THRESHOLD as default |
1704 | * for mcbsp2 instances. | 1714 | * for mcbsp2 instances. |