aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-omap2/mcbsp.c
diff options
context:
space:
mode:
authorKishon Vijay Abraham I <kishon@ti.com>2011-02-24 15:51:45 -0500
committerTony Lindgren <tony@atomide.com>2011-02-24 15:51:45 -0500
commit3cf32bba8ca0e0052ca41d74d455a5805b7fea85 (patch)
treef985fb7169d528e40fa94c475d64b03dbfdc6c92 /arch/arm/mach-omap2/mcbsp.c
parentcd5038024d6c92fbe4bf67af91eea5c6fb24a192 (diff)
OMAP: McBSP: Convert McBSP to platform device model
Implement McBSP as platform device and add support for registering through platform device layer using resource structures. Later in this patch series, OMAP2+ McBSP driver would be modified to use hwmod framework after populating the omap2+ hwmod database. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@nokia.com> Acked-by: Jarkko Nikula <jhnikula@gmail.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2/mcbsp.c')
-rw-r--r--arch/arm/mach-omap2/mcbsp.c613
1 files changed, 495 insertions, 118 deletions
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 0526b758bdcc..765ebe7da723 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -105,173 +105,542 @@ EXPORT_SYMBOL(omap2_mcbsp_set_clks_src);
105/* Platform data */ 105/* Platform data */
106 106
107#ifdef CONFIG_SOC_OMAP2420 107#ifdef CONFIG_SOC_OMAP2420
108static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { 108struct resource omap2420_mcbsp_res[][6] = {
109 { 109 {
110 .phys_base = OMAP24XX_MCBSP1_BASE, 110 {
111 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX, 111 .start = OMAP24XX_MCBSP1_BASE,
112 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, 112 .end = OMAP24XX_MCBSP1_BASE + SZ_256,
113 .rx_irq = INT_24XX_MCBSP1_IRQ_RX, 113 .flags = IORESOURCE_MEM,
114 .tx_irq = INT_24XX_MCBSP1_IRQ_TX, 114 },
115 {
116 .name = "rx",
117 .start = INT_24XX_MCBSP1_IRQ_RX,
118 .flags = IORESOURCE_IRQ,
119 },
120 {
121 .name = "tx",
122 .start = INT_24XX_MCBSP1_IRQ_TX,
123 .flags = IORESOURCE_IRQ,
124 },
125 {
126 .name = "rx",
127 .start = OMAP24XX_DMA_MCBSP1_RX,
128 .flags = IORESOURCE_DMA,
129 },
130 {
131 .name = "tx",
132 .start = OMAP24XX_DMA_MCBSP1_TX,
133 .flags = IORESOURCE_DMA,
134 },
115 }, 135 },
116 { 136 {
117 .phys_base = OMAP24XX_MCBSP2_BASE, 137 {
118 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX, 138 .start = OMAP24XX_MCBSP2_BASE,
119 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, 139 .end = OMAP24XX_MCBSP2_BASE + SZ_256,
120 .rx_irq = INT_24XX_MCBSP2_IRQ_RX, 140 .flags = IORESOURCE_MEM,
121 .tx_irq = INT_24XX_MCBSP2_IRQ_TX, 141 },
142 {
143 .name = "rx",
144 .start = INT_24XX_MCBSP2_IRQ_RX,
145 .flags = IORESOURCE_IRQ,
146 },
147 {
148 .name = "tx",
149 .start = INT_24XX_MCBSP2_IRQ_TX,
150 .flags = IORESOURCE_IRQ,
151 },
152 {
153 .name = "rx",
154 .start = OMAP24XX_DMA_MCBSP2_RX,
155 .flags = IORESOURCE_DMA,
156 },
157 {
158 .name = "tx",
159 .start = OMAP24XX_DMA_MCBSP2_TX,
160 .flags = IORESOURCE_DMA,
161 },
122 }, 162 },
123}; 163};
124#define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata) 164#define OMAP2420_MCBSP_RES_SZ ARRAY_SIZE(omap2420_mcbsp_res[1])
125#define OMAP2420_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1) 165#define OMAP2420_MCBSP_COUNT ARRAY_SIZE(omap2420_mcbsp_res)
126#else 166#else
127#define omap2420_mcbsp_pdata NULL 167#define omap2420_mcbsp_res NULL
128#define OMAP2420_MCBSP_PDATA_SZ 0 168#define OMAP2420_MCBSP_RES_SZ 0
129#define OMAP2420_MCBSP_REG_NUM 0 169#define OMAP2420_MCBSP_COUNT 0
130#endif 170#endif
131 171
172#define omap2420_mcbsp_pdata NULL
173
132#ifdef CONFIG_SOC_OMAP2430 174#ifdef CONFIG_SOC_OMAP2430
133static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { 175struct resource omap2430_mcbsp_res[][6] = {
134 { 176 {
135 .phys_base = OMAP24XX_MCBSP1_BASE, 177 {
136 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX, 178 .start = OMAP24XX_MCBSP1_BASE,
137 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, 179 .end = OMAP24XX_MCBSP1_BASE + SZ_256,
138 .rx_irq = INT_24XX_MCBSP1_IRQ_RX, 180 .flags = IORESOURCE_MEM,
139 .tx_irq = INT_24XX_MCBSP1_IRQ_TX, 181 },
182 {
183 .name = "rx",
184 .start = INT_24XX_MCBSP1_IRQ_RX,
185 .flags = IORESOURCE_IRQ,
186 },
187 {
188 .name = "tx",
189 .start = INT_24XX_MCBSP1_IRQ_TX,
190 .flags = IORESOURCE_IRQ,
191 },
192 {
193 .name = "rx",
194 .start = OMAP24XX_DMA_MCBSP1_RX,
195 .flags = IORESOURCE_DMA,
196 },
197 {
198 .name = "tx",
199 .start = OMAP24XX_DMA_MCBSP1_TX,
200 .flags = IORESOURCE_DMA,
201 },
140 }, 202 },
141 { 203 {
142 .phys_base = OMAP24XX_MCBSP2_BASE, 204 {
143 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX, 205 .start = OMAP24XX_MCBSP2_BASE,
144 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, 206 .end = OMAP24XX_MCBSP2_BASE + SZ_256,
145 .rx_irq = INT_24XX_MCBSP2_IRQ_RX, 207 .flags = IORESOURCE_MEM,
146 .tx_irq = INT_24XX_MCBSP2_IRQ_TX, 208 },
209 {
210 .name = "rx",
211 .start = INT_24XX_MCBSP2_IRQ_RX,
212 .flags = IORESOURCE_IRQ,
213 },
214 {
215 .name = "tx",
216 .start = INT_24XX_MCBSP2_IRQ_TX,
217 .flags = IORESOURCE_IRQ,
218 },
219 {
220 .name = "rx",
221 .start = OMAP24XX_DMA_MCBSP2_RX,
222 .flags = IORESOURCE_DMA,
223 },
224 {
225 .name = "tx",
226 .start = OMAP24XX_DMA_MCBSP2_TX,
227 .flags = IORESOURCE_DMA,
228 },
147 }, 229 },
148 { 230 {
149 .phys_base = OMAP2430_MCBSP3_BASE, 231 {
150 .dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX, 232 .start = OMAP2430_MCBSP3_BASE,
151 .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX, 233 .end = OMAP2430_MCBSP3_BASE + SZ_256,
152 .rx_irq = INT_24XX_MCBSP3_IRQ_RX, 234 .flags = IORESOURCE_MEM,
153 .tx_irq = INT_24XX_MCBSP3_IRQ_TX, 235 },
236 {
237 .name = "rx",
238 .start = INT_24XX_MCBSP3_IRQ_RX,
239 .flags = IORESOURCE_IRQ,
240 },
241 {
242 .name = "tx",
243 .start = INT_24XX_MCBSP3_IRQ_TX,
244 .flags = IORESOURCE_IRQ,
245 },
246 {
247 .name = "rx",
248 .start = OMAP24XX_DMA_MCBSP3_RX,
249 .flags = IORESOURCE_DMA,
250 },
251 {
252 .name = "tx",
253 .start = OMAP24XX_DMA_MCBSP3_TX,
254 .flags = IORESOURCE_DMA,
255 },
154 }, 256 },
155 { 257 {
156 .phys_base = OMAP2430_MCBSP4_BASE, 258 {
157 .dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX, 259 .start = OMAP2430_MCBSP4_BASE,
158 .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX, 260 .end = OMAP2430_MCBSP4_BASE + SZ_256,
159 .rx_irq = INT_24XX_MCBSP4_IRQ_RX, 261 .flags = IORESOURCE_MEM,
160 .tx_irq = INT_24XX_MCBSP4_IRQ_TX, 262 },
263 {
264 .name = "rx",
265 .start = INT_24XX_MCBSP4_IRQ_RX,
266 .flags = IORESOURCE_IRQ,
267 },
268 {
269 .name = "tx",
270 .start = INT_24XX_MCBSP4_IRQ_TX,
271 .flags = IORESOURCE_IRQ,
272 },
273 {
274 .name = "rx",
275 .start = OMAP24XX_DMA_MCBSP4_RX,
276 .flags = IORESOURCE_DMA,
277 },
278 {
279 .name = "tx",
280 .start = OMAP24XX_DMA_MCBSP4_TX,
281 .flags = IORESOURCE_DMA,
282 },
161 }, 283 },
162 { 284 {
163 .phys_base = OMAP2430_MCBSP5_BASE, 285 {
164 .dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX, 286 .start = OMAP2430_MCBSP5_BASE,
165 .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX, 287 .end = OMAP2430_MCBSP5_BASE + SZ_256,
166 .rx_irq = INT_24XX_MCBSP5_IRQ_RX, 288 .flags = IORESOURCE_MEM,
167 .tx_irq = INT_24XX_MCBSP5_IRQ_TX, 289 },
290 {
291 .name = "rx",
292 .start = INT_24XX_MCBSP5_IRQ_RX,
293 .flags = IORESOURCE_IRQ,
294 },
295 {
296 .name = "tx",
297 .start = INT_24XX_MCBSP5_IRQ_TX,
298 .flags = IORESOURCE_IRQ,
299 },
300 {
301 .name = "rx",
302 .start = OMAP24XX_DMA_MCBSP5_RX,
303 .flags = IORESOURCE_DMA,
304 },
305 {
306 .name = "tx",
307 .start = OMAP24XX_DMA_MCBSP5_TX,
308 .flags = IORESOURCE_DMA,
309 },
168 }, 310 },
169}; 311};
170#define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata) 312#define OMAP2430_MCBSP_RES_SZ ARRAY_SIZE(omap2430_mcbsp_res[1])
171#define OMAP2430_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1) 313#define OMAP2430_MCBSP_COUNT ARRAY_SIZE(omap2430_mcbsp_res)
172#else 314#else
173#define omap2430_mcbsp_pdata NULL 315#define omap2430_mcbsp_res NULL
174#define OMAP2430_MCBSP_PDATA_SZ 0 316#define OMAP2430_MCBSP_RES_SZ 0
175#define OMAP2430_MCBSP_REG_NUM 0 317#define OMAP2430_MCBSP_COUNT 0
176#endif 318#endif
177 319
320#define omap2430_mcbsp_pdata NULL
321
178#ifdef CONFIG_ARCH_OMAP3 322#ifdef CONFIG_ARCH_OMAP3
323struct resource omap34xx_mcbsp_res[][7] = {
324 {
325 {
326 .start = OMAP34XX_MCBSP1_BASE,
327 .end = OMAP34XX_MCBSP1_BASE + SZ_256,
328 .flags = IORESOURCE_MEM,
329 },
330 {
331 .name = "rx",
332 .start = INT_24XX_MCBSP1_IRQ_RX,
333 .flags = IORESOURCE_IRQ,
334 },
335 {
336 .name = "tx",
337 .start = INT_24XX_MCBSP1_IRQ_TX,
338 .flags = IORESOURCE_IRQ,
339 },
340 {
341 .name = "rx",
342 .start = OMAP24XX_DMA_MCBSP1_RX,
343 .flags = IORESOURCE_DMA,
344 },
345 {
346 .name = "tx",
347 .start = OMAP24XX_DMA_MCBSP1_TX,
348 .flags = IORESOURCE_DMA,
349 },
350 },
351 {
352 {
353 .start = OMAP34XX_MCBSP2_BASE,
354 .end = OMAP34XX_MCBSP2_BASE + SZ_256,
355 .flags = IORESOURCE_MEM,
356 },
357 {
358 .name = "sidetone",
359 .start = OMAP34XX_MCBSP2_ST_BASE,
360 .end = OMAP34XX_MCBSP2_ST_BASE + SZ_256,
361 .flags = IORESOURCE_MEM,
362 },
363 {
364 .name = "rx",
365 .start = INT_24XX_MCBSP2_IRQ_RX,
366 .flags = IORESOURCE_IRQ,
367 },
368 {
369 .name = "tx",
370 .start = INT_24XX_MCBSP2_IRQ_TX,
371 .flags = IORESOURCE_IRQ,
372 },
373 {
374 .name = "rx",
375 .start = OMAP24XX_DMA_MCBSP2_RX,
376 .flags = IORESOURCE_DMA,
377 },
378 {
379 .name = "tx",
380 .start = OMAP24XX_DMA_MCBSP2_TX,
381 .flags = IORESOURCE_DMA,
382 },
383 },
384 {
385 {
386 .start = OMAP34XX_MCBSP3_BASE,
387 .end = OMAP34XX_MCBSP3_BASE + SZ_256,
388 .flags = IORESOURCE_MEM,
389 },
390 {
391 .name = "sidetone",
392 .start = OMAP34XX_MCBSP3_ST_BASE,
393 .end = OMAP34XX_MCBSP3_ST_BASE + SZ_256,
394 .flags = IORESOURCE_MEM,
395 },
396 {
397 .name = "rx",
398 .start = INT_24XX_MCBSP3_IRQ_RX,
399 .flags = IORESOURCE_IRQ,
400 },
401 {
402 .name = "tx",
403 .start = INT_24XX_MCBSP3_IRQ_TX,
404 .flags = IORESOURCE_IRQ,
405 },
406 {
407 .name = "rx",
408 .start = OMAP24XX_DMA_MCBSP3_RX,
409 .flags = IORESOURCE_DMA,
410 },
411 {
412 .name = "tx",
413 .start = OMAP24XX_DMA_MCBSP3_TX,
414 .flags = IORESOURCE_DMA,
415 },
416 },
417 {
418 {
419 .start = OMAP34XX_MCBSP4_BASE,
420 .end = OMAP34XX_MCBSP4_BASE + SZ_256,
421 .flags = IORESOURCE_MEM,
422 },
423 {
424 .name = "rx",
425 .start = INT_24XX_MCBSP4_IRQ_RX,
426 .flags = IORESOURCE_IRQ,
427 },
428 {
429 .name = "tx",
430 .start = INT_24XX_MCBSP4_IRQ_TX,
431 .flags = IORESOURCE_IRQ,
432 },
433 {
434 .name = "rx",
435 .start = OMAP24XX_DMA_MCBSP4_RX,
436 .flags = IORESOURCE_DMA,
437 },
438 {
439 .name = "tx",
440 .start = OMAP24XX_DMA_MCBSP4_TX,
441 .flags = IORESOURCE_DMA,
442 },
443 },
444 {
445 {
446 .start = OMAP34XX_MCBSP5_BASE,
447 .end = OMAP34XX_MCBSP5_BASE + SZ_256,
448 .flags = IORESOURCE_MEM,
449 },
450 {
451 .name = "rx",
452 .start = INT_24XX_MCBSP5_IRQ_RX,
453 .flags = IORESOURCE_IRQ,
454 },
455 {
456 .name = "tx",
457 .start = INT_24XX_MCBSP5_IRQ_TX,
458 .flags = IORESOURCE_IRQ,
459 },
460 {
461 .name = "rx",
462 .start = OMAP24XX_DMA_MCBSP5_RX,
463 .flags = IORESOURCE_DMA,
464 },
465 {
466 .name = "tx",
467 .start = OMAP24XX_DMA_MCBSP5_TX,
468 .flags = IORESOURCE_DMA,
469 },
470 },
471};
472
179static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { 473static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
180 { 474 {
181 .phys_base = OMAP34XX_MCBSP1_BASE,
182 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
183 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
184 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
185 .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
186 .buffer_size = 0x80, /* The FIFO has 128 locations */ 475 .buffer_size = 0x80, /* The FIFO has 128 locations */
187 }, 476 },
188 { 477 {
189 .phys_base = OMAP34XX_MCBSP2_BASE,
190 .phys_base_st = OMAP34XX_MCBSP2_ST_BASE,
191 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
192 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
193 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
194 .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
195 .buffer_size = 0x500, /* The FIFO has 1024 + 256 locations */ 478 .buffer_size = 0x500, /* The FIFO has 1024 + 256 locations */
196 }, 479 },
197 { 480 {
198 .phys_base = OMAP34XX_MCBSP3_BASE,
199 .phys_base_st = OMAP34XX_MCBSP3_ST_BASE,
200 .dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX,
201 .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX,
202 .rx_irq = INT_24XX_MCBSP3_IRQ_RX,
203 .tx_irq = INT_24XX_MCBSP3_IRQ_TX,
204 .buffer_size = 0x80, /* The FIFO has 128 locations */ 481 .buffer_size = 0x80, /* The FIFO has 128 locations */
205 }, 482 },
206 { 483 {
207 .phys_base = OMAP34XX_MCBSP4_BASE,
208 .dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX,
209 .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX,
210 .rx_irq = INT_24XX_MCBSP4_IRQ_RX,
211 .tx_irq = INT_24XX_MCBSP4_IRQ_TX,
212 .buffer_size = 0x80, /* The FIFO has 128 locations */ 484 .buffer_size = 0x80, /* The FIFO has 128 locations */
213 }, 485 },
214 { 486 {
215 .phys_base = OMAP34XX_MCBSP5_BASE,
216 .dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX,
217 .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX,
218 .rx_irq = INT_24XX_MCBSP5_IRQ_RX,
219 .tx_irq = INT_24XX_MCBSP5_IRQ_TX,
220 .buffer_size = 0x80, /* The FIFO has 128 locations */ 487 .buffer_size = 0x80, /* The FIFO has 128 locations */
221 }, 488 },
222}; 489};
223#define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata) 490#define OMAP34XX_MCBSP_RES_SZ ARRAY_SIZE(omap34xx_mcbsp_res[1])
224#define OMAP34XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1) 491#define OMAP34XX_MCBSP_COUNT ARRAY_SIZE(omap34xx_mcbsp_res)
225#else 492#else
226#define omap34xx_mcbsp_pdata NULL 493#define omap34xx_mcbsp_pdata NULL
227#define OMAP34XX_MCBSP_PDATA_SZ 0 494#define omap34XX_mcbsp_res NULL
228#define OMAP34XX_MCBSP_REG_NUM 0 495#define OMAP34XX_MCBSP_RES_SZ 0
496#define OMAP34XX_MCBSP_COUNT 0
229#endif 497#endif
230 498
231static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = { 499struct resource omap44xx_mcbsp_res[][6] = {
232 { 500 {
233 .phys_base = OMAP44XX_MCBSP1_BASE, 501 {
234 .dma_rx_sync = OMAP44XX_DMA_MCBSP1_RX, 502 .name = "mpu",
235 .dma_tx_sync = OMAP44XX_DMA_MCBSP1_TX, 503 .start = OMAP44XX_MCBSP1_BASE,
236 .tx_irq = OMAP44XX_IRQ_MCBSP1, 504 .end = OMAP44XX_MCBSP1_BASE + SZ_256,
505 .flags = IORESOURCE_MEM,
506 },
507 {
508 .name = "dma",
509 .start = OMAP44XX_MCBSP1_DMA_BASE,
510 .end = OMAP44XX_MCBSP1_DMA_BASE + SZ_256,
511 .flags = IORESOURCE_MEM,
512 },
513 {
514 .name = "rx",
515 .start = 0,
516 .flags = IORESOURCE_IRQ,
517 },
518 {
519 .name = "tx",
520 .start = OMAP44XX_IRQ_MCBSP1,
521 .flags = IORESOURCE_IRQ,
522 },
523 {
524 .name = "rx",
525 .start = OMAP44XX_DMA_MCBSP1_RX,
526 .flags = IORESOURCE_DMA,
527 },
528 {
529 .name = "tx",
530 .start = OMAP44XX_DMA_MCBSP1_TX,
531 .flags = IORESOURCE_DMA,
532 },
237 }, 533 },
238 { 534 {
239 .phys_base = OMAP44XX_MCBSP2_BASE, 535 {
240 .dma_rx_sync = OMAP44XX_DMA_MCBSP2_RX, 536 .name = "mpu",
241 .dma_tx_sync = OMAP44XX_DMA_MCBSP2_TX, 537 .start = OMAP44XX_MCBSP2_BASE,
242 .tx_irq = OMAP44XX_IRQ_MCBSP2, 538 .end = OMAP44XX_MCBSP2_BASE + SZ_256,
539 .flags = IORESOURCE_MEM,
540 },
541 {
542 .name = "dma",
543 .start = OMAP44XX_MCBSP2_DMA_BASE,
544 .end = OMAP44XX_MCBSP2_DMA_BASE + SZ_256,
545 .flags = IORESOURCE_MEM,
546 },
547 {
548 .name = "rx",
549 .start = 0,
550 .flags = IORESOURCE_IRQ,
551 },
552 {
553 .name = "tx",
554 .start = OMAP44XX_IRQ_MCBSP2,
555 .flags = IORESOURCE_IRQ,
556 },
557 {
558 .name = "rx",
559 .start = OMAP44XX_DMA_MCBSP2_RX,
560 .flags = IORESOURCE_DMA,
561 },
562 {
563 .name = "tx",
564 .start = OMAP44XX_DMA_MCBSP2_TX,
565 .flags = IORESOURCE_DMA,
566 },
243 }, 567 },
244 { 568 {
245 .phys_base = OMAP44XX_MCBSP3_BASE, 569 {
246 .dma_rx_sync = OMAP44XX_DMA_MCBSP3_RX, 570 .name = "mpu",
247 .dma_tx_sync = OMAP44XX_DMA_MCBSP3_TX, 571 .start = OMAP44XX_MCBSP3_BASE,
248 .tx_irq = OMAP44XX_IRQ_MCBSP3, 572 .end = OMAP44XX_MCBSP3_BASE + SZ_256,
573 .flags = IORESOURCE_MEM,
574 },
575 {
576 .name = "dma",
577 .start = OMAP44XX_MCBSP3_DMA_BASE,
578 .end = OMAP44XX_MCBSP3_DMA_BASE + SZ_256,
579 .flags = IORESOURCE_MEM,
580 },
581 {
582 .name = "rx",
583 .start = 0,
584 .flags = IORESOURCE_IRQ,
585 },
586 {
587 .name = "tx",
588 .start = OMAP44XX_IRQ_MCBSP3,
589 .flags = IORESOURCE_IRQ,
590 },
591 {
592 .name = "rx",
593 .start = OMAP44XX_DMA_MCBSP3_RX,
594 .flags = IORESOURCE_DMA,
595 },
596 {
597 .name = "tx",
598 .start = OMAP44XX_DMA_MCBSP3_TX,
599 .flags = IORESOURCE_DMA,
600 },
249 }, 601 },
250 { 602 {
251 .phys_base = OMAP44XX_MCBSP4_BASE, 603 {
252 .dma_rx_sync = OMAP44XX_DMA_MCBSP4_RX, 604 .start = OMAP44XX_MCBSP4_BASE,
253 .dma_tx_sync = OMAP44XX_DMA_MCBSP4_TX, 605 .end = OMAP44XX_MCBSP4_BASE + SZ_256,
254 .tx_irq = OMAP44XX_IRQ_MCBSP4, 606 .flags = IORESOURCE_MEM,
607 },
608 {
609 .name = "rx",
610 .start = 0,
611 .flags = IORESOURCE_IRQ,
612 },
613 {
614 .name = "tx",
615 .start = OMAP44XX_IRQ_MCBSP4,
616 .flags = IORESOURCE_IRQ,
617 },
618 {
619 .name = "rx",
620 .start = OMAP44XX_DMA_MCBSP4_RX,
621 .flags = IORESOURCE_DMA,
622 },
623 {
624 .name = "tx",
625 .start = OMAP44XX_DMA_MCBSP4_TX,
626 .flags = IORESOURCE_DMA,
627 },
255 }, 628 },
256}; 629};
257#define OMAP44XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap44xx_mcbsp_pdata) 630#define omap44xx_mcbsp_pdata NULL
258#define OMAP44XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1) 631#define OMAP44XX_MCBSP_RES_SZ ARRAY_SIZE(omap44xx_mcbsp_res[1])
632#define OMAP44XX_MCBSP_COUNT ARRAY_SIZE(omap44xx_mcbsp_res)
259 633
260static int __init omap2_mcbsp_init(void) 634static int __init omap2_mcbsp_init(void)
261{ 635{
262 if (cpu_is_omap2420()) { 636 if (cpu_is_omap2420())
263 omap_mcbsp_count = OMAP2420_MCBSP_PDATA_SZ; 637 omap_mcbsp_count = OMAP2420_MCBSP_COUNT;
264 omap_mcbsp_cache_size = OMAP2420_MCBSP_REG_NUM * sizeof(u16); 638 else if (cpu_is_omap2430())
265 } else if (cpu_is_omap2430()) { 639 omap_mcbsp_count = OMAP2430_MCBSP_COUNT;
266 omap_mcbsp_count = OMAP2430_MCBSP_PDATA_SZ; 640 else if (cpu_is_omap34xx())
267 omap_mcbsp_cache_size = OMAP2430_MCBSP_REG_NUM * sizeof(u32); 641 omap_mcbsp_count = OMAP34XX_MCBSP_COUNT;
268 } else if (cpu_is_omap34xx()) { 642 else if (cpu_is_omap44xx())
269 omap_mcbsp_count = OMAP34XX_MCBSP_PDATA_SZ; 643 omap_mcbsp_count = OMAP44XX_MCBSP_COUNT;
270 omap_mcbsp_cache_size = OMAP34XX_MCBSP_REG_NUM * sizeof(u32);
271 } else if (cpu_is_omap44xx()) {
272 omap_mcbsp_count = OMAP44XX_MCBSP_PDATA_SZ;
273 omap_mcbsp_cache_size = OMAP44XX_MCBSP_REG_NUM * sizeof(u32);
274 }
275 644
276 mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *), 645 mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
277 GFP_KERNEL); 646 GFP_KERNEL);
@@ -279,17 +648,25 @@ static int __init omap2_mcbsp_init(void)
279 return -ENOMEM; 648 return -ENOMEM;
280 649
281 if (cpu_is_omap2420()) 650 if (cpu_is_omap2420())
282 omap_mcbsp_register_board_cfg(omap2420_mcbsp_pdata, 651 omap_mcbsp_register_board_cfg(omap2420_mcbsp_res[0],
283 OMAP2420_MCBSP_PDATA_SZ); 652 OMAP2420_MCBSP_RES_SZ,
653 omap2420_mcbsp_pdata,
654 OMAP2420_MCBSP_COUNT);
284 if (cpu_is_omap2430()) 655 if (cpu_is_omap2430())
285 omap_mcbsp_register_board_cfg(omap2430_mcbsp_pdata, 656 omap_mcbsp_register_board_cfg(omap2430_mcbsp_res[0],
286 OMAP2430_MCBSP_PDATA_SZ); 657 OMAP2420_MCBSP_RES_SZ,
658 omap2430_mcbsp_pdata,
659 OMAP2430_MCBSP_COUNT);
287 if (cpu_is_omap34xx()) 660 if (cpu_is_omap34xx())
288 omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata, 661 omap_mcbsp_register_board_cfg(omap34xx_mcbsp_res[0],
289 OMAP34XX_MCBSP_PDATA_SZ); 662 OMAP34XX_MCBSP_RES_SZ,
663 omap34xx_mcbsp_pdata,
664 OMAP34XX_MCBSP_COUNT);
290 if (cpu_is_omap44xx()) 665 if (cpu_is_omap44xx())
291 omap_mcbsp_register_board_cfg(omap44xx_mcbsp_pdata, 666 omap_mcbsp_register_board_cfg(omap44xx_mcbsp_res[0],
292 OMAP44XX_MCBSP_PDATA_SZ); 667 OMAP44XX_MCBSP_RES_SZ,
668 omap44xx_mcbsp_pdata,
669 OMAP44XX_MCBSP_COUNT);
293 670
294 return omap_mcbsp_init(); 671 return omap_mcbsp_init();
295} 672}
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-21 05:37:31 -0400