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authorKishon Vijay Abraham I <kishon@ti.com>2011-02-24 15:51:45 -0500
committerTony Lindgren <tony@atomide.com>2011-02-24 15:51:45 -0500
commit3cf32bba8ca0e0052ca41d74d455a5805b7fea85 (patch)
treef985fb7169d528e40fa94c475d64b03dbfdc6c92
parentcd5038024d6c92fbe4bf67af91eea5c6fb24a192 (diff)
OMAP: McBSP: Convert McBSP to platform device model
Implement McBSP as platform device and add support for registering through platform device layer using resource structures. Later in this patch series, OMAP2+ McBSP driver would be modified to use hwmod framework after populating the omap2+ hwmod database. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@nokia.com> Acked-by: Jarkko Nikula <jhnikula@gmail.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat
-rw-r--r--arch/arm/mach-omap1/mcbsp.c327
-rw-r--r--arch/arm/mach-omap2/mcbsp.c613
-rw-r--r--arch/arm/plat-omap/devices.c10
-rw-r--r--arch/arm/plat-omap/include/plat/mcbsp.h14
-rw-r--r--arch/arm/plat-omap/mcbsp.c59
5 files changed, 818 insertions, 205 deletions
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index 820973666f34..e68f6c012fde 100644
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -10,6 +10,7 @@
10 * 10 *
11 * Multichannel mode not supported. 11 * Multichannel mode not supported.
12 */ 12 */
13#include <linux/ioport.h>
13#include <linux/module.h> 14#include <linux/module.h>
14#include <linux/init.h> 15#include <linux/init.h>
15#include <linux/clk.h> 16#include <linux/clk.h>
@@ -78,100 +79,288 @@ static struct omap_mcbsp_ops omap1_mcbsp_ops = {
78}; 79};
79 80
80#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) 81#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
82struct resource omap7xx_mcbsp_res[][6] = {
83 {
84 {
85 .start = OMAP7XX_MCBSP1_BASE,
86 .end = OMAP7XX_MCBSP1_BASE + SZ_256,
87 .flags = IORESOURCE_MEM,
88 },
89 {
90 .name = "rx",
91 .start = INT_7XX_McBSP1RX,
92 .flags = IORESOURCE_IRQ,
93 },
94 {
95 .name = "tx",
96 .start = INT_7XX_McBSP1TX,
97 .flags = IORESOURCE_IRQ,
98 },
99 {
100 .name = "rx",
101 .start = OMAP_DMA_MCBSP1_RX,
102 .flags = IORESOURCE_DMA,
103 },
104 {
105 .name = "tx",
106 .start = OMAP_DMA_MCBSP1_TX,
107 .flags = IORESOURCE_DMA,
108 },
109 },
110 {
111 {
112 .start = OMAP7XX_MCBSP2_BASE,
113 .end = OMAP7XX_MCBSP2_BASE + SZ_256,
114 .flags = IORESOURCE_MEM,
115 },
116 {
117 .name = "rx",
118 .start = INT_7XX_McBSP2RX,
119 .flags = IORESOURCE_IRQ,
120 },
121 {
122 .name = "tx",
123 .start = INT_7XX_McBSP2TX,
124 .flags = IORESOURCE_IRQ,
125 },
126 {
127 .name = "rx",
128 .start = OMAP_DMA_MCBSP3_RX,
129 .flags = IORESOURCE_DMA,
130 },
131 {
132 .name = "tx",
133 .start = OMAP_DMA_MCBSP3_TX,
134 .flags = IORESOURCE_DMA,
135 },
136 },
137};
138
81static struct omap_mcbsp_platform_data omap7xx_mcbsp_pdata[] = { 139static struct omap_mcbsp_platform_data omap7xx_mcbsp_pdata[] = {
82 { 140 {
83 .phys_base = OMAP7XX_MCBSP1_BASE,
84 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
85 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
86 .rx_irq = INT_7XX_McBSP1RX,
87 .tx_irq = INT_7XX_McBSP1TX,
88 .ops = &omap1_mcbsp_ops, 141 .ops = &omap1_mcbsp_ops,
89 }, 142 },
90 { 143 {
91 .phys_base = OMAP7XX_MCBSP2_BASE,
92 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
93 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
94 .rx_irq = INT_7XX_McBSP2RX,
95 .tx_irq = INT_7XX_McBSP2TX,
96 .ops = &omap1_mcbsp_ops, 144 .ops = &omap1_mcbsp_ops,
97 }, 145 },
98}; 146};
99#define OMAP7XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap7xx_mcbsp_pdata) 147#define OMAP7XX_MCBSP_RES_SZ ARRAY_SIZE(omap7xx_mcbsp_res[1])
100#define OMAP7XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1) 148#define OMAP7XX_MCBSP_COUNT ARRAY_SIZE(omap7xx_mcbsp_res)
101#else 149#else
150#define omap7xx_mcbsp_res NULL
102#define omap7xx_mcbsp_pdata NULL 151#define omap7xx_mcbsp_pdata NULL
103#define OMAP7XX_MCBSP_PDATA_SZ 0 152#define OMAP7XX_MCBSP_RES_SZ 0
104#define OMAP7XX_MCBSP_REG_NUM 0 153#define OMAP7XX_MCBSP_COUNT 0
105#endif 154#endif
106 155
107#ifdef CONFIG_ARCH_OMAP15XX 156#ifdef CONFIG_ARCH_OMAP15XX
157struct resource omap15xx_mcbsp_res[][6] = {
158 {
159 {
160 .start = OMAP1510_MCBSP1_BASE,
161 .end = OMAP1510_MCBSP1_BASE + SZ_256,
162 .flags = IORESOURCE_MEM,
163 },
164 {
165 .name = "rx",
166 .start = INT_McBSP1RX,
167 .flags = IORESOURCE_IRQ,
168 },
169 {
170 .name = "tx",
171 .start = INT_McBSP1TX,
172 .flags = IORESOURCE_IRQ,
173 },
174 {
175 .name = "rx",
176 .start = OMAP_DMA_MCBSP1_RX,
177 .flags = IORESOURCE_DMA,
178 },
179 {
180 .name = "tx",
181 .start = OMAP_DMA_MCBSP1_TX,
182 .flags = IORESOURCE_DMA,
183 },
184 },
185 {
186 {
187 .start = OMAP1510_MCBSP2_BASE,
188 .end = OMAP1510_MCBSP2_BASE + SZ_256,
189 .flags = IORESOURCE_MEM,
190 },
191 {
192 .name = "rx",
193 .start = INT_1510_SPI_RX,
194 .flags = IORESOURCE_IRQ,
195 },
196 {
197 .name = "tx",
198 .start = INT_1510_SPI_TX,
199 .flags = IORESOURCE_IRQ,
200 },
201 {
202 .name = "rx",
203 .start = OMAP_DMA_MCBSP2_RX,
204 .flags = IORESOURCE_DMA,
205 },
206 {
207 .name = "tx",
208 .start = OMAP_DMA_MCBSP2_TX,
209 .flags = IORESOURCE_DMA,
210 },
211 },
212 {
213 {
214 .start = OMAP1510_MCBSP3_BASE,
215 .end = OMAP1510_MCBSP3_BASE + SZ_256,
216 .flags = IORESOURCE_MEM,
217 },
218 {
219 .name = "rx",
220 .start = INT_McBSP3RX,
221 .flags = IORESOURCE_IRQ,
222 },
223 {
224 .name = "tx",
225 .start = INT_McBSP3TX,
226 .flags = IORESOURCE_IRQ,
227 },
228 {
229 .name = "rx",
230 .start = OMAP_DMA_MCBSP3_RX,
231 .flags = IORESOURCE_DMA,
232 },
233 {
234 .name = "tx",
235 .start = OMAP_DMA_MCBSP3_TX,
236 .flags = IORESOURCE_DMA,
237 },
238 },
239};
240
108static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = { 241static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
109 { 242 {
110 .phys_base = OMAP1510_MCBSP1_BASE,
111 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
112 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
113 .rx_irq = INT_McBSP1RX,
114 .tx_irq = INT_McBSP1TX,
115 .ops = &omap1_mcbsp_ops, 243 .ops = &omap1_mcbsp_ops,
116 }, 244 },
117 { 245 {
118 .phys_base = OMAP1510_MCBSP2_BASE,
119 .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
120 .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
121 .rx_irq = INT_1510_SPI_RX,
122 .tx_irq = INT_1510_SPI_TX,
123 .ops = &omap1_mcbsp_ops, 246 .ops = &omap1_mcbsp_ops,
124 }, 247 },
125 { 248 {
126 .phys_base = OMAP1510_MCBSP3_BASE,
127 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
128 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
129 .rx_irq = INT_McBSP3RX,
130 .tx_irq = INT_McBSP3TX,
131 .ops = &omap1_mcbsp_ops, 249 .ops = &omap1_mcbsp_ops,
132 }, 250 },
133}; 251};
134#define OMAP15XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap15xx_mcbsp_pdata) 252#define OMAP15XX_MCBSP_RES_SZ ARRAY_SIZE(omap15xx_mcbsp_res[1])
135#define OMAP15XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1) 253#define OMAP15XX_MCBSP_COUNT ARRAY_SIZE(omap15xx_mcbsp_res)
136#else 254#else
255#define omap15xx_mcbsp_res NULL
137#define omap15xx_mcbsp_pdata NULL 256#define omap15xx_mcbsp_pdata NULL
138#define OMAP15XX_MCBSP_PDATA_SZ 0 257#define OMAP15XX_MCBSP_RES_SZ 0
139#define OMAP15XX_MCBSP_REG_NUM 0 258#define OMAP15XX_MCBSP_COUNT 0
140#endif 259#endif
141 260
142#ifdef CONFIG_ARCH_OMAP16XX 261#ifdef CONFIG_ARCH_OMAP16XX
262struct resource omap16xx_mcbsp_res[][6] = {
263 {
264 {
265 .start = OMAP1610_MCBSP1_BASE,
266 .end = OMAP1610_MCBSP1_BASE + SZ_256,
267 .flags = IORESOURCE_MEM,
268 },
269 {
270 .name = "rx",
271 .start = INT_McBSP1RX,
272 .flags = IORESOURCE_IRQ,
273 },
274 {
275 .name = "tx",
276 .start = INT_McBSP1TX,
277 .flags = IORESOURCE_IRQ,
278 },
279 {
280 .name = "rx",
281 .start = OMAP_DMA_MCBSP1_RX,
282 .flags = IORESOURCE_DMA,
283 },
284 {
285 .name = "tx",
286 .start = OMAP_DMA_MCBSP1_TX,
287 .flags = IORESOURCE_DMA,
288 },
289 },
290 {
291 {
292 .start = OMAP1610_MCBSP2_BASE,
293 .end = OMAP1610_MCBSP2_BASE + SZ_256,
294 .flags = IORESOURCE_MEM,
295 },
296 {
297 .name = "rx",
298 .start = INT_1610_McBSP2_RX,
299 .flags = IORESOURCE_IRQ,
300 },
301 {
302 .name = "tx",
303 .start = INT_1610_McBSP2_TX,
304 .flags = IORESOURCE_IRQ,
305 },
306 {
307 .name = "rx",
308 .start = OMAP_DMA_MCBSP2_RX,
309 .flags = IORESOURCE_DMA,
310 },
311 {
312 .name = "tx",
313 .start = OMAP_DMA_MCBSP2_TX,
314 .flags = IORESOURCE_DMA,
315 },
316 },
317 {
318 {
319 .start = OMAP1610_MCBSP3_BASE,
320 .end = OMAP1610_MCBSP3_BASE + SZ_256,
321 .flags = IORESOURCE_MEM,
322 },
323 {
324 .name = "rx",
325 .start = INT_McBSP3RX,
326 .flags = IORESOURCE_IRQ,
327 },
328 {
329 .name = "tx",
330 .start = INT_McBSP3TX,
331 .flags = IORESOURCE_IRQ,
332 },
333 {
334 .name = "rx",
335 .start = OMAP_DMA_MCBSP3_RX,
336 .flags = IORESOURCE_DMA,
337 },
338 {
339 .name = "tx",
340 .start = OMAP_DMA_MCBSP3_TX,
341 .flags = IORESOURCE_DMA,
342 },
343 },
344};
345
143static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = { 346static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
144 { 347 {
145 .phys_base = OMAP1610_MCBSP1_BASE,
146 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
147 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
148 .rx_irq = INT_McBSP1RX,
149 .tx_irq = INT_McBSP1TX,
150 .ops = &omap1_mcbsp_ops, 348 .ops = &omap1_mcbsp_ops,
151 }, 349 },
152 { 350 {
153 .phys_base = OMAP1610_MCBSP2_BASE,
154 .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
155 .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
156 .rx_irq = INT_1610_McBSP2_RX,
157 .tx_irq = INT_1610_McBSP2_TX,
158 .ops = &omap1_mcbsp_ops, 351 .ops = &omap1_mcbsp_ops,
159 }, 352 },
160 { 353 {
161 .phys_base = OMAP1610_MCBSP3_BASE,
162 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
163 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
164 .rx_irq = INT_McBSP3RX,
165 .tx_irq = INT_McBSP3TX,
166 .ops = &omap1_mcbsp_ops, 354 .ops = &omap1_mcbsp_ops,
167 }, 355 },
168}; 356};
169#define OMAP16XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap16xx_mcbsp_pdata) 357#define OMAP16XX_MCBSP_RES_SZ ARRAY_SIZE(omap16xx_mcbsp_res[1])
170#define OMAP16XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1) 358#define OMAP16XX_MCBSP_COUNT ARRAY_SIZE(omap16xx_mcbsp_res)
171#else 359#else
360#define omap16xx_mcbsp_res NULL
172#define omap16xx_mcbsp_pdata NULL 361#define omap16xx_mcbsp_pdata NULL
173#define OMAP16XX_MCBSP_PDATA_SZ 0 362#define OMAP16XX_MCBSP_RES_SZ 0
174#define OMAP16XX_MCBSP_REG_NUM 0 363#define OMAP16XX_MCBSP_COUNT 0
175#endif 364#endif
176 365
177static int __init omap1_mcbsp_init(void) 366static int __init omap1_mcbsp_init(void)
@@ -179,16 +368,12 @@ static int __init omap1_mcbsp_init(void)
179 if (!cpu_class_is_omap1()) 368 if (!cpu_class_is_omap1())
180 return -ENODEV; 369 return -ENODEV;
181 370
182 if (cpu_is_omap7xx()) { 371 if (cpu_is_omap7xx())
183 omap_mcbsp_count = OMAP7XX_MCBSP_PDATA_SZ; 372 omap_mcbsp_count = OMAP7XX_MCBSP_COUNT;
184 omap_mcbsp_cache_size = OMAP7XX_MCBSP_REG_NUM * sizeof(u16); 373 else if (cpu_is_omap15xx())
185 } else if (cpu_is_omap15xx()) { 374 omap_mcbsp_count = OMAP15XX_MCBSP_COUNT;
186 omap_mcbsp_count = OMAP15XX_MCBSP_PDATA_SZ; 375 else if (cpu_is_omap16xx())
187 omap_mcbsp_cache_size = OMAP15XX_MCBSP_REG_NUM * sizeof(u16); 376 omap_mcbsp_count = OMAP16XX_MCBSP_COUNT;
188 } else if (cpu_is_omap16xx()) {
189 omap_mcbsp_count = OMAP16XX_MCBSP_PDATA_SZ;
190 omap_mcbsp_cache_size = OMAP16XX_MCBSP_REG_NUM * sizeof(u16);
191 }
192 377
193 mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *), 378 mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
194 GFP_KERNEL); 379 GFP_KERNEL);
@@ -196,16 +381,22 @@ static int __init omap1_mcbsp_init(void)
196 return -ENOMEM; 381 return -ENOMEM;
197 382
198 if (cpu_is_omap7xx()) 383 if (cpu_is_omap7xx())
199 omap_mcbsp_register_board_cfg(omap7xx_mcbsp_pdata, 384 omap_mcbsp_register_board_cfg(omap7xx_mcbsp_res[0],
200 OMAP7XX_MCBSP_PDATA_SZ); 385 OMAP7XX_MCBSP_RES_SZ,
386 omap7xx_mcbsp_pdata,
387 OMAP7XX_MCBSP_COUNT);
201 388
202 if (cpu_is_omap15xx()) 389 if (cpu_is_omap15xx())
203 omap_mcbsp_register_board_cfg(omap15xx_mcbsp_pdata, 390 omap_mcbsp_register_board_cfg(omap15xx_mcbsp_res[0],
204 OMAP15XX_MCBSP_PDATA_SZ); 391 OMAP15XX_MCBSP_RES_SZ,
392 omap15xx_mcbsp_pdata,
393 OMAP15XX_MCBSP_COUNT);
205 394
206 if (cpu_is_omap16xx()) 395 if (cpu_is_omap16xx())
207 omap_mcbsp_register_board_cfg(omap16xx_mcbsp_pdata, 396 omap_mcbsp_register_board_cfg(omap16xx_mcbsp_res[0],
208 OMAP16XX_MCBSP_PDATA_SZ); 397 OMAP16XX_MCBSP_RES_SZ,
398 omap16xx_mcbsp_pdata,
399 OMAP16XX_MCBSP_COUNT);
209 400
210 return omap_mcbsp_init(); 401 return omap_mcbsp_init();
211} 402}
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 0526b758bdcc..765ebe7da723 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -105,173 +105,542 @@ EXPORT_SYMBOL(omap2_mcbsp_set_clks_src);
105/* Platform data */ 105/* Platform data */
106 106
107#ifdef CONFIG_SOC_OMAP2420 107#ifdef CONFIG_SOC_OMAP2420
108static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { 108struct resource omap2420_mcbsp_res[][6] = {
109 { 109 {
110 .phys_base = OMAP24XX_MCBSP1_BASE, 110 {
111 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX, 111 .start = OMAP24XX_MCBSP1_BASE,
112 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, 112 .end = OMAP24XX_MCBSP1_BASE + SZ_256,
113 .rx_irq = INT_24XX_MCBSP1_IRQ_RX, 113 .flags = IORESOURCE_MEM,
114 .tx_irq = INT_24XX_MCBSP1_IRQ_TX, 114 },
115 {
116 .name = "rx",
117 .start = INT_24XX_MCBSP1_IRQ_RX,
118 .flags = IORESOURCE_IRQ,
119 },
120 {
121 .name = "tx",
122 .start = INT_24XX_MCBSP1_IRQ_TX,
123 .flags = IORESOURCE_IRQ,
124 },
125 {
126 .name = "rx",
127 .start = OMAP24XX_DMA_MCBSP1_RX,
128 .flags = IORESOURCE_DMA,
129 },
130 {
131 .name = "tx",
132 .start = OMAP24XX_DMA_MCBSP1_TX,
133 .flags = IORESOURCE_DMA,
134 },
115 }, 135 },
116 { 136 {
117 .phys_base = OMAP24XX_MCBSP2_BASE, 137 {
118 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX, 138 .start = OMAP24XX_MCBSP2_BASE,
119 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, 139 .end = OMAP24XX_MCBSP2_BASE + SZ_256,
120 .rx_irq = INT_24XX_MCBSP2_IRQ_RX, 140 .flags = IORESOURCE_MEM,
121 .tx_irq = INT_24XX_MCBSP2_IRQ_TX, 141 },
142 {
143 .name = "rx",
144 .start = INT_24XX_MCBSP2_IRQ_RX,
145 .flags = IORESOURCE_IRQ,
146 },
147 {
148 .name = "tx",
149 .start = INT_24XX_MCBSP2_IRQ_TX,
150 .flags = IORESOURCE_IRQ,
151 },
152 {
153 .name = "rx",
154 .start = OMAP24XX_DMA_MCBSP2_RX,
155 .flags = IORESOURCE_DMA,
156 },
157 {
158 .name = "tx",
159 .start = OMAP24XX_DMA_MCBSP2_TX,
160 .flags = IORESOURCE_DMA,
161 },
122 }, 162 },
123}; 163};
124#define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata) 164#define OMAP2420_MCBSP_RES_SZ ARRAY_SIZE(omap2420_mcbsp_res[1])
125#define OMAP2420_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1) 165#define OMAP2420_MCBSP_COUNT ARRAY_SIZE(omap2420_mcbsp_res)
126#else 166#else
127#define omap2420_mcbsp_pdata NULL 167#define omap2420_mcbsp_res NULL
128#define OMAP2420_MCBSP_PDATA_SZ 0 168#define OMAP2420_MCBSP_RES_SZ 0
129#define OMAP2420_MCBSP_REG_NUM 0 169#define OMAP2420_MCBSP_COUNT 0
130#endif 170#endif
131 171
172#define omap2420_mcbsp_pdata NULL
173
132#ifdef CONFIG_SOC_OMAP2430 174#ifdef CONFIG_SOC_OMAP2430
133static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { 175struct resource omap2430_mcbsp_res[][6] = {
134 { 176 {
135 .phys_base = OMAP24XX_MCBSP1_BASE, 177 {
136 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX, 178 .start = OMAP24XX_MCBSP1_BASE,
137 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, 179 .end = OMAP24XX_MCBSP1_BASE + SZ_256,
138 .rx_irq = INT_24XX_MCBSP1_IRQ_RX, 180 .flags = IORESOURCE_MEM,
139 .tx_irq = INT_24XX_MCBSP1_IRQ_TX, 181 },
182 {
183 .name = "rx",
184 .start = INT_24XX_MCBSP1_IRQ_RX,
185 .flags = IORESOURCE_IRQ,
186 },
187 {
188 .name = "tx",
189 .start = INT_24XX_MCBSP1_IRQ_TX,
190 .flags = IORESOURCE_IRQ,
191 },
192 {
193 .name = "rx",
194 .start = OMAP24XX_DMA_MCBSP1_RX,
195 .flags = IORESOURCE_DMA,
196 },
197 {
198 .name = "tx",
199 .start = OMAP24XX_DMA_MCBSP1_TX,
200 .flags = IORESOURCE_DMA,
201 },
140 }, 202 },
141 { 203 {
142 .phys_base = OMAP24XX_MCBSP2_BASE, 204 {
143 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX, 205 .start = OMAP24XX_MCBSP2_BASE,
144 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, 206 .end = OMAP24XX_MCBSP2_BASE + SZ_256,
145 .rx_irq = INT_24XX_MCBSP2_IRQ_RX, 207 .flags = IORESOURCE_MEM,
146 .tx_irq = INT_24XX_MCBSP2_IRQ_TX, 208 },
209 {
210 .name = "rx",
211 .start = INT_24XX_MCBSP2_IRQ_RX,
212 .flags = IORESOURCE_IRQ,
213 },
214 {
215 .name = "tx",
216 .start = INT_24XX_MCBSP2_IRQ_TX,
217 .flags = IORESOURCE_IRQ,
218 },
219 {
220 .name = "rx",
221 .start = OMAP24XX_DMA_MCBSP2_RX,
222 .flags = IORESOURCE_DMA,
223 },
224 {
225 .name = "tx",
226 .start = OMAP24XX_DMA_MCBSP2_TX,
227 .flags = IORESOURCE_DMA,
228 },
147 }, 229 },
148 { 230 {
149 .phys_base = OMAP2430_MCBSP3_BASE, 231 {
150 .dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX, 232 .start = OMAP2430_MCBSP3_BASE,
151 .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX, 233 .end = OMAP2430_MCBSP3_BASE + SZ_256,
152 .rx_irq = INT_24XX_MCBSP3_IRQ_RX, 234 .flags = IORESOURCE_MEM,
153 .tx_irq = INT_24XX_MCBSP3_IRQ_TX, 235 },
236 {
237 .name = "rx",
238 .start = INT_24XX_MCBSP3_IRQ_RX,
239 .flags = IORESOURCE_IRQ,
240 },
241 {
242 .name = "tx",
243 .start = INT_24XX_MCBSP3_IRQ_TX,
244 .flags = IORESOURCE_IRQ,
245 },
246 {
247 .name = "rx",
248 .start = OMAP24XX_DMA_MCBSP3_RX,
249 .flags = IORESOURCE_DMA,
250 },
251 {
252 .name = "tx",
253 .start = OMAP24XX_DMA_MCBSP3_TX,
254 .flags = IORESOURCE_DMA,
255 },
154 }, 256 },
155 { 257 {
156 .phys_base = OMAP2430_MCBSP4_BASE, 258 {
157 .dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX, 259 .start = OMAP2430_MCBSP4_BASE,
158 .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX, 260 .end = OMAP2430_MCBSP4_BASE + SZ_256,
159 .rx_irq = INT_24XX_MCBSP4_IRQ_RX, 261 .flags = IORESOURCE_MEM,
160 .tx_irq = INT_24XX_MCBSP4_IRQ_TX, 262 },
263 {
264 .name = "rx",
265 .start = INT_24XX_MCBSP4_IRQ_RX,
266 .flags = IORESOURCE_IRQ,
267 },
268 {
269 .name = "tx",
270 .start = INT_24XX_MCBSP4_IRQ_TX,
271 .flags = IORESOURCE_IRQ,
272 },
273 {
274 .name = "rx",
275 .start = OMAP24XX_DMA_MCBSP4_RX,
276 .flags = IORESOURCE_DMA,
277 },
278 {
279 .name = "tx",
280 .start = OMAP24XX_DMA_MCBSP4_TX,
281 .flags = IORESOURCE_DMA,
282 },
161 }, 283 },
162 { 284 {
163 .phys_base = OMAP2430_MCBSP5_BASE, 285 {
164 .dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX, 286 .start = OMAP2430_MCBSP5_BASE,
165 .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX, 287 .end = OMAP2430_MCBSP5_BASE + SZ_256,
166 .rx_irq = INT_24XX_MCBSP5_IRQ_RX, 288 .flags = IORESOURCE_MEM,
167 .tx_irq = INT_24XX_MCBSP5_IRQ_TX, 289 },
290 {
291 .name = "rx",
292 .start = INT_24XX_MCBSP5_IRQ_RX,
293 .flags = IORESOURCE_IRQ,
294 },
295 {
296 .name = "tx",
297 .start = INT_24XX_MCBSP5_IRQ_TX,
298 .flags = IORESOURCE_IRQ,
299 },
300 {
301 .name = "rx",
302 .start = OMAP24XX_DMA_MCBSP5_RX,
303 .flags = IORESOURCE_DMA,
304 },
305 {
306 .name = "tx",
307 .start = OMAP24XX_DMA_MCBSP5_TX,
308 .flags = IORESOURCE_DMA,
309 },
168 }, 310 },
169}; 311};
170#define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata) 312#define OMAP2430_MCBSP_RES_SZ ARRAY_SIZE(omap2430_mcbsp_res[1])
171#define OMAP2430_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1) 313#define OMAP2430_MCBSP_COUNT ARRAY_SIZE(omap2430_mcbsp_res)
172#else 314#else
173#define omap2430_mcbsp_pdata NULL 315#define omap2430_mcbsp_res NULL
174#define OMAP2430_MCBSP_PDATA_SZ 0 316#define OMAP2430_MCBSP_RES_SZ 0
175#define OMAP2430_MCBSP_REG_NUM 0 317#define OMAP2430_MCBSP_COUNT 0
176#endif 318#endif
177 319
320#define omap2430_mcbsp_pdata NULL
321
178#ifdef CONFIG_ARCH_OMAP3 322#ifdef CONFIG_ARCH_OMAP3
323struct resource omap34xx_mcbsp_res[][7] = {
324 {
325 {
326 .start = OMAP34XX_MCBSP1_BASE,
327 .end = OMAP34XX_MCBSP1_BASE + SZ_256,
328 .flags = IORESOURCE_MEM,
329 },
330 {
331 .name = "rx",
332 .start = INT_24XX_MCBSP1_IRQ_RX,
333 .flags = IORESOURCE_IRQ,
334 },
335 {
336 .name = "tx",
337 .start = INT_24XX_MCBSP1_IRQ_TX,
338 .flags = IORESOURCE_IRQ,
339 },
340 {
341 .name = "rx",
342 .start = OMAP24XX_DMA_MCBSP1_RX,
343 .flags = IORESOURCE_DMA,
344 },
345 {
346 .name = "tx",
347 .start = OMAP24XX_DMA_MCBSP1_TX,
348 .flags = IORESOURCE_DMA,
349 },
350 },
351 {
352 {
353 .start = OMAP34XX_MCBSP2_BASE,
354 .end = OMAP34XX_MCBSP2_BASE + SZ_256,
355 .flags = IORESOURCE_MEM,
356 },
357 {
358 .name = "sidetone",
359 .start = OMAP34XX_MCBSP2_ST_BASE,
360 .end = OMAP34XX_MCBSP2_ST_BASE + SZ_256,
361 .flags = IORESOURCE_MEM,
362 },
363 {
364 .name = "rx",
365 .start = INT_24XX_MCBSP2_IRQ_RX,
366 .flags = IORESOURCE_IRQ,
367 },
368 {
369 .name = "tx",
370 .start = INT_24XX_MCBSP2_IRQ_TX,
371 .flags = IORESOURCE_IRQ,
372 },
373 {
374 .name = "rx",
375 .start = OMAP24XX_DMA_MCBSP2_RX,
376 .flags = IORESOURCE_DMA,
377 },
378 {
379 .name = "tx",
380 .start = OMAP24XX_DMA_MCBSP2_TX,
381 .flags = IORESOURCE_DMA,
382 },
383 },
384 {
385 {
386 .start = OMAP34XX_MCBSP3_BASE,
387 .end = OMAP34XX_MCBSP3_BASE + SZ_256,
388 .flags = IORESOURCE_MEM,
389 },
390 {
391 .name = "sidetone",
392 .start = OMAP34XX_MCBSP3_ST_BASE,
393 .end = OMAP34XX_MCBSP3_ST_BASE + SZ_256,
394 .flags = IORESOURCE_MEM,
395 },
396 {
397 .name = "rx",
398 .start = INT_24XX_MCBSP3_IRQ_RX,
399 .flags = IORESOURCE_IRQ,
400 },
401 {
402 .name = "tx",
403 .start = INT_24XX_MCBSP3_IRQ_TX,
404 .flags = IORESOURCE_IRQ,
405 },
406 {
407 .name = "rx",
408 .start = OMAP24XX_DMA_MCBSP3_RX,
409 .flags = IORESOURCE_DMA,
410 },
411 {
412 .name = "tx",
413 .start = OMAP24XX_DMA_MCBSP3_TX,
414 .flags = IORESOURCE_DMA,
415 },
416 },
417 {
418 {
419 .start = OMAP34XX_MCBSP4_BASE,
420 .end = OMAP34XX_MCBSP4_BASE + SZ_256,
421 .flags = IORESOURCE_MEM,
422 },
423 {
424 .name = "rx",
425 .start = INT_24XX_MCBSP4_IRQ_RX,
426 .flags = IORESOURCE_IRQ,
427 },
428 {
429 .name = "tx",
430 .start = INT_24XX_MCBSP4_IRQ_TX,
431 .flags = IORESOURCE_IRQ,
432 },
433 {
434 .name = "rx",
435 .start = OMAP24XX_DMA_MCBSP4_RX,
436 .flags = IORESOURCE_DMA,
437 },
438 {
439 .name = "tx",
440 .start = OMAP24XX_DMA_MCBSP4_TX,
441 .flags = IORESOURCE_DMA,
442 },
443 },
444 {
445 {
446 .start = OMAP34XX_MCBSP5_BASE,
447 .end = OMAP34XX_MCBSP5_BASE + SZ_256,
448 .flags = IORESOURCE_MEM,
449 },
450 {
451 .name = "rx",
452 .start = INT_24XX_MCBSP5_IRQ_RX,
453 .flags = IORESOURCE_IRQ,
454 },
455 {
456 .name = "tx",
457 .start = INT_24XX_MCBSP5_IRQ_TX,
458 .flags = IORESOURCE_IRQ,
459 },
460 {
461 .name = "rx",
462 .start = OMAP24XX_DMA_MCBSP5_RX,
463 .flags = IORESOURCE_DMA,
464 },
465 {
466 .name = "tx",
467 .start = OMAP24XX_DMA_MCBSP5_TX,
468 .flags = IORESOURCE_DMA,
469 },
470 },
471};
472
179static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { 473static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
180 { 474 {
181 .phys_base = OMAP34XX_MCBSP1_BASE,
182 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
183 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
184 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
185 .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
186 .buffer_size = 0x80, /* The FIFO has 128 locations */ 475 .buffer_size = 0x80, /* The FIFO has 128 locations */
187 }, 476 },
188 { 477 {
189 .phys_base = OMAP34XX_MCBSP2_BASE,
190 .phys_base_st = OMAP34XX_MCBSP2_ST_BASE,
191 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
192 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
193 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
194 .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
195 .buffer_size = 0x500, /* The FIFO has 1024 + 256 locations */ 478 .buffer_size = 0x500, /* The FIFO has 1024 + 256 locations */
196 }, 479 },
197 { 480 {
198 .phys_base = OMAP34XX_MCBSP3_BASE,
199 .phys_base_st = OMAP34XX_MCBSP3_ST_BASE,
200 .dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX,
201 .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX,
202 .rx_irq = INT_24XX_MCBSP3_IRQ_RX,
203 .tx_irq = INT_24XX_MCBSP3_IRQ_TX,
204 .buffer_size = 0x80, /* The FIFO has 128 locations */ 481 .buffer_size = 0x80, /* The FIFO has 128 locations */
205 }, 482 },
206 { 483 {
207 .phys_base = OMAP34XX_MCBSP4_BASE,
208 .dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX,
209 .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX,
210 .rx_irq = INT_24XX_MCBSP4_IRQ_RX,
211 .tx_irq = INT_24XX_MCBSP4_IRQ_TX,
212 .buffer_size = 0x80, /* The FIFO has 128 locations */ 484 .buffer_size = 0x80, /* The FIFO has 128 locations */
213 }, 485 },
214 { 486 {
215 .phys_base = OMAP34XX_MCBSP5_BASE,
216 .dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX,
217 .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX,
218 .rx_irq = INT_24XX_MCBSP5_IRQ_RX,
219 .tx_irq = INT_24XX_MCBSP5_IRQ_TX,
220 .buffer_size = 0x80, /* The FIFO has 128 locations */ 487 .buffer_size = 0x80, /* The FIFO has 128 locations */
221 }, 488 },
222}; 489};
223#define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata) 490#define OMAP34XX_MCBSP_RES_SZ ARRAY_SIZE(omap34xx_mcbsp_res[1])
224#define OMAP34XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1) 491#define OMAP34XX_MCBSP_COUNT ARRAY_SIZE(omap34xx_mcbsp_res)
225#else 492#else
226#define omap34xx_mcbsp_pdata NULL 493#define omap34xx_mcbsp_pdata NULL
227#define OMAP34XX_MCBSP_PDATA_SZ 0 494#define omap34XX_mcbsp_res NULL
228#define OMAP34XX_MCBSP_REG_NUM 0 495#define OMAP34XX_MCBSP_RES_SZ 0
496#define OMAP34XX_MCBSP_COUNT 0
229#endif 497#endif
230 498
231static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = { 499struct resource omap44xx_mcbsp_res[][6] = {
232 { 500 {
233 .phys_base = OMAP44XX_MCBSP1_BASE, 501 {
234 .dma_rx_sync = OMAP44XX_DMA_MCBSP1_RX, 502 .name = "mpu",
235 .dma_tx_sync = OMAP44XX_DMA_MCBSP1_TX, 503 .start = OMAP44XX_MCBSP1_BASE,
236 .tx_irq = OMAP44XX_IRQ_MCBSP1, 504 .end = OMAP44XX_MCBSP1_BASE + SZ_256,
505 .flags = IORESOURCE_MEM,
506 },
507 {
508 .name = "dma",
509 .start = OMAP44XX_MCBSP1_DMA_BASE,
510 .end = OMAP44XX_MCBSP1_DMA_BASE + SZ_256,
511 .flags = IORESOURCE_MEM,
512 },
513 {
514 .name = "rx",
515 .start = 0,
516 .flags = IORESOURCE_IRQ,
517 },
518 {
519 .name = "tx",
520 .start = OMAP44XX_IRQ_MCBSP1,
521 .flags = IORESOURCE_IRQ,
522 },
523 {
524 .name = "rx",
525 .start = OMAP44XX_DMA_MCBSP1_RX,
526 .flags = IORESOURCE_DMA,
527 },
528 {
529 .name = "tx",
530 .start = OMAP44XX_DMA_MCBSP1_TX,
531 .flags = IORESOURCE_DMA,
532 },
237 }, 533 },
238 { 534 {
239 .phys_base = OMAP44XX_MCBSP2_BASE, 535 {
240 .dma_rx_sync = OMAP44XX_DMA_MCBSP2_RX, 536 .name = "mpu",
241 .dma_tx_sync = OMAP44XX_DMA_MCBSP2_TX, 537 .start = OMAP44XX_MCBSP2_BASE,
242 .tx_irq = OMAP44XX_IRQ_MCBSP2, 538 .end = OMAP44XX_MCBSP2_BASE + SZ_256,
539 .flags = IORESOURCE_MEM,
540 },
541 {
542 .name = "dma",
543 .start = OMAP44XX_MCBSP2_DMA_BASE,
544 .end = OMAP44XX_MCBSP2_DMA_BASE + SZ_256,
545 .flags = IORESOURCE_MEM,
546 },
547 {
548 .name = "rx",
549 .start = 0,
550 .flags = IORESOURCE_IRQ,
551 },
552 {
553 .name = "tx",
554 .start = OMAP44XX_IRQ_MCBSP2,
555 .flags = IORESOURCE_IRQ,
556 },
557 {
558 .name = "rx",
559 .start = OMAP44XX_DMA_MCBSP2_RX,
560 .flags = IORESOURCE_DMA,
561 },
562 {
563 .name = "tx",
564 .start = OMAP44XX_DMA_MCBSP2_TX,
565 .flags = IORESOURCE_DMA,
566 },
243 }, 567 },
244 { 568 {
245 .phys_base = OMAP44XX_MCBSP3_BASE, 569 {
246 .dma_rx_sync = OMAP44XX_DMA_MCBSP3_RX, 570 .name = "mpu",
247 .dma_tx_sync = OMAP44XX_DMA_MCBSP3_TX, 571 .start = OMAP44XX_MCBSP3_BASE,
248 .tx_irq = OMAP44XX_IRQ_MCBSP3, 572 .end = OMAP44XX_MCBSP3_BASE + SZ_256,
573 .flags = IORESOURCE_MEM,
574 },
575 {
576 .name = "dma",
577 .start = OMAP44XX_MCBSP3_DMA_BASE,
578 .end = OMAP44XX_MCBSP3_DMA_BASE + SZ_256,
579 .flags = IORESOURCE_MEM,
580 },
581 {
582 .name = "rx",
583 .start = 0,
584 .flags = IORESOURCE_IRQ,
585 },
586 {
587 .name = "tx",
588 .start = OMAP44XX_IRQ_MCBSP3,
589 .flags = IORESOURCE_IRQ,
590 },
591 {
592 .name = "rx",
593 .start = OMAP44XX_DMA_MCBSP3_RX,
594 .flags = IORESOURCE_DMA,
595 },
596 {
597 .name = "tx",
598 .start = OMAP44XX_DMA_MCBSP3_TX,
599 .flags = IORESOURCE_DMA,
600 },
249 }, 601 },
250 { 602 {
251 .phys_base = OMAP44XX_MCBSP4_BASE, 603 {
252 .dma_rx_sync = OMAP44XX_DMA_MCBSP4_RX, 604 .start = OMAP44XX_MCBSP4_BASE,
253 .dma_tx_sync = OMAP44XX_DMA_MCBSP4_TX, 605 .end = OMAP44XX_MCBSP4_BASE + SZ_256,
254 .tx_irq = OMAP44XX_IRQ_MCBSP4, 606 .flags = IORESOURCE_MEM,
607 },
608 {
609 .name = "rx",
610 .start = 0,
611 .flags = IORESOURCE_IRQ,
612 },
613 {
614 .name = "tx",
615 .start = OMAP44XX_IRQ_MCBSP4,
616 .flags = IORESOURCE_IRQ,
617 },
618 {
619 .name = "rx",
620 .start = OMAP44XX_DMA_MCBSP4_RX,
621 .flags = IORESOURCE_DMA,
622 },
623 {
624 .name = "tx",
625 .start = OMAP44XX_DMA_MCBSP4_TX,
626 .flags = IORESOURCE_DMA,
627 },
255 }, 628 },
256}; 629};
257#define OMAP44XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap44xx_mcbsp_pdata) 630#define omap44xx_mcbsp_pdata NULL
258#define OMAP44XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1) 631#define OMAP44XX_MCBSP_RES_SZ ARRAY_SIZE(omap44xx_mcbsp_res[1])
632#define OMAP44XX_MCBSP_COUNT ARRAY_SIZE(omap44xx_mcbsp_res)
259 633
260static int __init omap2_mcbsp_init(void) 634static int __init omap2_mcbsp_init(void)
261{ 635{
262 if (cpu_is_omap2420()) { 636 if (cpu_is_omap2420())
263 omap_mcbsp_count = OMAP2420_MCBSP_PDATA_SZ; 637 omap_mcbsp_count = OMAP2420_MCBSP_COUNT;
264 omap_mcbsp_cache_size = OMAP2420_MCBSP_REG_NUM * sizeof(u16); 638 else if (cpu_is_omap2430())
265 } else if (cpu_is_omap2430()) { 639 omap_mcbsp_count = OMAP2430_MCBSP_COUNT;
266 omap_mcbsp_count = OMAP2430_MCBSP_PDATA_SZ; 640 else if (cpu_is_omap34xx())
267 omap_mcbsp_cache_size = OMAP2430_MCBSP_REG_NUM * sizeof(u32); 641 omap_mcbsp_count = OMAP34XX_MCBSP_COUNT;
268 } else if (cpu_is_omap34xx()) { 642 else if (cpu_is_omap44xx())
269 omap_mcbsp_count = OMAP34XX_MCBSP_PDATA_SZ; 643 omap_mcbsp_count = OMAP44XX_MCBSP_COUNT;
270 omap_mcbsp_cache_size = OMAP34XX_MCBSP_REG_NUM * sizeof(u32);
271 } else if (cpu_is_omap44xx()) {
272 omap_mcbsp_count = OMAP44XX_MCBSP_PDATA_SZ;
273 omap_mcbsp_cache_size = OMAP44XX_MCBSP_REG_NUM * sizeof(u32);
274 }
275 644
276 mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *), 645 mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
277 GFP_KERNEL); 646 GFP_KERNEL);
@@ -279,17 +648,25 @@ static int __init omap2_mcbsp_init(void)
279 return -ENOMEM; 648 return -ENOMEM;
280 649
281 if (cpu_is_omap2420()) 650 if (cpu_is_omap2420())
282 omap_mcbsp_register_board_cfg(omap2420_mcbsp_pdata, 651 omap_mcbsp_register_board_cfg(omap2420_mcbsp_res[0],
283 OMAP2420_MCBSP_PDATA_SZ); 652 OMAP2420_MCBSP_RES_SZ,
653 omap2420_mcbsp_pdata,
654 OMAP2420_MCBSP_COUNT);
284 if (cpu_is_omap2430()) 655 if (cpu_is_omap2430())
285 omap_mcbsp_register_board_cfg(omap2430_mcbsp_pdata, 656 omap_mcbsp_register_board_cfg(omap2430_mcbsp_res[0],
286 OMAP2430_MCBSP_PDATA_SZ); 657 OMAP2420_MCBSP_RES_SZ,
658 omap2430_mcbsp_pdata,
659 OMAP2430_MCBSP_COUNT);
287 if (cpu_is_omap34xx()) 660 if (cpu_is_omap34xx())
288 omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata, 661 omap_mcbsp_register_board_cfg(omap34xx_mcbsp_res[0],
289 OMAP34XX_MCBSP_PDATA_SZ); 662 OMAP34XX_MCBSP_RES_SZ,
663 omap34xx_mcbsp_pdata,
664 OMAP34XX_MCBSP_COUNT);
290 if (cpu_is_omap44xx()) 665 if (cpu_is_omap44xx())
291 omap_mcbsp_register_board_cfg(omap44xx_mcbsp_pdata, 666 omap_mcbsp_register_board_cfg(omap44xx_mcbsp_res[0],
292 OMAP44XX_MCBSP_PDATA_SZ); 667 OMAP44XX_MCBSP_RES_SZ,
668 omap44xx_mcbsp_pdata,
669 OMAP44XX_MCBSP_COUNT);
293 670
294 return omap_mcbsp_init(); 671 return omap_mcbsp_init();
295} 672}
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index 10245b837c10..7d9f815cedec 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -35,8 +35,8 @@
35 35
36static struct platform_device **omap_mcbsp_devices; 36static struct platform_device **omap_mcbsp_devices;
37 37
38void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, 38void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
39 int size) 39 struct omap_mcbsp_platform_data *config, int size)
40{ 40{
41 int i; 41 int i;
42 42
@@ -54,6 +54,8 @@ void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
54 new_mcbsp = platform_device_alloc("omap-mcbsp", i + 1); 54 new_mcbsp = platform_device_alloc("omap-mcbsp", i + 1);
55 if (!new_mcbsp) 55 if (!new_mcbsp)
56 continue; 56 continue;
57 platform_device_add_resources(new_mcbsp, &res[i * res_count],
58 res_count);
57 new_mcbsp->dev.platform_data = &config[i]; 59 new_mcbsp->dev.platform_data = &config[i];
58 ret = platform_device_add(new_mcbsp); 60 ret = platform_device_add(new_mcbsp);
59 if (ret) { 61 if (ret) {
@@ -65,8 +67,8 @@ void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
65} 67}
66 68
67#else 69#else
68void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, 70void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
69 int size) 71 struct omap_mcbsp_platform_data *config, int size)
70{ } 72{ }
71#endif 73#endif
72 74
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index 6ecf1051e5f4..dc1a28299ae2 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -63,9 +63,12 @@ static struct platform_device omap_mcbsp##port_nr = { \
63#define OMAP34XX_MCBSP4_BASE 0x49026000 63#define OMAP34XX_MCBSP4_BASE 0x49026000
64#define OMAP34XX_MCBSP5_BASE 0x48096000 64#define OMAP34XX_MCBSP5_BASE 0x48096000
65 65
66#define OMAP44XX_MCBSP1_BASE 0x49022000 66#define OMAP44XX_MCBSP1_BASE 0x40122000
67#define OMAP44XX_MCBSP2_BASE 0x49024000 67#define OMAP44XX_MCBSP1_DMA_BASE 0x49022000
68#define OMAP44XX_MCBSP3_BASE 0x49026000 68#define OMAP44XX_MCBSP2_BASE 0x40124000
69#define OMAP44XX_MCBSP2_DMA_BASE 0x49024000
70#define OMAP44XX_MCBSP3_BASE 0x40126000
71#define OMAP44XX_MCBSP3_DMA_BASE 0x49026000
69#define OMAP44XX_MCBSP4_BASE 0x48096000 72#define OMAP44XX_MCBSP4_BASE 0x48096000
70 73
71#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) 74#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
@@ -431,6 +434,7 @@ struct omap_mcbsp_st_data {
431struct omap_mcbsp { 434struct omap_mcbsp {
432 struct device *dev; 435 struct device *dev;
433 unsigned long phys_base; 436 unsigned long phys_base;
437 unsigned long phys_dma_base;
434 void __iomem *io_base; 438 void __iomem *io_base;
435 u8 id; 439 u8 id;
436 u8 free; 440 u8 free;
@@ -474,8 +478,8 @@ extern int omap_mcbsp_count, omap_mcbsp_cache_size;
474#define id_to_mcbsp_ptr(id) mcbsp_ptr[id]; 478#define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
475 479
476int omap_mcbsp_init(void); 480int omap_mcbsp_init(void);
477void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, 481void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
478 int size); 482 struct omap_mcbsp_platform_data *config, int size);
479void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config); 483void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
480#ifdef CONFIG_ARCH_OMAP3 484#ifdef CONFIG_ARCH_OMAP3
481void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold); 485void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index b5a6e178a7f9..5f25ae5f9c1d 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -1649,7 +1649,8 @@ static const struct attribute_group sidetone_attr_group = {
1649 1649
1650static int __devinit omap_st_add(struct omap_mcbsp *mcbsp) 1650static int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
1651{ 1651{
1652 struct omap_mcbsp_platform_data *pdata = mcbsp->pdata; 1652 struct platform_device *pdev;
1653 struct resource *res;
1653 struct omap_mcbsp_st_data *st_data; 1654 struct omap_mcbsp_st_data *st_data;
1654 int err; 1655 int err;
1655 1656
@@ -1659,7 +1660,10 @@ static int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
1659 goto err1; 1660 goto err1;
1660 } 1661 }
1661 1662
1662 st_data->io_base_st = ioremap(pdata->phys_base_st, SZ_4K); 1663 pdev = container_of(mcbsp->dev, struct platform_device, dev);
1664
1665 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
1666 st_data->io_base_st = ioremap(res->start, resource_size(res));
1663 if (!st_data->io_base_st) { 1667 if (!st_data->io_base_st) {
1664 err = -ENOMEM; 1668 err = -ENOMEM;
1665 goto err2; 1669 goto err2;
@@ -1748,6 +1752,7 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1748 struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data; 1752 struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
1749 struct omap_mcbsp *mcbsp; 1753 struct omap_mcbsp *mcbsp;
1750 int id = pdev->id - 1; 1754 int id = pdev->id - 1;
1755 struct resource *res;
1751 int ret = 0; 1756 int ret = 0;
1752 1757
1753 if (!pdata) { 1758 if (!pdata) {
@@ -1777,25 +1782,59 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1777 mcbsp->dma_tx_lch = -1; 1782 mcbsp->dma_tx_lch = -1;
1778 mcbsp->dma_rx_lch = -1; 1783 mcbsp->dma_rx_lch = -1;
1779 1784
1780 mcbsp->phys_base = pdata->phys_base; 1785 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1781 mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K); 1786 if (!res) {
1787 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1788 if (!res) {
1789 dev_err(&pdev->dev, "%s:mcbsp%d has invalid memory"
1790 "resource\n", __func__, pdev->id);
1791 ret = -ENOMEM;
1792 goto exit;
1793 }
1794 }
1795 mcbsp->phys_base = res->start;
1796 omap_mcbsp_cache_size = resource_size(res);
1797 mcbsp->io_base = ioremap(res->start, resource_size(res));
1782 if (!mcbsp->io_base) { 1798 if (!mcbsp->io_base) {
1783 ret = -ENOMEM; 1799 ret = -ENOMEM;
1784 goto err_ioremap; 1800 goto err_ioremap;
1785 } 1801 }
1786 1802
1803 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
1804 if (!res)
1805 mcbsp->phys_dma_base = mcbsp->phys_base;
1806 else
1807 mcbsp->phys_dma_base = res->start;
1808
1787 /* Default I/O is IRQ based */ 1809 /* Default I/O is IRQ based */
1788 mcbsp->io_type = OMAP_MCBSP_IRQ_IO; 1810 mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
1789 mcbsp->tx_irq = pdata->tx_irq; 1811
1790 mcbsp->rx_irq = pdata->rx_irq; 1812 mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
1791 mcbsp->dma_rx_sync = pdata->dma_rx_sync; 1813 mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
1792 mcbsp->dma_tx_sync = pdata->dma_tx_sync; 1814
1815 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1816 if (!res) {
1817 dev_err(&pdev->dev, "%s:mcbsp%d has invalid rx DMA channel\n",
1818 __func__, pdev->id);
1819 ret = -ENODEV;
1820 goto err_res;
1821 }
1822 mcbsp->dma_rx_sync = res->start;
1823
1824 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1825 if (!res) {
1826 dev_err(&pdev->dev, "%s:mcbsp%d has invalid tx DMA channel\n",
1827 __func__, pdev->id);
1828 ret = -ENODEV;
1829 goto err_res;
1830 }
1831 mcbsp->dma_tx_sync = res->start;
1793 1832
1794 mcbsp->iclk = clk_get(&pdev->dev, "ick"); 1833 mcbsp->iclk = clk_get(&pdev->dev, "ick");
1795 if (IS_ERR(mcbsp->iclk)) { 1834 if (IS_ERR(mcbsp->iclk)) {
1796 ret = PTR_ERR(mcbsp->iclk); 1835 ret = PTR_ERR(mcbsp->iclk);
1797 dev_err(&pdev->dev, "unable to get ick: %d\n", ret); 1836 dev_err(&pdev->dev, "unable to get ick: %d\n", ret);
1798 goto err_iclk; 1837 goto err_res;
1799 } 1838 }
1800 1839
1801 mcbsp->fclk = clk_get(&pdev->dev, "fck"); 1840 mcbsp->fclk = clk_get(&pdev->dev, "fck");
@@ -1817,7 +1856,7 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1817 1856
1818err_fclk: 1857err_fclk:
1819 clk_put(mcbsp->iclk); 1858 clk_put(mcbsp->iclk);
1820err_iclk: 1859err_res:
1821 iounmap(mcbsp->io_base); 1860 iounmap(mcbsp->io_base);
1822err_ioremap: 1861err_ioremap:
1823 kfree(mcbsp); 1862 kfree(mcbsp);
generated by cgit v1.2.2 (git 2.25.0) at 2026-03-03 07:08:47 -0500