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authorPaul Walmsley <paul@pwsan.com>2013-01-26 02:48:54 -0500
committerPaul Walmsley <paul@pwsan.com>2013-01-26 02:48:54 -0500
commit17b7e7d33530e2bbd3bdc90f4db09b91cfdde2bb (patch)
tree4377cb69183835d0ad1a36469bcbce68449ce5d1 /arch/arm/mach-omap2/cclock44xx_data.c
parentc1d1cd597fc77af3086470f8627d77f52f7f8b6c (diff)
ARM: OMAP4: clock/hwmod data: start to remove some IP block control "clocks"
Remove some leaf "clocks" that are actually IP block idle control points, since these should now be handled by the hwmod code. There are still a few types of MODULEMODE clocks that need to be cleaned up: - those still in use by driver or integration code - those in DEFINE_CLK_OMAP_MUX_GATE() blocks; the gate portion of these should be removed A similar process may also be possible on OMAP2/3. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoît Cousson <b-cousson@ti.com> Cc: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'arch/arm/mach-omap2/cclock44xx_data.c')
-rw-r--r--arch/arm/mach-omap2/cclock44xx_data.c291
1 files changed, 5 insertions, 286 deletions
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
index a2cc046b47f4..4c3f5a32694c 100644
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ b/arch/arm/mach-omap2/cclock44xx_data.c
@@ -16,6 +16,11 @@
16 * XXX Some of the ES1 clocks have been removed/changed; once support 16 * XXX Some of the ES1 clocks have been removed/changed; once support
17 * is added for discriminating clocks by ES level, these should be added back 17 * is added for discriminating clocks by ES level, these should be added back
18 * in. 18 * in.
19 *
20 * XXX All of the CLK_OMAP_MUX_GATE entries with MODULEMODE registers should
21 * be split into separate mux and gate nodes, then the gates should be removed
22 * (handled by hwmod). Also all of the other remaining MODULEMODE entries
23 * should be removed once the drivers are updated to use pm_runtime.
19 */ 24 */
20 25
21#include <linux/kernel.h> 26#include <linux/kernel.h>
@@ -749,10 +754,6 @@ DEFINE_CLK_GATE(aes2_fck, "l3_div_ck", &l3_div_ck, 0x0,
749 OMAP4430_CM_L4SEC_AES2_CLKCTRL, 754 OMAP4430_CM_L4SEC_AES2_CLKCTRL,
750 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); 755 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
751 756
752DEFINE_CLK_GATE(aess_fck, "aess_fclk", &aess_fclk, 0x0,
753 OMAP4430_CM1_ABE_AESS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
754 0x0, NULL);
755
756DEFINE_CLK_GATE(bandgap_fclk, "sys_32k_ck", &sys_32k_ck, 0x0, 757DEFINE_CLK_GATE(bandgap_fclk, "sys_32k_ck", &sys_32k_ck, 0x0,
757 OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, 758 OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
758 OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, 0x0, NULL); 759 OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, 0x0, NULL);
@@ -774,11 +775,6 @@ DEFINE_CLK_GATE(bandgap_ts_fclk, "div_ts_ck", &div_ts_ck, 0x0,
774 OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT, 775 OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
775 0x0, NULL); 776 0x0, NULL);
776 777
777DEFINE_CLK_GATE(des3des_fck, "l4_div_ck", &l4_div_ck, 0x0,
778 OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
779 OMAP4430_MODULEMODE_SWCTRL_SHIFT,
780 0x0, NULL);
781
782static const char *dmic_sync_mux_ck_parents[] = { 778static const char *dmic_sync_mux_ck_parents[] = {
783 "abe_24m_fclk", "syc_clk_div_ck", "func_24m_clk", 779 "abe_24m_fclk", "syc_clk_div_ck", "func_24m_clk",
784}; 780};
@@ -809,10 +805,6 @@ DEFINE_CLK_OMAP_MUX_GATE(dmic_fck, "abe_clkdm", func_dmic_abe_gfclk_sel,
809 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, 805 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
810 dmic_fck_parents, dmic_fck_ops); 806 dmic_fck_parents, dmic_fck_ops);
811 807
812DEFINE_CLK_GATE(dsp_fck, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, 0x0,
813 OMAP4430_CM_TESLA_TESLA_CLKCTRL,
814 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
815
816DEFINE_CLK_GATE(dss_sys_clk, "syc_clk_div_ck", &syc_clk_div_ck, 0x0, 808DEFINE_CLK_GATE(dss_sys_clk, "syc_clk_div_ck", &syc_clk_div_ck, 0x0,
817 OMAP4430_CM_DSS_DSS_CLKCTRL, 809 OMAP4430_CM_DSS_DSS_CLKCTRL,
818 OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, 0x0, NULL); 810 OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, 0x0, NULL);
@@ -833,78 +825,34 @@ DEFINE_CLK_GATE(dss_fck, "l3_div_ck", &l3_div_ck, 0x0,
833 OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, 825 OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
834 0x0, NULL); 826 0x0, NULL);
835 827
836DEFINE_CLK_GATE(efuse_ctrl_cust_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
837 OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
838 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
839
840DEFINE_CLK_GATE(emif1_fck, "ddrphy_ck", &ddrphy_ck, 0x0,
841 OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
842 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
843
844DEFINE_CLK_GATE(emif2_fck, "ddrphy_ck", &ddrphy_ck, 0x0,
845 OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
846 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
847
848DEFINE_CLK_DIVIDER(fdif_fck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0, 828DEFINE_CLK_DIVIDER(fdif_fck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
849 OMAP4430_CM_CAM_FDIF_CLKCTRL, OMAP4430_CLKSEL_FCLK_SHIFT, 829 OMAP4430_CM_CAM_FDIF_CLKCTRL, OMAP4430_CLKSEL_FCLK_SHIFT,
850 OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); 830 OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
851 831
852DEFINE_CLK_GATE(fpka_fck, "l4_div_ck", &l4_div_ck, 0x0,
853 OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
854 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
855
856DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, 832DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
857 OMAP4430_CM_WKUP_GPIO1_CLKCTRL, 833 OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
858 OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL); 834 OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
859 835
860DEFINE_CLK_GATE(gpio1_ick, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, 0x0,
861 OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
862 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
863
864DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, 836DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
865 OMAP4430_CM_L4PER_GPIO2_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 837 OMAP4430_CM_L4PER_GPIO2_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
866 0x0, NULL); 838 0x0, NULL);
867 839
868DEFINE_CLK_GATE(gpio2_ick, "l4_div_ck", &l4_div_ck, 0x0,
869 OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
870 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
871
872DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, 840DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
873 OMAP4430_CM_L4PER_GPIO3_CLKCTRL, 841 OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
874 OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL); 842 OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
875 843
876DEFINE_CLK_GATE(gpio3_ick, "l4_div_ck", &l4_div_ck, 0x0,
877 OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
878 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
879
880DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, 844DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
881 OMAP4430_CM_L4PER_GPIO4_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 845 OMAP4430_CM_L4PER_GPIO4_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
882 0x0, NULL); 846 0x0, NULL);
883 847
884DEFINE_CLK_GATE(gpio4_ick, "l4_div_ck", &l4_div_ck, 0x0,
885 OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
886 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
887
888DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, 848DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
889 OMAP4430_CM_L4PER_GPIO5_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 849 OMAP4430_CM_L4PER_GPIO5_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
890 0x0, NULL); 850 0x0, NULL);
891 851
892DEFINE_CLK_GATE(gpio5_ick, "l4_div_ck", &l4_div_ck, 0x0,
893 OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
894 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
895
896DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, 852DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
897 OMAP4430_CM_L4PER_GPIO6_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 853 OMAP4430_CM_L4PER_GPIO6_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
898 0x0, NULL); 854 0x0, NULL);
899 855
900DEFINE_CLK_GATE(gpio6_ick, "l4_div_ck", &l4_div_ck, 0x0,
901 OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
902 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
903
904DEFINE_CLK_GATE(gpmc_ick, "l3_div_ck", &l3_div_ck, 0x0,
905 OMAP4430_CM_L3_2_GPMC_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
906 0x0, NULL);
907
908static const struct clksel sgx_clk_mux_sel[] = { 856static const struct clksel sgx_clk_mux_sel[] = {
909 { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates }, 857 { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
910 { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates }, 858 { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
@@ -923,87 +871,15 @@ DEFINE_CLK_OMAP_MUX_GATE(gpu_fck, "l3_gfx_clkdm", sgx_clk_mux_sel,
923 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, 871 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
924 gpu_fck_parents, dmic_fck_ops); 872 gpu_fck_parents, dmic_fck_ops);
925 873
926DEFINE_CLK_GATE(hdq1w_fck, "func_12m_fclk", &func_12m_fclk, 0x0,
927 OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
928 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
929
930DEFINE_CLK_DIVIDER(hsi_fck, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0, 874DEFINE_CLK_DIVIDER(hsi_fck, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0,
931 OMAP4430_CM_L3INIT_HSI_CLKCTRL, OMAP4430_CLKSEL_24_25_SHIFT, 875 OMAP4430_CM_L3INIT_HSI_CLKCTRL, OMAP4430_CLKSEL_24_25_SHIFT,
932 OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_POWER_OF_TWO, 876 OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
933 NULL); 877 NULL);
934 878
935DEFINE_CLK_GATE(i2c1_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
936 OMAP4430_CM_L4PER_I2C1_CLKCTRL,
937 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
938
939DEFINE_CLK_GATE(i2c2_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
940 OMAP4430_CM_L4PER_I2C2_CLKCTRL,
941 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
942
943DEFINE_CLK_GATE(i2c3_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
944 OMAP4430_CM_L4PER_I2C3_CLKCTRL,
945 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
946
947DEFINE_CLK_GATE(i2c4_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
948 OMAP4430_CM_L4PER_I2C4_CLKCTRL,
949 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
950
951DEFINE_CLK_GATE(ipu_fck, "ducati_clk_mux_ck", &ducati_clk_mux_ck, 0x0,
952 OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
953 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
954
955DEFINE_CLK_GATE(iss_ctrlclk, "func_96m_fclk", &func_96m_fclk, 0x0, 879DEFINE_CLK_GATE(iss_ctrlclk, "func_96m_fclk", &func_96m_fclk, 0x0,
956 OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT, 880 OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
957 0x0, NULL); 881 0x0, NULL);
958 882
959DEFINE_CLK_GATE(iss_fck, "ducati_clk_mux_ck", &ducati_clk_mux_ck, 0x0,
960 OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
961 0x0, NULL);
962
963DEFINE_CLK_GATE(iva_fck, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, 0x0,
964 OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
965 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
966
967DEFINE_CLK_GATE(kbd_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
968 OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
969 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
970
971static struct clk l3_instr_ick;
972
973static const char *l3_instr_ick_parent_names[] = {
974 "l3_div_ck",
975};
976
977static const struct clk_ops l3_instr_ick_ops = {
978 .enable = &omap2_dflt_clk_enable,
979 .disable = &omap2_dflt_clk_disable,
980 .is_enabled = &omap2_dflt_clk_is_enabled,
981 .init = &omap2_init_clk_clkdm,
982};
983
984static struct clk_hw_omap l3_instr_ick_hw = {
985 .hw = {
986 .clk = &l3_instr_ick,
987 },
988 .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
989 .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
990 .clkdm_name = "l3_instr_clkdm",
991};
992
993DEFINE_STRUCT_CLK(l3_instr_ick, l3_instr_ick_parent_names, l3_instr_ick_ops);
994
995static struct clk l3_main_3_ick;
996static struct clk_hw_omap l3_main_3_ick_hw = {
997 .hw = {
998 .clk = &l3_main_3_ick,
999 },
1000 .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
1001 .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
1002 .clkdm_name = "l3_instr_clkdm",
1003};
1004
1005DEFINE_STRUCT_CLK(l3_main_3_ick, l3_instr_ick_parent_names, l3_instr_ick_ops);
1006
1007DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, 883DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
1008 OMAP4430_CM1_ABE_MCASP_CLKCTRL, 884 OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1009 OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, 885 OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
@@ -1127,26 +1003,6 @@ DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "l4_per_clkdm", per_mcbsp4_gfclk_sel,
1127 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, 1003 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1128 mcbsp4_fck_parents, dmic_fck_ops); 1004 mcbsp4_fck_parents, dmic_fck_ops);
1129 1005
1130DEFINE_CLK_GATE(mcpdm_fck, "pad_clks_ck", &pad_clks_ck, 0x0,
1131 OMAP4430_CM1_ABE_PDM_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
1132 0x0, NULL);
1133
1134DEFINE_CLK_GATE(mcspi1_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1135 OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
1136 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1137
1138DEFINE_CLK_GATE(mcspi2_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1139 OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
1140 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1141
1142DEFINE_CLK_GATE(mcspi3_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1143 OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
1144 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1145
1146DEFINE_CLK_GATE(mcspi4_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1147 OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
1148 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1149
1150static const struct clksel hsmmc1_fclk_sel[] = { 1006static const struct clksel hsmmc1_fclk_sel[] = {
1151 { .parent = &func_64m_fclk, .rates = div_1_0_rates }, 1007 { .parent = &func_64m_fclk, .rates = div_1_0_rates },
1152 { .parent = &func_96m_fclk, .rates = div_1_1_rates }, 1008 { .parent = &func_96m_fclk, .rates = div_1_1_rates },
@@ -1171,51 +1027,10 @@ DEFINE_CLK_OMAP_MUX_GATE(mmc2_fck, "l3_init_clkdm", hsmmc1_fclk_sel,
1171 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, 1027 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1172 mmc1_fck_parents, dmic_fck_ops); 1028 mmc1_fck_parents, dmic_fck_ops);
1173 1029
1174DEFINE_CLK_GATE(mmc3_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1175 OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
1176 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1177
1178DEFINE_CLK_GATE(mmc4_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1179 OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
1180 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1181
1182DEFINE_CLK_GATE(mmc5_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1183 OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
1184 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1185
1186DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0,
1187 OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
1188 OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL);
1189
1190DEFINE_CLK_GATE(ocp2scp_usb_phy_ick, "l4_div_ck", &l4_div_ck, 0x0,
1191 OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
1192 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
1193
1194static struct clk ocp_wp_noc_ick;
1195
1196static struct clk_hw_omap ocp_wp_noc_ick_hw = {
1197 .hw = {
1198 .clk = &ocp_wp_noc_ick,
1199 },
1200 .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
1201 .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
1202 .clkdm_name = "l3_instr_clkdm",
1203};
1204
1205DEFINE_STRUCT_CLK(ocp_wp_noc_ick, l3_instr_ick_parent_names, l3_instr_ick_ops);
1206
1207DEFINE_CLK_GATE(rng_ick, "l4_div_ck", &l4_div_ck, 0x0,
1208 OMAP4430_CM_L4SEC_RNG_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
1209 0x0, NULL);
1210
1211DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0, 1030DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0,
1212 OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, 1031 OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
1213 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); 1032 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1214 1033
1215DEFINE_CLK_GATE(sl2if_ick, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, 0x0,
1216 OMAP4430_CM_IVAHD_SL2_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
1217 0x0, NULL);
1218
1219DEFINE_CLK_GATE(slimbus1_fclk_1, "func_24m_clk", &func_24m_clk, 0x0, 1034DEFINE_CLK_GATE(slimbus1_fclk_1, "func_24m_clk", &func_24m_clk, 0x0,
1220 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, 1035 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1221 OMAP4430_OPTFCLKEN_FCLK1_SHIFT, 0x0, NULL); 1036 OMAP4430_OPTFCLKEN_FCLK1_SHIFT, 0x0, NULL);
@@ -1232,10 +1047,6 @@ DEFINE_CLK_GATE(slimbus1_slimbus_clk, "slimbus_clk", &slimbus_clk, 0x0,
1232 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, 1047 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1233 OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, 0x0, NULL); 1048 OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, 0x0, NULL);
1234 1049
1235DEFINE_CLK_GATE(slimbus1_fck, "ocp_abe_iclk", &ocp_abe_iclk, 0x0,
1236 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1237 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1238
1239DEFINE_CLK_GATE(slimbus2_fclk_1, "per_abe_24m_fclk", &per_abe_24m_fclk, 0x0, 1050DEFINE_CLK_GATE(slimbus2_fclk_1, "per_abe_24m_fclk", &per_abe_24m_fclk, 0x0,
1240 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, 1051 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
1241 OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, 0x0, NULL); 1052 OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, 0x0, NULL);
@@ -1249,10 +1060,6 @@ DEFINE_CLK_GATE(slimbus2_slimbus_clk, "pad_slimbus_core_clks_ck",
1249 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, 1060 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
1250 OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 0x0, NULL); 1061 OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 0x0, NULL);
1251 1062
1252DEFINE_CLK_GATE(slimbus2_fck, "l4_div_ck", &l4_div_ck, 0x0,
1253 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
1254 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1255
1256DEFINE_CLK_GATE(smartreflex_core_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, 1063DEFINE_CLK_GATE(smartreflex_core_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
1257 0x0, OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, 1064 0x0, OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
1258 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); 1065 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
@@ -1364,22 +1171,6 @@ DEFINE_CLK_OMAP_MUX_GATE(timer9_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
1364 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, 1171 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1365 abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); 1172 abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
1366 1173
1367DEFINE_CLK_GATE(uart1_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1368 OMAP4430_CM_L4PER_UART1_CLKCTRL,
1369 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1370
1371DEFINE_CLK_GATE(uart2_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1372 OMAP4430_CM_L4PER_UART2_CLKCTRL,
1373 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1374
1375DEFINE_CLK_GATE(uart3_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1376 OMAP4430_CM_L4PER_UART3_CLKCTRL,
1377 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1378
1379DEFINE_CLK_GATE(uart4_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1380 OMAP4430_CM_L4PER_UART4_CLKCTRL,
1381 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1382
1383static struct clk usb_host_fs_fck; 1174static struct clk usb_host_fs_fck;
1384 1175
1385static const char *usb_host_fs_fck_parent_names[] = { 1176static const char *usb_host_fs_fck_parent_names[] = {
@@ -1512,18 +1303,6 @@ DEFINE_CLK_GATE(usim_fclk, "usim_ck", &usim_ck, 0x0,
1512 OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK_SHIFT, 1303 OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK_SHIFT,
1513 0x0, NULL); 1304 0x0, NULL);
1514 1305
1515DEFINE_CLK_GATE(usim_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
1516 OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
1517 0x0, NULL);
1518
1519DEFINE_CLK_GATE(wd_timer2_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
1520 OMAP4430_CM_WKUP_WDT2_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
1521 0x0, NULL);
1522
1523DEFINE_CLK_GATE(wd_timer3_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
1524 OMAP4430_CM1_ABE_WDT3_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
1525 0x0, NULL);
1526
1527/* Remaining optional clocks */ 1306/* Remaining optional clocks */
1528static const char *pmd_stm_clock_mux_ck_parents[] = { 1307static const char *pmd_stm_clock_mux_ck_parents[] = {
1529 "sys_clkin_ck", "dpll_core_m6x2_ck", "tie_low_clock_ck", 1308 "sys_clkin_ck", "dpll_core_m6x2_ck", "tie_low_clock_ck",
@@ -1774,52 +1553,27 @@ static struct omap_clk omap44xx_clks[] = {
1774 CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X), 1553 CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X),
1775 CLK(NULL, "aes1_fck", &aes1_fck, CK_443X), 1554 CLK(NULL, "aes1_fck", &aes1_fck, CK_443X),
1776 CLK(NULL, "aes2_fck", &aes2_fck, CK_443X), 1555 CLK(NULL, "aes2_fck", &aes2_fck, CK_443X),
1777 CLK(NULL, "aess_fck", &aess_fck, CK_443X),
1778 CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X), 1556 CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X),
1779 CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X), 1557 CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X),
1780 CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X), 1558 CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X),
1781 CLK(NULL, "des3des_fck", &des3des_fck, CK_443X),
1782 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), 1559 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X),
1783 CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), 1560 CLK(NULL, "dmic_fck", &dmic_fck, CK_443X),
1784 CLK(NULL, "dsp_fck", &dsp_fck, CK_443X),
1785 CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X), 1561 CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X),
1786 CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X), 1562 CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X),
1787 CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X), 1563 CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X),
1788 CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X), 1564 CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X),
1789 CLK(NULL, "dss_fck", &dss_fck, CK_443X), 1565 CLK(NULL, "dss_fck", &dss_fck, CK_443X),
1790 CLK("omapdss_dss", "ick", &dss_fck, CK_443X), 1566 CLK("omapdss_dss", "ick", &dss_fck, CK_443X),
1791 CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X),
1792 CLK(NULL, "emif1_fck", &emif1_fck, CK_443X),
1793 CLK(NULL, "emif2_fck", &emif2_fck, CK_443X),
1794 CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), 1567 CLK(NULL, "fdif_fck", &fdif_fck, CK_443X),
1795 CLK(NULL, "fpka_fck", &fpka_fck, CK_443X),
1796 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_443X), 1568 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_443X),
1797 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X),
1798 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_443X), 1569 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_443X),
1799 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X),
1800 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_443X), 1570 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_443X),
1801 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X),
1802 CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_443X), 1571 CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_443X),
1803 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X),
1804 CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_443X), 1572 CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_443X),
1805 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X),
1806 CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_443X), 1573 CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_443X),
1807 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X),
1808 CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X),
1809 CLK(NULL, "gpu_fck", &gpu_fck, CK_443X), 1574 CLK(NULL, "gpu_fck", &gpu_fck, CK_443X),
1810 CLK(NULL, "hdq1w_fck", &hdq1w_fck, CK_443X),
1811 CLK(NULL, "hsi_fck", &hsi_fck, CK_443X), 1575 CLK(NULL, "hsi_fck", &hsi_fck, CK_443X),
1812 CLK(NULL, "i2c1_fck", &i2c1_fck, CK_443X),
1813 CLK(NULL, "i2c2_fck", &i2c2_fck, CK_443X),
1814 CLK(NULL, "i2c3_fck", &i2c3_fck, CK_443X),
1815 CLK(NULL, "i2c4_fck", &i2c4_fck, CK_443X),
1816 CLK(NULL, "ipu_fck", &ipu_fck, CK_443X),
1817 CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X), 1576 CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X),
1818 CLK(NULL, "iss_fck", &iss_fck, CK_443X),
1819 CLK(NULL, "iva_fck", &iva_fck, CK_443X),
1820 CLK(NULL, "kbd_fck", &kbd_fck, CK_443X),
1821 CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_443X),
1822 CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_443X),
1823 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), 1577 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X),
1824 CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X), 1578 CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X),
1825 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), 1579 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X),
@@ -1830,32 +1584,16 @@ static struct omap_clk omap44xx_clks[] = {
1830 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_443X), 1584 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_443X),
1831 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), 1585 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X),
1832 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_443X), 1586 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_443X),
1833 CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X),
1834 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_443X),
1835 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_443X),
1836 CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_443X),
1837 CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_443X),
1838 CLK(NULL, "mmc1_fck", &mmc1_fck, CK_443X), 1587 CLK(NULL, "mmc1_fck", &mmc1_fck, CK_443X),
1839 CLK(NULL, "mmc2_fck", &mmc2_fck, CK_443X), 1588 CLK(NULL, "mmc2_fck", &mmc2_fck, CK_443X),
1840 CLK(NULL, "mmc3_fck", &mmc3_fck, CK_443X),
1841 CLK(NULL, "mmc4_fck", &mmc4_fck, CK_443X),
1842 CLK(NULL, "mmc5_fck", &mmc5_fck, CK_443X),
1843 CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X),
1844 CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X),
1845 CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X),
1846 CLK(NULL, "rng_ick", &rng_ick, CK_443X),
1847 CLK("omap_rng", "ick", &rng_ick, CK_443X),
1848 CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X), 1589 CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X),
1849 CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X),
1850 CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X), 1590 CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X),
1851 CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X), 1591 CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X),
1852 CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X), 1592 CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X),
1853 CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X), 1593 CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X),
1854 CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X),
1855 CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X), 1594 CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X),
1856 CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X), 1595 CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X),
1857 CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X), 1596 CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X),
1858 CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X),
1859 CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X), 1597 CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X),
1860 CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X), 1598 CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X),
1861 CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X), 1599 CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X),
@@ -1870,10 +1608,6 @@ static struct omap_clk omap44xx_clks[] = {
1870 CLK(NULL, "timer7_fck", &timer7_fck, CK_443X), 1608 CLK(NULL, "timer7_fck", &timer7_fck, CK_443X),
1871 CLK(NULL, "timer8_fck", &timer8_fck, CK_443X), 1609 CLK(NULL, "timer8_fck", &timer8_fck, CK_443X),
1872 CLK(NULL, "timer9_fck", &timer9_fck, CK_443X), 1610 CLK(NULL, "timer9_fck", &timer9_fck, CK_443X),
1873 CLK(NULL, "uart1_fck", &uart1_fck, CK_443X),
1874 CLK(NULL, "uart2_fck", &uart2_fck, CK_443X),
1875 CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
1876 CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
1877 CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), 1611 CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X),
1878 CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck, CK_443X), 1612 CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck, CK_443X),
1879 CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), 1613 CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X),
@@ -1901,9 +1635,6 @@ static struct omap_clk omap44xx_clks[] = {
1901 CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick, CK_443X), 1635 CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
1902 CLK(NULL, "usim_ck", &usim_ck, CK_443X), 1636 CLK(NULL, "usim_ck", &usim_ck, CK_443X),
1903 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), 1637 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
1904 CLK(NULL, "usim_fck", &usim_fck, CK_443X),
1905 CLK(NULL, "wd_timer2_fck", &wd_timer2_fck, CK_443X),
1906 CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X),
1907 CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X), 1638 CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X),
1908 CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X), 1639 CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X),
1909 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), 1640 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
@@ -1980,15 +1711,6 @@ static struct omap_clk omap44xx_clks[] = {
1980 CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X), 1711 CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X),
1981}; 1712};
1982 1713
1983static const char *enable_init_clks[] = {
1984 "emif1_fck",
1985 "emif2_fck",
1986 "gpmc_ick",
1987 "l3_instr_ick",
1988 "l3_main_3_ick",
1989 "ocp_wp_noc_ick",
1990};
1991
1992int __init omap4xxx_clk_init(void) 1714int __init omap4xxx_clk_init(void)
1993{ 1715{
1994 u32 cpu_clkflg; 1716 u32 cpu_clkflg;
@@ -2019,9 +1741,6 @@ int __init omap4xxx_clk_init(void)
2019 1741
2020 omap2_clk_disable_autoidle_all(); 1742 omap2_clk_disable_autoidle_all();
2021 1743
2022 omap2_clk_enable_init_clocks(enable_init_clks,
2023 ARRAY_SIZE(enable_init_clks));
2024
2025 /* 1744 /*
2026 * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power 1745 * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
2027 * state when turning the ABE clock domain. Workaround this by 1746 * state when turning the ABE clock domain. Workaround this by
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-13 14:28:42 -0400