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authorLinus Torvalds <torvalds@linux-foundation.org>2009-03-28 17:03:14 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2009-03-28 17:03:14 -0400
commit0fe41b8982001cd14ee2c77cd776735a5024e98b (patch)
tree83e65d595c413d55259ea14fb97748ce5efe5707 /arch/arm/mach-mmp/include/mach
parenteedf2c5296a8dfaaf9aec1a938c1d3bd73159a30 (diff)
parent9759d22c8348343b0da4e25d6150c41712686c14 (diff)
Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (422 commits) [ARM] 5435/1: fix compile warning in sanity_check_meminfo() [ARM] 5434/1: ARM: OMAP: Fix mailbox compile for 24xx [ARM] pxa: fix the bad assumption that PCMCIA sockets always start with 0 [ARM] pxa: fix Colibri PXA300 and PXA320 LCD backlight pins imxfb: Fix TFT mode i.MX21/27: remove ifdef CONFIG_FB_IMX imxfb: add clock support mxc: add arch_reset() function clkdev: add possibility to get a clock based on the device name i.MX1: remove fb support from mach-imx [ARM] pxa: build arch/arm/plat-pxa/mfp.c only when PXA3xx or ARCH_MMP defined Gemini: Add support for Teltonika RUT100 Gemini: gpiolib based GPIO support v2 MAINTAINERS: add myself as Gemini architecture maintainer ARM: Add Gemini architecture v3 [ARM] OMAP: Fix compile for omap2_init_common_hw() MAINTAINERS: Add myself as Faraday ARM core variant maintainer ARM: Add support for FA526 v2 [ARM] acorn,ebsa110,footbridge,integrator,sa1100: Convert asm/io.h to linux/io.h [ARM] collie: fix two minor formatting nits ...
Diffstat (limited to 'arch/arm/mach-mmp/include/mach')
-rw-r--r--arch/arm/mach-mmp/include/mach/addr-map.h34
-rw-r--r--arch/arm/mach-mmp/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-mmp/include/mach/cputype.h30
-rw-r--r--arch/arm/mach-mmp/include/mach/debug-macro.S23
-rw-r--r--arch/arm/mach-mmp/include/mach/devices.h37
-rw-r--r--arch/arm/mach-mmp/include/mach/dma.h13
-rw-r--r--arch/arm/mach-mmp/include/mach/entry-macro.S25
-rw-r--r--arch/arm/mach-mmp/include/mach/gpio.h36
-rw-r--r--arch/arm/mach-mmp/include/mach/hardware.h4
-rw-r--r--arch/arm/mach-mmp/include/mach/io.h21
-rw-r--r--arch/arm/mach-mmp/include/mach/irqs.h119
-rw-r--r--arch/arm/mach-mmp/include/mach/memory.h14
-rw-r--r--arch/arm/mach-mmp/include/mach/mfp-pxa168.h258
-rw-r--r--arch/arm/mach-mmp/include/mach/mfp-pxa910.h157
-rw-r--r--arch/arm/mach-mmp/include/mach/mfp.h37
-rw-r--r--arch/arm/mach-mmp/include/mach/pxa168.h23
-rw-r--r--arch/arm/mach-mmp/include/mach/pxa910.h23
-rw-r--r--arch/arm/mach-mmp/include/mach/regs-apbc.h78
-rw-r--r--arch/arm/mach-mmp/include/mach/regs-apmu.h36
-rw-r--r--arch/arm/mach-mmp/include/mach/regs-icu.h31
-rw-r--r--arch/arm/mach-mmp/include/mach/regs-timers.h44
-rw-r--r--arch/arm/mach-mmp/include/mach/system.h21
-rw-r--r--arch/arm/mach-mmp/include/mach/timex.h9
-rw-r--r--arch/arm/mach-mmp/include/mach/uncompress.h41
-rw-r--r--arch/arm/mach-mmp/include/mach/vmalloc.h5
25 files changed, 1126 insertions, 0 deletions
diff --git a/arch/arm/mach-mmp/include/mach/addr-map.h b/arch/arm/mach-mmp/include/mach/addr-map.h
new file mode 100644
index 000000000000..3254089a644d
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/addr-map.h
@@ -0,0 +1,34 @@
1/*
2 * linux/arch/arm/mach-mmp/include/mach/addr-map.h
3 *
4 * Common address map definitions
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_MACH_ADDR_MAP_H
12#define __ASM_MACH_ADDR_MAP_H
13
14/* APB - Application Subsystem Peripheral Bus
15 *
16 * NOTE: the DMA controller registers are actually on the AXI fabric #1
17 * slave port to AHB/APB bridge, due to its close relationship to those
18 * peripherals on APB, let's count it into the ABP mapping area.
19 */
20#define APB_PHYS_BASE 0xd4000000
21#define APB_VIRT_BASE 0xfe000000
22#define APB_PHYS_SIZE 0x00200000
23
24#define AXI_PHYS_BASE 0xd4200000
25#define AXI_VIRT_BASE 0xfe200000
26#define AXI_PHYS_SIZE 0x00200000
27
28/* Static Memory Controller - Chip Select 0 and 1 */
29#define SMC_CS0_PHYS_BASE 0x80000000
30#define SMC_CS0_PHYS_SIZE 0x10000000
31#define SMC_CS1_PHYS_BASE 0x90000000
32#define SMC_CS1_PHYS_SIZE 0x10000000
33
34#endif /* __ASM_MACH_ADDR_MAP_H */
diff --git a/arch/arm/mach-mmp/include/mach/clkdev.h b/arch/arm/mach-mmp/include/mach/clkdev.h
new file mode 100644
index 000000000000..2fb354e54e0d
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/clkdev.h
@@ -0,0 +1,7 @@
1#ifndef __ASM_MACH_CLKDEV_H
2#define __ASM_MACH_CLKDEV_H
3
4#define __clk_get(clk) ({ 1; })
5#define __clk_put(clk) do { } while (0)
6
7#endif /* __ASM_MACH_CLKDEV_H */
diff --git a/arch/arm/mach-mmp/include/mach/cputype.h b/arch/arm/mach-mmp/include/mach/cputype.h
new file mode 100644
index 000000000000..25e797b09083
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/cputype.h
@@ -0,0 +1,30 @@
1#ifndef __ASM_MACH_CPUTYPE_H
2#define __ASM_MACH_CPUTYPE_H
3
4#include <asm/cputype.h>
5
6/*
7 * CPU Stepping OLD_ID CPU_ID CHIP_ID
8 *
9 * PXA168 A0 0x41159263 0x56158400 0x00A0A333
10 * PXA910 Y0 0x41159262 0x56158000 0x00F0C910
11 */
12
13#ifdef CONFIG_CPU_PXA168
14# define __cpu_is_pxa168(id) \
15 ({ unsigned int _id = ((id) >> 8) & 0xff; _id == 0x84; })
16#else
17# define __cpu_is_pxa168(id) (0)
18#endif
19
20#ifdef CONFIG_CPU_PXA910
21# define __cpu_is_pxa910(id) \
22 ({ unsigned int _id = ((id) >> 8) & 0xff; _id == 0x80; })
23#else
24# define __cpu_is_pxa910(id) (0)
25#endif
26
27#define cpu_is_pxa168() ({ __cpu_is_pxa168(read_cpuid_id()); })
28#define cpu_is_pxa910() ({ __cpu_is_pxa910(read_cpuid_id()); })
29
30#endif /* __ASM_MACH_CPUTYPE_H */
diff --git a/arch/arm/mach-mmp/include/mach/debug-macro.S b/arch/arm/mach-mmp/include/mach/debug-macro.S
new file mode 100644
index 000000000000..a850f87de51d
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/debug-macro.S
@@ -0,0 +1,23 @@
1/* arch/arm/mach-mmp/include/mach/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copied from arch/arm/mach-pxa/include/mach/debug.S
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <mach/addr-map.h>
13
14 .macro addruart,rx
15 mrc p15, 0, \rx, c1, c0
16 tst \rx, #1 @ MMU enabled?
17 ldreq \rx, =APB_PHYS_BASE @ physical
18 ldrne \rx, =APB_VIRT_BASE @ virtual
19 orr \rx, \rx, #0x00017000
20 .endm
21
22#define UART_SHIFT 2
23#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-mmp/include/mach/devices.h b/arch/arm/mach-mmp/include/mach/devices.h
new file mode 100644
index 000000000000..24585397217e
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/devices.h
@@ -0,0 +1,37 @@
1#include <linux/types.h>
2
3#define MAX_RESOURCE_DMA 2
4
5/* structure for describing the on-chip devices */
6struct pxa_device_desc {
7 const char *dev_name;
8 const char *drv_name;
9 int id;
10 int irq;
11 unsigned long start;
12 unsigned long size;
13 int dma[MAX_RESOURCE_DMA];
14};
15
16#define PXA168_DEVICE(_name, _drv, _id, _irq, _start, _size, _dma...) \
17struct pxa_device_desc pxa168_device_##_name __initdata = { \
18 .dev_name = "pxa168-" #_name, \
19 .drv_name = _drv, \
20 .id = _id, \
21 .irq = IRQ_PXA168_##_irq, \
22 .start = _start, \
23 .size = _size, \
24 .dma = { _dma }, \
25};
26
27#define PXA910_DEVICE(_name, _drv, _id, _irq, _start, _size, _dma...) \
28struct pxa_device_desc pxa910_device_##_name __initdata = { \
29 .dev_name = "pxa910-" #_name, \
30 .drv_name = _drv, \
31 .id = _id, \
32 .irq = IRQ_PXA910_##_irq, \
33 .start = _start, \
34 .size = _size, \
35 .dma = { _dma }, \
36};
37extern int pxa_register_device(struct pxa_device_desc *, void *, size_t);
diff --git a/arch/arm/mach-mmp/include/mach/dma.h b/arch/arm/mach-mmp/include/mach/dma.h
new file mode 100644
index 000000000000..1d6914544da4
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/dma.h
@@ -0,0 +1,13 @@
1/*
2 * linux/arch/arm/mach-mmp/include/mach/dma.h
3 */
4
5#ifndef __ASM_MACH_DMA_H
6#define __ASM_MACH_DMA_H
7
8#include <mach/addr-map.h>
9
10#define DMAC_REGS_VIRT (APB_VIRT_BASE + 0x00000)
11
12#include <plat/dma.h>
13#endif /* __ASM_MACH_DMA_H */
diff --git a/arch/arm/mach-mmp/include/mach/entry-macro.S b/arch/arm/mach-mmp/include/mach/entry-macro.S
new file mode 100644
index 000000000000..6d3cd35478b5
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/entry-macro.S
@@ -0,0 +1,25 @@
1/*
2 * linux/arch/arm/mach-mmp/include/mach/entry-macro.S
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <mach/regs-icu.h>
10
11 .macro disable_fiq
12 .endm
13
14 .macro arch_ret_to_user, tmp1, tmp2
15 .endm
16
17 .macro get_irqnr_preamble, base, tmp
18 ldr \base, =ICU_AP_IRQ_SEL_INT_NUM
19 .endm
20
21 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
22 ldr \tmp, [\base, #0]
23 and \irqnr, \tmp, #0x3f
24 tst \tmp, #(1 << 6)
25 .endm
diff --git a/arch/arm/mach-mmp/include/mach/gpio.h b/arch/arm/mach-mmp/include/mach/gpio.h
new file mode 100644
index 000000000000..ab26d13295c4
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/gpio.h
@@ -0,0 +1,36 @@
1#ifndef __ASM_MACH_GPIO_H
2#define __ASM_MACH_GPIO_H
3
4#include <mach/addr-map.h>
5#include <mach/irqs.h>
6#include <asm-generic/gpio.h>
7
8#define GPIO_REGS_VIRT (APB_VIRT_BASE + 0x19000)
9
10#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
11#define GPIO_REG(x) (*((volatile u32 *)(GPIO_REGS_VIRT + (x))))
12
13#define NR_BUILTIN_GPIO (128)
14
15#define gpio_to_bank(gpio) ((gpio) >> 5)
16#define gpio_to_irq(gpio) (IRQ_GPIO_START + (gpio))
17#define irq_to_gpio(irq) ((irq) - IRQ_GPIO_START)
18
19
20#define __gpio_is_inverted(gpio) (0)
21#define __gpio_is_occupied(gpio) (0)
22
23/* NOTE: these macros are defined here to make optimization of
24 * gpio_{get,set}_value() to work when 'gpio' is a constant.
25 * Usage of these macros otherwise is no longer recommended,
26 * use generic GPIO API whenever possible.
27 */
28#define GPIO_bit(gpio) (1 << ((gpio) & 0x1f))
29
30#define GPLR(x) GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x00)
31#define GPDR(x) GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x0c)
32#define GPSR(x) GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x18)
33#define GPCR(x) GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x24)
34
35#include <plat/gpio.h>
36#endif /* __ASM_MACH_GPIO_H */
diff --git a/arch/arm/mach-mmp/include/mach/hardware.h b/arch/arm/mach-mmp/include/mach/hardware.h
new file mode 100644
index 000000000000..99264a5ce5e4
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/hardware.h
@@ -0,0 +1,4 @@
1#ifndef __ASM_MACH_HARDWARE_H
2#define __ASM_MACH_HARDWARE_H
3
4#endif /* __ASM_MACH_HARDWARE_H */
diff --git a/arch/arm/mach-mmp/include/mach/io.h b/arch/arm/mach-mmp/include/mach/io.h
new file mode 100644
index 000000000000..e7adf3d012c1
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/io.h
@@ -0,0 +1,21 @@
1/*
2 * linux/arch/arm/mach-mmp/include/mach/io.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef __ASM_MACH_IO_H
10#define __ASM_MACH_IO_H
11
12#define IO_SPACE_LIMIT 0xffffffff
13
14/*
15 * We don't actually have real ISA nor PCI buses, but there is so many
16 * drivers out there that might just work if we fake them...
17 */
18#define __io(a) __typesafe_io(a)
19#define __mem_pci(a) (a)
20
21#endif /* __ASM_MACH_IO_H */
diff --git a/arch/arm/mach-mmp/include/mach/irqs.h b/arch/arm/mach-mmp/include/mach/irqs.h
new file mode 100644
index 000000000000..e83e45ebf7a4
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/irqs.h
@@ -0,0 +1,119 @@
1#ifndef __ASM_MACH_IRQS_H
2#define __ASM_MACH_IRQS_H
3
4/*
5 * Interrupt numbers for PXA168
6 */
7#define IRQ_PXA168_NONE (-1)
8#define IRQ_PXA168_SSP3 0
9#define IRQ_PXA168_SSP2 1
10#define IRQ_PXA168_SSP1 2
11#define IRQ_PXA168_SSP0 3
12#define IRQ_PXA168_PMIC_INT 4
13#define IRQ_PXA168_RTC_INT 5
14#define IRQ_PXA168_RTC_ALARM 6
15#define IRQ_PXA168_TWSI0 7
16#define IRQ_PXA168_GPU 8
17#define IRQ_PXA168_KEYPAD 9
18#define IRQ_PXA168_ONEWIRE 12
19#define IRQ_PXA168_TIMER1 13
20#define IRQ_PXA168_TIMER2 14
21#define IRQ_PXA168_TIMER3 15
22#define IRQ_PXA168_CMU 16
23#define IRQ_PXA168_SSP4 17
24#define IRQ_PXA168_MSP_WAKEUP 19
25#define IRQ_PXA168_CF_WAKEUP 20
26#define IRQ_PXA168_XD_WAKEUP 21
27#define IRQ_PXA168_MFU 22
28#define IRQ_PXA168_MSP 23
29#define IRQ_PXA168_CF 24
30#define IRQ_PXA168_XD 25
31#define IRQ_PXA168_DDR_INT 26
32#define IRQ_PXA168_UART1 27
33#define IRQ_PXA168_UART2 28
34#define IRQ_PXA168_WDT 35
35#define IRQ_PXA168_FRQ_CHANGE 38
36#define IRQ_PXA168_SDH1 39
37#define IRQ_PXA168_SDH2 40
38#define IRQ_PXA168_LCD 41
39#define IRQ_PXA168_CI 42
40#define IRQ_PXA168_USB1 44
41#define IRQ_PXA168_NAND 45
42#define IRQ_PXA168_HIFI_DMA 46
43#define IRQ_PXA168_DMA_INT0 47
44#define IRQ_PXA168_DMA_INT1 48
45#define IRQ_PXA168_GPIOX 49
46#define IRQ_PXA168_USB2 51
47#define IRQ_PXA168_AC97 57
48#define IRQ_PXA168_TWSI1 58
49#define IRQ_PXA168_PMU 60
50#define IRQ_PXA168_SM_INT 63
51
52/*
53 * Interrupt numbers for PXA910
54 */
55#define IRQ_PXA910_AIRQ 0
56#define IRQ_PXA910_SSP3 1
57#define IRQ_PXA910_SSP2 2
58#define IRQ_PXA910_SSP1 3
59#define IRQ_PXA910_PMIC_INT 4
60#define IRQ_PXA910_RTC_INT 5
61#define IRQ_PXA910_RTC_ALARM 6
62#define IRQ_PXA910_TWSI0 7
63#define IRQ_PXA910_GPU 8
64#define IRQ_PXA910_KEYPAD 9
65#define IRQ_PXA910_ROTARY 10
66#define IRQ_PXA910_TRACKBALL 11
67#define IRQ_PXA910_ONEWIRE 12
68#define IRQ_PXA910_AP1_TIMER1 13
69#define IRQ_PXA910_AP1_TIMER2 14
70#define IRQ_PXA910_AP1_TIMER3 15
71#define IRQ_PXA910_IPC_AP0 16
72#define IRQ_PXA910_IPC_AP1 17
73#define IRQ_PXA910_IPC_AP2 18
74#define IRQ_PXA910_IPC_AP3 19
75#define IRQ_PXA910_IPC_AP4 20
76#define IRQ_PXA910_IPC_CP0 21
77#define IRQ_PXA910_IPC_CP1 22
78#define IRQ_PXA910_IPC_CP2 23
79#define IRQ_PXA910_IPC_CP3 24
80#define IRQ_PXA910_IPC_CP4 25
81#define IRQ_PXA910_L2_DDR 26
82#define IRQ_PXA910_UART2 27
83#define IRQ_PXA910_UART3 28
84#define IRQ_PXA910_AP2_TIMER1 29
85#define IRQ_PXA910_AP2_TIMER2 30
86#define IRQ_PXA910_CP2_TIMER1 31
87#define IRQ_PXA910_CP2_TIMER2 32
88#define IRQ_PXA910_CP2_TIMER3 33
89#define IRQ_PXA910_GSSP 34
90#define IRQ_PXA910_CP2_WDT 35
91#define IRQ_PXA910_MAIN_PMU 36
92#define IRQ_PXA910_CP_FREQ_CHG 37
93#define IRQ_PXA910_AP_FREQ_CHG 38
94#define IRQ_PXA910_MMC 39
95#define IRQ_PXA910_AEU 40
96#define IRQ_PXA910_LCD 41
97#define IRQ_PXA910_CCIC 42
98#define IRQ_PXA910_IRE 43
99#define IRQ_PXA910_USB1 44
100#define IRQ_PXA910_NAND 45
101#define IRQ_PXA910_HIFI_DMA 46
102#define IRQ_PXA910_DMA_INT0 47
103#define IRQ_PXA910_DMA_INT1 48
104#define IRQ_PXA910_AP_GPIO 49
105#define IRQ_PXA910_AP2_TIMER3 50
106#define IRQ_PXA910_USB2 51
107#define IRQ_PXA910_TWSI1 54
108#define IRQ_PXA910_CP_GPIO 55
109#define IRQ_PXA910_UART1 59 /* Slow UART */
110#define IRQ_PXA910_AP_PMU 60
111#define IRQ_PXA910_SM_INT 63 /* from PinMux */
112
113#define IRQ_GPIO_START 64
114#define IRQ_GPIO_NUM 128
115#define IRQ_GPIO(x) (IRQ_GPIO_START + (x))
116
117#define NR_IRQS (IRQ_GPIO_START + IRQ_GPIO_NUM)
118
119#endif /* __ASM_MACH_IRQS_H */
diff --git a/arch/arm/mach-mmp/include/mach/memory.h b/arch/arm/mach-mmp/include/mach/memory.h
new file mode 100644
index 000000000000..bdb21d70714c
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/memory.h
@@ -0,0 +1,14 @@
1/*
2 * linux/arch/arm/mach-mmp/include/mach/memory.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef __ASM_MACH_MEMORY_H
10#define __ASM_MACH_MEMORY_H
11
12#define PHYS_OFFSET UL(0x00000000)
13
14#endif /* __ASM_MACH_MEMORY_H */
diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
new file mode 100644
index 000000000000..d0bdb6e3682b
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
@@ -0,0 +1,258 @@
1#ifndef __ASM_MACH_MFP_PXA168_H
2#define __ASM_MACH_MFP_PXA168_H
3
4#include <mach/mfp.h>
5
6/* GPIO */
7#define GPIO0_GPIO MFP_CFG(GPIO0, AF5)
8#define GPIO1_GPIO MFP_CFG(GPIO1, AF5)
9#define GPIO2_GPIO MFP_CFG(GPIO2, AF5)
10#define GPIO3_GPIO MFP_CFG(GPIO3, AF5)
11#define GPIO4_GPIO MFP_CFG(GPIO4, AF5)
12#define GPIO5_GPIO MFP_CFG(GPIO5, AF5)
13#define GPIO6_GPIO MFP_CFG(GPIO6, AF5)
14#define GPIO7_GPIO MFP_CFG(GPIO7, AF5)
15#define GPIO8_GPIO MFP_CFG(GPIO8, AF5)
16#define GPIO9_GPIO MFP_CFG(GPIO9, AF5)
17#define GPIO10_GPIO MFP_CFG(GPIO10, AF5)
18#define GPIO11_GPIO MFP_CFG(GPIO11, AF5)
19#define GPIO12_GPIO MFP_CFG(GPIO12, AF5)
20#define GPIO13_GPIO MFP_CFG(GPIO13, AF5)
21#define GPIO14_GPIO MFP_CFG(GPIO14, AF5)
22#define GPIO15_GPIO MFP_CFG(GPIO15, AF5)
23#define GPIO16_GPIO MFP_CFG(GPIO16, AF0)
24#define GPIO17_GPIO MFP_CFG(GPIO17, AF5)
25#define GPIO18_GPIO MFP_CFG(GPIO18, AF0)
26#define GPIO19_GPIO MFP_CFG(GPIO19, AF5)
27#define GPIO20_GPIO MFP_CFG(GPIO20, AF0)
28#define GPIO21_GPIO MFP_CFG(GPIO21, AF5)
29#define GPIO22_GPIO MFP_CFG(GPIO22, AF5)
30#define GPIO23_GPIO MFP_CFG(GPIO23, AF5)
31#define GPIO24_GPIO MFP_CFG(GPIO24, AF5)
32#define GPIO25_GPIO MFP_CFG(GPIO25, AF5)
33#define GPIO26_GPIO MFP_CFG(GPIO26, AF0)
34#define GPIO27_GPIO MFP_CFG(GPIO27, AF5)
35#define GPIO28_GPIO MFP_CFG(GPIO28, AF5)
36#define GPIO29_GPIO MFP_CFG(GPIO29, AF5)
37#define GPIO30_GPIO MFP_CFG(GPIO30, AF5)
38#define GPIO31_GPIO MFP_CFG(GPIO31, AF5)
39#define GPIO32_GPIO MFP_CFG(GPIO32, AF5)
40#define GPIO33_GPIO MFP_CFG(GPIO33, AF5)
41#define GPIO34_GPIO MFP_CFG(GPIO34, AF0)
42#define GPIO35_GPIO MFP_CFG(GPIO35, AF0)
43#define GPIO36_GPIO MFP_CFG(GPIO36, AF0)
44#define GPIO37_GPIO MFP_CFG(GPIO37, AF0)
45#define GPIO38_GPIO MFP_CFG(GPIO38, AF0)
46#define GPIO39_GPIO MFP_CFG(GPIO39, AF0)
47#define GPIO40_GPIO MFP_CFG(GPIO40, AF0)
48#define GPIO41_GPIO MFP_CFG(GPIO41, AF0)
49#define GPIO42_GPIO MFP_CFG(GPIO42, AF0)
50#define GPIO43_GPIO MFP_CFG(GPIO43, AF0)
51#define GPIO44_GPIO MFP_CFG(GPIO44, AF0)
52#define GPIO45_GPIO MFP_CFG(GPIO45, AF0)
53#define GPIO46_GPIO MFP_CFG(GPIO46, AF0)
54#define GPIO47_GPIO MFP_CFG(GPIO47, AF0)
55#define GPIO48_GPIO MFP_CFG(GPIO48, AF0)
56#define GPIO49_GPIO MFP_CFG(GPIO49, AF0)
57#define GPIO50_GPIO MFP_CFG(GPIO50, AF0)
58#define GPIO51_GPIO MFP_CFG(GPIO51, AF0)
59#define GPIO52_GPIO MFP_CFG(GPIO52, AF0)
60#define GPIO53_GPIO MFP_CFG(GPIO53, AF0)
61#define GPIO54_GPIO MFP_CFG(GPIO54, AF0)
62#define GPIO55_GPIO MFP_CFG(GPIO55, AF0)
63#define GPIO56_GPIO MFP_CFG(GPIO56, AF0)
64#define GPIO57_GPIO MFP_CFG(GPIO57, AF0)
65#define GPIO58_GPIO MFP_CFG(GPIO58, AF0)
66#define GPIO59_GPIO MFP_CFG(GPIO59, AF0)
67#define GPIO60_GPIO MFP_CFG(GPIO60, AF0)
68#define GPIO61_GPIO MFP_CFG(GPIO61, AF0)
69#define GPIO62_GPIO MFP_CFG(GPIO62, AF0)
70#define GPIO63_GPIO MFP_CFG(GPIO63, AF0)
71#define GPIO64_GPIO MFP_CFG(GPIO64, AF0)
72#define GPIO65_GPIO MFP_CFG(GPIO65, AF0)
73#define GPIO66_GPIO MFP_CFG(GPIO66, AF0)
74#define GPIO67_GPIO MFP_CFG(GPIO67, AF0)
75#define GPIO68_GPIO MFP_CFG(GPIO68, AF0)
76#define GPIO69_GPIO MFP_CFG(GPIO69, AF0)
77#define GPIO70_GPIO MFP_CFG(GPIO70, AF0)
78#define GPIO71_GPIO MFP_CFG(GPIO71, AF0)
79#define GPIO72_GPIO MFP_CFG(GPIO72, AF0)
80#define GPIO73_GPIO MFP_CFG(GPIO73, AF0)
81#define GPIO74_GPIO MFP_CFG(GPIO74, AF0)
82#define GPIO75_GPIO MFP_CFG(GPIO75, AF0)
83#define GPIO76_GPIO MFP_CFG(GPIO76, AF0)
84#define GPIO77_GPIO MFP_CFG(GPIO77, AF0)
85#define GPIO78_GPIO MFP_CFG(GPIO78, AF0)
86#define GPIO79_GPIO MFP_CFG(GPIO79, AF0)
87#define GPIO80_GPIO MFP_CFG(GPIO80, AF0)
88#define GPIO81_GPIO MFP_CFG(GPIO81, AF0)
89#define GPIO82_GPIO MFP_CFG(GPIO82, AF0)
90#define GPIO83_GPIO MFP_CFG(GPIO83, AF0)
91#define GPIO84_GPIO MFP_CFG(GPIO84, AF0)
92#define GPIO85_GPIO MFP_CFG(GPIO85, AF0)
93#define GPIO86_GPIO MFP_CFG(GPIO86, AF0)
94#define GPIO87_GPIO MFP_CFG(GPIO87, AF0)
95#define GPIO88_GPIO MFP_CFG(GPIO88, AF0)
96#define GPIO89_GPIO MFP_CFG(GPIO89, AF0)
97#define GPIO90_GPIO MFP_CFG(GPIO90, AF0)
98#define GPIO91_GPIO MFP_CFG(GPIO91, AF0)
99#define GPIO92_GPIO MFP_CFG(GPIO92, AF0)
100#define GPIO93_GPIO MFP_CFG(GPIO93, AF0)
101#define GPIO94_GPIO MFP_CFG(GPIO94, AF0)
102#define GPIO95_GPIO MFP_CFG(GPIO95, AF0)
103#define GPIO96_GPIO MFP_CFG(GPIO96, AF0)
104#define GPIO97_GPIO MFP_CFG(GPIO97, AF0)
105#define GPIO98_GPIO MFP_CFG(GPIO98, AF0)
106#define GPIO99_GPIO MFP_CFG(GPIO99, AF0)
107#define GPIO100_GPIO MFP_CFG(GPIO100, AF0)
108#define GPIO101_GPIO MFP_CFG(GPIO101, AF0)
109#define GPIO102_GPIO MFP_CFG(GPIO102, AF0)
110#define GPIO103_GPIO MFP_CFG(GPIO103, AF0)
111#define GPIO104_GPIO MFP_CFG(GPIO104, AF0)
112#define GPIO105_GPIO MFP_CFG(GPIO105, AF0)
113#define GPIO106_GPIO MFP_CFG(GPIO106, AF0)
114#define GPIO107_GPIO MFP_CFG(GPIO107, AF0)
115#define GPIO108_GPIO MFP_CFG(GPIO108, AF0)
116#define GPIO109_GPIO MFP_CFG(GPIO109, AF0)
117#define GPIO110_GPIO MFP_CFG(GPIO110, AF0)
118#define GPIO111_GPIO MFP_CFG(GPIO111, AF0)
119#define GPIO112_GPIO MFP_CFG(GPIO112, AF0)
120#define GPIO113_GPIO MFP_CFG(GPIO113, AF0)
121#define GPIO114_GPIO MFP_CFG(GPIO114, AF0)
122#define GPIO115_GPIO MFP_CFG(GPIO115, AF0)
123#define GPIO116_GPIO MFP_CFG(GPIO116, AF0)
124#define GPIO117_GPIO MFP_CFG(GPIO117, AF0)
125#define GPIO118_GPIO MFP_CFG(GPIO118, AF0)
126#define GPIO119_GPIO MFP_CFG(GPIO119, AF0)
127#define GPIO120_GPIO MFP_CFG(GPIO120, AF0)
128#define GPIO121_GPIO MFP_CFG(GPIO121, AF0)
129#define GPIO122_GPIO MFP_CFG(GPIO122, AF0)
130
131/* DFI */
132#define GPIO0_DFI_D15 MFP_CFG(GPIO0, AF0)
133#define GPIO1_DFI_D14 MFP_CFG(GPIO1, AF0)
134#define GPIO2_DFI_D13 MFP_CFG(GPIO2, AF0)
135#define GPIO3_DFI_D12 MFP_CFG(GPIO3, AF0)
136#define GPIO4_DFI_D11 MFP_CFG(GPIO4, AF0)
137#define GPIO5_DFI_D10 MFP_CFG(GPIO5, AF0)
138#define GPIO6_DFI_D9 MFP_CFG(GPIO6, AF0)
139#define GPIO7_DFI_D8 MFP_CFG(GPIO7, AF0)
140#define GPIO8_DFI_D7 MFP_CFG(GPIO8, AF0)
141#define GPIO9_DFI_D6 MFP_CFG(GPIO9, AF0)
142#define GPIO10_DFI_D5 MFP_CFG(GPIO10, AF0)
143#define GPIO11_DFI_D4 MFP_CFG(GPIO11, AF0)
144#define GPIO12_DFI_D3 MFP_CFG(GPIO12, AF0)
145#define GPIO13_DFI_D2 MFP_CFG(GPIO13, AF0)
146#define GPIO14_DFI_D1 MFP_CFG(GPIO14, AF0)
147#define GPIO15_DFI_D0 MFP_CFG(GPIO15, AF0)
148
149#define GPIO30_DFI_ADDR0 MFP_CFG(GPIO30, AF0)
150#define GPIO31_DFI_ADDR1 MFP_CFG(GPIO31, AF0)
151#define GPIO32_DFI_ADDR2 MFP_CFG(GPIO32, AF0)
152#define GPIO33_DFI_ADDR3 MFP_CFG(GPIO33, AF0)
153
154/* NAND */
155#define GPIO16_ND_nCS0 MFP_CFG(GPIO16, AF1)
156#define GPIO17_ND_nWE MFP_CFG(GPIO17, AF0)
157#define GPIO21_ND_ALE MFP_CFG(GPIO21, AF0)
158#define GPIO22_ND_CLE MFP_CFG(GPIO22, AF0)
159#define GPIO24_ND_nRE MFP_CFG(GPIO24, AF0)
160#define GPIO26_ND_RnB1 MFP_CFG(GPIO26, AF1)
161#define GPIO27_ND_RnB2 MFP_CFG(GPIO27, AF1)
162
163/* Static Memory Controller */
164#define GPIO18_SMC_nCS0 MFP_CFG(GPIO18, AF3)
165#define GPIO18_SMC_nCS1 MFP_CFG(GPIO18, AF2)
166#define GPIO16_SMC_nCS0 MFP_CFG(GPIO16, AF2)
167#define GPIO16_SMC_nCS1 MFP_CFG(GPIO16, AF3)
168#define GPIO19_SMC_nCS0 MFP_CFG(GPIO19, AF0)
169#define GPIO20_SMC_nCS1 MFP_CFG(GPIO20, AF2)
170#define GPIO23_SMC_nLUA MFP_CFG(GPIO23, AF0)
171#define GPIO25_SMC_nLLA MFP_CFG(GPIO25, AF0)
172#define GPIO27_SMC_IRQ MFP_CFG(GPIO27, AF0)
173#define GPIO28_SMC_RDY MFP_CFG(GPIO28, AF0)
174#define GPIO29_SMC_SCLK MFP_CFG(GPIO29, AF0)
175#define GPIO34_SMC_nCS1 MFP_CFG(GPIO34, AF2)
176#define GPIO35_SMC_BE1 MFP_CFG(GPIO35, AF2)
177#define GPIO36_SMC_BE2 MFP_CFG(GPIO36, AF2)
178
179/* Compact Flash */
180#define GPIO19_CF_nCE1 MFP_CFG(GPIO19, AF3)
181#define GPIO20_CF_nCE2 MFP_CFG(GPIO20, AF3)
182#define GPIO23_CF_nALE MFP_CFG(GPIO23, AF3)
183#define GPIO25_CF_nRESET MFP_CFG(GPIO25, AF3)
184#define GPIO28_CF_RDY MFP_CFG(GPIO28, AF3)
185#define GPIO29_CF_STSCH MFP_CFG(GPIO29, AF3)
186#define GPIO30_CF_nREG MFP_CFG(GPIO30, AF3)
187#define GPIO31_CF_nIOIS16 MFP_CFG(GPIO31, AF3)
188#define GPIO32_CF_nCD1 MFP_CFG(GPIO32, AF3)
189#define GPIO33_CF_nCD2 MFP_CFG(GPIO33, AF3)
190
191/* UART1 */
192#define GPIO107_UART1_TXD MFP_CFG_DRV(GPIO107, AF1, FAST)
193#define GPIO107_UART1_RXD MFP_CFG_DRV(GPIO107, AF2, FAST)
194#define GPIO108_UART1_RXD MFP_CFG_DRV(GPIO108, AF1, FAST)
195#define GPIO108_UART1_TXD MFP_CFG_DRV(GPIO108, AF2, FAST)
196#define GPIO109_UART1_CTS MFP_CFG(GPIO109, AF1)
197#define GPIO109_UART1_RTS MFP_CFG(GPIO109, AF2)
198#define GPIO110_UART1_RTS MFP_CFG(GPIO110, AF1)
199#define GPIO110_UART1_CTS MFP_CFG(GPIO110, AF2)
200#define GPIO111_UART1_RI MFP_CFG(GPIO111, AF1)
201#define GPIO111_UART1_DSR MFP_CFG(GPIO111, AF2)
202#define GPIO112_UART1_DTR MFP_CFG(GPIO111, AF1)
203#define GPIO112_UART1_DCD MFP_CFG(GPIO112, AF2)
204
205/* MMC1 */
206#define GPIO37_MMC1_DAT7 MFP_CFG(GPIO37, AF1)
207#define GPIO38_MMC1_DAT6 MFP_CFG(GPIO38, AF1)
208#define GPIO54_MMC1_DAT5 MFP_CFG(GPIO54, AF1)
209#define GPIO48_MMC1_DAT4 MFP_CFG(GPIO48, AF1)
210#define GPIO51_MMC1_DAT3 MFP_CFG(GPIO51, AF1)
211#define GPIO52_MMC1_DAT2 MFP_CFG(GPIO52, AF1)
212#define GPIO40_MMC1_DAT1 MFP_CFG(GPIO40, AF1)
213#define GPIO41_MMC1_DAT0 MFP_CFG(GPIO41, AF1)
214#define GPIO49_MMC1_CMD MFP_CFG(GPIO49, AF1)
215#define GPIO43_MMC1_CLK MFP_CFG(GPIO43, AF1)
216#define GPIO53_MMC1_CD MFP_CFG(GPIO53, AF1)
217#define GPIO46_MMC1_WP MFP_CFG(GPIO46, AF1)
218
219/* LCD */
220#define GPIO84_LCD_CS MFP_CFG(GPIO84, AF1)
221#define GPIO60_LCD_DD0 MFP_CFG(GPIO60, AF1)
222#define GPIO61_LCD_DD1 MFP_CFG(GPIO61, AF1)
223#define GPIO70_LCD_DD10 MFP_CFG(GPIO70, AF1)
224#define GPIO71_LCD_DD11 MFP_CFG(GPIO71, AF1)
225#define GPIO72_LCD_DD12 MFP_CFG(GPIO72, AF1)
226#define GPIO73_LCD_DD13 MFP_CFG(GPIO73, AF1)
227#define GPIO74_LCD_DD14 MFP_CFG(GPIO74, AF1)
228#define GPIO75_LCD_DD15 MFP_CFG(GPIO75, AF1)
229#define GPIO76_LCD_DD16 MFP_CFG(GPIO76, AF1)
230#define GPIO77_LCD_DD17 MFP_CFG(GPIO77, AF1)
231#define GPIO78_LCD_DD18 MFP_CFG(GPIO78, AF1)
232#define GPIO79_LCD_DD19 MFP_CFG(GPIO79, AF1)
233#define GPIO62_LCD_DD2 MFP_CFG(GPIO62, AF1)
234#define GPIO80_LCD_DD20 MFP_CFG(GPIO80, AF1)
235#define GPIO81_LCD_DD21 MFP_CFG(GPIO81, AF1)
236#define GPIO82_LCD_DD22 MFP_CFG(GPIO82, AF1)
237#define GPIO83_LCD_DD23 MFP_CFG(GPIO83, AF1)
238#define GPIO63_LCD_DD3 MFP_CFG(GPIO63, AF1)
239#define GPIO64_LCD_DD4 MFP_CFG(GPIO64, AF1)
240#define GPIO65_LCD_DD5 MFP_CFG(GPIO65, AF1)
241#define GPIO66_LCD_DD6 MFP_CFG(GPIO66, AF1)
242#define GPIO67_LCD_DD7 MFP_CFG(GPIO67, AF1)
243#define GPIO68_LCD_DD8 MFP_CFG(GPIO68, AF1)
244#define GPIO69_LCD_DD9 MFP_CFG(GPIO69, AF1)
245#define GPIO59_LCD_DENA_BIAS MFP_CFG(GPIO59, AF1)
246#define GPIO56_LCD_FCLK_RD MFP_CFG(GPIO56, AF1)
247#define GPIO57_LCD_LCLK_A0 MFP_CFG(GPIO57, AF1)
248#define GPIO58_LCD_PCLK_WR MFP_CFG(GPIO58, AF1)
249#define GPIO85_LCD_VSYNC MFP_CFG(GPIO85, AF1)
250
251/* I2S */
252#define GPIO113_I2S_MCLK MFP_CFG(GPIO113,AF6)
253#define GPIO114_I2S_FRM MFP_CFG(GPIO114,AF1)
254#define GPIO115_I2S_BCLK MFP_CFG(GPIO115,AF1)
255#define GPIO116_I2S_RXD MFP_CFG(GPIO116,AF2)
256#define GPIO117_I2S_TXD MFP_CFG(GPIO117,AF2)
257
258#endif /* __ASM_MACH_MFP_PXA168_H */
diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
new file mode 100644
index 000000000000..48a1cbc7c56b
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
@@ -0,0 +1,157 @@
1#ifndef __ASM_MACH_MFP_PXA910_H
2#define __ASM_MACH_MFP_PXA910_H
3
4#include <mach/mfp.h>
5
6/* UART2 */
7#define GPIO47_UART2_RXD MFP_CFG(GPIO47, AF6)
8#define GPIO48_UART2_TXD MFP_CFG(GPIO48, AF6)
9
10/* UART3 */
11#define GPIO31_UART3_RXD MFP_CFG(GPIO31, AF4)
12#define GPIO32_UART3_TXD MFP_CFG(GPIO32, AF4)
13
14/*IRDA*/
15#define GPIO51_IRDA_SHDN MFP_CFG(GPIO51, AF0)
16
17/* SMC */
18#define SM_nCS0_nCS0 MFP_CFG(SM_nCS0, AF0)
19#define SM_ADV_SM_ADV MFP_CFG(SM_ADV, AF0)
20#define SM_SCLK_SM_SCLK MFP_CFG(SM_SCLK, AF0)
21#define SM_SCLK_SM_SCLK MFP_CFG(SM_SCLK, AF0)
22#define SM_BE0_SM_BE0 MFP_CFG(SM_BE0, AF1)
23#define SM_BE1_SM_BE1 MFP_CFG(SM_BE1, AF1)
24
25/* I2C */
26#define GPIO53_CI2C_SCL MFP_CFG(GPIO53, AF2)
27#define GPIO54_CI2C_SDA MFP_CFG(GPIO54, AF2)
28
29/* SSP1 (I2S) */
30#define GPIO24_SSP1_SDATA_IN MFP_CFG_DRV(GPIO24, AF1, MEDIUM)
31#define GPIO21_SSP1_BITCLK MFP_CFG_DRV(GPIO21, AF1, MEDIUM)
32#define GPIO20_SSP1_SYSCLK MFP_CFG_DRV(GPIO20, AF1, MEDIUM)
33#define GPIO22_SSP1_SYNC MFP_CFG_DRV(GPIO22, AF1, MEDIUM)
34#define GPIO23_SSP1_DATA_OUT MFP_CFG_DRV(GPIO23, AF1, MEDIUM)
35#define GPIO124_MN_CLK_OUT MFP_CFG_DRV(GPIO124, AF1, MEDIUM)
36#define GPIO123_CLK_REQ MFP_CFG_DRV(GPIO123, AF0, MEDIUM)
37
38/* DFI */
39#define DF_IO0_ND_IO0 MFP_CFG(DF_IO0, AF0)
40#define DF_IO1_ND_IO1 MFP_CFG(DF_IO1, AF0)
41#define DF_IO2_ND_IO2 MFP_CFG(DF_IO2, AF0)
42#define DF_IO3_ND_IO3 MFP_CFG(DF_IO3, AF0)
43#define DF_IO4_ND_IO4 MFP_CFG(DF_IO4, AF0)
44#define DF_IO5_ND_IO5 MFP_CFG(DF_IO5, AF0)
45#define DF_IO6_ND_IO6 MFP_CFG(DF_IO6, AF0)
46#define DF_IO7_ND_IO7 MFP_CFG(DF_IO7, AF0)
47#define DF_IO8_ND_IO8 MFP_CFG(DF_IO8, AF0)
48#define DF_IO9_ND_IO9 MFP_CFG(DF_IO9, AF0)
49#define DF_IO10_ND_IO10 MFP_CFG(DF_IO10, AF0)
50#define DF_IO11_ND_IO11 MFP_CFG(DF_IO11, AF0)
51#define DF_IO12_ND_IO12 MFP_CFG(DF_IO12, AF0)
52#define DF_IO13_ND_IO13 MFP_CFG(DF_IO13, AF0)
53#define DF_IO14_ND_IO14 MFP_CFG(DF_IO14, AF0)
54#define DF_IO15_ND_IO15 MFP_CFG(DF_IO15, AF0)
55#define DF_nCS0_SM_nCS2_nCS0 MFP_CFG(DF_nCS0_SM_nCS2, AF0)
56#define DF_ALE_SM_WEn_ND_ALE MFP_CFG(DF_ALE_SM_WEn, AF1)
57#define DF_CLE_SM_OEn_ND_CLE MFP_CFG(DF_CLE_SM_OEn, AF0)
58#define DF_WEn_DF_WEn MFP_CFG(DF_WEn, AF1)
59#define DF_REn_DF_REn MFP_CFG(DF_REn, AF1)
60#define DF_RDY0_DF_RDY0 MFP_CFG(DF_RDY0, AF0)
61
62/*keypad*/
63#define GPIO00_KP_MKIN0 MFP_CFG(GPIO0, AF1)
64#define GPIO01_KP_MKOUT0 MFP_CFG(GPIO1, AF1)
65#define GPIO02_KP_MKIN1 MFP_CFG(GPIO2, AF1)
66#define GPIO03_KP_MKOUT1 MFP_CFG(GPIO3, AF1)
67#define GPIO04_KP_MKIN2 MFP_CFG(GPIO4, AF1)
68#define GPIO05_KP_MKOUT2 MFP_CFG(GPIO5, AF1)
69#define GPIO06_KP_MKIN3 MFP_CFG(GPIO6, AF1)
70#define GPIO07_KP_MKOUT3 MFP_CFG(GPIO7, AF1)
71#define GPIO08_KP_MKIN4 MFP_CFG(GPIO8, AF1)
72#define GPIO09_KP_MKOUT4 MFP_CFG(GPIO9, AF1)
73#define GPIO10_KP_MKIN5 MFP_CFG(GPIO10, AF1)
74#define GPIO11_KP_MKOUT5 MFP_CFG(GPIO11, AF1)
75#define GPIO12_KP_MKIN6 MFP_CFG(GPIO12, AF1)
76#define GPIO13_KP_MKOUT6 MFP_CFG(GPIO13, AF1)
77#define GPIO14_KP_MKIN7 MFP_CFG(GPIO14, AF1)
78#define GPIO15_KP_MKOUT7 MFP_CFG(GPIO15, AF1)
79#define GPIO16_KP_DKIN0 MFP_CFG(GPIO16, AF1)
80#define GPIO17_KP_DKIN1 MFP_CFG(GPIO17, AF1)
81#define GPIO18_KP_DKIN2 MFP_CFG(GPIO18, AF1)
82#define GPIO19_KP_DKIN3 MFP_CFG(GPIO19, AF1)
83
84/* LCD */
85#define GPIO81_LCD_FCLK MFP_CFG(GPIO81, AF1)
86#define GPIO82_LCD_LCLK MFP_CFG(GPIO82, AF1)
87#define GPIO83_LCD_PCLK MFP_CFG(GPIO83, AF1)
88#define GPIO84_LCD_DENA MFP_CFG(GPIO84, AF1)
89#define GPIO85_LCD_DD0 MFP_CFG(GPIO85, AF1)
90#define GPIO86_LCD_DD1 MFP_CFG(GPIO86, AF1)
91#define GPIO87_LCD_DD2 MFP_CFG(GPIO87, AF1)
92#define GPIO88_LCD_DD3 MFP_CFG(GPIO88, AF1)
93#define GPIO89_LCD_DD4 MFP_CFG(GPIO89, AF1)
94#define GPIO90_LCD_DD5 MFP_CFG(GPIO90, AF1)
95#define GPIO91_LCD_DD6 MFP_CFG(GPIO91, AF1)
96#define GPIO92_LCD_DD7 MFP_CFG(GPIO92, AF1)
97#define GPIO93_LCD_DD8 MFP_CFG(GPIO93, AF1)
98#define GPIO94_LCD_DD9 MFP_CFG(GPIO94, AF1)
99#define GPIO95_LCD_DD10 MFP_CFG(GPIO95, AF1)
100#define GPIO96_LCD_DD11 MFP_CFG(GPIO96, AF1)
101#define GPIO97_LCD_DD12 MFP_CFG(GPIO97, AF1)
102#define GPIO98_LCD_DD13 MFP_CFG(GPIO98, AF1)
103#define GPIO100_LCD_DD14 MFP_CFG(GPIO100, AF1)
104#define GPIO101_LCD_DD15 MFP_CFG(GPIO101, AF1)
105#define GPIO102_LCD_DD16 MFP_CFG(GPIO102, AF1)
106#define GPIO103_LCD_DD17 MFP_CFG(GPIO103, AF1)
107#define GPIO104_LCD_DD18 MFP_CFG(GPIO104, AF1)
108#define GPIO105_LCD_DD19 MFP_CFG(GPIO105, AF1)
109#define GPIO106_LCD_DD20 MFP_CFG(GPIO106, AF1)
110#define GPIO107_LCD_DD21 MFP_CFG(GPIO107, AF1)
111#define GPIO108_LCD_DD22 MFP_CFG(GPIO108, AF1)
112#define GPIO109_LCD_DD23 MFP_CFG(GPIO109, AF1)
113
114#define GPIO104_LCD_SPIDOUT MFP_CFG(GPIO104, AF3)
115#define GPIO105_LCD_SPIDIN MFP_CFG(GPIO105, AF3)
116#define GPIO107_LCD_CS1 MFP_CFG(GPIO107, AF3)
117#define GPIO108_LCD_DCLK MFP_CFG(GPIO108, AF3)
118
119#define GPIO106_LCD_RESET MFP_CFG(GPIO106, AF0)
120
121/*smart panel*/
122#define GPIO82_LCD_A0 MFP_CFG(GPIO82, AF0)
123#define GPIO83_LCD_WR MFP_CFG(GPIO83, AF0)
124#define GPIO103_LCD_CS MFP_CFG(GPIO103, AF0)
125
126/*1wire*/
127#define GPIO106_1WIRE MFP_CFG(GPIO106, AF3)
128
129/*CCIC*/
130#define GPIO67_CCIC_IN7 MFP_CFG_DRV(GPIO67, AF1, MEDIUM)
131#define GPIO68_CCIC_IN6 MFP_CFG_DRV(GPIO68, AF1, MEDIUM)
132#define GPIO69_CCIC_IN5 MFP_CFG_DRV(GPIO69, AF1, MEDIUM)
133#define GPIO70_CCIC_IN4 MFP_CFG_DRV(GPIO70, AF1, MEDIUM)
134#define GPIO71_CCIC_IN3 MFP_CFG_DRV(GPIO71, AF1, MEDIUM)
135#define GPIO72_CCIC_IN2 MFP_CFG_DRV(GPIO72, AF1, MEDIUM)
136#define GPIO73_CCIC_IN1 MFP_CFG_DRV(GPIO73, AF1, MEDIUM)
137#define GPIO74_CCIC_IN0 MFP_CFG_DRV(GPIO74, AF1, MEDIUM)
138#define GPIO75_CAM_HSYNC MFP_CFG_DRV(GPIO75, AF1, MEDIUM)
139#define GPIO76_CAM_VSYNC MFP_CFG_DRV(GPIO76, AF1, MEDIUM)
140#define GPIO77_CAM_MCLK MFP_CFG_DRV(GPIO77, AF1, MEDIUM)
141#define GPIO78_CAM_PCLK MFP_CFG_DRV(GPIO78, AF1, MEDIUM)
142
143/* MMC1 */
144#define MMC1_DAT7_MMC1_DAT7 MFP_CFG_DRV(MMC1_DAT7, AF0, MEDIUM)
145#define MMC1_DAT6_MMC1_DAT6 MFP_CFG_DRV(MMC1_DAT6, AF0, MEDIUM)
146#define MMC1_DAT5_MMC1_DAT5 MFP_CFG_DRV(MMC1_DAT5, AF0, MEDIUM)
147#define MMC1_DAT4_MMC1_DAT4 MFP_CFG_DRV(MMC1_DAT4, AF0, MEDIUM)
148#define MMC1_DAT3_MMC1_DAT3 MFP_CFG_DRV(MMC1_DAT3, AF0, MEDIUM)
149#define MMC1_DAT2_MMC1_DAT2 MFP_CFG_DRV(MMC1_DAT2, AF0, MEDIUM)
150#define MMC1_DAT1_MMC1_DAT1 MFP_CFG_DRV(MMC1_DAT1, AF0, MEDIUM)
151#define MMC1_DAT0_MMC1_DAT0 MFP_CFG_DRV(MMC1_DAT0, AF0, MEDIUM)
152#define MMC1_CMD_MMC1_CMD MFP_CFG_DRV(MMC1_CMD, AF0, MEDIUM)
153#define MMC1_CLK_MMC1_CLK MFP_CFG_DRV(MMC1_CLK, AF0, MEDIUM)
154#define MMC1_CD_MMC1_CD MFP_CFG_DRV(MMC1_CD, AF0, MEDIUM)
155#define MMC1_WP_MMC1_WP MFP_CFG_DRV(MMC1_WP, AF0, MEDIUM)
156
157#endif /* __ASM_MACH MFP_PXA910_H */
diff --git a/arch/arm/mach-mmp/include/mach/mfp.h b/arch/arm/mach-mmp/include/mach/mfp.h
new file mode 100644
index 000000000000..277ea4cd0f9f
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/mfp.h
@@ -0,0 +1,37 @@
1#ifndef __ASM_MACH_MFP_H
2#define __ASM_MACH_MFP_H
3
4#include <plat/mfp.h>
5
6/*
7 * NOTE: the MFPR register bit definitions on PXA168 processor lines are a
8 * bit different from those on PXA3xx. Bit [7:10] are now reserved, which
9 * were SLEEP_OE_N, SLEEP_DATA, SLEEP_SEL and the LSB of DRIVE bits.
10 *
11 * To cope with this difference and re-use the pxa3xx mfp code as much as
12 * possible, we make the following compromise:
13 *
14 * 1. SLEEP_OE_N will always be programmed to '1' (by MFP_LPM_FLOAT)
15 * 2. DRIVE strength definitions redefined to include the reserved bit10
16 * 3. Override MFP_CFG() and MFP_CFG_DRV()
17 * 4. Drop the use of MFP_CFG_LPM() and MFP_CFG_X()
18 */
19
20#define MFP_DRIVE_VERY_SLOW (0x0 << 13)
21#define MFP_DRIVE_SLOW (0x2 << 13)
22#define MFP_DRIVE_MEDIUM (0x4 << 13)
23#define MFP_DRIVE_FAST (0x8 << 13)
24
25#undef MFP_CFG
26#undef MFP_CFG_DRV
27#undef MFP_CFG_LPM
28#undef MFP_CFG_X
29#undef MFP_CFG_DEFAULT
30
31#define MFP_CFG(pin, af) \
32 (MFP_LPM_FLOAT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_MEDIUM)
33
34#define MFP_CFG_DRV(pin, af, drv) \
35 (MFP_LPM_FLOAT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_##drv)
36
37#endif /* __ASM_MACH_MFP_H */
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h
new file mode 100644
index 000000000000..ef0a8a2076e9
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -0,0 +1,23 @@
1#ifndef __ASM_MACH_PXA168_H
2#define __ASM_MACH_PXA168_H
3
4#include <mach/devices.h>
5
6extern struct pxa_device_desc pxa168_device_uart1;
7extern struct pxa_device_desc pxa168_device_uart2;
8
9static inline int pxa168_add_uart(int id)
10{
11 struct pxa_device_desc *d = NULL;
12
13 switch (id) {
14 case 1: d = &pxa168_device_uart1; break;
15 case 2: d = &pxa168_device_uart2; break;
16 }
17
18 if (d == NULL)
19 return -EINVAL;
20
21 return pxa_register_device(d, NULL, 0);
22}
23#endif /* __ASM_MACH_PXA168_H */
diff --git a/arch/arm/mach-mmp/include/mach/pxa910.h b/arch/arm/mach-mmp/include/mach/pxa910.h
new file mode 100644
index 000000000000..b7aeaf574c36
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/pxa910.h
@@ -0,0 +1,23 @@
1#ifndef __ASM_MACH_PXA910_H
2#define __ASM_MACH_PXA910_H
3
4#include <mach/devices.h>
5
6extern struct pxa_device_desc pxa910_device_uart1;
7extern struct pxa_device_desc pxa910_device_uart2;
8
9static inline int pxa910_add_uart(int id)
10{
11 struct pxa_device_desc *d = NULL;
12
13 switch (id) {
14 case 1: d = &pxa910_device_uart1; break;
15 case 2: d = &pxa910_device_uart2; break;
16 }
17
18 if (d == NULL)
19 return -EINVAL;
20
21 return pxa_register_device(d, NULL, 0);
22}
23#endif /* __ASM_MACH_PXA910_H */
diff --git a/arch/arm/mach-mmp/include/mach/regs-apbc.h b/arch/arm/mach-mmp/include/mach/regs-apbc.h
new file mode 100644
index 000000000000..c6b8c9dc2026
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/regs-apbc.h
@@ -0,0 +1,78 @@
1/*
2 * linux/arch/arm/mach-mmp/include/mach/regs-apbc.h
3 *
4 * Application Peripheral Bus Clock Unit
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_MACH_REGS_APBC_H
12#define __ASM_MACH_REGS_APBC_H
13
14#include <mach/addr-map.h>
15
16#define APBC_VIRT_BASE (APB_VIRT_BASE + 0x015000)
17#define APBC_REG(x) (APBC_VIRT_BASE + (x))
18
19/*
20 * APB clock register offsets for PXA168
21 */
22#define APBC_PXA168_UART1 APBC_REG(0x000)
23#define APBC_PXA168_UART2 APBC_REG(0x004)
24#define APBC_PXA168_GPIO APBC_REG(0x008)
25#define APBC_PXA168_PWM0 APBC_REG(0x00c)
26#define APBC_PXA168_PWM1 APBC_REG(0x010)
27#define APBC_PXA168_SSP1 APBC_REG(0x01c)
28#define APBC_PXA168_SSP2 APBC_REG(0x020)
29#define APBC_PXA168_RTC APBC_REG(0x028)
30#define APBC_PXA168_TWSI0 APBC_REG(0x02c)
31#define APBC_PXA168_KPC APBC_REG(0x030)
32#define APBC_PXA168_TIMERS APBC_REG(0x034)
33#define APBC_PXA168_AIB APBC_REG(0x03c)
34#define APBC_PXA168_SW_JTAG APBC_REG(0x040)
35#define APBC_PXA168_ONEWIRE APBC_REG(0x048)
36#define APBC_PXA168_SSP3 APBC_REG(0x04c)
37#define APBC_PXA168_ASFAR APBC_REG(0x050)
38#define APBC_PXA168_ASSAR APBC_REG(0x054)
39#define APBC_PXA168_SSP4 APBC_REG(0x058)
40#define APBC_PXA168_SSP5 APBC_REG(0x05c)
41#define APBC_PXA168_TWSI1 APBC_REG(0x06c)
42#define APBC_PXA168_UART3 APBC_REG(0x070)
43#define APBC_PXA168_AC97 APBC_REG(0x084)
44
45/*
46 * APB Clock register offsets for PXA910
47 */
48#define APBC_PXA910_UART0 APBC_REG(0x000)
49#define APBC_PXA910_UART1 APBC_REG(0x004)
50#define APBC_PXA910_GPIO APBC_REG(0x008)
51#define APBC_PXA910_PWM0 APBC_REG(0x00c)
52#define APBC_PXA910_PWM1 APBC_REG(0x010)
53#define APBC_PXA910_PWM2 APBC_REG(0x014)
54#define APBC_PXA910_PWM3 APBC_REG(0x018)
55#define APBC_PXA910_SSP1 APBC_REG(0x01c)
56#define APBC_PXA910_SSP2 APBC_REG(0x020)
57#define APBC_PXA910_IPC APBC_REG(0x024)
58#define APBC_PXA910_TWSI0 APBC_REG(0x02c)
59#define APBC_PXA910_KPC APBC_REG(0x030)
60#define APBC_PXA910_TIMERS APBC_REG(0x034)
61#define APBC_PXA910_TBROT APBC_REG(0x038)
62#define APBC_PXA910_AIB APBC_REG(0x03c)
63#define APBC_PXA910_SW_JTAG APBC_REG(0x040)
64#define APBC_PXA910_TIMERS1 APBC_REG(0x044)
65#define APBC_PXA910_ONEWIRE APBC_REG(0x048)
66#define APBC_PXA910_SSP3 APBC_REG(0x04c)
67#define APBC_PXA910_ASFAR APBC_REG(0x050)
68#define APBC_PXA910_ASSAR APBC_REG(0x054)
69
70/* Common APB clock register bit definitions */
71#define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */
72#define APBC_FNCLK (1 << 1) /* Functional Clock Enable */
73#define APBC_RST (1 << 2) /* Reset Generation */
74
75/* Functional Clock Selection Mask */
76#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4)
77
78#endif /* __ASM_MACH_REGS_APBC_H */
diff --git a/arch/arm/mach-mmp/include/mach/regs-apmu.h b/arch/arm/mach-mmp/include/mach/regs-apmu.h
new file mode 100644
index 000000000000..919030514120
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/regs-apmu.h
@@ -0,0 +1,36 @@
1/*
2 * linux/arch/arm/mach-mmp/include/mach/regs-apmu.h
3 *
4 * Application Subsystem Power Management Unit
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_MACH_REGS_APMU_H
12#define __ASM_MACH_REGS_APMU_H
13
14#include <mach/addr-map.h>
15
16#define APMU_VIRT_BASE (AXI_VIRT_BASE + 0x82800)
17#define APMU_REG(x) (APMU_VIRT_BASE + (x))
18
19/* Clock Reset Control */
20#define APMU_IRE APMU_REG(0x048)
21#define APMU_LCD APMU_REG(0x04c)
22#define APMU_CCIC APMU_REG(0x050)
23#define APMU_SDH0 APMU_REG(0x054)
24#define APMU_SDH1 APMU_REG(0x058)
25#define APMU_USB APMU_REG(0x05c)
26#define APMU_NAND APMU_REG(0x060)
27#define APMU_DMA APMU_REG(0x064)
28#define APMU_GEU APMU_REG(0x068)
29#define APMU_BUS APMU_REG(0x06c)
30
31#define APMU_FNCLK_EN (1 << 4)
32#define APMU_AXICLK_EN (1 << 3)
33#define APMU_FNRST_DIS (1 << 1)
34#define APMU_AXIRST_DIS (1 << 0)
35
36#endif /* __ASM_MACH_REGS_APMU_H */
diff --git a/arch/arm/mach-mmp/include/mach/regs-icu.h b/arch/arm/mach-mmp/include/mach/regs-icu.h
new file mode 100644
index 000000000000..e5f08723e0cc
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/regs-icu.h
@@ -0,0 +1,31 @@
1/*
2 * linux/arch/arm/mach-mmp/include/mach/regs-icu.h
3 *
4 * Interrupt Control Unit
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_MACH_ICU_H
12#define __ASM_MACH_ICU_H
13
14#include <mach/addr-map.h>
15
16#define ICU_VIRT_BASE (AXI_VIRT_BASE + 0x82000)
17#define ICU_REG(x) (ICU_VIRT_BASE + (x))
18
19#define ICU_INT_CONF(n) ICU_REG((n) << 2)
20#define ICU_INT_CONF_AP_INT (1 << 6)
21#define ICU_INT_CONF_CP_INT (1 << 5)
22#define ICU_INT_CONF_IRQ (1 << 4)
23#define ICU_INT_CONF_MASK (0xf)
24
25#define ICU_AP_FIQ_SEL_INT_NUM ICU_REG(0x108) /* AP FIQ Selected Interrupt */
26#define ICU_AP_IRQ_SEL_INT_NUM ICU_REG(0x10C) /* AP IRQ Selected Interrupt */
27#define ICU_AP_GBL_IRQ_MSK ICU_REG(0x114) /* AP Global Interrupt Mask */
28#define ICU_INT_STATUS_0 ICU_REG(0x128) /* Interrupt Stuats 0 */
29#define ICU_INT_STATUS_1 ICU_REG(0x12C) /* Interrupt Status 1 */
30
31#endif /* __ASM_MACH_ICU_H */
diff --git a/arch/arm/mach-mmp/include/mach/regs-timers.h b/arch/arm/mach-mmp/include/mach/regs-timers.h
new file mode 100644
index 000000000000..45589fec9fc7
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/regs-timers.h
@@ -0,0 +1,44 @@
1/*
2 * linux/arch/arm/mach-mmp/include/mach/regs-timers.h
3 *
4 * Timers Module
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_MACH_REGS_TIMERS_H
12#define __ASM_MACH_REGS_TIMERS_H
13
14#include <mach/addr-map.h>
15
16#define TIMERS1_VIRT_BASE (APB_VIRT_BASE + 0x14000)
17#define TIMERS2_VIRT_BASE (APB_VIRT_BASE + 0x16000)
18
19#define TMR_CCR (0x0000)
20#define TMR_TN_MM(n, m) (0x0004 + ((n) << 3) + (((n) + (m)) << 2))
21#define TMR_CR(n) (0x0028 + ((n) << 2))
22#define TMR_SR(n) (0x0034 + ((n) << 2))
23#define TMR_IER(n) (0x0040 + ((n) << 2))
24#define TMR_PLVR(n) (0x004c + ((n) << 2))
25#define TMR_PLCR(n) (0x0058 + ((n) << 2))
26#define TMR_WMER (0x0064)
27#define TMR_WMR (0x0068)
28#define TMR_WVR (0x006c)
29#define TMR_WSR (0x0070)
30#define TMR_ICR(n) (0x0074 + ((n) << 2))
31#define TMR_WICR (0x0080)
32#define TMR_CER (0x0084)
33#define TMR_CMR (0x0088)
34#define TMR_ILR(n) (0x008c + ((n) << 2))
35#define TMR_WCR (0x0098)
36#define TMR_WFAR (0x009c)
37#define TMR_WSAR (0x00A0)
38#define TMR_CVWR(n) (0x00A4 + ((n) << 2))
39
40#define TMR_CCR_CS_0(x) (((x) & 0x3) << 0)
41#define TMR_CCR_CS_1(x) (((x) & 0x7) << 2)
42#define TMR_CCR_CS_2(x) (((x) & 0x3) << 5)
43
44#endif /* __ASM_MACH_REGS_TIMERS_H */
diff --git a/arch/arm/mach-mmp/include/mach/system.h b/arch/arm/mach-mmp/include/mach/system.h
new file mode 100644
index 000000000000..001edfefec19
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/system.h
@@ -0,0 +1,21 @@
1/*
2 * linux/arch/arm/mach-mmp/include/mach/system.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef __ASM_MACH_SYSTEM_H
10#define __ASM_MACH_SYSTEM_H
11
12static inline void arch_idle(void)
13{
14 cpu_do_idle();
15}
16
17static inline void arch_reset(char mode)
18{
19 cpu_reset(0);
20}
21#endif /* __ASM_MACH_SYSTEM_H */
diff --git a/arch/arm/mach-mmp/include/mach/timex.h b/arch/arm/mach-mmp/include/mach/timex.h
new file mode 100644
index 000000000000..6cebbd0ca8f4
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/timex.h
@@ -0,0 +1,9 @@
1/*
2 * linux/arch/arm/mach-mmp/include/mach/timex.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#define CLOCK_TICK_RATE 3250000
diff --git a/arch/arm/mach-mmp/include/mach/uncompress.h b/arch/arm/mach-mmp/include/mach/uncompress.h
new file mode 100644
index 000000000000..c93d5fa5865c
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/uncompress.h
@@ -0,0 +1,41 @@
1/*
2 * arch/arm/mach-mmp/include/mach/uncompress.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/serial_reg.h>
10#include <mach/addr-map.h>
11
12#define UART1_BASE (APB_PHYS_BASE + 0x36000)
13#define UART2_BASE (APB_PHYS_BASE + 0x17000)
14#define UART3_BASE (APB_PHYS_BASE + 0x18000)
15
16static inline void putc(char c)
17{
18 volatile unsigned long *UART = (unsigned long *)UART2_BASE;
19
20 /* UART enabled? */
21 if (!(UART[UART_IER] & UART_IER_UUE))
22 return;
23
24 while (!(UART[UART_LSR] & UART_LSR_THRE))
25 barrier();
26
27 UART[UART_TX] = c;
28}
29
30/*
31 * This does not append a newline
32 */
33static inline void flush(void)
34{
35}
36
37/*
38 * nothing to do
39 */
40#define arch_decomp_setup()
41#define arch_decomp_wdog()
diff --git a/arch/arm/mach-mmp/include/mach/vmalloc.h b/arch/arm/mach-mmp/include/mach/vmalloc.h
new file mode 100644
index 000000000000..b60ccaf9fee7
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/vmalloc.h
@@ -0,0 +1,5 @@
1/*
2 * linux/arch/arm/mach-mmp/include/mach/vmalloc.h
3 */
4
5#define VMALLOC_END 0xfe000000
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 05:13:08 -0500