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authorLinus Torvalds <torvalds@linux-foundation.org>2011-01-15 15:33:40 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2011-01-15 15:33:40 -0500
commit16c1020362083b320868c0deef492249089c3cd3 (patch)
treeff200df3502e6010745713275d69fd0a07e399cf /arch/arm/mach-lpc32xx
parent65e5d002b5ad220db2bf9557f53de5a98f7dab86 (diff)
parentbbba75606963c82febf7bd2761ea848ac5d1a1bb (diff)
Merge branch 'devel-stable' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel-stable' of master.kernel.org:/home/rmk/linux-2.6-arm: (161 commits) ARM: pxa: fix building issue of missing physmap.h ARM: mmp: PXA910 drive strength FAST using wrong value ARM: mmp: MMP2 drive strength FAST using wrong value ARM: pxa: fix recursive calls in pxa_low_gpio_chip AT91: Support for gsia18s board AT91: Acme Systems FOX Board G20 board files AT91: board-sam9m10g45ek.c: Remove duplicate inclusion of mach/hardware.h ARM: pxa: fix suspend/resume array index miscalculation ARM: pxa: use cpu_has_ipr() consistently in irq.c ARM: pxa: remove unused variable in clock-pxa3xx.c ARM: pxa: fix warning in zeus.c ARM: sa1111: fix typo in sa1111_retrigger_lowirq() ARM mxs: clkdev related compile fixes ARM i.MX mx31_3ds: Fix MC13783 regulator names ARM: plat-stmp3xxx: irq_data conversion. ARM: plat-spear: irq_data conversion. ARM: plat-orion: irq_data conversion. ARM: plat-omap: irq_data conversion. ARM: plat-nomadik: irq_data conversion. ARM: plat-mxc: irq_data conversion. ... Fix up trivial conflict in arch/arm/plat-omap/gpio.c (Lennert Buytenhek's irq_data conversion clashing with some omap irq updates)
Diffstat (limited to 'arch/arm/mach-lpc32xx')
-rw-r--r--arch/arm/mach-lpc32xx/irq.c56
1 files changed, 28 insertions, 28 deletions
diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c
index bd0df26c415b..316ecbf6c586 100644
--- a/arch/arm/mach-lpc32xx/irq.c
+++ b/arch/arm/mach-lpc32xx/irq.c
@@ -191,38 +191,38 @@ static void get_controller(unsigned int irq, unsigned int *base,
191 } 191 }
192} 192}
193 193
194static void lpc32xx_mask_irq(unsigned int irq) 194static void lpc32xx_mask_irq(struct irq_data *d)
195{ 195{
196 unsigned int reg, ctrl, mask; 196 unsigned int reg, ctrl, mask;
197 197
198 get_controller(irq, &ctrl, &mask); 198 get_controller(d->irq, &ctrl, &mask);
199 199
200 reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) & ~mask; 200 reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) & ~mask;
201 __raw_writel(reg, LPC32XX_INTC_MASK(ctrl)); 201 __raw_writel(reg, LPC32XX_INTC_MASK(ctrl));
202} 202}
203 203
204static void lpc32xx_unmask_irq(unsigned int irq) 204static void lpc32xx_unmask_irq(struct irq_data *d)
205{ 205{
206 unsigned int reg, ctrl, mask; 206 unsigned int reg, ctrl, mask;
207 207
208 get_controller(irq, &ctrl, &mask); 208 get_controller(d->irq, &ctrl, &mask);
209 209
210 reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) | mask; 210 reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) | mask;
211 __raw_writel(reg, LPC32XX_INTC_MASK(ctrl)); 211 __raw_writel(reg, LPC32XX_INTC_MASK(ctrl));
212} 212}
213 213
214static void lpc32xx_ack_irq(unsigned int irq) 214static void lpc32xx_ack_irq(struct irq_data *d)
215{ 215{
216 unsigned int ctrl, mask; 216 unsigned int ctrl, mask;
217 217
218 get_controller(irq, &ctrl, &mask); 218 get_controller(d->irq, &ctrl, &mask);
219 219
220 __raw_writel(mask, LPC32XX_INTC_RAW_STAT(ctrl)); 220 __raw_writel(mask, LPC32XX_INTC_RAW_STAT(ctrl));
221 221
222 /* Also need to clear pending wake event */ 222 /* Also need to clear pending wake event */
223 if (lpc32xx_events[irq].mask != 0) 223 if (lpc32xx_events[d->irq].mask != 0)
224 __raw_writel(lpc32xx_events[irq].mask, 224 __raw_writel(lpc32xx_events[d->irq].mask,
225 lpc32xx_events[irq].event_group->rawstat_reg); 225 lpc32xx_events[d->irq].event_group->rawstat_reg);
226} 226}
227 227
228static void __lpc32xx_set_irq_type(unsigned int irq, int use_high_level, 228static void __lpc32xx_set_irq_type(unsigned int irq, int use_high_level,
@@ -261,27 +261,27 @@ static void __lpc32xx_set_irq_type(unsigned int irq, int use_high_level,
261 } 261 }
262} 262}
263 263
264static int lpc32xx_set_irq_type(unsigned int irq, unsigned int type) 264static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type)
265{ 265{
266 switch (type) { 266 switch (type) {
267 case IRQ_TYPE_EDGE_RISING: 267 case IRQ_TYPE_EDGE_RISING:
268 /* Rising edge sensitive */ 268 /* Rising edge sensitive */
269 __lpc32xx_set_irq_type(irq, 1, 1); 269 __lpc32xx_set_irq_type(d->irq, 1, 1);
270 break; 270 break;
271 271
272 case IRQ_TYPE_EDGE_FALLING: 272 case IRQ_TYPE_EDGE_FALLING:
273 /* Falling edge sensitive */ 273 /* Falling edge sensitive */
274 __lpc32xx_set_irq_type(irq, 0, 1); 274 __lpc32xx_set_irq_type(d->irq, 0, 1);
275 break; 275 break;
276 276
277 case IRQ_TYPE_LEVEL_LOW: 277 case IRQ_TYPE_LEVEL_LOW:
278 /* Low level sensitive */ 278 /* Low level sensitive */
279 __lpc32xx_set_irq_type(irq, 0, 0); 279 __lpc32xx_set_irq_type(d->irq, 0, 0);
280 break; 280 break;
281 281
282 case IRQ_TYPE_LEVEL_HIGH: 282 case IRQ_TYPE_LEVEL_HIGH:
283 /* High level sensitive */ 283 /* High level sensitive */
284 __lpc32xx_set_irq_type(irq, 1, 0); 284 __lpc32xx_set_irq_type(d->irq, 1, 0);
285 break; 285 break;
286 286
287 /* Other modes are not supported */ 287 /* Other modes are not supported */
@@ -290,33 +290,33 @@ static int lpc32xx_set_irq_type(unsigned int irq, unsigned int type)
290 } 290 }
291 291
292 /* Ok to use the level handler for all types */ 292 /* Ok to use the level handler for all types */
293 set_irq_handler(irq, handle_level_irq); 293 set_irq_handler(d->irq, handle_level_irq);
294 294
295 return 0; 295 return 0;
296} 296}
297 297
298static int lpc32xx_irq_wake(unsigned int irqno, unsigned int state) 298static int lpc32xx_irq_wake(struct irq_data *d, unsigned int state)
299{ 299{
300 unsigned long eventreg; 300 unsigned long eventreg;
301 301
302 if (lpc32xx_events[irqno].mask != 0) { 302 if (lpc32xx_events[d->irq].mask != 0) {
303 eventreg = __raw_readl(lpc32xx_events[irqno]. 303 eventreg = __raw_readl(lpc32xx_events[d->irq].
304 event_group->enab_reg); 304 event_group->enab_reg);
305 305
306 if (state) 306 if (state)
307 eventreg |= lpc32xx_events[irqno].mask; 307 eventreg |= lpc32xx_events[d->irq].mask;
308 else 308 else
309 eventreg &= ~lpc32xx_events[irqno].mask; 309 eventreg &= ~lpc32xx_events[d->irq].mask;
310 310
311 __raw_writel(eventreg, 311 __raw_writel(eventreg,
312 lpc32xx_events[irqno].event_group->enab_reg); 312 lpc32xx_events[d->irq].event_group->enab_reg);
313 313
314 return 0; 314 return 0;
315 } 315 }
316 316
317 /* Clear event */ 317 /* Clear event */
318 __raw_writel(lpc32xx_events[irqno].mask, 318 __raw_writel(lpc32xx_events[d->irq].mask,
319 lpc32xx_events[irqno].event_group->rawstat_reg); 319 lpc32xx_events[d->irq].event_group->rawstat_reg);
320 320
321 return -ENODEV; 321 return -ENODEV;
322} 322}
@@ -336,11 +336,11 @@ static void __init lpc32xx_set_default_mappings(unsigned int apr,
336} 336}
337 337
338static struct irq_chip lpc32xx_irq_chip = { 338static struct irq_chip lpc32xx_irq_chip = {
339 .ack = lpc32xx_ack_irq, 339 .irq_ack = lpc32xx_ack_irq,
340 .mask = lpc32xx_mask_irq, 340 .irq_mask = lpc32xx_mask_irq,
341 .unmask = lpc32xx_unmask_irq, 341 .irq_unmask = lpc32xx_unmask_irq,
342 .set_type = lpc32xx_set_irq_type, 342 .irq_set_type = lpc32xx_set_irq_type,
343 .set_wake = lpc32xx_irq_wake 343 .irq_set_wake = lpc32xx_irq_wake
344}; 344};
345 345
346static void lpc32xx_sic1_handler(unsigned int irq, struct irq_desc *desc) 346static void lpc32xx_sic1_handler(unsigned int irq, struct irq_desc *desc)