Merge branch 'devel-stable' of master.kernel.org:/home/rmk/linux-2.6-arm

* 'devel-stable' of master.kernel.org:/home/rmk/linux-2.6-arm: (161 commits)
  ARM: pxa: fix building issue of missing physmap.h
  ARM: mmp: PXA910 drive strength FAST using wrong value
  ARM: mmp: MMP2 drive strength FAST using wrong value
  ARM: pxa: fix recursive calls in pxa_low_gpio_chip
  AT91: Support for gsia18s board
  AT91: Acme Systems FOX Board G20 board files
  AT91: board-sam9m10g45ek.c: Remove duplicate inclusion of mach/hardware.h
  ARM: pxa: fix suspend/resume array index miscalculation
  ARM: pxa: use cpu_has_ipr() consistently in irq.c
  ARM: pxa: remove unused variable in clock-pxa3xx.c
  ARM: pxa: fix warning in zeus.c
  ARM: sa1111: fix typo in sa1111_retrigger_lowirq()
  ARM mxs: clkdev related compile fixes
  ARM i.MX mx31_3ds: Fix MC13783 regulator names
  ARM: plat-stmp3xxx: irq_data conversion.
  ARM: plat-spear: irq_data conversion.
  ARM: plat-orion: irq_data conversion.
  ARM: plat-omap: irq_data conversion.
  ARM: plat-nomadik: irq_data conversion.
  ARM: plat-mxc: irq_data conversion.
  ...

Fix up trivial conflict in arch/arm/plat-omap/gpio.c (Lennert
Buytenhek's irq_data conversion clashing with some omap irq updates)

249 files changed, 6533 insertions, 2396 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 629ff8261fc1..5cff165b7eb0 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -26,6 +26,8 @@ config ARM
         select HAVE_REGS_AND_STACK_ACCESS_API
         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V7))
         select HAVE_C_RECORDMCOUNT
+        select HAVE_GENERIC_HARDIRQS
+        select HAVE_SPARSE_IRQ
         help
           The ARM series is a line of low-power-consumption RISC chip designs
           licensed by ARM Ltd and targeted at embedded applications and
@@ -97,10 +99,6 @@ config MCA
           <file:Documentation/mca.txt> (and especially the web page given
           there) before attempting to build an MCA bus kernel.
 
-config GENERIC_HARDIRQS
-        bool
-        default y
-
 config STACKTRACE_SUPPORT
         bool
         default y
@@ -180,9 +178,6 @@ config FIQ
 config ARCH_MTD_XIP
         bool
 
-config GENERIC_HARDIRQS_NO__DO_IRQ
-        def_bool y
-
 config ARM_L1_CACHE_SHIFT_6
         bool
         help
@@ -368,7 +363,7 @@ config ARCH_MXS
         bool "Freescale MXS-based"
         select GENERIC_CLOCKEVENTS
         select ARCH_REQUIRE_GPIOLIB
-        select COMMON_CLKDEV
+        select CLKDEV_LOOKUP
         help
           Support for Freescale MXS-based family of processors
 
@@ -771,6 +766,7 @@ config ARCH_S5PV310
         select ARCH_SPARSEMEM_ENABLE
         select GENERIC_GPIO
         select HAVE_CLK
+        select ARCH_HAS_CPUFREQ
         select GENERIC_CLOCKEVENTS
         select HAVE_S3C_RTC if RTC_CLASS
         select HAVE_S3C2410_I2C if I2C
@@ -1452,15 +1448,6 @@ config HW_PERF_EVENTS
           Enable hardware performance counter support for perf events. If
           disabled, perf events will use software events only.
 
-config SPARSE_IRQ
-        def_bool n
-        help
-          This enables support for sparse irqs. This is useful in general
-          as most CPUs have a fairly sparse array of IRQ vectors, which
-          the irq_desc then maps directly on to. Systems with a high
-          number of off-chip IRQs will want to treat this as
-          experimental until they have been independently verified.
-
 source "mm/Kconfig"
 
 config FORCE_MAX_ZONEORDER
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 0b89ef001330..224377211151 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -50,57 +50,56 @@ struct gic_chip_data {
 
 static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
 
-static inline void __iomem *gic_dist_base(unsigned int irq)
+static inline void __iomem *gic_dist_base(struct irq_data *d)
 {
-        struct gic_chip_data *gic_data = get_irq_chip_data(irq);
+        struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
         return gic_data->dist_base;
 }
 
-static inline void __iomem *gic_cpu_base(unsigned int irq)
+static inline void __iomem *gic_cpu_base(struct irq_data *d)
 {
-        struct gic_chip_data *gic_data = get_irq_chip_data(irq);
+        struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
         return gic_data->cpu_base;
 }
 
-static inline unsigned int gic_irq(unsigned int irq)
+static inline unsigned int gic_irq(struct irq_data *d)
 {
-        struct gic_chip_data *gic_data = get_irq_chip_data(irq);
-        return irq - gic_data->irq_offset;
+        struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
+        return d->irq - gic_data->irq_offset;
 }
 
 /*
  * Routines to acknowledge, disable and enable interrupts
  */
-static void gic_ack_irq(unsigned int irq)
+static void gic_ack_irq(struct irq_data *d)
 {
-
         spin_lock(&irq_controller_lock);
-        writel(gic_irq(irq), gic_cpu_base(irq) + GIC_CPU_EOI);
+        writel(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
         spin_unlock(&irq_controller_lock);
 }
 
-static void gic_mask_irq(unsigned int irq)
+static void gic_mask_irq(struct irq_data *d)
 {
-        u32 mask = 1 << (irq % 32);
+        u32 mask = 1 << (d->irq % 32);
 
         spin_lock(&irq_controller_lock);
-        writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_CLEAR + (gic_irq(irq) / 32) * 4);
+        writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
         spin_unlock(&irq_controller_lock);
 }
 
-static void gic_unmask_irq(unsigned int irq)
+static void gic_unmask_irq(struct irq_data *d)
 {
-        u32 mask = 1 << (irq % 32);
+        u32 mask = 1 << (d->irq % 32);
 
         spin_lock(&irq_controller_lock);
-        writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_SET + (gic_irq(irq) / 32) * 4);
+        writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
         spin_unlock(&irq_controller_lock);
 }
 
-static int gic_set_type(unsigned int irq, unsigned int type)
+static int gic_set_type(struct irq_data *d, unsigned int type)
 {
-        void __iomem *base = gic_dist_base(irq);
-        unsigned int gicirq = gic_irq(irq);
+        void __iomem *base = gic_dist_base(d);
+        unsigned int gicirq = gic_irq(d);
         u32 enablemask = 1 << (gicirq % 32);
         u32 enableoff = (gicirq / 32) * 4;
         u32 confmask = 0x2 << ((gicirq % 16) * 2);
@@ -143,21 +142,22 @@ static int gic_set_type(unsigned int irq, unsigned int type)
 }
 
 #ifdef CONFIG_SMP
-static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val)
+static int
+gic_set_cpu(struct irq_data *d, const struct cpumask *mask_val, bool force)
 {
-        void __iomem *reg = gic_dist_base(irq) + GIC_DIST_TARGET + (gic_irq(irq) & ~3);
-        unsigned int shift = (irq % 4) * 8;
+        void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
+        unsigned int shift = (d->irq % 4) * 8;
         unsigned int cpu = cpumask_first(mask_val);
         u32 val;
         struct irq_desc *desc;
 
         spin_lock(&irq_controller_lock);
-        desc = irq_to_desc(irq);
+        desc = irq_to_desc(d->irq);
         if (desc == NULL) {
                 spin_unlock(&irq_controller_lock);
                 return -EINVAL;
         }
-        desc->node = cpu;
+        d->node = cpu;
         val = readl(reg) & ~(0xff << shift);
         val |= 1 << (cpu + shift);
         writel(val, reg);
@@ -175,7 +175,7 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
         unsigned long status;
 
         /* primary controller ack'ing */
-        chip->ack(irq);
+        chip->irq_ack(&desc->irq_data);
 
         spin_lock(&irq_controller_lock);
         status = readl(chip_data->cpu_base + GIC_CPU_INTACK);
@@ -193,17 +193,17 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 
  out:
         /* primary controller unmasking */
-        chip->unmask(irq);
+        chip->irq_unmask(&desc->irq_data);
 }
 
 static struct irq_chip gic_chip = {
-        .name           = "GIC",
-        .ack            = gic_ack_irq,
-        .mask           = gic_mask_irq,
-        .unmask         = gic_unmask_irq,
-        .set_type       = gic_set_type,
+        .name                   = "GIC",
+        .irq_ack                = gic_ack_irq,
+        .irq_mask               = gic_mask_irq,
+        .irq_unmask             = gic_unmask_irq,
+        .irq_set_type           = gic_set_type,
 #ifdef CONFIG_SMP
-        .set_affinity   = gic_set_cpu,
+        .irq_set_affinity       = gic_set_cpu,
 #endif
 };
 
@@ -337,7 +337,7 @@ void __cpuinit gic_enable_ppi(unsigned int irq)
 
         local_irq_save(flags);
         irq_to_desc(irq)->status |= IRQ_NOPROBE;
-        gic_unmask_irq(irq);
+        gic_unmask_irq(irq_get_irq_data(irq));
         local_irq_restore(flags);
 }
 
diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
index 665ebf7e62a6..fcddd48fe9da 100644
--- a/arch/arm/common/it8152.c
+++ b/arch/arm/common/it8152.c
@@ -31,8 +31,10 @@
 
 #define MAX_SLOTS               21
 
-static void it8152_mask_irq(unsigned int irq)
+static void it8152_mask_irq(struct irq_data *d)
 {
+        unsigned int irq = d->irq;
+
        if (irq >= IT8152_LD_IRQ(0)) {
                __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) |
                             (1 << (irq - IT8152_LD_IRQ(0)))),
@@ -48,8 +50,10 @@ static void it8152_mask_irq(unsigned int irq)
        }
 }
 
-static void it8152_unmask_irq(unsigned int irq)
+static void it8152_unmask_irq(struct irq_data *d)
 {
+        unsigned int irq = d->irq;
+
        if (irq >= IT8152_LD_IRQ(0)) {
                __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) &
                              ~(1 << (irq - IT8152_LD_IRQ(0)))),
@@ -67,9 +71,9 @@ static void it8152_unmask_irq(unsigned int irq)
 
 static struct irq_chip it8152_irq_chip = {
         .name           = "it8152",
-        .ack            = it8152_mask_irq,
-        .mask           = it8152_mask_irq,
-        .unmask         = it8152_unmask_irq,
+        .irq_ack        = it8152_mask_irq,
+        .irq_mask       = it8152_mask_irq,
+        .irq_unmask     = it8152_unmask_irq,
 };
 
 void it8152_init_irq(void)
diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c
index 9dff07c80ddb..a026a6bf4892 100644
--- a/arch/arm/common/locomo.c
+++ b/arch/arm/common/locomo.c
@@ -144,7 +144,7 @@ static void locomo_handler(unsigned int irq, struct irq_desc *desc)
         int req, i;
 
         /* Acknowledge the parent IRQ */
-        desc->chip->ack(irq);
+        desc->irq_data.chip->irq_ack(&desc->irq_data);
 
         /* check why this interrupt was generated */
         req = locomo_readl(lchip->base + LOCOMO_ICR) & 0x0f00;
@@ -161,33 +161,33 @@ static void locomo_handler(unsigned int irq, struct irq_desc *desc)
         }
 }
 
-static void locomo_ack_irq(unsigned int irq)
+static void locomo_ack_irq(struct irq_data *d)
 {
 }
 
-static void locomo_mask_irq(unsigned int irq)
+static void locomo_mask_irq(struct irq_data *d)
 {
-        struct locomo *lchip = get_irq_chip_data(irq);
+        struct locomo *lchip = irq_data_get_irq_chip_data(d);
         unsigned int r;
         r = locomo_readl(lchip->base + LOCOMO_ICR);
-        r &= ~(0x0010 << (irq - lchip->irq_base));
+        r &= ~(0x0010 << (d->irq - lchip->irq_base));
         locomo_writel(r, lchip->base + LOCOMO_ICR);
 }
 
-static void locomo_unmask_irq(unsigned int irq)
+static void locomo_unmask_irq(struct irq_data *d)
 {
-        struct locomo *lchip = get_irq_chip_data(irq);
+        struct locomo *lchip = irq_data_get_irq_chip_data(d);
         unsigned int r;
         r = locomo_readl(lchip->base + LOCOMO_ICR);
-        r |= (0x0010 << (irq - lchip->irq_base));
+        r |= (0x0010 << (d->irq - lchip->irq_base));
         locomo_writel(r, lchip->base + LOCOMO_ICR);
 }
 
 static struct irq_chip locomo_chip = {
-        .name   = "LOCOMO",
-        .ack    = locomo_ack_irq,
-        .mask   = locomo_mask_irq,
-        .unmask = locomo_unmask_irq,
+        .name           = "LOCOMO",
+        .irq_ack        = locomo_ack_irq,
+        .irq_mask       = locomo_mask_irq,
+        .irq_unmask     = locomo_unmask_irq,
 };
 
 static void locomo_setup_irq(struct locomo *lchip)
diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c
index c0258a8c103b..eb9796b0dab2 100644
--- a/arch/arm/common/sa1111.c
+++ b/arch/arm/common/sa1111.c
@@ -210,7 +210,7 @@ sa1111_irq_handler(unsigned int irq, struct irq_desc *desc)
 
         sa1111_writel(stat0, mapbase + SA1111_INTSTATCLR0);
 
-        desc->chip->ack(irq);
+        desc->irq_data.chip->irq_ack(&desc->irq_data);
 
         sa1111_writel(stat1, mapbase + SA1111_INTSTATCLR1);
 
@@ -228,35 +228,35 @@ sa1111_irq_handler(unsigned int irq, struct irq_desc *desc)
                         generic_handle_irq(i + sachip->irq_base);
 
         /* For level-based interrupts */
-        desc->chip->unmask(irq);
+        desc->irq_data.chip->irq_unmask(&desc->irq_data);
 }
 
 #define SA1111_IRQMASK_LO(x)    (1 << (x - sachip->irq_base))
 #define SA1111_IRQMASK_HI(x)    (1 << (x - sachip->irq_base - 32))
 
-static void sa1111_ack_irq(unsigned int irq)
+static void sa1111_ack_irq(struct irq_data *d)
 {
 }
 
-static void sa1111_mask_lowirq(unsigned int irq)
+static void sa1111_mask_lowirq(struct irq_data *d)
 {
-        struct sa1111 *sachip = get_irq_chip_data(irq);
+        struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
         void __iomem *mapbase = sachip->base + SA1111_INTC;
         unsigned long ie0;
 
         ie0 = sa1111_readl(mapbase + SA1111_INTEN0);
-        ie0 &= ~SA1111_IRQMASK_LO(irq);
+        ie0 &= ~SA1111_IRQMASK_LO(d->irq);
         writel(ie0, mapbase + SA1111_INTEN0);
 }
 
-static void sa1111_unmask_lowirq(unsigned int irq)
+static void sa1111_unmask_lowirq(struct irq_data *d)
 {
-        struct sa1111 *sachip = get_irq_chip_data(irq);
+        struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
         void __iomem *mapbase = sachip->base + SA1111_INTC;
         unsigned long ie0;
 
         ie0 = sa1111_readl(mapbase + SA1111_INTEN0);
-        ie0 |= SA1111_IRQMASK_LO(irq);
+        ie0 |= SA1111_IRQMASK_LO(d->irq);
         sa1111_writel(ie0, mapbase + SA1111_INTEN0);
 }
 
@@ -267,11 +267,11 @@ static void sa1111_unmask_lowirq(unsigned int irq)
  * be triggered.  In fact, its very difficult, if not impossible to get
  * INTSET to re-trigger the interrupt.
  */
-static int sa1111_retrigger_lowirq(unsigned int irq)
+static int sa1111_retrigger_lowirq(struct irq_data *d)
 {
-        struct sa1111 *sachip = get_irq_chip_data(irq);
+        struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
         void __iomem *mapbase = sachip->base + SA1111_INTC;
-        unsigned int mask = SA1111_IRQMASK_LO(irq);
+        unsigned int mask = SA1111_IRQMASK_LO(d->irq);
         unsigned long ip0;
         int i;
 
@@ -279,21 +279,21 @@ static int sa1111_retrigger_lowirq(unsigned int irq)
         for (i = 0; i < 8; i++) {
                 sa1111_writel(ip0 ^ mask, mapbase + SA1111_INTPOL0);
                 sa1111_writel(ip0, mapbase + SA1111_INTPOL0);
-                if (sa1111_readl(mapbase + SA1111_INTSTATCLR1) & mask)
+                if (sa1111_readl(mapbase + SA1111_INTSTATCLR0) & mask)
                         break;
         }
 
         if (i == 8)
                 printk(KERN_ERR "Danger Will Robinson: failed to "
-                        "re-trigger IRQ%d\n", irq);
+                        "re-trigger IRQ%d\n", d->irq);
         return i == 8 ? -1 : 0;
 }
 
-static int sa1111_type_lowirq(unsigned int irq, unsigned int flags)
+static int sa1111_type_lowirq(struct irq_data *d, unsigned int flags)
 {
-        struct sa1111 *sachip = get_irq_chip_data(irq);
+        struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
         void __iomem *mapbase = sachip->base + SA1111_INTC;
-        unsigned int mask = SA1111_IRQMASK_LO(irq);
+        unsigned int mask = SA1111_IRQMASK_LO(d->irq);
         unsigned long ip0;
 
         if (flags == IRQ_TYPE_PROBE)
@@ -313,11 +313,11 @@ static int sa1111_type_lowirq(unsigned int irq, unsigned int flags)
         return 0;
 }
 
-static int sa1111_wake_lowirq(unsigned int irq, unsigned int on)
+static int sa1111_wake_lowirq(struct irq_data *d, unsigned int on)
 {
-        struct sa1111 *sachip = get_irq_chip_data(irq);
+        struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
         void __iomem *mapbase = sachip->base + SA1111_INTC;
-        unsigned int mask = SA1111_IRQMASK_LO(irq);
+        unsigned int mask = SA1111_IRQMASK_LO(d->irq);
         unsigned long we0;
 
         we0 = sa1111_readl(mapbase + SA1111_WAKEEN0);
@@ -332,33 +332,33 @@ static int sa1111_wake_lowirq(unsigned int irq, unsigned int on)
 
 static struct irq_chip sa1111_low_chip = {
         .name           = "SA1111-l",
-        .ack            = sa1111_ack_irq,
-        .mask           = sa1111_mask_lowirq,
-        .unmask         = sa1111_unmask_lowirq,
-        .retrigger      = sa1111_retrigger_lowirq,
-        .set_type       = sa1111_type_lowirq,
-        .set_wake       = sa1111_wake_lowirq,
+        .irq_ack        = sa1111_ack_irq,
+        .irq_mask       = sa1111_mask_lowirq,
+        .irq_unmask     = sa1111_unmask_lowirq,
+        .irq_retrigger  = sa1111_retrigger_lowirq,
+        .irq_set_type   = sa1111_type_lowirq,
+        .irq_set_wake   = sa1111_wake_lowirq,
 };
 
-static void sa1111_mask_highirq(unsigned int irq)
+static void sa1111_mask_highirq(struct irq_data *d)
 {
-        struct sa1111 *sachip = get_irq_chip_data(irq);
+        struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
         void __iomem *mapbase = sachip->base + SA1111_INTC;
         unsigned long ie1;
 
         ie1 = sa1111_readl(mapbase + SA1111_INTEN1);
-        ie1 &= ~SA1111_IRQMASK_HI(irq);
+        ie1 &= ~SA1111_IRQMASK_HI(d->irq);
         sa1111_writel(ie1, mapbase + SA1111_INTEN1);
 }
 
-static void sa1111_unmask_highirq(unsigned int irq)
+static void sa1111_unmask_highirq(struct irq_data *d)
 {
-        struct sa1111 *sachip = get_irq_chip_data(irq);
+        struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
         void __iomem *mapbase = sachip->base + SA1111_INTC;
         unsigned long ie1;
 
         ie1 = sa1111_readl(mapbase + SA1111_INTEN1);
-        ie1 |= SA1111_IRQMASK_HI(irq);
+        ie1 |= SA1111_IRQMASK_HI(d->irq);
         sa1111_writel(ie1, mapbase + SA1111_INTEN1);
 }
 
@@ -369,11 +369,11 @@ static void sa1111_unmask_highirq(unsigned int irq)
  * be triggered.  In fact, its very difficult, if not impossible to get
  * INTSET to re-trigger the interrupt.
  */
-static int sa1111_retrigger_highirq(unsigned int irq)
+static int sa1111_retrigger_highirq(struct irq_data *d)
 {
-        struct sa1111 *sachip = get_irq_chip_data(irq);
+        struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
         void __iomem *mapbase = sachip->base + SA1111_INTC;
-        unsigned int mask = SA1111_IRQMASK_HI(irq);
+        unsigned int mask = SA1111_IRQMASK_HI(d->irq);
         unsigned long ip1;
         int i;
 
@@ -387,15 +387,15 @@ static int sa1111_retrigger_highirq(unsigned int irq)
 
         if (i == 8)
                 printk(KERN_ERR "Danger Will Robinson: failed to "
-                        "re-trigger IRQ%d\n", irq);
+                        "re-trigger IRQ%d\n", d->irq);
         return i == 8 ? -1 : 0;
 }
 
-static int sa1111_type_highirq(unsigned int irq, unsigned int flags)
+static int sa1111_type_highirq(struct irq_data *d, unsigned int flags)
 {
-        struct sa1111 *sachip = get_irq_chip_data(irq);
+        struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
         void __iomem *mapbase = sachip->base + SA1111_INTC;
-        unsigned int mask = SA1111_IRQMASK_HI(irq);
+        unsigned int mask = SA1111_IRQMASK_HI(d->irq);
         unsigned long ip1;
 
         if (flags == IRQ_TYPE_PROBE)
@@ -415,11 +415,11 @@ static int sa1111_type_highirq(unsigned int irq, unsigned int flags)
         return 0;
 }
 
-static int sa1111_wake_highirq(unsigned int irq, unsigned int on)
+static int sa1111_wake_highirq(struct irq_data *d, unsigned int on)
 {
-        struct sa1111 *sachip = get_irq_chip_data(irq);
+        struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
         void __iomem *mapbase = sachip->base + SA1111_INTC;
-        unsigned int mask = SA1111_IRQMASK_HI(irq);
+        unsigned int mask = SA1111_IRQMASK_HI(d->irq);
         unsigned long we1;
 
         we1 = sa1111_readl(mapbase + SA1111_WAKEEN1);
@@ -434,12 +434,12 @@ static int sa1111_wake_highirq(unsigned int irq, unsigned int on)
 
 static struct irq_chip sa1111_high_chip = {
         .name           = "SA1111-h",
-        .ack            = sa1111_ack_irq,
-        .mask           = sa1111_mask_highirq,
-        .unmask         = sa1111_unmask_highirq,
-        .retrigger      = sa1111_retrigger_highirq,
-        .set_type       = sa1111_type_highirq,
-        .set_wake       = sa1111_wake_highirq,
+        .irq_ack        = sa1111_ack_irq,
+        .irq_mask       = sa1111_mask_highirq,
+        .irq_unmask     = sa1111_unmask_highirq,
+        .irq_retrigger  = sa1111_retrigger_highirq,
+        .irq_set_type   = sa1111_type_highirq,
+        .irq_set_wake   = sa1111_wake_highirq,
 };
 
 static void sa1111_setup_irq(struct sa1111 *sachip)
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
index cb660bc54d7a..ae5fe7292e0d 100644
--- a/arch/arm/common/vic.c
+++ b/arch/arm/common/vic.c
@@ -204,26 +204,26 @@ static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 res
 static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { }
 #endif /* CONFIG_PM */
 
-static void vic_ack_irq(unsigned int irq)
+static void vic_ack_irq(struct irq_data *d)
 {
-        void __iomem *base = get_irq_chip_data(irq);
-        irq &= 31;
+        void __iomem *base = irq_data_get_irq_chip_data(d);
+        unsigned int irq = d->irq & 31;
         writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
         /* moreover, clear the soft-triggered, in case it was the reason */
         writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
 }
 
-static void vic_mask_irq(unsigned int irq)
+static void vic_mask_irq(struct irq_data *d)
 {
-        void __iomem *base = get_irq_chip_data(irq);
-        irq &= 31;
+        void __iomem *base = irq_data_get_irq_chip_data(d);
+        unsigned int irq = d->irq & 31;
         writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
 }
 
-static void vic_unmask_irq(unsigned int irq)
+static void vic_unmask_irq(struct irq_data *d)
 {
-        void __iomem *base = get_irq_chip_data(irq);
-        irq &= 31;
+        void __iomem *base = irq_data_get_irq_chip_data(d);
+        unsigned int irq = d->irq & 31;
         writel(1 << irq, base + VIC_INT_ENABLE);
 }
 
@@ -242,10 +242,10 @@ static struct vic_device *vic_from_irq(unsigned int irq)
         return NULL;
 }
 
-static int vic_set_wake(unsigned int irq, unsigned int on)
+static int vic_set_wake(struct irq_data *d, unsigned int on)
 {
-        struct vic_device *v = vic_from_irq(irq);
-        unsigned int off = irq & 31;
+        struct vic_device *v = vic_from_irq(d->irq);
+        unsigned int off = d->irq & 31;
         u32 bit = 1 << off;
 
         if (!v)
@@ -267,10 +267,10 @@ static int vic_set_wake(unsigned int irq, unsigned int on)
 
 static struct irq_chip vic_chip = {
         .name           = "VIC",
-        .ack            = vic_ack_irq,
-        .mask           = vic_mask_irq,
-        .unmask         = vic_unmask_irq,
-        .set_wake       = vic_set_wake,
+        .irq_ack        = vic_ack_irq,
+        .irq_mask       = vic_mask_irq,
+        .irq_unmask     = vic_unmask_irq,
+        .irq_set_wake   = vic_set_wake,
 };
 
 static void __init vic_disable(void __iomem *base)
diff --git a/arch/arm/kernel/ecard.c b/arch/arm/kernel/ecard.c
index eed2f795e1b3..2ad62df37730 100644
--- a/arch/arm/kernel/ecard.c
+++ b/arch/arm/kernel/ecard.c
@@ -443,40 +443,40 @@ static expansioncard_ops_t ecard_default_ops = {
  *
  * They are not meant to be called directly, but via enable/disable_irq.
  */
-static void ecard_irq_unmask(unsigned int irqnr)
+static void ecard_irq_unmask(struct irq_data *d)
 {
-        ecard_t *ec = slot_to_ecard(irqnr - 32);
+        ecard_t *ec = slot_to_ecard(d->irq - 32);
 
         if (ec) {
                 if (!ec->ops)
                         ec->ops = &ecard_default_ops;
 
                 if (ec->claimed && ec->ops->irqenable)
-                        ec->ops->irqenable(ec, irqnr);
+                        ec->ops->irqenable(ec, d->irq);
                 else
                         printk(KERN_ERR "ecard: rejecting request to "
-                                "enable IRQs for %d\n", irqnr);
+                                "enable IRQs for %d\n", d->irq);
         }
 }
 
-static void ecard_irq_mask(unsigned int irqnr)
+static void ecard_irq_mask(struct irq_data *d)
 {
-        ecard_t *ec = slot_to_ecard(irqnr - 32);
+        ecard_t *ec = slot_to_ecard(d->irq - 32);
 
         if (ec) {
                 if (!ec->ops)
                         ec->ops = &ecard_default_ops;
 
                 if (ec->ops && ec->ops->irqdisable)
-                        ec->ops->irqdisable(ec, irqnr);
+                        ec->ops->irqdisable(ec, d->irq);
         }
 }
 
 static struct irq_chip ecard_chip = {
-        .name   = "ECARD",
-        .ack    = ecard_irq_mask,
-        .mask   = ecard_irq_mask,
-        .unmask = ecard_irq_unmask,
+        .name           = "ECARD",
+        .irq_ack        = ecard_irq_mask,
+        .irq_mask       = ecard_irq_mask,
+        .irq_unmask     = ecard_irq_unmask,
 };
 
 void ecard_enablefiq(unsigned int fiqnr)
@@ -551,7 +551,7 @@ static void ecard_check_lockup(struct irq_desc *desc)
                         printk(KERN_ERR "\nInterrupt lockup detected - "
                                "disabling all expansion card interrupts\n");
 
-                        desc->chip->mask(IRQ_EXPANSIONCARD);
+                        desc->irq_data.chip->irq_mask(&desc->irq_data);
                         ecard_dump_irq_state();
                 }
         } else
@@ -574,7 +574,7 @@ ecard_irq_handler(unsigned int irq, struct irq_desc *desc)
         ecard_t *ec;
         int called = 0;
 
-        desc->chip->mask(irq);
+        desc->irq_data.chip->irq_mask(&desc->irq_data);
         for (ec = cards; ec; ec = ec->next) {
                 int pending;
 
@@ -591,7 +591,7 @@ ecard_irq_handler(unsigned int irq, struct irq_desc *desc)
                         called ++;
                 }
         }
-        desc->chip->unmask(irq);
+        desc->irq_data.chip->irq_unmask(&desc->irq_data);
 
         if (called == 0)
                 ecard_check_lockup(desc);
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 8135438b8818..28536e352deb 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -88,7 +88,7 @@ int show_interrupts(struct seq_file *p, void *v)
                 seq_printf(p, "%*d: ", prec, i);
                 for_each_present_cpu(cpu)
                         seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu));
-                seq_printf(p, " %10s", desc->chip->name ? : "-");
+                seq_printf(p, " %10s", desc->irq_data.chip->name ? : "-");
                 seq_printf(p, "  %s", action->name);
                 for (action = action->next; action; action = action->next)
                         seq_printf(p, ", %s", action->name);
@@ -181,10 +181,11 @@ int __init arch_probe_nr_irqs(void)
 
 static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu)
 {
-        pr_debug("IRQ%u: moving from cpu%u to cpu%u\n", irq, desc->node, cpu);
+        pr_debug("IRQ%u: moving from cpu%u to cpu%u\n", irq, desc->irq_data.node, cpu);
 
         raw_spin_lock_irq(&desc->lock);
-        desc->chip->set_affinity(irq, cpumask_of(cpu));
+        desc->irq_data.chip->irq_set_affinity(&desc->irq_data,
+                                              cpumask_of(cpu), false);
         raw_spin_unlock_irq(&desc->lock);
 }
 
@@ -199,16 +200,18 @@ void migrate_irqs(void)
         struct irq_desc *desc;
 
         for_each_irq_desc(i, desc) {
-                if (desc->node == cpu) {
-                        unsigned int newcpu = cpumask_any_and(desc->affinity,
+                struct irq_data *d = &desc->irq_data;
+
+                if (d->node == cpu) {
+                        unsigned int newcpu = cpumask_any_and(d->affinity,
                                                               cpu_online_mask);
                         if (newcpu >= nr_cpu_ids) {
                                 if (printk_ratelimit())
                                         printk(KERN_INFO "IRQ%u no longer affine to CPU%u\n",
                                                i, cpu);
 
-                                cpumask_setall(desc->affinity);
-                                newcpu = cpumask_any_and(desc->affinity,
+                                cpumask_setall(d->affinity);
+                                newcpu = cpumask_any_and(d->affinity,
                                                          cpu_online_mask);
                         }
 
diff --git a/arch/arm/mach-aaec2000/core.c b/arch/arm/mach-aaec2000/core.c
index 3ef68330452a..f8465bd17e67 100644
--- a/arch/arm/mach-aaec2000/core.c
+++ b/arch/arm/mach-aaec2000/core.c
@@ -68,25 +68,25 @@ void __init aaec2000_map_io(void)
 /*
  * Interrupt handling routines
  */
-static void aaec2000_int_ack(unsigned int irq)
+static void aaec2000_int_ack(struct irq_data *d)
 {
-        IRQ_INTSR = 1 << irq;
+        IRQ_INTSR = 1 << d->irq;
 }
 
-static void aaec2000_int_mask(unsigned int irq)
+static void aaec2000_int_mask(struct irq_data *d)
 {
-        IRQ_INTENC |= (1 << irq);
+        IRQ_INTENC |= (1 << d->irq);
 }
 
-static void aaec2000_int_unmask(unsigned int irq)
+static void aaec2000_int_unmask(struct irq_data *d)
 {
-        IRQ_INTENS |= (1 << irq);
+        IRQ_INTENS |= (1 << d->irq);
 }
 
 static struct irq_chip aaec2000_irq_chip = {
-        .ack    = aaec2000_int_ack,
-        .mask   = aaec2000_int_mask,
-        .unmask = aaec2000_int_unmask,
+        .irq_ack        = aaec2000_int_ack,
+        .irq_mask       = aaec2000_int_mask,
+        .irq_unmask     = aaec2000_int_unmask,
 };
 
 void __init aaec2000_init_irq(void)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index c015b684b4fe..19390231a0e9 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -362,6 +362,12 @@ config MACH_CPU9G20
           Select this if you are using a Eukrea Electromatique's
           CPU9G20 Board <http://www.eukrea.com/>
 
+config MACH_ACMENETUSFOXG20
+        bool "Acme Systems srl FOX Board G20"
+        help
+          Select this if you are using Acme Systems
+          FOX Board G20 <http://www.acmesystems.it>
+
 config MACH_PORTUXG20
         bool "taskit PortuxG20"
         help
@@ -381,6 +387,13 @@ config MACH_PCONTROL_G20
           Select this if you are using taskit's Stamp9G20 CPU module on this
           carrier board, beeing the decentralized unit of a building automation
           system; featuring nvram, eth-switch, iso-rs485, display, io
+
+config MACH_GSIA18S
+        bool "GS_IA18_S board"
+        help
+          This enables support for the GS_IA18_S board
+          produced by GeoSIG Ltd company. This is an internet accelerograph.
+          <http://www.geosig.com>
 endif
 
 if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20)
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index d13add71f72a..a83835e0c185 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -63,9 +63,11 @@ obj-$(CONFIG_MACH_AT91SAM9RLEK)	+= board-sam9rlek.o
 # AT91SAM9G20 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o
 obj-$(CONFIG_MACH_CPU9G20)      += board-cpu9krea.o
+obj-$(CONFIG_MACH_ACMENETUSFOXG20) += board-foxg20.o
 obj-$(CONFIG_MACH_STAMP9G20)    += board-stamp9g20.o
 obj-$(CONFIG_MACH_PORTUXG20)    += board-stamp9g20.o
 obj-$(CONFIG_MACH_PCONTROL_G20) += board-pcontrol-g20.o board-stamp9g20.o
+obj-$(CONFIG_MACH_GSIA18S)      += board-gsia18s.o board-stamp9g20.o
 
 # AT91SAM9260/AT91SAM9G20 board-specific support
 obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o
diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c
new file mode 100644
index 000000000000..dfc7dfe738e4
--- /dev/null
+++ b/arch/arm/mach-at91/board-foxg20.c
@@ -0,0 +1,274 @@
+/*
+ *  Copyright (C) 2005 SAN People
+ *  Copyright (C) 2008 Atmel
+ *  Copyright (C) 2010 Lee McLoughlin - lee@lmmrtech.com
+ *  Copyright (C) 2010 Sergio Tanzilli - tanzilli@acmesystems.it
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/at73c213.h>
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/clk.h>
+#include <linux/w1-gpio.h>
+
+#include <mach/hardware.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <mach/board.h>
+#include <mach/at91sam9_smc.h>
+
+#include "sam9_smc.h"
+#include "generic.h"
+
+/*
+ * The FOX Board G20 hardware comes as the "Netus G20" board with
+ * just the cpu, ram, dataflash and two header connectors.
+ * This is plugged into the FOX Board which provides the ethernet,
+ * usb, rtc, leds, switch, ...
+ *
+ * For more info visit: http://www.acmesystems.it/foxg20
+ */
+
+
+static void __init foxg20_map_io(void)
+{
+        /* Initialize processor: 18.432 MHz crystal */
+        at91sam9260_initialize(18432000);
+
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91SAM9260_ID_US0, 1,
+                                ATMEL_UART_CTS
+                                | ATMEL_UART_RTS
+                                | ATMEL_UART_DTR
+                                | ATMEL_UART_DSR
+                                | ATMEL_UART_DCD
+                                | ATMEL_UART_RI);
+
+        /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
+        at91_register_uart(AT91SAM9260_ID_US1, 2,
+                ATMEL_UART_CTS
+                | ATMEL_UART_RTS);
+
+        /* USART2 on ttyS3. (Rx & Tx only) */
+        at91_register_uart(AT91SAM9260_ID_US2, 3, 0);
+
+        /* USART3 on ttyS4. (Rx, Tx, RTS, CTS) */
+        at91_register_uart(AT91SAM9260_ID_US3, 4,
+                ATMEL_UART_CTS
+                | ATMEL_UART_RTS);
+
+        /* USART4 on ttyS5. (Rx & Tx only) */
+        at91_register_uart(AT91SAM9260_ID_US4, 5, 0);
+
+        /* USART5 on ttyS6. (Rx & Tx only) */
+        at91_register_uart(AT91SAM9260_ID_US5, 6, 0);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
+
+        /* Set the internal pull-up resistor on DRXD */
+        at91_set_A_periph(AT91_PIN_PB14, 1);
+
+}
+
+static void __init foxg20_init_irq(void)
+{
+        at91sam9260_init_interrupts(NULL);
+}
+
+
+/*
+ * USB Host port
+ */
+static struct at91_usbh_data __initdata foxg20_usbh_data = {
+        .ports          = 2,
+};
+
+/*
+ * USB Device port
+ */
+static struct at91_udc_data __initdata foxg20_udc_data = {
+        .vbus_pin       = AT91_PIN_PC6,
+        .pullup_pin     = 0,            /* pull-up driven by UDC */
+};
+
+
+/*
+ * SPI devices.
+ */
+static struct spi_board_info foxg20_spi_devices[] = {
+#if !defined(CONFIG_MMC_AT91)
+        {
+                .modalias       = "mtd_dataflash",
+                .chip_select    = 1,
+                .max_speed_hz   = 15 * 1000 * 1000,
+                .bus_num        = 0,
+        },
+#endif
+};
+
+
+/*
+ * MACB Ethernet device
+ */
+static struct at91_eth_data __initdata foxg20_macb_data = {
+        .phy_irq_pin    = AT91_PIN_PA7,
+        .is_rmii        = 1,
+};
+
+/*
+ * MCI (SD/MMC)
+ * det_pin, wp_pin and vcc_pin are not connected
+ */
+static struct at91_mmc_data __initdata foxg20_mmc_data = {
+        .slot_b         = 1,
+        .wire4          = 1,
+};
+
+
+/*
+ * LEDs
+ */
+static struct gpio_led foxg20_leds[] = {
+        {       /* user led, red */
+                .name                   = "user_led",
+                .gpio                   = AT91_PIN_PC7,
+                .active_low             = 0,
+                .default_trigger        = "heartbeat",
+        },
+};
+
+
+/*
+ * GPIO Buttons
+ */
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+static struct gpio_keys_button foxg20_buttons[] = {
+        {
+                .gpio           = AT91_PIN_PC4,
+                .code           = BTN_1,
+                .desc           = "Button 1",
+                .active_low     = 1,
+                .wakeup         = 1,
+        },
+};
+
+static struct gpio_keys_platform_data foxg20_button_data = {
+        .buttons        = foxg20_buttons,
+        .nbuttons       = ARRAY_SIZE(foxg20_buttons),
+};
+
+static struct platform_device foxg20_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &foxg20_button_data,
+        }
+};
+
+static void __init foxg20_add_device_buttons(void)
+{
+        at91_set_gpio_input(AT91_PIN_PC4, 1);   /* btn1 */
+        at91_set_deglitch(AT91_PIN_PC4, 1);
+
+        platform_device_register(&foxg20_button_device);
+}
+#else
+static void __init foxg20_add_device_buttons(void) {}
+#endif
+
+
+#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE)
+static struct w1_gpio_platform_data w1_gpio_pdata = {
+        /* If you choose to use a pin other than PB16 it needs to be 3.3V */
+        .pin            = AT91_PIN_PB16,
+        .is_open_drain  = 1,
+};
+
+static struct platform_device w1_device = {
+        .name                   = "w1-gpio",
+        .id                     = -1,
+        .dev.platform_data      = &w1_gpio_pdata,
+};
+
+static void __init at91_add_device_w1(void)
+{
+        at91_set_GPIO_periph(w1_gpio_pdata.pin, 1);
+        at91_set_multi_drive(w1_gpio_pdata.pin, 1);
+        platform_device_register(&w1_device);
+}
+
+#endif
+
+
+static struct i2c_board_info __initdata foxg20_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("24c512", 0x50),
+        },
+};
+
+
+static void __init foxg20_board_init(void)
+{
+        /* Serial */
+        at91_add_device_serial();
+        /* USB Host */
+        at91_add_device_usbh(&foxg20_usbh_data);
+        /* USB Device */
+        at91_add_device_udc(&foxg20_udc_data);
+        /* SPI */
+        at91_add_device_spi(foxg20_spi_devices, ARRAY_SIZE(foxg20_spi_devices));
+        /* Ethernet */
+        at91_add_device_eth(&foxg20_macb_data);
+        /* MMC */
+        at91_add_device_mmc(0, &foxg20_mmc_data);
+        /* I2C */
+        at91_add_device_i2c(foxg20_i2c_devices, ARRAY_SIZE(foxg20_i2c_devices));
+        /* LEDs */
+        at91_gpio_leds(foxg20_leds, ARRAY_SIZE(foxg20_leds));
+        /* Push Buttons */
+        foxg20_add_device_buttons();
+#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE)
+        at91_add_device_w1();
+#endif
+}
+
+MACHINE_START(ACMENETUSFOXG20, "Acme Systems srl FOX Board G20")
+        /* Maintainer: Sergio Tanzilli */
+        .boot_params    = AT91_SDRAM_BASE + 0x100,
+        .timer          = &at91sam926x_timer,
+        .map_io         = foxg20_map_io,
+        .init_irq       = foxg20_init_irq,
+        .init_machine   = foxg20_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c
new file mode 100644
index 000000000000..bc28136ee249
--- /dev/null
+++ b/arch/arm/mach-at91/board-gsia18s.c
@@ -0,0 +1,584 @@
+/*
+ *  Copyright (C) 2010 Christian Glindkamp <christian.glindkamp@taskit.de>
+ *                     taskit GmbH
+ *                2010 Igor Plyatov <plyatov@gmail.com>
+ *                     GeoSIG Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/w1-gpio.h>
+#include <linux/i2c.h>
+#include <linux/i2c/pcf857x.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#include <mach/board.h>
+#include <mach/at91sam9_smc.h>
+#include <mach/gsia18s.h>
+#include <mach/stamp9g20.h>
+
+#include "sam9_smc.h"
+#include "generic.h"
+
+static void __init gsia18s_map_io(void)
+{
+        stamp9g20_map_io();
+
+        /*
+         * USART0 on ttyS1 (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI).
+         * Used for Internal Analog Modem.
+         */
+        at91_register_uart(AT91SAM9260_ID_US0, 1,
+                                ATMEL_UART_CTS | ATMEL_UART_RTS |
+                                ATMEL_UART_DTR | ATMEL_UART_DSR |
+                                ATMEL_UART_DCD | ATMEL_UART_RI);
+        /*
+         * USART1 on ttyS2 (Rx, Tx, CTS, RTS).
+         * Used for GPS or WiFi or Data stream.
+         */
+        at91_register_uart(AT91SAM9260_ID_US1, 2,
+                                ATMEL_UART_CTS | ATMEL_UART_RTS);
+        /*
+         * USART2 on ttyS3 (Rx, Tx, CTS, RTS).
+         * Used for External Modem.
+         */
+        at91_register_uart(AT91SAM9260_ID_US2, 3,
+                                ATMEL_UART_CTS | ATMEL_UART_RTS);
+        /*
+         * USART3 on ttyS4 (Rx, Tx, RTS).
+         * Used for RS-485.
+         */
+        at91_register_uart(AT91SAM9260_ID_US3, 4, ATMEL_UART_RTS);
+
+        /*
+         * USART4 on ttyS5 (Rx, Tx).
+         * Used for TRX433 Radio Module.
+         */
+        at91_register_uart(AT91SAM9260_ID_US4, 5, 0);
+}
+
+static void __init init_irq(void)
+{
+        at91sam9260_init_interrupts(NULL);
+}
+
+/*
+ * Two USB Host ports
+ */
+static struct at91_usbh_data __initdata usbh_data = {
+        .ports          = 2,
+};
+
+/*
+ * USB Device port
+ */
+static struct at91_udc_data __initdata udc_data = {
+        .vbus_pin       = AT91_PIN_PA22,
+        .pullup_pin     = 0,            /* pull-up driven by UDC */
+};
+
+/*
+ * MACB Ethernet device
+ */
+static struct at91_eth_data __initdata macb_data = {
+        .phy_irq_pin    = AT91_PIN_PA28,
+        .is_rmii        = 1,
+};
+
+/*
+ * LEDs and GPOs
+ */
+static struct gpio_led gpio_leds[] = {
+        {
+                .name                   = "gpo:spi1reset",
+                .gpio                   = AT91_PIN_PC1,
+                .active_low             = 0,
+                .default_trigger        = "none",
+                .default_state          = LEDS_GPIO_DEFSTATE_OFF,
+        },
+        {
+                .name                   = "gpo:trig_net_out",
+                .gpio                   = AT91_PIN_PB20,
+                .active_low             = 0,
+                .default_trigger        = "none",
+                .default_state          = LEDS_GPIO_DEFSTATE_OFF,
+        },
+        {
+                .name                   = "gpo:trig_net_dir",
+                .gpio                   = AT91_PIN_PB19,
+                .active_low             = 0,
+                .default_trigger        = "none",
+                .default_state          = LEDS_GPIO_DEFSTATE_OFF,
+        },
+        {
+                .name                   = "gpo:charge_dis",
+                .gpio                   = AT91_PIN_PC2,
+                .active_low             = 0,
+                .default_trigger        = "none",
+                .default_state          = LEDS_GPIO_DEFSTATE_OFF,
+        },
+        {
+                .name                   = "led:event",
+                .gpio                   = AT91_PIN_PB17,
+                .active_low             = 1,
+                .default_trigger        = "none",
+                .default_state          = LEDS_GPIO_DEFSTATE_OFF,
+        },
+        {
+                .name                   = "led:lan",
+                .gpio                   = AT91_PIN_PB18,
+                .active_low             = 1,
+                .default_trigger        = "none",
+                .default_state          = LEDS_GPIO_DEFSTATE_OFF,
+        },
+        {
+                .name                   = "led:error",
+                .gpio                   = AT91_PIN_PB16,
+                .active_low             = 1,
+                .default_trigger        = "none",
+                .default_state          = LEDS_GPIO_DEFSTATE_ON,
+        }
+};
+
+static struct gpio_led_platform_data gpio_led_info = {
+        .leds           = gpio_leds,
+        .num_leds       = ARRAY_SIZE(gpio_leds),
+};
+
+static struct platform_device leds = {
+        .name   = "leds-gpio",
+        .id     = 0,
+        .dev    = {
+                .platform_data  = &gpio_led_info,
+        }
+};
+
+static void __init gsia18s_leds_init(void)
+{
+        platform_device_register(&leds);
+}
+
+/* PCF8574 0x20 GPIO - U1 on the GS_IA18-CB_V3 board */
+static struct gpio_led pcf_gpio_leds1[] = {
+        { /* bit 0 */
+                .name                   = "gpo:hdc_power",
+                .gpio                   = PCF_GPIO_HDC_POWER,
+                .active_low             = 0,
+                .default_trigger        = "none",
+                .default_state          = LEDS_GPIO_DEFSTATE_OFF,
+        },
+        { /* bit 1 */
+                .name                   = "gpo:wifi_setup",
+                .gpio                   = PCF_GPIO_WIFI_SETUP,
+                .active_low             = 1,
+                .default_trigger        = "none",
+                .default_state          = LEDS_GPIO_DEFSTATE_OFF,
+        },
+        { /* bit 2 */
+                .name                   = "gpo:wifi_enable",
+                .gpio                   = PCF_GPIO_WIFI_ENABLE,
+                .active_low             = 1,
+                .default_trigger        = "none",
+                .default_state          = LEDS_GPIO_DEFSTATE_OFF,
+        },
+        { /* bit 3      */
+                .name                   = "gpo:wifi_reset",
+                .gpio                   = PCF_GPIO_WIFI_RESET,
+                .active_low             = 1,
+                .default_trigger        = "none",
+                .default_state          = LEDS_GPIO_DEFSTATE_ON,
+        },
+        /* bit 4 used as GPI    */
+        { /* bit 5 */
+                .name                   = "gpo:gps_setup",
+                .gpio                   = PCF_GPIO_GPS_SETUP,
+                .active_low             = 1,
+                .default_trigger        = "none",
+                .default_state          = LEDS_GPIO_DEFSTATE_OFF,
+        },
+        { /* bit 6 */
+                .name                   = "gpo:gps_standby",
+                .gpio                   = PCF_GPIO_GPS_STANDBY,
+                .active_low             = 0,
+                .default_trigger        = "none",
+                .default_state          = LEDS_GPIO_DEFSTATE_ON,
+        },
+        { /* bit 7 */
+                .name                   = "gpo:gps_power",
+                .gpio                   = PCF_GPIO_GPS_POWER,
+                .active_low             = 0,
+                .default_trigger        = "none",
+                .default_state          = LEDS_GPIO_DEFSTATE_OFF,
+        }
+};
+
+static struct gpio_led_platform_data pcf_gpio_led_info1 = {
+        .leds           = pcf_gpio_leds1,
+        .num_leds       = ARRAY_SIZE(pcf_gpio_leds1),
+};
+
+static struct platform_device pcf_leds1 = {
+        .name   = "leds-gpio", /* GS_IA18-CB_board */
+        .id     = 1,
+        .dev    = {
+                .platform_data  = &pcf_gpio_led_info1,
+        }
+};
+
+/* PCF8574 0x22 GPIO - U1 on the GS_2G_OPT1-A_V0 board (Alarm) */
+static struct gpio_led pcf_gpio_leds2[] = {
+        { /* bit 0 */
+                .name                   = "gpo:alarm_1",
+                .gpio                   = PCF_GPIO_ALARM1,
+                .active_low             = 1,
+                .default_trigger        = "none",
+                .default_state          = LEDS_GPIO_DEFSTATE_OFF,
+        },
+        { /* bit 1 */
+                .name                   = "gpo:alarm_2",
+                .gpio                   = PCF_GPIO_ALARM2,
+                .active_low             = 1,
+                .default_trigger        = "none",
+                .default_state          = LEDS_GPIO_DEFSTATE_OFF,
+        },
+        { /* bit 2 */
+                .name                   = "gpo:alarm_3",
+                .gpio                   = PCF_GPIO_ALARM3,
+                .active_low             = 1,
+                .default_trigger        = "none",
+                .default_state          = LEDS_GPIO_DEFSTATE_OFF,
+        },
+        { /* bit 3 */
+                .name                   = "gpo:alarm_4",
+                .gpio                   = PCF_GPIO_ALARM4,
+                .active_low             = 1,
+                .default_trigger        = "none",
+                .default_state          = LEDS_GPIO_DEFSTATE_OFF,
+        },
+        /* bits 4, 5, 6 not used */
+        { /* bit 7 */
+                .name                   = "gpo:alarm_v_relay_on",
+                .gpio                   = PCF_GPIO_ALARM_V_RELAY_ON,
+                .active_low             = 0,
+                .default_trigger        = "none",
+                .default_state          = LEDS_GPIO_DEFSTATE_OFF,
+        },
+};
+
+static struct gpio_led_platform_data pcf_gpio_led_info2 = {
+        .leds           = pcf_gpio_leds2,
+        .num_leds       = ARRAY_SIZE(pcf_gpio_leds2),
+};
+
+static struct platform_device pcf_leds2 = {
+        .name   = "leds-gpio",
+        .id     = 2,
+        .dev    = {
+                .platform_data  = &pcf_gpio_led_info2,
+        }
+};
+
+/* PCF8574 0x24 GPIO U1 on the GS_2G-OPT23-A_V0 board (Modem) */
+static struct gpio_led pcf_gpio_leds3[] = {
+        { /* bit 0 */
+                .name                   = "gpo:modem_power",
+                .gpio                   = PCF_GPIO_MODEM_POWER,
+                .active_low             = 1,
+                .default_trigger        = "none",
+                .default_state          = LEDS_GPIO_DEFSTATE_OFF,
+        },
+                /* bits 1 and 2 not used */
+        { /* bit 3 */
+                .name                   = "gpo:modem_reset",
+                .gpio                   = PCF_GPIO_MODEM_RESET,
+                .active_low             = 1,
+                .default_trigger        = "none",
+                .default_state          = LEDS_GPIO_DEFSTATE_ON,
+        },
+                /* bits 4, 5 and 6 not used */
+        { /* bit 7 */
+                .name                   = "gpo:trx_reset",
+                .gpio                   = PCF_GPIO_TRX_RESET,
+                .active_low             = 1,
+                .default_trigger        = "none",
+                .default_state          = LEDS_GPIO_DEFSTATE_ON,
+        }
+};
+
+static struct gpio_led_platform_data pcf_gpio_led_info3 = {
+        .leds           = pcf_gpio_leds3,
+        .num_leds       = ARRAY_SIZE(pcf_gpio_leds3),
+};
+
+static struct platform_device pcf_leds3 = {
+        .name   = "leds-gpio",
+        .id     = 3,
+        .dev    = {
+                .platform_data  = &pcf_gpio_led_info3,
+        }
+};
+
+static void __init gsia18s_pcf_leds_init(void)
+{
+        platform_device_register(&pcf_leds1);
+        platform_device_register(&pcf_leds2);
+        platform_device_register(&pcf_leds3);
+}
+
+/*
+ * SPI busses.
+ */
+static struct spi_board_info gsia18s_spi_devices[] = {
+        { /* User accessible spi0, cs0 used for communication with MSP RTC */
+                .modalias       = "spidev",
+                .bus_num        = 0,
+                .chip_select    = 0,
+                .max_speed_hz   = 580000,
+                .mode           = SPI_MODE_1,
+        },
+        { /* User accessible spi1, cs0 used for communication with int. DSP */
+                .modalias       = "spidev",
+                .bus_num        = 1,
+                .chip_select    = 0,
+                .max_speed_hz   = 5600000,
+                .mode           = SPI_MODE_0,
+        },
+        { /* User accessible spi1, cs1 used for communication with ext. DSP */
+                .modalias       = "spidev",
+                .bus_num        = 1,
+                .chip_select    = 1,
+                .max_speed_hz   = 5600000,
+                .mode           = SPI_MODE_0,
+        },
+        { /* User accessible spi1, cs2 used for communication with ext. DSP */
+                .modalias       = "spidev",
+                .bus_num        = 1,
+                .chip_select    = 2,
+                .max_speed_hz   = 5600000,
+                .mode           = SPI_MODE_0,
+        },
+        { /* User accessible spi1, cs3 used for communication with ext. DSP */
+                .modalias       = "spidev",
+                .bus_num        = 1,
+                .chip_select    = 3,
+                .max_speed_hz   = 5600000,
+                .mode           = SPI_MODE_0,
+        }
+};
+
+/*
+ * GPI Buttons
+ */
+static struct gpio_keys_button buttons[] = {
+        {
+                .gpio           = GPIO_TRIG_NET_IN,
+                .code           = BTN_1,
+                .desc           = "TRIG_NET_IN",
+                .type           = EV_KEY,
+                .active_low     = 0,
+                .wakeup         = 1,
+        },
+        { /* SW80 on the GS_IA18_S-MN board*/
+                .gpio           = GPIO_CARD_UNMOUNT_0,
+                .code           = BTN_2,
+                .desc           = "Card umount 0",
+                .type           = EV_KEY,
+                .active_low     = 1,
+                .wakeup         = 1,
+        },
+        { /* SW79 on the GS_IA18_S-MN board*/
+                .gpio           = GPIO_CARD_UNMOUNT_1,
+                .code           = BTN_3,
+                .desc           = "Card umount 1",
+                .type           = EV_KEY,
+                .active_low     = 1,
+                .wakeup         = 1,
+        },
+        { /* SW280 on the GS_IA18-CB board*/
+                .gpio           = GPIO_KEY_POWER,
+                .code           = KEY_POWER,
+                .desc           = "Power Off Button",
+                .type           = EV_KEY,
+                .active_low     = 0,
+                .wakeup         = 1,
+        }
+};
+
+static struct gpio_keys_platform_data button_data = {
+        .buttons        = buttons,
+        .nbuttons       = ARRAY_SIZE(buttons),
+};
+
+static struct platform_device button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &button_data,
+        }
+};
+
+static void __init gsia18s_add_device_buttons(void)
+{
+        at91_set_gpio_input(GPIO_TRIG_NET_IN, 1);
+        at91_set_deglitch(GPIO_TRIG_NET_IN, 1);
+        at91_set_gpio_input(GPIO_CARD_UNMOUNT_0, 1);
+        at91_set_deglitch(GPIO_CARD_UNMOUNT_0, 1);
+        at91_set_gpio_input(GPIO_CARD_UNMOUNT_1, 1);
+        at91_set_deglitch(GPIO_CARD_UNMOUNT_1, 1);
+        at91_set_gpio_input(GPIO_KEY_POWER, 0);
+        at91_set_deglitch(GPIO_KEY_POWER, 1);
+
+        platform_device_register(&button_device);
+}
+
+/*
+ * I2C
+ */
+static int pcf8574x_0x20_setup(struct i2c_client *client, int gpio,
+                                unsigned int ngpio, void *context)
+{
+        int status;
+
+        status = gpio_request(gpio + PCF_GPIO_ETH_DETECT, "eth_det");
+        if (status < 0) {
+                pr_err("error: can't request GPIO%d\n",
+                        gpio + PCF_GPIO_ETH_DETECT);
+                return status;
+        }
+        status = gpio_direction_input(gpio + PCF_GPIO_ETH_DETECT);
+        if (status < 0) {
+                pr_err("error: can't setup GPIO%d as input\n",
+                        gpio + PCF_GPIO_ETH_DETECT);
+                return status;
+        }
+        status = gpio_export(gpio + PCF_GPIO_ETH_DETECT, false);
+        if (status < 0) {
+                pr_err("error: can't export GPIO%d\n",
+                        gpio + PCF_GPIO_ETH_DETECT);
+                return status;
+        }
+        status = gpio_sysfs_set_active_low(gpio + PCF_GPIO_ETH_DETECT, 1);
+        if (status < 0) {
+                pr_err("error: gpio_sysfs_set active_low(GPIO%d, 1)\n",
+                        gpio + PCF_GPIO_ETH_DETECT);
+                return status;
+        }
+
+        return 0;
+}
+
+static int pcf8574x_0x20_teardown(struct i2c_client *client, int gpio,
+                                        unsigned ngpio, void *context)
+{
+        gpio_free(gpio + PCF_GPIO_ETH_DETECT);
+        return 0;
+}
+
+static struct pcf857x_platform_data pcf20_pdata = {
+        .gpio_base      = GS_IA18_S_PCF_GPIO_BASE0,
+        .n_latch        = (1 << 4),
+        .setup          = pcf8574x_0x20_setup,
+        .teardown       = pcf8574x_0x20_teardown,
+};
+
+static struct pcf857x_platform_data pcf22_pdata = {
+        .gpio_base      = GS_IA18_S_PCF_GPIO_BASE1,
+};
+
+static struct pcf857x_platform_data pcf24_pdata = {
+        .gpio_base      = GS_IA18_S_PCF_GPIO_BASE2,
+};
+
+static struct i2c_board_info __initdata gsia18s_i2c_devices[] = {
+        { /* U1 on the GS_IA18-CB_V3 board */
+                I2C_BOARD_INFO("pcf8574", 0x20),
+                .platform_data = &pcf20_pdata,
+        },
+        { /* U1 on the GS_2G_OPT1-A_V0 board (Alarm) */
+                I2C_BOARD_INFO("pcf8574", 0x22),
+                .platform_data = &pcf22_pdata,
+        },
+        { /* U1 on the GS_2G-OPT23-A_V0 board (Modem) */
+                I2C_BOARD_INFO("pcf8574", 0x24),
+                .platform_data = &pcf24_pdata,
+        },
+        { /* U161 on the GS_IA18_S-MN board */
+                I2C_BOARD_INFO("24c1024", 0x50),
+        },
+        { /* U162 on the GS_IA18_S-MN board */
+                I2C_BOARD_INFO("24c01", 0x53),
+        },
+};
+
+/*
+ * Compact Flash
+ */
+static struct at91_cf_data __initdata gsia18s_cf1_data = {
+        .irq_pin        = AT91_PIN_PA27,
+        .det_pin        = AT91_PIN_PB30,
+        .rst_pin        = AT91_PIN_PB31,
+        .chipselect     = 5,
+        .flags          = AT91_CF_TRUE_IDE,
+};
+
+/* Power Off by RTC */
+static void gsia18s_power_off(void)
+{
+        pr_notice("Power supply will be switched off automatically now or after 60 seconds without ArmDAS.\n");
+        at91_set_gpio_output(AT91_PIN_PA25, 1);
+        /* Spin to death... */
+        while (1)
+                ;
+}
+
+static int __init gsia18s_power_off_init(void)
+{
+        pm_power_off = gsia18s_power_off;
+        return 0;
+}
+
+/* ---------------------------------------------------------------------------*/
+
+static void __init gsia18s_board_init(void)
+{
+        stamp9g20_board_init();
+        at91_add_device_usbh(&usbh_data);
+        at91_add_device_udc(&udc_data);
+        at91_add_device_eth(&macb_data);
+        gsia18s_leds_init();
+        gsia18s_pcf_leds_init();
+        gsia18s_add_device_buttons();
+        at91_add_device_i2c(gsia18s_i2c_devices,
+                                ARRAY_SIZE(gsia18s_i2c_devices));
+        at91_add_device_cf(&gsia18s_cf1_data);
+        at91_add_device_spi(gsia18s_spi_devices,
+                                ARRAY_SIZE(gsia18s_spi_devices));
+        gsia18s_power_off_init();
+}
+
+MACHINE_START(GSIA18S, "GS_IA18_S")
+        .boot_params    = AT91_SDRAM_BASE + 0x100,
+        .timer          = &at91sam926x_timer,
+        .map_io         = gsia18s_map_io,
+        .init_irq       = init_irq,
+        .init_machine   = gsia18s_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index 86ff4b52db32..6c999dbd2bcf 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -37,7 +37,6 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
 #include <mach/board.h>
 #include <mach/gpio.h>
 #include <mach/at91sam9_smc.h>
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index ae4772e744ac..af818a21587c 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -274,10 +274,10 @@ EXPORT_SYMBOL(at91_get_gpio_value);
 static u32 wakeups[MAX_GPIO_BANKS];
 static u32 backups[MAX_GPIO_BANKS];
 
-static int gpio_irq_set_wake(unsigned pin, unsigned state)
+static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
 {
-        unsigned        mask = pin_to_mask(pin);
-        unsigned        bank = (pin - PIN_BASE) / 32;
+        unsigned        mask = pin_to_mask(d->irq);
+        unsigned        bank = (d->irq - PIN_BASE) / 32;
 
         if (unlikely(bank >= MAX_GPIO_BANKS))
                 return -EINVAL;
@@ -344,25 +344,25 @@ void at91_gpio_resume(void)
  * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
  */
 
-static void gpio_irq_mask(unsigned pin)
+static void gpio_irq_mask(struct irq_data *d)
 {
-        void __iomem    *pio = pin_to_controller(pin);
-        unsigned        mask = pin_to_mask(pin);
+        void __iomem    *pio = pin_to_controller(d->irq);
+        unsigned        mask = pin_to_mask(d->irq);
 
         if (pio)
                 __raw_writel(mask, pio + PIO_IDR);
 }
 
-static void gpio_irq_unmask(unsigned pin)
+static void gpio_irq_unmask(struct irq_data *d)
 {
-        void __iomem    *pio = pin_to_controller(pin);
-        unsigned        mask = pin_to_mask(pin);
+        void __iomem    *pio = pin_to_controller(d->irq);
+        unsigned        mask = pin_to_mask(d->irq);
 
         if (pio)
                 __raw_writel(mask, pio + PIO_IER);
 }
 
-static int gpio_irq_type(unsigned pin, unsigned type)
+static int gpio_irq_type(struct irq_data *d, unsigned type)
 {
         switch (type) {
         case IRQ_TYPE_NONE:
@@ -375,10 +375,10 @@ static int gpio_irq_type(unsigned pin, unsigned type)
 
 static struct irq_chip gpio_irqchip = {
         .name           = "GPIO",
-        .mask           = gpio_irq_mask,
-        .unmask         = gpio_irq_unmask,
-        .set_type       = gpio_irq_type,
-        .set_wake       = gpio_irq_set_wake,
+        .irq_mask       = gpio_irq_mask,
+        .irq_unmask     = gpio_irq_unmask,
+        .irq_set_type   = gpio_irq_type,
+        .irq_set_wake   = gpio_irq_set_wake,
 };
 
 static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
@@ -393,7 +393,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
         pio = at91_gpio->regbase;
 
         /* temporarily mask (level sensitive) parent IRQ */
-        desc->chip->ack(irq);
+        desc->irq_data.chip->irq_ack(&desc->irq_data);
         for (;;) {
                 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
                  * When there none are pending, we're finished unless we need
@@ -419,7 +419,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
                                          * another IRQ must be generated before it actually gets
                                          * here to be disabled on the GPIO controller.
                                          */
-                                        gpio_irq_mask(pin);
+                                        gpio_irq_mask(irq_get_irq_data(pin));
                                 }
                                 else
                                         generic_handle_irq(pin);
@@ -429,7 +429,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
                         isr >>= 1;
                 }
         }
-        desc->chip->unmask(irq);
+        desc->irq_data.chip->irq_unmask(&desc->irq_data);
         /* now it may re-trigger */
 }
 
diff --git a/arch/arm/mach-at91/include/mach/gsia18s.h b/arch/arm/mach-at91/include/mach/gsia18s.h
new file mode 100644
index 000000000000..307c194926f9
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/gsia18s.h
@@ -0,0 +1,33 @@
+/* Buttons */
+#define GPIO_TRIG_NET_IN                AT91_PIN_PB21
+#define GPIO_CARD_UNMOUNT_0             AT91_PIN_PB13
+#define GPIO_CARD_UNMOUNT_1             AT91_PIN_PB12
+#define GPIO_KEY_POWER                  AT91_PIN_PA25
+
+/* PCF8574 0x20 GPIO - U1 on the GS_IA18-CB_V3 board */
+#define GS_IA18_S_PCF_GPIO_BASE0        NR_BUILTIN_GPIO
+#define PCF_GPIO_HDC_POWER              (GS_IA18_S_PCF_GPIO_BASE0 + 0)
+#define PCF_GPIO_WIFI_SETUP             (GS_IA18_S_PCF_GPIO_BASE0 + 1)
+#define PCF_GPIO_WIFI_ENABLE            (GS_IA18_S_PCF_GPIO_BASE0 + 2)
+#define PCF_GPIO_WIFI_RESET             (GS_IA18_S_PCF_GPIO_BASE0 + 3)
+#define PCF_GPIO_ETH_DETECT             4 /* this is a GPI */
+#define PCF_GPIO_GPS_SETUP              (GS_IA18_S_PCF_GPIO_BASE0 + 5)
+#define PCF_GPIO_GPS_STANDBY            (GS_IA18_S_PCF_GPIO_BASE0 + 6)
+#define PCF_GPIO_GPS_POWER              (GS_IA18_S_PCF_GPIO_BASE0 + 7)
+
+/* PCF8574 0x22 GPIO - U1 on the GS_2G_OPT1-A_V0 board (Alarm) */
+#define GS_IA18_S_PCF_GPIO_BASE1        (GS_IA18_S_PCF_GPIO_BASE0 + 8)
+#define PCF_GPIO_ALARM1                 (GS_IA18_S_PCF_GPIO_BASE1 + 0)
+#define PCF_GPIO_ALARM2                 (GS_IA18_S_PCF_GPIO_BASE1 + 1)
+#define PCF_GPIO_ALARM3                 (GS_IA18_S_PCF_GPIO_BASE1 + 2)
+#define PCF_GPIO_ALARM4                 (GS_IA18_S_PCF_GPIO_BASE1 + 3)
+/* bits 4, 5, 6 not used */
+#define PCF_GPIO_ALARM_V_RELAY_ON       (GS_IA18_S_PCF_GPIO_BASE1 + 7)
+
+/* PCF8574 0x24 GPIO U1 on the GS_2G-OPT23-A_V0 board (Modem) */
+#define GS_IA18_S_PCF_GPIO_BASE2        (GS_IA18_S_PCF_GPIO_BASE1 + 8)
+#define PCF_GPIO_MODEM_POWER            (GS_IA18_S_PCF_GPIO_BASE2 + 0)
+#define PCF_GPIO_MODEM_RESET            (GS_IA18_S_PCF_GPIO_BASE2 + 3)
+/* bits 1, 2, 4, 5 not used */
+#define PCF_GPIO_TRX_RESET              (GS_IA18_S_PCF_GPIO_BASE2 + 6)
+/* bit 7 not used */
diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c
index da3494a53423..b56d6b3a4087 100644
--- a/arch/arm/mach-at91/irq.c
+++ b/arch/arm/mach-at91/irq.c
@@ -34,23 +34,23 @@
 #include <asm/mach/map.h>
 
 
-static void at91_aic_mask_irq(unsigned int irq)
+static void at91_aic_mask_irq(struct irq_data *d)
 {
         /* Disable interrupt on AIC */
-        at91_sys_write(AT91_AIC_IDCR, 1 << irq);
+        at91_sys_write(AT91_AIC_IDCR, 1 << d->irq);
 }
 
-static void at91_aic_unmask_irq(unsigned int irq)
+static void at91_aic_unmask_irq(struct irq_data *d)
 {
         /* Enable interrupt on AIC */
-        at91_sys_write(AT91_AIC_IECR, 1 << irq);
+        at91_sys_write(AT91_AIC_IECR, 1 << d->irq);
 }
 
 unsigned int at91_extern_irq;
 
 #define is_extern_irq(irq) ((1 << (irq)) & at91_extern_irq)
 
-static int at91_aic_set_type(unsigned irq, unsigned type)
+static int at91_aic_set_type(struct irq_data *d, unsigned type)
 {
         unsigned int smr, srctype;
 
@@ -62,13 +62,13 @@ static int at91_aic_set_type(unsigned irq, unsigned type)
                 srctype = AT91_AIC_SRCTYPE_RISING;
                 break;
         case IRQ_TYPE_LEVEL_LOW:
-                if ((irq == AT91_ID_FIQ) || is_extern_irq(irq))         /* only supported on external interrupts */
+                if ((d->irq == AT91_ID_FIQ) || is_extern_irq(d->irq))           /* only supported on external interrupts */
                         srctype = AT91_AIC_SRCTYPE_LOW;
                 else
                         return -EINVAL;
                 break;
         case IRQ_TYPE_EDGE_FALLING:
-                if ((irq == AT91_ID_FIQ) || is_extern_irq(irq))         /* only supported on external interrupts */
+                if ((d->irq == AT91_ID_FIQ) || is_extern_irq(d->irq))           /* only supported on external interrupts */
                         srctype = AT91_AIC_SRCTYPE_FALLING;
                 else
                         return -EINVAL;
@@ -77,8 +77,8 @@ static int at91_aic_set_type(unsigned irq, unsigned type)
                 return -EINVAL;
         }
 
-        smr = at91_sys_read(AT91_AIC_SMR(irq)) & ~AT91_AIC_SRCTYPE;
-        at91_sys_write(AT91_AIC_SMR(irq), smr | srctype);
+        smr = at91_sys_read(AT91_AIC_SMR(d->irq)) & ~AT91_AIC_SRCTYPE;
+        at91_sys_write(AT91_AIC_SMR(d->irq), smr | srctype);
         return 0;
 }
 
@@ -87,15 +87,15 @@ static int at91_aic_set_type(unsigned irq, unsigned type)
 static u32 wakeups;
 static u32 backups;
 
-static int at91_aic_set_wake(unsigned irq, unsigned value)
+static int at91_aic_set_wake(struct irq_data *d, unsigned value)
 {
-        if (unlikely(irq >= 32))
+        if (unlikely(d->irq >= 32))
                 return -EINVAL;
 
         if (value)
-                wakeups |= (1 << irq);
+                wakeups |= (1 << d->irq);
         else
-                wakeups &= ~(1 << irq);
+                wakeups &= ~(1 << d->irq);
 
         return 0;
 }
@@ -119,11 +119,11 @@ void at91_irq_resume(void)
 
 static struct irq_chip at91_aic_chip = {
         .name           = "AIC",
-        .ack            = at91_aic_mask_irq,
-        .mask           = at91_aic_mask_irq,
-        .unmask         = at91_aic_unmask_irq,
-        .set_type       = at91_aic_set_type,
-        .set_wake       = at91_aic_set_wake,
+        .irq_ack        = at91_aic_mask_irq,
+        .irq_mask       = at91_aic_mask_irq,
+        .irq_unmask     = at91_aic_unmask_irq,
+        .irq_set_type   = at91_aic_set_type,
+        .irq_set_wake   = at91_aic_set_wake,
 };
 
 /*
diff --git a/arch/arm/mach-bcmring/irq.c b/arch/arm/mach-bcmring/irq.c
index e3152631eb37..84dcda0d1d9a 100644
--- a/arch/arm/mach-bcmring/irq.c
+++ b/arch/arm/mach-bcmring/irq.c
@@ -30,61 +30,61 @@
 #include <mach/csp/intcHw_reg.h>
 #include <mach/csp/mm_io.h>
 
-static void bcmring_mask_irq0(unsigned int irq)
+static void bcmring_mask_irq0(struct irq_data *d)
 {
-        writel(1 << (irq - IRQ_INTC0_START),
+        writel(1 << (d->irq - IRQ_INTC0_START),
                MM_IO_BASE_INTC0 + INTCHW_INTENCLEAR);
 }
 
-static void bcmring_unmask_irq0(unsigned int irq)
+static void bcmring_unmask_irq0(struct irq_data *d)
 {
-        writel(1 << (irq - IRQ_INTC0_START),
+        writel(1 << (d->irq - IRQ_INTC0_START),
                MM_IO_BASE_INTC0 + INTCHW_INTENABLE);
 }
 
-static void bcmring_mask_irq1(unsigned int irq)
+static void bcmring_mask_irq1(struct irq_data *d)
 {
-        writel(1 << (irq - IRQ_INTC1_START),
+        writel(1 << (d->irq - IRQ_INTC1_START),
                MM_IO_BASE_INTC1 + INTCHW_INTENCLEAR);
 }
 
-static void bcmring_unmask_irq1(unsigned int irq)
+static void bcmring_unmask_irq1(struct irq_data *d)
 {
-        writel(1 << (irq - IRQ_INTC1_START),
+        writel(1 << (d->irq - IRQ_INTC1_START),
                MM_IO_BASE_INTC1 + INTCHW_INTENABLE);
 }
 
-static void bcmring_mask_irq2(unsigned int irq)
+static void bcmring_mask_irq2(struct irq_data *d)
 {
-        writel(1 << (irq - IRQ_SINTC_START),
+        writel(1 << (d->irq - IRQ_SINTC_START),
                MM_IO_BASE_SINTC + INTCHW_INTENCLEAR);
 }
 
-static void bcmring_unmask_irq2(unsigned int irq)
+static void bcmring_unmask_irq2(struct irq_data *d)
 {
-        writel(1 << (irq - IRQ_SINTC_START),
+        writel(1 << (d->irq - IRQ_SINTC_START),
                MM_IO_BASE_SINTC + INTCHW_INTENABLE);
 }
 
 static struct irq_chip bcmring_irq0_chip = {
         .name = "ARM-INTC0",
-        .ack = bcmring_mask_irq0,
-        .mask = bcmring_mask_irq0,      /* mask a specific interrupt, blocking its delivery. */
-        .unmask = bcmring_unmask_irq0,  /* unmaks an interrupt */
+        .irq_ack = bcmring_mask_irq0,
+        .irq_mask = bcmring_mask_irq0,  /* mask a specific interrupt, blocking its delivery. */
+        .irq_unmask = bcmring_unmask_irq0,      /* unmaks an interrupt */
 };
 
 static struct irq_chip bcmring_irq1_chip = {
         .name = "ARM-INTC1",
-        .ack = bcmring_mask_irq1,
-        .mask = bcmring_mask_irq1,
-        .unmask = bcmring_unmask_irq1,
+        .irq_ack = bcmring_mask_irq1,
+        .irq_mask = bcmring_mask_irq1,
+        .irq_unmask = bcmring_unmask_irq1,
 };
 
 static struct irq_chip bcmring_irq2_chip = {
         .name = "ARM-SINTC",
-        .ack = bcmring_mask_irq2,
-        .mask = bcmring_mask_irq2,
-        .unmask = bcmring_unmask_irq2,
+        .irq_ack = bcmring_mask_irq2,
+        .irq_mask = bcmring_mask_irq2,
+        .irq_unmask = bcmring_unmask_irq2,
 };
 
 static void vic_init(void __iomem *base, struct irq_chip *chip,
diff --git a/arch/arm/mach-clps711x/irq.c b/arch/arm/mach-clps711x/irq.c
index 9a12d8562284..86da7a1b2bbe 100644
--- a/arch/arm/mach-clps711x/irq.c
+++ b/arch/arm/mach-clps711x/irq.c
@@ -27,24 +27,24 @@
 
 #include <asm/hardware/clps7111.h>
 
-static void int1_mask(unsigned int irq)
+static void int1_mask(struct irq_data *d)
 {
         u32 intmr1;
 
         intmr1 = clps_readl(INTMR1);
-        intmr1 &= ~(1 << irq);
+        intmr1 &= ~(1 << d->irq);
         clps_writel(intmr1, INTMR1);
 }
 
-static void int1_ack(unsigned int irq)
+static void int1_ack(struct irq_data *d)
 {
         u32 intmr1;
 
         intmr1 = clps_readl(INTMR1);
-        intmr1 &= ~(1 << irq);
+        intmr1 &= ~(1 << d->irq);
         clps_writel(intmr1, INTMR1);
 
-        switch (irq) {
+        switch (d->irq) {
         case IRQ_CSINT:  clps_writel(0, COEOI);  break;
         case IRQ_TC1OI:  clps_writel(0, TC1EOI); break;
         case IRQ_TC2OI:  clps_writel(0, TC2EOI); break;
@@ -54,56 +54,56 @@ static void int1_ack(unsigned int irq)
         }
 }
 
-static void int1_unmask(unsigned int irq)
+static void int1_unmask(struct irq_data *d)
 {
         u32 intmr1;
 
         intmr1 = clps_readl(INTMR1);
-        intmr1 |= 1 << irq;
+        intmr1 |= 1 << d->irq;
         clps_writel(intmr1, INTMR1);
 }
 
 static struct irq_chip int1_chip = {
-        .ack    = int1_ack,
-        .mask   = int1_mask,
-        .unmask = int1_unmask,
+        .irq_ack        = int1_ack,
+        .irq_mask       = int1_mask,
+        .irq_unmask     = int1_unmask,
 };
 
-static void int2_mask(unsigned int irq)
+static void int2_mask(struct irq_data *d)
 {
         u32 intmr2;
 
         intmr2 = clps_readl(INTMR2);
-        intmr2 &= ~(1 << (irq - 16));
+        intmr2 &= ~(1 << (d->irq - 16));
         clps_writel(intmr2, INTMR2);
 }
 
-static void int2_ack(unsigned int irq)
+static void int2_ack(struct irq_data *d)
 {
         u32 intmr2;
 
         intmr2 = clps_readl(INTMR2);
-        intmr2 &= ~(1 << (irq - 16));
+        intmr2 &= ~(1 << (d->irq - 16));
         clps_writel(intmr2, INTMR2);
 
-        switch (irq) {
+        switch (d->irq) {
         case IRQ_KBDINT: clps_writel(0, KBDEOI); break;
         }
 }
 
-static void int2_unmask(unsigned int irq)
+static void int2_unmask(struct irq_data *d)
 {
         u32 intmr2;
 
         intmr2 = clps_readl(INTMR2);
-        intmr2 |= 1 << (irq - 16);
+        intmr2 |= 1 << (d->irq - 16);
         clps_writel(intmr2, INTMR2);
 }
 
 static struct irq_chip int2_chip = {
-        .ack    = int2_ack,
-        .mask   = int2_mask,
-        .unmask = int2_unmask,
+        .irq_ack        = int2_ack,
+        .irq_mask       = int2_mask,
+        .irq_unmask     = int2_unmask,
 };
 
 void __init clps711x_init_irq(void)
diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c
index bb4c40ecb803..9abc80a86a22 100644
--- a/arch/arm/mach-davinci/cp_intc.c
+++ b/arch/arm/mach-davinci/cp_intc.c
@@ -26,30 +26,30 @@ static inline void cp_intc_write(unsigned long value, unsigned offset)
         __raw_writel(value, davinci_intc_base + offset);
 }
 
-static void cp_intc_ack_irq(unsigned int irq)
+static void cp_intc_ack_irq(struct irq_data *d)
 {
-        cp_intc_write(irq, CP_INTC_SYS_STAT_IDX_CLR);
+        cp_intc_write(d->irq, CP_INTC_SYS_STAT_IDX_CLR);
 }
 
 /* Disable interrupt */
-static void cp_intc_mask_irq(unsigned int irq)
+static void cp_intc_mask_irq(struct irq_data *d)
 {
         /* XXX don't know why we need to disable nIRQ here... */
         cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_CLR);
-        cp_intc_write(irq, CP_INTC_SYS_ENABLE_IDX_CLR);
+        cp_intc_write(d->irq, CP_INTC_SYS_ENABLE_IDX_CLR);
         cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET);
 }
 
 /* Enable interrupt */
-static void cp_intc_unmask_irq(unsigned int irq)
+static void cp_intc_unmask_irq(struct irq_data *d)
 {
-        cp_intc_write(irq, CP_INTC_SYS_ENABLE_IDX_SET);
+        cp_intc_write(d->irq, CP_INTC_SYS_ENABLE_IDX_SET);
 }
 
-static int cp_intc_set_irq_type(unsigned int irq, unsigned int flow_type)
+static int cp_intc_set_irq_type(struct irq_data *d, unsigned int flow_type)
 {
-        unsigned reg            = BIT_WORD(irq);
-        unsigned mask           = BIT_MASK(irq);
+        unsigned reg            = BIT_WORD(d->irq);
+        unsigned mask           = BIT_MASK(d->irq);
         unsigned polarity       = cp_intc_read(CP_INTC_SYS_POLARITY(reg));
         unsigned type           = cp_intc_read(CP_INTC_SYS_TYPE(reg));
 
@@ -85,18 +85,18 @@ static int cp_intc_set_irq_type(unsigned int irq, unsigned int flow_type)
  * generic drivers which call {enable|disable}_irq_wake for
  * wake up interrupt sources (eg RTC on DA850).
  */
-static int cp_intc_set_wake(unsigned int irq, unsigned int on)
+static int cp_intc_set_wake(struct irq_data *d, unsigned int on)
 {
         return 0;
 }
 
 static struct irq_chip cp_intc_irq_chip = {
         .name           = "cp_intc",
-        .ack            = cp_intc_ack_irq,
-        .mask           = cp_intc_mask_irq,
-        .unmask         = cp_intc_unmask_irq,
-        .set_type       = cp_intc_set_irq_type,
-        .set_wake       = cp_intc_set_wake,
+        .irq_ack        = cp_intc_ack_irq,
+        .irq_mask       = cp_intc_mask_irq,
+        .irq_unmask     = cp_intc_unmask_irq,
+        .irq_set_type   = cp_intc_set_irq_type,
+        .irq_set_wake   = cp_intc_set_wake,
 };
 
 void __init cp_intc_init(void)
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index bf0ff587e46a..20d66e5e4663 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -205,20 +205,20 @@ pure_initcall(davinci_gpio_setup);
  * serve as EDMA event triggers.
  */
 
-static void gpio_irq_disable(unsigned irq)
+static void gpio_irq_disable(struct irq_data *d)
 {
-        struct davinci_gpio_regs __iomem *g = irq2regs(irq);
-        u32 mask = (u32) get_irq_data(irq);
+        struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
+        u32 mask = (u32) irq_data_get_irq_data(d);
 
         __raw_writel(mask, &g->clr_falling);
         __raw_writel(mask, &g->clr_rising);
 }
 
-static void gpio_irq_enable(unsigned irq)
+static void gpio_irq_enable(struct irq_data *d)
 {
-        struct davinci_gpio_regs __iomem *g = irq2regs(irq);
-        u32 mask = (u32) get_irq_data(irq);
-        unsigned status = irq_desc[irq].status;
+        struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
+        u32 mask = (u32) irq_data_get_irq_data(d);
+        unsigned status = irq_desc[d->irq].status;
 
         status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
         if (!status)
@@ -230,19 +230,19 @@ static void gpio_irq_enable(unsigned irq)
                 __raw_writel(mask, &g->set_rising);
 }
 
-static int gpio_irq_type(unsigned irq, unsigned trigger)
+static int gpio_irq_type(struct irq_data *d, unsigned trigger)
 {
-        struct davinci_gpio_regs __iomem *g = irq2regs(irq);
-        u32 mask = (u32) get_irq_data(irq);
+        struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
+        u32 mask = (u32) irq_data_get_irq_data(d);
 
         if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
                 return -EINVAL;
 
-        irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
-        irq_desc[irq].status |= trigger;
+        irq_desc[d->irq].status &= ~IRQ_TYPE_SENSE_MASK;
+        irq_desc[d->irq].status |= trigger;
 
         /* don't enable the IRQ if it's currently disabled */
-        if (irq_desc[irq].depth == 0) {
+        if (irq_desc[d->irq].depth == 0) {
                 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
                              ? &g->set_falling : &g->clr_falling);
                 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
@@ -253,9 +253,9 @@ static int gpio_irq_type(unsigned irq, unsigned trigger)
 
 static struct irq_chip gpio_irqchip = {
         .name           = "GPIO",
-        .enable         = gpio_irq_enable,
-        .disable        = gpio_irq_disable,
-        .set_type       = gpio_irq_type,
+        .irq_enable     = gpio_irq_enable,
+        .irq_disable    = gpio_irq_disable,
+        .irq_set_type   = gpio_irq_type,
 };
 
 static void
@@ -269,8 +269,8 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
                 mask <<= 16;
 
         /* temporarily mask (level sensitive) parent IRQ */
-        desc->chip->mask(irq);
-        desc->chip->ack(irq);
+        desc->irq_data.chip->irq_mask(&desc->irq_data);
+        desc->irq_data.chip->irq_ack(&desc->irq_data);
         while (1) {
                 u32             status;
                 int             n;
@@ -293,7 +293,7 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
                         status >>= res;
                 }
         }
-        desc->chip->unmask(irq);
+        desc->irq_data.chip->irq_unmask(&desc->irq_data);
         /* now it may re-trigger */
 }
 
@@ -320,10 +320,10 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
                 return -ENODEV;
 }
 
-static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger)
+static int gpio_irq_type_unbanked(struct irq_data *d, unsigned trigger)
 {
-        struct davinci_gpio_regs __iomem *g = irq2regs(irq);
-        u32 mask = (u32) get_irq_data(irq);
+        struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
+        u32 mask = (u32) irq_data_get_irq_data(d);
 
         if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
                 return -EINVAL;
@@ -397,7 +397,7 @@ static int __init davinci_gpio_irq_setup(void)
                 irq = bank_irq;
                 gpio_irqchip_unbanked = *get_irq_desc_chip(irq_to_desc(irq));
                 gpio_irqchip_unbanked.name = "GPIO-AINTC";
-                gpio_irqchip_unbanked.set_type = gpio_irq_type_unbanked;
+                gpio_irqchip_unbanked.irq_set_type = gpio_irq_type_unbanked;
 
                 /* default trigger: both edges */
                 g = gpio2regs(0);
diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c
index 784ddf3c5ad4..5e05c9b64e1f 100644
--- a/arch/arm/mach-davinci/irq.c
+++ b/arch/arm/mach-davinci/irq.c
@@ -53,14 +53,14 @@ static inline void davinci_irq_writel(unsigned long value, int offset)
 }
 
 /* Disable interrupt */
-static void davinci_mask_irq(unsigned int irq)
+static void davinci_mask_irq(struct irq_data *d)
 {
         unsigned int mask;
         u32 l;
 
-        mask = 1 << IRQ_BIT(irq);
+        mask = 1 << IRQ_BIT(d->irq);
 
-        if (irq > 31) {
+        if (d->irq > 31) {
                 l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
                 l &= ~mask;
                 davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
@@ -72,14 +72,14 @@ static void davinci_mask_irq(unsigned int irq)
 }
 
 /* Enable interrupt */
-static void davinci_unmask_irq(unsigned int irq)
+static void davinci_unmask_irq(struct irq_data *d)
 {
         unsigned int mask;
         u32 l;
 
-        mask = 1 << IRQ_BIT(irq);
+        mask = 1 << IRQ_BIT(d->irq);
 
-        if (irq > 31) {
+        if (d->irq > 31) {
                 l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
                 l |= mask;
                 davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
@@ -91,23 +91,23 @@ static void davinci_unmask_irq(unsigned int irq)
 }
 
 /* EOI interrupt */
-static void davinci_ack_irq(unsigned int irq)
+static void davinci_ack_irq(struct irq_data *d)
 {
         unsigned int mask;
 
-        mask = 1 << IRQ_BIT(irq);
+        mask = 1 << IRQ_BIT(d->irq);
 
-        if (irq > 31)
+        if (d->irq > 31)
                 davinci_irq_writel(mask, IRQ_REG1_OFFSET);
         else
                 davinci_irq_writel(mask, IRQ_REG0_OFFSET);
 }
 
 static struct irq_chip davinci_irq_chip_0 = {
-        .name   = "AINTC",
-        .ack    = davinci_ack_irq,
-        .mask   = davinci_mask_irq,
-        .unmask = davinci_unmask_irq,
+        .name           = "AINTC",
+        .irq_ack        = davinci_ack_irq,
+        .irq_mask       = davinci_mask_irq,
+        .irq_unmask     = davinci_unmask_irq,
 };
 
 /* ARM Interrupt Controller Initialization */
diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c
index 61bfcb3b08c2..9317f0558b57 100644
--- a/arch/arm/mach-dove/irq.c
+++ b/arch/arm/mach-dove/irq.c
@@ -36,9 +36,9 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
         }
 }
 
-static void pmu_irq_mask(unsigned int irq)
+static void pmu_irq_mask(struct irq_data *d)
 {
-        int pin = irq_to_pmu(irq);
+        int pin = irq_to_pmu(d->irq);
         u32 u;
 
         u = readl(PMU_INTERRUPT_MASK);
@@ -46,9 +46,9 @@ static void pmu_irq_mask(unsigned int irq)
         writel(u, PMU_INTERRUPT_MASK);
 }
 
-static void pmu_irq_unmask(unsigned int irq)
+static void pmu_irq_unmask(struct irq_data *d)
 {
-        int pin = irq_to_pmu(irq);
+        int pin = irq_to_pmu(d->irq);
         u32 u;
 
         u = readl(PMU_INTERRUPT_MASK);
@@ -56,9 +56,9 @@ static void pmu_irq_unmask(unsigned int irq)
         writel(u, PMU_INTERRUPT_MASK);
 }
 
-static void pmu_irq_ack(unsigned int irq)
+static void pmu_irq_ack(struct irq_data *d)
 {
-        int pin = irq_to_pmu(irq);
+        int pin = irq_to_pmu(d->irq);
         u32 u;
 
         u = ~(1 << (pin & 31));
@@ -67,9 +67,9 @@ static void pmu_irq_ack(unsigned int irq)
 
 static struct irq_chip pmu_irq_chip = {
         .name           = "pmu_irq",
-        .mask           = pmu_irq_mask,
-        .unmask         = pmu_irq_unmask,
-        .ack            = pmu_irq_ack,
+        .irq_mask       = pmu_irq_mask,
+        .irq_unmask     = pmu_irq_unmask,
+        .irq_ack        = pmu_irq_ack,
 };
 
 static void pmu_irq_handler(unsigned int irq, struct irq_desc *desc)
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index 5df4099fc14f..7df083f37fa7 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -35,20 +35,20 @@
 #define IRQ_STAT                0xff000000      /* read */
 #define IRQ_MCLR                0xff000000      /* write */
 
-static void ebsa110_mask_irq(unsigned int irq)
+static void ebsa110_mask_irq(struct irq_data *d)
 {
-        __raw_writeb(1 << irq, IRQ_MCLR);
+        __raw_writeb(1 << d->irq, IRQ_MCLR);
 }
 
-static void ebsa110_unmask_irq(unsigned int irq)
+static void ebsa110_unmask_irq(struct irq_data *d)
 {
-        __raw_writeb(1 << irq, IRQ_MSET);
+        __raw_writeb(1 << d->irq, IRQ_MSET);
 }
 
 static struct irq_chip ebsa110_irq_chip = {
-        .ack    = ebsa110_mask_irq,
-        .mask   = ebsa110_mask_irq,
-        .unmask = ebsa110_unmask_irq,
+        .irq_ack        = ebsa110_mask_irq,
+        .irq_mask       = ebsa110_mask_irq,
+        .irq_unmask     = ebsa110_unmask_irq,
 };
  
 static void __init ebsa110_init_irq(void)
diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c
index cf547ad7ebd4..f3dc76fdcea8 100644
--- a/arch/arm/mach-ep93xx/gpio.c
+++ b/arch/arm/mach-ep93xx/gpio.c
@@ -112,13 +112,13 @@ static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
         generic_handle_irq(gpio_irq);
 }
 
-static void ep93xx_gpio_irq_ack(unsigned int irq)
+static void ep93xx_gpio_irq_ack(struct irq_data *d)
 {
-        int line = irq_to_gpio(irq);
+        int line = irq_to_gpio(d->irq);
         int port = line >> 3;
         int port_mask = 1 << (line & 7);
 
-        if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
+        if ((irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
                 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
                 ep93xx_gpio_update_int_params(port);
         }
@@ -126,13 +126,13 @@ static void ep93xx_gpio_irq_ack(unsigned int irq)
         __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
 }
 
-static void ep93xx_gpio_irq_mask_ack(unsigned int irq)
+static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
 {
-        int line = irq_to_gpio(irq);
+        int line = irq_to_gpio(d->irq);
         int port = line >> 3;
         int port_mask = 1 << (line & 7);
 
-        if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
+        if ((irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
                 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
 
         gpio_int_unmasked[port] &= ~port_mask;
@@ -141,18 +141,18 @@ static void ep93xx_gpio_irq_mask_ack(unsigned int irq)
         __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
 }
 
-static void ep93xx_gpio_irq_mask(unsigned int irq)
+static void ep93xx_gpio_irq_mask(struct irq_data *d)
 {
-        int line = irq_to_gpio(irq);
+        int line = irq_to_gpio(d->irq);
         int port = line >> 3;
 
         gpio_int_unmasked[port] &= ~(1 << (line & 7));
         ep93xx_gpio_update_int_params(port);
 }
 
-static void ep93xx_gpio_irq_unmask(unsigned int irq)
+static void ep93xx_gpio_irq_unmask(struct irq_data *d)
 {
-        int line = irq_to_gpio(irq);
+        int line = irq_to_gpio(d->irq);
         int port = line >> 3;
 
         gpio_int_unmasked[port] |= 1 << (line & 7);
@@ -164,10 +164,10 @@ static void ep93xx_gpio_irq_unmask(unsigned int irq)
  * edge (1) triggered, while gpio_int_type2 controls whether it
  * triggers on low/falling (0) or high/rising (1).
  */
-static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
+static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
 {
-        struct irq_desc *desc = irq_desc + irq;
-        const int gpio = irq_to_gpio(irq);
+        struct irq_desc *desc = irq_desc + d->irq;
+        const int gpio = irq_to_gpio(d->irq);
         const int port = gpio >> 3;
         const int port_mask = 1 << (gpio & 7);
 
@@ -220,11 +220,11 @@ static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
 
 static struct irq_chip ep93xx_gpio_irq_chip = {
         .name           = "GPIO",
-        .ack            = ep93xx_gpio_irq_ack,
-        .mask_ack       = ep93xx_gpio_irq_mask_ack,
-        .mask           = ep93xx_gpio_irq_mask,
-        .unmask         = ep93xx_gpio_irq_unmask,
-        .set_type       = ep93xx_gpio_irq_type,
+        .irq_ack        = ep93xx_gpio_irq_ack,
+        .irq_mask_ack   = ep93xx_gpio_irq_mask_ack,
+        .irq_mask       = ep93xx_gpio_irq_mask,
+        .irq_unmask     = ep93xx_gpio_irq_unmask,
+        .irq_set_type   = ep93xx_gpio_irq_type,
 };
 
 void __init ep93xx_gpio_init_irq(void)
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index 88b3dd89be89..84c5f258f2d8 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -75,20 +75,20 @@ static const int fb_irq_mask[] = {
         IRQ_MASK_PCI_PERR,      /* 19 */
 };
 
-static void fb_mask_irq(unsigned int irq)
+static void fb_mask_irq(struct irq_data *d)
 {
-        *CSR_IRQ_DISABLE = fb_irq_mask[_DC21285_INR(irq)];
+        *CSR_IRQ_DISABLE = fb_irq_mask[_DC21285_INR(d->irq)];
 }
 
-static void fb_unmask_irq(unsigned int irq)
+static void fb_unmask_irq(struct irq_data *d)
 {
-        *CSR_IRQ_ENABLE = fb_irq_mask[_DC21285_INR(irq)];
+        *CSR_IRQ_ENABLE = fb_irq_mask[_DC21285_INR(d->irq)];
 }
 
 static struct irq_chip fb_chip = {
-        .ack    = fb_mask_irq,
-        .mask   = fb_mask_irq,
-        .unmask = fb_unmask_irq,
+        .irq_ack        = fb_mask_irq,
+        .irq_mask       = fb_mask_irq,
+        .irq_unmask     = fb_unmask_irq,
 };
 
 static void __init __fb_init_irq(void)
diff --git a/arch/arm/mach-footbridge/isa-irq.c b/arch/arm/mach-footbridge/isa-irq.c
index 8bfd06aeb64d..de7a5cb5dbe1 100644
--- a/arch/arm/mach-footbridge/isa-irq.c
+++ b/arch/arm/mach-footbridge/isa-irq.c
@@ -30,61 +30,61 @@
 
 #include "common.h"
 
-static void isa_mask_pic_lo_irq(unsigned int irq)
+static void isa_mask_pic_lo_irq(struct irq_data *d)
 {
-        unsigned int mask = 1 << (irq & 7);
+        unsigned int mask = 1 << (d->irq & 7);
 
         outb(inb(PIC_MASK_LO) | mask, PIC_MASK_LO);
 }
 
-static void isa_ack_pic_lo_irq(unsigned int irq)
+static void isa_ack_pic_lo_irq(struct irq_data *d)
 {
-        unsigned int mask = 1 << (irq & 7);
+        unsigned int mask = 1 << (d->irq & 7);
 
         outb(inb(PIC_MASK_LO) | mask, PIC_MASK_LO);
         outb(0x20, PIC_LO);
 }
 
-static void isa_unmask_pic_lo_irq(unsigned int irq)
+static void isa_unmask_pic_lo_irq(struct irq_data *d)
 {
-        unsigned int mask = 1 << (irq & 7);
+        unsigned int mask = 1 << (d->irq & 7);
 
         outb(inb(PIC_MASK_LO) & ~mask, PIC_MASK_LO);
 }
 
 static struct irq_chip isa_lo_chip = {
-        .ack    = isa_ack_pic_lo_irq,
-        .mask   = isa_mask_pic_lo_irq,
-        .unmask = isa_unmask_pic_lo_irq,
+        .irq_ack        = isa_ack_pic_lo_irq,
+        .irq_mask       = isa_mask_pic_lo_irq,
+        .irq_unmask     = isa_unmask_pic_lo_irq,
 };
 
-static void isa_mask_pic_hi_irq(unsigned int irq)
+static void isa_mask_pic_hi_irq(struct irq_data *d)
 {
-        unsigned int mask = 1 << (irq & 7);
+        unsigned int mask = 1 << (d->irq & 7);
 
         outb(inb(PIC_MASK_HI) | mask, PIC_MASK_HI);
 }
 
-static void isa_ack_pic_hi_irq(unsigned int irq)
+static void isa_ack_pic_hi_irq(struct irq_data *d)
 {
-        unsigned int mask = 1 << (irq & 7);
+        unsigned int mask = 1 << (d->irq & 7);
 
         outb(inb(PIC_MASK_HI) | mask, PIC_MASK_HI);
         outb(0x62, PIC_LO);
         outb(0x20, PIC_HI);
 }
 
-static void isa_unmask_pic_hi_irq(unsigned int irq)
+static void isa_unmask_pic_hi_irq(struct irq_data *d)
 {
-        unsigned int mask = 1 << (irq & 7);
+        unsigned int mask = 1 << (d->irq & 7);
 
         outb(inb(PIC_MASK_HI) & ~mask, PIC_MASK_HI);
 }
 
 static struct irq_chip isa_hi_chip = {
-        .ack    = isa_ack_pic_hi_irq,
-        .mask   = isa_mask_pic_hi_irq,
-        .unmask = isa_unmask_pic_hi_irq,
+        .irq_ack        = isa_ack_pic_hi_irq,
+        .irq_mask       = isa_mask_pic_hi_irq,
+        .irq_unmask     = isa_unmask_pic_hi_irq,
 };
 
 static void
diff --git a/arch/arm/mach-gemini/gpio.c b/arch/arm/mach-gemini/gpio.c
index fe3bd5ac8b10..fa3d333f21e1 100644
--- a/arch/arm/mach-gemini/gpio.c
+++ b/arch/arm/mach-gemini/gpio.c
@@ -54,33 +54,33 @@ static void _set_gpio_irqenable(unsigned int base, unsigned int index,
         __raw_writel(reg, base + GPIO_INT_EN);
 }
 
-static void gpio_ack_irq(unsigned int irq)
+static void gpio_ack_irq(struct irq_data *d)
 {
-        unsigned int gpio = irq_to_gpio(irq);
+        unsigned int gpio = irq_to_gpio(d->irq);
         unsigned int base = GPIO_BASE(gpio / 32);
 
         __raw_writel(1 << (gpio % 32), base + GPIO_INT_CLR);
 }
 
-static void gpio_mask_irq(unsigned int irq)
+static void gpio_mask_irq(struct irq_data *d)
 {
-        unsigned int gpio = irq_to_gpio(irq);
+        unsigned int gpio = irq_to_gpio(d->irq);
         unsigned int base = GPIO_BASE(gpio / 32);
 
         _set_gpio_irqenable(base, gpio % 32, 0);
 }
 
-static void gpio_unmask_irq(unsigned int irq)
+static void gpio_unmask_irq(struct irq_data *d)
 {
-        unsigned int gpio = irq_to_gpio(irq);
+        unsigned int gpio = irq_to_gpio(d->irq);
         unsigned int base = GPIO_BASE(gpio / 32);
 
         _set_gpio_irqenable(base, gpio % 32, 1);
 }
 
-static int gpio_set_irq_type(unsigned int irq, unsigned int type)
+static int gpio_set_irq_type(struct irq_data *d, unsigned int type)
 {
-        unsigned int gpio = irq_to_gpio(irq);
+        unsigned int gpio = irq_to_gpio(d->irq);
         unsigned int gpio_mask = 1 << (gpio % 32);
         unsigned int base = GPIO_BASE(gpio / 32);
         unsigned int reg_both, reg_level, reg_type;
@@ -120,7 +120,7 @@ static int gpio_set_irq_type(unsigned int irq, unsigned int type)
         __raw_writel(reg_level, base + GPIO_INT_LEVEL);
         __raw_writel(reg_both, base + GPIO_INT_BOTH_EDGE);
 
-        gpio_ack_irq(irq);
+        gpio_ack_irq(d->irq);
 
         return 0;
 }
@@ -146,10 +146,10 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 
 static struct irq_chip gpio_irq_chip = {
         .name = "GPIO",
-        .ack = gpio_ack_irq,
-        .mask = gpio_mask_irq,
-        .unmask = gpio_unmask_irq,
-        .set_type = gpio_set_irq_type,
+        .irq_ack = gpio_ack_irq,
+        .irq_mask = gpio_mask_irq,
+        .irq_unmask = gpio_unmask_irq,
+        .irq_set_type = gpio_set_irq_type,
 };
 
 static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
diff --git a/arch/arm/mach-gemini/irq.c b/arch/arm/mach-gemini/irq.c
index 9e613ca8120d..96bc227dd849 100644
--- a/arch/arm/mach-gemini/irq.c
+++ b/arch/arm/mach-gemini/irq.c
@@ -32,34 +32,34 @@
 #define FIQ_LEVEL(base_addr)    (base_addr + 0x30)
 #define FIQ_STATUS(base_addr)   (base_addr + 0x34)
 
-static void gemini_ack_irq(unsigned int irq)
+static void gemini_ack_irq(struct irq_data *d)
 {
-        __raw_writel(1 << irq, IRQ_CLEAR(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
+        __raw_writel(1 << d->irq, IRQ_CLEAR(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
 }
 
-static void gemini_mask_irq(unsigned int irq)
+static void gemini_mask_irq(struct irq_data *d)
 {
         unsigned int mask;
 
         mask = __raw_readl(IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
-        mask &= ~(1 << irq);
+        mask &= ~(1 << d->irq);
         __raw_writel(mask, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
 }
 
-static void gemini_unmask_irq(unsigned int irq)
+static void gemini_unmask_irq(struct irq_data *d)
 {
         unsigned int mask;
 
         mask = __raw_readl(IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
-        mask |= (1 << irq);
+        mask |= (1 << d->irq);
         __raw_writel(mask, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
 }
 
 static struct irq_chip gemini_irq_chip = {
-        .name   = "INTC",
-        .ack    = gemini_ack_irq,
-        .mask   = gemini_mask_irq,
-        .unmask = gemini_unmask_irq,
+        .name           = "INTC",
+        .irq_ack        = gemini_ack_irq,
+        .irq_mask       = gemini_mask_irq,
+        .irq_unmask     = gemini_unmask_irq,
 };
 
 static struct resource irq_resource = {
diff --git a/arch/arm/mach-h720x/common.c b/arch/arm/mach-h720x/common.c
index bdb3f6706801..1f28c90932c7 100644
--- a/arch/arm/mach-h720x/common.c
+++ b/arch/arm/mach-h720x/common.c
@@ -52,17 +52,17 @@ unsigned long h720x_gettimeoffset(void)
 /*
  * mask Global irq's
  */
-static void mask_global_irq (unsigned int irq )
+static void mask_global_irq(struct irq_data *d)
 {
-        CPU_REG (IRQC_VIRT, IRQC_IER) &= ~(1 << irq);
+        CPU_REG (IRQC_VIRT, IRQC_IER) &= ~(1 << d->irq);
 }
 
 /*
  * unmask Global irq's
  */
-static void unmask_global_irq (unsigned int irq )
+static void unmask_global_irq(struct irq_data *d)
 {
-        CPU_REG (IRQC_VIRT, IRQC_IER) |= (1 << irq);
+        CPU_REG (IRQC_VIRT, IRQC_IER) |= (1 << d->irq);
 }
 
 
@@ -70,10 +70,10 @@ static void unmask_global_irq (unsigned int irq )
  * ack GPIO irq's
  * Ack only for edge triggered int's valid
  */
-static void inline ack_gpio_irq(u32 irq)
+static void inline ack_gpio_irq(struct irq_data *d)
 {
-        u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq));
-        u32 bit = IRQ_TO_BIT(irq);
+        u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(d->irq));
+        u32 bit = IRQ_TO_BIT(d->irq);
         if ( (CPU_REG (reg_base, GPIO_EDGE) & bit))
                 CPU_REG (reg_base, GPIO_CLR) = bit;
 }
@@ -81,20 +81,20 @@ static void inline ack_gpio_irq(u32 irq)
 /*
  * mask GPIO irq's
  */
-static void inline mask_gpio_irq(u32 irq)
+static void inline mask_gpio_irq(struct irq_data *d)
 {
-        u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq));
-        u32 bit = IRQ_TO_BIT(irq);
+        u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(d->irq));
+        u32 bit = IRQ_TO_BIT(d->irq);
         CPU_REG (reg_base, GPIO_MASK) &= ~bit;
 }
 
 /*
  * unmask GPIO irq's
  */
-static void inline unmask_gpio_irq(u32 irq)
+static void inline unmask_gpio_irq(struct irq_data *d)
 {
-        u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq));
-        u32 bit = IRQ_TO_BIT(irq);
+        u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(d->irq));
+        u32 bit = IRQ_TO_BIT(d->irq);
         CPU_REG (reg_base, GPIO_MASK) |= bit;
 }
 
@@ -170,15 +170,15 @@ h720x_gpioe_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
 #endif
 
 static struct irq_chip h720x_global_chip = {
-        .ack = mask_global_irq,
-        .mask = mask_global_irq,
-        .unmask = unmask_global_irq,
+        .irq_ack = mask_global_irq,
+        .irq_mask = mask_global_irq,
+        .irq_unmask = unmask_global_irq,
 };
 
 static struct irq_chip h720x_gpio_chip = {
-        .ack = ack_gpio_irq,
-        .mask = mask_gpio_irq,
-        .unmask = unmask_gpio_irq,
+        .irq_ack = ack_gpio_irq,
+        .irq_mask = mask_gpio_irq,
+        .irq_unmask = unmask_gpio_irq,
 };
 
 /*
diff --git a/arch/arm/mach-h720x/cpu-h7202.c b/arch/arm/mach-h720x/cpu-h7202.c
index fd33a19c813a..ac3f91442376 100644
--- a/arch/arm/mach-h720x/cpu-h7202.c
+++ b/arch/arm/mach-h720x/cpu-h7202.c
@@ -141,27 +141,27 @@ h7202_timer_interrupt(int irq, void *dev_id)
 /*
  * mask multiplexed timer IRQs
  */
-static void inline mask_timerx_irq (u32 irq)
+static void inline mask_timerx_irq(struct irq_data *d)
 {
         unsigned int bit;
-        bit = 2 << ((irq == IRQ_TIMER64B) ? 4 : (irq - IRQ_TIMER1));
+        bit = 2 << ((d->irq == IRQ_TIMER64B) ? 4 : (d->irq - IRQ_TIMER1));
         CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) &= ~bit;
 }
 
 /*
  * unmask multiplexed timer IRQs
  */
-static void inline unmask_timerx_irq (u32 irq)
+static void inline unmask_timerx_irq(struct irq_data *d)
 {
         unsigned int bit;
-        bit = 2 << ((irq == IRQ_TIMER64B) ? 4 : (irq - IRQ_TIMER1));
+        bit = 2 << ((d->irq == IRQ_TIMER64B) ? 4 : (d->irq - IRQ_TIMER1));
         CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) |= bit;
 }
 
 static struct irq_chip h7202_timerx_chip = {
-        .ack = mask_timerx_irq,
-        .mask = mask_timerx_irq,
-        .unmask = unmask_timerx_irq,
+        .irq_ack = mask_timerx_irq,
+        .irq_mask = mask_timerx_irq,
+        .irq_unmask = unmask_timerx_irq,
 };
 
 static struct irqaction h7202_timer_irq = {
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 17d2e608a214..56684b517070 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -243,6 +243,7 @@ config MACH_MX27_3DS
         select IMX_HAVE_PLATFORM_MXC_EHCI
         select IMX_HAVE_PLATFORM_MXC_MMC
         select IMX_HAVE_PLATFORM_SPI_IMX
+        select MXC_DEBUG_BOARD
         select MXC_ULPI if USB_ULPI
         help
           Include support for MX27PDK platform. This includes specific
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index 6fd0f8f6deb6..164331518bdd 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -37,12 +37,15 @@
 #include <mach/common.h>
 #include <mach/iomux-mx27.h>
 #include <mach/ulpi.h>
+#include <mach/irqs.h>
+#include <mach/3ds_debugboard.h>
 
 #include "devices-imx27.h"
 
 #define SD1_EN_GPIO (GPIO_PORTB + 25)
 #define OTG_PHY_RESET_GPIO (GPIO_PORTB + 23)
 #define SPI2_SS0 (GPIO_PORTD + 21)
+#define EXPIO_PARENT_INT        (MXC_INTERNAL_IRQS + GPIO_PORTC + 28)
 
 static const int mx27pdk_pins[] __initconst = {
         /* UART1 */
@@ -215,10 +218,10 @@ static struct regulator_init_data vgen_init = {
 
 static struct mc13783_regulator_init_data mx27_3ds_regulators[] = {
         {
-                .id = MC13783_REGU_VMMC1,
+                .id = MC13783_REG_VMMC1,
                 .init_data = &vmmc1_init,
         }, {
-                .id = MC13783_REGU_VGEN,
+                .id = MC13783_REG_VGEN,
                 .init_data = &vgen_init,
         },
 };
@@ -276,6 +279,9 @@ static void __init mx27pdk_init(void)
         imx27_add_spi_imx1(&spi2_pdata);
         spi_register_board_info(mx27_3ds_spi_devs,
                                                 ARRAY_SIZE(mx27_3ds_spi_devs));
+
+        if (mxc_expio_init(MX27_CS5_BASE_ADDR, EXPIO_PARENT_INT))
+                pr_warn("Init of the debugboard failed, all devices on the debugboard are unusable.\n");
 }
 
 static void __init mx27pdk_timer_init(void)
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 2774df8021dc..b666443b5cbb 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -156,21 +156,21 @@ static void __init ap_map_io(void)
 
 #define INTEGRATOR_SC_VALID_INT 0x003fffff
 
-static void sc_mask_irq(unsigned int irq)
+static void sc_mask_irq(struct irq_data *d)
 {
-        writel(1 << irq, VA_IC_BASE + IRQ_ENABLE_CLEAR);
+        writel(1 << d->irq, VA_IC_BASE + IRQ_ENABLE_CLEAR);
 }
 
-static void sc_unmask_irq(unsigned int irq)
+static void sc_unmask_irq(struct irq_data *d)
 {
-        writel(1 << irq, VA_IC_BASE + IRQ_ENABLE_SET);
+        writel(1 << d->irq, VA_IC_BASE + IRQ_ENABLE_SET);
 }
 
 static struct irq_chip sc_chip = {
-        .name   = "SC",
-        .ack    = sc_mask_irq,
-        .mask   = sc_mask_irq,
-        .unmask = sc_unmask_irq,
+        .name           = "SC",
+        .irq_ack        = sc_mask_irq,
+        .irq_mask       = sc_mask_irq,
+        .irq_unmask     = sc_unmask_irq,
 };
 
 static void __init ap_init_irq(void)
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 85e48a5f77b9..e9327da1382e 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -146,61 +146,61 @@ static void __init intcp_map_io(void)
 #define sic_writel      __raw_writel
 #define sic_readl       __raw_readl
 
-static void cic_mask_irq(unsigned int irq)
+static void cic_mask_irq(struct irq_data *d)
 {
-        irq -= IRQ_CIC_START;
+        unsigned int irq = d->irq - IRQ_CIC_START;
         cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
 }
 
-static void cic_unmask_irq(unsigned int irq)
+static void cic_unmask_irq(struct irq_data *d)
 {
-        irq -= IRQ_CIC_START;
+        unsigned int irq = d->irq - IRQ_CIC_START;
         cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_SET);
 }
 
 static struct irq_chip cic_chip = {
-        .name   = "CIC",
-        .ack    = cic_mask_irq,
-        .mask   = cic_mask_irq,
-        .unmask = cic_unmask_irq,
+        .name           = "CIC",
+        .irq_ack        = cic_mask_irq,
+        .irq_mask       = cic_mask_irq,
+        .irq_unmask     = cic_unmask_irq,
 };
 
-static void pic_mask_irq(unsigned int irq)
+static void pic_mask_irq(struct irq_data *d)
 {
-        irq -= IRQ_PIC_START;
+        unsigned int irq = d->irq - IRQ_PIC_START;
         pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
 }
 
-static void pic_unmask_irq(unsigned int irq)
+static void pic_unmask_irq(struct irq_data *d)
 {
-        irq -= IRQ_PIC_START;
+        unsigned int irq = d->irq - IRQ_PIC_START;
         pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_SET);
 }
 
 static struct irq_chip pic_chip = {
-        .name   = "PIC",
-        .ack    = pic_mask_irq,
-        .mask   = pic_mask_irq,
-        .unmask = pic_unmask_irq,
+        .name           = "PIC",
+        .irq_ack        = pic_mask_irq,
+        .irq_mask       = pic_mask_irq,
+        .irq_unmask     = pic_unmask_irq,
 };
 
-static void sic_mask_irq(unsigned int irq)
+static void sic_mask_irq(struct irq_data *d)
 {
-        irq -= IRQ_SIC_START;
+        unsigned int irq = d->irq - IRQ_SIC_START;
         sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
 }
 
-static void sic_unmask_irq(unsigned int irq)
+static void sic_unmask_irq(struct irq_data *d)
 {
-        irq -= IRQ_SIC_START;
+        unsigned int irq = d->irq - IRQ_SIC_START;
         sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_SET);
 }
 
 static struct irq_chip sic_chip = {
-        .name   = "SIC",
-        .ack    = sic_mask_irq,
-        .mask   = sic_mask_irq,
-        .unmask = sic_unmask_irq,
+        .name           = "SIC",
+        .irq_ack        = sic_mask_irq,
+        .irq_mask       = sic_mask_irq,
+        .irq_unmask     = sic_unmask_irq,
 };
 
 static void
diff --git a/arch/arm/mach-iop13xx/irq.c b/arch/arm/mach-iop13xx/irq.c
index 0d099ca87bdf..a233470dd10c 100644
--- a/arch/arm/mach-iop13xx/irq.c
+++ b/arch/arm/mach-iop13xx/irq.c
@@ -123,79 +123,79 @@ static void write_intsize(u32 val)
 
 /* 0 = Interrupt Masked and 1 = Interrupt not masked */
 static void
-iop13xx_irq_mask0 (unsigned int irq)
+iop13xx_irq_mask0 (struct irq_data *d)
 {
-        write_intctl_0(read_intctl_0() & ~(1 << (irq - 0)));
+        write_intctl_0(read_intctl_0() & ~(1 << (d->irq - 0)));
 }
 
 static void
-iop13xx_irq_mask1 (unsigned int irq)
+iop13xx_irq_mask1 (struct irq_data *d)
 {
-        write_intctl_1(read_intctl_1() & ~(1 << (irq - 32)));
+        write_intctl_1(read_intctl_1() & ~(1 << (d->irq - 32)));
 }
 
 static void
-iop13xx_irq_mask2 (unsigned int irq)
+iop13xx_irq_mask2 (struct irq_data *d)
 {
-        write_intctl_2(read_intctl_2() & ~(1 << (irq - 64)));
+        write_intctl_2(read_intctl_2() & ~(1 << (d->irq - 64)));
 }
 
 static void
-iop13xx_irq_mask3 (unsigned int irq)
+iop13xx_irq_mask3 (struct irq_data *d)
 {
-        write_intctl_3(read_intctl_3() & ~(1 << (irq - 96)));
+        write_intctl_3(read_intctl_3() & ~(1 << (d->irq - 96)));
 }
 
 static void
-iop13xx_irq_unmask0(unsigned int irq)
+iop13xx_irq_unmask0(struct irq_data *d)
 {
-        write_intctl_0(read_intctl_0() | (1 << (irq - 0)));
+        write_intctl_0(read_intctl_0() | (1 << (d->irq - 0)));
 }
 
 static void
-iop13xx_irq_unmask1(unsigned int irq)
+iop13xx_irq_unmask1(struct irq_data *d)
 {
-        write_intctl_1(read_intctl_1() | (1 << (irq - 32)));
+        write_intctl_1(read_intctl_1() | (1 << (d->irq - 32)));
 }
 
 static void
-iop13xx_irq_unmask2(unsigned int irq)
+iop13xx_irq_unmask2(struct irq_data *d)
 {
-        write_intctl_2(read_intctl_2() | (1 << (irq - 64)));
+        write_intctl_2(read_intctl_2() | (1 << (d->irq - 64)));
 }
 
 static void
-iop13xx_irq_unmask3(unsigned int irq)
+iop13xx_irq_unmask3(struct irq_data *d)
 {
-        write_intctl_3(read_intctl_3() | (1 << (irq - 96)));
+        write_intctl_3(read_intctl_3() | (1 << (d->irq - 96)));
 }
 
 static struct irq_chip iop13xx_irqchip1 = {
-        .name   = "IOP13xx-1",
-        .ack    = iop13xx_irq_mask0,
-        .mask   = iop13xx_irq_mask0,
-        .unmask = iop13xx_irq_unmask0,
+        .name       = "IOP13xx-1",
+        .irq_ack    = iop13xx_irq_mask0,
+        .irq_mask   = iop13xx_irq_mask0,
+        .irq_unmask = iop13xx_irq_unmask0,
 };
 
 static struct irq_chip iop13xx_irqchip2 = {
-        .name   = "IOP13xx-2",
-        .ack    = iop13xx_irq_mask1,
-        .mask   = iop13xx_irq_mask1,
-        .unmask = iop13xx_irq_unmask1,
+        .name       = "IOP13xx-2",
+        .irq_ack    = iop13xx_irq_mask1,
+        .irq_mask   = iop13xx_irq_mask1,
+        .irq_unmask = iop13xx_irq_unmask1,
 };
 
 static struct irq_chip iop13xx_irqchip3 = {
-        .name   = "IOP13xx-3",
-        .ack    = iop13xx_irq_mask2,
-        .mask   = iop13xx_irq_mask2,
-        .unmask = iop13xx_irq_unmask2,
+        .name       = "IOP13xx-3",
+        .irq_ack    = iop13xx_irq_mask2,
+        .irq_mask   = iop13xx_irq_mask2,
+        .irq_unmask = iop13xx_irq_unmask2,
 };
 
 static struct irq_chip iop13xx_irqchip4 = {
-        .name   = "IOP13xx-4",
-        .ack    = iop13xx_irq_mask3,
-        .mask   = iop13xx_irq_mask3,
-        .unmask = iop13xx_irq_unmask3,
+        .name       = "IOP13xx-4",
+        .irq_ack    = iop13xx_irq_mask3,
+        .irq_mask   = iop13xx_irq_mask3,
+        .irq_unmask = iop13xx_irq_unmask3,
 };
 
 extern void iop_init_cp6_handler(void);
diff --git a/arch/arm/mach-iop13xx/msi.c b/arch/arm/mach-iop13xx/msi.c
index 7149fcc16c8a..c9c02e3698bc 100644
--- a/arch/arm/mach-iop13xx/msi.c
+++ b/arch/arm/mach-iop13xx/msi.c
@@ -156,14 +156,14 @@ void arch_teardown_msi_irq(unsigned int irq)
         destroy_irq(irq);
 }
 
-static void iop13xx_msi_nop(unsigned int irq)
+static void iop13xx_msi_nop(struct irq_data *d)
 {
         return;
 }
 
 static struct irq_chip iop13xx_msi_chip = {
         .name = "PCI-MSI",
-        .ack = iop13xx_msi_nop,
+        .irq_ack = iop13xx_msi_nop,
         .irq_enable = unmask_msi_irq,
         .irq_disable = mask_msi_irq,
         .irq_mask = mask_msi_irq,
diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c
index ba59b2d17db1..d3426a120599 100644
--- a/arch/arm/mach-iop32x/irq.c
+++ b/arch/arm/mach-iop32x/irq.c
@@ -32,24 +32,24 @@ static void intstr_write(u32 val)
 }
 
 static void
-iop32x_irq_mask(unsigned int irq)
+iop32x_irq_mask(struct irq_data *d)
 {
-        iop32x_mask &= ~(1 << irq);
+        iop32x_mask &= ~(1 << d->irq);
         intctl_write(iop32x_mask);
 }
 
 static void
-iop32x_irq_unmask(unsigned int irq)
+iop32x_irq_unmask(struct irq_data *d)
 {
-        iop32x_mask |= 1 << irq;
+        iop32x_mask |= 1 << d->irq;
         intctl_write(iop32x_mask);
 }
 
 struct irq_chip ext_chip = {
-        .name   = "IOP32x",
-        .ack    = iop32x_irq_mask,
-        .mask   = iop32x_irq_mask,
-        .unmask = iop32x_irq_unmask,
+        .name           = "IOP32x",
+        .irq_ack        = iop32x_irq_mask,
+        .irq_mask       = iop32x_irq_mask,
+        .irq_unmask     = iop32x_irq_unmask,
 };
 
 void __init iop32x_init_irq(void)
diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c
index abb4ea2ed4fd..0ff2f74363a5 100644
--- a/arch/arm/mach-iop33x/irq.c
+++ b/arch/arm/mach-iop33x/irq.c
@@ -53,45 +53,45 @@ static void intsize_write(u32 val)
 }
 
 static void
-iop33x_irq_mask1 (unsigned int irq)
+iop33x_irq_mask1 (struct irq_data *d)
 {
-        iop33x_mask0 &= ~(1 << irq);
+        iop33x_mask0 &= ~(1 << d->irq);
         intctl0_write(iop33x_mask0);
 }
 
 static void
-iop33x_irq_mask2 (unsigned int irq)
+iop33x_irq_mask2 (struct irq_data *d)
 {
-        iop33x_mask1 &= ~(1 << (irq - 32));
+        iop33x_mask1 &= ~(1 << (d->irq - 32));
         intctl1_write(iop33x_mask1);
 }
 
 static void
-iop33x_irq_unmask1(unsigned int irq)
+iop33x_irq_unmask1(struct irq_data *d)
 {
-        iop33x_mask0 |= 1 << irq;
+        iop33x_mask0 |= 1 << d->irq;
         intctl0_write(iop33x_mask0);
 }
 
 static void
-iop33x_irq_unmask2(unsigned int irq)
+iop33x_irq_unmask2(struct irq_data *d)
 {
-        iop33x_mask1 |= (1 << (irq - 32));
+        iop33x_mask1 |= (1 << (d->irq - 32));
         intctl1_write(iop33x_mask1);
 }
 
 struct irq_chip iop33x_irqchip1 = {
-        .name   = "IOP33x-1",
-        .ack    = iop33x_irq_mask1,
-        .mask   = iop33x_irq_mask1,
-        .unmask = iop33x_irq_unmask1,
+        .name           = "IOP33x-1",
+        .irq_ack        = iop33x_irq_mask1,
+        .irq_mask       = iop33x_irq_mask1,
+        .irq_unmask     = iop33x_irq_unmask1,
 };
 
 struct irq_chip iop33x_irqchip2 = {
-        .name   = "IOP33x-2",
-        .ack    = iop33x_irq_mask2,
-        .mask   = iop33x_irq_mask2,
-        .unmask = iop33x_irq_unmask2,
+        .name           = "IOP33x-2",
+        .irq_ack        = iop33x_irq_mask2,
+        .irq_mask       = iop33x_irq_mask2,
+        .irq_unmask     = iop33x_irq_unmask2,
 };
 
 void __init iop33x_init_irq(void)
diff --git a/arch/arm/mach-ixp2000/core.c b/arch/arm/mach-ixp2000/core.c
index e24e3d05397f..5fc4e064b650 100644
--- a/arch/arm/mach-ixp2000/core.c
+++ b/arch/arm/mach-ixp2000/core.c
@@ -309,9 +309,9 @@ static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irq_desc *desc)
         }
 }
 
-static int ixp2000_GPIO_irq_type(unsigned int irq, unsigned int type)
+static int ixp2000_GPIO_irq_type(struct irq_data *d, unsigned int type)
 {
-        int line = irq - IRQ_IXP2000_GPIO0;
+        int line = d->irq - IRQ_IXP2000_GPIO0;
 
         /*
          * First, configure this GPIO line as an input.
@@ -342,8 +342,10 @@ static int ixp2000_GPIO_irq_type(unsigned int irq, unsigned int type)
         return 0;
 }
 
-static void ixp2000_GPIO_irq_mask_ack(unsigned int irq)
+static void ixp2000_GPIO_irq_mask_ack(struct irq_data *d)
 {
+        unsigned int irq = d->irq;
+
         ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
 
         ixp2000_reg_write(IXP2000_GPIO_EDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
@@ -351,38 +353,42 @@ static void ixp2000_GPIO_irq_mask_ack(unsigned int irq)
         ixp2000_reg_wrb(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0)));
 }
 
-static void ixp2000_GPIO_irq_mask(unsigned int irq)
+static void ixp2000_GPIO_irq_mask(struct irq_data *d)
 {
+        unsigned int irq = d->irq;
+
         ixp2000_reg_wrb(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
 }
 
-static void ixp2000_GPIO_irq_unmask(unsigned int irq)
+static void ixp2000_GPIO_irq_unmask(struct irq_data *d)
 {
+        unsigned int irq = d->irq;
+
         ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
 }
 
 static struct irq_chip ixp2000_GPIO_irq_chip = {
-        .ack            = ixp2000_GPIO_irq_mask_ack,
-        .mask           = ixp2000_GPIO_irq_mask,
-        .unmask         = ixp2000_GPIO_irq_unmask,
-        .set_type       = ixp2000_GPIO_irq_type,
+        .irq_ack        = ixp2000_GPIO_irq_mask_ack,
+        .irq_mask       = ixp2000_GPIO_irq_mask,
+        .irq_unmask     = ixp2000_GPIO_irq_unmask,
+        .irq_set_type   = ixp2000_GPIO_irq_type,
 };
 
-static void ixp2000_pci_irq_mask(unsigned int irq)
+static void ixp2000_pci_irq_mask(struct irq_data *d)
 {
         unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
-        if (irq == IRQ_IXP2000_PCIA)
+        if (d->irq == IRQ_IXP2000_PCIA)
                 ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26)));
-        else if (irq == IRQ_IXP2000_PCIB)
+        else if (d->irq == IRQ_IXP2000_PCIB)
                 ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27)));
 }
 
-static void ixp2000_pci_irq_unmask(unsigned int irq)
+static void ixp2000_pci_irq_unmask(struct irq_data *d)
 {
         unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
-        if (irq == IRQ_IXP2000_PCIA)
+        if (d->irq == IRQ_IXP2000_PCIA)
                 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 26)));
-        else if (irq == IRQ_IXP2000_PCIB)
+        else if (d->irq == IRQ_IXP2000_PCIB)
                 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 27)));
 }
 
@@ -401,44 +407,44 @@ static void ixp2000_err_irq_handler(unsigned int irq, struct irq_desc *desc)
         }
 }
 
-static void ixp2000_err_irq_mask(unsigned int irq)
+static void ixp2000_err_irq_mask(struct irq_data *d)
 {
         ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_CLR,
-                        (1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
+                        (1 << (d->irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
 }
 
-static void ixp2000_err_irq_unmask(unsigned int irq)
+static void ixp2000_err_irq_unmask(struct irq_data *d)
 {
         ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_SET,
-                        (1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
+                        (1 << (d->irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
 }
 
 static struct irq_chip ixp2000_err_irq_chip = {
-        .ack    = ixp2000_err_irq_mask,
-        .mask   = ixp2000_err_irq_mask,
-        .unmask = ixp2000_err_irq_unmask
+        .irq_ack        = ixp2000_err_irq_mask,
+        .irq_mask       = ixp2000_err_irq_mask,
+        .irq_unmask     = ixp2000_err_irq_unmask
 };
 
 static struct irq_chip ixp2000_pci_irq_chip = {
-        .ack    = ixp2000_pci_irq_mask,
-        .mask   = ixp2000_pci_irq_mask,
-        .unmask = ixp2000_pci_irq_unmask
+        .irq_ack        = ixp2000_pci_irq_mask,
+        .irq_mask       = ixp2000_pci_irq_mask,
+        .irq_unmask     = ixp2000_pci_irq_unmask
 };
 
-static void ixp2000_irq_mask(unsigned int irq)
+static void ixp2000_irq_mask(struct irq_data *d)
 {
-        ixp2000_reg_wrb(IXP2000_IRQ_ENABLE_CLR, (1 << irq));
+        ixp2000_reg_wrb(IXP2000_IRQ_ENABLE_CLR, (1 << d->irq));
 }
 
-static void ixp2000_irq_unmask(unsigned int irq)
+static void ixp2000_irq_unmask(struct irq_data *d)
 {
-        ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << irq));
+        ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << d->irq));
 }
 
 static struct irq_chip ixp2000_irq_chip = {
-        .ack    = ixp2000_irq_mask,
-        .mask   = ixp2000_irq_mask,
-        .unmask = ixp2000_irq_unmask
+        .irq_ack        = ixp2000_irq_mask,
+        .irq_mask       = ixp2000_irq_mask,
+        .irq_unmask     = ixp2000_irq_unmask
 };
 
 void __init ixp2000_init_irq(void)
diff --git a/arch/arm/mach-ixp2000/ixdp2x00.c b/arch/arm/mach-ixp2000/ixdp2x00.c
index 91fffb9b2084..7d90d3f13ee8 100644
--- a/arch/arm/mach-ixp2000/ixdp2x00.c
+++ b/arch/arm/mach-ixp2000/ixdp2x00.c
@@ -63,7 +63,7 @@ static struct slowport_cfg slowport_cpld_cfg = {
 };
 #endif
 
-static void ixdp2x00_irq_mask(unsigned int irq)
+static void ixdp2x00_irq_mask(struct irq_data *d)
 {
         unsigned long dummy;
         static struct slowport_cfg old_cfg;
@@ -78,7 +78,7 @@ static void ixdp2x00_irq_mask(unsigned int irq)
 #endif
 
         dummy = *board_irq_mask;
-        dummy |=  IXP2000_BOARD_IRQ_MASK(irq);
+        dummy |=  IXP2000_BOARD_IRQ_MASK(d->irq);
         ixp2000_reg_wrb(board_irq_mask, dummy);
 
 #ifdef CONFIG_ARCH_IXDP2400
@@ -87,7 +87,7 @@ static void ixdp2x00_irq_mask(unsigned int irq)
 #endif
 }
 
-static void ixdp2x00_irq_unmask(unsigned int irq)
+static void ixdp2x00_irq_unmask(struct irq_data *d)
 {
         unsigned long dummy;
         static struct slowport_cfg old_cfg;
@@ -98,7 +98,7 @@ static void ixdp2x00_irq_unmask(unsigned int irq)
 #endif
 
         dummy = *board_irq_mask;
-        dummy &=  ~IXP2000_BOARD_IRQ_MASK(irq);
+        dummy &=  ~IXP2000_BOARD_IRQ_MASK(d->irq);
         ixp2000_reg_wrb(board_irq_mask, dummy);
 
         if (machine_is_ixdp2400()) 
@@ -111,7 +111,7 @@ static void ixdp2x00_irq_handler(unsigned int irq, struct irq_desc *desc)
         static struct slowport_cfg old_cfg;
         int i;
 
-        desc->chip->mask(irq);
+        desc->irq_data.chip->irq_mask(&desc->irq_data);
 
 #ifdef CONFIG_ARCH_IXDP2400
         if (machine_is_ixdp2400())
@@ -133,13 +133,13 @@ static void ixdp2x00_irq_handler(unsigned int irq, struct irq_desc *desc)
                 }
         }
 
-        desc->chip->unmask(irq);
+        desc->irq_data.chip->irq_unmask(&desc->irq_data);
 }
 
 static struct irq_chip ixdp2x00_cpld_irq_chip = {
-        .ack    = ixdp2x00_irq_mask,
-        .mask   = ixdp2x00_irq_mask,
-        .unmask = ixdp2x00_irq_unmask
+        .irq_ack        = ixdp2x00_irq_mask,
+        .irq_mask       = ixdp2x00_irq_mask,
+        .irq_unmask     = ixdp2x00_irq_unmask
 };
 
 void __init ixdp2x00_init_irq(volatile unsigned long *stat_reg, volatile unsigned long *mask_reg, unsigned long nr_of_irqs)
diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c
index 6c121bdbe311..34b1b2af37c8 100644
--- a/arch/arm/mach-ixp2000/ixdp2x01.c
+++ b/arch/arm/mach-ixp2000/ixdp2x01.c
@@ -48,16 +48,16 @@
 /*************************************************************************
  * IXDP2x01 IRQ Handling
  *************************************************************************/
-static void ixdp2x01_irq_mask(unsigned int irq)
+static void ixdp2x01_irq_mask(struct irq_data *d)
 {
         ixp2000_reg_wrb(IXDP2X01_INT_MASK_SET_REG,
-                                IXP2000_BOARD_IRQ_MASK(irq));
+                                IXP2000_BOARD_IRQ_MASK(d->irq));
 }
 
-static void ixdp2x01_irq_unmask(unsigned int irq)
+static void ixdp2x01_irq_unmask(struct irq_data *d)
 {
         ixp2000_reg_write(IXDP2X01_INT_MASK_CLR_REG,
-                                IXP2000_BOARD_IRQ_MASK(irq));
+                                IXP2000_BOARD_IRQ_MASK(d->irq));
 }
 
 static u32 valid_irq_mask;
@@ -67,7 +67,7 @@ static void ixdp2x01_irq_handler(unsigned int irq, struct irq_desc *desc)
         u32 ex_interrupt;
         int i;
 
-        desc->chip->mask(irq);
+        desc->irq_data.chip->irq_mask(&desc->irq_data);
 
         ex_interrupt = *IXDP2X01_INT_STAT_REG & valid_irq_mask;
 
@@ -83,13 +83,13 @@ static void ixdp2x01_irq_handler(unsigned int irq, struct irq_desc *desc)
                 }
         }
 
-        desc->chip->unmask(irq);
+        desc->irq_data.chip->irq_unmask(&desc->irq_data);
 }
 
 static struct irq_chip ixdp2x01_irq_chip = {
-        .mask   = ixdp2x01_irq_mask,
-        .ack    = ixdp2x01_irq_mask,
-        .unmask = ixdp2x01_irq_unmask
+        .irq_mask       = ixdp2x01_irq_mask,
+        .irq_ack        = ixdp2x01_irq_mask,
+        .irq_unmask     = ixdp2x01_irq_unmask
 };
 
 /*
diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c
index aa4c4420ff3d..9c8a33903216 100644
--- a/arch/arm/mach-ixp23xx/core.c
+++ b/arch/arm/mach-ixp23xx/core.c
@@ -111,9 +111,9 @@ enum ixp23xx_irq_type {
 
 static void ixp23xx_config_irq(unsigned int, enum ixp23xx_irq_type);
 
-static int ixp23xx_irq_set_type(unsigned int irq, unsigned int type)
+static int ixp23xx_irq_set_type(struct irq_data *d, unsigned int type)
 {
-        int line = irq - IRQ_IXP23XX_GPIO6 + 6;
+        int line = d->irq - IRQ_IXP23XX_GPIO6 + 6;
         u32 int_style;
         enum ixp23xx_irq_type irq_type;
         volatile u32 *int_reg;
@@ -149,7 +149,7 @@ static int ixp23xx_irq_set_type(unsigned int irq, unsigned int type)
                 return -EINVAL;
         }
 
-        ixp23xx_config_irq(irq, irq_type);
+        ixp23xx_config_irq(d->irq, irq_type);
 
         if (line >= 8) {        /* pins 8-15 */
                 line -= 8;
@@ -173,9 +173,10 @@ static int ixp23xx_irq_set_type(unsigned int irq, unsigned int type)
         return 0;
 }
 
-static void ixp23xx_irq_mask(unsigned int irq)
+static void ixp23xx_irq_mask(struct irq_data *d)
 {
         volatile unsigned long *intr_reg;
+        unsigned int irq = d->irq;
 
         if (irq >= 56)
                 irq += 8;
@@ -184,9 +185,9 @@ static void ixp23xx_irq_mask(unsigned int irq)
         *intr_reg &= ~(1 << (irq % 32));
 }
 
-static void ixp23xx_irq_ack(unsigned int irq)
+static void ixp23xx_irq_ack(struct irq_data *d)
 {
-        int line = irq - IRQ_IXP23XX_GPIO6 + 6;
+        int line = d->irq - IRQ_IXP23XX_GPIO6 + 6;
 
         if ((line < 6) || (line > 15))
                 return;
@@ -198,11 +199,12 @@ static void ixp23xx_irq_ack(unsigned int irq)
  * Level triggered interrupts on GPIO lines can only be cleared when the
  * interrupt condition disappears.
  */
-static void ixp23xx_irq_level_unmask(unsigned int irq)
+static void ixp23xx_irq_level_unmask(struct irq_data *d)
 {
         volatile unsigned long *intr_reg;
+        unsigned int irq = d->irq;
 
-        ixp23xx_irq_ack(irq);
+        ixp23xx_irq_ack(d);
 
         if (irq >= 56)
                 irq += 8;
@@ -211,9 +213,10 @@ static void ixp23xx_irq_level_unmask(unsigned int irq)
         *intr_reg |= (1 << (irq % 32));
 }
 
-static void ixp23xx_irq_edge_unmask(unsigned int irq)
+static void ixp23xx_irq_edge_unmask(struct irq_data *d)
 {
         volatile unsigned long *intr_reg;
+        unsigned int irq = d->irq;
 
         if (irq >= 56)
                 irq += 8;
@@ -223,26 +226,30 @@ static void ixp23xx_irq_edge_unmask(unsigned int irq)
 }
 
 static struct irq_chip ixp23xx_irq_level_chip = {
-        .ack            = ixp23xx_irq_mask,
-        .mask           = ixp23xx_irq_mask,
-        .unmask         = ixp23xx_irq_level_unmask,
-        .set_type       = ixp23xx_irq_set_type
+        .irq_ack        = ixp23xx_irq_mask,
+        .irq_mask       = ixp23xx_irq_mask,
+        .irq_unmask     = ixp23xx_irq_level_unmask,
+        .irq_set_type   = ixp23xx_irq_set_type
 };
 
 static struct irq_chip ixp23xx_irq_edge_chip = {
-        .ack            = ixp23xx_irq_ack,
-        .mask           = ixp23xx_irq_mask,
-        .unmask         = ixp23xx_irq_edge_unmask,
-        .set_type       = ixp23xx_irq_set_type
+        .irq_ack        = ixp23xx_irq_ack,
+        .irq_mask       = ixp23xx_irq_mask,
+        .irq_unmask     = ixp23xx_irq_edge_unmask,
+        .irq_set_type   = ixp23xx_irq_set_type
 };
 
-static void ixp23xx_pci_irq_mask(unsigned int irq)
+static void ixp23xx_pci_irq_mask(struct irq_data *d)
 {
+        unsigned int irq = d->irq;
+
         *IXP23XX_PCI_XSCALE_INT_ENABLE &= ~(1 << (IRQ_IXP23XX_INTA + 27 - irq));
 }
 
-static void ixp23xx_pci_irq_unmask(unsigned int irq)
+static void ixp23xx_pci_irq_unmask(struct irq_data *d)
 {
+        unsigned int irq = d->irq;
+
         *IXP23XX_PCI_XSCALE_INT_ENABLE |= (1 << (IRQ_IXP23XX_INTA + 27 - irq));
 }
 
@@ -256,7 +263,7 @@ static void pci_handler(unsigned int irq, struct irq_desc *desc)
 
         pci_interrupt = *IXP23XX_PCI_XSCALE_INT_STATUS;
 
-        desc->chip->ack(irq);
+        desc->irq_data.chip->irq_ack(&desc->irq_data);
 
         /* See which PCI_INTA, or PCI_INTB interrupted */
         if (pci_interrupt & (1 << 26)) {
@@ -269,13 +276,13 @@ static void pci_handler(unsigned int irq, struct irq_desc *desc)
 
         generic_handle_irq(irqno);
 
-        desc->chip->unmask(irq);
+        desc->irq_data.chip->irq_unmask(&desc->irq_data);
 }
 
 static struct irq_chip ixp23xx_pci_irq_chip = {
-        .ack    = ixp23xx_pci_irq_mask,
-        .mask   = ixp23xx_pci_irq_mask,
-        .unmask = ixp23xx_pci_irq_unmask
+        .irq_ack        = ixp23xx_pci_irq_mask,
+        .irq_mask       = ixp23xx_pci_irq_mask,
+        .irq_unmask     = ixp23xx_pci_irq_unmask
 };
 
 static void ixp23xx_config_irq(unsigned int irq, enum ixp23xx_irq_type type)
diff --git a/arch/arm/mach-ixp23xx/ixdp2351.c b/arch/arm/mach-ixp23xx/ixdp2351.c
index 664e39c2a903..181116aa6591 100644
--- a/arch/arm/mach-ixp23xx/ixdp2351.c
+++ b/arch/arm/mach-ixp23xx/ixdp2351.c
@@ -48,14 +48,14 @@
 /*
  * IXDP2351 Interrupt Handling
  */
-static void ixdp2351_inta_mask(unsigned int irq)
+static void ixdp2351_inta_mask(struct irq_data *d)
 {
-        *IXDP2351_CPLD_INTA_MASK_SET_REG = IXDP2351_INTA_IRQ_MASK(irq);
+        *IXDP2351_CPLD_INTA_MASK_SET_REG = IXDP2351_INTA_IRQ_MASK(d->irq);
 }
 
-static void ixdp2351_inta_unmask(unsigned int irq)
+static void ixdp2351_inta_unmask(struct irq_data *d)
 {
-        *IXDP2351_CPLD_INTA_MASK_CLR_REG = IXDP2351_INTA_IRQ_MASK(irq);
+        *IXDP2351_CPLD_INTA_MASK_CLR_REG = IXDP2351_INTA_IRQ_MASK(d->irq);
 }
 
 static void ixdp2351_inta_handler(unsigned int irq, struct irq_desc *desc)
@@ -64,7 +64,7 @@ static void ixdp2351_inta_handler(unsigned int irq, struct irq_desc *desc)
                 *IXDP2351_CPLD_INTA_STAT_REG & IXDP2351_INTA_IRQ_VALID;
         int i;
 
-        desc->chip->mask(irq);
+        desc->irq_data.chip->irq_mask(&desc->irq_data);
 
         for (i = 0; i < IXDP2351_INTA_IRQ_NUM; i++) {
                 if (ex_interrupt & (1 << i)) {
@@ -74,23 +74,23 @@ static void ixdp2351_inta_handler(unsigned int irq, struct irq_desc *desc)
                 }
         }
 
-        desc->chip->unmask(irq);
+        desc->irq_data.chip->irq_unmask(&desc->irq_data);
 }
 
 static struct irq_chip ixdp2351_inta_chip = {
-        .ack    = ixdp2351_inta_mask,
-        .mask   = ixdp2351_inta_mask,
-        .unmask = ixdp2351_inta_unmask
+        .irq_ack        = ixdp2351_inta_mask,
+        .irq_mask       = ixdp2351_inta_mask,
+        .irq_unmask     = ixdp2351_inta_unmask
 };
 
-static void ixdp2351_intb_mask(unsigned int irq)
+static void ixdp2351_intb_mask(struct irq_data *d)
 {
-        *IXDP2351_CPLD_INTB_MASK_SET_REG = IXDP2351_INTB_IRQ_MASK(irq);
+        *IXDP2351_CPLD_INTB_MASK_SET_REG = IXDP2351_INTB_IRQ_MASK(d->irq);
 }
 
-static void ixdp2351_intb_unmask(unsigned int irq)
+static void ixdp2351_intb_unmask(struct irq_data *d)
 {
-        *IXDP2351_CPLD_INTB_MASK_CLR_REG = IXDP2351_INTB_IRQ_MASK(irq);
+        *IXDP2351_CPLD_INTB_MASK_CLR_REG = IXDP2351_INTB_IRQ_MASK(d->irq);
 }
 
 static void ixdp2351_intb_handler(unsigned int irq, struct irq_desc *desc)
@@ -99,7 +99,7 @@ static void ixdp2351_intb_handler(unsigned int irq, struct irq_desc *desc)
                 *IXDP2351_CPLD_INTB_STAT_REG & IXDP2351_INTB_IRQ_VALID;
         int i;
 
-        desc->chip->ack(irq);
+        desc->irq_data.chip->irq_ack(&desc->irq_data);
 
         for (i = 0; i < IXDP2351_INTB_IRQ_NUM; i++) {
                 if (ex_interrupt & (1 << i)) {
@@ -109,13 +109,13 @@ static void ixdp2351_intb_handler(unsigned int irq, struct irq_desc *desc)
                 }
         }
 
-        desc->chip->unmask(irq);
+        desc->irq_data.chip->irq_unmask(&desc->irq_data);
 }
 
 static struct irq_chip ixdp2351_intb_chip = {
-        .ack    = ixdp2351_intb_mask,
-        .mask   = ixdp2351_intb_mask,
-        .unmask = ixdp2351_intb_unmask
+        .irq_ack        = ixdp2351_intb_mask,
+        .irq_mask       = ixdp2351_intb_mask,
+        .irq_unmask     = ixdp2351_intb_unmask
 };
 
 void __init ixdp2351_init_irq(void)
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 4dbfcbb9163c..4dc68d6bb6be 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -128,9 +128,9 @@ int irq_to_gpio(unsigned int irq)
 }
 EXPORT_SYMBOL(irq_to_gpio);
 
-static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type)
+static int ixp4xx_set_irq_type(struct irq_data *d, unsigned int type)
 {
-        int line = irq2gpio[irq];
+        int line = irq2gpio[d->irq];
         u32 int_style;
         enum ixp4xx_irq_type irq_type;
         volatile u32 *int_reg;
@@ -167,9 +167,9 @@ static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type)
         }
 
         if (irq_type == IXP4XX_IRQ_EDGE)
-                ixp4xx_irq_edge |= (1 << irq);
+                ixp4xx_irq_edge |= (1 << d->irq);
         else
-                ixp4xx_irq_edge &= ~(1 << irq);
+                ixp4xx_irq_edge &= ~(1 << d->irq);
 
         if (line >= 8) {        /* pins 8-15 */
                 line -= 8;
@@ -188,22 +188,22 @@ static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type)
         *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
 
         /* Configure the line as an input */
-        gpio_line_config(irq2gpio[irq], IXP4XX_GPIO_IN);
+        gpio_line_config(irq2gpio[d->irq], IXP4XX_GPIO_IN);
 
         return 0;
 }
 
-static void ixp4xx_irq_mask(unsigned int irq)
+static void ixp4xx_irq_mask(struct irq_data *d)
 {
-        if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && irq >= 32)
-                *IXP4XX_ICMR2 &= ~(1 << (irq - 32));
+        if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32)
+                *IXP4XX_ICMR2 &= ~(1 << (d->irq - 32));
         else
-                *IXP4XX_ICMR &= ~(1 << irq);
+                *IXP4XX_ICMR &= ~(1 << d->irq);
 }
 
-static void ixp4xx_irq_ack(unsigned int irq)
+static void ixp4xx_irq_ack(struct irq_data *d)
 {
-        int line = (irq < 32) ? irq2gpio[irq] : -1;
+        int line = (d->irq < 32) ? irq2gpio[d->irq] : -1;
 
         if (line >= 0)
                 *IXP4XX_GPIO_GPISR = (1 << line);
@@ -213,23 +213,23 @@ static void ixp4xx_irq_ack(unsigned int irq)
  * Level triggered interrupts on GPIO lines can only be cleared when the
  * interrupt condition disappears.
  */
-static void ixp4xx_irq_unmask(unsigned int irq)
+static void ixp4xx_irq_unmask(struct irq_data *d)
 {
-        if (!(ixp4xx_irq_edge & (1 << irq)))
-                ixp4xx_irq_ack(irq);
+        if (!(ixp4xx_irq_edge & (1 << d->irq)))
+                ixp4xx_irq_ack(d);
 
-        if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && irq >= 32)
-                *IXP4XX_ICMR2 |= (1 << (irq - 32));
+        if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32)
+                *IXP4XX_ICMR2 |= (1 << (d->irq - 32));
         else
-                *IXP4XX_ICMR |= (1 << irq);
+                *IXP4XX_ICMR |= (1 << d->irq);
 }
 
 static struct irq_chip ixp4xx_irq_chip = {
         .name           = "IXP4xx",
-        .ack            = ixp4xx_irq_ack,
-        .mask           = ixp4xx_irq_mask,
-        .unmask         = ixp4xx_irq_unmask,
-        .set_type       = ixp4xx_set_irq_type,
+        .irq_ack        = ixp4xx_irq_ack,
+        .irq_mask       = ixp4xx_irq_mask,
+        .irq_unmask     = ixp4xx_irq_unmask,
+        .irq_set_type   = ixp4xx_set_irq_type,
 };
 
 void __init ixp4xx_init_irq(void)
diff --git a/arch/arm/mach-ks8695/irq.c b/arch/arm/mach-ks8695/irq.c
index e375c1d53f81..7998ccaa6333 100644
--- a/arch/arm/mach-ks8695/irq.c
+++ b/arch/arm/mach-ks8695/irq.c
@@ -34,29 +34,29 @@
 #include <mach/regs-irq.h>
 #include <mach/regs-gpio.h>
 
-static void ks8695_irq_mask(unsigned int irqno)
+static void ks8695_irq_mask(struct irq_data *d)
 {
         unsigned long inten;
 
         inten = __raw_readl(KS8695_IRQ_VA + KS8695_INTEN);
-        inten &= ~(1 << irqno);
+        inten &= ~(1 << d->irq);
 
         __raw_writel(inten, KS8695_IRQ_VA + KS8695_INTEN);
 }
 
-static void ks8695_irq_unmask(unsigned int irqno)
+static void ks8695_irq_unmask(struct irq_data *d)
 {
         unsigned long inten;
 
         inten = __raw_readl(KS8695_IRQ_VA + KS8695_INTEN);
-        inten |= (1 << irqno);
+        inten |= (1 << d->irq);
 
         __raw_writel(inten, KS8695_IRQ_VA + KS8695_INTEN);
 }
 
-static void ks8695_irq_ack(unsigned int irqno)
+static void ks8695_irq_ack(struct irq_data *d)
 {
-        __raw_writel((1 << irqno), KS8695_IRQ_VA + KS8695_INTST);
+        __raw_writel((1 << d->irq), KS8695_IRQ_VA + KS8695_INTST);
 }
 
 
@@ -64,7 +64,7 @@ static struct irq_chip ks8695_irq_level_chip;
 static struct irq_chip ks8695_irq_edge_chip;
 
 
-static int ks8695_irq_set_type(unsigned int irqno, unsigned int type)
+static int ks8695_irq_set_type(struct irq_data *d, unsigned int type)
 {
         unsigned long ctrl, mode;
         unsigned short level_triggered = 0;
@@ -93,7 +93,7 @@ static int ks8695_irq_set_type(unsigned int irqno, unsigned int type)
                         return -EINVAL;
         }
 
-        switch (irqno) {
+        switch (d->irq) {
                 case KS8695_IRQ_EXTERN0:
                         ctrl &= ~IOPC_IOEINT0TM;
                         ctrl |= IOPC_IOEINT0_MODE(mode);
@@ -115,12 +115,12 @@ static int ks8695_irq_set_type(unsigned int irqno, unsigned int type)
         }
 
         if (level_triggered) {
-                set_irq_chip(irqno, &ks8695_irq_level_chip);
-                set_irq_handler(irqno, handle_level_irq);
+                set_irq_chip(d->irq, &ks8695_irq_level_chip);
+                set_irq_handler(d->irq, handle_level_irq);
         }
         else {
-                set_irq_chip(irqno, &ks8695_irq_edge_chip);
-                set_irq_handler(irqno, handle_edge_irq);
+                set_irq_chip(d->irq, &ks8695_irq_edge_chip);
+                set_irq_handler(d->irq, handle_edge_irq);
         }
 
         __raw_writel(ctrl, KS8695_GPIO_VA + KS8695_IOPC);
@@ -128,17 +128,17 @@ static int ks8695_irq_set_type(unsigned int irqno, unsigned int type)
 }
 
 static struct irq_chip ks8695_irq_level_chip = {
-        .ack            = ks8695_irq_mask,
-        .mask           = ks8695_irq_mask,
-        .unmask         = ks8695_irq_unmask,
-        .set_type       = ks8695_irq_set_type,
+        .irq_ack        = ks8695_irq_mask,
+        .irq_mask       = ks8695_irq_mask,
+        .irq_unmask     = ks8695_irq_unmask,
+        .irq_set_type   = ks8695_irq_set_type,
 };
 
 static struct irq_chip ks8695_irq_edge_chip = {
-        .ack            = ks8695_irq_ack,
-        .mask           = ks8695_irq_mask,
-        .unmask         = ks8695_irq_unmask,
-        .set_type       = ks8695_irq_set_type,
+        .irq_ack        = ks8695_irq_ack,
+        .irq_mask       = ks8695_irq_mask,
+        .irq_unmask     = ks8695_irq_unmask,
+        .irq_set_type   = ks8695_irq_set_type,
 };
 
 void __init ks8695_init_irq(void)
@@ -164,7 +164,8 @@ void __init ks8695_init_irq(void)
 
                         /* Edge-triggered interrupts */
                         default:
-                                ks8695_irq_ack(irq);    /* clear pending bit */
+                                /* clear pending bit */
+                                ks8695_irq_ack(irq_get_irq_data(irq));
                                 set_irq_chip(irq, &ks8695_irq_edge_chip);
                                 set_irq_handler(irq, handle_edge_irq);
                 }
diff --git a/arch/arm/mach-lh7a40x/arch-kev7a400.c b/arch/arm/mach-lh7a40x/arch-kev7a400.c
index 9088c16662e8..71129c33c7d2 100644
--- a/arch/arm/mach-lh7a40x/arch-kev7a400.c
+++ b/arch/arm/mach-lh7a40x/arch-kev7a400.c
@@ -46,28 +46,28 @@ void __init kev7a400_map_io(void)
 
 static u16 CPLD_IRQ_mask;       /* Mask for CPLD IRQs, 1 == unmasked */
 
-static void kev7a400_ack_cpld_irq (u32 irq)
+static void kev7a400_ack_cpld_irq(struct irq_data *d)
 {
-        CPLD_CL_INT = 1 << (irq - IRQ_KEV7A400_CPLD);
+        CPLD_CL_INT = 1 << (d->irq - IRQ_KEV7A400_CPLD);
 }
 
-static void kev7a400_mask_cpld_irq (u32 irq)
+static void kev7a400_mask_cpld_irq(struct irq_data *d)
 {
-        CPLD_IRQ_mask &= ~(1 << (irq - IRQ_KEV7A400_CPLD));
+        CPLD_IRQ_mask &= ~(1 << (d->irq - IRQ_KEV7A400_CPLD));
         CPLD_WR_PB_INT_MASK = CPLD_IRQ_mask;
 }
 
-static void kev7a400_unmask_cpld_irq (u32 irq)
+static void kev7a400_unmask_cpld_irq(struct irq_data *d)
 {
-        CPLD_IRQ_mask |= 1 << (irq - IRQ_KEV7A400_CPLD);
+        CPLD_IRQ_mask |= 1 << (d->irq - IRQ_KEV7A400_CPLD);
         CPLD_WR_PB_INT_MASK = CPLD_IRQ_mask;
 }
 
 static struct irq_chip kev7a400_cpld_chip = {
-        .name   = "CPLD",
-        .ack    = kev7a400_ack_cpld_irq,
-        .mask   = kev7a400_mask_cpld_irq,
-        .unmask = kev7a400_unmask_cpld_irq,
+        .name           = "CPLD",
+        .irq_ack        = kev7a400_ack_cpld_irq,
+        .irq_mask       = kev7a400_mask_cpld_irq,
+        .irq_unmask     = kev7a400_unmask_cpld_irq,
 };
 
 
diff --git a/arch/arm/mach-lh7a40x/arch-lpd7a40x.c b/arch/arm/mach-lh7a40x/arch-lpd7a40x.c
index 7315a569aea1..e735546181ad 100644
--- a/arch/arm/mach-lh7a40x/arch-lpd7a40x.c
+++ b/arch/arm/mach-lh7a40x/arch-lpd7a40x.c
@@ -159,7 +159,7 @@ static void __init lpd7a40x_init (void)
 #endif
 }
 
-static void lh7a40x_ack_cpld_irq (u32 irq)
+static void lh7a40x_ack_cpld_irq(struct irq_data *d)
 {
         /* CPLD doesn't have ack capability, but some devices may */
 
@@ -167,14 +167,14 @@ static void lh7a40x_ack_cpld_irq (u32 irq)
         /* The touch control *must* mask the interrupt because the
          * interrupt bit is read by the driver to determine if the pen
          * is still down. */
-        if (irq == IRQ_TOUCH)
+        if (d->irq == IRQ_TOUCH)
                 CPLD_INTERRUPTS |= CPLD_INTMASK_TOUCH;
 #endif
 }
 
-static void lh7a40x_mask_cpld_irq (u32 irq)
+static void lh7a40x_mask_cpld_irq(struct irq_data *d)
 {
-        switch (irq) {
+        switch (d->irq) {
         case IRQ_LPD7A40X_ETH_INT:
                 CPLD_INTERRUPTS |= CPLD_INTMASK_ETHERNET;
                 break;
@@ -186,9 +186,9 @@ static void lh7a40x_mask_cpld_irq (u32 irq)
         }
 }
 
-static void lh7a40x_unmask_cpld_irq (u32 irq)
+static void lh7a40x_unmask_cpld_irq(struct irq_data *d)
 {
-        switch (irq) {
+        switch (d->irq) {
         case IRQ_LPD7A40X_ETH_INT:
                 CPLD_INTERRUPTS &= ~CPLD_INTMASK_ETHERNET;
                 break;
@@ -201,17 +201,17 @@ static void lh7a40x_unmask_cpld_irq (u32 irq)
 }
 
 static struct irq_chip lpd7a40x_cpld_chip = {
-        .name   = "CPLD",
-        .ack    = lh7a40x_ack_cpld_irq,
-        .mask   = lh7a40x_mask_cpld_irq,
-        .unmask = lh7a40x_unmask_cpld_irq,
+        .name           = "CPLD",
+        .irq_ack        = lh7a40x_ack_cpld_irq,
+        .irq_mask       = lh7a40x_mask_cpld_irq,
+        .irq_unmask     = lh7a40x_unmask_cpld_irq,
 };
 
 static void lpd7a40x_cpld_handler (unsigned int irq, struct irq_desc *desc)
 {
         unsigned int mask = CPLD_INTERRUPTS;
 
-        desc->chip->ack (irq);
+        desc->irq_data.chip->irq_ack(&desc->irq_data);
 
         if ((mask & (1<<0)) == 0)       /* WLAN */
                 generic_handle_irq(IRQ_LPD7A40X_ETH_INT);
@@ -221,7 +221,8 @@ static void lpd7a40x_cpld_handler (unsigned int irq, struct irq_desc *desc)
                 generic_handle_irq(IRQ_TOUCH);
 #endif
 
-        desc->chip->unmask (irq); /* Level-triggered need this */
+        /* Level-triggered need this */
+        desc->irq_data.chip->irq_unmask(&desc->irq_data);
 }
 
 
diff --git a/arch/arm/mach-lh7a40x/irq-lh7a400.c b/arch/arm/mach-lh7a40x/irq-lh7a400.c
index 1ad3afcf6b3d..f2e7e655ca35 100644
--- a/arch/arm/mach-lh7a40x/irq-lh7a400.c
+++ b/arch/arm/mach-lh7a40x/irq-lh7a400.c
@@ -21,34 +21,34 @@
 
   /* CPU IRQ handling */
 
-static void lh7a400_mask_irq (u32 irq)
+static void lh7a400_mask_irq(struct irq_data *d)
 {
-        INTC_INTENC = (1 << irq);
+        INTC_INTENC = (1 << d->irq);
 }
 
-static void lh7a400_unmask_irq (u32 irq)
+static void lh7a400_unmask_irq(struct irq_data *d)
 {
-        INTC_INTENS = (1 << irq);
+        INTC_INTENS = (1 << d->irq);
 }
 
-static void lh7a400_ack_gpio_irq (u32 irq)
+static void lh7a400_ack_gpio_irq(struct irq_data *d)
 {
-        GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (irq));
-        INTC_INTENC = (1 << irq);
+        GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (d->irq));
+        INTC_INTENC = (1 << d->irq);
 }
 
 static struct irq_chip lh7a400_internal_chip = {
-        .name   = "MPU",
-        .ack    = lh7a400_mask_irq, /* Level triggering -> mask is ack */
-        .mask   = lh7a400_mask_irq,
-        .unmask = lh7a400_unmask_irq,
+        .name           = "MPU",
+        .irq_ack        = lh7a400_mask_irq, /* Level triggering -> mask is ack */
+        .irq_mask       = lh7a400_mask_irq,
+        .irq_unmask     = lh7a400_unmask_irq,
 };
 
 static struct irq_chip lh7a400_gpio_chip = {
-        .name   = "GPIO",
-        .ack    = lh7a400_ack_gpio_irq,
-        .mask   = lh7a400_mask_irq,
-        .unmask = lh7a400_unmask_irq,
+        .name           = "GPIO",
+        .irq_ack        = lh7a400_ack_gpio_irq,
+        .irq_mask       = lh7a400_mask_irq,
+        .irq_unmask     = lh7a400_unmask_irq,
 };
 
 
diff --git a/arch/arm/mach-lh7a40x/irq-lh7a404.c b/arch/arm/mach-lh7a40x/irq-lh7a404.c
index 12b045b688c6..14b173389573 100644
--- a/arch/arm/mach-lh7a40x/irq-lh7a404.c
+++ b/arch/arm/mach-lh7a40x/irq-lh7a404.c
@@ -43,64 +43,64 @@ static unsigned char irq_pri_vic2[] = {
 
   /* CPU IRQ handling */
 
-static void lh7a404_vic1_mask_irq (u32 irq)
+static void lh7a404_vic1_mask_irq(struct irq_data *d)
 {
-        VIC1_INTENCLR = (1 << irq);
+        VIC1_INTENCLR = (1 << d->irq);
 }
 
-static void lh7a404_vic1_unmask_irq (u32 irq)
+static void lh7a404_vic1_unmask_irq(struct irq_data *d)
 {
-        VIC1_INTEN = (1 << irq);
+        VIC1_INTEN = (1 << d->irq);
 }
 
-static void lh7a404_vic2_mask_irq (u32 irq)
+static void lh7a404_vic2_mask_irq(struct irq_data *d)
 {
-        VIC2_INTENCLR = (1 << (irq - 32));
+        VIC2_INTENCLR = (1 << (d->irq - 32));
 }
 
-static void lh7a404_vic2_unmask_irq (u32 irq)
+static void lh7a404_vic2_unmask_irq(struct irq_data *d)
 {
-        VIC2_INTEN = (1 << (irq - 32));
+        VIC2_INTEN = (1 << (d->irq - 32));
 }
 
-static void lh7a404_vic1_ack_gpio_irq (u32 irq)
+static void lh7a404_vic1_ack_gpio_irq(struct irq_data *d)
 {
-        GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (irq));
-        VIC1_INTENCLR = (1 << irq);
+        GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (d->irq));
+        VIC1_INTENCLR = (1 << d->irq);
 }
 
-static void lh7a404_vic2_ack_gpio_irq (u32 irq)
+static void lh7a404_vic2_ack_gpio_irq(struct irq_data *d)
 {
-        GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (irq));
-        VIC2_INTENCLR = (1 << irq);
+        GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (d->irq));
+        VIC2_INTENCLR = (1 << d->irq);
 }
 
 static struct irq_chip lh7a404_vic1_chip = {
-        .name   = "VIC1",
-        .ack    = lh7a404_vic1_mask_irq, /* Because level-triggered */
-        .mask   = lh7a404_vic1_mask_irq,
-        .unmask = lh7a404_vic1_unmask_irq,
+        .name           = "VIC1",
+        .irq_ack        = lh7a404_vic1_mask_irq, /* Because level-triggered */
+        .irq_mask       = lh7a404_vic1_mask_irq,
+        .irq_unmask     = lh7a404_vic1_unmask_irq,
 };
 
 static struct irq_chip lh7a404_vic2_chip = {
-        .name   = "VIC2",
-        .ack    = lh7a404_vic2_mask_irq, /* Because level-triggered */
-        .mask   = lh7a404_vic2_mask_irq,
-        .unmask = lh7a404_vic2_unmask_irq,
+        .name           = "VIC2",
+        .irq_ack        = lh7a404_vic2_mask_irq, /* Because level-triggered */
+        .irq_mask       = lh7a404_vic2_mask_irq,
+        .irq_unmask     = lh7a404_vic2_unmask_irq,
 };
 
 static struct irq_chip lh7a404_gpio_vic1_chip = {
-        .name   = "GPIO-VIC1",
-        .ack    = lh7a404_vic1_ack_gpio_irq,
-        .mask   = lh7a404_vic1_mask_irq,
-        .unmask = lh7a404_vic1_unmask_irq,
+        .name           = "GPIO-VIC1",
+        .irq_ack        = lh7a404_vic1_ack_gpio_irq,
+        .irq_mask       = lh7a404_vic1_mask_irq,
+        .irq_unmask     = lh7a404_vic1_unmask_irq,
 };
 
 static struct irq_chip lh7a404_gpio_vic2_chip = {
-        .name   = "GPIO-VIC2",
-        .ack    = lh7a404_vic2_ack_gpio_irq,
-        .mask   = lh7a404_vic2_mask_irq,
-        .unmask = lh7a404_vic2_unmask_irq,
+        .name           = "GPIO-VIC2",
+        .irq_ack        = lh7a404_vic2_ack_gpio_irq,
+        .irq_mask       = lh7a404_vic2_mask_irq,
+        .irq_unmask     = lh7a404_vic2_unmask_irq,
 };
 
   /* IRQ initialization */
diff --git a/arch/arm/mach-lh7a40x/irq-lpd7a40x.c b/arch/arm/mach-lh7a40x/irq-lpd7a40x.c
index fd033bb4342f..1bfdcddcb93e 100644
--- a/arch/arm/mach-lh7a40x/irq-lpd7a40x.c
+++ b/arch/arm/mach-lh7a40x/irq-lpd7a40x.c
@@ -20,14 +20,14 @@
 
 #include "common.h"
 
-static void lh7a40x_ack_cpld_irq (u32 irq)
+static void lh7a40x_ack_cpld_irq(struct irq_data *d)
 {
         /* CPLD doesn't have ack capability */
 }
 
-static void lh7a40x_mask_cpld_irq (u32 irq)
+static void lh7a40x_mask_cpld_irq(struct irq_data *d)
 {
-        switch (irq) {
+        switch (d->irq) {
         case IRQ_LPD7A40X_ETH_INT:
                 CPLD_INTERRUPTS = CPLD_INTERRUPTS | 0x4;
                 break;
@@ -37,9 +37,9 @@ static void lh7a40x_mask_cpld_irq (u32 irq)
         }
 }
 
-static void lh7a40x_unmask_cpld_irq (u32 irq)
+static void lh7a40x_unmask_cpld_irq(struct irq_data *d)
 {
-        switch (irq) {
+        switch (d->irq) {
         case IRQ_LPD7A40X_ETH_INT:
                 CPLD_INTERRUPTS = CPLD_INTERRUPTS & ~ 0x4;
                 break;
@@ -50,17 +50,17 @@ static void lh7a40x_unmask_cpld_irq (u32 irq)
 }
 
 static struct irq_chip lh7a40x_cpld_chip = {
-        .name   = "CPLD",
-        .ack    = lh7a40x_ack_cpld_irq,
-        .mask   = lh7a40x_mask_cpld_irq,
-        .unmask = lh7a40x_unmask_cpld_irq,
+        .name           = "CPLD",
+        .irq_ack        = lh7a40x_ack_cpld_irq,
+        .irq_mask       = lh7a40x_mask_cpld_irq,
+        .irq_unmask     = lh7a40x_unmask_cpld_irq,
 };
 
 static void lh7a40x_cpld_handler (unsigned int irq, struct irq_desc *desc)
 {
         unsigned int mask = CPLD_INTERRUPTS;
 
-        desc->chip->ack (irq);
+        desc->irq_data.chip->ack (irq);
 
         if ((mask & 0x1) == 0)  /* WLAN */
                 generic_handle_irq(IRQ_LPD7A40X_ETH_INT);
@@ -68,7 +68,7 @@ static void lh7a40x_cpld_handler (unsigned int irq, struct irq_desc *desc)
         if ((mask & 0x2) == 0)  /* Touch */
                 generic_handle_irq(IRQ_LPD7A400_TS);
 
-        desc->chip->unmask (irq); /* Level-triggered need this */
+        desc->irq_data.chip->unmask (irq); /* Level-triggered need this */
 }
 
 
diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c
index bd0df26c415b..316ecbf6c586 100644
--- a/arch/arm/mach-lpc32xx/irq.c
+++ b/arch/arm/mach-lpc32xx/irq.c
@@ -191,38 +191,38 @@ static void get_controller(unsigned int irq, unsigned int *base,
         }
 }
 
-static void lpc32xx_mask_irq(unsigned int irq)
+static void lpc32xx_mask_irq(struct irq_data *d)
 {
         unsigned int reg, ctrl, mask;
 
-        get_controller(irq, &ctrl, &mask);
+        get_controller(d->irq, &ctrl, &mask);
 
         reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) & ~mask;
         __raw_writel(reg, LPC32XX_INTC_MASK(ctrl));
 }
 
-static void lpc32xx_unmask_irq(unsigned int irq)
+static void lpc32xx_unmask_irq(struct irq_data *d)
 {
         unsigned int reg, ctrl, mask;
 
-        get_controller(irq, &ctrl, &mask);
+        get_controller(d->irq, &ctrl, &mask);
 
         reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) | mask;
         __raw_writel(reg, LPC32XX_INTC_MASK(ctrl));
 }
 
-static void lpc32xx_ack_irq(unsigned int irq)
+static void lpc32xx_ack_irq(struct irq_data *d)
 {
         unsigned int ctrl, mask;
 
-        get_controller(irq, &ctrl, &mask);
+        get_controller(d->irq, &ctrl, &mask);
 
         __raw_writel(mask, LPC32XX_INTC_RAW_STAT(ctrl));
 
         /* Also need to clear pending wake event */
-        if (lpc32xx_events[irq].mask != 0)
-                __raw_writel(lpc32xx_events[irq].mask,
-                        lpc32xx_events[irq].event_group->rawstat_reg);
+        if (lpc32xx_events[d->irq].mask != 0)
+                __raw_writel(lpc32xx_events[d->irq].mask,
+                        lpc32xx_events[d->irq].event_group->rawstat_reg);
 }
 
 static void __lpc32xx_set_irq_type(unsigned int irq, int use_high_level,
@@ -261,27 +261,27 @@ static void __lpc32xx_set_irq_type(unsigned int irq, int use_high_level,
         }
 }
 
-static int lpc32xx_set_irq_type(unsigned int irq, unsigned int type)
+static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type)
 {
         switch (type) {
         case IRQ_TYPE_EDGE_RISING:
                 /* Rising edge sensitive */
-                __lpc32xx_set_irq_type(irq, 1, 1);
+                __lpc32xx_set_irq_type(d->irq, 1, 1);
                 break;
 
         case IRQ_TYPE_EDGE_FALLING:
                 /* Falling edge sensitive */
-                __lpc32xx_set_irq_type(irq, 0, 1);
+                __lpc32xx_set_irq_type(d->irq, 0, 1);
                 break;
 
         case IRQ_TYPE_LEVEL_LOW:
                 /* Low level sensitive */
-                __lpc32xx_set_irq_type(irq, 0, 0);
+                __lpc32xx_set_irq_type(d->irq, 0, 0);
                 break;
 
         case IRQ_TYPE_LEVEL_HIGH:
                 /* High level sensitive */
-                __lpc32xx_set_irq_type(irq, 1, 0);
+                __lpc32xx_set_irq_type(d->irq, 1, 0);
                 break;
 
         /* Other modes are not supported */
@@ -290,33 +290,33 @@ static int lpc32xx_set_irq_type(unsigned int irq, unsigned int type)
         }
 
         /* Ok to use the level handler for all types */
-        set_irq_handler(irq, handle_level_irq);
+        set_irq_handler(d->irq, handle_level_irq);
 
         return 0;
 }
 
-static int lpc32xx_irq_wake(unsigned int irqno, unsigned int state)
+static int lpc32xx_irq_wake(struct irq_data *d, unsigned int state)
 {
         unsigned long eventreg;
 
-        if (lpc32xx_events[irqno].mask != 0) {
-                eventreg = __raw_readl(lpc32xx_events[irqno].
+        if (lpc32xx_events[d->irq].mask != 0) {
+                eventreg = __raw_readl(lpc32xx_events[d->irq].
                         event_group->enab_reg);
 
                 if (state)
-                        eventreg |= lpc32xx_events[irqno].mask;
+                        eventreg |= lpc32xx_events[d->irq].mask;
                 else
-                        eventreg &= ~lpc32xx_events[irqno].mask;
+                        eventreg &= ~lpc32xx_events[d->irq].mask;
 
                 __raw_writel(eventreg,
-                        lpc32xx_events[irqno].event_group->enab_reg);
+                        lpc32xx_events[d->irq].event_group->enab_reg);
 
                 return 0;
         }
 
         /* Clear event */
-        __raw_writel(lpc32xx_events[irqno].mask,
-                lpc32xx_events[irqno].event_group->rawstat_reg);
+        __raw_writel(lpc32xx_events[d->irq].mask,
+                lpc32xx_events[d->irq].event_group->rawstat_reg);
 
         return -ENODEV;
 }
@@ -336,11 +336,11 @@ static void __init lpc32xx_set_default_mappings(unsigned int apr,
 }
 
 static struct irq_chip lpc32xx_irq_chip = {
-        .ack = lpc32xx_ack_irq,
-        .mask = lpc32xx_mask_irq,
-        .unmask = lpc32xx_unmask_irq,
-        .set_type = lpc32xx_set_irq_type,
-        .set_wake = lpc32xx_irq_wake
+        .irq_ack = lpc32xx_ack_irq,
+        .irq_mask = lpc32xx_mask_irq,
+        .irq_unmask = lpc32xx_unmask_irq,
+        .irq_set_type = lpc32xx_set_irq_type,
+        .irq_set_wake = lpc32xx_irq_wake
 };
 
 static void lpc32xx_sic1_handler(unsigned int irq, struct irq_desc *desc)
diff --git a/arch/arm/mach-mmp/include/mach/mfp-mmp2.h b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
index 117e30366087..4ad38629c3f6 100644
--- a/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
+++ b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
@@ -6,7 +6,7 @@
 #define MFP_DRIVE_VERY_SLOW     (0x0 << 13)
 #define MFP_DRIVE_SLOW          (0x2 << 13)
 #define MFP_DRIVE_MEDIUM        (0x4 << 13)
-#define MFP_DRIVE_FAST          (0x8 << 13)
+#define MFP_DRIVE_FAST          (0x6 << 13)
 
 /* GPIO */
 #define GPIO0_GPIO      MFP_CFG(GPIO0, AF0)
diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
index 7e8a80f25ddc..fbd7ee8e4897 100644
--- a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
+++ b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
@@ -6,7 +6,7 @@
 #define MFP_DRIVE_VERY_SLOW     (0x0 << 13)
 #define MFP_DRIVE_SLOW          (0x2 << 13)
 #define MFP_DRIVE_MEDIUM        (0x4 << 13)
-#define MFP_DRIVE_FAST          (0x8 << 13)
+#define MFP_DRIVE_FAST          (0x6 << 13)
 
 /* UART2 */
 #define GPIO47_UART2_RXD        MFP_CFG(GPIO47, AF6)
diff --git a/arch/arm/mach-mmp/irq-mmp2.c b/arch/arm/mach-mmp/irq-mmp2.c
index 01342be91c3c..fa037038e7b8 100644
--- a/arch/arm/mach-mmp/irq-mmp2.c
+++ b/arch/arm/mach-mmp/irq-mmp2.c
@@ -20,48 +20,48 @@
 
 #include "common.h"
 
-static void icu_mask_irq(unsigned int irq)
+static void icu_mask_irq(struct irq_data *d)
 {
-        uint32_t r = __raw_readl(ICU_INT_CONF(irq));
+        uint32_t r = __raw_readl(ICU_INT_CONF(d->irq));
 
         r &= ~ICU_INT_ROUTE_PJ4_IRQ;
-        __raw_writel(r, ICU_INT_CONF(irq));
+        __raw_writel(r, ICU_INT_CONF(d->irq));
 }
 
-static void icu_unmask_irq(unsigned int irq)
+static void icu_unmask_irq(struct irq_data *d)
 {
-        uint32_t r = __raw_readl(ICU_INT_CONF(irq));
+        uint32_t r = __raw_readl(ICU_INT_CONF(d->irq));
 
         r |= ICU_INT_ROUTE_PJ4_IRQ;
-        __raw_writel(r, ICU_INT_CONF(irq));
+        __raw_writel(r, ICU_INT_CONF(d->irq));
 }
 
 static struct irq_chip icu_irq_chip = {
         .name           = "icu_irq",
-        .mask           = icu_mask_irq,
-        .mask_ack       = icu_mask_irq,
-        .unmask         = icu_unmask_irq,
+        .irq_mask       = icu_mask_irq,
+        .irq_mask_ack   = icu_mask_irq,
+        .irq_unmask     = icu_unmask_irq,
 };
 
-static void pmic_irq_ack(unsigned int irq)
+static void pmic_irq_ack(struct irq_data *d)
 {
-        if (irq == IRQ_MMP2_PMIC)
+        if (d->irq == IRQ_MMP2_PMIC)
                 mmp2_clear_pmic_int();
 }
 
 #define SECOND_IRQ_MASK(_name_, irq_base, prefix)                       \
-static void _name_##_mask_irq(unsigned int irq)                         \
+static void _name_##_mask_irq(struct irq_data *d)                       \
 {                                                                       \
         uint32_t r;                                                     \
-        r = __raw_readl(prefix##_MASK) | (1 << (irq - irq_base));       \
+        r = __raw_readl(prefix##_MASK) | (1 << (d->irq - irq_base));    \
         __raw_writel(r, prefix##_MASK);                                 \
 }
 
 #define SECOND_IRQ_UNMASK(_name_, irq_base, prefix)                     \
-static void _name_##_unmask_irq(unsigned int irq)                       \
+static void _name_##_unmask_irq(struct irq_data *d)                     \
 {                                                                       \
         uint32_t r;                                                     \
-        r = __raw_readl(prefix##_MASK) & ~(1 << (irq - irq_base));      \
+        r = __raw_readl(prefix##_MASK) & ~(1 << (d->irq - irq_base));   \
         __raw_writel(r, prefix##_MASK);                                 \
 }
 
@@ -88,8 +88,8 @@ SECOND_IRQ_UNMASK(_name_, irq_base, prefix)				\
 SECOND_IRQ_DEMUX(_name_, irq_base, prefix)                              \
 static struct irq_chip _name_##_irq_chip = {                            \
         .name           = #_name_,                                      \
-        .mask           = _name_##_mask_irq,                            \
-        .unmask         = _name_##_unmask_irq,                          \
+        .irq_mask       = _name_##_mask_irq,                            \
+        .irq_unmask     = _name_##_unmask_irq,                          \
 }
 
 SECOND_IRQ_CHIP(pmic, IRQ_MMP2_PMIC_BASE, MMP2_ICU_INT4);
@@ -103,10 +103,12 @@ static void init_mux_irq(struct irq_chip *chip, int start, int num)
         int irq;
 
         for (irq = start; num > 0; irq++, num--) {
+                struct irq_data *d = irq_get_irq_data(irq);
+
                 /* mask and clear the IRQ */
-                chip->mask(irq);
-                if (chip->ack)
-                        chip->ack(irq);
+                chip->irq_mask(d);
+                if (chip->irq_ack)
+                        chip->irq_ack(d);
 
                 set_irq_chip(irq, chip);
                 set_irq_flags(irq, IRQF_VALID);
@@ -119,7 +121,7 @@ void __init mmp2_init_icu(void)
         int irq;
 
         for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) {
-                icu_mask_irq(irq);
+                icu_mask_irq(irq_get_irq_data(irq));
                 set_irq_chip(irq, &icu_irq_chip);
                 set_irq_flags(irq, IRQF_VALID);
 
@@ -139,7 +141,7 @@ void __init mmp2_init_icu(void)
         /* NOTE: IRQ_MMP2_PMIC requires the PMIC MFPR register
          * to be written to clear the interrupt
          */
-        pmic_irq_chip.ack = pmic_irq_ack;
+        pmic_irq_chip.irq_ack = pmic_irq_ack;
 
         init_mux_irq(&pmic_irq_chip, IRQ_MMP2_PMIC_BASE, 2);
         init_mux_irq(&rtc_irq_chip, IRQ_MMP2_RTC_BASE, 2);
diff --git a/arch/arm/mach-mmp/irq-pxa168.c b/arch/arm/mach-mmp/irq-pxa168.c
index 52ff2f065eba..f86b450cb93c 100644
--- a/arch/arm/mach-mmp/irq-pxa168.c
+++ b/arch/arm/mach-mmp/irq-pxa168.c
@@ -25,21 +25,21 @@
 #define PRIORITY_DEFAULT        0x1
 #define PRIORITY_NONE           0x0     /* means IRQ disabled */
 
-static void icu_mask_irq(unsigned int irq)
+static void icu_mask_irq(struct irq_data *d)
 {
-        __raw_writel(PRIORITY_NONE, ICU_INT_CONF(irq));
+        __raw_writel(PRIORITY_NONE, ICU_INT_CONF(d->irq));
 }
 
-static void icu_unmask_irq(unsigned int irq)
+static void icu_unmask_irq(struct irq_data *d)
 {
-        __raw_writel(IRQ_ROUTE_TO_AP | PRIORITY_DEFAULT, ICU_INT_CONF(irq));
+        __raw_writel(IRQ_ROUTE_TO_AP | PRIORITY_DEFAULT, ICU_INT_CONF(d->irq));
 }
 
 static struct irq_chip icu_irq_chip = {
-        .name   = "icu_irq",
-        .ack    = icu_mask_irq,
-        .mask   = icu_mask_irq,
-        .unmask = icu_unmask_irq,
+        .name           = "icu_irq",
+        .irq_ack        = icu_mask_irq,
+        .irq_mask       = icu_mask_irq,
+        .irq_unmask     = icu_unmask_irq,
 };
 
 void __init icu_init_irq(void)
@@ -47,7 +47,7 @@ void __init icu_init_irq(void)
         int irq;
 
         for (irq = 0; irq < 64; irq++) {
-                icu_mask_irq(irq);
+                icu_mask_irq(irq_get_irq_data(irq));
                 set_irq_chip(irq, &icu_irq_chip);
                 set_irq_handler(irq, handle_level_irq);
                 set_irq_flags(irq, IRQF_VALID);
diff --git a/arch/arm/mach-msm/board-trout-gpio.c b/arch/arm/mach-msm/board-trout-gpio.c
index f8c09ef6666f..a604ec1e44bf 100644
--- a/arch/arm/mach-msm/board-trout-gpio.c
+++ b/arch/arm/mach-msm/board-trout-gpio.c
@@ -113,52 +113,52 @@ static struct msm_gpio_chip msm_gpio_banks[] = {
         TROUT_GPIO_BANK("VIRTUAL", 0x12, TROUT_GPIO_VIRTUAL_BASE, 0),
 };
 
-static void trout_gpio_irq_ack(unsigned int irq)
+static void trout_gpio_irq_ack(struct irq_data *d)
 {
-        int bank = TROUT_INT_TO_BANK(irq);
-        uint8_t mask = TROUT_INT_TO_MASK(irq);
+        int bank = TROUT_INT_TO_BANK(d->irq);
+        uint8_t mask = TROUT_INT_TO_MASK(d->irq);
         int reg = TROUT_BANK_TO_STAT_REG(bank);
-        /*printk(KERN_INFO "trout_gpio_irq_ack irq %d\n", irq);*/
+        /*printk(KERN_INFO "trout_gpio_irq_ack irq %d\n", d->irq);*/
         writeb(mask, TROUT_CPLD_BASE + reg);
 }
 
-static void trout_gpio_irq_mask(unsigned int irq)
+static void trout_gpio_irq_mask(struct irq_data *d)
 {
         unsigned long flags;
         uint8_t reg_val;
-        int bank = TROUT_INT_TO_BANK(irq);
-        uint8_t mask = TROUT_INT_TO_MASK(irq);
+        int bank = TROUT_INT_TO_BANK(d->irq);
+        uint8_t mask = TROUT_INT_TO_MASK(d->irq);
         int reg = TROUT_BANK_TO_MASK_REG(bank);
 
         local_irq_save(flags);
         reg_val = trout_int_mask[bank] |= mask;
         /*printk(KERN_INFO "trout_gpio_irq_mask irq %d => %d:%02x\n",
-               irq, bank, reg_val);*/
+               d->irq, bank, reg_val);*/
         writeb(reg_val, TROUT_CPLD_BASE + reg);
         local_irq_restore(flags);
 }
 
-static void trout_gpio_irq_unmask(unsigned int irq)
+static void trout_gpio_irq_unmask(struct irq_data *d)
 {
         unsigned long flags;
         uint8_t reg_val;
-        int bank = TROUT_INT_TO_BANK(irq);
-        uint8_t mask = TROUT_INT_TO_MASK(irq);
+        int bank = TROUT_INT_TO_BANK(d->irq);
+        uint8_t mask = TROUT_INT_TO_MASK(d->irq);
         int reg = TROUT_BANK_TO_MASK_REG(bank);
 
         local_irq_save(flags);
         reg_val = trout_int_mask[bank] &= ~mask;
         /*printk(KERN_INFO "trout_gpio_irq_unmask irq %d => %d:%02x\n",
-               irq, bank, reg_val);*/
+               d->irq, bank, reg_val);*/
         writeb(reg_val, TROUT_CPLD_BASE + reg);
         local_irq_restore(flags);
 }
 
-int trout_gpio_irq_set_wake(unsigned int irq, unsigned int on)
+int trout_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
 {
         unsigned long flags;
-        int bank = TROUT_INT_TO_BANK(irq);
-        uint8_t mask = TROUT_INT_TO_MASK(irq);
+        int bank = TROUT_INT_TO_BANK(d->irq);
+        uint8_t mask = TROUT_INT_TO_MASK(d->irq);
 
         local_irq_save(flags);
         if(on)
@@ -198,15 +198,15 @@ static void trout_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
                 }
                 int_base += TROUT_INT_BANK0_COUNT;
         }
-        desc->chip->ack(irq);
+        desc->irq_data.chip->irq_ack(&desc->irq_data);
 }
 
 static struct irq_chip trout_gpio_irq_chip = {
-        .name      = "troutgpio",
-        .ack       = trout_gpio_irq_ack,
-        .mask      = trout_gpio_irq_mask,
-        .unmask    = trout_gpio_irq_unmask,
-        .set_wake  = trout_gpio_irq_set_wake,
+        .name          = "troutgpio",
+        .irq_ack       = trout_gpio_irq_ack,
+        .irq_mask      = trout_gpio_irq_mask,
+        .irq_unmask    = trout_gpio_irq_unmask,
+        .irq_set_wake  = trout_gpio_irq_set_wake,
 };
 
 /*
diff --git a/arch/arm/mach-msm/gpio.c b/arch/arm/mach-msm/gpio.c
index 33051b509e88..176af9dcb8ee 100644
--- a/arch/arm/mach-msm/gpio.c
+++ b/arch/arm/mach-msm/gpio.c
@@ -225,21 +225,21 @@ struct msm_gpio_chip msm_gpio_chips[] = {
 #endif
 };
 
-static void msm_gpio_irq_ack(unsigned int irq)
+static void msm_gpio_irq_ack(struct irq_data *d)
 {
         unsigned long irq_flags;
-        struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
+        struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
         spin_lock_irqsave(&msm_chip->lock, irq_flags);
         msm_gpio_clear_detect_status(msm_chip,
-                                     irq - gpio_to_irq(msm_chip->chip.base));
+                                     d->irq - gpio_to_irq(msm_chip->chip.base));
         spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
 }
 
-static void msm_gpio_irq_mask(unsigned int irq)
+static void msm_gpio_irq_mask(struct irq_data *d)
 {
         unsigned long irq_flags;
-        struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
-        unsigned offset = irq - gpio_to_irq(msm_chip->chip.base);
+        struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
+        unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
 
         spin_lock_irqsave(&msm_chip->lock, irq_flags);
         /* level triggered interrupts are also latched */
@@ -250,11 +250,11 @@ static void msm_gpio_irq_mask(unsigned int irq)
         spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
 }
 
-static void msm_gpio_irq_unmask(unsigned int irq)
+static void msm_gpio_irq_unmask(struct irq_data *d)
 {
         unsigned long irq_flags;
-        struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
-        unsigned offset = irq - gpio_to_irq(msm_chip->chip.base);
+        struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
+        unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
 
         spin_lock_irqsave(&msm_chip->lock, irq_flags);
         /* level triggered interrupts are also latched */
@@ -265,11 +265,11 @@ static void msm_gpio_irq_unmask(unsigned int irq)
         spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
 }
 
-static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on)
+static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
 {
         unsigned long irq_flags;
-        struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
-        unsigned offset = irq - gpio_to_irq(msm_chip->chip.base);
+        struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
+        unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
 
         spin_lock_irqsave(&msm_chip->lock, irq_flags);
 
@@ -282,21 +282,21 @@ static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on)
         return 0;
 }
 
-static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
+static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
 {
         unsigned long irq_flags;
-        struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
-        unsigned offset = irq - gpio_to_irq(msm_chip->chip.base);
+        struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
+        unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
         unsigned val, mask = BIT(offset);
 
         spin_lock_irqsave(&msm_chip->lock, irq_flags);
         val = readl(msm_chip->regs.int_edge);
         if (flow_type & IRQ_TYPE_EDGE_BOTH) {
                 writel(val | mask, msm_chip->regs.int_edge);
-                irq_desc[irq].handle_irq = handle_edge_irq;
+                irq_desc[d->irq].handle_irq = handle_edge_irq;
         } else {
                 writel(val & ~mask, msm_chip->regs.int_edge);
-                irq_desc[irq].handle_irq = handle_level_irq;
+                irq_desc[d->irq].handle_irq = handle_level_irq;
         }
         if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
                 msm_chip->both_edge_detect |= mask;
@@ -333,16 +333,16 @@ static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
                                            msm_chip->chip.base + j);
                 }
         }
-        desc->chip->ack(irq);
+        desc->irq_data.chip->irq_ack(&desc->irq_data);
 }
 
 static struct irq_chip msm_gpio_irq_chip = {
-        .name      = "msmgpio",
-        .ack       = msm_gpio_irq_ack,
-        .mask      = msm_gpio_irq_mask,
-        .unmask    = msm_gpio_irq_unmask,
-        .set_wake  = msm_gpio_irq_set_wake,
-        .set_type  = msm_gpio_irq_set_type,
+        .name          = "msmgpio",
+        .irq_ack       = msm_gpio_irq_ack,
+        .irq_mask      = msm_gpio_irq_mask,
+        .irq_unmask    = msm_gpio_irq_unmask,
+        .irq_set_wake  = msm_gpio_irq_set_wake,
+        .irq_set_type  = msm_gpio_irq_set_type,
 };
 
 static int __init msm_init_gpio(void)
diff --git a/arch/arm/mach-msm/irq-vic.c b/arch/arm/mach-msm/irq-vic.c
index 99f2c3473033..68c28bbdc969 100644
--- a/arch/arm/mach-msm/irq-vic.c
+++ b/arch/arm/mach-msm/irq-vic.c
@@ -226,19 +226,18 @@ static inline void msm_irq_write_all_regs(void __iomem *base, unsigned int val)
                 writel(val, base + (i * 4));
 }
 
-static void msm_irq_ack(unsigned int irq)
+static void msm_irq_ack(struct irq_data *d)
 {
-        void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_CLEAR0, irq);
-        irq = 1 << (irq & 31);
-        writel(irq, reg);
+        void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_CLEAR0, d->irq);
+        writel(1 << (d->irq & 31), reg);
 }
 
-static void msm_irq_mask(unsigned int irq)
+static void msm_irq_mask(struct irq_data *d)
 {
-        void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_ENCLEAR0, irq);
-        unsigned index = VIC_INT_TO_REG_INDEX(irq);
-        uint32_t mask = 1UL << (irq & 31);
-        int smsm_irq = msm_irq_to_smsm[irq];
+        void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_ENCLEAR0, d->irq);
+        unsigned index = VIC_INT_TO_REG_INDEX(d->irq);
+        uint32_t mask = 1UL << (d->irq & 31);
+        int smsm_irq = msm_irq_to_smsm[d->irq];
 
         msm_irq_shadow_reg[index].int_en[0] &= ~mask;
         writel(mask, reg);
@@ -250,12 +249,12 @@ static void msm_irq_mask(unsigned int irq)
         }
 }
 
-static void msm_irq_unmask(unsigned int irq)
+static void msm_irq_unmask(struct irq_data *d)
 {
-        void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_ENSET0, irq);
-        unsigned index = VIC_INT_TO_REG_INDEX(irq);
-        uint32_t mask = 1UL << (irq & 31);
-        int smsm_irq = msm_irq_to_smsm[irq];
+        void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_ENSET0, d->irq);
+        unsigned index = VIC_INT_TO_REG_INDEX(d->irq);
+        uint32_t mask = 1UL << (d->irq & 31);
+        int smsm_irq = msm_irq_to_smsm[d->irq];
 
         msm_irq_shadow_reg[index].int_en[0] |= mask;
         writel(mask, reg);
@@ -268,14 +267,14 @@ static void msm_irq_unmask(unsigned int irq)
         }
 }
 
-static int msm_irq_set_wake(unsigned int irq, unsigned int on)
+static int msm_irq_set_wake(struct irq_data *d, unsigned int on)
 {
-        unsigned index = VIC_INT_TO_REG_INDEX(irq);
-        uint32_t mask = 1UL << (irq & 31);
-        int smsm_irq = msm_irq_to_smsm[irq];
+        unsigned index = VIC_INT_TO_REG_INDEX(d->irq);
+        uint32_t mask = 1UL << (d->irq & 31);
+        int smsm_irq = msm_irq_to_smsm[d->irq];
 
         if (smsm_irq == 0) {
-                printk(KERN_ERR "msm_irq_set_wake: bad wakeup irq %d\n", irq);
+                printk(KERN_ERR "msm_irq_set_wake: bad wakeup irq %d\n", d->irq);
                 return -EINVAL;
         }
         if (on)
@@ -294,12 +293,12 @@ static int msm_irq_set_wake(unsigned int irq, unsigned int on)
         return 0;
 }
 
-static int msm_irq_set_type(unsigned int irq, unsigned int flow_type)
+static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type)
 {
-        void __iomem *treg = VIC_INT_TO_REG_ADDR(VIC_INT_TYPE0, irq);
-        void __iomem *preg = VIC_INT_TO_REG_ADDR(VIC_INT_POLARITY0, irq);
-        unsigned index = VIC_INT_TO_REG_INDEX(irq);
-        int b = 1 << (irq & 31);
+        void __iomem *treg = VIC_INT_TO_REG_ADDR(VIC_INT_TYPE0, d->irq);
+        void __iomem *preg = VIC_INT_TO_REG_ADDR(VIC_INT_POLARITY0, d->irq);
+        unsigned index = VIC_INT_TO_REG_INDEX(d->irq);
+        int b = 1 << (d->irq & 31);
         uint32_t polarity;
         uint32_t type;
 
@@ -314,11 +313,11 @@ static int msm_irq_set_type(unsigned int irq, unsigned int flow_type)
         type = msm_irq_shadow_reg[index].int_type;
         if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
                 type |= b;
-                irq_desc[irq].handle_irq = handle_edge_irq;
+                irq_desc[d->irq].handle_irq = handle_edge_irq;
         }
         if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) {
                 type &= ~b;
-                irq_desc[irq].handle_irq = handle_level_irq;
+                irq_desc[d->irq].handle_irq = handle_level_irq;
         }
         writel(type, treg);
         msm_irq_shadow_reg[index].int_type = type;
@@ -326,13 +325,13 @@ static int msm_irq_set_type(unsigned int irq, unsigned int flow_type)
 }
 
 static struct irq_chip msm_irq_chip = {
-        .name      = "msm",
-        .disable   = msm_irq_mask,
-        .ack       = msm_irq_ack,
-        .mask      = msm_irq_mask,
-        .unmask    = msm_irq_unmask,
-        .set_wake  = msm_irq_set_wake,
-        .set_type  = msm_irq_set_type,
+        .name          = "msm",
+        .irq_disable   = msm_irq_mask,
+        .irq_ack       = msm_irq_ack,
+        .irq_mask      = msm_irq_mask,
+        .irq_unmask    = msm_irq_unmask,
+        .irq_set_wake  = msm_irq_set_wake,
+        .irq_set_type  = msm_irq_set_type,
 };
 
 void __init msm_init_irq(void)
diff --git a/arch/arm/mach-msm/irq.c b/arch/arm/mach-msm/irq.c
index 6c8d5f8caef3..0b27d899f40e 100644
--- a/arch/arm/mach-msm/irq.c
+++ b/arch/arm/mach-msm/irq.c
@@ -64,35 +64,34 @@
 #define VIC_VECTPRIORITY(n) VIC_REG(0x0200+((n) * 4))
 #define VIC_VECTADDR(n)     VIC_REG(0x0400+((n) * 4))
 
-static void msm_irq_ack(unsigned int irq)
+static void msm_irq_ack(struct irq_data *d)
 {
-        void __iomem *reg = VIC_INT_CLEAR0 + ((irq & 32) ? 4 : 0);
-        irq = 1 << (irq & 31);
-        writel(irq, reg);
+        void __iomem *reg = VIC_INT_CLEAR0 + ((d->irq & 32) ? 4 : 0);
+        writel(1 << (d->irq & 31), reg);
 }
 
-static void msm_irq_mask(unsigned int irq)
+static void msm_irq_mask(struct irq_data *d)
 {
-        void __iomem *reg = VIC_INT_ENCLEAR0 + ((irq & 32) ? 4 : 0);
-        writel(1 << (irq & 31), reg);
+        void __iomem *reg = VIC_INT_ENCLEAR0 + ((d->irq & 32) ? 4 : 0);
+        writel(1 << (d->irq & 31), reg);
 }
 
-static void msm_irq_unmask(unsigned int irq)
+static void msm_irq_unmask(struct irq_data *d)
 {
-        void __iomem *reg = VIC_INT_ENSET0 + ((irq & 32) ? 4 : 0);
-        writel(1 << (irq & 31), reg);
+        void __iomem *reg = VIC_INT_ENSET0 + ((d->irq & 32) ? 4 : 0);
+        writel(1 << (d->irq & 31), reg);
 }
 
-static int msm_irq_set_wake(unsigned int irq, unsigned int on)
+static int msm_irq_set_wake(struct irq_data *d, unsigned int on)
 {
         return -EINVAL;
 }
 
-static int msm_irq_set_type(unsigned int irq, unsigned int flow_type)
+static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type)
 {
-        void __iomem *treg = VIC_INT_TYPE0 + ((irq & 32) ? 4 : 0);
-        void __iomem *preg = VIC_INT_POLARITY0 + ((irq & 32) ? 4 : 0);
-        int b = 1 << (irq & 31);
+        void __iomem *treg = VIC_INT_TYPE0 + ((d->irq & 32) ? 4 : 0);
+        void __iomem *preg = VIC_INT_POLARITY0 + ((d->irq & 32) ? 4 : 0);
+        int b = 1 << (d->irq & 31);
 
         if (flow_type & (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_LOW))
                 writel(readl(preg) | b, preg);
@@ -101,22 +100,22 @@ static int msm_irq_set_type(unsigned int irq, unsigned int flow_type)
 
         if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
                 writel(readl(treg) | b, treg);
-                irq_desc[irq].handle_irq = handle_edge_irq;
+                irq_desc[d->irq].handle_irq = handle_edge_irq;
         }
         if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) {
                 writel(readl(treg) & (~b), treg);
-                irq_desc[irq].handle_irq = handle_level_irq;
+                irq_desc[d->irq].handle_irq = handle_level_irq;
         }
         return 0;
 }
 
 static struct irq_chip msm_irq_chip = {
-        .name      = "msm",
-        .ack       = msm_irq_ack,
-        .mask      = msm_irq_mask,
-        .unmask    = msm_irq_unmask,
-        .set_wake  = msm_irq_set_wake,
-        .set_type  = msm_irq_set_type,
+        .name          = "msm",
+        .irq_ack       = msm_irq_ack,
+        .irq_mask      = msm_irq_mask,
+        .irq_unmask    = msm_irq_unmask,
+        .irq_set_wake  = msm_irq_set_wake,
+        .irq_set_type  = msm_irq_set_type,
 };
 
 void __init msm_init_irq(void)
diff --git a/arch/arm/mach-msm/sirc.c b/arch/arm/mach-msm/sirc.c
index 152eefda3ce6..11b54c7aeb09 100644
--- a/arch/arm/mach-msm/sirc.c
+++ b/arch/arm/mach-msm/sirc.c
@@ -42,12 +42,11 @@ static struct sirc_cascade_regs sirc_reg_table[] = {
 
 /* Mask off the given interrupt. Keep the int_enable mask in sync with
    the enable reg, so it can be restored after power collapse. */
-static void sirc_irq_mask(unsigned int irq)
+static void sirc_irq_mask(struct irq_data *d)
 {
         unsigned int mask;
 
-
-        mask = 1 << (irq - FIRST_SIRC_IRQ);
+        mask = 1 << (d->irq - FIRST_SIRC_IRQ);
         writel(mask, sirc_regs.int_enable_clear);
         int_enable &= ~mask;
         return;
@@ -55,31 +54,31 @@ static void sirc_irq_mask(unsigned int irq)
 
 /* Unmask the given interrupt. Keep the int_enable mask in sync with
    the enable reg, so it can be restored after power collapse. */
-static void sirc_irq_unmask(unsigned int irq)
+static void sirc_irq_unmask(struct irq_data *d)
 {
         unsigned int mask;
 
-        mask = 1 << (irq - FIRST_SIRC_IRQ);
+        mask = 1 << (d->irq - FIRST_SIRC_IRQ);
         writel(mask, sirc_regs.int_enable_set);
         int_enable |= mask;
         return;
 }
 
-static void sirc_irq_ack(unsigned int irq)
+static void sirc_irq_ack(struct irq_data *d)
 {
         unsigned int mask;
 
-        mask = 1 << (irq - FIRST_SIRC_IRQ);
+        mask = 1 << (d->irq - FIRST_SIRC_IRQ);
         writel(mask, sirc_regs.int_clear);
         return;
 }
 
-static int sirc_irq_set_wake(unsigned int irq, unsigned int on)
+static int sirc_irq_set_wake(struct irq_data *d, unsigned int on)
 {
         unsigned int mask;
 
         /* Used to set the interrupt enable mask during power collapse. */
-        mask = 1 << (irq - FIRST_SIRC_IRQ);
+        mask = 1 << (d->irq - FIRST_SIRC_IRQ);
         if (on)
                 wake_enable |= mask;
         else
@@ -88,12 +87,12 @@ static int sirc_irq_set_wake(unsigned int irq, unsigned int on)
         return 0;
 }
 
-static int sirc_irq_set_type(unsigned int irq, unsigned int flow_type)
+static int sirc_irq_set_type(struct irq_data *d, unsigned int flow_type)
 {
         unsigned int mask;
         unsigned int val;
 
-        mask = 1 << (irq - FIRST_SIRC_IRQ);
+        mask = 1 << (d->irq - FIRST_SIRC_IRQ);
         val = readl(sirc_regs.int_polarity);
 
         if (flow_type & (IRQF_TRIGGER_LOW | IRQF_TRIGGER_FALLING))
@@ -106,10 +105,10 @@ static int sirc_irq_set_type(unsigned int irq, unsigned int flow_type)
         val = readl(sirc_regs.int_type);
         if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
                 val |= mask;
-                irq_desc[irq].handle_irq = handle_edge_irq;
+                irq_desc[d->irq].handle_irq = handle_edge_irq;
         } else {
                 val &= ~mask;
-                irq_desc[irq].handle_irq = handle_level_irq;
+                irq_desc[d->irq].handle_irq = handle_level_irq;
         }
 
         writel(val, sirc_regs.int_type);
@@ -139,16 +138,16 @@ static void sirc_irq_handler(unsigned int irq, struct irq_desc *desc)
                 ;
         generic_handle_irq(sirq+FIRST_SIRC_IRQ);
 
-        desc->chip->ack(irq);
+        desc->irq_data.chip->irq_ack(&desc->irq_data);
 }
 
 static struct irq_chip sirc_irq_chip = {
-        .name      = "sirc",
-        .ack       = sirc_irq_ack,
-        .mask      = sirc_irq_mask,
-        .unmask    = sirc_irq_unmask,
-        .set_wake  = sirc_irq_set_wake,
-        .set_type  = sirc_irq_set_type,
+        .name          = "sirc",
+        .irq_ack       = sirc_irq_ack,
+        .irq_mask      = sirc_irq_mask,
+        .irq_unmask    = sirc_irq_unmask,
+        .irq_set_wake  = sirc_irq_set_wake,
+        .irq_set_type  = sirc_irq_set_type,
 };
 
 void __init msm_init_sirc(void)
diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
index 899a969e92fa..0d65db885be7 100644
--- a/arch/arm/mach-mx3/mach-mx31_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx31_3ds.c
@@ -147,10 +147,10 @@ static struct mc13783_regulator_init_data mx31_3ds_regulators[] = {
                 .init_data = &pwgtx_init,
         }, {
 
-                .id = MC13783_REGU_GPO1, /* Turn on 1.8V */
+                .id = MC13783_REG_GPO1, /* Turn on 1.8V */
                 .init_data = &gpo_init,
         }, {
-                .id = MC13783_REGU_GPO3, /* Turn on 3.3V */
+                .id = MC13783_REG_GPO3, /* Turn on 3.3V */
                 .init_data = &gpo_init,
         },
 };
diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c
index b993b9bf6179..88b97d62b57e 100644
--- a/arch/arm/mach-mx3/mach-mx31ads.c
+++ b/arch/arm/mach-mx3/mach-mx31ads.c
@@ -162,9 +162,9 @@ static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
  * Disable an expio pin's interrupt by setting the bit in the imr.
  * @param irq           an expio virtual irq number
  */
-static void expio_mask_irq(u32 irq)
+static void expio_mask_irq(struct irq_data *d)
 {
-        u32 expio = MXC_IRQ_TO_EXPIO(irq);
+        u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
         /* mask the interrupt */
         __raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
         __raw_readw(PBC_INTMASK_CLEAR_REG);
@@ -174,9 +174,9 @@ static void expio_mask_irq(u32 irq)
  * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
  * @param irq           an expanded io virtual irq number
  */
-static void expio_ack_irq(u32 irq)
+static void expio_ack_irq(struct irq_data *d)
 {
-        u32 expio = MXC_IRQ_TO_EXPIO(irq);
+        u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
         /* clear the interrupt status */
         __raw_writew(1 << expio, PBC_INTSTATUS_REG);
 }
@@ -185,18 +185,18 @@ static void expio_ack_irq(u32 irq)
  * Enable a expio pin's interrupt by clearing the bit in the imr.
  * @param irq           a expio virtual irq number
  */
-static void expio_unmask_irq(u32 irq)
+static void expio_unmask_irq(struct irq_data *d)
 {
-        u32 expio = MXC_IRQ_TO_EXPIO(irq);
+        u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
         /* unmask the interrupt */
         __raw_writew(1 << expio, PBC_INTMASK_SET_REG);
 }
 
 static struct irq_chip expio_irq_chip = {
         .name = "EXPIO(CPLD)",
-        .ack = expio_ack_irq,
-        .mask = expio_mask_irq,
-        .unmask = expio_unmask_irq,
+        .irq_ack = expio_ack_irq,
+        .irq_mask = expio_mask_irq,
+        .irq_unmask = expio_unmask_irq,
 };
 
 static void __init mx31ads_init_expio(void)
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index 55254b6e9460..de4fa992fc3e 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -50,6 +50,7 @@ config MACH_MX51_BABBAGE
 config MACH_MX51_3DS
         bool "Support MX51PDK (3DS)"
         select SOC_IMX51
+        select IMX_HAVE_PLATFORM_IMX_KEYPAD
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
         select IMX_HAVE_PLATFORM_SPI_IMX
@@ -77,6 +78,7 @@ choice
 config MACH_EUKREA_MBIMX51_BASEBOARD
         prompt "Eukrea MBIMX51 development board"
         bool
+        select IMX_HAVE_PLATFORM_IMX_KEYPAD
         select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
         help
           This adds board specific devices that can be found on Eukrea's
@@ -124,10 +126,28 @@ config MACH_MX53_EVK
         bool "Support MX53 EVK platforms"
         select SOC_IMX53
         select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+        select IMX_HAVE_PLATFORM_SPI_IMX
         help
           Include support for MX53 EVK platform. This includes specific
           configurations for the board and its peripherals.
 
+config MACH_MX53_SMD
+        bool "Support MX53 SMD platforms"
+        select SOC_IMX53
+        select IMX_HAVE_PLATFORM_IMX_UART
+        help
+          Include support for MX53 SMD platform. This includes specific
+          configurations for the board and its peripherals.
+
+config MACH_MX53_LOCO
+        bool "Support MX53 LOCO platforms"
+        select SOC_IMX53
+        select IMX_HAVE_PLATFORM_IMX_UART
+        help
+          Include support for MX53 LOCO platform. This includes specific
+          configurations for the board and its peripherals.
 
 config MACH_MX50_RDP
         bool "Support MX50 reference design platform"
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index 0c398baf11fe..0d43be98e51c 100644
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -10,6 +10,8 @@ obj-$(CONFIG_CPU_FREQ_IMX)    += cpu_op-mx51.o
 obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
 obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
 obj-$(CONFIG_MACH_MX53_EVK) += board-mx53_evk.o
+obj-$(CONFIG_MACH_MX53_SMD) += board-mx53_smd.o
+obj-$(CONFIG_MACH_MX53_LOCO) += board-mx53_loco.o
 obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o
 obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o
 obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += board-cpuimx51sd.o
diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
index e42bd2eb034e..49d644842379 100644
--- a/arch/arm/mach-mx5/board-mx51_3ds.c
+++ b/arch/arm/mach-mx5/board-mx51_3ds.c
@@ -12,7 +12,6 @@
 
 #include <linux/irq.h>
 #include <linux/platform_device.h>
-#include <linux/input/matrix_keypad.h>
 #include <linux/spi/spi.h>
 
 #include <asm/mach-types.h>
@@ -120,14 +119,14 @@ static int mx51_3ds_board_keymap[] = {
         KEY(3, 5, KEY_BACK)
 };
 
-static struct matrix_keymap_data mx51_3ds_map_data = {
+static const struct matrix_keymap_data mx51_3ds_map_data __initconst = {
         .keymap         = mx51_3ds_board_keymap,
         .keymap_size    = ARRAY_SIZE(mx51_3ds_board_keymap),
 };
 
 static void mxc_init_keypad(void)
 {
-        mxc_register_device(&mxc_keypad_device, &mx51_3ds_map_data);
+        imx51_add_imx_keypad(&mx51_3ds_map_data);
 }
 #else
 static inline void mxc_init_keypad(void)
diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c
index fa97d0d5dd05..caee04c08238 100644
--- a/arch/arm/mach-mx5/board-mx53_evk.c
+++ b/arch/arm/mach-mx5/board-mx53_evk.c
@@ -21,6 +21,11 @@
 
 #include <linux/init.h>
 #include <linux/clk.h>
+#include <linux/fec.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -29,6 +34,10 @@
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx53.h>
 
+#define SMD_FEC_PHY_RST         IMX_GPIO_NR(7, 6)
+#define EVK_ECSPI1_CS0          IMX_GPIO_NR(2, 30)
+#define EVK_ECSPI1_CS1          IMX_GPIO_NR(3, 19)
+
 #include "crm_regs.h"
 #include "devices-imx53.h"
 
@@ -47,6 +56,14 @@ static iomux_v3_cfg_t mx53_evk_pads[] = {
         MX53_PAD_ATA_CS_1__UART3_RXD,
         MX53_PAD_ATA_DA_1__UART3_CTS,
         MX53_PAD_ATA_DA_2__UART3_RTS,
+
+        MX53_PAD_EIM_D16__CSPI1_SCLK,
+        MX53_PAD_EIM_D17__CSPI1_MISO,
+        MX53_PAD_EIM_D18__CSPI1_MOSI,
+
+        /* ecspi chip select lines */
+        MX53_PAD_EIM_EB2__GPIO_2_30,
+        MX53_PAD_EIM_D19__GPIO_3_19,
 };
 
 static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = {
@@ -60,11 +77,68 @@ static inline void mx53_evk_init_uart(void)
         imx53_add_imx_uart(2, &mx53_evk_uart_pdata);
 }
 
+static const struct imxi2c_platform_data mx53_evk_i2c_data __initconst = {
+        .bitrate = 100000,
+};
+
+static inline void mx53_evk_fec_reset(void)
+{
+        int ret;
+
+        /* reset FEC PHY */
+        ret = gpio_request(SMD_FEC_PHY_RST, "fec-phy-reset");
+        if (ret) {
+                printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
+                return;
+        }
+        gpio_direction_output(SMD_FEC_PHY_RST, 0);
+        gpio_set_value(SMD_FEC_PHY_RST, 0);
+        msleep(1);
+        gpio_set_value(SMD_FEC_PHY_RST, 1);
+}
+
+static struct fec_platform_data mx53_evk_fec_pdata = {
+        .phy = PHY_INTERFACE_MODE_RMII,
+};
+
+static struct spi_board_info mx53_evk_spi_board_info[] __initdata = {
+        {
+                .modalias = "mtd_dataflash",
+                .max_speed_hz = 25000000,
+                .bus_num = 0,
+                .chip_select = 1,
+                .mode = SPI_MODE_0,
+                .platform_data = NULL,
+        },
+};
+
+static int mx53_evk_spi_cs[] = {
+        EVK_ECSPI1_CS0,
+        EVK_ECSPI1_CS1,
+};
+
+static const struct spi_imx_master mx53_evk_spi_data __initconst = {
+        .chipselect     = mx53_evk_spi_cs,
+        .num_chipselect = ARRAY_SIZE(mx53_evk_spi_cs),
+};
+
 static void __init mx53_evk_board_init(void)
 {
         mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads,
                                         ARRAY_SIZE(mx53_evk_pads));
         mx53_evk_init_uart();
+        mx53_evk_fec_reset();
+        imx53_add_fec(&mx53_evk_fec_pdata);
+
+        imx53_add_imx_i2c(0, &mx53_evk_i2c_data);
+        imx53_add_imx_i2c(1, &mx53_evk_i2c_data);
+
+        imx53_add_sdhci_esdhc_imx(0, NULL);
+        imx53_add_sdhci_esdhc_imx(1, NULL);
+
+        spi_register_board_info(mx53_evk_spi_board_info,
+                ARRAY_SIZE(mx53_evk_spi_board_info));
+        imx53_add_ecspi(0, &mx53_evk_spi_data);
 }
 
 static void __init mx53_evk_timer_init(void)
diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c
new file mode 100644
index 000000000000..d1348e04ace3
--- /dev/null
+++ b/arch/arm/mach-mx5/board-mx53_loco.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/fec.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux-mx53.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include "crm_regs.h"
+#include "devices-imx53.h"
+
+#define LOCO_FEC_PHY_RST                IMX_GPIO_NR(7, 6)
+
+static iomux_v3_cfg_t mx53_loco_pads[] = {
+        MX53_PAD_CSI0_D10__UART1_TXD,
+        MX53_PAD_CSI0_D11__UART1_RXD,
+        MX53_PAD_ATA_DIOW__UART1_TXD,
+        MX53_PAD_ATA_DMACK__UART1_RXD,
+
+        MX53_PAD_ATA_BUFFER_EN__UART2_RXD,
+        MX53_PAD_ATA_DMARQ__UART2_TXD,
+        MX53_PAD_ATA_DIOR__UART2_RTS,
+        MX53_PAD_ATA_INTRQ__UART2_CTS,
+
+        MX53_PAD_ATA_CS_0__UART3_TXD,
+        MX53_PAD_ATA_CS_1__UART3_RXD,
+        MX53_PAD_ATA_DA_1__UART3_CTS,
+        MX53_PAD_ATA_DA_2__UART3_RTS,
+};
+
+static const struct imxuart_platform_data mx53_loco_uart_data __initconst = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static inline void mx53_loco_init_uart(void)
+{
+        imx53_add_imx_uart(0, &mx53_loco_uart_data);
+        imx53_add_imx_uart(1, &mx53_loco_uart_data);
+        imx53_add_imx_uart(2, &mx53_loco_uart_data);
+}
+
+static inline void mx53_loco_fec_reset(void)
+{
+        int ret;
+
+        /* reset FEC PHY */
+        ret = gpio_request(LOCO_FEC_PHY_RST, "fec-phy-reset");
+        if (ret) {
+                printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
+                return;
+        }
+        gpio_direction_output(LOCO_FEC_PHY_RST, 0);
+        msleep(1);
+        gpio_set_value(LOCO_FEC_PHY_RST, 1);
+}
+
+static struct fec_platform_data mx53_loco_fec_data = {
+        .phy = PHY_INTERFACE_MODE_RMII,
+};
+
+static void __init mx53_loco_board_init(void)
+{
+        mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads,
+                                        ARRAY_SIZE(mx53_loco_pads));
+        mx53_loco_init_uart();
+        mx53_loco_fec_reset();
+        imx53_add_fec(&mx53_loco_fec_data);
+}
+
+static void __init mx53_loco_timer_init(void)
+{
+        mx53_clocks_init(32768, 24000000, 0, 0);
+}
+
+static struct sys_timer mx53_loco_timer = {
+        .init   = mx53_loco_timer_init,
+};
+
+MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board")
+        .map_io = mx53_map_io,
+        .init_irq = mx53_init_irq,
+        .init_machine = mx53_loco_board_init,
+        .timer = &mx53_loco_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx53_smd.c b/arch/arm/mach-mx5/board-mx53_smd.c
new file mode 100644
index 000000000000..7970f7a48588
--- /dev/null
+++ b/arch/arm/mach-mx5/board-mx53_smd.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/fec.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux-mx53.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include "crm_regs.h"
+#include "devices-imx53.h"
+
+#define SMD_FEC_PHY_RST         IMX_GPIO_NR(7, 6)
+
+static iomux_v3_cfg_t mx53_smd_pads[] = {
+        MX53_PAD_CSI0_D10__UART1_TXD,
+        MX53_PAD_CSI0_D11__UART1_RXD,
+        MX53_PAD_ATA_DIOW__UART1_TXD,
+        MX53_PAD_ATA_DMACK__UART1_RXD,
+
+        MX53_PAD_ATA_BUFFER_EN__UART2_RXD,
+        MX53_PAD_ATA_DMARQ__UART2_TXD,
+        MX53_PAD_ATA_DIOR__UART2_RTS,
+        MX53_PAD_ATA_INTRQ__UART2_CTS,
+
+        MX53_PAD_ATA_CS_0__UART3_TXD,
+        MX53_PAD_ATA_CS_1__UART3_RXD,
+        MX53_PAD_ATA_DA_1__UART3_CTS,
+        MX53_PAD_ATA_DA_2__UART3_RTS,
+};
+
+static const struct imxuart_platform_data mx53_smd_uart_data __initconst = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static inline void mx53_smd_init_uart(void)
+{
+        imx53_add_imx_uart(0, &mx53_smd_uart_data);
+        imx53_add_imx_uart(1, &mx53_smd_uart_data);
+        imx53_add_imx_uart(2, &mx53_smd_uart_data);
+}
+
+static inline void mx53_smd_fec_reset(void)
+{
+        int ret;
+
+        /* reset FEC PHY */
+        ret = gpio_request(SMD_FEC_PHY_RST, "fec-phy-reset");
+        if (ret) {
+                printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
+                return;
+        }
+        gpio_direction_output(SMD_FEC_PHY_RST, 0);
+        msleep(1);
+        gpio_set_value(SMD_FEC_PHY_RST, 1);
+}
+
+static struct fec_platform_data mx53_smd_fec_data = {
+        .phy = PHY_INTERFACE_MODE_RMII,
+};
+
+static void __init mx53_smd_board_init(void)
+{
+        mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads,
+                                        ARRAY_SIZE(mx53_smd_pads));
+        mx53_smd_init_uart();
+        mx53_smd_fec_reset();
+        imx53_add_fec(&mx53_smd_fec_data);
+}
+
+static void __init mx53_smd_timer_init(void)
+{
+        mx53_clocks_init(32768, 24000000, 22579200, 0);
+}
+
+static struct sys_timer mx53_smd_timer = {
+        .init   = mx53_smd_timer_init,
+};
+
+MACHINE_START(MX53_SMD, "Freescale MX53 SMD Board")
+        .map_io = mx53_map_io,
+        .init_irq = mx53_init_irq,
+        .init_machine = mx53_smd_board_init,
+        .timer = &mx53_smd_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c
index 785e1a336183..0a19e7567c0b 100644
--- a/arch/arm/mach-mx5/clock-mx51-mx53.c
+++ b/arch/arm/mach-mx5/clock-mx51-mx53.c
@@ -1191,6 +1191,11 @@ DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
 DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
         NULL,  NULL, &ipg_clk, &gpt_ipg_clk);
 
+DEFINE_CLOCK(pwm1_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG6_OFFSET,
+        NULL, NULL, &ipg_clk, NULL);
+DEFINE_CLOCK(pwm2_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG8_OFFSET,
+        NULL, NULL, &ipg_clk, NULL);
+
 /* I2C */
 DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG9_OFFSET,
         NULL, NULL, &ipg_clk, NULL);
@@ -1283,6 +1288,8 @@ static struct clk_lookup mx51_lookups[] = {
         _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
         _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
         _REGISTER_CLOCK("fec.0", NULL, fec_clk)
+        _REGISTER_CLOCK("mxc_pwm.0", "pwm", pwm1_clk)
+        _REGISTER_CLOCK("mxc_pwm.1", "pwm", pwm2_clk)
         _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
         _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
         _REGISTER_CLOCK("imx-i2c.2", NULL, hsi2c_clk)
@@ -1295,7 +1302,7 @@ static struct clk_lookup mx51_lookups[] = {
         _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_ahb_clk)
         _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
         _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
-        _REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk)
+        _REGISTER_CLOCK("imx-keypad", NULL, kpp_clk)
         _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk)
         _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
         _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
@@ -1326,6 +1333,13 @@ static struct clk_lookup mx53_lookups[] = {
         _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
         _REGISTER_CLOCK("fec.0", NULL, fec_clk)
         _REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
+        _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
+        _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
+        _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
+        _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
+        _REGISTER_CLOCK("imx53-ecspi.0", NULL, ecspi1_clk)
+        _REGISTER_CLOCK("imx53-ecspi.1", NULL, ecspi2_clk)
+        _REGISTER_CLOCK("imx53-cspi.0", NULL, cspi_clk)
 };
 
 static void clk_tree_init(void)
@@ -1363,7 +1377,6 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
 
         clk_tree_init();
 
-        clk_set_parent(&uart_root_clk, &pll3_sw_clk);
         clk_enable(&cpu_clk);
         clk_enable(&main_bus_clk);
 
@@ -1406,6 +1419,7 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
 
         clk_tree_init();
 
+        clk_set_parent(&uart_root_clk, &pll3_sw_clk);
         clk_enable(&cpu_clk);
         clk_enable(&main_bus_clk);
 
diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h
index 6302e4670000..7fff485e5603 100644
--- a/arch/arm/mach-mx5/devices-imx51.h
+++ b/arch/arm/mach-mx5/devices-imx51.h
@@ -47,3 +47,11 @@ extern const struct imx_spi_imx_data imx51_ecspi_data[] __initconst;
 extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[] __initconst;
 #define imx51_add_imx2_wdt(id, pdata)   \
         imx_add_imx2_wdt(&imx51_imx2_wdt_data[id])
+
+extern const struct imx_mxc_pwm_data imx51_mxc_pwm_data[] __initconst;
+#define imx51_add_mxc_pwm(id)   \
+        imx_add_mxc_pwm(&imx51_mxc_pwm_data[id])
+
+extern const struct imx_imx_keypad_data imx51_imx_keypad_data __initconst;
+#define imx51_add_imx_keypad(pdata)     \
+        imx_add_imx_keypad(&imx51_imx_keypad_data, pdata)
diff --git a/arch/arm/mach-mx5/devices-imx53.h b/arch/arm/mach-mx5/devices-imx53.h
index 9d0ec2507fa6..8639735a117b 100644
--- a/arch/arm/mach-mx5/devices-imx53.h
+++ b/arch/arm/mach-mx5/devices-imx53.h
@@ -8,6 +8,24 @@
 #include <mach/mx53.h>
 #include <mach/devices-common.h>
 
+extern const struct imx_fec_data imx53_fec_data __initconst;
+#define imx53_add_fec(pdata)   \
+        imx_add_fec(&imx53_fec_data, pdata)
+
 extern const struct imx_imx_uart_1irq_data imx53_imx_uart_data[] __initconst;
 #define imx53_add_imx_uart(id, pdata)   \
         imx_add_imx_uart_1irq(&imx53_imx_uart_data[id], pdata)
+
+
+extern const struct imx_imx_i2c_data imx53_imx_i2c_data[] __initconst;
+#define imx53_add_imx_i2c(id, pdata)    \
+        imx_add_imx_i2c(&imx53_imx_i2c_data[id], pdata)
+
+extern const struct imx_sdhci_esdhc_imx_data
+imx53_sdhci_esdhc_imx_data[] __initconst;
+#define imx53_add_sdhci_esdhc_imx(id, pdata)    \
+        imx_add_sdhci_esdhc_imx(&imx53_sdhci_esdhc_imx_data[id], pdata)
+
+extern const struct imx_spi_imx_data imx53_ecspi_data[] __initconst;
+#define imx53_add_ecspi(id, pdata)      \
+        imx_add_spi_imx(&imx53_ecspi_data[id], pdata)
diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c
index 1bda5cb339dc..153ada53e575 100644
--- a/arch/arm/mach-mx5/devices.c
+++ b/arch/arm/mach-mx5/devices.c
@@ -120,25 +120,6 @@ struct platform_device mxc_usbh2_device = {
         },
 };
 
-static struct resource mxc_kpp_resources[] = {
-        {
-                .start = MX51_MXC_INT_KPP,
-                .end = MX51_MXC_INT_KPP,
-                .flags = IORESOURCE_IRQ,
-        } , {
-                .start = MX51_KPP_BASE_ADDR,
-                .end = MX51_KPP_BASE_ADDR + 0x8 - 1,
-                .flags = IORESOURCE_MEM,
-        },
-};
-
-struct platform_device mxc_keypad_device = {
-        .name = "imx-keypad",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(mxc_kpp_resources),
-        .resource = mxc_kpp_resources,
-};
-
 static struct mxc_gpio_port mxc_gpio_ports[] = {
         {
                 .chip.label = "gpio-0",
diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h
index 16891aa3573c..55a5129bc29f 100644
--- a/arch/arm/mach-mx5/devices.h
+++ b/arch/arm/mach-mx5/devices.h
@@ -3,4 +3,3 @@ extern struct platform_device mxc_usbh1_device;
 extern struct platform_device mxc_usbh2_device;
 extern struct platform_device mxc_usbdr_udc_device;
 extern struct platform_device mxc_hsi2c_device;
-extern struct platform_device mxc_keypad_device;
diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
index c96d018ff8a2..e83ffadb65f8 100644
--- a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
+++ b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
@@ -21,7 +21,6 @@
 #include <linux/fsl_devices.h>
 #include <linux/i2c/tsc2007.h>
 #include <linux/leds.h>
-#include <linux/input/matrix_keypad.h>
 
 #include <mach/common.h>
 #include <mach/hardware.h>
@@ -157,7 +156,7 @@ static int mbimx51_keymap[] = {
         KEY(3, 3, KEY_ENTER),
 };
 
-static struct matrix_keymap_data mbimx51_map_data = {
+static const struct matrix_keymap_data mbimx51_map_data __initconst = {
         .keymap         = mbimx51_keymap,
         .keymap_size    = ARRAY_SIZE(mbimx51_keymap),
 };
@@ -209,7 +208,7 @@ void __init eukrea_mbimx51_baseboard_init(void)
 
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
-        mxc_register_device(&mxc_keypad_device, &mbimx51_map_data);
+        imx51_add_imx_keypad(&mbimx51_map_data);
 
         gpio_request(MBIMX51_TSC2007_GPIO, "tsc2007_irq");
         gpio_direction_input(MBIMX51_TSC2007_GPIO);
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index c4ac7b415195..8bfc8df54617 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -15,7 +15,7 @@ comment "MXS platforms:"
 config MACH_MX23EVK
         bool "Support MX23EVK Platform"
         select SOC_IMX23
-        select MXS_HAVE_PLATFORM_DUART
+        select MXS_HAVE_AMBA_DUART
         default y
         help
           Include support for MX23EVK platform. This includes specific
@@ -24,7 +24,7 @@ config MACH_MX23EVK
 config MACH_MX28EVK
         bool "Support MX28EVK Platform"
         select SOC_IMX28
-        select MXS_HAVE_PLATFORM_DUART
+        select MXS_HAVE_AMBA_DUART
         select MXS_HAVE_PLATFORM_FEC
         default y
         help
diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c
index 8f5a19ab558c..b1a362ebfded 100644
--- a/arch/arm/mach-mxs/clock-mx23.c
+++ b/arch/arm/mach-mxs/clock-mx23.c
@@ -21,6 +21,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/jiffies.h>
+#include <linux/clkdev.h>
 
 #include <asm/clkdev.h>
 #include <asm/div64.h>
@@ -437,10 +438,12 @@ _DEFINE_CLOCK(clk32k_clk, XTAL, TIMROT_CLK32K_GATE, &ref_xtal_clk);
         },
 
 static struct clk_lookup lookups[] = {
-        _REGISTER_CLOCK("mxs-duart.0", NULL, uart_clk)
+        /* for amba bus driver */
+        _REGISTER_CLOCK("duart", "apb_pclk", xbus_clk)
+        /* for amba-pl011 driver */
+        _REGISTER_CLOCK("duart", NULL, uart_clk)
         _REGISTER_CLOCK("rtc", NULL, rtc_clk)
         _REGISTER_CLOCK(NULL, "hclk", hbus_clk)
-        _REGISTER_CLOCK(NULL, "xclk", xbus_clk)
         _REGISTER_CLOCK(NULL, "usb", usb_clk)
         _REGISTER_CLOCK(NULL, "audio", audio_clk)
         _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
@@ -518,6 +521,12 @@ int __init mx23_clocks_init(void)
 {
         clk_misc_init();
 
+        clk_enable(&cpu_clk);
+        clk_enable(&hbus_clk);
+        clk_enable(&xbus_clk);
+        clk_enable(&emi_clk);
+        clk_enable(&uart_clk);
+
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         mxs_timer_init(&clk32k_clk, MX23_INT_TIMER0);
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
index 74e2103c6011..56312c092a9e 100644
--- a/arch/arm/mach-mxs/clock-mx28.c
+++ b/arch/arm/mach-mxs/clock-mx28.c
@@ -21,6 +21,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/jiffies.h>
+#include <linux/clkdev.h>
 
 #include <asm/clkdev.h>
 #include <asm/div64.h>
@@ -602,7 +603,12 @@ _DEFINE_CLOCK(fec_clk, ENET, DISABLE, &hbus_clk);
         },
 
 static struct clk_lookup lookups[] = {
-        _REGISTER_CLOCK("mxs-duart.0", NULL, uart_clk)
+        /* for amba bus driver */
+        _REGISTER_CLOCK("duart", "apb_pclk", xbus_clk)
+        /* for amba-pl011 driver */
+        _REGISTER_CLOCK("duart", NULL, uart_clk)
+        _REGISTER_CLOCK("imx28-fec.0", NULL, fec_clk)
+        _REGISTER_CLOCK("imx28-fec.1", NULL, fec_clk)
         _REGISTER_CLOCK("fec.0", NULL, fec_clk)
         _REGISTER_CLOCK("rtc", NULL, rtc_clk)
         _REGISTER_CLOCK("pll2", NULL, pll2_clk)
@@ -726,6 +732,12 @@ int __init mx28_clocks_init(void)
 {
         clk_misc_init();
 
+        clk_enable(&cpu_clk);
+        clk_enable(&hbus_clk);
+        clk_enable(&xbus_clk);
+        clk_enable(&emi_clk);
+        clk_enable(&uart_clk);
+
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         mxs_timer_init(&clk32k_clk, MX28_INT_TIMER0);
diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h
index d0f49fc0abb5..1256788561d0 100644
--- a/arch/arm/mach-mxs/devices-mx23.h
+++ b/arch/arm/mach-mxs/devices-mx23.h
@@ -11,6 +11,6 @@
 #include <mach/mx23.h>
 #include <mach/devices-common.h>
 
-extern const struct mxs_duart_data mx23_duart_data __initconst;
+extern const struct amba_device mx23_duart_device __initconst;
 #define mx23_add_duart() \
-        mxs_add_duart(&mx23_duart_data)
+        mxs_add_duart(&mx23_duart_device)
diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h
index 00b736c434ba..33773a6333a2 100644
--- a/arch/arm/mach-mxs/devices-mx28.h
+++ b/arch/arm/mach-mxs/devices-mx28.h
@@ -11,9 +11,9 @@
 #include <mach/mx28.h>
 #include <mach/devices-common.h>
 
-extern const struct mxs_duart_data mx28_duart_data __initconst;
+extern const struct amba_device mx28_duart_device __initconst;
 #define mx28_add_duart() \
-        mxs_add_duart(&mx28_duart_data)
+        mxs_add_duart(&mx28_duart_device)
 
 extern const struct mxs_fec_data mx28_fec_data[] __initconst;
 #define mx28_add_fec(id, pdata) \
diff --git a/arch/arm/mach-mxs/devices.c b/arch/arm/mach-mxs/devices.c
index 6b60f02ca2e3..c20d54740b0b 100644
--- a/arch/arm/mach-mxs/devices.c
+++ b/arch/arm/mach-mxs/devices.c
@@ -19,9 +19,8 @@
 #include <linux/kernel.h>
 #include <linux/slab.h>
 #include <linux/init.h>
-#include <linux/err.h>
 #include <linux/platform_device.h>
-#include <mach/common.h>
+#include <linux/amba/bus.h>
 
 struct platform_device *__init mxs_add_platform_device_dmamask(
                 const char *name, int id,
@@ -73,3 +72,17 @@ err:
 
         return pdev;
 }
+
+int __init mxs_add_amba_device(const struct amba_device *dev)
+{
+        struct amba_device *adev = kmalloc(sizeof(*adev), GFP_KERNEL);
+
+        if (!adev) {
+                pr_err("%s: failed to allocate memory", __func__);
+                return -ENOMEM;
+        }
+
+        *adev = *dev;
+
+        return amba_device_register(adev, &iomem_resource);
+}
diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig
index a35a2dc55395..cf7dc1ae575b 100644
--- a/arch/arm/mach-mxs/devices/Kconfig
+++ b/arch/arm/mach-mxs/devices/Kconfig
@@ -1,5 +1,6 @@
-config MXS_HAVE_PLATFORM_DUART
+config MXS_HAVE_AMBA_DUART
         bool
+        select ARM_AMBA
 
 config MXS_HAVE_PLATFORM_FEC
         bool
diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile
index 4b5266a3e6d9..d0a09f6934b8 100644
--- a/arch/arm/mach-mxs/devices/Makefile
+++ b/arch/arm/mach-mxs/devices/Makefile
@@ -1,2 +1,2 @@
-obj-$(CONFIG_MXS_HAVE_PLATFORM_DUART) += platform-duart.o
+obj-$(CONFIG_MXS_HAVE_AMBA_DUART) += amba-duart.o
 obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o
diff --git a/arch/arm/mach-mxs/devices/amba-duart.c b/arch/arm/mach-mxs/devices/amba-duart.c
new file mode 100644
index 000000000000..a559db09b49c
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/amba-duart.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2009-2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <asm/irq.h>
+#include <mach/mx23.h>
+#include <mach/mx28.h>
+#include <mach/devices-common.h>
+
+#define MXS_AMBA_DUART_DEVICE(name, soc)                        \
+const struct amba_device name##_device __initconst = {          \
+        .dev = {                                                \
+                .init_name = "duart",                           \
+        },                                                      \
+        .res = {                                                \
+                .start = soc ## _DUART_BASE_ADDR,               \
+                .end = (soc ## _DUART_BASE_ADDR) + SZ_8K - 1,   \
+                .flags = IORESOURCE_MEM,                        \
+        },                                                      \
+        .irq = {soc ## _INT_DUART, NO_IRQ},                     \
+}
+
+#ifdef CONFIG_SOC_IMX23
+MXS_AMBA_DUART_DEVICE(mx23_duart, MX23);
+#endif
+
+#ifdef CONFIG_SOC_IMX28
+MXS_AMBA_DUART_DEVICE(mx28_duart, MX28);
+#endif
+
+int __init mxs_add_duart(const struct amba_device *dev)
+{
+        return mxs_add_amba_device(dev);
+}
diff --git a/arch/arm/mach-mxs/devices/platform-duart.c b/arch/arm/mach-mxs/devices/platform-duart.c
deleted file mode 100644
index 2fe0df5b0aad..000000000000
--- a/arch/arm/mach-mxs/devices/platform-duart.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-
-#define mxs_duart_data_entry(soc)                                       \
-        {                                                               \
-                .iobase = soc ## _DUART_BASE_ADDR,                      \
-                .irq = soc ## _INT_DUART,                               \
-        }
-
-#ifdef CONFIG_SOC_IMX23
-const struct mxs_duart_data mx23_duart_data __initconst =
-        mxs_duart_data_entry(MX23);
-#endif
-
-#ifdef CONFIG_SOC_IMX28
-const struct mxs_duart_data mx28_duart_data __initconst =
-        mxs_duart_data_entry(MX28);
-#endif
-
-struct platform_device *__init mxs_add_duart(
-                const struct mxs_duart_data *data)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + SZ_8K - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        return mxs_add_platform_device("mxs-duart", 0, res, ARRAY_SIZE(res),
-                                        NULL, 0);
-}
diff --git a/arch/arm/mach-mxs/devices/platform-fec.c b/arch/arm/mach-mxs/devices/platform-fec.c
index c08168cf3dec..c42dff72b46c 100644
--- a/arch/arm/mach-mxs/devices/platform-fec.c
+++ b/arch/arm/mach-mxs/devices/platform-fec.c
@@ -45,6 +45,6 @@ struct platform_device *__init mxs_add_fec(
                 },
         };
 
-        return mxs_add_platform_device("fec", data->id,
+        return mxs_add_platform_device("imx28-fec", data->id,
                         res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
 }
diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h
index 3da48d4d3273..6c3d1a103433 100644
--- a/arch/arm/mach-mxs/include/mach/devices-common.h
+++ b/arch/arm/mach-mxs/include/mach/devices-common.h
@@ -9,6 +9,7 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 #include <linux/init.h>
+#include <linux/amba/bus.h>
 
 struct platform_device *mxs_add_platform_device_dmamask(
                 const char *name, int id,
@@ -24,14 +25,10 @@ static inline struct platform_device *mxs_add_platform_device(
                         name, id, res, num_resources, data, size_data, 0);
 }
 
+int __init mxs_add_amba_device(const struct amba_device *dev);
+
 /* duart */
-struct mxs_duart_data {
-        resource_size_t iobase;
-        resource_size_t iosize;
-        resource_size_t irq;
-};
-struct platform_device *__init mxs_add_duart(
-                const struct mxs_duart_data *data);
+int __init mxs_add_duart(const struct amba_device *dev);
 
 /* fec */
 #include <linux/fec.h>
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c
index d162e95910f3..8e2c5975001e 100644
--- a/arch/arm/mach-mxs/mach-mx28evk.c
+++ b/arch/arm/mach-mxs/mach-mx28evk.c
@@ -57,6 +57,19 @@ static const iomux_cfg_t mx28evk_pads[] __initconst = {
                 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
         MX28_PAD_ENET_CLK__CLKCTRL_ENET |
                 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        /* fec1 */
+        MX28_PAD_ENET0_CRS__ENET1_RX_EN |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_ENET0_RXD2__ENET1_RXD0 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_ENET0_RXD3__ENET1_RXD1 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_ENET0_COL__ENET1_TX_EN |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_ENET0_TXD2__ENET1_TXD0 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_ENET0_TXD3__ENET1_TXD1 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
         /* phy power line */
         MX28_PAD_SSP1_DATA3__GPIO_2_15 |
                 (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
@@ -106,8 +119,14 @@ static void __init mx28evk_fec_reset(void)
         gpio_set_value(MX28EVK_FEC_PHY_RESET, 1);
 }
 
-static const struct fec_platform_data mx28_fec_pdata __initconst = {
-        .phy = PHY_INTERFACE_MODE_RMII,
+static struct fec_platform_data mx28_fec_pdata[] = {
+        {
+                /* fec0 */
+                .phy = PHY_INTERFACE_MODE_RMII,
+        }, {
+                /* fec1 */
+                .phy = PHY_INTERFACE_MODE_RMII,
+        },
 };
 
 static void __init mx28evk_init(void)
@@ -117,7 +136,8 @@ static void __init mx28evk_init(void)
         mx28_add_duart();
 
         mx28evk_fec_reset();
-        mx28_add_fec(0, &mx28_fec_pdata);
+        mx28_add_fec(0, &mx28_fec_pdata[0]);
+        mx28_add_fec(1, &mx28_fec_pdata[1]);
 }
 
 static void __init mx28evk_timer_init(void)
diff --git a/arch/arm/mach-netx/generic.c b/arch/arm/mach-netx/generic.c
index 43da8bb4926b..29ffa750fbe6 100644
--- a/arch/arm/mach-netx/generic.c
+++ b/arch/arm/mach-netx/generic.c
@@ -88,13 +88,13 @@ netx_hif_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
 }
 
 static int
-netx_hif_irq_type(unsigned int _irq, unsigned int type)
+netx_hif_irq_type(struct irq_data *d, unsigned int type)
 {
         unsigned int val, irq;
 
         val = readl(NETX_DPMAS_IF_CONF1);
 
-        irq = _irq - NETX_IRQ_HIF_CHAINED(0);
+        irq = d->irq - NETX_IRQ_HIF_CHAINED(0);
 
         if (type & IRQ_TYPE_EDGE_RISING) {
                 DEBUG_IRQ("rising edges\n");
@@ -119,49 +119,49 @@ netx_hif_irq_type(unsigned int _irq, unsigned int type)
 }
 
 static void
-netx_hif_ack_irq(unsigned int _irq)
+netx_hif_ack_irq(struct irq_data *d)
 {
         unsigned int val, irq;
 
-        irq = _irq - NETX_IRQ_HIF_CHAINED(0);
+        irq = d->irq - NETX_IRQ_HIF_CHAINED(0);
         writel((1 << 24) << irq, NETX_DPMAS_INT_STAT);
 
         val = readl(NETX_DPMAS_INT_EN);
         val &= ~((1 << 24) << irq);
         writel(val, NETX_DPMAS_INT_EN);
 
-        DEBUG_IRQ("%s: irq %d\n", __func__, _irq);
+        DEBUG_IRQ("%s: irq %d\n", __func__, d->irq);
 }
 
 static void
-netx_hif_mask_irq(unsigned int _irq)
+netx_hif_mask_irq(struct irq_data *d)
 {
         unsigned int val, irq;
 
-        irq = _irq - NETX_IRQ_HIF_CHAINED(0);
+        irq = d->irq - NETX_IRQ_HIF_CHAINED(0);
         val = readl(NETX_DPMAS_INT_EN);
         val &= ~((1 << 24) << irq);
         writel(val, NETX_DPMAS_INT_EN);
-        DEBUG_IRQ("%s: irq %d\n", __func__, _irq);
+        DEBUG_IRQ("%s: irq %d\n", __func__, d->irq);
 }
 
 static void
-netx_hif_unmask_irq(unsigned int _irq)
+netx_hif_unmask_irq(struct irq_data *d)
 {
         unsigned int val, irq;
 
-        irq = _irq - NETX_IRQ_HIF_CHAINED(0);
+        irq = d->irq - NETX_IRQ_HIF_CHAINED(0);
         val = readl(NETX_DPMAS_INT_EN);
         val |= (1 << 24) << irq;
         writel(val, NETX_DPMAS_INT_EN);
-        DEBUG_IRQ("%s: irq %d\n", __func__, _irq);
+        DEBUG_IRQ("%s: irq %d\n", __func__, d->irq);
 }
 
 static struct irq_chip netx_hif_chip = {
-        .ack = netx_hif_ack_irq,
-        .mask = netx_hif_mask_irq,
-        .unmask = netx_hif_unmask_irq,
-        .set_type = netx_hif_irq_type,
+        .irq_ack = netx_hif_ack_irq,
+        .irq_mask = netx_hif_mask_irq,
+        .irq_unmask = netx_hif_unmask_irq,
+        .irq_set_type = netx_hif_irq_type,
 };
 
 void __init netx_init_irq(void)
diff --git a/arch/arm/mach-ns9xxx/board-a9m9750dev.c b/arch/arm/mach-ns9xxx/board-a9m9750dev.c
index b45bb3b802f1..0c0d5248c368 100644
--- a/arch/arm/mach-ns9xxx/board-a9m9750dev.c
+++ b/arch/arm/mach-ns9xxx/board-a9m9750dev.c
@@ -37,44 +37,44 @@ void __init board_a9m9750dev_map_io(void)
                      ARRAY_SIZE(board_a9m9750dev_io_desc));
 }
 
-static void a9m9750dev_fpga_ack_irq(unsigned int irq)
+static void a9m9750dev_fpga_ack_irq(struct irq_data *d)
 {
         /* nothing */
 }
 
-static void a9m9750dev_fpga_mask_irq(unsigned int irq)
+static void a9m9750dev_fpga_mask_irq(struct irq_data *d)
 {
         u8 ier;
 
         ier = __raw_readb(FPGA_IER);
 
-        ier &= ~(1 << (irq - FPGA_IRQ(0)));
+        ier &= ~(1 << (d->irq - FPGA_IRQ(0)));
 
         __raw_writeb(ier, FPGA_IER);
 }
 
-static void a9m9750dev_fpga_maskack_irq(unsigned int irq)
+static void a9m9750dev_fpga_maskack_irq(struct irq_data *d)
 {
-        a9m9750dev_fpga_mask_irq(irq);
-        a9m9750dev_fpga_ack_irq(irq);
+        a9m9750dev_fpga_mask_irq(d);
+        a9m9750dev_fpga_ack_irq(d);
 }
 
-static void a9m9750dev_fpga_unmask_irq(unsigned int irq)
+static void a9m9750dev_fpga_unmask_irq(struct irq_data *d)
 {
         u8 ier;
 
         ier = __raw_readb(FPGA_IER);
 
-        ier |= 1 << (irq - FPGA_IRQ(0));
+        ier |= 1 << (d->irq - FPGA_IRQ(0));
 
         __raw_writeb(ier, FPGA_IER);
 }
 
 static struct irq_chip a9m9750dev_fpga_chip = {
-        .ack            = a9m9750dev_fpga_ack_irq,
-        .mask           = a9m9750dev_fpga_mask_irq,
-        .mask_ack       = a9m9750dev_fpga_maskack_irq,
-        .unmask         = a9m9750dev_fpga_unmask_irq,
+        .irq_ack        = a9m9750dev_fpga_ack_irq,
+        .irq_mask       = a9m9750dev_fpga_mask_irq,
+        .irq_mask_ack   = a9m9750dev_fpga_maskack_irq,
+        .irq_unmask     = a9m9750dev_fpga_unmask_irq,
 };
 
 static void a9m9750dev_fpga_demux_handler(unsigned int irq,
@@ -82,7 +82,7 @@ static void a9m9750dev_fpga_demux_handler(unsigned int irq,
 {
         u8 stat = __raw_readb(FPGA_ISR);
 
-        desc->chip->mask_ack(irq);
+        desc->irq_data.chip->irq_mask_ack(&desc->irq_data);
 
         while (stat != 0) {
                 int irqno = fls(stat) - 1;
@@ -92,7 +92,7 @@ static void a9m9750dev_fpga_demux_handler(unsigned int irq,
                 generic_handle_irq(FPGA_IRQ(irqno));
         }
 
-        desc->chip->unmask(irq);
+        desc->irq_data.chip->irq_unmask(&desc->irq_data);
 }
 
 void __init board_a9m9750dev_init_irq(void)
diff --git a/arch/arm/mach-ns9xxx/irq.c b/arch/arm/mach-ns9xxx/irq.c
index 038f24d47023..389fa5c669de 100644
--- a/arch/arm/mach-ns9xxx/irq.c
+++ b/arch/arm/mach-ns9xxx/irq.c
@@ -22,40 +22,40 @@
 #define irq2prio(i) (i)
 #define prio2irq(p) (p)
 
-static void ns9xxx_mask_irq(unsigned int irq)
+static void ns9xxx_mask_irq(struct irq_data *d)
 {
         /* XXX: better use cpp symbols */
-        int prio = irq2prio(irq);
+        int prio = irq2prio(d->irq);
         u32 ic = __raw_readl(SYS_IC(prio / 4));
         ic &= ~(1 << (7 + 8 * (3 - (prio & 3))));
         __raw_writel(ic, SYS_IC(prio / 4));
 }
 
-static void ns9xxx_ack_irq(unsigned int irq)
+static void ns9xxx_ack_irq(struct irq_data *d)
 {
         __raw_writel(0, SYS_ISRADDR);
 }
 
-static void ns9xxx_maskack_irq(unsigned int irq)
+static void ns9xxx_maskack_irq(struct irq_data *d)
 {
-        ns9xxx_mask_irq(irq);
-        ns9xxx_ack_irq(irq);
+        ns9xxx_mask_irq(d);
+        ns9xxx_ack_irq(d);
 }
 
-static void ns9xxx_unmask_irq(unsigned int irq)
+static void ns9xxx_unmask_irq(struct irq_data *d)
 {
         /* XXX: better use cpp symbols */
-        int prio = irq2prio(irq);
+        int prio = irq2prio(d->irq);
         u32 ic = __raw_readl(SYS_IC(prio / 4));
         ic |= 1 << (7 + 8 * (3 - (prio & 3)));
         __raw_writel(ic, SYS_IC(prio / 4));
 }
 
 static struct irq_chip ns9xxx_chip = {
-        .ack            = ns9xxx_ack_irq,
-        .mask           = ns9xxx_mask_irq,
-        .mask_ack       = ns9xxx_maskack_irq,
-        .unmask         = ns9xxx_unmask_irq,
+        .irq_ack        = ns9xxx_ack_irq,
+        .irq_mask       = ns9xxx_mask_irq,
+        .irq_mask_ack   = ns9xxx_maskack_irq,
+        .irq_unmask     = ns9xxx_unmask_irq,
 };
 
 #if 0
@@ -92,10 +92,10 @@ static void handle_prio_irq(unsigned int irq, struct irq_desc *desc)
 
         if (desc->status & IRQ_DISABLED)
 out_mask:
-                desc->chip->mask(irq);
+                desc->irq_data.chip->irq_mask(&desc->irq_data);
 
         /* ack unconditionally to unmask lower prio irqs */
-        desc->chip->ack(irq);
+        desc->irq_data.chip->irq_ack(&desc->irq_data);
 
         raw_spin_unlock(&desc->lock);
 }
diff --git a/arch/arm/mach-nuc93x/irq.c b/arch/arm/mach-nuc93x/irq.c
index a7a88ea4ec31..1f8a05a22834 100644
--- a/arch/arm/mach-nuc93x/irq.c
+++ b/arch/arm/mach-nuc93x/irq.c
@@ -25,9 +25,9 @@
 #include <mach/hardware.h>
 #include <mach/regs-irq.h>
 
-static void nuc93x_irq_mask(unsigned int irq)
+static void nuc93x_irq_mask(struct irq_data *d)
 {
-        __raw_writel(1 << irq, REG_AIC_MDCR);
+        __raw_writel(1 << d->irq, REG_AIC_MDCR);
 }
 
 /*
@@ -35,21 +35,21 @@ static void nuc93x_irq_mask(unsigned int irq)
  * to REG_AIC_EOSCR for ACK
  */
 
-static void nuc93x_irq_ack(unsigned int irq)
+static void nuc93x_irq_ack(struct irq_data *d)
 {
         __raw_writel(0x01, REG_AIC_EOSCR);
 }
 
-static void nuc93x_irq_unmask(unsigned int irq)
+static void nuc93x_irq_unmask(struct irq_data *d)
 {
-        __raw_writel(1 << irq, REG_AIC_MECR);
+        __raw_writel(1 << d->irq, REG_AIC_MECR);
 
 }
 
 static struct irq_chip nuc93x_irq_chip = {
-        .ack       = nuc93x_irq_ack,
-        .mask      = nuc93x_irq_mask,
-        .unmask    = nuc93x_irq_unmask,
+        .irq_ack        = nuc93x_irq_ack,
+        .irq_mask       = nuc93x_irq_mask,
+        .irq_unmask     = nuc93x_irq_unmask,
 };
 
 void __init nuc93x_init_irq(void)
diff --git a/arch/arm/mach-omap1/ams-delta-fiq.c b/arch/arm/mach-omap1/ams-delta-fiq.c
index 6c994e2d8879..152b32c15e28 100644
--- a/arch/arm/mach-omap1/ams-delta-fiq.c
+++ b/arch/arm/mach-omap1/ams-delta-fiq.c
@@ -49,7 +49,7 @@ static irqreturn_t deferred_fiq(int irq, void *dev_id)
 
         irq_desc = irq_to_desc(IH_GPIO_BASE);
         if (irq_desc)
-                irq_chip = irq_desc->chip;
+                irq_chip = irq_desc->irq_data.chip;
 
         /*
          * For each handled GPIO interrupt, keep calling its interrupt handler
@@ -62,13 +62,15 @@ static irqreturn_t deferred_fiq(int irq, void *dev_id)
 
                 while (irq_counter[gpio] < fiq_count) {
                         if (gpio != AMS_DELTA_GPIO_PIN_KEYBRD_CLK) {
+                                struct irq_data *d = irq_get_irq_data(irq_num);
+
                                 /*
                                  * It looks like handle_edge_irq() that
                                  * OMAP GPIO edge interrupts default to,
                                  * expects interrupt already unmasked.
                                  */
-                                if (irq_chip && irq_chip->unmask)
-                                        irq_chip->unmask(irq_num);
+                                if (irq_chip && irq_chip->irq_unmask)
+                                        irq_chip->irq_unmask(d);
                         }
                         generic_handle_irq(irq_num);
 
diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c
index 8780e75cdc3d..0ace7998aaa5 100644
--- a/arch/arm/mach-omap1/fpga.c
+++ b/arch/arm/mach-omap1/fpga.c
@@ -30,9 +30,9 @@
 #include <plat/fpga.h>
 #include <mach/gpio.h>
 
-static void fpga_mask_irq(unsigned int irq)
+static void fpga_mask_irq(struct irq_data *d)
 {
-        irq -= OMAP_FPGA_IRQ_BASE;
+        unsigned int irq = d->irq - OMAP_FPGA_IRQ_BASE;
 
         if (irq < 8)
                 __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO)
@@ -58,14 +58,14 @@ static inline u32 get_fpga_unmasked_irqs(void)
 }
 
 
-static void fpga_ack_irq(unsigned int irq)
+static void fpga_ack_irq(struct irq_data *d)
 {
         /* Don't need to explicitly ACK FPGA interrupts */
 }
 
-static void fpga_unmask_irq(unsigned int irq)
+static void fpga_unmask_irq(struct irq_data *d)
 {
-        irq -= OMAP_FPGA_IRQ_BASE;
+        unsigned int irq = d->irq - OMAP_FPGA_IRQ_BASE;
 
         if (irq < 8)
                 __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO) | (1 << irq)),
@@ -78,10 +78,10 @@ static void fpga_unmask_irq(unsigned int irq)
                               | (1 << (irq - 16))), INNOVATOR_FPGA_IMR2);
 }
 
-static void fpga_mask_ack_irq(unsigned int irq)
+static void fpga_mask_ack_irq(struct irq_data *d)
 {
-        fpga_mask_irq(irq);
-        fpga_ack_irq(irq);
+        fpga_mask_irq(d);
+        fpga_ack_irq(d);
 }
 
 void innovator_fpga_IRQ_demux(unsigned int irq, struct irq_desc *desc)
@@ -105,17 +105,17 @@ void innovator_fpga_IRQ_demux(unsigned int irq, struct irq_desc *desc)
 
 static struct irq_chip omap_fpga_irq_ack = {
         .name           = "FPGA-ack",
-        .ack            = fpga_mask_ack_irq,
-        .mask           = fpga_mask_irq,
-        .unmask         = fpga_unmask_irq,
+        .irq_ack        = fpga_mask_ack_irq,
+        .irq_mask       = fpga_mask_irq,
+        .irq_unmask     = fpga_unmask_irq,
 };
 
 
 static struct irq_chip omap_fpga_irq = {
         .name           = "FPGA",
-        .ack            = fpga_ack_irq,
-        .mask           = fpga_mask_irq,
-        .unmask         = fpga_unmask_irq,
+        .irq_ack        = fpga_ack_irq,
+        .irq_mask       = fpga_mask_irq,
+        .irq_unmask     = fpga_unmask_irq,
 };
 
 /*
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c
index 6bddbc869f4c..47701584df35 100644
--- a/arch/arm/mach-omap1/irq.c
+++ b/arch/arm/mach-omap1/irq.c
@@ -70,48 +70,48 @@ static inline void irq_bank_writel(unsigned long value, int bank, int offset)
         omap_writel(value, irq_banks[bank].base_reg + offset);
 }
 
-static void omap_ack_irq(unsigned int irq)
+static void omap_ack_irq(struct irq_data *d)
 {
-        if (irq > 31)
+        if (d->irq > 31)
                 omap_writel(0x1, OMAP_IH2_BASE + IRQ_CONTROL_REG_OFFSET);
 
         omap_writel(0x1, OMAP_IH1_BASE + IRQ_CONTROL_REG_OFFSET);
 }
 
-static void omap_mask_irq(unsigned int irq)
+static void omap_mask_irq(struct irq_data *d)
 {
-        int bank = IRQ_BANK(irq);
+        int bank = IRQ_BANK(d->irq);
         u32 l;
 
         l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
-        l |= 1 << IRQ_BIT(irq);
+        l |= 1 << IRQ_BIT(d->irq);
         omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
 }
 
-static void omap_unmask_irq(unsigned int irq)
+static void omap_unmask_irq(struct irq_data *d)
 {
-        int bank = IRQ_BANK(irq);
+        int bank = IRQ_BANK(d->irq);
         u32 l;
 
         l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
-        l &= ~(1 << IRQ_BIT(irq));
+        l &= ~(1 << IRQ_BIT(d->irq));
         omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
 }
 
-static void omap_mask_ack_irq(unsigned int irq)
+static void omap_mask_ack_irq(struct irq_data *d)
 {
-        omap_mask_irq(irq);
-        omap_ack_irq(irq);
+        omap_mask_irq(d);
+        omap_ack_irq(d);
 }
 
-static int omap_wake_irq(unsigned int irq, unsigned int enable)
+static int omap_wake_irq(struct irq_data *d, unsigned int enable)
 {
-        int bank = IRQ_BANK(irq);
+        int bank = IRQ_BANK(d->irq);
 
         if (enable)
-                irq_banks[bank].wake_enable |= IRQ_BIT(irq);
+                irq_banks[bank].wake_enable |= IRQ_BIT(d->irq);
         else
-                irq_banks[bank].wake_enable &= ~IRQ_BIT(irq);
+                irq_banks[bank].wake_enable &= ~IRQ_BIT(d->irq);
 
         return 0;
 }
@@ -168,10 +168,10 @@ static struct omap_irq_bank omap1610_irq_banks[] = {
 
 static struct irq_chip omap_irq_chip = {
         .name           = "MPU",
-        .ack            = omap_mask_ack_irq,
-        .mask           = omap_mask_irq,
-        .unmask         = omap_unmask_irq,
-        .set_wake       = omap_wake_irq,
+        .irq_ack        = omap_mask_ack_irq,
+        .irq_mask       = omap_mask_irq,
+        .irq_unmask     = omap_unmask_irq,
+        .irq_set_wake   = omap_wake_irq,
 };
 
 void __init omap_init_irq(void)
@@ -239,9 +239,9 @@ void __init omap_init_irq(void)
         /* Unmask level 2 handler */
 
         if (cpu_is_omap7xx())
-                omap_unmask_irq(INT_7XX_IH2_IRQ);
+                omap_unmask_irq(irq_get_irq_data(INT_7XX_IH2_IRQ));
         else if (cpu_is_omap15xx())
-                omap_unmask_irq(INT_1510_IH2_IRQ);
+                omap_unmask_irq(irq_get_irq_data(INT_1510_IH2_IRQ));
         else if (cpu_is_omap16xx())
-                omap_unmask_irq(INT_1610_IH2_IRQ);
+                omap_unmask_irq(irq_get_irq_data(INT_1610_IH2_IRQ));
 }
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 85bf8ca95fd3..23049c487c47 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -100,13 +100,14 @@ static int omap_check_spurious(unsigned int irq)
 }
 
 /* XXX: FIQ and additional INTC support (only MPU at the moment) */
-static void omap_ack_irq(unsigned int irq)
+static void omap_ack_irq(struct irq_data *d)
 {
         intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
 }
 
-static void omap_mask_irq(unsigned int irq)
+static void omap_mask_irq(struct irq_data *d)
 {
+        unsigned int irq = d->irq;
         int offset = irq & (~(IRQ_BITS_PER_REG - 1));
 
         if (cpu_is_omap34xx()) {
@@ -128,8 +129,9 @@ static void omap_mask_irq(unsigned int irq)
         intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_SET0 + offset);
 }
 
-static void omap_unmask_irq(unsigned int irq)
+static void omap_unmask_irq(struct irq_data *d)
 {
+        unsigned int irq = d->irq;
         int offset = irq & (~(IRQ_BITS_PER_REG - 1));
 
         irq &= (IRQ_BITS_PER_REG - 1);
@@ -137,17 +139,17 @@ static void omap_unmask_irq(unsigned int irq)
         intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_CLEAR0 + offset);
 }
 
-static void omap_mask_ack_irq(unsigned int irq)
+static void omap_mask_ack_irq(struct irq_data *d)
 {
-        omap_mask_irq(irq);
-        omap_ack_irq(irq);
+        omap_mask_irq(d);
+        omap_ack_irq(d);
 }
 
 static struct irq_chip omap_irq_chip = {
-        .name   = "INTC",
-        .ack    = omap_mask_ack_irq,
-        .mask   = omap_mask_irq,
-        .unmask = omap_unmask_irq,
+        .name           = "INTC",
+        .irq_ack        = omap_mask_ack_irq,
+        .irq_mask       = omap_mask_irq,
+        .irq_unmask     = omap_unmask_irq,
 };
 
 static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
diff --git a/arch/arm/mach-pnx4008/irq.c b/arch/arm/mach-pnx4008/irq.c
index a9ce02b4bf17..c69c180aec76 100644
--- a/arch/arm/mach-pnx4008/irq.c
+++ b/arch/arm/mach-pnx4008/irq.c
@@ -36,44 +36,44 @@
 
 static u8 pnx4008_irq_type[NR_IRQS] = PNX4008_IRQ_TYPES;
 
-static void pnx4008_mask_irq(unsigned int irq)
+static void pnx4008_mask_irq(struct irq_data *d)
 {
-        __raw_writel(__raw_readl(INTC_ER(irq)) & ~INTC_BIT(irq), INTC_ER(irq)); /* mask interrupt */
+        __raw_writel(__raw_readl(INTC_ER(d->irq)) & ~INTC_BIT(d->irq), INTC_ER(d->irq));        /* mask interrupt */
 }
 
-static void pnx4008_unmask_irq(unsigned int irq)
+static void pnx4008_unmask_irq(struct irq_data *d)
 {
-        __raw_writel(__raw_readl(INTC_ER(irq)) | INTC_BIT(irq), INTC_ER(irq));  /* unmask interrupt */
+        __raw_writel(__raw_readl(INTC_ER(d->irq)) | INTC_BIT(d->irq), INTC_ER(d->irq)); /* unmask interrupt */
 }
 
-static void pnx4008_mask_ack_irq(unsigned int irq)
+static void pnx4008_mask_ack_irq(struct irq_data *d)
 {
-        __raw_writel(__raw_readl(INTC_ER(irq)) & ~INTC_BIT(irq), INTC_ER(irq)); /* mask interrupt */
-        __raw_writel(INTC_BIT(irq), INTC_SR(irq));      /* clear interrupt status */
+        __raw_writel(__raw_readl(INTC_ER(d->irq)) & ~INTC_BIT(d->irq), INTC_ER(d->irq));        /* mask interrupt */
+        __raw_writel(INTC_BIT(d->irq), INTC_SR(d->irq));        /* clear interrupt status */
 }
 
-static int pnx4008_set_irq_type(unsigned int irq, unsigned int type)
+static int pnx4008_set_irq_type(struct irq_data *d, unsigned int type)
 {
         switch (type) {
         case IRQ_TYPE_EDGE_RISING:
-                __raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq));        /*edge sensitive */
-                __raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq));        /*rising edge */
-                set_irq_handler(irq, handle_edge_irq);
+                __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq));       /*edge sensitive */
+                __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq));       /*rising edge */
+                set_irq_handler(d->irq, handle_edge_irq);
                 break;
         case IRQ_TYPE_EDGE_FALLING:
-                __raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq));        /*edge sensitive */
-                __raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq));       /*falling edge */
-                set_irq_handler(irq, handle_edge_irq);
+                __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq));       /*edge sensitive */
+                __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq));      /*falling edge */
+                set_irq_handler(d->irq, handle_edge_irq);
                 break;
         case IRQ_TYPE_LEVEL_LOW:
-                __raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq));       /*level sensitive */
-                __raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq));       /*low level */
-                set_irq_handler(irq, handle_level_irq);
+                __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq));      /*level sensitive */
+                __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq));      /*low level */
+                set_irq_handler(d->irq, handle_level_irq);
                 break;
         case IRQ_TYPE_LEVEL_HIGH:
-                __raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq));       /*level sensitive */
-                __raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq));        /* high level */
-                set_irq_handler(irq, handle_level_irq);
+                __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq));      /*level sensitive */
+                __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq));       /* high level */
+                set_irq_handler(d->irq, handle_level_irq);
                 break;
 
         /* IRQ_TYPE_EDGE_BOTH is not supported */
@@ -85,10 +85,10 @@ static int pnx4008_set_irq_type(unsigned int irq, unsigned int type)
 }
 
 static struct irq_chip pnx4008_irq_chip = {
-        .ack = pnx4008_mask_ack_irq,
-        .mask = pnx4008_mask_irq,
-        .unmask = pnx4008_unmask_irq,
-        .set_type = pnx4008_set_irq_type,
+        .irq_ack = pnx4008_mask_ack_irq,
+        .irq_mask = pnx4008_mask_irq,
+        .irq_unmask = pnx4008_unmask_irq,
+        .irq_set_type = pnx4008_set_irq_type,
 };
 
 void __init pnx4008_init_irq(void)
@@ -99,14 +99,18 @@ void __init pnx4008_init_irq(void)
         for (i = 0; i < NR_IRQS; i++) {
                 set_irq_flags(i, IRQF_VALID);
                 set_irq_chip(i, &pnx4008_irq_chip);
-                pnx4008_set_irq_type(i, pnx4008_irq_type[i]);
+                pnx4008_set_irq_type(irq_get_irq_data(i), pnx4008_irq_type[i]);
         }
 
         /* configure and enable IRQ 0,1,30,31 (cascade interrupts) */
-        pnx4008_set_irq_type(SUB1_IRQ_N, pnx4008_irq_type[SUB1_IRQ_N]);
-        pnx4008_set_irq_type(SUB2_IRQ_N, pnx4008_irq_type[SUB2_IRQ_N]);
-        pnx4008_set_irq_type(SUB1_FIQ_N, pnx4008_irq_type[SUB1_FIQ_N]);
-        pnx4008_set_irq_type(SUB2_FIQ_N, pnx4008_irq_type[SUB2_FIQ_N]);
+        pnx4008_set_irq_type(irq_get_irq_data(SUB1_IRQ_N),
+                             pnx4008_irq_type[SUB1_IRQ_N]);
+        pnx4008_set_irq_type(irq_get_irq_data(SUB2_IRQ_N),
+                             pnx4008_irq_type[SUB2_IRQ_N]);
+        pnx4008_set_irq_type(irq_get_irq_data(SUB1_FIQ_N),
+                             pnx4008_irq_type[SUB1_FIQ_N]);
+        pnx4008_set_irq_type(irq_get_irq_data(SUB2_FIQ_N),
+                             pnx4008_irq_type[SUB2_FIQ_N]);
 
         /* mask all others */
         __raw_writel((1 << SUB2_FIQ_N) | (1 << SUB1_FIQ_N) |
diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c
index ccb2d0cebcc3..a134a1413e01 100644
--- a/arch/arm/mach-pxa/balloon3.c
+++ b/arch/arm/mach-pxa/balloon3.c
@@ -477,25 +477,25 @@ static inline void balloon3_leds_init(void) {}
 /******************************************************************************
  * FPGA IRQ
  ******************************************************************************/
-static void balloon3_mask_irq(unsigned int irq)
+static void balloon3_mask_irq(struct irq_data *d)
 {
-        int balloon3_irq = (irq - BALLOON3_IRQ(0));
+        int balloon3_irq = (d->irq - BALLOON3_IRQ(0));
         balloon3_irq_enabled &= ~(1 << balloon3_irq);
         __raw_writel(~balloon3_irq_enabled, BALLOON3_INT_CONTROL_REG);
 }
 
-static void balloon3_unmask_irq(unsigned int irq)
+static void balloon3_unmask_irq(struct irq_data *d)
 {
-        int balloon3_irq = (irq - BALLOON3_IRQ(0));
+        int balloon3_irq = (d->irq - BALLOON3_IRQ(0));
         balloon3_irq_enabled |= (1 << balloon3_irq);
         __raw_writel(~balloon3_irq_enabled, BALLOON3_INT_CONTROL_REG);
 }
 
 static struct irq_chip balloon3_irq_chip = {
         .name           = "FPGA",
-        .ack            = balloon3_mask_irq,
-        .mask           = balloon3_mask_irq,
-        .unmask         = balloon3_unmask_irq,
+        .irq_ack        = balloon3_mask_irq,
+        .irq_mask       = balloon3_mask_irq,
+        .irq_unmask     = balloon3_unmask_irq,
 };
 
 static void balloon3_irq_handler(unsigned int irq, struct irq_desc *desc)
@@ -504,8 +504,13 @@ static void balloon3_irq_handler(unsigned int irq, struct irq_desc *desc)
                                         balloon3_irq_enabled;
         do {
                 /* clear useless edge notification */
-                if (desc->chip->ack)
-                        desc->chip->ack(BALLOON3_AUX_NIRQ);
+                if (desc->irq_data.chip->irq_ack) {
+                        struct irq_data *d;
+
+                        d = irq_get_irq_data(BALLOON3_AUX_NIRQ);
+                        desc->irq_data.chip->irq_ack(d);
+                }
+
                 while (pending) {
                         irq = BALLOON3_IRQ(0) + __ffs(pending);
                         generic_handle_irq(irq);
diff --git a/arch/arm/mach-pxa/clock-pxa3xx.c b/arch/arm/mach-pxa/clock-pxa3xx.c
index 1b08a34ab234..3f864cd0bd28 100644
--- a/arch/arm/mach-pxa/clock-pxa3xx.c
+++ b/arch/arm/mach-pxa/clock-pxa3xx.c
@@ -115,7 +115,6 @@ static unsigned long clk_pxa3xx_smemc_getrate(struct clk *clk)
 {
         unsigned long acsr = ACSR;
         unsigned long memclkcfg = __raw_readl(MEMCLKCFG);
-        unsigned int smcfs = (acsr >> 23) & 0x7;
 
         return BASE_CLK * smcfs_mult[(acsr >> 23) & 0x7] /
                         df_clkdiv[(memclkcfg >> 16) & 0x3];
diff --git a/arch/arm/mach-pxa/cm-x2xx-pci.c b/arch/arm/mach-pxa/cm-x2xx-pci.c
index 0f3130599770..a2380cd76f80 100644
--- a/arch/arm/mach-pxa/cm-x2xx-pci.c
+++ b/arch/arm/mach-pxa/cm-x2xx-pci.c
@@ -59,7 +59,7 @@ void __init cmx2xx_pci_adjust_zones(unsigned long *zone_size,
 static void cmx2xx_it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
 {
         /* clear our parent irq */
-        desc->chip->ack(irq);
+        desc->irq_data.chip->irq_ack(&desc->irq_data);
 
         it8152_irq_demux(irq, desc);
 }
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h
index 6205dc9a2b9d..a079d8baa45a 100644
--- a/arch/arm/mach-pxa/generic.h
+++ b/arch/arm/mach-pxa/generic.h
@@ -9,11 +9,13 @@
  * published by the Free Software Foundation.
  */
 
+struct irq_data;
 struct sys_timer;
 
 extern struct sys_timer pxa_timer;
 extern void __init pxa_init_irq(int irq_nr,
-                                int (*set_wake)(unsigned int, unsigned int));
+                                int (*set_wake)(struct irq_data *,
+                                                unsigned int));
 extern void __init pxa25x_init_irq(void);
 #ifdef CONFIG_CPU_PXA26x
 extern void __init pxa26x_init_irq(void);
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index 54e91c9e71c8..2693e3c3776f 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -53,37 +53,48 @@ static inline int cpu_has_ipr(void)
         return !cpu_is_pxa25x();
 }
 
-static void pxa_mask_irq(unsigned int irq)
+static inline void __iomem *irq_base(int i)
+{
+        static unsigned long phys_base[] = {
+                0x40d00000,
+                0x40d0009c,
+                0x40d00130,
+        };
+
+        return (void __iomem *)io_p2v(phys_base[i]);
+}
+
+static void pxa_mask_irq(struct irq_data *d)
 {
-        void __iomem *base = get_irq_chip_data(irq);
+        void __iomem *base = irq_data_get_irq_chip_data(d);
         uint32_t icmr = __raw_readl(base + ICMR);
 
-        icmr &= ~(1 << IRQ_BIT(irq));
+        icmr &= ~(1 << IRQ_BIT(d->irq));
         __raw_writel(icmr, base + ICMR);
 }
 
-static void pxa_unmask_irq(unsigned int irq)
+static void pxa_unmask_irq(struct irq_data *d)
 {
-        void __iomem *base = get_irq_chip_data(irq);
+        void __iomem *base = irq_data_get_irq_chip_data(d);
         uint32_t icmr = __raw_readl(base + ICMR);
 
-        icmr |= 1 << IRQ_BIT(irq);
+        icmr |= 1 << IRQ_BIT(d->irq);
         __raw_writel(icmr, base + ICMR);
 }
 
 static struct irq_chip pxa_internal_irq_chip = {
         .name           = "SC",
-        .ack            = pxa_mask_irq,
-        .mask           = pxa_mask_irq,
-        .unmask         = pxa_unmask_irq,
+        .irq_ack        = pxa_mask_irq,
+        .irq_mask       = pxa_mask_irq,
+        .irq_unmask     = pxa_unmask_irq,
 };
 
 /*
  * GPIO IRQs for GPIO 0 and 1
  */
-static int pxa_set_low_gpio_type(unsigned int irq, unsigned int type)
+static int pxa_set_low_gpio_type(struct irq_data *d, unsigned int type)
 {
-        int gpio = irq - IRQ_GPIO0;
+        int gpio = d->irq - IRQ_GPIO0;
 
         if (__gpio_is_occupied(gpio)) {
                 pr_err("%s failed: GPIO is configured\n", __func__);
@@ -103,31 +114,17 @@ static int pxa_set_low_gpio_type(unsigned int irq, unsigned int type)
         return 0;
 }
 
-static void pxa_ack_low_gpio(unsigned int irq)
-{
-        GEDR0 = (1 << (irq - IRQ_GPIO0));
-}
-
-static void pxa_mask_low_gpio(unsigned int irq)
-{
-        struct irq_desc *desc = irq_to_desc(irq);
-
-        desc->chip->mask(irq);
-}
-
-static void pxa_unmask_low_gpio(unsigned int irq)
+static void pxa_ack_low_gpio(struct irq_data *d)
 {
-        struct irq_desc *desc = irq_to_desc(irq);
-
-        desc->chip->unmask(irq);
+        GEDR0 = (1 << (d->irq - IRQ_GPIO0));
 }
 
 static struct irq_chip pxa_low_gpio_chip = {
         .name           = "GPIO-l",
-        .ack            = pxa_ack_low_gpio,
-        .mask           = pxa_mask_low_gpio,
-        .unmask         = pxa_unmask_low_gpio,
-        .set_type       = pxa_set_low_gpio_type,
+        .irq_ack        = pxa_ack_low_gpio,
+        .irq_mask       = pxa_mask_irq,
+        .irq_unmask     = pxa_unmask_irq,
+        .irq_set_type   = pxa_set_low_gpio_type,
 };
 
 static void __init pxa_init_low_gpio_irq(set_wake_t fn)
@@ -141,22 +138,12 @@ static void __init pxa_init_low_gpio_irq(set_wake_t fn)
 
         for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
                 set_irq_chip(irq, &pxa_low_gpio_chip);
+                set_irq_chip_data(irq, irq_base(0));
                 set_irq_handler(irq, handle_edge_irq);
                 set_irq_flags(irq, IRQF_VALID);
         }
 
-        pxa_low_gpio_chip.set_wake = fn;
-}
-
-static inline void __iomem *irq_base(int i)
-{
-        static unsigned long phys_base[] = {
-                0x40d00000,
-                0x40d0009c,
-                0x40d00130,
-        };
-
-        return (void __iomem *)io_p2v(phys_base[i >> 5]);
+        pxa_low_gpio_chip.irq_set_wake = fn;
 }
 
 void __init pxa_init_irq(int irq_nr, set_wake_t fn)
@@ -168,7 +155,7 @@ void __init pxa_init_irq(int irq_nr, set_wake_t fn)
         pxa_internal_irq_nr = irq_nr;
 
         for (n = 0; n < irq_nr; n += 32) {
-                void __iomem *base = irq_base(n);
+                void __iomem *base = irq_base(n >> 5);
 
                 __raw_writel(0, base + ICMR);   /* disable all IRQs */
                 __raw_writel(0, base + ICLR);   /* all IRQs are IRQ, not FIQ */
@@ -188,7 +175,7 @@ void __init pxa_init_irq(int irq_nr, set_wake_t fn)
         /* only unmasked interrupts kick us out of idle */
         __raw_writel(1, irq_base(0) + ICCR);
 
-        pxa_internal_irq_chip.set_wake = fn;
+        pxa_internal_irq_chip.irq_set_wake = fn;
         pxa_init_low_gpio_irq(fn);
 }
 
@@ -200,7 +187,7 @@ static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state)
 {
         int i;
 
-        for (i = 0; i < pxa_internal_irq_nr; i += 32) {
+        for (i = 0; i < pxa_internal_irq_nr / 32; i++) {
                 void __iomem *base = irq_base(i);
 
                 saved_icmr[i] = __raw_readl(base + ICMR);
@@ -219,14 +206,14 @@ static int pxa_irq_resume(struct sys_device *dev)
 {
         int i;
 
-        for (i = 0; i < pxa_internal_irq_nr; i += 32) {
+        for (i = 0; i < pxa_internal_irq_nr / 32; i++) {
                 void __iomem *base = irq_base(i);
 
                 __raw_writel(saved_icmr[i], base + ICMR);
                 __raw_writel(0, base + ICLR);
         }
 
-        if (!cpu_is_pxa25x())
+        if (cpu_has_ipr())
                 for (i = 0; i < pxa_internal_irq_nr; i++)
                         __raw_writel(saved_ipr[i], IRQ_BASE + IPR(i));
 
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index 8ab62a677807..c9a3e775c2de 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -95,9 +95,9 @@ static unsigned long lpd270_pin_config[] __initdata = {
 
 static unsigned int lpd270_irq_enabled;
 
-static void lpd270_mask_irq(unsigned int irq)
+static void lpd270_mask_irq(struct irq_data *d)
 {
-        int lpd270_irq = irq - LPD270_IRQ(0);
+        int lpd270_irq = d->irq - LPD270_IRQ(0);
 
         __raw_writew(~(1 << lpd270_irq), LPD270_INT_STATUS);
 
@@ -105,9 +105,9 @@ static void lpd270_mask_irq(unsigned int irq)
         __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
 }
 
-static void lpd270_unmask_irq(unsigned int irq)
+static void lpd270_unmask_irq(struct irq_data *d)
 {
-        int lpd270_irq = irq - LPD270_IRQ(0);
+        int lpd270_irq = d->irq - LPD270_IRQ(0);
 
         lpd270_irq_enabled |= 1 << lpd270_irq;
         __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
@@ -115,9 +115,9 @@ static void lpd270_unmask_irq(unsigned int irq)
 
 static struct irq_chip lpd270_irq_chip = {
         .name           = "CPLD",
-        .ack            = lpd270_mask_irq,
-        .mask           = lpd270_mask_irq,
-        .unmask         = lpd270_unmask_irq,
+        .irq_ack        = lpd270_mask_irq,
+        .irq_mask       = lpd270_mask_irq,
+        .irq_unmask     = lpd270_unmask_irq,
 };
 
 static void lpd270_irq_handler(unsigned int irq, struct irq_desc *desc)
@@ -126,7 +126,8 @@ static void lpd270_irq_handler(unsigned int irq, struct irq_desc *desc)
 
         pending = __raw_readw(LPD270_INT_STATUS) & lpd270_irq_enabled;
         do {
-                desc->chip->ack(irq);   /* clear useless edge notification */
+                /* clear useless edge notification */
+                desc->irq_data.chip->irq_ack(&desc->irq_data);
                 if (likely(pending)) {
                         irq = LPD270_IRQ(0) + __ffs(pending);
                         generic_handle_irq(irq);
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index 3072dbea5c1f..dca20de306bb 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -122,15 +122,15 @@ EXPORT_SYMBOL(lubbock_set_misc_wr);
 
 static unsigned long lubbock_irq_enabled;
 
-static void lubbock_mask_irq(unsigned int irq)
+static void lubbock_mask_irq(struct irq_data *d)
 {
-        int lubbock_irq = (irq - LUBBOCK_IRQ(0));
+        int lubbock_irq = (d->irq - LUBBOCK_IRQ(0));
         LUB_IRQ_MASK_EN = (lubbock_irq_enabled &= ~(1 << lubbock_irq));
 }
 
-static void lubbock_unmask_irq(unsigned int irq)
+static void lubbock_unmask_irq(struct irq_data *d)
 {
-        int lubbock_irq = (irq - LUBBOCK_IRQ(0));
+        int lubbock_irq = (d->irq - LUBBOCK_IRQ(0));
         /* the irq can be acknowledged only if deasserted, so it's done here */
         LUB_IRQ_SET_CLR &= ~(1 << lubbock_irq);
         LUB_IRQ_MASK_EN = (lubbock_irq_enabled |= (1 << lubbock_irq));
@@ -138,16 +138,17 @@ static void lubbock_unmask_irq(unsigned int irq)
 
 static struct irq_chip lubbock_irq_chip = {
         .name           = "FPGA",
-        .ack            = lubbock_mask_irq,
-        .mask           = lubbock_mask_irq,
-        .unmask         = lubbock_unmask_irq,
+        .irq_ack        = lubbock_mask_irq,
+        .irq_mask       = lubbock_mask_irq,
+        .irq_unmask     = lubbock_unmask_irq,
 };
 
 static void lubbock_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
         unsigned long pending = LUB_IRQ_SET_CLR & lubbock_irq_enabled;
         do {
-                desc->chip->ack(irq);   /* clear our parent irq */
+                /* clear our parent irq */
+                desc->irq_data.chip->irq_ack(&desc->irq_data);
                 if (likely(pending)) {
                         irq = LUBBOCK_IRQ(0) + __ffs(pending);
                         generic_handle_irq(irq);
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 740c03590e3b..d4b6f2375f2c 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -123,15 +123,15 @@ static unsigned long mainstone_pin_config[] = {
 
 static unsigned long mainstone_irq_enabled;
 
-static void mainstone_mask_irq(unsigned int irq)
+static void mainstone_mask_irq(struct irq_data *d)
 {
-        int mainstone_irq = (irq - MAINSTONE_IRQ(0));
+        int mainstone_irq = (d->irq - MAINSTONE_IRQ(0));
         MST_INTMSKENA = (mainstone_irq_enabled &= ~(1 << mainstone_irq));
 }
 
-static void mainstone_unmask_irq(unsigned int irq)
+static void mainstone_unmask_irq(struct irq_data *d)
 {
-        int mainstone_irq = (irq - MAINSTONE_IRQ(0));
+        int mainstone_irq = (d->irq - MAINSTONE_IRQ(0));
         /* the irq can be acknowledged only if deasserted, so it's done here */
         MST_INTSETCLR &= ~(1 << mainstone_irq);
         MST_INTMSKENA = (mainstone_irq_enabled |= (1 << mainstone_irq));
@@ -139,16 +139,17 @@ static void mainstone_unmask_irq(unsigned int irq)
 
 static struct irq_chip mainstone_irq_chip = {
         .name           = "FPGA",
-        .ack            = mainstone_mask_irq,
-        .mask           = mainstone_mask_irq,
-        .unmask         = mainstone_unmask_irq,
+        .irq_ack        = mainstone_mask_irq,
+        .irq_mask       = mainstone_mask_irq,
+        .irq_unmask     = mainstone_unmask_irq,
 };
 
 static void mainstone_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
         unsigned long pending = MST_INTSETCLR & mainstone_irq_enabled;
         do {
-                desc->chip->ack(irq);   /* clear useless edge notification */
+                /* clear useless edge notification */
+                desc->irq_data.chip->irq_ack(&desc->irq_data);
                 if (likely(pending)) {
                         irq = MAINSTONE_IRQ(0) + __ffs(pending);
                         generic_handle_irq(irq);
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c
index f33647a8e0b7..90820faa711a 100644
--- a/arch/arm/mach-pxa/pcm990-baseboard.c
+++ b/arch/arm/mach-pxa/pcm990-baseboard.c
@@ -241,23 +241,23 @@ static struct platform_device pcm990_backlight_device = {
 
 static unsigned long pcm990_irq_enabled;
 
-static void pcm990_mask_ack_irq(unsigned int irq)
+static void pcm990_mask_ack_irq(struct irq_data *d)
 {
-        int pcm990_irq = (irq - PCM027_IRQ(0));
+        int pcm990_irq = (d->irq - PCM027_IRQ(0));
         PCM990_INTMSKENA = (pcm990_irq_enabled &= ~(1 << pcm990_irq));
 }
 
-static void pcm990_unmask_irq(unsigned int irq)
+static void pcm990_unmask_irq(struct irq_data *d)
 {
-        int pcm990_irq = (irq - PCM027_IRQ(0));
+        int pcm990_irq = (d->irq - PCM027_IRQ(0));
         /* the irq can be acknowledged only if deasserted, so it's done here */
         PCM990_INTSETCLR |= 1 << pcm990_irq;
         PCM990_INTMSKENA  = (pcm990_irq_enabled |= (1 << pcm990_irq));
 }
 
 static struct irq_chip pcm990_irq_chip = {
-        .mask_ack       = pcm990_mask_ack_irq,
-        .unmask         = pcm990_unmask_irq,
+        .irq_mask_ack   = pcm990_mask_ack_irq,
+        .irq_unmask     = pcm990_unmask_irq,
 };
 
 static void pcm990_irq_handler(unsigned int irq, struct irq_desc *desc)
@@ -265,7 +265,8 @@ static void pcm990_irq_handler(unsigned int irq, struct irq_desc *desc)
         unsigned long pending = (~PCM990_INTSETCLR) & pcm990_irq_enabled;
 
         do {
-                desc->chip->ack(irq);   /* clear our parent IRQ */
+                /* clear our parent IRQ */
+                desc->irq_data.chip->irq_ack(&desc->irq_data);
                 if (likely(pending)) {
                         irq = PCM027_IRQ(0) + __ffs(pending);
                         generic_handle_irq(irq);
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index 3f5241c84894..fbc5b775f895 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -22,6 +22,7 @@
 #include <linux/platform_device.h>
 #include <linux/suspend.h>
 #include <linux/sysdev.h>
+#include <linux/irq.h>
 
 #include <asm/mach/map.h>
 #include <mach/hardware.h>
@@ -282,15 +283,15 @@ static inline void pxa25x_init_pm(void) {}
 /* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm
  */
 
-static int pxa25x_set_wake(unsigned int irq, unsigned int on)
+static int pxa25x_set_wake(struct irq_data *d, unsigned int on)
 {
-        int gpio = IRQ_TO_GPIO(irq);
+        int gpio = IRQ_TO_GPIO(d->irq);
         uint32_t mask = 0;
 
         if (gpio >= 0 && gpio < 85)
                 return gpio_set_wake(gpio, on);
 
-        if (irq == IRQ_RTCAlrm) {
+        if (d->irq == IRQ_RTCAlrm) {
                 mask = PWER_RTC;
                 goto set_pwer;
         }
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index b2130b7a7b52..987301ff4c33 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -18,6 +18,7 @@
 #include <linux/platform_device.h>
 #include <linux/sysdev.h>
 #include <linux/io.h>
+#include <linux/irq.h>
 
 #include <asm/mach/map.h>
 #include <mach/hardware.h>
@@ -343,18 +344,18 @@ static inline void pxa27x_init_pm(void) {}
 /* PXA27x:  Various gpios can issue wakeup events.  This logic only
  * handles the simple cases, not the WEMUX2 and WEMUX3 options
  */
-static int pxa27x_set_wake(unsigned int irq, unsigned int on)
+static int pxa27x_set_wake(struct irq_data *d, unsigned int on)
 {
-        int gpio = IRQ_TO_GPIO(irq);
+        int gpio = IRQ_TO_GPIO(d->irq);
         uint32_t mask;
 
         if (gpio >= 0 && gpio < 128)
                 return gpio_set_wake(gpio, on);
 
-        if (irq == IRQ_KEYPAD)
+        if (d->irq == IRQ_KEYPAD)
                 return keypad_set_wake(on);
 
-        switch (irq) {
+        switch (d->irq) {
         case IRQ_RTCAlrm:
                 mask = PWER_RTC;
                 break;
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index e14818f5d950..a7a19e1cd640 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -229,11 +229,11 @@ static void __init pxa3xx_init_pm(void)
         pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
 }
 
-static int pxa3xx_set_wake(unsigned int irq, unsigned int on)
+static int pxa3xx_set_wake(struct irq_data *d, unsigned int on)
 {
         unsigned long flags, mask = 0;
 
-        switch (irq) {
+        switch (d->irq) {
         case IRQ_SSP3:
                 mask = ADXER_MFP_WSSP3;
                 break;
@@ -322,40 +322,40 @@ static inline void pxa3xx_init_pm(void) {}
 #define pxa3xx_set_wake NULL
 #endif
 
-static void pxa_ack_ext_wakeup(unsigned int irq)
+static void pxa_ack_ext_wakeup(struct irq_data *d)
 {
-        PECR |= PECR_IS(irq - IRQ_WAKEUP0);
+        PECR |= PECR_IS(d->irq - IRQ_WAKEUP0);
 }
 
-static void pxa_mask_ext_wakeup(unsigned int irq)
+static void pxa_mask_ext_wakeup(struct irq_data *d)
 {
-        ICMR2 &= ~(1 << ((irq - PXA_IRQ(0)) & 0x1f));
-        PECR &= ~PECR_IE(irq - IRQ_WAKEUP0);
+        ICMR2 &= ~(1 << ((d->irq - PXA_IRQ(0)) & 0x1f));
+        PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0);
 }
 
-static void pxa_unmask_ext_wakeup(unsigned int irq)
+static void pxa_unmask_ext_wakeup(struct irq_data *d)
 {
-        ICMR2 |= 1 << ((irq - PXA_IRQ(0)) & 0x1f);
-        PECR |= PECR_IE(irq - IRQ_WAKEUP0);
+        ICMR2 |= 1 << ((d->irq - PXA_IRQ(0)) & 0x1f);
+        PECR |= PECR_IE(d->irq - IRQ_WAKEUP0);
 }
 
-static int pxa_set_ext_wakeup_type(unsigned int irq, unsigned int flow_type)
+static int pxa_set_ext_wakeup_type(struct irq_data *d, unsigned int flow_type)
 {
         if (flow_type & IRQ_TYPE_EDGE_RISING)
-                PWER |= 1 << (irq - IRQ_WAKEUP0);
+                PWER |= 1 << (d->irq - IRQ_WAKEUP0);
 
         if (flow_type & IRQ_TYPE_EDGE_FALLING)
-                PWER |= 1 << (irq - IRQ_WAKEUP0 + 2);
+                PWER |= 1 << (d->irq - IRQ_WAKEUP0 + 2);
 
         return 0;
 }
 
 static struct irq_chip pxa_ext_wakeup_chip = {
         .name           = "WAKEUP",
-        .ack            = pxa_ack_ext_wakeup,
-        .mask           = pxa_mask_ext_wakeup,
-        .unmask         = pxa_unmask_ext_wakeup,
-        .set_type       = pxa_set_ext_wakeup_type,
+        .irq_ack        = pxa_ack_ext_wakeup,
+        .irq_mask       = pxa_mask_ext_wakeup,
+        .irq_unmask     = pxa_unmask_ext_wakeup,
+        .irq_set_type   = pxa_set_ext_wakeup_type,
 };
 
 static void __init pxa_init_ext_wakeup_irq(set_wake_t fn)
@@ -368,7 +368,7 @@ static void __init pxa_init_ext_wakeup_irq(set_wake_t fn)
                 set_irq_flags(irq, IRQF_VALID);
         }
 
-        pxa_ext_wakeup_chip.set_wake = fn;
+        pxa_ext_wakeup_chip.irq_set_wake = fn;
 }
 
 void __init pxa3xx_init_irq(void)
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 0bc938729c4c..b49a2c21124c 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -25,6 +25,7 @@
 #include <linux/spi/corgi_lcd.h>
 #include <linux/spi/pxa2xx_spi.h>
 #include <linux/mtd/sharpsl.h>
+#include <linux/mtd/physmap.h>
 #include <linux/input/matrix_keypad.h>
 #include <linux/regulator/machine.h>
 #include <linux/io.h>
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
index de69b203afa7..49eeeab23689 100644
--- a/arch/arm/mach-pxa/viper.c
+++ b/arch/arm/mach-pxa/viper.c
@@ -249,9 +249,9 @@ static inline int viper_bit_to_irq(int bit)
         return viper_isa_irqs[bit] + PXA_ISA_IRQ(0);
 }
 
-static void viper_ack_irq(unsigned int irq)
+static void viper_ack_irq(struct irq_data *d)
 {
-        int viper_irq = viper_irq_to_bitmask(irq);
+        int viper_irq = viper_irq_to_bitmask(d->irq);
 
         if (viper_irq & 0xff)
                 VIPER_LO_IRQ_STATUS = viper_irq;
@@ -259,14 +259,14 @@ static void viper_ack_irq(unsigned int irq)
                 VIPER_HI_IRQ_STATUS = (viper_irq >> 8);
 }
 
-static void viper_mask_irq(unsigned int irq)
+static void viper_mask_irq(struct irq_data *d)
 {
-        viper_irq_enabled_mask &= ~(viper_irq_to_bitmask(irq));
+        viper_irq_enabled_mask &= ~(viper_irq_to_bitmask(d->irq));
 }
 
-static void viper_unmask_irq(unsigned int irq)
+static void viper_unmask_irq(struct irq_data *d)
 {
-        viper_irq_enabled_mask |= viper_irq_to_bitmask(irq);
+        viper_irq_enabled_mask |= viper_irq_to_bitmask(d->irq);
 }
 
 static inline unsigned long viper_irq_pending(void)
@@ -283,7 +283,7 @@ static void viper_irq_handler(unsigned int irq, struct irq_desc *desc)
         do {
                 /* we're in a chained irq handler,
                  * so ack the interrupt by hand */
-                desc->chip->ack(irq);
+                desc->irq_data.chip->irq_ack(&desc->irq_data);
 
                 if (likely(pending)) {
                         irq = viper_bit_to_irq(__ffs(pending));
@@ -294,10 +294,10 @@ static void viper_irq_handler(unsigned int irq, struct irq_desc *desc)
 }
 
 static struct irq_chip viper_irq_chip = {
-        .name   = "ISA",
-        .ack    = viper_ack_irq,
-        .mask   = viper_mask_irq,
-        .unmask = viper_unmask_irq
+        .name           = "ISA",
+        .irq_ack        = viper_ack_irq,
+        .irq_mask       = viper_mask_irq,
+        .irq_unmask     = viper_unmask_irq
 };
 
 static void __init viper_init_irq(void)
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c
index bf034c7670dd..f4b053b35815 100644
--- a/arch/arm/mach-pxa/zeus.c
+++ b/arch/arm/mach-pxa/zeus.c
@@ -83,19 +83,19 @@ static inline int zeus_bit_to_irq(int bit)
         return zeus_isa_irqs[bit] + PXA_ISA_IRQ(0);
 }
 
-static void zeus_ack_irq(unsigned int irq)
+static void zeus_ack_irq(struct irq_data *d)
 {
-        __raw_writew(zeus_irq_to_bitmask(irq), ZEUS_CPLD_ISA_IRQ);
+        __raw_writew(zeus_irq_to_bitmask(d->irq), ZEUS_CPLD_ISA_IRQ);
 }
 
-static void zeus_mask_irq(unsigned int irq)
+static void zeus_mask_irq(struct irq_data *d)
 {
-        zeus_irq_enabled_mask &= ~(zeus_irq_to_bitmask(irq));
+        zeus_irq_enabled_mask &= ~(zeus_irq_to_bitmask(d->irq));
 }
 
-static void zeus_unmask_irq(unsigned int irq)
+static void zeus_unmask_irq(struct irq_data *d)
 {
-        zeus_irq_enabled_mask |= zeus_irq_to_bitmask(irq);
+        zeus_irq_enabled_mask |= zeus_irq_to_bitmask(d->irq);
 }
 
 static inline unsigned long zeus_irq_pending(void)
@@ -111,7 +111,7 @@ static void zeus_irq_handler(unsigned int irq, struct irq_desc *desc)
         do {
                 /* we're in a chained irq handler,
                  * so ack the interrupt by hand */
-                desc->chip->ack(gpio_to_irq(ZEUS_ISA_GPIO));
+                desc->irq_data.chip->irq_ack(&desc->irq_data);
 
                 if (likely(pending)) {
                         irq = zeus_bit_to_irq(__ffs(pending));
@@ -122,10 +122,10 @@ static void zeus_irq_handler(unsigned int irq, struct irq_desc *desc)
 }
 
 static struct irq_chip zeus_irq_chip = {
-        .name   = "ISA",
-        .ack    = zeus_ack_irq,
-        .mask   = zeus_mask_irq,
-        .unmask = zeus_unmask_irq,
+        .name           = "ISA",
+        .irq_ack        = zeus_ack_irq,
+        .irq_mask       = zeus_mask_irq,
+        .irq_unmask     = zeus_unmask_irq,
 };
 
 static void __init zeus_init_irq(void)
@@ -830,8 +830,8 @@ static void __init zeus_init(void)
         pr_info("Zeus CPLD V%dI%d\n", (system_rev & 0xf0) >> 4, (system_rev & 0x0f));
 
         /* Fix timings for dm9000s (CS1/CS2)*/
-        msc0 = __raw_readl(MSC0) & 0x0000ffff | (dm9000_msc << 16);
-        msc1 = __raw_readl(MSC1) & 0xffff0000 | dm9000_msc;
+        msc0 = (__raw_readl(MSC0) & 0x0000ffff) | (dm9000_msc << 16);
+        msc1 = (__raw_readl(MSC1) & 0xffff0000) | dm9000_msc;
         __raw_writel(msc0, MSC0);
         __raw_writel(msc1, MSC1);
 
diff --git a/arch/arm/mach-rpc/irq.c b/arch/arm/mach-rpc/irq.c
index 9dd15d679c5d..d29cd9b737fc 100644
--- a/arch/arm/mach-rpc/irq.c
+++ b/arch/arm/mach-rpc/irq.c
@@ -6,110 +6,110 @@
 #include <asm/hardware/iomd.h>
 #include <asm/irq.h>
 
-static void iomd_ack_irq_a(unsigned int irq)
+static void iomd_ack_irq_a(struct irq_data *d)
 {
         unsigned int val, mask;
 
-        mask = 1 << irq;
+        mask = 1 << d->irq;
         val = iomd_readb(IOMD_IRQMASKA);
         iomd_writeb(val & ~mask, IOMD_IRQMASKA);
         iomd_writeb(mask, IOMD_IRQCLRA);
 }
 
-static void iomd_mask_irq_a(unsigned int irq)
+static void iomd_mask_irq_a(struct irq_data *d)
 {
         unsigned int val, mask;
 
-        mask = 1 << irq;
+        mask = 1 << d->irq;
         val = iomd_readb(IOMD_IRQMASKA);
         iomd_writeb(val & ~mask, IOMD_IRQMASKA);
 }
 
-static void iomd_unmask_irq_a(unsigned int irq)
+static void iomd_unmask_irq_a(struct irq_data *d)
 {
         unsigned int val, mask;
 
-        mask = 1 << irq;
+        mask = 1 << d->irq;
         val = iomd_readb(IOMD_IRQMASKA);
         iomd_writeb(val | mask, IOMD_IRQMASKA);
 }
 
 static struct irq_chip iomd_a_chip = {
-        .ack    = iomd_ack_irq_a,
-        .mask   = iomd_mask_irq_a,
-        .unmask = iomd_unmask_irq_a,
+        .irq_ack        = iomd_ack_irq_a,
+        .irq_mask       = iomd_mask_irq_a,
+        .irq_unmask     = iomd_unmask_irq_a,
 };
 
-static void iomd_mask_irq_b(unsigned int irq)
+static void iomd_mask_irq_b(struct irq_data *d)
 {
         unsigned int val, mask;
 
-        mask = 1 << (irq & 7);
+        mask = 1 << (d->irq & 7);
         val = iomd_readb(IOMD_IRQMASKB);
         iomd_writeb(val & ~mask, IOMD_IRQMASKB);
 }
 
-static void iomd_unmask_irq_b(unsigned int irq)
+static void iomd_unmask_irq_b(struct irq_data *d)
 {
         unsigned int val, mask;
 
-        mask = 1 << (irq & 7);
+        mask = 1 << (d->irq & 7);
         val = iomd_readb(IOMD_IRQMASKB);
         iomd_writeb(val | mask, IOMD_IRQMASKB);
 }
 
 static struct irq_chip iomd_b_chip = {
-        .ack    = iomd_mask_irq_b,
-        .mask   = iomd_mask_irq_b,
-        .unmask = iomd_unmask_irq_b,
+        .irq_ack        = iomd_mask_irq_b,
+        .irq_mask       = iomd_mask_irq_b,
+        .irq_unmask     = iomd_unmask_irq_b,
 };
 
-static void iomd_mask_irq_dma(unsigned int irq)
+static void iomd_mask_irq_dma(struct irq_data *d)
 {
         unsigned int val, mask;
 
-        mask = 1 << (irq & 7);
+        mask = 1 << (d->irq & 7);
         val = iomd_readb(IOMD_DMAMASK);
         iomd_writeb(val & ~mask, IOMD_DMAMASK);
 }
 
-static void iomd_unmask_irq_dma(unsigned int irq)
+static void iomd_unmask_irq_dma(struct irq_data *d)
 {
         unsigned int val, mask;
 
-        mask = 1 << (irq & 7);
+        mask = 1 << (d->irq & 7);
         val = iomd_readb(IOMD_DMAMASK);
         iomd_writeb(val | mask, IOMD_DMAMASK);
 }
 
 static struct irq_chip iomd_dma_chip = {
-        .ack    = iomd_mask_irq_dma,
-        .mask   = iomd_mask_irq_dma,
-        .unmask = iomd_unmask_irq_dma,
+        .irq_ack        = iomd_mask_irq_dma,
+        .irq_mask       = iomd_mask_irq_dma,
+        .irq_unmask     = iomd_unmask_irq_dma,
 };
 
-static void iomd_mask_irq_fiq(unsigned int irq)
+static void iomd_mask_irq_fiq(struct irq_data *d)
 {
         unsigned int val, mask;
 
-        mask = 1 << (irq & 7);
+        mask = 1 << (d->irq & 7);
         val = iomd_readb(IOMD_FIQMASK);
         iomd_writeb(val & ~mask, IOMD_FIQMASK);
 }
 
-static void iomd_unmask_irq_fiq(unsigned int irq)
+static void iomd_unmask_irq_fiq(struct irq_data *d)
 {
         unsigned int val, mask;
 
-        mask = 1 << (irq & 7);
+        mask = 1 << (d->irq & 7);
         val = iomd_readb(IOMD_FIQMASK);
         iomd_writeb(val | mask, IOMD_FIQMASK);
 }
 
 static struct irq_chip iomd_fiq_chip = {
-        .ack    = iomd_mask_irq_fiq,
-        .mask   = iomd_mask_irq_fiq,
-        .unmask = iomd_unmask_irq_fiq,
+        .irq_ack        = iomd_mask_irq_fiq,
+        .irq_mask       = iomd_mask_irq_fiq,
+        .irq_unmask     = iomd_unmask_irq_fiq,
 };
 
 void __init rpc_init_irq(void)
diff --git a/arch/arm/mach-s3c2410/bast-irq.c b/arch/arm/mach-s3c2410/bast-irq.c
index 217b102866d0..606cb6b1cc47 100644
--- a/arch/arm/mach-s3c2410/bast-irq.c
+++ b/arch/arm/mach-s3c2410/bast-irq.c
@@ -75,38 +75,38 @@ static unsigned char bast_pc104_irqmasks[] = {
 static unsigned char bast_pc104_irqs[] = { 3, 5, 7, 10 };
 
 static void
-bast_pc104_mask(unsigned int irqno)
+bast_pc104_mask(struct irq_data *data)
 {
         unsigned long temp;
 
         temp = __raw_readb(BAST_VA_PC104_IRQMASK);
-        temp &= ~bast_pc104_irqmasks[irqno];
+        temp &= ~bast_pc104_irqmasks[data->irq];
         __raw_writeb(temp, BAST_VA_PC104_IRQMASK);
 }
 
 static void
-bast_pc104_maskack(unsigned int irqno)
+bast_pc104_maskack(struct irq_data *data)
 {
         struct irq_desc *desc = irq_desc + IRQ_ISA;
 
-        bast_pc104_mask(irqno);
-        desc->chip->ack(IRQ_ISA);
+        bast_pc104_mask(data);
+        desc->irq_data.chip->irq_ack(&desc->irq_data);
 }
 
 static void
-bast_pc104_unmask(unsigned int irqno)
+bast_pc104_unmask(struct irq_data *data)
 {
         unsigned long temp;
 
         temp = __raw_readb(BAST_VA_PC104_IRQMASK);
-        temp |= bast_pc104_irqmasks[irqno];
+        temp |= bast_pc104_irqmasks[data->irq];
         __raw_writeb(temp, BAST_VA_PC104_IRQMASK);
 }
 
 static struct irq_chip  bast_pc104_chip = {
-        .mask        = bast_pc104_mask,
-        .unmask      = bast_pc104_unmask,
-        .ack         = bast_pc104_maskack
+        .irq_mask       = bast_pc104_mask,
+        .irq_unmask     = bast_pc104_unmask,
+        .irq_ack        = bast_pc104_maskack
 };
 
 static void
@@ -123,7 +123,7 @@ bast_irq_pc104_demux(unsigned int irq,
                 /* ack if we get an irq with nothing (ie, startup) */
 
                 desc = irq_desc + IRQ_ISA;
-                desc->chip->ack(IRQ_ISA);
+                desc->irq_data.chip->irq_ack(&desc->irq_data);
         } else {
                 /* handle the IRQ */
 
diff --git a/arch/arm/mach-s3c2410/include/mach/irqs.h b/arch/arm/mach-s3c2410/include/mach/irqs.h
index 11bb0f08fe6a..e5a68ea13113 100644
--- a/arch/arm/mach-s3c2410/include/mach/irqs.h
+++ b/arch/arm/mach-s3c2410/include/mach/irqs.h
@@ -152,8 +152,8 @@
 
 #define IRQ_S3C2416_HSMMC0      S3C2410_IRQ(21)         /* S3C2416/S3C2450 */
 
-#define IRQ_HSMMC0              IRQ_S3C2443_HSMMC
-#define IRQ_HSMMC1              IRQ_S3C2416_HSMMC0
+#define IRQ_HSMMC0              IRQ_S3C2416_HSMMC0
+#define IRQ_HSMMC1              IRQ_S3C2443_HSMMC
 
 #define IRQ_S3C2443_LCD1        S3C2410_IRQSUB(14)
 #define IRQ_S3C2443_LCD2        S3C2410_IRQSUB(15)
diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h
index cd3983ad4160..25bbf5a942dd 100644
--- a/arch/arm/mach-s3c2410/include/mach/map.h
+++ b/arch/arm/mach-s3c2410/include/mach/map.h
@@ -112,8 +112,8 @@
 #define S3C_PA_IIC          S3C2410_PA_IIC
 #define S3C_PA_UART         S3C24XX_PA_UART
 #define S3C_PA_USBHOST  S3C2410_PA_USBHOST
-#define S3C_PA_HSMMC0       S3C2443_PA_HSMMC
-#define S3C_PA_HSMMC1       S3C2416_PA_HSMMC0
+#define S3C_PA_HSMMC0       S3C2416_PA_HSMMC0
+#define S3C_PA_HSMMC1       S3C2443_PA_HSMMC
 #define S3C_PA_WDT          S3C2410_PA_WATCHDOG
 #define S3C_PA_NAND         S3C24XX_PA_NAND
 
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
index 101aeea22310..44494a56e68b 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
@@ -86,6 +86,7 @@
 #define S3C2443_HCLKCON_LCDC            (1<<9)
 #define S3C2443_HCLKCON_USBH            (1<<11)
 #define S3C2443_HCLKCON_USBD            (1<<12)
+#define S3C2416_HCLKCON_HSMMC0          (1<<15)
 #define S3C2443_HCLKCON_HSMMC           (1<<16)
 #define S3C2443_HCLKCON_CFC             (1<<17)
 #define S3C2443_HCLKCON_SSMC            (1<<18)
diff --git a/arch/arm/mach-s3c2412/irq.c b/arch/arm/mach-s3c2412/irq.c
index 6000ca9d1815..eddb52ba5b65 100644
--- a/arch/arm/mach-s3c2412/irq.c
+++ b/arch/arm/mach-s3c2412/irq.c
@@ -49,9 +49,9 @@
 */
 
 static void
-s3c2412_irq_mask(unsigned int irqno)
+s3c2412_irq_mask(struct irq_data *data)
 {
-        unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
+        unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
         unsigned long mask;
 
         mask = __raw_readl(S3C2410_INTMSK);
@@ -62,9 +62,9 @@ s3c2412_irq_mask(unsigned int irqno)
 }
 
 static inline void
-s3c2412_irq_ack(unsigned int irqno)
+s3c2412_irq_ack(struct irq_data *data)
 {
-        unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
+        unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
 
         __raw_writel(bitval, S3C2412_EINTPEND);
         __raw_writel(bitval, S3C2410_SRCPND);
@@ -72,9 +72,9 @@ s3c2412_irq_ack(unsigned int irqno)
 }
 
 static inline void
-s3c2412_irq_maskack(unsigned int irqno)
+s3c2412_irq_maskack(struct irq_data *data)
 {
-        unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
+        unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
         unsigned long mask;
 
         mask = __raw_readl(S3C2410_INTMSK);
@@ -89,9 +89,9 @@ s3c2412_irq_maskack(unsigned int irqno)
 }
 
 static void
-s3c2412_irq_unmask(unsigned int irqno)
+s3c2412_irq_unmask(struct irq_data *data)
 {
-        unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
+        unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
         unsigned long mask;
 
         mask = __raw_readl(S3C2412_EINTMASK);
@@ -102,11 +102,11 @@ s3c2412_irq_unmask(unsigned int irqno)
 }
 
 static struct irq_chip s3c2412_irq_eint0t4 = {
-        .ack       = s3c2412_irq_ack,
-        .mask      = s3c2412_irq_mask,
-        .unmask    = s3c2412_irq_unmask,
-        .set_wake  = s3c_irq_wake,
-        .set_type  = s3c_irqext_type,
+        .irq_ack        = s3c2412_irq_ack,
+        .irq_mask       = s3c2412_irq_mask,
+        .irq_unmask     = s3c2412_irq_unmask,
+        .irq_set_wake   = s3c_irq_wake,
+        .irq_set_type   = s3c_irqext_type,
 };
 
 #define INTBIT(x)       (1 << ((x) - S3C2410_IRQSUB(0)))
@@ -132,29 +132,29 @@ static void s3c2412_irq_demux_cfsdi(unsigned int irq, struct irq_desc *desc)
 #define INTMSK_CFSDI    (1UL << (IRQ_S3C2412_CFSDI - IRQ_EINT0))
 #define SUBMSK_CFSDI    INTMSK_SUB(IRQ_S3C2412_SDI, IRQ_S3C2412_CF)
 
-static void s3c2412_irq_cfsdi_mask(unsigned int irqno)
+static void s3c2412_irq_cfsdi_mask(struct irq_data *data)
 {
-        s3c_irqsub_mask(irqno, INTMSK_CFSDI, SUBMSK_CFSDI);
+        s3c_irqsub_mask(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI);
 }
 
-static void s3c2412_irq_cfsdi_unmask(unsigned int irqno)
+static void s3c2412_irq_cfsdi_unmask(struct irq_data *data)
 {
-        s3c_irqsub_unmask(irqno, INTMSK_CFSDI);
+        s3c_irqsub_unmask(data->irq, INTMSK_CFSDI);
 }
 
-static void s3c2412_irq_cfsdi_ack(unsigned int irqno)
+static void s3c2412_irq_cfsdi_ack(struct irq_data *data)
 {
-        s3c_irqsub_maskack(irqno, INTMSK_CFSDI, SUBMSK_CFSDI);
+        s3c_irqsub_maskack(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI);
 }
 
 static struct irq_chip s3c2412_irq_cfsdi = {
         .name           = "s3c2412-cfsdi",
-        .ack            = s3c2412_irq_cfsdi_ack,
-        .mask           = s3c2412_irq_cfsdi_mask,
-        .unmask         = s3c2412_irq_cfsdi_unmask,
+        .irq_ack        = s3c2412_irq_cfsdi_ack,
+        .irq_mask       = s3c2412_irq_cfsdi_mask,
+        .irq_unmask     = s3c2412_irq_cfsdi_unmask,
 };
 
-static int s3c2412_irq_rtc_wake(unsigned int irqno, unsigned int state)
+static int s3c2412_irq_rtc_wake(struct irq_data *data, unsigned int state)
 {
         unsigned long pwrcfg;
 
@@ -165,7 +165,7 @@ static int s3c2412_irq_rtc_wake(unsigned int irqno, unsigned int state)
                 pwrcfg |= S3C2412_PWRCFG_RTC_MASKIRQ;
         __raw_writel(pwrcfg, S3C2412_PWRCFG);
 
-        return s3c_irq_chip.set_wake(irqno, state);
+        return s3c_irq_chip.irq_set_wake(data, state);
 }
 
 static struct irq_chip s3c2412_irq_rtc_chip;
@@ -193,7 +193,7 @@ static int s3c2412_irq_add(struct sys_device *sysdev)
         /* change RTC IRQ's set wake method */
 
         s3c2412_irq_rtc_chip = s3c_irq_chip;
-        s3c2412_irq_rtc_chip.set_wake = s3c2412_irq_rtc_wake;
+        s3c2412_irq_rtc_chip.irq_set_wake = s3c2412_irq_rtc_wake;
 
         set_irq_chip(IRQ_RTC, &s3c2412_irq_rtc_chip);
 
diff --git a/arch/arm/mach-s3c2416/Kconfig b/arch/arm/mach-s3c2416/Kconfig
index df8d14974c90..69b48a7d1dbd 100644
--- a/arch/arm/mach-s3c2416/Kconfig
+++ b/arch/arm/mach-s3c2416/Kconfig
@@ -31,6 +31,17 @@ config S3C2416_PM
         help
           Internal config node to apply S3C2416 power management
 
+config S3C2416_SETUP_SDHCI
+        bool
+        select S3C2416_SETUP_SDHCI_GPIO
+        help
+          Internal helper functions for S3C2416 based SDHCI systems
+
+config S3C2416_SETUP_SDHCI_GPIO
+        bool
+        help
+          Common setup code for SDHCI gpio.
+
 menu "S3C2416 Machines"
 
 config MACH_SMDK2416
@@ -42,6 +53,7 @@ config MACH_SMDK2416
         select S3C_DEV_HSMMC1
         select S3C_DEV_NAND
         select S3C_DEV_USB_HOST
+        select S3C2416_SETUP_SDHCI
         select S3C2416_PM if PM
         help
           Say Y here if you are using an SMDK2416
diff --git a/arch/arm/mach-s3c2416/Makefile b/arch/arm/mach-s3c2416/Makefile
index ef038d62ffdb..7b805b279caf 100644
--- a/arch/arm/mach-s3c2416/Makefile
+++ b/arch/arm/mach-s3c2416/Makefile
@@ -14,6 +14,10 @@ obj-$(CONFIG_CPU_S3C2416)	+= irq.o
 obj-$(CONFIG_S3C2416_PM)        += pm.o
 #obj-$(CONFIG_S3C2416_DMA)      += dma.o
 
+# Device setup
+obj-$(CONFIG_S3C2416_SETUP_SDHCI) += setup-sdhci.o
+obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
+
 # Machine support
 
 obj-$(CONFIG_MACH_SMDK2416)     += mach-smdk2416.o
diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c
index 7ccf5a2a2bfc..3b02d8506e25 100644
--- a/arch/arm/mach-s3c2416/clock.c
+++ b/arch/arm/mach-s3c2416/clock.c
@@ -38,12 +38,11 @@ static unsigned int armdiv[8] = {
         [7] = 8,
 };
 
-/* ID to hardware numbering, 0 is HSMMC1, 1 is HSMMC0 */
 static struct clksrc_clk hsmmc_div[] = {
         [0] = {
                 .clk = {
                         .name   = "hsmmc-div",
-                        .id     = 1,
+                        .id     = 0,
                         .parent = &clk_esysclk.clk,
                 },
                 .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
@@ -51,7 +50,7 @@ static struct clksrc_clk hsmmc_div[] = {
         [1] = {
                 .clk = {
                         .name   = "hsmmc-div",
-                        .id     = 0,
+                        .id     = 1,
                         .parent = &clk_esysclk.clk,
                 },
                 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
@@ -61,7 +60,7 @@ static struct clksrc_clk hsmmc_div[] = {
 static struct clksrc_clk hsmmc_mux[] = {
         [0] = {
                 .clk    = {
-                        .id     = 1,
+                        .id     = 0,
                         .name   = "hsmmc-if",
                         .ctrlbit = (1 << 6),
                         .enable = s3c2443_clkcon_enable_s,
@@ -77,7 +76,7 @@ static struct clksrc_clk hsmmc_mux[] = {
         },
         [1] = {
                 .clk    = {
-                        .id     = 0,
+                        .id     = 1,
                         .name   = "hsmmc-if",
                         .ctrlbit = (1 << 12),
                         .enable = s3c2443_clkcon_enable_s,
@@ -93,6 +92,13 @@ static struct clksrc_clk hsmmc_mux[] = {
         },
 };
 
+static struct clk hsmmc0_clk = {
+        .name           = "hsmmc",
+        .id             = 0,
+        .parent         = &clk_h,
+        .enable         = s3c2443_clkcon_enable_h,
+        .ctrlbit        = S3C2416_HCLKCON_HSMMC0,
+};
 
 static inline unsigned int s3c2416_fclk_div(unsigned long clkcon0)
 {
@@ -130,6 +136,8 @@ void __init s3c2416_init_clocks(int xtal)
         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
                 s3c_register_clksrc(clksrcs[ptr], 1);
 
+        s3c24xx_register_clock(&hsmmc0_clk);
+
         s3c_pwmclk_init();
 
 }
diff --git a/arch/arm/mach-s3c2416/irq.c b/arch/arm/mach-s3c2416/irq.c
index 00174daf1526..680fe386aca5 100644
--- a/arch/arm/mach-s3c2416/irq.c
+++ b/arch/arm/mach-s3c2416/irq.c
@@ -77,28 +77,27 @@ static void s3c2416_irq_demux_wdtac97(unsigned int irq, struct irq_desc *desc)
 #define INTMSK_WDTAC97  (1UL << (IRQ_WDT - IRQ_EINT0))
 #define SUBMSK_WDTAC97  INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97)
 
-static void s3c2416_irq_wdtac97_mask(unsigned int irqno)
+static void s3c2416_irq_wdtac97_mask(struct irq_data *data)
 {
-        s3c_irqsub_mask(irqno, INTMSK_WDTAC97, SUBMSK_WDTAC97);
+        s3c_irqsub_mask(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
 }
 
-static void s3c2416_irq_wdtac97_unmask(unsigned int irqno)
+static void s3c2416_irq_wdtac97_unmask(struct irq_data *data)
 {
-        s3c_irqsub_unmask(irqno, INTMSK_WDTAC97);
+        s3c_irqsub_unmask(data->irq, INTMSK_WDTAC97);
 }
 
-static void s3c2416_irq_wdtac97_ack(unsigned int irqno)
+static void s3c2416_irq_wdtac97_ack(struct irq_data *data)
 {
-        s3c_irqsub_maskack(irqno, INTMSK_WDTAC97, SUBMSK_WDTAC97);
+        s3c_irqsub_maskack(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
 }
 
 static struct irq_chip s3c2416_irq_wdtac97 = {
-        .mask       = s3c2416_irq_wdtac97_mask,
-        .unmask     = s3c2416_irq_wdtac97_unmask,
-        .ack        = s3c2416_irq_wdtac97_ack,
+        .irq_mask       = s3c2416_irq_wdtac97_mask,
+        .irq_unmask     = s3c2416_irq_wdtac97_unmask,
+        .irq_ack        = s3c2416_irq_wdtac97_ack,
 };
 
-
 /* LCD sub interrupts */
 
 static void s3c2416_irq_demux_lcd(unsigned int irq, struct irq_desc *desc)
@@ -109,28 +108,27 @@ static void s3c2416_irq_demux_lcd(unsigned int irq, struct irq_desc *desc)
 #define INTMSK_LCD      (1UL << (IRQ_LCD - IRQ_EINT0))
 #define SUBMSK_LCD      INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4)
 
-static void s3c2416_irq_lcd_mask(unsigned int irqno)
+static void s3c2416_irq_lcd_mask(struct irq_data *data)
 {
-        s3c_irqsub_mask(irqno, INTMSK_LCD, SUBMSK_LCD);
+        s3c_irqsub_mask(data->irq, INTMSK_LCD, SUBMSK_LCD);
 }
 
-static void s3c2416_irq_lcd_unmask(unsigned int irqno)
+static void s3c2416_irq_lcd_unmask(struct irq_data *data)
 {
-        s3c_irqsub_unmask(irqno, INTMSK_LCD);
+        s3c_irqsub_unmask(data->irq, INTMSK_LCD);
 }
 
-static void s3c2416_irq_lcd_ack(unsigned int irqno)
+static void s3c2416_irq_lcd_ack(struct irq_data *data)
 {
-        s3c_irqsub_maskack(irqno, INTMSK_LCD, SUBMSK_LCD);
+        s3c_irqsub_maskack(data->irq, INTMSK_LCD, SUBMSK_LCD);
 }
 
 static struct irq_chip s3c2416_irq_lcd = {
-        .mask       = s3c2416_irq_lcd_mask,
-        .unmask     = s3c2416_irq_lcd_unmask,
-        .ack        = s3c2416_irq_lcd_ack,
+        .irq_mask       = s3c2416_irq_lcd_mask,
+        .irq_unmask     = s3c2416_irq_lcd_unmask,
+        .irq_ack        = s3c2416_irq_lcd_ack,
 };
 
-
 /* DMA sub interrupts */
 
 static void s3c2416_irq_demux_dma(unsigned int irq, struct irq_desc *desc)
@@ -142,28 +140,27 @@ static void s3c2416_irq_demux_dma(unsigned int irq, struct irq_desc *desc)
 #define SUBMSK_DMA      INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5)
 
 
-static void s3c2416_irq_dma_mask(unsigned int irqno)
+static void s3c2416_irq_dma_mask(struct irq_data *data)
 {
-        s3c_irqsub_mask(irqno, INTMSK_DMA, SUBMSK_DMA);
+        s3c_irqsub_mask(data->irq, INTMSK_DMA, SUBMSK_DMA);
 }
 
-static void s3c2416_irq_dma_unmask(unsigned int irqno)
+static void s3c2416_irq_dma_unmask(struct irq_data *data)
 {
-        s3c_irqsub_unmask(irqno, INTMSK_DMA);
+        s3c_irqsub_unmask(data->irq, INTMSK_DMA);
 }
 
-static void s3c2416_irq_dma_ack(unsigned int irqno)
+static void s3c2416_irq_dma_ack(struct irq_data *data)
 {
-        s3c_irqsub_maskack(irqno, INTMSK_DMA, SUBMSK_DMA);
+        s3c_irqsub_maskack(data->irq, INTMSK_DMA, SUBMSK_DMA);
 }
 
 static struct irq_chip s3c2416_irq_dma = {
-        .mask       = s3c2416_irq_dma_mask,
-        .unmask     = s3c2416_irq_dma_unmask,
-        .ack        = s3c2416_irq_dma_ack,
+        .irq_mask       = s3c2416_irq_dma_mask,
+        .irq_unmask     = s3c2416_irq_dma_unmask,
+        .irq_ack        = s3c2416_irq_dma_ack,
 };
 
-
 /* UART3 sub interrupts */
 
 static void s3c2416_irq_demux_uart3(unsigned int irq, struct irq_desc *desc)
@@ -174,28 +171,27 @@ static void s3c2416_irq_demux_uart3(unsigned int irq, struct irq_desc *desc)
 #define INTMSK_UART3    (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0))
 #define SUBMSK_UART3    (0x7 << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0)))
 
-static void s3c2416_irq_uart3_mask(unsigned int irqno)
+static void s3c2416_irq_uart3_mask(struct irq_data *data)
 {
-        s3c_irqsub_mask(irqno, INTMSK_UART3, SUBMSK_UART3);
+        s3c_irqsub_mask(data->irq, INTMSK_UART3, SUBMSK_UART3);
 }
 
-static void s3c2416_irq_uart3_unmask(unsigned int irqno)
+static void s3c2416_irq_uart3_unmask(struct irq_data *data)
 {
-        s3c_irqsub_unmask(irqno, INTMSK_UART3);
+        s3c_irqsub_unmask(data->irq, INTMSK_UART3);
 }
 
-static void s3c2416_irq_uart3_ack(unsigned int irqno)
+static void s3c2416_irq_uart3_ack(struct irq_data *data)
 {
-        s3c_irqsub_maskack(irqno, INTMSK_UART3, SUBMSK_UART3);
+        s3c_irqsub_maskack(data->irq, INTMSK_UART3, SUBMSK_UART3);
 }
 
 static struct irq_chip s3c2416_irq_uart3 = {
-        .mask       = s3c2416_irq_uart3_mask,
-        .unmask     = s3c2416_irq_uart3_unmask,
-        .ack        = s3c2416_irq_uart3_ack,
+        .irq_mask       = s3c2416_irq_uart3_mask,
+        .irq_unmask     = s3c2416_irq_uart3_unmask,
+        .irq_ack        = s3c2416_irq_uart3_ack,
 };
 
-
 /* IRQ initialisation code */
 
 static int __init s3c2416_add_sub(unsigned int base,
diff --git a/arch/arm/mach-s3c2416/mach-smdk2416.c b/arch/arm/mach-s3c2416/mach-smdk2416.c
index 7fc366476d7e..3f83177246c7 100644
--- a/arch/arm/mach-s3c2416/mach-smdk2416.c
+++ b/arch/arm/mach-s3c2416/mach-smdk2416.c
@@ -46,6 +46,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/nand.h>
+#include <plat/sdhci.h>
 
 #include <plat/regs-fb-v4.h>
 #include <plat/fb.h>
@@ -110,6 +111,13 @@ static struct s3c2410_uartcfg smdk2416_uartcfgs[] __initdata = {
                 .ucon        = UCON,
                 .ulcon       = ULCON | 0x50,
                 .ufcon       = UFCON,
+        },
+        [3] = {
+                .hwport      = 3,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
         }
 };
 
@@ -159,6 +167,18 @@ static struct s3c_fb_platdata smdk2416_fb_platdata = {
         .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
 };
 
+static struct s3c_sdhci_platdata smdk2416_hsmmc0_pdata __initdata = {
+        .max_width              = 4,
+        .cd_type                = S3C_SDHCI_CD_GPIO,
+        .ext_cd_gpio            = S3C2410_GPF(1),
+        .ext_cd_gpio_invert     = 1,
+};
+
+static struct s3c_sdhci_platdata smdk2416_hsmmc1_pdata __initdata = {
+        .max_width              = 4,
+        .cd_type                = S3C_SDHCI_CD_NONE,
+};
+
 static struct platform_device *smdk2416_devices[] __initdata = {
         &s3c_device_fb,
         &s3c_device_wdt,
@@ -180,6 +200,9 @@ static void __init smdk2416_machine_init(void)
         s3c_i2c0_set_platdata(NULL);
         s3c_fb_set_platdata(&smdk2416_fb_platdata);
 
+        s3c_sdhci0_set_platdata(&smdk2416_hsmmc0_pdata);
+        s3c_sdhci1_set_platdata(&smdk2416_hsmmc1_pdata);
+
         gpio_request(S3C2410_GPB(4), "USBHost Power");
         gpio_direction_output(S3C2410_GPB(4), 1);
 
diff --git a/arch/arm/mach-s3c2416/s3c2416.c b/arch/arm/mach-s3c2416/s3c2416.c
index 63f39cdc0972..ba7fd8737434 100644
--- a/arch/arm/mach-s3c2416/s3c2416.c
+++ b/arch/arm/mach-s3c2416/s3c2416.c
@@ -53,6 +53,7 @@
 #include <plat/s3c2416.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/sdhci.h>
 
 #include <plat/iic-core.h>
 #include <plat/fb-core.h>
@@ -115,6 +116,10 @@ void __init s3c2416_map_io(void)
         s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_updown;
         s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_updown;
 
+        /* initialize device information early */
+        s3c2416_default_sdhci0();
+        s3c2416_default_sdhci1();
+
         iotable_init(s3c2416_iodesc, ARRAY_SIZE(s3c2416_iodesc));
 }
 
diff --git a/arch/arm/mach-s3c2416/setup-sdhci-gpio.c b/arch/arm/mach-s3c2416/setup-sdhci-gpio.c
new file mode 100644
index 000000000000..f65cb3ef16ce
--- /dev/null
+++ b/arch/arm/mach-s3c2416/setup-sdhci-gpio.c
@@ -0,0 +1,34 @@
+/* linux/arch/arm/plat-s3c2416/setup-sdhci-gpio.c
+ *
+ * Copyright 2010 Promwad Innovation Company
+ *      Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
+ *
+ * S3C2416 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
+ *
+ * Based on mach-s3c64xx/setup-sdhci-gpio.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <mach/regs-gpio.h>
+#include <plat/gpio-cfg.h>
+
+void s3c2416_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
+{
+        s3c_gpio_cfgrange_nopull(S3C2410_GPE(5), 2 + width, S3C_GPIO_SFN(2));
+}
+
+void s3c2416_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
+{
+        s3c_gpio_cfgrange_nopull(S3C2410_GPL(0), width, S3C_GPIO_SFN(2));
+        s3c_gpio_cfgrange_nopull(S3C2410_GPL(8), 2, S3C_GPIO_SFN(2));
+}
diff --git a/arch/arm/mach-s3c2416/setup-sdhci.c b/arch/arm/mach-s3c2416/setup-sdhci.c
new file mode 100644
index 000000000000..ed34fad8f2c6
--- /dev/null
+++ b/arch/arm/mach-s3c2416/setup-sdhci.c
@@ -0,0 +1,61 @@
+/* linux/arch/arm/mach-s3c2416/setup-sdhci.c
+ *
+ * Copyright 2010 Promwad Innovation Company
+ *      Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
+ *
+ * S3C2416 - Helper functions for settign up SDHCI device(s) (HSMMC)
+ *
+ * Based on mach-s3c64xx/setup-sdhci.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <linux/mmc/card.h>
+#include <linux/mmc/host.h>
+
+#include <plat/regs-sdhci.h>
+#include <plat/sdhci.h>
+
+/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
+
+char *s3c2416_hsmmc_clksrcs[4] = {
+        [0] = "hsmmc",
+        [1] = "hsmmc",
+        [2] = "hsmmc-if",
+        /* [3] = "48m", - note not successfully used yet */
+};
+
+void s3c2416_setup_sdhci_cfg_card(struct platform_device *dev,
+                                  void __iomem *r,
+                                  struct mmc_ios *ios,
+                                  struct mmc_card *card)
+{
+        u32 ctrl2, ctrl3;
+
+        ctrl2 = __raw_readl(r + S3C_SDHCI_CONTROL2);
+        ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
+        ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
+                  S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
+                  S3C_SDHCI_CTRL2_ENFBCLKRX |
+                  S3C_SDHCI_CTRL2_DFCNT_NONE |
+                  S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
+
+        if (ios->clock < 25 * 1000000)
+                ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
+                         S3C_SDHCI_CTRL3_FCSEL2 |
+                         S3C_SDHCI_CTRL3_FCSEL1 |
+                         S3C_SDHCI_CTRL3_FCSEL0);
+        else
+                ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
+
+        __raw_writel(ctrl2, r + S3C_SDHCI_CONTROL2);
+        __raw_writel(ctrl3, r + S3C_SDHCI_CONTROL3);
+}
diff --git a/arch/arm/mach-s3c2440/irq.c b/arch/arm/mach-s3c2440/irq.c
index 0c049b95c378..acad4428bef0 100644
--- a/arch/arm/mach-s3c2440/irq.c
+++ b/arch/arm/mach-s3c2440/irq.c
@@ -69,27 +69,27 @@ static void s3c_irq_demux_wdtac97(unsigned int irq,
 #define INTMSK_WDT       (1UL << (IRQ_WDT - IRQ_EINT0))
 
 static void
-s3c_irq_wdtac97_mask(unsigned int irqno)
+s3c_irq_wdtac97_mask(struct irq_data *data)
 {
-        s3c_irqsub_mask(irqno, INTMSK_WDT, 3<<13);
+        s3c_irqsub_mask(data->irq, INTMSK_WDT, 3 << 13);
 }
 
 static void
-s3c_irq_wdtac97_unmask(unsigned int irqno)
+s3c_irq_wdtac97_unmask(struct irq_data *data)
 {
-        s3c_irqsub_unmask(irqno, INTMSK_WDT);
+        s3c_irqsub_unmask(data->irq, INTMSK_WDT);
 }
 
 static void
-s3c_irq_wdtac97_ack(unsigned int irqno)
+s3c_irq_wdtac97_ack(struct irq_data *data)
 {
-        s3c_irqsub_maskack(irqno, INTMSK_WDT, 3<<13);
+        s3c_irqsub_maskack(data->irq, INTMSK_WDT, 3 << 13);
 }
 
 static struct irq_chip s3c_irq_wdtac97 = {
-        .mask       = s3c_irq_wdtac97_mask,
-        .unmask     = s3c_irq_wdtac97_unmask,
-        .ack        = s3c_irq_wdtac97_ack,
+        .irq_mask       = s3c_irq_wdtac97_mask,
+        .irq_unmask     = s3c_irq_wdtac97_unmask,
+        .irq_ack        = s3c_irq_wdtac97_ack,
 };
 
 static int s3c2440_irq_add(struct sys_device *sysdev)
diff --git a/arch/arm/mach-s3c2440/s3c244x-irq.c b/arch/arm/mach-s3c2440/s3c244x-irq.c
index a75c0c2431ea..83daf4ece764 100644
--- a/arch/arm/mach-s3c2440/s3c244x-irq.c
+++ b/arch/arm/mach-s3c2440/s3c244x-irq.c
@@ -68,27 +68,27 @@ static void s3c_irq_demux_cam(unsigned int irq,
 #define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0))
 
 static void
-s3c_irq_cam_mask(unsigned int irqno)
+s3c_irq_cam_mask(struct irq_data *data)
 {
-        s3c_irqsub_mask(irqno, INTMSK_CAM, 3<<11);
+        s3c_irqsub_mask(data->irq, INTMSK_CAM, 3 << 11);
 }
 
 static void
-s3c_irq_cam_unmask(unsigned int irqno)
+s3c_irq_cam_unmask(struct irq_data *data)
 {
-        s3c_irqsub_unmask(irqno, INTMSK_CAM);
+        s3c_irqsub_unmask(data->irq, INTMSK_CAM);
 }
 
 static void
-s3c_irq_cam_ack(unsigned int irqno)
+s3c_irq_cam_ack(struct irq_data *data)
 {
-        s3c_irqsub_maskack(irqno, INTMSK_CAM, 3<<11);
+        s3c_irqsub_maskack(data->irq, INTMSK_CAM, 3 << 11);
 }
 
 static struct irq_chip s3c_irq_cam = {
-        .mask       = s3c_irq_cam_mask,
-        .unmask     = s3c_irq_cam_unmask,
-        .ack        = s3c_irq_cam_ack,
+        .irq_mask       = s3c_irq_cam_mask,
+        .irq_unmask     = s3c_irq_cam_unmask,
+        .irq_ack        = s3c_irq_cam_ack,
 };
 
 static int s3c244x_irq_add(struct sys_device *sysdev)
diff --git a/arch/arm/mach-s3c2443/Kconfig b/arch/arm/mach-s3c2443/Kconfig
index 31babec90cec..d8eb86823df7 100644
--- a/arch/arm/mach-s3c2443/Kconfig
+++ b/arch/arm/mach-s3c2443/Kconfig
@@ -10,6 +10,7 @@ config CPU_S3C2443
         select CPU_LLSERIAL_S3C2440
         select SAMSUNG_CLKSRC
         select S3C2443_CLOCK
+        select S3C_GPIO_PULL_S3C2443
         help
           Support for the S3C2443 SoC from the S3C24XX line
 
@@ -25,7 +26,7 @@ config MACH_SMDK2443
         bool "SMDK2443"
         select CPU_S3C2443
         select MACH_SMDK
-        select S3C_DEV_HSMMC
+        select S3C_DEV_HSMMC1
         help
           Say Y here if you are using an SMDK2443
 
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c
index 0c3c0c884cd3..f4ec6d5715c8 100644
--- a/arch/arm/mach-s3c2443/clock.c
+++ b/arch/arm/mach-s3c2443/clock.c
@@ -196,7 +196,7 @@ static struct clksrc_clk clk_hsspi = {
 static struct clksrc_clk clk_hsmmc_div = {
         .clk    = {
                 .name           = "hsmmc-div",
-                .id             = -1,
+                .id             = 1,
                 .parent         = &clk_esysclk.clk,
         },
         .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
@@ -231,7 +231,7 @@ static int s3c2443_enable_hsmmc(struct clk *clk, int enable)
 
 static struct clk clk_hsmmc = {
         .name           = "hsmmc-if",
-        .id             = -1,
+        .id             = 1,
         .parent         = &clk_hsmmc_div.clk,
         .enable         = s3c2443_enable_hsmmc,
         .ops            = &(struct clk_ops) {
diff --git a/arch/arm/mach-s3c2443/irq.c b/arch/arm/mach-s3c2443/irq.c
index 893424767ce1..c7820f9c1352 100644
--- a/arch/arm/mach-s3c2443/irq.c
+++ b/arch/arm/mach-s3c2443/irq.c
@@ -75,28 +75,27 @@ static void s3c2443_irq_demux_wdtac97(unsigned int irq, struct irq_desc *desc)
 #define INTMSK_WDTAC97  (1UL << (IRQ_WDT - IRQ_EINT0))
 #define SUBMSK_WDTAC97  INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97)
 
-static void s3c2443_irq_wdtac97_mask(unsigned int irqno)
+static void s3c2443_irq_wdtac97_mask(struct irq_data *data)
 {
-        s3c_irqsub_mask(irqno, INTMSK_WDTAC97, SUBMSK_WDTAC97);
+        s3c_irqsub_mask(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
 }
 
-static void s3c2443_irq_wdtac97_unmask(unsigned int irqno)
+static void s3c2443_irq_wdtac97_unmask(struct irq_data *data)
 {
-        s3c_irqsub_unmask(irqno, INTMSK_WDTAC97);
+        s3c_irqsub_unmask(data->irq, INTMSK_WDTAC97);
 }
 
-static void s3c2443_irq_wdtac97_ack(unsigned int irqno)
+static void s3c2443_irq_wdtac97_ack(struct irq_data *data)
 {
-        s3c_irqsub_maskack(irqno, INTMSK_WDTAC97, SUBMSK_WDTAC97);
+        s3c_irqsub_maskack(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
 }
 
 static struct irq_chip s3c2443_irq_wdtac97 = {
-        .mask       = s3c2443_irq_wdtac97_mask,
-        .unmask     = s3c2443_irq_wdtac97_unmask,
-        .ack        = s3c2443_irq_wdtac97_ack,
+        .irq_mask       = s3c2443_irq_wdtac97_mask,
+        .irq_unmask     = s3c2443_irq_wdtac97_unmask,
+        .irq_ack        = s3c2443_irq_wdtac97_ack,
 };
 
-
 /* LCD sub interrupts */
 
 static void s3c2443_irq_demux_lcd(unsigned int irq, struct irq_desc *desc)
@@ -107,28 +106,27 @@ static void s3c2443_irq_demux_lcd(unsigned int irq, struct irq_desc *desc)
 #define INTMSK_LCD      (1UL << (IRQ_LCD - IRQ_EINT0))
 #define SUBMSK_LCD      INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4)
 
-static void s3c2443_irq_lcd_mask(unsigned int irqno)
+static void s3c2443_irq_lcd_mask(struct irq_data *data)
 {
-        s3c_irqsub_mask(irqno, INTMSK_LCD, SUBMSK_LCD);
+        s3c_irqsub_mask(data->irq, INTMSK_LCD, SUBMSK_LCD);
 }
 
-static void s3c2443_irq_lcd_unmask(unsigned int irqno)
+static void s3c2443_irq_lcd_unmask(struct irq_data *data)
 {
-        s3c_irqsub_unmask(irqno, INTMSK_LCD);
+        s3c_irqsub_unmask(data->irq, INTMSK_LCD);
 }
 
-static void s3c2443_irq_lcd_ack(unsigned int irqno)
+static void s3c2443_irq_lcd_ack(struct irq_data *data)
 {
-        s3c_irqsub_maskack(irqno, INTMSK_LCD, SUBMSK_LCD);
+        s3c_irqsub_maskack(data->irq, INTMSK_LCD, SUBMSK_LCD);
 }
 
 static struct irq_chip s3c2443_irq_lcd = {
-        .mask       = s3c2443_irq_lcd_mask,
-        .unmask     = s3c2443_irq_lcd_unmask,
-        .ack        = s3c2443_irq_lcd_ack,
+        .irq_mask       = s3c2443_irq_lcd_mask,
+        .irq_unmask     = s3c2443_irq_lcd_unmask,
+        .irq_ack        = s3c2443_irq_lcd_ack,
 };
 
-
 /* DMA sub interrupts */
 
 static void s3c2443_irq_demux_dma(unsigned int irq, struct irq_desc *desc)
@@ -139,29 +137,27 @@ static void s3c2443_irq_demux_dma(unsigned int irq, struct irq_desc *desc)
 #define INTMSK_DMA      (1UL << (IRQ_S3C2443_DMA - IRQ_EINT0))
 #define SUBMSK_DMA      INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5)
 
-
-static void s3c2443_irq_dma_mask(unsigned int irqno)
+static void s3c2443_irq_dma_mask(struct irq_data *data)
 {
-        s3c_irqsub_mask(irqno, INTMSK_DMA, SUBMSK_DMA);
+        s3c_irqsub_mask(data->irq, INTMSK_DMA, SUBMSK_DMA);
 }
 
-static void s3c2443_irq_dma_unmask(unsigned int irqno)
+static void s3c2443_irq_dma_unmask(struct irq_data *data)
 {
-        s3c_irqsub_unmask(irqno, INTMSK_DMA);
+        s3c_irqsub_unmask(data->irq, INTMSK_DMA);
 }
 
-static void s3c2443_irq_dma_ack(unsigned int irqno)
+static void s3c2443_irq_dma_ack(struct irq_data *data)
 {
-        s3c_irqsub_maskack(irqno, INTMSK_DMA, SUBMSK_DMA);
+        s3c_irqsub_maskack(data->irq, INTMSK_DMA, SUBMSK_DMA);
 }
 
 static struct irq_chip s3c2443_irq_dma = {
-        .mask       = s3c2443_irq_dma_mask,
-        .unmask     = s3c2443_irq_dma_unmask,
-        .ack        = s3c2443_irq_dma_ack,
+        .irq_mask       = s3c2443_irq_dma_mask,
+        .irq_unmask     = s3c2443_irq_dma_unmask,
+        .irq_ack        = s3c2443_irq_dma_ack,
 };
 
-
 /* UART3 sub interrupts */
 
 static void s3c2443_irq_demux_uart3(unsigned int irq, struct irq_desc *desc)
@@ -172,28 +168,27 @@ static void s3c2443_irq_demux_uart3(unsigned int irq, struct irq_desc *desc)
 #define INTMSK_UART3    (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0))
 #define SUBMSK_UART3    (0x7 << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0)))
 
-static void s3c2443_irq_uart3_mask(unsigned int irqno)
+static void s3c2443_irq_uart3_mask(struct irq_data *data)
 {
-        s3c_irqsub_mask(irqno, INTMSK_UART3, SUBMSK_UART3);
+        s3c_irqsub_mask(data->irq, INTMSK_UART3, SUBMSK_UART3);
 }
 
-static void s3c2443_irq_uart3_unmask(unsigned int irqno)
+static void s3c2443_irq_uart3_unmask(struct irq_data *data)
 {
-        s3c_irqsub_unmask(irqno, INTMSK_UART3);
+        s3c_irqsub_unmask(data->irq, INTMSK_UART3);
 }
 
-static void s3c2443_irq_uart3_ack(unsigned int irqno)
+static void s3c2443_irq_uart3_ack(struct irq_data *data)
 {
-        s3c_irqsub_maskack(irqno, INTMSK_UART3, SUBMSK_UART3);
+        s3c_irqsub_maskack(data->irq, INTMSK_UART3, SUBMSK_UART3);
 }
 
 static struct irq_chip s3c2443_irq_uart3 = {
-        .mask       = s3c2443_irq_uart3_mask,
-        .unmask     = s3c2443_irq_uart3_unmask,
-        .ack        = s3c2443_irq_uart3_ack,
+        .irq_mask       = s3c2443_irq_uart3_mask,
+        .irq_unmask     = s3c2443_irq_uart3_unmask,
+        .irq_ack        = s3c2443_irq_uart3_ack,
 };
 
-
 /* CAM sub interrupts */
 
 static void s3c2443_irq_demux_cam(unsigned int irq, struct irq_desc *desc)
@@ -204,25 +199,25 @@ static void s3c2443_irq_demux_cam(unsigned int irq, struct irq_desc *desc)
 #define INTMSK_CAM      (1UL << (IRQ_CAM - IRQ_EINT0))
 #define SUBMSK_CAM      INTMSK(IRQ_S3C2440_CAM_C, IRQ_S3C2440_CAM_P)
 
-static void s3c2443_irq_cam_mask(unsigned int irqno)
+static void s3c2443_irq_cam_mask(struct irq_data *data)
 {
-        s3c_irqsub_mask(irqno, INTMSK_CAM, SUBMSK_CAM);
+        s3c_irqsub_mask(data->irq, INTMSK_CAM, SUBMSK_CAM);
 }
 
-static void s3c2443_irq_cam_unmask(unsigned int irqno)
+static void s3c2443_irq_cam_unmask(struct irq_data *data)
 {
-        s3c_irqsub_unmask(irqno, INTMSK_CAM);
+        s3c_irqsub_unmask(data->irq, INTMSK_CAM);
 }
 
-static void s3c2443_irq_cam_ack(unsigned int irqno)
+static void s3c2443_irq_cam_ack(struct irq_data *data)
 {
-        s3c_irqsub_maskack(irqno, INTMSK_CAM, SUBMSK_CAM);
+        s3c_irqsub_maskack(data->irq, INTMSK_CAM, SUBMSK_CAM);
 }
 
 static struct irq_chip s3c2443_irq_cam = {
-        .mask       = s3c2443_irq_cam_mask,
-        .unmask     = s3c2443_irq_cam_unmask,
-        .ack        = s3c2443_irq_cam_ack,
+        .irq_mask       = s3c2443_irq_cam_mask,
+        .irq_unmask     = s3c2443_irq_cam_unmask,
+        .irq_ack        = s3c2443_irq_cam_ack,
 };
 
 /* IRQ initialisation code */
diff --git a/arch/arm/mach-s3c2443/mach-smdk2443.c b/arch/arm/mach-s3c2443/mach-smdk2443.c
index 4337f0a9960d..514275e43ca0 100644
--- a/arch/arm/mach-s3c2443/mach-smdk2443.c
+++ b/arch/arm/mach-s3c2443/mach-smdk2443.c
@@ -99,13 +99,20 @@ static struct s3c2410_uartcfg smdk2443_uartcfgs[] __initdata = {
                 .ucon        = 0x3c5,
                 .ulcon       = 0x43,
                 .ufcon       = 0x51,
+        },
+        [3] = {
+                .hwport      = 3,
+                .flags       = 0,
+                .ucon        = 0x3c5,
+                .ulcon       = 0x03,
+                .ufcon       = 0x51,
         }
 };
 
 static struct platform_device *smdk2443_devices[] __initdata = {
         &s3c_device_wdt,
         &s3c_device_i2c0,
-        &s3c_device_hsmmc0,
+        &s3c_device_hsmmc1,
 #ifdef CONFIG_SND_SOC_SMDK2443_WM9710
         &s3c_device_ac97,
 #endif
diff --git a/arch/arm/mach-s3c2443/s3c2443.c b/arch/arm/mach-s3c2443/s3c2443.c
index 33d18dd1ebd5..e6a28ba52c7d 100644
--- a/arch/arm/mach-s3c2443/s3c2443.c
+++ b/arch/arm/mach-s3c2443/s3c2443.c
@@ -16,6 +16,7 @@
 #include <linux/list.h>
 #include <linux/timer.h>
 #include <linux/init.h>
+#include <linux/gpio.h>
 #include <linux/platform_device.h>
 #include <linux/serial_core.h>
 #include <linux/sysdev.h>
@@ -32,6 +33,9 @@
 #include <mach/regs-s3c2443-clock.h>
 #include <mach/reset.h>
 
+#include <plat/gpio-core.h>
+#include <plat/gpio-cfg.h>
+#include <plat/gpio-cfg-helpers.h>
 #include <plat/s3c2443.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
@@ -86,6 +90,9 @@ void __init s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 
 void __init s3c2443_map_io(void)
 {
+        s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_s3c2443;
+        s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_s3c2443;
+
         iotable_init(s3c2443_iodesc, ARRAY_SIZE(s3c2443_iodesc));
 }
 
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 1c98d2ff2ed6..dd3782064508 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -127,7 +127,7 @@ int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
         return s3c64xx_gate(S3C_SCLK_GATE, clk, enable);
 }
 
-static struct clk init_clocks_disable[] = {
+static struct clk init_clocks_off[] = {
         {
                 .name           = "nand",
                 .id             = -1,
@@ -834,10 +834,6 @@ static struct clk *clks[] __initdata = {
 void __init s3c64xx_register_clocks(unsigned long xtal, 
                                     unsigned armclk_divlimit)
 {
-        struct clk *clkp;
-        int ret;
-        int ptr;
-
         armclk_mask = armclk_divlimit;
 
         s3c24xx_register_baseclocks(xtal);
@@ -845,17 +841,8 @@ void __init s3c64xx_register_clocks(unsigned long xtal,
 
         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
 
-        clkp = init_clocks_disable;
-        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
-
-                ret = s3c24xx_register_clock(clkp);
-                if (ret < 0) {
-                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
-                               clkp->name, ret);
-                }
-
-                (clkp->enable)(clkp, 0);
-        }
+        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 
         s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c
index 372ea6855454..135db1b41252 100644
--- a/arch/arm/mach-s3c64xx/dma.c
+++ b/arch/arm/mach-s3c64xx/dma.c
@@ -212,6 +212,7 @@ static int s3c64xx_dma_start(struct s3c2410_dma_chan *chan)
 
         config = readl(chan->regs + PL080S_CH_CONFIG);
         config |= PL080_CONFIG_ENABLE;
+        config &= ~PL080_CONFIG_HALT;
 
         pr_debug("%s: writing config %08x\n", __func__, config);
         writel(config, chan->regs + PL080S_CH_CONFIG);
diff --git a/arch/arm/mach-s3c64xx/irq-eint.c b/arch/arm/mach-s3c64xx/irq-eint.c
index 5682d6a7f4af..2ead8189da74 100644
--- a/arch/arm/mach-s3c64xx/irq-eint.c
+++ b/arch/arm/mach-s3c64xx/irq-eint.c
@@ -30,41 +30,41 @@
 #include <plat/pm.h>
 
 #define eint_offset(irq)        ((irq) - IRQ_EINT(0))
-#define eint_irq_to_bit(irq)    (1 << eint_offset(irq))
+#define eint_irq_to_bit(irq)    ((u32)(1 << eint_offset(irq)))
 
-static inline void s3c_irq_eint_mask(unsigned int irq)
+static inline void s3c_irq_eint_mask(struct irq_data *data)
 {
         u32 mask;
 
         mask = __raw_readl(S3C64XX_EINT0MASK);
-        mask |= eint_irq_to_bit(irq);
+        mask |= (u32)data->chip_data;
         __raw_writel(mask, S3C64XX_EINT0MASK);
 }
 
-static void s3c_irq_eint_unmask(unsigned int irq)
+static void s3c_irq_eint_unmask(struct irq_data *data)
 {
         u32 mask;
 
         mask = __raw_readl(S3C64XX_EINT0MASK);
-        mask &= ~eint_irq_to_bit(irq);
+        mask &= ~((u32)data->chip_data);
         __raw_writel(mask, S3C64XX_EINT0MASK);
 }
 
-static inline void s3c_irq_eint_ack(unsigned int irq)
+static inline void s3c_irq_eint_ack(struct irq_data *data)
 {
-        __raw_writel(eint_irq_to_bit(irq), S3C64XX_EINT0PEND);
+        __raw_writel((u32)data->chip_data, S3C64XX_EINT0PEND);
 }
 
-static void s3c_irq_eint_maskack(unsigned int irq)
+static void s3c_irq_eint_maskack(struct irq_data *data)
 {
         /* compiler should in-line these */
-        s3c_irq_eint_mask(irq);
-        s3c_irq_eint_ack(irq);
+        s3c_irq_eint_mask(data);
+        s3c_irq_eint_ack(data);
 }
 
-static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
+static int s3c_irq_eint_set_type(struct irq_data *data, unsigned int type)
 {
-        int offs = eint_offset(irq);
+        int offs = eint_offset(data->irq);
         int pin, pin_val;
         int shift;
         u32 ctrl, mask;
@@ -140,12 +140,12 @@ static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
 
 static struct irq_chip s3c_irq_eint = {
         .name           = "s3c-eint",
-        .mask           = s3c_irq_eint_mask,
-        .unmask         = s3c_irq_eint_unmask,
-        .mask_ack       = s3c_irq_eint_maskack,
-        .ack            = s3c_irq_eint_ack,
-        .set_type       = s3c_irq_eint_set_type,
-        .set_wake       = s3c_irqext_wake,
+        .irq_mask       = s3c_irq_eint_mask,
+        .irq_unmask     = s3c_irq_eint_unmask,
+        .irq_mask_ack   = s3c_irq_eint_maskack,
+        .irq_ack        = s3c_irq_eint_ack,
+        .irq_set_type   = s3c_irq_eint_set_type,
+        .irq_set_wake   = s3c_irqext_wake,
 };
 
 /* s3c_irq_demux_eint
@@ -198,6 +198,7 @@ static int __init s3c64xx_init_irq_eint(void)
 
         for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
                 set_irq_chip(irq, &s3c_irq_eint);
+                set_irq_chip_data(irq, (void *)eint_irq_to_bit(irq));
                 set_irq_handler(irq, handle_level_irq);
                 set_irq_flags(irq, IRQF_VALID);
         }
diff --git a/arch/arm/mach-s5p6442/clock.c b/arch/arm/mach-s5p6442/clock.c
index 16d6e7e61b50..fbbc7bede685 100644
--- a/arch/arm/mach-s5p6442/clock.c
+++ b/arch/arm/mach-s5p6442/clock.c
@@ -340,7 +340,7 @@ void __init_or_cpufreq s5p6442_setup_clocks(void)
         clk_pclkd1.rate = pclkd1;
 }
 
-static struct clk init_clocks_disable[] = {
+static struct clk init_clocks_off[] = {
         {
                 .name           = "pdma",
                 .id             = -1,
@@ -408,23 +408,13 @@ static struct clk *clks[] __initdata = {
 
 void __init s5p6442_register_clocks(void)
 {
-        struct clk *clkptr;
-        int i, ret;
-
         s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
 
         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
 
-        clkptr = init_clocks_disable;
-        for (i = 0; i < ARRAY_SIZE(init_clocks_disable); i++, clkptr++) {
-                ret = s3c24xx_register_clock(clkptr);
-                if (ret < 0) {
-                        printk(KERN_ERR "Fail to register clock %s (%d)\n",
-                                        clkptr->name, ret);
-                } else
-                        (clkptr->enable)(clkptr, 0);
-        }
+        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 
         s3c_pwmclk_init();
 }
diff --git a/arch/arm/mach-s5p6442/include/mach/map.h b/arch/arm/mach-s5p6442/include/mach/map.h
index 31fb2e68d527..203dd5a18bd5 100644
--- a/arch/arm/mach-s5p6442/include/mach/map.h
+++ b/arch/arm/mach-s5p6442/include/mach/map.h
@@ -28,6 +28,9 @@
 #define S5P6442_PA_VIC1         (0xE4100000)
 #define S5P6442_PA_VIC2         (0xE4200000)
 
+#define S5P6442_PA_SROMC        (0xE7000000)
+#define S5P_PA_SROMC            S5P6442_PA_SROMC
+
 #define S5P6442_PA_MDMA         0xE8000000
 #define S5P6442_PA_PDMA         0xE9000000
 
diff --git a/arch/arm/mach-s5p6442/mach-smdk6442.c b/arch/arm/mach-s5p6442/mach-smdk6442.c
index 819fd80d00af..e69f137b0a39 100644
--- a/arch/arm/mach-s5p6442/mach-smdk6442.c
+++ b/arch/arm/mach-s5p6442/mach-smdk6442.c
@@ -12,6 +12,7 @@
 #include <linux/types.h>
 #include <linux/init.h>
 #include <linux/serial_core.h>
+#include <linux/i2c.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -25,6 +26,7 @@
 #include <plat/s5p6442.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/iic.h>
 
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define SMDK6442_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
@@ -65,10 +67,15 @@ static struct s3c2410_uartcfg smdk6442_uartcfgs[] __initdata = {
 };
 
 static struct platform_device *smdk6442_devices[] __initdata = {
+        &s3c_device_i2c0,
         &s5p6442_device_iis0,
         &s3c_device_wdt,
 };
 
+static struct i2c_board_info smdk6442_i2c_devs0[] __initdata = {
+        { I2C_BOARD_INFO("wm8580", 0x1b), },
+};
+
 static void __init smdk6442_map_io(void)
 {
         s5p_init_io(NULL, 0, S5P_VA_CHIPID);
@@ -78,6 +85,9 @@ static void __init smdk6442_map_io(void)
 
 static void __init smdk6442_machine_init(void)
 {
+        s3c_i2c0_set_platdata(NULL);
+        i2c_register_board_info(0, smdk6442_i2c_devs0,
+                        ARRAY_SIZE(smdk6442_i2c_devs0));
         platform_add_devices(smdk6442_devices, ARRAY_SIZE(smdk6442_devices));
 }
 
diff --git a/arch/arm/mach-s5p6442/setup-i2c0.c b/arch/arm/mach-s5p6442/setup-i2c0.c
index 662695dd7761..aad85656b0cc 100644
--- a/arch/arm/mach-s5p6442/setup-i2c0.c
+++ b/arch/arm/mach-s5p6442/setup-i2c0.c
@@ -14,12 +14,15 @@
 
 #include <linux/kernel.h>
 #include <linux/types.h>
+#include <linux/gpio.h>
 
 struct platform_device; /* don't need the contents */
 
+#include <plat/gpio-cfg.h>
 #include <plat/iic.h>
 
 void s3c_i2c0_cfg_gpio(struct platform_device *dev)
 {
-        /* Will be populated later */
+        s3c_gpio_cfgall_range(S5P6442_GPD1(0), 2,
+                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
 }
diff --git a/arch/arm/mach-s5p64x0/Makefile b/arch/arm/mach-s5p64x0/Makefile
index 2655829e6bf8..ae6bf6feba89 100644
--- a/arch/arm/mach-s5p64x0/Makefile
+++ b/arch/arm/mach-s5p64x0/Makefile
@@ -12,9 +12,9 @@ obj-				:=
 
 # Core support for S5P64X0 system
 
-obj-$(CONFIG_ARCH_S5P64X0)      += cpu.o init.o clock.o dma.o
+obj-$(CONFIG_ARCH_S5P64X0)      += cpu.o init.o clock.o dma.o gpiolib.o
 obj-$(CONFIG_ARCH_S5P64X0)      += setup-i2c0.o
-obj-$(CONFIG_CPU_S5P6440)       += clock-s5p6440.o gpio.o
+obj-$(CONFIG_CPU_S5P6440)       += clock-s5p6440.o
 obj-$(CONFIG_CPU_S5P6450)       += clock-s5p6450.o
 
 # machine support
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index 409c5fc3670d..9f12c2ebf416 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -133,7 +133,7 @@ static struct clksrc_clk clk_pclk_low = {
  * recommended to keep the following clocks disabled until the driver requests
  * for enabling the clock.
  */
-static struct clk init_clocks_disable[] = {
+static struct clk init_clocks_off[] = {
         {
                 .name           = "nand",
                 .id             = -1,
@@ -419,7 +419,7 @@ static struct clksrc_sources clkset_audio = {
 static struct clksrc_clk clksrcs[] = {
         {
                 .clk    = {
-                        .name           = "mmc_bus",
+                        .name           = "sclk_mmc",
                         .id             = 0,
                         .ctrlbit        = (1 << 24),
                         .enable         = s5p64x0_sclk_ctrl,
@@ -429,7 +429,7 @@ static struct clksrc_clk clksrcs[] = {
                 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
         }, {
                 .clk    = {
-                        .name           = "mmc_bus",
+                        .name           = "sclk_mmc",
                         .id             = 1,
                         .ctrlbit        = (1 << 25),
                         .enable         = s5p64x0_sclk_ctrl,
@@ -439,7 +439,7 @@ static struct clksrc_clk clksrcs[] = {
                 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
         }, {
                 .clk    = {
-                        .name           = "mmc_bus",
+                        .name           = "sclk_mmc",
                         .id             = 2,
                         .ctrlbit        = (1 << 26),
                         .enable         = s5p64x0_sclk_ctrl,
@@ -602,8 +602,6 @@ static struct clk *clks[] __initdata = {
 
 void __init s5p6440_register_clocks(void)
 {
-        struct clk *clkp;
-        int ret;
         int ptr;
 
         s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
@@ -614,16 +612,8 @@ void __init s5p6440_register_clocks(void)
         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
 
-        clkp = init_clocks_disable;
-        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
-
-                ret = s3c24xx_register_clock(clkp);
-                if (ret < 0) {
-                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
-                               clkp->name, ret);
-                }
-                (clkp->enable)(clkp, 0);
-        }
+        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 
         s3c_pwmclk_init();
 }
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index 7fc6abd35914..4eec457ddccc 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -181,7 +181,7 @@ static struct clksrc_clk clk_pclk_low = {
  * recommended to keep the following clocks disabled until the driver requests
  * for enabling the clock.
  */
-static struct clk init_clocks_disable[] = {
+static struct clk init_clocks_off[] = {
         {
                 .name           = "usbhost",
                 .id             = -1,
@@ -231,6 +231,12 @@ static struct clk init_clocks_disable[] = {
                 .enable         = s5p64x0_pclk_ctrl,
                 .ctrlbit        = (1 << 5),
         }, {
+                .name           = "rtc",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 6),
+        }, {
                 .name           = "adc",
                 .id             = -1,
                 .parent         = &clk_pclk_low.clk,
@@ -261,6 +267,18 @@ static struct clk init_clocks_disable[] = {
                 .enable         = s5p64x0_pclk_ctrl,
                 .ctrlbit        = (1 << 26),
         }, {
+                .name           = "iis",
+                .id             = 1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 15),
+        }, {
+                .name           = "iis",
+                .id             = 2,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 16),
+        }, {
                 .name           = "i2c",
                 .id             = 1,
                 .parent         = &clk_pclk_low.clk,
@@ -633,8 +651,6 @@ void __init_or_cpufreq s5p6450_setup_clocks(void)
 
 void __init s5p6450_register_clocks(void)
 {
-        struct clk *clkp;
-        int ret;
         int ptr;
 
         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
@@ -643,16 +659,8 @@ void __init s5p6450_register_clocks(void)
         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
 
-        clkp = init_clocks_disable;
-        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
-
-                ret = s3c24xx_register_clock(clkp);
-                if (ret < 0) {
-                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
-                               clkp->name, ret);
-                }
-                (clkp->enable)(clkp, 0);
-        }
+        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 
         s3c_pwmclk_init();
 }
diff --git a/arch/arm/mach-s5p64x0/dev-audio.c b/arch/arm/mach-s5p64x0/dev-audio.c
index 14f89e73b8de..35f1f226dabb 100644
--- a/arch/arm/mach-s5p64x0/dev-audio.c
+++ b/arch/arm/mach-s5p64x0/dev-audio.c
@@ -24,13 +24,13 @@ static const char *rclksrc[] = {
         [1] = "sclk_audio2",
 };
 
-static int s5p64x0_cfg_i2s(struct platform_device *pdev)
+static int s5p6440_cfg_i2s(struct platform_device *pdev)
 {
-        /* configure GPIO for i2s port */
         switch (pdev->id) {
         case 0:
-                s3c_gpio_cfgpin_range(S5P6440_GPR(4), 5, S3C_GPIO_SFN(5));
-                s3c_gpio_cfgpin_range(S5P6440_GPR(13), 2, S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin_range(S5P6440_GPC(4), 2, S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6440_GPC(7), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin_range(S5P6440_GPH(6), 4, S3C_GPIO_SFN(5));
                 break;
         default:
                 printk(KERN_ERR "Invalid Device %d\n", pdev->id);
@@ -40,8 +40,8 @@ static int s5p64x0_cfg_i2s(struct platform_device *pdev)
         return 0;
 }
 
-static struct s3c_audio_pdata s5p64x0_i2s_pdata = {
-        .cfg_gpio = s5p64x0_cfg_i2s,
+static struct s3c_audio_pdata s5p6440_i2s_pdata = {
+        .cfg_gpio = s5p6440_cfg_i2s,
         .type = {
                 .i2s = {
                         .quirks = QUIRK_PRI_6CHAN,
@@ -50,7 +50,7 @@ static struct s3c_audio_pdata s5p64x0_i2s_pdata = {
         },
 };
 
-static struct resource s5p64x0_iis0_resource[] = {
+static struct resource s5p64x0_i2s0_resource[] = {
         [0] = {
                 .start  = S5P64X0_PA_I2S,
                 .end    = S5P64X0_PA_I2S + 0x100 - 1,
@@ -71,20 +71,117 @@ static struct resource s5p64x0_iis0_resource[] = {
 struct platform_device s5p6440_device_iis = {
         .name           = "samsung-i2s",
         .id             = 0,
-        .num_resources  = ARRAY_SIZE(s5p64x0_iis0_resource),
-        .resource       = s5p64x0_iis0_resource,
+        .num_resources  = ARRAY_SIZE(s5p64x0_i2s0_resource),
+        .resource       = s5p64x0_i2s0_resource,
         .dev = {
-                .platform_data = &s5p64x0_i2s_pdata,
+                .platform_data = &s5p6440_i2s_pdata,
+        },
+};
+
+static int s5p6450_cfg_i2s(struct platform_device *pdev)
+{
+        switch (pdev->id) {
+        case 0:
+                s3c_gpio_cfgpin_range(S5P6450_GPR(4), 5, S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin_range(S5P6450_GPR(13), 2, S3C_GPIO_SFN(5));
+                break;
+        case 1:
+                s3c_gpio_cfgpin(S5P6440_GPB(4), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin_range(S5P6450_GPC(0), 4, S3C_GPIO_SFN(5));
+                break;
+        case 2:
+                s3c_gpio_cfgpin_range(S5P6450_GPK(0), 5, S3C_GPIO_SFN(5));
+                break;
+        default:
+                printk(KERN_ERR "Invalid Device %d\n", pdev->id);
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static struct s3c_audio_pdata s5p6450_i2s0_pdata = {
+        .cfg_gpio = s5p6450_cfg_i2s,
+        .type = {
+                .i2s = {
+                        .quirks = QUIRK_PRI_6CHAN,
+                        .src_clk = rclksrc,
+                },
         },
 };
 
 struct platform_device s5p6450_device_iis0 = {
         .name           = "samsung-i2s",
         .id             = 0,
-        .num_resources  = ARRAY_SIZE(s5p64x0_iis0_resource),
-        .resource       = s5p64x0_iis0_resource,
+        .num_resources  = ARRAY_SIZE(s5p64x0_i2s0_resource),
+        .resource       = s5p64x0_i2s0_resource,
+        .dev = {
+                .platform_data = &s5p6450_i2s0_pdata,
+        },
+};
+
+static struct s3c_audio_pdata s5p6450_i2s_pdata = {
+        .cfg_gpio = s5p6450_cfg_i2s,
+        .type = {
+                .i2s = {
+                        .src_clk = rclksrc,
+                },
+        },
+};
+
+static struct resource s5p6450_i2s1_resource[] = {
+        [0] = {
+                .start  = S5P6450_PA_I2S1,
+                .end    = S5P6450_PA_I2S1 + 0x100 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = DMACH_I2S1_TX,
+                .end    = DMACH_I2S1_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start  = DMACH_I2S1_RX,
+                .end    = DMACH_I2S1_RX,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+struct platform_device s5p6450_device_iis1 = {
+        .name           = "samsung-i2s",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(s5p6450_i2s1_resource),
+        .resource       = s5p6450_i2s1_resource,
+        .dev = {
+                .platform_data = &s5p6450_i2s_pdata,
+        },
+};
+
+static struct resource s5p6450_i2s2_resource[] = {
+        [0] = {
+                .start  = S5P6450_PA_I2S2,
+                .end    = S5P6450_PA_I2S2 + 0x100 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = DMACH_I2S2_TX,
+                .end    = DMACH_I2S2_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start  = DMACH_I2S2_RX,
+                .end    = DMACH_I2S2_RX,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+struct platform_device s5p6450_device_iis2 = {
+        .name           = "samsung-i2s",
+        .id             = 2,
+        .num_resources  = ARRAY_SIZE(s5p6450_i2s2_resource),
+        .resource       = s5p6450_i2s2_resource,
         .dev = {
-                .platform_data = &s5p64x0_i2s_pdata,
+                .platform_data = &s5p6450_i2s_pdata,
         },
 };
 
diff --git a/arch/arm/mach-s5p64x0/gpio.c b/arch/arm/mach-s5p64x0/gpiolib.c
index 39159dd5a29a..e7fb3b004e77 100644
--- a/arch/arm/mach-s5p64x0/gpio.c
+++ b/arch/arm/mach-s5p64x0/gpiolib.c
@@ -1,4 +1,4 @@
-/* linux/arch/arm/mach-s5p64x0/gpio.c
+/* linux/arch/arm/mach-s5p64x0/gpiolib.c
  *
  * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
@@ -17,13 +17,12 @@
 
 #include <mach/map.h>
 #include <mach/regs-gpio.h>
+#include <mach/regs-clock.h>
 
 #include <plat/gpio-core.h>
 #include <plat/gpio-cfg.h>
 #include <plat/gpio-cfg-helpers.h>
 
-/* To be implemented S5P6450 GPIO */
-
 /*
  * S5P6440 GPIO bank summary:
  *
@@ -40,6 +39,25 @@
  * P    8       2Bit    Yes     8
  * R    15      4Bit[2] Yes     8
  *
+ * S5P6450 GPIO bank summary:
+ *
+ * Bank GPIOs   Style   SlpCon  ExtInt Group
+ * A    6       4Bit    Yes     1
+ * B    7       4Bit    Yes     1
+ * C    8       4Bit    Yes     2
+ * D    8       4Bit    Yes     None
+ * F    2       2Bit    Yes     None
+ * G    14      4Bit[2] Yes     5
+ * H    10      4Bit[2] Yes     6
+ * I    16      2Bit    Yes     None
+ * J    12      2Bit    Yes     None
+ * K    5       4Bit    Yes     None
+ * N    16      2Bit    No      IRQ_EINT
+ * P    11      2Bit    Yes     8
+ * Q    14      2Bit    Yes     None
+ * R    15      4Bit[2] Yes     None
+ * S    8       2Bit    Yes     None
+ *
  * [1] BANKF pins 14,15 do not form part of the external interrupt sources
  * [2] BANK has two control registers, GPxCON0 and GPxCON1
  */
@@ -190,7 +208,7 @@ static struct s3c_gpio_cfg s5p64x0_gpio_cfgs[] = {
 
 static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
         {
-                .base   = S5P6440_GPA_BASE,
+                .base   = S5P64X0_GPA_BASE,
                 .config = &s5p64x0_gpio_cfgs[1],
                 .chip   = {
                         .base   = S5P6440_GPA(0),
@@ -198,7 +216,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
                         .label  = "GPA",
                 },
         }, {
-                .base   = S5P6440_GPB_BASE,
+                .base   = S5P64X0_GPB_BASE,
                 .config = &s5p64x0_gpio_cfgs[1],
                 .chip   = {
                         .base   = S5P6440_GPB(0),
@@ -206,7 +224,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
                         .label  = "GPB",
                 },
         }, {
-                .base   = S5P6440_GPC_BASE,
+                .base   = S5P64X0_GPC_BASE,
                 .config = &s5p64x0_gpio_cfgs[1],
                 .chip   = {
                         .base   = S5P6440_GPC(0),
@@ -214,7 +232,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
                         .label  = "GPC",
                 },
         }, {
-                .base   = S5P6440_GPG_BASE,
+                .base   = S5P64X0_GPG_BASE,
                 .config = &s5p64x0_gpio_cfgs[1],
                 .chip   = {
                         .base   = S5P6440_GPG(0),
@@ -226,7 +244,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
 
 static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
         {
-                .base   = S5P6440_GPH_BASE + 0x4,
+                .base   = S5P64X0_GPH_BASE + 0x4,
                 .config = &s5p64x0_gpio_cfgs[1],
                 .chip   = {
                         .base   = S5P6440_GPH(0),
@@ -238,7 +256,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
 
 static struct s3c_gpio_chip s5p6440_gpio_rbank_4bit2[] = {
         {
-                .base   = S5P6440_GPR_BASE + 0x4,
+                .base   = S5P64X0_GPR_BASE + 0x4,
                 .config = &s5p64x0_gpio_cfgs[2],
                 .chip   = {
                         .base   = S5P6440_GPR(0),
@@ -250,7 +268,7 @@ static struct s3c_gpio_chip s5p6440_gpio_rbank_4bit2[] = {
 
 static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
         {
-                .base   = S5P6440_GPF_BASE,
+                .base   = S5P64X0_GPF_BASE,
                 .config = &s5p64x0_gpio_cfgs[5],
                 .chip   = {
                         .base   = S5P6440_GPF(0),
@@ -258,7 +276,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
                         .label  = "GPF",
                 },
         }, {
-                .base   = S5P6440_GPI_BASE,
+                .base   = S5P64X0_GPI_BASE,
                 .config = &s5p64x0_gpio_cfgs[3],
                 .chip   = {
                         .base   = S5P6440_GPI(0),
@@ -266,7 +284,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
                         .label  = "GPI",
                 },
         }, {
-                .base   = S5P6440_GPJ_BASE,
+                .base   = S5P64X0_GPJ_BASE,
                 .config = &s5p64x0_gpio_cfgs[3],
                 .chip   = {
                         .base   = S5P6440_GPJ(0),
@@ -274,7 +292,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
                         .label  = "GPJ",
                 },
         }, {
-                .base   = S5P6440_GPN_BASE,
+                .base   = S5P64X0_GPN_BASE,
                 .config = &s5p64x0_gpio_cfgs[4],
                 .chip   = {
                         .base   = S5P6440_GPN(0),
@@ -282,7 +300,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
                         .label  = "GPN",
                 },
         }, {
-                .base   = S5P6440_GPP_BASE,
+                .base   = S5P64X0_GPP_BASE,
                 .config = &s5p64x0_gpio_cfgs[5],
                 .chip   = {
                         .base   = S5P6440_GPP(0),
@@ -292,6 +310,142 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
         },
 };
 
+static struct s3c_gpio_chip s5p6450_gpio_4bit[] = {
+        {
+                .base   = S5P64X0_GPA_BASE,
+                .config = &s5p64x0_gpio_cfgs[1],
+                .chip   = {
+                        .base   = S5P6450_GPA(0),
+                        .ngpio  = S5P6450_GPIO_A_NR,
+                        .label  = "GPA",
+                },
+        }, {
+                .base   = S5P64X0_GPB_BASE,
+                .config = &s5p64x0_gpio_cfgs[1],
+                .chip   = {
+                        .base   = S5P6450_GPB(0),
+                        .ngpio  = S5P6450_GPIO_B_NR,
+                        .label  = "GPB",
+                },
+        }, {
+                .base   = S5P64X0_GPC_BASE,
+                .config = &s5p64x0_gpio_cfgs[1],
+                .chip   = {
+                        .base   = S5P6450_GPC(0),
+                        .ngpio  = S5P6450_GPIO_C_NR,
+                        .label  = "GPC",
+                },
+        }, {
+                .base   = S5P6450_GPD_BASE,
+                .config = &s5p64x0_gpio_cfgs[1],
+                .chip   = {
+                        .base   = S5P6450_GPD(0),
+                        .ngpio  = S5P6450_GPIO_D_NR,
+                        .label  = "GPD",
+                },
+        }, {
+                .base   = S5P6450_GPK_BASE,
+                .config = &s5p64x0_gpio_cfgs[1],
+                .chip   = {
+                        .base   = S5P6450_GPK(0),
+                        .ngpio  = S5P6450_GPIO_K_NR,
+                        .label  = "GPK",
+                },
+        },
+};
+
+static struct s3c_gpio_chip s5p6450_gpio_4bit2[] = {
+        {
+                .base   = S5P64X0_GPG_BASE + 0x4,
+                .config = &s5p64x0_gpio_cfgs[1],
+                .chip   = {
+                        .base   = S5P6450_GPG(0),
+                        .ngpio  = S5P6450_GPIO_G_NR,
+                        .label  = "GPG",
+                },
+        }, {
+                .base   = S5P64X0_GPH_BASE + 0x4,
+                .config = &s5p64x0_gpio_cfgs[1],
+                .chip   = {
+                        .base   = S5P6450_GPH(0),
+                        .ngpio  = S5P6450_GPIO_H_NR,
+                        .label  = "GPH",
+                },
+        },
+};
+
+static struct s3c_gpio_chip s5p6450_gpio_rbank_4bit2[] = {
+        {
+                .base   = S5P64X0_GPR_BASE + 0x4,
+                .config = &s5p64x0_gpio_cfgs[2],
+                .chip   = {
+                        .base   = S5P6450_GPR(0),
+                        .ngpio  = S5P6450_GPIO_R_NR,
+                        .label  = "GPR",
+                },
+        },
+};
+
+static struct s3c_gpio_chip s5p6450_gpio_2bit[] = {
+        {
+                .base   = S5P64X0_GPF_BASE,
+                .config = &s5p64x0_gpio_cfgs[5],
+                .chip   = {
+                        .base   = S5P6450_GPF(0),
+                        .ngpio  = S5P6450_GPIO_F_NR,
+                        .label  = "GPF",
+                },
+        }, {
+                .base   = S5P64X0_GPI_BASE,
+                .config = &s5p64x0_gpio_cfgs[3],
+                .chip   = {
+                        .base   = S5P6450_GPI(0),
+                        .ngpio  = S5P6450_GPIO_I_NR,
+                        .label  = "GPI",
+                },
+        }, {
+                .base   = S5P64X0_GPJ_BASE,
+                .config = &s5p64x0_gpio_cfgs[3],
+                .chip   = {
+                        .base   = S5P6450_GPJ(0),
+                        .ngpio  = S5P6450_GPIO_J_NR,
+                        .label  = "GPJ",
+                },
+        }, {
+                .base   = S5P64X0_GPN_BASE,
+                .config = &s5p64x0_gpio_cfgs[4],
+                .chip   = {
+                        .base   = S5P6450_GPN(0),
+                        .ngpio  = S5P6450_GPIO_N_NR,
+                        .label  = "GPN",
+                },
+        }, {
+                .base   = S5P64X0_GPP_BASE,
+                .config = &s5p64x0_gpio_cfgs[5],
+                .chip   = {
+                        .base   = S5P6450_GPP(0),
+                        .ngpio  = S5P6450_GPIO_P_NR,
+                        .label  = "GPP",
+                },
+        }, {
+                .base   = S5P6450_GPQ_BASE,
+                .config = &s5p64x0_gpio_cfgs[4],
+                .chip   = {
+                        .base   = S5P6450_GPQ(0),
+                        .ngpio  = S5P6450_GPIO_Q_NR,
+                        .label  = "GPQ",
+                },
+        }, {
+                .base   = S5P6450_GPS_BASE,
+                .config = &s5p64x0_gpio_cfgs[5],
+                .chip   = {
+                        .base   = S5P6450_GPS(0),
+                        .ngpio  = S5P6450_GPIO_S_NR,
+                        .label  = "GPS",
+                },
+        },
+};
+
 void __init s5p64x0_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
 {
         for (; nr_chips > 0; nr_chips--, chipcfg++) {
@@ -317,26 +471,41 @@ static void __init s5p64x0_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip,
         }
 }
 
-static int __init s5p6440_gpiolib_init(void)
+static int __init s5p64x0_gpiolib_init(void)
 {
-        struct s3c_gpio_chip *chips = s5p6440_gpio_2bit;
-        int nr_chips = ARRAY_SIZE(s5p6440_gpio_2bit);
+        unsigned int chipid;
+
+        chipid = __raw_readl(S5P64X0_SYS_ID);
 
         s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs,
                                 ARRAY_SIZE(s5p64x0_gpio_cfgs));
 
-        for (; nr_chips > 0; nr_chips--, chips++)
-                s3c_gpiolib_add(chips);
+        if ((chipid & 0xff000) == 0x50000) {
+                samsung_gpiolib_add_2bit_chips(s5p6450_gpio_2bit,
+                                        ARRAY_SIZE(s5p6450_gpio_2bit));
+
+                samsung_gpiolib_add_4bit_chips(s5p6450_gpio_4bit,
+                                        ARRAY_SIZE(s5p6450_gpio_4bit));
 
-        samsung_gpiolib_add_4bit_chips(s5p6440_gpio_4bit,
-                                ARRAY_SIZE(s5p6440_gpio_4bit));
+                samsung_gpiolib_add_4bit2_chips(s5p6450_gpio_4bit2,
+                                        ARRAY_SIZE(s5p6450_gpio_4bit2));
 
-        samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2,
-                                ARRAY_SIZE(s5p6440_gpio_4bit2));
+                s5p64x0_gpio_add_rbank_4bit2(s5p6450_gpio_rbank_4bit2,
+                                        ARRAY_SIZE(s5p6450_gpio_rbank_4bit2));
+        } else {
+                samsung_gpiolib_add_2bit_chips(s5p6440_gpio_2bit,
+                                        ARRAY_SIZE(s5p6440_gpio_2bit));
 
-        s5p64x0_gpio_add_rbank_4bit2(s5p6440_gpio_rbank_4bit2,
-                                ARRAY_SIZE(s5p6440_gpio_rbank_4bit2));
+                samsung_gpiolib_add_4bit_chips(s5p6440_gpio_4bit,
+                                        ARRAY_SIZE(s5p6440_gpio_4bit));
+
+                samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2,
+                                        ARRAY_SIZE(s5p6440_gpio_4bit2));
+
+                s5p64x0_gpio_add_rbank_4bit2(s5p6440_gpio_rbank_4bit2,
+                                        ARRAY_SIZE(s5p6440_gpio_rbank_4bit2));
+        }
 
         return 0;
 }
-arch_initcall(s5p6440_gpiolib_init);
+core_initcall(s5p64x0_gpiolib_init);
diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-s5p64x0/include/mach/map.h
index 31e534156e06..a9365e5ba614 100644
--- a/arch/arm/mach-s5p64x0/include/mach/map.h
+++ b/arch/arm/mach-s5p64x0/include/mach/map.h
@@ -29,6 +29,9 @@
 #define S5P64X0_PA_VIC0         (0xE4000000)
 #define S5P64X0_PA_VIC1         (0xE4100000)
 
+#define S5P64X0_PA_SROMC        (0xE7000000)
+#define S5P_PA_SROMC            S5P64X0_PA_SROMC
+
 #define S5P64X0_PA_PDMA         (0xE9000000)
 
 #define S5P64X0_PA_TIMER        (0xEA000000)
@@ -63,6 +66,8 @@
 #define S5P64X0_PA_HSMMC(x)     (0xED800000 + ((x) * 0x100000))
 
 #define S5P64X0_PA_I2S          (0xF2000000)
+#define S5P6450_PA_I2S1         0xF2800000
+#define S5P6450_PA_I2S2         0xF2900000
 
 #define S5P64X0_PA_PCM          (0xF2100000)
 
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
index 85f448e20a8b..0953ef6b1c77 100644
--- a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
@@ -15,48 +15,23 @@
 
 #include <mach/map.h>
 
-/* Will be implemented S5P6442 GPIOlib */
-
 /* Base addresses for each of the banks */
 
-#define S5P6440_GPA_BASE                (S5P_VA_GPIO + 0x0000)
-#define S5P6440_GPB_BASE                (S5P_VA_GPIO + 0x0020)
-#define S5P6440_GPC_BASE                (S5P_VA_GPIO + 0x0040)
-#define S5P6440_GPF_BASE                (S5P_VA_GPIO + 0x00A0)
-#define S5P6440_GPG_BASE                (S5P_VA_GPIO + 0x00C0)
-#define S5P6440_GPH_BASE                (S5P_VA_GPIO + 0x00E0)
-#define S5P6440_GPI_BASE                (S5P_VA_GPIO + 0x0100)
-#define S5P6440_GPJ_BASE                (S5P_VA_GPIO + 0x0120)
-#define S5P6440_GPN_BASE                (S5P_VA_GPIO + 0x0830)
-#define S5P6440_GPP_BASE                (S5P_VA_GPIO + 0x0160)
-#define S5P6440_GPR_BASE                (S5P_VA_GPIO + 0x0290)
-
-#define S5P6440_EINT0CON0               (S5P_VA_GPIO + 0x900)
-#define S5P6440_EINT0FLTCON0            (S5P_VA_GPIO + 0x910)
-#define S5P6440_EINT0FLTCON1            (S5P_VA_GPIO + 0x914)
-#define S5P6440_EINT0MASK               (S5P_VA_GPIO + 0x920)
-#define S5P6440_EINT0PEND               (S5P_VA_GPIO + 0x924)
-
-/* for LCD */
-
-#define S5P6440_SPCON_LCD_SEL_RGB       (1 << 0)
-#define S5P6440_SPCON_LCD_SEL_MASK      (3 << 0)
-
-/*
- * These set of macros are not really useful for the
- * GPF/GPI/GPJ/GPN/GPP, useful for others set of GPIO's (4 bit)
- */
-
-#define S5P6440_GPIO_CONMASK(__gpio)    (0xf << ((__gpio) * 4))
-#define S5P6440_GPIO_INPUT(__gpio)      (0x0 << ((__gpio) * 4))
-#define S5P6440_GPIO_OUTPUT(__gpio)     (0x1 << ((__gpio) * 4))
-
-/*
- * Use these macros for GPF/GPI/GPJ/GPN/GPP set of GPIO (2 bit)
- */
-
-#define S5P6440_GPIO2_CONMASK(__gpio)   (0x3 << ((__gpio) * 2))
-#define S5P6440_GPIO2_INPUT(__gpio)     (0x0 << ((__gpio) * 2))
-#define S5P6440_GPIO2_OUTPUT(__gpio)    (0x1 << ((__gpio) * 2))
+#define S5P64X0_GPA_BASE                (S5P_VA_GPIO + 0x0000)
+#define S5P64X0_GPB_BASE                (S5P_VA_GPIO + 0x0020)
+#define S5P64X0_GPC_BASE                (S5P_VA_GPIO + 0x0040)
+#define S5P64X0_GPF_BASE                (S5P_VA_GPIO + 0x00A0)
+#define S5P64X0_GPG_BASE                (S5P_VA_GPIO + 0x00C0)
+#define S5P64X0_GPH_BASE                (S5P_VA_GPIO + 0x00E0)
+#define S5P64X0_GPI_BASE                (S5P_VA_GPIO + 0x0100)
+#define S5P64X0_GPJ_BASE                (S5P_VA_GPIO + 0x0120)
+#define S5P64X0_GPN_BASE                (S5P_VA_GPIO + 0x0830)
+#define S5P64X0_GPP_BASE                (S5P_VA_GPIO + 0x0160)
+#define S5P64X0_GPR_BASE                (S5P_VA_GPIO + 0x0290)
+
+#define S5P6450_GPD_BASE                (S5P_VA_GPIO + 0x0060)
+#define S5P6450_GPK_BASE                (S5P_VA_GPIO + 0x0140)
+#define S5P6450_GPQ_BASE                (S5P_VA_GPIO + 0x0180)
+#define S5P6450_GPS_BASE                (S5P_VA_GPIO + 0x0300)
 
 #endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index 87c3f03c618c..e9802755daeb 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -117,6 +117,7 @@ static struct s3c2410_platform_i2c s5p6440_i2c1_data __initdata = {
 
 static struct i2c_board_info smdk6440_i2c_devs0[] __initdata = {
         { I2C_BOARD_INFO("24c08", 0x50), },
+        { I2C_BOARD_INFO("wm8580", 0x1b), },
 };
 
 static struct i2c_board_info smdk6440_i2c_devs1[] __initdata = {
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index d609f5af2b98..b78f56292780 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -135,6 +135,7 @@ static struct s3c2410_platform_i2c s5p6450_i2c1_data __initdata = {
 };
 
 static struct i2c_board_info smdk6450_i2c_devs0[] __initdata = {
+        { I2C_BOARD_INFO("wm8580", 0x1b), },
         { I2C_BOARD_INFO("24c08", 0x50), },     /* Samsung KS24C080C EEPROM */
 };
 
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index 2d4a761a5163..0305e9b8282d 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -396,7 +396,7 @@ static int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
  * recommended to keep the following clocks disabled until the driver requests
  * for enabling the clock.
  */
-static struct clk init_clocks_disable[] = {
+static struct clk init_clocks_off[] = {
         {
                 .name           = "cssys",
                 .id             = -1,
@@ -1381,8 +1381,6 @@ static struct clk *clks[] __initdata = {
 
 void __init s5pc100_register_clocks(void)
 {
-        struct clk *clkp;
-        int ret;
         int ptr;
 
         s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
@@ -1393,16 +1391,8 @@ void __init s5pc100_register_clocks(void)
         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
 
-        clkp = init_clocks_disable;
-        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
-
-                ret = s3c24xx_register_clock(clkp);
-                if (ret < 0) {
-                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
-                               clkp->name, ret);
-                }
-                (clkp->enable)(clkp, 0);
-        }
+        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 
         s3c_pwmclk_init();
 }
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index 32e9cab5c864..328467b346aa 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -55,6 +55,8 @@
 #define S5PC100_VA_VIC_OFFSET   0x10000
 #define S5PC1XX_VA_VIC(x)       (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET))
 
+#define S5PC100_PA_SROMC        (0xE7000000)
+#define S5P_PA_SROMC            S5PC100_PA_SROMC
 
 #define S5PC100_PA_ONENAND      (0xE7100000)
 
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 862f239a0fdb..53aabef1e9ce 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -118,6 +118,7 @@ menu "S5PV210 Machines"
 config MACH_SMDKV210
         bool "SMDKV210"
         select CPU_S5PV210
+        select S3C_DEV_FB
         select S3C_DEV_HSMMC
         select S3C_DEV_HSMMC1
         select S3C_DEV_HSMMC2
@@ -130,6 +131,7 @@ config MACH_SMDKV210
         select SAMSUNG_DEV_IDE
         select SAMSUNG_DEV_KEYPAD
         select SAMSUNG_DEV_TS
+        select S5PV210_SETUP_FB_24BPP
         select S5PV210_SETUP_I2C1
         select S5PV210_SETUP_I2C2
         select S5PV210_SETUP_IDE
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index b774ff1805db..2d599499cefe 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -309,7 +309,7 @@ static struct clk_ops clk_fout_apll_ops = {
         .get_rate       = s5pv210_clk_fout_apll_get_rate,
 };
 
-static struct clk init_clocks_disable[] = {
+static struct clk init_clocks_off[] = {
         {
                 .name           = "pdma",
                 .id             = 0,
@@ -525,6 +525,12 @@ static struct clk init_clocks[] = {
                 .parent         = &clk_pclk_psys.clk,
                 .enable         = s5pv210_clk_ip3_ctrl,
                 .ctrlbit        = (1 << 20),
+        }, {
+                .name           = "sromc",
+                .id             = -1,
+                .parent         = &clk_hclk_psys.clk,
+                .enable         = s5pv210_clk_ip1_ctrl,
+                .ctrlbit        = (1 << 26),
         },
 };
 
@@ -1220,13 +1226,9 @@ static struct clk *clks[] __initdata = {
 
 void __init s5pv210_register_clocks(void)
 {
-        struct clk *clkp;
-        int ret;
         int ptr;
 
-        ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
-        if (ret > 0)
-                printk(KERN_ERR "Failed to register %u clocks\n", ret);
+        s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
 
         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
                 s3c_register_clksrc(sysclks[ptr], 1);
@@ -1234,15 +1236,8 @@ void __init s5pv210_register_clocks(void)
         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
 
-        clkp = init_clocks_disable;
-        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
-                ret = s3c24xx_register_clock(clkp);
-                if (ret < 0) {
-                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
-                               clkp->name, ret);
-                }
-                (clkp->enable)(clkp, 0);
-        }
+        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 
         s3c_pwmclk_init();
 }
diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c
index 8eb480e201b0..61e6c24b90ac 100644
--- a/arch/arm/mach-s5pv210/cpu.c
+++ b/arch/arm/mach-s5pv210/cpu.c
@@ -81,11 +81,6 @@ static struct map_desc s5pv210_iodesc[] __initdata = {
                 .length         = SZ_512K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = (unsigned long)S5P_VA_SROMC,
-                .pfn            = __phys_to_pfn(S5PV210_PA_SROMC),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
                 .virtual        = (unsigned long)S5P_VA_DMC0,
                 .pfn            = __phys_to_pfn(S5PV210_PA_DMC0),
                 .length         = SZ_4K,
diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h
index 119b95fdc3ce..26710b35ef87 100644
--- a/arch/arm/mach-s5pv210/include/mach/irqs.h
+++ b/arch/arm/mach-s5pv210/include/mach/irqs.h
@@ -65,7 +65,7 @@
 #define IRQ_HSMMC0              S5P_IRQ_VIC1(26)
 #define IRQ_HSMMC1              S5P_IRQ_VIC1(27)
 #define IRQ_HSMMC2              S5P_IRQ_VIC1(28)
-#define IRQ_MIPICSI             S5P_IRQ_VIC1(29)
+#define IRQ_MIPI_CSIS           S5P_IRQ_VIC1(29)
 #define IRQ_MIPIDSI             S5P_IRQ_VIC1(30)
 #define IRQ_ONENAND_AUDI        S5P_IRQ_VIC1(31)
 
@@ -132,5 +132,6 @@
 #define IRQ_LCD_FIFO            IRQ_LCD0
 #define IRQ_LCD_VSYNC           IRQ_LCD1
 #define IRQ_LCD_SYSTEM          IRQ_LCD2
+#define IRQ_MIPI_CSIS0          IRQ_MIPI_CSIS
 
 #endif /* ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index 861d7fe11fc9..3611492ad681 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -16,6 +16,8 @@
 #include <plat/map-base.h>
 #include <plat/map-s5p.h>
 
+#define S5PV210_PA_SROM_BANK5   (0xA8000000)
+
 #define S5PC110_PA_ONENAND      (0xB0000000)
 #define S5P_PA_ONENAND          S5PC110_PA_ONENAND
 
@@ -60,6 +62,7 @@
 #define S3C_VA_UARTx(x)         (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
 
 #define S5PV210_PA_SROMC        (0xE8000000)
+#define S5P_PA_SROMC            S5PV210_PA_SROMC
 
 #define S5PV210_PA_CFCON        (0xE8200000)
 
@@ -107,6 +110,8 @@
 #define S5PV210_PA_DMC0         (0xF0000000)
 #define S5PV210_PA_DMC1         (0xF1400000)
 
+#define S5PV210_PA_MIPI_CSIS    0xFA600000
+
 /* compatibiltiy defines. */
 #define S3C_PA_UART             S5PV210_PA_UART
 #define S3C_PA_HSMMC0           S5PV210_PA_HSMMC(0)
@@ -123,6 +128,7 @@
 #define S5P_PA_FIMC0            S5PV210_PA_FIMC0
 #define S5P_PA_FIMC1            S5PV210_PA_FIMC1
 #define S5P_PA_FIMC2            S5PV210_PA_FIMC2
+#define S5P_PA_MIPI_CSIS0       S5PV210_PA_MIPI_CSIS
 
 #define SAMSUNG_PA_ADC          S5PV210_PA_ADC
 #define SAMSUNG_PA_CFCON        S5PV210_PA_CFCON
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
index ebaabe021af9..4c45b74def5f 100644
--- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
@@ -161,7 +161,7 @@
 #define S5P_MDNIE_SEL           S5P_CLKREG(0x7008)
 #define S5P_MIPI_PHY_CON0       S5P_CLKREG(0x7200)
 #define S5P_MIPI_PHY_CON1       S5P_CLKREG(0x7204)
-#define S5P_MIPI_CONTROL        S5P_CLKREG(0xE814)
+#define S5P_MIPI_DPHY_CONTROL   S5P_CLKREG(0xE814)
 
 #define S5P_IDLE_CFG_TL_MASK    (3 << 30)
 #define S5P_IDLE_CFG_TM_MASK    (3 << 28)
@@ -195,9 +195,6 @@
 #define S5P_OTHERS_RET_UART             (1 << 28)
 #define S5P_OTHERS_USB_SIG_MASK         (1 << 16)
 
-/* MIPI */
-#define S5P_MIPI_DPHY_EN                (3)
-
 /* S5P_DAC_CONTROL */
 #define S5P_DAC_ENABLE                  (1)
 #define S5P_DAC_DISABLE                 (0)
diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c
index 5dd1681c069e..bb20a14da100 100644
--- a/arch/arm/mach-s5pv210/mach-smdkc110.c
+++ b/arch/arm/mach-s5pv210/mach-smdkc110.c
@@ -94,6 +94,7 @@ static struct platform_device *smdkc110_devices[] __initdata = {
 
 static struct i2c_board_info smdkc110_i2c_devs0[] __initdata = {
         { I2C_BOARD_INFO("24c08", 0x50), },     /* Samsung S524AD0XD1 */
+        { I2C_BOARD_INFO("wm8580", 0x1b), },
 };
 
 static struct i2c_board_info smdkc110_i2c_devs1[] __initdata = {
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index 1fbc45b2a432..88e45223c8af 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -14,16 +14,25 @@
 #include <linux/init.h>
 #include <linux/serial_core.h>
 #include <linux/sysdev.h>
+#include <linux/dm9000.h>
+#include <linux/fb.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 
+#include <video/platform_lcd.h>
+
 #include <mach/map.h>
 #include <mach/regs-clock.h>
+#include <mach/regs-fb.h>
 
 #include <plat/regs-serial.h>
+#include <plat/regs-srom.h>
+#include <plat/gpio-cfg.h>
 #include <plat/s5pv210.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
@@ -33,6 +42,7 @@
 #include <plat/iic.h>
 #include <plat/keypad.h>
 #include <plat/pm.h>
+#include <plat/fb.h>
 
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define SMDKV210_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
@@ -102,12 +112,106 @@ static struct samsung_keypad_platdata smdkv210_keypad_data __initdata = {
         .cols           = 8,
 };
 
+static struct resource smdkv210_dm9000_resources[] = {
+        [0] = {
+                .start  = S5PV210_PA_SROM_BANK5,
+                .end    = S5PV210_PA_SROM_BANK5,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = S5PV210_PA_SROM_BANK5 + 2,
+                .end    = S5PV210_PA_SROM_BANK5 + 2,
+                .flags  = IORESOURCE_MEM,
+        },
+        [2] = {
+                .start  = IRQ_EINT(9),
+                .end    = IRQ_EINT(9),
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
+        },
+};
+
+static struct dm9000_plat_data smdkv210_dm9000_platdata = {
+        .flags          = DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM,
+        .dev_addr       = { 0x00, 0x09, 0xc0, 0xff, 0xec, 0x48 },
+};
+
+struct platform_device smdkv210_dm9000 = {
+        .name           = "dm9000",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(smdkv210_dm9000_resources),
+        .resource       = smdkv210_dm9000_resources,
+        .dev            = {
+                .platform_data  = &smdkv210_dm9000_platdata,
+        },
+};
+
+static void smdkv210_lte480wv_set_power(struct plat_lcd_data *pd,
+                                        unsigned int power)
+{
+        if (power) {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+                gpio_request(S5PV210_GPD0(3), "GPD0");
+                gpio_direction_output(S5PV210_GPD0(3), 1);
+                gpio_free(S5PV210_GPD0(3));
+#endif
+
+                /* fire nRESET on power up */
+                gpio_request(S5PV210_GPH0(6), "GPH0");
+
+                gpio_direction_output(S5PV210_GPH0(6), 1);
+
+                gpio_set_value(S5PV210_GPH0(6), 0);
+                mdelay(10);
+
+                gpio_set_value(S5PV210_GPH0(6), 1);
+                mdelay(10);
+
+                gpio_free(S5PV210_GPH0(6));
+        } else {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+                gpio_request(S5PV210_GPD0(3), "GPD0");
+                gpio_direction_output(S5PV210_GPD0(3), 0);
+                gpio_free(S5PV210_GPD0(3));
+#endif
+        }
+}
+
+static struct plat_lcd_data smdkv210_lcd_lte480wv_data = {
+        .set_power      = smdkv210_lte480wv_set_power,
+};
+
+static struct platform_device smdkv210_lcd_lte480wv = {
+        .name                   = "platform-lcd",
+        .dev.parent             = &s3c_device_fb.dev,
+        .dev.platform_data      = &smdkv210_lcd_lte480wv_data,
+};
+
+static struct s3c_fb_pd_win smdkv210_fb_win0 = {
+        .win_mode = {
+                .left_margin    = 13,
+                .right_margin   = 8,
+                .upper_margin   = 7,
+                .lower_margin   = 5,
+                .hsync_len      = 3,
+                .vsync_len      = 1,
+                .xres           = 800,
+                .yres           = 480,
+        },
+        .max_bpp        = 32,
+        .default_bpp    = 24,
+};
+
+static struct s3c_fb_platdata smdkv210_lcd0_pdata __initdata = {
+        .win[0]         = &smdkv210_fb_win0,
+        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+        .setup_gpio     = s5pv210_fb_gpio_setup_24bpp,
+};
+
 static struct platform_device *smdkv210_devices[] __initdata = {
-        &s5pv210_device_iis0,
-        &s5pv210_device_ac97,
-        &s5pv210_device_spdif,
         &s3c_device_adc,
         &s3c_device_cfcon,
+        &s3c_device_fb,
         &s3c_device_hsmmc0,
         &s3c_device_hsmmc1,
         &s3c_device_hsmmc2,
@@ -115,14 +219,37 @@ static struct platform_device *smdkv210_devices[] __initdata = {
         &s3c_device_i2c0,
         &s3c_device_i2c1,
         &s3c_device_i2c2,
-        &samsung_device_keypad,
         &s3c_device_rtc,
         &s3c_device_ts,
         &s3c_device_wdt,
+        &s5pv210_device_ac97,
+        &s5pv210_device_iis0,
+        &s5pv210_device_spdif,
+        &samsung_device_keypad,
+        &smdkv210_dm9000,
+        &smdkv210_lcd_lte480wv,
 };
 
+static void __init smdkv210_dm9000_init(void)
+{
+        unsigned int tmp;
+
+        gpio_request(S5PV210_MP01(5), "nCS5");
+        s3c_gpio_cfgpin(S5PV210_MP01(5), S3C_GPIO_SFN(2));
+        gpio_free(S5PV210_MP01(5));
+
+        tmp = (5 << S5P_SROM_BCX__TACC__SHIFT);
+        __raw_writel(tmp, S5P_SROM_BC5);
+
+        tmp = __raw_readl(S5P_SROM_BW);
+        tmp &= (S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS5__SHIFT);
+        tmp |= (1 << S5P_SROM_BW__NCS5__SHIFT);
+        __raw_writel(tmp, S5P_SROM_BW);
+}
+
 static struct i2c_board_info smdkv210_i2c_devs0[] __initdata = {
         { I2C_BOARD_INFO("24c08", 0x50), },     /* Samsung S524AD0XD1 */
+        { I2C_BOARD_INFO("wm8580", 0x1b), },
 };
 
 static struct i2c_board_info smdkv210_i2c_devs1[] __initdata = {
@@ -150,6 +277,8 @@ static void __init smdkv210_machine_init(void)
 {
         s3c_pm_init();
 
+        smdkv210_dm9000_init();
+
         samsung_keypad_set_platdata(&smdkv210_keypad_data);
         s3c24xx_ts_set_platdata(&s3c_ts_platform);
 
@@ -165,6 +294,8 @@ static void __init smdkv210_machine_init(void)
 
         s3c_ide_set_platdata(&smdkv210_ide_pdata);
 
+        s3c_fb_set_platdata(&smdkv210_lcd0_pdata);
+
         platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices));
 }
 
diff --git a/arch/arm/mach-s5pv310/Kconfig b/arch/arm/mach-s5pv310/Kconfig
index d64efe0d4c97..09c4c21b70cc 100644
--- a/arch/arm/mach-s5pv310/Kconfig
+++ b/arch/arm/mach-s5pv310/Kconfig
@@ -15,6 +15,11 @@ config CPU_S5PV310
         help
           Enable S5PV310 CPU support
 
+config S5PV310_DEV_PD
+        bool
+        help
+          Compile in platform device definitions for Power Domain
+
 config S5PV310_SETUP_I2C1
         bool
         help
@@ -61,6 +66,11 @@ config S5PV310_SETUP_SDHCI_GPIO
         help
           Common setup code for SDHCI gpio.
 
+config S5PV310_DEV_SYSMMU
+        bool
+        help
+          Common setup code for SYSTEM MMU in S5PV310
+
 # machine support
 
 menu "S5PC210 Machines"
@@ -70,11 +80,15 @@ config MACH_SMDKC210
         select CPU_S5PV310
         select S3C_DEV_RTC
         select S3C_DEV_WDT
+        select S3C_DEV_I2C1
         select S3C_DEV_HSMMC
         select S3C_DEV_HSMMC1
         select S3C_DEV_HSMMC2
         select S3C_DEV_HSMMC3
+        select S5PV310_DEV_PD
+        select S5PV310_SETUP_I2C1
         select S5PV310_SETUP_SDHCI
+        select S5PV310_DEV_SYSMMU
         help
           Machine support for Samsung SMDKC210
           S5PC210(MCP) is one of package option of S5PV310
@@ -83,6 +97,10 @@ config MACH_UNIVERSAL_C210
         bool "Mobile UNIVERSAL_C210 Board"
         select CPU_S5PV310
         select S5P_DEV_ONENAND
+        select S3C_DEV_HSMMC
+        select S3C_DEV_HSMMC2
+        select S3C_DEV_HSMMC3
+        select S5PV310_SETUP_SDHCI
         select S3C_DEV_I2C1
         select S5PV310_SETUP_I2C1
         help
@@ -98,10 +116,13 @@ config MACH_SMDKV310
         select CPU_S5PV310
         select S3C_DEV_RTC
         select S3C_DEV_WDT
+        select S3C_DEV_I2C1
         select S3C_DEV_HSMMC
         select S3C_DEV_HSMMC1
         select S3C_DEV_HSMMC2
         select S3C_DEV_HSMMC3
+        select S5PV310_DEV_PD
+        select S5PV310_SETUP_I2C1
         select S5PV310_SETUP_SDHCI
         help
           Machine support for Samsung SMDKV310
diff --git a/arch/arm/mach-s5pv310/Makefile b/arch/arm/mach-s5pv310/Makefile
index 61e3cb654269..036fb383b830 100644
--- a/arch/arm/mach-s5pv310/Makefile
+++ b/arch/arm/mach-s5pv310/Makefile
@@ -14,6 +14,7 @@ obj-				:=
 
 obj-$(CONFIG_CPU_S5PV310)       += cpu.o init.o clock.o irq-combiner.o
 obj-$(CONFIG_CPU_S5PV310)       += setup-i2c0.o time.o gpiolib.o irq-eint.o dma.o
+obj-$(CONFIG_CPU_FREQ)          += cpufreq.o
 
 obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
 obj-$(CONFIG_LOCAL_TIMERS)      += localtimer.o
@@ -27,7 +28,10 @@ obj-$(CONFIG_MACH_UNIVERSAL_C210)	+= mach-universal_c210.o
 
 # device support
 
-obj-y += dev-audio.o
+obj-y                                   += dev-audio.o
+obj-$(CONFIG_S5PV310_DEV_PD)            += dev-pd.o
+obj-$(CONFIG_S5PV310_DEV_SYSMMU)        += dev-sysmmu.o
+
 obj-$(CONFIG_S5PV310_SETUP_I2C1)        += setup-i2c1.o
 obj-$(CONFIG_S5PV310_SETUP_I2C2)        += setup-i2c2.o
 obj-$(CONFIG_S5PV310_SETUP_I2C3)        += setup-i2c3.o
diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
index 58c9d33f36fe..fc7c2f8d165e 100644
--- a/arch/arm/mach-s5pv310/clock.c
+++ b/arch/arm/mach-s5pv310/clock.c
@@ -244,7 +244,7 @@ static struct clksrc_clk clk_mout_corebus = {
                 .id             = -1,
         },
         .sources        = &clkset_mout_corebus,
-        .reg_src        = { .reg = S5P_CLKSRC_CORE, .shift = 4, .size = 1 },
+        .reg_src        = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
 };
 
 static struct clksrc_clk clk_sclk_dmc = {
@@ -253,7 +253,7 @@ static struct clksrc_clk clk_sclk_dmc = {
                 .id             = -1,
                 .parent         = &clk_mout_corebus.clk,
         },
-        .reg_div        = { .reg = S5P_CLKDIV_CORE0, .shift = 12, .size = 3 },
+        .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
 };
 
 static struct clksrc_clk clk_aclk_cored = {
@@ -262,7 +262,7 @@ static struct clksrc_clk clk_aclk_cored = {
                 .id             = -1,
                 .parent         = &clk_sclk_dmc.clk,
         },
-        .reg_div        = { .reg = S5P_CLKDIV_CORE0, .shift = 16, .size = 3 },
+        .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
 };
 
 static struct clksrc_clk clk_aclk_corep = {
@@ -271,7 +271,7 @@ static struct clksrc_clk clk_aclk_corep = {
                 .id             = -1,
                 .parent         = &clk_aclk_cored.clk,
         },
-        .reg_div        = { .reg = S5P_CLKDIV_CORE0, .shift = 20, .size = 3 },
+        .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
 };
 
 static struct clksrc_clk clk_aclk_acp = {
@@ -280,7 +280,7 @@ static struct clksrc_clk clk_aclk_acp = {
                 .id             = -1,
                 .parent         = &clk_mout_corebus.clk,
         },
-        .reg_div        = { .reg = S5P_CLKDIV_CORE0, .shift = 0, .size = 3 },
+        .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
 };
 
 static struct clksrc_clk clk_pclk_acp = {
@@ -289,7 +289,7 @@ static struct clksrc_clk clk_pclk_acp = {
                 .id             = -1,
                 .parent         = &clk_aclk_acp.clk,
         },
-        .reg_div        = { .reg = S5P_CLKDIV_CORE0, .shift = 4, .size = 3 },
+        .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
 };
 
 /* Core list of CMU_TOP side */
@@ -384,7 +384,7 @@ static struct clksrc_clk clk_sclk_vpll = {
         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
 };
 
-static struct clk init_clocks_disable[] = {
+static struct clk init_clocks_off[] = {
         {
                 .name           = "timers",
                 .id             = -1,
@@ -467,6 +467,16 @@ static struct clk init_clocks_disable[] = {
                 .enable         = s5pv310_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 10),
         }, {
+                .name           = "pdma",
+                .id             = 0,
+                .enable         = s5pv310_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "pdma",
+                .id             = 1,
+                .enable         = s5pv310_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
                 .name           = "adc",
                 .id             = -1,
                 .enable         = s5pv310_clk_ip_peril_ctrl,
@@ -507,6 +517,26 @@ static struct clk init_clocks_disable[] = {
                 .enable         = s5pv310_clk_ip_peril_ctrl,
                 .ctrlbit        = (1 << 18),
         }, {
+                .name           = "iis",
+                .id             = 0,
+                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 19),
+        }, {
+                .name           = "iis",
+                .id             = 1,
+                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 20),
+        }, {
+                .name           = "iis",
+                .id             = 2,
+                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 21),
+        }, {
+                .name           = "ac97",
+                .id             = -1,
+                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 27),
+        }, {
                 .name           = "fimg2d",
                 .id             = -1,
                 .enable         = s5pv310_clk_ip_image_ctrl,
@@ -990,6 +1020,17 @@ static struct clksrc_clk *sysclks[] = {
         &clk_dout_mmc4,
 };
 
+static int xtal_rate;
+
+static unsigned long s5pv310_fout_apll_get_rate(struct clk *clk)
+{
+        return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508);
+}
+
+static struct clk_ops s5pv310_fout_apll_ops = {
+        .get_rate = s5pv310_fout_apll_get_rate,
+};
+
 void __init_or_cpufreq s5pv310_setup_clocks(void)
 {
         struct clk *xtal_clk;
@@ -1013,6 +1054,9 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
         BUG_ON(IS_ERR(xtal_clk));
 
         xtal = clk_get_rate(xtal_clk);
+
+        xtal_rate = xtal;
+
         clk_put(xtal_clk);
 
         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
@@ -1026,7 +1070,7 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
         vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
                                 __raw_readl(S5P_VPLL_CON1), pll_4650);
 
-        clk_fout_apll.rate = apll;
+        clk_fout_apll.ops = &s5pv310_fout_apll_ops;
         clk_fout_mpll.rate = mpll;
         clk_fout_epll.rate = epll;
         clk_fout_vpll.rate = vpll;
@@ -1061,13 +1105,9 @@ static struct clk *clks[] __initdata = {
 
 void __init s5pv310_register_clocks(void)
 {
-        struct clk *clkp;
-        int ret;
         int ptr;
 
-        ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
-        if (ret > 0)
-                printk(KERN_ERR "Failed to register %u clocks\n", ret);
+        s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
 
         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
                 s3c_register_clksrc(sysclks[ptr], 1);
@@ -1075,15 +1115,8 @@ void __init s5pv310_register_clocks(void)
         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
 
-        clkp = init_clocks_disable;
-        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
-                ret = s3c24xx_register_clock(clkp);
-                if (ret < 0) {
-                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
-                               clkp->name, ret);
-                }
-                (clkp->enable)(clkp, 0);
-        }
+        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 
         s3c_pwmclk_init();
 }
diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-s5pv310/cpu.c
index 72ab289e7816..0db0fb65bd70 100644
--- a/arch/arm/mach-s5pv310/cpu.c
+++ b/arch/arm/mach-s5pv310/cpu.c
@@ -41,6 +41,11 @@ static struct map_desc s5pv310_iodesc[] __initdata = {
                 .length         = SZ_128K,
                 .type           = MT_DEVICE,
         }, {
+                .virtual        = (unsigned long)S5P_VA_PMU,
+                .pfn            = __phys_to_pfn(S5PV310_PA_PMU),
+                .length         = SZ_64K,
+                .type           = MT_DEVICE,
+        }, {
                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
                 .pfn            = __phys_to_pfn(S5PV310_PA_COMBINER),
                 .length         = SZ_4K,
@@ -71,6 +76,11 @@ static struct map_desc s5pv310_iodesc[] __initdata = {
                 .length         = SZ_256,
                 .type           = MT_DEVICE,
         }, {
+                .virtual        = (unsigned long)S5P_VA_DMC0,
+                .pfn            = __phys_to_pfn(S5PV310_PA_DMC0),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
                 .virtual        = (unsigned long)S3C_VA_UART,
                 .pfn            = __phys_to_pfn(S3C_PA_UART),
                 .length         = SZ_512K,
@@ -123,6 +133,15 @@ void __init s5pv310_init_irq(void)
         gic_init(0, IRQ_LOCALTIMER, S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
 
         for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
+
+                /*
+                 * From SPI(0) to SPI(39) and SPI(51), SPI(53) are
+                 * connected to the interrupt combiner. These irqs
+                 * should be initialized to support cascade interrupt.
+                 */
+                if ((irq >= 40) && !(irq == 51) && !(irq == 53))
+                        continue;
+
                 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
                                 COMBINER_IRQ(irq, 0));
                 combiner_cascade_irq(irq, IRQ_SPI(irq));
@@ -164,7 +183,7 @@ static int __init s5pv310_l2x0_cache_init(void)
         __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
                      S5P_VA_L2CC + L2X0_POWER_CTRL);
 
-        l2x0_init(S5P_VA_L2CC, 0x7C070001, 0xC200ffff);
+        l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
 
         return 0;
 }
diff --git a/arch/arm/mach-s5pv310/cpufreq.c b/arch/arm/mach-s5pv310/cpufreq.c
new file mode 100644
index 000000000000..b04cbc731128
--- /dev/null
+++ b/arch/arm/mach-s5pv310/cpufreq.c
@@ -0,0 +1,580 @@
+/* linux/arch/arm/mach-s5pv310/cpufreq.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5PV310 - CPU frequency scaling support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/regulator/consumer.h>
+#include <linux/cpufreq.h>
+
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-mem.h>
+
+#include <plat/clock.h>
+#include <plat/pm.h>
+
+static struct clk *cpu_clk;
+static struct clk *moutcore;
+static struct clk *mout_mpll;
+static struct clk *mout_apll;
+
+#ifdef CONFIG_REGULATOR
+static struct regulator *arm_regulator;
+static struct regulator *int_regulator;
+#endif
+
+static struct cpufreq_freqs freqs;
+static unsigned int memtype;
+
+enum s5pv310_memory_type {
+        DDR2 = 4,
+        LPDDR2,
+        DDR3,
+};
+
+enum cpufreq_level_index {
+        L0, L1, L2, L3, CPUFREQ_LEVEL_END,
+};
+
+static struct cpufreq_frequency_table s5pv310_freq_table[] = {
+        {L0, 1000*1000},
+        {L1, 800*1000},
+        {L2, 400*1000},
+        {L3, 100*1000},
+        {0, CPUFREQ_TABLE_END},
+};
+
+static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = {
+        /*
+         * Clock divider value for following
+         * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
+         *              DIVATB, DIVPCLK_DBG, DIVAPLL }
+         */
+
+        /* ARM L0: 1000MHz */
+        { 0, 3, 7, 3, 3, 0, 1 },
+
+        /* ARM L1: 800MHz */
+        { 0, 3, 7, 3, 3, 0, 1 },
+
+        /* ARM L2: 400MHz */
+        { 0, 1, 3, 1, 3, 0, 1 },
+
+        /* ARM L3: 100MHz */
+        { 0, 0, 1, 0, 3, 1, 1 },
+};
+
+static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = {
+        /*
+         * Clock divider value for following
+         * { DIVCOPY, DIVHPM }
+         */
+
+         /* ARM L0: 1000MHz */
+        { 3, 0 },
+
+        /* ARM L1: 800MHz */
+        { 3, 0 },
+
+        /* ARM L2: 400MHz */
+        { 3, 0 },
+
+        /* ARM L3: 100MHz */
+        { 3, 0 },
+};
+
+static unsigned int clkdiv_dmc0[CPUFREQ_LEVEL_END][8] = {
+        /*
+         * Clock divider value for following
+         * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD
+         *              DIVDMCP, DIVCOPY2, DIVCORE_TIMERS }
+         */
+
+        /* DMC L0: 400MHz */
+        { 3, 1, 1, 1, 1, 1, 3, 1 },
+
+        /* DMC L1: 400MHz */
+        { 3, 1, 1, 1, 1, 1, 3, 1 },
+
+        /* DMC L2: 266.7MHz */
+        { 7, 1, 1, 2, 1, 1, 3, 1 },
+
+        /* DMC L3: 200MHz */
+        { 7, 1, 1, 3, 1, 1, 3, 1 },
+};
+
+static unsigned int clkdiv_top[CPUFREQ_LEVEL_END][5] = {
+        /*
+         * Clock divider value for following
+         * { DIVACLK200, DIVACLK100, DIVACLK160, DIVACLK133, DIVONENAND }
+         */
+
+        /* ACLK200 L0: 200MHz */
+        { 3, 7, 4, 5, 1 },
+
+        /* ACLK200 L1: 200MHz */
+        { 3, 7, 4, 5, 1 },
+
+        /* ACLK200 L2: 160MHz */
+        { 4, 7, 5, 7, 1 },
+
+        /* ACLK200 L3: 133.3MHz */
+        { 5, 7, 7, 7, 1 },
+};
+
+static unsigned int clkdiv_lr_bus[CPUFREQ_LEVEL_END][2] = {
+        /*
+         * Clock divider value for following
+         * { DIVGDL/R, DIVGPL/R }
+         */
+
+        /* ACLK_GDL/R L0: 200MHz */
+        { 3, 1 },
+
+        /* ACLK_GDL/R L1: 200MHz */
+        { 3, 1 },
+
+        /* ACLK_GDL/R L2: 160MHz */
+        { 4, 1 },
+
+        /* ACLK_GDL/R L3: 133.3MHz */
+        { 5, 1 },
+};
+
+struct cpufreq_voltage_table {
+        unsigned int    index;          /* any */
+        unsigned int    arm_volt;       /* uV */
+        unsigned int    int_volt;
+};
+
+static struct cpufreq_voltage_table s5pv310_volt_table[CPUFREQ_LEVEL_END] = {
+        {
+                .index          = L0,
+                .arm_volt       = 1200000,
+                .int_volt       = 1100000,
+        }, {
+                .index          = L1,
+                .arm_volt       = 1100000,
+                .int_volt       = 1100000,
+        }, {
+                .index          = L2,
+                .arm_volt       = 1000000,
+                .int_volt       = 1000000,
+        }, {
+                .index          = L3,
+                .arm_volt       = 900000,
+                .int_volt       = 1000000,
+        },
+};
+
+static unsigned int s5pv310_apll_pms_table[CPUFREQ_LEVEL_END] = {
+        /* APLL FOUT L0: 1000MHz */
+        ((250 << 16) | (6 << 8) | 1),
+
+        /* APLL FOUT L1: 800MHz */
+        ((200 << 16) | (6 << 8) | 1),
+
+        /* APLL FOUT L2 : 400MHz */
+        ((200 << 16) | (6 << 8) | 2),
+
+        /* APLL FOUT L3: 100MHz */
+        ((200 << 16) | (6 << 8) | 4),
+};
+
+int s5pv310_verify_speed(struct cpufreq_policy *policy)
+{
+        return cpufreq_frequency_table_verify(policy, s5pv310_freq_table);
+}
+
+unsigned int s5pv310_getspeed(unsigned int cpu)
+{
+        return clk_get_rate(cpu_clk) / 1000;
+}
+
+void s5pv310_set_clkdiv(unsigned int div_index)
+{
+        unsigned int tmp;
+
+        /* Change Divider - CPU0 */
+
+        tmp = __raw_readl(S5P_CLKDIV_CPU);
+
+        tmp &= ~(S5P_CLKDIV_CPU0_CORE_MASK | S5P_CLKDIV_CPU0_COREM0_MASK |
+                S5P_CLKDIV_CPU0_COREM1_MASK | S5P_CLKDIV_CPU0_PERIPH_MASK |
+                S5P_CLKDIV_CPU0_ATB_MASK | S5P_CLKDIV_CPU0_PCLKDBG_MASK |
+                S5P_CLKDIV_CPU0_APLL_MASK);
+
+        tmp |= ((clkdiv_cpu0[div_index][0] << S5P_CLKDIV_CPU0_CORE_SHIFT) |
+                (clkdiv_cpu0[div_index][1] << S5P_CLKDIV_CPU0_COREM0_SHIFT) |
+                (clkdiv_cpu0[div_index][2] << S5P_CLKDIV_CPU0_COREM1_SHIFT) |
+                (clkdiv_cpu0[div_index][3] << S5P_CLKDIV_CPU0_PERIPH_SHIFT) |
+                (clkdiv_cpu0[div_index][4] << S5P_CLKDIV_CPU0_ATB_SHIFT) |
+                (clkdiv_cpu0[div_index][5] << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT) |
+                (clkdiv_cpu0[div_index][6] << S5P_CLKDIV_CPU0_APLL_SHIFT));
+
+        __raw_writel(tmp, S5P_CLKDIV_CPU);
+
+        do {
+                tmp = __raw_readl(S5P_CLKDIV_STATCPU);
+        } while (tmp & 0x1111111);
+
+        /* Change Divider - CPU1 */
+
+        tmp = __raw_readl(S5P_CLKDIV_CPU1);
+
+        tmp &= ~((0x7 << 4) | 0x7);
+
+        tmp |= ((clkdiv_cpu1[div_index][0] << 4) |
+                (clkdiv_cpu1[div_index][1] << 0));
+
+        __raw_writel(tmp, S5P_CLKDIV_CPU1);
+
+        do {
+                tmp = __raw_readl(S5P_CLKDIV_STATCPU1);
+        } while (tmp & 0x11);
+
+        /* Change Divider - DMC0 */
+
+        tmp = __raw_readl(S5P_CLKDIV_DMC0);
+
+        tmp &= ~(S5P_CLKDIV_DMC0_ACP_MASK | S5P_CLKDIV_DMC0_ACPPCLK_MASK |
+                S5P_CLKDIV_DMC0_DPHY_MASK | S5P_CLKDIV_DMC0_DMC_MASK |
+                S5P_CLKDIV_DMC0_DMCD_MASK | S5P_CLKDIV_DMC0_DMCP_MASK |
+                S5P_CLKDIV_DMC0_COPY2_MASK | S5P_CLKDIV_DMC0_CORETI_MASK);
+
+        tmp |= ((clkdiv_dmc0[div_index][0] << S5P_CLKDIV_DMC0_ACP_SHIFT) |
+                (clkdiv_dmc0[div_index][1] << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT) |
+                (clkdiv_dmc0[div_index][2] << S5P_CLKDIV_DMC0_DPHY_SHIFT) |
+                (clkdiv_dmc0[div_index][3] << S5P_CLKDIV_DMC0_DMC_SHIFT) |
+                (clkdiv_dmc0[div_index][4] << S5P_CLKDIV_DMC0_DMCD_SHIFT) |
+                (clkdiv_dmc0[div_index][5] << S5P_CLKDIV_DMC0_DMCP_SHIFT) |
+                (clkdiv_dmc0[div_index][6] << S5P_CLKDIV_DMC0_COPY2_SHIFT) |
+                (clkdiv_dmc0[div_index][7] << S5P_CLKDIV_DMC0_CORETI_SHIFT));
+
+        __raw_writel(tmp, S5P_CLKDIV_DMC0);
+
+        do {
+                tmp = __raw_readl(S5P_CLKDIV_STAT_DMC0);
+        } while (tmp & 0x11111111);
+
+        /* Change Divider - TOP */
+
+        tmp = __raw_readl(S5P_CLKDIV_TOP);
+
+        tmp &= ~(S5P_CLKDIV_TOP_ACLK200_MASK | S5P_CLKDIV_TOP_ACLK100_MASK |
+                S5P_CLKDIV_TOP_ACLK160_MASK | S5P_CLKDIV_TOP_ACLK133_MASK |
+                S5P_CLKDIV_TOP_ONENAND_MASK);
+
+        tmp |= ((clkdiv_top[div_index][0] << S5P_CLKDIV_TOP_ACLK200_SHIFT) |
+                (clkdiv_top[div_index][1] << S5P_CLKDIV_TOP_ACLK100_SHIFT) |
+                (clkdiv_top[div_index][2] << S5P_CLKDIV_TOP_ACLK160_SHIFT) |
+                (clkdiv_top[div_index][3] << S5P_CLKDIV_TOP_ACLK133_SHIFT) |
+                (clkdiv_top[div_index][4] << S5P_CLKDIV_TOP_ONENAND_SHIFT));
+
+        __raw_writel(tmp, S5P_CLKDIV_TOP);
+
+        do {
+                tmp = __raw_readl(S5P_CLKDIV_STAT_TOP);
+        } while (tmp & 0x11111);
+
+        /* Change Divider - LEFTBUS */
+
+        tmp = __raw_readl(S5P_CLKDIV_LEFTBUS);
+
+        tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
+
+        tmp |= ((clkdiv_lr_bus[div_index][0] << S5P_CLKDIV_BUS_GDLR_SHIFT) |
+                (clkdiv_lr_bus[div_index][1] << S5P_CLKDIV_BUS_GPLR_SHIFT));
+
+        __raw_writel(tmp, S5P_CLKDIV_LEFTBUS);
+
+        do {
+                tmp = __raw_readl(S5P_CLKDIV_STAT_LEFTBUS);
+        } while (tmp & 0x11);
+
+        /* Change Divider - RIGHTBUS */
+
+        tmp = __raw_readl(S5P_CLKDIV_RIGHTBUS);
+
+        tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
+
+        tmp |= ((clkdiv_lr_bus[div_index][0] << S5P_CLKDIV_BUS_GDLR_SHIFT) |
+                (clkdiv_lr_bus[div_index][1] << S5P_CLKDIV_BUS_GPLR_SHIFT));
+
+        __raw_writel(tmp, S5P_CLKDIV_RIGHTBUS);
+
+        do {
+                tmp = __raw_readl(S5P_CLKDIV_STAT_RIGHTBUS);
+        } while (tmp & 0x11);
+}
+
+static void s5pv310_set_apll(unsigned int index)
+{
+        unsigned int tmp;
+
+        /* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
+        clk_set_parent(moutcore, mout_mpll);
+
+        do {
+                tmp = (__raw_readl(S5P_CLKMUX_STATCPU)
+                        >> S5P_CLKSRC_CPU_MUXCORE_SHIFT);
+                tmp &= 0x7;
+        } while (tmp != 0x2);
+
+        /* 2. Set APLL Lock time */
+        __raw_writel(S5P_APLL_LOCKTIME, S5P_APLL_LOCK);
+
+        /* 3. Change PLL PMS values */
+        tmp = __raw_readl(S5P_APLL_CON0);
+        tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
+        tmp |= s5pv310_apll_pms_table[index];
+        __raw_writel(tmp, S5P_APLL_CON0);
+
+        /* 4. wait_lock_time */
+        do {
+                tmp = __raw_readl(S5P_APLL_CON0);
+        } while (!(tmp & (0x1 << S5P_APLLCON0_LOCKED_SHIFT)));
+
+        /* 5. MUX_CORE_SEL = APLL */
+        clk_set_parent(moutcore, mout_apll);
+
+        do {
+                tmp = __raw_readl(S5P_CLKMUX_STATCPU);
+                tmp &= S5P_CLKMUX_STATCPU_MUXCORE_MASK;
+        } while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT));
+}
+
+static void s5pv310_set_frequency(unsigned int old_index, unsigned int new_index)
+{
+        unsigned int tmp;
+
+        if (old_index > new_index) {
+                /* The frequency changing to L0 needs to change apll */
+                if (freqs.new == s5pv310_freq_table[L0].frequency) {
+                        /* 1. Change the system clock divider values */
+                        s5pv310_set_clkdiv(new_index);
+
+                        /* 2. Change the apll m,p,s value */
+                        s5pv310_set_apll(new_index);
+                } else {
+                        /* 1. Change the system clock divider values */
+                        s5pv310_set_clkdiv(new_index);
+
+                        /* 2. Change just s value in apll m,p,s value */
+                        tmp = __raw_readl(S5P_APLL_CON0);
+                        tmp &= ~(0x7 << 0);
+                        tmp |= (s5pv310_apll_pms_table[new_index] & 0x7);
+                        __raw_writel(tmp, S5P_APLL_CON0);
+                }
+        }
+
+        else if (old_index < new_index) {
+                /* The frequency changing from L0 needs to change apll */
+                if (freqs.old == s5pv310_freq_table[L0].frequency) {
+                        /* 1. Change the apll m,p,s value */
+                        s5pv310_set_apll(new_index);
+
+                        /* 2. Change the system clock divider values */
+                        s5pv310_set_clkdiv(new_index);
+                } else {
+                        /* 1. Change just s value in apll m,p,s value */
+                        tmp = __raw_readl(S5P_APLL_CON0);
+                        tmp &= ~(0x7 << 0);
+                        tmp |= (s5pv310_apll_pms_table[new_index] & 0x7);
+                        __raw_writel(tmp, S5P_APLL_CON0);
+
+                        /* 2. Change the system clock divider values */
+                        s5pv310_set_clkdiv(new_index);
+                }
+        }
+}
+
+static int s5pv310_target(struct cpufreq_policy *policy,
+                          unsigned int target_freq,
+                          unsigned int relation)
+{
+        unsigned int index, old_index;
+        unsigned int arm_volt, int_volt;
+
+        freqs.old = s5pv310_getspeed(policy->cpu);
+
+        if (cpufreq_frequency_table_target(policy, s5pv310_freq_table,
+                                           freqs.old, relation, &old_index))
+                return -EINVAL;
+
+        if (cpufreq_frequency_table_target(policy, s5pv310_freq_table,
+                                           target_freq, relation, &index))
+                return -EINVAL;
+
+        freqs.new = s5pv310_freq_table[index].frequency;
+        freqs.cpu = policy->cpu;
+
+        if (freqs.new == freqs.old)
+                return 0;
+
+        /* get the voltage value */
+        arm_volt = s5pv310_volt_table[index].arm_volt;
+        int_volt = s5pv310_volt_table[index].int_volt;
+
+        cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+
+        /* control regulator */
+        if (freqs.new > freqs.old) {
+                /* Voltage up */
+#ifdef CONFIG_REGULATOR
+                regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
+                regulator_set_voltage(int_regulator, int_volt, int_volt);
+#endif
+        }
+
+        /* Clock Configuration Procedure */
+        s5pv310_set_frequency(old_index, index);
+
+        /* control regulator */
+        if (freqs.new < freqs.old) {
+                /* Voltage down */
+#ifdef CONFIG_REGULATOR
+                regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
+                regulator_set_voltage(int_regulator, int_volt, int_volt);
+#endif
+        }
+
+        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+
+        return 0;
+}
+
+#ifdef CONFIG_PM
+static int s5pv310_cpufreq_suspend(struct cpufreq_policy *policy,
+                                   pm_message_t pmsg)
+{
+        return 0;
+}
+
+static int s5pv310_cpufreq_resume(struct cpufreq_policy *policy)
+{
+        return 0;
+}
+#endif
+
+static int s5pv310_cpufreq_cpu_init(struct cpufreq_policy *policy)
+{
+        policy->cur = policy->min = policy->max = s5pv310_getspeed(policy->cpu);
+
+        cpufreq_frequency_table_get_attr(s5pv310_freq_table, policy->cpu);
+
+        /* set the transition latency value */
+        policy->cpuinfo.transition_latency = 100000;
+
+        /*
+         * S5PV310 multi-core processors has 2 cores
+         * that the frequency cannot be set independently.
+         * Each cpu is bound to the same speed.
+         * So the affected cpu is all of the cpus.
+         */
+        cpumask_setall(policy->cpus);
+
+        return cpufreq_frequency_table_cpuinfo(policy, s5pv310_freq_table);
+}
+
+static struct cpufreq_driver s5pv310_driver = {
+        .flags          = CPUFREQ_STICKY,
+        .verify         = s5pv310_verify_speed,
+        .target         = s5pv310_target,
+        .get            = s5pv310_getspeed,
+        .init           = s5pv310_cpufreq_cpu_init,
+        .name           = "s5pv310_cpufreq",
+#ifdef CONFIG_PM
+        .suspend        = s5pv310_cpufreq_suspend,
+        .resume         = s5pv310_cpufreq_resume,
+#endif
+};
+
+static int __init s5pv310_cpufreq_init(void)
+{
+        cpu_clk = clk_get(NULL, "armclk");
+        if (IS_ERR(cpu_clk))
+                return PTR_ERR(cpu_clk);
+
+        moutcore = clk_get(NULL, "moutcore");
+        if (IS_ERR(moutcore))
+                goto out;
+
+        mout_mpll = clk_get(NULL, "mout_mpll");
+        if (IS_ERR(mout_mpll))
+                goto out;
+
+        mout_apll = clk_get(NULL, "mout_apll");
+        if (IS_ERR(mout_apll))
+                goto out;
+
+#ifdef CONFIG_REGULATOR
+        arm_regulator = regulator_get(NULL, "vdd_arm");
+        if (IS_ERR(arm_regulator)) {
+                printk(KERN_ERR "failed to get resource %s\n", "vdd_arm");
+                goto out;
+        }
+
+        int_regulator = regulator_get(NULL, "vdd_int");
+        if (IS_ERR(int_regulator)) {
+                printk(KERN_ERR "failed to get resource %s\n", "vdd_int");
+                goto out;
+        }
+#endif
+
+        /*
+         * Check DRAM type.
+         * Because DVFS level is different according to DRAM type.
+         */
+        memtype = __raw_readl(S5P_VA_DMC0 + S5P_DMC0_MEMCON_OFFSET);
+        memtype = (memtype >> S5P_DMC0_MEMTYPE_SHIFT);
+        memtype &= S5P_DMC0_MEMTYPE_MASK;
+
+        if ((memtype < DDR2) && (memtype > DDR3)) {
+                printk(KERN_ERR "%s: wrong memtype= 0x%x\n", __func__, memtype);
+                goto out;
+        } else {
+                printk(KERN_DEBUG "%s: memtype= 0x%x\n", __func__, memtype);
+        }
+
+        return cpufreq_register_driver(&s5pv310_driver);
+
+out:
+        if (!IS_ERR(cpu_clk))
+                clk_put(cpu_clk);
+
+        if (!IS_ERR(moutcore))
+                clk_put(moutcore);
+
+        if (!IS_ERR(mout_mpll))
+                clk_put(mout_mpll);
+
+        if (!IS_ERR(mout_apll))
+                clk_put(mout_apll);
+
+#ifdef CONFIG_REGULATOR
+        if (!IS_ERR(arm_regulator))
+                regulator_put(arm_regulator);
+
+        if (!IS_ERR(int_regulator))
+                regulator_put(int_regulator);
+#endif
+
+        printk(KERN_ERR "%s: failed initialization\n", __func__);
+
+        return -EINVAL;
+}
+late_initcall(s5pv310_cpufreq_init);
diff --git a/arch/arm/mach-s5pv310/dev-pd.c b/arch/arm/mach-s5pv310/dev-pd.c
new file mode 100644
index 000000000000..58a50c2d0b67
--- /dev/null
+++ b/arch/arm/mach-s5pv310/dev-pd.c
@@ -0,0 +1,139 @@
+/* linux/arch/arm/mach-s5pv310/dev-pd.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5PV310 - Power Domain support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+
+#include <mach/regs-pmu.h>
+
+#include <plat/pd.h>
+
+static int s5pv310_pd_enable(struct device *dev)
+{
+        struct samsung_pd_info *pdata =  dev->platform_data;
+        u32 timeout;
+
+        __raw_writel(S5P_INT_LOCAL_PWR_EN, pdata->base);
+
+        /* Wait max 1ms */
+        timeout = 10;
+        while ((__raw_readl(pdata->base + 0x4) & S5P_INT_LOCAL_PWR_EN)
+                != S5P_INT_LOCAL_PWR_EN) {
+                if (timeout == 0) {
+                        printk(KERN_ERR "Power domain %s enable failed.\n",
+                                dev_name(dev));
+                        return -ETIMEDOUT;
+                }
+                timeout--;
+                udelay(100);
+        }
+
+        return 0;
+}
+
+static int s5pv310_pd_disable(struct device *dev)
+{
+        struct samsung_pd_info *pdata =  dev->platform_data;
+        u32 timeout;
+
+        __raw_writel(0, pdata->base);
+
+        /* Wait max 1ms */
+        timeout = 10;
+        while (__raw_readl(pdata->base + 0x4) & S5P_INT_LOCAL_PWR_EN) {
+                if (timeout == 0) {
+                        printk(KERN_ERR "Power domain %s disable failed.\n",
+                                dev_name(dev));
+                        return -ETIMEDOUT;
+                }
+                timeout--;
+                udelay(100);
+        }
+
+        return 0;
+}
+
+struct platform_device s5pv310_device_pd[] = {
+        {
+                .name           = "samsung-pd",
+                .id             = 0,
+                .dev = {
+                        .platform_data = &(struct samsung_pd_info) {
+                                .enable         = s5pv310_pd_enable,
+                                .disable        = s5pv310_pd_disable,
+                                .base           = S5P_PMU_MFC_CONF,
+                        },
+                },
+        }, {
+                .name           = "samsung-pd",
+                .id             = 1,
+                .dev = {
+                        .platform_data = &(struct samsung_pd_info) {
+                                .enable         = s5pv310_pd_enable,
+                                .disable        = s5pv310_pd_disable,
+                                .base           = S5P_PMU_G3D_CONF,
+                        },
+                },
+        }, {
+                .name           = "samsung-pd",
+                .id             = 2,
+                .dev = {
+                        .platform_data = &(struct samsung_pd_info) {
+                                .enable         = s5pv310_pd_enable,
+                                .disable        = s5pv310_pd_disable,
+                                .base           = S5P_PMU_LCD0_CONF,
+                        },
+                },
+        }, {
+                .name           = "samsung-pd",
+                .id             = 3,
+                .dev = {
+                        .platform_data = &(struct samsung_pd_info) {
+                                .enable         = s5pv310_pd_enable,
+                                .disable        = s5pv310_pd_disable,
+                                .base           = S5P_PMU_LCD1_CONF,
+                        },
+                },
+        }, {
+                .name           = "samsung-pd",
+                .id             = 4,
+                .dev = {
+                        .platform_data = &(struct samsung_pd_info) {
+                                .enable         = s5pv310_pd_enable,
+                                .disable        = s5pv310_pd_disable,
+                                .base           = S5P_PMU_TV_CONF,
+                        },
+                },
+        }, {
+                .name           = "samsung-pd",
+                .id             = 5,
+                .dev = {
+                        .platform_data = &(struct samsung_pd_info) {
+                                .enable         = s5pv310_pd_enable,
+                                .disable        = s5pv310_pd_disable,
+                                .base           = S5P_PMU_CAM_CONF,
+                        },
+                },
+        }, {
+                .name           = "samsung-pd",
+                .id             = 6,
+                .dev = {
+                        .platform_data = &(struct samsung_pd_info) {
+                                .enable         = s5pv310_pd_enable,
+                                .disable        = s5pv310_pd_disable,
+                                .base           = S5P_PMU_GPS_CONF,
+                        },
+                },
+        },
+};
diff --git a/arch/arm/mach-s5pv310/dev-sysmmu.c b/arch/arm/mach-s5pv310/dev-sysmmu.c
new file mode 100644
index 000000000000..e1bb200ac0f0
--- /dev/null
+++ b/arch/arm/mach-s5pv310/dev-sysmmu.c
@@ -0,0 +1,187 @@
+/* linux/arch/arm/mach-s5pv310/dev-sysmmu.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+
+#include <mach/map.h>
+#include <mach/irqs.h>
+
+static struct resource s5pv310_sysmmu_resource[] = {
+        [0] = {
+                .start  = S5PV310_PA_SYSMMU_MDMA,
+                .end    = S5PV310_PA_SYSMMU_MDMA + SZ_64K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_SYSMMU_MDMA0_0,
+                .end    = IRQ_SYSMMU_MDMA0_0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = S5PV310_PA_SYSMMU_SSS,
+                .end    = S5PV310_PA_SYSMMU_SSS + SZ_64K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [3] = {
+                .start  = IRQ_SYSMMU_SSS_0,
+                .end    = IRQ_SYSMMU_SSS_0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [4] = {
+                .start  = S5PV310_PA_SYSMMU_FIMC0,
+                .end    = S5PV310_PA_SYSMMU_FIMC0 + SZ_64K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [5] = {
+                .start  = IRQ_SYSMMU_FIMC0_0,
+                .end    = IRQ_SYSMMU_FIMC0_0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [6] = {
+                .start  = S5PV310_PA_SYSMMU_FIMC1,
+                .end    = S5PV310_PA_SYSMMU_FIMC1 + SZ_64K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [7] = {
+                .start  = IRQ_SYSMMU_FIMC1_0,
+                .end    = IRQ_SYSMMU_FIMC1_0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [8] = {
+                .start  = S5PV310_PA_SYSMMU_FIMC2,
+                .end    = S5PV310_PA_SYSMMU_FIMC2 + SZ_64K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [9] = {
+                .start  = IRQ_SYSMMU_FIMC2_0,
+                .end    = IRQ_SYSMMU_FIMC2_0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [10] = {
+                .start  = S5PV310_PA_SYSMMU_FIMC3,
+                .end    = S5PV310_PA_SYSMMU_FIMC3 + SZ_64K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [11] = {
+                .start  = IRQ_SYSMMU_FIMC3_0,
+                .end    = IRQ_SYSMMU_FIMC3_0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [12] = {
+                .start  = S5PV310_PA_SYSMMU_JPEG,
+                .end    = S5PV310_PA_SYSMMU_JPEG + SZ_64K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [13] = {
+                .start  = IRQ_SYSMMU_JPEG_0,
+                .end    = IRQ_SYSMMU_JPEG_0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [14] = {
+                .start  = S5PV310_PA_SYSMMU_FIMD0,
+                .end    = S5PV310_PA_SYSMMU_FIMD0 + SZ_64K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [15] = {
+                .start  = IRQ_SYSMMU_LCD0_M0_0,
+                .end    = IRQ_SYSMMU_LCD0_M0_0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [16] = {
+                .start  = S5PV310_PA_SYSMMU_FIMD1,
+                .end    = S5PV310_PA_SYSMMU_FIMD1 + SZ_64K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [17] = {
+                .start  = IRQ_SYSMMU_LCD1_M1_0,
+                .end    = IRQ_SYSMMU_LCD1_M1_0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [18] = {
+                .start  = S5PV310_PA_SYSMMU_PCIe,
+                .end    = S5PV310_PA_SYSMMU_PCIe + SZ_64K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [19] = {
+                .start  = IRQ_SYSMMU_PCIE_0,
+                .end    = IRQ_SYSMMU_PCIE_0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [20] = {
+                .start  = S5PV310_PA_SYSMMU_G2D,
+                .end    = S5PV310_PA_SYSMMU_G2D + SZ_64K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [21] = {
+                .start  = IRQ_SYSMMU_2D_0,
+                .end    = IRQ_SYSMMU_2D_0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [22] = {
+                .start  = S5PV310_PA_SYSMMU_ROTATOR,
+                .end    = S5PV310_PA_SYSMMU_ROTATOR + SZ_64K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [23] = {
+                .start  = IRQ_SYSMMU_ROTATOR_0,
+                .end    = IRQ_SYSMMU_ROTATOR_0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [24] = {
+                .start  = S5PV310_PA_SYSMMU_MDMA2,
+                .end    = S5PV310_PA_SYSMMU_MDMA2 + SZ_64K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [25] = {
+                .start  = IRQ_SYSMMU_MDMA1_0,
+                .end    = IRQ_SYSMMU_MDMA1_0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [26] = {
+                .start  = S5PV310_PA_SYSMMU_TV,
+                .end    = S5PV310_PA_SYSMMU_TV + SZ_64K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [27] = {
+                .start  = IRQ_SYSMMU_TV_M0_0,
+                .end    = IRQ_SYSMMU_TV_M0_0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [28] = {
+                .start  = S5PV310_PA_SYSMMU_MFC_L,
+                .end    = S5PV310_PA_SYSMMU_MFC_L + SZ_64K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [29] = {
+                .start  = IRQ_SYSMMU_MFC_M0_0,
+                .end    = IRQ_SYSMMU_MFC_M0_0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [30] = {
+                .start  = S5PV310_PA_SYSMMU_MFC_R,
+                .end    = S5PV310_PA_SYSMMU_MFC_R + SZ_64K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [31] = {
+                .start  = IRQ_SYSMMU_MFC_M1_0,
+                .end    = IRQ_SYSMMU_MFC_M1_0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device s5pv310_device_sysmmu = {
+        .name           = "s5p-sysmmu",
+        .id             = 32,
+        .num_resources  = ARRAY_SIZE(s5pv310_sysmmu_resource),
+        .resource       = s5pv310_sysmmu_resource,
+};
+
+EXPORT_SYMBOL(s5pv310_device_sysmmu);
diff --git a/arch/arm/mach-s5pv310/include/mach/irqs.h b/arch/arm/mach-s5pv310/include/mach/irqs.h
index 3c05c58b5392..536b0b59fc83 100644
--- a/arch/arm/mach-s5pv310/include/mach/irqs.h
+++ b/arch/arm/mach-s5pv310/include/mach/irqs.h
@@ -25,6 +25,8 @@
 
 #define IRQ_SPI(x)              S5P_IRQ(x+32)
 
+#define IRQ_MCT1                IRQ_SPI(35)
+
 #define IRQ_EINT0               IRQ_SPI(40)
 #define IRQ_EINT1               IRQ_SPI(41)
 #define IRQ_EINT2               IRQ_SPI(42)
@@ -36,9 +38,8 @@
 #define IRQ_JPEG                IRQ_SPI(48)
 #define IRQ_2D                  IRQ_SPI(49)
 #define IRQ_PCIE                IRQ_SPI(50)
-#define IRQ_SYSTEM_TIMER        IRQ_SPI(51)
+#define IRQ_MCT0                IRQ_SPI(51)
 #define IRQ_MFC                 IRQ_SPI(52)
-#define IRQ_WDT                 IRQ_SPI(53)
 #define IRQ_AUDIO_SS            IRQ_SPI(54)
 #define IRQ_AC97                IRQ_SPI(55)
 #define IRQ_SPDIF               IRQ_SPI(56)
@@ -54,6 +55,24 @@
 #define COMBINER_GROUP(x)       ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(64))
 #define COMBINER_IRQ(x, y)      (COMBINER_GROUP(x) + y)
 
+#define IRQ_SYSMMU_MDMA0_0      COMBINER_IRQ(4, 0)
+#define IRQ_SYSMMU_SSS_0        COMBINER_IRQ(4, 1)
+#define IRQ_SYSMMU_FIMC0_0      COMBINER_IRQ(4, 2)
+#define IRQ_SYSMMU_FIMC1_0      COMBINER_IRQ(4, 3)
+#define IRQ_SYSMMU_FIMC2_0      COMBINER_IRQ(4, 4)
+#define IRQ_SYSMMU_FIMC3_0      COMBINER_IRQ(4, 5)
+#define IRQ_SYSMMU_JPEG_0       COMBINER_IRQ(4, 6)
+#define IRQ_SYSMMU_2D_0         COMBINER_IRQ(4, 7)
+
+#define IRQ_SYSMMU_ROTATOR_0    COMBINER_IRQ(5, 0)
+#define IRQ_SYSMMU_MDMA1_0      COMBINER_IRQ(5, 1)
+#define IRQ_SYSMMU_LCD0_M0_0    COMBINER_IRQ(5, 2)
+#define IRQ_SYSMMU_LCD1_M1_0    COMBINER_IRQ(5, 3)
+#define IRQ_SYSMMU_TV_M0_0      COMBINER_IRQ(5, 4)
+#define IRQ_SYSMMU_MFC_M0_0     COMBINER_IRQ(5, 5)
+#define IRQ_SYSMMU_MFC_M1_0     COMBINER_IRQ(5, 6)
+#define IRQ_SYSMMU_PCIE_0       COMBINER_IRQ(5, 7)
+
 #define IRQ_PDMA0               COMBINER_IRQ(21, 0)
 #define IRQ_PDMA1               COMBINER_IRQ(21, 1)
 
@@ -86,8 +105,13 @@
 #define IRQ_HSMMC2              COMBINER_IRQ(29, 2)
 #define IRQ_HSMMC3              COMBINER_IRQ(29, 3)
 
+#define IRQ_MIPI_CSIS0          COMBINER_IRQ(30, 0)
+#define IRQ_MIPI_CSIS1          COMBINER_IRQ(30, 1)
+
 #define IRQ_ONENAND_AUDI        COMBINER_IRQ(34, 0)
 
+#define IRQ_MCT_L1              COMBINER_IRQ(35, 3)
+
 #define IRQ_EINT4               COMBINER_IRQ(37, 0)
 #define IRQ_EINT5               COMBINER_IRQ(37, 1)
 #define IRQ_EINT6               COMBINER_IRQ(37, 2)
@@ -104,7 +128,11 @@
 
 #define IRQ_EINT16_31           COMBINER_IRQ(39, 0)
 
-#define MAX_COMBINER_NR         40
+#define IRQ_MCT_L0              COMBINER_IRQ(51, 0)
+
+#define IRQ_WDT                 COMBINER_IRQ(53, 0)
+
+#define MAX_COMBINER_NR         54
 
 #define S5P_IRQ_EINT_BASE       COMBINER_IRQ(MAX_COMBINER_NR, 0)
 
diff --git a/arch/arm/mach-s5pv310/include/mach/map.h b/arch/arm/mach-s5pv310/include/mach/map.h
index 53994467605d..74d400625a23 100644
--- a/arch/arm/mach-s5pv310/include/mach/map.h
+++ b/arch/arm/mach-s5pv310/include/mach/map.h
@@ -39,11 +39,15 @@
 #define S5PV310_PA_SYSCON               (0x10010000)
 #define S5P_PA_SYSCON                   S5PV310_PA_SYSCON
 
+#define S5PV310_PA_PMU                  (0x10020000)
+
 #define S5PV310_PA_CMU                  (0x10030000)
 
 #define S5PV310_PA_WATCHDOG             (0x10060000)
 #define S5PV310_PA_RTC                  (0x10070000)
 
+#define S5PV310_PA_DMC0                 (0x10400000)
+
 #define S5PV310_PA_COMBINER             (0x10448000)
 
 #define S5PV310_PA_COREPERI             (0x10500000)
@@ -61,9 +65,13 @@
 #define S5PV310_PA_GPIO2                (0x11000000)
 #define S5PV310_PA_GPIO3                (0x03860000)
 
+#define S5PV310_PA_MIPI_CSIS0           0x11880000
+#define S5PV310_PA_MIPI_CSIS1           0x11890000
+
 #define S5PV310_PA_HSMMC(x)             (0x12510000 + ((x) * 0x10000))
 
 #define S5PV310_PA_SROMC                (0x12570000)
+#define S5P_PA_SROMC                    S5PV310_PA_SROMC
 
 /* S/PDIF */
 #define S5PV310_PA_SPDIF        0xE1100000
@@ -100,6 +108,25 @@
 #define S5PV310_PA_SDRAM                (0x40000000)
 #define S5P_PA_SDRAM                    S5PV310_PA_SDRAM
 
+#define S5PV310_PA_SYSMMU_MDMA          0x10A40000
+#define S5PV310_PA_SYSMMU_SSS           0x10A50000
+#define S5PV310_PA_SYSMMU_FIMC0         0x11A20000
+#define S5PV310_PA_SYSMMU_FIMC1         0x11A30000
+#define S5PV310_PA_SYSMMU_FIMC2         0x11A40000
+#define S5PV310_PA_SYSMMU_FIMC3         0x11A50000
+#define S5PV310_PA_SYSMMU_JPEG          0x11A60000
+#define S5PV310_PA_SYSMMU_FIMD0         0x11E20000
+#define S5PV310_PA_SYSMMU_FIMD1         0x12220000
+#define S5PV310_PA_SYSMMU_PCIe          0x12620000
+#define S5PV310_PA_SYSMMU_G2D           0x12A20000
+#define S5PV310_PA_SYSMMU_ROTATOR       0x12A30000
+#define S5PV310_PA_SYSMMU_MDMA2         0x12A40000
+#define S5PV310_PA_SYSMMU_TV            0x12E20000
+#define S5PV310_PA_SYSMMU_MFC_L         0x13620000
+#define S5PV310_PA_SYSMMU_MFC_R         0x13630000
+#define S5PV310_SYSMMU_TOTAL_IPNUM      16
+#define S5P_SYSMMU_TOTAL_IPNUM          S5PV310_SYSMMU_TOTAL_IPNUM
+
 /* compatibiltiy defines. */
 #define S3C_PA_UART                     S5PV310_PA_UART
 #define S3C_PA_HSMMC0                   S5PV310_PA_HSMMC(0)
@@ -116,5 +143,7 @@
 #define S3C_PA_IIC7                     S5PV310_PA_IIC(7)
 #define S3C_PA_RTC                      S5PV310_PA_RTC
 #define S3C_PA_WDT                      S5PV310_PA_WATCHDOG
+#define S5P_PA_MIPI_CSIS0               S5PV310_PA_MIPI_CSIS0
+#define S5P_PA_MIPI_CSIS1               S5PV310_PA_MIPI_CSIS1
 
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-clock.h b/arch/arm/mach-s5pv310/include/mach/regs-clock.h
index f1028cad9788..b5c4ada1cff5 100644
--- a/arch/arm/mach-s5pv310/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pv310/include/mach/regs-clock.h
@@ -19,6 +19,12 @@
 
 #define S5P_INFORM0                     S5P_CLKREG(0x800)
 
+#define S5P_CLKDIV_LEFTBUS              S5P_CLKREG(0x04500)
+#define S5P_CLKDIV_STAT_LEFTBUS         S5P_CLKREG(0x04600)
+
+#define S5P_CLKDIV_RIGHTBUS             S5P_CLKREG(0x08500)
+#define S5P_CLKDIV_STAT_RIGHTBUS        S5P_CLKREG(0x08600)
+
 #define S5P_EPLL_CON0                   S5P_CLKREG(0x0C110)
 #define S5P_EPLL_CON1                   S5P_CLKREG(0x0C114)
 #define S5P_VPLL_CON0                   S5P_CLKREG(0x0C120)
@@ -58,6 +64,8 @@
 #define S5P_CLKSRC_MASK_PERIL0          S5P_CLKREG(0x0C350)
 #define S5P_CLKSRC_MASK_PERIL1          S5P_CLKREG(0x0C354)
 
+#define S5P_CLKDIV_STAT_TOP             S5P_CLKREG(0x0C610)
+
 #define S5P_CLKGATE_IP_CAM              S5P_CLKREG(0x0C920)
 #define S5P_CLKGATE_IP_IMAGE            S5P_CLKREG(0x0C930)
 #define S5P_CLKGATE_IP_LCD0             S5P_CLKREG(0x0C934)
@@ -66,8 +74,9 @@
 #define S5P_CLKGATE_IP_PERIL            S5P_CLKREG(0x0C950)
 #define S5P_CLKGATE_IP_PERIR            S5P_CLKREG(0x0C960)
 
-#define S5P_CLKSRC_CORE                 S5P_CLKREG(0x10200)
-#define S5P_CLKDIV_CORE0                S5P_CLKREG(0x10500)
+#define S5P_CLKSRC_DMC                  S5P_CLKREG(0x10200)
+#define S5P_CLKDIV_DMC0                 S5P_CLKREG(0x10500)
+#define S5P_CLKDIV_STAT_DMC0            S5P_CLKREG(0x10600)
 
 #define S5P_APLL_LOCK                   S5P_CLKREG(0x14000)
 #define S5P_MPLL_LOCK                   S5P_CLKREG(0x14004)
@@ -80,10 +89,77 @@
 #define S5P_CLKMUX_STATCPU              S5P_CLKREG(0x14400)
 
 #define S5P_CLKDIV_CPU                  S5P_CLKREG(0x14500)
+#define S5P_CLKDIV_CPU1                 S5P_CLKREG(0x14504)
 #define S5P_CLKDIV_STATCPU              S5P_CLKREG(0x14600)
+#define S5P_CLKDIV_STATCPU1             S5P_CLKREG(0x14604)
 
 #define S5P_CLKGATE_SCLKCPU             S5P_CLKREG(0x14800)
 
+/* APLL_LOCK */
+#define S5P_APLL_LOCKTIME               (0x1C20)        /* 300us */
+
+/* APLL_CON0 */
+#define S5P_APLLCON0_ENABLE_SHIFT       (31)
+#define S5P_APLLCON0_LOCKED_SHIFT       (29)
+#define S5P_APLL_VAL_1000               ((250 << 16) | (6 << 8) | 1)
+#define S5P_APLL_VAL_800                ((200 << 16) | (6 << 8) | 1)
+
+/* CLK_SRC_CPU */
+#define S5P_CLKSRC_CPU_MUXCORE_SHIFT    (16)
+#define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)
+
+/* CLKDIV_CPU0 */
+#define S5P_CLKDIV_CPU0_CORE_SHIFT      (0)
+#define S5P_CLKDIV_CPU0_CORE_MASK       (0x7 << S5P_CLKDIV_CPU0_CORE_SHIFT)
+#define S5P_CLKDIV_CPU0_COREM0_SHIFT    (4)
+#define S5P_CLKDIV_CPU0_COREM0_MASK     (0x7 << S5P_CLKDIV_CPU0_COREM0_SHIFT)
+#define S5P_CLKDIV_CPU0_COREM1_SHIFT    (8)
+#define S5P_CLKDIV_CPU0_COREM1_MASK     (0x7 << S5P_CLKDIV_CPU0_COREM1_SHIFT)
+#define S5P_CLKDIV_CPU0_PERIPH_SHIFT    (12)
+#define S5P_CLKDIV_CPU0_PERIPH_MASK     (0x7 << S5P_CLKDIV_CPU0_PERIPH_SHIFT)
+#define S5P_CLKDIV_CPU0_ATB_SHIFT       (16)
+#define S5P_CLKDIV_CPU0_ATB_MASK        (0x7 << S5P_CLKDIV_CPU0_ATB_SHIFT)
+#define S5P_CLKDIV_CPU0_PCLKDBG_SHIFT   (20)
+#define S5P_CLKDIV_CPU0_PCLKDBG_MASK    (0x7 << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT)
+#define S5P_CLKDIV_CPU0_APLL_SHIFT      (24)
+#define S5P_CLKDIV_CPU0_APLL_MASK       (0x7 << S5P_CLKDIV_CPU0_APLL_SHIFT)
+
+/* CLKDIV_DMC0 */
+#define S5P_CLKDIV_DMC0_ACP_SHIFT       (0)
+#define S5P_CLKDIV_DMC0_ACP_MASK        (0x7 << S5P_CLKDIV_DMC0_ACP_SHIFT)
+#define S5P_CLKDIV_DMC0_ACPPCLK_SHIFT   (4)
+#define S5P_CLKDIV_DMC0_ACPPCLK_MASK    (0x7 << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT)
+#define S5P_CLKDIV_DMC0_DPHY_SHIFT      (8)
+#define S5P_CLKDIV_DMC0_DPHY_MASK       (0x7 << S5P_CLKDIV_DMC0_DPHY_SHIFT)
+#define S5P_CLKDIV_DMC0_DMC_SHIFT       (12)
+#define S5P_CLKDIV_DMC0_DMC_MASK        (0x7 << S5P_CLKDIV_DMC0_DMC_SHIFT)
+#define S5P_CLKDIV_DMC0_DMCD_SHIFT      (16)
+#define S5P_CLKDIV_DMC0_DMCD_MASK       (0x7 << S5P_CLKDIV_DMC0_DMCD_SHIFT)
+#define S5P_CLKDIV_DMC0_DMCP_SHIFT      (20)
+#define S5P_CLKDIV_DMC0_DMCP_MASK       (0x7 << S5P_CLKDIV_DMC0_DMCP_SHIFT)
+#define S5P_CLKDIV_DMC0_COPY2_SHIFT     (24)
+#define S5P_CLKDIV_DMC0_COPY2_MASK      (0x7 << S5P_CLKDIV_DMC0_COPY2_SHIFT)
+#define S5P_CLKDIV_DMC0_CORETI_SHIFT    (28)
+#define S5P_CLKDIV_DMC0_CORETI_MASK     (0x7 << S5P_CLKDIV_DMC0_CORETI_SHIFT)
+
+/* CLKDIV_TOP */
+#define S5P_CLKDIV_TOP_ACLK200_SHIFT    (0)
+#define S5P_CLKDIV_TOP_ACLK200_MASK     (0x7 << S5P_CLKDIV_TOP_ACLK200_SHIFT)
+#define S5P_CLKDIV_TOP_ACLK100_SHIFT    (4)
+#define S5P_CLKDIV_TOP_ACLK100_MASK     (0xf << S5P_CLKDIV_TOP_ACLK100_SHIFT)
+#define S5P_CLKDIV_TOP_ACLK160_SHIFT    (8)
+#define S5P_CLKDIV_TOP_ACLK160_MASK     (0x7 << S5P_CLKDIV_TOP_ACLK160_SHIFT)
+#define S5P_CLKDIV_TOP_ACLK133_SHIFT    (12)
+#define S5P_CLKDIV_TOP_ACLK133_MASK     (0x7 << S5P_CLKDIV_TOP_ACLK133_SHIFT)
+#define S5P_CLKDIV_TOP_ONENAND_SHIFT    (16)
+#define S5P_CLKDIV_TOP_ONENAND_MASK     (0x7 << S5P_CLKDIV_TOP_ONENAND_SHIFT)
+
+/* CLKDIV_LEFTBUS / CLKDIV_RIGHTBUS*/
+#define S5P_CLKDIV_BUS_GDLR_SHIFT       (0)
+#define S5P_CLKDIV_BUS_GDLR_MASK        (0x7 << S5P_CLKDIV_BUS_GDLR_SHIFT)
+#define S5P_CLKDIV_BUS_GPLR_SHIFT       (4)
+#define S5P_CLKDIV_BUS_GPLR_MASK        (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT)
+
 /* Compatibility defines */
 
 #define S5P_EPLL_CON                    S5P_EPLL_CON0
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-mem.h b/arch/arm/mach-s5pv310/include/mach/regs-mem.h
new file mode 100644
index 000000000000..834227140eaa
--- /dev/null
+++ b/arch/arm/mach-s5pv310/include/mach/regs-mem.h
@@ -0,0 +1,23 @@
+/* linux/arch/arm/mach-s5pv310/include/mach/regs-mem.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5PV310 - SROMC and DMC register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_MEM_H
+#define __ASM_ARCH_REGS_MEM_H __FILE__
+
+#include <mach/map.h>
+
+#define S5P_DMC0_MEMCON_OFFSET          0x04
+
+#define S5P_DMC0_MEMTYPE_SHIFT          8
+#define S5P_DMC0_MEMTYPE_MASK           0xF
+
+#endif /* __ASM_ARCH_REGS_MEM_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-pmu.h b/arch/arm/mach-s5pv310/include/mach/regs-pmu.h
new file mode 100644
index 000000000000..fb333d0f6073
--- /dev/null
+++ b/arch/arm/mach-s5pv310/include/mach/regs-pmu.h
@@ -0,0 +1,30 @@
+/* linux/arch/arm/mach-s5pv310/include/mach/regs-pmu.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5PV310 - Power management unit definition
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_PMU_H
+#define __ASM_ARCH_REGS_PMU_H __FILE__
+
+#include <mach/map.h>
+
+#define S5P_PMUREG(x)                   (S5P_VA_PMU + (x))
+
+#define S5P_PMU_CAM_CONF                S5P_PMUREG(0x3C00)
+#define S5P_PMU_TV_CONF         S5P_PMUREG(0x3C20)
+#define S5P_PMU_MFC_CONF                S5P_PMUREG(0x3C40)
+#define S5P_PMU_G3D_CONF                S5P_PMUREG(0x3C60)
+#define S5P_PMU_LCD0_CONF               S5P_PMUREG(0x3C80)
+#define S5P_PMU_LCD1_CONF               S5P_PMUREG(0x3CA0)
+#define S5P_PMU_GPS_CONF                S5P_PMUREG(0x3CE0)
+
+#define S5P_INT_LOCAL_PWR_EN            0x7
+
+#endif /* __ASM_ARCH_REGS_PMU_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-srom.h b/arch/arm/mach-s5pv310/include/mach/regs-srom.h
deleted file mode 100644
index 1898b3e10550..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/regs-srom.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* linux/arch/arm/mach-s5pv310/include/mach/regs-srom.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * S5PV310 - SROMC register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_SROM_H
-#define __ASM_ARCH_REGS_SROM_H __FILE__
-
-#include <mach/map.h>
-
-#define S5PV310_SROMREG(x)      (S5P_VA_SROMC + (x))
-
-#define S5PV310_SROM_BW         S5PV310_SROMREG(0x0)
-#define S5PV310_SROM_BC0        S5PV310_SROMREG(0x4)
-#define S5PV310_SROM_BC1        S5PV310_SROMREG(0x8)
-#define S5PV310_SROM_BC2        S5PV310_SROMREG(0xc)
-#define S5PV310_SROM_BC3        S5PV310_SROMREG(0x10)
-
-/* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */
-
-#define S5PV310_SROM_BW__DATAWIDTH__SHIFT       0
-#define S5PV310_SROM_BW__ADDRMODE__SHIFT        1
-#define S5PV310_SROM_BW__WAITENABLE__SHIFT      2
-#define S5PV310_SROM_BW__BYTEENABLE__SHIFT      3
-
-#define S5PV310_SROM_BW__CS_MASK                0xf
-
-#define S5PV310_SROM_BW__NCS0__SHIFT            0
-#define S5PV310_SROM_BW__NCS1__SHIFT            4
-#define S5PV310_SROM_BW__NCS2__SHIFT            8
-#define S5PV310_SROM_BW__NCS3__SHIFT            12
-
-/* applies to same to BCS0 - BCS3 */
-
-#define S5PV310_SROM_BCX__PMC__SHIFT            0
-#define S5PV310_SROM_BCX__TACP__SHIFT           4
-#define S5PV310_SROM_BCX__TCAH__SHIFT           8
-#define S5PV310_SROM_BCX__TCOH__SHIFT           12
-#define S5PV310_SROM_BCX__TACC__SHIFT           16
-#define S5PV310_SROM_BCX__TCOS__SHIFT           24
-#define S5PV310_SROM_BCX__TACS__SHIFT           28
-
-#endif /* __ASM_ARCH_REGS_SROM_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h b/arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h
new file mode 100644
index 000000000000..0b28e81a16f7
--- /dev/null
+++ b/arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h
@@ -0,0 +1,24 @@
+/* linux/arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5PV310 - System MMU register
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_SYSMMU_H
+#define __ASM_ARCH_REGS_SYSMMU_H __FILE__
+
+#define S5P_MMU_CTRL                    0x000
+#define S5P_MMU_CFG                     0x004
+#define S5P_MMU_STATUS                  0x008
+#define S5P_MMU_FLUSH                   0x00C
+#define S5P_PT_BASE_ADDR                0x014
+#define S5P_INT_STATUS                  0x018
+#define S5P_PAGE_FAULT_ADDR             0x024
+
+#endif /* __ASM_ARCH_REGS_SYSMMU_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/sysmmu.h b/arch/arm/mach-s5pv310/include/mach/sysmmu.h
new file mode 100644
index 000000000000..662fe85ff4d5
--- /dev/null
+++ b/arch/arm/mach-s5pv310/include/mach/sysmmu.h
@@ -0,0 +1,119 @@
+/* linux/arch/arm/mach-s5pv310/include/mach/sysmmu.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * Samsung sysmmu driver for S5PV310
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARM_ARCH_SYSMMU_H
+#define __ASM_ARM_ARCH_SYSMMU_H __FILE__
+
+enum s5pv310_sysmmu_ips {
+        SYSMMU_MDMA,
+        SYSMMU_SSS,
+        SYSMMU_FIMC0,
+        SYSMMU_FIMC1,
+        SYSMMU_FIMC2,
+        SYSMMU_FIMC3,
+        SYSMMU_JPEG,
+        SYSMMU_FIMD0,
+        SYSMMU_FIMD1,
+        SYSMMU_PCIe,
+        SYSMMU_G2D,
+        SYSMMU_ROTATOR,
+        SYSMMU_MDMA2,
+        SYSMMU_TV,
+        SYSMMU_MFC_L,
+        SYSMMU_MFC_R,
+};
+
+static char *sysmmu_ips_name[S5P_SYSMMU_TOTAL_IPNUM] = {
+        "SYSMMU_MDMA"   ,
+        "SYSMMU_SSS"    ,
+        "SYSMMU_FIMC0"  ,
+        "SYSMMU_FIMC1"  ,
+        "SYSMMU_FIMC2"  ,
+        "SYSMMU_FIMC3"  ,
+        "SYSMMU_JPEG"   ,
+        "SYSMMU_FIMD0"  ,
+        "SYSMMU_FIMD1"  ,
+        "SYSMMU_PCIe"   ,
+        "SYSMMU_G2D"    ,
+        "SYSMMU_ROTATOR",
+        "SYSMMU_MDMA2"  ,
+        "SYSMMU_TV"     ,
+        "SYSMMU_MFC_L"  ,
+        "SYSMMU_MFC_R"  ,
+};
+
+typedef enum s5pv310_sysmmu_ips sysmmu_ips;
+
+struct sysmmu_tt_info {
+        unsigned long *pgd;
+        unsigned long pgd_paddr;
+        unsigned long *pte;
+};
+
+struct sysmmu_controller {
+        const char              *name;
+
+        /* channels registers */
+        void __iomem            *regs;
+
+        /* channel irq */
+        unsigned int            irq;
+
+        sysmmu_ips              ips;
+
+        /* Translation Table Info. */
+        struct sysmmu_tt_info   *tt_info;
+
+        struct resource         *mem;
+        struct device           *dev;
+
+        /* SysMMU controller enable - true : enable */
+        bool                    enable;
+};
+
+/**
+ * s5p_sysmmu_enable() - enable system mmu of ip
+ * @ips: The ip connected system mmu.
+ *
+ * This function enable system mmu to transfer address
+ * from virtual address to physical address
+ */
+int s5p_sysmmu_enable(sysmmu_ips ips);
+
+/**
+ * s5p_sysmmu_disable() - disable sysmmu mmu of ip
+ * @ips: The ip connected system mmu.
+ *
+ * This function disable system mmu to transfer address
+ * from virtual address to physical address
+ */
+int s5p_sysmmu_disable(sysmmu_ips ips);
+
+/**
+ * s5p_sysmmu_set_tablebase_pgd() - set page table base address to refer page table
+ * @ips: The ip connected system mmu.
+ * @pgd: The page table base address.
+ *
+ * This function set page table base address
+ * When system mmu transfer address from virtaul address to physical address,
+ * system mmu refer address information from page table
+ */
+int s5p_sysmmu_set_tablebase_pgd(sysmmu_ips ips, unsigned long pgd);
+
+/**
+ * s5p_sysmmu_tlb_invalidate() - flush all TLB entry in system mmu
+ * @ips: The ip connected system mmu.
+ *
+ * This function flush all TLB entry in system mmu
+ */
+int s5p_sysmmu_tlb_invalidate(sysmmu_ips ips);
+#endif /* __ASM_ARM_ARCH_SYSMMU_H */
diff --git a/arch/arm/mach-s5pv310/irq-combiner.c b/arch/arm/mach-s5pv310/irq-combiner.c
index c3f88c3faf6c..1ea4a9e83bbe 100644
--- a/arch/arm/mach-s5pv310/irq-combiner.c
+++ b/arch/arm/mach-s5pv310/irq-combiner.c
@@ -24,29 +24,32 @@ static DEFINE_SPINLOCK(irq_controller_lock);
 
 struct combiner_chip_data {
         unsigned int irq_offset;
+        unsigned int irq_mask;
         void __iomem *base;
 };
 
 static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
 
-static inline void __iomem *combiner_base(unsigned int irq)
+static inline void __iomem *combiner_base(struct irq_data *data)
 {
-        struct combiner_chip_data *combiner_data = get_irq_chip_data(irq);
+        struct combiner_chip_data *combiner_data =
+                irq_data_get_irq_chip_data(data);
+
         return combiner_data->base;
 }
 
-static void combiner_mask_irq(unsigned int irq)
+static void combiner_mask_irq(struct irq_data *data)
 {
-        u32 mask = 1 << (irq % 32);
+        u32 mask = 1 << (data->irq % 32);
 
-        __raw_writel(mask, combiner_base(irq) + COMBINER_ENABLE_CLEAR);
+        __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
 }
 
-static void combiner_unmask_irq(unsigned int irq)
+static void combiner_unmask_irq(struct irq_data *data)
 {
-        u32 mask = 1 << (irq % 32);
+        u32 mask = 1 << (data->irq % 32);
 
-        __raw_writel(mask, combiner_base(irq) + COMBINER_ENABLE_SET);
+        __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
 }
 
 static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
@@ -57,11 +60,12 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
         unsigned long status;
 
         /* primary controller ack'ing */
-        chip->ack(irq);
+        chip->irq_ack(&desc->irq_data);
 
         spin_lock(&irq_controller_lock);
         status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
         spin_unlock(&irq_controller_lock);
+        status &= chip_data->irq_mask;
 
         if (status == 0)
                 goto out;
@@ -76,13 +80,13 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 
  out:
         /* primary controller unmasking */
-        chip->unmask(irq);
+        chip->irq_unmask(&desc->irq_data);
 }
 
 static struct irq_chip combiner_chip = {
         .name           = "COMBINER",
-        .mask           = combiner_mask_irq,
-        .unmask         = combiner_unmask_irq,
+        .irq_mask       = combiner_mask_irq,
+        .irq_unmask     = combiner_unmask_irq,
 };
 
 void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
@@ -104,10 +108,12 @@ void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
 
         combiner_data[combiner_nr].base = base;
         combiner_data[combiner_nr].irq_offset = irq_start;
+        combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
 
         /* Disable all interrupts */
 
-        __raw_writel(0xffffffff, base + COMBINER_ENABLE_CLEAR);
+        __raw_writel(combiner_data[combiner_nr].irq_mask,
+                     base + COMBINER_ENABLE_CLEAR);
 
         /* Setup the Linux IRQ subsystem */
 
diff --git a/arch/arm/mach-s5pv310/irq-eint.c b/arch/arm/mach-s5pv310/irq-eint.c
index 5877503e92c3..477bd9e97f0f 100644
--- a/arch/arm/mach-s5pv310/irq-eint.c
+++ b/arch/arm/mach-s5pv310/irq-eint.c
@@ -48,42 +48,43 @@ static unsigned int s5pv310_get_irq_nr(unsigned int number)
         return ret;
 }
 
-static inline void s5pv310_irq_eint_mask(unsigned int irq)
+static inline void s5pv310_irq_eint_mask(struct irq_data *data)
 {
         u32 mask;
 
         spin_lock(&eint_lock);
-        mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq)));
-        mask |= eint_irq_to_bit(irq);
-        __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq)));
+        mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+        mask |= eint_irq_to_bit(data->irq);
+        __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
         spin_unlock(&eint_lock);
 }
 
-static void s5pv310_irq_eint_unmask(unsigned int irq)
+static void s5pv310_irq_eint_unmask(struct irq_data *data)
 {
         u32 mask;
 
         spin_lock(&eint_lock);
-        mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq)));
-        mask &= ~(eint_irq_to_bit(irq));
-        __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq)));
+        mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+        mask &= ~(eint_irq_to_bit(data->irq));
+        __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
         spin_unlock(&eint_lock);
 }
 
-static inline void s5pv310_irq_eint_ack(unsigned int irq)
+static inline void s5pv310_irq_eint_ack(struct irq_data *data)
 {
-        __raw_writel(eint_irq_to_bit(irq), S5P_EINT_PEND(EINT_REG_NR(irq)));
+        __raw_writel(eint_irq_to_bit(data->irq),
+                     S5P_EINT_PEND(EINT_REG_NR(data->irq)));
 }
 
-static void s5pv310_irq_eint_maskack(unsigned int irq)
+static void s5pv310_irq_eint_maskack(struct irq_data *data)
 {
-        s5pv310_irq_eint_mask(irq);
-        s5pv310_irq_eint_ack(irq);
+        s5pv310_irq_eint_mask(data);
+        s5pv310_irq_eint_ack(data);
 }
 
-static int s5pv310_irq_eint_set_type(unsigned int irq, unsigned int type)
+static int s5pv310_irq_eint_set_type(struct irq_data *data, unsigned int type)
 {
-        int offs = EINT_OFFSET(irq);
+        int offs = EINT_OFFSET(data->irq);
         int shift;
         u32 ctrl, mask;
         u32 newvalue = 0;
@@ -118,10 +119,10 @@ static int s5pv310_irq_eint_set_type(unsigned int irq, unsigned int type)
         mask = 0x7 << shift;
 
         spin_lock(&eint_lock);
-        ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(irq)));
+        ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
         ctrl &= ~mask;
         ctrl |= newvalue << shift;
-        __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(irq)));
+        __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
         spin_unlock(&eint_lock);
 
         switch (offs) {
@@ -146,13 +147,13 @@ static int s5pv310_irq_eint_set_type(unsigned int irq, unsigned int type)
 
 static struct irq_chip s5pv310_irq_eint = {
         .name           = "s5pv310-eint",
-        .mask           = s5pv310_irq_eint_mask,
-        .unmask         = s5pv310_irq_eint_unmask,
-        .mask_ack       = s5pv310_irq_eint_maskack,
-        .ack            = s5pv310_irq_eint_ack,
-        .set_type       = s5pv310_irq_eint_set_type,
+        .irq_mask       = s5pv310_irq_eint_mask,
+        .irq_unmask     = s5pv310_irq_eint_unmask,
+        .irq_mask_ack   = s5pv310_irq_eint_maskack,
+        .irq_ack        = s5pv310_irq_eint_ack,
+        .irq_set_type   = s5pv310_irq_eint_set_type,
 #ifdef CONFIG_PM
-        .set_wake       = s3c_irqext_wake,
+        .irq_set_wake   = s3c_irqext_wake,
 #endif
 };
 
@@ -192,14 +193,14 @@ static void s5pv310_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
         u32 *irq_data = get_irq_data(irq);
         struct irq_chip *chip = get_irq_chip(irq);
 
-        chip->mask(irq);
+        chip->irq_mask(&desc->irq_data);
 
-        if (chip->ack)
-                chip->ack(irq);
+        if (chip->irq_ack)
+                chip->irq_ack(&desc->irq_data);
 
         generic_handle_irq(*irq_data);
 
-        chip->unmask(irq);
+        chip->irq_unmask(&desc->irq_data);
 }
 
 int __init s5pv310_init_irq_eint(void)
diff --git a/arch/arm/mach-s5pv310/mach-smdkc210.c b/arch/arm/mach-s5pv310/mach-smdkc210.c
index 2b8d4fc52d7c..2d49273c0a26 100644
--- a/arch/arm/mach-s5pv310/mach-smdkc210.c
+++ b/arch/arm/mach-s5pv310/mach-smdkc210.c
@@ -14,18 +14,21 @@
 #include <linux/platform_device.h>
 #include <linux/smsc911x.h>
 #include <linux/io.h>
+#include <linux/i2c.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
 #include <plat/regs-serial.h>
+#include <plat/regs-srom.h>
 #include <plat/s5pv310.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/sdhci.h>
+#include <plat/iic.h>
+#include <plat/pd.h>
 
 #include <mach/map.h>
-#include <mach/regs-srom.h>
 
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define SMDKC210_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
@@ -139,14 +142,29 @@ static struct platform_device smdkc210_smsc911x = {
         },
 };
 
+static struct i2c_board_info i2c_devs1[] __initdata = {
+        {I2C_BOARD_INFO("wm8994", 0x1a),},
+};
+
 static struct platform_device *smdkc210_devices[] __initdata = {
         &s3c_device_hsmmc0,
         &s3c_device_hsmmc1,
         &s3c_device_hsmmc2,
         &s3c_device_hsmmc3,
+        &s3c_device_i2c1,
         &s3c_device_rtc,
         &s3c_device_wdt,
+        &s5pv310_device_ac97,
+        &s5pv310_device_i2s0,
+        &s5pv310_device_pd[PD_MFC],
+        &s5pv310_device_pd[PD_G3D],
+        &s5pv310_device_pd[PD_LCD0],
+        &s5pv310_device_pd[PD_LCD1],
+        &s5pv310_device_pd[PD_CAM],
+        &s5pv310_device_pd[PD_TV],
+        &s5pv310_device_pd[PD_GPS],
         &smdkc210_smsc911x,
+        &s5pv310_device_sysmmu,
 };
 
 static void __init smdkc210_smsc911x_init(void)
@@ -154,23 +172,22 @@ static void __init smdkc210_smsc911x_init(void)
         u32 cs1;
 
         /* configure nCS1 width to 16 bits */
-        cs1 = __raw_readl(S5PV310_SROM_BW) &
-                    ~(S5PV310_SROM_BW__CS_MASK <<
-                                    S5PV310_SROM_BW__NCS1__SHIFT);
-        cs1 |= ((1 << S5PV310_SROM_BW__DATAWIDTH__SHIFT) |
-                (1 << S5PV310_SROM_BW__WAITENABLE__SHIFT) |
-                (1 << S5PV310_SROM_BW__BYTEENABLE__SHIFT)) <<
-                S5PV310_SROM_BW__NCS1__SHIFT;
-        __raw_writel(cs1, S5PV310_SROM_BW);
+        cs1 = __raw_readl(S5P_SROM_BW) &
+                ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
+        cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
+                (1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
+                (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
+                S5P_SROM_BW__NCS1__SHIFT;
+        __raw_writel(cs1, S5P_SROM_BW);
 
         /* set timing for nCS1 suitable for ethernet chip */
-        __raw_writel((0x1 << S5PV310_SROM_BCX__PMC__SHIFT) |
-                     (0x9 << S5PV310_SROM_BCX__TACP__SHIFT) |
-                     (0xc << S5PV310_SROM_BCX__TCAH__SHIFT) |
-                     (0x1 << S5PV310_SROM_BCX__TCOH__SHIFT) |
-                     (0x6 << S5PV310_SROM_BCX__TACC__SHIFT) |
-                     (0x1 << S5PV310_SROM_BCX__TCOS__SHIFT) |
-                     (0x1 << S5PV310_SROM_BCX__TACS__SHIFT), S5PV310_SROM_BC1);
+        __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
+                     (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
+                     (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
+                     (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
+                     (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
+                     (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
+                     (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
 }
 
 static void __init smdkc210_map_io(void)
@@ -182,6 +199,9 @@ static void __init smdkc210_map_io(void)
 
 static void __init smdkc210_machine_init(void)
 {
+        s3c_i2c1_set_platdata(NULL);
+        i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
+
         smdkc210_smsc911x_init();
 
         s3c_sdhci0_set_platdata(&smdkc210_hsmmc0_pdata);
diff --git a/arch/arm/mach-s5pv310/mach-smdkv310.c b/arch/arm/mach-s5pv310/mach-smdkv310.c
index 35826d66632c..28680cf9a72c 100644
--- a/arch/arm/mach-s5pv310/mach-smdkv310.c
+++ b/arch/arm/mach-s5pv310/mach-smdkv310.c
@@ -14,18 +14,21 @@
 #include <linux/platform_device.h>
 #include <linux/smsc911x.h>
 #include <linux/io.h>
+#include <linux/i2c.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
 #include <plat/regs-serial.h>
+#include <plat/regs-srom.h>
 #include <plat/s5pv310.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/sdhci.h>
+#include <plat/iic.h>
+#include <plat/pd.h>
 
 #include <mach/map.h>
-#include <mach/regs-srom.h>
 
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define SMDKV310_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
@@ -139,14 +142,29 @@ static struct platform_device smdkv310_smsc911x = {
         },
 };
 
+static struct i2c_board_info i2c_devs1[] __initdata = {
+        {I2C_BOARD_INFO("wm8994", 0x1a),},
+};
+
 static struct platform_device *smdkv310_devices[] __initdata = {
         &s3c_device_hsmmc0,
         &s3c_device_hsmmc1,
         &s3c_device_hsmmc2,
         &s3c_device_hsmmc3,
+        &s3c_device_i2c1,
         &s3c_device_rtc,
         &s3c_device_wdt,
+        &s5pv310_device_ac97,
+        &s5pv310_device_i2s0,
+        &s5pv310_device_pd[PD_MFC],
+        &s5pv310_device_pd[PD_G3D],
+        &s5pv310_device_pd[PD_LCD0],
+        &s5pv310_device_pd[PD_LCD1],
+        &s5pv310_device_pd[PD_CAM],
+        &s5pv310_device_pd[PD_TV],
+        &s5pv310_device_pd[PD_GPS],
         &smdkv310_smsc911x,
+        &s5pv310_device_sysmmu,
 };
 
 static void __init smdkv310_smsc911x_init(void)
@@ -154,23 +172,22 @@ static void __init smdkv310_smsc911x_init(void)
         u32 cs1;
 
         /* configure nCS1 width to 16 bits */
-        cs1 = __raw_readl(S5PV310_SROM_BW) &
-                    ~(S5PV310_SROM_BW__CS_MASK <<
-                                    S5PV310_SROM_BW__NCS1__SHIFT);
-        cs1 |= ((1 << S5PV310_SROM_BW__DATAWIDTH__SHIFT) |
-                (1 << S5PV310_SROM_BW__WAITENABLE__SHIFT) |
-                (1 << S5PV310_SROM_BW__BYTEENABLE__SHIFT)) <<
-                S5PV310_SROM_BW__NCS1__SHIFT;
-        __raw_writel(cs1, S5PV310_SROM_BW);
+        cs1 = __raw_readl(S5P_SROM_BW) &
+                ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
+        cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
+                (1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
+                (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
+                S5P_SROM_BW__NCS1__SHIFT;
+        __raw_writel(cs1, S5P_SROM_BW);
 
         /* set timing for nCS1 suitable for ethernet chip */
-        __raw_writel((0x1 << S5PV310_SROM_BCX__PMC__SHIFT) |
-                     (0x9 << S5PV310_SROM_BCX__TACP__SHIFT) |
-                     (0xc << S5PV310_SROM_BCX__TCAH__SHIFT) |
-                     (0x1 << S5PV310_SROM_BCX__TCOH__SHIFT) |
-                     (0x6 << S5PV310_SROM_BCX__TACC__SHIFT) |
-                     (0x1 << S5PV310_SROM_BCX__TCOS__SHIFT) |
-                     (0x1 << S5PV310_SROM_BCX__TACS__SHIFT), S5PV310_SROM_BC1);
+        __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
+                     (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
+                     (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
+                     (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
+                     (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
+                     (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
+                     (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
 }
 
 static void __init smdkv310_map_io(void)
@@ -182,6 +199,9 @@ static void __init smdkv310_map_io(void)
 
 static void __init smdkv310_machine_init(void)
 {
+        s3c_i2c1_set_platdata(NULL);
+        i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
+
         smdkv310_smsc911x_init();
 
         s3c_sdhci0_set_platdata(&smdkv310_hsmmc0_pdata);
diff --git a/arch/arm/mach-s5pv310/mach-universal_c210.c b/arch/arm/mach-s5pv310/mach-universal_c210.c
index 16d8fc00cafd..36bc3cf825e3 100644
--- a/arch/arm/mach-s5pv310/mach-universal_c210.c
+++ b/arch/arm/mach-s5pv310/mach-universal_c210.c
@@ -13,6 +13,9 @@
 #include <linux/i2c.h>
 #include <linux/gpio_keys.h>
 #include <linux/gpio.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/mmc/host.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
@@ -21,6 +24,7 @@
 #include <plat/s5pv310.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
+#include <plat/sdhci.h>
 
 #include <mach/map.h>
 
@@ -116,6 +120,73 @@ static struct platform_device universal_gpio_keys = {
         },
 };
 
+/* eMMC */
+static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
+        .max_width              = 8,
+        .host_caps              = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
+                                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
+                                MMC_CAP_DISABLE),
+        .cd_type                = S3C_SDHCI_CD_PERMANENT,
+        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+static struct regulator_consumer_supply mmc0_supplies[] = {
+        REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
+};
+
+static struct regulator_init_data mmc0_fixed_voltage_init_data = {
+        .constraints            = {
+                .name           = "VMEM_VDD_2.8V",
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(mmc0_supplies),
+        .consumer_supplies      = mmc0_supplies,
+};
+
+static struct fixed_voltage_config mmc0_fixed_voltage_config = {
+        .supply_name            = "MASSMEMORY_EN",
+        .microvolts             = 2800000,
+        .gpio                   = S5PV310_GPE1(3),
+        .enable_high            = true,
+        .init_data              = &mmc0_fixed_voltage_init_data,
+};
+
+static struct platform_device mmc0_fixed_voltage = {
+        .name                   = "reg-fixed-voltage",
+        .id                     = 0,
+        .dev                    = {
+                .platform_data  = &mmc0_fixed_voltage_config,
+        },
+};
+
+/* SD */
+static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {
+        .max_width              = 4,
+        .host_caps              = MMC_CAP_4_BIT_DATA |
+                                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
+                                MMC_CAP_DISABLE,
+        .ext_cd_gpio            = S5PV310_GPX3(4),      /* XEINT_28 */
+        .ext_cd_gpio_invert     = 1,
+        .cd_type                = S3C_SDHCI_CD_GPIO,
+        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+/* WiFi */
+static struct s3c_sdhci_platdata universal_hsmmc3_data __initdata = {
+        .max_width              = 4,
+        .host_caps              = MMC_CAP_4_BIT_DATA |
+                                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
+                                MMC_CAP_DISABLE,
+        .cd_type                = S3C_SDHCI_CD_EXTERNAL,
+};
+
+static void __init universal_sdhci_init(void)
+{
+        s3c_sdhci0_set_platdata(&universal_hsmmc0_data);
+        s3c_sdhci2_set_platdata(&universal_hsmmc2_data);
+        s3c_sdhci3_set_platdata(&universal_hsmmc3_data);
+}
+
 /* I2C0 */
 static struct i2c_board_info i2c0_devs[] __initdata = {
         /* Camera, To be updated */
@@ -127,6 +198,13 @@ static struct i2c_board_info i2c1_devs[] __initdata = {
 };
 
 static struct platform_device *universal_devices[] __initdata = {
+        /* Samsung Platform Devices */
+        &mmc0_fixed_voltage,
+        &s3c_device_hsmmc0,
+        &s3c_device_hsmmc2,
+        &s3c_device_hsmmc3,
+
+        /* Universal Devices */
         &universal_gpio_keys,
         &s5p_device_onenand,
 };
@@ -140,6 +218,8 @@ static void __init universal_map_io(void)
 
 static void __init universal_machine_init(void)
 {
+        universal_sdhci_init();
+
         i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
         i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
 
diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c
index 3093d46a9c6f..3d85dfad9c1f 100644
--- a/arch/arm/mach-sa1100/irq.c
+++ b/arch/arm/mach-sa1100/irq.c
@@ -37,14 +37,14 @@ static int GPIO_IRQ_mask = (1 << 11) - 1;
 #define GPIO_11_27_IRQ(i)       ((i) - 21)
 #define GPIO11_27_MASK(irq)     (1 << GPIO_11_27_IRQ(irq))
 
-static int sa1100_gpio_type(unsigned int irq, unsigned int type)
+static int sa1100_gpio_type(struct irq_data *d, unsigned int type)
 {
         unsigned int mask;
 
-        if (irq <= 10)
-                mask = 1 << irq;
+        if (d->irq <= 10)
+                mask = 1 << d->irq;
         else
-                mask = GPIO11_27_MASK(irq);
+                mask = GPIO11_27_MASK(d->irq);
 
         if (type == IRQ_TYPE_PROBE) {
                 if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
@@ -70,37 +70,37 @@ static int sa1100_gpio_type(unsigned int irq, unsigned int type)
 /*
  * GPIO IRQs must be acknowledged.  This is for IRQs from 0 to 10.
  */
-static void sa1100_low_gpio_ack(unsigned int irq)
+static void sa1100_low_gpio_ack(struct irq_data *d)
 {
-        GEDR = (1 << irq);
+        GEDR = (1 << d->irq);
 }
 
-static void sa1100_low_gpio_mask(unsigned int irq)
+static void sa1100_low_gpio_mask(struct irq_data *d)
 {
-        ICMR &= ~(1 << irq);
+        ICMR &= ~(1 << d->irq);
 }
 
-static void sa1100_low_gpio_unmask(unsigned int irq)
+static void sa1100_low_gpio_unmask(struct irq_data *d)
 {
-        ICMR |= 1 << irq;
+        ICMR |= 1 << d->irq;
 }
 
-static int sa1100_low_gpio_wake(unsigned int irq, unsigned int on)
+static int sa1100_low_gpio_wake(struct irq_data *d, unsigned int on)
 {
         if (on)
-                PWER |= 1 << irq;
+                PWER |= 1 << d->irq;
         else
-                PWER &= ~(1 << irq);
+                PWER &= ~(1 << d->irq);
         return 0;
 }
 
 static struct irq_chip sa1100_low_gpio_chip = {
         .name           = "GPIO-l",
-        .ack            = sa1100_low_gpio_ack,
-        .mask           = sa1100_low_gpio_mask,
-        .unmask         = sa1100_low_gpio_unmask,
-        .set_type       = sa1100_gpio_type,
-        .set_wake       = sa1100_low_gpio_wake,
+        .irq_ack        = sa1100_low_gpio_ack,
+        .irq_mask       = sa1100_low_gpio_mask,
+        .irq_unmask     = sa1100_low_gpio_unmask,
+        .irq_set_type   = sa1100_gpio_type,
+        .irq_set_wake   = sa1100_low_gpio_wake,
 };
 
 /*
@@ -139,16 +139,16 @@ sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc)
  * In addition, the IRQs are all collected up into one bit in the
  * interrupt controller registers.
  */
-static void sa1100_high_gpio_ack(unsigned int irq)
+static void sa1100_high_gpio_ack(struct irq_data *d)
 {
-        unsigned int mask = GPIO11_27_MASK(irq);
+        unsigned int mask = GPIO11_27_MASK(d->irq);
 
         GEDR = mask;
 }
 
-static void sa1100_high_gpio_mask(unsigned int irq)
+static void sa1100_high_gpio_mask(struct irq_data *d)
 {
-        unsigned int mask = GPIO11_27_MASK(irq);
+        unsigned int mask = GPIO11_27_MASK(d->irq);
 
         GPIO_IRQ_mask &= ~mask;
 
@@ -156,9 +156,9 @@ static void sa1100_high_gpio_mask(unsigned int irq)
         GFER &= ~mask;
 }
 
-static void sa1100_high_gpio_unmask(unsigned int irq)
+static void sa1100_high_gpio_unmask(struct irq_data *d)
 {
-        unsigned int mask = GPIO11_27_MASK(irq);
+        unsigned int mask = GPIO11_27_MASK(d->irq);
 
         GPIO_IRQ_mask |= mask;
 
@@ -166,44 +166,44 @@ static void sa1100_high_gpio_unmask(unsigned int irq)
         GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
 }
 
-static int sa1100_high_gpio_wake(unsigned int irq, unsigned int on)
+static int sa1100_high_gpio_wake(struct irq_data *d, unsigned int on)
 {
         if (on)
-                PWER |= GPIO11_27_MASK(irq);
+                PWER |= GPIO11_27_MASK(d->irq);
         else
-                PWER &= ~GPIO11_27_MASK(irq);
+                PWER &= ~GPIO11_27_MASK(d->irq);
         return 0;
 }
 
 static struct irq_chip sa1100_high_gpio_chip = {
         .name           = "GPIO-h",
-        .ack            = sa1100_high_gpio_ack,
-        .mask           = sa1100_high_gpio_mask,
-        .unmask         = sa1100_high_gpio_unmask,
-        .set_type       = sa1100_gpio_type,
-        .set_wake       = sa1100_high_gpio_wake,
+        .irq_ack        = sa1100_high_gpio_ack,
+        .irq_mask       = sa1100_high_gpio_mask,
+        .irq_unmask     = sa1100_high_gpio_unmask,
+        .irq_set_type   = sa1100_gpio_type,
+        .irq_set_wake   = sa1100_high_gpio_wake,
 };
 
 /*
  * We don't need to ACK IRQs on the SA1100 unless they're GPIOs
  * this is for internal IRQs i.e. from 11 to 31.
  */
-static void sa1100_mask_irq(unsigned int irq)
+static void sa1100_mask_irq(struct irq_data *d)
 {
-        ICMR &= ~(1 << irq);
+        ICMR &= ~(1 << d->irq);
 }
 
-static void sa1100_unmask_irq(unsigned int irq)
+static void sa1100_unmask_irq(struct irq_data *d)
 {
-        ICMR |= (1 << irq);
+        ICMR |= (1 << d->irq);
 }
 
 /*
  * Apart form GPIOs, only the RTC alarm can be a wakeup event.
  */
-static int sa1100_set_wake(unsigned int irq, unsigned int on)
+static int sa1100_set_wake(struct irq_data *d, unsigned int on)
 {
-        if (irq == IRQ_RTCAlrm) {
+        if (d->irq == IRQ_RTCAlrm) {
                 if (on)
                         PWER |= PWER_RTC;
                 else
@@ -215,10 +215,10 @@ static int sa1100_set_wake(unsigned int irq, unsigned int on)
 
 static struct irq_chip sa1100_normal_chip = {
         .name           = "SC",
-        .ack            = sa1100_mask_irq,
-        .mask           = sa1100_mask_irq,
-        .unmask         = sa1100_unmask_irq,
-        .set_wake       = sa1100_set_wake,
+        .irq_ack        = sa1100_mask_irq,
+        .irq_mask       = sa1100_mask_irq,
+        .irq_unmask     = sa1100_unmask_irq,
+        .irq_set_wake   = sa1100_set_wake,
 };
 
 static struct resource irq_resource = {
diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c
index c601a75a333d..4aad01f73660 100644
--- a/arch/arm/mach-sa1100/neponset.c
+++ b/arch/arm/mach-sa1100/neponset.c
@@ -35,7 +35,7 @@ neponset_irq_handler(unsigned int irq, struct irq_desc *desc)
                 /*
                  * Acknowledge the parent IRQ.
                  */
-                desc->chip->ack(irq);
+                desc->irq_data.chip->irq_ack(&desc->irq_data);
 
                 /*
                  * Read the interrupt reason register.  Let's have all
@@ -53,7 +53,7 @@ neponset_irq_handler(unsigned int irq, struct irq_desc *desc)
                  * recheck the register for any pending IRQs.
                  */
                 if (irr & (IRR_ETHERNET | IRR_USAR)) {
-                        desc->chip->mask(irq);
+                        desc->irq_data.chip->irq_mask(&desc->irq_data);
 
                         /*
                          * Ack the interrupt now to prevent re-entering
@@ -61,7 +61,7 @@ neponset_irq_handler(unsigned int irq, struct irq_desc *desc)
                          * since we'll check the IRR register prior to
                          * leaving.
                          */
-                        desc->chip->ack(irq);
+                        desc->irq_data.chip->irq_ack(&desc->irq_data);
 
                         if (irr & IRR_ETHERNET) {
                                 generic_handle_irq(IRQ_NEPONSET_SMC9196);
@@ -71,7 +71,7 @@ neponset_irq_handler(unsigned int irq, struct irq_desc *desc)
                                 generic_handle_irq(IRQ_NEPONSET_USAR);
                         }
 
-                        desc->chip->unmask(irq);
+                        desc->irq_data.chip->irq_unmask(&desc->irq_data);
                 }
 
                 if (irr & IRR_SA1111) {
diff --git a/arch/arm/mach-shark/irq.c b/arch/arm/mach-shark/irq.c
index c04eb6a1e2be..831fc66dfa4d 100644
--- a/arch/arm/mach-shark/irq.c
+++ b/arch/arm/mach-shark/irq.c
@@ -30,35 +30,35 @@ static unsigned char cached_irq_mask[2] = { 0xfb, 0xff };
  * These have to be protected by the irq controller spinlock
  * before being called.
  */
-static void shark_disable_8259A_irq(unsigned int irq)
+static void shark_disable_8259A_irq(struct irq_data *d)
 {
         unsigned int mask;
-        if (irq<8) {
-          mask = 1 << irq;
+        if (d->irq<8) {
+          mask = 1 << d->irq;
           cached_irq_mask[0] |= mask;
           outb(cached_irq_mask[1],0xA1);
         } else {
-          mask = 1 << (irq-8);
+          mask = 1 << (d->irq-8);
           cached_irq_mask[1] |= mask;
           outb(cached_irq_mask[0],0x21);
         }
 }
 
-static void shark_enable_8259A_irq(unsigned int irq)
+static void shark_enable_8259A_irq(struct irq_data *d)
 {
         unsigned int mask;
-        if (irq<8) {
-          mask = ~(1 << irq);
+        if (d->irq<8) {
+          mask = ~(1 << d->irq);
           cached_irq_mask[0] &= mask;
           outb(cached_irq_mask[0],0x21);
         } else {
-          mask = ~(1 << (irq-8));
+          mask = ~(1 << (d->irq-8));
           cached_irq_mask[1] &= mask;
           outb(cached_irq_mask[1],0xA1);
         }
 }
 
-static void shark_ack_8259A_irq(unsigned int irq){}
+static void shark_ack_8259A_irq(struct irq_data *d){}
 
 static irqreturn_t bogus_int(int irq, void *dev_id)
 {
@@ -69,10 +69,10 @@ static irqreturn_t bogus_int(int irq, void *dev_id)
 static struct irqaction cascade;
 
 static struct irq_chip fb_chip = {
-        .name   = "XT-PIC",
-        .ack    = shark_ack_8259A_irq,
-        .mask   = shark_disable_8259A_irq,
-        .unmask = shark_enable_8259A_irq,
+        .name           = "XT-PIC",
+        .irq_ack        = shark_ack_8259A_irq,
+        .irq_mask       = shark_disable_8259A_irq,
+        .irq_unmask     = shark_enable_8259A_irq,
 };
 
 void __init shark_init_irq(void)
diff --git a/arch/arm/mach-stmp378x/stmp378x.c b/arch/arm/mach-stmp378x/stmp378x.c
index ddd49a760fd4..c2f9fe04c112 100644
--- a/arch/arm/mach-stmp378x/stmp378x.c
+++ b/arch/arm/mach-stmp378x/stmp378x.c
@@ -47,7 +47,7 @@
 /*
  * IRQ handling
  */
-static void stmp378x_ack_irq(unsigned int irq)
+static void stmp378x_ack_irq(struct irq_data *d)
 {
         /* Tell ICOLL to release IRQ line */
         __raw_writel(0, REGS_ICOLL_BASE + HW_ICOLL_VECTOR);
@@ -60,24 +60,24 @@ static void stmp378x_ack_irq(unsigned int irq)
         (void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT);
 }
 
-static void stmp378x_mask_irq(unsigned int irq)
+static void stmp378x_mask_irq(struct irq_data *d)
 {
         /* IRQ disable */
         stmp3xxx_clearl(BM_ICOLL_INTERRUPTn_ENABLE,
-                        REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + irq * 0x10);
+                        REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + d->irq * 0x10);
 }
 
-static void stmp378x_unmask_irq(unsigned int irq)
+static void stmp378x_unmask_irq(struct irq_data *d)
 {
         /* IRQ enable */
         stmp3xxx_setl(BM_ICOLL_INTERRUPTn_ENABLE,
-                      REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + irq * 0x10);
+                      REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + d->irq * 0x10);
 }
 
 static struct irq_chip stmp378x_chip = {
-        .ack    = stmp378x_ack_irq,
-        .mask   = stmp378x_mask_irq,
-        .unmask = stmp378x_unmask_irq,
+        .irq_ack        = stmp378x_ack_irq,
+        .irq_mask       = stmp378x_mask_irq,
+        .irq_unmask     = stmp378x_unmask_irq,
 };
 
 void __init stmp378x_init_irq(void)
diff --git a/arch/arm/mach-stmp37xx/stmp37xx.c b/arch/arm/mach-stmp37xx/stmp37xx.c
index 8c7d6fb191a3..a9aed06ff376 100644
--- a/arch/arm/mach-stmp37xx/stmp37xx.c
+++ b/arch/arm/mach-stmp37xx/stmp37xx.c
@@ -43,11 +43,11 @@
 /*
  * IRQ handling
  */
-static void stmp37xx_ack_irq(unsigned int irq)
+static void stmp37xx_ack_irq(struct irq_data *d)
 {
         /* Disable IRQ */
-        stmp3xxx_clearl(0x04 << ((irq % 4) * 8),
-                REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + irq / 4 * 0x10);
+        stmp3xxx_clearl(0x04 << ((d->irq % 4) * 8),
+                REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + d->irq / 4 * 0x10);
 
         /* ACK current interrupt */
         __raw_writel(1, REGS_ICOLL_BASE + HW_ICOLL_LEVELACK);
@@ -56,24 +56,24 @@ static void stmp37xx_ack_irq(unsigned int irq)
         (void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT);
 }
 
-static void stmp37xx_mask_irq(unsigned int irq)
+static void stmp37xx_mask_irq(struct irq_data *d)
 {
         /* IRQ disable */
-        stmp3xxx_clearl(0x04 << ((irq % 4) * 8),
-                REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + irq / 4 * 0x10);
+        stmp3xxx_clearl(0x04 << ((d->irq % 4) * 8),
+                REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + d->irq / 4 * 0x10);
 }
 
-static void stmp37xx_unmask_irq(unsigned int irq)
+static void stmp37xx_unmask_irq(struct irq_data *d)
 {
         /* IRQ enable */
-        stmp3xxx_setl(0x04 << ((irq % 4) * 8),
-                REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + irq / 4 * 0x10);
+        stmp3xxx_setl(0x04 << ((d->irq % 4) * 8),
+                REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + d->irq / 4 * 0x10);
 }
 
 static struct irq_chip stmp37xx_chip = {
-        .ack    = stmp37xx_ack_irq,
-        .mask   = stmp37xx_mask_irq,
-        .unmask = stmp37xx_unmask_irq,
+        .irq_ack        = stmp37xx_ack_irq,
+        .irq_mask       = stmp37xx_mask_irq,
+        .irq_unmask     = stmp37xx_unmask_irq,
 };
 
 void __init stmp37xx_init_irq(void)
diff --git a/arch/arm/mach-tcc8k/irq.c b/arch/arm/mach-tcc8k/irq.c
index 34575c4963f0..aa9231f4fc6e 100644
--- a/arch/arm/mach-tcc8k/irq.c
+++ b/arch/arm/mach-tcc8k/irq.c
@@ -18,65 +18,65 @@
 #include "common.h"
 
 /* Disable IRQ */
-static void tcc8000_mask_ack_irq0(unsigned int irq)
+static void tcc8000_mask_ack_irq0(struct irq_data *d)
 {
-        PIC0_IEN &= ~(1 << irq);
-        PIC0_CREQ |=  (1 << irq);
+        PIC0_IEN &= ~(1 << d->irq);
+        PIC0_CREQ |=  (1 << d->irq);
 }
 
-static void tcc8000_mask_ack_irq1(unsigned int irq)
+static void tcc8000_mask_ack_irq1(struct irq_data *d)
 {
-        PIC1_IEN &= ~(1 << (irq - 32));
-        PIC1_CREQ |= (1 << (irq - 32));
+        PIC1_IEN &= ~(1 << (d->irq - 32));
+        PIC1_CREQ |= (1 << (d->irq - 32));
 }
 
-static void tcc8000_mask_irq0(unsigned int irq)
+static void tcc8000_mask_irq0(struct irq_data *d)
 {
-        PIC0_IEN &= ~(1 << irq);
+        PIC0_IEN &= ~(1 << d->irq);
 }
 
-static void tcc8000_mask_irq1(unsigned int irq)
+static void tcc8000_mask_irq1(struct irq_data *d)
 {
-        PIC1_IEN &= ~(1 << (irq - 32));
+        PIC1_IEN &= ~(1 << (d->irq - 32));
 }
 
-static void tcc8000_ack_irq0(unsigned int irq)
+static void tcc8000_ack_irq0(struct irq_data *d)
 {
-        PIC0_CREQ |=  (1 << irq);
+        PIC0_CREQ |=  (1 << d->irq);
 }
 
-static void tcc8000_ack_irq1(unsigned int irq)
+static void tcc8000_ack_irq1(struct irq_data *d)
 {
-        PIC1_CREQ |= (1 << (irq - 32));
+        PIC1_CREQ |= (1 << (d->irq - 32));
 }
 
 /* Enable IRQ */
-static void tcc8000_unmask_irq0(unsigned int irq)
+static void tcc8000_unmask_irq0(struct irq_data *d)
 {
-        PIC0_IEN |= (1 << irq);
-        PIC0_INTOEN |= (1 << irq);
+        PIC0_IEN |= (1 << d->irq);
+        PIC0_INTOEN |= (1 << d->irq);
 }
 
-static void tcc8000_unmask_irq1(unsigned int irq)
+static void tcc8000_unmask_irq1(struct irq_data *d)
 {
-        PIC1_IEN |= (1 << (irq - 32));
-        PIC1_INTOEN |= (1 << (irq - 32));
+        PIC1_IEN |= (1 << (d->irq - 32));
+        PIC1_INTOEN |= (1 << (d->irq - 32));
 }
 
 static struct irq_chip tcc8000_irq_chip0 = {
         .name           = "tcc_irq0",
-        .mask           = tcc8000_mask_irq0,
-        .ack            = tcc8000_ack_irq0,
-        .mask_ack       = tcc8000_mask_ack_irq0,
-        .unmask         = tcc8000_unmask_irq0,
+        .irq_mask       = tcc8000_mask_irq0,
+        .irq_ack        = tcc8000_ack_irq0,
+        .irq_mask_ack   = tcc8000_mask_ack_irq0,
+        .irq_unmask     = tcc8000_unmask_irq0,
 };
 
 static struct irq_chip tcc8000_irq_chip1 = {
         .name           = "tcc_irq1",
-        .mask           = tcc8000_mask_irq1,
-        .ack            = tcc8000_ack_irq1,
-        .mask_ack       = tcc8000_mask_ack_irq1,
-        .unmask         = tcc8000_unmask_irq1,
+        .irq_mask       = tcc8000_mask_irq1,
+        .irq_ack        = tcc8000_ack_irq1,
+        .irq_mask_ack   = tcc8000_mask_ack_irq1,
+        .irq_unmask     = tcc8000_unmask_irq1,
 };
 
 void __init tcc8k_init_irq(void)
diff --git a/arch/arm/mach-tegra/gpio.c b/arch/arm/mach-tegra/gpio.c
index 0775265e69f5..bd066206e110 100644
--- a/arch/arm/mach-tegra/gpio.c
+++ b/arch/arm/mach-tegra/gpio.c
@@ -142,31 +142,31 @@ static struct gpio_chip tegra_gpio_chip = {
         .ngpio                  = TEGRA_NR_GPIOS,
 };
 
-static void tegra_gpio_irq_ack(unsigned int irq)
+static void tegra_gpio_irq_ack(struct irq_data *d)
 {
-        int gpio = irq - INT_GPIO_BASE;
+        int gpio = d->irq - INT_GPIO_BASE;
 
         __raw_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
 }
 
-static void tegra_gpio_irq_mask(unsigned int irq)
+static void tegra_gpio_irq_mask(struct irq_data *d)
 {
-        int gpio = irq - INT_GPIO_BASE;
+        int gpio = d->irq - INT_GPIO_BASE;
 
         tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
 }
 
-static void tegra_gpio_irq_unmask(unsigned int irq)
+static void tegra_gpio_irq_unmask(struct irq_data *d)
 {
-        int gpio = irq - INT_GPIO_BASE;
+        int gpio = d->irq - INT_GPIO_BASE;
 
         tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
 }
 
-static int tegra_gpio_irq_set_type(unsigned int irq, unsigned int type)
+static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 {
-        int gpio = irq - INT_GPIO_BASE;
-        struct tegra_gpio_bank *bank = get_irq_chip_data(irq);
+        int gpio = d->irq - INT_GPIO_BASE;
+        struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
         int port = GPIO_PORT(gpio);
         int lvl_type;
         int val;
@@ -221,7 +221,7 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
         int pin;
         int unmasked = 0;
 
-        desc->chip->ack(irq);
+        desc->irq_data.chip->irq_ack(&desc->irq_data);
 
         bank = get_irq_data(irq);
 
@@ -240,7 +240,7 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
                          */
                         if (lvl & (0x100 << pin)) {
                                 unmasked = 1;
-                                desc->chip->unmask(irq);
+                                desc->irq_data.chip->irq_unmask(&desc->irq_data);
                         }
 
                         generic_handle_irq(gpio_to_irq(gpio + pin));
@@ -248,7 +248,7 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
         }
 
         if (!unmasked)
-                desc->chip->unmask(irq);
+                desc->irq_data.chip->irq_unmask(&desc->irq_data);
 
 }
 
@@ -316,21 +316,21 @@ void tegra_gpio_suspend(void)
         local_irq_restore(flags);
 }
 
-static int tegra_gpio_wake_enable(unsigned int irq, unsigned int enable)
+static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
 {
-        struct tegra_gpio_bank *bank = get_irq_chip_data(irq);
+        struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
         return set_irq_wake(bank->irq, enable);
 }
 #endif
 
 static struct irq_chip tegra_gpio_irq_chip = {
         .name           = "GPIO",
-        .ack            = tegra_gpio_irq_ack,
-        .mask           = tegra_gpio_irq_mask,
-        .unmask         = tegra_gpio_irq_unmask,
-        .set_type       = tegra_gpio_irq_set_type,
+        .irq_ack        = tegra_gpio_irq_ack,
+        .irq_mask       = tegra_gpio_irq_mask,
+        .irq_unmask     = tegra_gpio_irq_unmask,
+        .irq_set_type   = tegra_gpio_irq_set_type,
 #ifdef CONFIG_PM
-        .set_wake       = tegra_gpio_wake_enable,
+        .irq_set_wake   = tegra_gpio_wake_enable,
 #endif
 };
 
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 5407de01abf0..de7dfad6f769 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -46,30 +46,30 @@
 #define ICTLR_COP_IER_CLR       0x38
 #define ICTLR_COP_IEP_CLASS     0x3c
 
-static void (*gic_mask_irq)(unsigned int irq);
-static void (*gic_unmask_irq)(unsigned int irq);
+static void (*gic_mask_irq)(struct irq_data *d);
+static void (*gic_unmask_irq)(struct irq_data *d);
 
 #define irq_to_ictlr(irq) (((irq)-32) >> 5)
 static void __iomem *tegra_ictlr_base = IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE);
 #define ictlr_to_virt(ictlr) (tegra_ictlr_base + (ictlr)*0x100)
 
-static void tegra_mask(unsigned int irq)
+static void tegra_mask(struct irq_data *d)
 {
-        void __iomem *addr = ictlr_to_virt(irq_to_ictlr(irq));
-        gic_mask_irq(irq);
-        writel(1<<(irq&31), addr+ICTLR_CPU_IER_CLR);
+        void __iomem *addr = ictlr_to_virt(irq_to_ictlr(d->irq));
+        gic_mask_irq(d);
+        writel(1<<(d->irq&31), addr+ICTLR_CPU_IER_CLR);
 }
 
-static void tegra_unmask(unsigned int irq)
+static void tegra_unmask(struct irq_data *d)
 {
-        void __iomem *addr = ictlr_to_virt(irq_to_ictlr(irq));
-        gic_unmask_irq(irq);
-        writel(1<<(irq&31), addr+ICTLR_CPU_IER_SET);
+        void __iomem *addr = ictlr_to_virt(irq_to_ictlr(d->irq));
+        gic_unmask_irq(d);
+        writel(1<<(d->irq&31), addr+ICTLR_CPU_IER_SET);
 }
 
 #ifdef CONFIG_PM
 
-static int tegra_set_wake(unsigned int irq, unsigned int on)
+static int tegra_set_wake(struct irq_data *d, unsigned int on)
 {
         return 0;
 }
@@ -77,10 +77,10 @@ static int tegra_set_wake(unsigned int irq, unsigned int on)
 
 static struct irq_chip tegra_irq = {
         .name           = "PPI",
-        .mask           = tegra_mask,
-        .unmask         = tegra_unmask,
+        .irq_mask       = tegra_mask,
+        .irq_unmask     = tegra_unmask,
 #ifdef CONFIG_PM
-        .set_wake       = tegra_set_wake,
+        .irq_set_wake   = tegra_set_wake,
 #endif
 };
 
@@ -98,11 +98,11 @@ void __init tegra_init_irq(void)
                  IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
 
         gic = get_irq_chip(29);
-        gic_unmask_irq = gic->unmask;
-        gic_mask_irq = gic->mask;
-        tegra_irq.ack = gic->ack;
+        gic_unmask_irq = gic->irq_unmask;
+        gic_mask_irq = gic->irq_mask;
+        tegra_irq.irq_ack = gic->irq_ack;
 #ifdef CONFIG_SMP
-        tegra_irq.set_affinity = gic->set_affinity;
+        tegra_irq.irq_set_affinity = gic->irq_set_affinity;
 #endif
 
         for (i = INT_PRI_BASE; i < INT_GPIO_BASE; i++) {
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 13a83e45a33b..136c32e7ed8e 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -63,23 +63,25 @@
 #define VA_VIC_BASE             __io_address(VERSATILE_VIC_BASE)
 #define VA_SIC_BASE             __io_address(VERSATILE_SIC_BASE)
 
-static void sic_mask_irq(unsigned int irq)
+static void sic_mask_irq(struct irq_data *d)
 {
-        irq -= IRQ_SIC_START;
+        unsigned int irq = d->irq - IRQ_SIC_START;
+
         writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
 }
 
-static void sic_unmask_irq(unsigned int irq)
+static void sic_unmask_irq(struct irq_data *d)
 {
-        irq -= IRQ_SIC_START;
+        unsigned int irq = d->irq - IRQ_SIC_START;
+
         writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET);
 }
 
 static struct irq_chip sic_chip = {
-        .name   = "SIC",
-        .ack    = sic_mask_irq,
-        .mask   = sic_mask_irq,
-        .unmask = sic_unmask_irq,
+        .name           = "SIC",
+        .irq_ack        = sic_mask_irq,
+        .irq_mask       = sic_mask_irq,
+        .irq_unmask     = sic_unmask_irq,
 };
 
 static void
diff --git a/arch/arm/mach-w90x900/irq.c b/arch/arm/mach-w90x900/irq.c
index 0ce9d8e867eb..9c350103dcda 100644
--- a/arch/arm/mach-w90x900/irq.c
+++ b/arch/arm/mach-w90x900/irq.c
@@ -92,15 +92,15 @@ static void nuc900_group_enable(struct group_irq *gpirq, int enable)
         __raw_writel(regval, REG_AIC_GEN);
 }
 
-static void nuc900_irq_mask(unsigned int irq)
+static void nuc900_irq_mask(struct irq_data *d)
 {
         struct group_irq *group_irq;
 
         group_irq = NULL;
 
-        __raw_writel(1 << irq, REG_AIC_MDCR);
+        __raw_writel(1 << d->irq, REG_AIC_MDCR);
 
-        switch (irq) {
+        switch (d->irq) {
         case IRQ_GROUP0:
                 group_irq = &group_nirq0;
                 break;
@@ -143,20 +143,20 @@ static void nuc900_irq_mask(unsigned int irq)
  * to REG_AIC_EOSCR for ACK
  */
 
-static void nuc900_irq_ack(unsigned int irq)
+static void nuc900_irq_ack(struct irq_data *d)
 {
         __raw_writel(0x01, REG_AIC_EOSCR);
 }
 
-static void nuc900_irq_unmask(unsigned int irq)
+static void nuc900_irq_unmask(struct irq_data *d)
 {
         struct group_irq *group_irq;
 
         group_irq = NULL;
 
-        __raw_writel(1 << irq, REG_AIC_MECR);
+        __raw_writel(1 << d->irq, REG_AIC_MECR);
 
-        switch (irq) {
+        switch (d->irq) {
         case IRQ_GROUP0:
                 group_irq = &group_nirq0;
                 break;
@@ -195,9 +195,9 @@ static void nuc900_irq_unmask(unsigned int irq)
 }
 
 static struct irq_chip nuc900_irq_chip = {
-        .ack       = nuc900_irq_ack,
-        .mask      = nuc900_irq_mask,
-        .unmask    = nuc900_irq_unmask,
+        .irq_ack        = nuc900_irq_ack,
+        .irq_mask       = nuc900_irq_mask,
+        .irq_unmask     = nuc900_irq_unmask,
 };
 
 void __init nuc900_init_irq(void)
diff --git a/arch/arm/plat-mxc/3ds_debugboard.c b/arch/arm/plat-mxc/3ds_debugboard.c
index 639c54a07992..c856fa397606 100644
--- a/arch/arm/plat-mxc/3ds_debugboard.c
+++ b/arch/arm/plat-mxc/3ds_debugboard.c
@@ -60,7 +60,6 @@
 #define EXPIO_INT_BUTTON_B      (MXC_BOARD_IRQ_START + 4)
 
 static void __iomem *brd_io;
-static void expio_ack_irq(u32 irq);
 
 static struct resource smsc911x_resources[] = {
         {
@@ -93,7 +92,8 @@ static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
         u32 int_valid;
         u32 expio_irq;
 
-        desc->chip->mask(irq);  /* irq = gpio irq number */
+        /* irq = gpio irq number */
+        desc->irq_data.chip->irq_mask(&desc->irq_data);
 
         imr_val = __raw_readw(brd_io + INTR_MASK_REG);
         int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val;
@@ -110,37 +110,37 @@ static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
                         d->handle_irq(expio_irq, d);
         }
 
-        desc->chip->ack(irq);
-        desc->chip->unmask(irq);
+        desc->irq_data.chip->irq_ack(&desc->irq_data);
+        desc->irq_data.chip->irq_unmask(&desc->irq_data);
 }
 
 /*
  * Disable an expio pin's interrupt by setting the bit in the imr.
  * Irq is an expio virtual irq number
  */
-static void expio_mask_irq(u32 irq)
+static void expio_mask_irq(struct irq_data *d)
 {
         u16 reg;
-        u32 expio = MXC_IRQ_TO_EXPIO(irq);
+        u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
 
         reg = __raw_readw(brd_io + INTR_MASK_REG);
         reg |= (1 << expio);
         __raw_writew(reg, brd_io + INTR_MASK_REG);
 }
 
-static void expio_ack_irq(u32 irq)
+static void expio_ack_irq(struct irq_data *d)
 {
-        u32 expio = MXC_IRQ_TO_EXPIO(irq);
+        u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
 
         __raw_writew(1 << expio, brd_io + INTR_RESET_REG);
         __raw_writew(0, brd_io + INTR_RESET_REG);
-        expio_mask_irq(irq);
+        expio_mask_irq(d);
 }
 
-static void expio_unmask_irq(u32 irq)
+static void expio_unmask_irq(struct irq_data *d)
 {
         u16 reg;
-        u32 expio = MXC_IRQ_TO_EXPIO(irq);
+        u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
 
         reg = __raw_readw(brd_io + INTR_MASK_REG);
         reg &= ~(1 << expio);
@@ -148,9 +148,9 @@ static void expio_unmask_irq(u32 irq)
 }
 
 static struct irq_chip expio_irq_chip = {
-        .ack = expio_ack_irq,
-        .mask = expio_mask_irq,
-        .unmask = expio_unmask_irq,
+        .irq_ack = expio_ack_irq,
+        .irq_mask = expio_mask_irq,
+        .irq_unmask = expio_unmask_irq,
 };
 
 int __init mxc_expio_init(u32 base, u32 p_irq)
diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c
index 9a4e8a22dd0a..deb284bc7c4b 100644
--- a/arch/arm/plat-mxc/avic.c
+++ b/arch/arm/plat-mxc/avic.c
@@ -89,22 +89,22 @@ static int avic_set_irq_fiq(unsigned int irq, unsigned int type)
 #endif /* CONFIG_FIQ */
 
 /* Disable interrupt number "irq" in the AVIC */
-static void mxc_mask_irq(unsigned int irq)
+static void mxc_mask_irq(struct irq_data *d)
 {
-        __raw_writel(irq, avic_base + AVIC_INTDISNUM);
+        __raw_writel(d->irq, avic_base + AVIC_INTDISNUM);
 }
 
 /* Enable interrupt number "irq" in the AVIC */
-static void mxc_unmask_irq(unsigned int irq)
+static void mxc_unmask_irq(struct irq_data *d)
 {
-        __raw_writel(irq, avic_base + AVIC_INTENNUM);
+        __raw_writel(d->irq, avic_base + AVIC_INTENNUM);
 }
 
 static struct mxc_irq_chip mxc_avic_chip = {
         .base = {
-                .ack = mxc_mask_irq,
-                .mask = mxc_mask_irq,
-                .unmask = mxc_unmask_irq,
+                .irq_ack = mxc_mask_irq,
+                .irq_mask = mxc_mask_irq,
+                .irq_unmask = mxc_unmask_irq,
         },
 #ifdef CONFIG_MXC_IRQ_PRIOR
         .set_priority = avic_irq_set_priority,
diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig
index 2537166468ac..b9ab1d58b5e7 100644
--- a/arch/arm/plat-mxc/devices/Kconfig
+++ b/arch/arm/plat-mxc/devices/Kconfig
@@ -1,6 +1,6 @@
 config IMX_HAVE_PLATFORM_FEC
         bool
-        default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX51
+        default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX51 || SOC_IMX53
 
 config IMX_HAVE_PLATFORM_FLEXCAN
         select HAVE_CAN_FLEXCAN if CAN
diff --git a/arch/arm/plat-mxc/devices/platform-fec.c b/arch/arm/plat-mxc/devices/platform-fec.c
index 269ec78aba77..b50c3517d083 100644
--- a/arch/arm/plat-mxc/devices/platform-fec.c
+++ b/arch/arm/plat-mxc/devices/platform-fec.c
@@ -36,6 +36,11 @@ const struct imx_fec_data imx51_fec_data __initconst =
         imx_fec_data_entry_single(MX51);
 #endif
 
+#ifdef CONFIG_SOC_IMX53
+const struct imx_fec_data imx53_fec_data __initconst =
+        imx_fec_data_entry_single(MX53);
+#endif
+
 struct platform_device *__init imx_add_fec(
                 const struct imx_fec_data *data,
                 const struct fec_platform_data *pdata)
diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
index 72ba880c75af..7ba94e1bbda3 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-i2c.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
@@ -78,6 +78,15 @@ const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = {
 };
 #endif /* ifdef CONFIG_SOC_IMX51 */
 
+#ifdef CONFIG_SOC_IMX53
+const struct imx_imx_i2c_data imx53_imx_i2c_data[] __initconst = {
+#define imx53_imx_i2c_data_entry(_id, _hwid)                            \
+        imx_imx_i2c_data_entry(MX53, _id, _hwid, SZ_4K)
+        imx53_imx_i2c_data_entry(0, 1),
+        imx53_imx_i2c_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_SOC_IMX51 */
+
 struct platform_device *__init imx_add_imx_i2c(
                 const struct imx_imx_i2c_data *data,
                 const struct imxi2c_platform_data *pdata)
diff --git a/arch/arm/plat-mxc/devices/platform-imx-keypad.c b/arch/arm/plat-mxc/devices/platform-imx-keypad.c
index 40238f0b8643..26366114b021 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-keypad.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-keypad.c
@@ -41,6 +41,11 @@ const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst =
         imx_imx_keypad_data_entry_single(MX35, SZ_16);
 #endif /* ifdef CONFIG_SOC_IMX35 */
 
+#ifdef CONFIG_SOC_IMX51
+const struct imx_imx_keypad_data imx51_imx_keypad_data __initconst =
+        imx_imx_keypad_data_entry_single(MX51, SZ_16);
+#endif /* ifdef CONFIG_SOC_IMX51 */
+
 struct platform_device *__init imx_add_imx_keypad(
                 const struct imx_imx_keypad_data *data,
                 const struct matrix_keymap_data *pdata)
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_pwm.c b/arch/arm/plat-mxc/devices/platform-mxc_pwm.c
index 3d8ebdba38ee..b0c4ae298111 100644
--- a/arch/arm/plat-mxc/devices/platform-mxc_pwm.c
+++ b/arch/arm/plat-mxc/devices/platform-mxc_pwm.c
@@ -40,6 +40,15 @@ const struct imx_mxc_pwm_data imx27_mxc_pwm_data __initconst =
         imx_mxc_pwm_data_entry_single(MX27, 0, , SZ_4K);
 #endif /* ifdef CONFIG_SOC_IMX27 */
 
+#ifdef CONFIG_SOC_IMX51
+const struct imx_mxc_pwm_data imx51_mxc_pwm_data[] __initconst = {
+#define imx51_mxc_pwm_data_entry(_id, _hwid)                            \
+        imx_mxc_pwm_data_entry(MX51, _id, _hwid, SZ_16K)
+        imx51_mxc_pwm_data_entry(0, 1),
+        imx51_mxc_pwm_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_SOC_IMX51 */
+
 struct platform_device *__init imx_add_mxc_pwm(
                 const struct imx_mxc_pwm_data *data)
 {
diff --git a/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c b/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c
index b3525648a01d..6b2940b93d94 100644
--- a/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c
+++ b/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c
@@ -53,6 +53,18 @@ imx51_sdhci_esdhc_imx_data[] __initconst = {
 };
 #endif /* ifdef CONFIG_SOC_IMX51 */
 
+#ifdef CONFIG_SOC_IMX53
+const struct imx_sdhci_esdhc_imx_data
+imx53_sdhci_esdhc_imx_data[] __initconst = {
+#define imx53_sdhci_esdhc_imx_data_entry(_id, _hwid)                    \
+        imx_sdhci_esdhc_imx_data_entry(MX53, _id, _hwid)
+        imx53_sdhci_esdhc_imx_data_entry(0, 1),
+        imx53_sdhci_esdhc_imx_data_entry(1, 2),
+        imx53_sdhci_esdhc_imx_data_entry(2, 3),
+        imx53_sdhci_esdhc_imx_data_entry(3, 4),
+};
+#endif /* ifdef CONFIG_SOC_IMX53 */
+
 struct platform_device *__init imx_add_sdhci_esdhc_imx(
                 const struct imx_sdhci_esdhc_imx_data *data,
                 const struct esdhc_platform_data *pdata)
diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c
index 8ea49adcdfc1..013c85f20b58 100644
--- a/arch/arm/plat-mxc/devices/platform-spi_imx.c
+++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c
@@ -81,6 +81,18 @@ const struct imx_spi_imx_data imx51_ecspi_data[] __initconst = {
 };
 #endif /* ifdef CONFIG_SOC_IMX51 */
 
+#ifdef CONFIG_SOC_IMX53
+const struct imx_spi_imx_data imx53_cspi_data __initconst =
+        imx_spi_imx_data_entry_single(MX53, CSPI, "imx53-cspi", 0, , SZ_4K);
+
+const struct imx_spi_imx_data imx53_ecspi_data[] __initconst = {
+#define imx53_ecspi_data_entry(_id, _hwid)                              \
+        imx_spi_imx_data_entry(MX53, ECSPI, "imx53-ecspi", _id, _hwid, SZ_4K)
+        imx53_ecspi_data_entry(0, 1),
+        imx53_ecspi_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_SOC_IMX53 */
+
 struct platform_device *__init imx_add_spi_imx(
                 const struct imx_spi_imx_data *data,
                 const struct spi_imx_master *pdata)
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index bc2c7bc6f10a..d17b3c996b84 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -63,29 +63,29 @@ static void _set_gpio_irqenable(struct mxc_gpio_port *port, u32 index,
         __raw_writel(l, port->base + GPIO_IMR);
 }
 
-static void gpio_ack_irq(u32 irq)
+static void gpio_ack_irq(struct irq_data *d)
 {
-        u32 gpio = irq_to_gpio(irq);
+        u32 gpio = irq_to_gpio(d->irq);
         _clear_gpio_irqstatus(&mxc_gpio_ports[gpio / 32], gpio & 0x1f);
 }
 
-static void gpio_mask_irq(u32 irq)
+static void gpio_mask_irq(struct irq_data *d)
 {
-        u32 gpio = irq_to_gpio(irq);
+        u32 gpio = irq_to_gpio(d->irq);
         _set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 0);
 }
 
-static void gpio_unmask_irq(u32 irq)
+static void gpio_unmask_irq(struct irq_data *d)
 {
-        u32 gpio = irq_to_gpio(irq);
+        u32 gpio = irq_to_gpio(d->irq);
         _set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 1);
 }
 
 static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset);
 
-static int gpio_set_irq_type(u32 irq, u32 type)
+static int gpio_set_irq_type(struct irq_data *d, u32 type)
 {
-        u32 gpio = irq_to_gpio(irq);
+        u32 gpio = irq_to_gpio(d->irq);
         struct mxc_gpio_port *port = &mxc_gpio_ports[gpio / 32];
         u32 bit, val;
         int edge;
@@ -211,9 +211,9 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
  * @param  enable       enable as wake-up if equal to non-zero
  * @return       This function returns 0 on success.
  */
-static int gpio_set_wake_irq(u32 irq, u32 enable)
+static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
 {
-        u32 gpio = irq_to_gpio(irq);
+        u32 gpio = irq_to_gpio(d->irq);
         u32 gpio_idx = gpio & 0x1F;
         struct mxc_gpio_port *port = &mxc_gpio_ports[gpio / 32];
 
@@ -233,11 +233,11 @@ static int gpio_set_wake_irq(u32 irq, u32 enable)
 }
 
 static struct irq_chip gpio_irq_chip = {
-        .ack = gpio_ack_irq,
-        .mask = gpio_mask_irq,
-        .unmask = gpio_unmask_irq,
-        .set_type = gpio_set_irq_type,
-        .set_wake = gpio_set_wake_irq,
+        .irq_ack = gpio_ack_irq,
+        .irq_mask = gpio_mask_irq,
+        .irq_unmask = gpio_unmask_irq,
+        .irq_set_type = gpio_set_irq_type,
+        .irq_set_wake = gpio_set_wake_irq,
 };
 
 static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
index 5deee019c29e..68e11d7ab79d 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx53.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
@@ -34,7 +34,6 @@ typedef enum iomux_config {
         IOMUX_CONFIG_ALT6,
         IOMUX_CONFIG_ALT7,
         IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */
-        IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */
 } iomux_pin_cfg_t;
 
 /* These 2 defines are for pins that may not have a mux register, but could
@@ -135,6 +134,9 @@ typedef enum iomux_config {
 #define MX53_PAD_EIM_D16__GPIO_3_16             IOMUX_PAD(0x460, 0x118,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
 #define MX53_PAD_EIM_D17__GPIO_3_17             IOMUX_PAD(0x464, 0x11C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
 #define MX53_PAD_EIM_D18__GPIO_3_18             IOMUX_PAD(0x468, 0x120,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D16__CSPI1_SCLK            IOMUX_PAD(0x460, 0x118,IOMUX_CONFIG_ALT4, 0x79c, 3, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D17__CSPI1_MISO            IOMUX_PAD(0x464, 0x11C,IOMUX_CONFIG_ALT4, 0x7a0, 3, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D18__CSPI1_MOSI            IOMUX_PAD(0x468, 0x120,IOMUX_CONFIG_ALT4, 0x7a4, 3, NO_PAD_CTRL)
 #define MX53_PAD_EIM_D19__GPIO_3_19             IOMUX_PAD(0x46C, 0x124,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
 #define MX53_PAD_EIM_D20__GPIO_3_20             IOMUX_PAD(0x470, 0x128,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
 #define MX53_PAD_EIM_D21__GPIO_3_21             IOMUX_PAD(0x474, 0x12C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index 2277b01c855d..82620af1922f 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -105,6 +105,7 @@ typedef u64 iomux_v3_cfg_t;
 #define PAD_CTL_SRE_FAST                (1 << 0)
 #define PAD_CTL_SRE_SLOW                (0 << 0)
 
+#define IOMUX_CONFIG_SION               (0x1 << 4)
 
 #define MX51_NUM_GPIO_PORT      4
 
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
index 873807f96d70..1eb339e6c857 100644
--- a/arch/arm/plat-mxc/include/mach/mx51.h
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -301,8 +301,8 @@
 #define MX51_MXC_INT_GPIO4_HIGH         57
 #define MX51_MXC_INT_WDOG1              58
 #define MX51_MXC_INT_WDOG2              59
-#define MX51_MXC_INT_KPP                60
-#define MX51_MXC_INT_PWM1               61
+#define MX51_INT_KPP                    60
+#define MX51_INT_PWM1                   61
 #define MX51_INT_I2C1                   62
 #define MX51_INT_I2C2                   63
 #define MX51_MXC_INT_HS_I2C             64
@@ -335,7 +335,7 @@
 #define MX51_MXC_INT_SPDIF              91
 #define MX51_MXC_INT_TVE                92
 #define MX51_MXC_INT_FIRI               93
-#define MX51_MXC_INT_PWM2               94
+#define MX51_INT_PWM2                   94
 #define MX51_MXC_INT_SLIM_EXP           95
 #define MX51_INT_SSI3                   96
 #define MX51_MXC_INT_EMI_BOOT           97
diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h
index 9577cdbf7fad..d7a8e52181ea 100644
--- a/arch/arm/plat-mxc/include/mach/mx53.h
+++ b/arch/arm/plat-mxc/include/mach/mx53.h
@@ -53,13 +53,13 @@
 #define MX53_SPBA0_BASE_ADDR            0x50000000
 #define MX53_SPBA0_SIZE         SZ_1M
 
-#define MX53_MMC_SDHC1_BASE_ADDR        (MX53_SPBA0_BASE_ADDR + 0x00004000)
-#define MX53_MMC_SDHC2_BASE_ADDR        (MX53_SPBA0_BASE_ADDR + 0x00008000)
+#define MX53_ESDHC1_BASE_ADDR   (MX53_SPBA0_BASE_ADDR + 0x00004000)
+#define MX53_ESDHC2_BASE_ADDR   (MX53_SPBA0_BASE_ADDR + 0x00008000)
 #define MX53_UART3_BASE_ADDR            (MX53_SPBA0_BASE_ADDR + 0x0000C000)
-#define MX53_CSPI1_BASE_ADDR            (MX53_SPBA0_BASE_ADDR + 0x00010000)
+#define MX53_ECSPI1_BASE_ADDR           (MX53_SPBA0_BASE_ADDR + 0x00010000)
 #define MX53_SSI2_BASE_ADDR             (MX53_SPBA0_BASE_ADDR + 0x00014000)
-#define MX53_MMC_SDHC3_BASE_ADDR        (MX53_SPBA0_BASE_ADDR + 0x00020000)
-#define MX53_MMC_SDHC4_BASE_ADDR        (MX53_SPBA0_BASE_ADDR + 0x00024000)
+#define MX53_ESDHC3_BASE_ADDR   (MX53_SPBA0_BASE_ADDR + 0x00020000)
+#define MX53_ESDHC4_BASE_ADDR   (MX53_SPBA0_BASE_ADDR + 0x00024000)
 #define MX53_SPDIF_BASE_ADDR            (MX53_SPBA0_BASE_ADDR + 0x00028000)
 #define MX53_ASRC_BASE_ADDR             (MX53_SPBA0_BASE_ADDR + 0x0002C000)
 #define MX53_ATA_DMA_BASE_ADDR  (MX53_SPBA0_BASE_ADDR + 0x00030000)
@@ -117,12 +117,12 @@
 #define MX53_ARM_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000A0000)
 #define MX53_OWIRE_BASE_ADDR    (MX53_AIPS2_BASE_ADDR + 0x000A4000)
 #define MX53_FIRI_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000A8000)
-#define MX53_CSPI2_BASE_ADDR    (MX53_AIPS2_BASE_ADDR + 0x000AC000)
+#define MX53_ECSPI2_BASE_ADDR   (MX53_AIPS2_BASE_ADDR + 0x000AC000)
 #define MX53_SDMA_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000B0000)
 #define MX53_SCC_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000B4000)
 #define MX53_ROMCP_BASE_ADDR    (MX53_AIPS2_BASE_ADDR + 0x000B8000)
 #define MX53_RTIC_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000BC000)
-#define MX53_CSPI3_BASE_ADDR    (MX53_AIPS2_BASE_ADDR + 0x000C0000)
+#define MX53_CSPI_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000C0000)
 #define MX53_I2C2_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000C4000)
 #define MX53_I2C1_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000C8000)
 #define MX53_SSI1_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000CC000)
@@ -136,7 +136,7 @@
 #define MX53_MIPI_HSC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DC000)
 #define MX53_MLB_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000E4000)
 #define MX53_SSI3_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000E8000)
-#define MX53_MXC_FEC_BASE_ADDR  (MX53_AIPS2_BASE_ADDR + 0x000EC000)
+#define MX53_FEC_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000EC000)
 #define MX53_TVE_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000F0000)
 #define MX53_VPU_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000F4000)
 #define MX53_SAHARA_BASE_ADDR   (MX53_AIPS2_BASE_ADDR + 0x000F8000)
@@ -229,10 +229,10 @@
  * Interrupt numbers
  */
 #define MX53_INT_RESV0          0
-#define MX53_INT_MMC_SDHC1      1
-#define MX53_INT_MMC_SDHC2      2
-#define MX53_INT_MMC_SDHC3      3
-#define MX53_INT_MMC_SDHC4      4
+#define MX53_INT_ESDHC1 1
+#define MX53_INT_ESDHC2 2
+#define MX53_INT_ESDHC3 3
+#define MX53_INT_ESDHC4 4
 #define MX53_INT_RESV5  5
 #define MX53_INT_SDMA   6
 #define MX53_INT_IOMUX  7
@@ -264,8 +264,8 @@
 #define MX53_INT_UART3  33
 #define MX53_INT_RESV34 34
 #define MX53_INT_RESV35 35
-#define MX53_INT_CSPI1  36
-#define MX53_INT_CSPI2  37
+#define MX53_INT_ECSPI1 36
+#define MX53_INT_ECSPI2 37
 #define MX53_INT_CSPI   38
 #define MX53_INT_GPT    39
 #define MX53_INT_EPIT1  40
diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c
index c36f2630ed93..7a61ef8f471a 100644
--- a/arch/arm/plat-mxc/pwm.c
+++ b/arch/arm/plat-mxc/pwm.c
@@ -57,7 +57,7 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
         if (pwm == NULL || period_ns == 0 || duty_ns > period_ns)
                 return -EINVAL;
 
-        if (cpu_is_mx27() || cpu_is_mx3() || cpu_is_mx25()) {
+        if (cpu_is_mx27() || cpu_is_mx3() || cpu_is_mx25() || cpu_is_mx51()) {
                 unsigned long long c;
                 unsigned long period_cycles, duty_cycles, prescale;
                 u32 cr;
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
index e69ed8a8c203..bc3a6be8a27f 100644
--- a/arch/arm/plat-mxc/tzic.c
+++ b/arch/arm/plat-mxc/tzic.c
@@ -69,50 +69,50 @@ static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)
 #endif
 
 /**
- * tzic_mask_irq() - Disable interrupt number "irq" in the TZIC
+ * tzic_mask_irq() - Disable interrupt source "d" in the TZIC
  *
- * @param  irq          interrupt source number
+ * @param  d            interrupt source
  */
-static void tzic_mask_irq(unsigned int irq)
+static void tzic_mask_irq(struct irq_data *d)
 {
         int index, off;
 
-        index = irq >> 5;
-        off = irq & 0x1F;
+        index = d->irq >> 5;
+        off = d->irq & 0x1F;
         __raw_writel(1 << off, tzic_base + TZIC_ENCLEAR0(index));
 }
 
 /**
- * tzic_unmask_irq() - Enable interrupt number "irq" in the TZIC
+ * tzic_unmask_irq() - Enable interrupt source "d" in the TZIC
  *
- * @param  irq          interrupt source number
+ * @param  d            interrupt source
  */
-static void tzic_unmask_irq(unsigned int irq)
+static void tzic_unmask_irq(struct irq_data *d)
 {
         int index, off;
 
-        index = irq >> 5;
-        off = irq & 0x1F;
+        index = d->irq >> 5;
+        off = d->irq & 0x1F;
         __raw_writel(1 << off, tzic_base + TZIC_ENSET0(index));
 }
 
 static unsigned int wakeup_intr[4];
 
 /**
- * tzic_set_wake_irq() - Set interrupt number "irq" in the TZIC as a wake-up source.
+ * tzic_set_wake_irq() - Set interrupt source "d" in the TZIC as a wake-up source.
  *
- * @param  irq          interrupt source number
+ * @param  d            interrupt source
  * @param  enable       enable as wake-up if equal to non-zero
  *                      disble as wake-up if equal to zero
  *
  * @return       This function returns 0 on success.
  */
-static int tzic_set_wake_irq(unsigned int irq, unsigned int enable)
+static int tzic_set_wake_irq(struct irq_data *d, unsigned int enable)
 {
         unsigned int index, off;
 
-        index = irq >> 5;
-        off = irq & 0x1F;
+        index = d->irq >> 5;
+        off = d->irq & 0x1F;
 
         if (index > 3)
                 return -EINVAL;
@@ -128,10 +128,10 @@ static int tzic_set_wake_irq(unsigned int irq, unsigned int enable)
 static struct mxc_irq_chip mxc_tzic_chip = {
         .base = {
                 .name = "MXC_TZIC",
-                .ack = tzic_mask_irq,
-                .mask = tzic_mask_irq,
-                .unmask = tzic_unmask_irq,
-                .set_wake = tzic_set_wake_irq,
+                .irq_ack = tzic_mask_irq,
+                .irq_mask = tzic_mask_irq,
+                .irq_unmask = tzic_unmask_irq,
+                .irq_set_wake = tzic_set_wake_irq,
         },
 #ifdef CONFIG_FIQ
         .set_irq_fiq = tzic_set_irq_fiq,
diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c
index eda4e3a11a3d..1e88ecb846d1 100644
--- a/arch/arm/plat-nomadik/gpio.c
+++ b/arch/arm/plat-nomadik/gpio.c
@@ -356,13 +356,13 @@ static inline int nmk_gpio_get_bitmask(int gpio)
         return 1 << (gpio % 32);
 }
 
-static void nmk_gpio_irq_ack(unsigned int irq)
+static void nmk_gpio_irq_ack(struct irq_data *d)
 {
         int gpio;
         struct nmk_gpio_chip *nmk_chip;
 
-        gpio = NOMADIK_IRQ_TO_GPIO(irq);
-        nmk_chip = get_irq_chip_data(irq);
+        gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
+        nmk_chip = irq_data_get_irq_chip_data(d);
         if (!nmk_chip)
                 return;
         writel(nmk_gpio_get_bitmask(gpio), nmk_chip->addr + NMK_GPIO_IC);
@@ -401,7 +401,7 @@ static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
         }
 }
 
-static int nmk_gpio_irq_modify(unsigned int irq, enum nmk_gpio_irq_type which,
+static int nmk_gpio_irq_modify(struct irq_data *d, enum nmk_gpio_irq_type which,
                                bool enable)
 {
         int gpio;
@@ -409,8 +409,8 @@ static int nmk_gpio_irq_modify(unsigned int irq, enum nmk_gpio_irq_type which,
         unsigned long flags;
         u32 bitmask;
 
-        gpio = NOMADIK_IRQ_TO_GPIO(irq);
-        nmk_chip = get_irq_chip_data(irq);
+        gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
+        nmk_chip = irq_data_get_irq_chip_data(d);
         bitmask = nmk_gpio_get_bitmask(gpio);
         if (!nmk_chip)
                 return -EINVAL;
@@ -422,24 +422,24 @@ static int nmk_gpio_irq_modify(unsigned int irq, enum nmk_gpio_irq_type which,
         return 0;
 }
 
-static void nmk_gpio_irq_mask(unsigned int irq)
+static void nmk_gpio_irq_mask(struct irq_data *d)
 {
-        nmk_gpio_irq_modify(irq, NORMAL, false);
+        nmk_gpio_irq_modify(d, NORMAL, false);
 }
 
-static void nmk_gpio_irq_unmask(unsigned int irq)
+static void nmk_gpio_irq_unmask(struct irq_data *d)
 {
-        nmk_gpio_irq_modify(irq, NORMAL, true);
+        nmk_gpio_irq_modify(d, NORMAL, true);
 }
 
-static int nmk_gpio_irq_set_wake(unsigned int irq, unsigned int on)
+static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
 {
         struct nmk_gpio_chip *nmk_chip;
         unsigned long flags;
         int gpio;
 
-        gpio = NOMADIK_IRQ_TO_GPIO(irq);
-        nmk_chip = get_irq_chip_data(irq);
+        gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
+        nmk_chip = irq_data_get_irq_chip_data(d);
         if (!nmk_chip)
                 return -EINVAL;
 
@@ -457,9 +457,9 @@ static int nmk_gpio_irq_set_wake(unsigned int irq, unsigned int on)
         return 0;
 }
 
-static int nmk_gpio_irq_set_type(unsigned int irq, unsigned int type)
+static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 {
-        struct irq_desc *desc = irq_to_desc(irq);
+        struct irq_desc *desc = irq_to_desc(d->irq);
         bool enabled = !(desc->status & IRQ_DISABLED);
         bool wake = desc->wake_depth;
         int gpio;
@@ -467,8 +467,8 @@ static int nmk_gpio_irq_set_type(unsigned int irq, unsigned int type)
         unsigned long flags;
         u32 bitmask;
 
-        gpio = NOMADIK_IRQ_TO_GPIO(irq);
-        nmk_chip = get_irq_chip_data(irq);
+        gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
+        nmk_chip = irq_data_get_irq_chip_data(d);
         bitmask = nmk_gpio_get_bitmask(gpio);
         if (!nmk_chip)
                 return -EINVAL;
@@ -507,11 +507,11 @@ static int nmk_gpio_irq_set_type(unsigned int irq, unsigned int type)
 
 static struct irq_chip nmk_gpio_irq_chip = {
         .name           = "Nomadik-GPIO",
-        .ack            = nmk_gpio_irq_ack,
-        .mask           = nmk_gpio_irq_mask,
-        .unmask         = nmk_gpio_irq_unmask,
-        .set_type       = nmk_gpio_irq_set_type,
-        .set_wake       = nmk_gpio_irq_set_wake,
+        .irq_ack        = nmk_gpio_irq_ack,
+        .irq_mask       = nmk_gpio_irq_mask,
+        .irq_unmask     = nmk_gpio_irq_unmask,
+        .irq_set_type   = nmk_gpio_irq_set_type,
+        .irq_set_wake   = nmk_gpio_irq_set_wake,
 };
 
 static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
@@ -522,12 +522,12 @@ static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
         u32 pending;
         unsigned int first_irq;
 
-        if (host_chip->mask_ack)
-                host_chip->mask_ack(irq);
+        if (host_chip->irq_mask_ack)
+                host_chip->irq_mask_ack(&desc->irq_data);
         else {
-                host_chip->mask(irq);
-                if (host_chip->ack)
-                        host_chip->ack(irq);
+                host_chip->irq_mask(&desc->irq_data);
+                if (host_chip->irq_ack)
+                        host_chip->irq_ack(&desc->irq_data);
         }
 
         nmk_chip = get_irq_data(irq);
@@ -537,7 +537,7 @@ static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
                 generic_handle_irq(gpio_irq);
         }
 
-        host_chip->unmask(irq);
+        host_chip->irq_unmask(&desc->irq_data);
 }
 
 static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index ccf2660f4151..971d18636942 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -729,17 +729,17 @@ bad:
         return -EINVAL;
 }
 
-static int gpio_irq_type(unsigned irq, unsigned type)
+static int gpio_irq_type(struct irq_data *d, unsigned type)
 {
         struct gpio_bank *bank;
         unsigned gpio;
         int retval;
         unsigned long flags;
 
-        if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
-                gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
+        if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
+                gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
         else
-                gpio = irq - IH_GPIO_BASE;
+                gpio = d->irq - IH_GPIO_BASE;
 
         if (check_gpio(gpio) < 0)
                 return -EINVAL;
@@ -752,21 +752,21 @@ static int gpio_irq_type(unsigned irq, unsigned type)
                         && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
                 return -EINVAL;
 
-        bank = get_irq_chip_data(irq);
+        bank = irq_data_get_irq_chip_data(d);
         spin_lock_irqsave(&bank->lock, flags);
         retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
         if (retval == 0) {
-                struct irq_desc *d = irq_to_desc(irq);
+                struct irq_desc *desc = irq_to_desc(d->irq);
 
-                d->status &= ~IRQ_TYPE_SENSE_MASK;
-                d->status |= type;
+                desc->status &= ~IRQ_TYPE_SENSE_MASK;
+                desc->status |= type;
         }
         spin_unlock_irqrestore(&bank->lock, flags);
 
         if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
-                __set_irq_handler_unlocked(irq, handle_level_irq);
+                __set_irq_handler_unlocked(d->irq, handle_level_irq);
         else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
-                __set_irq_handler_unlocked(irq, handle_edge_irq);
+                __set_irq_handler_unlocked(d->irq, handle_edge_irq);
 
         return retval;
 }
@@ -1023,15 +1023,15 @@ static void _reset_gpio(struct gpio_bank *bank, int gpio)
 }
 
 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
-static int gpio_wake_enable(unsigned int irq, unsigned int enable)
+static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
 {
-        unsigned int gpio = irq - IH_GPIO_BASE;
+        unsigned int gpio = d->irq - IH_GPIO_BASE;
         struct gpio_bank *bank;
         int retval;
 
         if (check_gpio(gpio) < 0)
                 return -ENODEV;
-        bank = get_irq_chip_data(irq);
+        bank = irq_data_get_irq_chip_data(d);
         retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
 
         return retval;
@@ -1144,7 +1144,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
         u32 retrigger = 0;
         int unmasked = 0;
 
-        desc->chip->ack(irq);
+        desc->irq_data.chip->irq_ack(&desc->irq_data);
 
         bank = get_irq_data(irq);
 #ifdef CONFIG_ARCH_OMAP1
@@ -1201,7 +1201,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
                 configured, we could unmask GPIO bank interrupt immediately */
                 if (!level_mask && !unmasked) {
                         unmasked = 1;
-                        desc->chip->unmask(irq);
+                        desc->irq_data.chip->irq_unmask(&desc->irq_data);
                 }
 
                 isr |= retrigger;
@@ -1237,41 +1237,40 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
         interrupt */
 exit:
         if (!unmasked)
-                desc->chip->unmask(irq);
-
+                desc->irq_data.chip->irq_unmask(&desc->irq_data);
 }
 
-static void gpio_irq_shutdown(unsigned int irq)
+static void gpio_irq_shutdown(struct irq_data *d)
 {
-        unsigned int gpio = irq - IH_GPIO_BASE;
-        struct gpio_bank *bank = get_irq_chip_data(irq);
+        unsigned int gpio = d->irq - IH_GPIO_BASE;
+        struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
 
         _reset_gpio(bank, gpio);
 }
 
-static void gpio_ack_irq(unsigned int irq)
+static void gpio_ack_irq(struct irq_data *d)
 {
-        unsigned int gpio = irq - IH_GPIO_BASE;
-        struct gpio_bank *bank = get_irq_chip_data(irq);
+        unsigned int gpio = d->irq - IH_GPIO_BASE;
+        struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
 
         _clear_gpio_irqstatus(bank, gpio);
 }
 
-static void gpio_mask_irq(unsigned int irq)
+static void gpio_mask_irq(struct irq_data *d)
 {
-        unsigned int gpio = irq - IH_GPIO_BASE;
-        struct gpio_bank *bank = get_irq_chip_data(irq);
+        unsigned int gpio = d->irq - IH_GPIO_BASE;
+        struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
 
         _set_gpio_irqenable(bank, gpio, 0);
         _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
 }
 
-static void gpio_unmask_irq(unsigned int irq)
+static void gpio_unmask_irq(struct irq_data *d)
 {
-        unsigned int gpio = irq - IH_GPIO_BASE;
-        struct gpio_bank *bank = get_irq_chip_data(irq);
+        unsigned int gpio = d->irq - IH_GPIO_BASE;
+        struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
         unsigned int irq_mask = 1 << get_gpio_index(gpio);
-        struct irq_desc *desc = irq_to_desc(irq);
+        struct irq_desc *desc = irq_to_desc(d->irq);
         u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
 
         if (trigger)
@@ -1289,12 +1288,12 @@ static void gpio_unmask_irq(unsigned int irq)
 
 static struct irq_chip gpio_irq_chip = {
         .name           = "GPIO",
-        .shutdown       = gpio_irq_shutdown,
-        .ack            = gpio_ack_irq,
-        .mask           = gpio_mask_irq,
-        .unmask         = gpio_unmask_irq,
-        .set_type       = gpio_irq_type,
-        .set_wake       = gpio_wake_enable,
+        .irq_shutdown   = gpio_irq_shutdown,
+        .irq_ack        = gpio_ack_irq,
+        .irq_mask       = gpio_mask_irq,
+        .irq_unmask     = gpio_unmask_irq,
+        .irq_set_type   = gpio_irq_type,
+        .irq_set_wake   = gpio_wake_enable,
 };
 
 /*---------------------------------------------------------------------*/
@@ -1303,36 +1302,36 @@ static struct irq_chip gpio_irq_chip = {
 
 /* MPUIO uses the always-on 32k clock */
 
-static void mpuio_ack_irq(unsigned int irq)
+static void mpuio_ack_irq(struct irq_data *d)
 {
         /* The ISR is reset automatically, so do nothing here. */
 }
 
-static void mpuio_mask_irq(unsigned int irq)
+static void mpuio_mask_irq(struct irq_data *d)
 {
-        unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
-        struct gpio_bank *bank = get_irq_chip_data(irq);
+        unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
+        struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
 
         _set_gpio_irqenable(bank, gpio, 0);
 }
 
-static void mpuio_unmask_irq(unsigned int irq)
+static void mpuio_unmask_irq(struct irq_data *d)
 {
-        unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
-        struct gpio_bank *bank = get_irq_chip_data(irq);
+        unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
+        struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
 
         _set_gpio_irqenable(bank, gpio, 1);
 }
 
 static struct irq_chip mpuio_irq_chip = {
         .name           = "MPUIO",
-        .ack            = mpuio_ack_irq,
-        .mask           = mpuio_mask_irq,
-        .unmask         = mpuio_unmask_irq,
-        .set_type       = gpio_irq_type,
+        .irq_ack        = mpuio_ack_irq,
+        .irq_mask       = mpuio_mask_irq,
+        .irq_unmask     = mpuio_unmask_irq,
+        .irq_set_type   = gpio_irq_type,
 #ifdef CONFIG_ARCH_OMAP16XX
         /* REVISIT: assuming only 16xx supports MPUIO wake events */
-        .set_wake       = gpio_wake_enable,
+        .irq_set_wake   = gpio_wake_enable,
 #endif
 };
 
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index e814803d4741..5f3522314815 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -232,20 +232,19 @@ EXPORT_SYMBOL(orion_gpio_set_blink);
  *        polarity    LEVEL          mask
  *
  ****************************************************************************/
-
-static void gpio_irq_ack(u32 irq)
+static void gpio_irq_ack(struct irq_data *d)
 {
-        int type = irq_desc[irq].status & IRQ_TYPE_SENSE_MASK;
+        int type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
-                int pin = irq_to_gpio(irq);
+                int pin = irq_to_gpio(d->irq);
                 writel(~(1 << (pin & 31)), GPIO_EDGE_CAUSE(pin));
         }
 }
 
-static void gpio_irq_mask(u32 irq)
+static void gpio_irq_mask(struct irq_data *d)
 {
-        int pin = irq_to_gpio(irq);
-        int type = irq_desc[irq].status & IRQ_TYPE_SENSE_MASK;
+        int pin = irq_to_gpio(d->irq);
+        int type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
         u32 reg = (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) ?
                 GPIO_EDGE_MASK(pin) : GPIO_LEVEL_MASK(pin);
         u32 u = readl(reg);
@@ -253,10 +252,10 @@ static void gpio_irq_mask(u32 irq)
         writel(u, reg);
 }
 
-static void gpio_irq_unmask(u32 irq)
+static void gpio_irq_unmask(struct irq_data *d)
 {
-        int pin = irq_to_gpio(irq);
-        int type = irq_desc[irq].status & IRQ_TYPE_SENSE_MASK;
+        int pin = irq_to_gpio(d->irq);
+        int type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
         u32 reg = (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) ?
                 GPIO_EDGE_MASK(pin) : GPIO_LEVEL_MASK(pin);
         u32 u = readl(reg);
@@ -264,20 +263,20 @@ static void gpio_irq_unmask(u32 irq)
         writel(u, reg);
 }
 
-static int gpio_irq_set_type(u32 irq, u32 type)
+static int gpio_irq_set_type(struct irq_data *d, u32 type)
 {
-        int pin = irq_to_gpio(irq);
+        int pin = irq_to_gpio(d->irq);
         struct irq_desc *desc;
         u32 u;
 
         u = readl(GPIO_IO_CONF(pin)) & (1 << (pin & 31));
         if (!u) {
                 printk(KERN_ERR "orion gpio_irq_set_type failed "
-                                "(irq %d, pin %d).\n", irq, pin);
+                                "(irq %d, pin %d).\n", d->irq, pin);
                 return -EINVAL;
         }
 
-        desc = irq_desc + irq;
+        desc = irq_desc + d->irq;
 
         /*
          * Set edge/level type.
@@ -287,7 +286,7 @@ static int gpio_irq_set_type(u32 irq, u32 type)
         } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
                 desc->handle_irq = handle_level_irq;
         } else {
-                printk(KERN_ERR "failed to set irq=%d (type=%d)\n", irq, type);
+                printk(KERN_ERR "failed to set irq=%d (type=%d)\n", d->irq, type);
                 return -EINVAL;
         }
 
@@ -325,10 +324,10 @@ static int gpio_irq_set_type(u32 irq, u32 type)
 
 struct irq_chip orion_gpio_irq_chip = {
         .name           = "orion_gpio_irq",
-        .ack            = gpio_irq_ack,
-        .mask           = gpio_irq_mask,
-        .unmask         = gpio_irq_unmask,
-        .set_type       = gpio_irq_set_type,
+        .irq_ack        = gpio_irq_ack,
+        .irq_mask       = gpio_irq_mask,
+        .irq_unmask     = gpio_irq_unmask,
+        .irq_set_type   = gpio_irq_set_type,
 };
 
 void orion_gpio_irq_handler(int pinoff)
diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c
index 3f9d34fc738c..7d0c7eb59f09 100644
--- a/arch/arm/plat-orion/irq.c
+++ b/arch/arm/plat-orion/irq.c
@@ -14,31 +14,31 @@
 #include <linux/io.h>
 #include <plat/irq.h>
 
-static void orion_irq_mask(u32 irq)
+static void orion_irq_mask(struct irq_data *d)
 {
-        void __iomem *maskaddr = get_irq_chip_data(irq);
+        void __iomem *maskaddr = irq_data_get_irq_chip_data(d);
         u32 mask;
 
         mask = readl(maskaddr);
-        mask &= ~(1 << (irq & 31));
+        mask &= ~(1 << (d->irq & 31));
         writel(mask, maskaddr);
 }
 
-static void orion_irq_unmask(u32 irq)
+static void orion_irq_unmask(struct irq_data *d)
 {
-        void __iomem *maskaddr = get_irq_chip_data(irq);
+        void __iomem *maskaddr = irq_data_get_irq_chip_data(d);
         u32 mask;
 
         mask = readl(maskaddr);
-        mask |= 1 << (irq & 31);
+        mask |= 1 << (d->irq & 31);
         writel(mask, maskaddr);
 }
 
 static struct irq_chip orion_irq_chip = {
         .name           = "orion_irq",
-        .mask           = orion_irq_mask,
-        .mask_ack       = orion_irq_mask,
-        .unmask         = orion_irq_unmask,
+        .irq_mask       = orion_irq_mask,
+        .irq_mask_ack   = orion_irq_mask,
+        .irq_unmask     = orion_irq_unmask,
 };
 
 void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
diff --git a/arch/arm/plat-pxa/gpio.c b/arch/arm/plat-pxa/gpio.c
index 98548c6903a0..e7de6ae2a1e8 100644
--- a/arch/arm/plat-pxa/gpio.c
+++ b/arch/arm/plat-pxa/gpio.c
@@ -155,10 +155,10 @@ static inline void update_edge_detect(struct pxa_gpio_chip *c)
         __raw_writel(gfer, c->regbase + GFER_OFFSET);
 }
 
-static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
+static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
 {
         struct pxa_gpio_chip *c;
-        int gpio = irq_to_gpio(irq);
+        int gpio = irq_to_gpio(d->irq);
         unsigned long gpdr, mask = GPIO_bit(gpio);
 
         c = gpio_to_chip(gpio);
@@ -195,7 +195,7 @@ static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
 
         update_edge_detect(c);
 
-        pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, irq, gpio,
+        pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio,
                 ((type & IRQ_TYPE_EDGE_RISING)  ? " rising"  : ""),
                 ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
         return 0;
@@ -227,17 +227,17 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
         } while (loop);
 }
 
-static void pxa_ack_muxed_gpio(unsigned int irq)
+static void pxa_ack_muxed_gpio(struct irq_data *d)
 {
-        int gpio = irq_to_gpio(irq);
+        int gpio = irq_to_gpio(d->irq);
         struct pxa_gpio_chip *c = gpio_to_chip(gpio);
 
         __raw_writel(GPIO_bit(gpio), c->regbase + GEDR_OFFSET);
 }
 
-static void pxa_mask_muxed_gpio(unsigned int irq)
+static void pxa_mask_muxed_gpio(struct irq_data *d)
 {
-        int gpio = irq_to_gpio(irq);
+        int gpio = irq_to_gpio(d->irq);
         struct pxa_gpio_chip *c = gpio_to_chip(gpio);
         uint32_t grer, gfer;
 
@@ -249,9 +249,9 @@ static void pxa_mask_muxed_gpio(unsigned int irq)
         __raw_writel(gfer, c->regbase + GFER_OFFSET);
 }
 
-static void pxa_unmask_muxed_gpio(unsigned int irq)
+static void pxa_unmask_muxed_gpio(struct irq_data *d)
 {
-        int gpio = irq_to_gpio(irq);
+        int gpio = irq_to_gpio(d->irq);
         struct pxa_gpio_chip *c = gpio_to_chip(gpio);
 
         c->irq_mask |= GPIO_bit(gpio);
@@ -260,10 +260,10 @@ static void pxa_unmask_muxed_gpio(unsigned int irq)
 
 static struct irq_chip pxa_muxed_gpio_chip = {
         .name           = "GPIO",
-        .ack            = pxa_ack_muxed_gpio,
-        .mask           = pxa_mask_muxed_gpio,
-        .unmask         = pxa_unmask_muxed_gpio,
-        .set_type       = pxa_gpio_irq_type,
+        .irq_ack        = pxa_ack_muxed_gpio,
+        .irq_mask       = pxa_mask_muxed_gpio,
+        .irq_unmask     = pxa_unmask_muxed_gpio,
+        .irq_set_type   = pxa_gpio_irq_type,
 };
 
 void __init pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn)
@@ -291,7 +291,7 @@ void __init pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn)
 
         /* Install handler for GPIO>=2 edge detect interrupts */
         set_irq_chained_handler(mux_irq, pxa_gpio_demux_handler);
-        pxa_muxed_gpio_chip.set_wake = fn;
+        pxa_muxed_gpio_chip.irq_set_wake = fn;
 }
 
 #ifdef CONFIG_PM
diff --git a/arch/arm/plat-pxa/include/plat/gpio.h b/arch/arm/plat-pxa/include/plat/gpio.h
index 44248cb926a5..1ddd2b97a729 100644
--- a/arch/arm/plat-pxa/include/plat/gpio.h
+++ b/arch/arm/plat-pxa/include/plat/gpio.h
@@ -1,6 +1,8 @@
 #ifndef __PLAT_GPIO_H
 #define __PLAT_GPIO_H
 
+struct irq_data;
+
 /*
  * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
  * one set of registers. The register offsets are organized below:
@@ -56,7 +58,7 @@ static inline void gpio_set_value(unsigned gpio, int value)
  */
 extern int pxa_last_gpio;
 
-typedef int (*set_wake_t)(unsigned int irq, unsigned int on);
+typedef int (*set_wake_t)(struct irq_data *d, unsigned int on);
 
 extern void pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn);
 #endif /* __PLAT_GPIO_H */
diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c
index 8a42bc48dbf0..268f3ed0a105 100644
--- a/arch/arm/plat-s3c24xx/devs.c
+++ b/arch/arm/plat-s3c24xx/devs.c
@@ -194,7 +194,6 @@ void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *hard_s3c2410ts_
         memcpy(&s3c2410ts_info, hard_s3c2410ts_info, sizeof(struct s3c2410_ts_mach_info));
         s3c_device_ts.dev.platform_data = &s3c2410ts_info;
 }
-EXPORT_SYMBOL(s3c24xx_ts_set_platdata);
 
 /* USB Device (Gadget)*/
 
diff --git a/arch/arm/plat-s3c24xx/include/plat/irq.h b/arch/arm/plat-s3c24xx/include/plat/irq.h
index 69e1be8bec35..ec087d6054b1 100644
--- a/arch/arm/plat-s3c24xx/include/plat/irq.h
+++ b/arch/arm/plat-s3c24xx/include/plat/irq.h
@@ -107,9 +107,9 @@ s3c_irqsub_ack(unsigned int irqno, unsigned int parentmask, unsigned int group)
 /* exported for use in arch/arm/mach-s3c2410 */
 
 #ifdef CONFIG_PM
-extern int s3c_irq_wake(unsigned int irqno, unsigned int state);
+extern int s3c_irq_wake(struct irq_data *data, unsigned int state);
 #else
 #define s3c_irq_wake NULL
 #endif
 
-extern int s3c_irqext_type(unsigned int irq, unsigned int type);
+extern int s3c_irqext_type(struct irq_data *d, unsigned int type);
diff --git a/arch/arm/plat-s3c24xx/irq-pm.c b/arch/arm/plat-s3c24xx/irq-pm.c
index ea8dea3339a4..c3624d898630 100644
--- a/arch/arm/plat-s3c24xx/irq-pm.c
+++ b/arch/arm/plat-s3c24xx/irq-pm.c
@@ -15,11 +15,14 @@
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/sysdev.h>
+#include <linux/irq.h>
 
 #include <plat/cpu.h>
 #include <plat/pm.h>
 #include <plat/irq.h>
 
+#include <asm/irq.h>
+
 /* state for IRQs over sleep */
 
 /* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources
@@ -30,15 +33,15 @@
 unsigned long s3c_irqwake_intallow      = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL;
 unsigned long s3c_irqwake_eintallow     = 0x0000fff0L;
 
-int s3c_irq_wake(unsigned int irqno, unsigned int state)
+int s3c_irq_wake(struct irq_data *data, unsigned int state)
 {
-        unsigned long irqbit = 1 << (irqno - IRQ_EINT0);
+        unsigned long irqbit = 1 << (data->irq - IRQ_EINT0);
 
         if (!(s3c_irqwake_intallow & irqbit))
                 return -ENOENT;
 
         printk(KERN_INFO "wake %s for irq %d\n",
-               state ? "enabled" : "disabled", irqno);
+               state ? "enabled" : "disabled", data->irq);
 
         if (!state)
                 s3c_irqwake_intmask |= irqbit;
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c
index ad0d44ef1f93..4434cb56bd9a 100644
--- a/arch/arm/plat-s3c24xx/irq.c
+++ b/arch/arm/plat-s3c24xx/irq.c
@@ -34,30 +34,29 @@
 #include <plat/irq.h>
 
 static void
-s3c_irq_mask(unsigned int irqno)
+s3c_irq_mask(struct irq_data *data)
 {
+        unsigned int irqno = data->irq - IRQ_EINT0;
         unsigned long mask;
 
-        irqno -= IRQ_EINT0;
-
         mask = __raw_readl(S3C2410_INTMSK);
         mask |= 1UL << irqno;
         __raw_writel(mask, S3C2410_INTMSK);
 }
 
 static inline void
-s3c_irq_ack(unsigned int irqno)
+s3c_irq_ack(struct irq_data *data)
 {
-        unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
+        unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
 
         __raw_writel(bitval, S3C2410_SRCPND);
         __raw_writel(bitval, S3C2410_INTPND);
 }
 
 static inline void
-s3c_irq_maskack(unsigned int irqno)
+s3c_irq_maskack(struct irq_data *data)
 {
-        unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
+        unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
         unsigned long mask;
 
         mask = __raw_readl(S3C2410_INTMSK);
@@ -69,8 +68,9 @@ s3c_irq_maskack(unsigned int irqno)
 
 
 static void
-s3c_irq_unmask(unsigned int irqno)
+s3c_irq_unmask(struct irq_data *data)
 {
+        unsigned int irqno = data->irq;
         unsigned long mask;
 
         if (irqno != IRQ_TIMER4 && irqno != IRQ_EINT8t23)
@@ -85,40 +85,39 @@ s3c_irq_unmask(unsigned int irqno)
 
 struct irq_chip s3c_irq_level_chip = {
         .name           = "s3c-level",
-        .ack            = s3c_irq_maskack,
-        .mask           = s3c_irq_mask,
-        .unmask         = s3c_irq_unmask,
-        .set_wake       = s3c_irq_wake
+        .irq_ack        = s3c_irq_maskack,
+        .irq_mask       = s3c_irq_mask,
+        .irq_unmask     = s3c_irq_unmask,
+        .irq_set_wake   = s3c_irq_wake
 };
 
 struct irq_chip s3c_irq_chip = {
         .name           = "s3c",
-        .ack            = s3c_irq_ack,
-        .mask           = s3c_irq_mask,
-        .unmask         = s3c_irq_unmask,
-        .set_wake       = s3c_irq_wake
+        .irq_ack        = s3c_irq_ack,
+        .irq_mask       = s3c_irq_mask,
+        .irq_unmask     = s3c_irq_unmask,
+        .irq_set_wake   = s3c_irq_wake
 };
 
 static void
-s3c_irqext_mask(unsigned int irqno)
+s3c_irqext_mask(struct irq_data *data)
 {
+        unsigned int irqno = data->irq - EXTINT_OFF;
         unsigned long mask;
 
-        irqno -= EXTINT_OFF;
-
         mask = __raw_readl(S3C24XX_EINTMASK);
         mask |= ( 1UL << irqno);
         __raw_writel(mask, S3C24XX_EINTMASK);
 }
 
 static void
-s3c_irqext_ack(unsigned int irqno)
+s3c_irqext_ack(struct irq_data *data)
 {
         unsigned long req;
         unsigned long bit;
         unsigned long mask;
 
-        bit = 1UL << (irqno - EXTINT_OFF);
+        bit = 1UL << (data->irq - EXTINT_OFF);
 
         mask = __raw_readl(S3C24XX_EINTMASK);
 
@@ -129,64 +128,57 @@ s3c_irqext_ack(unsigned int irqno)
 
         /* not sure if we should be acking the parent irq... */
 
-        if (irqno <= IRQ_EINT7 ) {
+        if (data->irq <= IRQ_EINT7) {
                 if ((req & 0xf0) == 0)
-                        s3c_irq_ack(IRQ_EINT4t7);
+                        s3c_irq_ack(irq_get_irq_data(IRQ_EINT4t7));
         } else {
                 if ((req >> 8) == 0)
-                        s3c_irq_ack(IRQ_EINT8t23);
+                        s3c_irq_ack(irq_get_irq_data(IRQ_EINT8t23));
         }
 }
 
 static void
-s3c_irqext_unmask(unsigned int irqno)
+s3c_irqext_unmask(struct irq_data *data)
 {
+        unsigned int irqno = data->irq - EXTINT_OFF;
         unsigned long mask;
 
-        irqno -= EXTINT_OFF;
-
         mask = __raw_readl(S3C24XX_EINTMASK);
-        mask &= ~( 1UL << irqno);
+        mask &= ~(1UL << irqno);
         __raw_writel(mask, S3C24XX_EINTMASK);
 }
 
 int
-s3c_irqext_type(unsigned int irq, unsigned int type)
+s3c_irqext_type(struct irq_data *data, unsigned int type)
 {
         void __iomem *extint_reg;
         void __iomem *gpcon_reg;
         unsigned long gpcon_offset, extint_offset;
         unsigned long newvalue = 0, value;
 
-        if ((irq >= IRQ_EINT0) && (irq <= IRQ_EINT3))
-        {
+        if ((data->irq >= IRQ_EINT0) && (data->irq <= IRQ_EINT3)) {
                 gpcon_reg = S3C2410_GPFCON;
                 extint_reg = S3C24XX_EXTINT0;
-                gpcon_offset = (irq - IRQ_EINT0) * 2;
-                extint_offset = (irq - IRQ_EINT0) * 4;
-        }
-        else if ((irq >= IRQ_EINT4) && (irq <= IRQ_EINT7))
-        {
+                gpcon_offset = (data->irq - IRQ_EINT0) * 2;
+                extint_offset = (data->irq - IRQ_EINT0) * 4;
+        } else if ((data->irq >= IRQ_EINT4) && (data->irq <= IRQ_EINT7)) {
                 gpcon_reg = S3C2410_GPFCON;
                 extint_reg = S3C24XX_EXTINT0;
-                gpcon_offset = (irq - (EXTINT_OFF)) * 2;
-                extint_offset = (irq - (EXTINT_OFF)) * 4;
-        }
-        else if ((irq >= IRQ_EINT8) && (irq <= IRQ_EINT15))
-        {
+                gpcon_offset = (data->irq - (EXTINT_OFF)) * 2;
+                extint_offset = (data->irq - (EXTINT_OFF)) * 4;
+        } else if ((data->irq >= IRQ_EINT8) && (data->irq <= IRQ_EINT15)) {
                 gpcon_reg = S3C2410_GPGCON;
                 extint_reg = S3C24XX_EXTINT1;
-                gpcon_offset = (irq - IRQ_EINT8) * 2;
-                extint_offset = (irq - IRQ_EINT8) * 4;
-        }
-        else if ((irq >= IRQ_EINT16) && (irq <= IRQ_EINT23))
-        {
+                gpcon_offset = (data->irq - IRQ_EINT8) * 2;
+                extint_offset = (data->irq - IRQ_EINT8) * 4;
+        } else if ((data->irq >= IRQ_EINT16) && (data->irq <= IRQ_EINT23)) {
                 gpcon_reg = S3C2410_GPGCON;
                 extint_reg = S3C24XX_EXTINT2;
-                gpcon_offset = (irq - IRQ_EINT8) * 2;
-                extint_offset = (irq - IRQ_EINT16) * 4;
-        } else
+                gpcon_offset = (data->irq - IRQ_EINT8) * 2;
+                extint_offset = (data->irq - IRQ_EINT16) * 4;
+        } else {
                 return -1;
+        }
 
         /* Set the GPIO to external interrupt mode */
         value = __raw_readl(gpcon_reg);
@@ -234,20 +226,20 @@ s3c_irqext_type(unsigned int irq, unsigned int type)
 
 static struct irq_chip s3c_irqext_chip = {
         .name           = "s3c-ext",
-        .mask           = s3c_irqext_mask,
-        .unmask         = s3c_irqext_unmask,
-        .ack            = s3c_irqext_ack,
-        .set_type       = s3c_irqext_type,
-        .set_wake       = s3c_irqext_wake
+        .irq_mask       = s3c_irqext_mask,
+        .irq_unmask     = s3c_irqext_unmask,
+        .irq_ack        = s3c_irqext_ack,
+        .irq_set_type   = s3c_irqext_type,
+        .irq_set_wake   = s3c_irqext_wake
 };
 
 static struct irq_chip s3c_irq_eint0t4 = {
         .name           = "s3c-ext0",
-        .ack            = s3c_irq_ack,
-        .mask           = s3c_irq_mask,
-        .unmask         = s3c_irq_unmask,
-        .set_wake       = s3c_irq_wake,
-        .set_type       = s3c_irqext_type,
+        .irq_ack        = s3c_irq_ack,
+        .irq_mask       = s3c_irq_mask,
+        .irq_unmask     = s3c_irq_unmask,
+        .irq_set_wake   = s3c_irq_wake,
+        .irq_set_type   = s3c_irqext_type,
 };
 
 /* mask values for the parent registers for each of the interrupt types */
@@ -261,109 +253,109 @@ static struct irq_chip s3c_irq_eint0t4 = {
 /* UART0 */
 
 static void
-s3c_irq_uart0_mask(unsigned int irqno)
+s3c_irq_uart0_mask(struct irq_data *data)
 {
-        s3c_irqsub_mask(irqno, INTMSK_UART0, 7);
+        s3c_irqsub_mask(data->irq, INTMSK_UART0, 7);
 }
 
 static void
-s3c_irq_uart0_unmask(unsigned int irqno)
+s3c_irq_uart0_unmask(struct irq_data *data)
 {
-        s3c_irqsub_unmask(irqno, INTMSK_UART0);
+        s3c_irqsub_unmask(data->irq, INTMSK_UART0);
 }
 
 static void
-s3c_irq_uart0_ack(unsigned int irqno)
+s3c_irq_uart0_ack(struct irq_data *data)
 {
-        s3c_irqsub_maskack(irqno, INTMSK_UART0, 7);
+        s3c_irqsub_maskack(data->irq, INTMSK_UART0, 7);
 }
 
 static struct irq_chip s3c_irq_uart0 = {
         .name           = "s3c-uart0",
-        .mask           = s3c_irq_uart0_mask,
-        .unmask         = s3c_irq_uart0_unmask,
-        .ack            = s3c_irq_uart0_ack,
+        .irq_mask       = s3c_irq_uart0_mask,
+        .irq_unmask     = s3c_irq_uart0_unmask,
+        .irq_ack        = s3c_irq_uart0_ack,
 };
 
 /* UART1 */
 
 static void
-s3c_irq_uart1_mask(unsigned int irqno)
+s3c_irq_uart1_mask(struct irq_data *data)
 {
-        s3c_irqsub_mask(irqno, INTMSK_UART1, 7 << 3);
+        s3c_irqsub_mask(data->irq, INTMSK_UART1, 7 << 3);
 }
 
 static void
-s3c_irq_uart1_unmask(unsigned int irqno)
+s3c_irq_uart1_unmask(struct irq_data *data)
 {
-        s3c_irqsub_unmask(irqno, INTMSK_UART1);
+        s3c_irqsub_unmask(data->irq, INTMSK_UART1);
 }
 
 static void
-s3c_irq_uart1_ack(unsigned int irqno)
+s3c_irq_uart1_ack(struct irq_data *data)
 {
-        s3c_irqsub_maskack(irqno, INTMSK_UART1, 7 << 3);
+        s3c_irqsub_maskack(data->irq, INTMSK_UART1, 7 << 3);
 }
 
 static struct irq_chip s3c_irq_uart1 = {
         .name           = "s3c-uart1",
-        .mask           = s3c_irq_uart1_mask,
-        .unmask         = s3c_irq_uart1_unmask,
-        .ack            = s3c_irq_uart1_ack,
+        .irq_mask       = s3c_irq_uart1_mask,
+        .irq_unmask     = s3c_irq_uart1_unmask,
+        .irq_ack        = s3c_irq_uart1_ack,
 };
 
 /* UART2 */
 
 static void
-s3c_irq_uart2_mask(unsigned int irqno)
+s3c_irq_uart2_mask(struct irq_data *data)
 {
-        s3c_irqsub_mask(irqno, INTMSK_UART2, 7 << 6);
+        s3c_irqsub_mask(data->irq, INTMSK_UART2, 7 << 6);
 }
 
 static void
-s3c_irq_uart2_unmask(unsigned int irqno)
+s3c_irq_uart2_unmask(struct irq_data *data)
 {
-        s3c_irqsub_unmask(irqno, INTMSK_UART2);
+        s3c_irqsub_unmask(data->irq, INTMSK_UART2);
 }
 
 static void
-s3c_irq_uart2_ack(unsigned int irqno)
+s3c_irq_uart2_ack(struct irq_data *data)
 {
-        s3c_irqsub_maskack(irqno, INTMSK_UART2, 7 << 6);
+        s3c_irqsub_maskack(data->irq, INTMSK_UART2, 7 << 6);
 }
 
 static struct irq_chip s3c_irq_uart2 = {
         .name           = "s3c-uart2",
-        .mask           = s3c_irq_uart2_mask,
-        .unmask         = s3c_irq_uart2_unmask,
-        .ack            = s3c_irq_uart2_ack,
+        .irq_mask       = s3c_irq_uart2_mask,
+        .irq_unmask     = s3c_irq_uart2_unmask,
+        .irq_ack        = s3c_irq_uart2_ack,
 };
 
 /* ADC and Touchscreen */
 
 static void
-s3c_irq_adc_mask(unsigned int irqno)
+s3c_irq_adc_mask(struct irq_data *d)
 {
-        s3c_irqsub_mask(irqno, INTMSK_ADCPARENT, 3 << 9);
+        s3c_irqsub_mask(d->irq, INTMSK_ADCPARENT, 3 << 9);
 }
 
 static void
-s3c_irq_adc_unmask(unsigned int irqno)
+s3c_irq_adc_unmask(struct irq_data *d)
 {
-        s3c_irqsub_unmask(irqno, INTMSK_ADCPARENT);
+        s3c_irqsub_unmask(d->irq, INTMSK_ADCPARENT);
 }
 
 static void
-s3c_irq_adc_ack(unsigned int irqno)
+s3c_irq_adc_ack(struct irq_data *d)
 {
-        s3c_irqsub_ack(irqno, INTMSK_ADCPARENT, 3 << 9);
+        s3c_irqsub_ack(d->irq, INTMSK_ADCPARENT, 3 << 9);
 }
 
 static struct irq_chip s3c_irq_adc = {
         .name           = "s3c-adc",
-        .mask           = s3c_irq_adc_mask,
-        .unmask         = s3c_irq_adc_unmask,
-        .ack            = s3c_irq_adc_ack,
+        .irq_mask       = s3c_irq_adc_mask,
+        .irq_unmask     = s3c_irq_adc_unmask,
+        .irq_ack        = s3c_irq_adc_ack,
 };
 
 /* irq demux for adc */
diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c
index 461f070eb62d..82f2d4a39291 100644
--- a/arch/arm/plat-s3c24xx/s3c2443-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c
@@ -271,7 +271,7 @@ static struct clk init_clocks[] = {
                 .ctrlbit        = S3C2443_HCLKCON_DMA5,
         }, {
                 .name           = "hsmmc",
-                .id             = 0,
+                .id             = 1,
                 .parent         = &clk_h,
                 .enable         = s3c2443_clkcon_enable_h,
                 .ctrlbit        = S3C2443_HCLKCON_HSMMC,
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 65dbfa8e0a86..deb39951a22e 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -56,3 +56,29 @@ config S5P_DEV_ONENAND
         bool
         help
           Compile in platform device definition for OneNAND controller
+
+config S5P_DEV_CSIS0
+        bool
+        help
+          Compile in platform device definitions for MIPI-CSIS channel 0
+
+config S5P_DEV_CSIS1
+        bool
+        help
+          Compile in platform device definitions for MIPI-CSIS channel 1
+
+menuconfig S5P_SYSMMU
+        bool "SYSMMU support"
+        depends on ARCH_S5PV310
+        help
+          This is a System MMU driver for Samsung ARM based Soc.
+
+if S5P_SYSMMU
+
+config S5P_SYSMMU_DEBUG
+        bool "Enables debug messages"
+        depends on S5P_SYSMMU
+        help
+          This enables SYSMMU driver debug massages.
+
+endif
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index de65238a7aef..92efe1adcfd6 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -28,3 +28,6 @@ obj-$(CONFIG_S5P_DEV_FIMC0)	+= dev-fimc0.o
 obj-$(CONFIG_S5P_DEV_FIMC1)     += dev-fimc1.o
 obj-$(CONFIG_S5P_DEV_FIMC2)     += dev-fimc2.o
 obj-$(CONFIG_S5P_DEV_ONENAND)   += dev-onenand.o
+obj-$(CONFIG_S5P_DEV_CSIS0)     += dev-csis0.o
+obj-$(CONFIG_S5P_DEV_CSIS1)     += dev-csis1.o
+obj-$(CONFIG_S5P_SYSMMU)        += sysmmu.o
diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c
index 74f7f5a5446c..047d31c1bbd8 100644
--- a/arch/arm/plat-s5p/cpu.c
+++ b/arch/arm/plat-s5p/cpu.c
@@ -108,6 +108,11 @@ static struct map_desc s5p_iodesc[] __initdata = {
                 .pfn            = __phys_to_pfn(S3C_PA_WDT),
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_SROMC,
+                .pfn            = __phys_to_pfn(S5P_PA_SROMC),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
         },
 };
 
diff --git a/arch/arm/plat-s5p/dev-csis0.c b/arch/arm/plat-s5p/dev-csis0.c
new file mode 100644
index 000000000000..dfab1c85f54f
--- /dev/null
+++ b/arch/arm/plat-s5p/dev-csis0.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ *
+ * S5P series device definition for MIPI-CSIS channel 0
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <mach/map.h>
+
+static struct resource s5p_mipi_csis0_resource[] = {
+        [0] = {
+                .start = S5P_PA_MIPI_CSIS0,
+                .end   = S5P_PA_MIPI_CSIS0 + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_MIPI_CSIS0,
+                .end   = IRQ_MIPI_CSIS0,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device s5p_device_mipi_csis0 = {
+        .name             = "s5p-mipi-csis",
+        .id               = 0,
+        .num_resources    = ARRAY_SIZE(s5p_mipi_csis0_resource),
+        .resource         = s5p_mipi_csis0_resource,
+};
diff --git a/arch/arm/plat-s5p/dev-csis1.c b/arch/arm/plat-s5p/dev-csis1.c
new file mode 100644
index 000000000000..e3053f27fbbf
--- /dev/null
+++ b/arch/arm/plat-s5p/dev-csis1.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ *
+ * S5P series device definition for MIPI-CSIS channel 1
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <mach/map.h>
+
+static struct resource s5p_mipi_csis1_resource[] = {
+        [0] = {
+                .start = S5P_PA_MIPI_CSIS1,
+                .end   = S5P_PA_MIPI_CSIS1 + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_MIPI_CSIS1,
+                .end   = IRQ_MIPI_CSIS1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device s5p_device_mipi_csis1 = {
+        .name             = "s5p-mipi-csis",
+        .id               = 1,
+        .num_resources    = ARRAY_SIZE(s5p_mipi_csis1_resource),
+        .resource         = s5p_mipi_csis1_resource,
+};
diff --git a/arch/arm/plat-s5p/include/plat/csis.h b/arch/arm/plat-s5p/include/plat/csis.h
new file mode 100644
index 000000000000..51e308c7981d
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/csis.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ *
+ * S5P series MIPI CSI slave device support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef PLAT_S5P_CSIS_H_
+#define PLAT_S5P_CSIS_H_ __FILE__
+
+/**
+ * struct s5p_platform_mipi_csis - platform data for MIPI-CSIS
+ * @clk_rate: bus clock frequency
+ * @lanes: number of data lanes used
+ * @alignment: data alignment in bits
+ * @hs_settle: HS-RX settle time
+ */
+struct s5p_platform_mipi_csis {
+        unsigned long clk_rate;
+        u8 lanes;
+        u8 alignment;
+        u8 hs_settle;
+};
+
+#endif /* PLAT_S5P_CSIS_H_ */
diff --git a/arch/arm/plat-s5p/include/plat/map-s5p.h b/arch/arm/plat-s5p/include/plat/map-s5p.h
index fef353d44513..d973d39666a3 100644
--- a/arch/arm/plat-s5p/include/plat/map-s5p.h
+++ b/arch/arm/plat-s5p/include/plat/map-s5p.h
@@ -15,6 +15,7 @@
 
 #define S5P_VA_CHIPID           S3C_ADDR(0x02000000)
 #define S5P_VA_CMU              S3C_ADDR(0x02100000)
+#define S5P_VA_PMU              S3C_ADDR(0x02180000)
 #define S5P_VA_GPIO             S3C_ADDR(0x02200000)
 #define S5P_VA_GPIO1            S5P_VA_GPIO
 #define S5P_VA_GPIO2            S3C_ADDR(0x02240000)
diff --git a/arch/arm/plat-s5p/include/plat/regs-srom.h b/arch/arm/plat-s5p/include/plat/regs-srom.h
new file mode 100644
index 000000000000..f121ab5e76cb
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/regs-srom.h
@@ -0,0 +1,54 @@
+/* linux/arch/arm/plat-s5p/include/plat/regs-srom.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P SROMC register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_PLAT_S5P_REGS_SROM_H
+#define __ASM_PLAT_S5P_REGS_SROM_H __FILE__
+
+#include <mach/map.h>
+
+#define S5P_SROMREG(x)          (S5P_VA_SROMC + (x))
+
+#define S5P_SROM_BW             S5P_SROMREG(0x0)
+#define S5P_SROM_BC0            S5P_SROMREG(0x4)
+#define S5P_SROM_BC1            S5P_SROMREG(0x8)
+#define S5P_SROM_BC2            S5P_SROMREG(0xc)
+#define S5P_SROM_BC3            S5P_SROMREG(0x10)
+#define S5P_SROM_BC4            S5P_SROMREG(0x14)
+#define S5P_SROM_BC5            S5P_SROMREG(0x18)
+
+/* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */
+
+#define S5P_SROM_BW__DATAWIDTH__SHIFT           0
+#define S5P_SROM_BW__ADDRMODE__SHIFT            1
+#define S5P_SROM_BW__WAITENABLE__SHIFT          2
+#define S5P_SROM_BW__BYTEENABLE__SHIFT          3
+
+#define S5P_SROM_BW__CS_MASK                    0xf
+
+#define S5P_SROM_BW__NCS0__SHIFT                0
+#define S5P_SROM_BW__NCS1__SHIFT                4
+#define S5P_SROM_BW__NCS2__SHIFT                8
+#define S5P_SROM_BW__NCS3__SHIFT                12
+#define S5P_SROM_BW__NCS4__SHIFT                16
+#define S5P_SROM_BW__NCS5__SHIFT                20
+
+/* applies to same to BCS0 - BCS3 */
+
+#define S5P_SROM_BCX__PMC__SHIFT                0
+#define S5P_SROM_BCX__TACP__SHIFT               4
+#define S5P_SROM_BCX__TCAH__SHIFT               8
+#define S5P_SROM_BCX__TCOH__SHIFT               12
+#define S5P_SROM_BCX__TACC__SHIFT               16
+#define S5P_SROM_BCX__TCOS__SHIFT               24
+#define S5P_SROM_BCX__TACS__SHIFT               28
+
+#endif /* __ASM_PLAT_S5P_REGS_SROM_H */
diff --git a/arch/arm/plat-s5p/include/plat/sysmmu.h b/arch/arm/plat-s5p/include/plat/sysmmu.h
new file mode 100644
index 000000000000..db298fc5438a
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/sysmmu.h
@@ -0,0 +1,23 @@
+/* linux/arch/arm/plat-s5p/include/plat/sysmmu.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * Samsung sysmmu driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_PLAT_S5P_SYSMMU_H
+#define __ASM_PLAT_S5P_SYSMMU_H __FILE__
+
+/* debug macro */
+#ifdef CONFIG_S5P_SYSMMU_DEBUG
+#define sysmmu_debug(fmt, arg...)       printk(KERN_INFO "[%s] " fmt, __func__, ## arg)
+#else
+#define sysmmu_debug(fmt, arg...)       do { } while (0)
+#endif
+
+#endif /* __ASM_PLAT_S5P_SYSMMU_H */
diff --git a/arch/arm/plat-s5p/irq-eint.c b/arch/arm/plat-s5p/irq-eint.c
index 752f1a645f9d..225aa25405db 100644
--- a/arch/arm/plat-s5p/irq-eint.c
+++ b/arch/arm/plat-s5p/irq-eint.c
@@ -28,39 +28,40 @@
 #include <plat/gpio-cfg.h>
 #include <mach/regs-gpio.h>
 
-static inline void s5p_irq_eint_mask(unsigned int irq)
+static inline void s5p_irq_eint_mask(struct irq_data *data)
 {
         u32 mask;
 
-        mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq)));
-        mask |= eint_irq_to_bit(irq);
-        __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq)));
+        mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+        mask |= eint_irq_to_bit(data->irq);
+        __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
 }
 
-static void s5p_irq_eint_unmask(unsigned int irq)
+static void s5p_irq_eint_unmask(struct irq_data *data)
 {
         u32 mask;
 
-        mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq)));
-        mask &= ~(eint_irq_to_bit(irq));
-        __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq)));
+        mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+        mask &= ~(eint_irq_to_bit(data->irq));
+        __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
 }
 
-static inline void s5p_irq_eint_ack(unsigned int irq)
+static inline void s5p_irq_eint_ack(struct irq_data *data)
 {
-        __raw_writel(eint_irq_to_bit(irq), S5P_EINT_PEND(EINT_REG_NR(irq)));
+        __raw_writel(eint_irq_to_bit(data->irq),
+                     S5P_EINT_PEND(EINT_REG_NR(data->irq)));
 }
 
-static void s5p_irq_eint_maskack(unsigned int irq)
+static void s5p_irq_eint_maskack(struct irq_data *data)
 {
         /* compiler should in-line these */
-        s5p_irq_eint_mask(irq);
-        s5p_irq_eint_ack(irq);
+        s5p_irq_eint_mask(data);
+        s5p_irq_eint_ack(data);
 }
 
-static int s5p_irq_eint_set_type(unsigned int irq, unsigned int type)
+static int s5p_irq_eint_set_type(struct irq_data *data, unsigned int type)
 {
-        int offs = EINT_OFFSET(irq);
+        int offs = EINT_OFFSET(data->irq);
         int shift;
         u32 ctrl, mask;
         u32 newvalue = 0;
@@ -94,10 +95,10 @@ static int s5p_irq_eint_set_type(unsigned int irq, unsigned int type)
         shift = (offs & 0x7) * 4;
         mask = 0x7 << shift;
 
-        ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(irq)));
+        ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
         ctrl &= ~mask;
         ctrl |= newvalue << shift;
-        __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(irq)));
+        __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
 
         if ((0 <= offs) && (offs < 8))
                 s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
@@ -119,13 +120,13 @@ static int s5p_irq_eint_set_type(unsigned int irq, unsigned int type)
 
 static struct irq_chip s5p_irq_eint = {
         .name           = "s5p-eint",
-        .mask           = s5p_irq_eint_mask,
-        .unmask         = s5p_irq_eint_unmask,
-        .mask_ack       = s5p_irq_eint_maskack,
-        .ack            = s5p_irq_eint_ack,
-        .set_type       = s5p_irq_eint_set_type,
+        .irq_mask       = s5p_irq_eint_mask,
+        .irq_unmask     = s5p_irq_eint_unmask,
+        .irq_mask_ack   = s5p_irq_eint_maskack,
+        .irq_ack        = s5p_irq_eint_ack,
+        .irq_set_type   = s5p_irq_eint_set_type,
 #ifdef CONFIG_PM
-        .set_wake       = s3c_irqext_wake,
+        .irq_set_wake   = s3c_irqext_wake,
 #endif
 };
 
@@ -159,42 +160,43 @@ static void s5p_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
         s5p_irq_demux_eint(IRQ_EINT(24));
 }
 
-static inline void s5p_irq_vic_eint_mask(unsigned int irq)
+static inline void s5p_irq_vic_eint_mask(struct irq_data *data)
 {
-        void __iomem *base = get_irq_chip_data(irq);
+        void __iomem *base = irq_data_get_irq_chip_data(data);
 
-        s5p_irq_eint_mask(irq);
-        writel(1 << EINT_OFFSET(irq), base + VIC_INT_ENABLE_CLEAR);
+        s5p_irq_eint_mask(data);
+        writel(1 << EINT_OFFSET(data->irq), base + VIC_INT_ENABLE_CLEAR);
 }
 
-static void s5p_irq_vic_eint_unmask(unsigned int irq)
+static void s5p_irq_vic_eint_unmask(struct irq_data *data)
 {
-        void __iomem *base = get_irq_chip_data(irq);
+        void __iomem *base = irq_data_get_irq_chip_data(data);
 
-        s5p_irq_eint_unmask(irq);
-        writel(1 << EINT_OFFSET(irq), base + VIC_INT_ENABLE);
+        s5p_irq_eint_unmask(data);
+        writel(1 << EINT_OFFSET(data->irq), base + VIC_INT_ENABLE);
 }
 
-static inline void s5p_irq_vic_eint_ack(unsigned int irq)
+static inline void s5p_irq_vic_eint_ack(struct irq_data *data)
 {
-        __raw_writel(eint_irq_to_bit(irq), S5P_EINT_PEND(EINT_REG_NR(irq)));
+        __raw_writel(eint_irq_to_bit(data->irq),
+                     S5P_EINT_PEND(EINT_REG_NR(data->irq)));
 }
 
-static void s5p_irq_vic_eint_maskack(unsigned int irq)
+static void s5p_irq_vic_eint_maskack(struct irq_data *data)
 {
-        s5p_irq_vic_eint_mask(irq);
-        s5p_irq_vic_eint_ack(irq);
+        s5p_irq_vic_eint_mask(data);
+        s5p_irq_vic_eint_ack(data);
 }
 
 static struct irq_chip s5p_irq_vic_eint = {
         .name           = "s5p_vic_eint",
-        .mask           = s5p_irq_vic_eint_mask,
-        .unmask         = s5p_irq_vic_eint_unmask,
-        .mask_ack       = s5p_irq_vic_eint_maskack,
-        .ack            = s5p_irq_vic_eint_ack,
-        .set_type       = s5p_irq_eint_set_type,
+        .irq_mask       = s5p_irq_vic_eint_mask,
+        .irq_unmask     = s5p_irq_vic_eint_unmask,
+        .irq_mask_ack   = s5p_irq_vic_eint_maskack,
+        .irq_ack        = s5p_irq_vic_eint_ack,
+        .irq_set_type   = s5p_irq_eint_set_type,
 #ifdef CONFIG_PM
-        .set_wake       = s3c_irqext_wake,
+        .irq_set_wake   = s3c_irqext_wake,
 #endif
 };
 
diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c
index 0e5dc8cbf5e3..3b6bf89d1739 100644
--- a/arch/arm/plat-s5p/irq-gpioint.c
+++ b/arch/arm/plat-s5p/irq-gpioint.c
@@ -30,9 +30,9 @@
 
 static struct s3c_gpio_chip *irq_chips[S5P_GPIOINT_GROUP_MAXNR];
 
-static int s5p_gpioint_get_group(unsigned int irq)
+static int s5p_gpioint_get_group(struct irq_data *data)
 {
-        struct gpio_chip *chip = get_irq_data(irq);
+        struct gpio_chip *chip = irq_data_get_irq_data(data);
         struct s3c_gpio_chip *s3c_chip = container_of(chip,
                         struct s3c_gpio_chip, chip);
         int group;
@@ -44,22 +44,22 @@ static int s5p_gpioint_get_group(unsigned int irq)
         return group;
 }
 
-static int s5p_gpioint_get_offset(unsigned int irq)
+static int s5p_gpioint_get_offset(struct irq_data *data)
 {
-        struct gpio_chip *chip = get_irq_data(irq);
+        struct gpio_chip *chip = irq_data_get_irq_data(data);
         struct s3c_gpio_chip *s3c_chip = container_of(chip,
                         struct s3c_gpio_chip, chip);
 
-        return irq - s3c_chip->irq_base;
+        return data->irq - s3c_chip->irq_base;
 }
 
-static void s5p_gpioint_ack(unsigned int irq)
+static void s5p_gpioint_ack(struct irq_data *data)
 {
         int group, offset, pend_offset;
         unsigned int value;
 
-        group = s5p_gpioint_get_group(irq);
-        offset = s5p_gpioint_get_offset(irq);
+        group = s5p_gpioint_get_group(data);
+        offset = s5p_gpioint_get_offset(data);
         pend_offset = group << 2;
 
         value = __raw_readl(S5P_GPIOREG(GPIOINT_PEND_OFFSET) + pend_offset);
@@ -67,13 +67,13 @@ static void s5p_gpioint_ack(unsigned int irq)
         __raw_writel(value, S5P_GPIOREG(GPIOINT_PEND_OFFSET) + pend_offset);
 }
 
-static void s5p_gpioint_mask(unsigned int irq)
+static void s5p_gpioint_mask(struct irq_data *data)
 {
         int group, offset, mask_offset;
         unsigned int value;
 
-        group = s5p_gpioint_get_group(irq);
-        offset = s5p_gpioint_get_offset(irq);
+        group = s5p_gpioint_get_group(data);
+        offset = s5p_gpioint_get_offset(data);
         mask_offset = group << 2;
 
         value = __raw_readl(S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset);
@@ -81,13 +81,13 @@ static void s5p_gpioint_mask(unsigned int irq)
         __raw_writel(value, S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset);
 }
 
-static void s5p_gpioint_unmask(unsigned int irq)
+static void s5p_gpioint_unmask(struct irq_data *data)
 {
         int group, offset, mask_offset;
         unsigned int value;
 
-        group = s5p_gpioint_get_group(irq);
-        offset = s5p_gpioint_get_offset(irq);
+        group = s5p_gpioint_get_group(data);
+        offset = s5p_gpioint_get_offset(data);
         mask_offset = group << 2;
 
         value = __raw_readl(S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset);
@@ -95,19 +95,19 @@ static void s5p_gpioint_unmask(unsigned int irq)
         __raw_writel(value, S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset);
 }
 
-static void s5p_gpioint_mask_ack(unsigned int irq)
+static void s5p_gpioint_mask_ack(struct irq_data *data)
 {
-        s5p_gpioint_mask(irq);
-        s5p_gpioint_ack(irq);
+        s5p_gpioint_mask(data);
+        s5p_gpioint_ack(data);
 }
 
-static int s5p_gpioint_set_type(unsigned int irq, unsigned int type)
+static int s5p_gpioint_set_type(struct irq_data *data, unsigned int type)
 {
         int group, offset, con_offset;
         unsigned int value;
 
-        group = s5p_gpioint_get_group(irq);
-        offset = s5p_gpioint_get_offset(irq);
+        group = s5p_gpioint_get_group(data);
+        offset = s5p_gpioint_get_offset(data);
         con_offset = group << 2;
 
         switch (type) {
@@ -142,11 +142,11 @@ static int s5p_gpioint_set_type(unsigned int irq, unsigned int type)
 
 struct irq_chip s5p_gpioint = {
         .name           = "s5p_gpioint",
-        .ack            = s5p_gpioint_ack,
-        .mask           = s5p_gpioint_mask,
-        .mask_ack       = s5p_gpioint_mask_ack,
-        .unmask         = s5p_gpioint_unmask,
-        .set_type       = s5p_gpioint_set_type,
+        .irq_ack        = s5p_gpioint_ack,
+        .irq_mask       = s5p_gpioint_mask,
+        .irq_mask_ack   = s5p_gpioint_mask_ack,
+        .irq_unmask     = s5p_gpioint_unmask,
+        .irq_set_type   = s5p_gpioint_set_type,
 };
 
 static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
diff --git a/arch/arm/plat-s5p/irq-pm.c b/arch/arm/plat-s5p/irq-pm.c
index dc33b9ecda45..5259ad458bc8 100644
--- a/arch/arm/plat-s5p/irq-pm.c
+++ b/arch/arm/plat-s5p/irq-pm.c
@@ -37,14 +37,14 @@
 unsigned long s3c_irqwake_intallow      = 0x00000006L;
 unsigned long s3c_irqwake_eintallow     = 0xffffffffL;
 
-int s3c_irq_wake(unsigned int irqno, unsigned int state)
+int s3c_irq_wake(struct irq_data *data, unsigned int state)
 {
         unsigned long irqbit;
 
-        switch (irqno) {
+        switch (data->irq) {
         case IRQ_RTC_TIC:
         case IRQ_RTC_ALARM:
-                irqbit = 1 << (irqno + 1 - IRQ_RTC_ALARM);
+                irqbit = 1 << (data->irq + 1 - IRQ_RTC_ALARM);
                 if (!state)
                         s3c_irqwake_intmask |= irqbit;
                 else
diff --git a/arch/arm/plat-s5p/sysmmu.c b/arch/arm/plat-s5p/sysmmu.c
new file mode 100644
index 000000000000..d804914dc2e2
--- /dev/null
+++ b/arch/arm/plat-s5p/sysmmu.c
@@ -0,0 +1,328 @@
+/* linux/arch/arm/plat-s5p/sysmmu.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+
+#include <mach/map.h>
+#include <mach/regs-sysmmu.h>
+#include <mach/sysmmu.h>
+
+#include <plat/sysmmu.h>
+
+struct sysmmu_controller s5p_sysmmu_cntlrs[S5P_SYSMMU_TOTAL_IPNUM];
+
+void s5p_sysmmu_register(struct sysmmu_controller *sysmmuconp)
+{
+        unsigned int reg_mmu_ctrl;
+        unsigned int reg_mmu_status;
+        unsigned int reg_pt_base_addr;
+        unsigned int reg_int_status;
+        unsigned int reg_page_ft_addr;
+
+        reg_int_status = __raw_readl(sysmmuconp->regs + S5P_INT_STATUS);
+        reg_mmu_ctrl = __raw_readl(sysmmuconp->regs + S5P_MMU_CTRL);
+        reg_mmu_status = __raw_readl(sysmmuconp->regs + S5P_MMU_STATUS);
+        reg_pt_base_addr = __raw_readl(sysmmuconp->regs + S5P_PT_BASE_ADDR);
+        reg_page_ft_addr = __raw_readl(sysmmuconp->regs + S5P_PAGE_FAULT_ADDR);
+
+        printk(KERN_INFO "%s: ips:%s\n", __func__, sysmmuconp->name);
+        printk(KERN_INFO "%s: MMU_CTRL:0x%X, ", __func__, reg_mmu_ctrl);
+        printk(KERN_INFO "MMU_STATUS:0x%X, PT_BASE_ADDR:0x%X\n", reg_mmu_status, reg_pt_base_addr);
+        printk(KERN_INFO "%s: INT_STATUS:0x%X, PAGE_FAULT_ADDR:0x%X\n", __func__, reg_int_status, reg_page_ft_addr);
+
+        switch (reg_int_status & 0xFF) {
+        case 0x1:
+                printk(KERN_INFO "%s: Page fault\n", __func__);
+                printk(KERN_INFO "%s: Virtual address causing last page fault or bus error : 0x%x\n", __func__ , reg_page_ft_addr);
+                break;
+        case 0x2:
+                printk(KERN_INFO "%s: AR multi-hit fault\n", __func__);
+                break;
+        case 0x4:
+                printk(KERN_INFO "%s: AW multi-hit fault\n", __func__);
+                break;
+        case 0x8:
+                printk(KERN_INFO "%s: Bus error\n", __func__);
+                break;
+        case 0x10:
+                printk(KERN_INFO "%s: AR Security protection fault\n", __func__);
+                break;
+        case 0x20:
+                printk(KERN_INFO "%s: AR Access protection fault\n", __func__);
+                break;
+        case 0x40:
+                printk(KERN_INFO "%s: AW Security protection fault\n", __func__);
+                break;
+        case 0x80:
+                printk(KERN_INFO "%s: AW Access protection fault\n", __func__);
+                break;
+        }
+}
+
+static irqreturn_t s5p_sysmmu_irq(int irq, void *dev_id)
+{
+        unsigned int i;
+        unsigned int reg_int_status;
+        struct sysmmu_controller *sysmmuconp;
+
+        for (i = 0; i < S5P_SYSMMU_TOTAL_IPNUM; i++) {
+                sysmmuconp = &s5p_sysmmu_cntlrs[i];
+
+                if (sysmmuconp->enable == true) {
+                        reg_int_status = __raw_readl(sysmmuconp->regs + S5P_INT_STATUS);
+
+                        if (reg_int_status & 0xFF)
+                                s5p_sysmmu_register(sysmmuconp);
+                }
+        }
+        return IRQ_HANDLED;
+}
+
+int s5p_sysmmu_set_tablebase_pgd(sysmmu_ips ips, unsigned long pgd)
+{
+        struct sysmmu_controller *sysmmuconp = NULL;
+
+        sysmmuconp = &s5p_sysmmu_cntlrs[ips];
+
+        if (sysmmuconp == NULL) {
+                printk(KERN_ERR "failed to get ip's sysmmu info\n");
+                return 1;
+        }
+
+        /* Set sysmmu page table base address */
+        __raw_writel(pgd, sysmmuconp->regs + S5P_PT_BASE_ADDR);
+
+        if (s5p_sysmmu_tlb_invalidate(ips) != 0)
+                printk(KERN_ERR "failed s5p_sysmmu_tlb_invalidate\n");
+
+        return 0;
+}
+
+static int s5p_sysmmu_set_tablebase(sysmmu_ips ips)
+{
+        unsigned int pg;
+        struct sysmmu_controller *sysmmuconp;
+
+        sysmmuconp = &s5p_sysmmu_cntlrs[ips];
+
+        if (sysmmuconp == NULL) {
+                printk(KERN_ERR "failed to get ip's sysmmu info\n");
+                return 1;
+        }
+
+        __asm__("mrc    p15, 0, %0, c2, c0, 0"  \
+                : "=r" (pg) : : "cc");          \
+                pg &= ~0x3fff;
+
+        sysmmu_debug("CP15 TTBR0 : 0x%x\n", pg);
+
+        /* Set sysmmu page table base address */
+        __raw_writel(pg, sysmmuconp->regs + S5P_PT_BASE_ADDR);
+
+        return 0;
+}
+
+int s5p_sysmmu_enable(sysmmu_ips ips)
+{
+        unsigned int reg;
+
+        struct sysmmu_controller *sysmmuconp;
+
+        sysmmuconp = &s5p_sysmmu_cntlrs[ips];
+
+        if (sysmmuconp == NULL) {
+                printk(KERN_ERR "failed to get ip's sysmmu info\n");
+                return 1;
+        }
+
+        s5p_sysmmu_set_tablebase(ips);
+
+        /* replacement policy : LRU */
+        reg = __raw_readl(sysmmuconp->regs + S5P_MMU_CFG);
+        reg |= 0x1;
+        __raw_writel(reg, sysmmuconp->regs + S5P_MMU_CFG);
+
+        /* Enable interrupt, Enable MMU */
+        reg = __raw_readl(sysmmuconp->regs + S5P_MMU_CTRL);
+        reg |= (0x1 << 2) | (0x1 << 0);
+
+        __raw_writel(reg, sysmmuconp->regs + S5P_MMU_CTRL);
+
+        sysmmuconp->enable = true;
+
+        return 0;
+}
+
+int s5p_sysmmu_disable(sysmmu_ips ips)
+{
+        unsigned int reg;
+
+        struct sysmmu_controller *sysmmuconp = NULL;
+
+        if (ips > S5P_SYSMMU_TOTAL_IPNUM)
+                printk(KERN_ERR "failed to get ips parameter\n");
+
+        sysmmuconp = &s5p_sysmmu_cntlrs[ips];
+
+        if (sysmmuconp == NULL) {
+                printk(KERN_ERR "failed to get ip's sysmmu info\n");
+                return 1;
+        }
+
+        reg = __raw_readl(sysmmuconp->regs + S5P_MMU_CFG);
+
+        /* replacement policy : LRU */
+        reg |= 0x1;
+        __raw_writel(reg, sysmmuconp->regs + S5P_MMU_CFG);
+
+        reg = __raw_readl(sysmmuconp->regs + S5P_MMU_CTRL);
+
+        /* Disable MMU */
+        reg &= ~0x1;
+        __raw_writel(reg, sysmmuconp->regs + S5P_MMU_CTRL);
+
+        sysmmuconp->enable = false;
+
+        return 0;
+}
+
+int s5p_sysmmu_tlb_invalidate(sysmmu_ips ips)
+{
+        unsigned int reg;
+        struct sysmmu_controller *sysmmuconp = NULL;
+
+        sysmmuconp = &s5p_sysmmu_cntlrs[ips];
+
+        if (sysmmuconp == NULL) {
+                printk(KERN_ERR "failed to get ip's sysmmu info\n");
+                return 1;
+        }
+
+        /* set Block MMU for flush TLB */
+        reg = __raw_readl(sysmmuconp->regs + S5P_MMU_CTRL);
+        reg |= 0x1 << 1;
+        __raw_writel(reg, sysmmuconp->regs + S5P_MMU_CTRL);
+
+        /* flush all TLB entry */
+        __raw_writel(0x1, sysmmuconp->regs + S5P_MMU_FLUSH);
+
+        /* set Un-block MMU after flush TLB */
+        reg = __raw_readl(sysmmuconp->regs + S5P_MMU_CTRL);
+        reg &= ~(0x1 << 1);
+        __raw_writel(reg, sysmmuconp->regs + S5P_MMU_CTRL);
+
+        return 0;
+}
+
+static int s5p_sysmmu_probe(struct platform_device *pdev)
+{
+        int i;
+        int ret;
+        struct resource *res;
+        struct sysmmu_controller *sysmmuconp;
+        sysmmu_ips ips;
+
+        for (i = 0; i < S5P_SYSMMU_TOTAL_IPNUM; i++) {
+                sysmmuconp = &s5p_sysmmu_cntlrs[i];
+                if (sysmmuconp == NULL) {
+                        printk(KERN_ERR "failed to get ip's sysmmu info\n");
+                        ret = -ENOENT;
+                        goto err_res;
+                }
+
+                sysmmuconp->name = sysmmu_ips_name[i];
+
+                res = platform_get_resource(pdev, IORESOURCE_MEM, i);
+                if (!res) {
+                        printk(KERN_ERR "failed to get sysmmu resource\n");
+                        ret = -ENODEV;
+                        goto err_res;
+                }
+
+                sysmmuconp->mem = request_mem_region(res->start,
+                                ((res->end) - (res->start)) + 1, pdev->name);
+                if (!sysmmuconp->mem) {
+                        pr_err("failed to request sysmmu memory region\n");
+                        ret = -EBUSY;
+                        goto err_res;
+                }
+
+                sysmmuconp->regs = ioremap(res->start, res->end - res->start + 1);
+                if (!sysmmuconp->regs) {
+                        pr_err("failed to sysmmu ioremap\n");
+                        ret = -ENXIO;
+                        goto err_reg;
+                }
+
+                sysmmuconp->irq = platform_get_irq(pdev, i);
+                if (sysmmuconp->irq <= 0) {
+                        pr_err("failed to get sysmmu irq resource\n");
+                        ret = -ENOENT;
+                        goto err_map;
+                }
+
+                ret = request_irq(sysmmuconp->irq, s5p_sysmmu_irq, IRQF_DISABLED, pdev->name, sysmmuconp);
+                if (ret) {
+                        pr_err("failed to request irq\n");
+                        ret = -ENOENT;
+                        goto err_map;
+                }
+
+                ips = (sysmmu_ips)i;
+
+                sysmmuconp->ips = ips;
+        }
+
+        return 0;
+
+err_reg:
+        release_mem_region((resource_size_t)sysmmuconp->mem, (resource_size_t)((res->end) - (res->start) + 1));
+err_map:
+        iounmap(sysmmuconp->regs);
+err_res:
+        return ret;
+}
+
+static int s5p_sysmmu_remove(struct platform_device *pdev)
+{
+        return 0;
+}
+int s5p_sysmmu_runtime_suspend(struct device *dev)
+{
+        return 0;
+}
+
+int s5p_sysmmu_runtime_resume(struct device *dev)
+{
+        return 0;
+}
+
+const struct dev_pm_ops s5p_sysmmu_pm_ops = {
+        .runtime_suspend        = s5p_sysmmu_runtime_suspend,
+        .runtime_resume         = s5p_sysmmu_runtime_resume,
+};
+
+static struct platform_driver s5p_sysmmu_driver = {
+        .probe          = s5p_sysmmu_probe,
+        .remove         = s5p_sysmmu_remove,
+        .driver         = {
+                .owner          = THIS_MODULE,
+                .name           = "s5p-sysmmu",
+                .pm             = &s5p_sysmmu_pm_ops,
+        }
+};
+
+static int __init s5p_sysmmu_init(void)
+{
+        return platform_driver_register(&s5p_sysmmu_driver);
+}
+arch_initcall(s5p_sysmmu_init);
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index dcd6eff4ee53..32be05cf82a3 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -95,6 +95,12 @@ config S3C_GPIO_PULL_UPDOWN
         help
           Internal configuration to enable the correct GPIO pull helper
 
+config S3C_GPIO_PULL_S3C2443
+        bool
+        select S3C_GPIO_PULL_UPDOWN
+        help
+          Internal configuration to enable the correct GPIO pull helper for S3C2443-style GPIO
+
 config S3C_GPIO_PULL_DOWN
         bool
         help
@@ -333,4 +339,12 @@ config SAMSUNG_WAKEMASK
           and above. This code allows a set of interrupt to wakeup-mask
           mappings. See <plat/wakeup-mask.h>
 
+comment "Power Domain"
+
+config SAMSUNG_PD
+        bool "Samsung Power Domain"
+        depends on PM_RUNTIME
+        help
+          Say Y here if you want to control Power Domain by Runtime PM.
+
 endif
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 19d8a16c3066..29932f88a8d6 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -74,6 +74,10 @@ obj-$(CONFIG_SAMSUNG_PM_CHECK)	+= pm-check.o
 
 obj-$(CONFIG_SAMSUNG_WAKEMASK)  += wakeup-mask.o
 
+# PD support
+
+obj-$(CONFIG_SAMSUNG_PD)        += pd.o
+
 # PWM support
 
 obj-$(CONFIG_HAVE_PWM)          += pwm.o
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
index e8d20b0bc50e..772892826ffc 100644
--- a/arch/arm/plat-samsung/clock.c
+++ b/arch/arm/plat-samsung/clock.c
@@ -39,6 +39,9 @@
 #include <linux/clk.h>
 #include <linux/spinlock.h>
 #include <linux/io.h>
+#if defined(CONFIG_DEBUG_FS)
+#include <linux/debugfs.h>
+#endif
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -447,3 +450,92 @@ int __init s3c24xx_register_baseclocks(unsigned long xtal)
         return 0;
 }
 
+#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
+/* debugfs support to trace clock tree hierarchy and attributes */
+
+static struct dentry *clk_debugfs_root;
+
+static int clk_debugfs_register_one(struct clk *c)
+{
+        int err;
+        struct dentry *d, *child, *child_tmp;
+        struct clk *pa = c->parent;
+        char s[255];
+        char *p = s;
+
+        p += sprintf(p, "%s", c->name);
+
+        if (c->id >= 0)
+                sprintf(p, ":%d", c->id);
+
+        d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root);
+        if (!d)
+                return -ENOMEM;
+
+        c->dent = d;
+
+        d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usage);
+        if (!d) {
+                err = -ENOMEM;
+                goto err_out;
+        }
+
+        d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
+        if (!d) {
+                err = -ENOMEM;
+                goto err_out;
+        }
+        return 0;
+
+err_out:
+        d = c->dent;
+        list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child)
+                debugfs_remove(child);
+        debugfs_remove(c->dent);
+        return err;
+}
+
+static int clk_debugfs_register(struct clk *c)
+{
+        int err;
+        struct clk *pa = c->parent;
+
+        if (pa && !pa->dent) {
+                err = clk_debugfs_register(pa);
+                if (err)
+                        return err;
+        }
+
+        if (!c->dent) {
+                err = clk_debugfs_register_one(c);
+                if (err)
+                        return err;
+        }
+        return 0;
+}
+
+static int __init clk_debugfs_init(void)
+{
+        struct clk *c;
+        struct dentry *d;
+        int err;
+
+        d = debugfs_create_dir("clock", NULL);
+        if (!d)
+                return -ENOMEM;
+        clk_debugfs_root = d;
+
+        list_for_each_entry(c, &clocks, list) {
+                err = clk_debugfs_register(c);
+                if (err)
+                        goto err_out;
+        }
+        return 0;
+
+err_out:
+        debugfs_remove_recursive(clk_debugfs_root);
+        return err;
+}
+late_initcall(clk_debugfs_init);
+
+#endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */
diff --git a/arch/arm/plat-samsung/dev-nand.c b/arch/arm/plat-samsung/dev-nand.c
index 3a7b8891ba4f..6927ae8fd118 100644
--- a/arch/arm/plat-samsung/dev-nand.c
+++ b/arch/arm/plat-samsung/dev-nand.c
@@ -126,5 +126,3 @@ void __init s3c_nand_set_platdata(struct s3c2410_platform_nand *nand)
 
         s3c_device_nand.dev.platform_data = npd;
 }
-
-EXPORT_SYMBOL_GPL(s3c_nand_set_platdata);
diff --git a/arch/arm/plat-samsung/gpio-config.c b/arch/arm/plat-samsung/gpio-config.c
index 0aa32f242ee4..1c0b0401594b 100644
--- a/arch/arm/plat-samsung/gpio-config.c
+++ b/arch/arm/plat-samsung/gpio-config.c
@@ -278,6 +278,48 @@ s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip,
         pup &= 0x3;
         return (__force s3c_gpio_pull_t)pup;
 }
+
+#ifdef CONFIG_S3C_GPIO_PULL_S3C2443
+int s3c_gpio_setpull_s3c2443(struct s3c_gpio_chip *chip,
+                                unsigned int off, s3c_gpio_pull_t pull)
+{
+        switch (pull) {
+        case S3C_GPIO_PULL_NONE:
+                pull = 0x01;
+                break;
+        case S3C_GPIO_PULL_UP:
+                pull = 0x00;
+                break;
+        case S3C_GPIO_PULL_DOWN:
+                pull = 0x02;
+                break;
+        }
+        return s3c_gpio_setpull_updown(chip, off, pull);
+}
+
+s3c_gpio_pull_t s3c_gpio_getpull_s3c2443(struct s3c_gpio_chip *chip,
+                                        unsigned int off)
+{
+        s3c_gpio_pull_t pull;
+
+        pull = s3c_gpio_getpull_updown(chip, off);
+
+        switch (pull) {
+        case 0x00:
+                pull = S3C_GPIO_PULL_UP;
+                break;
+        case 0x01:
+        case 0x03:
+                pull = S3C_GPIO_PULL_NONE;
+                break;
+        case 0x02:
+                pull = S3C_GPIO_PULL_DOWN;
+                break;
+        }
+
+        return pull;
+}
+#endif
 #endif
 
 #if defined(CONFIG_S3C_GPIO_PULL_UP) || defined(CONFIG_S3C_GPIO_PULL_DOWN)
diff --git a/arch/arm/plat-samsung/gpiolib.c b/arch/arm/plat-samsung/gpiolib.c
index c354089254fc..ea37c0461788 100644
--- a/arch/arm/plat-samsung/gpiolib.c
+++ b/arch/arm/plat-samsung/gpiolib.c
@@ -197,3 +197,10 @@ void __init samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip,
                 s3c_gpiolib_add(chip);
         }
 }
+
+void __init samsung_gpiolib_add_2bit_chips(struct s3c_gpio_chip *chip,
+                                           int nr_chips)
+{
+        for (; nr_chips > 0; nr_chips--, chip++)
+                s3c_gpiolib_add(chip);
+}
diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h
index 0fbcd0effd8e..9a82b8874918 100644
--- a/arch/arm/plat-samsung/include/plat/clock.h
+++ b/arch/arm/plat-samsung/include/plat/clock.h
@@ -47,6 +47,9 @@ struct clk {
 
         struct clk_ops          *ops;
         int                 (*enable)(struct clk *, int enable);
+#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
+        struct dentry           *dent;  /* For visible tree hierarchy */
+#endif
 };
 
 /* other clocks which may be registered by board support */
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index e9e3b6e3ec74..b4d208b42957 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -104,6 +104,7 @@ extern struct platform_device s5pv310_device_i2s0;
 extern struct platform_device s5pv310_device_i2s1;
 extern struct platform_device s5pv310_device_i2s2;
 extern struct platform_device s5pv310_device_spdif;
+extern struct platform_device s5pv310_device_pd[];
 
 extern struct platform_device s5p6442_device_pcm0;
 extern struct platform_device s5p6442_device_pcm1;
@@ -115,6 +116,8 @@ extern struct platform_device s5p6440_device_pcm;
 extern struct platform_device s5p6440_device_iis;
 
 extern struct platform_device s5p6450_device_iis0;
+extern struct platform_device s5p6450_device_iis1;
+extern struct platform_device s5p6450_device_iis2;
 extern struct platform_device s5p6450_device_pcm0;
 
 extern struct platform_device s5pc100_device_ac97;
@@ -131,6 +134,11 @@ extern struct platform_device s5p_device_fimc0;
 extern struct platform_device s5p_device_fimc1;
 extern struct platform_device s5p_device_fimc2;
 
+extern struct platform_device s5p_device_mipi_csis0;
+extern struct platform_device s5p_device_mipi_csis1;
+
+extern struct platform_device s5pv310_device_sysmmu;
+
 /* s3c2440 specific devices */
 
 #ifdef CONFIG_CPU_S3C2440
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
index 0d2c5703f1ee..5603db0b79bc 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
@@ -244,7 +244,7 @@ extern int s3c_gpio_setpull_s3c2443(struct s3c_gpio_chip *chip,
  * This helper function reads the state of the pull-{up,down} resistor for the
  * given GPIO in the same case as s3c_gpio_setpull_upown.
 */
-extern s3c_gpio_pull_t s3c_gpio_getpull_s3c24xx(struct s3c_gpio_chip *chip,
+extern s3c_gpio_pull_t s3c_gpio_getpull_s3c2443(struct s3c_gpio_chip *chip,
                                                 unsigned int off);
 
 #endif /* __PLAT_GPIO_CFG_HELPERS_H */
diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h
index 13a22b8861ef..dac35d0a711d 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-core.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-core.h
@@ -118,6 +118,8 @@ extern void samsung_gpiolib_add_4bit_chips(struct s3c_gpio_chip *chip,
                                            int nr_chips);
 extern void samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip,
                                             int nr_chips);
+extern void samsung_gpiolib_add_2bit_chips(struct s3c_gpio_chip *chip,
+                                           int nr_chips);
 
 extern void samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip);
 extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip);
diff --git a/arch/arm/plat-samsung/include/plat/pd.h b/arch/arm/plat-samsung/include/plat/pd.h
new file mode 100644
index 000000000000..5f0ad85783db
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/pd.h
@@ -0,0 +1,30 @@
+/* linux/arch/arm/plat-samsung/include/plat/pd.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_PLAT_SAMSUNG_PD_H
+#define __ASM_PLAT_SAMSUNG_PD_H __FILE__
+
+struct samsung_pd_info {
+        int (*enable)(struct device *dev);
+        int (*disable)(struct device *dev);
+        void __iomem *base;
+};
+
+enum s5pv310_pd_block {
+        PD_MFC,
+        PD_G3D,
+        PD_LCD0,
+        PD_LCD1,
+        PD_TV,
+        PD_CAM,
+        PD_GPS
+};
+
+#endif /* __ASM_PLAT_SAMSUNG_PD_H */
diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h
index 245836d91931..d9025e377675 100644
--- a/arch/arm/plat-samsung/include/plat/pm.h
+++ b/arch/arm/plat-samsung/include/plat/pm.h
@@ -15,6 +15,8 @@
  * management
 */
 
+#include <linux/irq.h>
+
 #ifdef CONFIG_PM
 
 extern __init int s3c_pm_init(void);
@@ -100,7 +102,7 @@ extern void s3c_pm_do_restore(struct sleep_save *ptr, int count);
 extern void s3c_pm_do_restore_core(struct sleep_save *ptr, int count);
 
 #ifdef CONFIG_PM
-extern int s3c_irqext_wake(unsigned int irqno, unsigned int state);
+extern int s3c_irqext_wake(struct irq_data *data, unsigned int state);
 extern int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state);
 extern int s3c24xx_irq_resume(struct sys_device *dev);
 #else
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index 85853f8c4c5d..5a41a0b69eec 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -107,6 +107,8 @@ extern struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata;
 
 /* Helper function availablity */
 
+extern void s3c2416_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
+extern void s3c2416_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
 extern void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
 extern void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
 extern void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
@@ -122,6 +124,39 @@ extern void s5pv310_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
 extern void s5pv310_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
 extern void s5pv310_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
 
+/* S3C2416 SDHCI setup */
+
+#ifdef CONFIG_S3C2416_SETUP_SDHCI
+extern char *s3c2416_hsmmc_clksrcs[4];
+
+extern void s3c2416_setup_sdhci_cfg_card(struct platform_device *dev,
+                                           void __iomem *r,
+                                           struct mmc_ios *ios,
+                                           struct mmc_card *card);
+
+static inline void s3c2416_default_sdhci0(void)
+{
+#ifdef CONFIG_S3C_DEV_HSMMC
+        s3c_hsmmc0_def_platdata.clocks = s3c2416_hsmmc_clksrcs;
+        s3c_hsmmc0_def_platdata.cfg_gpio = s3c2416_setup_sdhci0_cfg_gpio;
+        s3c_hsmmc0_def_platdata.cfg_card = s3c2416_setup_sdhci_cfg_card;
+#endif /* CONFIG_S3C_DEV_HSMMC */
+}
+
+static inline void s3c2416_default_sdhci1(void)
+{
+#ifdef CONFIG_S3C_DEV_HSMMC1
+        s3c_hsmmc1_def_platdata.clocks = s3c2416_hsmmc_clksrcs;
+        s3c_hsmmc1_def_platdata.cfg_gpio = s3c2416_setup_sdhci1_cfg_gpio;
+        s3c_hsmmc1_def_platdata.cfg_card = s3c2416_setup_sdhci_cfg_card;
+#endif /* CONFIG_S3C_DEV_HSMMC1 */
+}
+
+#else
+static inline void s3c2416_default_sdhci0(void) { }
+static inline void s3c2416_default_sdhci1(void) { }
+
+#endif /* CONFIG_S3C2416_SETUP_SDHCI */
 /* S3C64XX SDHCI setup */
 
 #ifdef CONFIG_S3C64XX_SETUP_SDHCI
diff --git a/arch/arm/plat-samsung/irq-uart.c b/arch/arm/plat-samsung/irq-uart.c
index 4f8c102674ae..4e770355ccbc 100644
--- a/arch/arm/plat-samsung/irq-uart.c
+++ b/arch/arm/plat-samsung/irq-uart.c
@@ -28,9 +28,9 @@
  * are consecutive when looking up the interrupt in the demux routines.
  */
 
-static inline void __iomem *s3c_irq_uart_base(unsigned int irq)
+static inline void __iomem *s3c_irq_uart_base(struct irq_data *data)
 {
-        struct s3c_uart_irq *uirq = get_irq_chip_data(irq);
+        struct s3c_uart_irq *uirq = irq_data_get_irq_chip_data(data);
         return uirq->regs;
 }
 
@@ -39,10 +39,10 @@ static inline unsigned int s3c_irq_uart_bit(unsigned int irq)
         return irq & 3;
 }
 
-static void s3c_irq_uart_mask(unsigned int irq)
+static void s3c_irq_uart_mask(struct irq_data *data)
 {
-        void __iomem *regs = s3c_irq_uart_base(irq);
-        unsigned int bit = s3c_irq_uart_bit(irq);
+        void __iomem *regs = s3c_irq_uart_base(data);
+        unsigned int bit = s3c_irq_uart_bit(data->irq);
         u32 reg;
 
         reg = __raw_readl(regs + S3C64XX_UINTM);
@@ -50,10 +50,10 @@ static void s3c_irq_uart_mask(unsigned int irq)
         __raw_writel(reg, regs + S3C64XX_UINTM);
 }
 
-static void s3c_irq_uart_maskack(unsigned int irq)
+static void s3c_irq_uart_maskack(struct irq_data *data)
 {
-        void __iomem *regs = s3c_irq_uart_base(irq);
-        unsigned int bit = s3c_irq_uart_bit(irq);
+        void __iomem *regs = s3c_irq_uart_base(data);
+        unsigned int bit = s3c_irq_uart_bit(data->irq);
         u32 reg;
 
         reg = __raw_readl(regs + S3C64XX_UINTM);
@@ -62,10 +62,10 @@ static void s3c_irq_uart_maskack(unsigned int irq)
         __raw_writel(1 << bit, regs + S3C64XX_UINTP);
 }
 
-static void s3c_irq_uart_unmask(unsigned int irq)
+static void s3c_irq_uart_unmask(struct irq_data *data)
 {
-        void __iomem *regs = s3c_irq_uart_base(irq);
-        unsigned int bit = s3c_irq_uart_bit(irq);
+        void __iomem *regs = s3c_irq_uart_base(data);
+        unsigned int bit = s3c_irq_uart_bit(data->irq);
         u32 reg;
 
         reg = __raw_readl(regs + S3C64XX_UINTM);
@@ -73,17 +73,17 @@ static void s3c_irq_uart_unmask(unsigned int irq)
         __raw_writel(reg, regs + S3C64XX_UINTM);
 }
 
-static void s3c_irq_uart_ack(unsigned int irq)
+static void s3c_irq_uart_ack(struct irq_data *data)
 {
-        void __iomem *regs = s3c_irq_uart_base(irq);
-        unsigned int bit = s3c_irq_uart_bit(irq);
+        void __iomem *regs = s3c_irq_uart_base(data);
+        unsigned int bit = s3c_irq_uart_bit(data->irq);
 
         __raw_writel(1 << bit, regs + S3C64XX_UINTP);
 }
 
 static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
 {
-        struct s3c_uart_irq *uirq = desc->handler_data;
+        struct s3c_uart_irq *uirq = desc->irq_data.handler_data;
         u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP);
         int base = uirq->base_irq;
 
@@ -99,10 +99,10 @@ static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
 
 static struct irq_chip s3c_irq_uart = {
         .name           = "s3c-uart",
-        .mask           = s3c_irq_uart_mask,
-        .unmask         = s3c_irq_uart_unmask,
-        .mask_ack       = s3c_irq_uart_maskack,
-        .ack            = s3c_irq_uart_ack,
+        .irq_mask       = s3c_irq_uart_mask,
+        .irq_unmask     = s3c_irq_uart_unmask,
+        .irq_mask_ack   = s3c_irq_uart_maskack,
+        .irq_ack        = s3c_irq_uart_ack,
 };
 
 static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq)
@@ -124,7 +124,7 @@ static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq)
                 set_irq_flags(irq, IRQF_VALID);
         }
 
-        desc->handler_data = uirq;
+        desc->irq_data.handler_data = uirq;
         set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart);
 }
 
diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c
index 0270519fcabc..dd8692ae5c4c 100644
--- a/arch/arm/plat-samsung/irq-vic-timer.c
+++ b/arch/arm/plat-samsung/irq-vic-timer.c
@@ -24,43 +24,46 @@
 
 static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc)
 {
-        generic_handle_irq((int)desc->handler_data);
+        generic_handle_irq((int)desc->irq_data.handler_data);
 }
 
 /* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */
 
-static void s3c_irq_timer_mask(unsigned int irq)
+static void s3c_irq_timer_mask(struct irq_data *data)
 {
         u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
+        u32 mask = (u32)data->chip_data;
 
         reg &= 0x1f;  /* mask out pending interrupts */
-        reg &= ~(1 << (irq - IRQ_TIMER0));
+        reg &= ~mask;
         __raw_writel(reg, S3C64XX_TINT_CSTAT);
 }
 
-static void s3c_irq_timer_unmask(unsigned int irq)
+static void s3c_irq_timer_unmask(struct irq_data *data)
 {
         u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
+        u32 mask = (u32)data->chip_data;
 
         reg &= 0x1f;  /* mask out pending interrupts */
-        reg |= 1 << (irq - IRQ_TIMER0);
+        reg |= mask;
         __raw_writel(reg, S3C64XX_TINT_CSTAT);
 }
 
-static void s3c_irq_timer_ack(unsigned int irq)
+static void s3c_irq_timer_ack(struct irq_data *data)
 {
         u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
+        u32 mask = (u32)data->chip_data;
 
         reg &= 0x1f;
-        reg |= (1 << 5) << (irq - IRQ_TIMER0);
+        reg |= mask << 5;
         __raw_writel(reg, S3C64XX_TINT_CSTAT);
 }
 
 static struct irq_chip s3c_irq_timer = {
         .name           = "s3c-timer",
-        .mask           = s3c_irq_timer_mask,
-        .unmask         = s3c_irq_timer_unmask,
-        .ack            = s3c_irq_timer_ack,
+        .irq_mask       = s3c_irq_timer_mask,
+        .irq_unmask     = s3c_irq_timer_unmask,
+        .irq_ack        = s3c_irq_timer_ack,
 };
 
 /**
@@ -79,8 +82,9 @@ void __init s3c_init_vic_timer_irq(unsigned int parent_irq,
         set_irq_chained_handler(parent_irq, s3c_irq_demux_vic_timer);
 
         set_irq_chip(timer_irq, &s3c_irq_timer);
+        set_irq_chip_data(timer_irq, (void *)(1 << (timer_irq - IRQ_TIMER0)));
         set_irq_handler(timer_irq, handle_level_irq);
         set_irq_flags(timer_irq, IRQF_VALID);
 
-        desc->handler_data = (void *)timer_irq;
+        desc->irq_data.handler_data = (void *)timer_irq;
 }
diff --git a/arch/arm/plat-samsung/pd.c b/arch/arm/plat-samsung/pd.c
new file mode 100644
index 000000000000..efe1d564473e
--- /dev/null
+++ b/arch/arm/plat-samsung/pd.c
@@ -0,0 +1,95 @@
+/* linux/arch/arm/plat-samsung/pd.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Samsung Power domain support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/pm_runtime.h>
+
+#include <plat/pd.h>
+
+static int samsung_pd_probe(struct platform_device *pdev)
+{
+        struct samsung_pd_info *pdata = pdev->dev.platform_data;
+        struct device *dev = &pdev->dev;
+
+        if (!pdata) {
+                dev_err(dev, "no device data specified\n");
+                return -ENOENT;
+        }
+
+        pm_runtime_set_active(dev);
+        pm_runtime_enable(dev);
+
+        dev_info(dev, "power domain registered\n");
+        return 0;
+}
+
+static int __devexit samsung_pd_remove(struct platform_device *pdev)
+{
+        struct device *dev = &pdev->dev;
+
+        pm_runtime_disable(dev);
+        return 0;
+}
+
+static int samsung_pd_runtime_suspend(struct device *dev)
+{
+        struct samsung_pd_info *pdata = dev->platform_data;
+        int ret = 0;
+
+        if (pdata->disable)
+                ret = pdata->disable(dev);
+
+        dev_dbg(dev, "suspended\n");
+        return ret;
+}
+
+static int samsung_pd_runtime_resume(struct device *dev)
+{
+        struct samsung_pd_info *pdata = dev->platform_data;
+        int ret = 0;
+
+        if (pdata->enable)
+                ret = pdata->enable(dev);
+
+        dev_dbg(dev, "resumed\n");
+        return ret;
+}
+
+static const struct dev_pm_ops samsung_pd_pm_ops = {
+        .runtime_suspend        = samsung_pd_runtime_suspend,
+        .runtime_resume         = samsung_pd_runtime_resume,
+};
+
+static struct platform_driver samsung_pd_driver = {
+        .driver         = {
+                .name           = "samsung-pd",
+                .owner          = THIS_MODULE,
+                .pm             = &samsung_pd_pm_ops,
+        },
+        .probe          = samsung_pd_probe,
+        .remove         = __devexit_p(samsung_pd_remove),
+};
+
+static int __init samsung_pd_init(void)
+{
+        int ret;
+
+        ret = platform_driver_register(&samsung_pd_driver);
+        if (ret)
+                printk(KERN_ERR "%s: failed to add PD driver\n", __func__);
+
+        return ret;
+}
+arch_initcall(samsung_pd_init);
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
index 5bf3f2f09e74..02d531fb3f81 100644
--- a/arch/arm/plat-samsung/pm.c
+++ b/arch/arm/plat-samsung/pm.c
@@ -136,15 +136,15 @@ static void s3c_pm_restore_uarts(void) { }
 unsigned long s3c_irqwake_intmask       = 0xffffffffL;
 unsigned long s3c_irqwake_eintmask      = 0xffffffffL;
 
-int s3c_irqext_wake(unsigned int irqno, unsigned int state)
+int s3c_irqext_wake(struct irq_data *data, unsigned int state)
 {
-        unsigned long bit = 1L << IRQ_EINT_BIT(irqno);
+        unsigned long bit = 1L << IRQ_EINT_BIT(data->irq);
 
         if (!(s3c_irqwake_eintallow & bit))
                 return -ENOENT;
 
         printk(KERN_INFO "wake %s for irq %d\n",
-               state ? "enabled" : "disabled", irqno);
+               state ? "enabled" : "disabled", data->irq);
 
         if (!state)
                 s3c_irqwake_eintmask |= bit;
diff --git a/arch/arm/plat-spear/shirq.c b/arch/arm/plat-spear/shirq.c
index 2172d6946aea..78189035e7f1 100644
--- a/arch/arm/plat-spear/shirq.c
+++ b/arch/arm/plat-spear/shirq.c
@@ -20,10 +20,10 @@
 struct spear_shirq *shirq;
 static DEFINE_SPINLOCK(lock);
 
-static void shirq_irq_mask(unsigned irq)
+static void shirq_irq_mask(struct irq_data *d)
 {
-        struct spear_shirq *shirq = get_irq_chip_data(irq);
-        u32 val, id = irq - shirq->dev_config[0].virq;
+        struct spear_shirq *shirq = irq_data_get_irq_chip_data(d);
+        u32 val, id = d->irq - shirq->dev_config[0].virq;
         unsigned long flags;
 
         if ((shirq->regs.enb_reg == -1) || shirq->dev_config[id].enb_mask == -1)
@@ -39,10 +39,10 @@ static void shirq_irq_mask(unsigned irq)
         spin_unlock_irqrestore(&lock, flags);
 }
 
-static void shirq_irq_unmask(unsigned irq)
+static void shirq_irq_unmask(struct irq_data *d)
 {
-        struct spear_shirq *shirq = get_irq_chip_data(irq);
-        u32 val, id = irq - shirq->dev_config[0].virq;
+        struct spear_shirq *shirq = irq_data_get_irq_chip_data(d);
+        u32 val, id = d->irq - shirq->dev_config[0].virq;
         unsigned long flags;
 
         if ((shirq->regs.enb_reg == -1) || shirq->dev_config[id].enb_mask == -1)
@@ -60,9 +60,9 @@ static void shirq_irq_unmask(unsigned irq)
 
 static struct irq_chip shirq_chip = {
         .name           = "spear_shirq",
-        .ack            = shirq_irq_mask,
-        .mask           = shirq_irq_mask,
-        .unmask         = shirq_irq_unmask,
+        .irq_ack        = shirq_irq_mask,
+        .irq_mask       = shirq_irq_mask,
+        .irq_unmask     = shirq_irq_unmask,
 };
 
 static void shirq_handler(unsigned irq, struct irq_desc *desc)
@@ -70,7 +70,7 @@ static void shirq_handler(unsigned irq, struct irq_desc *desc)
         u32 i, val, mask;
         struct spear_shirq *shirq = get_irq_data(irq);
 
-        desc->chip->ack(irq);
+        desc->irq_data.chip->irq_ack(&desc->irq_data);
         while ((val = readl(shirq->regs.base + shirq->regs.status_reg) &
                                 shirq->regs.status_reg_mask)) {
                 for (i = 0; (i < shirq->dev_count) && val; i++) {
@@ -92,7 +92,7 @@ static void shirq_handler(unsigned irq, struct irq_desc *desc)
                         writel(mask, shirq->regs.base + shirq->regs.clear_reg);
                 }
         }
-        desc->chip->unmask(irq);
+        desc->irq_data.chip->irq_unmask(&desc->irq_data);
 }
 
 int spear_shirq_register(struct spear_shirq *shirq)
diff --git a/arch/arm/plat-stmp3xxx/irq.c b/arch/arm/plat-stmp3xxx/irq.c
index 20de4e0401ef..aaa168683d4e 100644
--- a/arch/arm/plat-stmp3xxx/irq.c
+++ b/arch/arm/plat-stmp3xxx/irq.c
@@ -34,7 +34,7 @@ void __init stmp3xxx_init_irq(struct irq_chip *chip)
 
         /* Disable all interrupts initially */
         for (i = 0; i < NR_REAL_IRQS; i++) {
-                chip->mask(i);
+                chip->irq_mask(irq_get_irq_data(i));
                 set_irq_chip(i, chip);
                 set_irq_handler(i, handle_level_irq);
                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
diff --git a/arch/arm/plat-stmp3xxx/pinmux.c b/arch/arm/plat-stmp3xxx/pinmux.c
index 6d6b1a468eda..66d5bac3ace2 100644
--- a/arch/arm/plat-stmp3xxx/pinmux.c
+++ b/arch/arm/plat-stmp3xxx/pinmux.c
@@ -351,27 +351,27 @@ void stmp3xxx_release_pin_group(struct pin_group *pin_group, const char *label)
 }
 EXPORT_SYMBOL(stmp3xxx_release_pin_group);
 
-static int stmp3xxx_irq_to_gpio(int irq,
+static int stmp3xxx_irq_data_to_gpio(struct irq_data *d,
         struct stmp3xxx_pinmux_bank **bank, unsigned *gpio)
 {
         struct stmp3xxx_pinmux_bank *pm;
 
         for (pm = pinmux_banks; pm < pinmux_banks + NR_BANKS; pm++)
-                if (pm->virq <= irq && irq < pm->virq + 32) {
+                if (pm->virq <= d->irq && d->irq < pm->virq + 32) {
                         *bank = pm;
-                        *gpio = irq - pm->virq;
+                        *gpio = d->irq - pm->virq;
                         return 0;
                 }
         return -ENOENT;
 }
 
-static int stmp3xxx_set_irqtype(unsigned irq, unsigned type)
+static int stmp3xxx_set_irqtype(struct irq_data *d, unsigned type)
 {
         struct stmp3xxx_pinmux_bank *pm;
         unsigned gpio;
         int l, p;
 
-        stmp3xxx_irq_to_gpio(irq, &pm, &gpio);
+        stmp3xxx_irq_data_to_gpio(d, &pm, &gpio);
         switch (type) {
         case IRQ_TYPE_EDGE_RISING:
                 l = 0; p = 1; break;
@@ -398,33 +398,33 @@ static int stmp3xxx_set_irqtype(unsigned irq, unsigned type)
         return 0;
 }
 
-static void stmp3xxx_pin_ack_irq(unsigned irq)
+static void stmp3xxx_pin_ack_irq(struct irq_data *d)
 {
         u32 stat;
         struct stmp3xxx_pinmux_bank *pm;
         unsigned gpio;
 
-        stmp3xxx_irq_to_gpio(irq, &pm, &gpio);
+        stmp3xxx_irq_data_to_gpio(d, &pm, &gpio);
         stat = __raw_readl(pm->irqstat) & (1 << gpio);
         stmp3xxx_clearl(stat, pm->irqstat);
 }
 
-static void stmp3xxx_pin_mask_irq(unsigned irq)
+static void stmp3xxx_pin_mask_irq(struct irq_data *d)
 {
         struct stmp3xxx_pinmux_bank *pm;
         unsigned gpio;
 
-        stmp3xxx_irq_to_gpio(irq, &pm, &gpio);
+        stmp3xxx_irq_data_to_gpio(d, &pm, &gpio);
         stmp3xxx_clearl(1 << gpio, pm->irqen);
         stmp3xxx_clearl(1 << gpio, pm->pin2irq);
 }
 
-static void stmp3xxx_pin_unmask_irq(unsigned irq)
+static void stmp3xxx_pin_unmask_irq(struct irq_data *d)
 {
         struct stmp3xxx_pinmux_bank *pm;
         unsigned gpio;
 
-        stmp3xxx_irq_to_gpio(irq, &pm, &gpio);
+        stmp3xxx_irq_data_to_gpio(d, &pm, &gpio);
         stmp3xxx_setl(1 << gpio, pm->irqen);
         stmp3xxx_setl(1 << gpio, pm->pin2irq);
 }
@@ -503,10 +503,10 @@ static void stmp3xxx_gpio_irq(u32 irq, struct irq_desc *desc)
 }
 
 static struct irq_chip gpio_irq_chip = {
-        .ack    = stmp3xxx_pin_ack_irq,
-        .mask   = stmp3xxx_pin_mask_irq,
-        .unmask = stmp3xxx_pin_unmask_irq,
-        .set_type = stmp3xxx_set_irqtype,
+        .irq_ack        = stmp3xxx_pin_ack_irq,
+        .irq_mask       = stmp3xxx_pin_mask_irq,
+        .irq_unmask     = stmp3xxx_pin_unmask_irq,
+        .irq_set_type   = stmp3xxx_set_irqtype,
 };
 
 int __init stmp3xxx_pinmux_init(int virtual_irq_start)
@@ -533,7 +533,7 @@ int __init stmp3xxx_pinmux_init(int virtual_irq_start)
                 pm->virq = virtual_irq_start + b * 32;
 
                 for (virq = pm->virq; virq < pm->virq; virq++) {
-                        gpio_irq_chip.mask(virq);
+                        gpio_irq_chip.irq_mask(irq_get_irq_data(virq));
                         set_irq_chip(virq, &gpio_irq_chip);
                         set_irq_handler(virq, handle_level_irq);
                         set_irq_flags(virq, IRQF_VALID);