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authorLinus Torvalds <torvalds@linux-foundation.org>2014-01-23 21:45:38 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2014-01-23 21:45:38 -0500
commit9b6d351a75dae25430383b29a3764ae7921f6c47 (patch)
tree605b1ec9f90138553cb7efedf9dbb3df93bef3a8 /arch/arm/mach-integrator
parentdfd10e7ae60c6c1b24b5d601744b4fd1ecab2f31 (diff)
parent310c85476d5047f5ace4d1c527e1bbbc0c7ad672 (diff)
Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC DT updates from Olof Johansson: "DT and DT-conversion-related changes for various ARM platforms. Most of these are to enable various devices on various boards, etc, and not necessarily worth enumerating. New boards and systems continue to come in as new devicetree files that don't require corresponding C changes any more, which is indicating that the system is starting to work fairly well. A few things worth pointing out: * ST Ericsson ux500 platforms have made the major push to move over to fully support the platform with DT * Renesas platforms continue their conversion over from legacy platform devices to DT-based for hardware description" * tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (327 commits) ARM: dts: SiRF: add pin group for USP0 with only RX or TX frame sync ARM: dts: SiRF: add lost usp1_uart_nostreamctrl pin group for atlas6 ARM: dts: sirf: add lost minigpsrtc device node ARM: dts: sirf: add clock, frequence-voltage table for CPU0 ARM: dts: sirf: add lost bus_width, clock and status for sdhci ARM: dts: sirf: add lost clocks for cphifbg ARM: dts: socfpga: add pl330 clock ARM: dts: socfpga: update L2 tag and data latency arm: sun7i: cubietruck: Enable the i2c controllers ARM: dts: add support for EXYNOS4412 based TINY4412 board ARM: dts: Add initial support for Arndale Octa board ARM: bcm2835: add USB controller to device tree ARM: dts: MSM8974: Add MMIO architected timer node ARM: dts: MSM8974: Add restart node ARM: dts: sun7i: external clock outputs ARM: dts: sun7i: Change 32768 Hz oscillator node name to clk@N style ARM: dts: sun7i: Add pin muxing options for clock outputs ARM: dts: sun7i: Add rtp controller node ARM: dts: sun5i: Add rtp controller node ARM: dts: sun4i: Add rtp controller node ...
Diffstat (limited to 'arch/arm/mach-integrator')
-rw-r--r--arch/arm/mach-integrator/integrator_ap.c60
-rw-r--r--arch/arm/mach-integrator/integrator_cp.c14
2 files changed, 31 insertions, 43 deletions
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 473e21b87364..17c0fe627435 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -63,6 +63,9 @@
63 63
64/* Base address to the AP system controller */ 64/* Base address to the AP system controller */
65void __iomem *ap_syscon_base; 65void __iomem *ap_syscon_base;
66/* Base address to the external bus interface */
67static void __iomem *ebi_base;
68
66 69
67/* 70/*
68 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx 71 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
@@ -72,15 +75,11 @@ void __iomem *ap_syscon_base;
72 * just for now). 75 * just for now).
73 */ 76 */
74#define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE) 77#define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE)
75#define VA_EBI_BASE __io_address(INTEGRATOR_EBI_BASE)
76#define VA_CMIC_BASE __io_address(INTEGRATOR_HDR_IC)
77 78
78/* 79/*
79 * Logical Physical 80 * Logical Physical
80 * ef000000 Cache flush 81 * ef000000 Cache flush
81 * f1000000 10000000 Core module registers
82 * f1100000 11000000 System controller registers 82 * f1100000 11000000 System controller registers
83 * f1200000 12000000 EBI registers
84 * f1300000 13000000 Counter/Timer 83 * f1300000 13000000 Counter/Timer
85 * f1400000 14000000 Interrupt controller 84 * f1400000 14000000 Interrupt controller
86 * f1600000 16000000 UART 0 85 * f1600000 16000000 UART 0
@@ -91,16 +90,6 @@ void __iomem *ap_syscon_base;
91 90
92static struct map_desc ap_io_desc[] __initdata __maybe_unused = { 91static struct map_desc ap_io_desc[] __initdata __maybe_unused = {
93 { 92 {
94 .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
95 .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
96 .length = SZ_4K,
97 .type = MT_DEVICE
98 }, {
99 .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
100 .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
101 .length = SZ_4K,
102 .type = MT_DEVICE
103 }, {
104 .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE), 93 .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
105 .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE), 94 .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
106 .length = SZ_4K, 95 .length = SZ_4K,
@@ -174,9 +163,6 @@ device_initcall(irq_syscore_init);
174/* 163/*
175 * Flash handling. 164 * Flash handling.
176 */ 165 */
177#define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
178#define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
179
180static int ap_flash_init(struct platform_device *dev) 166static int ap_flash_init(struct platform_device *dev)
181{ 167{
182 u32 tmp; 168 u32 tmp;
@@ -184,13 +170,15 @@ static int ap_flash_init(struct platform_device *dev)
184 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, 170 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
185 ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET); 171 ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
186 172
187 tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE; 173 tmp = readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) |
188 writel(tmp, EBI_CSR1); 174 INTEGRATOR_EBI_WRITE_ENABLE;
175 writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
189 176
190 if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) { 177 if (!(readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET)
191 writel(0xa05f, EBI_LOCK); 178 & INTEGRATOR_EBI_WRITE_ENABLE)) {
192 writel(tmp, EBI_CSR1); 179 writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
193 writel(0, EBI_LOCK); 180 writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
181 writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
194 } 182 }
195 return 0; 183 return 0;
196} 184}
@@ -202,13 +190,15 @@ static void ap_flash_exit(struct platform_device *dev)
202 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, 190 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
203 ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET); 191 ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
204 192
205 tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE; 193 tmp = readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) &
206 writel(tmp, EBI_CSR1); 194 ~INTEGRATOR_EBI_WRITE_ENABLE;
195 writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
207 196
208 if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) { 197 if (readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) &
209 writel(0xa05f, EBI_LOCK); 198 INTEGRATOR_EBI_WRITE_ENABLE) {
210 writel(tmp, EBI_CSR1); 199 writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
211 writel(0, EBI_LOCK); 200 writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
201 writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
212 } 202 }
213} 203}
214 204
@@ -475,11 +465,17 @@ static const struct of_device_id ap_syscon_match[] = {
475 { }, 465 { },
476}; 466};
477 467
468static const struct of_device_id ebi_match[] = {
469 { .compatible = "arm,external-bus-interface"},
470 { },
471};
472
478static void __init ap_init_of(void) 473static void __init ap_init_of(void)
479{ 474{
480 unsigned long sc_dec; 475 unsigned long sc_dec;
481 struct device_node *root; 476 struct device_node *root;
482 struct device_node *syscon; 477 struct device_node *syscon;
478 struct device_node *ebi;
483 struct device *parent; 479 struct device *parent;
484 struct soc_device *soc_dev; 480 struct soc_device *soc_dev;
485 struct soc_device_attribute *soc_dev_attr; 481 struct soc_device_attribute *soc_dev_attr;
@@ -495,10 +491,16 @@ static void __init ap_init_of(void)
495 syscon = of_find_matching_node(root, ap_syscon_match); 491 syscon = of_find_matching_node(root, ap_syscon_match);
496 if (!syscon) 492 if (!syscon)
497 return; 493 return;
494 ebi = of_find_matching_node(root, ebi_match);
495 if (!ebi)
496 return;
498 497
499 ap_syscon_base = of_iomap(syscon, 0); 498 ap_syscon_base = of_iomap(syscon, 0);
500 if (!ap_syscon_base) 499 if (!ap_syscon_base)
501 return; 500 return;
501 ebi_base = of_iomap(ebi, 0);
502 if (!ebi_base)
503 return;
502 504
503 ap_sc_id = readl(ap_syscon_base); 505 ap_sc_id = readl(ap_syscon_base);
504 506
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 4fc0a195de01..5e84149d1790 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -64,9 +64,6 @@ static void __iomem *intcp_con_base;
64 64
65/* 65/*
66 * Logical Physical 66 * Logical Physical
67 * f1000000 10000000 Core module registers
68 * f1100000 11000000 System controller registers
69 * f1200000 12000000 EBI registers
70 * f1300000 13000000 Counter/Timer 67 * f1300000 13000000 Counter/Timer
71 * f1400000 14000000 Interrupt controller 68 * f1400000 14000000 Interrupt controller
72 * f1600000 16000000 UART 0 69 * f1600000 16000000 UART 0
@@ -74,21 +71,10 @@ static void __iomem *intcp_con_base;
74 * f1a00000 1a000000 Debug LEDs 71 * f1a00000 1a000000 Debug LEDs
75 * fc900000 c9000000 GPIO 72 * fc900000 c9000000 GPIO
76 * fca00000 ca000000 SIC 73 * fca00000 ca000000 SIC
77 * fcb00000 cb000000 CP system control
78 */ 74 */
79 75
80static struct map_desc intcp_io_desc[] __initdata __maybe_unused = { 76static struct map_desc intcp_io_desc[] __initdata __maybe_unused = {
81 { 77 {
82 .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
83 .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
84 .length = SZ_4K,
85 .type = MT_DEVICE
86 }, {
87 .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
88 .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
89 .length = SZ_4K,
90 .type = MT_DEVICE
91 }, {
92 .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE), 78 .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
93 .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE), 79 .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
94 .length = SZ_4K, 80 .length = SZ_4K,