238 files changed, 12679 insertions, 4211 deletions

diff --git a/Documentation/devicetree/bindings/arm/arm-boards b/Documentation/devicetree/bindings/arm/arm-boards
index 5fac246a9530..3509707f9320 100644
--- a/Documentation/devicetree/bindings/arm/arm-boards
+++ b/Documentation/devicetree/bindings/arm/arm-boards
@@ -14,6 +14,9 @@ Required nodes:
 - core-module: the root node to the Integrator platforms must have
   a core-module with regs and the compatible string
   "arm,core-module-integrator"
+- external-bus-interface: the root node to the Integrator platforms
+  must have an external bus interface with regs and the
+  compatible-string "arm,external-bus-interface"
 
   Required properties for the core module:
   - regs: the location and size of the core module registers, one
@@ -48,6 +51,11 @@ Required nodes:
                 reg = <0x10000000 0x200>;
         };
 
+        ebi@12000000 {
+                compatible = "arm,external-bus-interface";
+                reg = <0x12000000 0x100>;
+        };
+
         syscon {
                 compatible = "arm,integrator-ap-syscon";
                 reg = <0x11000000 0x100>;
diff --git a/Documentation/devicetree/bindings/arm/atmel-aic.txt b/Documentation/devicetree/bindings/arm/atmel-aic.txt
index ad031211b5b8..2742e9cfd6b1 100644
--- a/Documentation/devicetree/bindings/arm/atmel-aic.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-aic.txt
@@ -2,6 +2,7 @@
 
 Required properties:
 - compatible: Should be "atmel,<chip>-aic"
+  <chip> can be "at91rm9200" or "sama5d3"
 - interrupt-controller: Identifies the node as an interrupt controller.
 - interrupt-parent: For single AIC system, it is an empty property.
 - #interrupt-cells: The number of cells to define the interrupts. It should be 3.
diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
index 78530e621a1e..16f60b41c147 100644
--- a/Documentation/devicetree/bindings/arm/atmel-at91.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
@@ -58,7 +58,8 @@ Example:
         };
 
 RAMC SDRAM/DDR Controller required properties:
-- compatible: Should be "atmel,at91sam9260-sdramc",
+- compatible: Should be "atmel,at91rm9200-sdramc",
+                        "atmel,at91sam9260-sdramc",
                         "atmel,at91sam9g45-ddramc",
 - reg: Should contain registers location and length
   For at91sam9263 and at91sam9g45 you must specify 2 entries.
diff --git a/Documentation/devicetree/bindings/arm/moxart.txt b/Documentation/devicetree/bindings/arm/moxart.txt
new file mode 100644
index 000000000000..11087edb0658
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/moxart.txt
@@ -0,0 +1,12 @@
+MOXA ART device tree bindings
+
+Boards with the MOXA ART SoC shall have the following properties:
+
+Required root node property:
+
+compatible = "moxa,moxart";
+
+Boards:
+
+- UC-7112-LX: embedded computer
+  compatible = "moxa,moxart-uc-7112-lx", "moxa,moxart"
diff --git a/Documentation/devicetree/bindings/arm/samsung/sysreg.txt b/Documentation/devicetree/bindings/arm/samsung/sysreg.txt
index 5039c0a12f55..0ab3251a6ec2 100644
--- a/Documentation/devicetree/bindings/arm/samsung/sysreg.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/sysreg.txt
@@ -1,7 +1,12 @@
 SAMSUNG S5P/Exynos SoC series System Registers (SYSREG)
 
 Properties:
- - name : should be 'sysreg';
  - compatible : should contain "samsung,<chip name>-sysreg", "syscon";
    For Exynos4 SoC series it should be "samsung,exynos4-sysreg", "syscon";
  - reg : offset and length of the register set.
+
+Example:
+        syscon@10010000 {
+                compatible = "samsung,exynos4-sysreg", "syscon";
+                reg = <0x10010000 0x400>;
+        };
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
new file mode 100644
index 000000000000..952e373178d2
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
@@ -0,0 +1,28 @@
+* Renesas CPG DIV6 Clock
+
+The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
+Generator (CPG). They clock input is divided by a configurable factor from 1
+to 64.
+
+Required Properties:
+
+  - compatible: Must be one of the following
+    - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks
+    - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2) DIV6 clocks
+    - "renesas,cpg-div6-clock" for generic DIV6 clocks
+  - reg: Base address and length of the memory resource used by the DIV6 clock
+  - clocks: Reference to the parent clock
+  - #clock-cells: Must be 0
+  - clock-output-names: The name of the clock as a free-form string
+
+
+Example
+-------
+
+        sd2_clk: sd2_clk@e6150078 {
+                compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
+                reg = <0 0xe6150078 0 4>;
+                clocks = <&pll1_div2_clk>;
+                #clock-cells = <0>;
+                clock-output-names = "sd2";
+        };
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
new file mode 100644
index 000000000000..a6a352c2771e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
@@ -0,0 +1,51 @@
+* Renesas CPG Module Stop (MSTP) Clocks
+
+The CPG can gate SoC device clocks. The gates are organized in groups of up to
+32 gates.
+
+This device tree binding describes a single 32 gate clocks group per node.
+Clocks are referenced by user nodes by the MSTP node phandle and the clock
+index in the group, from 0 to 31.
+
+Required Properties:
+
+  - compatible: Must be one of the following
+    - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
+    - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks
+    - "renesas,cpg-mstp-clock" for generic MSTP gate clocks
+  - reg: Base address and length of the I/O mapped registers used by the MSTP
+    clocks. The first register is the clock control register and is mandatory.
+    The second register is the clock status register and is optional when not
+    implemented in hardware.
+  - clocks: Reference to the parent clocks, one per output clock. The parents
+    must appear in the same order as the output clocks.
+  - #clock-cells: Must be 1
+  - clock-output-names: The name of the clocks as free-form strings
+  - renesas,indices: Indices of the gate clocks into the group (0 to 31)
+
+The clocks, clock-output-names and renesas,indices properties contain one
+entry per gate clock. The MSTP groups are sparsely populated. Unimplemented
+gate clocks must not be declared.
+
+
+Example
+-------
+
+        #include <dt-bindings/clock/r8a7790-clock.h>
+
+        mstp3_clks: mstp3_clks@e615013c {
+                compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
+                reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
+                clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>,
+                         <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>,
+                         <&mmc0_clk>;
+                #clock-cells = <1>;
+                clock-output-names =
+                        "tpu0", "mmcif1", "sdhi3", "sdhi2",
+                         "sdhi1", "sdhi0", "mmcif0";
+                renesas,clock-indices = <
+                        R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
+                        R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0
+                        R8A7790_CLK_MMCIF0
+                >;
+        };
diff --git a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
new file mode 100644
index 000000000000..7b41c2fe54db
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
@@ -0,0 +1,32 @@
+* Renesas R-Car Gen2 Clock Pulse Generator (CPG)
+
+The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs
+and several fixed ratio dividers.
+
+Required Properties:
+
+  - compatible: Must be one of
+    - "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG
+    - "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG
+    - "renesas,rcar-gen2-cpg-clocks" for the generic R-Car Gen2 CPG
+
+  - reg: Base address and length of the memory resource used by the CPG
+
+  - clocks: Reference to the parent clock
+  - #clock-cells: Must be 1
+  - clock-output-names: The names of the clocks. Supported clocks are "main",
+    "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1" and "z"
+
+
+Example
+-------
+
+        cpg_clocks: cpg_clocks@e6150000 {
+                compatible = "renesas,r8a7790-cpg-clocks",
+                             "renesas,rcar-gen2-cpg-clocks";
+                reg = <0 0xe6150000 0 0x1000>;
+                clocks = <&extal_clk>;
+                #clock-cells = <1>;
+                clock-output-names = "main", "pll0, "pll1", "pll3",
+                                     "lb", "qspi", "sdh", "sd0", "sd1", "z";
+        };
diff --git a/Documentation/devicetree/bindings/dma/ste-dma40.txt b/Documentation/devicetree/bindings/dma/ste-dma40.txt
index a8c21c256baa..1f5729f10621 100644
--- a/Documentation/devicetree/bindings/dma/ste-dma40.txt
+++ b/Documentation/devicetree/bindings/dma/ste-dma40.txt
@@ -50,6 +50,9 @@ Each dmas request consists of 4 cells:
         0x00000008: Use fixed channel:
                 Use automatic channel selection when unset
                 Use DMA request line number when set
+        0x00000010: Set channel as high priority:
+                Normal priority when unset
+                High priority when set
 
 Example:
 
diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
index c67b975c8906..532b1d440abc 100644
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -16,6 +16,8 @@ Required Properties:
           specific extensions.
         - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
           specific extensions.
+        - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
+          specific extensions.
 
 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
   unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
index b5a86d20ee36..167d5dab9f64 100644
--- a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
+++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
@@ -31,38 +31,58 @@ Required properties:
         7: ..
         i: Local Timer Interrupt n
 
-Example 1: In this example, the system uses only the first global timer
-           interrupt generated by MCT and the remaining three global timer
-           interrupts are unused. Two local timer interrupts have been
-           specified.
+  For MCT block that uses a per-processor interrupt for local timers, such
+  as ones compatible with "samsung,exynos4412-mct", only one local timer
+  interrupt might be specified, meaning that all local timers use the same
+  per processor interrupt.
+
+Example 1: In this example, the IP contains two local timers, using separate
+           interrupts, so two local timer interrupts have been specified,
+           in addition to four global timer interrupts.
 
         mct@10050000 {
                 compatible = "samsung,exynos4210-mct";
                 reg = <0x10050000 0x800>;
-                interrupts = <0 57 0>, <0 0 0>, <0 0 0>, <0 0 0>,
+                interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>,
                              <0 42 0>, <0 48 0>;
         };
 
-Example 2: In this example, the MCT global and local timer interrupts are
-           connected to two separate interrupt controllers. Hence, an
-           interrupt-map is created to map the interrupts to the respective
-           interrupt controllers.
+Example 2: In this example, the timer interrupts are connected to two separate
+           interrupt controllers. Hence, an interrupt-map is created to map
+           the interrupts to the respective interrupt controllers.
 
         mct@101C0000 {
                 compatible = "samsung,exynos4210-mct";
                 reg = <0x101C0000 0x800>;
-                interrupt-controller;
-                #interrups-cells = <2>;
                 interrupt-parent = <&mct_map>;
-                interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
-                             <4 0>, <5 0>;
+                interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
 
                 mct_map: mct-map {
-                        #interrupt-cells = <2>;
+                        #interrupt-cells = <1>;
                         #address-cells = <0>;
                         #size-cells = <0>;
-                        interrupt-map = <0x0 0 &combiner 23 3>,
-                                        <0x4 0 &gic 0 120 0>,
-                                        <0x5 0 &gic 0 121 0>;
+                        interrupt-map = <0 &gic 0 57 0>,
+                                        <1 &gic 0 69 0>,
+                                        <2 &combiner 12 6>,
+                                        <3 &combiner 12 7>,
+                                        <4 &gic 0 42 0>,
+                                        <5 &gic 0 48 0>;
                 };
         };
+
+Example 3: In this example, the IP contains four local timers, but using
+           a per-processor interrupt to handle them. Either all the local
+           timer interrupts can be specified, with the same interrupt specifier
+           value or just the first one.
+
+        mct@10050000 {
+                compatible = "samsung,exynos4412-mct";
+                reg = <0x10050000 0x800>;
+
+                /* Both ways are possible in this case. Either: */
+                interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>,
+                             <0 42 0>;
+                /* or: */
+                interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>,
+                             <0 42 0>, <0 42 0>, <0 42 0>, <0 42 0>;
+        };
diff --git a/Documentation/devicetree/bindings/usb/keystone-phy.txt b/Documentation/devicetree/bindings/usb/keystone-phy.txt
new file mode 100644
index 000000000000..f37b3a86341d
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/keystone-phy.txt
@@ -0,0 +1,20 @@
+TI Keystone USB PHY
+
+Required properties:
+ - compatible: should be "ti,keystone-usbphy".
+ - #address-cells, #size-cells : should be '1' if the device has sub-nodes
+   with 'reg' property.
+ - reg : Address and length of the usb phy control register set.
+
+The main purpose of this PHY driver is to enable the USB PHY reference clock
+gate on the Keystone SOC for both the USB2 and USB3 PHY. Otherwise it is just
+an NOP PHY driver.  Hence this node is referenced as both the usb2 and usb3
+phy node in the USB Glue layer driver node.
+
+usb_phy: usb_phy@2620738 {
+        compatible = "ti,keystone-usbphy";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        reg = <0x2620738 32>;
+        status = "disabled";
+};
diff --git a/Documentation/devicetree/bindings/usb/keystone-usb.txt b/Documentation/devicetree/bindings/usb/keystone-usb.txt
new file mode 100644
index 000000000000..60527d335b58
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/keystone-usb.txt
@@ -0,0 +1,42 @@
+TI Keystone Soc USB Controller
+
+DWC3 GLUE
+
+Required properties:
+ - compatible: should be "ti,keystone-dwc3".
+ - #address-cells, #size-cells : should be '1' if the device has sub-nodes
+   with 'reg' property.
+ - reg : Address and length of the register set for the USB subsystem on
+   the SOC.
+ - interrupts : The irq number of this device that is used to interrupt the
+   MPU.
+ - ranges: allows valid 1:1 translation between child's address space and
+   parent's address space.
+ - clocks: Clock IDs array as required by the controller.
+ - clock-names: names of clocks correseponding to IDs in the clock property.
+
+Sub-nodes:
+The dwc3 core should be added as subnode to Keystone DWC3 glue.
+- dwc3 :
+   The binding details of dwc3 can be found in:
+   Documentation/devicetree/bindings/usb/dwc3.txt
+
+Example:
+        usb: usb@2680000 {
+                compatible = "ti,keystone-dwc3";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0x2680000 0x10000>;
+                clocks = <&clkusb>;
+                clock-names = "usb";
+                interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
+                ranges;
+                status = "disabled";
+
+                dwc3@2690000 {
+                        compatible = "synopsys,dwc3";
+                        reg = <0x2690000 0x70000>;
+                        interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
+                        usb-phy = <&usb_phy>, <&usb_phy>;
+                };
+        };
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 91896a3f703a..faa38bcc7001 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -31,6 +31,7 @@ dtb-$(CONFIG_ARCH_AT91) += pm9g45.dtb
 dtb-$(CONFIG_ARCH_AT91) += at91sam9n12ek.dtb
 # sam9x5
 dtb-$(CONFIG_ARCH_AT91) += at91-ariag25.dtb
+dtb-$(CONFIG_ARCH_AT91) += at91-cosino_mega2560.dtb
 dtb-$(CONFIG_ARCH_AT91) += at91sam9g15ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += at91sam9g25ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb
@@ -41,6 +42,8 @@ dtb-$(CONFIG_ARCH_AT91)	+= sama5d31ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += sama5d33ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb
+dtb-$(CONFIG_ARCH_AT91) += sama5d36ek.dtb
+
 dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
 dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm11351-brt.dtb \
@@ -64,10 +67,12 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
         exynos4412-odroidx.dtb \
         exynos4412-origen.dtb \
         exynos4412-smdk4412.dtb \
+        exynos4412-tiny4412.dtb \
         exynos4412-trats2.dtb \
         exynos5250-arndale.dtb \
         exynos5250-smdk5250.dtb \
         exynos5250-snow.dtb \
+        exynos5420-arndale-octa.dtb \
         exynos5420-smdk5420.dtb \
         exynos5440-sd5v1.dtb \
         exynos5440-ssdk5440.dtb
@@ -91,11 +96,13 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
         kirkwood-iomega_ix2_200.dtb \
         kirkwood-is2.dtb \
         kirkwood-km_kirkwood.dtb \
+        kirkwood-laplug.dtb \
         kirkwood-lschlv2.dtb \
         kirkwood-lsxhl.dtb \
         kirkwood-mplcec4.dtb \
         kirkwood-mv88f6281gtw-ge.dtb \
         kirkwood-netgear_readynas_duo_v2.dtb \
+        kirkwood-netgear_readynas_nv+_v2.dtb \
         kirkwood-ns2.dtb \
         kirkwood-ns2lite.dtb \
         kirkwood-ns2max.dtb \
@@ -110,6 +117,7 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
         kirkwood-ts219-6281.dtb \
         kirkwood-ts219-6282.dtb
 dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
+dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb
 dtb-$(CONFIG_ARCH_MSM) += qcom-msm8660-surf.dtb \
         qcom-msm8960-cdp.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
@@ -120,6 +128,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
         armada-xp-axpwifiap.dtb \
         armada-xp-db.dtb \
         armada-xp-gp.dtb \
+        armada-xp-netgear-rn2120.dtb \
         armada-xp-matrix.dtb \
         armada-xp-openblocks-ax3-4.dtb
 dtb-$(CONFIG_ARCH_MXC) += \
@@ -261,6 +270,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
         sun4i-a10-hackberry.dtb \
         sun5i-a10s-olinuxino-micro.dtb \
         sun5i-a13-olinuxino.dtb \
+        sun5i-a13-olinuxino-micro.dtb \
         sun6i-a31-colombus.dtb \
         sun7i-a20-cubieboard2.dtb \
         sun7i-a20-cubietruck.dtb \
diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts
index 3a1de9eb5111..3c4f6d983cbd 100644
--- a/arch/arm/boot/dts/animeo_ip.dts
+++ b/arch/arm/boot/dts/animeo_ip.dts
@@ -90,34 +90,19 @@
                         nand-on-flash-bbt;
                         status = "okay";
 
-                        at91bootstrap@0 {
-                                label = "at91bootstrap";
-                                reg = <0x0 0x8000>;
-                        };
-
-                        barebox@8000 {
+                        barebox@0 {
                                 label = "barebox";
-                                reg = <0x8000 0x40000>;
-                        };
-
-                        bareboxenv@48000 {
-                                label = "bareboxenv";
-                                reg = <0x48000 0x8000>;
-                        };
-
-                        user_block@0x50000 {
-                                label = "user_block";
-                                reg = <0x50000 0xb0000>;
+                                reg = <0x0 0x58000>;
                         };
 
-                        kernel@100000 {
-                                label = "kernel";
-                                reg = <0x100000 0x1b0000>;
+                        u_boot_env@58000 {
+                                label = "u_boot_env";
+                                reg = <0x58000 0x8000>;
                         };
 
-                        root@2b0000 {
-                                label = "root";
-                                reg = <0x2b0000 0x1D50000>;
+                        ubi@60000 {
+                                label = "ubi";
+                                reg = <0x60000 0x1FA0000>;
                         };
                 };
 
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index 2471d9da767b..944e8785b308 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -74,13 +74,13 @@
                                 green_pwr_led {
                                         label = "mirabox:green:pwr";
                                         gpios = <&gpio1 31 1>;
-                                        linux,default-trigger = "heartbeat";
+                                        default-state = "keep";
                                 };
 
                                 blue_stat_led {
                                         label = "mirabox:blue:stat";
                                         gpios = <&gpio2 0 1>;
-                                        linux,default-trigger = "cpu0";
+                                        default-state = "off";
                                 };
 
                                 green_stat_led {
@@ -139,6 +139,27 @@
                                         reg = <0x25>;
                                 };
                         };
+
+                        nand@d0000 {
+                                status = "okay";
+                                num-cs = <1>;
+                                marvell,nand-keep-config;
+                                marvell,nand-enable-arbiter;
+                                nand-on-flash-bbt;
+
+                                partition@0 {
+                                        label = "U-Boot";
+                                        reg = <0 0x400000>;
+                                };
+                                partition@400000 {
+                                        label = "Linux";
+                                        reg = <0x400000 0x400000>;
+                                };
+                                partition@800000 {
+                                        label = "Filesystem";
+                                        reg = <0x800000 0x3f800000>;
+                                };
+                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
index 8ac2ac1f69cc..651aeb5ef439 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
@@ -11,6 +11,8 @@
 
 /dts-v1/;
 
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
 #include "armada-370.dtsi"
 
 / {
@@ -62,6 +64,7 @@
                                         marvell,pins = "mpp57";
                                         marvell,function = "gpio";
                                 };
+
                                 sata1_led_pin: sata1-led-pin {
                                         marvell,pins = "mpp15";
                                         marvell,function = "gpio";
@@ -77,6 +80,21 @@
                                         marvell,function = "gpio";
                                 };
 
+                                backup_button_pin: backup-button-pin {
+                                        marvell,pins = "mpp58";
+                                        marvell,function = "gpio";
+                                };
+
+                                power_button_pin: power-button-pin {
+                                        marvell,pins = "mpp62";
+                                        marvell,function = "gpio";
+                                };
+
+                                reset_button_pin: reset-button-pin {
+                                        marvell,pins = "mpp6";
+                                        marvell,function = "gpio";
+                                };
+
                                 poweroff: poweroff {
                                         marvell,pins = "mpp8";
                                         marvell,function = "gpio";
@@ -84,7 +102,7 @@
                         };
 
                         mdio {
-                                phy0: ethernet-phy@0 {
+                                phy0: ethernet-phy@0 { /* Marvell 88E1318 */
                                         reg = <0>;
                                 };
                         };
@@ -104,6 +122,11 @@
                                 clock-frequency = <100000>;
                                 status = "okay";
 
+                                isl12057: isl12057@68 {
+                                        compatible = "isl,isl12057";
+                                        reg = <0x68>;
+                                };
+
                                 g762: g762@3e {
                                         compatible = "gmt,g762";
                                         reg = <0x3e>;
@@ -113,82 +136,116 @@
                                         pwm_polarity = <0>;
                                 };
                         };
+
+                        nand@d0000 {
+                                status = "okay";
+                                num-cs = <1>;
+                                marvell,nand-keep-config;
+                                marvell,nand-enable-arbiter;
+                                nand-on-flash-bbt;
+
+                                partition@0 {
+                                        label = "u-boot";
+                                        reg = <0x0000000 0x180000>;  /* 1.5MB */
+                                        read-only;
+                                };
+
+                                partition@180000 {
+                                        label = "u-boot-env";
+                                        reg = <0x180000 0x20000>;    /* 128KB */
+                                        read-only;
+                                };
+
+                                partition@200000 {
+                                        label = "uImage";
+                                        reg = <0x0200000 0x600000>;    /* 6MB */
+                                };
+
+                                partition@800000 {
+                                        label = "minirootfs";
+                                        reg = <0x0800000 0x400000>;    /* 4MB */
+                                };
+
+                                /* Last MB is for the BBT, i.e. not writable */
+                                partition@c00000 {
+                                        label = "ubifs";
+                                        reg = <0x0c00000 0x7400000>; /* 116MB */
+                                };
+                        };
                 };
         };
 
         clocks {
-               #address-cells = <1>;
-               #size-cells = <0>;
-
-               g762_clk: fixedclk {
+               g762_clk: g762-oscillator {
                          compatible = "fixed-clock";
                          #clock-cells = <0>;
                          clock-frequency = <8192>;
                };
         };
 
-        gpio_leds {
+        gpio-leds {
                 compatible = "gpio-leds";
-                pinctrl-0 = < &power_led_pin
-                              &sata1_led_pin
-                              &sata2_led_pin
-                              &backup_led_pin >;
+                pinctrl-0 = <&power_led_pin
+                             &sata1_led_pin
+                             &sata2_led_pin
+                             &backup_led_pin>;
                 pinctrl-names = "default";
 
-                blue_power_led {
+                blue-power-led {
                         label = "rn102:blue:pwr";
-                        gpios = <&gpio1 25 1>;  /* GPIO 57 Active Low */
-                        linux,default-trigger = "heartbeat";
+                        gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
+                        default-state = "keep";
                 };
 
-                green_sata1_led {
+                green-sata1-led {
                         label = "rn102:green:sata1";
-                        gpios = <&gpio0 15 1>;  /* GPIO 15 Active Low */
+                        gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
                         default-state = "on";
                 };
 
-                green_sata2_led {
+                green-sata2-led {
                         label = "rn102:green:sata2";
-                        gpios = <&gpio0 14 1>;   /* GPIO 14 Active Low */
+                        gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
                         default-state = "on";
                 };
 
-                green_backup_led {
+                green-backup-led {
                         label = "rn102:green:backup";
-                        gpios = <&gpio1 24 1>;   /* GPIO 56 Active Low */
+                        gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
                         default-state = "on";
                 };
         };
 
-        gpio_keys {
+        gpio-keys {
                 compatible = "gpio-keys";
-                #address-cells = <1>;
-                #size-cells = <0>;
+                pinctrl-0 = <&power_button_pin
+                             &reset_button_pin
+                             &backup_button_pin>;
+                pinctrl-names = "default";
 
-                button@1 {
+                power-button {
                         label = "Power Button";
-                        linux,code = <116>;     /* KEY_POWER */
-                        gpios = <&gpio1 30 0>;
+                        linux,code = <KEY_POWER>;
+                        gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
                 };
 
-                button@2 {
+                reset-button {
                         label = "Reset Button";
-                        linux,code = <0x198>;   /* KEY_RESTART */
-                        gpios = <&gpio0 6 1>;
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
                 };
 
-                button@3 {
+                backup-button {
                         label = "Backup Button";
-                        linux,code = <133>;     /* KEY_COPY */
-                        gpios = <&gpio1 26 1>;
+                        linux,code = <KEY_COPY>;
+                        gpios = <&gpio1 26 GPIO_ACTIVE_LOW>;
                 };
         };
 
-        gpio_poweroff {
+        gpio-poweroff {
                 compatible = "gpio-poweroff";
                 pinctrl-0 = <&poweroff>;
                 pinctrl-names = "default";
-                gpios = <&gpio0 8 1>;
+                gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
         };
-
 };
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
index b0b32f5fbeb4..4e27587667bf 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
@@ -11,6 +11,8 @@
 
 /dts-v1/;
 
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
 #include "armada-370.dtsi"
 
 / {
@@ -58,12 +60,12 @@
                                         marvell,function = "gpio";
                                 };
 
-                                backup_key_pin: backup-key-pin {
+                                backup_button_pin: backup-button-pin {
                                         marvell,pins = "mpp52";
                                         marvell,function = "gpio";
                                 };
 
-                                power_key_pin: power-key-pin {
+                                power_button_pin: power-button-pin {
                                         marvell,pins = "mpp62";
                                         marvell,function = "gpio";
                                 };
@@ -78,18 +80,18 @@
                                         marvell,function = "gpio";
                                 };
 
-                                reset_key_pin: reset-key-pin {
+                                reset_button_pin: reset-button-pin {
                                         marvell,pins = "mpp65";
                                         marvell,function = "gpio";
                                 };
                         };
 
                         mdio {
-                                phy0: ethernet-phy@0 {
+                                phy0: ethernet-phy@0 { /* Marvell 88E1318 */
                                         reg = <0>;
                                 };
 
-                                phy1: ethernet-phy@1 {
+                                phy1: ethernet-phy@1 { /* Marvell 88E1318 */
                                         reg = <1>;
                                 };
                         };
@@ -115,6 +117,11 @@
                                 clock-frequency = <100000>;
                                 status = "okay";
 
+                                isl12057: isl12057@68 {
+                                        compatible = "isl,isl12057";
+                                        reg = <0x68>;
+                                };
+
                                 g762: g762@3e {
                                         compatible = "gmt,g762";
                                         reg = <0x3e>;
@@ -123,71 +130,133 @@
                                         fan_startv = <1>;
                                         pwm_polarity = <0>;
                                 };
+
+                                pca9554: pca9554@23 {
+                                        compatible = "nxp,pca9554";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        reg = <0x23>;
+                                };
+                        };
+
+                        nand@d0000 {
+                                status = "okay";
+                                num-cs = <1>;
+                                marvell,nand-keep-config;
+                                marvell,nand-enable-arbiter;
+                                nand-on-flash-bbt;
+
+                                partition@0 {
+                                        label = "u-boot";
+                                        reg = <0x0000000 0x180000>;  /* 1.5MB */
+                                        read-only;
+                                };
+
+                                partition@180000 {
+                                        label = "u-boot-env";
+                                        reg = <0x180000 0x20000>;    /* 128KB */
+                                        read-only;
+                                };
+
+                                partition@200000 {
+                                        label = "uImage";
+                                        reg = <0x0200000 0x600000>;    /* 6MB */
+                                };
+
+                                partition@800000 {
+                                        label = "minirootfs";
+                                        reg = <0x0800000 0x400000>;    /* 4MB */
+                                };
+
+                                /* Last MB is for the BBT, i.e. not writable */
+                                partition@c00000 {
+                                        label = "ubifs";
+                                        reg = <0x0c00000 0x7400000>; /* 116MB */
+                                };
                         };
                 };
         };
 
         clocks {
-               #address-cells = <1>;
-               #size-cells = <0>;
-
-               g762_clk: fixedclk {
+               g762_clk: g762-oscillator {
                          compatible = "fixed-clock";
                          #clock-cells = <0>;
                          clock-frequency = <8192>;
                };
         };
 
-        gpio_leds {
+        gpio-leds {
                 compatible = "gpio-leds";
                 pinctrl-0 = <&backup_led_pin &power_led_pin>;
                 pinctrl-names = "default";
 
-                blue_backup_led {
+                blue-backup-led {
                         label = "rn104:blue:backup";
-                        gpios = <&gpio1 31 0>;   /* GPIO 63 Active High */
+                        gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
                         default-state = "off";
                 };
 
-                blue_power_led {
+                blue-power-led {
                         label = "rn104:blue:pwr";
-                        gpios = <&gpio2 0 1>;    /* GPIO 64 Active Low */
+                        gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
                         linux,default-trigger = "keep";
                 };
+
+                blue-sata1-led {
+                        label = "rn104:blue:sata1";
+                        gpios = <&pca9554 0 GPIO_ACTIVE_LOW>;
+                        default-state = "off";
+                };
+
+                blue-sata2-led {
+                        label = "rn104:blue:sata2";
+                        gpios = <&pca9554 1 GPIO_ACTIVE_LOW>;
+                        default-state = "off";
+                };
+
+                blue-sata3-led {
+                        label = "rn104:blue:sata3";
+                        gpios = <&pca9554 2 GPIO_ACTIVE_LOW>;
+                        default-state = "off";
+                };
+
+                blue-sata4-led {
+                        label = "rn104:blue:sata4";
+                        gpios = <&pca9554 3 GPIO_ACTIVE_LOW>;
+                        default-state = "off";
+                };
         };
 
-        gpio_keys {
+        gpio-keys {
                 compatible = "gpio-keys";
-                #address-cells = <1>;
-                #size-cells = <0>;
-                pinctrl-0 = <&backup_key_pin
-                             &power_key_pin
-                             &reset_key_pin>;
+                pinctrl-0 = <&backup_button_pin
+                             &power_button_pin
+                             &reset_button_pin>;
                 pinctrl-names = "default";
 
-                button@1 {
+                backup-button {
                         label = "Backup Button";
-                        linux,code = <133>;     /* KEY_COPY */
-                        gpios = <&gpio1 20 1>;
+                        linux,code = <KEY_COPY>;
+                        gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
                 };
 
-                button@2 {
+                power-button {
                         label = "Power Button";
-                        linux,code = <116>;     /* KEY_POWER */
-                        gpios = <&gpio1 30 0>;
+                        linux,code = <KEY_POWER>;
+                        gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
                 };
 
-                button@3 {
+                reset-button {
                         label = "Reset Button";
-                        linux,code = <0x198>;   /* KEY_RESTART */
-                        gpios = <&gpio2 1 1>;
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
                 };
         };
 
-        gpio_poweroff {
+        gpio-poweroff {
                 compatible = "gpio-poweroff";
                 pinctrl-0 = <&poweroff>;
                 pinctrl-names = "default";
-                gpios = <&gpio1 28 1>;
+                gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
         };
 };
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index f81810a59629..abbb807459d2 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -104,6 +104,27 @@
                                         gpios = <&gpio0 6 1>;
                                 };
                         };
+
+                        nand@d0000 {
+                                status = "okay";
+                                num-cs = <1>;
+                                marvell,nand-keep-config;
+                                marvell,nand-enable-arbiter;
+                                nand-on-flash-bbt;
+
+                                partition@0 {
+                                        label = "U-Boot";
+                                        reg = <0 0x800000>;
+                                };
+                                partition@800000 {
+                                        label = "Linux";
+                                        reg = <0x800000 0x800000>;
+                                };
+                                partition@1000000 {
+                                        label = "Filesystem";
+                                        reg = <0x1000000 0x3f000000>;
+                                };
+                        };
                 };
         };
  };
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 80ffacd128f8..74b5964430ac 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -103,22 +103,52 @@
                         #size-cells = <1>;
                         ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
 
-                        mbusc: mbus-controller@20000 {
-                                compatible = "marvell,mbus-controller";
-                                reg = <0x20000 0x100>, <0x20180 0x20>;
+                        rtc@10300 {
+                                compatible = "marvell,orion-rtc";
+                                reg = <0x10300 0x20>;
+                                interrupts = <50>;
                         };
 
-                        mpic: interrupt-controller@20000 {
-                                compatible = "marvell,mpic";
-                                #interrupt-cells = <1>;
-                                #size-cells = <1>;
-                                interrupt-controller;
-                                msi-controller;
+                        spi0: spi@10600 {
+                                compatible = "marvell,orion-spi";
+                                reg = <0x10600 0x28>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                cell-index = <0>;
+                                interrupts = <30>;
+                                clocks = <&coreclk 0>;
+                                status = "disabled";
                         };
 
-                        coherency-fabric@20200 {
-                                compatible = "marvell,coherency-fabric";
-                                reg = <0x20200 0xb0>, <0x21010 0x1c>;
+                        spi1: spi@10680 {
+                                compatible = "marvell,orion-spi";
+                                reg = <0x10680 0x28>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                cell-index = <1>;
+                                interrupts = <92>;
+                                clocks = <&coreclk 0>;
+                                status = "disabled";
+                        };
+
+                        i2c0: i2c@11000 {
+                                compatible = "marvell,mv64xxx-i2c";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                interrupts = <31>;
+                                timeout-ms = <1000>;
+                                clocks = <&coreclk 0>;
+                                status = "disabled";
+                        };
+
+                        i2c1: i2c@11100 {
+                                compatible = "marvell,mv64xxx-i2c";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                interrupts = <32>;
+                                timeout-ms = <1000>;
+                                clocks = <&coreclk 0>;
+                                status = "disabled";
                         };
 
                         serial@12000 {
@@ -146,25 +176,41 @@
                                 clock-output-names = "nand";
                         };
 
+                        mbusc: mbus-controller@20000 {
+                                compatible = "marvell,mbus-controller";
+                                reg = <0x20000 0x100>, <0x20180 0x20>;
+                        };
+
+                        mpic: interrupt-controller@20000 {
+                                compatible = "marvell,mpic";
+                                #interrupt-cells = <1>;
+                                #size-cells = <1>;
+                                interrupt-controller;
+                                msi-controller;
+                        };
+
+                        coherency-fabric@20200 {
+                                compatible = "marvell,coherency-fabric";
+                                reg = <0x20200 0xb0>, <0x21010 0x1c>;
+                        };
+
                         timer@20300 {
                                 reg = <0x20300 0x30>, <0x21040 0x30>;
                                 interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
                         };
 
-                        sata@a0000 {
-                                compatible = "marvell,armada-370-sata";
-                                reg = <0xa0000 0x5000>;
-                                interrupts = <55>;
-                                clocks = <&gateclk 15>, <&gateclk 30>;
-                                clock-names = "0", "1";
+                        usb@50000 {
+                                compatible = "marvell,orion-ehci";
+                                reg = <0x50000 0x500>;
+                                interrupts = <45>;
                                 status = "disabled";
                         };
 
-                        mdio {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "marvell,orion-mdio";
-                                reg = <0x72004 0x4>;
+                        usb@51000 {
+                                compatible = "marvell,orion-ehci";
+                                reg = <0x51000 0x500>;
+                                interrupts = <46>;
+                                status = "disabled";
                         };
 
                         eth0: ethernet@70000 {
@@ -175,6 +221,13 @@
                                 status = "disabled";
                         };
 
+                        mdio {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "marvell,orion-mdio";
+                                reg = <0x72004 0x4>;
+                        };
+
                         eth1: ethernet@74000 {
                                 compatible = "marvell,armada-370-neta";
                                 reg = <0x74000 0x4000>;
@@ -183,32 +236,25 @@
                                 status = "disabled";
                         };
 
-                        i2c0: i2c@11000 {
-                                compatible = "marvell,mv64xxx-i2c";
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                interrupts = <31>;
-                                timeout-ms = <1000>;
-                                clocks = <&coreclk 0>;
+                        sata@a0000 {
+                                compatible = "marvell,armada-370-sata";
+                                reg = <0xa0000 0x5000>;
+                                interrupts = <55>;
+                                clocks = <&gateclk 15>, <&gateclk 30>;
+                                clock-names = "0", "1";
                                 status = "disabled";
                         };
 
-                        i2c1: i2c@11100 {
-                                compatible = "marvell,mv64xxx-i2c";
+                        nand@d0000 {
+                                compatible = "marvell,armada370-nand";
+                                reg = <0xd0000 0x54>;
                                 #address-cells = <1>;
-                                #size-cells = <0>;
-                                interrupts = <32>;
-                                timeout-ms = <1000>;
-                                clocks = <&coreclk 0>;
+                                #size-cells = <1>;
+                                interrupts = <113>;
+                                clocks = <&coredivclk 0>;
                                 status = "disabled";
                         };
 
-                        rtc@10300 {
-                                compatible = "marvell,orion-rtc";
-                                reg = <0x10300 0x20>;
-                                interrupts = <50>;
-                        };
-
                         mvsdio@d4000 {
                                 compatible = "marvell,orion-sdio";
                                 reg = <0xd4000 0x200>;
@@ -220,43 +266,6 @@
                                 cap-mmc-highspeed;
                                 status = "disabled";
                         };
-
-                        usb@50000 {
-                                compatible = "marvell,orion-ehci";
-                                reg = <0x50000 0x500>;
-                                interrupts = <45>;
-                                status = "disabled";
-                        };
-
-                        usb@51000 {
-                                compatible = "marvell,orion-ehci";
-                                reg = <0x51000 0x500>;
-                                interrupts = <46>;
-                                status = "disabled";
-                        };
-
-                        spi0: spi@10600 {
-                                compatible = "marvell,orion-spi";
-                                reg = <0x10600 0x28>;
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                cell-index = <0>;
-                                interrupts = <30>;
-                                clocks = <&coreclk 0>;
-                                status = "disabled";
-                        };
-
-                        spi1: spi@10680 {
-                                compatible = "marvell,orion-spi";
-                                reg = <0x10680 0x28>;
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                cell-index = <1>;
-                                interrupts = <92>;
-                                clocks = <&coreclk 0>;
-                                status = "disabled";
-                        };
-
                 };
         };
 
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 7a4b82e71aaf..0d8530c98cf5 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -91,11 +91,6 @@
                 };
 
                 internal-regs {
-                        system-controller@18200 {
-                                compatible = "marvell,armada-370-xp-system-controller";
-                                reg = <0x18200 0x100>;
-                        };
-
                         L2: l2-cache {
                                 compatible = "marvell,aurora-outer-cache";
                                 reg = <0x08000 0x1000>;
@@ -103,8 +98,17 @@
                                 wt-override;
                         };
 
-                        interrupt-controller@20000 {
-                                reg = <0x20a00 0x1d0>, <0x21870 0x58>;
+                        i2c0: i2c@11000 {
+                                reg = <0x11000 0x20>;
+                        };
+
+                        i2c1: i2c@11100 {
+                                reg = <0x11100 0x20>;
+                        };
+
+                        system-controller@18200 {
+                                compatible = "marvell,armada-370-xp-system-controller";
+                                reg = <0x18200 0x100>;
                         };
 
                         pinctrl {
@@ -163,9 +167,11 @@
                                 interrupts = <91>;
                         };
 
-                        timer@20300 {
-                                compatible = "marvell,armada-370-timer";
-                                clocks = <&coreclk 2>;
+                        gateclk: clock-gating-control@18220 {
+                                compatible = "marvell,armada-370-gating-clock";
+                                reg = <0x18220 0x4>;
+                                clocks = <&coreclk 0>;
+                                #clock-cells = <1>;
                         };
 
                         coreclk: mvebu-sar@18230 {
@@ -174,11 +180,28 @@
                                 #clock-cells = <1>;
                         };
 
-                        gateclk: clock-gating-control@18220 {
-                                compatible = "marvell,armada-370-gating-clock";
-                                reg = <0x18220 0x4>;
+                        thermal@18300 {
+                                compatible = "marvell,armada370-thermal";
+                                reg = <0x18300 0x4
+                                        0x18304 0x4>;
+                                status = "okay";
+                        };
+
+                        interrupt-controller@20000 {
+                                reg = <0x20a00 0x1d0>, <0x21870 0x58>;
+                        };
+
+                        timer@20300 {
+                                compatible = "marvell,armada-370-timer";
+                                clocks = <&coreclk 2>;
+                        };
+
+                        usb@50000 {
+                                clocks = <&coreclk 0>;
+                        };
+
+                        usb@51000 {
                                 clocks = <&coreclk 0>;
-                                #clock-cells = <1>;
                         };
 
                         xor@60800 {
@@ -218,29 +241,6 @@
                                         dmacap,memset;
                                 };
                         };
-
-                        i2c0: i2c@11000 {
-                                reg = <0x11000 0x20>;
-                        };
-
-                        i2c1: i2c@11100 {
-                                reg = <0x11100 0x20>;
-                        };
-
-                        usb@50000 {
-                                clocks = <&coreclk 0>;
-                        };
-
-                        usb@51000 {
-                                clocks = <&coreclk 0>;
-                        };
-
-                        thermal@18300 {
-                                compatible = "marvell,armada370-thermal";
-                                reg = <0x18300 0x4
-                                        0x18304 0x4>;
-                                status = "okay";
-                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 2298e4a910e2..274e2ad5f51c 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -175,6 +175,14 @@
                                         spi-max-frequency = <108000000>;
                                 };
                         };
+
+                        nand@d0000 {
+                                status = "okay";
+                                num-cs = <1>;
+                                marvell,nand-keep-config;
+                                marvell,nand-enable-arbiter;
+                                nand-on-flash-bbt;
+                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
new file mode 100644
index 000000000000..ff049ee862eb
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
@@ -0,0 +1,327 @@
+/*
+ * Device Tree file for NETGEAR ReadyNAS 2120
+ *
+ * Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "armada-xp-mv78230.dtsi"
+
+/ {
+        model = "NETGEAR ReadyNAS 2120";
+        compatible = "netgear,readynas-2120", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
+
+        chosen {
+                bootargs = "console=ttyS0,115200 earlyprintk";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0 0x00000000 0 0x80000000>; /* 2GB */
+        };
+
+        soc {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
+                          MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
+
+                pcie-controller {
+                        status = "okay";
+
+                        /* Connected to first Marvell 88SE9170 SATA controller */
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+
+                        /* Connected to second Marvell 88SE9170 SATA controller */
+                        pcie@2,0 {
+                                /* Port 0, Lane 1 */
+                                status = "okay";
+                        };
+
+                        /* Connected to Fresco Logic FL1009 USB 3.0 controller */
+                        pcie@5,0 {
+                                /* Port 1, Lane 0 */
+                                status = "okay";
+                        };
+                };
+
+                internal-regs {
+                        pinctrl {
+                                poweroff: poweroff {
+                                        marvell,pins = "mpp42";
+                                        marvell,function = "gpio";
+                                };
+
+                                power_button_pin: power-button-pin {
+                                        marvell,pins = "mpp27";
+                                        marvell,function = "gpio";
+                                };
+
+                                reset_button_pin: reset-button-pin {
+                                        marvell,pins = "mpp41";
+                                        marvell,function = "gpio";
+                                };
+
+                                sata1_led_pin: sata1-led-pin {
+                                        marvell,pins = "mpp31";
+                                        marvell,function = "gpio";
+                                };
+
+                                sata2_led_pin: sata2-led-pin {
+                                        marvell,pins = "mpp40";
+                                        marvell,function = "gpio";
+                                };
+
+                                sata3_led_pin: sata3-led-pin {
+                                        marvell,pins = "mpp44";
+                                        marvell,function = "gpio";
+                                };
+
+                                sata4_led_pin: sata4-led-pin {
+                                        marvell,pins = "mpp47";
+                                        marvell,function = "gpio";
+                                };
+
+                                sata1_power_pin: sata1-power-pin {
+                                        marvell,pins = "mpp24";
+                                        marvell,function = "gpio";
+                                };
+
+                                sata2_power_pin: sata2-power-pin {
+                                        marvell,pins = "mpp25";
+                                        marvell,function = "gpio";
+                                };
+
+                                sata3_power_pin: sata3-power-pin {
+                                        marvell,pins = "mpp26";
+                                        marvell,function = "gpio";
+                                };
+
+                                sata4_power_pin: sata4-power-pin {
+                                        marvell,pins = "mpp28";
+                                        marvell,function = "gpio";
+                                };
+
+                                sata1_pres_pin: sata1-pres-pin {
+                                        marvell,pins = "mpp32";
+                                        marvell,function = "gpio";
+                                };
+
+                                sata2_pres_pin: sata2-pres-pin {
+                                        marvell,pins = "mpp33";
+                                        marvell,function = "gpio";
+                                };
+
+                                sata3_pres_pin: sata3-pres-pin {
+                                        marvell,pins = "mpp34";
+                                        marvell,function = "gpio";
+                                };
+
+                                sata4_pres_pin: sata4-pres-pin {
+                                        marvell,pins = "mpp35";
+                                        marvell,function = "gpio";
+                                };
+
+                                err_led_pin: err-led-pin {
+                                        marvell,pins = "mpp45";
+                                        marvell,function = "gpio";
+                                };
+                        };
+
+                        serial@12000 {
+                                clocks = <&coreclk 0>;
+                                status = "okay";
+                        };
+
+                        mdio {
+                                phy0: ethernet-phy@0 { /* Marvell 88E1318 */
+                                        reg = <0>;
+                                };
+
+                                phy1: ethernet-phy@1 { /* Marvell 88E1318 */
+                                        reg = <1>;
+                                };
+                        };
+
+                        ethernet@70000 {
+                                status = "okay";
+                                phy = <&phy0>;
+                                phy-mode = "rgmii-id";
+                        };
+
+                        ethernet@74000 {
+                                status = "okay";
+                                phy = <&phy1>;
+                                phy-mode = "rgmii-id";
+                        };
+
+                        /* Front USB 2.0 port */
+                        usb@50000 {
+                                status = "okay";
+                        };
+
+                        i2c@11000 {
+                                compatible = "marvell,mv64xxx-i2c";
+                                clock-frequency = <400000>;
+                                status = "okay";
+
+                                isl12057: isl12057@68 {
+                                        compatible = "isl,isl12057";
+                                        reg = <0x68>;
+                                };
+
+                                /* Controller for rear fan #1 of 3 (Protechnic
+                                 * MGT4012XB-O20, 8000RPM) near eSATA port */
+                                g762_fan1: g762@3e {
+                                        compatible = "gmt,g762";
+                                        reg = <0x3e>;
+                                        clocks = <&g762_clk>; /* input clock */
+                                        fan_gear_mode = <0>;
+                                        fan_startv = <1>;
+                                        pwm_polarity = <0>;
+                                };
+
+                                /*  Controller for rear (center) fan #2 of 3 */
+                                g762_fan2: g762@48 {
+                                        compatible = "gmt,g762";
+                                        reg = <0x48>;
+                                        clocks = <&g762_clk>; /* input clock */
+                                        fan_gear_mode = <0>;
+                                        fan_startv = <1>;
+                                        pwm_polarity = <0>;
+                                };
+
+                                /*  Controller for rear fan #3 of 3 */
+                                g762_fan3: g762@49 {
+                                        compatible = "gmt,g762";
+                                        reg = <0x49>;
+                                        clocks = <&g762_clk>; /* input clock */
+                                        fan_gear_mode = <0>;
+                                        fan_startv = <1>;
+                                        pwm_polarity = <0>;
+                                };
+
+                                /* Temperature sensor */
+                                g751: g751@4c {
+                                        compatible = "gmt,g751";
+                                        reg = <0x4c>;
+                                };
+                        };
+
+                        nand@d0000 {
+                                status = "okay";
+                                num-cs = <1>;
+                                marvell,nand-keep-config;
+                                marvell,nand-enable-arbiter;
+                                nand-on-flash-bbt;
+
+                                partition@0 {
+                                        label = "u-boot";
+                                        reg = <0x0000000 0x180000>;  /* 1.5MB */
+                                        read-only;
+                                };
+
+                                partition@180000 {
+                                        label = "u-boot-env";
+                                        reg = <0x180000 0x20000>;    /* 128KB */
+                                        read-only;
+                                };
+
+                                partition@200000 {
+                                        label = "uImage";
+                                        reg = <0x0200000 0x600000>;    /* 6MB */
+                                };
+
+                                partition@800000 {
+                                        label = "minirootfs";
+                                        reg = <0x0800000 0x400000>;    /* 4MB */
+                                };
+
+                                /* Last MB is for the BBT, i.e. not writable */
+                                partition@c00000 {
+                                        label = "ubifs";
+                                        reg = <0x0c00000 0x7400000>; /* 116MB */
+                                };
+                        };
+                };
+        };
+
+        clocks {
+               g762_clk: g762-oscillator {
+                         compatible = "fixed-clock";
+                         #clock-cells = <0>;
+                         clock-frequency = <32768>;
+               };
+        };
+
+        gpio-leds {
+                compatible = "gpio-leds";
+                pinctrl-0 = <&sata1_led_pin &sata2_led_pin &err_led_pin
+                             &sata3_led_pin &sata4_led_pin>;
+                pinctrl-names = "default";
+
+                red-sata1-led {
+                        label = "rn2120:red:sata1";
+                        gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                red-sata2-led {
+                        label = "rn2120:red:sata2";
+                        gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                red-sata3-led {
+                        label = "rn2120:red:sata3";
+                        gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                red-sata4-led {
+                        label = "rn2120:red:sata4";
+                        gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                red-err-led {
+                        label = "rn2120:red:err";
+                        gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
+                        default-state = "off";
+                };
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                pinctrl-0 = <&power_button_pin &reset_button_pin>;
+                pinctrl-names = "default";
+
+                power-button {
+                        label = "Power Button";
+                        linux,code = <KEY_POWER>;
+                        gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>;
+                };
+
+                reset-button {
+                        label = "Reset Button";
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+                };
+        };
+
+        gpio-poweroff {
+                compatible = "gpio-poweroff";
+                pinctrl-0 = <&poweroff>;
+                pinctrl-names = "default";
+                gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+        };
+};
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 5695afcc04bf..99bcf76e6953 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -103,8 +103,7 @@
                                 green_led {
                                         label = "green_led";
                                         gpios = <&gpio1 21 1>;
-                                        default-state = "off";
-                                        linux,default-trigger = "heartbeat";
+                                        default-state = "keep";
                                 };
                         };
 
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 281c6447e872..b8b84a22f0f3 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -42,13 +42,14 @@
                                 wt-override;
                         };
 
-                        interrupt-controller@20000 {
-                              reg = <0x20a00 0x2d0>, <0x21070 0x58>;
+                        i2c0: i2c@11000 {
+                                compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
+                                reg = <0x11000 0x100>;
                         };
 
-                        armada-370-xp-pmsu@22000 {
-                                compatible = "marvell,armada-370-xp-pmsu";
-                                reg = <0x22100 0x430>, <0x20800 0x20>;
+                        i2c1: i2c@11100 {
+                                compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
+                                reg = <0x11100 0x100>;
                         };
 
                         serial@12200 {
@@ -68,10 +69,16 @@
                                 status = "disabled";
                         };
 
-                        timer@20300 {
-                                compatible = "marvell,armada-xp-timer";
-                                clocks = <&coreclk 2>, <&refclk>;
-                                clock-names = "nbclk", "fixed";
+                        system-controller@18200 {
+                                compatible = "marvell,armada-370-xp-system-controller";
+                                reg = <0x18200 0x500>;
+                        };
+
+                        gateclk: clock-gating-control@18220 {
+                                compatible = "marvell,armada-xp-gating-clock";
+                                reg = <0x18220 0x4>;
+                                clocks = <&coreclk 0>;
+                                #clock-cells = <1>;
                         };
 
                         coreclk: mvebu-sar@18230 {
@@ -80,6 +87,13 @@
                                 #clock-cells = <1>;
                         };
 
+                        thermal@182b0 {
+                                compatible = "marvell,armadaxp-thermal";
+                                reg = <0x182b0 0x4
+                                        0x184d0 0x4>;
+                                status = "okay";
+                        };
+
                         cpuclk: clock-complex@18700 {
                                 #clock-cells = <1>;
                                 compatible = "marvell,armada-xp-cpu-clock";
@@ -87,16 +101,19 @@
                                 clocks = <&coreclk 1>;
                         };
 
-                        gateclk: clock-gating-control@18220 {
-                                compatible = "marvell,armada-xp-gating-clock";
-                                reg = <0x18220 0x4>;
-                                clocks = <&coreclk 0>;
-                                #clock-cells = <1>;
+                        interrupt-controller@20000 {
+                              reg = <0x20a00 0x2d0>, <0x21070 0x58>;
                         };
 
-                        system-controller@18200 {
-                                compatible = "marvell,armada-370-xp-system-controller";
-                                reg = <0x18200 0x500>;
+                        timer@20300 {
+                                compatible = "marvell,armada-xp-timer";
+                                clocks = <&coreclk 2>, <&refclk>;
+                                clock-names = "nbclk", "fixed";
+                        };
+
+                        armada-370-xp-pmsu@22000 {
+                                compatible = "marvell,armada-370-xp-pmsu";
+                                reg = <0x22100 0x400>, <0x20800 0x20>;
                         };
 
                         eth2: ethernet@30000 {
@@ -107,6 +124,22 @@
                                 status = "disabled";
                         };
 
+                        usb@50000 {
+                                clocks = <&gateclk 18>;
+                        };
+
+                        usb@51000 {
+                                clocks = <&gateclk 19>;
+                        };
+
+                        usb@52000 {
+                                compatible = "marvell,orion-ehci";
+                                reg = <0x52000 0x500>;
+                                interrupts = <47>;
+                                clocks = <&gateclk 20>;
+                                status = "disabled";
+                        };
+
                         xor@60900 {
                                 compatible = "marvell,orion-xor";
                                 reg = <0x60900 0x100
@@ -146,39 +179,6 @@
                                         dmacap,memset;
                                 };
                         };
-
-                        i2c0: i2c@11000 {
-                                compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
-                                reg = <0x11000 0x100>;
-                        };
-
-                        i2c1: i2c@11100 {
-                                compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
-                                reg = <0x11100 0x100>;
-                        };
-
-                        usb@50000 {
-                                clocks = <&gateclk 18>;
-                        };
-
-                        usb@51000 {
-                                clocks = <&gateclk 19>;
-                        };
-
-                        usb@52000 {
-                                compatible = "marvell,orion-ehci";
-                                reg = <0x52000 0x500>;
-                                interrupts = <47>;
-                                clocks = <&gateclk 20>;
-                                status = "disabled";
-                        };
-
-                        thermal@182b0 {
-                                compatible = "marvell,armadaxp-thermal";
-                                reg = <0x182b0 0x4
-                                        0x184d0 0x4>;
-                                status = "okay";
-                        };
                 };
         };
 
diff --git a/arch/arm/boot/dts/at91-cosino.dtsi b/arch/arm/boot/dts/at91-cosino.dtsi
new file mode 100644
index 000000000000..2093c4d7cd6a
--- /dev/null
+++ b/arch/arm/boot/dts/at91-cosino.dtsi
@@ -0,0 +1,122 @@
+/*
+ * at91-cosino.dtsi - Device Tree file for Cosino core module
+ *
+ * Copyright (C) 2013 - Rodolfo Giometti <giometti@linux.it>
+ *                      HCE Engineering
+ *
+ * Derived from at91sam9x5ek.dtsi by:
+ *      Copyright (C) 2012 Atmel,
+ *      2012 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include "at91sam9g35.dtsi"
+
+/ {
+        model = "HCE Cosino core module";
+        compatible = "hce,cosino", "atmel,at91sam9x5", "atmel,at91sam9";
+
+        chosen {
+                bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootfstype=ext3 rootwait";
+        };
+
+        memory {
+                reg = <0x20000000 0x8000000>;
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <12000000>;
+                };
+        };
+
+        ahb {
+                apb {
+                        mmc0: mmc@f0008000 {
+                                pinctrl-0 = <
+                                        &pinctrl_board_mmc0
+                                        &pinctrl_mmc0_slot0_clk_cmd_dat0
+                                        &pinctrl_mmc0_slot0_dat1_3>;
+                                status = "okay";
+                                slot@0 {
+                                        reg = <0>;
+                                        bus-width = <4>;
+                                        cd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>;
+                                };
+                        };
+
+                        dbgu: serial@fffff200 {
+                                status = "okay";
+                        };
+
+                        usart0: serial@f801c000 {
+                                status = "okay";
+                        };
+
+                        i2c0: i2c@f8010000 {
+                                status = "okay";
+                        };
+
+                        adc0: adc@f804c000 {
+                                atmel,adc-clock-rate = <1000000>;
+                                atmel,adc-ts-wires = <4>;
+                                atmel,adc-ts-pressure-threshold = <10000>;
+                                status = "okay";
+                        };
+
+                        pinctrl@fffff400 {
+                                mmc0 {
+                                        pinctrl_board_mmc0: mmc0-board {
+                                                atmel,pins =
+                                                        <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;  /* PD15 gpio CD pin pull up and deglitch */
+                                        };
+                                };
+                        };
+
+                        watchdog@fffffe40 {
+                                status = "okay";
+                        };
+                };
+
+                nand0: nand@40000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "hw";
+                        atmel,has-pmecc;        /* Enable PMECC */
+                        atmel,pmecc-cap = <4>;
+                        atmel,pmecc-sector-size = <512>;
+                        nand-on-flash-bbt;
+                        status = "okay";
+
+                        at91bootstrap@0 {
+                                label = "at91bootstrap";
+                                reg = <0x0 0x40000>;
+                        };
+
+                        uboot@40000 {
+                                label = "u-boot";
+                                reg = <0x40000 0x80000>;
+                        };
+
+                        ubootenv@c0000 {
+                                label = "U-Boot Env";
+                                reg = <0xc0000 0x140000>;
+                        };
+
+                        kernel@200000 {
+                                label = "kernel";
+                                reg = <0x200000 0x600000>;
+                        };
+
+                        rootfs@800000 {
+                                label = "rootfs";
+                                reg = <0x800000 0x0f800000>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91-cosino_mega2560.dts b/arch/arm/boot/dts/at91-cosino_mega2560.dts
new file mode 100644
index 000000000000..f9415dd11f17
--- /dev/null
+++ b/arch/arm/boot/dts/at91-cosino_mega2560.dts
@@ -0,0 +1,84 @@
+/*
+ * at91-cosino_mega2560.dts - Device Tree file for Cosino board with
+ *                            Mega 2560 extension
+ *
+ * Copyright (C) 2013 - Rodolfo Giometti <giometti@linux.it>
+ *                      HCE Engineering
+ *
+ * Derived from at91sam9g35ek.dts by:
+ *      Copyright (C) 2012 Atmel,
+ *      2012 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/dts-v1/;
+#include "at91-cosino.dtsi"
+
+/ {
+        model = "HCE Cosino Mega 2560";
+        compatible = "hce,cosino_mega2560", "atmel,at91sam9x5", "atmel,at91sam9";
+
+        ahb {
+                apb {
+                        macb0: ethernet@f802c000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+
+                        adc0: adc@f804c000 {
+                                atmel,adc-clock-rate = <1000000>;
+                                atmel,adc-ts-wires = <4>;
+                                atmel,adc-ts-pressure-threshold = <10000>;
+                                status = "okay";
+                        };
+
+
+                        tsadcc: tsadcc@f804c000 {
+                                status = "okay";
+                        };
+
+                        rtc@fffffeb0 {
+                                status = "okay";
+                        };
+
+                        usart1: serial@f8020000 {
+                                status = "okay";
+                        };
+
+                        usart2: serial@f8024000 {
+                                status = "okay";
+                        };
+
+                        usb2: gadget@f803c000 {
+                                atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>;
+                                status = "okay";
+                        };
+
+                        mmc1: mmc@f000c000 {
+                                pinctrl-0 = <
+                                        &pinctrl_mmc1_slot0_clk_cmd_dat0
+                                        &pinctrl_mmc1_slot0_dat1_3>;
+                                status = "okay";
+                                slot@0 {
+                                        reg = <0>;
+                                        bus-width = <4>;
+                                        non-removable;
+                                };
+                        };
+                };
+
+                usb0: ohci@00600000 {
+                        status = "okay";
+                        num-ports = <3>;
+                        atmel,vbus-gpio = <0 /* &pioD 18 GPIO_ACTIVE_LOW */
+                                           &pioD 19 GPIO_ACTIVE_LOW
+                                           &pioD 20 GPIO_ACTIVE_LOW
+                                          >;
+                };
+
+                usb1: ehci@00700000 {
+                        status = "okay";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index f77065506f1e..c61b16fba79b 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -191,12 +191,12 @@
                                                          AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA18 periph A */
                                         };
 
-                                        pinctrl_uart0_rts: uart0_rts-0 {
+                                        pinctrl_uart0_cts: uart0_cts-0 {
                                                 atmel,pins =
                                                         <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A */
                                         };
 
-                                        pinctrl_uart0_cts: uart0_cts-0 {
+                                        pinctrl_uart0_rts: uart0_rts-0 {
                                                 atmel,pins =
                                                         <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */
                                         };
diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts
index d2d72c3b44c4..df6b0aa0e4dd 100644
--- a/arch/arm/boot/dts/at91rm9200ek.dts
+++ b/arch/arm/boot/dts/at91rm9200ek.dts
@@ -29,10 +29,22 @@
 
         ahb {
                 apb {
-                        dbgu: serial@fffff200 {
+                        usb1: gadget@fffb0000 {
+                                atmel,vbus-gpio = <&pioD 4 GPIO_ACTIVE_HIGH>;
+                                atmel,pullup-gpio = <&pioD 5 GPIO_ACTIVE_HIGH>;
                                 status = "okay";
                         };
 
+                        macb0: ethernet@fffbc000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+
+                                phy0: ethernet-phy {
+                                        interrupt-parent = <&pioC>;
+                                        interrupts = <4 IRQ_TYPE_EDGE_BOTH>;
+                                };
+                        };
+
                         usart1: serial@fffc4000 {
                                 pinctrl-0 =
                                                 <&pinctrl_uart1
@@ -44,16 +56,6 @@
                                 status = "okay";
                         };
 
-                        macb0: ethernet@fffbc000 {
-                                phy-mode = "rmii";
-                                status = "okay";
-                        };
-
-                        usb1: gadget@fffb0000 {
-                                atmel,vbus-gpio = <&pioD 4 GPIO_ACTIVE_HIGH>;
-                                status = "okay";
-                        };
-
                         spi0: spi@fffe0000 {
                                 status = "okay";
                                 cs-gpios = <&pioA 3 0>, <0>, <0>, <0>;
@@ -63,12 +65,45 @@
                                         reg = <0>;
                                 };
                         };
+
+                        dbgu: serial@fffff200 {
+                                status = "okay";
+                        };
                 };
 
                 usb0: ohci@00300000 {
                         num-ports = <2>;
                         status = "okay";
                 };
+
+                nor_flash@10000000 {
+                        compatible = "cfi-flash";
+                        reg = <0x10000000 0x800000>;
+                        linux,mtd-name = "physmap-flash.0";
+                        bank-width = <2>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        barebox@0 {
+                                label = "barebox";
+                                reg = <0x00000 0x40000>;
+                        };
+
+                        bareboxenv@40000 {
+                                label = "bareboxenv";
+                                reg = <0x40000 0x10000>;
+                        };
+
+                        kernel@50000 {
+                                label = "kernel";
+                                reg = <0x50000 0x300000>;
+                        };
+
+                        root@350000  {
+                                label = "root";
+                                reg = <0x350000 0x4B0000>;
+                        };
+                };
         };
 
         leds {
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index d5bd65f74602..c8fa9b9f07e3 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -30,6 +30,7 @@
                 i2c0 = &i2c0;
                 ssc0 = &ssc0;
                 ssc1 = &ssc1;
+                pwm0 = &pwm0;
         };
         cpus {
                 #address-cells = <0>;
@@ -366,6 +367,34 @@
                                         };
                                 };
 
+                                fb {
+                                        pinctrl_fb: fb-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC1 periph A */
+                                                         AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC2 periph A */
+                                                         AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC3 periph A */
+                                                         AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE    /* PB9 periph B */
+                                                         AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC6 periph A */
+                                                         AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC7 periph A */
+                                                         AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC8 periph A */
+                                                         AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC9 periph A */
+                                                         AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC10 periph A */
+                                                         AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC11 periph A */
+                                                         AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC14 periph A */
+                                                         AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC15 periph A */
+                                                         AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC16 periph A */
+                                                         AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC12 periph B */
+                                                         AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC18 periph A */
+                                                         AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC19 periph A */
+                                                         AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC22 periph A */
+                                                         AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC23 periph A */
+                                                         AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC24 periph A */
+                                                         AT91_PIOC 17 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC17 periph B */
+                                                         AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC26 periph A */
+                                                         AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC27 periph A */
+                                        };
+                                };
+
                                 pioA: gpio@fffff200 {
                                         compatible = "atmel,at91rm9200-gpio";
                                         reg = <0xfffff200 0x200>;
@@ -547,6 +576,23 @@
                                 pinctrl-0 = <&pinctrl_spi1>;
                                 status = "disabled";
                         };
+
+                        pwm0: pwm@fffb8000 {
+                                compatible = "atmel,at91sam9rl-pwm";
+                                reg = <0xfffb8000 0x300>;
+                                interrupts = <20 IRQ_TYPE_LEVEL_HIGH 4>;
+                                #pwm-cells = <3>;
+                                status = "disabled";
+                        };
+                };
+
+                fb0: fb@0x00700000 {
+                        compatible = "atmel,at91sam9263-lcdc";
+                        reg = <0x00700000 0x1000>;
+                        interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_fb>;
+                        status = "disabled";
                 };
 
                 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
index 70f835b55c0b..15009c9f2293 100644
--- a/arch/arm/boot/dts/at91sam9263ek.dts
+++ b/arch/arm/boot/dts/at91sam9263ek.dts
@@ -95,6 +95,36 @@
                         };
                 };
 
+                fb0: fb@0x00700000 {
+                        display = <&display0>;
+                        status = "okay";
+
+                        display0: display {
+                                bits-per-pixel = <16>;
+                                atmel,lcdcon-backlight;
+                                atmel,dmacon = <0x1>;
+                                atmel,lcdcon2 = <0x80008002>;
+                                atmel,guard-time = <1>;
+
+                                display-timings {
+                                        native-mode = <&timing0>;
+                                        timing0: timing0 {
+                                                clock-frequency = <4965000>;
+                                                hactive = <240>;
+                                                vactive = <320>;
+                                                hback-porch = <1>;
+                                                hfront-porch = <33>;
+                                                vback-porch = <1>;
+                                                vfront-porch = <0>;
+                                                hsync-len = <5>;
+                                                vsync-len = <1>;
+                                                hsync-active = <1>;
+                                                vsync-active = <1>;
+                                        };
+                                };
+                        };
+                };
+
                 nand0: nand@40000000 {
                         nand-bus-width = <8>;
                         nand-ecc-mode = "soft";
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index c3e514837074..ef0857cb171c 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -37,6 +37,7 @@
                 i2c1 = &i2c1;
                 ssc0 = &ssc0;
                 ssc1 = &ssc1;
+                pwm0 = &pwm0;
         };
         cpus {
                 #address-cells = <0>;
@@ -143,6 +144,22 @@
                                         };
                                 };
 
+                                i2c0 {
+                                        pinctrl_i2c0: i2c0-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA21 periph A TWCK0 */
+                                                         AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A TWD0 */
+                                        };
+                                };
+
+                                i2c1 {
+                                        pinctrl_i2c1: i2c1-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB11 periph A TWCK1 */
+                                                         AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A TWD1 */
+                                        };
+                                };
+
                                 usart0 {
                                         pinctrl_usart0: usart0-0 {
                                                 atmel,pins =
@@ -425,6 +442,42 @@
                                         };
                                 };
 
+                                fb {
+                                        pinctrl_fb: fb-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PE0 periph A */
+                                                         AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PE2 periph A */
+                                                         AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PE3 periph A */
+                                                         AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PE4 periph A */
+                                                         AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PE5 periph A */
+                                                         AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PE6 periph A */
+                                                         AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PE7 periph A */
+                                                         AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PE8 periph A */
+                                                         AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PE9 periph A */
+                                                         AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE10 periph A */
+                                                         AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE11 periph A */
+                                                         AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE12 periph A */
+                                                         AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE13 periph A */
+                                                         AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE14 periph A */
+                                                         AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE15 periph A */
+                                                         AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE16 periph A */
+                                                         AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE17 periph A */
+                                                         AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE18 periph A */
+                                                         AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE19 periph A */
+                                                         AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE20 periph A */
+                                                         AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE21 periph A */
+                                                         AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE22 periph A */
+                                                         AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE23 periph A */
+                                                         AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE24 periph A */
+                                                         AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE25 periph A */
+                                                         AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE26 periph A */
+                                                         AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE27 periph A */
+                                                         AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE28 periph A */
+                                                         AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE29 periph A */
+                                                         AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */
+                                        };
+                                };
+
                                 pioA: gpio@fffff200 {
                                         compatible = "atmel,at91rm9200-gpio";
                                         reg = <0xfffff200 0x200>;
@@ -542,6 +595,8 @@
                                 compatible = "atmel,at91sam9g10-i2c";
                                 reg = <0xfff84000 0x100>;
                                 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c0>;
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 status = "disabled";
@@ -551,6 +606,8 @@
                                 compatible = "atmel,at91sam9g10-i2c";
                                 reg = <0xfff88000 0x100>;
                                 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c1>;
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 status = "disabled";
@@ -614,10 +671,19 @@
                                 };
                         };
 
+                        pwm0: pwm@fffb8000 {
+                                compatible = "atmel,at91sam9rl-pwm";
+                                reg = <0xfffb8000 0x300>;
+                                interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
+                                #pwm-cells = <3>;
+                                status = "disabled";
+                        };
+
                         mmc0: mmc@fff80000 {
                                 compatible = "atmel,hsmci";
                                 reg = <0xfff80000 0x600>;
                                 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
+                                pinctrl-names = "default";
                                 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
                                 dma-names = "rxtx";
                                 #address-cells = <1>;
@@ -629,6 +695,7 @@
                                 compatible = "atmel,hsmci";
                                 reg = <0xfffd0000 0x600>;
                                 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>;
+                                pinctrl-names = "default";
                                 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>;
                                 dma-names = "rxtx";
                                 #address-cells = <1>;
@@ -727,6 +794,15 @@
                         };
                 };
 
+                fb0: fb@0x00500000 {
+                        compatible = "atmel,at91sam9g45-lcdc";
+                        reg = <0x00500000 0x1000>;
+                        interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_fb>;
+                        status = "disabled";
+                };
+
                 nand0: nand@40000000 {
                         compatible = "atmel,at91rm9200-nand";
                         #address-cells = <1>;
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index a4b00e5c61c0..7ff665a8c708 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -105,6 +105,14 @@
                                                          AT91_PIOD 29 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;   /* PD29 gpio WP pin pull up */
                                         };
                                 };
+
+                                pwm0 {
+                                        pinctrl_pwm_leds: pwm-led {
+                                                atmel,pins =
+                                                        <AT91_PIOD 0  AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* PD0 periph B */
+                                                         AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;      /* PD31 periph B */
+                                        };
+                                };
                         };
 
                         spi0: spi@fffa4000{
@@ -121,6 +129,42 @@
                                 atmel,vbus-gpio = <&pioB 19 GPIO_ACTIVE_HIGH>;
                                 status = "okay";
                         };
+
+                        pwm0: pwm@fffb8000 {
+                                status = "okay";
+
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_pwm_leds>;
+                        };
+                };
+
+                fb0: fb@0x00500000 {
+                        display = <&display0>;
+                        status = "okay";
+
+                        display0: display {
+                                bits-per-pixel = <32>;
+                                atmel,lcdcon-backlight;
+                                atmel,dmacon = <0x1>;
+                                atmel,lcdcon2 = <0x80008002>;
+                                atmel,guard-time = <9>;
+                                atmel,lcd-wiring-mode = "RGB";
+
+                                display-timings {
+                                        native-mode = <&timing0>;
+                                        timing0: timing0 {
+                                                clock-frequency = <9000000>;
+                                                hactive = <480>;
+                                                vactive = <272>;
+                                                hback-porch = <1>;
+                                                hfront-porch = <1>;
+                                                vback-porch = <40>;
+                                                vfront-porch = <1>;
+                                                hsync-len = <45>;
+                                                vsync-len = <1>;
+                                        };
+                                };
+                        };
                 };
 
                 nand0: nand@40000000 {
@@ -165,16 +209,22 @@
                         gpios = <&pioD 30 GPIO_ACTIVE_HIGH>;
                         linux,default-trigger = "heartbeat";
                 };
+        };
+
+        pwmleds {
+                compatible = "pwm-leds";
 
                 d6 {
                         label = "d6";
-                        gpios = <&pioD 0 GPIO_ACTIVE_LOW>;
+                        pwms = <&pwm0 3 5000 0>;
+                        max-brightness = <255>;
                         linux,default-trigger = "nand-disk";
                 };
 
                 d7 {
                         label = "d7";
-                        gpios = <&pioD 31 GPIO_ACTIVE_LOW>;
+                        pwms = <&pwm0 1 5000 0>;
+                        max-brightness = <255>;
                         linux,default-trigger = "mmc0";
                 };
         };
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 6224f9fe2f2b..7248270a3ea6 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -33,6 +33,7 @@
                 i2c0 = &i2c0;
                 i2c1 = &i2c1;
                 ssc0 = &ssc0;
+                pwm0 = &pwm0;
         };
         cpus {
                 #address-cells = <0>;
@@ -542,6 +543,14 @@
                                 reg = <0xfffffe40 0x10>;
                                 status = "disabled";
                         };
+
+                        pwm0: pwm@f8034000 {
+                                compatible = "atmel,at91sam9rl-pwm";
+                                reg = <0xf8034000 0x300>;
+                                interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
+                                #pwm-cells = <3>;
+                                status = "disabled";
+                        };
                 };
 
                 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 40267a116c3c..6e5e9cfc3c49 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -35,6 +35,7 @@
                 i2c1 = &i2c1;
                 i2c2 = &i2c2;
                 ssc0 = &ssc0;
+                pwm0 = &pwm0;
         };
         cpus {
                 #address-cells = <0>;
@@ -762,6 +763,14 @@
                                 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                                 status = "disabled";
                         };
+
+                        pwm0: pwm@f8034000 {
+                                compatible = "atmel,at91sam9rl-pwm";
+                                reg = <0xf8034000 0x300>;
+                                interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
+                                #pwm-cells = <3>;
+                                status = "disabled";
+                        };
                 };
 
                 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi
index 978bab4991df..f8674bcc4489 100644
--- a/arch/arm/boot/dts/atlas6.dtsi
+++ b/arch/arm/boot/dts/atlas6.dtsi
@@ -27,6 +27,15 @@
                         timebase-frequency = <0>;
                         bus-frequency = <0>;
                         clock-frequency = <0>;
+                        clocks = <&clks 12>;
+                        operating-points = <
+                                /* kHz    uV */
+                                200000  1025000
+                                400000  1025000
+                                600000  1050000
+                                800000  1100000
+                        >;
+                        clock-latency = <150000>;
                 };
         };
 
@@ -69,6 +78,7 @@
                         cphifbg@88030000 {
                                 compatible = "sirf,prima2-cphifbg";
                                 reg = <0x88030000 0x1000>;
+                                clocks = <&clks 42>;
                         };
                 };
 
@@ -546,6 +556,12 @@
                                                 sirf,function = "usp1";
                                         };
                                 };
+                                usp1_uart_nostreamctrl_pins_a: usp1@1 {
+                                        usp1 {
+                                                sirf,pins = "usp1_uart_nostreamctrl_grp";
+                                                sirf,function = "usp1_uart_nostreamctrl";
+                                        };
+                                };
                                 usb0_upli_drvbus_pins_a: usb0_upli_drvbus@0 {
                                         usb0_upli_drvbus {
                                                 sirf,pins = "usb0_upli_drvbusgrp";
@@ -636,6 +652,7 @@
                                         reg = <0x56100000 0x100000>;
                                         interrupts = <38>;
                                         status = "disabled";
+                                        bus-width = <4>;
                                         clocks = <&clks 36>;
                                 };
 
@@ -645,6 +662,7 @@
                                         reg = <0x56200000 0x100000>;
                                         interrupts = <23>;
                                         status = "disabled";
+                                        bus-width = <4>;
                                         clocks = <&clks 37>;
                                 };
 
@@ -654,6 +672,7 @@
                                         reg = <0x56300000 0x100000>;
                                         interrupts = <23>;
                                         status = "disabled";
+                                        bus-width = <4>;
                                         clocks = <&clks 37>;
                                 };
 
@@ -663,6 +682,7 @@
                                         reg = <0x56500000 0x100000>;
                                         interrupts = <39>;
                                         status = "disabled";
+                                        bus-width = <4>;
                                         clocks = <&clks 38>;
                                 };
 
@@ -697,6 +717,12 @@
                                 interrupts = <52 53 54>;
                         };
 
+                        minigpsrtc@2000 {
+                                compatible = "sirf,prima2-minigpsrtc";
+                                reg = <0x2000 0x1000>;
+                                interrupts = <54>;
+                        };
+
                         pwrc@3000 {
                                 compatible = "sirf,prima2-pwrc";
                                 reg = <0x3000 0x1000>;
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts
index 6e9deb786a7d..2a3b1c1313a0 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts
@@ -23,10 +23,15 @@
 
 &gpio {
         pinctrl-names = "default";
-        pinctrl-0 = <&alt0 &alt3>;
+        pinctrl-0 = <&gpioout &alt0 &alt3>;
+
+        gpioout: gpioout {
+                brcm,pins = <6>;
+                brcm,function = <1>; /* GPIO out */
+        };
 
         alt0: alt0 {
-                brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11 14 15 40 45>;
+                brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 14 15 40 45>;
                 brcm,function = <4>; /* alt0 */
         };
 
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
index aa537ed13f0a..b021c96d3ba1 100644
--- a/arch/arm/boot/dts/bcm2835.dtsi
+++ b/arch/arm/boot/dts/bcm2835.dtsi
@@ -107,6 +107,12 @@
                         clocks = <&clk_mmc>;
                         status = "disabled";
                 };
+
+                usb {
+                        compatible = "brcm,bcm2835-usb";
+                        reg = <0x7e980000 0x10000>;
+                        interrupts = <1 9>;
+                };
         };
 
         clocks {
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index 588ce58a2959..1e11e5a5f723 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -101,6 +101,9 @@
                         pinctrl-names = "default";
                         pinctrl-0 = <&mii_pins>;
                 };
+                gpio: gpio@1e26000 {
+                        status = "okay";
+                };
         };
         nand_cs3@62000000 {
                 status = "okay";
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 8d17346f9702..b695548dbb4e 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -8,6 +8,7 @@
  * option) any later version.
  */
 #include "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
         arm {
@@ -256,6 +257,19 @@
                                         36
                                         >;
                 };
+                gpio: gpio@1e26000 {
+                        compatible = "ti,dm6441-gpio";
+                        gpio-controller;
+                        reg = <0x226000 0x1000>;
+                        interrupts = <42 IRQ_TYPE_EDGE_BOTH
+                                43 IRQ_TYPE_EDGE_BOTH 44 IRQ_TYPE_EDGE_BOTH
+                                45 IRQ_TYPE_EDGE_BOTH 46 IRQ_TYPE_EDGE_BOTH
+                                47 IRQ_TYPE_EDGE_BOTH 48 IRQ_TYPE_EDGE_BOTH
+                                49 IRQ_TYPE_EDGE_BOTH 50 IRQ_TYPE_EDGE_BOTH>;
+                        ti,ngpio = <144>;
+                        ti,davinci-gpio-unbanked = <0>;
+                        status = "disabled";
+                };
         };
         nand_cs3@62000000 {
                 compatible = "ti,davinci-nand";
diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts
index 8349a248ecea..7a70f4ca502a 100644
--- a/arch/arm/boot/dts/dove-cubox.dts
+++ b/arch/arm/boot/dts/dove-cubox.dts
@@ -23,7 +23,7 @@
                 power {
                         label = "Power";
                         gpios = <&gpio0 18 1>;
-                        linux,default-trigger = "default-on";
+                        default-state = "keep";
                 };
         };
 
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 113a8bc7bee7..8de1031233ae 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -107,51 +107,29 @@
                                   0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800   /* CESA SRAM  2k */
                                   0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU  SRAM  2k */
 
-                        mbusc: mbus-ctrl@20000 {
-                                compatible = "marvell,mbus-controller";
-                                reg = <0x20000 0x80>, <0x800100 0x8>;
-                        };
-
-                        timer: timer@20300 {
-                                compatible = "marvell,orion-timer";
-                                reg = <0x20300 0x20>;
-                                interrupt-parent = <&bridge_intc>;
-                                interrupts = <1>, <2>;
+                        spi0: spi-ctrl@10600 {
+                                compatible = "marvell,orion-spi";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                cell-index = <0>;
+                                interrupts = <6>;
+                                reg = <0x10600 0x28>;
                                 clocks = <&core_clk 0>;
+                                pinctrl-0 = <&pmx_spi0>;
+                                pinctrl-names = "default";
+                                status = "disabled";
                         };
 
-                        intc: main-interrupt-ctrl@20200 {
-                                compatible = "marvell,orion-intc";
-                                interrupt-controller;
-                                #interrupt-cells = <1>;
-                                reg = <0x20200 0x10>, <0x20210 0x10>;
-                        };
-
-                        bridge_intc: bridge-interrupt-ctrl@20110 {
-                                compatible = "marvell,orion-bridge-intc";
-                                interrupt-controller;
-                                #interrupt-cells = <1>;
-                                reg = <0x20110 0x8>;
-                                interrupts = <0>;
-                                marvell,#interrupts = <5>;
-                        };
-
-                        core_clk: core-clocks@d0214 {
-                                compatible = "marvell,dove-core-clock";
-                                reg = <0xd0214 0x4>;
-                                #clock-cells = <1>;
-                        };
-
-                        gate_clk: clock-gating-ctrl@d0038 {
-                                compatible = "marvell,dove-gating-clock";
-                                reg = <0xd0038 0x4>;
+                        i2c0: i2c-ctrl@11000 {
+                                compatible = "marvell,mv64xxx-i2c";
+                                reg = <0x11000 0x20>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                interrupts = <11>;
+                                clock-frequency = <400000>;
+                                timeout-ms = <1000>;
                                 clocks = <&core_clk 0>;
-                                #clock-cells = <1>;
-                        };
-
-                        thermal: thermal-diode@d001c {
-                                compatible = "marvell,dove-thermal";
-                                reg = <0xd001c 0x0c>, <0xd005c 0x08>;
+                                status = "disabled";
                         };
 
                         uart0: serial@12000 {
@@ -192,34 +170,224 @@
                                 status = "disabled";
                         };
 
-                        gpio0: gpio-ctrl@d0400 {
-                                compatible = "marvell,orion-gpio";
-                                #gpio-cells = <2>;
-                                gpio-controller;
-                                reg = <0xd0400 0x20>;
-                                ngpios = <32>;
+                        spi1: spi-ctrl@14600 {
+                                compatible = "marvell,orion-spi";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                cell-index = <1>;
+                                interrupts = <5>;
+                                reg = <0x14600 0x28>;
+                                clocks = <&core_clk 0>;
+                                status = "disabled";
+                        };
+
+                        mbusc: mbus-ctrl@20000 {
+                                compatible = "marvell,mbus-controller";
+                                reg = <0x20000 0x80>, <0x800100 0x8>;
+                        };
+
+                        bridge_intc: bridge-interrupt-ctrl@20110 {
+                                compatible = "marvell,orion-bridge-intc";
                                 interrupt-controller;
-                                #interrupt-cells = <2>;
-                                interrupts = <12>, <13>, <14>, <60>;
+                                #interrupt-cells = <1>;
+                                reg = <0x20110 0x8>;
+                                interrupts = <0>;
+                                marvell,#interrupts = <5>;
                         };
 
-                        gpio1: gpio-ctrl@d0420 {
-                                compatible = "marvell,orion-gpio";
-                                #gpio-cells = <2>;
-                                gpio-controller;
-                                reg = <0xd0420 0x20>;
-                                ngpios = <32>;
+                        intc: main-interrupt-ctrl@20200 {
+                                compatible = "marvell,orion-intc";
                                 interrupt-controller;
-                                #interrupt-cells = <2>;
-                                interrupts = <61>;
+                                #interrupt-cells = <1>;
+                                reg = <0x20200 0x10>, <0x20210 0x10>;
                         };
 
-                        gpio2: gpio-ctrl@e8400 {
-                                compatible = "marvell,orion-gpio";
-                                #gpio-cells = <2>;
-                                gpio-controller;
-                                reg = <0xe8400 0x0c>;
-                                ngpios = <8>;
+                        timer: timer@20300 {
+                                compatible = "marvell,orion-timer";
+                                reg = <0x20300 0x20>;
+                                interrupt-parent = <&bridge_intc>;
+                                interrupts = <1>, <2>;
+                                clocks = <&core_clk 0>;
+                        };
+
+                        crypto: crypto-engine@30000 {
+                                compatible = "marvell,orion-crypto";
+                                reg = <0x30000 0x10000>,
+                                      <0xffffe000 0x800>;
+                                reg-names = "regs", "sram";
+                                interrupts = <31>;
+                                clocks = <&gate_clk 15>;
+                                status = "okay";
+                        };
+
+                        ehci0: usb-host@50000 {
+                                compatible = "marvell,orion-ehci";
+                                reg = <0x50000 0x1000>;
+                                interrupts = <24>;
+                                clocks = <&gate_clk 0>;
+                                status = "okay";
+                        };
+
+                        ehci1: usb-host@51000 {
+                                compatible = "marvell,orion-ehci";
+                                reg = <0x51000 0x1000>;
+                                interrupts = <25>;
+                                clocks = <&gate_clk 1>;
+                                status = "okay";
+                        };
+
+                        xor0: dma-engine@60800 {
+                                compatible = "marvell,orion-xor";
+                                reg = <0x60800 0x100
+                                       0x60a00 0x100>;
+                                clocks = <&gate_clk 23>;
+                                status = "okay";
+
+                                channel0 {
+                                        interrupts = <39>;
+                                        dmacap,memcpy;
+                                        dmacap,xor;
+                                };
+
+                                channel1 {
+                                        interrupts = <40>;
+                                        dmacap,memcpy;
+                                        dmacap,xor;
+                                };
+                        };
+
+                        xor1: dma-engine@60900 {
+                                compatible = "marvell,orion-xor";
+                                reg = <0x60900 0x100
+                                       0x60b00 0x100>;
+                                clocks = <&gate_clk 24>;
+                                status = "okay";
+
+                                channel0 {
+                                        interrupts = <42>;
+                                        dmacap,memcpy;
+                                        dmacap,xor;
+                                };
+
+                                channel1 {
+                                        interrupts = <43>;
+                                        dmacap,memcpy;
+                                        dmacap,xor;
+                                };
+                        };
+
+                        sdio1: sdio-host@90000 {
+                                compatible = "marvell,dove-sdhci";
+                                reg = <0x90000 0x100>;
+                                interrupts = <36>, <38>;
+                                clocks = <&gate_clk 9>;
+                                pinctrl-0 = <&pmx_sdio1>;
+                                pinctrl-names = "default";
+                                status = "disabled";
+                        };
+
+                        eth: ethernet-ctrl@72000 {
+                                compatible = "marvell,orion-eth";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                reg = <0x72000 0x4000>;
+                                clocks = <&gate_clk 2>;
+                                marvell,tx-checksum-limit = <1600>;
+                                status = "disabled";
+
+                                ethernet-port@0 {
+                                        device_type = "network";
+                                        compatible = "marvell,orion-eth-port";
+                                        reg = <0>;
+                                        interrupts = <29>;
+                                        /* overwrite MAC address in bootloader */
+                                        local-mac-address = [00 00 00 00 00 00];
+                                        phy-handle = <&ethphy>;
+                                };
+                        };
+
+                        mdio: mdio-bus@72004 {
+                                compatible = "marvell,orion-mdio";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                reg = <0x72004 0x84>;
+                                interrupts = <30>;
+                                clocks = <&gate_clk 2>;
+                                status = "disabled";
+
+                                ethphy: ethernet-phy {
+                                        device_type = "ethernet-phy";
+                                        /* set phy address in board file */
+                                };
+                        };
+
+                        sdio0: sdio-host@92000 {
+                                compatible = "marvell,dove-sdhci";
+                                reg = <0x92000 0x100>;
+                                interrupts = <35>, <37>;
+                                clocks = <&gate_clk 8>;
+                                pinctrl-0 = <&pmx_sdio0>;
+                                pinctrl-names = "default";
+                                status = "disabled";
+                        };
+
+                        sata0: sata-host@a0000 {
+                                compatible = "marvell,orion-sata";
+                                reg = <0xa0000 0x2400>;
+                                interrupts = <62>;
+                                clocks = <&gate_clk 3>;
+                                phys = <&sata_phy0>;
+                                phy-names = "port0";
+                                nr-ports = <1>;
+                                status = "disabled";
+                        };
+
+                        sata_phy0: sata-phy@a2000 {
+                                compatible = "marvell,mvebu-sata-phy";
+                                reg = <0xa2000 0x0334>;
+                                clocks = <&gate_clk 3>;
+                                clock-names = "sata";
+                                #phy-cells = <0>;
+                                status = "ok";
+                        };
+
+                        audio0: audio-controller@b0000 {
+                                compatible = "marvell,dove-audio";
+                                reg = <0xb0000 0x2210>;
+                                interrupts = <19>, <20>;
+                                clocks = <&gate_clk 12>;
+                                clock-names = "internal";
+                                status = "disabled";
+                        };
+
+                        audio1: audio-controller@b4000 {
+                                compatible = "marvell,dove-audio";
+                                reg = <0xb4000 0x2210>;
+                                interrupts = <21>, <22>;
+                                clocks = <&gate_clk 13>;
+                                clock-names = "internal";
+                                status = "disabled";
+                        };
+
+                        thermal: thermal-diode@d001c {
+                                compatible = "marvell,dove-thermal";
+                                reg = <0xd001c 0x0c>, <0xd005c 0x08>;
+                        };
+
+                        gate_clk: clock-gating-ctrl@d0038 {
+                                compatible = "marvell,dove-gating-clock";
+                                reg = <0xd0038 0x4>;
+                                clocks = <&core_clk 0>;
+                                #clock-cells = <1>;
+                        };
+
+                        pmu_intc: pmu-interrupt-ctrl@d0050 {
+                                compatible = "marvell,dove-pmu-intc";
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                reg = <0xd0050 0x8>;
+                                interrupts = <33>;
+                                marvell,#interrupts = <7>;
                         };
 
                         pinctrl: pin-ctrl@d0200 {
@@ -413,193 +581,47 @@
                                 };
                         };
 
-                        spi0: spi-ctrl@10600 {
-                                compatible = "marvell,orion-spi";
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                cell-index = <0>;
-                                interrupts = <6>;
-                                reg = <0x10600 0x28>;
-                                clocks = <&core_clk 0>;
-                                pinctrl-0 = <&pmx_spi0>;
-                                pinctrl-names = "default";
-                                status = "disabled";
-                        };
-
-                        spi1: spi-ctrl@14600 {
-                                compatible = "marvell,orion-spi";
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                cell-index = <1>;
-                                interrupts = <5>;
-                                reg = <0x14600 0x28>;
-                                clocks = <&core_clk 0>;
-                                status = "disabled";
-                        };
-
-                        i2c0: i2c-ctrl@11000 {
-                                compatible = "marvell,mv64xxx-i2c";
-                                reg = <0x11000 0x20>;
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                interrupts = <11>;
-                                clock-frequency = <400000>;
-                                timeout-ms = <1000>;
-                                clocks = <&core_clk 0>;
-                                status = "disabled";
-                        };
-
-                        ehci0: usb-host@50000 {
-                                compatible = "marvell,orion-ehci";
-                                reg = <0x50000 0x1000>;
-                                interrupts = <24>;
-                                clocks = <&gate_clk 0>;
-                                status = "okay";
-                        };
-
-                        ehci1: usb-host@51000 {
-                                compatible = "marvell,orion-ehci";
-                                reg = <0x51000 0x1000>;
-                                interrupts = <25>;
-                                clocks = <&gate_clk 1>;
-                                status = "okay";
-                        };
-
-                        sdio0: sdio-host@92000 {
-                                compatible = "marvell,dove-sdhci";
-                                reg = <0x92000 0x100>;
-                                interrupts = <35>, <37>;
-                                clocks = <&gate_clk 8>;
-                                pinctrl-0 = <&pmx_sdio0>;
-                                pinctrl-names = "default";
-                                status = "disabled";
+                        core_clk: core-clocks@d0214 {
+                                compatible = "marvell,dove-core-clock";
+                                reg = <0xd0214 0x4>;
+                                #clock-cells = <1>;
                         };
 
-                        sdio1: sdio-host@90000 {
-                                compatible = "marvell,dove-sdhci";
-                                reg = <0x90000 0x100>;
-                                interrupts = <36>, <38>;
-                                clocks = <&gate_clk 9>;
-                                pinctrl-0 = <&pmx_sdio1>;
-                                pinctrl-names = "default";
-                                status = "disabled";
+                        gpio0: gpio-ctrl@d0400 {
+                                compatible = "marvell,orion-gpio";
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                reg = <0xd0400 0x20>;
+                                ngpios = <32>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                interrupts = <12>, <13>, <14>, <60>;
                         };
 
-                        sata0: sata-host@a0000 {
-                                compatible = "marvell,orion-sata";
-                                reg = <0xa0000 0x2400>;
-                                interrupts = <62>;
-                                clocks = <&gate_clk 3>;
-                                nr-ports = <1>;
-                                status = "disabled";
+                        gpio1: gpio-ctrl@d0420 {
+                                compatible = "marvell,orion-gpio";
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                reg = <0xd0420 0x20>;
+                                ngpios = <32>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                interrupts = <61>;
                         };
 
                         rtc: real-time-clock@d8500 {
                                 compatible = "marvell,orion-rtc";
                                 reg = <0xd8500 0x20>;
+                                interrupt-parent = <&pmu_intc>;
+                                interrupts = <5>;
                         };
 
-                        crypto: crypto-engine@30000 {
-                                compatible = "marvell,orion-crypto";
-                                reg = <0x30000 0x10000>,
-                                      <0xffffe000 0x800>;
-                                reg-names = "regs", "sram";
-                                interrupts = <31>;
-                                clocks = <&gate_clk 15>;
-                                status = "okay";
-                        };
-
-                        xor0: dma-engine@60800 {
-                                compatible = "marvell,orion-xor";
-                                reg = <0x60800 0x100
-                                       0x60a00 0x100>;
-                                clocks = <&gate_clk 23>;
-                                status = "okay";
-
-                                channel0 {
-                                        interrupts = <39>;
-                                        dmacap,memcpy;
-                                        dmacap,xor;
-                                };
-
-                                channel1 {
-                                        interrupts = <40>;
-                                        dmacap,memcpy;
-                                        dmacap,xor;
-                                };
-                        };
-
-                        xor1: dma-engine@60900 {
-                                compatible = "marvell,orion-xor";
-                                reg = <0x60900 0x100
-                                       0x60b00 0x100>;
-                                clocks = <&gate_clk 24>;
-                                status = "okay";
-
-                                channel0 {
-                                        interrupts = <42>;
-                                        dmacap,memcpy;
-                                        dmacap,xor;
-                                };
-
-                                channel1 {
-                                        interrupts = <43>;
-                                        dmacap,memcpy;
-                                        dmacap,xor;
-                                };
-                        };
-
-                        mdio: mdio-bus@72004 {
-                                compatible = "marvell,orion-mdio";
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                reg = <0x72004 0x84>;
-                                interrupts = <30>;
-                                clocks = <&gate_clk 2>;
-                                status = "disabled";
-
-                                ethphy: ethernet-phy {
-                                        device-type = "ethernet-phy";
-                                        /* set phy address in board file */
-                                };
-                        };
-
-                        eth: ethernet-ctrl@72000 {
-                                compatible = "marvell,orion-eth";
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                reg = <0x72000 0x4000>;
-                                clocks = <&gate_clk 2>;
-                                marvell,tx-checksum-limit = <1600>;
-                                status = "disabled";
-
-                                ethernet-port@0 {
-                                        device_type = "network";
-                                        compatible = "marvell,orion-eth-port";
-                                        reg = <0>;
-                                        interrupts = <29>;
-                                        /* overwrite MAC address in bootloader */
-                                        local-mac-address = [00 00 00 00 00 00];
-                                        phy-handle = <&ethphy>;
-                                };
-                        };
-
-                        audio0: audio-controller@b0000 {
-                                compatible = "marvell,dove-audio";
-                                reg = <0xb0000 0x2210>;
-                                interrupts = <19>, <20>;
-                                clocks = <&gate_clk 12>;
-                                clock-names = "internal";
-                                status = "disabled";
-                        };
-
-                        audio1: audio-controller@b4000 {
-                                compatible = "marvell,dove-audio";
-                                reg = <0xb4000 0x2210>;
-                                interrupts = <21>, <22>;
-                                clocks = <&gate_clk 13>;
-                                clock-names = "internal";
-                                status = "disabled";
+                        gpio2: gpio-ctrl@e8400 {
+                                compatible = "marvell,orion-gpio";
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                reg = <0xe8400 0x0c>;
+                                ngpios = <8>;
                         };
                 };
         };
diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts
index 861aa7d6fc7d..50ccd151091e 100644
--- a/arch/arm/boot/dts/emev2-kzm9d.dts
+++ b/arch/arm/boot/dts/emev2-kzm9d.dts
@@ -9,7 +9,10 @@
  */
 /dts-v1/;
 
-/include/ "emev2.dtsi"
+#include "emev2.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
         model = "EMEV2 KZM9D Board";
@@ -47,11 +50,46 @@
                 reg = <0x20000000 0x10000>;
                 phy-mode = "mii";
                 interrupt-parent = <&gpio0>;
-                interrupts = <1 1>;     /* active high */
+                interrupts = <1 IRQ_TYPE_EDGE_RISING>;
                 reg-io-width = <4>;
                 smsc,irq-active-high;
                 smsc,irq-push-pull;
                 vddvario-supply = <&reg_1p8v>;
                 vdd33a-supply = <&reg_3p3v>;
         };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                button@1 {
+                        debounce_interval = <50>;
+                        wakeup = <1>;
+                        label = "DSW2-1";
+                        linux,code = <KEY_1>;
+                        gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+                };
+                button@2 {
+                        debounce_interval = <50>;
+                        wakeup = <1>;
+                        label = "DSW2-2";
+                        linux,code = <KEY_2>;
+                        gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
+                };
+                button@3 {
+                        debounce_interval = <50>;
+                        wakeup = <1>;
+                        label = "DSW2-3";
+                        linux,code = <KEY_3>;
+                        gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
+                };
+                button@4 {
+                        debounce_interval = <50>;
+                        wakeup = <1>;
+                        label = "DSW2-4";
+                        linux,code = <KEY_4>;
+                        gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi
index 9063a4434d6a..e37985fa10e2 100644
--- a/arch/arm/boot/dts/emev2.dtsi
+++ b/arch/arm/boot/dts/emev2.dtsi
@@ -8,7 +8,8 @@
  * kind, whether express or implied.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
         compatible = "renesas,emev2";
@@ -48,44 +49,129 @@
 
         pmu {
                 compatible = "arm,cortex-a9-pmu";
-                interrupts = <0 120 4>,
-                             <0 121 4>;
+                interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 121 IRQ_TYPE_LEVEL_HIGH>;
+        };
+
+        smu@e0110000 {
+                compatible = "renesas,emev2-smu";
+                reg = <0xe0110000 0x10000>;
+                #address-cells = <2>;
+                #size-cells = <0>;
+
+                c32ki: c32ki {
+                        compatible = "fixed-clock";
+                        clock-frequency = <32768>;
+                        #clock-cells = <0>;
+                };
+                pll3_fo: pll3_fo {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&c32ki>;
+                        clock-div = <1>;
+                        clock-mult = <7000>;
+                        #clock-cells = <0>;
+                };
+                usia_u0_sclkdiv: usia_u0_sclkdiv {
+                        compatible = "renesas,emev2-smu-clkdiv";
+                        reg = <0x610 0>;
+                        clocks = <&pll3_fo>;
+                        #clock-cells = <0>;
+                };
+                usib_u1_sclkdiv: usib_u1_sclkdiv {
+                        compatible = "renesas,emev2-smu-clkdiv";
+                        reg = <0x65c 0>;
+                        clocks = <&pll3_fo>;
+                        #clock-cells = <0>;
+                };
+                usib_u2_sclkdiv: usib_u2_sclkdiv {
+                        compatible = "renesas,emev2-smu-clkdiv";
+                        reg = <0x65c 16>;
+                        clocks = <&pll3_fo>;
+                        #clock-cells = <0>;
+                };
+                usib_u3_sclkdiv: usib_u3_sclkdiv {
+                        compatible = "renesas,emev2-smu-clkdiv";
+                        reg = <0x660 0>;
+                        clocks = <&pll3_fo>;
+                        #clock-cells = <0>;
+                };
+                usia_u0_sclk: usia_u0_sclk {
+                        compatible = "renesas,emev2-smu-gclk";
+                        reg = <0x4a0 1>;
+                        clocks = <&usia_u0_sclkdiv>;
+                        #clock-cells = <0>;
+                };
+                usib_u1_sclk: usib_u1_sclk {
+                        compatible = "renesas,emev2-smu-gclk";
+                        reg = <0x4b8 1>;
+                        clocks = <&usib_u1_sclkdiv>;
+                        #clock-cells = <0>;
+                };
+                usib_u2_sclk: usib_u2_sclk {
+                        compatible = "renesas,emev2-smu-gclk";
+                        reg = <0x4bc 1>;
+                        clocks = <&usib_u2_sclkdiv>;
+                        #clock-cells = <0>;
+                };
+                usib_u3_sclk: usib_u3_sclk {
+                        compatible = "renesas,emev2-smu-gclk";
+                        reg = <0x4c0 1>;
+                        clocks = <&usib_u3_sclkdiv>;
+                        #clock-cells = <0>;
+                };
+                sti_sclk: sti_sclk {
+                        compatible = "renesas,emev2-smu-gclk";
+                        reg = <0x528 1>;
+                        clocks = <&c32ki>;
+                        #clock-cells = <0>;
+                };
         };
 
         sti@e0180000 {
                 compatible = "renesas,em-sti";
                 reg = <0xe0180000 0x54>;
-                interrupts = <0 125 0>;
+                interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&sti_sclk>;
+                clock-names = "sclk";
         };
 
         uart@e1020000 {
                 compatible = "renesas,em-uart";
                 reg = <0xe1020000 0x38>;
-                interrupts = <0 8 0>;
+                interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&usia_u0_sclk>;
+                clock-names = "sclk";
         };
 
         uart@e1030000 {
                 compatible = "renesas,em-uart";
                 reg = <0xe1030000 0x38>;
-                interrupts = <0 9 0>;
+                interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&usib_u1_sclk>;
+                clock-names = "sclk";
         };
 
         uart@e1040000 {
                 compatible = "renesas,em-uart";
                 reg = <0xe1040000 0x38>;
-                interrupts = <0 10 0>;
+                interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&usib_u2_sclk>;
+                clock-names = "sclk";
         };
 
         uart@e1050000 {
                 compatible = "renesas,em-uart";
                 reg = <0xe1050000 0x38>;
-                interrupts = <0 11 0>;
+                interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&usib_u3_sclk>;
+                clock-names = "sclk";
         };
 
         gpio0: gpio@e0050000 {
                 compatible = "renesas,em-gio";
                 reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;
-                interrupts = <0 67 0>, <0 68 0>;
+                interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 68 IRQ_TYPE_LEVEL_HIGH>;
                 gpio-controller;
                 #gpio-cells = <2>;
                 ngpios = <32>;
@@ -95,7 +181,8 @@
         gpio1: gpio@e0050080 {
                 compatible = "renesas,em-gio";
                 reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>;
-                interrupts = <0 69 0>, <0 70 0>;
+                interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 70 IRQ_TYPE_LEVEL_HIGH>;
                 gpio-controller;
                 #gpio-cells = <2>;
                 ngpios = <32>;
@@ -105,7 +192,8 @@
         gpio2: gpio@e0050100 {
                 compatible = "renesas,em-gio";
                 reg = <0xe0050100 0x2c>, <0xe0050140 0x20>;
-                interrupts = <0 71 0>, <0 72 0>;
+                interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 72 IRQ_TYPE_LEVEL_HIGH>;
                 gpio-controller;
                 #gpio-cells = <2>;
                 ngpios = <32>;
@@ -115,7 +203,8 @@
         gpio3: gpio@e0050180 {
                 compatible = "renesas,em-gio";
                 reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>;
-                interrupts = <0 73 0>, <0 74 0>;
+                interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 74 IRQ_TYPE_LEVEL_HIGH>;
                 gpio-controller;
                 #gpio-cells = <2>;
                 ngpios = <32>;
@@ -125,7 +214,8 @@
         gpio4: gpio@e0050200 {
                 compatible = "renesas,em-gio";
                 reg = <0xe0050200 0x2c>, <0xe0050240 0x20>;
-                interrupts = <0 75 0>, <0 76 0>;
+                interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 76 IRQ_TYPE_LEVEL_HIGH>;
                 gpio-controller;
                 #gpio-cells = <2>;
                 ngpios = <31>;
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index a73eeb5f258f..08452e183b57 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -85,21 +85,21 @@
                 reg = <0x10023CE0 0x20>;
         };
 
-        gic:interrupt-controller@10490000 {
+        gic: interrupt-controller@10490000 {
                 compatible = "arm,cortex-a9-gic";
                 #interrupt-cells = <3>;
                 interrupt-controller;
                 reg = <0x10490000 0x1000>, <0x10480000 0x100>;
         };
 
-        combiner:interrupt-controller@10440000 {
+        combiner: interrupt-controller@10440000 {
                 compatible = "samsung,exynos4210-combiner";
                 #interrupt-cells = <2>;
                 interrupt-controller;
                 reg = <0x10440000 0x1000>;
         };
 
-        sys_reg: sysreg {
+        sys_reg: syscon@10010000 {
                 compatible = "samsung,exynos4-sysreg", "syscon";
                 reg = <0x10010000 0x400>;
         };
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 057d6829d319..48ecd7a755ab 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -36,11 +36,11 @@
                 reg = <0x10023CA0 0x20>;
         };
 
-        gic:interrupt-controller@10490000 {
+        gic: interrupt-controller@10490000 {
                 cpu-offset = <0x8000>;
         };
 
-        combiner:interrupt-controller@10440000 {
+        combiner: interrupt-controller@10440000 {
                 samsung,combiner-nr = <16>;
                 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
                              <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
@@ -51,24 +51,21 @@
         mct@10050000 {
                 compatible = "samsung,exynos4210-mct";
                 reg = <0x10050000 0x800>;
-                interrupt-controller;
-                #interrups-cells = <2>;
                 interrupt-parent = <&mct_map>;
-                interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
-                             <4 0>, <5 0>;
+                interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
                 clocks = <&clock 3>, <&clock 344>;
                 clock-names = "fin_pll", "mct";
 
                 mct_map: mct-map {
-                        #interrupt-cells = <2>;
+                        #interrupt-cells = <1>;
                         #address-cells = <0>;
                         #size-cells = <0>;
-                        interrupt-map = <0x0 0 &gic 0 57 0>,
-                                        <0x1 0 &gic 0 69 0>,
-                                        <0x2 0 &combiner 12 6>,
-                                        <0x3 0 &combiner 12 7>,
-                                        <0x4 0 &gic 0 42 0>,
-                                        <0x5 0 &gic 0 48 0>;
+                        interrupt-map = <0 &gic 0 57 0>,
+                                        <1 &gic 0 69 0>,
+                                        <2 &combiner 12 6>,
+                                        <3 &combiner 12 7>,
+                                        <4 &gic 0 42 0>,
+                                        <5 &gic 0 48 0>;
                 };
         };
 
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
index 6f34d7f6ba7e..94a43f9a05e2 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -22,7 +22,7 @@
 / {
         compatible = "samsung,exynos4212";
 
-        gic:interrupt-controller@10490000 {
+        gic: interrupt-controller@10490000 {
                 cpu-offset = <0x8000>;
         };
 
@@ -34,26 +34,4 @@
                              <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
                              <0 107 0>, <0 108 0>;
         };
-
-        mct@10050000 {
-                compatible = "samsung,exynos4412-mct";
-                reg = <0x10050000 0x800>;
-                interrupt-controller;
-                #interrups-cells = <2>;
-                interrupt-parent = <&mct_map>;
-                interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
-                             <4 0>, <5 0>;
-
-                mct_map: mct-map {
-                        #interrupt-cells = <2>;
-                        #address-cells = <0>;
-                        #size-cells = <0>;
-                        interrupt-map = <0x0 0 &gic 0 57 0>,
-                                        <0x1 0 &combiner 12 5>,
-                                        <0x2 0 &combiner 12 6>,
-                                        <0x3 0 &combiner 12 7>,
-                                        <0x4 0 &gic 1 12 0>,
-                                        <0x5 0 &gic 1 12 0>;
-                };
-        };
 };
diff --git a/arch/arm/boot/dts/exynos4412-tiny4412.dts b/arch/arm/boot/dts/exynos4412-tiny4412.dts
new file mode 100644
index 000000000000..0a9831256b33
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-tiny4412.dts
@@ -0,0 +1,93 @@
+/*
+ * FriendlyARM's Exynos4412 based TINY4412 board device tree source
+ *
+ * Copyright (c) 2013 Alex Ling <kasimling@gmail.com>
+ *
+ * Device tree source file for FriendlyARM's TINY4412 board which is based on
+ * Samsung's Exynos4412 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include "exynos4412.dtsi"
+
+/ {
+        model = "FriendlyARM TINY4412 board based on Exynos4412";
+        compatible = "friendlyarm,tiny4412", "samsung,exynos4412";
+
+        memory {
+                reg = <0x40000000 0x40000000>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                led1 {
+                        label = "led1";
+                        gpios = <&gpm4 0 1>;
+                        default-state = "off";
+                        linux,default-trigger = "heartbeat";
+                };
+
+                led2 {
+                        label = "led2";
+                        gpios = <&gpm4 1 1>;
+                        default-state = "off";
+                };
+
+                led3 {
+                        label = "led3";
+                        gpios = <&gpm4 2 1>;
+                        default-state = "off";
+                };
+
+                led4 {
+                        label = "led4";
+                        gpios = <&gpm4 3 1>;
+                        default-state = "off";
+                        linux,default-trigger = "mmc0";
+                };
+        };
+
+        rtc@10070000 {
+                status = "okay";
+        };
+
+        sdhci@12530000 {
+                bus-width = <4>;
+                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+                pinctrl-names = "default";
+                status = "okay";
+        };
+
+        serial@13800000 {
+                status = "okay";
+        };
+
+        serial@13810000 {
+                status = "okay";
+        };
+
+        serial@13820000 {
+                status = "okay";
+        };
+
+        serial@13830000 {
+                status = "okay";
+        };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <0>;
+                };
+
+                xusbxti {
+                        compatible = "samsung,clock-xusbxti";
+                        clock-frequency = <24000000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index 85812bd95a86..87b339c739de 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -22,7 +22,7 @@
 / {
         compatible = "samsung,exynos4412";
 
-        gic:interrupt-controller@10490000 {
+        gic: interrupt-controller@10490000 {
                 cpu-offset = <0x4000>;
         };
 
@@ -35,30 +35,4 @@
                              <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
         };
 
-        mct@10050000 {
-                compatible = "samsung,exynos4412-mct";
-                reg = <0x10050000 0x800>;
-                interrupt-controller;
-                #interrups-cells = <2>;
-                interrupt-parent = <&mct_map>;
-                interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
-                             <4 0>, <5 0>, <6 0>, <7 0>;
-                clocks = <&clock 3>, <&clock 344>;
-                clock-names = "fin_pll", "mct";
-
-                mct_map: mct-map {
-                        #interrupt-cells = <2>;
-                        #address-cells = <0>;
-                        #size-cells = <0>;
-                        interrupt-map = <0x0 0 &gic 0 57 0>,
-                                        <0x1 0 &combiner 12 5>,
-                                        <0x2 0 &combiner 12 6>,
-                                        <0x3 0 &combiner 12 7>,
-                                        <0x4 0 &gic 1 12 0>,
-                                        <0x5 0 &gic 1 12 0>,
-                                        <0x6 0 &gic 1 12 0>,
-                                        <0x7 0 &gic 1 12 0>;
-                };
-        };
-
 };
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index 1917c829e64e..5c412aa14738 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -42,6 +42,26 @@
                 #clock-cells = <1>;
         };
 
+        mct@10050000 {
+                compatible = "samsung,exynos4412-mct";
+                reg = <0x10050000 0x800>;
+                interrupt-parent = <&mct_map>;
+                interrupts = <0>, <1>, <2>, <3>, <4>;
+                clocks = <&clock 3>, <&clock 344>;
+                clock-names = "fin_pll", "mct";
+
+                mct_map: mct-map {
+                        #interrupt-cells = <1>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = <0 &gic 0 57 0>,
+                                        <1 &combiner 12 5>,
+                                        <2 &combiner 12 6>,
+                                        <3 &combiner 12 7>,
+                                        <4 &gic 1 12 0>;
+                };
+        };
+
         pinctrl_0: pinctrl@11400000 {
                 compatible = "samsung,exynos4x12-pinctrl";
                 reg = <0x11400000 0x1000>;
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 074739d39e2d..258dca441f36 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -23,7 +23,7 @@
                 reg = <0x10000000 0x100>;
         };
 
-        combiner:interrupt-controller@10440000 {
+        combiner: interrupt-controller@10440000 {
                 compatible = "samsung,exynos4210-combiner";
                 #interrupt-cells = <2>;
                 interrupt-controller;
@@ -39,7 +39,7 @@
                                 <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
         };
 
-        gic:interrupt-controller@10481000 {
+        gic: interrupt-controller@10481000 {
                 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
                 #interrupt-cells = <3>;
                 interrupt-controller;
@@ -50,27 +50,6 @@
                 interrupts = <1 9 0xf04>;
         };
 
-        dwmmc_0: dwmmc0@12200000 {
-                compatible = "samsung,exynos5250-dw-mshc";
-                interrupts = <0 75 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-        };
-
-        dwmmc_1: dwmmc1@12210000 {
-                compatible = "samsung,exynos5250-dw-mshc";
-                interrupts = <0 76 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-        };
-
-        dwmmc_2: dwmmc2@12220000 {
-                compatible = "samsung,exynos5250-dw-mshc";
-                interrupts = <0 77 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-        };
-
         serial@12C00000 {
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x12C00000 0x100>;
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index bbfb23f942e1..b42e658876e5 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -34,6 +34,7 @@
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <20000>;
                 samsung,i2c-slave-addr = <0x66>;
+                status = "okay";
 
                 s5m8767_pmic@66 {
                         compatible = "samsung,s5m8767-pmic";
@@ -266,7 +267,7 @@
 
                                 buck2_reg: BUCK2 {
                                         regulator-name = "vdd_arm";
-                                        regulator-min-microvolt = <925000>;
+                                        regulator-min-microvolt = <912500>;
                                         regulator-max-microvolt = <1300000>;
                                         regulator-always-on;
                                         regulator-boot-on;
@@ -321,11 +322,9 @@
                 };
         };
 
-        i2c@12C70000 {
-                status = "disabled";
-        };
-
         i2c@12C80000 {
+                status = "okay";
+
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <66000>;
                 samsung,i2c-slave-addr = <0x50>;
@@ -337,7 +336,10 @@
         };
 
         i2c@12C90000 {
+                status = "okay";
+
                 wm1811a@1a {
+
                         compatible = "wlf,wm1811";
                         reg = <0x1a>;
 
@@ -355,23 +357,9 @@
                 };
         };
 
-        i2c@12CA0000 {
-                status = "disabled";
-        };
-
-        i2c@12CB0000 {
-                status = "disabled";
-        };
-
-        i2c@12CC0000 {
-                status = "disabled";
-        };
-
-        i2c@12CD0000 {
-                status = "disabled";
-        };
-
         i2c@12CE0000 {
+                status = "okay";
+
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <66000>;
                 samsung,i2c-slave-addr = <0x38>;
@@ -382,15 +370,11 @@
                 };
         };
 
-        i2c@121D0000 {
-                status = "disabled";
-        };
-
-        dwmmc_0: dwmmc0@12200000 {
+        mmc_0: mmc@12200000 {
+                status = "okay";
                 num-slots = <1>;
                 supports-highspeed;
                 broken-cd;
-                fifo-depth = <0x80>;
                 card-detect-delay = <200>;
                 samsung,dw-mshc-ciu-div = <3>;
                 samsung,dw-mshc-sdr-timing = <2 3>;
@@ -405,14 +389,10 @@
                 };
         };
 
-        dwmmc_1: dwmmc1@12210000 {
-                status = "disabled";
-        };
-
-        dwmmc_2: dwmmc2@12220000 {
+        mmc_2: mmc@12220000 {
+                status = "okay";
                 num-slots = <1>;
                 supports-highspeed;
-                fifo-depth = <0x80>;
                 card-detect-delay = <200>;
                 samsung,dw-mshc-ciu-div = <3>;
                 samsung,dw-mshc-sdr-timing = <2 3>;
@@ -428,26 +408,10 @@
                 };
         };
 
-        dwmmc_3: dwmmc3@12230000 {
-                status = "disabled";
-        };
-
         i2s0: i2s@03830000 {
                 status = "okay";
         };
 
-        spi_0: spi@12d20000 {
-                status = "disabled";
-        };
-
-        spi_1: spi@12d30000 {
-                status = "disabled";
-        };
-
-        spi_2: spi@12d40000 {
-                status = "disabled";
-        };
-
         gpio_keys {
                 compatible = "gpio-keys";
 
diff --git a/arch/arm/boot/dts/cros5250-common.dtsi b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
index 9b186ac06c8b..9a61494f45f5 100644
--- a/arch/arm/boot/dts/cros5250-common.dtsi
+++ b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
@@ -37,6 +37,7 @@
         };
 
         i2c@12C60000 {
+                status = "okay";
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <378000>;
 
@@ -185,6 +186,7 @@
         };
 
         i2c@12C70000 {
+                status = "okay";
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <378000>;
 
@@ -198,6 +200,7 @@
         };
 
         i2c@12C80000 {
+                status = "okay";
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <66000>;
 
@@ -208,30 +211,31 @@
         };
 
         i2c@12C90000 {
+                status = "okay";
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <66000>;
         };
 
         i2c@12CA0000 {
+                status = "okay";
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <66000>;
         };
 
         i2c@12CB0000 {
+                status = "okay";
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <66000>;
         };
 
-        i2c@12CC0000 {
-                status = "disabled";
-        };
-
         i2c@12CD0000 {
+                status = "okay";
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <66000>;
         };
 
         i2c@12CE0000 {
+                status = "okay";
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <378000>;
 
@@ -241,11 +245,10 @@
                 };
         };
 
-        dwmmc0@12200000 {
+        mmc@12200000 {
                 num-slots = <1>;
                 supports-highspeed;
                 broken-cd;
-                fifo-depth = <0x80>;
                 card-detect-delay = <200>;
                 samsung,dw-mshc-ciu-div = <3>;
                 samsung,dw-mshc-sdr-timing = <2 3>;
@@ -259,14 +262,9 @@
                 };
         };
 
-        dwmmc1@12210000 {
-                status = "disabled";
-        };
-
-        dwmmc2@12220000 {
+        mmc@12220000 {
                 num-slots = <1>;
                 supports-highspeed;
-                fifo-depth = <0x80>;
                 card-detect-delay = <200>;
                 samsung,dw-mshc-ciu-div = <3>;
                 samsung,dw-mshc-sdr-timing = <2 3>;
@@ -281,11 +279,10 @@
                 };
         };
 
-        dwmmc3@12230000 {
+        mmc@12230000 {
                 num-slots = <1>;
                 supports-highspeed;
                 broken-cd;
-                fifo-depth = <0x80>;
                 card-detect-delay = <200>;
                 samsung,dw-mshc-ciu-div = <3>;
                 samsung,dw-mshc-sdr-timing = <2 3>;
@@ -298,19 +295,12 @@
                 };
         };
 
-        spi_0: spi@12d20000 {
-                status = "disabled";
-        };
-
         spi_1: spi@12d30000 {
+                status = "okay";
                 samsung,spi-src-clk = <0>;
                 num-cs = <1>;
         };
 
-        spi_2: spi@12d40000 {
-                status = "disabled";
-        };
-
         hdmi {
                 hpd-gpio = <&gpx3 7 0>;
         };
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index f86d56760a45..3e69837c435c 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -30,6 +30,7 @@
         i2c@12C60000 {
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <20000>;
+                status = "okay";
 
                 eeprom@50 {
                         compatible = "samsung,s524ad0xd1";
@@ -37,7 +38,7 @@
                 };
         };
 
-        vdd:fixed-regulator@0 {
+        vdd: fixed-regulator@0 {
                 compatible = "regulator-fixed";
                 regulator-name = "vdd-supply";
                 regulator-min-microvolt = <1800000>;
@@ -45,7 +46,7 @@
                 regulator-always-on;
         };
 
-        dbvdd:fixed-regulator@1 {
+        dbvdd: fixed-regulator@1 {
                 compatible = "regulator-fixed";
                 regulator-name = "dbvdd-supply";
                 regulator-min-microvolt = <3300000>;
@@ -53,7 +54,7 @@
                 regulator-always-on;
         };
 
-        spkvdd:fixed-regulator@2 {
+        spkvdd: fixed-regulator@2 {
                 compatible = "regulator-fixed";
                 regulator-name = "spkvdd-supply";
                 regulator-min-microvolt = <5000000>;
@@ -64,6 +65,7 @@
         i2c@12C70000 {
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <20000>;
+                status = "okay";
 
                 eeprom@51 {
                         compatible = "samsung,s524ad0xd1";
@@ -77,6 +79,9 @@
                         gpio-controller;
                         #gpio-cells = <2>;
 
+                        clocks = <&codec_mclk>;
+                        clock-names = "MCLK1";
+
                         AVDD2-supply = <&vdd>;
                         CPVDD-supply = <&vdd>;
                         DBVDD-supply = <&dbvdd>;
@@ -89,6 +94,7 @@
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <40000>;
                 samsung,i2c-slave-addr = <0x38>;
+                status = "okay";
 
                 sata-phy {
                         compatible = "samsung,sata-phy";
@@ -103,6 +109,7 @@
         i2c@12C80000 {
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <66000>;
+                status = "okay";
 
                 hdmiddc@50 {
                         compatible = "samsung,exynos4210-hdmiddc";
@@ -110,29 +117,10 @@
                 };
         };
 
-        i2c@12C90000 {
-                status = "disabled";
-        };
-
-        i2c@12CA0000 {
-                status = "disabled";
-        };
-
-        i2c@12CB0000 {
-                status = "disabled";
-        };
-
-        i2c@12CC0000 {
-                status = "disabled";
-        };
-
-        i2c@12CD0000 {
-                status = "disabled";
-        };
-
         i2c@12CE0000 {
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <66000>;
+                status = "okay";
 
                 hdmiphy@38 {
                         compatible = "samsung,exynos4212-hdmiphy";
@@ -140,11 +128,11 @@
                 };
         };
 
-        dwmmc0@12200000 {
+        mmc@12200000 {
+                status = "okay";
                 num-slots = <1>;
                 supports-highspeed;
                 broken-cd;
-                fifo-depth = <0x80>;
                 card-detect-delay = <200>;
                 samsung,dw-mshc-ciu-div = <3>;
                 samsung,dw-mshc-sdr-timing = <2 3>;
@@ -158,14 +146,10 @@
                 };
         };
 
-        dwmmc1@12210000 {
-                status = "disabled";
-        };
-
-        dwmmc2@12220000 {
+        mmc@12220000 {
+                status = "okay";
                 num-slots = <1>;
                 supports-highspeed;
-                fifo-depth = <0x80>;
                 card-detect-delay = <200>;
                 samsung,dw-mshc-ciu-div = <3>;
                 samsung,dw-mshc-sdr-timing = <2 3>;
@@ -180,15 +164,13 @@
                 };
         };
 
-        dwmmc3@12230000 {
-                status = "disabled";
-        };
-
         spi_0: spi@12d20000 {
                 status = "disabled";
         };
 
         spi_1: spi@12d30000 {
+                status = "okay";
+
                 w25q80bw@0 {
                         #address-cells = <1>;
                         #size-cells = <1>;
@@ -214,10 +196,6 @@
                 };
         };
 
-        spi_2: spi@12d40000 {
-                status = "disabled";
-        };
-
         hdmi {
                 hpd-gpio = <&gpx3 7 0>;
         };
@@ -279,5 +257,11 @@
                         compatible = "samsung,clock-xxti";
                         clock-frequency = <24000000>;
                 };
+
+                codec_mclk: codec-mclk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <16934000>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index c65f52a6dcea..7e45eea2d78f 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -10,7 +10,7 @@
 
 /dts-v1/;
 #include "exynos5250.dtsi"
-#include "cros5250-common.dtsi"
+#include "exynos5250-cros-common.dtsi"
 
 / {
         model = "Google Snow";
@@ -172,11 +172,20 @@
                 };
         };
 
+        mmc@12200000 {
+                status = "okay";
+        };
+
+        mmc@12220000 {
+                status = "okay";
+        };
+
         /*
          * On Snow we've got SIP WiFi and so can keep drive strengths low to
          * reduce EMI.
          */
-        dwmmc3@12230000 {
+        mmc@12230000 {
+                status = "okay";
                 slot@0 {
                         pinctrl-names = "default";
                         pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 6feaa1c454fa..587dd3e36f6c 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -33,10 +33,10 @@
                 gsc1 = &gsc_1;
                 gsc2 = &gsc_2;
                 gsc3 = &gsc_3;
-                mshc0 = &dwmmc_0;
-                mshc1 = &dwmmc_1;
-                mshc2 = &dwmmc_2;
-                mshc3 = &dwmmc_3;
+                mshc0 = &mmc_0;
+                mshc1 = &mmc_1;
+                mshc2 = &mmc_2;
+                mshc3 = &mmc_3;
                 i2c0 = &i2c_0;
                 i2c1 = &i2c_1;
                 i2c2 = &i2c_2;
@@ -244,6 +244,7 @@
                 clock-names = "i2c";
                 pinctrl-names = "default";
                 pinctrl-0 = <&i2c0_bus>;
+                status = "disabled";
         };
 
         i2c_1: i2c@12C70000 {
@@ -256,6 +257,7 @@
                 clock-names = "i2c";
                 pinctrl-names = "default";
                 pinctrl-0 = <&i2c1_bus>;
+                status = "disabled";
         };
 
         i2c_2: i2c@12C80000 {
@@ -268,6 +270,7 @@
                 clock-names = "i2c";
                 pinctrl-names = "default";
                 pinctrl-0 = <&i2c2_bus>;
+                status = "disabled";
         };
 
         i2c_3: i2c@12C90000 {
@@ -280,6 +283,7 @@
                 clock-names = "i2c";
                 pinctrl-names = "default";
                 pinctrl-0 = <&i2c3_bus>;
+                status = "disabled";
         };
 
         i2c_4: i2c@12CA0000 {
@@ -292,6 +296,7 @@
                 clock-names = "i2c";
                 pinctrl-names = "default";
                 pinctrl-0 = <&i2c4_bus>;
+                status = "disabled";
         };
 
         i2c_5: i2c@12CB0000 {
@@ -304,6 +309,7 @@
                 clock-names = "i2c";
                 pinctrl-names = "default";
                 pinctrl-0 = <&i2c5_bus>;
+                status = "disabled";
         };
 
         i2c_6: i2c@12CC0000 {
@@ -316,6 +322,7 @@
                 clock-names = "i2c";
                 pinctrl-names = "default";
                 pinctrl-0 = <&i2c6_bus>;
+                status = "disabled";
         };
 
         i2c_7: i2c@12CD0000 {
@@ -328,6 +335,7 @@
                 clock-names = "i2c";
                 pinctrl-names = "default";
                 pinctrl-0 = <&i2c7_bus>;
+                status = "disabled";
         };
 
         i2c_8: i2c@12CE0000 {
@@ -338,6 +346,7 @@
                 #size-cells = <0>;
                 clocks = <&clock 302>;
                 clock-names = "i2c";
+                status = "disabled";
         };
 
         i2c@121D0000 {
@@ -347,10 +356,12 @@
                 #size-cells = <0>;
                 clocks = <&clock 288>;
                 clock-names = "i2c";
+                status = "disabled";
         };
 
         spi_0: spi@12d20000 {
                 compatible = "samsung,exynos4210-spi";
+                status = "disabled";
                 reg = <0x12d20000 0x100>;
                 interrupts = <0 66 0>;
                 dmas = <&pdma0 5
@@ -366,6 +377,7 @@
 
         spi_1: spi@12d30000 {
                 compatible = "samsung,exynos4210-spi";
+                status = "disabled";
                 reg = <0x12d30000 0x100>;
                 interrupts = <0 67 0>;
                 dmas = <&pdma1 5
@@ -381,6 +393,7 @@
 
         spi_2: spi@12d40000 {
                 compatible = "samsung,exynos4210-spi";
+                status = "disabled";
                 reg = <0x12d40000 0x100>;
                 interrupts = <0 68 0>;
                 dmas = <&pdma0 7
@@ -394,25 +407,43 @@
                 pinctrl-0 = <&spi2_bus>;
         };
 
-        dwmmc_0: dwmmc0@12200000 {
+        mmc_0: mmc@12200000 {
+                compatible = "samsung,exynos5250-dw-mshc";
+                interrupts = <0 75 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
                 reg = <0x12200000 0x1000>;
                 clocks = <&clock 280>, <&clock 139>;
                 clock-names = "biu", "ciu";
+                fifo-depth = <0x80>;
+                status = "disabled";
         };
 
-        dwmmc_1: dwmmc1@12210000 {
+        mmc_1: mmc@12210000 {
+                compatible = "samsung,exynos5250-dw-mshc";
+                interrupts = <0 76 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
                 reg = <0x12210000 0x1000>;
                 clocks = <&clock 281>, <&clock 140>;
                 clock-names = "biu", "ciu";
+                fifo-depth = <0x80>;
+                status = "disabled";
         };
 
-        dwmmc_2: dwmmc2@12220000 {
+        mmc_2: mmc@12220000 {
+                compatible = "samsung,exynos5250-dw-mshc";
+                interrupts = <0 77 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
                 reg = <0x12220000 0x1000>;
                 clocks = <&clock 282>, <&clock 141>;
                 clock-names = "biu", "ciu";
+                fifo-depth = <0x80>;
+                status = "disabled";
         };
 
-        dwmmc_3: dwmmc3@12230000 {
+        mmc_3: mmc@12230000 {
                 compatible = "samsung,exynos5250-dw-mshc";
                 reg = <0x12230000 0x1000>;
                 interrupts = <0 78 0>;
@@ -420,6 +451,8 @@
                 #size-cells = <0>;
                 clocks = <&clock 283>, <&clock 142>;
                 clock-names = "biu", "ciu";
+                fifo-depth = <0x80>;
+                status = "disabled";
         };
 
         i2s0: i2s@03830000 {
@@ -528,6 +561,15 @@
                 };
         };
 
+        pwm: pwm@12dd0000 {
+                compatible = "samsung,exynos4210-pwm";
+                reg = <0x12dd0000 0x100>;
+                samsung,pwm-outputs = <0>, <1>, <2>, <3>;
+                #pwm-cells = <3>;
+                clocks = <&clock 311>;
+                clock-names = "timers";
+        };
+
         amba {
                 #address-cells = <1>;
                 #size-cells = <1>;
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
new file mode 100644
index 000000000000..7340745ff979
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -0,0 +1,66 @@
+/*
+ * Samsung's Exynos5420 based Arndale Octa board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include "exynos5420.dtsi"
+
+/ {
+        model = "Insignal Arndale Octa evaluation board based on EXYNOS5420";
+        compatible = "insignal,arndale-octa", "samsung,exynos5420";
+
+        memory {
+                reg = <0x20000000 0x80000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttySAC3,115200";
+        };
+
+        fixed-rate-clocks {
+                oscclk {
+                        compatible = "samsung,exynos5420-oscclk";
+                        clock-frequency = <24000000>;
+                };
+        };
+
+        mmc@12200000 {
+                status = "okay";
+                broken-cd;
+                supports-highspeed;
+                card-detect-delay = <200>;
+                samsung,dw-mshc-ciu-div = <3>;
+                samsung,dw-mshc-sdr-timing = <0 4>;
+                samsung,dw-mshc-ddr-timing = <0 2>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+
+                slot@0 {
+                        reg = <0>;
+                        bus-width = <8>;
+                };
+        };
+
+        mmc@12220000 {
+                status = "okay";
+                supports-highspeed;
+                card-detect-delay = <200>;
+                samsung,dw-mshc-ciu-div = <3>;
+                samsung,dw-mshc-sdr-timing = <2 3>;
+                samsung,dw-mshc-ddr-timing = <1 2>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+
+                slot@0 {
+                        reg = <0>;
+                        bus-width = <4>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 79524c74c603..fb5a1e25c632 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -31,6 +31,39 @@
                 };
         };
 
+        mmc@12200000 {
+                status = "okay";
+                broken-cd;
+                supports-highspeed;
+                card-detect-delay = <200>;
+                samsung,dw-mshc-ciu-div = <3>;
+                samsung,dw-mshc-sdr-timing = <0 4>;
+                samsung,dw-mshc-ddr-timing = <0 2>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+
+                slot@0 {
+                        reg = <0>;
+                        bus-width = <8>;
+                };
+        };
+
+        mmc@12220000 {
+                status = "okay";
+                supports-highspeed;
+                card-detect-delay = <200>;
+                samsung,dw-mshc-ciu-div = <3>;
+                samsung,dw-mshc-sdr-timing = <2 3>;
+                samsung,dw-mshc-ddr-timing = <1 2>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+
+                slot@0 {
+                        reg = <0>;
+                        bus-width = <4>;
+                };
+        };
+
         dp-controller@145B0000 {
                 pinctrl-names = "default";
                 pinctrl-0 = <&dp_hpd>;
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 09aa06cb3d3a..11dd202c54bb 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -22,6 +22,9 @@
         compatible = "samsung,exynos5420";
 
         aliases {
+                mshc0 = &mmc_0;
+                mshc1 = &mmc_1;
+                mshc2 = &mmc_2;
                 pinctrl0 = &pinctrl_0;
                 pinctrl1 = &pinctrl_1;
                 pinctrl2 = &pinctrl_2;
@@ -31,6 +34,18 @@
                 i2c1 = &i2c_1;
                 i2c2 = &i2c_2;
                 i2c3 = &i2c_3;
+                i2c4 = &hsi2c_4;
+                i2c5 = &hsi2c_5;
+                i2c6 = &hsi2c_6;
+                i2c7 = &hsi2c_7;
+                i2c8 = &hsi2c_8;
+                i2c9 = &hsi2c_9;
+                i2c10 = &hsi2c_10;
+                gsc0 = &gsc_0;
+                gsc1 = &gsc_1;
+                spi0 = &spi_0;
+                spi1 = &spi_1;
+                spi2 = &spi_2;
         };
 
         cpus {
@@ -64,6 +79,34 @@
                         reg = <0x3>;
                         clock-frequency = <1800000000>;
                 };
+
+                cpu4: cpu@100 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x100>;
+                        clock-frequency = <1000000000>;
+                };
+
+                cpu5: cpu@101 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x101>;
+                        clock-frequency = <1000000000>;
+                };
+
+                cpu6: cpu@102 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x102>;
+                        clock-frequency = <1000000000>;
+                };
+
+                cpu7: cpu@103 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x103>;
+                        clock-frequency = <1000000000>;
+                };
         };
 
         clock: clock-controller@10010000 {
@@ -88,13 +131,50 @@
                 clock-names = "mfc";
         };
 
+        mmc_0: mmc@12200000 {
+                compatible = "samsung,exynos5420-dw-mshc-smu";
+                interrupts = <0 75 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0x12200000 0x2000>;
+                clocks = <&clock 351>, <&clock 132>;
+                clock-names = "biu", "ciu";
+                fifo-depth = <0x40>;
+                status = "disabled";
+        };
+
+        mmc_1: mmc@12210000 {
+                compatible = "samsung,exynos5420-dw-mshc-smu";
+                interrupts = <0 76 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0x12210000 0x2000>;
+                clocks = <&clock 352>, <&clock 133>;
+                clock-names = "biu", "ciu";
+                fifo-depth = <0x40>;
+                status = "disabled";
+        };
+
+        mmc_2: mmc@12220000 {
+                compatible = "samsung,exynos5420-dw-mshc";
+                interrupts = <0 77 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0x12220000 0x1000>;
+                clocks = <&clock 353>, <&clock 134>;
+                clock-names = "biu", "ciu";
+                fifo-depth = <0x40>;
+                status = "disabled";
+        };
+
         mct@101C0000 {
                 compatible = "samsung,exynos4210-mct";
                 reg = <0x101C0000 0x800>;
                 interrupt-controller;
                 #interrups-cells = <1>;
                 interrupt-parent = <&mct_map>;
-                interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>;
+                interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
+                                <8>, <9>, <10>, <11>;
                 clocks = <&clock 1>, <&clock 315>;
                 clock-names = "fin_pll", "mct";
 
@@ -109,7 +189,11 @@
                                         <4 &gic 0 120 0>,
                                         <5 &gic 0 121 0>,
                                         <6 &gic 0 122 0>,
-                                        <7 &gic 0 123 0>;
+                                        <7 &gic 0 123 0>,
+                                        <8 &gic 0 128 0>,
+                                        <9 &gic 0 129 0>,
+                                        <10 &gic 0 130 0>,
+                                        <11 &gic 0 131 0>;
                 };
         };
 
@@ -190,6 +274,106 @@
                 status = "okay";
         };
 
+        amba {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "arm,amba-bus";
+                interrupt-parent = <&gic>;
+                ranges;
+
+                pdma0: pdma@121A0000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0x121A0000 0x1000>;
+                        interrupts = <0 34 0>;
+                        clocks = <&clock 362>;
+                        clock-names = "apb_pclk";
+                        #dma-cells = <1>;
+                        #dma-channels = <8>;
+                        #dma-requests = <32>;
+                };
+
+                pdma1: pdma@121B0000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0x121B0000 0x1000>;
+                        interrupts = <0 35 0>;
+                        clocks = <&clock 363>;
+                        clock-names = "apb_pclk";
+                        #dma-cells = <1>;
+                        #dma-channels = <8>;
+                        #dma-requests = <32>;
+                };
+
+                mdma0: mdma@10800000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0x10800000 0x1000>;
+                        interrupts = <0 33 0>;
+                        clocks = <&clock 473>;
+                        clock-names = "apb_pclk";
+                        #dma-cells = <1>;
+                        #dma-channels = <8>;
+                        #dma-requests = <1>;
+                };
+
+                mdma1: mdma@11C10000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0x11C10000 0x1000>;
+                        interrupts = <0 124 0>;
+                        clocks = <&clock 442>;
+                        clock-names = "apb_pclk";
+                        #dma-cells = <1>;
+                        #dma-channels = <8>;
+                        #dma-requests = <1>;
+                };
+        };
+
+        spi_0: spi@12d20000 {
+                compatible = "samsung,exynos4210-spi";
+                reg = <0x12d20000 0x100>;
+                interrupts = <0 66 0>;
+                dmas = <&pdma0 5
+                        &pdma0 4>;
+                dma-names = "tx", "rx";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&spi0_bus>;
+                clocks = <&clock 271>, <&clock 135>;
+                clock-names = "spi", "spi_busclk0";
+                status = "disabled";
+        };
+
+        spi_1: spi@12d30000 {
+                compatible = "samsung,exynos4210-spi";
+                reg = <0x12d30000 0x100>;
+                interrupts = <0 67 0>;
+                dmas = <&pdma1 5
+                        &pdma1 4>;
+                dma-names = "tx", "rx";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&spi1_bus>;
+                clocks = <&clock 272>, <&clock 136>;
+                clock-names = "spi", "spi_busclk0";
+                status = "disabled";
+        };
+
+        spi_2: spi@12d40000 {
+                compatible = "samsung,exynos4210-spi";
+                reg = <0x12d40000 0x100>;
+                interrupts = <0 68 0>;
+                dmas = <&pdma0 7
+                        &pdma0 6>;
+                dma-names = "tx", "rx";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&spi2_bus>;
+                clocks = <&clock 273>, <&clock 137>;
+                clock-names = "spi", "spi_busclk0";
+                status = "disabled";
+        };
+
         serial@12C00000 {
                 clocks = <&clock 257>, <&clock 128>;
                 clock-names = "uart", "clk_uart_baud0";
@@ -210,6 +394,15 @@
                 clock-names = "uart", "clk_uart_baud0";
         };
 
+        pwm: pwm@12dd0000 {
+                compatible = "samsung,exynos4210-pwm";
+                reg = <0x12dd0000 0x100>;
+                samsung,pwm-outputs = <0>, <1>, <2>, <3>;
+                #pwm-cells = <3>;
+                clocks = <&clock 279>;
+                clock-names = "timers";
+        };
+
         dp_phy: video-phy@10040728 {
                 compatible = "samsung,exynos5250-dp-video-phy";
                 reg = <0x10040728 4>;
@@ -292,6 +485,97 @@
                 status = "disabled";
         };
 
+        hsi2c_4: i2c@12CA0000 {
+                compatible = "samsung,exynos5-hsi2c";
+                reg = <0x12CA0000 0x1000>;
+                interrupts = <0 60 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c4_hs_bus>;
+                clocks = <&clock 265>;
+                clock-names = "hsi2c";
+                status = "disabled";
+        };
+
+        hsi2c_5: i2c@12CB0000 {
+                compatible = "samsung,exynos5-hsi2c";
+                reg = <0x12CB0000 0x1000>;
+                interrupts = <0 61 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c5_hs_bus>;
+                clocks = <&clock 266>;
+                clock-names = "hsi2c";
+                status = "disabled";
+        };
+
+        hsi2c_6: i2c@12CC0000 {
+                compatible = "samsung,exynos5-hsi2c";
+                reg = <0x12CC0000 0x1000>;
+                interrupts = <0 62 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c6_hs_bus>;
+                clocks = <&clock 267>;
+                clock-names = "hsi2c";
+                status = "disabled";
+        };
+
+        hsi2c_7: i2c@12CD0000 {
+                compatible = "samsung,exynos5-hsi2c";
+                reg = <0x12CD0000 0x1000>;
+                interrupts = <0 63 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c7_hs_bus>;
+                clocks = <&clock 268>;
+                clock-names = "hsi2c";
+                status = "disabled";
+        };
+
+        hsi2c_8: i2c@12E00000 {
+                compatible = "samsung,exynos5-hsi2c";
+                reg = <0x12E00000 0x1000>;
+                interrupts = <0 87 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c8_hs_bus>;
+                clocks = <&clock 281>;
+                clock-names = "hsi2c";
+                status = "disabled";
+        };
+
+        hsi2c_9: i2c@12E10000 {
+                compatible = "samsung,exynos5-hsi2c";
+                reg = <0x12E10000 0x1000>;
+                interrupts = <0 88 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c9_hs_bus>;
+                clocks = <&clock 282>;
+                clock-names = "hsi2c";
+                status = "disabled";
+        };
+
+        hsi2c_10: i2c@12E20000 {
+                compatible = "samsung,exynos5-hsi2c";
+                reg = <0x12E20000 0x1000>;
+                interrupts = <0 203 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c10_hs_bus>;
+                clocks = <&clock 283>;
+                clock-names = "hsi2c";
+                status = "disabled";
+        };
+
         hdmi@14530000 {
                 compatible = "samsung,exynos4212-hdmi";
                 reg = <0x14530000 0x70000>;
@@ -310,4 +594,62 @@
                 clocks = <&clock 431>, <&clock 143>;
                 clock-names = "mixer", "sclk_hdmi";
         };
+
+        gsc_0: video-scaler@13e00000 {
+                compatible = "samsung,exynos5-gsc";
+                reg = <0x13e00000 0x1000>;
+                interrupts = <0 85 0>;
+                clocks = <&clock 465>;
+                clock-names = "gscl";
+                samsung,power-domain = <&gsc_pd>;
+        };
+
+        gsc_1: video-scaler@13e10000 {
+                compatible = "samsung,exynos5-gsc";
+                reg = <0x13e10000 0x1000>;
+                interrupts = <0 86 0>;
+                clocks = <&clock 466>;
+                clock-names = "gscl";
+                samsung,power-domain = <&gsc_pd>;
+        };
+
+        tmu_cpu0: tmu@10060000 {
+                compatible = "samsung,exynos5420-tmu";
+                reg = <0x10060000 0x100>;
+                interrupts = <0 65 0>;
+                clocks = <&clock 318>;
+                clock-names = "tmu_apbif";
+        };
+
+        tmu_cpu1: tmu@10064000 {
+                compatible = "samsung,exynos5420-tmu";
+                reg = <0x10064000 0x100>;
+                interrupts = <0 183 0>;
+                clocks = <&clock 318>;
+                clock-names = "tmu_apbif";
+        };
+
+        tmu_cpu2: tmu@10068000 {
+                compatible = "samsung,exynos5420-tmu-ext-triminfo";
+                reg = <0x10068000 0x100>, <0x1006c000 0x4>;
+                interrupts = <0 184 0>;
+                clocks = <&clock 318>, <&clock 318>;
+                clock-names = "tmu_apbif", "tmu_triminfo_apbif";
+        };
+
+        tmu_cpu3: tmu@1006c000 {
+                compatible = "samsung,exynos5420-tmu-ext-triminfo";
+                reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
+                interrupts = <0 185 0>;
+                clocks = <&clock 318>, <&clock 319>;
+                clock-names = "tmu_apbif", "tmu_triminfo_apbif";
+        };
+
+        tmu_gpu: tmu@100a0000 {
+                compatible = "samsung,exynos5420-tmu-ext-triminfo";
+                reg = <0x100a0000 0x100>, <0x10068000 0x4>;
+                interrupts = <0 215 0>;
+                clocks = <&clock 319>, <&clock 318>;
+                clock-names = "tmu_apbif", "tmu_triminfo_apbif";
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index 8da107088ce4..02a0a1226cef 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -29,7 +29,7 @@
                 #clock-cells = <1>;
         };
 
-        gic:interrupt-controller@2E0000 {
+        gic: interrupt-controller@2E0000 {
                 compatible = "arm,cortex-a15-gic";
                 #interrupt-cells = <3>;
                 interrupt-controller;
diff --git a/arch/arm/boot/dts/integrator.dtsi b/arch/arm/boot/dts/integrator.dtsi
index 0f06f8687b0b..88e3d477bf16 100644
--- a/arch/arm/boot/dts/integrator.dtsi
+++ b/arch/arm/boot/dts/integrator.dtsi
@@ -10,6 +10,11 @@
                 reg = <0x10000000 0x200>;
         };
 
+        ebi@12000000 {
+                compatible = "arm,external-bus-interface";
+                reg = <0x12000000 0x100>;
+        };
+
         timer@13000000 {
                 reg = <0x13000000 0x100>;
                 interrupt-parent = <&pic>;
diff --git a/arch/arm/boot/dts/k2hk-evm.dts b/arch/arm/boot/dts/k2hk-evm.dts
new file mode 100644
index 000000000000..eaefdfef65c3
--- /dev/null
+++ b/arch/arm/boot/dts/k2hk-evm.dts
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2013 Texas Instruments, Inc.
+ *
+ * Keystone 2 Kepler/Hawking EVM device tree
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "keystone.dtsi"
+
+/ {
+        compatible =  "ti,keystone-evm";
+
+        soc {
+                clock {
+                        refclksys: refclksys {
+                                #clock-cells = <0>;
+                                compatible = "fixed-clock";
+                                clock-frequency = <122880000>;
+                                clock-output-names = "refclk-sys";
+                        };
+
+                        refclkpass: refclkpass {
+                                #clock-cells = <0>;
+                                compatible = "fixed-clock";
+                                clock-frequency = <122880000>;
+                                clock-output-names = "refclk-pass";
+                        };
+
+                        refclkarm: refclkarm {
+                                #clock-cells = <0>;
+                                compatible = "fixed-clock";
+                                clock-frequency = <125000000>;
+                                clock-output-names = "refclk-arm";
+                        };
+
+                        refclkddr3a: refclkddr3a {
+                                #clock-cells = <0>;
+                                compatible = "fixed-clock";
+                                clock-frequency = <100000000>;
+                                clock-output-names = "refclk-ddr3a";
+                        };
+
+                        refclkddr3b: refclkddr3b {
+                                #clock-cells = <0>;
+                                compatible = "fixed-clock";
+                                clock-frequency = <100000000>;
+                                clock-output-names = "refclk-ddr3b";
+                        };
+                };
+        };
+};
+
+&usb_phy {
+        status = "okay";
+};
+
+&usb {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/keystone-clocks.dtsi b/arch/arm/boot/dts/keystone-clocks.dtsi
index d6713b113258..2363593e1050 100644
--- a/arch/arm/boot/dts/keystone-clocks.dtsi
+++ b/arch/arm/boot/dts/keystone-clocks.dtsi
@@ -13,17 +13,10 @@ clocks {
         #size-cells = <1>;
         ranges;
 
-        refclkmain: refclkmain {
-                #clock-cells = <0>;
-                compatible = "fixed-clock";
-                clock-frequency = <122880000>;
-                clock-output-names = "refclk-main";
-        };
-
         mainpllclk: mainpllclk@2310110 {
                 #clock-cells = <0>;
                 compatible = "ti,keystone,main-pll-clock";
-                clocks = <&refclkmain>;
+                clocks = <&refclksys>;
                 reg = <0x02620350 4>, <0x02310110 4>;
                 reg-names = "control", "multiplier";
                 fixed-postdiv = <2>;
@@ -32,47 +25,43 @@ clocks {
         papllclk: papllclk@2620358 {
                 #clock-cells = <0>;
                 compatible = "ti,keystone,pll-clock";
-                clocks = <&refclkmain>;
+                clocks = <&refclkpass>;
                 clock-output-names = "pa-pll-clk";
                 reg = <0x02620358 4>;
                 reg-names = "control";
-                fixed-postdiv = <6>;
         };
 
-        ddr3allclk: ddr3apllclk@2620360 {
+        ddr3apllclk: ddr3apllclk@2620360 {
                 #clock-cells = <0>;
                 compatible = "ti,keystone,pll-clock";
-                clocks = <&refclkmain>;
+                clocks = <&refclkddr3a>;
                 clock-output-names = "ddr-3a-pll-clk";
                 reg = <0x02620360 4>;
                 reg-names = "control";
-                fixed-postdiv = <6>;
         };
 
-        ddr3bllclk: ddr3bpllclk@2620368 {
+        ddr3bpllclk: ddr3bpllclk@2620368 {
                 #clock-cells = <0>;
                 compatible = "ti,keystone,pll-clock";
-                clocks = <&refclkmain>;
+                clocks = <&refclkddr3b>;
                 clock-output-names = "ddr-3b-pll-clk";
                 reg = <0x02620368 4>;
                 reg-names = "control";
-                fixed-postdiv = <6>;
         };
 
         armpllclk: armpllclk@2620370 {
                 #clock-cells = <0>;
                 compatible = "ti,keystone,pll-clock";
-                clocks = <&refclkmain>;
+                clocks = <&refclkarm>;
                 clock-output-names = "arm-pll-clk";
                 reg = <0x02620370 4>;
                 reg-names = "control";
-                fixed-postdiv = <6>;
         };
 
         mainmuxclk: mainmuxclk@2310108 {
                 #clock-cells = <0>;
                 compatible = "ti,keystone,pll-mux-clock";
-                clocks = <&mainpllclk>, <&refclkmain>;
+                clocks = <&mainpllclk>, <&refclksys>;
                 reg = <0x02310108 4>;
                 bit-shift = <23>;
                 bit-mask = <1>;
@@ -135,6 +124,15 @@ clocks {
                 clock-output-names = "chipclk13";
         };
 
+        paclk13: paclk13 {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&papllclk>;
+                clock-div = <3>;
+                clock-mult = <1>;
+                clock-output-names = "paclk13";
+        };
+
         chipclk14: chipclk14 {
                 #clock-cells = <0>;
                 compatible = "fixed-factor-clock";
diff --git a/arch/arm/boot/dts/keystone.dts b/arch/arm/boot/dts/keystone.dtsi
index 100bdf52b847..b4202907a27b 100644
--- a/arch/arm/boot/dts/keystone.dts
+++ b/arch/arm/boot/dts/keystone.dtsi
@@ -6,14 +6,12 @@
  * published by the Free Software Foundation.
  */
 
-/dts-v1/;
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
 #include "skeleton.dtsi"
 
 / {
         model = "Texas Instruments Keystone 2 SoC";
-        compatible =  "ti,keystone-evm";
         #address-cells = <2>;
         #size-cells = <2>;
         interrupt-parent = <&gic>;
@@ -64,7 +62,11 @@
                 #address-cells = <1>;
                 interrupt-controller;
                 reg = <0x0 0x02561000 0x0 0x1000>,
-                      <0x0 0x02562000 0x0 0x2000>;
+                      <0x0 0x02562000 0x0 0x2000>,
+                      <0x0 0x02564000 0x0 0x1000>,
+                      <0x0 0x02566000 0x0 0x2000>;
+                interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
+                                IRQ_TYPE_LEVEL_HIGH)>;
         };
 
         timer {
@@ -179,5 +181,32 @@
                         interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>;
                         clocks = <&clkspi>;
                 };
+
+                usb_phy: usb_phy@2620738 {
+                        compatible = "ti,keystone-usbphy";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x2620738 32>;
+                        status = "disabled";
+                };
+
+                usb: usb@2680000 {
+                        compatible = "ti,keystone-dwc3";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x2680000 0x10000>;
+                        clocks = <&clkusb>;
+                        clock-names = "usb";
+                        interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
+                        ranges;
+                        status = "disabled";
+
+                        dwc3@2690000 {
+                                compatible = "synopsys,dwc3";
+                                reg = <0x2690000 0x70000>;
+                                interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
+                                usb-phy = <&usb_phy>, <&usb_phy>;
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-6192.dtsi b/arch/arm/boot/dts/kirkwood-6192.dtsi
new file mode 100644
index 000000000000..3916937d6818
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-6192.dtsi
@@ -0,0 +1,107 @@
+/ {
+        mbus {
+                pcie-controller {
+                        compatible = "marvell,kirkwood-pcie";
+                        status = "disabled";
+                        device_type = "pci";
+
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+
+                        bus-range = <0x00 0xff>;
+
+                        ranges =
+                               <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
+                                0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */
+                                0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */>;
+
+                        pcie@1,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
+                                reg = <0x0800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &intc 9>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gate_clk 2>;
+                                status = "disabled";
+                        };
+                };
+        };
+
+        ocp@f1000000 {
+                pinctrl: pinctrl@10000 {
+                        compatible = "marvell,88f6192-pinctrl";
+                        reg = <0x10000 0x20>;
+
+                        pmx_nand: pmx-nand {
+                                marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
+                                               "mpp4", "mpp5", "mpp18",
+                                               "mpp19";
+                                marvell,function = "nand";
+                        };
+                        pmx_sata0: pmx-sata0 {
+                                marvell,pins = "mpp5", "mpp21", "mpp23";
+                                marvell,function = "sata0";
+                        };
+                        pmx_sata1: pmx-sata1 {
+                                marvell,pins = "mpp4", "mpp20", "mpp22";
+                                marvell,function = "sata1";
+                        };
+                        pmx_spi: pmx-spi {
+                                marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3";
+                                marvell,function = "spi";
+                        };
+                        pmx_twsi0: pmx-twsi0 {
+                                marvell,pins = "mpp8", "mpp9";
+                                marvell,function = "twsi0";
+                        };
+                        pmx_uart0: pmx-uart0 {
+                                marvell,pins = "mpp10", "mpp11";
+                                marvell,function = "uart0";
+                        };
+                        pmx_uart1: pmx-uart1 {
+                                marvell,pins = "mpp13", "mpp14";
+                                marvell,function = "uart1";
+                        };
+                        pmx_sdio: pmx-sdio {
+                                marvell,pins = "mpp12", "mpp13", "mpp14",
+                                               "mpp15", "mpp16", "mpp17";
+                                marvell,function = "sdio";
+                        };
+                };
+
+                rtc@10300 {
+                        compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
+                        reg = <0x10300 0x20>;
+                        interrupts = <53>;
+                        clocks = <&gate_clk 7>;
+                };
+
+                sata@80000 {
+                        compatible = "marvell,orion-sata";
+                        reg = <0x80000 0x5000>;
+                        interrupts = <21>;
+                        clocks = <&gate_clk 14>, <&gate_clk 15>;
+                        clock-names = "0", "1";
+                        status = "disabled";
+                };
+
+                mvsdio@90000 {
+                        compatible = "marvell,orion-sdio";
+                        reg = <0x90000 0x200>;
+                        interrupts = <28>;
+                        clocks = <&gate_clk 4>;
+                        bus-width = <4>;
+                        cap-sdio-irq;
+                        cap-sd-highspeed;
+                        cap-mmc-highspeed;
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi
index 650ef30e1856..416d96e1302f 100644
--- a/arch/arm/boot/dts/kirkwood-6281.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6281.dtsi
@@ -89,6 +89,8 @@
                         interrupts = <21>;
                         clocks = <&gate_clk 14>, <&gate_clk 15>;
                         clock-names = "0", "1";
+                        phys = <&sata_phy0>, <&sata_phy1>;
+                        phy-names = "port0", "port1";
                         status = "disabled";
                 };
 
@@ -97,6 +99,8 @@
                         reg = <0x90000 0x200>;
                         interrupts = <28>;
                         clocks = <&gate_clk 4>;
+                        pinctrl-0 = <&pmx_sdio>;
+                        pinctrl-names = "default";
                         bus-width = <4>;
                         cap-sdio-irq;
                         cap-sd-highspeed;
diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi
index 3933a331ddc2..2902e0d7971d 100644
--- a/arch/arm/boot/dts/kirkwood-6282.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6282.dtsi
@@ -104,6 +104,12 @@
                         };
                 };
 
+                thermal@10078 {
+                        compatible = "marvell,kirkwood-thermal";
+                        reg = <0x10078 0x4>;
+                        status = "okay";
+                };
+
                 rtc@10300 {
                         compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
                         reg = <0x10300 0x20>;
@@ -111,12 +117,25 @@
                         clocks = <&gate_clk 7>;
                 };
 
+                i2c@11100 {
+                        compatible = "marvell,mv64xxx-i2c";
+                        reg = <0x11100 0x20>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        interrupts = <32>;
+                        clock-frequency = <100000>;
+                        clocks = <&gate_clk 7>;
+                        status = "disabled";
+                };
+
                 sata@80000 {
                         compatible = "marvell,orion-sata";
                         reg = <0x80000 0x5000>;
                         interrupts = <21>;
                         clocks = <&gate_clk 14>, <&gate_clk 15>;
                         clock-names = "0", "1";
+                        phys = <&sata_phy0>, <&sata_phy1>;
+                        phy-names = "port0", "port1";
                         status = "disabled";
                 };
 
@@ -125,29 +144,13 @@
                         reg = <0x90000 0x200>;
                         interrupts = <28>;
                         clocks = <&gate_clk 4>;
+                        pinctrl-0 = <&pmx_sdio>;
+                        pinctrl-names = "default";
                         bus-width = <4>;
                         cap-sdio-irq;
                         cap-sd-highspeed;
                         cap-mmc-highspeed;
                         status = "disabled";
                 };
-
-                thermal@10078 {
-                        compatible = "marvell,kirkwood-thermal";
-                        reg = <0x10078 0x4>;
-                        status = "okay";
-                };
-
-                i2c@11100 {
-                        compatible = "marvell,mv64xxx-i2c";
-                        reg = <0x11100 0x20>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        interrupts = <32>;
-                        clock-frequency = <100000>;
-                        clocks = <&gate_clk 7>;
-                        status = "disabled";
-                };
-
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-cloudbox.dts b/arch/arm/boot/dts/kirkwood-cloudbox.dts
index 142b9cd3b454..bb4df405527c 100644
--- a/arch/arm/boot/dts/kirkwood-cloudbox.dts
+++ b/arch/arm/boot/dts/kirkwood-cloudbox.dts
@@ -66,8 +66,8 @@
 
                 button@1 {
                         label = "Power push button";
-                        linux,code = <116>;
-                        gpios = <&gpio0 16 1>;
+                        linux,code = <KEY_POWER>;
+                        gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
                 };
         };
 
@@ -76,17 +76,17 @@
 
                 red-fail {
                         label = "cloudbox:red:fail";
-                        gpios = <&gpio0 14 0>;
+                        gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
                 };
                 blue-sata {
                         label = "cloudbox:blue:sata";
-                        gpios = <&gpio0 15 0>;
+                        gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
                 };
         };
 
         gpio_poweroff {
                 compatible = "gpio-poweroff";
-                gpios = <&gpio0 17 0>;
+                gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
         };
 };
 
diff --git a/arch/arm/boot/dts/kirkwood-db.dtsi b/arch/arm/boot/dts/kirkwood-db.dtsi
index 053aa20fb30f..afebc1570318 100644
--- a/arch/arm/boot/dts/kirkwood-db.dtsi
+++ b/arch/arm/boot/dts/kirkwood-db.dtsi
@@ -51,8 +51,8 @@
                 mvsdio@90000 {
                         pinctrl-0 = <&pmx_sdio_gpios>;
                         pinctrl-names = "default";
-                        wp-gpios = <&gpio1 5 0>;
-                        cd-gpios = <&gpio1 6 0>;
+                        wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+                        cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
                         status = "okay";
                 };
         };
diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts
index e112ca62d978..bf7fe8ab88f4 100644
--- a/arch/arm/boot/dts/kirkwood-dns320.dts
+++ b/arch/arm/boot/dts/kirkwood-dns320.dts
@@ -24,24 +24,24 @@
 
                 blue-power {
                         label = "dns320:blue:power";
-                        gpios = <&gpio0 26 1>; /* GPIO 26 Active Low */
-                        linux,default-trigger = "default-on";
+                        gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
+                        default-state = "keep";
                 };
                 blue-usb {
                         label = "dns320:blue:usb";
-                        gpios = <&gpio1 11 1>; /* GPIO 43 Active Low */
+                        gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
                 };
                 orange-l_hdd {
                         label = "dns320:orange:l_hdd";
-                        gpios = <&gpio0 28 1>; /* GPIO 28 Active Low */
+                        gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
                 };
                 orange-r_hdd {
                         label = "dns320:orange:r_hdd";
-                        gpios = <&gpio0 27 1>; /* GPIO 27 Active Low */
+                        gpios = <&gpio0 27 GPIO_ACTIVE_LOW>;
                 };
                 orange-usb {
                         label = "dns320:orange:usb";
-                        gpios = <&gpio1 3 1>; /* GPIO 35 Active Low */
+                        gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; /* GPIO 35 */
                 };
         };
 
diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts b/arch/arm/boot/dts/kirkwood-dns325.dts
index 5119fb8a8eb6..cb9978c652f2 100644
--- a/arch/arm/boot/dts/kirkwood-dns325.dts
+++ b/arch/arm/boot/dts/kirkwood-dns325.dts
@@ -24,24 +24,24 @@
 
                 white-power {
                         label = "dns325:white:power";
-                        gpios = <&gpio0 26 1>; /* GPIO 26 Active Low */
-                        linux,default-trigger = "default-on";
+                        gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
+                        default-state = "keep";
                 };
                 white-usb {
                         label = "dns325:white:usb";
-                        gpios = <&gpio1 11 1>; /* GPIO 43 Active Low */
+                        gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; /* GPIO 43 */
                 };
                 red-l_hdd {
                         label = "dns325:red:l_hdd";
-                        gpios = <&gpio0 28 1>; /* GPIO 28 Active Low */
+                        gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
                 };
                 red-r_hdd {
                         label = "dns325:red:r_hdd";
-                        gpios = <&gpio0 27 1>; /* GPIO 27 Active Low */
+                        gpios = <&gpio0 27 GPIO_ACTIVE_LOW>;
                 };
                 red-usb {
                         label = "dns325:red:usb";
-                        gpios = <&gpio0 29 1>; /* GPIO 29 Active Low */
+                        gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
                 };
         };
 
diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
index aefa375a550d..12087566ac6d 100644
--- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi
+++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
@@ -15,18 +15,18 @@
 
                 button@1 {
                         label = "Power button";
-                        linux,code = <116>;
-                        gpios = <&gpio1 2 1>;
+                        linux,code = <KEY_POWER>;
+                        gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
                 };
                 button@2 {
                         label = "USB unmount button";
-                        linux,code = <161>;
-                        gpios = <&gpio1 15 1>;
+                        linux,code = <KEY_EJECTCD>;
+                        gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
                 };
                 button@3 {
                         label = "Reset button";
-                        linux,code = <0x198>;
-                        gpios = <&gpio1 16 1>;
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
                 };
         };
 
@@ -35,8 +35,8 @@
                 compatible = "gpio-fan";
                 pinctrl-0 = <&pmx_fan_high_speed &pmx_fan_low_speed>;
                 pinctrl-names = "default";
-                gpios = <&gpio1 14 1
-                         &gpio1 13 1>;
+                gpios = <&gpio1 14 GPIO_ACTIVE_LOW
+                         &gpio1 13 GPIO_ACTIVE_LOW>;
                 gpio-fan,speed-map = <0    0
                                       3000 1
                                       6000 2>;
@@ -46,7 +46,7 @@
                 compatible = "gpio-poweroff";
                 pinctrl-0 = <&pmx_power_off>;
                 pinctrl-names = "default";
-                gpios = <&gpio1 4 0>;
+                gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
         };
 
         ocp@f1000000 {
diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts
index 33ff368fbfa5..2a41c75c5c21 100644
--- a/arch/arm/boot/dts/kirkwood-dockstar.dts
+++ b/arch/arm/boot/dts/kirkwood-dockstar.dts
@@ -42,12 +42,12 @@
 
                 health {
                         label = "status:green:health";
-                        gpios = <&gpio1 14 1>;
-                        linux,default-trigger = "default-on";
+                        gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+                        default-state = "keep";
                 };
                 fault {
                         label = "status:orange:fault";
-                        gpios = <&gpio1 15 1>;
+                        gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
                 };
         };
         regulators {
diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
index 6f62af99c9cb..a7558375e06f 100644
--- a/arch/arm/boot/dts/kirkwood-dreamplug.dts
+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
@@ -87,15 +87,15 @@
 
                 bluetooth {
                         label = "dreamplug:blue:bluetooth";
-                        gpios = <&gpio1 15 1>;
+                        gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
                 };
                 wifi {
                         label = "dreamplug:green:wifi";
-                        gpios = <&gpio1 16 1>;
+                        gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
                 };
                 wifi-ap {
                         label = "dreamplug:green:wifi_ap";
-                        gpios = <&gpio1 17 1>;
+                        gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts
index a43bebb25110..c2e512953570 100644
--- a/arch/arm/boot/dts/kirkwood-goflexnet.dts
+++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts
@@ -85,44 +85,44 @@
 
                 health {
                         label = "status:green:health";
-                        gpios = <&gpio1 14 1>;
-                        linux,default-trigger = "default-on";
+                        gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+                        default-state = "keep";
                 };
                 fault {
                         label = "status:orange:fault";
-                        gpios = <&gpio1 15 1>;
+                        gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
                 };
                 left0 {
                         label = "status:white:left0";
-                        gpios = <&gpio1 10 0>;
+                        gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
                 };
                 left1 {
                         label = "status:white:left1";
-                        gpios = <&gpio1 11 0>;
+                        gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
                 };
                 left2 {
                         label = "status:white:left2";
-                        gpios = <&gpio1 12 0>;
+                        gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
                 };
                 left3 {
                         label = "status:white:left3";
-                        gpios = <&gpio1 13 0>;
+                        gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
                 };
                 right0 {
                         label = "status:white:right0";
-                        gpios = <&gpio1 6 0>;
+                        gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
                 };
                 right1 {
                         label = "status:white:right1";
-                        gpios = <&gpio1 7 0>;
+                        gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
                 };
                 right2 {
                         label = "status:white:right2";
-                        gpios = <&gpio1 8 0>;
+                        gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
                 };
                 right3 {
                         label = "status:white:right3";
-                        gpios = <&gpio1 9 0>;
+                        gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
                 };
         };
         regulators {
@@ -141,7 +141,7 @@
                         enable-active-high;
                         regulator-always-on;
                         regulator-boot-on;
-                        gpio = <&gpio0 29 0>;
+                        gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
index d30a91a5047d..0b557d5cb723 100644
--- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
+++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
@@ -45,10 +45,10 @@
                         nr-ports = <1>;
                 };
 
+                /* AzureWave AW-GH381 WiFi/BT */
                 mvsdio@90000 {
                         status = "okay";
-                        /* No CD or WP GPIOs */
-                        broken-cd;
+                        non-removable;
                 };
         };
 
@@ -60,19 +60,19 @@
 
                 health-r {
                         label = "guruplug:red:health";
-                        gpios = <&gpio1 14 1>;
+                        gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
                 };
                 health-g {
                         label = "guruplug:green:health";
-                        gpios = <&gpio1 15 1>;
+                        gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
                 };
                 wmode-r {
                         label = "guruplug:red:wmode";
-                        gpios = <&gpio1 16 1>;
+                        gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
                 };
                 wmode-g {
                         label = "guruplug:green:wmode";
-                        gpios = <&gpio1 17 1>;
+                        gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts
index c5fb02f7ebc3..6ccc78866e6d 100644
--- a/arch/arm/boot/dts/kirkwood-ib62x0.dts
+++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts
@@ -63,13 +63,13 @@
 
                 button@1 {
                         label = "USB Copy";
-                        linux,code = <133>;
-                        gpios = <&gpio0 29 1>;
+                        linux,code = <KEY_COPY>;
+                        gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
                 };
                 button@2 {
                         label = "Reset";
-                        linux,code = <0x198>;
-                        gpios = <&gpio0 28 1>;
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
                 };
         };
 
@@ -81,16 +81,16 @@
 
                 green-os {
                         label = "ib62x0:green:os";
-                        gpios = <&gpio0 25 0>;
-                        linux,default-trigger = "default-on";
+                        gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
+                        default-state = "keep";
                 };
                 red-os {
                         label = "ib62x0:red:os";
-                        gpios = <&gpio0 22 0>;
+                        gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
                 };
                 usb-copy {
                         label = "ib62x0:red:usb_copy";
-                        gpios = <&gpio0 27 0>;
+                        gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>;
                 };
         };
 
@@ -98,7 +98,7 @@
                 compatible = "gpio-poweroff";
                 pinctrl-0 = <&pmx_power_off>;
                 pinctrl-names = "default";
-                gpios = <&gpio0 24 0>;
+                gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
         };
 };
 
diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts
index 4a62b206f680..f7636291de77 100644
--- a/arch/arm/boot/dts/kirkwood-iconnect.dts
+++ b/arch/arm/boot/dts/kirkwood-iconnect.dts
@@ -94,37 +94,37 @@
 
                 led-level {
                         label = "led_level";
-                        gpios = <&gpio1 9 0>;
-                        linux,default-trigger = "default-on";
+                        gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+                        default-state = "on";
                 };
                 power-blue {
                         label = "power:blue";
-                        gpios = <&gpio1 10 0>;
-                        linux,default-trigger = "timer";
+                        gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+                        default-state = "keep";
                 };
                 power-red {
                         label = "power:red";
-                        gpios = <&gpio1 11 0>;
+                        gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
                 };
                 usb1 {
                         label = "usb1:blue";
-                        gpios = <&gpio1 12 0>;
+                        gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
                 };
                 usb2 {
                         label = "usb2:blue";
-                        gpios = <&gpio1 13 0>;
+                        gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
                 };
                 usb3 {
                         label = "usb3:blue";
-                        gpios = <&gpio1 14 0>;
+                        gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
                 };
                 usb4 {
                         label = "usb4:blue";
-                        gpios = <&gpio1 15 0>;
+                        gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
                 };
                 otb {
                         label = "otb:blue";
-                        gpios = <&gpio1 16 0>;
+                        gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
                 };
         };
 
@@ -137,14 +137,14 @@
 
                 button@1 {
                         label = "OTB Button";
-                        linux,code = <133>;
-                        gpios = <&gpio1 3 1>;
+                        linux,code = <KEY_COPY>;
+                        gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
                         debounce-interval = <100>;
                 };
                 button@2 {
                         label = "Reset";
-                        linux,code = <0x198>;
-                        gpios = <&gpio0 12 1>;
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
                         debounce-interval = <100>;
                 };
         };
diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
index d15395d671ed..589000631b5a 100644
--- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
+++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
@@ -127,20 +127,20 @@
 
                 power_led {
                         label = "status:white:power_led";
-                        gpios = <&gpio0 16 0>;
-                        linux,default-trigger = "default-on";
+                        gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
+                        default-state = "keep";
                 };
                 rebuild_led {
                         label = "status:white:rebuild_led";
-                        gpios = <&gpio1 4 0>;
+                        gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
                 };
                 health_led {
                         label = "status:red:health_led";
-                        gpios = <&gpio1 5 0>;
+                        gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
                 };
                 backup_led {
                         label = "status:blue:backup_led";
-                        gpios = <&gpio0 15 0>;
+                        gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
                 };
         };
         gpio-keys {
@@ -154,18 +154,18 @@
 
                 Power {
                         label = "Power Button";
-                        linux,code = <116>;
-                        gpios = <&gpio0 14 1>;
+                        linux,code = <KEY_POWER>;
+                        gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
                 };
                 Reset {
                         label = "Reset Button";
-                        linux,code = <0x198>;
-                        gpios = <&gpio0 12 1>;
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
                 };
                 OTB {
                         label = "OTB Button";
-                        linux,code = <133>;
-                        gpios = <&gpio1 3 1>;
+                        linux,code = <KEY_COPY>;
+                        gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
index cd44f37e54b5..5b5808ebc6e0 100644
--- a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
+++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
@@ -38,8 +38,8 @@
 
         i2c@0 {
                 compatible = "i2c-gpio";
-                gpios = < &gpio0 8 0            /* sda */
-                        &gpio0 9 0 >;           /* scl */
+                gpios = < &gpio0 8 GPIO_ACTIVE_HIGH             /* sda */
+                          &gpio0 9 GPIO_ACTIVE_HIGH>;           /* scl */
                 i2c-gpio,delay-us = <2>;        /* ~100 kHz */
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-laplug.dts b/arch/arm/boot/dts/kirkwood-laplug.dts
new file mode 100644
index 000000000000..c9e82eff9bf2
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-laplug.dts
@@ -0,0 +1,175 @@
+/*
+ * Copyright (C) 2013 Maxime Hadjinlian <maxime.hadjinlian@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "kirkwood.dtsi"
+#include "kirkwood-6192.dtsi"
+
+/ {
+        model = "LaCie LaPlug";
+        compatible = "lacie,laplug", "marvell,kirkwood-88f6192", "marvell,kirkwood";
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x8000000>; /* 128 MB */
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+
+        mbus {
+                pcie-controller {
+                        status = "okay";
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
+        };
+
+        ocp@f1000000 {
+                serial@12000 {
+                        pinctrl-0 = <&pmx_uart0>;
+                        pinctrl-names = "default";
+                        status = "okay";
+                };
+
+                i2c@11000 {
+                        pinctrl-0 = <&pmx_twsi0>;
+                        pinctrl-names = "default";
+                        status = "okay";
+
+                        eeprom@50 {
+                                compatible = "at,24c04";
+                                pagesize = <16>;
+                                reg = <0x50>;
+                        };
+                };
+
+                pinctrl: pinctrl@10000 {
+                        pmx_usb_power_enable: pmx-usb-power-enable {
+                                marvell,pins = "mpp14";
+                                marvell,function = "gpio";
+                        };
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+
+                button@1{
+                        label = "Power push button";
+                        linux,code = <KEY_POWER>;
+                        gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
+                };
+        };
+
+        gpio-leds {
+                compatible = "gpio-leds";
+
+                red-fail {
+                        label = "laplug_v2:red:power";
+                        gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+                };
+                blue-power {
+                        label = "laplug_v2:blue:power";
+                        gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "default-on";
+                };
+        };
+
+        gpio_poweroff {
+                compatible = "gpio-poweroff";
+                gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>;
+        };
+
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-0 = <&pmx_usb_power_enable>;
+                pinctrl-names = "default";
+
+                usb_power_back1: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "USB Power Back 1";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>;
+                };
+
+                usb_power_back2: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "USB Power Back 2";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio0 28 GPIO_ACTIVE_HIGH>;
+                };
+
+                usb_power_front: regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "USB Power Front";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+                };
+        };
+};
+
+&nand {
+        /* Total size : 512MB */
+        status = "okay";
+        pinctrl-0 = <&pmx_nand>;
+
+        partition@0 {
+                label = "u-boot";
+                reg = <0x0 0x100000>; /* 1MB */
+                read-only;
+        };
+
+        partition@100000 {
+                label = "uImage";
+                reg = <0x100000 0x1000000>; /* 16MB */
+        };
+
+        partition@1100000 {
+                label = "rootfs";
+                reg = <0x1100000 0x1EF00000>; /* 495MB */
+        };
+};
+
+&mdio {
+        status = "okay";
+
+        ethphy0: ethernet-phy@0 {
+                device_type = "ethernet-phy";
+                reg = <0>;
+        };
+};
+
+&eth0 {
+        status = "okay";
+        ethernet0-port@0 {
+                phy-handle = <&ethphy0>;
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
index 4e8f9e42c592..fc1cd3b7b968 100644
--- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi
+++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
@@ -108,20 +108,20 @@
 
                 button@1 {
                         label = "Function Button";
-                        linux,code = <357>;
-                        gpios = <&gpio1 9 1>;
+                        linux,code = <KEY_OPTION>;
+                        gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
                 };
                 button@2 {
                         label = "Power-on Switch";
-                        linux,code = <0>;
+                        linux,code = <KEY_RESERVED>;
                         linux,input-type = <5>;
-                        gpios = <&gpio1 10 1>;
+                        gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
                 };
                 button@3 {
                         label = "Power-auto Switch";
-                        linux,code = <1>;
+                        linux,code = <KEY_ESC>;
                         linux,input-type = <5>;
-                        gpios = <&gpio1 11 1>;
+                        gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
                 };
         };
 
@@ -134,28 +134,28 @@
 
                 led@1 {
                         label = "lsxl:blue:func";
-                        gpios = <&gpio1 4 1>;
+                        gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
                 };
 
                 led@2 {
                         label = "lsxl:red:alarm";
-                        gpios = <&gpio1 5 1>;
+                        gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
                 };
 
                 led@3 {
                         label = "lsxl:amber:info";
-                        gpios = <&gpio1 6 1>;
+                        gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
                 };
 
                 led@4 {
                         label = "lsxl:blue:power";
-                        gpios = <&gpio1 7 1>;
-                        linux,default-trigger = "default-on";
+                        gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
+                        default-state = "keep";
                 };
 
                 led@5 {
                         label = "lsxl:red:func";
-                        gpios = <&gpio1 16 1>;
+                        gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
                 };
         };
 
@@ -163,13 +163,13 @@
                 compatible = "gpio-fan";
                 pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>;
                 pinctrl-names = "default";
-                gpios = <&gpio0 19 1
-                         &gpio0 18 1>;
+                gpios = <&gpio0 19 GPIO_ACTIVE_LOW
+                         &gpio0 18 GPIO_ACTIVE_LOW>;
                 gpio-fan,speed-map = <0    3
                                       1500 2
                                       3250 1
                                       5000 0>;
-                alarm-gpios = <&gpio1 8 0>;
+                alarm-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
         };
 
         restart_poweroff {
diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts
index 6c1ec2786e6e..c20607cd7d7c 100644
--- a/arch/arm/boot/dts/kirkwood-mplcec4.dts
+++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts
@@ -110,7 +110,7 @@
                         pinctrl-0 = <&pmx_sdio &pmx_sdio_cd>;
                         pinctrl-names = "default";
                         status = "okay";
-                        cd-gpios = <&gpio1 15 1>;
+                        cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
                         /* No WP GPIO */
                 };
         };
@@ -126,36 +126,36 @@
 
                 health {
                         label = "status:green:health";
-                        gpios = <&gpio0 7 1>;
+                        gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
                 };
 
                 user1o {
                         label = "user1:orange";
-                        gpios = <&gpio1 8 1>;
+                        gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
                         default-state = "on";
                 };
 
                 user1g {
                         label = "user1:green";
-                        gpios = <&gpio1 9 1>;
+                        gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
                         default-state = "on";
                 };
 
                 user0o {
                         label = "user0:orange";
-                        gpios = <&gpio1 12 1>;
+                        gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
                         default-state = "on";
                 };
 
                 user0g {
                         label = "user0:green";
-                        gpios = <&gpio1 13 1>;
+                        gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
                         default-state = "on";
                 };
 
                 misc {
                         label = "status:orange:misc";
-                        gpios = <&gpio1 14 1>;
+                        gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
                         default-state = "on";
                 };
 
diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
index 6317e1d088b3..dc86429756d7 100644
--- a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
+++ b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
@@ -90,17 +90,17 @@
 
                 green-status {
                         label = "gtw:green:Status";
-                        gpios = <&gpio0 20 0>;
+                        gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
                 };
 
                 red-status {
                         label = "gtw:red:Status";
-                        gpios = <&gpio0 21 0>;
+                        gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
                 };
 
                 green-usb {
                         label = "gtw:green:USB";
-                        gpios = <&gpio0 12 0>;
+                        gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
                 };
         };
 
@@ -113,13 +113,13 @@
 
                 button@1 {
                         label = "SWR Button";
-                        linux,code = <0x198>; /* KEY_RESTART */
-                        gpios = <&gpio1 15 1>;
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
                 };
                 button@2 {
                         label = "WPS Button";
-                        linux,code = <0x211>; /* KEY_WPS_BUTTON */
-                        gpios = <&gpio1 14 1>;
+                        linux,code = <KEY_WPS_BUTTON>;
+                        gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
index e6a102cf424c..4d2a8db9ab77 100644
--- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
+++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
@@ -1,3 +1,14 @@
+/*
+ * Device Tree file for NETGEAR ReadyNAS Duo v2
+ *
+ * Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
 /dts-v1/;
 
 #include "kirkwood.dtsi"
@@ -32,41 +43,50 @@
                                 marvell,pins = "mpp47";
                                 marvell,function = "gpio";
                         };
+
                         pmx_button_backup: pmx-button-backup {
                                 marvell,pins = "mpp45";
                                 marvell,function = "gpio";
                         };
+
                         pmx_button_reset: pmx-button-reset {
                                 marvell,pins = "mpp13";
                                 marvell,function = "gpio";
                         };
+
                         pmx_led_blue_power: pmx-led-blue-power {
                                 marvell,pins = "mpp31";
                                 marvell,function = "gpio";
                         };
+
                         pmx_led_blue_activity: pmx-led-blue-activity {
                                 marvell,pins = "mpp38";
                                 marvell,function = "gpio";
                         };
+
                         pmx_led_blue_disk1: pmx-led-blue-disk1 {
                                 marvell,pins = "mpp23";
                                 marvell,function = "gpio";
                         };
+
                         pmx_led_blue_disk2: pmx-led-blue-disk2 {
                                 marvell,pins = "mpp22";
                                 marvell,function = "gpio";
                         };
+
                         pmx_led_blue_backup: pmx-led-blue-backup {
                                 marvell,pins = "mpp29";
                                 marvell,function = "gpio";
                         };
+
+                        pmx_poweroff: pmx-poweroff {
+                                marvell,pins = "mpp30";
+                                marvell,function = "gpio";
+                        };
                 };
 
                 clocks {
-                       #address-cells = <1>;
-                       #size-cells = <0>;
-
-                       g762_clk: fixedclk {
+                       g762_clk: g762-oscillator {
                                  compatible = "fixed-clock";
                                  #clock-cells = <0>;
                                  clock-frequency = <8192>;
@@ -112,69 +132,80 @@
 
                 power_led {
                         label = "status:blue:power_led";
-                        gpios = <&gpio0 31 1>;   /* GPIO 31 Active Low */
-                        linux,default-trigger = "default-on";
+                        gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
+                        default-state = "keep";
                 };
+
                 activity_led {
                         label = "status:blue:activity_led";
-                        gpios = <&gpio1 6 1>;    /* GPIO 38 Active Low */
+                        gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
                 };
+
                 disk1_led {
                         label = "status:blue:disk1_led";
-                        gpios = <&gpio0 23 1>;   /* GPIO 23 Active Low */
+                        gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
                 };
+
                 disk2_led {
                         label = "status:blue:disk2_led";
-                        gpios = <&gpio0 22 1>;   /* GPIO 22 Active Low */
+                        gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
                 };
+
                 backup_led {
                         label = "status:blue:backup_led";
-                        gpios = <&gpio0 29 1>;   /* GPIO 29 Active Low*/
+                        gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
                 };
         };
 
-        gpio_keys {
+        gpio-keys {
                 compatible = "gpio-keys";
-                #address-cells = <1>;
-                #size-cells = <0>;
                 pinctrl-0 = <&pmx_button_power &pmx_button_backup
                              &pmx_button_reset>;
                 pinctrl-names = "default";
 
-                button@1 {
+                power-button {
                         label = "Power Button";
-                        linux,code = <116>;     /* KEY_POWER */
-                        gpios = <&gpio1 15 1>;
+                        linux,code = <KEY_POWER>;
+                        gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
                 };
-                button@2 {
+
+                reset-button {
                         label = "Reset Button";
-                        linux,code = <0x198>;   /* KEY_RESTART */
-                        gpios = <&gpio0 13 1>;
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
                 };
-                button@3 {
+
+                backup-button {
                         label = "Backup Button";
-                        linux,code = <133>;     /* KEY_COPY */
-                        gpios = <&gpio1 13 1>;
+                        linux,code = <KEY_COPY>;
+                        gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
                 };
         };
 
-        regulators {
-                compatible = "simple-bus";
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                usb_power: regulator@1 {
-                        compatible = "regulator-fixed";
-                        reg = <1>;
-                        regulator-name = "USB 3.0 Power";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                        enable-active-high;
-                        regulator-always-on;
-                        regulator-boot-on;
-                        gpio = <&gpio1 14 0>;
-                };
-        };
+        gpio-poweroff {
+                compatible = "gpio-poweroff";
+                pinctrl-0 = <&pmx_poweroff>;
+                pinctrl-names = "default";
+                gpios = <&gpio0 30 GPIO_ACTIVE_LOW>;
+        };
+
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                usb3_regulator: usb3-regulator {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "USB 3.0 Power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+                };
+        };
 };
 
 &nand {
@@ -210,7 +241,7 @@
 &mdio {
         status = "okay";
 
-        ethphy0: ethernet-phy@0 {
+        ethphy0: ethernet-phy@0 { /* Marvell 88E1318 */
                 device_type = "ethernet-phy";
                 reg = <0>;
         };
diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts
new file mode 100644
index 000000000000..7c8a0d9d8d1f
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts
@@ -0,0 +1,268 @@
+/*
+ * Device Tree file for NETGEAR ReadyNAS NV+ v2
+ *
+ * Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+/dts-v1/;
+
+#include "kirkwood.dtsi"
+#include "kirkwood-6282.dtsi"
+
+/ {
+        model = "NETGEAR ReadyNAS NV+ v2";
+        compatible = "netgear,readynas-nv+-v2", "netgear,readynas", "marvell,kirkwood-88f6282", "marvell,kirkwood";
+
+        memory { /* 256 MB */
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+
+        mbus {
+                pcie-controller {
+                        status = "okay";
+
+                        /* Connected to NEC uPD720200 USB 3.0 controller */
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+                };
+        };
+
+        ocp@f1000000 {
+                pinctrl: pinctrl@10000 {
+                        pmx_button_power: pmx-button-power {
+                                marvell,pins = "mpp47";
+                                marvell,function = "gpio";
+                        };
+
+                        pmx_button_backup: pmx-button-backup {
+                                marvell,pins = "mpp45";
+                                marvell,function = "gpio";
+                        };
+
+                        pmx_button_reset: pmx-button-reset {
+                                marvell,pins = "mpp13";
+                                marvell,function = "gpio";
+                        };
+
+                        pmx_led_blue_power: pmx-led-blue-power {
+                                marvell,pins = "mpp31";
+                                marvell,function = "gpio";
+                        };
+
+                        pmx_led_blue_backup: pmx-led-blue-backup {
+                                marvell,pins = "mpp22";
+                                marvell,function = "gpio";
+                        };
+
+                        pmx_led_blue_disk1: pmx-led-blue-disk1 {
+                                marvell,pins = "mpp20";
+                                marvell,function = "gpio";
+                        };
+
+                        pmx_led_blue_disk2: pmx-led-blue-disk2 {
+                                marvell,pins = "mpp23";
+                                marvell,function = "gpio";
+                        };
+
+                        pmx_led_blue_disk3: pmx-led-blue-disk3 {
+                                marvell,pins = "mpp24";
+                                marvell,function = "gpio";
+                        };
+
+                        pmx_led_blue_disk4: pmx-led-blue-disk4 {
+                                marvell,pins = "mpp29";
+                                marvell,function = "gpio";
+                        };
+
+                        pmx_poweroff: pmx-poweroff {
+                                marvell,pins = "mpp30";
+                                marvell,function = "gpio";
+                        };
+                };
+
+                clocks {
+                       g762_clk: g762-oscillator {
+                                 compatible = "fixed-clock";
+                                 #clock-cells = <0>;
+                                 clock-frequency = <8192>;
+                       };
+                };
+
+                i2c@11000 {
+                        status = "okay";
+
+                        rs5c372a: rs5c372a@32 {
+                                compatible = "ricoh,rs5c372a";
+                                reg = <0x32>;
+                        };
+
+                        g762: g762@3e {
+                                compatible = "gmt,g762";
+                                reg = <0x3e>;
+                                clocks = <&g762_clk>; /* input clock */
+                                fan_gear_mode = <0>;
+                                fan_startv = <1>;
+                                pwm_polarity = <0>;
+                        };
+                };
+
+                serial@12000 {
+                        pinctrl-0 = <&pmx_uart0>;
+                        pinctrl-names = "default";
+                        status = "okay";
+                };
+
+                sata@80000 { /* Connected to Marvell 88SM4140 SATA port multiplier */
+                        status = "okay";
+                        nr-ports = <1>;
+                };
+        };
+
+        gpio-leds {
+                compatible = "gpio-leds";
+                pinctrl-0 = < &pmx_led_blue_power &pmx_led_blue_backup
+                              &pmx_led_blue_disk1 &pmx_led_blue_disk2
+                              &pmx_led_blue_disk3 &pmx_led_blue_disk3 >;
+                pinctrl-names = "default";
+
+                power_led {
+                        label = "status:blue:power_led";
+                        gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-on";
+                };
+
+                backup_led {
+                        label = "status:blue:backup_led";
+                        gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
+                };
+
+                disk1_led {
+                        label = "status:blue:disk1_led";
+                        gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
+                };
+
+                disk2_led {
+                        label = "status:blue:disk2_led";
+                        gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
+                };
+
+                disk3_led {
+                        label = "status:blue:disk3_led";
+                        gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
+                };
+
+                disk4_led {
+                        label = "status:blue:disk4_led";
+                        gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
+                };
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                pinctrl-0 = <&pmx_button_power &pmx_button_backup
+                             &pmx_button_reset>;
+                pinctrl-names = "default";
+
+                power-button {
+                        label = "Power Button";
+                        linux,code = <KEY_POWER>;
+                        gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+                };
+
+                reset-button {
+                        label = "Reset Button";
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
+                };
+
+                backup-button {
+                        label = "Backup Button";
+                        linux,code = <KEY_COPY>;
+                        gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
+                };
+        };
+
+        gpio-poweroff {
+                compatible = "gpio-poweroff";
+                pinctrl-0 = <&pmx_poweroff>;
+                pinctrl-names = "default";
+                gpios = <&gpio0 30 GPIO_ACTIVE_LOW>;
+        };
+
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                usb3_regulator: usb3-regulator {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "USB 3.0 Power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+                };
+        };
+};
+
+&nand {
+        status = "okay";
+
+        partition@0 {
+                label = "u-boot";
+                reg = <0x0000000 0x180000>;
+                read-only;
+        };
+
+        partition@180000 {
+                label = "u-boot-env";
+                reg = <0x180000 0x20000>;
+        };
+
+        partition@200000 {
+                label = "uImage";
+                reg = <0x0200000 0x600000>;
+        };
+
+        partition@800000 {
+                label = "minirootfs";
+                reg = <0x0800000 0x1000000>;
+        };
+
+        partition@1800000 {
+                label = "jffs2";
+                reg = <0x1800000 0x6800000>;
+        };
+};
+
+&mdio {
+        status = "okay";
+
+        ethphy0: ethernet-phy@0 { /* Marvell 88E1318 */
+                device_type = "ethernet-phy";
+                reg = <0>;
+        };
+};
+
+&eth0 {
+        status = "okay";
+
+        ethernet0-port@0 {
+                phy-handle = <&ethphy0>;
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
index 2fcb82e20828..ae1ccbe41029 100644
--- a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
+++ b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
@@ -64,8 +64,8 @@
 
                 button@1 {
                         label = "Power push button";
-                        linux,code = <116>;
-                        gpios = <&gpio1 0 0>;
+                        linux,code = <KEY_POWER>;
+                        gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
                 };
         };
 
@@ -74,13 +74,13 @@
 
                 red-fail {
                         label = "ns2:red:fail";
-                        gpios = <&gpio0 12 0>;
+                        gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
                 };
         };
 
         gpio_poweroff {
                 compatible = "gpio-poweroff";
-                gpios = <&gpio0 31 0>;
+                gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>;
         };
 
 };
diff --git a/arch/arm/boot/dts/kirkwood-ns2lite.dts b/arch/arm/boot/dts/kirkwood-ns2lite.dts
index 279607093cdb..1f2ca60d8b3d 100644
--- a/arch/arm/boot/dts/kirkwood-ns2lite.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2lite.dts
@@ -25,8 +25,8 @@
 
                 blue-sata {
                         label = "ns2:blue:sata";
-                        gpios = <&gpio0 30 1>;
-                        linux,default-trigger = "default-on";
+                        gpios = <&gpio0 30 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "ide-disk";
                 };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-ns2max.dts b/arch/arm/boot/dts/kirkwood-ns2max.dts
index defdc77fb550..72c78d0b1116 100644
--- a/arch/arm/boot/dts/kirkwood-ns2max.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2max.dts
@@ -22,10 +22,10 @@
 
         gpio_fan {
                 compatible = "gpio-fan";
-                gpios = <&gpio0 22 1
-                         &gpio0  7 1
-                         &gpio1  1 1
-                         &gpio0 23 1>;
+                gpios = <&gpio0 22 GPIO_ACTIVE_LOW
+                         &gpio0  7 GPIO_ACTIVE_LOW
+                         &gpio1  1 GPIO_ACTIVE_LOW
+                         &gpio0 23 GPIO_ACTIVE_LOW>;
                 gpio-fan,speed-map =
                         <   0  0
                          1500 15
@@ -36,7 +36,7 @@
                          3300 10
                          4300  9
                          5500  8>;
-                alarm-gpios = <&gpio0 25 1>;
+                alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
         };
 
         ns2-leds {
diff --git a/arch/arm/boot/dts/kirkwood-ns2mini.dts b/arch/arm/boot/dts/kirkwood-ns2mini.dts
index adbafdd90991..c441bf62c09f 100644
--- a/arch/arm/boot/dts/kirkwood-ns2mini.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2mini.dts
@@ -23,10 +23,10 @@
 
         gpio_fan {
                 compatible = "gpio-fan";
-                gpios = <&gpio0 22 1
-                         &gpio0  7 1
-                         &gpio1  1 1
-                         &gpio0 23 1>;
+                gpios = <&gpio0 22 GPIO_ACTIVE_LOW
+                         &gpio0  7 GPIO_ACTIVE_LOW
+                         &gpio1  1 GPIO_ACTIVE_LOW
+                         &gpio0 23 GPIO_ACTIVE_LOW>;
                 gpio-fan,speed-map =
                         <   0  0
                          3000 15
@@ -37,7 +37,7 @@
                          7140 10
                          7980  9
                          9200  8>;
-                alarm-gpios = <&gpio0 25 1>;
+                alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
         };
 
         ns2-leds {
diff --git a/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi b/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi
index e3f915defd3d..aa78c2d11fe7 100644
--- a/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi
+++ b/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi
@@ -40,7 +40,7 @@
                 compatible = "gpio-poweroff";
                 pinctrl-0 = <&pmx_pwr_off>;
                 pinctrl-names = "default";
-                gpios = <&gpio1 16 0>;
+                gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
         };
 
         regulators {
@@ -58,7 +58,7 @@
                         regulator-max-microvolt = <5000000>;
                         regulator-always-on;
                         regulator-boot-on;
-                        gpio = <&gpio0 21 0>;
+                        gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts
index b5418bcaecce..03fa24cf3344 100644
--- a/arch/arm/boot/dts/kirkwood-nsa310.dts
+++ b/arch/arm/boot/dts/kirkwood-nsa310.dts
@@ -119,18 +119,18 @@
 
                 button@1 {
                         label = "Power Button";
-                        linux,code = <116>;
-                        gpios = <&gpio1 14 0>;
+                        linux,code = <KEY_POWER>;
+                        gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
                 };
                 button@2 {
                         label = "Copy Button";
-                        linux,code = <133>;
-                        gpios = <&gpio1 5 1>;
+                        linux,code = <KEY_COPY>;
+                        gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
                 };
                 button@3 {
                         label = "Reset Button";
-                        linux,code = <0x198>;
-                        gpios = <&gpio1 4 1>;
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
                 };
         };
 
@@ -145,43 +145,43 @@
 
                 green-sys {
                         label = "nsa310:green:sys";
-                        gpios = <&gpio0 28 0>;
+                        gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;
                 };
                 red-sys {
                         label = "nsa310:red:sys";
-                        gpios = <&gpio0 29 0>;
+                        gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
                 };
                 green-hdd {
                         label = "nsa310:green:hdd";
-                        gpios = <&gpio1 9 0>;
+                        gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
                 };
                 red-hdd {
                         label = "nsa310:red:hdd";
-                        gpios = <&gpio1 10 0>;
+                        gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
                 };
                 green-esata {
                         label = "nsa310:green:esata";
-                        gpios = <&gpio0 12 0>;
+                        gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
                 };
                 red-esata {
                         label = "nsa310:red:esata";
-                        gpios = <&gpio0 13 0>;
+                        gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
                 };
                 green-usb {
                         label = "nsa310:green:usb";
-                        gpios = <&gpio0 15 0>;
+                        gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
                 };
                 red-usb {
                         label = "nsa310:red:usb";
-                        gpios = <&gpio0 16 0>;
+                        gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
                 };
                 green-copy {
                         label = "nsa310:green:copy";
-                        gpios = <&gpio1 7 0>;
+                        gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
                 };
                 red-copy {
                         label = "nsa310:red:copy";
-                        gpios = <&gpio1 8 0>;
+                        gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-nsa310a.dts b/arch/arm/boot/dts/kirkwood-nsa310a.dts
index ab0212b0e6f5..a5e779452867 100644
--- a/arch/arm/boot/dts/kirkwood-nsa310a.dts
+++ b/arch/arm/boot/dts/kirkwood-nsa310a.dts
@@ -107,18 +107,18 @@
 
                 button@1 {
                         label = "Power Button";
-                        linux,code = <116>;
-                        gpios = <&gpio1 14 0>;
+                        linux,code = <KEY_POWER>;
+                        gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
                 };
                 button@2 {
                         label = "Copy Button";
-                        linux,code = <133>;
-                        gpios = <&gpio1 5 1>;
+                        linux,code = <KEY_COPY>;
+                        gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
                 };
                 button@3 {
                         label = "Reset Button";
-                        linux,code = <0x198>;
-                        gpios = <&gpio1 4 1>;
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
                 };
         };
 
@@ -127,39 +127,39 @@
 
                 green-sys {
                         label = "nsa310:green:sys";
-                        gpios = <&gpio0 28 0>;
+                        gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;
                 };
                 red-sys {
                         label = "nsa310:red:sys";
-                        gpios = <&gpio0 29 0>;
+                        gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
                 };
                 green-hdd {
                         label = "nsa310:green:hdd";
-                        gpios = <&gpio1 9 0>;
+                        gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
                 };
                 red-hdd {
                         label = "nsa310:red:hdd";
-                        gpios = <&gpio1 10 0>;
+                        gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
                 };
                 green-esata {
                         label = "nsa310:green:esata";
-                        gpios = <&gpio0 12 0>;
+                        gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
                 };
                 red-esata {
                         label = "nsa310:red:esata";
-                        gpios = <&gpio0 13 0>;
+                        gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
                 };
                 green-usb {
                         label = "nsa310:green:usb";
-                        gpios = <&gpio0 15 0>;
+                        gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
                 };
                 green-copy {
                         label = "nsa310:green:copy";
-                        gpios = <&gpio1 7 0>;
+                        gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
                 };
                 red-copy {
                         label = "nsa310:red:copy";
-                        gpios = <&gpio1 8 0>;
+                        gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
index f0e3d213604c..5c6a4f1b4e93 100644
--- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
+++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
@@ -101,17 +101,17 @@
 
                 led-red {
                         label = "obsa6:red:stat";
-                        gpios = <&gpio1 9 1>;
+                        gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
                 };
 
                 led-green {
                         label = "obsa6:green:stat";
-                        gpios = <&gpio1 10 1>;
+                        gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
                 };
 
                 led-yellow {
                         label = "obsa6:yellow:stat";
-                        gpios = <&gpio1 11 1>;
+                        gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
                 };
         };
 
@@ -124,8 +124,8 @@
 
                 button@1 {
                         label = "Init Button";
-                        linux,code = <116>;
-                        gpios = <&gpio1 6 0>;
+                        linux,code = <KEY_POWER>;
+                        gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts
index 851fb2a60f20..c054ef61cff5 100644
--- a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts
+++ b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts
@@ -126,17 +126,17 @@
 
                 led-red {
                         label = "obsa7:red:stat";
-                        gpios = <&gpio1 9 1>;
+                        gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
                 };
 
                 led-green {
                         label = "obsa7:green:stat";
-                        gpios = <&gpio1 10 1>;
+                        gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
                 };
 
                 led-yellow {
                         label = "obsa7:yellow:stat";
-                        gpios = <&gpio1 11 1>;
+                        gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
                 };
         };
 
@@ -149,8 +149,8 @@
 
                 button@1 {
                         label = "Init Button";
-                        linux,code = <116>;
-                        gpios = <&gpio1 6 0>;
+                        linux,code = <KEY_POWER>;
+                        gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
index 1173d7fb31b2..7b1cd993e891 100644
--- a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
+++ b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
@@ -1,5 +1,5 @@
 /*
- * kirkwood-sheevaplug-common.dts - Common parts for Sheevaplugs
+ * kirkwood-sheevaplug-common.dtsi - Common parts for Sheevaplugs
  *
  * Copyright (C) 2013 Simon Baatz <gmbnomis@gmail.com>
  *
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
index eac6a21f3b1f..e2b4ea4f9e10 100644
--- a/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
+++ b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
@@ -24,8 +24,8 @@
                         pinctrl-0 = <&pmx_sdio &pmx_sdio_cd &pmx_sdio_wp>;
                         pinctrl-names = "default";
                         status = "okay";
-                        cd-gpios = <&gpio1 12 1>;
-                        wp-gpios = <&gpio1 15 0>;
+                        cd-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
+                        wp-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
                 };
         };
 
@@ -36,8 +36,8 @@
 
                 health {
                         label = "sheevaplug:blue:health";
-                        gpios = <&gpio1 17 1>;
-                        linux,default-trigger = "default-on";
+                        gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
+                        default-state = "keep";
                 };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug.dts b/arch/arm/boot/dts/kirkwood-sheevaplug.dts
index bb61918313db..82f6abf120fd 100644
--- a/arch/arm/boot/dts/kirkwood-sheevaplug.dts
+++ b/arch/arm/boot/dts/kirkwood-sheevaplug.dts
@@ -1,5 +1,5 @@
 /*
- * kirkwood-sheevaplug-esata.dts - Device tree file for Sheevaplug
+ * kirkwood-sheevaplug.dts - Device tree file for Sheevaplug
  *
  * Copyright (C) 2013 Simon Baatz <gmbnomis@gmail.com>
  *
@@ -31,13 +31,13 @@
 
                 health {
                         label = "sheevaplug:blue:health";
-                        gpios = <&gpio1 17 1>;
-                        linux,default-trigger = "default-on";
+                        gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
+                        default-state = "keep";
                 };
 
                 misc {
                         label = "sheevaplug:red:misc";
-                        gpios = <&gpio1 14 1>;
+                        gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts
index 320da677b984..40d6adf678ca 100644
--- a/arch/arm/boot/dts/kirkwood-topkick.dts
+++ b/arch/arm/boot/dts/kirkwood-topkick.dts
@@ -131,25 +131,25 @@
 
                 disk {
                         label = "topkick:yellow:disk";
-                        gpios = <&gpio0 21 1>;
+                        gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
                         linux,default-trigger = "ide-disk";
                 };
                 system2 {
                         label = "topkick:red:system";
-                        gpios = <&gpio1 5 1>;
+                        gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
                 };
                 system {
                         label = "topkick:blue:system";
-                        gpios = <&gpio1 6 1>;
+                        gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
                         default-state = "on";
                 };
                 wifi {
                         label = "topkick:green:wifi";
-                        gpios = <&gpio1 7 1>;
+                        gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
                 };
                 wifi2 {
                         label = "topkick:yellow:wifi";
-                        gpios = <&gpio1 16 1>;
+                        gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
                 };
         };
         regulators {
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
index f755bc1dc604..c17ae45e19be 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
@@ -41,13 +41,13 @@
 
                 button@1 {
                         label = "USB Copy";
-                        linux,code = <133>;
-                        gpios = <&gpio0 15 1>;
+                        linux,code = <KEY_COPY>;
+                        gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
                 };
                 button@2 {
                         label = "Reset";
-                        linux,code = <0x198>;
-                        gpios = <&gpio0 16 1>;
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
index 345562f75891..0713d072758a 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
@@ -51,13 +51,13 @@
 
                 button@1 {
                         label = "USB Copy";
-                        linux,code = <133>;
-                        gpios = <&gpio1 11 1>;
+                        linux,code = <KEY_COPY>;
+                        gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
                 };
                 button@2 {
                         label = "Reset";
-                        linux,code = <0x198>;
-                        gpios = <&gpio1 5 1>;
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 8b73c80f1dad..81e6c409284e 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -1,4 +1,6 @@
 /include/ "skeleton.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
 
 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
 
@@ -68,39 +70,21 @@
                 #address-cells = <1>;
                 #size-cells = <1>;
 
-                mbusc: mbus-controller@20000 {
-                        compatible = "marvell,mbus-controller";
-                        reg = <0x20000 0x80>, <0x1500 0x20>;
-                };
-
-                timer: timer@20300 {
-                        compatible = "marvell,orion-timer";
-                        reg = <0x20300 0x20>;
-                        interrupt-parent = <&bridge_intc>;
-                        interrupts = <1>, <2>;
-                        clocks = <&core_clk 0>;
-                };
-
-                intc: main-interrupt-ctrl@20200 {
-                        compatible = "marvell,orion-intc";
-                        interrupt-controller;
-                        #interrupt-cells = <1>;
-                        reg = <0x20200 0x10>, <0x20210 0x10>;
-                };
-
-                bridge_intc: bridge-interrupt-ctrl@20110 {
-                        compatible = "marvell,orion-bridge-intc";
-                        interrupt-controller;
-                        #interrupt-cells = <1>;
-                        reg = <0x20110 0x8>;
-                        interrupts = <1>;
-                        marvell,#interrupts = <6>;
-                };
-
                 core_clk: core-clocks@10030 {
                         compatible = "marvell,kirkwood-core-clock";
                         reg = <0x10030 0x4>;
-                        #clock-cells = <1>;
+                        #clock-cells = <1>;
+                };
+
+                spi@10600 {
+                        compatible = "marvell,orion-spi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <0>;
+                        interrupts = <23>;
+                        reg = <0x10600 0x28>;
+                        clocks = <&gate_clk 7>;
+                        status = "disabled";
                 };
 
                 gpio0: gpio@10100 {
@@ -127,6 +111,17 @@
                         clocks = <&gate_clk 7>;
                 };
 
+                i2c@11000 {
+                        compatible = "marvell,mv64xxx-i2c";
+                        reg = <0x11000 0x20>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        interrupts = <29>;
+                        clock-frequency = <100000>;
+                        clocks = <&gate_clk 7>;
+                        status = "disabled";
+                };
+
                 serial@12000 {
                         compatible = "ns16550a";
                         reg = <0x12000 0x100>;
@@ -145,15 +140,18 @@
                         status = "disabled";
                 };
 
-                spi@10600 {
-                        compatible = "marvell,orion-spi";
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <0>;
-                        interrupts = <23>;
-                        reg = <0x10600 0x28>;
-                        clocks = <&gate_clk 7>;
-                        status = "disabled";
+                mbusc: mbus-controller@20000 {
+                        compatible = "marvell,mbus-controller";
+                        reg = <0x20000 0x80>, <0x1500 0x20>;
+                };
+
+                bridge_intc: bridge-interrupt-ctrl@20110 {
+                        compatible = "marvell,orion-bridge-intc";
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        reg = <0x20110 0x8>;
+                        interrupts = <1>;
+                        marvell,#interrupts = <6>;
                 };
 
                 gate_clk: clock-gating-control@2011c {
@@ -163,6 +161,21 @@
                         #clock-cells = <1>;
                 };
 
+                intc: main-interrupt-ctrl@20200 {
+                        compatible = "marvell,orion-intc";
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        reg = <0x20200 0x10>, <0x20210 0x10>;
+                };
+
+                timer: timer@20300 {
+                        compatible = "marvell,orion-timer";
+                        reg = <0x20300 0x20>;
+                        interrupt-parent = <&bridge_intc>;
+                        interrupts = <1>, <2>;
+                        clocks = <&core_clk 0>;
+                };
+
                 wdt: watchdog-timer@20300 {
                         compatible = "marvell,orion-wdt";
                         reg = <0x20300 0x28>;
@@ -172,6 +185,14 @@
                         status = "okay";
                 };
 
+                ehci@50000 {
+                        compatible = "marvell,orion-ehci";
+                        reg = <0x50000 0x1000>;
+                        interrupts = <19>;
+                        clocks = <&gate_clk 3>;
+                        status = "okay";
+                };
+
                 xor@60800 {
                         compatible = "marvell,orion-xor";
                         reg = <0x60800 0x100
@@ -212,37 +233,6 @@
                         };
                 };
 
-                ehci@50000 {
-                        compatible = "marvell,orion-ehci";
-                        reg = <0x50000 0x1000>;
-                        interrupts = <19>;
-                        clocks = <&gate_clk 3>;
-                        status = "okay";
-                };
-
-                i2c@11000 {
-                        compatible = "marvell,mv64xxx-i2c";
-                        reg = <0x11000 0x20>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        interrupts = <29>;
-                        clock-frequency = <100000>;
-                        clocks = <&gate_clk 7>;
-                        status = "disabled";
-                };
-
-                mdio: mdio-bus@72004 {
-                        compatible = "marvell,orion-mdio";
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        reg = <0x72004 0x84>;
-                        interrupts = <46>;
-                        clocks = <&gate_clk 0>;
-                        status = "disabled";
-
-                        /* add phy nodes in board file */
-                };
-
                 eth0: ethernet-controller@72000 {
                         compatible = "marvell,kirkwood-eth";
                         #address-cells = <1>;
@@ -263,6 +253,18 @@
                         };
                 };
 
+                mdio: mdio-bus@72004 {
+                        compatible = "marvell,orion-mdio";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x72004 0x84>;
+                        interrupts = <46>;
+                        clocks = <&gate_clk 0>;
+                        status = "disabled";
+
+                        /* add phy nodes in board file */
+                };
+
                 eth1: ethernet-controller@76000 {
                         compatible = "marvell,kirkwood-eth";
                         #address-cells = <1>;
@@ -282,5 +284,23 @@
                                 /* set phy-handle property in board file */
                         };
                 };
+
+                sata_phy0: sata-phy@82000 {
+                        compatible = "marvell,mvebu-sata-phy";
+                        reg = <0x82000 0x0334>;
+                        clocks = <&gate_clk 14>;
+                        clock-names = "sata";
+                        #phy-cells = <0>;
+                        status = "ok";
+                };
+
+                sata_phy1: sata-phy@84000 {
+                        compatible = "marvell,mvebu-sata-phy";
+                        reg = <0x84000 0x0334>;
+                        clocks = <&gate_clk 15>;
+                        clock-names = "sata";
+                        #phy-cells = <0>;
+                        status = "ok";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/moxart-uc7112lx.dts b/arch/arm/boot/dts/moxart-uc7112lx.dts
new file mode 100644
index 000000000000..90749d55de0d
--- /dev/null
+++ b/arch/arm/boot/dts/moxart-uc7112lx.dts
@@ -0,0 +1,109 @@
+/* moxart-uc7112lx.dts - Device Tree file for MOXA UC-7112-LX
+ *
+ * Copyright (C) 2013 Jonas Jensen <jonas.jensen@gmail.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/dts-v1/;
+/include/ "moxart.dtsi"
+
+/ {
+        model = "MOXA UC-7112-LX";
+        compatible = "moxa,moxart-uc-7112-lx", "moxa,moxart";
+
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x2000000>;
+        };
+
+        flash@80000000,0 {
+                compatible = "numonyx,js28f128", "cfi-flash";
+                reg = <0x80000000 0x1000000>;
+                bank-width = <2>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                partition@0 {
+                        label = "bootloader";
+                        reg = <0x0 0x40000>;
+                };
+                partition@40000 {
+                        label = "linux kernel";
+                        reg = <0x40000 0x1C0000>;
+                };
+                partition@200000 {
+                        label = "root filesystem";
+                        reg = <0x200000 0x800000>;
+                };
+                partition@a00000 {
+                        label = "user filesystem";
+                        reg = <0xa00000 0x600000>;
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                user-led {
+                        label = "ready-led";
+                        gpios = <&gpio 27 0x1>;
+                        default-state = "on";
+                        linux,default-trigger = "default-on";
+                };
+        };
+
+        gpio_keys_polled {
+                compatible = "gpio-keys-polled";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                poll-interval = <500>;
+                button@25 {
+                        label = "GPIO Reset";
+                        linux,code = <116>;
+                        gpios = <&gpio 25 1>;
+                };
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/mmcblk0p1 rw rootwait";
+        };
+};
+
+&clk_pll {
+        clocks = <&ref12>;
+};
+
+&sdhci {
+        status = "okay";
+};
+
+&mdio0 {
+        status = "okay";
+
+        ethphy0: ethernet-phy@1 {
+                device_type = "ethernet-phy";
+                compatible = "moxa,moxart-rtl8201cp", "ethernet-phy-ieee802.3-c22";
+                reg = <1>;
+        };
+};
+
+&mdio1 {
+        status = "okay";
+
+        ethphy1: ethernet-phy@1 {
+                device_type = "ethernet-phy";
+                compatible = "moxa,moxart-rtl8201cp", "ethernet-phy-ieee802.3-c22";
+                reg = <1>;
+        };
+};
+
+&mac0 {
+        status = "okay";
+};
+
+&mac1 {
+        status = "okay";
+};
+
+&uart0 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/moxart.dtsi b/arch/arm/boot/dts/moxart.dtsi
new file mode 100644
index 000000000000..da1d8effef97
--- /dev/null
+++ b/arch/arm/boot/dts/moxart.dtsi
@@ -0,0 +1,154 @@
+/* moxart.dtsi - Device Tree Include file for MOXA ART family SoC
+ *
+ * Copyright (C) 2013 Jonas Jensen <jonas.jensen@gmail.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        compatible = "moxa,moxart";
+        model = "MOXART";
+        interrupt-parent = <&intc>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "faraday,fa526";
+                        reg = <0>;
+                };
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ref12: ref12M {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <12000000>;
+                };
+        };
+
+        soc {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0x90000000 0x10000000>;
+                ranges;
+
+                intc: interrupt-controller@98800000 {
+                        compatible = "moxa,moxart-ic";
+                        reg = <0x98800000 0x38>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        interrupt-mask = <0x00080000>;
+                };
+
+                clk_pll: clk_pll@98100000 {
+                        compatible = "moxa,moxart-pll-clock";
+                        #clock-cells = <0>;
+                        reg = <0x98100000 0x34>;
+                };
+
+                clk_apb: clk_apb@98100000 {
+                        compatible = "moxa,moxart-apb-clock";
+                        #clock-cells = <0>;
+                        reg = <0x98100000 0x34>;
+                        clocks = <&clk_pll>;
+                };
+
+                timer: timer@98400000 {
+                        compatible = "moxa,moxart-timer";
+                        reg = <0x98400000 0x42>;
+                        interrupts = <19 1>;
+                        clocks = <&clk_apb>;
+                };
+
+                gpio: gpio@98700000 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        compatible = "moxa,moxart-gpio";
+                        reg = <0x98700000 0xC>;
+                };
+
+                rtc: rtc {
+                        compatible = "moxa,moxart-rtc";
+                        gpio-rtc-sclk = <&gpio 5 0>;
+                        gpio-rtc-data = <&gpio 6 0>;
+                        gpio-rtc-reset = <&gpio 7 0>;
+                };
+
+                dma: dma@90500000 {
+                        compatible = "moxa,moxart-dma";
+                        reg = <0x90500080 0x40>;
+                        interrupts = <24 0>;
+                        #dma-cells = <1>;
+                };
+
+                watchdog: watchdog@98500000 {
+                        compatible = "moxa,moxart-watchdog";
+                        reg = <0x98500000 0x10>;
+                        clocks = <&clk_apb>;
+                };
+
+                sdhci: sdhci@98e00000 {
+                        compatible = "moxa,moxart-sdhci";
+                        reg = <0x98e00000 0x5C>;
+                        interrupts = <5 0>;
+                        clocks = <&clk_apb>;
+                        dmas =  <&dma 5>,
+                                <&dma 5>;
+                        dma-names = "tx", "rx";
+                        status = "disabled";
+                };
+
+                mdio0: mdio@90900090 {
+                        compatible = "moxa,moxart-mdio";
+                        reg = <0x90900090 0x8>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                mdio1: mdio@92000090 {
+                        compatible = "moxa,moxart-mdio";
+                        reg = <0x92000090 0x8>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                mac0: mac@90900000 {
+                        compatible = "moxa,moxart-mac";
+                        reg = <0x90900000 0x90>;
+                        interrupts = <25 0>;
+                        phy-handle = <&ethphy0>;
+                        phy-mode = "mii";
+                        status = "disabled";
+                };
+
+                mac1: mac@92000000 {
+                        compatible = "moxa,moxart-mac";
+                        reg = <0x92000000 0x90>;
+                        interrupts = <27 0>;
+                        phy-handle = <&ethphy1>;
+                        phy-mode = "mii";
+                        status = "disabled";
+                };
+
+                uart0: uart@98200000 {
+                        compatible = "ns16550a";
+                        reg = <0x98200000 0x20>;
+                        interrupts = <31 8>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clock-frequency = <14745600>;
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
index aed83deaa991..fcc5bb63f03a 100644
--- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
+++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
@@ -58,7 +58,7 @@
         status = "okay";
 
         ethphy: ethernet-phy {
-                device-type = "ethernet-phy";
+                device_type = "ethernet-phy";
                 reg = <8>;
         };
 };
diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
index e06c37e91ac6..9f51538cd9ef 100644
--- a/arch/arm/boot/dts/orion5x.dtsi
+++ b/arch/arm/boot/dts/orion5x.dtsi
@@ -42,6 +42,25 @@
                         interrupts = <6>, <7>, <8>, <9>;
                 };
 
+                spi@10600 {
+                        compatible = "marvell,orion-spi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <0>;
+                        reg = <0x10600 0x28>;
+                        status = "disabled";
+                };
+
+                i2c@11000 {
+                        compatible = "marvell,mv64xxx-i2c";
+                        reg = <0x11000 0x20>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        interrupts = <5>;
+                        clock-frequency = <100000>;
+                        status = "disabled";
+                };
+
                 serial@12000 {
                         compatible = "ns16550a";
                         reg = <0x12000 0x100>;
@@ -60,15 +79,6 @@
                         status = "disabled";
                 };
 
-                spi@10600 {
-                        compatible = "marvell,orion-spi";
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <0>;
-                        reg = <0x10600 0x28>;
-                        status = "disabled";
-                };
-
                 wdt@20300 {
                         compatible = "marvell,orion-wdt";
                         reg = <0x20300 0x28>;
@@ -82,30 +92,6 @@
                         status = "disabled";
                 };
 
-                ehci@a0000 {
-                        compatible = "marvell,orion-ehci";
-                        reg = <0xa0000 0x1000>;
-                        interrupts = <12>;
-                        status = "disabled";
-                };
-
-                sata@80000 {
-                        compatible = "marvell,orion-sata";
-                        reg = <0x80000 0x5000>;
-                        interrupts = <29>;
-                        status = "disabled";
-                };
-
-                i2c@11000 {
-                        compatible = "marvell,mv64xxx-i2c";
-                        reg = <0x11000 0x20>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        interrupts = <5>;
-                        clock-frequency = <100000>;
-                        status = "disabled";
-                };
-
                 xor@60900 {
                         compatible = "marvell,orion-xor";
                         reg = <0x60900 0x100
@@ -125,26 +111,6 @@
                         };
                 };
 
-                crypto@90000 {
-                        compatible = "marvell,orion-crypto";
-                        reg = <0x90000 0x10000>,
-                              <0xf2200000 0x800>;
-                        reg-names = "regs", "sram";
-                        interrupts = <28>;
-                        status = "okay";
-                };
-
-                mdio: mdio-bus@72004 {
-                        compatible = "marvell,orion-mdio";
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        reg = <0x72004 0x84>;
-                        interrupts = <22>;
-                        status = "disabled";
-
-                        /* add phy nodes in board file */
-                };
-
                 eth: ethernet-controller@72000 {
                         compatible = "marvell,orion-eth";
                         #address-cells = <1>;
@@ -162,5 +128,39 @@
                                 /* set phy-handle property in board file */
                         };
                 };
+
+                mdio: mdio-bus@72004 {
+                        compatible = "marvell,orion-mdio";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x72004 0x84>;
+                        interrupts = <22>;
+                        status = "disabled";
+
+                        /* add phy nodes in board file */
+                };
+
+                sata@80000 {
+                        compatible = "marvell,orion-sata";
+                        reg = <0x80000 0x5000>;
+                        interrupts = <29>;
+                        status = "disabled";
+                };
+
+                crypto@90000 {
+                        compatible = "marvell,orion-crypto";
+                        reg = <0x90000 0x10000>,
+                              <0xf2200000 0x800>;
+                        reg-names = "regs", "sram";
+                        interrupts = <28>;
+                        status = "okay";
+                };
+
+                ehci@a0000 {
+                        compatible = "marvell,orion-ehci";
+                        reg = <0xa0000 0x1000>;
+                        interrupts = <12>;
+                        status = "disabled";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index daee58944e15..0e219932d7cc 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -29,6 +29,15 @@
                         timebase-frequency = <0>;
                         bus-frequency = <0>;
                         clock-frequency = <0>;
+                        clocks = <&clks 12>;
+                        operating-points = <
+                                /* kHz    uV */
+                                200000  1025000
+                                400000  1025000
+                                664000  1050000
+                                800000  1100000
+                        >;
+                        clock-latency = <150000>;
                 };
         };
 
@@ -80,6 +89,7 @@
                         cphifbg@88030000 {
                                 compatible = "sirf,prima2-cphifbg";
                                 reg = <0x88030000 0x1000>;
+                                clocks = <&clks 42>;
                         };
                 };
 
@@ -540,6 +550,18 @@
                                                         "usp0_uart_nostreamctrl";
                                         };
                                 };
+                                usp0_only_utfs_pins_a: usp0@2 {
+                                        usp0 {
+                                                sirf,pins = "usp0_only_utfs_grp";
+                                                sirf,function = "usp0_only_utfs";
+                                        };
+                                };
+                                usp0_only_urfs_pins_a: usp0@3 {
+                                        usp0 {
+                                                sirf,pins = "usp0_only_urfs_grp";
+                                                sirf,function = "usp0_only_urfs";
+                                        };
+                                };
                                 usp1_pins_a: usp1@0 {
                                         usp1 {
                                                 sirf,pins = "usp1grp";
@@ -648,6 +670,9 @@
                                         compatible = "sirf,prima2-sdhc";
                                         reg = <0x56000000 0x100000>;
                                         interrupts = <38>;
+                                        status = "disabled";
+                                        bus-width = <8>;
+                                        clocks = <&clks 36>;
                                 };
 
                                 sd1: sdhci@56100000 {
@@ -655,6 +680,9 @@
                                         compatible = "sirf,prima2-sdhc";
                                         reg = <0x56100000 0x100000>;
                                         interrupts = <38>;
+                                        status = "disabled";
+                                        bus-width = <4>;
+                                        clocks = <&clks 36>;
                                 };
 
                                 sd2: sdhci@56200000 {
@@ -662,6 +690,8 @@
                                         compatible = "sirf,prima2-sdhc";
                                         reg = <0x56200000 0x100000>;
                                         interrupts = <23>;
+                                        status = "disabled";
+                                        clocks = <&clks 37>;
                                 };
 
                                 sd3: sdhci@56300000 {
@@ -669,6 +699,8 @@
                                         compatible = "sirf,prima2-sdhc";
                                         reg = <0x56300000 0x100000>;
                                         interrupts = <23>;
+                                        status = "disabled";
+                                        clocks = <&clks 37>;
                                 };
 
                                 sd4: sdhci@56400000 {
@@ -676,6 +708,8 @@
                                         compatible = "sirf,prima2-sdhc";
                                         reg = <0x56400000 0x100000>;
                                         interrupts = <39>;
+                                        status = "disabled";
+                                        clocks = <&clks 38>;
                                 };
 
                                 sd5: sdhci@56500000 {
@@ -683,6 +717,7 @@
                                         compatible = "sirf,prima2-sdhc";
                                         reg = <0x56500000 0x100000>;
                                         interrupts = <39>;
+                                        clocks = <&clks 38>;
                                 };
 
                                 pci-copy@57900000 {
@@ -716,6 +751,12 @@
                                 interrupts = <52 53 54>;
                         };
 
+                        minigpsrtc@2000 {
+                                compatible = "sirf,prima2-minigpsrtc";
+                                reg = <0x2000 0x1000>;
+                                interrupts = <54>;
+                        };
+
                         pwrc@3000 {
                                 compatible = "sirf,prima2-pwrc";
                                 reg = <0x3000 0x1000>;
diff --git a/arch/arm/boot/dts/pxa27x.dtsi b/arch/arm/boot/dts/pxa27x.dtsi
index d7c5d721a5c7..a70546945985 100644
--- a/arch/arm/boot/dts/pxa27x.dtsi
+++ b/arch/arm/boot/dts/pxa27x.dtsi
@@ -10,5 +10,29 @@
                         marvell,intc-priority;
                         marvell,intc-nr-irqs = <34>;
                 };
+
+                pwm0: pwm@40b00000 {
+                        compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
+                        reg = <0x40b00000 0x10>;
+                        #pwm-cells = <1>;
+                };
+
+                pwm1: pwm@40b00010 {
+                        compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
+                        reg = <0x40b00010 0x10>;
+                        #pwm-cells = <1>;
+                };
+
+                pwm2: pwm@40c00000 {
+                        compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
+                        reg = <0x40c00000 0x10>;
+                        #pwm-cells = <1>;
+                };
+
+                pwm3: pwm@40c00010 {
+                        compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
+                        reg = <0x40c00010 0x10>;
+                        #pwm-cells = <1>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 2ebb4f09a9b6..6ac94967d2d3 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -29,5 +29,69 @@
                                      <1 1 0xf08>;
                         clock-frequency = <19200000>;
                 };
+
+                timer@f9020000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+                        compatible = "arm,armv7-timer-mem";
+                        reg = <0xf9020000 0x1000>;
+                        clock-frequency = <19200000>;
+
+                        frame@f9021000 {
+                                frame-number = <0>;
+                                interrupts = <0 8 0x4>,
+                                             <0 7 0x4>;
+                                reg = <0xf9021000 0x1000>,
+                                      <0xf9022000 0x1000>;
+                        };
+
+                        frame@f9023000 {
+                                frame-number = <1>;
+                                interrupts = <0 9 0x4>;
+                                reg = <0xf9023000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        frame@f9024000 {
+                                frame-number = <2>;
+                                interrupts = <0 10 0x4>;
+                                reg = <0xf9024000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        frame@f9025000 {
+                                frame-number = <3>;
+                                interrupts = <0 11 0x4>;
+                                reg = <0xf9025000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        frame@f9026000 {
+                                frame-number = <4>;
+                                interrupts = <0 12 0x4>;
+                                reg = <0xf9026000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        frame@f9027000 {
+                                frame-number = <5>;
+                                interrupts = <0 13 0x4>;
+                                reg = <0xf9027000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        frame@f9028000 {
+                                frame-number = <6>;
+                                interrupts = <0 14 0x4>;
+                                reg = <0xf9028000 0x1000>;
+                                status = "disabled";
+                        };
+                };
+
+                restart@fc4ab000 {
+                        compatible = "qcom,pshold";
+                        reg = <0xfc4ab000 0x4>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts
index 1fb20f2333cc..b1deaf7e2e06 100644
--- a/arch/arm/boot/dts/r7s72100-genmai.dts
+++ b/arch/arm/boot/dts/r7s72100-genmai.dts
@@ -9,7 +9,7 @@
  */
 
 /dts-v1/;
-/include/ "r7s72100.dtsi"
+#include "r7s72100.dtsi"
 
 / {
         model = "Genmai";
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
index 9443e93d3cac..70b1fff8f4a3 100644
--- a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
+++ b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
@@ -9,7 +9,7 @@
  */
 
 /dts-v1/;
-/include/ "r8a73a4.dtsi"
+#include "r8a73a4.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -25,6 +25,11 @@
                 reg = <0 0x40000000 0 0x40000000>;
         };
 
+        memory@200000000 {
+                device_type = "memory";
+                reg = <2 0x00000000 0 0x40000000>;
+        };
+
         vcc_mmc0: regulator@0 {
                 compatible = "regulator-fixed";
                 regulator-name = "MMC0 Vcc";
@@ -88,22 +93,22 @@
         pinctrl-0 = <&scifa0_pins>;
         pinctrl-names = "default";
 
-        scifa0_pins: scifa0 {
+        scifa0_pins: serial0 {
                 renesas,groups = "scifa0_data";
                 renesas,function = "scifa0";
         };
 
-        mmc0_pins: mmcif {
+        mmc0_pins: mmc {
                 renesas,groups = "mmc0_data8", "mmc0_ctrl";
                 renesas,function = "mmc0";
         };
 
-        sdhi0_pins: sdhi0 {
+        sdhi0_pins: sd0 {
                 renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
                 renesas,function = "sdhi0";
         };
 
-        sdhi1_pins: sdhi1 {
+        sdhi1_pins: sd1 {
                 renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
                 renesas,function = "sdhi1";
         };
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
index 91436b58016f..ce085fa444a1 100644
--- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts
+++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
@@ -9,7 +9,8 @@
  */
 
 /dts-v1/;
-/include/ "r8a73a4.dtsi"
+#include "r8a73a4.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
         model = "APE6EVM";
@@ -24,6 +25,11 @@
                 reg = <0 0x40000000 0 0x40000000>;
         };
 
+        memory@200000000 {
+                device_type = "memory";
+                reg = <2 0x00000000 0 0x40000000>;
+        };
+
         ape6evm_fixed_3v3: fixedregulator@0 {
                 compatible = "regulator-fixed";
                 regulator-name = "3V3";
@@ -40,7 +46,7 @@
                         compatible = "smsc,lan9118", "smsc,lan9115";
                         reg = <0x08000000 0x1000>;
                         interrupt-parent = <&irqc1>;
-                        interrupts = <8 0x4>;
+                        interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
                         phy-mode = "mii";
                         reg-io-width = <4>;
                         smsc,irq-active-high;
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 287e047592a0..62d0211bd192 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -9,6 +9,9 @@
  * kind, whether express or implied.
  */
 
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
 / {
         compatible = "renesas,r8a73a4";
         interrupt-parent = <&gic>;
@@ -36,15 +39,15 @@
                         <0 0xf1002000 0 0x1000>,
                         <0 0xf1004000 0 0x2000>,
                         <0 0xf1006000 0 0x2000>;
-                interrupts = <1 9 0xf04>;
+                interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
         };
 
         timer {
                 compatible = "arm,armv7-timer";
-                interrupts = <1 13 0xf08>,
-                                <1 14 0xf08>,
-                                <1 11 0xf08>,
-                                <1 10 0xf08>;
+                interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
         };
 
         irqc0: interrupt-controller@e61c0000 {
@@ -53,14 +56,38 @@
                 interrupt-controller;
                 reg = <0 0xe61c0000 0 0x200>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>,
-                                <0 4 4>, <0 5 4>, <0 6 4>, <0 7 4>,
-                                <0 8 4>, <0 9 4>, <0 10 4>, <0 11 4>,
-                                <0 12 4>, <0 13 4>, <0 14 4>, <0 15 4>,
-                                <0 16 4>, <0 17 4>, <0 18 4>, <0 19 4>,
-                                <0 20 4>, <0 21 4>, <0 22 4>, <0 23 4>,
-                                <0 24 4>, <0 25 4>, <0 26 4>, <0 27 4>,
-                                <0 28 4>, <0 29 4>, <0 30 4>, <0 31 4>;
+                interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 1 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 2 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 3 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 4 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 5 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 6 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 7 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 8 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 9 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 10 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 11 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 12 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 13 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 14 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 15 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 16 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 17 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 18 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 19 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 20 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 21 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 22 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 23 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 24 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 25 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 26 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 27 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 28 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 29 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 30 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 31 IRQ_TYPE_LEVEL_HIGH>;
         };
 
         irqc1: interrupt-controller@e61c0200 {
@@ -69,13 +96,32 @@
                 interrupt-controller;
                 reg = <0 0xe61c0200 0 0x200>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 32 4>, <0 33 4>, <0 34 4>, <0 35 4>,
-                                <0 36 4>, <0 37 4>, <0 38 4>, <0 39 4>,
-                                <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>,
-                                <0 44 4>, <0 45 4>, <0 46 4>, <0 47 4>,
-                                <0 48 4>, <0 49 4>, <0 50 4>, <0 51 4>,
-                                <0 52 4>, <0 53 4>, <0 54 4>, <0 55 4>,
-                                <0 56 4>, <0 57 4>;
+                interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 33 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 34 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 35 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 36 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 37 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 38 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 39 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 40 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 41 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 42 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 43 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 44 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 45 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 46 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 47 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 48 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 49 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 50 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 51 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 52 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 53 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 54 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 55 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 56 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 57 IRQ_TYPE_LEVEL_HIGH>;
         };
 
         dmac: dma-multiplexer@0 {
@@ -91,27 +137,27 @@
                         compatible = "renesas,shdma-r8a73a4";
                         reg = <0 0xe6700020 0 0x89e0>;
                         interrupt-parent = <&gic>;
-                        interrupts = <0 220 4
-                                        0 200 4
-                                        0 201 4
-                                        0 202 4
-                                        0 203 4
-                                        0 204 4
-                                        0 205 4
-                                        0 206 4
-                                        0 207 4
-                                        0 208 4
-                                        0 209 4
-                                        0 210 4
-                                        0 211 4
-                                        0 212 4
-                                        0 213 4
-                                        0 214 4
-                                        0 215 4
-                                        0 216 4
-                                        0 217 4
-                                        0 218 4
-                                        0 219 4>;
+                        interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
+                                        0 200 IRQ_TYPE_LEVEL_HIGH
+                                        0 201 IRQ_TYPE_LEVEL_HIGH
+                                        0 202 IRQ_TYPE_LEVEL_HIGH
+                                        0 203 IRQ_TYPE_LEVEL_HIGH
+                                        0 204 IRQ_TYPE_LEVEL_HIGH
+                                        0 205 IRQ_TYPE_LEVEL_HIGH
+                                        0 206 IRQ_TYPE_LEVEL_HIGH
+                                        0 207 IRQ_TYPE_LEVEL_HIGH
+                                        0 208 IRQ_TYPE_LEVEL_HIGH
+                                        0 209 IRQ_TYPE_LEVEL_HIGH
+                                        0 210 IRQ_TYPE_LEVEL_HIGH
+                                        0 211 IRQ_TYPE_LEVEL_HIGH
+                                        0 212 IRQ_TYPE_LEVEL_HIGH
+                                        0 213 IRQ_TYPE_LEVEL_HIGH
+                                        0 214 IRQ_TYPE_LEVEL_HIGH
+                                        0 215 IRQ_TYPE_LEVEL_HIGH
+                                        0 216 IRQ_TYPE_LEVEL_HIGH
+                                        0 217 IRQ_TYPE_LEVEL_HIGH
+                                        0 218 IRQ_TYPE_LEVEL_HIGH
+                                        0 219 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-names = "error",
                                         "ch0", "ch1", "ch2", "ch3",
                                         "ch4", "ch5", "ch6", "ch7",
@@ -126,7 +172,7 @@
                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
                          <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 69 4>;
+                interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
         };
 
         i2c0: i2c@e6500000 {
@@ -135,7 +181,7 @@
                 compatible = "renesas,rmobile-iic";
                 reg = <0 0xe6500000 0 0x428>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 174 0x4>;
+                interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
@@ -145,7 +191,7 @@
                 compatible = "renesas,rmobile-iic";
                 reg = <0 0xe6510000 0 0x428>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 175 0x4>;
+                interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
@@ -155,7 +201,7 @@
                 compatible = "renesas,rmobile-iic";
                 reg = <0 0xe6520000 0 0x428>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 176 0x4>;
+                interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
@@ -165,7 +211,7 @@
                 compatible = "renesas,rmobile-iic";
                 reg = <0 0xe6530000 0 0x428>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 177 0x4>;
+                interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
@@ -175,7 +221,7 @@
                 compatible = "renesas,rmobile-iic";
                 reg = <0 0xe6540000 0 0x428>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 178 0x4>;
+                interrupts = <0 178 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
@@ -185,7 +231,7 @@
                 compatible = "renesas,rmobile-iic";
                 reg = <0 0xe60b0000 0 0x428>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 179 0x4>;
+                interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
@@ -195,7 +241,7 @@
                 compatible = "renesas,rmobile-iic";
                 reg = <0 0xe6550000 0 0x428>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 184 0x4>;
+                interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
@@ -205,7 +251,7 @@
                 compatible = "renesas,rmobile-iic";
                 reg = <0 0xe6560000 0 0x428>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 185 0x4>;
+                interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
@@ -215,24 +261,24 @@
                 compatible = "renesas,rmobile-iic";
                 reg = <0 0xe6570000 0 0x428>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 173 0x4>;
+                interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
-        mmcif0: mmcif@ee200000 {
+        mmcif0: mmc@ee200000 {
                 compatible = "renesas,sh-mmcif";
                 reg = <0 0xee200000 0 0x80>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 169 0x4>;
+                interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
                 reg-io-width = <4>;
                 status = "disabled";
         };
 
-        mmcif1: mmcif@ee220000 {
+        mmcif1: mmc@ee220000 {
                 compatible = "renesas,sh-mmcif";
                 reg = <0 0xee220000 0 0x80>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 170 0x4>;
+                interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
                 reg-io-width = <4>;
                 status = "disabled";
         };
@@ -242,31 +288,47 @@
                 reg = <0 0xe6050000 0 0x9000>;
                 gpio-controller;
                 #gpio-cells = <2>;
+                interrupts-extended =
+                        <&irqc0  0 0>, <&irqc0  1 0>, <&irqc0  2 0>, <&irqc0  3 0>,
+                        <&irqc0  4 0>, <&irqc0  5 0>, <&irqc0  6 0>, <&irqc0  7 0>,
+                        <&irqc0  8 0>, <&irqc0  9 0>, <&irqc0 10 0>, <&irqc0 11 0>,
+                        <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>,
+                        <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>,
+                        <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>,
+                        <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>,
+                        <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>,
+                        <&irqc1  0 0>, <&irqc1  1 0>, <&irqc1  2 0>, <&irqc1  3 0>,
+                        <&irqc1  4 0>, <&irqc1  5 0>, <&irqc1  6 0>, <&irqc1  7 0>,
+                        <&irqc1  8 0>, <&irqc1  9 0>, <&irqc1 10 0>, <&irqc1 11 0>,
+                        <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>,
+                        <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>,
+                        <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>,
+                        <&irqc1 24 0>, <&irqc1 25 0>;
         };
 
-        sdhi0: sdhi@ee100000 {
+        sdhi0: sd@ee100000 {
                 compatible = "renesas,sdhi-r8a73a4";
                 reg = <0 0xee100000 0 0x100>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 165 4>;
+                interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
                 cap-sd-highspeed;
                 status = "disabled";
         };
 
-        sdhi1: sdhi@ee120000 {
+        sdhi1: sd@ee120000 {
                 compatible = "renesas,sdhi-r8a73a4";
                 reg = <0 0xee120000 0 0x100>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 166 4>;
+                interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
                 cap-sd-highspeed;
                 status = "disabled";
         };
 
-        sdhi2: sdhi@ee140000 {
+        sdhi2: sd@ee140000 {
                 compatible = "renesas,sdhi-r8a73a4";
                 reg = <0 0xee140000 0 0x100>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 167 4>;
+                interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
                 cap-sd-highspeed;
                 status = "disabled";
         };
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
index 1c56c5e56950..95a849bf921f 100644
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
@@ -9,8 +9,9 @@
  */
 
 /dts-v1/;
-/include/ "r8a7740.dtsi"
+#include "r8a7740.dtsi"
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/pwm/pwm.h>
 
 / {
@@ -62,6 +63,44 @@
                 enable-active-high;
         };
 
+        reg_5p0v: regulator@3 {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-5.0V";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-always-on;
+                regulator-boot-on;
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+
+                power-key {
+                        gpios = <&pfc 99 GPIO_ACTIVE_LOW>;
+                        linux,code = <116>;
+                        label = "SW3";
+                        gpio-key,wakeup;
+                };
+
+                back-key {
+                        gpios = <&pfc 100 GPIO_ACTIVE_LOW>;
+                        linux,code = <158>;
+                        label = "SW4";
+                };
+
+                menu-key {
+                        gpios = <&pfc 97 GPIO_ACTIVE_LOW>;
+                        linux,code = <139>;
+                        label = "SW5";
+                };
+
+                home-key {
+                        gpios = <&pfc 98 GPIO_ACTIVE_LOW>;
+                        linux,code = <102>;
+                        label = "SW6";
+                };
+        };
+
         leds {
                 compatible = "gpio-leds";
                 led1 {
@@ -85,32 +124,58 @@
                 default-brightness-level = <9>;
                 pinctrl-0 = <&backlight_pins>;
                 pinctrl-names = "default";
+                power-supply = <&reg_5p0v>;
+                enable-gpios = <&pfc 61 GPIO_ACTIVE_HIGH>;
+        };
+
+        sound {
+                compatible = "simple-audio-card";
+
+                simple-audio-card,format = "i2s";
+
+                simple-audio-card,cpu {
+                        sound-dai = <&sh_fsi2 0>;
+                        bitclock-inversion;
+                };
+
+                simple-audio-card,codec {
+                        sound-dai = <&wm8978>;
+                        bitclock-master;
+                        frame-master;
+                        system-clock-frequency = <12288000>;
+                };
         };
 };
 
 &i2c0 {
         status = "okay";
-        touchscreen: st1232@55 {
+        touchscreen@55 {
                 compatible = "sitronix,st1232";
                 reg = <0x55>;
                 interrupt-parent = <&irqpin1>;
-                interrupts = <2 0>; /* IRQ10: hwirq 2 on irqpin1 */
+                interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
                 pinctrl-0 = <&st1232_pins>;
                 pinctrl-names = "default";
                 gpios = <&pfc 166 GPIO_ACTIVE_LOW>;
         };
+
+        wm8978: wm8978@1a {
+                #sound-dai-cells = <0>;
+                compatible = "wlf,wm8978";
+                reg = <0x1a>;
+        };
 };
 
 &pfc {
         pinctrl-0 = <&scifa1_pins>;
         pinctrl-names = "default";
 
-        scifa1_pins: scifa1 {
+        scifa1_pins: serial1 {
                 renesas,groups = "scifa1_data";
                 renesas,function = "scifa1";
         };
 
-        st1232_pins: st1232 {
+        st1232_pins: touchscreen {
                 renesas,groups = "intc_irq10";
                 renesas,function = "intc";
         };
@@ -125,10 +190,16 @@
                 renesas,function = "mmc0";
         };
 
-        sdhi0_pins: sdhi0 {
+        sdhi0_pins: sd0 {
                 renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp";
                 renesas,function = "sdhi0";
         };
+
+        fsia_pins: sounda {
+                renesas,groups = "fsia_sclk_in", "fsia_mclk_out",
+                                 "fsia_data_in_1", "fsia_data_out_0";
+                renesas,function = "fsia";
+        };
 };
 
 &tpu {
@@ -155,3 +226,10 @@
         cd-gpios = <&pfc 167 GPIO_ACTIVE_LOW>;
         status = "okay";
 };
+
+&sh_fsi2 {
+        pinctrl-0 = <&fsia_pins>;
+        pinctrl-names = "default";
+
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
index 426cd9c3e1c4..a06a11e1a840 100644
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
@@ -9,7 +9,7 @@
  */
 
 /dts-v1/;
-/include/ "r8a7740.dtsi"
+#include "r8a7740.dtsi"
 
 / {
         model = "armadillo 800 eva";
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index ae1e230f711d..8280884bfa59 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -10,6 +10,8 @@
 
 /include/ "skeleton.dtsi"
 
+#include <dt-bindings/interrupt-controller/irq.h>
+
 / {
         compatible = "renesas,r8a7740";
 
@@ -34,12 +36,12 @@
 
         pmu {
                 compatible = "arm,cortex-a9-pmu";
-                interrupts = <0 83 4>;
+                interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
         };
 
         /* irqpin0: IRQ0 - IRQ7 */
         irqpin0: irqpin@e6900000 {
-                compatible = "renesas,intc-irqpin";
+                compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
                 #interrupt-cells = <2>;
                 interrupt-controller;
                 reg = <0xe6900000 4>,
@@ -48,19 +50,19 @@
                         <0xe6900040 1>,
                         <0xe6900060 1>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4>;
+                interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH>;
         };
 
         /* irqpin1: IRQ8 - IRQ15 */
         irqpin1: irqpin@e6900004 {
-                compatible = "renesas,intc-irqpin";
+                compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
                 #interrupt-cells = <2>;
                 interrupt-controller;
                 reg = <0xe6900004 4>,
@@ -69,19 +71,19 @@
                         <0xe6900044 1>,
                         <0xe6900064 1>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4>;
+                interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH>;
         };
 
         /* irqpin2: IRQ16 - IRQ23 */
         irqpin2: irqpin@e6900008 {
-                compatible = "renesas,intc-irqpin";
+                compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
                 #interrupt-cells = <2>;
                 interrupt-controller;
                 reg = <0xe6900008 4>,
@@ -90,19 +92,19 @@
                         <0xe6900048 1>,
                         <0xe6900068 1>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4>;
+                interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH>;
         };
 
         /* irqpin3: IRQ24 - IRQ31 */
         irqpin3: irqpin@e690000c {
-                compatible = "renesas,intc-irqpin";
+                compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
                 #interrupt-cells = <2>;
                 interrupt-controller;
                 reg = <0xe690000c 4>,
@@ -111,14 +113,14 @@
                         <0xe690004c 1>,
                         <0xe690006c 1>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4>;
+                interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH>;
         };
 
         i2c0: i2c@fff20000 {
@@ -127,10 +129,10 @@
                 compatible = "renesas,rmobile-iic";
                 reg = <0xfff20000 0x425>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 201 0x4
-                              0 202 0x4
-                              0 203 0x4
-                              0 204 0x4>;
+                interrupts = <0 201 IRQ_TYPE_LEVEL_HIGH
+                              0 202 IRQ_TYPE_LEVEL_HIGH
+                              0 203 IRQ_TYPE_LEVEL_HIGH
+                              0 204 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
@@ -140,10 +142,10 @@
                 compatible = "renesas,rmobile-iic";
                 reg = <0xe6c20000 0x425>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 70 0x4
-                              0 71 0x4
-                              0 72 0x4
-                              0 73 0x4>;
+                interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH
+                              0 71 IRQ_TYPE_LEVEL_HIGH
+                              0 72 IRQ_TYPE_LEVEL_HIGH
+                              0 73 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
@@ -153,6 +155,15 @@
                       <0xe605800c 0x20>;
                 gpio-controller;
                 #gpio-cells = <2>;
+                interrupts-extended =
+                        <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
+                        <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
+                        <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
+                        <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
+                        <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
+                        <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
+                        <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
+                        <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
         };
 
         tpu: pwm@e6600000 {
@@ -162,36 +173,57 @@
                 #pwm-cells = <3>;
         };
 
-        mmcif0: mmcif@e6bd0000 {
+        mmcif0: mmc@e6bd0000 {
                 compatible = "renesas,sh-mmcif";
                 reg = <0xe6bd0000 0x100>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 56 4
-                                0 57 4>;
+                interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH
+                              0 57 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
-        sdhi0: sdhi@e6850000 {
+        sdhi0: sd@e6850000 {
                 compatible = "renesas,sdhi-r8a7740";
                 reg = <0xe6850000 0x100>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 117 4
-                                0 118 4
-                                0 119 4>;
+                interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH
+                              0 118 IRQ_TYPE_LEVEL_HIGH
+                              0 119 IRQ_TYPE_LEVEL_HIGH>;
                 cap-sd-highspeed;
                 cap-sdio-irq;
                 status = "disabled";
         };
 
-        sdhi1: sdhi@e6860000 {
+        sdhi1: sd@e6860000 {
                 compatible = "renesas,sdhi-r8a7740";
                 reg = <0xe6860000 0x100>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 121 4
-                                0 122 4
-                                0 123 4>;
+                interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH
+                              0 122 IRQ_TYPE_LEVEL_HIGH
+                              0 123 IRQ_TYPE_LEVEL_HIGH>;
+                cap-sd-highspeed;
+                cap-sdio-irq;
+                status = "disabled";
+        };
+
+        sdhi2: sd@e6870000 {
+                compatible = "renesas,sdhi-r8a7740";
+                reg = <0xe6870000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH
+                              0 126 IRQ_TYPE_LEVEL_HIGH
+                              0 127 IRQ_TYPE_LEVEL_HIGH>;
                 cap-sd-highspeed;
                 cap-sdio-irq;
                 status = "disabled";
         };
+
+        sh_fsi2: sound@fe1f0000 {
+                #sound-dai-cells = <1>;
+                compatible = "renesas,sh_fsi2";
+                reg = <0xfe1f0000 0x400>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 9 0x4>;
+                status = "disabled";
+        };
 };
diff --git a/arch/arm/boot/dts/r8a7778-bockw-reference.dts b/arch/arm/boot/dts/r8a7778-bockw-reference.dts
index 969e386e852c..bb62c7a906f4 100644
--- a/arch/arm/boot/dts/r8a7778-bockw-reference.dts
+++ b/arch/arm/boot/dts/r8a7778-bockw-reference.dts
@@ -15,7 +15,8 @@
  */
 
 /dts-v1/;
-/include/ "r8a7778.dtsi"
+#include "r8a7778.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
         model = "bockw";
@@ -45,13 +46,65 @@
 
                 phy-mode = "mii";
                 interrupt-parent = <&irqpin>;
-                interrupts = <0 0>; /* IRQ0: hwirq 0 on irqpin */
+                interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
                 reg-io-width = <4>;
                 vddvario-supply = <&fixedregulator3v3>;
                 vdd33a-supply = <&fixedregulator3v3>;
         };
+
+};
+
+&mmcif {
+        pinctrl-0 = <&mmc_pins>;
+        pinctrl-names = "default";
+
+        vmmc-supply = <&fixedregulator3v3>;
+        bus-width = <8>;
+        broken-cd;
+        status = "okay";
 };
 
 &irqpin {
         status = "okay";
 };
+
+&pfc {
+        pinctrl-0 = <&scif0_pins>;
+        pinctrl-names = "default";
+
+        scif0_pins: serial0 {
+                renesas,groups = "scif0_data_a", "scif0_ctrl";
+                renesas,function = "scif0";
+        };
+
+        mmc_pins: mmc {
+                renesas,groups = "mmc_data8", "mmc_ctrl";
+                renesas,function = "mmc";
+        };
+
+        sdhi0_pins: sd0 {
+                renesas,groups = "sdhi0_data4", "sdhi0_ctrl",
+                                  "sdhi0_cd", "sdhi0_wp";
+                renesas,function = "sdhi0";
+        };
+
+        hspi0_pins: hspi0 {
+                renesas,groups = "hspi0_a";
+                renesas,function = "hspi0";
+        };
+};
+
+&sdhi0 {
+        pinctrl-0 = <&sdhi0_pins>;
+        pinctrl-names = "default";
+
+        vmmc-supply = <&fixedregulator3v3>;
+        bus-width = <4>;
+        status = "okay";
+};
+
+&hspi0 {
+        pinctrl-0 = <&hspi0_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/r8a7778-bockw.dts
index 12bbebc9c955..46a884d45175 100644
--- a/arch/arm/boot/dts/r8a7778-bockw.dts
+++ b/arch/arm/boot/dts/r8a7778-bockw.dts
@@ -15,7 +15,7 @@
  */
 
 /dts-v1/;
-/include/ "r8a7778.dtsi"
+#include "r8a7778.dtsi"
 
 / {
         model = "bockw";
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index a6308a399e2d..ddb3bd7a8838 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -16,6 +16,8 @@
 
 /include/ "skeleton.dtsi"
 
+#include <dt-bindings/interrupt-controller/irq.h>
+
 / {
         compatible = "renesas,r8a7778";
 
@@ -25,6 +27,12 @@
                 };
         };
 
+        aliases {
+                spi0 = &hspi0;
+                spi1 = &hspi1;
+                spi2 = &hspi2;
+        };
+
         gic: interrupt-controller@fe438000 {
                 compatible = "arm,cortex-a9-gic";
                 #interrupt-cells = <3>;
@@ -35,7 +43,7 @@
 
         /* irqpin: IRQ0 - IRQ3 */
         irqpin: irqpin@fe78001c {
-                compatible = "renesas,intc-irqpin";
+                compatible = "renesas,intc-irqpin-r8a7778", "renesas,intc-irqpin";
                 #interrupt-cells = <2>;
                 interrupt-controller;
                 status = "disabled"; /* default off */
@@ -45,10 +53,10 @@
                         <0xfe780044 4>,
                         <0xfe780064 4>;
                 interrupt-parent = <&gic>;
-                interrupts =   <0 27 0x4
-                                0 28 0x4
-                                0 29 0x4
-                                0 30 0x4>;
+                interrupts =   <0 27 IRQ_TYPE_LEVEL_HIGH
+                                0 28 IRQ_TYPE_LEVEL_HIGH
+                                0 29 IRQ_TYPE_LEVEL_HIGH
+                                0 30 IRQ_TYPE_LEVEL_HIGH>;
                 sense-bitfield-width = <2>;
         };
 
@@ -56,7 +64,7 @@
                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
                 reg = <0xffc40000 0x2c>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 103 0x4>;
+                interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 0 32>;
@@ -68,7 +76,7 @@
                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
                 reg = <0xffc41000 0x2c>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 103 0x4>;
+                interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 32 32>;
@@ -80,7 +88,7 @@
                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
                 reg = <0xffc42000 0x2c>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 103 0x4>;
+                interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 64 32>;
@@ -92,7 +100,7 @@
                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
                 reg = <0xffc43000 0x2c>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 103 0x4>;
+                interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 96 32>;
@@ -104,7 +112,7 @@
                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
                 reg = <0xffc44000 0x2c>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 103 0x4>;
+                interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 128 27>;
@@ -114,6 +122,148 @@
 
         pfc: pfc@fffc0000 {
                 compatible = "renesas,pfc-r8a7778";
-                reg = <0xfffc000 0x118>;
+                reg = <0xfffc0000 0x118>;
+        };
+
+        i2c0: i2c@ffc70000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,i2c-r8a7778";
+                reg = <0xffc70000 0x1000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+
+        i2c1: i2c@ffc71000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,i2c-r8a7778";
+                reg = <0xffc71000 0x1000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+
+        i2c2: i2c@ffc72000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,i2c-r8a7778";
+                reg = <0xffc72000 0x1000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+
+        i2c3: i2c@ffc73000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,i2c-r8a7778";
+                reg = <0xffc73000 0x1000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+
+        mmcif: mmc@ffe4e000 {
+                compatible = "renesas,sh-mmcif";
+                reg = <0xffe4e000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+
+        sdhi0: sd@ffe4c000 {
+                compatible = "renesas,sdhi-r8a7778";
+                reg = <0xffe4c000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
+                cap-sd-highspeed;
+                cap-sdio-irq;
+                status = "disabled";
+        };
+
+        sdhi1: sd@ffe4d000 {
+                compatible = "renesas,sdhi-r8a7778";
+                reg = <0xffe4d000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
+                cap-sd-highspeed;
+                cap-sdio-irq;
+                status = "disabled";
+        };
+
+        sdhi2: sd@ffe4f000 {
+                compatible = "renesas,sdhi-r8a7778";
+                reg = <0xffe4f000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
+                cap-sd-highspeed;
+                cap-sdio-irq;
+                status = "disabled";
+        };
+
+        i2c0: i2c@ffc70000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,i2c-r8a7778";
+                reg = <0xffc70000 0x1000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+
+        i2c1: i2c@ffc71000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,i2c-r8a7778";
+                reg = <0xffc71000 0x1000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+
+        i2c2: i2c@ffc72000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,i2c-r8a7778";
+                reg = <0xffc72000 0x1000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+
+        i2c3: i2c@ffc73000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,i2c-r8a7778";
+                reg = <0xffc73000 0x1000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+
+        hspi0: spi@fffc7000 {
+                compatible = "renesas,hspi";
+                reg = <0xfffc7000 0x18>;
+                interrupt-controller = <&gic>;
+                interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+
+        hspi1: spi@fffc8000 {
+                compatible = "renesas,hspi";
+                reg = <0xfffc8000 0x18>;
+                interrupt-controller = <&gic>;
+                interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+
+        hspi2: spi@fffc6000 {
+                compatible = "renesas,hspi";
+                reg = <0xfffc6000 0x18>;
+                interrupt-controller = <&gic>;
+                interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
         };
 };
diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
index ab4110aa3c3b..76f5eef7d1cc 100644
--- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
@@ -10,8 +10,9 @@
  */
 
 /dts-v1/;
-/include/ "r8a7779.dtsi"
+#include "r8a7779.dtsi"
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
         model = "marzen";
@@ -43,7 +44,7 @@
 
                 phy-mode = "mii";
                 interrupt-parent = <&irqpin0>;
-                interrupts = <1 0>; /* IRQ1: hwirq 1 on irqpin0 */
+                interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
                 reg-io-width = <4>;
                 vddvario-supply = <&fixedregulator3v3>;
                 vdd33a-supply = <&fixedregulator3v3>;
@@ -68,7 +69,7 @@
 };
 
 &pfc {
-        pinctrl-0 = <&scif2_pins &scif4_pins &sdhi0_pins>;
+        pinctrl-0 = <&scif2_pins &scif4_pins>;
         pinctrl-names = "default";
 
         lan0_pins: lan0 {
@@ -82,19 +83,38 @@
                 };
         };
 
-        scif2_pins: scif2 {
+        scif2_pins: serial2 {
                 renesas,groups = "scif2_data_c";
                 renesas,function = "scif2";
         };
 
-        scif4_pins: scif4 {
+        scif4_pins: serial4 {
                 renesas,groups = "scif4_data";
                 renesas,function = "scif4";
         };
 
-        sdhi0_pins: sdhi0 {
-                renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd",
-                                 "sdhi0_wp";
+        sdhi0_pins: sd0 {
+                renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
                 renesas,function = "sdhi0";
         };
+
+        hspi0_pins: hspi0 {
+                renesas,groups = "hspi0";
+                renesas,function = "hspi0";
+        };
+};
+
+&sdhi0 {
+        pinctrl-0 = <&sdhi0_pins>;
+        pinctrl-names = "default";
+
+        vmmc-supply = <&fixedregulator3v3>;
+        bus-width = <4>;
+        status = "okay";
+};
+
+&hspi0 {
+        pinctrl-0 = <&hspi0_pins>;
+        pinctrl-names = "default";
+        status = "okay";
 };
diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index f3f7f7999736..a7af2c2371f2 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -10,7 +10,7 @@
  */
 
 /dts-v1/;
-/include/ "r8a7779.dtsi"
+#include "r8a7779.dtsi"
 
 / {
         model = "marzen";
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index 19faeac3fd2e..d0561d4c7c46 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -11,6 +11,8 @@
 
 /include/ "skeleton.dtsi"
 
+#include <dt-bindings/interrupt-controller/irq.h>
+
 / {
         compatible = "renesas,r8a7779";
 
@@ -40,6 +42,12 @@
                 };
         };
 
+        aliases {
+                spi0 = &hspi0;
+                spi1 = &hspi1;
+                spi2 = &hspi2;
+        };
+
         gic: interrupt-controller@f0001000 {
                 compatible = "arm,cortex-a9-gic";
                 #interrupt-cells = <3>;
@@ -52,7 +60,7 @@
                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
                 reg = <0xffc40000 0x2c>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 141 0x4>;
+                interrupts = <0 141 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 0 32>;
@@ -64,7 +72,7 @@
                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
                 reg = <0xffc41000 0x2c>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 142 0x4>;
+                interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 32 32>;
@@ -76,7 +84,7 @@
                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
                 reg = <0xffc42000 0x2c>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 143 0x4>;
+                interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 64 32>;
@@ -88,7 +96,7 @@
                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
                 reg = <0xffc43000 0x2c>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 144 0x4>;
+                interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 96 32>;
@@ -100,7 +108,7 @@
                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
                 reg = <0xffc44000 0x2c>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 145 0x4>;
+                interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 128 32>;
@@ -112,7 +120,7 @@
                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
                 reg = <0xffc45000 0x2c>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 146 0x4>;
+                interrupts = <0 146 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 160 32>;
@@ -124,7 +132,7 @@
                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
                 reg = <0xffc46000 0x2c>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 147 0x4>;
+                interrupts = <0 147 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 192 9>;
@@ -133,7 +141,7 @@
         };
 
         irqpin0: irqpin@fe780010 {
-                compatible = "renesas,intc-irqpin";
+                compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
                 #interrupt-cells = <2>;
                 status = "disabled";
                 interrupt-controller;
@@ -143,50 +151,50 @@
                         <0xfe780044 4>,
                         <0xfe780064 4>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 27 0x4
-                                0 28 0x4
-                                0 29 0x4
-                                0 30 0x4>;
+                interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH
+                              0 28 IRQ_TYPE_LEVEL_HIGH
+                              0 29 IRQ_TYPE_LEVEL_HIGH
+                              0 30 IRQ_TYPE_LEVEL_HIGH>;
                 sense-bitfield-width = <2>;
         };
 
         i2c0: i2c@ffc70000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
-                compatible = "renesas,rmobile-iic";
+                compatible = "renesas,i2c-r8a7779";
                 reg = <0xffc70000 0x1000>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 79 0x4>;
+                interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
         i2c1: i2c@ffc71000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
-                compatible = "renesas,rmobile-iic";
+                compatible = "renesas,i2c-r8a7779";
                 reg = <0xffc71000 0x1000>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 82 0x4>;
+                interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
         i2c2: i2c@ffc72000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
-                compatible = "renesas,rmobile-iic";
+                compatible = "renesas,i2c-r8a7779";
                 reg = <0xffc72000 0x1000>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 80 0x4>;
+                interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
         i2c3: i2c@ffc73000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
-                compatible = "renesas,rmobile-iic";
+                compatible = "renesas,i2c-r8a7779";
                 reg = <0xffc73000 0x1000>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 81 0x4>;
+                interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
@@ -204,6 +212,70 @@
                 compatible = "renesas,rcar-sata";
                 reg = <0xfc600000 0x2000>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 100 0x4>;
+                interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
+        };
+
+        sdhi0: sd@ffe4c000 {
+                compatible = "renesas,sdhi-r8a7779";
+                reg = <0xffe4c000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
+                cap-sd-highspeed;
+                cap-sdio-irq;
+                status = "disabled";
+        };
+
+        sdhi1: sd@ffe4d000 {
+                compatible = "renesas,sdhi-r8a7779";
+                reg = <0xffe4d000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
+                cap-sd-highspeed;
+                cap-sdio-irq;
+                status = "disabled";
+        };
+
+        sdhi2: sd@ffe4e000 {
+                compatible = "renesas,sdhi-r8a7779";
+                reg = <0xffe4e000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
+                cap-sd-highspeed;
+                cap-sdio-irq;
+                status = "disabled";
+        };
+
+        sdhi3: sd@ffe4f000 {
+                compatible = "renesas,sdhi-r8a7779";
+                reg = <0xffe4f000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
+                cap-sd-highspeed;
+                cap-sdio-irq;
+                status = "disabled";
+        };
+
+        hspi0: spi@fffc7000 {
+                compatible = "renesas,hspi";
+                reg = <0xfffc7000 0x18>;
+                interrupt-controller = <&gic>;
+                interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+
+        hspi1: spi@fffc8000 {
+                compatible = "renesas,hspi";
+                reg = <0xfffc8000 0x18>;
+                interrupt-controller = <&gic>;
+                interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+
+        hspi2: spi@fffc6000 {
+                compatible = "renesas,hspi";
+                reg = <0xfffc6000 0x18>;
+                interrupt-controller = <&gic>;
+                interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
         };
 };
diff --git a/arch/arm/boot/dts/r8a7790-lager-reference.dts b/arch/arm/boot/dts/r8a7790-lager-reference.dts
deleted file mode 100644
index c462ef138922..000000000000
--- a/arch/arm/boot/dts/r8a7790-lager-reference.dts
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Device Tree Source for the Lager board
- *
- * Copyright (C) 2013 Renesas Solutions Corp.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-/dts-v1/;
-/include/ "r8a7790.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-        model = "Lager";
-        compatible = "renesas,lager-reference", "renesas,r8a7790";
-
-        chosen {
-                bootargs = "console=ttySC6,115200 ignore_loglevel rw";
-        };
-
-        memory@40000000 {
-                device_type = "memory";
-                reg = <0 0x40000000 0 0x80000000>;
-        };
-
-        lbsc {
-                #address-cells = <1>;
-                #size-cells = <1>;
-        };
-
-        leds {
-                compatible = "gpio-leds";
-                led6 {
-                        gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
-                };
-                led7 {
-                        gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>;
-                };
-                led8 {
-                        gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
-                };
-        };
-};
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 203bd089af29..57569cba1528 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -9,7 +9,8 @@
  */
 
 /dts-v1/;
-/include/ "r8a7790.dtsi"
+#include "r8a7790.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
         model = "Lager";
@@ -24,8 +25,69 @@
                 reg = <0 0x40000000 0 0x80000000>;
         };
 
+        memory@180000000 {
+                device_type = "memory";
+                reg = <1 0x80000000 0 0x80000000>;
+        };
+
         lbsc {
                 #address-cells = <1>;
                 #size-cells = <1>;
         };
+
+        leds {
+                compatible = "gpio-leds";
+                led6 {
+                        gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
+                };
+                led7 {
+                        gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>;
+                };
+                led8 {
+                        gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
+                };
+        };
+
+        fixedregulator3v3: fixedregulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-3.3V";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-boot-on;
+                regulator-always-on;
+        };
+};
+
+&extal_clk {
+        clock-frequency = <20000000>;
+};
+
+&pfc {
+        pinctrl-0 = <&scif0_pins &scif1_pins>;
+        pinctrl-names = "default";
+
+        scif0_pins: serial0 {
+                renesas,groups = "scif0_data";
+                renesas,function = "scif0";
+        };
+
+        scif1_pins: serial1 {
+                renesas,groups = "scif1_data";
+                renesas,function = "scif1";
+        };
+
+        mmc1_pins: mmc1 {
+                renesas,groups = "mmc1_data8", "mmc1_ctrl";
+                renesas,function = "mmc1";
+        };
+};
+
+&mmcif1 {
+        pinctrl-0 = <&mmc1_pins>;
+        pinctrl-names = "default";
+
+        vmmc-supply = <&fixedregulator3v3>;
+        bus-width = <8>;
+        non-removable;
+        status = "okay";
 };
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 9987dd0e9c59..f48487c2a970 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -8,6 +8,10 @@
  * kind, whether express or implied.
  */
 
+#include <dt-bindings/clock/r8a7790-clock.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
 / {
         compatible = "renesas,r8a7790";
         interrupt-parent = <&gic>;
@@ -84,14 +88,14 @@
                         <0 0xf1002000 0 0x1000>,
                         <0 0xf1004000 0 0x2000>,
                         <0 0xf1006000 0 0x2000>;
-                interrupts = <1 9 0xf04>;
+                interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
         };
 
         gpio0: gpio@e6050000 {
                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
                 reg = <0 0xe6050000 0 0x50>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 4 0x4>;
+                interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 0 32>;
@@ -103,7 +107,7 @@
                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
                 reg = <0 0xe6051000 0 0x50>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 5 0x4>;
+                interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 32 32>;
@@ -115,7 +119,7 @@
                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
                 reg = <0 0xe6052000 0 0x50>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 6 0x4>;
+                interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 64 32>;
@@ -127,7 +131,7 @@
                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
                 reg = <0 0xe6053000 0 0x50>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 7 0x4>;
+                interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 96 32>;
@@ -139,7 +143,7 @@
                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
                 reg = <0 0xe6054000 0 0x50>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 8 0x4>;
+                interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 128 32>;
@@ -151,7 +155,7 @@
                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
                 reg = <0 0xe6055000 0 0x50>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 9 0x4>;
+                interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 160 32>;
@@ -159,21 +163,31 @@
                 interrupt-controller;
         };
 
+        thermal@e61f0000 {
+                compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
+                reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
+        };
+
         timer {
                 compatible = "arm,armv7-timer";
-                interrupts = <1 13 0xf08>,
-                                <1 14 0xf08>,
-                                <1 11 0xf08>,
-                                <1 10 0xf08>;
+                interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
         };
 
         irqc0: interrupt-controller@e61c0000 {
-                compatible = "renesas,irqc";
+                compatible = "renesas,irqc-r8a7790", "renesas,irqc";
                 #interrupt-cells = <2>;
                 interrupt-controller;
                 reg = <0 0xe61c0000 0 0x200>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>;
+                interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 1 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 2 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 3 IRQ_TYPE_LEVEL_HIGH>;
         };
 
         i2c0: i2c@e6508000 {
@@ -182,7 +196,8 @@
                 compatible = "renesas,i2c-r8a7790";
                 reg = <0 0xe6508000 0 0x40>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 287 0x4>;
+                interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7790_CLK_I2C0>;
                 status = "disabled";
         };
 
@@ -192,7 +207,8 @@
                 compatible = "renesas,i2c-r8a7790";
                 reg = <0 0xe6518000 0 0x40>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 288 0x4>;
+                interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7790_CLK_I2C1>;
                 status = "disabled";
         };
 
@@ -202,7 +218,8 @@
                 compatible = "renesas,i2c-r8a7790";
                 reg = <0 0xe6530000 0 0x40>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 286 0x4>;
+                interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7790_CLK_I2C2>;
                 status = "disabled";
         };
 
@@ -212,24 +229,27 @@
                 compatible = "renesas,i2c-r8a7790";
                 reg = <0 0xe6540000 0 0x40>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 290 0x4>;
+                interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7790_CLK_I2C3>;
                 status = "disabled";
         };
 
         mmcif0: mmcif@ee200000 {
-                compatible = "renesas,sh-mmcif";
+                compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
                 reg = <0 0xee200000 0 0x80>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 169 0x4>;
+                interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
                 reg-io-width = <4>;
                 status = "disabled";
         };
 
-        mmcif1: mmcif@ee220000 {
-                compatible = "renesas,sh-mmcif";
+        mmcif1: mmc@ee220000 {
+                compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
                 reg = <0 0xee220000 0 0x80>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 170 0x4>;
+                interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
                 reg-io-width = <4>;
                 status = "disabled";
         };
@@ -239,39 +259,372 @@
                 reg = <0 0xe6060000 0 0x250>;
         };
 
-        sdhi0: sdhi@ee100000 {
+        sdhi0: sd@ee100000 {
                 compatible = "renesas,sdhi-r8a7790";
                 reg = <0 0xee100000 0 0x200>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 165 4>;
+                interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
                 cap-sd-highspeed;
                 status = "disabled";
         };
 
-        sdhi1: sdhi@ee120000 {
+        sdhi1: sd@ee120000 {
                 compatible = "renesas,sdhi-r8a7790";
                 reg = <0 0xee120000 0 0x200>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 166 4>;
+                interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
                 cap-sd-highspeed;
                 status = "disabled";
         };
 
-        sdhi2: sdhi@ee140000 {
+        sdhi2: sd@ee140000 {
                 compatible = "renesas,sdhi-r8a7790";
                 reg = <0 0xee140000 0 0x100>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 167 4>;
+                interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
                 cap-sd-highspeed;
                 status = "disabled";
         };
 
-        sdhi3: sdhi@ee160000 {
+        sdhi3: sd@ee160000 {
                 compatible = "renesas,sdhi-r8a7790";
                 reg = <0 0xee160000 0 0x100>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 168 4>;
+                interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
                 cap-sd-highspeed;
                 status = "disabled";
         };
+
+        clocks {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+
+                /* External root clock */
+                extal_clk: extal_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        /* This value must be overriden by the board. */
+                        clock-frequency = <0>;
+                        clock-output-names = "extal";
+                };
+
+                /* Special CPG clocks */
+                cpg_clocks: cpg_clocks@e6150000 {
+                        compatible = "renesas,r8a7790-cpg-clocks",
+                                     "renesas,rcar-gen2-cpg-clocks";
+                        reg = <0 0xe6150000 0 0x1000>;
+                        clocks = <&extal_clk>;
+                        #clock-cells = <1>;
+                        clock-output-names = "main", "pll0", "pll1", "pll3",
+                                             "lb", "qspi", "sdh", "sd0", "sd1",
+                                             "z";
+                };
+
+                /* Variable factor clocks */
+                sd2_clk: sd2_clk@e6150078 {
+                        compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe6150078 0 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "sd2";
+                };
+                sd3_clk: sd3_clk@e615007c {
+                        compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe615007c 0 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "sd3";
+                };
+                mmc0_clk: mmc0_clk@e6150240 {
+                        compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe6150240 0 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "mmc0";
+                };
+                mmc1_clk: mmc1_clk@e6150244 {
+                        compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe6150244 0 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "mmc1";
+                };
+                ssp_clk: ssp_clk@e6150248 {
+                        compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe6150248 0 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "ssp";
+                };
+                ssprs_clk: ssprs_clk@e615024c {
+                        compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe615024c 0 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "ssprs";
+                };
+
+                /* Fixed factor clocks */
+                pll1_div2_clk: pll1_div2_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clock-output-names = "pll1_div2";
+                };
+                z2_clk: z2_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clock-output-names = "z2";
+                };
+                zg_clk: zg_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <3>;
+                        clock-mult = <1>;
+                        clock-output-names = "zg";
+                };
+                zx_clk: zx_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <3>;
+                        clock-mult = <1>;
+                        clock-output-names = "zx";
+                };
+                zs_clk: zs_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <6>;
+                        clock-mult = <1>;
+                        clock-output-names = "zs";
+                };
+                hp_clk: hp_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <12>;
+                        clock-mult = <1>;
+                        clock-output-names = "hp";
+                };
+                i_clk: i_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clock-output-names = "i";
+                };
+                b_clk: b_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <12>;
+                        clock-mult = <1>;
+                        clock-output-names = "b";
+                };
+                p_clk: p_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <24>;
+                        clock-mult = <1>;
+                        clock-output-names = "p";
+                };
+                cl_clk: cl_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <48>;
+                        clock-mult = <1>;
+                        clock-output-names = "cl";
+                };
+                m2_clk: m2_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <8>;
+                        clock-mult = <1>;
+                        clock-output-names = "m2";
+                };
+                imp_clk: imp_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <4>;
+                        clock-mult = <1>;
+                        clock-output-names = "imp";
+                };
+                rclk_clk: rclk_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <(48 * 1024)>;
+                        clock-mult = <1>;
+                        clock-output-names = "rclk";
+                };
+                oscclk_clk: oscclk_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <(12 * 1024)>;
+                        clock-mult = <1>;
+                        clock-output-names = "oscclk";
+                };
+                zb3_clk: zb3_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
+                        #clock-cells = <0>;
+                        clock-div = <4>;
+                        clock-mult = <1>;
+                        clock-output-names = "zb3";
+                };
+                zb3d2_clk: zb3d2_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
+                        #clock-cells = <0>;
+                        clock-div = <8>;
+                        clock-mult = <1>;
+                        clock-output-names = "zb3d2";
+                };
+                ddr_clk: ddr_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
+                        #clock-cells = <0>;
+                        clock-div = <8>;
+                        clock-mult = <1>;
+                        clock-output-names = "ddr";
+                };
+                mp_clk: mp_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-div = <15>;
+                        clock-mult = <1>;
+                        clock-output-names = "mp";
+                };
+                cp_clk: cp_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&extal_clk>;
+                        #clock-cells = <0>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clock-output-names = "cp";
+                };
+
+                /* Gate clocks */
+                mstp0_clks: mstp0_clks@e6150130 {
+                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
+                        clocks = <&mp_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <R8A7790_CLK_MSIOF0>;
+                        clock-output-names = "msiof0";
+                };
+                mstp1_clks: mstp1_clks@e6150134 {
+                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
+                        clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
+                                 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
+                                 <&zs_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
+                                R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1
+                                R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_RT R8A7790_CLK_VSP1_SY
+                        >;
+                        clock-output-names =
+                                "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
+                                "vsp1-du0", "vsp1-rt", "vsp1-sy";
+                };
+                mstp2_clks: mstp2_clks@e6150138 {
+                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
+                        clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
+                                 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
+                                R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
+                                R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
+                        >;
+                        clock-output-names =
+                                "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
+                                "scifb1", "msiof1", "msiof3", "scifb2";
+                };
+                mstp3_clks: mstp3_clks@e615013c {
+                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
+                        clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>,
+                                 <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>,
+                                 <&mmc0_clk>, <&rclk_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
+                                R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0
+                                R8A7790_CLK_MMCIF0 R8A7790_CLK_CMT1
+                        >;
+                        clock-output-names =
+                                "tpu0", "mmcif1", "sdhi3", "sdhi2",
+                                "sdhi1", "sdhi0", "mmcif0", "cmt1";
+                };
+                mstp5_clks: mstp5_clks@e6150144 {
+                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
+                        clocks = <&extal_clk>, <&p_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <R8A7790_CLK_THERMAL R8A7790_CLK_PWM>;
+                        clock-output-names = "thermal", "pwm";
+                };
+                mstp7_clks: mstp7_clks@e615014c {
+                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
+                        clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
+                                 <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
+                                 <&zx_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
+                                R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
+                                R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
+                                R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
+                        >;
+                        clock-output-names =
+                                "ehci", "hsusb", "hscif1", "hscif0", "scif1",
+                                "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
+                };
+                mstp8_clks: mstp8_clks@e6150990 {
+                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
+                        clocks = <&p_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <R8A7790_CLK_ETHER>;
+                        clock-output-names = "ether";
+                };
+                mstp9_clks: mstp9_clks@e6150994 {
+                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
+                        clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>,
+                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD
+                                R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1
+                                R8A7790_CLK_I2C0
+                        >;
+                        clock-output-names =
+                                "rcan1", "rcan0", "qspi_mod", "i2c3", "i2c2", "i2c1", "i2c0";
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/r8a7791-koelsch-reference.dts b/arch/arm/boot/dts/r8a7791-koelsch-reference.dts
new file mode 100644
index 000000000000..588ca17ea1f0
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7791-koelsch-reference.dts
@@ -0,0 +1,115 @@
+/*
+ * Device Tree Source for the Koelsch board
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013 Renesas Solutions Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "r8a7791.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+        model = "Koelsch";
+        compatible = "renesas,koelsch-reference", "renesas,r8a7791";
+
+        chosen {
+                bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp";
+        };
+
+        memory@40000000 {
+                device_type = "memory";
+                reg = <0 0x40000000 0 0x80000000>;
+        };
+
+        lbsc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+
+                key-a {
+                        gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
+                        linux,code = <30>;
+                        label = "SW30";
+                        gpio-key,wakeup;
+                        debounce-interval = <20>;
+                };
+                key-b {
+                        gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
+                        linux,code = <48>;
+                        label = "SW31";
+                        gpio-key,wakeup;
+                        debounce-interval = <20>;
+                };
+                key-c {
+                        gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
+                        linux,code = <46>;
+                        label = "SW32";
+                        gpio-key,wakeup;
+                        debounce-interval = <20>;
+                };
+                key-d {
+                        gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
+                        linux,code = <32>;
+                        label = "SW33";
+                        gpio-key,wakeup;
+                        debounce-interval = <20>;
+                };
+                key-e {
+                        gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
+                        linux,code = <18>;
+                        label = "SW34";
+                        gpio-key,wakeup;
+                        debounce-interval = <20>;
+                };
+                key-f {
+                        gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
+                        linux,code = <33>;
+                        label = "SW35";
+                        gpio-key,wakeup;
+                        debounce-interval = <20>;
+                };
+                key-g {
+                        gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
+                        linux,code = <34>;
+                        label = "SW36";
+                        gpio-key,wakeup;
+                        debounce-interval = <20>;
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                led6 {
+                        gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+                };
+                led7 {
+                        gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+                };
+                led8 {
+                        gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
+                };
+        };
+};
+
+&pfc {
+        pinctrl-0 = <&scif0_pins &scif1_pins>;
+        pinctrl-names = "default";
+
+        scif0_pins: serial0 {
+                renesas,groups = "scif0_data_d";
+                renesas,function = "scif0";
+        };
+
+        scif1_pins: serial1 {
+                renesas,groups = "scif1_data_d";
+                renesas,function = "scif1";
+        };
+};
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index 1ce5250ec278..fd556c3483e3 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -10,7 +10,8 @@
  */
 
 /dts-v1/;
-/include/ "r8a7791.dtsi"
+#include "r8a7791.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
         model = "Koelsch";
@@ -29,4 +30,36 @@
                 #address-cells = <1>;
                 #size-cells = <1>;
         };
+
+        leds {
+                compatible = "gpio-leds";
+                led6 {
+                        gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+                };
+                led7 {
+                        gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+                };
+                led8 {
+                        gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
+                };
+        };
+};
+
+&extal_clk {
+        clock-frequency = <20000000>;
+};
+
+&pfc {
+        pinctrl-0 = <&scif0_pins &scif1_pins>;
+        pinctrl-names = "default";
+
+        scif0_pins: serial0 {
+                renesas,groups = "scif0_data_d";
+                renesas,function = "scif0";
+        };
+
+        scif1_pins: serial1 {
+                renesas,groups = "scif1_data_d";
+                renesas,function = "scif1";
+        };
 };
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index fea5cfef4691..19c65509a22d 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -9,6 +9,10 @@
  * kind, whether express or implied.
  */
 
+#include <dt-bindings/clock/r8a7791-clock.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
 / {
         compatible = "renesas,r8a7791";
         interrupt-parent = <&gic>;
@@ -43,32 +47,463 @@
                         <0 0xf1002000 0 0x1000>,
                         <0 0xf1004000 0 0x2000>,
                         <0 0xf1006000 0 0x2000>;
-                interrupts = <1 9 0xf04>;
+                interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+        };
+
+        gpio0: gpio@e6050000 {
+                compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
+                reg = <0 0xe6050000 0 0x50>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
+                #gpio-cells = <2>;
+                gpio-controller;
+                gpio-ranges = <&pfc 0 0 32>;
+                #interrupt-cells = <2>;
+                interrupt-controller;
+        };
+
+        gpio1: gpio@e6051000 {
+                compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
+                reg = <0 0xe6051000 0 0x50>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
+                #gpio-cells = <2>;
+                gpio-controller;
+                gpio-ranges = <&pfc 0 32 32>;
+                #interrupt-cells = <2>;
+                interrupt-controller;
+        };
+
+        gpio2: gpio@e6052000 {
+                compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
+                reg = <0 0xe6052000 0 0x50>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
+                #gpio-cells = <2>;
+                gpio-controller;
+                gpio-ranges = <&pfc 0 64 32>;
+                #interrupt-cells = <2>;
+                interrupt-controller;
+        };
+
+        gpio3: gpio@e6053000 {
+                compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
+                reg = <0 0xe6053000 0 0x50>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
+                #gpio-cells = <2>;
+                gpio-controller;
+                gpio-ranges = <&pfc 0 96 32>;
+                #interrupt-cells = <2>;
+                interrupt-controller;
+        };
+
+        gpio4: gpio@e6054000 {
+                compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
+                reg = <0 0xe6054000 0 0x50>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
+                #gpio-cells = <2>;
+                gpio-controller;
+                gpio-ranges = <&pfc 0 128 32>;
+                #interrupt-cells = <2>;
+                interrupt-controller;
+        };
+
+        gpio5: gpio@e6055000 {
+                compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
+                reg = <0 0xe6055000 0 0x50>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
+                #gpio-cells = <2>;
+                gpio-controller;
+                gpio-ranges = <&pfc 0 160 32>;
+                #interrupt-cells = <2>;
+                interrupt-controller;
+        };
+
+        gpio6: gpio@e6055400 {
+                compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
+                reg = <0 0xe6055400 0 0x50>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
+                #gpio-cells = <2>;
+                gpio-controller;
+                gpio-ranges = <&pfc 0 192 32>;
+                #interrupt-cells = <2>;
+                interrupt-controller;
+        };
+
+        gpio7: gpio@e6055800 {
+                compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
+                reg = <0 0xe6055800 0 0x50>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
+                #gpio-cells = <2>;
+                gpio-controller;
+                gpio-ranges = <&pfc 0 224 26>;
+                #interrupt-cells = <2>;
+                interrupt-controller;
+        };
+
+        thermal@e61f0000 {
+                compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
+                reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
         };
 
         timer {
                 compatible = "arm,armv7-timer";
-                interrupts = <1 13 0xf08>,
-                                <1 14 0xf08>,
-                                <1 11 0xf08>,
-                                <1 10 0xf08>;
+                interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
         };
 
         irqc0: interrupt-controller@e61c0000 {
-                compatible = "renesas,irqc";
+                compatible = "renesas,irqc-r8a7791", "renesas,irqc";
                 #interrupt-cells = <2>;
                 interrupt-controller;
                 reg = <0 0xe61c0000 0 0x200>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 0 4>,
-                              <0 1 4>,
-                              <0 2 4>,
-                              <0 3 4>,
-                              <0 12 4>,
-                              <0 13 4>,
-                              <0 14 4>,
-                              <0 15 4>,
-                              <0 16 4>,
-                              <0 17 4>;
+                interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 1 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 2 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 3 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 12 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 13 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 14 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 15 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 16 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 17 IRQ_TYPE_LEVEL_HIGH>;
+        };
+
+        pfc: pfc@e6060000 {
+                compatible = "renesas,pfc-r8a7791";
+                reg = <0 0xe6060000 0 0x250>;
+                #gpio-range-cells = <3>;
+        };
+
+        clocks {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+
+                /* External root clock */
+                extal_clk: extal_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        /* This value must be overriden by the board. */
+                        clock-frequency = <0>;
+                        clock-output-names = "extal";
+                };
+
+                /* Special CPG clocks */
+                cpg_clocks: cpg_clocks@e6150000 {
+                        compatible = "renesas,r8a7791-cpg-clocks",
+                                     "renesas,rcar-gen2-cpg-clocks";
+                        reg = <0 0xe6150000 0 0x1000>;
+                        clocks = <&extal_clk>;
+                        #clock-cells = <1>;
+                        clock-output-names = "main", "pll0", "pll1", "pll3",
+                                             "lb", "qspi", "sdh", "sd0", "z";
+                };
+
+                /* Variable factor clocks */
+                sd1_clk: sd2_clk@e6150078 {
+                        compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe6150078 0 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "sd1";
+                };
+                sd2_clk: sd3_clk@e615007c {
+                        compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe615007c 0 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "sd2";
+                };
+                mmc0_clk: mmc0_clk@e6150240 {
+                        compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe6150240 0 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "mmc0";
+                };
+                ssp_clk: ssp_clk@e6150248 {
+                        compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe6150248 0 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "ssp";
+                };
+                ssprs_clk: ssprs_clk@e615024c {
+                        compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe615024c 0 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "ssprs";
+                };
+
+                /* Fixed factor clocks */
+                pll1_div2_clk: pll1_div2_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clock-output-names = "pll1_div2";
+                };
+                zg_clk: zg_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <3>;
+                        clock-mult = <1>;
+                        clock-output-names = "zg";
+                };
+                zx_clk: zx_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <3>;
+                        clock-mult = <1>;
+                        clock-output-names = "zx";
+                };
+                zs_clk: zs_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <6>;
+                        clock-mult = <1>;
+                        clock-output-names = "zs";
+                };
+                hp_clk: hp_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <12>;
+                        clock-mult = <1>;
+                        clock-output-names = "hp";
+                };
+                i_clk: i_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clock-output-names = "i";
+                };
+                b_clk: b_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <12>;
+                        clock-mult = <1>;
+                        clock-output-names = "b";
+                };
+                p_clk: p_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <24>;
+                        clock-mult = <1>;
+                        clock-output-names = "p";
+                };
+                cl_clk: cl_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <48>;
+                        clock-mult = <1>;
+                        clock-output-names = "cl";
+                };
+                m2_clk: m2_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <8>;
+                        clock-mult = <1>;
+                        clock-output-names = "m2";
+                };
+                imp_clk: imp_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <4>;
+                        clock-mult = <1>;
+                        clock-output-names = "imp";
+                };
+                rclk_clk: rclk_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <(48 * 1024)>;
+                        clock-mult = <1>;
+                        clock-output-names = "rclk";
+                };
+                oscclk_clk: oscclk_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <(12 * 1024)>;
+                        clock-mult = <1>;
+                        clock-output-names = "oscclk";
+                };
+                zb3_clk: zb3_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
+                        #clock-cells = <0>;
+                        clock-div = <4>;
+                        clock-mult = <1>;
+                        clock-output-names = "zb3";
+                };
+                zb3d2_clk: zb3d2_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
+                        #clock-cells = <0>;
+                        clock-div = <8>;
+                        clock-mult = <1>;
+                        clock-output-names = "zb3d2";
+                };
+                ddr_clk: ddr_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
+                        #clock-cells = <0>;
+                        clock-div = <8>;
+                        clock-mult = <1>;
+                        clock-output-names = "ddr";
+                };
+                mp_clk: mp_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-div = <15>;
+                        clock-mult = <1>;
+                        clock-output-names = "mp";
+                };
+                cp_clk: cp_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&extal_clk>;
+                        #clock-cells = <0>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clock-output-names = "cp";
+                };
+
+                /* Gate clocks */
+                mstp0_clks: mstp0_clks@e6150130 {
+                        compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
+                        clocks = <&mp_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <R8A7791_CLK_MSIOF0>;
+                        clock-output-names = "msiof0";
+                };
+                mstp1_clks: mstp1_clks@e6150134 {
+                        compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
+                        clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
+                                 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2
+                                R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1
+                                R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_SY
+                        >;
+                        clock-output-names =
+                                "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
+                                "vsp1-du0", "vsp1-sy";
+                };
+                mstp2_clks: mstp2_clks@e6150138 {
+                        compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
+                        clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
+                                 <&mp_clk>, <&mp_clk>, <&mp_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
+                                R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
+                                R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
+                        >;
+                        clock-output-names =
+                                "scifa2", "scifa1", "scifa0", "misof2", "scifb0",
+                                "scifb1", "msiof1", "scifb2";
+                };
+                mstp3_clks: mstp3_clks@e615013c {
+                        compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
+                        clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>,
+                                <&cpg_clocks R8A7791_CLK_SD0>, <&mmc0_clk>, <&rclk_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1
+                                R8A7791_CLK_SDHI0 R8A7791_CLK_MMCIF0 R8A7791_CLK_CMT1
+                        >;
+                        clock-output-names =
+                                "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0", "cmt1";
+                };
+                mstp5_clks: mstp5_clks@e6150144 {
+                        compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
+                        clocks = <&extal_clk>, <&p_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <R8A7791_CLK_THERMAL R8A7791_CLK_PWM>;
+                        clock-output-names = "thermal", "pwm";
+                };
+                mstp7_clks: mstp7_clks@e615014c {
+                        compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
+                        clocks = <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
+                                 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
+                                 <&zx_clk>, <&zx_clk>, <&zx_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
+                                R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
+                                R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
+                                R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
+                                R8A7791_CLK_LVDS0
+                        >;
+                        clock-output-names =
+                                "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
+                                "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
+                };
+                mstp8_clks: mstp8_clks@e6150990 {
+                        compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
+                        clocks = <&p_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <R8A7791_CLK_ETHER>;
+                        clock-output-names = "ether";
+                };
+                mstp9_clks: mstp9_clks@e6150994 {
+                        compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
+                        clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>,
+                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
+                                 <&p_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD
+                                R8A7791_CLK_I2C4 R8A7791_CLK_I2C4 R8A7791_CLK_I2C3
+                                R8A7791_CLK_I2C2 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
+                        >;
+                        clock-output-names =
+                                "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c4", "i2c3",
+                                "i2c2", "i2c1", "i2c0";
+                };
+                mstp11_clks: mstp11_clks@e615099c {
+                        compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
+                        clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
+                        >;
+                        clock-output-names = "scifa3", "scifa4", "scifa5";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index de9feced9935..1105558d188b 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -1,6 +1,6 @@
 /*
  * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
- *                applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35 SoC
+ *                applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36 SoC
  *
  *  Copyright (C) 2013 Atmel,
  *                2013 Ludovic Desroches <ludovic.desroches@atmel.com>
@@ -37,6 +37,7 @@
                 i2c2 = &i2c2;
                 ssc0 = &ssc0;
                 ssc1 = &ssc1;
+                pwm0 = &pwm0;
         };
         cpus {
                 #address-cells = <1>;
@@ -179,6 +180,15 @@
                                 status = "disabled";
                         };
 
+                        pwm0: pwm@f002c000 {
+                                compatible = "atmel,sama5d3-pwm";
+                                reg = <0xf002c000 0x300>;
+                                interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>;
+                                #pwm-cells = <3>;
+                                clocks = <&pwm_clk>;
+                                status = "disabled";
+                        };
+
                         isi: isi@f0034000 {
                                 compatible = "atmel,at91sam9g45-isi";
                                 reg = <0xf0034000 0x4000>;
@@ -304,6 +314,8 @@
                                 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>,
                                        <&dma1 2 AT91_DMA_CFG_PER_ID(12)>;
                                 dma-names = "tx", "rx";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c2>;
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 clocks = <&twi2_clk>;
@@ -333,21 +345,35 @@
                         };
 
                         sha@f8034000 {
-                                compatible = "atmel,sam9g46-sha";
+                                compatible = "atmel,at91sam9g46-sha";
                                 reg = <0xf8034000 0x100>;
                                 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
+                                dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>;
+                                dma-names = "tx";
+                                clocks = <&sha_clk>;
+                                clock-names = "sha_clk";
                         };
 
                         aes@f8038000 {
-                                compatible = "atmel,sam9g46-aes";
+                                compatible = "atmel,at91sam9g46-aes";
                                 reg = <0xf8038000 0x100>;
-                                interrupts = <43 4 0>;
+                                interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>;
+                                dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>,
+                                       <&dma1 2 AT91_DMA_CFG_PER_ID(19)>;
+                                dma-names = "tx", "rx";
+                                clocks = <&aes_clk>;
+                                clock-names = "aes_clk";
                         };
 
                         tdes@f803c000 {
-                                compatible = "atmel,sam9g46-tdes";
+                                compatible = "atmel,at91sam9g46-tdes";
                                 reg = <0xf803c000 0x100>;
                                 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>;
+                                dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>,
+                                       <&dma1 2 AT91_DMA_CFG_PER_ID(21)>;
+                                dma-names = "tx", "rx";
+                                clocks = <&tdes_clk>;
+                                clock-names = "tdes_clk";
                         };
 
                         dma0: dma-controller@ffffe600 {
@@ -486,6 +512,14 @@
                                         };
                                 };
 
+                                i2c2 {
+                                        pinctrl_i2c2: i2c2-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE   /* TWD2 pin, conflicts with LCDDAT18, ISI_D2 */
+                                                         AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */
+                                        };
+                                };
+
                                 isi {
                                         pinctrl_isi: isi-0 {
                                                 atmel,pins =
diff --git a/arch/arm/boot/dts/sama5d36.dtsi b/arch/arm/boot/dts/sama5d36.dtsi
new file mode 100644
index 000000000000..6c31c26e6cc0
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d36.dtsi
@@ -0,0 +1,20 @@
+/*
+ * sama5d36.dtsi - Device Tree Include file for SAMA5D36 SoC
+ *
+ *  Copyright (C) 2013 Atmel,
+ *                2013 Josh Wu <josh.wu@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+#include "sama5d3.dtsi"
+#include "sama5d3_can.dtsi"
+#include "sama5d3_emac.dtsi"
+#include "sama5d3_gmac.dtsi"
+#include "sama5d3_lcd.dtsi"
+#include "sama5d3_mci2.dtsi"
+#include "sama5d3_tcb1.dtsi"
+#include "sama5d3_uart.dtsi"
+
+/ {
+        compatible = "atmel,samad36", "atmel,sama5d3", "atmel,sama5";
+};
diff --git a/arch/arm/boot/dts/sama5d36ek.dts b/arch/arm/boot/dts/sama5d36ek.dts
new file mode 100644
index 000000000000..59576c6f9826
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d36ek.dts
@@ -0,0 +1,53 @@
+/*
+ * sama5d36ek.dts - Device Tree file for SAMA5D36-EK board
+ *
+ *  Copyright (C) 2013 Atmel,
+ *                2013 Josh Wu <josh.wu@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+#include "sama5d36.dtsi"
+#include "sama5d3xmb.dtsi"
+#include "sama5d3xdm.dtsi"
+
+/ {
+        model = "Atmel SAMA5D36-EK";
+        compatible = "atmel,sama5d36ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5";
+
+        ahb {
+                apb {
+                        spi0: spi@f0004000 {
+                                status = "okay";
+                        };
+
+                        ssc0: ssc@f0008000 {
+                                status = "okay";
+                        };
+
+                        can0: can@f000c000 {
+                                status = "okay";
+                        };
+
+                        i2c0: i2c@f0014000 {
+                                status = "okay";
+                        };
+
+                        i2c1: i2c@f0018000 {
+                                status = "okay";
+                        };
+
+                        macb0: ethernet@f0028000 {
+                                status = "okay";
+                        };
+
+                        macb1: ethernet@f802c000 {
+                                status = "okay";
+                        };
+                };
+        };
+
+        sound {
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/sama5d3_uart.dtsi b/arch/arm/boot/dts/sama5d3_uart.dtsi
index 49d4d76ca6f4..a9fa75e41652 100644
--- a/arch/arm/boot/dts/sama5d3_uart.dtsi
+++ b/arch/arm/boot/dts/sama5d3_uart.dtsi
@@ -12,6 +12,11 @@
 #include <dt-bindings/clk/at91.h>
 
 / {
+        aliases {
+                serial5 = &uart0;
+                serial6 = &uart1;
+        };
+
         ahb {
                 apb {
                         pinctrl@fffff200 {
diff --git a/arch/arm/boot/dts/sama5d3xdm.dtsi b/arch/arm/boot/dts/sama5d3xdm.dtsi
index 1c296d6b2f2a..f9bdde542ced 100644
--- a/arch/arm/boot/dts/sama5d3xdm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xdm.dtsi
@@ -18,6 +18,7 @@
                                         interrupts = <31 0x0>;
                                         pinctrl-names = "default";
                                         pinctrl-0 = <&pinctrl_qt1070_irq>;
+                                        wakeup-source;
                                 };
                         };
 
diff --git a/arch/arm/boot/dts/sh7372-mackerel.dts b/arch/arm/boot/dts/sh7372-mackerel.dts
index 8acf51e0cdae..a759a276c9a9 100644
--- a/arch/arm/boot/dts/sh7372-mackerel.dts
+++ b/arch/arm/boot/dts/sh7372-mackerel.dts
@@ -9,7 +9,7 @@
  */
 
 /dts-v1/;
-/include/ "sh7372.dtsi"
+#include "sh7372.dtsi"
 
 / {
         model = "Mackerel (AP4 EVM 2nd)";
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
index 8ee06dd81799..eb8886b535e4 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
@@ -12,8 +12,9 @@
  */
 
 /dts-v1/;
-/include/ "sh73a0.dtsi"
+#include "sh73a0.dtsi"
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
         model = "KZM-A9-GT";
@@ -82,7 +83,7 @@
                 reg = <0x10000000 0x100>;
                 phy-mode = "mii";
                 interrupt-parent = <&irqpin0>;
-                interrupts = <3 0>;     /* active low */
+                interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
                 reg-io-width = <4>;
                 smsc,irq-push-pull;
                 smsc,save-mac-address;
@@ -105,6 +106,66 @@
                         gpios = <&pfc 23 GPIO_ACTIVE_LOW>;
                 };
         };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+
+                back-key {
+                        gpios = <&pcf8575 8 GPIO_ACTIVE_LOW>;
+                        linux,code = <158>;
+                        label = "SW3";
+                };
+
+                right-key {
+                        gpios = <&pcf8575 9 GPIO_ACTIVE_LOW>;
+                        linux,code = <106>;
+                        label = "SW2-R";
+                };
+
+                left-key {
+                        gpios = <&pcf8575 10 GPIO_ACTIVE_LOW>;
+                        linux,code = <105>;
+                        label = "SW2-L";
+                };
+
+                enter-key {
+                        gpios = <&pcf8575 11 GPIO_ACTIVE_LOW>;
+                        linux,code = <28>;
+                        label = "SW2-P";
+                };
+
+                up-key {
+                        gpios = <&pcf8575 12 GPIO_ACTIVE_LOW>;
+                        linux,code = <103>;
+                        label = "SW2-U";
+                };
+
+                down-key {
+                        gpios = <&pcf8575 13 GPIO_ACTIVE_LOW>;
+                        linux,code = <108>;
+                        label = "SW2-D";
+                };
+
+                home-key {
+                        gpios = <&pcf8575 14 GPIO_ACTIVE_LOW>;
+                        linux,code = <102>;
+                        label = "SW1";
+                };
+        };
+
+        sound {
+                compatible = "simple-audio-card";
+                simple-audio-card,format = "left_j";
+                simple-audio-card,cpu {
+                        sound-dai = <&sh_fsi2 0>;
+                };
+                simple-audio-card,codec {
+                        sound-dai = <&ak4648>;
+                        bitclock-master;
+                        frame-master;
+                        system-clock-frequency = <11289600>;
+                };
+        };
 };
 
 &i2c0 {
@@ -179,12 +240,29 @@
                         };
                 };
         };
+
+        ak4648: ak4648@0x12 {
+                #sound-dai-cells = <0>;
+                compatible = "asahi-kasei,ak4648";
+                reg = <0x12>;
+        };
 };
 
 &i2c3 {
         pinctrl-0 = <&i2c3_pins>;
         pinctrl-names = "default";
         status = "okay";
+
+        pcf8575: gpio@20 {
+                compatible = "nxp,pcf8575";
+                reg = <0x20>;
+                interrupt-parent = <&irqpin2>;
+                interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
 };
 
 &mmcif {
@@ -205,7 +283,7 @@
                 renesas,function = "i2c3";
         };
 
-        mmcif_pins: mmcif {
+        mmcif_pins: mmc {
                 mux {
                         renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0";
                         renesas,function = "mmc0";
@@ -217,20 +295,26 @@
                 };
         };
 
-        scifa4_pins: scifa4 {
+        scifa4_pins: serial4 {
                 renesas,groups = "scifa4_data", "scifa4_ctrl";
                 renesas,function = "scifa4";
         };
 
-        sdhi0_pins: sdhi0 {
+        sdhi0_pins: sd0 {
                 renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp";
                 renesas,function = "sdhi0";
         };
 
-        sdhi2_pins: sdhi2 {
+        sdhi2_pins: sd2 {
                 renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
                 renesas,function = "sdhi2";
         };
+
+        fsia_pins: sounda {
+                renesas,groups = "fsia_mclk_in", "fsia_sclk_in",
+                                 "fsia_data_in", "fsia_data_out";
+                renesas,function = "fsia";
+        };
 };
 
 &sdhi0 {
@@ -251,3 +335,10 @@
         broken-cd;
         status = "okay";
 };
+
+&sh_fsi2 {
+        pinctrl-0 = <&fsia_pins>;
+        pinctrl-names = "default";
+
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g.dts b/arch/arm/boot/dts/sh73a0-kzm9g.dts
index 0f1ca7792c46..27c5f426d172 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g.dts
@@ -9,7 +9,7 @@
  */
 
 /dts-v1/;
-/include/ "sh73a0.dtsi"
+#include "sh73a0.dtsi"
 
 / {
         model = "KZM-A9-GT";
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index fcf26889a8a0..b7bd3b9a6753 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -10,6 +10,8 @@
 
 /include/ "skeleton.dtsi"
 
+#include <dt-bindings/interrupt-controller/irq.h>
+
 / {
         compatible = "renesas,sh73a0";
 
@@ -40,12 +42,12 @@
 
         pmu {
                 compatible = "arm,cortex-a9-pmu";
-                interrupts = <0 55 4>,
-                             <0 56 4>;
+                interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 56 IRQ_TYPE_LEVEL_HIGH>;
         };
 
         irqpin0: irqpin@e6900000 {
-                compatible = "renesas,intc-irqpin";
+                compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
                 #interrupt-cells = <2>;
                 interrupt-controller;
                 reg = <0xe6900000 4>,
@@ -54,18 +56,18 @@
                         <0xe6900040 1>,
                         <0xe6900060 1>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 1 0x4
-                              0 2 0x4
-                              0 3 0x4
-                              0 4 0x4
-                              0 5 0x4
-                              0 6 0x4
-                              0 7 0x4
-                              0 8 0x4>;
+                interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH
+                              0 2 IRQ_TYPE_LEVEL_HIGH
+                              0 3 IRQ_TYPE_LEVEL_HIGH
+                              0 4 IRQ_TYPE_LEVEL_HIGH
+                              0 5 IRQ_TYPE_LEVEL_HIGH
+                              0 6 IRQ_TYPE_LEVEL_HIGH
+                              0 7 IRQ_TYPE_LEVEL_HIGH
+                              0 8 IRQ_TYPE_LEVEL_HIGH>;
         };
 
         irqpin1: irqpin@e6900004 {
-                compatible = "renesas,intc-irqpin";
+                compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
                 #interrupt-cells = <2>;
                 interrupt-controller;
                 reg = <0xe6900004 4>,
@@ -74,19 +76,19 @@
                         <0xe6900044 1>,
                         <0xe6900064 1>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 9 0x4
-                              0 10 0x4
-                              0 11 0x4
-                              0 12 0x4
-                              0 13 0x4
-                              0 14 0x4
-                              0 15 0x4
-                              0 16 0x4>;
+                interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH
+                              0 10 IRQ_TYPE_LEVEL_HIGH
+                              0 11 IRQ_TYPE_LEVEL_HIGH
+                              0 12 IRQ_TYPE_LEVEL_HIGH
+                              0 13 IRQ_TYPE_LEVEL_HIGH
+                              0 14 IRQ_TYPE_LEVEL_HIGH
+                              0 15 IRQ_TYPE_LEVEL_HIGH
+                              0 16 IRQ_TYPE_LEVEL_HIGH>;
                 control-parent;
         };
 
         irqpin2: irqpin@e6900008 {
-                compatible = "renesas,intc-irqpin";
+                compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
                 #interrupt-cells = <2>;
                 interrupt-controller;
                 reg = <0xe6900008 4>,
@@ -95,18 +97,18 @@
                         <0xe6900048 1>,
                         <0xe6900068 1>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 17 0x4
-                              0 18 0x4
-                              0 19 0x4
-                              0 20 0x4
-                              0 21 0x4
-                              0 22 0x4
-                              0 23 0x4
-                              0 24 0x4>;
+                interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH
+                              0 18 IRQ_TYPE_LEVEL_HIGH
+                              0 19 IRQ_TYPE_LEVEL_HIGH
+                              0 20 IRQ_TYPE_LEVEL_HIGH
+                              0 21 IRQ_TYPE_LEVEL_HIGH
+                              0 22 IRQ_TYPE_LEVEL_HIGH
+                              0 23 IRQ_TYPE_LEVEL_HIGH
+                              0 24 IRQ_TYPE_LEVEL_HIGH>;
         };
 
         irqpin3: irqpin@e690000c {
-                compatible = "renesas,intc-irqpin";
+                compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
                 #interrupt-cells = <2>;
                 interrupt-controller;
                 reg = <0xe690000c 4>,
@@ -115,14 +117,14 @@
                         <0xe690004c 1>,
                         <0xe690006c 1>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 25 0x4
-                              0 26 0x4
-                              0 27 0x4
-                              0 28 0x4
-                              0 29 0x4
-                              0 30 0x4
-                              0 31 0x4
-                              0 32 0x4>;
+                interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH
+                              0 26 IRQ_TYPE_LEVEL_HIGH
+                              0 27 IRQ_TYPE_LEVEL_HIGH
+                              0 28 IRQ_TYPE_LEVEL_HIGH
+                              0 29 IRQ_TYPE_LEVEL_HIGH
+                              0 30 IRQ_TYPE_LEVEL_HIGH
+                              0 31 IRQ_TYPE_LEVEL_HIGH
+                              0 32 IRQ_TYPE_LEVEL_HIGH>;
         };
 
         i2c0: i2c@e6820000 {
@@ -131,10 +133,10 @@
                 compatible = "renesas,rmobile-iic";
                 reg = <0xe6820000 0x425>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 167 0x4
-                              0 168 0x4
-                              0 169 0x4
-                              0 170 0x4>;
+                interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH
+                              0 168 IRQ_TYPE_LEVEL_HIGH
+                              0 169 IRQ_TYPE_LEVEL_HIGH
+                              0 170 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
@@ -144,10 +146,10 @@
                 compatible = "renesas,rmobile-iic";
                 reg = <0xe6822000 0x425>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 51 0x4
-                              0 52 0x4
-                              0 53 0x4
-                              0 54 0x4>;
+                interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH
+                              0 52 IRQ_TYPE_LEVEL_HIGH
+                              0 53 IRQ_TYPE_LEVEL_HIGH
+                              0 54 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
@@ -157,10 +159,10 @@
                 compatible = "renesas,rmobile-iic";
                 reg = <0xe6824000 0x425>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 171 0x4
-                              0 172 0x4
-                              0 173 0x4
-                              0 174 0x4>;
+                interrupts = <0 171 IRQ_TYPE_LEVEL_HIGH
+                              0 172 IRQ_TYPE_LEVEL_HIGH
+                              0 173 IRQ_TYPE_LEVEL_HIGH
+                              0 174 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
@@ -170,10 +172,10 @@
                 compatible = "renesas,rmobile-iic";
                 reg = <0xe6826000 0x425>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 183 0x4
-                              0 184 0x4
-                              0 185 0x4
-                              0 186 0x4>;
+                interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH
+                              0 184 IRQ_TYPE_LEVEL_HIGH
+                              0 185 IRQ_TYPE_LEVEL_HIGH
+                              0 186 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
@@ -183,52 +185,52 @@
                 compatible = "renesas,rmobile-iic";
                 reg = <0xe6828000 0x425>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 187 0x4
-                              0 188 0x4
-                              0 189 0x4
-                              0 190 0x4>;
+                interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH
+                              0 188 IRQ_TYPE_LEVEL_HIGH
+                              0 189 IRQ_TYPE_LEVEL_HIGH
+                              0 190 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
-        mmcif: mmcif@e6bd0000 {
+        mmcif: mmc@e6bd0000 {
                 compatible = "renesas,sh-mmcif";
                 reg = <0xe6bd0000 0x100>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 140 0x4
-                              0 141 0x4>;
+                interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH
+                              0 141 IRQ_TYPE_LEVEL_HIGH>;
                 reg-io-width = <4>;
                 status = "disabled";
         };
 
-        sdhi0: sdhi@ee100000 {
-                compatible = "renesas,sdhi-r8a7740";
+        sdhi0: sd@ee100000 {
+                compatible = "renesas,sdhi-sh73a0";
                 reg = <0xee100000 0x100>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 83 4
-                                0 84 4
-                                0 85 4>;
+                interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH
+                              0 84 IRQ_TYPE_LEVEL_HIGH
+                              0 85 IRQ_TYPE_LEVEL_HIGH>;
                 cap-sd-highspeed;
                 status = "disabled";
         };
 
         /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
-        sdhi1: sdhi@ee120000 {
-                compatible = "renesas,sdhi-r8a7740";
+        sdhi1: sd@ee120000 {
+                compatible = "renesas,sdhi-sh73a0";
                 reg = <0xee120000 0x100>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 88 4
-                                0 89 4>;
+                interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH
+                              0 89 IRQ_TYPE_LEVEL_HIGH>;
                 toshiba,mmc-wrprotect-disable;
                 cap-sd-highspeed;
                 status = "disabled";
         };
 
-        sdhi2: sdhi@ee140000 {
-                compatible = "renesas,sdhi-r8a7740";
+        sdhi2: sd@ee140000 {
+                compatible = "renesas,sdhi-sh73a0";
                 reg = <0xee140000 0x100>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 104 4
-                                0 105 4>;
+                interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH
+                              0 105 IRQ_TYPE_LEVEL_HIGH>;
                 toshiba,mmc-wrprotect-disable;
                 cap-sd-highspeed;
                 status = "disabled";
@@ -240,5 +242,23 @@
                       <0xe605801c 0x1c>;
                 gpio-controller;
                 #gpio-cells = <2>;
+                interrupts-extended =
+                        <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
+                        <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
+                        <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
+                        <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
+                        <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
+                        <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
+                        <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
+                        <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
+        };
+
+        sh_fsi2: sound@ec230000 {
+                #sound-dai-cells = <1>;
+                compatible = "renesas,sh_fsi2";
+                reg = <0xec230000 0x400>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 146 0x4>;
+                status = "disabled";
         };
 };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index f936476c2753..537f1a5c07f5 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -79,6 +79,8 @@
                                 #dma-cells = <1>;
                                 #dma-channels = <8>;
                                 #dma-requests = <32>;
+                                clocks = <&l4_main_clk>;
+                                clock-names = "apb_pclk";
                         };
                 };
 
@@ -467,6 +469,8 @@
                         interrupts = <0 38 0x04>;
                         cache-unified;
                         cache-level = <2>;
+                        arm,tag-latency = <1 1 1>;
+                        arm,data-latency = <2 1 1>;
                 };
 
                 /* Local timer */
diff --git a/arch/arm/boot/dts/st-pincfg.h b/arch/arm/boot/dts/st-pincfg.h
index 8c45d85ac13e..4851c387d52d 100644
--- a/arch/arm/boot/dts/st-pincfg.h
+++ b/arch/arm/boot/dts/st-pincfg.h
@@ -15,7 +15,7 @@
 /* Pull Up */
 #define PU                      (1 << 26)
 /* Open Drain */
-#define OD                      (1 << 26)
+#define OD                      (1 << 25)
 #define RT                      (1 << 23)
 #define INVERTCLK               (1 << 22)
 #define CLKNOTDATA              (1 << 21)
diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi
index 7da99fe497e1..e0853ea02df2 100644
--- a/arch/arm/boot/dts/ste-dbx5x0.dtsi
+++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi
@@ -913,6 +913,10 @@
                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
                         v-ape-supply = <&db8500_vape_reg>;
 
+                        dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */
+                               <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */
+                        dma-names = "rx", "tx";
+
                         clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>;
                         clock-names = "msp", "apb_pclk";
 
@@ -925,6 +929,9 @@
                         interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
                         v-ape-supply = <&db8500_vape_reg>;
 
+                        dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */
+                        dma-names = "tx";
+
                         clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>;
                         clock-names = "msp", "apb_pclk";
 
@@ -938,6 +945,11 @@
                         interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
                         v-ape-supply = <&db8500_vape_reg>;
 
+                        dmas = <&dma 14 0 0x12>, /* Logical  - DevToMem - HighPrio */
+                               <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev
+                                                    HighPrio - Fixed */
+                        dma-names = "rx", "tx";
+
                         clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>;
                         clock-names = "msp", "apb_pclk";
 
@@ -950,6 +962,9 @@
                         interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
                         v-ape-supply = <&db8500_vape_reg>;
 
+                        dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */
+                        dma-names = "rx";
+
                         clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>;
                         clock-names = "msp", "apb_pclk";
 
@@ -987,6 +1002,23 @@
                         status = "disabled";
                 };
 
+                mcde@a0350000 {
+                        compatible = "stericsson,mcde";
+                        reg = <0xa0350000 0x1000>, /* MCDE */
+                              <0xa0351000 0x1000>, /* DSI link 1 */
+                              <0xa0352000 0x1000>, /* DSI link 2 */
+                              <0xa0353000 0x1000>; /* DSI link 3 */
+                        interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */
+                                 <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */
+                                 <&prcmu_clk PRCMU_PLLDSI>, /* HDMI clock */
+                                 <&prcmu_clk PRCMU_DSI0CLK>, /* DSI 0 */
+                                 <&prcmu_clk PRCMU_DSI1CLK>, /* DSI 1 */
+                                 <&prcmu_clk PRCMU_DSI0ESCCLK>, /* TVout clock 0 */
+                                 <&prcmu_clk PRCMU_DSI1ESCCLK>, /* TVout clock 1 */
+                                 <&prcmu_clk PRCMU_DSI2ESCCLK>; /* TVout clock 2 */
+                };
+
                 cryp@a03cb000 {
                         compatible = "stericsson,ux500-cryp";
                         reg = <0xa03cb000 0x1000>;
diff --git a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi
new file mode 100644
index 000000000000..addfcc7c2750
--- /dev/null
+++ b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi
@@ -0,0 +1,745 @@
+/*
+ * Copyright 2013 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "ste-nomadik-pinctrl.dtsi"
+
+/ {
+        soc {
+                pinctrl {
+                        /* Settings for all UART default and sleep states */
+                        uart0 {
+                                uart0_default_mode: uart0_default {
+                                        default_mux {
+                                                ste,function = "u0";
+                                                ste,pins = "u0_a_1";
+                                        };
+                                        default_cfg1 {
+                                                ste,pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
+                                                ste,config = <&in_pu>;
+                                        };
+
+                                        default_cfg2 {
+                                                ste,pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */
+                                                ste,config = <&out_hi>;
+                                        };
+                                };
+
+                                uart0_sleep_mode: uart0_sleep {
+                                        sleep_cfg1 {
+                                                ste,pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
+                                                ste,config = <&slpm_in_wkup_pdis>;
+                                        };
+
+                                        sleep_cfg2 {
+                                                ste,pins = "GPIO1_AJ3"; /* RTS */
+                                                ste,config = <&slpm_out_hi_wkup_pdis>;
+                                        };
+
+                                        sleep_cfg3 {
+                                                ste,pins = "GPIO3_AH3"; /* TXD */
+                                                ste,config = <&slpm_out_wkup_pdis>;
+                                        };
+                                };
+                        };
+
+                        uart1 {
+                                uart1_default_mode: uart1_default {
+                                        default_mux {
+                                                ste,function = "u1";
+                                                ste,pins = "u1rxtx_a_1";
+                                        };
+                                        default_cfg1 {
+                                                ste,pins = "GPIO4_AH6"; /* RXD */
+                                                ste,config = <&in_pu>;
+                                        };
+
+                                        default_cfg2 {
+                                                ste,pins = "GPIO5_AG6"; /* TXD */
+                                                ste,config = <&out_hi>;
+                                        };
+                                };
+
+                                uart1_sleep_mode: uart1_sleep {
+                                        sleep_cfg1 {
+                                                ste,pins = "GPIO4_AH6"; /* RXD */
+                                                ste,config = <&slpm_in_wkup_pdis>;
+                                        };
+
+                                        sleep_cfg2 {
+                                                ste,pins = "GPIO5_AG6"; /* TXD */
+                                                ste,config = <&slpm_out_wkup_pdis>;
+                                        };
+                                };
+                        };
+
+                        uart2 {
+                                uart2_default_mode: uart2_default {
+                                        default_mux {
+                                                ste,function = "u2";
+                                                ste,pins = "u2rxtx_c_1";
+                                        };
+                                        default_cfg1 {
+                                                ste,pins = "GPIO29_W2"; /* RXD */
+                                                ste,config = <&in_pu>;
+                                        };
+
+                                        default_cfg2 {
+                                                ste,pins = "GPIO30_W3"; /* TXD */
+                                                ste,config = <&out_hi>;
+                                        };
+                                };
+
+                                uart2_sleep_mode: uart2_sleep {
+                                        sleep_cfg1 {
+                                                ste,pins = "GPIO29_W2"; /* RXD */
+                                                ste,config = <&in_wkup_pdis>;
+                                        };
+
+                                        sleep_cfg2 {
+                                                ste,pins = "GPIO30_W3"; /* TXD */
+                                                ste,config = <&out_wkup_pdis>;
+                                        };
+                                };
+                        };
+
+                        /* Settings for all I2C default and sleep states */
+                        i2c0 {
+                                i2c0_default_mode: i2c_default {
+                                        default_mux {
+                                                ste,function = "i2c0";
+                                                ste,pins = "i2c0_a_1";
+                                        };
+                                        default_cfg1 {
+                                                ste,pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
+                                                ste,config = <&in_pu>;
+                                        };
+                                };
+
+                                i2c0_sleep_mode: i2c_sleep {
+                                        sleep_cfg1 {
+                                                ste,pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
+                                                ste,config = <&slpm_in_wkup_pdis>;
+                                        };
+                                };
+                        };
+
+                        i2c1 {
+                                i2c1_default_mode: i2c_default {
+                                        default_mux {
+                                                ste,function = "i2c1";
+                                                ste,pins = "i2c1_b_2";
+                                        };
+                                        default_cfg1 {
+                                                ste,pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
+                                                ste,config = <&in_pu>;
+                                        };
+                                };
+
+                                i2c1_sleep_mode: i2c_sleep {
+                                        sleep_cfg1 {
+                                                ste,pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
+                                                ste,config = <&slpm_in_wkup_pdis>;
+                                        };
+                                };
+                        };
+
+                        i2c2 {
+                                i2c2_default_mode: i2c_default {
+                                        default_mux {
+                                                ste,function = "i2c2";
+                                                ste,pins = "i2c2_b_2";
+                                        };
+                                        default_cfg1 {
+                                                ste,pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
+                                                ste,config = <&in_pu>;
+                                        };
+                                };
+
+                                i2c2_sleep_mode: i2c_sleep {
+                                        sleep_cfg1 {
+                                                ste,pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
+                                                ste,config = <&slpm_in_wkup_pdis>;
+                                        };
+                                };
+                        };
+
+                        i2c3 {
+                                i2c3_default_mode: i2c_default {
+                                        default_mux {
+                                                ste,function = "i2c3";
+                                                ste,pins = "i2c3_c_2";
+                                        };
+                                        default_cfg1 {
+                                                ste,pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
+                                                ste,config = <&in_pu>;
+                                        };
+                                };
+
+                                i2c3_sleep_mode: i2c_sleep {
+                                        sleep_cfg1 {
+                                                ste,pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
+                                                ste,config = <&slpm_in_wkup_pdis>;
+                                        };
+                                };
+                        };
+
+                        /*
+                         * Activating I2C4 will conflict with UART1 about the same pins so do not
+                         * enable I2C4 and UART1 at the same time.
+                         */
+                        i2c4 {
+                                i2c4_default_mode: i2c_default {
+                                        default_mux {
+                                                ste,function = "i2c4";
+                                                ste,pins = "i2c4_b_1";
+                                        };
+                                        default_cfg1 {
+                                                ste,pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
+                                                ste,config = <&in_pu>;
+                                        };
+                                };
+
+                                i2c4_sleep_mode: i2c_sleep {
+                                        sleep_cfg1 {
+                                                ste,pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
+                                                ste,config = <&slpm_in_wkup_pdis>;
+                                        };
+                                };
+                        };
+
+                        /* Settings for all SPI default and sleep states */
+                        spi2 {
+                                spi2_default_mode: spi_default {
+                                        default_mux {
+                                                ste,function = "spi2";
+                                                ste,pins = "spi2_oc1_2";
+                                        };
+                                        default_cfg1 {
+                                                ste,pins = "GPIO216_AG12"; /* FRM */
+                                                ste,config = <&gpio_out_hi>;
+                                        };
+                                        default_cfg2 {
+                                                ste,pins = "GPIO218_AH11"; /* RXD */
+                                                ste,config = <&in_pd>;
+                                        };
+                                        default_cfg3 {
+                                                ste,pins =
+                                                "GPIO215_AH13", /* TXD */
+                                                "GPIO217_AH12"; /* CLK */
+                                                ste,config = <&out_lo>;
+                                        };
+                                };
+
+                                spi2_idle_mode: spi_idle {
+                                        /*
+                                         * The idle mode is basically sleep mode sans wakeups. Also
+                                         * note that we have muxes the pins off the function here
+                                         * as we do not state any muxing.
+                                         */
+                                        idle_cfg1 {
+                                                ste,pins = "GPIO218_AH11"; /* RXD */
+                                                ste,config = <&slpm_in_pdis>;
+                                        };
+                                        idle_cfg2 {
+                                                ste,pins = "GPIO215_AH13"; /* TXD */
+                                                ste,config = <&slpm_out_lo_pdis>;
+                                        };
+                                        idle_cfg3 {
+                                                ste,pins = "GPIO217_AH12"; /* CLK */
+                                                ste,config = <&slpm_pdis>;
+                                        };
+                                };
+
+                                spi2_sleep_mode: spi_sleep {
+                                        sleep_cfg1 {
+                                                ste,pins =
+                                                "GPIO216_AG12", /* FRM */
+                                                "GPIO218_AH11"; /* RXD */
+                                                ste,config = <&slpm_in_wkup_pdis>;
+                                        };
+                                        sleep_cfg2 {
+                                                ste,pins = "GPIO215_AH13"; /* TXD */
+                                                ste,config = <&slpm_out_lo_wkup_pdis>;
+                                        };
+                                        sleep_cfg3 {
+                                                ste,pins = "GPIO217_AH12"; /* CLK */
+                                                ste,config = <&slpm_wkup_pdis>;
+                                        };
+                                };
+                        };
+
+                        /* Settings for all MMC/SD/SDIO default and sleep states */
+                        sdi0 {
+                                /* This is the external SD card slot, 4 bits wide */
+                                sdi0_default_mode: sdi0_default {
+                                        default_mux {
+                                                ste,function = "mc0";
+                                                ste,pins = "mc0_a_1";
+                                        };
+                                        default_cfg1 {
+                                                ste,pins =
+                                                "GPIO18_AC2", /* CMDDIR */
+                                                "GPIO19_AC1", /* DAT0DIR */
+                                                "GPIO20_AB4"; /* DAT2DIR */
+                                                ste,config = <&out_hi>;
+                                        };
+                                        default_cfg2 {
+                                                ste,pins = "GPIO22_AA3"; /* FBCLK */
+                                                ste,config = <&in_nopull>;
+                                        };
+                                        default_cfg3 {
+                                                ste,pins = "GPIO23_AA4"; /* CLK */
+                                                ste,config = <&out_lo>;
+                                        };
+                                        default_cfg4 {
+                                                ste,pins =
+                                                "GPIO24_AB2", /* CMD */
+                                                "GPIO25_Y4", /* DAT0 */
+                                                "GPIO26_Y2", /* DAT1 */
+                                                "GPIO27_AA2", /* DAT2 */
+                                                "GPIO28_AA1"; /* DAT3 */
+                                                ste,config = <&in_pu>;
+                                        };
+                                };
+
+                                sdi0_sleep_mode: sdi0_sleep {
+                                        sleep_cfg1 {
+                                                ste,pins =
+                                                "GPIO18_AC2", /* CMDDIR */
+                                                "GPIO19_AC1", /* DAT0DIR */
+                                                "GPIO20_AB4"; /* DAT2DIR */
+                                                ste,config = <&slpm_out_hi_wkup_pdis>;
+                                        };
+                                        sleep_cfg2 {
+                                                ste,pins =
+                                                "GPIO22_AA3", /* FBCLK */
+                                                "GPIO24_AB2", /* CMD */
+                                                "GPIO25_Y4", /* DAT0 */
+                                                "GPIO26_Y2", /* DAT1 */
+                                                "GPIO27_AA2", /* DAT2 */
+                                                "GPIO28_AA1"; /* DAT3 */
+                                                ste,config = <&slpm_in_wkup_pdis>;
+                                        };
+                                        sleep_cfg3 {
+                                                ste,pins = "GPIO23_AA4"; /* CLK */
+                                                ste,config = <&slpm_out_lo_wkup_pdis>;
+                                        };
+                                };
+                        };
+
+                        sdi1 {
+                                /* This is the WLAN SDIO 4 bits wide */
+                                sdi1_default_mode: sdi1_default {
+                                        default_mux {
+                                                ste,function = "mc1";
+                                                ste,pins = "mc1_a_1";
+                                        };
+                                        default_cfg1 {
+                                                ste,pins = "GPIO208_AH16"; /* CLK */
+                                                ste,config = <&out_lo>;
+                                        };
+                                        default_cfg2 {
+                                                ste,pins = "GPIO209_AG15"; /* FBCLK */
+                                                ste,config = <&in_nopull>;
+                                        };
+                                        default_cfg3 {
+                                                ste,pins =
+                                                "GPIO210_AJ15", /* CMD */
+                                                "GPIO211_AG14", /* DAT0 */
+                                                "GPIO212_AF13", /* DAT1 */
+                                                "GPIO213_AG13", /* DAT2 */
+                                                "GPIO214_AH15"; /* DAT3 */
+                                                ste,config = <&in_pu>;
+                                        };
+                                };
+
+                                sdi1_sleep_mode: sdi1_sleep {
+                                        sleep_cfg1 {
+                                                ste,pins = "GPIO208_AH16"; /* CLK */
+                                                ste,config = <&slpm_out_lo_wkup_pdis>;
+                                        };
+                                        sleep_cfg2 {
+                                                ste,pins =
+                                                "GPIO209_AG15", /* FBCLK */
+                                                "GPIO210_AJ15", /* CMD */
+                                                "GPIO211_AG14", /* DAT0 */
+                                                "GPIO212_AF13", /* DAT1 */
+                                                "GPIO213_AG13", /* DAT2 */
+                                                "GPIO214_AH15"; /* DAT3 */
+                                                ste,config = <&slpm_in_wkup_pdis>;
+                                        };
+                                };
+                        };
+
+                        sdi2 {
+                                /* This is the eMMC 8 bits wide, usually PoP eMMC */
+                                sdi2_default_mode: sdi2_default {
+                                        default_mux {
+                                                ste,function = "mc2";
+                                                ste,pins = "mc2_a_1";
+                                        };
+                                        default_cfg1 {
+                                                ste,pins = "GPIO128_A5"; /* CLK */
+                                                ste,config = <&out_lo>;
+                                        };
+                                        default_cfg2 {
+                                                ste,pins = "GPIO130_C8"; /* FBCLK */
+                                                ste,config = <&in_nopull>;
+                                        };
+                                        default_cfg3 {
+                                                ste,pins =
+                                                "GPIO129_B4", /* CMD */
+                                                "GPIO131_A12", /* DAT0 */
+                                                "GPIO132_C10", /* DAT1 */
+                                                "GPIO133_B10", /* DAT2 */
+                                                "GPIO134_B9", /* DAT3 */
+                                                "GPIO135_A9", /* DAT4 */
+                                                "GPIO136_C7", /* DAT5 */
+                                                "GPIO137_A7", /* DAT6 */
+                                                "GPIO138_C5"; /* DAT7 */
+                                                ste,config = <&in_pu>;
+                                        };
+                                };
+
+                                sdi2_sleep_mode: sdi2_sleep {
+                                        sleep_cfg1 {
+                                                ste,pins = "GPIO128_A5"; /* CLK */
+                                                ste,config = <&out_lo_wkup_pdis>;
+                                        };
+                                        sleep_cfg2 {
+                                                ste,pins =
+                                                "GPIO130_C8", /* FBCLK */
+                                                "GPIO129_B4"; /* CMD */
+                                                ste,config = <&in_wkup_pdis_en>;
+                                        };
+                                        sleep_cfg3 {
+                                                ste,pins =
+                                                "GPIO131_A12", /* DAT0 */
+                                                "GPIO132_C10", /* DAT1 */
+                                                "GPIO133_B10", /* DAT2 */
+                                                "GPIO134_B9", /* DAT3 */
+                                                "GPIO135_A9", /* DAT4 */
+                                                "GPIO136_C7", /* DAT5 */
+                                                "GPIO137_A7", /* DAT6 */
+                                                "GPIO138_C5"; /* DAT7 */
+                                                ste,config = <&in_wkup_pdis>;
+                                        };
+                                };
+                        };
+
+                        sdi4 {
+                                /* This is the eMMC 8 bits wide, usually PCB-mounted eMMC */
+                                sdi4_default_mode: sdi4_default {
+                                        default_mux {
+                                                ste,function = "mc4";
+                                                ste,pins = "mc4_a_1";
+                                        };
+                                        default_cfg1 {
+                                                ste,pins = "GPIO203_AE23"; /* CLK */
+                                                ste,config = <&out_lo>;
+                                        };
+                                        default_cfg2 {
+                                                ste,pins = "GPIO202_AF25"; /* FBCLK */
+                                                ste,config = <&in_nopull>;
+                                        };
+                                        default_cfg3 {
+                                                ste,pins =
+                                                "GPIO201_AF24", /* CMD */
+                                                "GPIO200_AH26", /* DAT0 */
+                                                "GPIO199_AH23", /* DAT1 */
+                                                "GPIO198_AG25", /* DAT2 */
+                                                "GPIO197_AH24", /* DAT3 */
+                                                "GPIO207_AJ23", /* DAT4 */
+                                                "GPIO206_AG24", /* DAT5 */
+                                                "GPIO205_AG23", /* DAT6 */
+                                                "GPIO204_AF23"; /* DAT7 */
+                                                ste,config = <&in_pu>;
+                                        };
+                                };
+
+                                sdi4_sleep_mode: sdi4_sleep {
+                                        sleep_cfg1 {
+                                                ste,pins = "GPIO203_AE23"; /* CLK */
+                                                ste,config = <&out_lo_wkup_pdis>;
+                                        };
+                                        sleep_cfg2 {
+                                                ste,pins =
+                                                "GPIO202_AF25", /* FBCLK */
+                                                "GPIO201_AF24", /* CMD */
+                                                "GPIO200_AH26", /* DAT0 */
+                                                "GPIO199_AH23", /* DAT1 */
+                                                "GPIO198_AG25", /* DAT2 */
+                                                "GPIO197_AH24", /* DAT3 */
+                                                "GPIO207_AJ23", /* DAT4 */
+                                                "GPIO206_AG24", /* DAT5 */
+                                                "GPIO205_AG23", /* DAT6 */
+                                                "GPIO204_AF23"; /* DAT7 */
+                                                ste,config = <&slpm_in_wkup_pdis>;
+                                        };
+                                };
+                        };
+
+                        /*
+                         * Multi-rate serial ports (MSPs) - MSP3 output is internal and
+                         * cannot be muxed onto any pins.
+                         */
+                        msp0 {
+                                msp0_default_mode: msp0_default {
+                                        default_msp0_mux {
+                                                ste,function = "msp0";
+                                                ste,pins = "msp0txrx_a_1", "msp0tfstck_a_1";
+                                        };
+                                        default_msp0_cfg {
+                                                ste,pins =
+                                                "GPIO12_AC4", /* TXD */
+                                                "GPIO15_AC3", /* RXD */
+                                                "GPIO13_AF3", /* TFS */
+                                                "GPIO14_AE3"; /* TCK */
+                                                ste,config = <&in_nopull>;
+                                        };
+                                };
+                        };
+
+                        msp1 {
+                                msp1_default_mode: msp1_default {
+                                        default_mux {
+                                                ste,function = "msp1";
+                                                ste,pins = "msp1txrx_a_1", "msp1_a_1";
+                                        };
+                                        default_cfg1 {
+                                                ste,pins = "GPIO33_AF2";
+                                                ste,config = <&out_lo>;
+                                        };
+                                        default_cfg2 {
+                                                ste,pins =
+                                                "GPIO34_AE1",
+                                                "GPIO35_AE2",
+                                                "GPIO36_AG2";
+                                                ste,config = <&in_nopull>;
+                                        };
+
+                                };
+                        };
+
+                        msp2 {
+                                msp2_default_mode: msp2_default {
+                                        /* MSP2 usually used for HDMI audio */
+                                        default_mux {
+                                                ste,function = "msp2";
+                                                ste,pins = "msp2_a_1";
+                                        };
+                                        default_cfg1 {
+                                                ste,pins =
+                                                "GPIO193_AH27", /* TXD */
+                                                "GPIO194_AF27", /* TCK */
+                                                "GPIO195_AG28"; /* TFS */
+                                                ste,config = <&in_pd>;
+                                        };
+                                        default_cfg2 {
+                                                ste,pins = "GPIO196_AG26"; /* RXD */
+                                                ste,config = <&out_lo>;
+                                        };
+                                };
+                        };
+
+
+                        musb {
+                                musb_default_mode: musb_default {
+                                        default_mux {
+                                                ste,function = "usb";
+                                                ste,pins = "usb_a_1";
+                                        };
+                                        default_cfg1 {
+                                                ste,pins =
+                                                "GPIO256_AF28", /* NXT */
+                                                "GPIO258_AD29", /* XCLK */
+                                                "GPIO259_AC29", /* DIR */
+                                                "GPIO260_AD28", /* DAT7 */
+                                                "GPIO261_AD26", /* DAT6 */
+                                                "GPIO262_AE26", /* DAT5 */
+                                                "GPIO263_AG29", /* DAT4 */
+                                                "GPIO264_AE27", /* DAT3 */
+                                                "GPIO265_AD27", /* DAT2 */
+                                                "GPIO266_AC28", /* DAT1 */
+                                                "GPIO267_AC27"; /* DAT0 */
+                                                ste,config = <&in_nopull>;
+                                        };
+                                        default_cfg2 {
+                                                ste,pins = "GPIO257_AE29"; /* STP */
+                                                ste,config = <&out_hi>;
+                                        };
+                                };
+
+                                musb_sleep_mode: musb_sleep {
+                                        sleep_cfg1 {
+                                                ste,pins =
+                                                "GPIO256_AF28", /* NXT */
+                                                "GPIO258_AD29", /* XCLK */
+                                                "GPIO259_AC29"; /* DIR */
+                                                ste,config = <&slpm_wkup_pdis_en>;
+                                        };
+                                        sleep_cfg2 {
+                                                ste,pins = "GPIO257_AE29"; /* STP */
+                                                ste,config = <&slpm_out_hi_wkup_pdis>;
+                                        };
+                                        sleep_cfg3 {
+                                                ste,pins =
+                                                "GPIO260_AD28", /* DAT7 */
+                                                "GPIO261_AD26", /* DAT6 */
+                                                "GPIO262_AE26", /* DAT5 */
+                                                "GPIO263_AG29", /* DAT4 */
+                                                "GPIO264_AE27", /* DAT3 */
+                                                "GPIO265_AD27", /* DAT2 */
+                                                "GPIO266_AC28", /* DAT1 */
+                                                "GPIO267_AC27"; /* DAT0 */
+                                                ste,config = <&slpm_in_wkup_pdis_en>;
+                                        };
+                                };
+                        };
+
+                        mcde {
+                                lcd_default_mode: lcd_default {
+                                        default_mux {
+                                                /* Mux in VSI0 and all the data lines */
+                                                ste,function = "lcd";
+                                                ste,pins =
+                                                "lcdvsi0_a_1", /* VSI0 for LCD */
+                                                "lcd_d0_d7_a_1", /* Data lines */
+                                                "lcd_d8_d11_a_1", /* TV-out */
+                                                "lcdaclk_b_1", /* Clock line for TV-out */
+                                                "lcdvsi1_a_1"; /* VSI1 for HDMI */
+                                        };
+                                        default_cfg1 {
+                                                ste,pins =
+                                                "GPIO68_E1", /* VSI0 */
+                                                "GPIO69_E2"; /* VSI1 */
+                                                ste,config = <&in_pu>;
+                                        };
+                                };
+                                lcd_sleep_mode: lcd_sleep {
+                                        sleep_cfg1 {
+                                                ste,pins = "GPIO69_E2"; /* VSI1 */
+                                                ste,config = <&slpm_in_wkup_pdis>;
+                                        };
+                                };
+                        };
+
+                        ske {
+                                /* SKE keys on position 2 in an 8x8 matrix */
+                                ske_kpa2_default_mode: ske_kpa2_default {
+                                        default_mux {
+                                                ste,function = "kp";
+                                                ste,pins = "kp_a_2";
+                                        };
+                                        default_cfg1 {
+                                                ste,pins =
+                                                "GPIO153_B17", /* I7 */
+                                                "GPIO154_C16", /* I6 */
+                                                "GPIO155_C19", /* I5 */
+                                                "GPIO156_C17", /* I4 */
+                                                "GPIO161_D21", /* I3 */
+                                                "GPIO162_D20", /* I2 */
+                                                "GPIO163_C20", /* I1 */
+                                                "GPIO164_B21"; /* I0 */
+                                                ste,config = <&in_pd>;
+                                        };
+                                        default_cfg2 {
+                                                ste,pins =
+                                                "GPIO157_A18", /* O7 */
+                                                "GPIO158_C18", /* O6 */
+                                                "GPIO159_B19", /* O5 */
+                                                "GPIO160_B20", /* O4 */
+                                                "GPIO165_C21", /* O3 */
+                                                "GPIO166_A22", /* O2 */
+                                                "GPIO167_B24", /* O1 */
+                                                "GPIO168_C22"; /* O0 */
+                                                ste,config = <&out_lo>;
+                                        };
+                                };
+                                ske_kpa2_sleep_mode: ske_kpa2_sleep {
+                                        sleep_cfg1 {
+                                                ste,pins =
+                                                "GPIO153_B17", /* I7 */
+                                                "GPIO154_C16", /* I6 */
+                                                "GPIO155_C19", /* I5 */
+                                                "GPIO156_C17", /* I4 */
+                                                "GPIO161_D21", /* I3 */
+                                                "GPIO162_D20", /* I2 */
+                                                "GPIO163_C20", /* I1 */
+                                                "GPIO164_B21"; /* I0 */
+                                                ste,config = <&slpm_in_pu_wkup_pdis_en>;
+                                        };
+                                        sleep_cfg2 {
+                                                ste,pins =
+                                                "GPIO157_A18", /* O7 */
+                                                "GPIO158_C18", /* O6 */
+                                                "GPIO159_B19", /* O5 */
+                                                "GPIO160_B20", /* O4 */
+                                                "GPIO165_C21", /* O3 */
+                                                "GPIO166_A22", /* O2 */
+                                                "GPIO167_B24", /* O1 */
+                                                "GPIO168_C22"; /* O0 */
+                                                ste,config = <&slpm_out_lo_pdis>;
+                                        };
+                                };
+                                /*
+                                 * SKE keys on position 1 and "other C1" combi giving
+                                 * six rows of six keys.
+                                 */
+                                ske_kpaoc1_default_mode: ske_kpaoc1_default {
+                                        default_mux {
+                                                ste,function = "kp";
+                                                ste,pins = "kp_a_1", "kp_oc1_1";
+                                        };
+                                        default_cfg1 {
+                                                ste,pins =
+                                                "GPIO91_B6", /* KP_O0 */
+                                                "GPIO90_A3", /* KP_O1 */
+                                                "GPIO87_B3", /* KP_O2 */
+                                                "GPIO86_C6", /* KP_O3 */
+                                                "GPIO96_D8", /* KP_O6 */
+                                                "GPIO94_D7"; /* KP_O7 */
+                                                ste,config = <&out_lo>;
+                                        };
+                                        default_cfg2 {
+                                                ste,pins =
+                                                "GPIO93_B7", /* KP_I0 */
+                                                "GPIO92_D6", /* KP_I1 */
+                                                "GPIO89_E6", /* KP_I2 */
+                                                "GPIO88_C4", /* KP_I3 */
+                                                "GPIO97_D9", /* KP_I6 */
+                                                "GPIO95_E8"; /* KP_I7 */
+                                                ste,config = <&in_pu>;
+                                        };
+                                };
+                        };
+
+                        wlan {
+                                wlan_default_mode: wlan_default {
+                                        /*
+                                         * Activate this mode with the WLAN chip.
+                                         * These are plain GPIO pins used by WLAN
+                                         */
+                                        default_cfg1 {
+                                                ste,pins =
+                                                "GPIO226_AF8", /* WLAN_PMU_EN */
+                                                "GPIO85_D5"; /* WLAN_ENA */
+                                                ste,config = <&gpio_out_lo>;
+                                        };
+                                        default_cfg2 {
+                                                ste,pins = "GPIO4_AH6"; /* WLAN_IRQ on UART1 */
+                                                ste,config = <&gpio_in_pu>;
+                                        };
+                                };
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/ste-href-stuib.dtsi b/arch/arm/boot/dts/ste-href-stuib.dtsi
index 76704ec0ffcc..1c3574435ea8 100644
--- a/arch/arm/boot/dts/ste-href-stuib.dtsi
+++ b/arch/arm/boot/dts/ste-href-stuib.dtsi
@@ -12,6 +12,28 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 
 / {
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                vdd-supply = <&ab8500_ldo_aux1_reg>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&prox_stuib_mode>, <&hall_stuib_mode>;
+
+                button@139 {
+                        /* Proximity sensor */
+                        gpios = <&gpio6 25 0x4>;
+                        linux,code = <11>; /* SW_FRONT_PROXIMITY */
+                        label = "SFH7741 Proximity Sensor";
+                };
+                button@145 {
+                        /* Hall sensor */
+                        gpios = <&gpio4 17 0x4>;
+                        linux,code = <0>; /* SW_LID */
+                        label = "HED54XXU11 Hall Effect Sensor";
+                };
+        };
+
         soc {
                 i2c@80004000 {
                         stmpe1601: stmpe1601@40 {
@@ -74,5 +96,24 @@
                                 rohm,flip-y;
                         };
                 };
+
+                pinctrl {
+                        prox {
+                                prox_stuib_mode: prox_stuib {
+                                        stuib_cfg {
+                                                ste,pins = "GPIO217_AH12";
+                                                ste,config = <&gpio_in_pu>;
+                                        };
+                                };
+                        };
+                        hall {
+                                hall_stuib_mode: stuib_tvk {
+                                        stuib_cfg {
+                                                ste,pins = "GPIO145_C13";
+                                                ste,config = <&gpio_in_pu>;
+                                        };
+                                };
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi
index 76d3ef13175f..c40565320978 100644
--- a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi
+++ b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi
@@ -14,27 +14,105 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 
 / {
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                vdd-supply = <&ab8500_ldo_aux1_reg>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&prox_tvk_mode>, <&hall_tvk_mode>;
+
+                button@139 {
+                        /* Proximity sensor */
+                        gpios = <&gpio6 25 0x4>;
+                        linux,code = <11>; /* SW_FRONT_PROXIMITY */
+                        label = "SFH7741 Proximity Sensor";
+                };
+                button@145 {
+                        /* Hall sensor */
+                        gpios = <&gpio4 17 0x4>;
+                        linux,code = <0>; /* SW_LID */
+                        label = "HED54XXU11 Hall Effect Sensor";
+                };
+        };
+
         soc {
-                /* Add Synaptics touch screen, TC35892 keypad etc here */
+                /* Add Synaptics touch screen, TC35893 keypad etc here */
                 i2c@80004000 {
-                        tc3589x@44 {
-                                compatible = "tc3589x";
+                        tc35893@44 {
+                                compatible = "toshiba,tc35893";
                                 reg = <0x44>;
                                 interrupt-parent = <&gpio6>;
                                 interrupts = <26 IRQ_TYPE_EDGE_RISING>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&tc35893_tvk_mode>;
 
                                 interrupt-controller;
-                                #interrupt-cells = <2>;
+                                #interrupt-cells = <1>;
 
                                 tc3589x_gpio {
-                                        compatible = "tc3589x-gpio";
-                                        interrupts = <0 IRQ_TYPE_EDGE_RISING>;
+                                        compatible = "toshiba,tc3589x-gpio";
+                                        interrupts = <0>;
 
                                         interrupt-controller;
                                         #interrupt-cells = <2>;
                                         gpio-controller;
                                         #gpio-cells = <2>;
                                 };
+                                tc3589x_keypad {
+                                        compatible = "toshiba,tc3589x-keypad";
+                                        interrupts = <6>;
+                                        debounce-delay-ms = <4>;
+                                        keypad,num-columns = <8>;
+                                        keypad,num-rows = <8>;
+                                        linux,no-autorepeat;
+                                        linux,wakeup;
+                                        linux,keymap = <0x0301006b
+                                                        0x04010066
+                                                        0x06040072
+                                                        0x040200d7
+                                                        0x0303006a
+                                                        0x0205000e
+                                                        0x0607008b
+                                                        0x0500001c
+                                                        0x0403000b
+                                                        0x03040034
+                                                        0x05020067
+                                                        0x0305006c
+                                                        0x040500e7
+                                                        0x0005009e
+                                                        0x06020073
+                                                        0x01030039
+                                                        0x07060069
+                                                        0x050500d9>;
+                                };
+                        };
+                };
+                pinctrl {
+                        /* Pull up this GPIO pin */
+                        tc35893 {
+                                tc35893_tvk_mode: tc35893_tvk {
+                                        tvk_cfg {
+                                                ste,pins = "GPIO218_AH11";
+                                                ste,config = <&gpio_in_pu>;
+                                        };
+                                };
+                        };
+                        prox {
+                                prox_tvk_mode: prox_tvk {
+                                        tvk_cfg {
+                                                ste,pins = "GPIO217_AH12";
+                                                ste,config = <&gpio_in_pu>;
+                                        };
+                                };
+                        };
+                        hall {
+                                hall_tvk_mode: hall_tvk {
+                                        tvk_cfg {
+                                                ste,pins = "GPIO145_C13";
+                                                ste,config = <&gpio_in_pu>;
+                                        };
+                                };
                         };
                 };
         };
diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi
index aa3f02060fdd..0c1e8d871ed1 100644
--- a/arch/arm/boot/dts/ste-href.dtsi
+++ b/arch/arm/boot/dts/ste-href.dtsi
@@ -11,37 +11,57 @@
 
 #include <dt-bindings/interrupt-controller/irq.h>
 #include "ste-dbx5x0.dtsi"
+#include "ste-href-family-pinctrl.dtsi"
 
 / {
         memory {
                 reg = <0x00000000 0x20000000>;
         };
 
-        gpio_keys {
-                compatible = "gpio-keys";
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                button@1 {
-                        linux,code = <11>;
-                        label = "SFH7741 Proximity Sensor";
+        soc {
+                usb_per5@a03e0000 {
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&musb_default_mode>;
+                        pinctrl-1 = <&musb_sleep_mode>;
                 };
-        };
 
-        soc {
                 uart@80120000 {
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&uart0_default_mode>;
+                        pinctrl-1 = <&uart0_sleep_mode>;
                         status = "okay";
                 };
 
                 uart@80121000 {
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&uart1_default_mode>;
+                        pinctrl-1 = <&uart1_sleep_mode>;
                         status = "okay";
                 };
 
                 uart@80007000 {
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&uart2_default_mode>;
+                        pinctrl-1 = <&uart2_sleep_mode>;
                         status = "okay";
                 };
 
+                i2c@80004000 {
+                        pinctrl-names = "default","sleep";
+                        pinctrl-0 = <&i2c0_default_mode>;
+                        pinctrl-1 = <&i2c0_sleep_mode>;
+                };
+
+                i2c@80122000 {
+                        pinctrl-names = "default","sleep";
+                        pinctrl-0 = <&i2c1_default_mode>;
+                        pinctrl-1 = <&i2c1_sleep_mode>;
+                };
+
                 i2c@80128000 {
+                        pinctrl-names = "default","sleep";
+                        pinctrl-0 = <&i2c2_default_mode>;
+                        pinctrl-1 = <&i2c2_sleep_mode>;
                         lp5521@33 {
                                 compatible = "national,lp5521";
                                 reg = <0x33>;
@@ -85,6 +105,12 @@
                         };
                 };
 
+                i2c@80110000 {
+                        pinctrl-names = "default","sleep";
+                        pinctrl-0 = <&i2c3_default_mode>;
+                        pinctrl-1 = <&i2c3_sleep_mode>;
+                };
+
                 // External Micro SD slot
                 sdi0_per1@80126000 {
                         arm,primecell-periphid = <0x10480180>;
@@ -94,8 +120,9 @@
                         mmc-cap-mmc-highspeed;
                         vmmc-supply = <&ab8500_ldo_aux3_reg>;
                         vqmmc-supply = <&vmmci>;
-
-                        cd-gpios  = <&tc3589x_gpio 3 0x4>;
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&sdi0_default_mode>;
+                        pinctrl-1 = <&sdi0_sleep_mode>;
 
                         status = "okay";
                 };
@@ -105,6 +132,9 @@
                         arm,primecell-periphid = <0x10480180>;
                         max-frequency = <100000000>;
                         bus-width = <4>;
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&sdi1_default_mode>;
+                        pinctrl-1 = <&sdi1_sleep_mode>;
 
                         status = "okay";
                 };
@@ -115,6 +145,9 @@
                         max-frequency = <100000000>;
                         bus-width = <8>;
                         mmc-cap-mmc-highspeed;
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&sdi2_default_mode>;
+                        pinctrl-1 = <&sdi2_sleep_mode>;
 
                         status = "okay";
                 };
@@ -126,6 +159,9 @@
                         bus-width = <8>;
                         mmc-cap-mmc-highspeed;
                         vmmc-supply = <&ab8500_ldo_aux2_reg>;
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&sdi4_default_mode>;
+                        pinctrl-1 = <&sdi4_sleep_mode>;
 
                         status = "okay";
                 };
@@ -137,7 +173,21 @@
                         stericsson,audio-codec = <&codec>;
                 };
 
+                msp0: msp@80123000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&msp0_default_mode>;
+                        status = "okay";
+                };
+
                 msp1: msp@80124000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&msp1_default_mode>;
+                        status = "okay";
+                };
+
+                msp2: msp@80117000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&msp2_default_mode>;
                         status = "okay";
                 };
 
@@ -198,5 +248,11 @@
                                 };
                         };
                 };
+
+                mcde@a0350000 {
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&lcd_default_mode>;
+                        pinctrl-1 = <&lcd_sleep_mode>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/ste-hrefprev60.dtsi b/arch/arm/boot/dts/ste-hrefprev60.dtsi
index b2cd7bc2752f..40f0ecdf9303 100644
--- a/arch/arm/boot/dts/ste-hrefprev60.dtsi
+++ b/arch/arm/boot/dts/ste-hrefprev60.dtsi
@@ -28,18 +28,20 @@
                                 reg = <0x33>;
                         };
 
-                        tc3589x@42 {
-                                compatible = "tc3589x";
+                        tc35892@42 {
+                                compatible = "toshiba,tc35892";
                                 reg = <0x42>;
                                 interrupt-parent = <&gpio6>;
                                 interrupts = <25 IRQ_TYPE_EDGE_RISING>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&tc35892_hrefprev60_mode>;
 
                                 interrupt-controller;
-                                #interrupt-cells = <2>;
+                                #interrupt-cells = <1>;
 
                                 tc3589x_gpio: tc3589x_gpio {
                                         compatible = "tc3589x-gpio";
-                                        interrupts = <0 IRQ_TYPE_EDGE_RISING>;
+                                        interrupts = <0>;
 
                                         interrupt-controller;
                                         #interrupt-cells = <2>;
@@ -49,11 +51,77 @@
                         };
                 };
 
+                ssp@80002000 {
+                        /*
+                         * On the first generation boards, this SSP/SPI port was connected
+                         * to the AB8500.
+                         */
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&ssp0_hrefprev60_mode>;
+                };
+
+                // External Micro SD slot
+                sdi0_per1@80126000 {
+                        cd-gpios  = <&tc3589x_gpio 3 0x4>;
+                };
+
                 vmmci: regulator-gpio {
                         gpios = <&tc3589x_gpio 18 0x4>;
                         enable-gpio = <&tc3589x_gpio 17 0x4>;
+                };
+
+                pinctrl {
+                        /* Set this up using hogs */
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&ipgpio_hrefprev60_mode>;
 
-                        status = "okay";
+                        ssp0 {
+                                ssp0_hrefprev60_mode: ssp0_hrefprev60_default {
+                                        hrefprev60_mux {
+                                                ste,function = "ssp0";
+                                                ste,pins = "ssp0_a_1";
+                                        };
+                                        hrefprev60_cfg1 {
+                                                ste,pins = "GPIO145_C13"; /* RXD */
+                                                ste,config = <&in_pd>;
+                                        };
+
+                                };
+                        };
+                        sdi0 {
+                                /* This additional pin needed on early MOP500 and HREFs previous to v60 */
+                                sdi0_default_mode: sdi0_default {
+                                        hrefprev60_mux {
+                                                ste,function = "mc0";
+                                                ste,pins = "mc0dat31dir_a_1";
+                                        };
+                                        hrefprev60_cfg1 {
+                                                ste,pins = "GPIO21_AB3"; /* DAT31DIR */
+                                                ste,config = <&out_hi>;
+                                        };
+
+                                };
+                        };
+                        tc35892 {
+                                tc35892_hrefprev60_mode: tc35892_hrefprev60 {
+                                        hrefprev60_cfg {
+                                                ste,pins = "GPIO217_AH12";
+                                                ste,config = <&gpio_in_pu>;
+                                        };
+                                };
+                        };
+                        ipgpio {
+                                 ipgpio_hrefprev60_mode: ipgpio_hrefprev60 {
+                                        hrefprev60_mux {
+                                                ste,function = "ipgpio";
+                                                ste,pins = "ipgpio0_c_1", "ipgpio1_c_1";
+                                        };
+                                        hrefprev60_cfg1 {
+                                                ste,pins = "GPIO6_AF6", "GPIO7_AG5";
+                                                ste,config = <&in_pu>;
+                                        };
+                                 };
+                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/ste-hrefv60plus.dtsi
index aed511b47a9e..3b6d1181939b 100644
--- a/arch/arm/boot/dts/ste-hrefv60plus.dtsi
+++ b/arch/arm/boot/dts/ste-hrefv60plus.dtsi
@@ -16,55 +16,226 @@
         model = "ST-Ericsson HREF (v60+) platform with Device Tree";
         compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500";
 
-        gpio_keys {
-                button@1 {
-                        gpios = <&gpio5 25 0x4>;
-                };
-        };
-
         soc {
                 // External Micro SD slot
                 sdi0_per1@80126000 {
-                        arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <100000000>;
-                        bus-width = <4>;
-                        mmc-cap-sd-highspeed;
-                        mmc-cap-mmc-highspeed;
-                        vmmc-supply = <&ab8500_ldo_aux3_reg>;
-
                         cd-gpios  = <&gpio2 31 0x4>; // 95
-
-                        status = "okay";
                 };
 
-                // WLAN SDIO channel
-                sdi1_per2@80118000 {
-                        arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <100000000>;
-                        bus-width = <4>;
-
-                        status = "okay";
-                };
-
-                // PoP:ed eMMC
-                sdi2_per3@80005000 {
-                        arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <100000000>;
-                        bus-width = <8>;
-                        mmc-cap-mmc-highspeed;
-
-                        status = "okay";
+                vmmci: regulator-gpio {
+                        gpios = <&gpio0 5 0x4>;
+                        enable-gpio = <&gpio5 9 0x4>;
                 };
 
-                // On-board eMMC
-                sdi4_per2@80114000 {
-                        arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <100000000>;
-                        bus-width = <8>;
-                        mmc-cap-mmc-highspeed;
-                        vmmc-supply = <&ab8500_ldo_aux2_reg>;
+                pinctrl {
+                        /*
+                         * Set this up using hogs, as time goes by and as seems fit, these
+                         * can be moved over to being controlled by respective device.
+                         */
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&ipgpio_hrefv60_mode>,
+                                  <&accel_hrefv60_mode>,
+                                  <&magneto_hrefv60_mode>,
+                                  <&etm_hrefv60_mode>,
+                                  <&nahj_hrefv60_mode>,
+                                  <&nfc_hrefv60_mode>,
+                                  <&force_hrefv60_mode>,
+                                  <&dipro_hrefv60_mode>,
+                                  <&vaudio_hf_hrefv60_mode>,
+                                  <&gbf_hrefv60_mode>,
+                                  <&hdtv_hrefv60_mode>,
+                                  <&touch_hrefv60_mode>;
 
-                        status = "okay";
+                        sdi0 {
+                                /* SD card detect GPIO pin, extend default state */
+                                sdi0_default_mode: sdi0_default {
+                                        default_hrefv60_cfg1 {
+                                                ste,pins = "GPIO95_E8";
+                                                ste,config = <&gpio_in_pu>;
+                                        };
+                                };
+                        };
+                        ipgpio {
+                                /*
+                                 * XENON Flashgun on image processor GPIO (controlled from image
+                                 * processor firmware), mux in these image processor GPIO lines 0
+                                 * (XENON_FLASH_ID), 1 (XENON_READY) and there is an assistant
+                                 * LED on IP GPIO 4 (XENON_EN2) on altfunction C, that need bias
+                                 * from GPIO21 so pull up 0, 1 and drive 4 and GPIO21 low as output.
+                                 */
+                                ipgpio_hrefv60_mode: ipgpio_hrefv60 {
+                                        hrefv60_mux {
+                                                ste,function = "ipgpio";
+                                                ste,pins = "ipgpio0_c_1", "ipgpio1_c_1", "ipgpio4_c_1";
+                                        };
+                                        hrefv60_cfg1 {
+                                                ste,pins = "GPIO6_AF6", "GPIO7_AG5";
+                                                ste,config = <&in_pu>;
+                                        };
+                                        hrefv60_cfg2 {
+                                                ste,pins = "GPIO21_AB3";
+                                                ste,config = <&gpio_out_lo>;
+                                        };
+                                        hrefv60_cfg3 {
+                                                ste,pins = "GPIO64_F3";
+                                                ste,config = <&out_lo>;
+                                        };
+                                };
+                        };
+                        accelerometer {
+                                accel_hrefv60_mode: accel_hrefv60 {
+                                        /* Accelerometer interrupt lines 1 & 2 */
+                                        hrefv60_cfg1 {
+                                                ste,pins = "GPIO82_C1", "GPIO83_D3";
+                                                ste,config = <&gpio_in_pu>;
+                                        };
+                                };
+                        };
+                        magnetometer {
+                                magneto_hrefv60_mode: magneto_hrefv60 {
+                                        /* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */
+                                        hrefv60_cfg1 {
+                                                ste,pins = "GPIO31_V3";
+                                                ste,config = <&gpio_in_pu>;
+                                        };
+                                        hrefv60_cfg2 {
+                                                ste,pins = "GPIO32_V2";
+                                                ste,config = <&gpio_in_pd>;
+                                        };
+                                };
+                        };
+                        etm {
+                                /*
+                                 * Drive D19-D23 for the ETM PTM trace interface low,
+                                 * (presumably pins are unconnected therefore grounded here,
+                                 * the "other alt C1" setting enables these pins)
+                                 */
+                                etm_hrefv60_mode: etm_hrefv60 {
+                                        hrefv60_cfg1 {
+                                                ste,pins =
+                                                "GPIO70_G5",
+                                                "GPIO71_G4",
+                                                "GPIO72_H4",
+                                                "GPIO73_H3",
+                                                "GPIO74_J3";
+                                                ste,config = <&gpio_out_lo>;
+                                        };
+                                 };
+                        };
+                        nahj {
+                                nahj_hrefv60_mode: nahj_hrefv60 {
+                                        /* NAHJ CTRL on GPIO76 to low, CTRL_INV on GPIO216 to high */
+                                        hrefv60_cfg1 {
+                                                ste,pins = "GPIO76_J2";
+                                                ste,config = <&gpio_out_lo>;
+                                        };
+                                        hrefv60_cfg2 {
+                                                ste,pins = "GPIO216_AG12";
+                                                ste,config = <&gpio_out_hi>;
+                                        };
+                                 };
+                        };
+                        nfc {
+                                nfc_hrefv60_mode: nfc_hrefv60 {
+                                        /* NFC ENA and RESET to low, pulldown IRQ line */
+                                        hrefv60_cfg1 {
+                                                ste,pins =
+                                                "GPIO77_H1", /* NFC_ENA */
+                                                "GPIO142_C11"; /* NFC_RESET */
+                                                ste,config = <&gpio_out_lo>;
+                                        };
+                                        hrefv60_cfg2 {
+                                                ste,pins = "GPIO144_B13"; /* NFC_IRQ */
+                                                ste,config = <&gpio_in_pd>;
+                                        };
+                                 };
+                        };
+                        force {
+                                force_hrefv60_mode: force_hrefv60 {
+                                        hrefv60_cfg1 {
+                                                ste,pins = "GPIO91_B6"; /* FORCE_SENSING_INT */
+                                                ste,config = <&gpio_in_pu>;
+                                        };
+                                        hrefv60_cfg2 {
+                                                ste,pins =
+                                                "GPIO92_D6", /* FORCE_SENSING_RST */
+                                                "GPIO97_D9"; /* FORCE_SENSING_WU */
+                                                ste,config = <&gpio_out_lo>;
+                                        };
+                                 };
+                        };
+                        dipro {
+                                dipro_hrefv60_mode: dipro_hrefv60 {
+                                        hrefv60_cfg1 {
+                                                ste,pins = "GPIO139_C9"; /* DIPRO_INT */
+                                                ste,config = <&gpio_in_pu>;
+                                        };
+                                 };
+                        };
+                        vaudio_hf {
+                                vaudio_hf_hrefv60_mode: vaudio_hf_hrefv60 {
+                                        /* Audio Amplifier HF enable GPIO */
+                                        hrefv60_cfg1 {
+                                                ste,pins = "GPIO149_B14"; /* VAUDIO_HF_EN, enable MAX8968 */
+                                                ste,config = <&gpio_out_hi>;
+                                        };
+                                 };
+                        };
+                        gbf {
+                                gbf_hrefv60_mode: gbf_hrefv60 {
+                                        /*
+                                         * GBF (GPS, Bluetooth, FM-radio) interface,
+                                         * pull low to reset state
+                                         */
+                                        hrefv60_cfg1 {
+                                                ste,pins = "GPIO171_D23"; /* GBF_ENA_RESET */
+                                                ste,config = <&gpio_out_lo>;
+                                        };
+                                 };
+                        };
+                        hdtv {
+                                hdtv_hrefv60_mode: hdtv_hrefv60 {
+                                        /* MSP : HDTV INTERFACE GPIO line */
+                                        hrefv60_cfg1 {
+                                                ste,pins = "GPIO192_AJ27";
+                                                ste,config = <&gpio_in_pd>;
+                                        };
+                                 };
+                        };
+                        touch {
+                                touch_hrefv60_mode: touch_hrefv60 {
+                                        /*
+                                         * Touch screen uses GPIO 143 for RST1, GPIO 146 for RST2 and
+                                         * GPIO 67 for interrupts. Pull-up the IRQ line and drive both
+                                         * reset signals low.
+                                         */
+                                        hrefv60_cfg1 {
+                                                ste,pins = "GPIO143_D12", "GPIO146_D13";
+                                                ste,config = <&gpio_out_lo>;
+                                        };
+                                        hrefv60_cfg2 {
+                                                ste,pins = "GPIO67_G2";
+                                                ste,config = <&gpio_in_pu>;
+                                        };
+                                };
+                        };
+                        mcde {
+                                lcd_hrefv60_mode: lcd_hrefv60 {
+                                        /*
+                                         * Display Interface 1 uses GPIO 65 for RST (reset).
+                                         * Display Interface 2 uses GPIO 66 for RST (reset).
+                                         * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset)
+                                         */
+                                        hrefv60_cfg1 {
+                                                ste,pins ="GPIO65_F1";
+                                                ste,config = <&gpio_out_hi>;
+                                        };
+                                        hrefv60_cfg2 {
+                                                ste,pins ="GPIO66_G3";
+                                                ste,config = <&gpio_out_lo>;
+                                        };
+                                };
+                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi b/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi
index efddee9403c4..e6f22b266420 100644
--- a/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi
+++ b/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi
@@ -31,17 +31,57 @@
                 ste,output = <OUTPUT_LOW>;
         };
 
+        gpio_in_pu: gpio_input_pull_up {
+                ste,gpio = <GPIOMODE_ENABLED>;
+                ste,input = <INPUT_PULLUP>;
+        };
+
+        gpio_in_pd: gpio_input_pull_down {
+                ste,gpio = <GPIOMODE_ENABLED>;
+                ste,input = <INPUT_PULLDOWN>;
+        };
+
         gpio_out_lo: gpio_output_low {
                 ste,gpio = <GPIOMODE_ENABLED>;
                 ste,output = <OUTPUT_LOW>;
         };
 
+        gpio_out_hi: gpio_output_high {
+                ste,gpio = <GPIOMODE_ENABLED>;
+                ste,output = <OUTPUT_HIGH>;
+        };
+
+        slpm_pdis: slpm_pdis {
+                ste,sleep = <SLPM_ENABLED>;
+                ste,sleep-wakeup = <SLPM_WAKEUP_DISABLE>;
+                ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
+        };
+
+        slpm_wkup_pdis: slpm_wkup_pdis {
+                ste,sleep = <SLPM_ENABLED>;
+                ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
+                ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
+        };
+
+        slpm_wkup_pdis_en: slpm_wkup_pdis_en {
+                ste,sleep = <SLPM_ENABLED>;
+                ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
+                ste,sleep-pull-disable = <SLPM_PDIS_ENABLED>;
+        };
+
         slpm_in_pu: slpm_in_pu {
                 ste,sleep = <SLPM_ENABLED>;
                 ste,sleep-input = <SLPM_INPUT_PULLUP>;
                 ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
         };
 
+        slpm_in_pdis: slpm_in_pdis {
+                ste,sleep = <SLPM_ENABLED>;
+                ste,sleep-input = <SLPM_DIR_INPUT>;
+                ste,sleep-wakeup = <SLPM_WAKEUP_DISABLE>;
+                ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
+        };
+
         slpm_in_wkup_pdis: slpm_in_wkup_pdis {
                 ste,sleep = <SLPM_ENABLED>;
                 ste,sleep-input = <SLPM_DIR_INPUT>;
@@ -49,6 +89,20 @@
                 ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
         };
 
+        slpm_in_wkup_pdis_en: slpm_in_wkup_pdis_en {
+                ste,sleep = <SLPM_ENABLED>;
+                ste,sleep-input = <SLPM_DIR_INPUT>;
+                ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
+                ste,sleep-pull-disable = <SLPM_PDIS_ENABLED>;
+        };
+
+        slpm_in_pu_wkup_pdis_en: slpm_in_wkup_pdis_en {
+                ste,sleep = <SLPM_ENABLED>;
+                ste,sleep-input = <SLPM_INPUT_PULLUP>;
+                ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
+                ste,sleep-pull-disable = <SLPM_PDIS_ENABLED>;
+        };
+
         slpm_out_lo: slpm_out_lo {
                 ste,sleep = <SLPM_ENABLED>;
                 ste,sleep-output = <SLPM_OUTPUT_LOW>;
@@ -68,6 +122,20 @@
                 ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
         };
 
+        slpm_out_lo_pdis: slpm_out_lo_pdis {
+                ste,sleep = <SLPM_ENABLED>;
+                ste,sleep-output = <SLPM_OUTPUT_LOW>;
+                ste,sleep-wakeup = <SLPM_WAKEUP_DISABLE>;
+                ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
+        };
+
+        slpm_out_lo_wkup_pdis: slpm_out_lo_wkup_pdis {
+                ste,sleep = <SLPM_ENABLED>;
+                ste,sleep-output = <SLPM_OUTPUT_LOW>;
+                ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
+                ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
+        };
+
         slpm_out_wkup_pdis: slpm_out_wkup_pdis {
                 ste,sleep = <SLPM_ENABLED>;
                 ste,sleep-output = <SLPM_DIR_OUTPUT>;
@@ -81,6 +149,18 @@
                 ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
         };
 
+        in_wkup_pdis_en: in_wkup_pdis_en {
+                ste,sleep-input = <SLPM_DIR_INPUT>;
+                ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
+                ste,sleep-pull-disable = <SLPM_PDIS_ENABLED>;
+        };
+
+        out_lo_wkup_pdis: out_lo_wkup_pdis {
+                ste,sleep-output = <SLPM_OUTPUT_LOW>;
+                ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
+                ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
+        };
+
         out_hi_wkup_pdis: out_hi_wkup_pdis {
                 ste,sleep-output = <SLPM_OUTPUT_HIGH>;
                 ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
diff --git a/arch/arm/boot/dts/ste-nomadik-s8815.dts b/arch/arm/boot/dts/ste-nomadik-s8815.dts
index 16c3888b7b15..f557feb997f4 100644
--- a/arch/arm/boot/dts/ste-nomadik-s8815.dts
+++ b/arch/arm/boot/dts/ste-nomadik-s8815.dts
@@ -67,10 +67,6 @@
 
         /* Custom board node with GPIO pins to active etc */
         usb-s8815 {
-                /* The S8815 is using this very GPIO pin for the SMSC91x IRQs */
-                ethernet-gpio {
-                        gpios = <&gpio3 8 0x1>;
-                };
                 /* This will bias the MMC/SD card detect line */
                 mmcsd-gpio {
                         gpios = <&gpio3 16 0x1>;
diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
index 79425e3836ce..5acc0449676a 100644
--- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
+++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
@@ -769,14 +769,14 @@
                 #size-cells = <1>;
                 ranges;
 
-                vica: intc@0x10140000 {
+                vica: intc@10140000 {
                         compatible = "arm,versatile-vic";
                         interrupt-controller;
                         #interrupt-cells = <1>;
                         reg = <0x10140000 0x20>;
                 };
 
-                vicb: intc@0x10140020 {
+                vicb: intc@10140020 {
                         compatible = "arm,versatile-vic";
                         interrupt-controller;
                         #interrupt-cells = <1>;
diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts
index f0b39f835914..97d5d21b7db7 100644
--- a/arch/arm/boot/dts/ste-snowball.dts
+++ b/arch/arm/boot/dts/ste-snowball.dts
@@ -11,6 +11,7 @@
 
 /dts-v1/;
 #include "ste-dbx5x0.dtsi"
+#include "ste-href-family-pinctrl.dtsi"
 
 / {
         model = "Calao Systems Snowball platform with device tree";
@@ -75,6 +76,8 @@
 
         leds {
                 compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&gpioled_snowball_mode>;
                 used-led {
                         label = "user_led";
                         gpios = <&gpio4 14 0x4>;
@@ -84,6 +87,11 @@
         };
 
         soc {
+                usb_per5@a03e0000 {
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&musb_default_mode>;
+                        pinctrl-1 = <&musb_sleep_mode>;
+                };
 
                 sound {
                         compatible = "stericsson,snd-soc-mop500";
@@ -92,7 +100,21 @@
                         stericsson,audio-codec = <&codec>;
                 };
 
+                msp0: msp@80123000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&msp0_default_mode>;
+                        status = "okay";
+                };
+
                 msp1: msp@80124000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&msp1_default_mode>;
+                        status = "okay";
+                };
+
+                msp2: msp@80117000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&msp2_default_mode>;
                         status = "okay";
                 };
 
@@ -110,6 +132,8 @@
                                 interrupt-parent = <&gpio4>;
                                 vdd33a-supply = <&en_3v3_reg>;
                                 vddvario-supply = <&db8500_vape_reg>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&eth_snowball_mode>;
 
                                 reg-shift = <1>;
                                 reg-io-width = <2>;
@@ -122,10 +146,8 @@
                 };
 
                 vmmci: regulator-gpio {
-                        gpios = <&gpio6 25 0x4>;
-                        enable-gpio = <&gpio7 4 0x4>;
-
-                        status = "okay";
+                        gpios = <&gpio7 4 0x4>;
+                        enable-gpio = <&gpio6 25 0x4>;
                 };
 
                 // External Micro SD slot
@@ -136,6 +158,9 @@
                         mmc-cap-mmc-highspeed;
                         vmmc-supply = <&ab8500_ldo_aux3_reg>;
                         vqmmc-supply = <&vmmci>;
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&sdi0_default_mode>;
+                        pinctrl-1 = <&sdi0_sleep_mode>;
 
                         cd-gpios  = <&gpio6 26 0x4>; // 218
                         cd-inverted;
@@ -143,6 +168,27 @@
                         status = "okay";
                 };
 
+                // WLAN SDIO channel
+                sdi1_per2@80118000 {
+                        arm,primecell-periphid = <0x10480180>;
+                        max-frequency = <100000000>;
+                        bus-width = <4>;
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&sdi1_default_mode>;
+                        pinctrl-1 = <&sdi1_sleep_mode>;
+
+                        status = "okay";
+                };
+
+                // Unused PoP eMMC - register and put it to sleep by default */
+                sdi2_per3@80005000 {
+                        arm,primecell-periphid = <0x10480180>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&sdi2_sleep_mode>;
+
+                        status = "okay";
+                };
+
                 // On-board eMMC
                 sdi4_per2@80114000 {
                         arm,primecell-periphid = <0x10480180>;
@@ -150,22 +196,63 @@
                         bus-width = <8>;
                         mmc-cap-mmc-highspeed;
                         vmmc-supply = <&ab8500_ldo_aux2_reg>;
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&sdi4_default_mode>;
+                        pinctrl-1 = <&sdi4_sleep_mode>;
 
                         status = "okay";
                 };
 
                 uart@80120000 {
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&uart0_default_mode>;
+                        pinctrl-1 = <&uart0_sleep_mode>;
                         status = "okay";
                 };
 
                 uart@80121000 {
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&uart1_default_mode>;
+                        pinctrl-1 = <&uart1_sleep_mode>;
                         status = "okay";
                 };
 
                 uart@80007000 {
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&uart2_default_mode>;
+                        pinctrl-1 = <&uart2_sleep_mode>;
                         status = "okay";
                 };
 
+                i2c@80004000 {
+                        pinctrl-names = "default","sleep";
+                        pinctrl-0 = <&i2c0_default_mode>;
+                        pinctrl-1 = <&i2c0_sleep_mode>;
+                };
+
+                i2c@80122000 {
+                        pinctrl-names = "default","sleep";
+                        pinctrl-0 = <&i2c1_default_mode>;
+                        pinctrl-1 = <&i2c1_sleep_mode>;
+                };
+
+                i2c@80128000 {
+                        pinctrl-names = "default","sleep";
+                        pinctrl-0 = <&i2c2_default_mode>;
+                        pinctrl-1 = <&i2c2_sleep_mode>;
+                };
+
+                i2c@80110000 {
+                        pinctrl-names = "default","sleep";
+                        pinctrl-0 = <&i2c3_default_mode>;
+                        pinctrl-1 = <&i2c3_sleep_mode>;
+                };
+
+                ssp@80002000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&ssp0_snowball_mode>;
+                };
+
                 cpufreq-cooling {
                         status = "okay";
                 };
@@ -266,5 +353,141 @@
                                 };
                         };
                 };
+
+                pinctrl {
+                        /*
+                         * Set this up using hogs, as time goes by and as seems fit, these
+                         * can be moved over to being controlled by respective device.
+                         */
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&accel_snowball_mode>,
+                                  <&magneto_snowball_mode>,
+                                  <&gbf_snowball_mode>,
+                                  <&wlan_snowball_mode>;
+
+                        ethernet {
+                                /*
+                                 * Mux in "SM" which is used for the
+                                 * SMSC911x Ethernet adapter
+                                 */
+                                eth_snowball_mode: eth_snowball {
+                                        snowball_mux {
+                                                ste,function = "sm";
+                                                ste,pins = "sm_b_1";
+                                        };
+                                        /* LAN IRQ pin */
+                                        snowball_cfg1 {
+                                                ste,pins = "GPIO140_B11";
+                                                ste,config = <&in_nopull>;
+                                        };
+                                        /* LAN reset pin */
+                                        snowball_cfg2 {
+                                                ste,pins = "GPIO141_C12";
+                                                ste,config = <&gpio_out_hi>;
+                                        };
+
+                                };
+                        };
+                        sdi0 {
+                                sdi0_default_mode: sdi0_default {
+                                        snowball_mux {
+                                                ste,function = "mc0";
+                                                ste,pins = "mc0dat31dir_a_1";
+                                        };
+                                        snowball_cfg1 {
+                                                ste,pins = "GPIO21_AB3"; /* DAT31DIR */
+                                                ste,config = <&out_hi>;
+                                        };
+
+                                };
+                        };
+                        ssp0 {
+                                ssp0_snowball_mode: ssp0_snowball_default {
+                                        snowball_mux {
+                                                ste,function = "ssp0";
+                                                ste,pins = "ssp0_a_1";
+                                        };
+                                        snowball_cfg1 {
+                                                ste,pins = "GPIO144_B13"; /* FRM */
+                                                ste,config = <&gpio_out_hi>;
+                                        };
+                                        snowball_cfg2 {
+                                                ste,pins = "GPIO145_C13"; /* RXD */
+                                                ste,config = <&in_pd>;
+                                        };
+                                        snowball_cfg3 {
+                                                ste,pins =
+                                                "GPIO146_D13", /* TXD */
+                                                "GPIO143_D12"; /* CLK */
+                                                ste,config = <&out_lo>;
+                                        };
+
+                                };
+                        };
+                        gpio_led {
+                                gpioled_snowball_mode: gpioled_default {
+                                        snowball_cfg1 {
+                                                ste,pins = "GPIO142_C11";
+                                                ste,config = <&gpio_out_hi>;
+                                        };
+
+                                };
+                        };
+                        accelerometer {
+                                accel_snowball_mode: accel_snowball {
+                                        /* Accelerometer lines */
+                                        snowball_cfg1 {
+                                                ste,pins =
+                                                "GPIO163_C20", /* ACCEL_IRQ1 */
+                                                "GPIO164_B21"; /* ACCEL_IRQ2 */
+                                                ste,config = <&gpio_in_pu>;
+                                        };
+                                };
+                        };
+                        magnetometer {
+                                magneto_snowball_mode: magneto_snowball {
+                                        snowball_cfg1 {
+                                                ste,pins = "GPIO165_C21"; /* MAG_DRDY */
+                                                ste,config = <&gpio_in_pu>;
+                                        };
+                                };
+                        };
+                        gbf {
+                                gbf_snowball_mode: gbf_snowball {
+                                        /*
+                                         * GBF (GPS, Bluetooth, FM-radio) interface,
+                                         * pull low to reset state
+                                         */
+                                        snowball_cfg1 {
+                                                ste,pins = "GPIO171_D23"; /* GBF_ENA_RESET */
+                                                ste,config = <&gpio_out_lo>;
+                                        };
+                                 };
+                        };
+                        wlan {
+                                wlan_snowball_mode: wlan_snowball {
+                                        /*
+                                         * Activate this mode with the WLAN chip.
+                                         * These are plain GPIO pins used by WLAN
+                                         */
+                                        snowball_cfg1 {
+                                                ste,pins =
+                                                "GPIO161_D21", /* WLAN_PMU_EN */
+                                                "GPIO215_AH13"; /* WLAN_ENA */
+                                                ste,config = <&gpio_out_lo>;
+                                        };
+                                        snowball_cfg2 {
+                                                ste,pins = "GPIO216_AG12"; /* WLAN_IRQ */
+                                                ste,config = <&gpio_in_pu>;
+                                        };
+                                };
+                        };
+                };
+
+                mcde@a0350000 {
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&lcd_default_mode>;
+                        pinctrl-1 = <&lcd_sleep_mode>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi
index 1d322b24d1e4..e56449d41481 100644
--- a/arch/arm/boot/dts/stih415-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi
@@ -86,6 +86,24 @@
                                         };
                                 };
                         };
+
+                        sbc_i2c0 {
+                                pinctrl_sbc_i2c0_default: sbc_i2c0-default {
+                                        st,pins {
+                                                sda = <&PIO4 6 ALT1 BIDIR>;
+                                                scl = <&PIO4 5 ALT1 BIDIR>;
+                                        };
+                                };
+                        };
+
+                        sbc_i2c1 {
+                                pinctrl_sbc_i2c1_default: sbc_i2c1-default {
+                                        st,pins {
+                                                sda = <&PIO3 2 ALT2 BIDIR>;
+                                                scl = <&PIO3 1 ALT2 BIDIR>;
+                                        };
+                                };
+                        };
                 };
 
                 pin-controller-front {
@@ -143,6 +161,24 @@
                                 reg             = <0x7000 0x100>;
                                 st,bank-name    = "PIO12";
                         };
+
+                        i2c0 {
+                                pinctrl_i2c0_default: i2c0-default {
+                                        st,pins {
+                                                sda = <&PIO9 3 ALT1 BIDIR>;
+                                                scl = <&PIO9 2 ALT1 BIDIR>;
+                                        };
+                                };
+                        };
+
+                        i2c1 {
+                                pinctrl_i2c1_default: i2c1-default {
+                                        st,pins {
+                                                sda = <&PIO12 1 ALT1 BIDIR>;
+                                                scl = <&PIO12 0 ALT1 BIDIR>;
+                                        };
+                                };
+                        };
                 };
 
                 pin-controller-rear {
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
index 74ab8ded4b49..d9c7dd1d95a4 100644
--- a/arch/arm/boot/dts/stih415.dtsi
+++ b/arch/arm/boot/dts/stih415.dtsi
@@ -9,6 +9,7 @@
 #include "stih41x.dtsi"
 #include "stih415-clock.dtsi"
 #include "stih415-pinctrl.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 / {
 
         L2: cache-controller {
@@ -83,5 +84,57 @@
                         pinctrl-names   = "default";
                         pinctrl-0       = <&pinctrl_sbc_serial1>;
                 };
+
+                i2c@fed40000 {
+                        compatible      = "st,comms-ssc4-i2c";
+                        reg             = <0xfed40000 0x110>;
+                        interrupts      = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks          = <&CLKS_ICN_REG_0>;
+                        clock-names     = "ssc";
+                        clock-frequency = <400000>;
+                        pinctrl-names   = "default";
+                        pinctrl-0       = <&pinctrl_i2c0_default>;
+
+                        status          = "disabled";
+                };
+
+                i2c@fed41000 {
+                        compatible      = "st,comms-ssc4-i2c";
+                        reg             = <0xfed41000 0x110>;
+                        interrupts      = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks          = <&CLKS_ICN_REG_0>;
+                        clock-names     = "ssc";
+                        clock-frequency = <400000>;
+                        pinctrl-names   = "default";
+                        pinctrl-0       = <&pinctrl_i2c1_default>;
+
+                        status          = "disabled";
+                };
+
+                i2c@fe540000 {
+                        compatible      = "st,comms-ssc4-i2c";
+                        reg             = <0xfe540000 0x110>;
+                        interrupts      = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks          = <&CLK_SYSIN>;
+                        clock-names     = "ssc";
+                        clock-frequency = <400000>;
+                        pinctrl-names   = "default";
+                        pinctrl-0       = <&pinctrl_sbc_i2c0_default>;
+
+                        status          = "disabled";
+                };
+
+                i2c@fe541000 {
+                        compatible      = "st,comms-ssc4-i2c";
+                        reg             = <0xfe541000 0x110>;
+                        interrupts      = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks          = <&CLK_SYSIN>;
+                        clock-names     = "ssc";
+                        clock-frequency = <400000>;
+                        pinctrl-names   = "default";
+                        pinctrl-0       = <&pinctrl_sbc_i2c1_default>;
+
+                        status          = "disabled";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi
index 0f246c979262..b29ff4ba542c 100644
--- a/arch/arm/boot/dts/stih416-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi
@@ -97,6 +97,24 @@
                                         };
                                 };
                         };
+
+                        sbc_i2c0 {
+                                pinctrl_sbc_i2c0_default: sbc_i2c0-default {
+                                        st,pins {
+                                                sda = <&PIO4 6 ALT1 BIDIR>;
+                                                scl = <&PIO4 5 ALT1 BIDIR>;
+                                        };
+                                };
+                        };
+
+                        sbc_i2c1 {
+                                pinctrl_sbc_i2c1_default: sbc_i2c1-default {
+                                        st,pins {
+                                                sda = <&PIO3 2 ALT2 BIDIR>;
+                                                scl = <&PIO3 1 ALT2 BIDIR>;
+                                        };
+                                };
+                        };
                 };
 
                 pin-controller-front {
@@ -175,6 +193,23 @@
                                 };
                         };
 
+                        i2c0 {
+                                pinctrl_i2c0_default: i2c0-default {
+                                        st,pins {
+                                                sda = <&PIO9 3 ALT1 BIDIR>;
+                                                scl = <&PIO9 2 ALT1 BIDIR>;
+                                        };
+                                };
+                        };
+
+                        i2c1 {
+                                pinctrl_i2c1_default: i2c1-default {
+                                        st,pins {
+                                                sda = <&PIO12 1 ALT1 BIDIR>;
+                                                scl = <&PIO12 0 ALT1 BIDIR>;
+                                        };
+                                };
+                        };
                 };
 
                 pin-controller-rear {
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index 1a0326ea7d07..b7ab47b95816 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -9,6 +9,7 @@
 #include "stih41x.dtsi"
 #include "stih416-clock.dtsi"
 #include "stih416-pinctrl.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 / {
         L2: cache-controller {
                 compatible = "arm,pl310-cache";
@@ -92,5 +93,57 @@
                         pinctrl-0       = <&pinctrl_sbc_serial1>;
                         clocks          = <&CLK_SYSIN>;
                 };
+
+                i2c@fed40000 {
+                        compatible      = "st,comms-ssc4-i2c";
+                        reg             = <0xfed40000 0x110>;
+                        interrupts      = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks          = <&CLK_S_ICN_REG_0>;
+                        clock-names     = "ssc";
+                        clock-frequency = <400000>;
+                        pinctrl-names   = "default";
+                        pinctrl-0       = <&pinctrl_i2c0_default>;
+
+                        status          = "disabled";
+                };
+
+                i2c@fed41000 {
+                        compatible      = "st,comms-ssc4-i2c";
+                        reg             = <0xfed41000 0x110>;
+                        interrupts      = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks          = <&CLK_S_ICN_REG_0>;
+                        clock-names     = "ssc";
+                        clock-frequency = <400000>;
+                        pinctrl-names   = "default";
+                        pinctrl-0       = <&pinctrl_i2c1_default>;
+
+                        status          = "disabled";
+                };
+
+                i2c@fe540000 {
+                        compatible      = "st,comms-ssc4-i2c";
+                        reg             = <0xfe540000 0x110>;
+                        interrupts      = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks          = <&CLK_SYSIN>;
+                        clock-names     = "ssc";
+                        clock-frequency = <400000>;
+                        pinctrl-names   = "default";
+                        pinctrl-0       = <&pinctrl_sbc_i2c0_default>;
+
+                        status          = "disabled";
+                };
+
+                i2c@fe541000 {
+                        compatible      = "st,comms-ssc4-i2c";
+                        reg             = <0xfe541000 0x110>;
+                        interrupts      = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks          = <&CLK_SYSIN>;
+                        clock-names     = "ssc";
+                        clock-frequency = <400000>;
+                        pinctrl-names   = "default";
+                        pinctrl-0       = <&pinctrl_sbc_i2c1_default>;
+
+                        status          = "disabled";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/stih41x-b2000.dtsi b/arch/arm/boot/dts/stih41x-b2000.dtsi
index 8e694d2b8f5b..1e6aa92772f5 100644
--- a/arch/arm/boot/dts/stih41x-b2000.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2000.dtsi
@@ -37,5 +37,14 @@
                         };
                 };
 
+                /* HDMI Tx I2C */
+                i2c@fed41000 {
+                        /* HDMI V1.3a supports Standard mode only */
+                        clock-frequency = <100000>;
+                        i2c-min-scl-pulse-width-us = <0>;
+                        i2c-min-sda-pulse-width-us = <5>;
+
+                        status = "okay";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi
index 133e18143b1b..0ef0a69df8ea 100644
--- a/arch/arm/boot/dts/stih41x-b2020.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2020.dtsi
@@ -38,5 +38,27 @@
                                 default-state = "off";
                         };
                 };
+
+                i2c@fed40000 {
+                        status = "okay";
+                };
+
+                /* HDMI Tx I2C */
+                i2c@fed41000 {
+                        /* HDMI V1.3a supports Standard mode only */
+                        clock-frequency = <100000>;
+                        i2c-min-scl-pulse-width-us = <0>;
+                        i2c-min-sda-pulse-width-us = <5>;
+
+                        status = "okay";
+                };
+
+                i2c@fe540000 {
+                        status = "okay";
+                };
+
+                i2c@fe541000 {
+                        status = "okay";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts
index eb4d73b6a090..d4b081d6a167 100644
--- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
@@ -18,10 +18,6 @@
         model = "Mele A1000";
         compatible = "mele,a1000", "allwinner,sun4i-a10";
 
-        aliases {
-                serial0 = &uart0;
-        };
-
         soc@01c00000 {
                 emac: ethernet@01c0b000 {
                         pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index 425a7db898c5..b139ee6bcf99 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -17,15 +17,6 @@
         model = "Cubietech Cubieboard";
         compatible = "cubietech,a10-cubieboard", "allwinner,sun4i-a10";
 
-        aliases {
-                serial0 = &uart0;
-                serial1 = &uart1;
-        };
-
-        chosen {
-                bootargs = "earlyprintk console=ttyS0,115200";
-        };
-
         soc@01c00000 {
                 emac: ethernet@01c0b000 {
                         pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
index b3ae51fa9372..3a1595f67823 100644
--- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
+++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
@@ -18,10 +18,6 @@
         model = "Miniand Hackberry";
         compatible = "miniand,hackberry", "allwinner,sun4i-a10";
 
-        chosen {
-                bootargs = "earlyprintk console=ttyS0,115200";
-        };
-
         soc@01c00000 {
                 emac: ethernet@01c0b000 {
                         pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
index 0c1447c68059..70b3323caf1a 100644
--- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
+++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
@@ -18,10 +18,6 @@
         model = "PineRiver Mini X-Plus";
         compatible = "pineriver,mini-xplus", "allwinner,sun4i-a10";
 
-        chosen {
-                bootargs = "earlyprintk console=ttyS0,115200";
-        };
-
         soc@01c00000 {
                 uart0: serial@01c28000 {
                         pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 319cc6b509da..040bb0eba152 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -15,6 +15,12 @@
 / {
         interrupt-parent = <&intc>;
 
+        aliases {
+                ethernet0 = &emac;
+                serial0 = &uart0;
+                serial1 = &uart1;
+        };
+
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -66,6 +72,29 @@
                         clocks = <&osc24M>;
                 };
 
+                pll4: pll4@01c20018 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-pll1-clk";
+                        reg = <0x01c20018 0x4>;
+                        clocks = <&osc24M>;
+                };
+
+                pll5: pll5@01c20020 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-pll5-clk";
+                        reg = <0x01c20020 0x4>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "pll5_ddr", "pll5_other";
+                };
+
+                pll6: pll6@01c20028 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-pll6-clk";
+                        reg = <0x01c20028 0x4>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "pll6_sata", "pll6_other", "pll6";
+                };
+
                 /* dummy is 200M */
                 cpu: cpu@01c20054 {
                         #clock-cells = <0>;
@@ -131,12 +160,11 @@
                                 "apb0_ir1", "apb0_keypad";
                 };
 
-                /* dummy is pll62 */
                 apb1_mux: apb1_mux@01c20058 {
                         #clock-cells = <0>;
                         compatible = "allwinner,sun4i-apb1-mux-clk";
                         reg = <0x01c20058 0x4>;
-                        clocks = <&osc24M>, <&dummy>, <&osc32k>;
+                        clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
                 };
 
                 apb1: apb1@01c20058 {
@@ -158,6 +186,126 @@
                                 "apb1_uart4", "apb1_uart5", "apb1_uart6",
                                 "apb1_uart7";
                 };
+
+                nand_clk: clk@01c20080 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20080 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "nand";
+                };
+
+                ms_clk: clk@01c20084 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20084 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ms";
+                };
+
+                mmc0_clk: clk@01c20088 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20088 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc0";
+                };
+
+                mmc1_clk: clk@01c2008c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c2008c 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc1";
+                };
+
+                mmc2_clk: clk@01c20090 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20090 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc2";
+                };
+
+                mmc3_clk: clk@01c20094 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20094 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc3";
+                };
+
+                ts_clk: clk@01c20098 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20098 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ts";
+                };
+
+                ss_clk: clk@01c2009c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c2009c 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ss";
+                };
+
+                spi0_clk: clk@01c200a0 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a0 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi0";
+                };
+
+                spi1_clk: clk@01c200a4 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a4 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi1";
+                };
+
+                spi2_clk: clk@01c200a8 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a8 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi2";
+                };
+
+                pata_clk: clk@01c200ac {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200ac 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "pata";
+                };
+
+                ir0_clk: clk@01c200b0 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200b0 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ir0";
+                };
+
+                ir1_clk: clk@01c200b4 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200b4 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ir1";
+                };
+
+                spi3_clk: clk@01c200d4 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200d4 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi3";
+                };
         };
 
         soc@01c00000 {
@@ -266,11 +414,23 @@
                         reg = <0x01c20c90 0x10>;
                 };
 
+                rtc: rtc@01c20d00 {
+                        compatible = "allwinner,sun4i-rtc";
+                        reg = <0x01c20d00 0x20>;
+                        interrupts = <24>;
+                };
+
                 sid: eeprom@01c23800 {
                         compatible = "allwinner,sun4i-sid";
                         reg = <0x01c23800 0x10>;
                 };
 
+                rtp: rtp@01c25000 {
+                        compatible = "allwinner,sun4i-ts";
+                        reg = <0x01c25000 0x100>;
+                        interrupts = <29>;
+                };
+
                 uart0: serial@01c28000 {
                         compatible = "snps,dw-apb-uart";
                         reg = <0x01c28000 0x400>;
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index e674c94c7206..ea16054857a4 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -16,6 +16,10 @@
 / {
         interrupt-parent = <&intc>;
 
+        aliases {
+                ethernet0 = &emac;
+        };
+
         cpus {
                 cpu@0 {
                         compatible = "arm,cortex-a8";
@@ -63,6 +67,29 @@
                         clocks = <&osc24M>;
                 };
 
+                pll4: pll4@01c20018 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-pll1-clk";
+                        reg = <0x01c20018 0x4>;
+                        clocks = <&osc24M>;
+                };
+
+                pll5: pll5@01c20020 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-pll5-clk";
+                        reg = <0x01c20020 0x4>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "pll5_ddr", "pll5_other";
+                };
+
+                pll6: pll6@01c20028 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-pll6-clk";
+                        reg = <0x01c20028 0x4>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "pll6_sata", "pll6_other", "pll6";
+                };
+
                 /* dummy is 200M */
                 cpu: cpu@01c20054 {
                         #clock-cells = <0>;
@@ -123,12 +150,11 @@
                                 "apb0_ir", "apb0_keypad";
                 };
 
-                /* dummy is pll62 */
                 apb1_mux: apb1_mux@01c20058 {
                         #clock-cells = <0>;
                         compatible = "allwinner,sun4i-apb1-mux-clk";
                         reg = <0x01c20058 0x4>;
-                        clocks = <&osc24M>, <&dummy>, <&osc32k>;
+                        clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
                 };
 
                 apb1: apb1@01c20058 {
@@ -147,6 +173,102 @@
                                 "apb1_i2c2", "apb1_uart0", "apb1_uart1",
                                 "apb1_uart2", "apb1_uart3";
                 };
+
+                nand_clk: clk@01c20080 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20080 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "nand";
+                };
+
+                ms_clk: clk@01c20084 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20084 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ms";
+                };
+
+                mmc0_clk: clk@01c20088 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20088 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc0";
+                };
+
+                mmc1_clk: clk@01c2008c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c2008c 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc1";
+                };
+
+                mmc2_clk: clk@01c20090 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20090 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc2";
+                };
+
+                ts_clk: clk@01c20098 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20098 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ts";
+                };
+
+                ss_clk: clk@01c2009c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c2009c 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ss";
+                };
+
+                spi0_clk: clk@01c200a0 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a0 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi0";
+                };
+
+                spi1_clk: clk@01c200a4 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a4 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi1";
+                };
+
+                spi2_clk: clk@01c200a8 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a8 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi2";
+                };
+
+                ir0_clk: clk@01c200b0 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200b0 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ir0";
+                };
+
+                mbus_clk: clk@01c2015c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c2015c 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mbus";
+                };
         };
 
         soc@01c00000 {
@@ -260,6 +382,12 @@
                         reg = <0x01c23800 0x10>;
                 };
 
+                rtp: rtp@01c25000 {
+                        compatible = "allwinner,sun4i-ts";
+                        reg = <0x01c25000 0x100>;
+                        interrupts = <29>;
+                };
+
                 uart0: serial@01c28000 {
                         compatible = "snps,dw-apb-uart";
                         reg = <0x01c28000 0x400>;
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
new file mode 100644
index 000000000000..fe2ce0acdb06
--- /dev/null
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
@@ -0,0 +1,68 @@
+/*
+ * Copyright 2012 Maxime Ripard
+ * Copyright 2013 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "sun5i-a13.dtsi"
+
+/ {
+        model = "Olimex A13-Olinuxino Micro";
+        compatible = "olimex,a13-olinuxino-micro", "allwinner,sun5i-a13";
+
+        soc@01c00000 {
+                pinctrl@01c20800 {
+                        led_pins_olinuxinom: led_pins@0 {
+                                allwinner,pins = "PG9";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <1>;
+                                allwinner,pull = <0>;
+                        };
+                };
+
+                uart1: serial@01c28400 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart1_pins_b>;
+                        status = "okay";
+                };
+
+                i2c0: i2c@01c2ac00 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_pins_a>;
+                        status = "okay";
+                };
+
+                i2c1: i2c@01c2b000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c1_pins_a>;
+                        status = "okay";
+                };
+
+                i2c2: i2c@01c2b400 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c2_pins_a>;
+                        status = "okay";
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins_olinuxinom>;
+
+                power {
+                        label = "a13-olinuxino-micro:green:power";
+                        gpios = <&pio 6 9 0>;
+                        default-state = "on";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index 9e508dcc4245..a4ba5ff010cf 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -18,10 +18,6 @@
         model = "Olimex A13-Olinuxino";
         compatible = "olimex,a13-olinuxino", "allwinner,sun5i-a13";
 
-        chosen {
-                bootargs = "earlyprintk console=ttyS0,115200";
-        };
-
         soc@01c00000 {
                 pinctrl@01c20800 {
                         led_pins_olinuxino: led_pins@0 {
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 1ccd75d37f49..320335abfccd 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -67,6 +67,29 @@
                         clocks = <&osc24M>;
                 };
 
+                pll4: pll4@01c20018 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-pll1-clk";
+                        reg = <0x01c20018 0x4>;
+                        clocks = <&osc24M>;
+                };
+
+                pll5: pll5@01c20020 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-pll5-clk";
+                        reg = <0x01c20020 0x4>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "pll5_ddr", "pll5_other";
+                };
+
+                pll6: pll6@01c20028 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-pll6-clk";
+                        reg = <0x01c20028 0x4>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "pll6_sata", "pll6_other", "pll6";
+                };
+
                 /* dummy is 200M */
                 cpu: cpu@01c20054 {
                         #clock-cells = <0>;
@@ -125,12 +148,11 @@
                         clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
                 };
 
-                /* dummy is pll6 */
                 apb1_mux: apb1_mux@01c20058 {
                         #clock-cells = <0>;
                         compatible = "allwinner,sun4i-apb1-mux-clk";
                         reg = <0x01c20058 0x4>;
-                        clocks = <&osc24M>, <&dummy>, <&osc32k>;
+                        clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
                 };
 
                 apb1: apb1@01c20058 {
@@ -148,6 +170,102 @@
                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
                                 "apb1_i2c2", "apb1_uart1", "apb1_uart3";
                 };
+
+                nand_clk: clk@01c20080 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20080 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "nand";
+                };
+
+                ms_clk: clk@01c20084 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20084 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ms";
+                };
+
+                mmc0_clk: clk@01c20088 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20088 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc0";
+                };
+
+                mmc1_clk: clk@01c2008c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c2008c 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc1";
+                };
+
+                mmc2_clk: clk@01c20090 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20090 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc2";
+                };
+
+                ts_clk: clk@01c20098 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20098 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ts";
+                };
+
+                ss_clk: clk@01c2009c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c2009c 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ss";
+                };
+
+                spi0_clk: clk@01c200a0 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a0 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi0";
+                };
+
+                spi1_clk: clk@01c200a4 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a4 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi1";
+                };
+
+                spi2_clk: clk@01c200a8 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a8 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi2";
+                };
+
+                ir0_clk: clk@01c200b0 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200b0 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ir0";
+                };
+
+                mbus_clk: clk@01c2015c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c2015c 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mbus";
+                };
         };
 
         soc@01c00000 {
@@ -227,6 +345,12 @@
                         reg = <0x01c23800 0x10>;
                 };
 
+                rtp: rtp@01c25000 {
+                        compatible = "allwinner,sun4i-ts";
+                        reg = <0x01c25000 0x100>;
+                        interrupts = <29>;
+                };
+
                 uart1: serial@01c28400 {
                         compatible = "snps,dw-apb-uart";
                         reg = <0x01c28400 0x400>;
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 7f5878c2784a..5256ad9be52c 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -212,6 +212,24 @@
                         };
                 };
 
+                ahb1_rst: reset@01c202c0 {
+                        #reset-cells = <1>;
+                        compatible = "allwinner,sun6i-a31-ahb1-reset";
+                        reg = <0x01c202c0 0xc>;
+                };
+
+                apb1_rst: reset@01c202d0 {
+                        #reset-cells = <1>;
+                        compatible = "allwinner,sun6i-a31-clock-reset";
+                        reg = <0x01c202d0 0x4>;
+                };
+
+                apb2_rst: reset@01c202d8 {
+                        #reset-cells = <1>;
+                        compatible = "allwinner,sun6i-a31-clock-reset";
+                        reg = <0x01c202d8 0x4>;
+                };
+
                 timer@01c20c00 {
                         compatible = "allwinner,sun4i-timer";
                         reg = <0x01c20c00 0xa0>;
@@ -235,6 +253,7 @@
                         reg-shift = <2>;
                         reg-io-width = <4>;
                         clocks = <&apb2_gates 16>;
+                        resets = <&apb2_rst 16>;
                         status = "disabled";
                 };
 
@@ -245,6 +264,7 @@
                         reg-shift = <2>;
                         reg-io-width = <4>;
                         clocks = <&apb2_gates 17>;
+                        resets = <&apb2_rst 17>;
                         status = "disabled";
                 };
 
@@ -255,6 +275,7 @@
                         reg-shift = <2>;
                         reg-io-width = <4>;
                         clocks = <&apb2_gates 18>;
+                        resets = <&apb2_rst 18>;
                         status = "disabled";
                 };
 
@@ -265,6 +286,7 @@
                         reg-shift = <2>;
                         reg-io-width = <4>;
                         clocks = <&apb2_gates 19>;
+                        resets = <&apb2_rst 19>;
                         status = "disabled";
                 };
 
@@ -275,6 +297,7 @@
                         reg-shift = <2>;
                         reg-io-width = <4>;
                         clocks = <&apb2_gates 20>;
+                        resets = <&apb2_rst 20>;
                         status = "disabled";
                 };
 
@@ -285,6 +308,7 @@
                         reg-shift = <2>;
                         reg-io-width = <4>;
                         clocks = <&apb2_gates 21>;
+                        resets = <&apb2_rst 21>;
                         status = "disabled";
                 };
 
@@ -298,5 +322,15 @@
                         #interrupt-cells = <3>;
                         interrupts = <1 9 0xf04>;
                 };
+
+                cpucfg@01f01c00 {
+                        compatible = "allwinner,sun6i-a31-cpuconfig";
+                        reg = <0x01f01c00 0x300>;
+                };
+
+                prcm@01f01c00 {
+                        compatible = "allwinner,sun6i-a31-prcm";
+                        reg = <0x01f01400 0x200>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index 8a1009d6c829..f9dcb61a5305 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
@@ -33,6 +33,24 @@
                         pinctrl-0 = <&uart0_pins_a>;
                         status = "okay";
                 };
+
+                i2c0: i2c@01c2ac00 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_pins_a>;
+                        status = "okay";
+                };
+
+                i2c1: i2c@01c2b000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c1_pins_a>;
+                        status = "okay";
+                };
+
+                i2c2: i2c@01c2b400 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c2_pins_a>;
+                        status = "okay";
+                };
         };
 
         leds {
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 0135039eff96..119f066f0d98 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -16,6 +16,10 @@
 / {
         interrupt-parent = <&gic>;
 
+        aliases {
+                ethernet0 = &emac;
+        };
+
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -49,10 +53,11 @@
                         clock-frequency = <24000000>;
                 };
 
-                osc32k: osc32k {
+                osc32k: clk@0 {
                         #clock-cells = <0>;
                         compatible = "fixed-clock";
                         clock-frequency = <32768>;
+                        clock-output-names = "osc32k";
                 };
 
                 pll1: pll1@01c20000 {
@@ -62,23 +67,34 @@
                         clocks = <&osc24M>;
                 };
 
-                /*
-                 * This is a dummy clock, to be used as placeholder on
-                 * other mux clocks when a specific parent clock is not
-                 * yet implemented. It should be dropped when the driver
-                 * is complete.
-                 */
-                pll6: pll6 {
+                pll4: pll4@01c20018 {
                         #clock-cells = <0>;
-                        compatible = "fixed-clock";
-                        clock-frequency = <0>;
+                        compatible = "allwinner,sun4i-pll1-clk";
+                        reg = <0x01c20018 0x4>;
+                        clocks = <&osc24M>;
+                };
+
+                pll5: pll5@01c20020 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-pll5-clk";
+                        reg = <0x01c20020 0x4>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "pll5_ddr", "pll5_other";
+                };
+
+                pll6: pll6@01c20028 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-pll6-clk";
+                        reg = <0x01c20028 0x4>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "pll6_sata", "pll6_other", "pll6";
                 };
 
                 cpu: cpu@01c20054 {
                         #clock-cells = <0>;
                         compatible = "allwinner,sun4i-cpu-clk";
                         reg = <0x01c20054 0x4>;
-                        clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6>;
+                        clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
                 };
 
                 axi: axi@01c20054 {
@@ -137,7 +153,7 @@
                         #clock-cells = <0>;
                         compatible = "allwinner,sun4i-apb1-mux-clk";
                         reg = <0x01c20058 0x4>;
-                        clocks = <&osc24M>, <&pll6>, <&osc32k>;
+                        clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
                 };
 
                 apb1: apb1@01c20058 {
@@ -159,6 +175,162 @@
                                 "apb1_uart2", "apb1_uart3", "apb1_uart4",
                                 "apb1_uart5", "apb1_uart6", "apb1_uart7";
                 };
+
+                nand_clk: clk@01c20080 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20080 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "nand";
+                };
+
+                ms_clk: clk@01c20084 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20084 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ms";
+                };
+
+                mmc0_clk: clk@01c20088 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20088 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc0";
+                };
+
+                mmc1_clk: clk@01c2008c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c2008c 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc1";
+                };
+
+                mmc2_clk: clk@01c20090 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20090 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc2";
+                };
+
+                mmc3_clk: clk@01c20094 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20094 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc3";
+                };
+
+                ts_clk: clk@01c20098 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20098 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ts";
+                };
+
+                ss_clk: clk@01c2009c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c2009c 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ss";
+                };
+
+                spi0_clk: clk@01c200a0 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a0 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi0";
+                };
+
+                spi1_clk: clk@01c200a4 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a4 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi1";
+                };
+
+                spi2_clk: clk@01c200a8 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a8 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi2";
+                };
+
+                pata_clk: clk@01c200ac {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200ac 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "pata";
+                };
+
+                ir0_clk: clk@01c200b0 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200b0 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ir0";
+                };
+
+                ir1_clk: clk@01c200b4 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200b4 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ir1";
+                };
+
+                spi3_clk: clk@01c200d4 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200d4 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi3";
+                };
+
+                mbus_clk: clk@01c2015c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c2015c 0x4>;
+                        clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
+                        clock-output-names = "mbus";
+                };
+
+                /*
+                 * Dummy clock used by output clocks
+                 */
+                osc24M_32k: clk@1 {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <750>;
+                        clock-mult = <1>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "osc24M_32k";
+                };
+
+                clk_out_a: clk@01c201f0 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun7i-a20-out-clk";
+                        reg = <0x01c201f0 0x4>;
+                        clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
+                        clock-output-names = "clk_out_a";
+                };
+
+                clk_out_b: clk@01c201f4 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun7i-a20-out-clk";
+                        reg = <0x01c201f4 0x4>;
+                        clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
+                        clock-output-names = "clk_out_b";
+                };
         };
 
         soc@01c00000 {
@@ -246,6 +418,20 @@
                                 allwinner,drive = <0>;
                                 allwinner,pull = <0>;
                         };
+
+                        clk_out_a_pins_a: clk_out_a@0 {
+                                allwinner,pins = "PI12";
+                                allwinner,function = "clk_out_a";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
+                        clk_out_b_pins_a: clk_out_b@0 {
+                                allwinner,pins = "PI13";
+                                allwinner,function = "clk_out_b";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
                 };
 
                 timer@01c20c00 {
@@ -265,11 +451,23 @@
                         reg = <0x01c20c90 0x10>;
                 };
 
+                rtc: rtc@01c20d00 {
+                        compatible = "allwinner,sun7i-a20-rtc";
+                        reg = <0x01c20d00 0x20>;
+                        interrupts = <0 24 1>;
+                };
+
                 sid: eeprom@01c23800 {
                         compatible = "allwinner,sun7i-a20-sid";
                         reg = <0x01c23800 0x200>;
                 };
 
+                rtp: rtp@01c25000 {
+                        compatible = "allwinner,sun4i-ts";
+                        reg = <0x01c25000 0x100>;
+                        interrupts = <0 29 4>;
+                };
+
                 uart0: serial@01c28000 {
                         compatible = "snps,dw-apb-uart";
                         reg = <0x01c28000 0x400>;
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index cb5ec23b03a7..73aecfb57ccb 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -7,11 +7,42 @@
         model = "NVIDIA Tegra114 Dalmore evaluation board";
         compatible = "nvidia,dalmore", "nvidia,tegra114";
 
+        aliases {
+                rtc0 = "/i2c@7000d000/tps65913@58";
+                rtc1 = "/rtc@7000e000";
+        };
+
         memory {
                 reg = <0x80000000 0x40000000>;
         };
 
-        pinmux {
+        host1x@50000000 {
+                hdmi@54280000 {
+                        status = "okay";
+
+                        vdd-supply = <&vdd_hdmi_reg>;
+                        pll-supply = <&palmas_smps3_reg>;
+
+                        nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+                        nvidia,hpd-gpio =
+                                <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
+                };
+
+                dsi@54300000 {
+                        status = "okay";
+
+                        panel@0 {
+                                compatible = "panasonic,vvx10f004b00",
+                                             "simple-panel";
+                                reg = <0>;
+
+                                power-supply = <&avdd_lcd_reg>;
+                                backlight = <&backlight>;
+                        };
+                };
+        };
+
+        pinmux@70000868 {
                 pinctrl-names = "default";
                 pinctrl-0 = <&state_default>;
 
@@ -19,41 +50,41 @@
                         clk1_out_pw4 {
                                 nvidia,pins = "clk1_out_pw4";
                                 nvidia,function = "extperiph1";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         dap1_din_pn1 {
                                 nvidia,pins = "dap1_din_pn1";
                                 nvidia,function = "i2s0";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         dap1_dout_pn2 {
                                 nvidia,pins = "dap1_dout_pn2",
                                                 "dap1_fs_pn0",
                                                 "dap1_sclk_pn3";
                                 nvidia,function = "i2s0";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         dap2_din_pa4 {
                                 nvidia,pins = "dap2_din_pa4";
                                 nvidia,function = "i2s1";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         dap2_dout_pa5 {
                                 nvidia,pins = "dap2_dout_pa5",
                                                 "dap2_fs_pa2",
                                                 "dap2_sclk_pa3";
                                 nvidia,function = "i2s1";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         dap4_din_pp5 {
                                 nvidia,pins = "dap4_din_pp5",
@@ -61,17 +92,17 @@
                                                 "dap4_fs_pp4",
                                                 "dap4_sclk_pp7";
                                 nvidia,function = "i2s3";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         dvfs_pwm_px0 {
                                 nvidia,pins = "dvfs_pwm_px0",
                                                 "dvfs_clk_px2";
                                 nvidia,function = "cldvfs";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         ulpi_clk_py0 {
                                 nvidia,pins = "ulpi_clk_py0",
@@ -84,128 +115,128 @@
                                                 "ulpi_data6_po7",
                                                 "ulpi_data7_po0";
                                 nvidia,function = "ulpi";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         ulpi_dir_py1 {
                                 nvidia,pins = "ulpi_dir_py1",
                                                 "ulpi_nxt_py2";
                                 nvidia,function = "ulpi";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         ulpi_stp_py3 {
                                 nvidia,pins = "ulpi_stp_py3";
                                 nvidia,function = "ulpi";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         cam_i2c_scl_pbb1 {
                                 nvidia,pins = "cam_i2c_scl_pbb1",
                                                 "cam_i2c_sda_pbb2";
                                 nvidia,function = "i2c3";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
-                                nvidia,lock = <0>;
-                                nvidia,open-drain = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
                         };
                         cam_mclk_pcc0 {
                                 nvidia,pins = "cam_mclk_pcc0",
                                                 "pbb0";
                                 nvidia,function = "vi_alt3";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
-                                nvidia,lock = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
                         };
                         gen2_i2c_scl_pt5 {
                                 nvidia,pins = "gen2_i2c_scl_pt5",
                                                 "gen2_i2c_sda_pt6";
                                 nvidia,function = "i2c2";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
-                                nvidia,lock = <0>;
-                                nvidia,open-drain = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
                         };
                         gmi_a16_pj7 {
                                 nvidia,pins = "gmi_a16_pj7";
                                 nvidia,function = "uartd";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         gmi_a17_pb0 {
                                 nvidia,pins = "gmi_a17_pb0",
                                                 "gmi_a18_pb1";
                                 nvidia,function = "uartd";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         gmi_a19_pk7 {
                                 nvidia,pins = "gmi_a19_pk7";
                                 nvidia,function = "uartd";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         gmi_ad5_pg5 {
                                 nvidia,pins = "gmi_ad5_pg5",
                                                 "gmi_cs6_n_pi3",
                                                 "gmi_wr_n_pi0";
                                 nvidia,function = "spi4";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         gmi_ad6_pg6 {
                                 nvidia,pins = "gmi_ad6_pg6",
                                                 "gmi_ad7_pg7";
                                 nvidia,function = "spi4";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         gmi_ad12_ph4 {
                                 nvidia,pins = "gmi_ad12_ph4";
                                 nvidia,function = "rsvd4";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         gmi_ad9_ph1 {
                                 nvidia,pins = "gmi_ad9_ph1";
                                 nvidia,function = "pwm1";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         gmi_cs1_n_pj2 {
                                 nvidia,pins = "gmi_cs1_n_pj2",
                                                 "gmi_oe_n_pi1";
                                 nvidia,function = "soc";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         clk2_out_pw5 {
                                 nvidia,pins = "clk2_out_pw5";
                                 nvidia,function = "extperiph2";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         sdmmc1_clk_pz0 {
                                 nvidia,pins = "sdmmc1_clk_pz0";
                                 nvidia,function = "sdmmc1";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         sdmmc1_cmd_pz1 {
                                 nvidia,pins = "sdmmc1_cmd_pz1",
@@ -214,23 +245,23 @@
                                                 "sdmmc1_dat2_py5",
                                                 "sdmmc1_dat3_py4";
                                 nvidia,function = "sdmmc1";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         sdmmc1_wp_n_pv3 {
                                 nvidia,pins = "sdmmc1_wp_n_pv3";
                                 nvidia,function = "spi4";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         sdmmc3_clk_pa6 {
                                 nvidia,pins = "sdmmc3_clk_pa6";
                                 nvidia,function = "sdmmc3";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         sdmmc3_cmd_pa7 {
                                 nvidia,pins = "sdmmc3_cmd_pa7",
@@ -242,16 +273,16 @@
                                                 "sdmmc3_clk_lb_out_pee4",
                                                 "sdmmc3_clk_lb_in_pee5";
                                 nvidia,function = "sdmmc3";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         sdmmc4_clk_pcc4 {
                                 nvidia,pins = "sdmmc4_clk_pcc4";
                                 nvidia,function = "sdmmc4";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         sdmmc4_cmd_pt7 {
                                 nvidia,pins = "sdmmc4_cmd_pt7",
@@ -264,16 +295,16 @@
                                                 "sdmmc4_dat6_paa6",
                                                 "sdmmc4_dat7_paa7";
                                 nvidia,function = "sdmmc4";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         clk_32k_out_pa0 {
                                 nvidia,pins = "clk_32k_out_pa0";
                                 nvidia,function = "blink";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         kb_col0_pq0 {
                                 nvidia,pins = "kb_col0_pq0",
@@ -283,265 +314,265 @@
                                                 "kb_row1_pr1",
                                                 "kb_row2_pr2";
                                 nvidia,function = "kbc";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         dap3_din_pp1 {
                                 nvidia,pins = "dap3_din_pp1",
                                                 "dap3_sclk_pp3";
                                 nvidia,function = "displayb";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         pv0 {
                                 nvidia,pins = "pv0";
                                 nvidia,function = "rsvd4";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         kb_row7_pr7 {
                                 nvidia,pins = "kb_row7_pr7";
                                 nvidia,function = "rsvd2";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         kb_row10_ps2 {
                                 nvidia,pins = "kb_row10_ps2";
                                 nvidia,function = "uarta";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         kb_row9_ps1 {
                                 nvidia,pins = "kb_row9_ps1";
                                 nvidia,function = "uarta";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         pwr_i2c_scl_pz6 {
                                 nvidia,pins = "pwr_i2c_scl_pz6",
                                                 "pwr_i2c_sda_pz7";
                                 nvidia,function = "i2cpwr";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
-                                nvidia,lock = <0>;
-                                nvidia,open-drain = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
                         };
                         sys_clk_req_pz5 {
                                 nvidia,pins = "sys_clk_req_pz5";
                                 nvidia,function = "sysclk";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         core_pwr_req {
                                 nvidia,pins = "core_pwr_req";
                                 nvidia,function = "pwron";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         cpu_pwr_req {
                                 nvidia,pins = "cpu_pwr_req";
                                 nvidia,function = "cpu";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         pwr_int_n {
                                 nvidia,pins = "pwr_int_n";
                                 nvidia,function = "pmi";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         reset_out_n {
                                 nvidia,pins = "reset_out_n";
                                 nvidia,function = "reset_out_n";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         clk3_out_pee0 {
                                 nvidia,pins = "clk3_out_pee0";
                                 nvidia,function = "extperiph3";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         gen1_i2c_scl_pc4 {
                                 nvidia,pins = "gen1_i2c_scl_pc4",
                                                 "gen1_i2c_sda_pc5";
                                 nvidia,function = "i2c1";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
-                                nvidia,lock = <0>;
-                                nvidia,open-drain = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
                         };
                         uart2_cts_n_pj5 {
                                 nvidia,pins = "uart2_cts_n_pj5";
                                 nvidia,function = "uartb";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         uart2_rts_n_pj6 {
                                 nvidia,pins = "uart2_rts_n_pj6";
                                 nvidia,function = "uartb";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         uart2_rxd_pc3 {
                                 nvidia,pins = "uart2_rxd_pc3";
                                 nvidia,function = "irda";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         uart2_txd_pc2 {
                                 nvidia,pins = "uart2_txd_pc2";
                                 nvidia,function = "irda";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         uart3_cts_n_pa1 {
                                 nvidia,pins = "uart3_cts_n_pa1",
                                                 "uart3_rxd_pw7";
                                 nvidia,function = "uartc";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         uart3_rts_n_pc0 {
                                 nvidia,pins = "uart3_rts_n_pc0",
                                                 "uart3_txd_pw6";
                                 nvidia,function = "uartc";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         owr {
                                 nvidia,pins = "owr";
                                 nvidia,function = "owr";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         hdmi_cec_pee3 {
                                 nvidia,pins = "hdmi_cec_pee3";
                                 nvidia,function = "cec";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
-                                nvidia,lock = <0>;
-                                nvidia,open-drain = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
                         };
                         ddc_scl_pv4 {
                                 nvidia,pins = "ddc_scl_pv4",
                                                 "ddc_sda_pv5";
                                 nvidia,function = "i2c4";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
-                                nvidia,lock = <0>;
-                                nvidia,rcv-sel = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
                         };
                         spdif_in_pk6 {
                                 nvidia,pins = "spdif_in_pk6";
                                 nvidia,function = "usb";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
-                                nvidia,lock = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
                         };
                         usb_vbus_en0_pn4 {
                                 nvidia,pins = "usb_vbus_en0_pn4";
                                 nvidia,function = "usb";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
-                                nvidia,lock = <0>;
-                                nvidia,open-drain = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
                         };
                         gpio_x6_aud_px6 {
                                 nvidia,pins = "gpio_x6_aud_px6";
                                 nvidia,function = "spi6";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <1>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         gpio_x4_aud_px4 {
                                 nvidia,pins = "gpio_x4_aud_px4",
                                                 "gpio_x7_aud_px7";
                                 nvidia,function = "rsvd1";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         gpio_x5_aud_px5 {
                                 nvidia,pins = "gpio_x5_aud_px5";
                                 nvidia,function = "rsvd1";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         gpio_w2_aud_pw2 {
                                 nvidia,pins = "gpio_w2_aud_pw2";
                                 nvidia,function = "rsvd2";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         gpio_w3_aud_pw3 {
                                 nvidia,pins = "gpio_w3_aud_pw3";
                                 nvidia,function = "spi6";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         gpio_x1_aud_px1 {
                                 nvidia,pins = "gpio_x1_aud_px1";
                                 nvidia,function = "rsvd4";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         gpio_x3_aud_px3 {
                                 nvidia,pins = "gpio_x3_aud_px3";
                                 nvidia,function = "rsvd4";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         dap3_fs_pp0 {
                                 nvidia,pins = "dap3_fs_pp0";
                                 nvidia,function = "i2s2";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         dap3_dout_pp2 {
                                 nvidia,pins = "dap3_dout_pp2";
                                 nvidia,function = "i2s2";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         pv1 {
                                 nvidia,pins = "pv1";
                                 nvidia,function = "rsvd1";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         pbb3 {
                                 nvidia,pins = "pbb3",
@@ -549,25 +580,25 @@
                                                 "pbb6",
                                                 "pbb7";
                                 nvidia,function = "rsvd4";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         pcc1 {
                                 nvidia,pins = "pcc1",
                                                 "pcc2";
                                 nvidia,function = "rsvd4";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         gmi_ad0_pg0 {
                                 nvidia,pins = "gmi_ad0_pg0",
                                                 "gmi_ad1_pg1";
                                 nvidia,function = "gmi";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         gmi_ad10_ph2 {
                                 nvidia,pins = "gmi_ad10_ph2",
@@ -576,17 +607,17 @@
                                                 "gmi_ad8_ph0",
                                                 "gmi_clk_pk1";
                                 nvidia,function = "gmi";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         gmi_ad2_pg2 {
                                 nvidia,pins = "gmi_ad2_pg2",
                                                 "gmi_ad3_pg3";
                                 nvidia,function = "gmi";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         gmi_adv_n_pk0 {
                                 nvidia,pins = "gmi_adv_n_pk0",
@@ -598,39 +629,39 @@
                                                 "gmi_iordy_pi5",
                                                 "gmi_wp_n_pc7";
                                 nvidia,function = "gmi";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         gmi_cs3_n_pk4 {
                                 nvidia,pins = "gmi_cs3_n_pk4";
                                 nvidia,function = "gmi";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         clk2_req_pcc5 {
                                 nvidia,pins = "clk2_req_pcc5";
                                 nvidia,function = "rsvd4";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         kb_col3_pq3 {
                                 nvidia,pins = "kb_col3_pq3",
                                                 "kb_col6_pq6",
                                                 "kb_col7_pq7";
                                 nvidia,function = "kbc";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         kb_col5_pq5 {
                                 nvidia,pins = "kb_col5_pq5";
                                 nvidia,function = "kbc";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         kb_row3_pr3 {
                                 nvidia,pins = "kb_row3_pr3",
@@ -638,77 +669,77 @@
                                                 "kb_row6_pr6",
                                                 "kb_row8_ps0";
                                 nvidia,function = "kbc";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         clk3_req_pee1 {
                                 nvidia,pins = "clk3_req_pee1";
                                 nvidia,function = "rsvd4";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         pu4 {
                                 nvidia,pins = "pu4";
                                 nvidia,function = "displayb";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         pu5 {
                                 nvidia,pins = "pu5",
                                                 "pu6";
                                 nvidia,function = "displayb";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         hdmi_int_pn7 {
                                 nvidia,pins = "hdmi_int_pn7";
                                 nvidia,function = "rsvd1";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         clk1_req_pee2 {
                                 nvidia,pins = "clk1_req_pee2",
                                                 "usb_vbus_en1_pn5";
                                 nvidia,function = "rsvd4";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <1>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
 
                         drive_sdio1 {
                                 nvidia,pins = "drive_sdio1";
-                                nvidia,high-speed-mode = <1>;
-                                nvidia,schmitt = <0>;
-                                nvidia,low-power-mode = <3>;
+                                nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+                                nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
                                 nvidia,pull-down-strength = <36>;
                                 nvidia,pull-up-strength = <20>;
-                                nvidia,slew-rate-rising = <2>;
-                                nvidia,slew-rate-falling = <2>;
+                                nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
+                                nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>;
                         };
                         drive_sdio3 {
                                 nvidia,pins = "drive_sdio3";
-                                nvidia,high-speed-mode = <1>;
-                                nvidia,schmitt = <0>;
-                                nvidia,low-power-mode = <3>;
+                                nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+                                nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
                                 nvidia,pull-down-strength = <22>;
                                 nvidia,pull-up-strength = <36>;
-                                nvidia,slew-rate-rising = <0>;
-                                nvidia,slew-rate-falling = <0>;
+                                nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+                                nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
                         };
                         drive_gma {
                                 nvidia,pins = "drive_gma";
-                                nvidia,high-speed-mode = <1>;
-                                nvidia,schmitt = <0>;
-                                nvidia,low-power-mode = <3>;
+                                nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+                                nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
                                 nvidia,pull-down-strength = <2>;
                                 nvidia,pull-up-strength = <1>;
-                                nvidia,slew-rate-rising = <0>;
-                                nvidia,slew-rate-falling = <0>;
+                                nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+                                nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
                                 nvidia,drive-type = <1>;
                         };
                 };
@@ -718,11 +749,15 @@
                 status = "okay";
         };
 
+        pwm@7000a000 {
+                status = "okay";
+        };
+
         i2c@7000c000 {
                 status = "okay";
                 clock-frequency = <100000>;
 
-                battery: smart-battery {
+                battery: smart-battery@b {
                         compatible = "ti,bq20z45", "sbs,sbs-battery";
                         reg = <0xb>;
                         battery-name = "battery";
@@ -731,7 +766,7 @@
                         power-supplies = <&charger>;
                 };
 
-                rt5640: rt5640 {
+                rt5640: rt5640@1c {
                         compatible = "realtek,rt5640";
                         reg = <0x1c>;
                         interrupt-parent = <&gpio>;
@@ -749,11 +784,15 @@
                 };
         };
 
+        hdmi_ddc: i2c@7000c700 {
+                status = "okay";
+        };
+
         i2c@7000d000 {
                 status = "okay";
                 clock-frequency = <400000>;
 
-                tps51632 {
+                tps51632@43 {
                         compatible = "ti,tps51632";
                         reg = <0x43>;
                         regulator-name = "vdd-cpu";
@@ -763,7 +802,7 @@
                         regulator-always-on;
                 };
 
-                tps65090 {
+                tps65090@48 {
                         compatible = "ti,tps65090";
                         reg = <0x48>;
                         interrupt-parent = <&gpio>;
@@ -806,7 +845,7 @@
                                         regulator-boot-on;
                                 };
 
-                                fet1 {
+                                vdd_bl_reg: fet1 {
                                         regulator-name = "vdd-lcd-bl";
                                 };
 
@@ -814,7 +853,7 @@
                                         regulator-name = "vdd-modem-3v3";
                                 };
 
-                                fet4 {
+                                avdd_lcd_reg: fet4 {
                                         regulator-name = "avdd-lcd";
                                 };
 
@@ -846,7 +885,7 @@
                         };
                 };
 
-                palmas: tps65913 {
+                palmas: tps65913@58 {
                         compatible = "ti,palmas";
                         reg = <0x58>;
                         interrupts = <0 86 IRQ_TYPE_LEVEL_LOW>;
@@ -1046,7 +1085,7 @@
                 };
         };
 
-        pmc {
+        pmc@7000e400 {
                 nvidia,invert-interrupt;
                 nvidia,suspend-mode = <1>;
                 nvidia,cpu-pwr-good-time = <500>;
@@ -1057,7 +1096,7 @@
                 nvidia,sys-clock-req-active-high;
         };
 
-        ahub {
+        ahub@70080000 {
                 i2s@70080400 {
                         status = "okay";
                 };
@@ -1084,12 +1123,23 @@
                 vbus-supply = <&usb3_vbus_reg>;
         };
 
+        backlight: backlight {
+                compatible = "pwm-backlight";
+
+                enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+                power-supply = <&vdd_bl_reg>;
+                pwms = <&pwm 1 1000000>;
+
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+        };
+
         clocks {
                 compatible = "simple-bus";
                 #address-cells = <1>;
                 #size-cells = <0>;
 
-                clk32k_in: clock {
+                clk32k_in: clock@0 {
                         compatible = "fixed-clock";
                         reg=<0>;
                         #clock-cells = <0>;
@@ -1150,16 +1200,6 @@
                         gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
                 };
 
-                lcd_bl_en_reg: regulator@2 {
-                        compatible = "regulator-fixed";
-                        reg = <2>;
-                        regulator-name = "lcd_bl_en";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                        enable-active-high;
-                        gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
-                };
-
                 usb1_vbus_reg: regulator@3 {
                         compatible = "regulator-fixed";
                         reg = <3>;
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 731249fbe206..389e987ec281 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -1,5 +1,6 @@
 #include <dt-bindings/clock/tegra114-car.h>
 #include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-tegra.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
 #include "skeleton.dtsi"
@@ -15,7 +16,113 @@
                 serial3 = &uartd;
         };
 
-        gic: interrupt-controller {
+        host1x@50000000 {
+                compatible = "nvidia,tegra114-host1x", "simple-bus";
+                reg = <0x50000000 0x00028000>;
+                interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
+                             <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
+                clocks = <&tegra_car TEGRA114_CLK_HOST1X>;
+                resets = <&tegra_car 28>;
+                reset-names = "host1x";
+
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                ranges = <0x54000000 0x54000000 0x01000000>;
+
+                gr2d@54140000 {
+                        compatible = "nvidia,tegra114-gr2d", "nvidia,tegra20-gr2d";
+                        reg = <0x54140000 0x00040000>;
+                        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA114_CLK_GR2D>;
+                        resets = <&tegra_car 21>;
+                        reset-names = "2d";
+                };
+
+                gr3d@54180000 {
+                        compatible = "nvidia,tegra114-gr3d", "nvidia,tegra20-gr3d";
+                        reg = <0x54180000 0x00040000>;
+                        clocks = <&tegra_car TEGRA114_CLK_GR3D>;
+                        resets = <&tegra_car 24>;
+                        reset-names = "3d";
+                };
+
+                dc@54200000 {
+                        compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
+                        reg = <0x54200000 0x00040000>;
+                        interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA114_CLK_DISP1>,
+                                 <&tegra_car TEGRA114_CLK_PLL_P>;
+                        clock-names = "dc", "parent";
+                        resets = <&tegra_car 27>;
+                        reset-names = "dc";
+
+                        rgb {
+                                status = "disabled";
+                        };
+                };
+
+                dc@54240000 {
+                        compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
+                        reg = <0x54240000 0x00040000>;
+                        interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA114_CLK_DISP2>,
+                                 <&tegra_car TEGRA114_CLK_PLL_P>;
+                        clock-names = "dc", "parent";
+                        resets = <&tegra_car 26>;
+                        reset-names = "dc";
+
+                        rgb {
+                                status = "disabled";
+                        };
+                };
+
+                hdmi@54280000 {
+                        compatible = "nvidia,tegra114-hdmi";
+                        reg = <0x54280000 0x00040000>;
+                        interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA114_CLK_HDMI>,
+                                 <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
+                        clock-names = "hdmi", "parent";
+                        resets = <&tegra_car 51>;
+                        reset-names = "hdmi";
+                        status = "disabled";
+                };
+
+                dsi@54300000 {
+                        compatible = "nvidia,tegra114-dsi";
+                        reg = <0x54300000 0x00040000>;
+                        clocks = <&tegra_car TEGRA114_CLK_DSIA>,
+                                 <&tegra_car TEGRA114_CLK_DSIALP>,
+                                 <&tegra_car TEGRA114_CLK_PLL_D_OUT0>;
+                        clock-names = "dsi", "lp", "parent";
+                        resets = <&tegra_car 48>;
+                        reset-names = "dsi";
+                        nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
+                        status = "disabled";
+
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
+                dsi@54400000 {
+                        compatible = "nvidia,tegra114-dsi";
+                        reg = <0x54400000 0x00040000>;
+                        clocks = <&tegra_car TEGRA114_CLK_DSIB>,
+                                 <&tegra_car TEGRA114_CLK_DSIBLP>,
+                                 <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
+                        clock-names = "dsi", "lp", "parent";
+                        resets = <&tegra_car 82>;
+                        reset-names = "dsi";
+                        nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
+                        status = "disabled";
+
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+        };
+
+        gic: interrupt-controller@50041000 {
                 compatible = "arm,cortex-a15-gic";
                 #interrupt-cells = <3>;
                 interrupt-controller;
@@ -39,14 +146,14 @@
                 clocks = <&tegra_car TEGRA114_CLK_TIMER>;
         };
 
-        tegra_car: clock {
+        tegra_car: clock@60006000 {
                 compatible = "nvidia,tegra114-car";
                 reg = <0x60006000 0x1000>;
                 #clock-cells = <1>;
                 #reset-cells = <1>;
         };
 
-        apbdma: dma {
+        apbdma: dma@6000a000 {
                 compatible = "nvidia,tegra114-apbdma";
                 reg = <0x6000a000 0x1400>;
                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
@@ -87,12 +194,12 @@
                 #dma-cells = <1>;
         };
 
-        ahb: ahb {
+        ahb: ahb@6000c004 {
                 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
                 reg = <0x6000c004 0x14c>;
         };
 
-        gpio: gpio {
+        gpio: gpio@6000d000 {
                 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
                 reg = <0x6000d000 0x1000>;
                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
@@ -109,7 +216,7 @@
                 interrupt-controller;
         };
 
-        pinmux: pinmux {
+        pinmux: pinmux@70000868 {
                 compatible = "nvidia,tegra114-pinmux";
                 reg = <0x70000868 0x148         /* Pad control registers */
                        0x70003000 0x40c>;       /* Mux registers */
@@ -175,7 +282,7 @@
                 status = "disabled";
         };
 
-        pwm: pwm {
+        pwm: pwm@7000a000 {
                 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
                 reg = <0x7000a000 0x100>;
                 #pwm-cells = <2>;
@@ -350,14 +457,14 @@
                 status = "disabled";
         };
 
-        rtc {
+        rtc@7000e000 {
                 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
                 reg = <0x7000e000 0x100>;
                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&tegra_car TEGRA114_CLK_RTC>;
         };
 
-        kbc {
+        kbc@7000e200 {
                 compatible = "nvidia,tegra114-kbc";
                 reg = <0x7000e200 0x100>;
                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
@@ -367,14 +474,14 @@
                 status = "disabled";
         };
 
-        pmc {
+        pmc@7000e400 {
                 compatible = "nvidia,tegra114-pmc";
                 reg = <0x7000e400 0x400>;
                 clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
                 clock-names = "pclk", "clk32k_in";
         };
 
-        iommu {
+        iommu@70019010 {
                 compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
                 reg = <0x70019010 0x02c
                        0x700191f0 0x010
@@ -385,7 +492,7 @@
                 nvidia,ahb = <&ahb>;
         };
 
-        ahub {
+        ahub@70080000 {
                 compatible = "nvidia,tegra114-ahub";
                 reg = <0x70080000 0x200>,
                       <0x70080200 0x100>,
@@ -479,6 +586,13 @@
                 };
         };
 
+        mipi: mipi@700e3000 {
+                compatible = "nvidia,tegra114-mipi";
+                reg = <0x700e3000 0x100>;
+                clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
+                #nvidia,mipi-calibrate-cells = <1>;
+        };
+
         sdhci@78000000 {
                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
                 reg = <0x78000000 0x200>;
diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts
index 431d67a2b413..c6dcef513e5d 100644
--- a/arch/arm/boot/dts/tegra124-venice2.dts
+++ b/arch/arm/boot/dts/tegra124-venice2.dts
@@ -1,19 +1,917 @@
 /dts-v1/;
 
+#include <dt-bindings/input/input.h>
 #include "tegra124.dtsi"
 
 / {
         model = "NVIDIA Tegra124 Venice2";
         compatible = "nvidia,venice2", "nvidia,tegra124";
 
+        aliases {
+                rtc0 = "/i2c@7000d000/as3722@40";
+                rtc1 = "/rtc@7000e000";
+        };
+
         memory {
                 reg = <0x80000000 0x80000000>;
         };
 
+        pinmux: pinmux@70000868 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinmux_default>;
+
+                pinmux_default: common {
+                        dap_mclk1_pw4 {
+                                nvidia,pins = "dap_mclk1_pw4";
+                                nvidia,function = "extperiph1";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap1_din_pn1 {
+                                nvidia,pins = "dap1_din_pn1";
+                                nvidia,function = "i2s0";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap1_dout_pn2 {
+                                nvidia,pins = "dap1_dout_pn2",
+                                              "dap1_fs_pn0",
+                                              "dap1_sclk_pn3";
+                                nvidia,function = "i2s0";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap2_din_pa4 {
+                                nvidia,pins = "dap2_din_pa4";
+                                nvidia,function = "i2s1";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap2_dout_pa5 {
+                                nvidia,pins = "dap2_dout_pa5",
+                                              "dap2_fs_pa2",
+                                              "dap2_sclk_pa3";
+                                nvidia,function = "i2s1";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        dvfs_pwm_px0 {
+                                nvidia,pins = "dvfs_pwm_px0",
+                                              "dvfs_clk_px2";
+                                nvidia,function = "cldvfs";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_clk_py0 {
+                                nvidia,pins = "ulpi_clk_py0",
+                                              "ulpi_nxt_py2",
+                                              "ulpi_stp_py3";
+                                nvidia,function = "spi1";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_dir_py1 {
+                                nvidia,pins = "ulpi_dir_py1";
+                                nvidia,function = "spi1";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        cam_i2c_scl_pbb1 {
+                                nvidia,pins = "cam_i2c_scl_pbb1",
+                                              "cam_i2c_sda_pbb2";
+                                nvidia,function = "i2c3";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        gen2_i2c_scl_pt5 {
+                                nvidia,pins = "gen2_i2c_scl_pt5",
+                                              "gen2_i2c_sda_pt6";
+                                nvidia,function = "i2c2";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        pg4 {
+                                nvidia,pins = "pg4",
+                                              "pg5",
+                                              "pg6",
+                                              "pi3";
+                                nvidia,function = "spi4";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        pg7 {
+                                nvidia,pins = "pg7";
+                                nvidia,function = "spi4";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        ph1 {
+                                nvidia,pins = "ph1";
+                                nvidia,function = "pwm1";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        pk0 {
+                                nvidia,pins = "pk0",
+                                              "kb_row15_ps7",
+                                              "clk_32k_out_pa0";
+                                nvidia,function = "soc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_clk_pz0 {
+                                nvidia,pins = "sdmmc1_clk_pz0",
+                                              "sdmmc1_cmd_pz1",
+                                              "sdmmc1_dat0_py7",
+                                              "sdmmc1_dat1_py6",
+                                              "sdmmc1_dat2_py5",
+                                              "sdmmc1_dat3_py4";
+                                nvidia,function = "sdmmc1";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc1_cmd_pz1 {
+                                nvidia,pins = "sdmmc1_cmd_pz1",
+                                              "sdmmc1_dat0_py7",
+                                              "sdmmc1_dat1_py6",
+                                              "sdmmc1_dat2_py5",
+                                              "sdmmc1_dat3_py4";
+                                nvidia,function = "sdmmc1";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc3_clk_pa6 {
+                                nvidia,pins = "sdmmc3_clk_pa6";
+                                nvidia,function = "sdmmc3";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc3_cmd_pa7 {
+                                nvidia,pins = "sdmmc3_cmd_pa7",
+                                              "sdmmc3_dat0_pb7",
+                                              "sdmmc3_dat1_pb6",
+                                              "sdmmc3_dat2_pb5",
+                                              "sdmmc3_dat3_pb4",
+                                              "sdmmc3_clk_lb_out_pee4",
+                                              "sdmmc3_clk_lb_in_pee5";
+                                nvidia,function = "sdmmc3";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc4_clk_pcc4 {
+                                nvidia,pins = "sdmmc4_clk_pcc4";
+                                nvidia,function = "sdmmc4";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc4_cmd_pt7 {
+                                nvidia,pins = "sdmmc4_cmd_pt7",
+                                              "sdmmc4_dat0_paa0",
+                                              "sdmmc4_dat1_paa1",
+                                              "sdmmc4_dat2_paa2",
+                                              "sdmmc4_dat3_paa3",
+                                              "sdmmc4_dat4_paa4",
+                                              "sdmmc4_dat5_paa5",
+                                              "sdmmc4_dat6_paa6",
+                                              "sdmmc4_dat7_paa7";
+                                nvidia,function = "sdmmc4";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        pwr_i2c_scl_pz6 {
+                                nvidia,pins = "pwr_i2c_scl_pz6",
+                                              "pwr_i2c_sda_pz7";
+                                nvidia,function = "i2cpwr";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        jtag_rtck {
+                                nvidia,pins = "jtag_rtck";
+                                nvidia,function = "rtck";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        clk_32k_in {
+                                nvidia,pins = "clk_32k_in";
+                                nvidia,function = "clk";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        core_pwr_req {
+                                nvidia,pins = "core_pwr_req";
+                                nvidia,function = "pwron";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        cpu_pwr_req {
+                                nvidia,pins = "cpu_pwr_req";
+                                nvidia,function = "cpu";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        pwr_int_n {
+                                nvidia,pins = "pwr_int_n";
+                                nvidia,function = "pmi";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        reset_out_n {
+                                nvidia,pins = "reset_out_n";
+                                nvidia,function = "reset_out_n";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        clk3_out_pee0 {
+                                nvidia,pins = "clk3_out_pee0";
+                                nvidia,function = "extperiph3";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap4_din_pp5 {
+                                nvidia,pins = "dap4_din_pp5";
+                                nvidia,function = "i2s3";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap4_dout_pp6 {
+                                nvidia,pins = "dap4_dout_pp6",
+                                              "dap4_fs_pp4",
+                                              "dap4_sclk_pp7";
+                                nvidia,function = "i2s3";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                        };
+                        gen1_i2c_sda_pc5 {
+                                nvidia,pins = "gen1_i2c_sda_pc5",
+                                              "gen1_i2c_scl_pc4";
+                                nvidia,function = "i2c1";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart2_cts_n_pj5 {
+                                nvidia,pins = "uart2_cts_n_pj5";
+                                nvidia,function = "uartb";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart2_rts_n_pj6 {
+                                nvidia,pins = "uart2_rts_n_pj6";
+                                nvidia,function = "uartb";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart2_rxd_pc3 {
+                                nvidia,pins = "uart2_rxd_pc3";
+                                nvidia,function = "irda";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart2_txd_pc2 {
+                                nvidia,pins = "uart2_txd_pc2";
+                                nvidia,function = "irda";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart3_cts_n_pa1 {
+                                nvidia,pins = "uart3_cts_n_pa1",
+                                              "uart3_rxd_pw7";
+                                nvidia,function = "uartc";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart3_rts_n_pc0 {
+                                nvidia,pins = "uart3_rts_n_pc0",
+                                              "uart3_txd_pw6";
+                                nvidia,function = "uartc";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        hdmi_cec_pee3 {
+                                nvidia,pins = "hdmi_cec_pee3";
+                                nvidia,function = "cec";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+                        hdmi_int_pn7 {
+                                nvidia,pins = "hdmi_int_pn7";
+                                nvidia,function = "rsvd1";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        ddc_scl_pv4 {
+                                nvidia,pins = "ddc_scl_pv4",
+                                              "ddc_sda_pv5";
+                                nvidia,function = "i2c4";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
+                        };
+                        pj7 {
+                                nvidia,pins = "pj7",
+                                              "pk7";
+                                nvidia,function = "uartd";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pb0 {
+                                nvidia,pins = "pb0",
+                                              "pb1";
+                                nvidia,function = "uartd";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ph0 {
+                                nvidia,pins = "ph0";
+                                nvidia,function = "pwm0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row10_ps2 {
+                                nvidia,pins = "kb_row10_ps2";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row9_ps1 {
+                                nvidia,pins = "kb_row9_ps1";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row6_pr6 {
+                                nvidia,pins = "kb_row6_pr6";
+                                nvidia,function = "displaya_alt";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        usb_vbus_en0_pn4 {
+                                nvidia,pins = "usb_vbus_en0_pn4";
+                                nvidia,function = "usb";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        usb_vbus_en1_pn5 {
+                                nvidia,pins = "usb_vbus_en1_pn5";
+                                nvidia,function = "usb";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        drive_sdio1 {
+                                nvidia,pins = "drive_sdio1";
+                                nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+                                nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+                                nvidia,pull-down-strength = <32>;
+                                nvidia,pull-up-strength = <42>;
+                                nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+                                nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+                        };
+                        drive_sdio3 {
+                                nvidia,pins = "drive_sdio3";
+                                nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+                                nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+                                nvidia,pull-down-strength = <20>;
+                                nvidia,pull-up-strength = <36>;
+                                nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+                                nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+                        };
+                        drive_gma {
+                                nvidia,pins = "drive_gma";
+                                nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+                                nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+                                nvidia,pull-down-strength = <1>;
+                                nvidia,pull-up-strength = <2>;
+                                nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+                                nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+                                nvidia,drive-type = <1>;
+                        };
+                        als_irq_l {
+                                nvidia,pins = "gpio_x3_aud_px3";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        codec_irq_l {
+                                nvidia,pins = "ph4";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_bl_en {
+                                nvidia,pins = "ph2";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        touch_irq_l {
+                                nvidia,pins = "gpio_w3_aud_pw3";
+                                nvidia,function = "spi6";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        tpm_davint_l {
+                                nvidia,pins = "ph6";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ts_irq_l {
+                                nvidia,pins = "pk2";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ts_reset_l {
+                                nvidia,pins = "pk4";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ts_shdn_l {
+                                nvidia,pins = "pk1";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ph7 {
+                                nvidia,pins = "ph7";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col0_ap {
+                                nvidia,pins = "kb_col0_pq0";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lid_open {
+                                nvidia,pins = "kb_row4_pr4";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        en_vdd_sd {
+                                nvidia,pins = "kb_row0_pr0";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ac_ok {
+                                nvidia,pins = "pj0";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sensor_irq_l {
+                                nvidia,pins = "pi6";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        wifi_en {
+                                nvidia,pins = "gpio_x7_aud_px7";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        wifi_rst_l {
+                                nvidia,pins = "clk2_req_pcc5";
+                                nvidia,function = "dap";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        hp_det_l {
+                                nvidia,pins = "ulpi_data1_po2";
+                                nvidia,function = "spi3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                };
+        };
+
         serial@70006000 {
                 status = "okay";
         };
 
+        pwm: pwm@7000a000 {
+                status = "okay";
+        };
+
+        i2c@7000c000 {
+                status = "okay";
+                clock-frequency = <100000>;
+
+                acodec: audio-codec@10 {
+                        compatible = "maxim,max98090";
+                        reg = <0x10>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
+                };
+        };
+
+        i2c@7000c400 {
+                status = "okay";
+                clock-frequency = <100000>;
+        };
+
+        i2c@7000c500 {
+                status = "okay";
+                clock-frequency = <100000>;
+        };
+
+        i2c@7000c700 {
+                status = "okay";
+                clock-frequency = <100000>;
+        };
+
+        i2c@7000d000 {
+                status = "okay";
+                clock-frequency = <400000>;
+
+                as3722: as3722@40 {
+                        compatible = "ams,as3722";
+                        reg = <0x40>;
+                        interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
+
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&as3722_default>;
+
+                        as3722_default: pinmux {
+                                gpio0 {
+                                        pins = "gpio0";
+                                        function = "gpio";
+                                        bias-pull-down;
+                                };
+
+                                gpio1_2_4_7 {
+                                        pins = "gpio1", "gpio2", "gpio4", "gpio7";
+                                        function = "gpio";
+                                        bias-pull-up;
+                                };
+
+                                gpio3_6 {
+                                        pins = "gpio3", "gpio6";
+                                        bias-high-impedance;
+                                };
+
+                                gpio5 {
+                                        pins = "gpio5";
+                                        function = "clk32k-out";
+                                };
+                        };
+
+                        regulators {
+                                vsup-sd2-supply = <&vdd_ac_bat_reg>;
+                                vsup-sd3-supply = <&vdd_ac_bat_reg>;
+                                vsup-sd4-supply = <&vdd_ac_bat_reg>;
+                                vsup-sd5-supply = <&vdd_ac_bat_reg>;
+                                vin-ldo0-supply = <&as3722_sd2>;
+                                vin-ldo1-6-supply = <&vdd_ac_bat_reg>;
+                                vin-ldo2-5-7-supply = <&as3722_sd5>;
+                                vin-ldo3-4-supply = <&vdd_ac_bat_reg>;
+                                vin-ldo9-10-supply = <&vdd_ac_bat_reg>;
+                                vin-ldo11-supply = <&vdd_ac_bat_reg>;
+
+                                sd0 {
+                                        regulator-name = "vdd-cpu";
+                                        regulator-min-microvolt = <700000>;
+                                        regulator-max-microvolt = <1400000>;
+                                        regulator-min-microamp = <3500000>;
+                                        regulator-max-microamp = <3500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        ams,external-control = <2>;
+                                };
+
+                                sd1 {
+                                        regulator-name = "vdd-core";
+                                        regulator-min-microvolt = <700000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-min-microamp = <2500000>;
+                                        regulator-max-microamp = <2500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        ams,external-control = <1>;
+                                };
+
+                                as3722_sd2: sd2 {
+                                        regulator-name = "vddio-ddr";
+                                        regulator-min-microvolt = <1350000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                sd3 {
+                                        regulator-name = "vddio-ddr-2phase";
+                                        regulator-min-microvolt = <1350000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                sd4 {
+                                        regulator-name = "avdd-pex-sata";
+                                        regulator-min-microvolt = <1050000>;
+                                        regulator-max-microvolt = <1050000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                };
+
+                                as3722_sd5: sd5 {
+                                        regulator-name = "vddio-sys";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                };
+
+                                sd6 {
+                                        regulator-name = "vdd-gpu";
+                                        regulator-min-microvolt = <650000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-min-microamp = <3500000>;
+                                        regulator-max-microamp = <3500000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                };
+
+                                ldo0 {
+                                        regulator-name = "avdd_pll";
+                                        regulator-min-microvolt = <1050000>;
+                                        regulator-max-microvolt = <1050000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                        ams,external-control = <1>;
+                                };
+
+                                ldo1 {
+                                        regulator-name = "run-cam-1.8";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+
+                                ldo2 {
+                                        regulator-name = "gen-avdd,vddio-hsic";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                };
+
+                                ldo3 {
+                                        regulator-name = "vdd-rtc";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                        ams,enable-tracking;
+                                };
+
+                                ldo4 {
+                                        regulator-name = "vdd-cam";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                };
+
+                                ldo5 {
+                                        regulator-name = "vdd-cam-front";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                };
+
+                                ldo6 {
+                                        regulator-name = "vddio-sdmmc3";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                };
+
+                                ldo7 {
+                                        regulator-name = "vdd-cam-rear";
+                                        regulator-min-microvolt = <1050000>;
+                                        regulator-max-microvolt = <1050000>;
+                                };
+
+                                ldo9 {
+                                        regulator-name = "vdd-touch";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                };
+
+                                ldo10 {
+                                        regulator-name = "vdd-cam-af";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                };
+
+                                ldo11 {
+                                        regulator-name = "vpp-fuse";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                        };
+                };
+        };
+
+        spi@7000d400 {
+                status = "okay";
+
+                cros-ec@0 {
+                        compatible = "google,cros-ec-spi";
+                        spi-max-frequency = <4000000>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
+                        reg = <0>;
+
+                        google,cros-ec-spi-msg-delay = <2000>;
+
+                        cros-ec-keyb {
+                                compatible = "google,cros-ec-keyb";
+                                keypad,num-rows = <8>;
+                                keypad,num-columns = <13>;
+                                google,needs-ghost-filter;
+
+                                linux,keymap = <
+                                        MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA)
+                                        MATRIX_KEY(0x00, 0x02, KEY_F1)
+                                        MATRIX_KEY(0x00, 0x03, KEY_B)
+                                        MATRIX_KEY(0x00, 0x04, KEY_F10)
+                                        MATRIX_KEY(0x00, 0x06, KEY_N)
+                                        MATRIX_KEY(0x00, 0x08, KEY_EQUAL)
+                                        MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT)
+
+                                        MATRIX_KEY(0x01, 0x01, KEY_ESC)
+                                        MATRIX_KEY(0x01, 0x02, KEY_F4)
+                                        MATRIX_KEY(0x01, 0x03, KEY_G)
+                                        MATRIX_KEY(0x01, 0x04, KEY_F7)
+                                        MATRIX_KEY(0x01, 0x06, KEY_H)
+                                        MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE)
+                                        MATRIX_KEY(0x01, 0x09, KEY_F9)
+                                        MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE)
+
+                                        MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL)
+                                        MATRIX_KEY(0x02, 0x01, KEY_TAB)
+                                        MATRIX_KEY(0x02, 0x02, KEY_F3)
+                                        MATRIX_KEY(0x02, 0x03, KEY_T)
+                                        MATRIX_KEY(0x02, 0x04, KEY_F6)
+                                        MATRIX_KEY(0x02, 0x05, KEY_RIGHTBRACE)
+                                        MATRIX_KEY(0x02, 0x06, KEY_Y)
+                                        MATRIX_KEY(0x02, 0x07, KEY_102ND)
+                                        MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE)
+                                        MATRIX_KEY(0x02, 0x09, KEY_F8)
+
+                                        MATRIX_KEY(0x03, 0x01, KEY_GRAVE)
+                                        MATRIX_KEY(0x03, 0x02, KEY_F2)
+                                        MATRIX_KEY(0x03, 0x03, KEY_5)
+                                        MATRIX_KEY(0x03, 0x04, KEY_F5)
+                                        MATRIX_KEY(0x03, 0x06, KEY_6)
+                                        MATRIX_KEY(0x03, 0x08, KEY_MINUS)
+                                        MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH)
+
+                                        MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL)
+                                        MATRIX_KEY(0x04, 0x01, KEY_A)
+                                        MATRIX_KEY(0x04, 0x02, KEY_D)
+                                        MATRIX_KEY(0x04, 0x03, KEY_F)
+                                        MATRIX_KEY(0x04, 0x04, KEY_S)
+                                        MATRIX_KEY(0x04, 0x05, KEY_K)
+                                        MATRIX_KEY(0x04, 0x06, KEY_J)
+                                        MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON)
+                                        MATRIX_KEY(0x04, 0x09, KEY_L)
+                                        MATRIX_KEY(0x04, 0x0a, KEY_BACKSLASH)
+                                        MATRIX_KEY(0x04, 0x0b, KEY_ENTER)
+
+                                        MATRIX_KEY(0x05, 0x01, KEY_Z)
+                                        MATRIX_KEY(0x05, 0x02, KEY_C)
+                                        MATRIX_KEY(0x05, 0x03, KEY_V)
+                                        MATRIX_KEY(0x05, 0x04, KEY_X)
+                                        MATRIX_KEY(0x05, 0x05, KEY_COMMA)
+                                        MATRIX_KEY(0x05, 0x06, KEY_M)
+                                        MATRIX_KEY(0x05, 0x07, KEY_LEFTSHIFT)
+                                        MATRIX_KEY(0x05, 0x08, KEY_SLASH)
+                                        MATRIX_KEY(0x05, 0x09, KEY_DOT)
+                                        MATRIX_KEY(0x05, 0x0b, KEY_SPACE)
+
+                                        MATRIX_KEY(0x06, 0x01, KEY_1)
+                                        MATRIX_KEY(0x06, 0x02, KEY_3)
+                                        MATRIX_KEY(0x06, 0x03, KEY_4)
+                                        MATRIX_KEY(0x06, 0x04, KEY_2)
+                                        MATRIX_KEY(0x06, 0x05, KEY_8)
+                                        MATRIX_KEY(0x06, 0x06, KEY_7)
+                                        MATRIX_KEY(0x06, 0x08, KEY_0)
+                                        MATRIX_KEY(0x06, 0x09, KEY_9)
+                                        MATRIX_KEY(0x06, 0x0a, KEY_LEFTALT)
+                                        MATRIX_KEY(0x06, 0x0b, KEY_DOWN)
+                                        MATRIX_KEY(0x06, 0x0c, KEY_RIGHT)
+
+                                        MATRIX_KEY(0x07, 0x01, KEY_Q)
+                                        MATRIX_KEY(0x07, 0x02, KEY_E)
+                                        MATRIX_KEY(0x07, 0x03, KEY_R)
+                                        MATRIX_KEY(0x07, 0x04, KEY_W)
+                                        MATRIX_KEY(0x07, 0x05, KEY_I)
+                                        MATRIX_KEY(0x07, 0x06, KEY_U)
+                                        MATRIX_KEY(0x07, 0x07, KEY_RIGHTSHIFT)
+                                        MATRIX_KEY(0x07, 0x08, KEY_P)
+                                        MATRIX_KEY(0x07, 0x09, KEY_O)
+                                        MATRIX_KEY(0x07, 0x0b, KEY_UP)
+                                        MATRIX_KEY(0x07, 0x0c, KEY_LEFT)
+                                >;
+                        };
+                };
+        };
+
         pmc@7000e400 {
                 nvidia,invert-interrupt;
                 nvidia,suspend-mode = <1>;
@@ -24,4 +922,170 @@
                 nvidia,core-power-req-active-high;
                 nvidia,sys-clock-req-active-high;
         };
+
+        sdhci@700b0400 {
+                cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
+                power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
+                status = "okay";
+                bus-width = <4>;
+        };
+
+        sdhci@700b0600 {
+                status = "okay";
+                bus-width = <8>;
+        };
+
+        ahub@70300000 {
+                i2s@70301100 {
+                        status = "okay";
+                };
+        };
+
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock@0 {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+
+                power {
+                        label = "Power";
+                        gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_POWER>;
+                        debounce-interval = <10>;
+                        gpio-key,wakeup;
+                };
+        };
+
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                vdd_ac_bat_reg: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "vdd_ac_bat";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                };
+
+                vdd_3v3_reg: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "vdd_3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        enable-active-high;
+                        gpio = <&as3722 1 GPIO_ACTIVE_HIGH>;
+                };
+
+                vdd_3v3_modem_reg: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "vdd-modem-3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        enable-active-high;
+                        gpio = <&as3722 2 GPIO_ACTIVE_HIGH>;
+                };
+
+                vdd_hdmi_5v0_reg: regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "vdd-hdmi-5v0";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
+                };
+
+                vdd_bl_reg: regulator@4 {
+                        compatible = "regulator-fixed";
+                        reg = <4>;
+                        regulator-name = "vdd-bl";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_LOW>;
+                };
+
+                vdd_ts_sw_5v0: regulator@5 {
+                        compatible = "regulator-fixed";
+                        reg = <5>;
+                        regulator-name = "vdd_ts_sw";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-boot-on;
+                        gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_LOW>;
+                };
+
+                usb1_vbus_reg: regulator@6 {
+                        compatible = "regulator-fixed";
+                        reg = <6>;
+                        regulator-name = "usb1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-boot-on;
+                        enable-active-high;
+                        gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
+                        gpio-open-drain;
+                };
+
+                usb3_vbus_reg: regulator@7 {
+                        compatible = "regulator-fixed";
+                        reg = <7>;
+                        regulator-name = "usb3_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-boot-on;
+                        enable-active-high;
+                        gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
+                        gpio-open-drain;
+                };
+
+                panel_3v3_reg: regulator@8 {
+                        compatible = "regulator-fixed";
+                        reg = <8>;
+                        regulator-name = "panel_3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        enable-active-high;
+                        gpio = <&as3722 4 GPIO_ACTIVE_HIGH>;
+                };
+        };
+
+        sound {
+                compatible = "nvidia,tegra-audio-max98090-venice2",
+                             "nvidia,tegra-audio-max98090";
+                nvidia,model = "NVIDIA Tegra Venice2";
+
+                nvidia,audio-routing =
+                        "Headphones", "HPR",
+                        "Headphones", "HPL",
+                        "Speakers", "SPKR",
+                        "Speakers", "SPKL",
+                        "Mic Jack", "MICBIAS",
+                        "IN34", "Mic Jack";
+
+                nvidia,i2s-controller = <&tegra_i2s1>;
+                nvidia,audio-codec = <&acodec>;
+
+                clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
+                         <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA124_CLK_EXTERN1>;
+                clock-names = "pll_a", "pll_a_out0", "mclk";
+        };
 };
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index b7413004ee77..ec0698a8354a 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -1,4 +1,6 @@
+#include <dt-bindings/clock/tegra124-car.h>
 #include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-tegra.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
 #include "skeleton.dtsi"
@@ -28,6 +30,14 @@
                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA124_CLK_TIMER>;
+        };
+
+        tegra_car: clock@60006000 {
+                compatible = "nvidia,tegra124-car";
+                reg = <0x60006000 0x1000>;
+                #clock-cells = <1>;
+                #reset-cells = <1>;
         };
 
         gpio: gpio@6000d000 {
@@ -47,6 +57,53 @@
                 interrupt-controller;
         };
 
+        apbdma: dma@60020000 {
+                compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
+                reg = <0x60020000 0x1400>;
+                interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
+                resets = <&tegra_car 34>;
+                reset-names = "dma";
+                #dma-cells = <1>;
+        };
+
+        pinmux: pinmux@70000868 {
+                compatible = "nvidia,tegra124-pinmux";
+                reg = <0x70000868 0x164>,       /* Pad control registers */
+                      <0x70003000 0x434>;       /* Mux registers */
+        };
+
         /*
          * There are two serial driver i.e. 8250 based simple serial
          * driver and APB DMA based serial driver for higher baudrate
@@ -60,6 +117,11 @@
                 reg = <0x70006000 0x40>;
                 reg-shift = <2>;
                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA124_CLK_UARTA>;
+                resets = <&tegra_car 6>;
+                reset-names = "serial";
+                dmas = <&apbdma 8>, <&apbdma 8>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -68,6 +130,11 @@
                 reg = <0x70006040 0x40>;
                 reg-shift = <2>;
                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA124_CLK_UARTB>;
+                resets = <&tegra_car 7>;
+                reset-names = "serial";
+                dmas = <&apbdma 9>, <&apbdma 9>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -76,6 +143,11 @@
                 reg = <0x70006200 0x40>;
                 reg-shift = <2>;
                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA124_CLK_UARTC>;
+                resets = <&tegra_car 55>;
+                reset-names = "serial";
+                dmas = <&apbdma 10>, <&apbdma 10>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -84,6 +156,11 @@
                 reg = <0x70006300 0x40>;
                 reg-shift = <2>;
                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA124_CLK_UARTD>;
+                resets = <&tegra_car 65>;
+                reset-names = "serial";
+                dmas = <&apbdma 19>, <&apbdma 19>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -92,6 +169,201 @@
                 reg = <0x70006400 0x40>;
                 reg-shift = <2>;
                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA124_CLK_UARTE>;
+                resets = <&tegra_car 66>;
+                reset-names = "serial";
+                dmas = <&apbdma 20>, <&apbdma 20>;
+                dma-names = "rx", "tx";
+                status = "disabled";
+        };
+
+        pwm@7000a000 {
+                compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
+                reg = <0x7000a000 0x100>;
+                #pwm-cells = <2>;
+                clocks = <&tegra_car TEGRA124_CLK_PWM>;
+                resets = <&tegra_car 17>;
+                reset-names = "pwm";
+                status = "disabled";
+        };
+
+        i2c@7000c000 {
+                compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+                reg = <0x7000c000 0x100>;
+                interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clocks = <&tegra_car TEGRA124_CLK_I2C1>;
+                clock-names = "div-clk";
+                resets = <&tegra_car 12>;
+                reset-names = "i2c";
+                dmas = <&apbdma 21>, <&apbdma 21>;
+                dma-names = "rx", "tx";
+                status = "disabled";
+        };
+
+        i2c@7000c400 {
+                compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+                reg = <0x7000c400 0x100>;
+                interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clocks = <&tegra_car TEGRA124_CLK_I2C2>;
+                clock-names = "div-clk";
+                resets = <&tegra_car 54>;
+                reset-names = "i2c";
+                dmas = <&apbdma 22>, <&apbdma 22>;
+                dma-names = "rx", "tx";
+                status = "disabled";
+        };
+
+        i2c@7000c500 {
+                compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+                reg = <0x7000c500 0x100>;
+                interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clocks = <&tegra_car TEGRA124_CLK_I2C3>;
+                clock-names = "div-clk";
+                resets = <&tegra_car 67>;
+                reset-names = "i2c";
+                dmas = <&apbdma 23>, <&apbdma 23>;
+                dma-names = "rx", "tx";
+                status = "disabled";
+        };
+
+        i2c@7000c700 {
+                compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+                reg = <0x7000c700 0x100>;
+                interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clocks = <&tegra_car TEGRA124_CLK_I2C4>;
+                clock-names = "div-clk";
+                resets = <&tegra_car 103>;
+                reset-names = "i2c";
+                dmas = <&apbdma 26>, <&apbdma 26>;
+                dma-names = "rx", "tx";
+                status = "disabled";
+        };
+
+        i2c@7000d000 {
+                compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+                reg = <0x7000d000 0x100>;
+                interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clocks = <&tegra_car TEGRA124_CLK_I2C5>;
+                clock-names = "div-clk";
+                resets = <&tegra_car 47>;
+                reset-names = "i2c";
+                dmas = <&apbdma 24>, <&apbdma 24>;
+                dma-names = "rx", "tx";
+                status = "disabled";
+        };
+
+        i2c@7000d100 {
+                compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+                reg = <0x7000d100 0x100>;
+                interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clocks = <&tegra_car TEGRA124_CLK_I2C6>;
+                clock-names = "div-clk";
+                resets = <&tegra_car 166>;
+                reset-names = "i2c";
+                dmas = <&apbdma 30>, <&apbdma 30>;
+                dma-names = "rx", "tx";
+                status = "disabled";
+        };
+
+        spi@7000d400 {
+                compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+                reg = <0x7000d400 0x200>;
+                interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clocks = <&tegra_car TEGRA124_CLK_SBC1>;
+                clock-names = "spi";
+                resets = <&tegra_car 41>;
+                reset-names = "spi";
+                dmas = <&apbdma 15>, <&apbdma 15>;
+                dma-names = "rx", "tx";
+                status = "disabled";
+        };
+
+        spi@7000d600 {
+                compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+                reg = <0x7000d600 0x200>;
+                interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clocks = <&tegra_car TEGRA124_CLK_SBC2>;
+                clock-names = "spi";
+                resets = <&tegra_car 44>;
+                reset-names = "spi";
+                dmas = <&apbdma 16>, <&apbdma 16>;
+                dma-names = "rx", "tx";
+                status = "disabled";
+        };
+
+        spi@7000d800 {
+                compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+                reg = <0x7000d800 0x200>;
+                interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clocks = <&tegra_car TEGRA124_CLK_SBC3>;
+                clock-names = "spi";
+                resets = <&tegra_car 46>;
+                reset-names = "spi";
+                dmas = <&apbdma 17>, <&apbdma 17>;
+                dma-names = "rx", "tx";
+                status = "disabled";
+        };
+
+        spi@7000da00 {
+                compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+                reg = <0x7000da00 0x200>;
+                interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clocks = <&tegra_car TEGRA124_CLK_SBC4>;
+                clock-names = "spi";
+                resets = <&tegra_car 68>;
+                reset-names = "spi";
+                dmas = <&apbdma 18>, <&apbdma 18>;
+                dma-names = "rx", "tx";
+                status = "disabled";
+        };
+
+        spi@7000dc00 {
+                compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+                reg = <0x7000dc00 0x200>;
+                interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clocks = <&tegra_car TEGRA124_CLK_SBC5>;
+                clock-names = "spi";
+                resets = <&tegra_car 104>;
+                reset-names = "spi";
+                dmas = <&apbdma 27>, <&apbdma 27>;
+                dma-names = "rx", "tx";
+                status = "disabled";
+        };
+
+        spi@7000de00 {
+                compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+                reg = <0x7000de00 0x200>;
+                interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clocks = <&tegra_car TEGRA124_CLK_SBC6>;
+                clock-names = "spi";
+                resets = <&tegra_car 105>;
+                reset-names = "spi";
+                dmas = <&apbdma 28>, <&apbdma 28>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -99,11 +371,157 @@
                 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
                 reg = <0x7000e000 0x100>;
                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA124_CLK_RTC>;
         };
 
         pmc@7000e400 {
                 compatible = "nvidia,tegra124-pmc";
                 reg = <0x7000e400 0x400>;
+                clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
+                clock-names = "pclk", "clk32k_in";
+        };
+
+        sdhci@700b0000 {
+                compatible = "nvidia,tegra124-sdhci";
+                reg = <0x700b0000 0x200>;
+                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
+                resets = <&tegra_car 14>;
+                reset-names = "sdhci";
+                status = "disable";
+        };
+
+        sdhci@700b0200 {
+                compatible = "nvidia,tegra124-sdhci";
+                reg = <0x700b0200 0x200>;
+                interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
+                resets = <&tegra_car 9>;
+                reset-names = "sdhci";
+                status = "disable";
+        };
+
+        sdhci@700b0400 {
+                compatible = "nvidia,tegra124-sdhci";
+                reg = <0x700b0400 0x200>;
+                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
+                resets = <&tegra_car 69>;
+                reset-names = "sdhci";
+                status = "disable";
+        };
+
+        sdhci@700b0600 {
+                compatible = "nvidia,tegra124-sdhci";
+                reg = <0x700b0600 0x200>;
+                interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
+                resets = <&tegra_car 15>;
+                reset-names = "sdhci";
+                status = "disable";
+        };
+
+        ahub@70300000 {
+                compatible = "nvidia,tegra124-ahub";
+                reg = <0x70300000 0x200>,
+                      <0x70300800 0x800>,
+                      <0x70300200 0x600>;
+                interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
+                         <&tegra_car TEGRA124_CLK_APBIF>;
+                clock-names = "d_audio", "apbif";
+                resets = <&tegra_car 106>, /* d_audio */
+                         <&tegra_car 107>, /* apbif */
+                         <&tegra_car 30>,  /* i2s0 */
+                         <&tegra_car 11>,  /* i2s1 */
+                         <&tegra_car 18>,  /* i2s2 */
+                         <&tegra_car 101>, /* i2s3 */
+                         <&tegra_car 102>, /* i2s4 */
+                         <&tegra_car 108>, /* dam0 */
+                         <&tegra_car 109>, /* dam1 */
+                         <&tegra_car 110>, /* dam2 */
+                         <&tegra_car 10>,  /* spdif */
+                         <&tegra_car 153>, /* amx */
+                         <&tegra_car 185>, /* amx1 */
+                         <&tegra_car 154>, /* adx */
+                         <&tegra_car 180>, /* adx1 */
+                         <&tegra_car 186>, /* afc0 */
+                         <&tegra_car 187>, /* afc1 */
+                         <&tegra_car 188>, /* afc2 */
+                         <&tegra_car 189>, /* afc3 */
+                         <&tegra_car 190>, /* afc4 */
+                         <&tegra_car 191>; /* afc5 */
+                reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
+                              "i2s3", "i2s4", "dam0", "dam1", "dam2",
+                              "spdif", "amx", "amx1", "adx", "adx1",
+                              "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
+                dmas = <&apbdma 1>, <&apbdma 1>,
+                       <&apbdma 2>, <&apbdma 2>,
+                       <&apbdma 3>, <&apbdma 3>,
+                       <&apbdma 4>, <&apbdma 4>,
+                       <&apbdma 6>, <&apbdma 6>,
+                       <&apbdma 7>, <&apbdma 7>,
+                       <&apbdma 12>, <&apbdma 12>,
+                       <&apbdma 13>, <&apbdma 13>,
+                       <&apbdma 14>, <&apbdma 14>,
+                       <&apbdma 29>, <&apbdma 29>;
+                dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
+                            "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
+                            "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
+                            "rx9", "tx9";
+                ranges;
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                tegra_i2s0: i2s@70301000 {
+                        compatible = "nvidia,tegra124-i2s";
+                        reg = <0x70301000 0x100>;
+                        nvidia,ahub-cif-ids = <4 4>;
+                        clocks = <&tegra_car TEGRA124_CLK_I2S0>;
+                        resets = <&tegra_car 30>;
+                        reset-names = "i2s";
+                        status = "disabled";
+                };
+
+                tegra_i2s1: i2s@70301100 {
+                        compatible = "nvidia,tegra124-i2s";
+                        reg = <0x70301100 0x100>;
+                        nvidia,ahub-cif-ids = <5 5>;
+                        clocks = <&tegra_car TEGRA124_CLK_I2S1>;
+                        resets = <&tegra_car 11>;
+                        reset-names = "i2s";
+                        status = "disabled";
+                };
+
+                tegra_i2s2: i2s@70301200 {
+                        compatible = "nvidia,tegra124-i2s";
+                        reg = <0x70301200 0x100>;
+                        nvidia,ahub-cif-ids = <6 6>;
+                        clocks = <&tegra_car TEGRA124_CLK_I2S2>;
+                        resets = <&tegra_car 18>;
+                        reset-names = "i2s";
+                        status = "disabled";
+                };
+
+                tegra_i2s3: i2s@70301300 {
+                        compatible = "nvidia,tegra124-i2s";
+                        reg = <0x70301300 0x100>;
+                        nvidia,ahub-cif-ids = <7 7>;
+                        clocks = <&tegra_car TEGRA124_CLK_I2S3>;
+                        resets = <&tegra_car 101>;
+                        reset-names = "i2s";
+                        status = "disabled";
+                };
+
+                tegra_i2s4: i2s@70301400 {
+                        compatible = "nvidia,tegra124-i2s";
+                        reg = <0x70301400 0x100>;
+                        nvidia,ahub-cif-ids = <8 8>;
+                        clocks = <&tegra_car TEGRA124_CLK_I2S4>;
+                        resets = <&tegra_car 102>;
+                        reset-names = "i2s";
+                        status = "disabled";
+                };
         };
 
         cpus {
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index cbe89ff10686..8e0066ad9628 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -4,12 +4,17 @@
         model = "Toradex Colibri T20 512MB";
         compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
 
+        aliases {
+                rtc0 = "/i2c@7000d000/tps6586x@34";
+                rtc1 = "/rtc@7000e000";
+        };
+
         memory {
                 reg = <0x00000000 0x20000000>;
         };
 
-        host1x {
-                hdmi {
+        host1x@50000000 {
+                hdmi@54280000 {
                         vdd-supply = <&hdmi_vdd_reg>;
                         pll-supply = <&hdmi_pll_reg>;
 
@@ -19,7 +24,7 @@
                 };
         };
 
-        pinmux {
+        pinmux@70000014 {
                 pinctrl-names = "default";
                 pinctrl-0 = <&state_default>;
 
@@ -27,20 +32,20 @@
                         audio_refclk {
                                 nvidia,pins = "cdev1";
                                 nvidia,function = "plla_out";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         crt {
                                 nvidia,pins = "crtp";
                                 nvidia,function = "crt";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         dap3 {
                                 nvidia,pins = "dap3";
                                 nvidia,function = "dap3";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         displaya {
                                 nvidia,pins = "ld0", "ld1", "ld2", "ld3",
@@ -50,155 +55,163 @@
                                         "lhs", "lpw0", "lpw2", "lsc0",
                                         "lsc1", "lsck", "lsda", "lspi", "lvs";
                                 nvidia,function = "displaya";
-                                nvidia,tristate = <1>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         gpio_dte {
                                 nvidia,pins = "dte";
                                 nvidia,function = "rsvd1";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         gpio_gmi {
                                 nvidia,pins = "ata", "atc", "atd", "ate",
                                         "dap1", "dap2", "dap4", "gpu", "irrx",
                                         "irtx", "spia", "spib", "spic";
                                 nvidia,function = "gmi";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         gpio_pta {
                                 nvidia,pins = "pta";
                                 nvidia,function = "rsvd4";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         gpio_uac {
                                 nvidia,pins = "uac";
                                 nvidia,function = "rsvd2";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         hdint {
                                 nvidia,pins = "hdint";
                                 nvidia,function = "hdmi";
-                                nvidia,tristate = <1>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         i2c1 {
                                 nvidia,pins = "rm";
                                 nvidia,function = "i2c1";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         i2c3 {
                                 nvidia,pins = "dtf";
                                 nvidia,function = "i2c3";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         i2cddc {
                                 nvidia,pins = "ddc";
                                 nvidia,function = "i2c2";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         i2cp {
                                 nvidia,pins = "i2cp";
                                 nvidia,function = "i2cp";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         irda {
                                 nvidia,pins = "uad";
                                 nvidia,function = "irda";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         nand {
                                 nvidia,pins = "kbca", "kbcc", "kbcd",
                                         "kbce", "kbcf";
                                 nvidia,function = "nand";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         owc {
                                 nvidia,pins = "owc";
                                 nvidia,function = "owr";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         pmc {
                                 nvidia,pins = "pmc";
                                 nvidia,function = "pwr_on";
-                                nvidia,tristate = <0>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         pwm {
                                 nvidia,pins = "sdb", "sdc", "sdd";
                                 nvidia,function = "pwm";
-                                nvidia,tristate = <1>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         sdio4 {
                                 nvidia,pins = "atb", "gma", "gme";
                                 nvidia,function = "sdio4";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         spi1 {
                                 nvidia,pins = "spid", "spie", "spif";
                                 nvidia,function = "spi1";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         spi4 {
                                 nvidia,pins = "slxa", "slxc", "slxd", "slxk";
                                 nvidia,function = "spi4";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         uarta {
                                 nvidia,pins = "sdio1";
                                 nvidia,function = "uarta";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         uartd {
                                 nvidia,pins = "gmc";
                                 nvidia,function = "uartd";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         ulpi {
                                 nvidia,pins = "uaa", "uab", "uda";
                                 nvidia,function = "ulpi";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         ulpi_refclk {
                                 nvidia,pins = "cdev2";
                                 nvidia,function = "pllp_out4";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         usb_gpio {
                                 nvidia,pins = "spig", "spih";
                                 nvidia,function = "spi2_alt";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         vi {
                                 nvidia,pins = "dta", "dtb", "dtc", "dtd";
                                 nvidia,function = "vi";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         vi_sc {
                                 nvidia,pins = "csus";
                                 nvidia,function = "vi_sensor_clk";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                 };
         };
 
+        ac97: ac97@70002000 {
+                status = "okay";
+                nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+                        GPIO_ACTIVE_HIGH>;
+                nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0)
+                        GPIO_ACTIVE_HIGH>;
+        };
+
         i2c@7000c000 {
                 clock-frequency = <400000>;
         };
@@ -225,15 +238,15 @@
                         #gpio-cells = <2>;
                         gpio-controller;
 
-                        sys-supply = <&vdd_5v0_reg>;
+                        sys-supply = <&vdd_3v3_reg>;
                         vin-sm0-supply = <&sys_reg>;
                         vin-sm1-supply = <&sys_reg>;
                         vin-sm2-supply = <&sys_reg>;
                         vinldo01-supply = <&sm2_reg>;
-                        vinldo23-supply = <&sm2_reg>;
-                        vinldo4-supply = <&sm2_reg>;
-                        vinldo678-supply = <&sm2_reg>;
-                        vinldo9-supply = <&sm2_reg>;
+                        vinldo23-supply = <&vdd_3v3_reg>;
+                        vinldo4-supply = <&vdd_3v3_reg>;
+                        vinldo678-supply = <&vdd_3v3_reg>;
+                        vinldo9-supply = <&vdd_3v3_reg>;
 
                         regulators {
                                 #address-cells = <1>;
@@ -250,8 +263,8 @@
                                         reg = <1>;
                                         regulator-compatible = "sm0";
                                         regulator-name = "vdd_sm0,vdd_core";
-                                        regulator-min-microvolt = <1275000>;
-                                        regulator-max-microvolt = <1275000>;
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
                                         regulator-always-on;
                                 };
 
@@ -259,8 +272,8 @@
                                         reg = <2>;
                                         regulator-compatible = "sm1";
                                         regulator-name = "vdd_sm1,vdd_cpu";
-                                        regulator-min-microvolt = <1100000>;
-                                        regulator-max-microvolt = <1100000>;
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
                                         regulator-always-on;
                                 };
 
@@ -316,8 +329,8 @@
                                         reg = <10>;
                                         regulator-compatible = "ldo6";
                                         regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
                                 };
 
                                 hdmi_vdd_reg: regulator@11 {
@@ -362,7 +375,7 @@
                 };
         };
 
-        pmc {
+        pmc@7000e400 {
                 nvidia,suspend-mode = <1>;
                 nvidia,cpu-pwr-good-time = <5000>;
                 nvidia,cpu-pwr-off-time = <5000>;
@@ -442,14 +455,6 @@
                 };
         };
 
-        ac97: ac97 {
-                status = "okay";
-                nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
-                        GPIO_ACTIVE_HIGH>;
-                nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0)
-                        GPIO_ACTIVE_HIGH>;
-        };
-
         usb@c5004000 {
                 status = "okay";
                 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
@@ -471,7 +476,7 @@
                 #address-cells = <1>;
                 #size-cells = <0>;
 
-                clk32k_in: clock {
+                clk32k_in: clock@0 {
                         compatible = "fixed-clock";
                         reg=<0>;
                         #clock-cells = <0>;
@@ -479,37 +484,17 @@
                 };
         };
 
-        sound {
-                compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
-                                 "nvidia,tegra-audio-wm9712";
-                nvidia,model = "Colibri T20 AC97 Audio";
-
-                nvidia,audio-routing =
-                        "Headphone", "HPOUTL",
-                        "Headphone", "HPOUTR",
-                        "LineIn", "LINEINL",
-                        "LineIn", "LINEINR",
-                        "Mic", "MIC1";
-
-                nvidia,ac97-controller = <&ac97>;
-
-                clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
-                         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
-                         <&tegra_car TEGRA20_CLK_CDEV1>;
-                clock-names = "pll_a", "pll_a_out0", "mclk";
-        };
-
         regulators {
                 compatible = "simple-bus";
                 #address-cells = <1>;
                 #size-cells = <0>;
 
-                vdd_5v0_reg: regulator@100 {
+                vdd_3v3_reg: regulator@100 {
                         compatible = "regulator-fixed";
                         reg = <100>;
-                        regulator-name = "vdd_5v0";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
+                        regulator-name = "vdd_3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
                         regulator-always-on;
                 };
 
@@ -525,4 +510,24 @@
                         gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
                 };
         };
+
+        sound {
+                compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
+                                 "nvidia,tegra-audio-wm9712";
+                nvidia,model = "Colibri T20 AC97 Audio";
+
+                nvidia,audio-routing =
+                        "Headphone", "HPOUTL",
+                        "Headphone", "HPOUTR",
+                        "LineIn", "LINEINL",
+                        "LineIn", "LINEINR",
+                        "Mic", "MIC1";
+
+                nvidia,ac97-controller = <&ac97>;
+
+                clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+                         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA20_CLK_CDEV1>;
+                clock-names = "pll_a", "pll_a_out0", "mclk";
+        };
 };
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index e156ab30e763..3fb1f50f6d46 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -1,17 +1,31 @@
 /dts-v1/;
 
+#include <dt-bindings/input/input.h>
 #include "tegra20.dtsi"
 
 / {
         model = "NVIDIA Tegra20 Harmony evaluation board";
         compatible = "nvidia,harmony", "nvidia,tegra20";
 
+        aliases {
+                rtc0 = "/i2c@7000d000/tps6586x@34";
+                rtc1 = "/rtc@7000e000";
+        };
+
         memory {
                 reg = <0x00000000 0x40000000>;
         };
 
-        host1x {
-                hdmi {
+        host1x@50000000 {
+                dc@54200000 {
+                        rgb {
+                                status = "okay";
+
+                                nvidia,panel = <&panel>;
+                        };
+                };
+
+                hdmi@54280000 {
                         status = "okay";
 
                         vdd-supply = <&hdmi_vdd_reg>;
@@ -23,7 +37,7 @@
                 };
         };
 
-        pinmux {
+        pinmux@70000014 {
                 pinctrl-names = "default";
                 pinctrl-0 = <&state_default>;
 
@@ -184,50 +198,50 @@
                                         "gmb", "gmc", "gmd", "gme", "gpu7",
                                         "gpv", "i2cp", "pta", "rm", "slxa",
                                         "slxk", "spia", "spib", "uac";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_ck32 {
                                 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
                                         "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
-                                nvidia,pull = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                         };
                         conf_csus {
                                 nvidia,pins = "csus", "spid", "spif";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_crtp {
                                 nvidia,pins = "crtp", "dap2", "dap3", "dap4",
                                         "dtc", "dte", "dtf", "gpu", "sdio1",
                                         "slxc", "slxd", "spdi", "spdo", "spig",
                                         "uda";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_ddc {
                                 nvidia,pins = "ddc", "dta", "dtd", "kbca",
                                         "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
                                         "sdc";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_hdint {
                                 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
                                         "lpw1", "lsc1", "lsck", "lsda", "lsdi",
                                         "lvp0", "owc", "sdb";
-                                nvidia,tristate = <1>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_irrx {
                                 nvidia,pins = "irrx", "irtx", "sdd", "spic",
                                         "spie", "spih", "uaa", "uab", "uad",
                                         "uca", "ucb";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_lc {
                                 nvidia,pins = "lc", "ls";
-                                nvidia,pull = <2>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                         };
                         conf_ld0 {
                                 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
@@ -237,12 +251,12 @@
                                         "lhp1", "lhp2", "lhs", "lm0", "lpp",
                                         "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
                                         "lvs", "pmc";
-                                nvidia,tristate = <0>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_ld17_0 {
                                 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
                                         "ld23_22";
-                                nvidia,pull = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                         };
                 };
         };
@@ -255,6 +269,10 @@
                 status = "okay";
         };
 
+        pwm: pwm@7000a000 {
+                status = "okay";
+        };
+
         i2c@7000c000 {
                 status = "okay";
                 clock-frequency = <400000>;
@@ -415,7 +433,124 @@
                 };
         };
 
-        pmc {
+        kbc@7000e200 {
+                status = "okay";
+                nvidia,debounce-delay-ms = <2>;
+                nvidia,repeat-delay-ms = <160>;
+                nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
+                nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
+                linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W)
+                                MATRIX_KEY(0x00, 0x03, KEY_S)
+                                MATRIX_KEY(0x00, 0x04, KEY_A)
+                                MATRIX_KEY(0x00, 0x05, KEY_Z)
+                                MATRIX_KEY(0x00, 0x07, KEY_FN)
+                                MATRIX_KEY(0x01, 0x07, KEY_MENU)
+                                MATRIX_KEY(0x02, 0x06, KEY_LEFTALT)
+                                MATRIX_KEY(0x02, 0x07, KEY_RIGHTALT)
+                                MATRIX_KEY(0x03, 0x00, KEY_5)
+                                MATRIX_KEY(0x03, 0x01, KEY_4)
+                                MATRIX_KEY(0x03, 0x02, KEY_R)
+                                MATRIX_KEY(0x03, 0x03, KEY_E)
+                                MATRIX_KEY(0x03, 0x04, KEY_F)
+                                MATRIX_KEY(0x03, 0x05, KEY_D)
+                                MATRIX_KEY(0x03, 0x06, KEY_X)
+                                MATRIX_KEY(0x04, 0x00, KEY_7)
+                                MATRIX_KEY(0x04, 0x01, KEY_6)
+                                MATRIX_KEY(0x04, 0x02, KEY_T)
+                                MATRIX_KEY(0x04, 0x03, KEY_H)
+                                MATRIX_KEY(0x04, 0x04, KEY_G)
+                                MATRIX_KEY(0x04, 0x05, KEY_V)
+                                MATRIX_KEY(0x04, 0x06, KEY_C)
+                                MATRIX_KEY(0x04, 0x07, KEY_SPACE)
+                                MATRIX_KEY(0x05, 0x00, KEY_9)
+                                MATRIX_KEY(0x05, 0x01, KEY_8)
+                                MATRIX_KEY(0x05, 0x02, KEY_U)
+                                MATRIX_KEY(0x05, 0x03, KEY_Y)
+                                MATRIX_KEY(0x05, 0x04, KEY_J)
+                                MATRIX_KEY(0x05, 0x05, KEY_N)
+                                MATRIX_KEY(0x05, 0x06, KEY_B)
+                                MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH)
+                                MATRIX_KEY(0x06, 0x00, KEY_MINUS)
+                                MATRIX_KEY(0x06, 0x01, KEY_0)
+                                MATRIX_KEY(0x06, 0x02, KEY_O)
+                                MATRIX_KEY(0x06, 0x03, KEY_I)
+                                MATRIX_KEY(0x06, 0x04, KEY_L)
+                                MATRIX_KEY(0x06, 0x05, KEY_K)
+                                MATRIX_KEY(0x06, 0x06, KEY_COMMA)
+                                MATRIX_KEY(0x06, 0x07, KEY_M)
+                                MATRIX_KEY(0x07, 0x01, KEY_EQUAL)
+                                MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE)
+                                MATRIX_KEY(0x07, 0x03, KEY_ENTER)
+                                MATRIX_KEY(0x07, 0x07, KEY_MENU)
+                                MATRIX_KEY(0x08, 0x04, KEY_LEFTSHIFT)
+                                MATRIX_KEY(0x08, 0x05, KEY_RIGHTSHIFT)
+                                MATRIX_KEY(0x09, 0x05, KEY_LEFTCTRL)
+                                MATRIX_KEY(0x09, 0x07, KEY_RIGHTCTRL)
+                                MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE)
+                                MATRIX_KEY(0x0B, 0x01, KEY_P)
+                                MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE)
+                                MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON)
+                                MATRIX_KEY(0x0B, 0x04, KEY_SLASH)
+                                MATRIX_KEY(0x0B, 0x05, KEY_DOT)
+                                MATRIX_KEY(0x0C, 0x00, KEY_F10)
+                                MATRIX_KEY(0x0C, 0x01, KEY_F9)
+                                MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE)
+                                MATRIX_KEY(0x0C, 0x03, KEY_3)
+                                MATRIX_KEY(0x0C, 0x04, KEY_2)
+                                MATRIX_KEY(0x0C, 0x05, KEY_UP)
+                                MATRIX_KEY(0x0C, 0x06, KEY_PRINT)
+                                MATRIX_KEY(0x0C, 0x07, KEY_PAUSE)
+                                MATRIX_KEY(0x0D, 0x00, KEY_INSERT)
+                                MATRIX_KEY(0x0D, 0x01, KEY_DELETE)
+                                MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP )
+                                MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN)
+                                MATRIX_KEY(0x0D, 0x05, KEY_RIGHT)
+                                MATRIX_KEY(0x0D, 0x06, KEY_DOWN)
+                                MATRIX_KEY(0x0D, 0x07, KEY_LEFT)
+                                MATRIX_KEY(0x0E, 0x00, KEY_F11)
+                                MATRIX_KEY(0x0E, 0x01, KEY_F12)
+                                MATRIX_KEY(0x0E, 0x02, KEY_F8)
+                                MATRIX_KEY(0x0E, 0x03, KEY_Q)
+                                MATRIX_KEY(0x0E, 0x04, KEY_F4)
+                                MATRIX_KEY(0x0E, 0x05, KEY_F3)
+                                MATRIX_KEY(0x0E, 0x06, KEY_1)
+                                MATRIX_KEY(0x0E, 0x07, KEY_F7)
+                                MATRIX_KEY(0x0F, 0x00, KEY_ESC)
+                                MATRIX_KEY(0x0F, 0x01, KEY_GRAVE)
+                                MATRIX_KEY(0x0F, 0x02, KEY_F5)
+                                MATRIX_KEY(0x0F, 0x03, KEY_TAB)
+                                MATRIX_KEY(0x0F, 0x04, KEY_F1)
+                                MATRIX_KEY(0x0F, 0x05, KEY_F2)
+                                MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK)
+                                MATRIX_KEY(0x0F, 0x07, KEY_F6)
+                                MATRIX_KEY(0x14, 0x00, KEY_KP7)
+                                MATRIX_KEY(0x15, 0x00, KEY_KP9)
+                                MATRIX_KEY(0x15, 0x01, KEY_KP8)
+                                MATRIX_KEY(0x15, 0x02, KEY_KP4)
+                                MATRIX_KEY(0x15, 0x04, KEY_KP1)
+                                MATRIX_KEY(0x16, 0x01, KEY_KPSLASH)
+                                MATRIX_KEY(0x16, 0x02, KEY_KP6)
+                                MATRIX_KEY(0x16, 0x03, KEY_KP5)
+                                MATRIX_KEY(0x16, 0x04, KEY_KP3)
+                                MATRIX_KEY(0x16, 0x05, KEY_KP2)
+                                MATRIX_KEY(0x16, 0x07, KEY_KP0)
+                                MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK)
+                                MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS)
+                                MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS)
+                                MATRIX_KEY(0x1B, 0x05, KEY_KPDOT)
+                                MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP)
+                                MATRIX_KEY(0x1D, 0x03, KEY_HOME)
+                                MATRIX_KEY(0x1D, 0x04, KEY_END)
+                                MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSUP)
+                                MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN)
+                                MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSDOWN)
+                                MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK)
+                                MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK)
+                                MATRIX_KEY(0x1E, 0x02, KEY_MUTE)
+                                MATRIX_KEY(0x1F, 0x04, KEY_QUESTION)>;
+        };
+
+        pmc@7000e400 {
                 nvidia,invert-interrupt;
                 nvidia,suspend-mode = <1>;
                 nvidia,cpu-pwr-good-time = <5000>;
@@ -425,7 +560,7 @@
                 nvidia,sys-clock-req-active-high;
         };
 
-        pcie-controller {
+        pcie-controller@80003000 {
                 pex-clk-supply = <&pci_clk_reg>;
                 vdd-supply = <&pci_vdd_reg>;
                 status = "okay";
@@ -483,12 +618,23 @@
                 bus-width = <8>;
         };
 
+        backlight: backlight {
+                compatible = "pwm-backlight";
+
+                enable-gpios = <&gpio TEGRA_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
+                power-supply = <&vdd_bl_reg>;
+                pwms = <&pwm 0 5000000>;
+
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+        };
+
         clocks {
                 compatible = "simple-bus";
                 #address-cells = <1>;
                 #size-cells = <0>;
 
-                clk32k_in: clock {
+                clk32k_in: clock@0 {
                         compatible = "fixed-clock";
                         reg=<0>;
                         #clock-cells = <0>;
@@ -502,126 +648,18 @@
                 power {
                         label = "Power";
                         gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
-                        linux,code = <116>; /* KEY_POWER */
+                        linux,code = <KEY_POWER>;
                         gpio-key,wakeup;
                 };
         };
 
-        kbc {
-                status = "okay";
-                nvidia,debounce-delay-ms = <2>;
-                nvidia,repeat-delay-ms = <160>;
-                nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
-                nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
-                linux,keymap = <0x00020011      /* KEY_W */
-                                0x0003001F      /* KEY_S */
-                                0x0004001E      /* KEY_A */
-                                0x0005002C      /* KEY_Z */
-                                0x000701D0      /* KEY_FN */
-                                0x0107008B      /* KEY_MENU */
-                                0x02060038      /* KEY_LEFTALT */
-                                0x02070064      /* KEY_RIGHTALT */
-                                0x03000006      /* KEY_5 */
-                                0x03010005      /* KEY_4 */
-                                0x03020013      /* KEY_R */
-                                0x03030012      /* KEY_E */
-                                0x03040021      /* KEY_F */
-                                0x03050020      /* KEY_D */
-                                0x0306002D      /* KEY_X */
-                                0x04000008      /* KEY_7 */
-                                0x04010007      /* KEY_6 */
-                                0x04020014      /* KEY_T */
-                                0x04030023      /* KEY_H */
-                                0x04040022      /* KEY_G */
-                                0x0405002F      /* KEY_V */
-                                0x0406002E      /* KEY_C */
-                                0x04070039      /* KEY_SPACE */
-                                0x0500000A      /* KEY_9 */
-                                0x05010009      /* KEY_8 */
-                                0x05020016      /* KEY_U */
-                                0x05030015      /* KEY_Y */
-                                0x05040024      /* KEY_J */
-                                0x05050031      /* KEY_N */
-                                0x05060030      /* KEY_B */
-                                0x0507002B      /* KEY_BACKSLASH */
-                                0x0600000C      /* KEY_MINUS */
-                                0x0601000B      /* KEY_0 */
-                                0x06020018      /* KEY_O */
-                                0x06030017      /* KEY_I */
-                                0x06040026      /* KEY_L */
-                                0x06050025      /* KEY_K */
-                                0x06060033      /* KEY_COMMA */
-                                0x06070032      /* KEY_M */
-                                0x0701000D      /* KEY_EQUAL */
-                                0x0702001B      /* KEY_RIGHTBRACE */
-                                0x0703001C      /* KEY_ENTER */
-                                0x0707008B      /* KEY_MENU */
-                                0x0804002A      /* KEY_LEFTSHIFT */
-                                0x08050036      /* KEY_RIGHTSHIFT */
-                                0x0905001D      /* KEY_LEFTCTRL */
-                                0x09070061      /* KEY_RIGHTCTRL */
-                                0x0B00001A      /* KEY_LEFTBRACE */
-                                0x0B010019      /* KEY_P */
-                                0x0B020028      /* KEY_APOSTROPHE */
-                                0x0B030027      /* KEY_SEMICOLON */
-                                0x0B040035      /* KEY_SLASH */
-                                0x0B050034      /* KEY_DOT */
-                                0x0C000044      /* KEY_F10 */
-                                0x0C010043      /* KEY_F9 */
-                                0x0C02000E      /* KEY_BACKSPACE */
-                                0x0C030004      /* KEY_3 */
-                                0x0C040003      /* KEY_2 */
-                                0x0C050067      /* KEY_UP */
-                                0x0C0600D2      /* KEY_PRINT */
-                                0x0C070077      /* KEY_PAUSE */
-                                0x0D00006E      /* KEY_INSERT */
-                                0x0D01006F      /* KEY_DELETE */
-                                0x0D030068      /* KEY_PAGEUP */
-                                0x0D04006D      /* KEY_PAGEDOWN */
-                                0x0D05006A      /* KEY_RIGHT */
-                                0x0D06006C      /* KEY_DOWN */
-                                0x0D070069      /* KEY_LEFT */
-                                0x0E000057      /* KEY_F11 */
-                                0x0E010058      /* KEY_F12 */
-                                0x0E020042      /* KEY_F8 */
-                                0x0E030010      /* KEY_Q */
-                                0x0E04003E      /* KEY_F4 */
-                                0x0E05003D      /* KEY_F3 */
-                                0x0E060002      /* KEY_1 */
-                                0x0E070041      /* KEY_F7 */
-                                0x0F000001      /* KEY_ESC */
-                                0x0F010029      /* KEY_GRAVE */
-                                0x0F02003F      /* KEY_F5 */
-                                0x0F03000F      /* KEY_TAB */
-                                0x0F04003B      /* KEY_F1 */
-                                0x0F05003C      /* KEY_F2 */
-                                0x0F06003A      /* KEY_CAPSLOCK */
-                                0x0F070040      /* KEY_F6 */
-                                0x14000047      /* KEY_KP7 */
-                                0x15000049      /* KEY_KP9 */
-                                0x15010048      /* KEY_KP8 */
-                                0x1502004B      /* KEY_KP4 */
-                                0x1504004F      /* KEY_KP1 */
-                                0x1601004E      /* KEY_KPSLASH */
-                                0x1602004D      /* KEY_KP6 */
-                                0x1603004C      /* KEY_KP5 */
-                                0x16040051      /* KEY_KP3 */
-                                0x16050050      /* KEY_KP2 */
-                                0x16070052      /* KEY_KP0 */
-                                0x1B010037      /* KEY_KPASTERISK */
-                                0x1B03004A      /* KEY_KPMINUS */
-                                0x1B04004E      /* KEY_KPPLUS */
-                                0x1B050053      /* KEY_KPDOT */
-                                0x1C050073      /* KEY_VOLUMEUP */
-                                0x1D030066      /* KEY_HOME */
-                                0x1D04006B      /* KEY_END */
-                                0x1D0500E1      /* KEY_BRIGHTNESSUP */
-                                0x1D060072      /* KEY_VOLUMEDOWN */
-                                0x1D0700E0      /* KEY_BRIGHTNESSDOWN */
-                                0x1E000045      /* KEY_NUMLOCK */
-                                0x1E010046      /* KEY_SCROLLLOCK */
-                                0x1E020071      /* KEY_MUTE */
-                                0x1F0400D6>;    /* KEY_QUESTION */
+        panel: panel {
+                compatible = "auo,b101aw03", "simple-panel";
+
+                power-supply = <&vdd_pnl_reg>;
+                enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
+
+                backlight = <&backlight>;
         };
 
         regulators {
@@ -667,7 +705,7 @@
                         enable-active-high;
                 };
 
-                regulator@4 {
+                vdd_pnl_reg: regulator@4 {
                         compatible = "regulator-fixed";
                         reg = <4>;
                         regulator-name = "vdd_pnl";
@@ -677,7 +715,7 @@
                         enable-active-high;
                 };
 
-                regulator@5 {
+                vdd_bl_reg: regulator@5 {
                         compatible = "regulator-fixed";
                         reg = <5>;
                         regulator-name = "vdd_bl";
diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts b/arch/arm/boot/dts/tegra20-iris-512.dts
index f2222bd74eab..8cfb83f42e1f 100644
--- a/arch/arm/boot/dts/tegra20-iris-512.dts
+++ b/arch/arm/boot/dts/tegra20-iris-512.dts
@@ -6,61 +6,61 @@
         model = "Toradex Colibri T20 512MB on Iris";
         compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20";
 
-        host1x {
-                hdmi {
+        host1x@50000000 {
+                hdmi@54280000 {
                         status = "okay";
                 };
         };
 
-        pinmux {
+        pinmux@70000014 {
                 state_default: pinmux {
                         hdint {
-                                nvidia,tristate = <0>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
 
                         i2cddc {
-                                nvidia,tristate = <0>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
 
                         sdio4 {
-                                nvidia,tristate = <0>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
 
                         uarta {
-                                nvidia,tristate = <0>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
 
                         uartd {
-                                nvidia,tristate = <0>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                 };
         };
 
-        usb@c5000000 {
+        serial@70006000 {
                 status = "okay";
         };
 
-        usb-phy@c5000000 {
+        serial@70006300 {
                 status = "okay";
         };
 
-        usb@c5008000 {
+        i2c_ddc: i2c@7000c400 {
                 status = "okay";
         };
 
-        usb-phy@c5008000 {
+        usb@c5000000 {
                 status = "okay";
         };
 
-        serial@70006000 {
+        usb-phy@c5000000 {
                 status = "okay";
         };
 
-        serial@70006300 {
+        usb@c5008000 {
                 status = "okay";
         };
 
-        i2c_ddc: i2c@7000c400 {
+        usb-phy@c5008000 {
                 status = "okay";
         };
 
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts
index 7580578903cf..6d3a4cbc36cc 100644
--- a/arch/arm/boot/dts/tegra20-medcom-wide.dts
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts
@@ -6,7 +6,7 @@
         model = "Avionic Design Medcom-Wide board";
         compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20";
 
-        pwm {
+        pwm@7000a000 {
                 status = "okay";
         };
 
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index e57fb3aefc2a..c7cd8e6802d7 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -1,17 +1,23 @@
 /dts-v1/;
 
+#include <dt-bindings/input/input.h>
 #include "tegra20.dtsi"
 
 / {
         model = "Toshiba AC100 / Dynabook AZ";
         compatible = "compal,paz00", "nvidia,tegra20";
 
+        aliases {
+                rtc0 = "/i2c@7000d000/tps6586x@34";
+                rtc1 = "/rtc@7000e000";
+        };
+
         memory {
                 reg = <0x00000000 0x20000000>;
         };
 
-        host1x {
-                hdmi {
+        host1x@50000000 {
+                hdmi@54280000 {
                         status = "okay";
 
                         vdd-supply = <&hdmi_vdd_reg>;
@@ -23,7 +29,7 @@
                 };
         };
 
-        pinmux {
+        pinmux@70000014 {
                 pinctrl-names = "default";
                 pinctrl-0 = <&state_default>;
 
@@ -177,39 +183,39 @@
                                         "gpu", "gpu7", "gpv", "i2cp", "pta",
                                         "rm", "sdio1", "slxk", "spdo", "uac",
                                         "uda";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_ck32 {
                                 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
                                         "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
-                                nvidia,pull = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                         };
                         conf_crtp {
                                 nvidia,pins = "crtp", "dap3", "dap4", "dtb",
                                         "dtc", "dte", "slxa", "slxc", "slxd",
                                         "spdi";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_csus {
                                 nvidia,pins = "csus", "spia", "spib", "spid",
                                         "spif";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_ddc {
                                 nvidia,pins = "ddc", "irrx", "irtx", "kbca",
                                         "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
                                         "spic", "spig", "uaa", "uab";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_dta {
                                 nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
                                         "spie", "spih", "uad", "uca", "ucb";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_hdint {
                                 nvidia,pins = "hdint", "ld0", "ld1", "ld2",
@@ -218,23 +224,23 @@
                                         "ld13", "ld14", "ld15", "ld16", "ld17",
                                         "ldc", "ldi", "lhs", "lsc0", "lspi",
                                         "lvs", "pmc";
-                                nvidia,tristate = <0>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_lc {
                                 nvidia,pins = "lc", "ls";
-                                nvidia,pull = <2>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                         };
                         conf_lcsn {
                                 nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
                                         "lm0", "lm1", "lpp", "lpw0", "lpw1",
                                         "lpw2", "lsc1", "lsck", "lsda", "lsdi",
                                         "lvp0", "lvp1", "sdb";
-                                nvidia,tristate = <1>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_ld17_0 {
                                 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
                                         "ld23_22";
-                                nvidia,pull = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                         };
                 };
         };
@@ -268,7 +274,7 @@
                 clock-frequency = <100000>;
         };
 
-        nvec {
+        nvec@7000c500 {
                 compatible = "nvidia,nvec";
                 reg = <0x7000c500 0x100>;
                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
@@ -417,7 +423,7 @@
                 };
         };
 
-        pmc {
+        pmc@7000e400 {
                 nvidia,invert-interrupt;
                 nvidia,suspend-mode = <1>;
                 nvidia,cpu-pwr-good-time = <2000>;
@@ -474,7 +480,7 @@
                 #address-cells = <1>;
                 #size-cells = <0>;
 
-                clk32k_in: clock {
+                clk32k_in: clock@0 {
                         compatible = "fixed-clock";
                         reg=<0>;
                         #clock-cells = <0>;
@@ -488,7 +494,7 @@
                 power {
                         label = "Power";
                         gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
-                        linux,code = <116>; /* KEY_POWER */
+                        linux,code = <KEY_POWER>;
                         gpio-key,wakeup;
                 };
         };
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts
index d7a358a6a647..29051a2ae0ae 100644
--- a/arch/arm/boot/dts/tegra20-plutux.dts
+++ b/arch/arm/boot/dts/tegra20-plutux.dts
@@ -6,8 +6,8 @@
         model = "Avionic Design Plutux board";
         compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20";
 
-        host1x {
-                hdmi {
+        host1x@50000000 {
+                hdmi@54280000 {
                         status = "okay";
                 };
         };
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 315aae26c3cd..a11b6e7b4759 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -1,17 +1,23 @@
 /dts-v1/;
 
+#include <dt-bindings/input/input.h>
 #include "tegra20.dtsi"
 
 / {
         model = "NVIDIA Seaboard";
         compatible = "nvidia,seaboard", "nvidia,tegra20";
 
+        aliases {
+                rtc0 = "/i2c@7000d000/tps6586x@34";
+                rtc1 = "/rtc@7000e000";
+        };
+
         memory {
                 reg = <0x00000000 0x40000000>;
         };
 
-        host1x {
-                hdmi {
+        host1x@50000000 {
+                hdmi@54280000 {
                         status = "okay";
 
                         vdd-supply = <&hdmi_vdd_reg>;
@@ -23,7 +29,7 @@
                 };
         };
 
-        pinmux {
+        pinmux@70000014 {
                 pinctrl-names = "default";
                 pinctrl-0 = <&state_default>;
 
@@ -189,53 +195,53 @@
                                         "irtx", "pta", "rm", "sdc", "sdd",
                                         "slxd", "slxk", "spdi", "spdo", "uac",
                                         "uad", "uca", "ucb", "uda";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_ate {
                                 nvidia,pins = "ate", "csus", "dap3",
                                         "gpv", "owc", "slxc", "spib", "spid",
                                         "spie";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_ck32 {
                                 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
                                         "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
-                                nvidia,pull = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                         };
                         conf_crtp {
                                 nvidia,pins = "crtp", "gmb", "slxa", "spia",
                                         "spig", "spih";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_dta {
                                 nvidia,pins = "dta", "dtb", "dtc", "dtd";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_dte {
                                 nvidia,pins = "dte", "spif";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_hdint {
                                 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
                                         "lpw1", "lsc1", "lsck", "lsda", "lsdi",
                                         "lvp0";
-                                nvidia,tristate = <1>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_kbca {
                                 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
                                         "kbce", "kbcf", "sdio1", "spic", "uaa",
                                         "uab";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_lc {
                                 nvidia,pins = "lc", "ls";
-                                nvidia,pull = <2>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                         };
                         conf_ld0 {
                                 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
@@ -245,22 +251,22 @@
                                         "lhp1", "lhp2", "lhs", "lm0", "lpp",
                                         "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
                                         "lvs", "pmc", "sdb";
-                                nvidia,tristate = <0>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_ld17_0 {
                                 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
                                         "ld23_22";
-                                nvidia,pull = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                         };
                         drive_sdio1 {
                                 nvidia,pins = "drive_sdio1";
-                                nvidia,high-speed-mode = <0>;
-                                nvidia,schmitt = <0>;
-                                nvidia,low-power-mode = <3>;
+                                nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+                                nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
                                 nvidia,pull-down-strength = <31>;
                                 nvidia,pull-up-strength = <31>;
-                                nvidia,slew-rate-rising = <3>;
-                                nvidia,slew-rate-falling = <3>;
+                                nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+                                nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
                         };
                 };
 
@@ -386,6 +392,13 @@
                 status = "okay";
                 clock-frequency = <400000>;
 
+                magnetometer@c {
+                        compatible = "ak,ak8975";
+                        reg = <0xc>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>;
+                };
+
                 pmic: tps6586x@34 {
                         compatible = "ti,tps6586x";
                         reg = <0x34>;
@@ -507,16 +520,149 @@
                         compatible = "onnn,nct1008";
                         reg = <0x4c>;
                 };
+        };
 
-                magnetometer@c {
-                        compatible = "ak,ak8975";
-                        reg = <0xc>;
-                        interrupt-parent = <&gpio>;
-                        interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>;
-                };
+        kbc@7000e200 {
+                status = "okay";
+                nvidia,debounce-delay-ms = <32>;
+                nvidia,repeat-delay-ms = <160>;
+                nvidia,ghost-filter;
+                nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
+                nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
+                linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W)
+                                MATRIX_KEY(0x00, 0x03, KEY_S)
+                                MATRIX_KEY(0x00, 0x04, KEY_A)
+                                MATRIX_KEY(0x00, 0x05, KEY_Z)
+                                MATRIX_KEY(0x00, 0x07, KEY_FN)
+
+                                MATRIX_KEY(0x01, 0x07, KEY_LEFTMETA)
+                                MATRIX_KEY(0x02, 0x06, KEY_RIGHTALT)
+                                MATRIX_KEY(0x02, 0x07, KEY_LEFTALT)
+
+                                MATRIX_KEY(0x03, 0x00, KEY_5)
+                                MATRIX_KEY(0x03, 0x01, KEY_4)
+                                MATRIX_KEY(0x03, 0x02, KEY_R)
+                                MATRIX_KEY(0x03, 0x03, KEY_E)
+                                MATRIX_KEY(0x03, 0x04, KEY_F)
+                                MATRIX_KEY(0x03, 0x05, KEY_D)
+                                MATRIX_KEY(0x03, 0x06, KEY_X)
+
+                                MATRIX_KEY(0x04, 0x00, KEY_7)
+                                MATRIX_KEY(0x04, 0x01, KEY_6)
+                                MATRIX_KEY(0x04, 0x02, KEY_T)
+                                MATRIX_KEY(0x04, 0x03, KEY_H)
+                                MATRIX_KEY(0x04, 0x04, KEY_G)
+                                MATRIX_KEY(0x04, 0x05, KEY_V)
+                                MATRIX_KEY(0x04, 0x06, KEY_C)
+                                MATRIX_KEY(0x04, 0x07, KEY_SPACE)
+
+                                MATRIX_KEY(0x05, 0x00, KEY_9)
+                                MATRIX_KEY(0x05, 0x01, KEY_8)
+                                MATRIX_KEY(0x05, 0x02, KEY_U)
+                                MATRIX_KEY(0x05, 0x03, KEY_Y)
+                                MATRIX_KEY(0x05, 0x04, KEY_J)
+                                MATRIX_KEY(0x05, 0x05, KEY_N)
+                                MATRIX_KEY(0x05, 0x06, KEY_B)
+                                MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH)
+
+                                MATRIX_KEY(0x06, 0x00, KEY_MINUS)
+                                MATRIX_KEY(0x06, 0x01, KEY_0)
+                                MATRIX_KEY(0x06, 0x02, KEY_O)
+                                MATRIX_KEY(0x06, 0x03, KEY_I)
+                                MATRIX_KEY(0x06, 0x04, KEY_L)
+                                MATRIX_KEY(0x06, 0x05, KEY_K)
+                                MATRIX_KEY(0x06, 0x06, KEY_COMMA)
+                                MATRIX_KEY(0x06, 0x07, KEY_M)
+
+                                MATRIX_KEY(0x07, 0x01, KEY_EQUAL)
+                                MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE)
+                                MATRIX_KEY(0x07, 0x03, KEY_ENTER)
+                                MATRIX_KEY(0x07, 0x07, KEY_MENU)
+
+                                MATRIX_KEY(0x08, 0x04, KEY_RIGHTSHIFT)
+                                MATRIX_KEY(0x08, 0x05, KEY_LEFTSHIFT)
+
+                                MATRIX_KEY(0x09, 0x05, KEY_RIGHTCTRL)
+                                MATRIX_KEY(0x09, 0x07, KEY_LEFTCTRL)
+
+                                MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE)
+                                MATRIX_KEY(0x0B, 0x01, KEY_P)
+                                MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE)
+                                MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON)
+                                MATRIX_KEY(0x0B, 0x04, KEY_SLASH)
+                                MATRIX_KEY(0x0B, 0x05, KEY_DOT)
+
+                                MATRIX_KEY(0x0C, 0x00, KEY_F10)
+                                MATRIX_KEY(0x0C, 0x01, KEY_F9)
+                                MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE)
+                                MATRIX_KEY(0x0C, 0x03, KEY_3)
+                                MATRIX_KEY(0x0C, 0x04, KEY_2)
+                                MATRIX_KEY(0x0C, 0x05, KEY_UP)
+                                MATRIX_KEY(0x0C, 0x06, KEY_PRINT)
+                                MATRIX_KEY(0x0C, 0x07, KEY_PAUSE)
+
+                                MATRIX_KEY(0x0D, 0x00, KEY_INSERT)
+                                MATRIX_KEY(0x0D, 0x01, KEY_DELETE)
+                                MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP )
+                                MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN)
+                                MATRIX_KEY(0x0D, 0x05, KEY_RIGHT)
+                                MATRIX_KEY(0x0D, 0x06, KEY_DOWN)
+                                MATRIX_KEY(0x0D, 0x07, KEY_LEFT)
+
+                                MATRIX_KEY(0x0E, 0x00, KEY_F11)
+                                MATRIX_KEY(0x0E, 0x01, KEY_F12)
+                                MATRIX_KEY(0x0E, 0x02, KEY_F8)
+                                MATRIX_KEY(0x0E, 0x03, KEY_Q)
+                                MATRIX_KEY(0x0E, 0x04, KEY_F4)
+                                MATRIX_KEY(0x0E, 0x05, KEY_F3)
+                                MATRIX_KEY(0x0E, 0x06, KEY_1)
+                                MATRIX_KEY(0x0E, 0x07, KEY_F7)
+
+                                MATRIX_KEY(0x0F, 0x00, KEY_ESC)
+                                MATRIX_KEY(0x0F, 0x01, KEY_GRAVE)
+                                MATRIX_KEY(0x0F, 0x02, KEY_F5)
+                                MATRIX_KEY(0x0F, 0x03, KEY_TAB)
+                                MATRIX_KEY(0x0F, 0x04, KEY_F1)
+                                MATRIX_KEY(0x0F, 0x05, KEY_F2)
+                                MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK)
+                                MATRIX_KEY(0x0F, 0x07, KEY_F6)
+
+                                /* Software Handled Function Keys */
+                                MATRIX_KEY(0x14, 0x00, KEY_KP7)
+
+                                MATRIX_KEY(0x15, 0x00, KEY_KP9)
+                                MATRIX_KEY(0x15, 0x01, KEY_KP8)
+                                MATRIX_KEY(0x15, 0x02, KEY_KP4)
+                                MATRIX_KEY(0x15, 0x04, KEY_KP1)
+
+                                MATRIX_KEY(0x16, 0x01, KEY_KPSLASH)
+                                MATRIX_KEY(0x16, 0x02, KEY_KP6)
+                                MATRIX_KEY(0x16, 0x03, KEY_KP5)
+                                MATRIX_KEY(0x16, 0x04, KEY_KP3)
+                                MATRIX_KEY(0x16, 0x05, KEY_KP2)
+                                MATRIX_KEY(0x16, 0x07, KEY_KP0)
+
+                                MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK)
+                                MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS)
+                                MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS)
+                                MATRIX_KEY(0x1B, 0x05, KEY_KPDOT)
+
+                                MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP)
+
+                                MATRIX_KEY(0x1D, 0x03, KEY_HOME)
+                                MATRIX_KEY(0x1D, 0x04, KEY_END)
+                                MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSDOWN)
+                                MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN)
+                                MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSUP)
+
+                                MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK)
+                                MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK)
+                                MATRIX_KEY(0x1E, 0x02, KEY_MUTE)
+
+                                MATRIX_KEY(0x1F, 0x04, KEY_HELP)>;
         };
 
-        pmc {
+        pmc@7000e400 {
                 nvidia,invert-interrupt;
                 nvidia,suspend-mode = <1>;
                 nvidia,cpu-pwr-good-time = <5000>;
@@ -621,7 +767,7 @@
                 #address-cells = <1>;
                 #size-cells = <0>;
 
-                clk32k_in: clock {
+                clk32k_in: clock@0 {
                         compatible = "fixed-clock";
                         reg=<0>;
                         #clock-cells = <0>;
@@ -635,7 +781,7 @@
                 power {
                         label = "Power";
                         gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
-                        linux,code = <116>; /* KEY_POWER */
+                        linux,code = <KEY_POWER>;
                         gpio-key,wakeup;
                 };
 
@@ -649,145 +795,6 @@
                 };
         };
 
-        kbc {
-                status = "okay";
-                nvidia,debounce-delay-ms = <32>;
-                nvidia,repeat-delay-ms = <160>;
-                nvidia,ghost-filter;
-                nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
-                nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
-                linux,keymap = <0x00020011      /* KEY_W */
-                                0x0003001F      /* KEY_S */
-                                0x0004001E      /* KEY_A */
-                                0x0005002C      /* KEY_Z */
-                                0x000701d0      /* KEY_FN */
-
-                                0x0107007D      /* KEY_LEFTMETA */
-                                0x02060064      /* KEY_RIGHTALT */
-                                0x02070038      /* KEY_LEFTALT */
-
-                                0x03000006      /* KEY_5 */
-                                0x03010005      /* KEY_4 */
-                                0x03020013      /* KEY_R */
-                                0x03030012      /* KEY_E */
-                                0x03040021      /* KEY_F */
-                                0x03050020      /* KEY_D */
-                                0x0306002D      /* KEY_X */
-
-                                0x04000008      /* KEY_7 */
-                                0x04010007      /* KEY_6 */
-                                0x04020014      /* KEY_T */
-                                0x04030023      /* KEY_H */
-                                0x04040022      /* KEY_G */
-                                0x0405002F      /* KEY_V */
-                                0x0406002E      /* KEY_C */
-                                0x04070039      /* KEY_SPACE */
-
-                                0x0500000A      /* KEY_9 */
-                                0x05010009      /* KEY_8 */
-                                0x05020016      /* KEY_U */
-                                0x05030015      /* KEY_Y */
-                                0x05040024      /* KEY_J */
-                                0x05050031      /* KEY_N */
-                                0x05060030      /* KEY_B */
-                                0x0507002B      /* KEY_BACKSLASH */
-
-                                0x0600000C      /* KEY_MINUS */
-                                0x0601000B      /* KEY_0 */
-                                0x06020018      /* KEY_O */
-                                0x06030017      /* KEY_I */
-                                0x06040026      /* KEY_L */
-                                0x06050025      /* KEY_K */
-                                0x06060033      /* KEY_COMMA */
-                                0x06070032      /* KEY_M */
-
-                                0x0701000D      /* KEY_EQUAL */
-                                0x0702001B      /* KEY_RIGHTBRACE */
-                                0x0703001C      /* KEY_ENTER */
-                                0x0707008B      /* KEY_MENU */
-
-                                0x08040036      /* KEY_RIGHTSHIFT */
-                                0x0805002A      /* KEY_LEFTSHIFT */
-
-                                0x09050061      /* KEY_RIGHTCTRL */
-                                0x0907001D      /* KEY_LEFTCTRL */
-
-                                0x0B00001A      /* KEY_LEFTBRACE */
-                                0x0B010019      /* KEY_P */
-                                0x0B020028      /* KEY_APOSTROPHE */
-                                0x0B030027      /* KEY_SEMICOLON */
-                                0x0B040035      /* KEY_SLASH */
-                                0x0B050034      /* KEY_DOT */
-
-                                0x0C000044      /* KEY_F10 */
-                                0x0C010043      /* KEY_F9 */
-                                0x0C02000E      /* KEY_BACKSPACE */
-                                0x0C030004      /* KEY_3 */
-                                0x0C040003      /* KEY_2 */
-                                0x0C050067      /* KEY_UP */
-                                0x0C0600D2      /* KEY_PRINT */
-                                0x0C070077      /* KEY_PAUSE */
-
-                                0x0D00006E      /* KEY_INSERT */
-                                0x0D01006F      /* KEY_DELETE */
-                                0x0D030068      /* KEY_PAGEUP  */
-                                0x0D04006D      /* KEY_PAGEDOWN */
-                                0x0D05006A      /* KEY_RIGHT */
-                                0x0D06006C      /* KEY_DOWN */
-                                0x0D070069      /* KEY_LEFT */
-
-                                0x0E000057      /* KEY_F11 */
-                                0x0E010058      /* KEY_F12 */
-                                0x0E020042      /* KEY_F8 */
-                                0x0E030010      /* KEY_Q */
-                                0x0E04003E      /* KEY_F4 */
-                                0x0E05003D      /* KEY_F3 */
-                                0x0E060002      /* KEY_1 */
-                                0x0E070041      /* KEY_F7 */
-
-                                0x0F000001      /* KEY_ESC */
-                                0x0F010029      /* KEY_GRAVE */
-                                0x0F02003F      /* KEY_F5 */
-                                0x0F03000F      /* KEY_TAB */
-                                0x0F04003B      /* KEY_F1 */
-                                0x0F05003C      /* KEY_F2 */
-                                0x0F06003A      /* KEY_CAPSLOCK */
-                                0x0F070040      /* KEY_F6 */
-
-                                /* Software Handled Function Keys */
-                                0x14000047      /* KEY_KP7 */
-
-                                0x15000049      /* KEY_KP9 */
-                                0x15010048      /* KEY_KP8 */
-                                0x1502004B      /* KEY_KP4 */
-                                0x1504004F      /* KEY_KP1 */
-
-                                0x1601004E      /* KEY_KPSLASH */
-                                0x1602004D      /* KEY_KP6 */
-                                0x1603004C      /* KEY_KP5 */
-                                0x16040051      /* KEY_KP3 */
-                                0x16050050      /* KEY_KP2 */
-                                0x16070052      /* KEY_KP0 */
-
-                                0x1B010037      /* KEY_KPASTERISK */
-                                0x1B03004A      /* KEY_KPMINUS */
-                                0x1B04004E      /* KEY_KPPLUS */
-                                0x1B050053      /* KEY_KPDOT */
-
-                                0x1C050073      /* KEY_VOLUMEUP */
-
-                                0x1D030066      /* KEY_HOME */
-                                0x1D04006B      /* KEY_END */
-                                0x1D0500E0      /* KEY_BRIGHTNESSDOWN */
-                                0x1D060072      /* KEY_VOLUMEDOWN */
-                                0x1D0700E1      /* KEY_BRIGHTNESSUP */
-
-                                0x1E000045      /* KEY_NUMLOCK */
-                                0x1E010046      /* KEY_SCROLLLOCK */
-                                0x1E020071      /* KEY_MUTE */
-
-                                0x1F04008A>;    /* KEY_HELP */
-        };
         regulators {
                 compatible = "simple-bus";
                 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index 7726dab3d08d..a1b0d965757f 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -4,12 +4,17 @@
         model = "Avionic Design Tamonten SOM";
         compatible = "ad,tamonten", "nvidia,tegra20";
 
+        aliases {
+                rtc0 = "/i2c@7000d000/tps6586x@34";
+                rtc1 = "/rtc@7000e000";
+        };
+
         memory {
                 reg = <0x00000000 0x20000000>;
         };
 
-        host1x {
-                hdmi {
+        host1x@50000000 {
+                hdmi@54280000 {
                         vdd-supply = <&hdmi_vdd_reg>;
                         pll-supply = <&hdmi_pll_reg>;
 
@@ -19,7 +24,7 @@
                 };
         };
 
-        pinmux {
+        pinmux@70000014 {
                 pinctrl-names = "default";
                 pinctrl-0 = <&state_default>;
 
@@ -176,50 +181,50 @@
                                         "gmb", "gmc", "gmd", "gme", "gpu7",
                                         "gpv", "i2cp", "pta", "rm", "slxa",
                                         "slxk", "spia", "spib", "uac";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_ck32 {
                                 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
                                         "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
-                                nvidia,pull = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                         };
                         conf_csus {
                                 nvidia,pins = "csus", "spid", "spif";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_crtp {
                                 nvidia,pins = "crtp", "dap2", "dap3", "dap4",
                                         "dtc", "dte", "dtf", "gpu", "sdio1",
                                         "slxc", "slxd", "spdi", "spdo", "spig",
                                         "uda";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_ddc {
                                 nvidia,pins = "ddc", "dta", "dtd", "kbca",
                                         "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
                                         "sdc";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_hdint {
                                 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
                                         "lpw1", "lsc1", "lsck", "lsda", "lsdi",
                                         "lvp0", "owc", "sdb";
-                                nvidia,tristate = <1>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_irrx {
                                 nvidia,pins = "irrx", "irtx", "sdd", "spic",
                                         "spie", "spih", "uaa", "uab", "uad",
                                         "uca", "ucb";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_lc {
                                 nvidia,pins = "lc", "ls";
-                                nvidia,pull = <2>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                         };
                         conf_ld0 {
                                 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
@@ -229,12 +234,12 @@
                                         "lhp1", "lhp2", "lhs", "lm0", "lpp",
                                         "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
                                         "lvs", "pmc";
-                                nvidia,tristate = <0>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_ld17_0 {
                                 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
                                         "ld23_22";
-                                nvidia,pull = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                         };
                 };
 
@@ -457,7 +462,7 @@
                 };
         };
 
-        pmc {
+        pmc@7000e400 {
                 nvidia,invert-interrupt;
                 nvidia,suspend-mode = <1>;
                 nvidia,cpu-pwr-good-time = <5000>;
@@ -467,7 +472,7 @@
                 nvidia,sys-clock-req-active-high;
         };
 
-        pcie-controller {
+        pcie-controller@80003000 {
                 pex-clk-supply = <&pci_clk_reg>;
                 vdd-supply = <&pci_vdd_reg>;
         };
@@ -492,7 +497,7 @@
                 #address-cells = <1>;
                 #size-cells = <0>;
 
-                clk32k_in: clock {
+                clk32k_in: clock@0 {
                         compatible = "fixed-clock";
                         reg=<0>;
                         #clock-cells = <0>;
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts
index 3ada3cb67f07..890562c667fb 100644
--- a/arch/arm/boot/dts/tegra20-tec.dts
+++ b/arch/arm/boot/dts/tegra20-tec.dts
@@ -6,8 +6,8 @@
         model = "Avionic Design Tamonten Evaluation Carrier";
         compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20";
 
-        host1x {
-                hdmi {
+        host1x@50000000 {
+                hdmi@54280000 {
                         status = "okay";
                 };
         };
@@ -32,7 +32,7 @@
                 };
         };
 
-        pcie-controller {
+        pcie-controller@80003000 {
                 status = "okay";
 
                 pci@1,0 {
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 78deea5c0d21..216fa6d50c65 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -1,17 +1,23 @@
 /dts-v1/;
 
+#include <dt-bindings/input/input.h>
 #include "tegra20.dtsi"
 
 / {
         model = "Compulab TrimSlice board";
         compatible = "compulab,trimslice", "nvidia,tegra20";
 
+        aliases {
+                rtc0 = "/i2c@7000c500/rtc@56";
+                rtc1 = "/rtc@7000e000";
+        };
+
         memory {
                 reg = <0x00000000 0x40000000>;
         };
 
-        host1x {
-                hdmi {
+        host1x@50000000 {
+                hdmi@54280000 {
                         status = "okay";
 
                         vdd-supply = <&hdmi_vdd_reg>;
@@ -23,7 +29,7 @@
                 };
         };
 
-        pinmux {
+        pinmux@70000014 {
                 pinctrl-names = "default";
                 pinctrl-0 = <&state_default>;
 
@@ -191,49 +197,49 @@
                                         "dtb", "dtc", "dtd", "dte", "gmb",
                                         "gme", "i2cp", "pta", "slxc", "slxd",
                                         "spdi", "spdo", "uda";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_atb {
                                 nvidia,pins = "atb", "cdev1", "cdev2", "dap1",
                                         "gma", "gmc", "gmd", "gpu", "gpu7",
                                         "gpv", "sdio1", "slxa", "slxk", "uac";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_ck32 {
                                 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
                                         "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
-                                nvidia,pull = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                         };
                         conf_csus {
                                 nvidia,pins = "csus", "spia", "spib",
                                         "spid", "spif";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_ddc {
                                 nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_hdint {
                                 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
                                         "lpw1", "lsc1", "lsck", "lsda", "lsdi",
                                         "lvp0", "pmc";
-                                nvidia,tristate = <1>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_irrx {
                                 nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
                                         "kbcc", "kbcd", "kbce", "kbcf", "owc",
                                         "spic", "spie", "spig", "spih", "uaa",
                                         "uab", "uad", "uca", "ucb";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_lc {
                                 nvidia,pins = "lc", "ls";
-                                nvidia,pull = <2>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                         };
                         conf_ld0 {
                                 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
@@ -243,17 +249,17 @@
                                         "lhp1", "lhp2", "lhs", "lm0", "lpp",
                                         "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
                                         "lvs", "sdb";
-                                nvidia,tristate = <0>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_ld17_0 {
                                 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
                                         "ld23_22";
-                                nvidia,pull = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                         };
                         conf_spif {
                                 nvidia,pins = "spif";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                 };
         };
@@ -301,7 +307,7 @@
                 };
         };
 
-        pmc {
+        pmc@7000e400 {
                 nvidia,suspend-mode = <1>;
                 nvidia,cpu-pwr-good-time = <5000>;
                 nvidia,cpu-pwr-off-time = <5000>;
@@ -310,7 +316,7 @@
                 nvidia,sys-clock-req-active-high;
         };
 
-        pcie-controller {
+        pcie-controller@80003000 {
                 status = "okay";
                 pex-clk-supply = <&pci_clk_reg>;
                 vdd-supply = <&pci_vdd_reg>;
@@ -366,7 +372,7 @@
                 #address-cells = <1>;
                 #size-cells = <0>;
 
-                clk32k_in: clock {
+                clk32k_in: clock@0 {
                         compatible = "fixed-clock";
                         reg=<0>;
                         #clock-cells = <0>;
@@ -380,7 +386,7 @@
                 power {
                         label = "Power";
                         gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
-                        linux,code = <116>; /* KEY_POWER */
+                        linux,code = <KEY_POWER>;
                         gpio-key,wakeup;
                 };
         };
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index aab872cd0530..571d12e6ac2d 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -1,17 +1,23 @@
 /dts-v1/;
 
+#include <dt-bindings/input/input.h>
 #include "tegra20.dtsi"
 
 / {
         model = "NVIDIA Tegra20 Ventana evaluation board";
         compatible = "nvidia,ventana", "nvidia,tegra20";
 
+        aliases {
+                rtc0 = "/i2c@7000d000/tps6586x@34";
+                rtc1 = "/rtc@7000e000";
+        };
+
         memory {
                 reg = <0x00000000 0x40000000>;
         };
 
-        host1x {
-                hdmi {
+        host1x@50000000 {
+                hdmi@54280000 {
                         status = "okay";
 
                         vdd-supply = <&hdmi_vdd_reg>;
@@ -23,7 +29,7 @@
                 };
         };
 
-        pinmux {
+        pinmux@70000014 {
                 pinctrl-names = "default";
                 pinctrl-0 = <&state_default>;
 
@@ -189,50 +195,50 @@
                                         "irtx", "pta", "rm", "sdc", "sdd",
                                         "slxc", "slxd", "slxk", "spdi", "spdo",
                                         "uac", "uad", "uca", "ucb", "uda";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_ate {
                                 nvidia,pins = "ate", "csus", "dap3", "gmd",
                                         "gpv", "owc", "spia", "spib", "spic",
                                         "spid", "spie", "spig";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_ck32 {
                                 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
                                         "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
-                                nvidia,pull = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                         };
                         conf_crtp {
                                 nvidia,pins = "crtp", "gmb", "slxa", "spih";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_dta {
                                 nvidia,pins = "dta", "dtb", "dtc", "dtd";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_dte {
                                 nvidia,pins = "dte", "spif";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_hdint {
                                 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
                                         "lpw1", "lsck", "lsda", "lsdi", "lvp0";
-                                nvidia,tristate = <1>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_kbca {
                                 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
                                         "kbce", "kbcf", "sdio1", "uaa", "uab";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_lc {
                                 nvidia,pins = "lc", "ls";
-                                nvidia,pull = <2>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                         };
                         conf_ld0 {
                                 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
@@ -242,22 +248,22 @@
                                         "lhp1", "lhp2", "lhs", "lm0", "lpp",
                                         "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
                                         "lvp1", "lvs", "pmc", "sdb";
-                                nvidia,tristate = <0>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_ld17_0 {
                                 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
                                         "ld23_22";
-                                nvidia,pull = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                         };
                         drive_sdio1 {
                                 nvidia,pins = "drive_sdio1";
-                                nvidia,high-speed-mode = <0>;
-                                nvidia,schmitt = <1>;
-                                nvidia,low-power-mode = <3>;
+                                nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+                                nvidia,schmitt = <TEGRA_PIN_ENABLE>;
+                                nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
                                 nvidia,pull-down-strength = <31>;
                                 nvidia,pull-up-strength = <31>;
-                                nvidia,slew-rate-rising = <3>;
-                                nvidia,slew-rate-falling = <3>;
+                                nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+                                nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
                         };
                 };
 
@@ -492,7 +498,7 @@
                 };
         };
 
-        pmc {
+        pmc@7000e400 {
                 nvidia,invert-interrupt;
                 nvidia,suspend-mode = <1>;
                 nvidia,cpu-pwr-good-time = <2000>;
@@ -556,7 +562,7 @@
                 #address-cells = <1>;
                 #size-cells = <0>;
 
-                clk32k_in: clock {
+                clk32k_in: clock@0 {
                         compatible = "fixed-clock";
                         reg=<0>;
                         #clock-cells = <0>;
@@ -570,7 +576,7 @@
                 power {
                         label = "Power";
                         gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
-                        linux,code = <116>; /* KEY_POWER */
+                        linux,code = <KEY_POWER>;
                         gpio-key,wakeup;
                 };
         };
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index d33a73cf167c..1843725785c9 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -1,17 +1,23 @@
 /dts-v1/;
 
+#include <dt-bindings/input/input.h>
 #include "tegra20.dtsi"
 
 / {
         model = "NVIDIA Tegra20 Whistler evaluation board";
         compatible = "nvidia,whistler", "nvidia,tegra20";
 
+        aliases {
+                rtc0 = "/i2c@7000d000/max8907@3c";
+                rtc1 = "/rtc@7000e000";
+        };
+
         memory {
                 reg = <0x00000000 0x20000000>;
         };
 
-        host1x {
-                hdmi {
+        host1x@50000000 {
+                hdmi@54280000 {
                         status = "okay";
 
                         vdd-supply = <&hdmi_vdd_reg>;
@@ -23,7 +29,7 @@
                 };
         };
 
-        pinmux {
+        pinmux@70000014 {
                 pinctrl-names = "default";
                 pinctrl-0 = <&state_default>;
 
@@ -189,8 +195,8 @@
                                         "kbcf", "sdc", "sdd", "spie", "spig",
                                         "spih", "uaa", "uab", "uad", "uca",
                                         "ucb";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_atd {
                                 nvidia,pins = "atd", "ate", "cdev1", "csus",
@@ -198,54 +204,54 @@
                                         "dtf", "gpu", "gpu7", "gpv", "i2cp",
                                         "rm", "sdio1", "slxa", "slxc", "slxd",
                                         "slxk", "spdi", "spdo", "uac", "uda";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_cdev2 {
                                 nvidia,pins = "cdev2", "spia", "spib";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_ck32 {
                                 nvidia,pins = "ck32", "ddrc", "lc", "pmca",
                                         "pmcb", "pmcc", "pmcd", "xm2c",
                                         "xm2d";
-                                nvidia,pull = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                         };
                         conf_crtp {
                                 nvidia,pins = "crtp";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_dta {
                                 nvidia,pins = "dta", "dtb", "dtc", "dtd",
                                         "spid", "spif";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_gme {
                                 nvidia,pins = "gme", "owc", "pta", "spic";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_ld17_0 {
                                 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
                                         "ld23_22";
-                                nvidia,pull = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                         };
                         conf_ls {
                                 nvidia,pins = "ls", "pmce";
-                                nvidia,pull = <2>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                         };
                         drive_dap1 {
                                 nvidia,pins = "drive_dap1";
-                                nvidia,high-speed-mode = <0>;
-                                nvidia,schmitt = <1>;
-                                nvidia,low-power-mode = <0>;
+                                nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+                                nvidia,schmitt = <TEGRA_PIN_ENABLE>;
+                                nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_8>;
                                 nvidia,pull-down-strength = <0>;
                                 nvidia,pull-up-strength = <0>;
-                                nvidia,slew-rate-rising = <0>;
-                                nvidia,slew-rate-falling = <0>;
+                                nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+                                nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
                         };
                 };
         };
@@ -495,7 +501,20 @@
                 };
         };
 
-        pmc {
+        kbc@7000e200 {
+                status = "okay";
+                nvidia,debounce-delay-ms = <20>;
+                nvidia,repeat-delay-ms = <160>;
+                nvidia,kbc-row-pins = <0 1 2>;
+                nvidia,kbc-col-pins = <16 17>;
+                nvidia,wakeup-source;
+                linux,keymap = <MATRIX_KEY(0x00, 0x00, KEY_POWER)
+                                MATRIX_KEY(0x01, 0x00, KEY_HOME)
+                                MATRIX_KEY(0x01, 0x01, KEY_BACK)
+                                MATRIX_KEY(0x02, 0x01, KEY_MENU)>;
+        };
+
+        pmc@7000e400 {
                 nvidia,invert-interrupt;
                 nvidia,suspend-mode = <1>;
                 nvidia,cpu-pwr-good-time = <2000>;
@@ -543,7 +562,7 @@
                 #address-cells = <1>;
                 #size-cells = <0>;
 
-                clk32k_in: clock {
+                clk32k_in: clock@0 {
                         compatible = "fixed-clock";
                         reg=<0>;
                         #clock-cells = <0>;
@@ -551,25 +570,12 @@
                 };
         };
 
-        kbc {
-                status = "okay";
-                nvidia,debounce-delay-ms = <20>;
-                nvidia,repeat-delay-ms = <160>;
-                nvidia,kbc-row-pins = <0 1 2>;
-                nvidia,kbc-col-pins = <16 17>;
-                nvidia,wakeup-source;
-                linux,keymap = <0x00000074      /* KEY_POWER */
-                                0x01000066      /* KEY_HOME */
-                                0x0101009E      /* KEY_BACK */
-                                0x0201008B>;    /* KEY_MENU */
-        };
-
         regulators {
                 compatible = "simple-bus";
                 #address-cells = <1>;
                 #size-cells = <0>;
 
-                usb0_vbus_reg: regulator {
+                usb0_vbus_reg: regulator@0 {
                         compatible = "regulator-fixed";
                         reg = <0>;
                         regulator-name = "usb0_vbus";
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index c90d0aac3afe..480ecda3416b 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -1,5 +1,6 @@
 #include <dt-bindings/clock/tegra20-car.h>
 #include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-tegra.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
 #include "skeleton.dtsi"
@@ -16,7 +17,7 @@
                 serial4 = &uarte;
         };
 
-        host1x {
+        host1x@50000000 {
                 compatible = "nvidia,tegra20-host1x", "simple-bus";
                 reg = <0x50000000 0x00024000>;
                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
@@ -30,7 +31,7 @@
 
                 ranges = <0x54000000 0x54000000 0x04000000>;
 
-                mpe {
+                mpe@54040000 {
                         compatible = "nvidia,tegra20-mpe";
                         reg = <0x54040000 0x00040000>;
                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
@@ -39,7 +40,7 @@
                         reset-names = "mpe";
                 };
 
-                vi {
+                vi@54080000 {
                         compatible = "nvidia,tegra20-vi";
                         reg = <0x54080000 0x00040000>;
                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
@@ -48,7 +49,7 @@
                         reset-names = "vi";
                 };
 
-                epp {
+                epp@540c0000 {
                         compatible = "nvidia,tegra20-epp";
                         reg = <0x540c0000 0x00040000>;
                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
@@ -57,7 +58,7 @@
                         reset-names = "epp";
                 };
 
-                isp {
+                isp@54100000 {
                         compatible = "nvidia,tegra20-isp";
                         reg = <0x54100000 0x00040000>;
                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
@@ -66,7 +67,7 @@
                         reset-names = "isp";
                 };
 
-                gr2d {
+                gr2d@54140000 {
                         compatible = "nvidia,tegra20-gr2d";
                         reg = <0x54140000 0x00040000>;
                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
@@ -75,9 +76,9 @@
                         reset-names = "2d";
                 };
 
-                gr3d {
+                gr3d@54140000 {
                         compatible = "nvidia,tegra20-gr3d";
-                        reg = <0x54180000 0x00040000>;
+                        reg = <0x54140000 0x00040000>;
                         clocks = <&tegra_car TEGRA20_CLK_GR3D>;
                         resets = <&tegra_car 24>;
                         reset-names = "3d";
@@ -113,7 +114,7 @@
                         };
                 };
 
-                hdmi {
+                hdmi@54280000 {
                         compatible = "nvidia,tegra20-hdmi";
                         reg = <0x54280000 0x00040000>;
                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
@@ -125,7 +126,7 @@
                         status = "disabled";
                 };
 
-                tvo {
+                tvo@542c0000 {
                         compatible = "nvidia,tegra20-tvo";
                         reg = <0x542c0000 0x00040000>;
                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
@@ -133,9 +134,9 @@
                         status = "disabled";
                 };
 
-                dsi {
+                dsi@542c0000 {
                         compatible = "nvidia,tegra20-dsi";
-                        reg = <0x54300000 0x00040000>;
+                        reg = <0x542c0000 0x00040000>;
                         clocks = <&tegra_car TEGRA20_CLK_DSI>;
                         resets = <&tegra_car 48>;
                         reset-names = "dsi";
@@ -151,7 +152,7 @@
                 clocks = <&tegra_car TEGRA20_CLK_TWD>;
         };
 
-        intc: interrupt-controller {
+        intc: interrupt-controller@50041000 {
                 compatible = "arm,cortex-a9-gic";
                 reg = <0x50041000 0x1000
                        0x50040100 0x0100>;
@@ -159,7 +160,7 @@
                 #interrupt-cells = <3>;
         };
 
-        cache-controller {
+        cache-controller@50043000 {
                 compatible = "arm,pl310-cache";
                 reg = <0x50043000 0x1000>;
                 arm,data-latency = <5 5 2>;
@@ -178,14 +179,14 @@
                 clocks = <&tegra_car TEGRA20_CLK_TIMER>;
         };
 
-        tegra_car: clock {
+        tegra_car: clock@60006000 {
                 compatible = "nvidia,tegra20-car";
                 reg = <0x60006000 0x1000>;
                 #clock-cells = <1>;
                 #reset-cells = <1>;
         };
 
-        apbdma: dma {
+        apbdma: dma@6000a000 {
                 compatible = "nvidia,tegra20-apbdma";
                 reg = <0x6000a000 0x1200>;
                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
@@ -210,12 +211,12 @@
                 #dma-cells = <1>;
         };
 
-        ahb {
+        ahb@6000c004 {
                 compatible = "nvidia,tegra20-ahb";
                 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
         };
 
-        gpio: gpio {
+        gpio: gpio@6000d000 {
                 compatible = "nvidia,tegra20-gpio";
                 reg = <0x6000d000 0x1000>;
                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
@@ -231,7 +232,7 @@
                 interrupt-controller;
         };
 
-        pinmux: pinmux {
+        pinmux: pinmux@70000014 {
                 compatible = "nvidia,tegra20-pinmux";
                 reg = <0x70000014 0x10   /* Tri-state registers */
                        0x70000080 0x20   /* Mux registers */
@@ -239,12 +240,12 @@
                        0x70000868 0xa8>; /* Pad control registers */
         };
 
-        das {
+        das@70000c00 {
                 compatible = "nvidia,tegra20-das";
                 reg = <0x70000c00 0x80>;
         };
 
-        tegra_ac97: ac97 {
+        tegra_ac97: ac97@70002000 {
                 compatible = "nvidia,tegra20-ac97";
                 reg = <0x70002000 0x200>;
                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
@@ -352,7 +353,7 @@
                 status = "disabled";
         };
 
-        pwm: pwm {
+        pwm: pwm@7000a000 {
                 compatible = "nvidia,tegra20-pwm";
                 reg = <0x7000a000 0x100>;
                 #pwm-cells = <2>;
@@ -362,7 +363,7 @@
                 status = "disabled";
         };
 
-        rtc {
+        rtc@7000e000 {
                 compatible = "nvidia,tegra20-rtc";
                 reg = <0x7000e000 0x100>;
                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
@@ -503,7 +504,7 @@
                 status = "disabled";
         };
 
-        kbc {
+        kbc@7000e200 {
                 compatible = "nvidia,tegra20-kbc";
                 reg = <0x7000e200 0x100>;
                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
@@ -513,7 +514,7 @@
                 status = "disabled";
         };
 
-        pmc {
+        pmc@7000e400 {
                 compatible = "nvidia,tegra20-pmc";
                 reg = <0x7000e400 0x400>;
                 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
@@ -527,7 +528,7 @@
                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
         };
 
-        iommu {
+        iommu@7000f024 {
                 compatible = "nvidia,tegra20-gart";
                 reg = <0x7000f024 0x00000018    /* controller registers */
                        0x58000000 0x02000000>;  /* GART aperture */
@@ -540,7 +541,7 @@
                 #size-cells = <0>;
         };
 
-        pcie-controller {
+        pcie-controller@80003000 {
                 compatible = "nvidia,tegra20-pcie";
                 device_type = "pci";
                 reg = <0x80003000 0x00000800   /* PADS registers */
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index 08cad696e89f..e93fe45b7803 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -6,11 +6,16 @@
         model = "NVIDIA Tegra30 Beaver evaluation board";
         compatible = "nvidia,beaver", "nvidia,tegra30";
 
+        aliases {
+                rtc0 = "/i2c@7000d000/tps65911@2d";
+                rtc1 = "/rtc@7000e000";
+        };
+
         memory {
                 reg = <0x80000000 0x7ff00000>;
         };
 
-        pcie-controller {
+        pcie-controller@00003000 {
                 status = "okay";
                 pex-clk-supply = <&sys_3v3_pexs_reg>;
                 vdd-supply = <&ldo1_reg>;
@@ -31,8 +36,8 @@
                 };
         };
 
-        host1x {
-                hdmi {
+        host1x@50000000 {
+                hdmi@54280000 {
                         status = "okay";
 
                         vdd-supply = <&sys_3v3_reg>;
@@ -44,7 +49,7 @@
                 };
         };
 
-        pinmux {
+        pinmux@70000868 {
                 pinctrl-names = "default";
                 pinctrl-0 = <&state_default>;
 
@@ -52,8 +57,8 @@
                         sdmmc1_clk_pz0 {
                                 nvidia,pins = "sdmmc1_clk_pz0";
                                 nvidia,function = "sdmmc1";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         sdmmc1_cmd_pz1 {
                                 nvidia,pins =   "sdmmc1_cmd_pz1",
@@ -62,14 +67,14 @@
                                                 "sdmmc1_dat2_py5",
                                                 "sdmmc1_dat3_py4";
                                 nvidia,function = "sdmmc1";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         sdmmc3_clk_pa6 {
                                 nvidia,pins = "sdmmc3_clk_pa6";
                                 nvidia,function = "sdmmc3";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         sdmmc3_cmd_pa7 {
                                 nvidia,pins =   "sdmmc3_cmd_pa7",
@@ -78,15 +83,15 @@
                                                 "sdmmc3_dat2_pb5",
                                                 "sdmmc3_dat3_pb4";
                                 nvidia,function = "sdmmc3";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         sdmmc4_clk_pcc4 {
                                 nvidia,pins =   "sdmmc4_clk_pcc4",
                                                 "sdmmc4_rst_n_pcc3";
                                 nvidia,function = "sdmmc4";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         sdmmc4_dat0_paa0 {
                                 nvidia,pins =   "sdmmc4_dat0_paa0",
@@ -98,8 +103,8 @@
                                                 "sdmmc4_dat6_paa6",
                                                 "sdmmc4_dat7_paa7";
                                 nvidia,function = "sdmmc4";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         dap2_fs_pa2 {
                                 nvidia,pins =   "dap2_fs_pa2",
@@ -107,18 +112,18 @@
                                                 "dap2_din_pa4",
                                                 "dap2_dout_pa5";
                                 nvidia,function = "i2s1";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         pex_l1_prsnt_n_pdd4 {
                                 nvidia,pins =   "pex_l1_prsnt_n_pdd4",
                                                 "pex_l1_clkreq_n_pdd6";
-                                nvidia,pull = <2>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                         };
                         sdio3 {
                                 nvidia,pins = "drive_sdio3";
-                                nvidia,high-speed-mode = <0>;
-                                nvidia,schmitt = <0>;
+                                nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
                                 nvidia,pull-down-strength = <46>;
                                 nvidia,pull-up-strength = <42>;
                                 nvidia,slew-rate-rising = <1>;
@@ -159,7 +164,7 @@
                 status = "okay";
                 clock-frequency = <100000>;
 
-                rt5640: rt5640 {
+                rt5640: rt5640@1c {
                         compatible = "realtek,rt5640";
                         reg = <0x1c>;
                         interrupt-parent = <&gpio>;
@@ -168,19 +173,6 @@
                                 <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>;
                 };
 
-                tps62361 {
-                        compatible = "ti,tps62361";
-                        reg = <0x60>;
-
-                        regulator-name = "tps62361-vout";
-                        regulator-min-microvolt = <500000>;
-                        regulator-max-microvolt = <1500000>;
-                        regulator-boot-on;
-                        regulator-always-on;
-                        ti,vsel0-state-high;
-                        ti,vsel1-state-high;
-                };
-
                 pmic: tps65911@2d {
                         compatible = "ti,tps65911";
                         reg = <0x2d>;
@@ -284,6 +276,19 @@
                                 };
                         };
                 };
+
+                tps62361@60 {
+                        compatible = "ti,tps62361";
+                        reg = <0x60>;
+
+                        regulator-name = "tps62361-vout";
+                        regulator-min-microvolt = <500000>;
+                        regulator-max-microvolt = <1500000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                        ti,vsel0-state-high;
+                        ti,vsel1-state-high;
+                };
         };
 
         spi@7000da00 {
@@ -296,13 +301,7 @@
                 };
         };
 
-        ahub {
-                i2s@70080400 {
-                        status = "okay";
-                };
-        };
-
-        pmc {
+        pmc@7000e400 {
                 status = "okay";
                 nvidia,invert-interrupt;
                 nvidia,suspend-mode = <1>;
@@ -314,6 +313,12 @@
                 nvidia,sys-clock-req-active-high;
         };
 
+        ahub@70080000 {
+                i2s@70080400 {
+                        status = "okay";
+                };
+        };
+
         sdhci@78000000 {
                 status = "okay";
                 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
@@ -328,6 +333,15 @@
                 non-removable;
         };
 
+        usb@7d004000 {
+                status = "okay";
+        };
+
+        phy2: usb-phy@7d004000 {
+                vbus-supply = <&sys_3v3_reg>;
+                status = "okay";
+        };
+
         usb@7d008000 {
                 status = "okay";
         };
@@ -342,7 +356,7 @@
                 #address-cells = <1>;
                 #size-cells = <0>;
 
-                clk32k_in: clock {
+                clk32k_in: clock@0 {
                         compatible = "fixed-clock";
                         reg=<0>;
                         #clock-cells = <0>;
@@ -350,6 +364,19 @@
                 };
         };
 
+        gpio-leds {
+                compatible = "gpio-leds";
+
+                gpled1 {
+                        label = "LED1"; /* CR5A1 (blue) */
+                        gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>;
+                };
+                gpled2 {
+                        label = "LED2"; /* CR4A2 (green) */
+                        gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>;
+                };
+        };
+
         regulators {
                 compatible = "simple-bus";
                 #address-cells = <1>;
@@ -453,19 +480,6 @@
                 };
         };
 
-        gpio-leds {
-                compatible = "gpio-leds";
-
-                gpled1 {
-                        label = "LED1"; /* CR5A1 (blue) */
-                        gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>;
-                };
-                gpled2 {
-                        label = "LED2"; /* CR4A2 (green) */
-                        gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>;
-                };
-        };
-
         sound {
                 compatible = "nvidia,tegra-audio-rt5640-beaver",
                              "nvidia,tegra-audio-rt5640";
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
index 1082c5ed90d1..c9bfedcca6ed 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a02.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
@@ -8,6 +8,13 @@
         model = "NVIDIA Tegra30 Cardhu A02 evaluation board";
         compatible = "nvidia,cardhu-a02", "nvidia,cardhu", "nvidia,tegra30";
 
+        sdhci@78000400 {
+                status = "okay";
+                power-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
+                bus-width = <4>;
+                keep-power-in-suspend;
+        };
+
         regulators {
                 compatible = "simple-bus";
                 #address-cells = <1>;
@@ -83,12 +90,5 @@
                         gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>;
                 };
         };
-
-        sdhci@78000400 {
-                status = "okay";
-                power-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
-                bus-width = <4>;
-                keep-power-in-suspend;
-        };
 };
 
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
index bf012bddaafb..fadf55e46b2b 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
@@ -8,6 +8,13 @@
         model = "NVIDIA Tegra30 Cardhu A04 (A05, A06, A07) evaluation board";
         compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30";
 
+        sdhci@78000400 {
+                status = "okay";
+                power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
+                bus-width = <4>;
+                keep-power-in-suspend;
+        };
+
         regulators {
                 compatible = "simple-bus";
                 #address-cells = <1>;
@@ -95,11 +102,4 @@
                         gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
                 };
         };
-
-        sdhci@78000400 {
-                status = "okay";
-                power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
-                bus-width = <4>;
-                keep-power-in-suspend;
-        };
 };
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 5ea7dfa4d9fa..9104224124ee 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -27,11 +27,16 @@
         model = "NVIDIA Tegra30 Cardhu evaluation board";
         compatible = "nvidia,cardhu", "nvidia,tegra30";
 
+        aliases {
+                rtc0 = "/i2c@7000d000/tps6586x@34";
+                rtc1 = "/rtc@7000e000";
+        };
+
         memory {
                 reg = <0x80000000 0x40000000>;
         };
 
-        pcie-controller {
+        pcie-controller@00003000 {
                 status = "okay";
                 pex-clk-supply = <&pex_hvdd_3v3_reg>;
                 vdd-supply = <&ldo1_reg>;
@@ -51,7 +56,17 @@
                 };
         };
 
-        pinmux {
+        host1x@50000000 {
+                dc@54200000 {
+                        rgb {
+                                status = "okay";
+
+                                nvidia,panel = <&panel>;
+                        };
+                };
+        };
+
+        pinmux@70000868 {
                 pinctrl-names = "default";
                 pinctrl-0 = <&state_default>;
 
@@ -59,8 +74,8 @@
                         sdmmc1_clk_pz0 {
                                 nvidia,pins = "sdmmc1_clk_pz0";
                                 nvidia,function = "sdmmc1";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         sdmmc1_cmd_pz1 {
                                 nvidia,pins =   "sdmmc1_cmd_pz1",
@@ -69,14 +84,14 @@
                                                 "sdmmc1_dat2_py5",
                                                 "sdmmc1_dat3_py4";
                                 nvidia,function = "sdmmc1";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         sdmmc3_clk_pa6 {
                                 nvidia,pins = "sdmmc3_clk_pa6";
                                 nvidia,function = "sdmmc3";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         sdmmc3_cmd_pa7 {
                                 nvidia,pins =   "sdmmc3_cmd_pa7",
@@ -85,15 +100,15 @@
                                                 "sdmmc3_dat2_pb5",
                                                 "sdmmc3_dat3_pb4";
                                 nvidia,function = "sdmmc3";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         sdmmc4_clk_pcc4 {
                                 nvidia,pins =   "sdmmc4_clk_pcc4",
                                                 "sdmmc4_rst_n_pcc3";
                                 nvidia,function = "sdmmc4";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         sdmmc4_dat0_paa0 {
                                 nvidia,pins =   "sdmmc4_dat0_paa0",
@@ -105,8 +120,8 @@
                                                 "sdmmc4_dat6_paa6",
                                                 "sdmmc4_dat7_paa7";
                                 nvidia,function = "sdmmc4";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         dap2_fs_pa2 {
                                 nvidia,pins =   "dap2_fs_pa2",
@@ -114,17 +129,17 @@
                                                 "dap2_din_pa4",
                                                 "dap2_dout_pa5";
                                 nvidia,function = "i2s1";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         sdio3 {
                                 nvidia,pins = "drive_sdio3";
-                                nvidia,high-speed-mode = <0>;
-                                nvidia,schmitt = <0>;
+                                nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
                                 nvidia,pull-down-strength = <46>;
                                 nvidia,pull-up-strength = <42>;
-                                nvidia,slew-rate-rising = <1>;
-                                nvidia,slew-rate-falling = <1>;
+                                nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
+                                nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
                         };
                         uart3_txd_pw6 {
                                 nvidia,pins =   "uart3_txd_pw6",
@@ -132,8 +147,8 @@
                                                 "uart3_rts_n_pc0",
                                                 "uart3_rxd_pw7";
                                 nvidia,function = "uartc";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                 };
         };
@@ -147,7 +162,11 @@
                 status = "okay";
         };
 
-        i2c@7000c000 {
+        pwm@7000a000 {
+                status = "okay";
+        };
+
+        panelddc: i2c@7000c000 {
                 status = "okay";
                 clock-frequency = <100000>;
         };
@@ -302,7 +321,7 @@
                         interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>;
                 };
 
-                tps62361 {
+                tps62361@60 {
                         compatible = "ti,tps62361";
                         reg = <0x60>;
 
@@ -326,13 +345,7 @@
                 };
         };
 
-        ahub {
-                i2s@70080400 {
-                        status = "okay";
-                };
-        };
-
-        pmc {
+        pmc@7000e400 {
                 status = "okay";
                 nvidia,invert-interrupt;
                 nvidia,suspend-mode = <1>;
@@ -344,6 +357,12 @@
                 nvidia,sys-clock-req-active-high;
         };
 
+        ahub@70080000 {
+                i2s@70080400 {
+                        status = "okay";
+                };
+        };
+
         sdhci@78000000 {
                 status = "okay";
                 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
@@ -367,12 +386,23 @@
                 status = "okay";
         };
 
+        backlight: backlight {
+                compatible = "pwm-backlight";
+
+                enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+                power-supply = <&vdd_bl_reg>;
+                pwms = <&pwm 0 5000000>;
+
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+        };
+
         clocks {
                 compatible = "simple-bus";
                 #address-cells = <1>;
                 #size-cells = <0>;
 
-                clk32k_in: clock {
+                clk32k_in: clock@0 {
                         compatible = "fixed-clock";
                         reg=<0>;
                         #clock-cells = <0>;
@@ -380,6 +410,16 @@
                 };
         };
 
+        panel: panel {
+                compatible = "chunghwa,claa101wb01", "simple-panel";
+                ddc-i2c-bus = <&panelddc>;
+
+                power-supply = <&vdd_pnl1_reg>;
+                enable-gpios = <&gpio TEGRA_GPIO(L, 2) GPIO_ACTIVE_HIGH>;
+
+                backlight = <&backlight>;
+        };
+
         regulators {
                 compatible = "simple-bus";
                 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 31259b09e7cc..ed8e7700b46d 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -1,5 +1,6 @@
 #include <dt-bindings/clock/tegra30-car.h>
 #include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-tegra.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
 #include "skeleton.dtsi"
@@ -16,7 +17,7 @@
                 serial4 = &uarte;
         };
 
-        pcie-controller {
+        pcie-controller@00003000 {
                 compatible = "nvidia,tegra30-pcie";
                 device_type = "pci";
                 reg = <0x00003000 0x00000800   /* PADS registers */
@@ -89,7 +90,7 @@
                 };
         };
 
-        host1x {
+        host1x@50000000 {
                 compatible = "nvidia,tegra30-host1x", "simple-bus";
                 reg = <0x50000000 0x00024000>;
                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
@@ -103,7 +104,7 @@
 
                 ranges = <0x54000000 0x54000000 0x04000000>;
 
-                mpe {
+                mpe@54040000 {
                         compatible = "nvidia,tegra30-mpe";
                         reg = <0x54040000 0x00040000>;
                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
@@ -112,7 +113,7 @@
                         reset-names = "mpe";
                 };
 
-                vi {
+                vi@54080000 {
                         compatible = "nvidia,tegra30-vi";
                         reg = <0x54080000 0x00040000>;
                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
@@ -121,7 +122,7 @@
                         reset-names = "vi";
                 };
 
-                epp {
+                epp@540c0000 {
                         compatible = "nvidia,tegra30-epp";
                         reg = <0x540c0000 0x00040000>;
                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
@@ -130,7 +131,7 @@
                         reset-names = "epp";
                 };
 
-                isp {
+                isp@54100000 {
                         compatible = "nvidia,tegra30-isp";
                         reg = <0x54100000 0x00040000>;
                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
@@ -139,7 +140,7 @@
                         reset-names = "isp";
                 };
 
-                gr2d {
+                gr2d@54140000 {
                         compatible = "nvidia,tegra30-gr2d";
                         reg = <0x54140000 0x00040000>;
                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
@@ -148,7 +149,7 @@
                         clocks = <&tegra_car TEGRA30_CLK_GR2D>;
                 };
 
-                gr3d {
+                gr3d@54180000 {
                         compatible = "nvidia,tegra30-gr3d";
                         reg = <0x54180000 0x00040000>;
                         clocks = <&tegra_car TEGRA30_CLK_GR3D
@@ -189,7 +190,7 @@
                         };
                 };
 
-                hdmi {
+                hdmi@54280000 {
                         compatible = "nvidia,tegra30-hdmi";
                         reg = <0x54280000 0x00040000>;
                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
@@ -201,7 +202,7 @@
                         status = "disabled";
                 };
 
-                tvo {
+                tvo@542c0000 {
                         compatible = "nvidia,tegra30-tvo";
                         reg = <0x542c0000 0x00040000>;
                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
@@ -209,7 +210,7 @@
                         status = "disabled";
                 };
 
-                dsi {
+                dsi@54300000 {
                         compatible = "nvidia,tegra30-dsi";
                         reg = <0x54300000 0x00040000>;
                         clocks = <&tegra_car TEGRA30_CLK_DSIA>;
@@ -227,7 +228,7 @@
                 clocks = <&tegra_car TEGRA30_CLK_TWD>;
         };
 
-        intc: interrupt-controller {
+        intc: interrupt-controller@50041000 {
                 compatible = "arm,cortex-a9-gic";
                 reg = <0x50041000 0x1000
                        0x50040100 0x0100>;
@@ -235,7 +236,7 @@
                 #interrupt-cells = <3>;
         };
 
-        cache-controller {
+        cache-controller@50043000 {
                 compatible = "arm,pl310-cache";
                 reg = <0x50043000 0x1000>;
                 arm,data-latency = <6 6 2>;
@@ -256,14 +257,14 @@
                 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
         };
 
-        tegra_car: clock {
+        tegra_car: clock@60006000 {
                 compatible = "nvidia,tegra30-car";
                 reg = <0x60006000 0x1000>;
                 #clock-cells = <1>;
                 #reset-cells = <1>;
         };
 
-        apbdma: dma {
+        apbdma: dma@6000a000 {
                 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
                 reg = <0x6000a000 0x1400>;
                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
@@ -304,12 +305,12 @@
                 #dma-cells = <1>;
         };
 
-        ahb: ahb {
+        ahb: ahb@6000c004 {
                 compatible = "nvidia,tegra30-ahb";
                 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
         };
 
-        gpio: gpio {
+        gpio: gpio@6000d000 {
                 compatible = "nvidia,tegra30-gpio";
                 reg = <0x6000d000 0x1000>;
                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
@@ -326,7 +327,7 @@
                 interrupt-controller;
         };
 
-        pinmux: pinmux {
+        pinmux: pinmux@70000868 {
                 compatible = "nvidia,tegra30-pinmux";
                 reg = <0x70000868 0xd4    /* Pad control registers */
                        0x70003000 0x3e4>; /* Mux registers */
@@ -405,7 +406,7 @@
                 status = "disabled";
         };
 
-        pwm: pwm {
+        pwm: pwm@7000a000 {
                 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
                 reg = <0x7000a000 0x100>;
                 #pwm-cells = <2>;
@@ -415,7 +416,7 @@
                 status = "disabled";
         };
 
-        rtc {
+        rtc@7000e000 {
                 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
                 reg = <0x7000e000 0x100>;
                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
@@ -586,7 +587,7 @@
                 status = "disabled";
         };
 
-        kbc {
+        kbc@7000e200 {
                 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
                 reg = <0x7000e200 0x100>;
                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
@@ -596,14 +597,14 @@
                 status = "disabled";
         };
 
-        pmc {
+        pmc@7000e400 {
                 compatible = "nvidia,tegra30-pmc";
                 reg = <0x7000e400 0x400>;
                 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
                 clock-names = "pclk", "clk32k_in";
         };
 
-        memory-controller {
+        memory-controller@7000f000 {
                 compatible = "nvidia,tegra30-mc";
                 reg = <0x7000f000 0x010
                        0x7000f03c 0x1b4
@@ -612,7 +613,7 @@
                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
         };
 
-        iommu {
+        iommu@7000f010 {
                 compatible = "nvidia,tegra30-smmu";
                 reg = <0x7000f010 0x02c
                        0x7000f1f0 0x010
@@ -622,7 +623,7 @@
                 nvidia,ahb = <&ahb>;
         };
 
-        ahub {
+        ahub@70080000 {
                 compatible = "nvidia,tegra30-ahub";
                 reg = <0x70080000 0x200
                        0x70080200 0x100>;
@@ -784,7 +785,7 @@
                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
                 reg = <0x7d004000 0x4000>;
                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
-                phy_type = "ulpi";
+                phy_type = "utmi";
                 clocks = <&tegra_car TEGRA30_CLK_USB2>;
                 resets = <&tegra_car 58>;
                 reset-names = "usb";
@@ -794,12 +795,23 @@
 
         phy2: usb-phy@7d004000 {
                 compatible = "nvidia,tegra30-usb-phy";
-                reg = <0x7d004000 0x4000>;
-                phy_type = "ulpi";
+                reg = <0x7d004000 0x4000 0x7d000000 0x4000>;
+                phy_type = "utmi";
                 clocks = <&tegra_car TEGRA30_CLK_USB2>,
                          <&tegra_car TEGRA30_CLK_PLL_U>,
-                         <&tegra_car TEGRA30_CLK_CDEV2>;
-                clock-names = "reg", "pll_u", "ulpi-link";
+                         <&tegra_car TEGRA30_CLK_USBD>;
+                clock-names = "reg", "pll_u", "utmi-pads";
+                nvidia,hssync-start-delay = <9>;
+                nvidia,idle-wait-delay = <17>;
+                nvidia,elastic-limit = <16>;
+                nvidia,term-range-adj = <6>;
+                nvidia,xcvr-setup = <51>;
+                nvidia.xcvr-setup-use-fuses;
+                nvidia,xcvr-lsfslew = <2>;
+                nvidia,xcvr-lsrslew = <2>;
+                nvidia,xcvr-hsslew = <32>;
+                nvidia,hssquelch-level = <2>;
+                nvidia,hsdiscon-level = <5>;
                 status = "disabled";
         };
 
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index e7f73b2e4550..5d7681be0580 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -15,6 +15,25 @@
 / {
         compatible = "xlnx,zynq-7000";
 
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
+                        reg = <0>;
+                        clocks = <&clkc 3>;
+                };
+
+                cpu@1 {
+                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
+                        reg = <1>;
+                        clocks = <&clkc 3>;
+                };
+        };
+
         pmu {
                 compatible = "arm,cortex-a9-pmu";
                 interrupts = <0 5 4>, <0 6 4>;
@@ -65,6 +84,24 @@
                         interrupts = <0 50 4>;
                 };
 
+                gem0: ethernet@e000b000 {
+                        compatible = "cdns,gem";
+                        reg = <0xe000b000 0x4000>;
+                        status = "disabled";
+                        interrupts = <0 22 4>;
+                        clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
+                        clock-names = "pclk", "hclk", "tx_clk";
+                };
+
+                gem1: ethernet@e000c000 {
+                        compatible = "cdns,gem";
+                        reg = <0xe000c000 0x4000>;
+                        status = "disabled";
+                        interrupts = <0 45 4>;
+                        clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
+                        clock-names = "pclk", "hclk", "tx_clk";
+                };
+
                 slcr: slcr@f8000000 {
                         compatible = "xlnx,zynq-slcr";
                         reg = <0xF8000000 0x1000>;
@@ -106,7 +143,6 @@
                         compatible = "cdns,ttc";
                         clocks = <&clkc 6>;
                         reg = <0xF8001000 0x1000>;
-                        clock-ranges;
                 };
 
                 ttc1: ttc1@f8002000 {
@@ -115,7 +151,6 @@
                         compatible = "cdns,ttc";
                         clocks = <&clkc 6>;
                         reg = <0xF8002000 0x1000>;
-                        clock-ranges;
                 };
                 scutimer: scutimer@f8f00600 {
                         interrupt-parent = <&intc>;
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
index 21aea99a067b..34d680a46b7e 100644
--- a/arch/arm/boot/dts/zynq-zc702.dts
+++ b/arch/arm/boot/dts/zynq-zc702.dts
@@ -29,6 +29,11 @@
 
 };
 
+&gem0 {
+        status = "okay";
+        phy-mode = "rgmii";
+};
+
 &uart1 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts
index 79009e0b74b9..b2835d5fc09a 100644
--- a/arch/arm/boot/dts/zynq-zc706.dts
+++ b/arch/arm/boot/dts/zynq-zc706.dts
@@ -30,6 +30,11 @@
 
 };
 
+&gem0 {
+        status = "okay";
+        phy-mode = "rgmii";
+};
+
 &uart1 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/zynq-zed.dts
index d6acf2b1cdf4..2eda06889dfc 100644
--- a/arch/arm/boot/dts/zynq-zed.dts
+++ b/arch/arm/boot/dts/zynq-zed.dts
@@ -30,6 +30,11 @@
 
 };
 
+&gem0 {
+        status = "okay";
+        phy-mode = "rgmii";
+};
+
 &uart1 {
         status = "okay";
 };
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 473e21b87364..17c0fe627435 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -63,6 +63,9 @@
 
 /* Base address to the AP system controller */
 void __iomem *ap_syscon_base;
+/* Base address to the external bus interface */
+static void __iomem *ebi_base;
+
 
 /*
  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
@@ -72,15 +75,11 @@ void __iomem *ap_syscon_base;
  * just for now).
  */
 #define VA_IC_BASE      __io_address(INTEGRATOR_IC_BASE)
-#define VA_EBI_BASE     __io_address(INTEGRATOR_EBI_BASE)
-#define VA_CMIC_BASE    __io_address(INTEGRATOR_HDR_IC)
 
 /*
  * Logical      Physical
  * ef000000                     Cache flush
- * f1000000     10000000        Core module registers
  * f1100000     11000000        System controller registers
- * f1200000     12000000        EBI registers
  * f1300000     13000000        Counter/Timer
  * f1400000     14000000        Interrupt controller
  * f1600000     16000000        UART 0
@@ -91,16 +90,6 @@ void __iomem *ap_syscon_base;
 
 static struct map_desc ap_io_desc[] __initdata __maybe_unused = {
         {
-                .virtual        = IO_ADDRESS(INTEGRATOR_HDR_BASE),
-                .pfn            = __phys_to_pfn(INTEGRATOR_HDR_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE
-        }, {
-                .virtual        = IO_ADDRESS(INTEGRATOR_EBI_BASE),
-                .pfn            = __phys_to_pfn(INTEGRATOR_EBI_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE
-        }, {
                 .virtual        = IO_ADDRESS(INTEGRATOR_CT_BASE),
                 .pfn            = __phys_to_pfn(INTEGRATOR_CT_BASE),
                 .length         = SZ_4K,
@@ -174,9 +163,6 @@ device_initcall(irq_syscore_init);
 /*
  * Flash handling.
  */
-#define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
-#define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
-
 static int ap_flash_init(struct platform_device *dev)
 {
         u32 tmp;
@@ -184,13 +170,15 @@ static int ap_flash_init(struct platform_device *dev)
         writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
                ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
 
-        tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
-        writel(tmp, EBI_CSR1);
+        tmp = readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) |
+                INTEGRATOR_EBI_WRITE_ENABLE;
+        writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
 
-        if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
-                writel(0xa05f, EBI_LOCK);
-                writel(tmp, EBI_CSR1);
-                writel(0, EBI_LOCK);
+        if (!(readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET)
+              & INTEGRATOR_EBI_WRITE_ENABLE)) {
+                writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
+                writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
+                writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
         }
         return 0;
 }
@@ -202,13 +190,15 @@ static void ap_flash_exit(struct platform_device *dev)
         writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
                ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
 
-        tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
-        writel(tmp, EBI_CSR1);
+        tmp = readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) &
+                ~INTEGRATOR_EBI_WRITE_ENABLE;
+        writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
 
-        if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
-                writel(0xa05f, EBI_LOCK);
-                writel(tmp, EBI_CSR1);
-                writel(0, EBI_LOCK);
+        if (readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) &
+            INTEGRATOR_EBI_WRITE_ENABLE) {
+                writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
+                writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
+                writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
         }
 }
 
@@ -475,11 +465,17 @@ static const struct of_device_id ap_syscon_match[] = {
         { },
 };
 
+static const struct of_device_id ebi_match[] = {
+        { .compatible = "arm,external-bus-interface"},
+        { },
+};
+
 static void __init ap_init_of(void)
 {
         unsigned long sc_dec;
         struct device_node *root;
         struct device_node *syscon;
+        struct device_node *ebi;
         struct device *parent;
         struct soc_device *soc_dev;
         struct soc_device_attribute *soc_dev_attr;
@@ -495,10 +491,16 @@ static void __init ap_init_of(void)
         syscon = of_find_matching_node(root, ap_syscon_match);
         if (!syscon)
                 return;
+        ebi = of_find_matching_node(root, ebi_match);
+        if (!ebi)
+                return;
 
         ap_syscon_base = of_iomap(syscon, 0);
         if (!ap_syscon_base)
                 return;
+        ebi_base = of_iomap(ebi, 0);
+        if (!ebi_base)
+                return;
 
         ap_sc_id = readl(ap_syscon_base);
 
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 4fc0a195de01..5e84149d1790 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -64,9 +64,6 @@ static void __iomem *intcp_con_base;
 
 /*
  * Logical      Physical
- * f1000000     10000000        Core module registers
- * f1100000     11000000        System controller registers
- * f1200000     12000000        EBI registers
  * f1300000     13000000        Counter/Timer
  * f1400000     14000000        Interrupt controller
  * f1600000     16000000        UART 0
@@ -74,21 +71,10 @@ static void __iomem *intcp_con_base;
  * f1a00000     1a000000        Debug LEDs
  * fc900000     c9000000        GPIO
  * fca00000     ca000000        SIC
- * fcb00000     cb000000        CP system control
  */
 
 static struct map_desc intcp_io_desc[] __initdata __maybe_unused = {
         {
-                .virtual        = IO_ADDRESS(INTEGRATOR_HDR_BASE),
-                .pfn            = __phys_to_pfn(INTEGRATOR_HDR_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE
-        }, {
-                .virtual        = IO_ADDRESS(INTEGRATOR_EBI_BASE),
-                .pfn            = __phys_to_pfn(INTEGRATOR_EBI_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE
-        }, {
                 .virtual        = IO_ADDRESS(INTEGRATOR_CT_BASE),
                 .pfn            = __phys_to_pfn(INTEGRATOR_CT_BASE),
                 .length         = SZ_4K,
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
index cce2c9dfb5d1..4a1065e41e9c 100644
--- a/arch/arm/mach-nomadik/cpu-8815.c
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -110,38 +110,6 @@ static void cpu8815_restart(enum reboot_mode mode, const char *cmd)
 }
 
 /*
- * The SMSC911x IRQ is connected to a GPIO pin, but the driver expects
- * to simply request an IRQ passed as a resource. So the GPIO pin needs
- * to be requested by this hog and set as input.
- */
-static int __init cpu8815_eth_init(void)
-{
-        struct device_node *eth;
-        int gpio, irq, err;
-
-        eth = of_find_node_by_path("/usb-s8815/ethernet-gpio");
-        if (!eth) {
-                pr_info("could not find any ethernet GPIO\n");
-                return 0;
-        }
-        gpio = of_get_gpio(eth, 0);
-        err = gpio_request(gpio, "eth_irq");
-        if (err) {
-                pr_info("failed to request ethernet GPIO\n");
-                return -ENODEV;
-        }
-        err = gpio_direction_input(gpio);
-        if (err) {
-                pr_info("failed to set ethernet GPIO as input\n");
-                return -ENODEV;
-        }
-        irq = gpio_to_irq(gpio);
-        pr_info("enabled USB-S8815 ethernet GPIO %d, IRQ %d\n", gpio, irq);
-        return 0;
-}
-device_initcall(cpu8815_eth_init);
-
-/*
  * This GPIO pin turns on a line that is used to detect card insertion
  * on this board.
  */
diff --git a/arch/arm/mach-shmobile/board-bockw-reference.c b/arch/arm/mach-shmobile/board-bockw-reference.c
index 1687df9b267f..875cf3f3f503 100644
--- a/arch/arm/mach-shmobile/board-bockw-reference.c
+++ b/arch/arm/mach-shmobile/board-bockw-reference.c
@@ -27,14 +27,6 @@
  *      see board-bock.c for checking detail of dip-switch
  */
 
-static const struct pinctrl_map bockw_pinctrl_map[] = {
-        /* SCIF0 */
-        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
-                                  "scif0_data_a", "scif0"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
-                                  "scif0_ctrl", "scif0"),
-};
-
 #define FPGA    0x18200000
 #define IRQ0MR  0x30
 #define COMCTLR 0x101c
@@ -44,10 +36,6 @@ static void __init bockw_init(void)
 
         r8a7778_clock_init();
         r8a7778_init_irq_extpin_dt(1);
-
-        pinctrl_register_mappings(bockw_pinctrl_map,
-                                  ARRAY_SIZE(bockw_pinctrl_map));
-        r8a7778_pinmux_init();
         r8a7778_add_dt_devices();
 
         fpga = ioremap_nocache(FPGA, SZ_1M);
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index 4f9e3ec42ddc..d832a4477b4b 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -347,8 +347,6 @@ static const struct pinctrl_map marzen_pinctrl_map[] = {
                                   "sdhi0_ctrl", "sdhi0"),
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
                                   "sdhi0_cd", "sdhi0"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
-                                  "sdhi0_wp", "sdhi0"),
         /* SMSC */
         PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
                                   "intc_irq1_b", "intc"),
diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
index 571409b611d3..7348d58f500e 100644
--- a/arch/arm/mach-shmobile/clock-r8a73a4.c
+++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
@@ -584,15 +584,15 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
         CLKDEV_DEV_ID("e6520000.i2c", &mstp_clks[MSTP300]),
         CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
-        CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]),
+        CLKDEV_DEV_ID("ee220000.mmc", &mstp_clks[MSTP305]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
-        CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP312]),
+        CLKDEV_DEV_ID("ee140000.sd", &mstp_clks[MSTP312]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
-        CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]),
+        CLKDEV_DEV_ID("ee120000.sd", &mstp_clks[MSTP313]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
-        CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]),
+        CLKDEV_DEV_ID("ee100000.sd", &mstp_clks[MSTP314]),
         CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
-        CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]),
+        CLKDEV_DEV_ID("ee200000.mmc", &mstp_clks[MSTP315]),
         CLKDEV_DEV_ID("e6550000.i2c", &mstp_clks[MSTP316]),
         CLKDEV_DEV_ID("e6560000.i2c", &mstp_clks[MSTP317]),
         CLKDEV_DEV_ID("e6500000.i2c", &mstp_clks[MSTP318]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index e9a3c6401845..dd989f93498f 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -590,18 +590,18 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("e6c20000.i2c",           &mstp_clks[MSTP323]),
         CLKDEV_DEV_ID("renesas_usbhs",          &mstp_clks[MSTP320]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.0",       &mstp_clks[MSTP314]),
-        CLKDEV_DEV_ID("e6850000.sdhi",          &mstp_clks[MSTP314]),
+        CLKDEV_DEV_ID("e6850000.sd",            &mstp_clks[MSTP314]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.1",       &mstp_clks[MSTP313]),
-        CLKDEV_DEV_ID("e6860000.sdhi",          &mstp_clks[MSTP313]),
+        CLKDEV_DEV_ID("e6860000.sd",            &mstp_clks[MSTP313]),
         CLKDEV_DEV_ID("sh_mmcif",               &mstp_clks[MSTP312]),
-        CLKDEV_DEV_ID("e6bd0000.mmcif",         &mstp_clks[MSTP312]),
+        CLKDEV_DEV_ID("e6bd0000.mmc",           &mstp_clks[MSTP312]),
         CLKDEV_DEV_ID("r8a7740-gether",         &mstp_clks[MSTP309]),
         CLKDEV_DEV_ID("e9a00000.sh-eth",        &mstp_clks[MSTP309]),
         CLKDEV_DEV_ID("renesas-tpu-pwm",        &mstp_clks[MSTP304]),
         CLKDEV_DEV_ID("e6600000.pwm",           &mstp_clks[MSTP304]),
 
         CLKDEV_DEV_ID("sh_mobile_sdhi.2",       &mstp_clks[MSTP415]),
-        CLKDEV_DEV_ID("e6870000.sdhi",          &mstp_clks[MSTP415]),
+        CLKDEV_DEV_ID("e6870000.sd",            &mstp_clks[MSTP415]),
 
         /* ICK */
         CLKDEV_ICK_ID("host",   "renesas_usbhs",        &mstp_clks[MSTP416]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c
index dfb0fff4d24c..9783945f8bc7 100644
--- a/arch/arm/mach-shmobile/clock-r8a7778.c
+++ b/arch/arm/mach-shmobile/clock-r8a7778.c
@@ -184,13 +184,13 @@ static struct clk_lookup lookups[] = {
 
         /* MSTP32 clocks */
         CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP331]), /* MMC */
-        CLKDEV_DEV_ID("ffe4e000.mmcif", &mstp_clks[MSTP331]), /* MMC */
+        CLKDEV_DEV_ID("ffe4e000.mmc", &mstp_clks[MSTP331]), /* MMC */
         CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
-        CLKDEV_DEV_ID("ffe4c000.sdhi", &mstp_clks[MSTP323]), /* SDHI0 */
+        CLKDEV_DEV_ID("ffe4c000.sd", &mstp_clks[MSTP323]), /* SDHI0 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
-        CLKDEV_DEV_ID("ffe4d000.sdhi", &mstp_clks[MSTP322]), /* SDHI1 */
+        CLKDEV_DEV_ID("ffe4d000.sd", &mstp_clks[MSTP322]), /* SDHI1 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
-        CLKDEV_DEV_ID("ffe4f000.sdhi", &mstp_clks[MSTP321]), /* SDHI2 */
+        CLKDEV_DEV_ID("ffe4f000.sd", &mstp_clks[MSTP321]), /* SDHI2 */
         CLKDEV_DEV_ID("r8a777x-ether", &mstp_clks[MSTP114]), /* Ether */
         CLKDEV_DEV_ID("r8a7778-vin.0", &mstp_clks[MSTP110]), /* VIN0 */
         CLKDEV_DEV_ID("r8a7778-vin.1", &mstp_clks[MSTP109]), /* VIN1 */
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index b545c8dbb818..f1fb89b76786 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -204,13 +204,13 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */
         CLKDEV_DEV_ID("fffc6000.spi", &mstp_clks[MSTP007]), /* HSPI2 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
-        CLKDEV_DEV_ID("ffe4c000.sdhi", &mstp_clks[MSTP323]), /* SDHI0 */
+        CLKDEV_DEV_ID("ffe4c000.sd", &mstp_clks[MSTP323]), /* SDHI0 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
-        CLKDEV_DEV_ID("ffe4d000.sdhi", &mstp_clks[MSTP322]), /* SDHI1 */
+        CLKDEV_DEV_ID("ffe4d000.sd", &mstp_clks[MSTP322]), /* SDHI1 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
-        CLKDEV_DEV_ID("ffe4e000.sdhi", &mstp_clks[MSTP321]), /* SDHI2 */
+        CLKDEV_DEV_ID("ffe4e000.sd", &mstp_clks[MSTP321]), /* SDHI2 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */
-        CLKDEV_DEV_ID("ffe4f000.sdhi", &mstp_clks[MSTP320]), /* SDHI3 */
+        CLKDEV_DEV_ID("ffe4f000.sd", &mstp_clks[MSTP320]), /* SDHI3 */
         CLKDEV_DEV_ID("rcar-du-r8a7779", &mstp_clks[MSTP103]), /* DU */
 };
 
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index 30552448b056..f44987a92ad4 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -302,17 +302,17 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
         CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
         CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
-        CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]),
+        CLKDEV_DEV_ID("ee200000.mmc", &mstp_clks[MSTP315]),
         CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
-        CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]),
+        CLKDEV_DEV_ID("ee100000.sd", &mstp_clks[MSTP314]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
-        CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]),
+        CLKDEV_DEV_ID("ee120000.sd", &mstp_clks[MSTP313]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
-        CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP312]),
+        CLKDEV_DEV_ID("ee140000.sd", &mstp_clks[MSTP312]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
-        CLKDEV_DEV_ID("ee160000.sdhi", &mstp_clks[MSTP311]),
+        CLKDEV_DEV_ID("ee160000.sd", &mstp_clks[MSTP311]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]),
-        CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]),
+        CLKDEV_DEV_ID("ee220000.mmc", &mstp_clks[MSTP305]),
         CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
         CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
         CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 87e349ddba7c..23edf8360c27 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -658,13 +658,13 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("e6822000.i2c", &mstp_clks[MSTP323]), /* I2C1 */
         CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP322]), /* USB */
         CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
-        CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), /* SDHI0 */
+        CLKDEV_DEV_ID("ee100000.sd", &mstp_clks[MSTP314]), /* SDHI0 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
-        CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]), /* SDHI1 */
+        CLKDEV_DEV_ID("ee120000.sd", &mstp_clks[MSTP313]), /* SDHI1 */
         CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */
-        CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), /* MMCIF0 */
+        CLKDEV_DEV_ID("e6bd0000.mmc", &mstp_clks[MSTP312]), /* MMCIF0 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), /* SDHI2 */
-        CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP311]), /* SDHI2 */
+        CLKDEV_DEV_ID("ee140000.sd", &mstp_clks[MSTP311]), /* SDHI2 */
         CLKDEV_DEV_ID("renesas-tpu-pwm.0", &mstp_clks[MSTP304]), /* TPU0 */
         CLKDEV_DEV_ID("renesas-tpu-pwm.1", &mstp_clks[MSTP303]), /* TPU1 */
         CLKDEV_DEV_ID("renesas-tpu-pwm.2", &mstp_clks[MSTP302]), /* TPU2 */
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index 616b96e86ad4..d05ba759da30 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -2,10 +2,10 @@
 # Makefile for the linux kernel, U8500 machine.
 #
 
-obj-y                           := cpu.o devices.o id.o timer.o pm.o
+obj-y                           := cpu.o id.o timer.o pm.o
 obj-$(CONFIG_CACHE_L2X0)        += cache-l2x0.o
-obj-$(CONFIG_UX500_SOC_DB8500)  += cpu-db8500.o devices-db8500.o
-obj-$(CONFIG_MACH_MOP500)       += board-mop500.o board-mop500-sdi.o \
+obj-$(CONFIG_UX500_SOC_DB8500)  += cpu-db8500.o
+obj-$(CONFIG_MACH_MOP500)       += board-mop500-sdi.o \
                                 board-mop500-regulators.o \
                                 board-mop500-pins.o \
                                 board-mop500-audio.o
diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c
index 43d6cb8c381d..9309ad4cbd09 100644
--- a/arch/arm/mach-ux500/board-mop500-audio.c
+++ b/arch/arm/mach-ux500/board-mop500-audio.c
@@ -7,16 +7,13 @@
 #include <linux/platform_device.h>
 #include <linux/init.h>
 #include <linux/gpio.h>
-#include <linux/platform_data/pinctrl-nomadik.h>
 #include <linux/platform_data/dma-ste-dma40.h>
 
-#include "devices.h"
 #include "irqs.h"
 #include <linux/platform_data/asoc-ux500-msp.h>
 
 #include "ste-dma40-db8500.h"
 #include "board-mop500.h"
-#include "devices-db8500.h"
 
 static struct stedma40_chan_cfg msp0_dma_rx = {
         .high_priority = true,
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index 0efb1560fc35..f63619b69113 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -10,94 +10,18 @@
 #include <linux/string.h>
 #include <linux/pinctrl/machine.h>
 #include <linux/pinctrl/pinconf-generic.h>
-#include <linux/platform_data/pinctrl-nomadik.h>
 
 #include <asm/mach-types.h>
 
 #include "board-mop500.h"
 
-enum custom_pin_cfg_t {
-        PINS_FOR_DEFAULT,
-        PINS_FOR_U9500,
-};
-
-static enum custom_pin_cfg_t pinsfor;
-
 /* These simply sets bias for pins */
 #define BIAS(a,b) static unsigned long a[] = { b }
 
-BIAS(pd, PIN_PULL_DOWN);
-BIAS(in_nopull, PIN_INPUT_NOPULL);
-BIAS(in_nopull_slpm_nowkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_DISABLE);
-BIAS(in_pu, PIN_INPUT_PULLUP);
-BIAS(in_pd, PIN_INPUT_PULLDOWN);
-BIAS(out_hi, PIN_OUTPUT_HIGH);
-BIAS(out_lo, PIN_OUTPUT_LOW);
-BIAS(out_lo_slpm_nowkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE);
-
 BIAS(abx500_out_lo, PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0));
 BIAS(abx500_in_pd, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 1));
 BIAS(abx500_in_nopull, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 0));
 
-/* These also force them into GPIO mode */
-BIAS(gpio_in_pu, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED);
-BIAS(gpio_in_pd, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED);
-BIAS(gpio_in_pu_slpm_gpio_nopull, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
-BIAS(gpio_in_pd_slpm_gpio_nopull, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
-BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED);
-BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED);
-/* Sleep modes */
-BIAS(slpm_in_wkup_pdis, PIN_SLEEPMODE_ENABLED|
-        PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
-BIAS(slpm_in_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|
-        PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
-BIAS(slpm_wkup_pdis, PIN_SLEEPMODE_ENABLED|
-        PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
-BIAS(slpm_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|
-        PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
-BIAS(slpm_out_lo_pdis, PIN_SLEEPMODE_ENABLED|
-        PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE|PIN_SLPM_PDIS_DISABLED);
-BIAS(slpm_out_lo_wkup_pdis, PIN_SLEEPMODE_ENABLED|
-        PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
-BIAS(slpm_out_hi_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_OUTPUT_HIGH|
-        PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
-BIAS(slpm_in_nopull_wkup_pdis, PIN_SLEEPMODE_ENABLED|
-        PIN_SLPM_INPUT_NOPULL|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
-BIAS(slpm_in_pu_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|PIN_SLPM_INPUT_PULLUP|
-        PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
-BIAS(slpm_out_wkup_pdis, PIN_SLEEPMODE_ENABLED|
-        PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
-BIAS(out_lo_wkup_pdis, PIN_SLPM_OUTPUT_LOW|
-        PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
-BIAS(in_wkup_pdis_en, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|
-        PIN_SLPM_PDIS_ENABLED);
-BIAS(in_wkup_pdis, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|
-        PIN_SLPM_PDIS_DISABLED);
-BIAS(out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|
-        PIN_SLPM_PDIS_DISABLED);
-
-/* We use these to define hog settings that are always done on boot */
-#define DB8500_MUX_HOG(group,func) \
-        PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-db8500", group, func)
-#define DB8500_PIN_HOG(pin,conf) \
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-db8500", pin, conf)
-
-/* These are default states associated with device and changed runtime */
-#define DB8500_MUX(group,func,dev) \
-        PIN_MAP_MUX_GROUP_DEFAULT(dev, "pinctrl-db8500", group, func)
-#define DB8500_PIN(pin,conf,dev) \
-        PIN_MAP_CONFIGS_PIN_DEFAULT(dev, "pinctrl-db8500", pin, conf)
-#define DB8500_PIN_IDLE(pin, conf, dev) \
-        PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_IDLE, "pinctrl-db8500",  \
-                            pin, conf)
-#define DB8500_PIN_SLEEP(pin, conf, dev) \
-        PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
-                            pin, conf)
-#define DB8500_MUX_STATE(group, func, dev, state) \
-        PIN_MAP_MUX_GROUP(dev, state, "pinctrl-db8500", group, func)
-#define DB8500_PIN_STATE(pin, conf, dev, state) \
-        PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-db8500", pin, conf)
-
 #define AB8500_MUX_HOG(group, func) \
         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8500.0", group, func)
 #define AB8500_PIN_HOG(pin, conf) \
@@ -344,725 +268,8 @@ static struct pinctrl_map __initdata ab8505_pinmap[] = {
         AB8505_PIN_HOG("GPIO53_D15", in_pd),
 };
 
-/* Pin control settings */
-static struct pinctrl_map __initdata mop500_family_pinmap[] = {
-        /*
-         * uMSP0, mux in 4 pins, regular placement of RX/TX
-         * explicitly set the pins to no pull
-         */
-        DB8500_MUX_HOG("msp0txrx_a_1", "msp0"),
-        DB8500_MUX_HOG("msp0tfstck_a_1", "msp0"),
-        DB8500_PIN_HOG("GPIO12_AC4", in_nopull), /* TXD */
-        DB8500_PIN_HOG("GPIO15_AC3", in_nopull), /* RXD */
-        DB8500_PIN_HOG("GPIO13_AF3", in_nopull), /* TFS */
-        DB8500_PIN_HOG("GPIO14_AE3", in_nopull), /* TCK */
-        /* MSP2 for HDMI, pull down TXD, TCK, TFS  */
-        DB8500_MUX_HOG("msp2_a_1", "msp2"),
-        DB8500_PIN_HOG("GPIO193_AH27", in_pd), /* TXD */
-        DB8500_PIN_HOG("GPIO194_AF27", in_pd), /* TCK */
-        DB8500_PIN_HOG("GPIO195_AG28", in_pd), /* TFS */
-        DB8500_PIN_HOG("GPIO196_AG26", out_lo), /* RXD */
-        /*
-         * LCD, set TE0 (using LCD VSI0) and D14 (touch screen interrupt) to
-         * pull-up
-         * TODO: is this really correct? Snowball doesn't have a LCD.
-         */
-        DB8500_MUX_HOG("lcdvsi0_a_1", "lcd"),
-        DB8500_PIN_HOG("GPIO68_E1", in_pu),
-        DB8500_PIN_HOG("GPIO84_C2", gpio_in_pu),
-        /*
-         * STMPE1601/tc35893 keypad IRQ GPIO 218
-         * TODO: set for snowball and HREF really??
-         */
-        DB8500_PIN_HOG("GPIO218_AH11", gpio_in_pu),
-        /*
-         * UART0, we do not mux in u0 here.
-         * uart-0 pins gpio configuration should be kept intact to prevent
-         * a glitch in tx line when the tty dev is opened. Later these pins
-         * are configured by uart driver
-         */
-        DB8500_PIN_HOG("GPIO0_AJ5", in_pu), /* CTS */
-        DB8500_PIN_HOG("GPIO1_AJ3", out_hi), /* RTS */
-        DB8500_PIN_HOG("GPIO2_AH4", in_pu), /* RXD */
-        DB8500_PIN_HOG("GPIO3_AH3", out_hi), /* TXD */
-        /*
-         * Mux in UART2 on altfunction C and set pull-ups.
-         * TODO: is this used on U8500 variants and Snowball really?
-         * The setting on GPIO31 conflicts with magnetometer use on hrefv60
-         */
-        /* default state for UART2 */
-        DB8500_MUX("u2rxtx_c_1", "u2", "uart2"),
-        DB8500_PIN("GPIO29_W2", in_pu, "uart2"), /* RXD */
-        DB8500_PIN("GPIO30_W3", out_hi, "uart2"), /* TXD */
-        /* Sleep state for UART2 */
-        DB8500_PIN_SLEEP("GPIO29_W2", in_wkup_pdis, "uart2"),
-        DB8500_PIN_SLEEP("GPIO30_W3", out_wkup_pdis, "uart2"),
-        /*
-         * The following pin sets were known as "runtime pins" before being
-         * converted to the pinctrl model. Here we model them as "default"
-         * states.
-         */
-        /* Mux in UART0 after initialization */
-        DB8500_MUX("u0_a_1", "u0", "uart0"),
-        DB8500_PIN("GPIO0_AJ5", in_pu, "uart0"), /* CTS */
-        DB8500_PIN("GPIO1_AJ3", out_hi, "uart0"), /* RTS */
-        DB8500_PIN("GPIO2_AH4", in_pu, "uart0"), /* RXD */
-        DB8500_PIN("GPIO3_AH3", out_hi, "uart0"), /* TXD */
-        /* Sleep state for UART0 */
-        DB8500_PIN_SLEEP("GPIO0_AJ5", slpm_in_wkup_pdis, "uart0"),
-        DB8500_PIN_SLEEP("GPIO1_AJ3", slpm_out_hi_wkup_pdis, "uart0"),
-        DB8500_PIN_SLEEP("GPIO2_AH4", slpm_in_wkup_pdis, "uart0"),
-        DB8500_PIN_SLEEP("GPIO3_AH3", slpm_out_wkup_pdis, "uart0"),
-        /* Mux in UART1 after initialization */
-        DB8500_MUX("u1rxtx_a_1", "u1", "uart1"),
-        DB8500_PIN("GPIO4_AH6", in_pu, "uart1"), /* RXD */
-        DB8500_PIN("GPIO5_AG6", out_hi, "uart1"), /* TXD */
-        /* Sleep state for UART1 */
-        DB8500_PIN_SLEEP("GPIO4_AH6", slpm_in_wkup_pdis, "uart1"),
-        DB8500_PIN_SLEEP("GPIO5_AG6", slpm_out_wkup_pdis, "uart1"),
-        /* MSP1 for ALSA codec */
-        DB8500_MUX_HOG("msp1txrx_a_1", "msp1"),
-        DB8500_MUX_HOG("msp1_a_1", "msp1"),
-        DB8500_PIN_HOG("GPIO33_AF2", out_lo_slpm_nowkup),
-        DB8500_PIN_HOG("GPIO34_AE1", in_nopull_slpm_nowkup),
-        DB8500_PIN_HOG("GPIO35_AE2", in_nopull_slpm_nowkup),
-        DB8500_PIN_HOG("GPIO36_AG2", in_nopull_slpm_nowkup),
-        /* Mux in LCD data lines 8 thru 11 and LCDA CLK for MCDE TVOUT */
-        DB8500_MUX("lcd_d8_d11_a_1", "lcd", "mcde-tvout"),
-        DB8500_MUX("lcdaclk_b_1", "lcda", "mcde-tvout"),
-        /* Mux in LCD VSI1 and pull it up for MCDE HDMI output */
-        DB8500_MUX("lcdvsi1_a_1", "lcd", "0-0070"),
-        DB8500_PIN("GPIO69_E2", in_pu, "0-0070"),
-        /* LCD VSI1 sleep state */
-        DB8500_PIN_SLEEP("GPIO69_E2", slpm_in_wkup_pdis, "0-0070"),
-        /* Mux in i2c0 block, default state */
-        DB8500_MUX("i2c0_a_1", "i2c0", "nmk-i2c.0"),
-        /* i2c0 sleep state */
-        DB8500_PIN_SLEEP("GPIO147_C15", slpm_in_nopull_wkup_pdis, "nmk-i2c.0"), /* SDA */
-        DB8500_PIN_SLEEP("GPIO148_B16", slpm_in_nopull_wkup_pdis, "nmk-i2c.0"), /* SCL */
-        /* Mux in i2c1 block, default state  */
-        DB8500_MUX("i2c1_b_2", "i2c1", "nmk-i2c.1"),
-        /* i2c1 sleep state */
-        DB8500_PIN_SLEEP("GPIO16_AD3", slpm_in_nopull_wkup_pdis, "nmk-i2c.1"), /* SDA */
-        DB8500_PIN_SLEEP("GPIO17_AD4", slpm_in_nopull_wkup_pdis, "nmk-i2c.1"), /* SCL */
-        /* Mux in i2c2 block, default state  */
-        DB8500_MUX("i2c2_b_2", "i2c2", "nmk-i2c.2"),
-        /* i2c2 sleep state */
-        DB8500_PIN_SLEEP("GPIO10_AF5", slpm_in_nopull_wkup_pdis, "nmk-i2c.2"), /* SDA */
-        DB8500_PIN_SLEEP("GPIO11_AG4", slpm_in_nopull_wkup_pdis, "nmk-i2c.2"), /* SCL */
-        /* Mux in i2c3 block, default state  */
-        DB8500_MUX("i2c3_c_2", "i2c3", "nmk-i2c.3"),
-        /* i2c3 sleep state */
-        DB8500_PIN_SLEEP("GPIO229_AG7", slpm_in_nopull_wkup_pdis, "nmk-i2c.3"), /* SDA */
-        DB8500_PIN_SLEEP("GPIO230_AF7", slpm_in_nopull_wkup_pdis, "nmk-i2c.3"), /* SCL */
-        /* Mux in SDI0 (here called MC0) used for removable MMC/SD/SDIO cards */
-        DB8500_MUX("mc0_a_1", "mc0", "sdi0"),
-        DB8500_PIN("GPIO18_AC2", out_hi, "sdi0"), /* CMDDIR */
-        DB8500_PIN("GPIO19_AC1", out_hi, "sdi0"), /* DAT0DIR */
-        DB8500_PIN("GPIO20_AB4", out_hi, "sdi0"), /* DAT2DIR */
-        DB8500_PIN("GPIO22_AA3", in_nopull, "sdi0"), /* FBCLK */
-        DB8500_PIN("GPIO23_AA4", out_lo, "sdi0"), /* CLK */
-        DB8500_PIN("GPIO24_AB2", in_pu, "sdi0"), /* CMD */
-        DB8500_PIN("GPIO25_Y4", in_pu, "sdi0"), /* DAT0 */
-        DB8500_PIN("GPIO26_Y2", in_pu, "sdi0"), /* DAT1 */
-        DB8500_PIN("GPIO27_AA2", in_pu, "sdi0"), /* DAT2 */
-        DB8500_PIN("GPIO28_AA1", in_pu, "sdi0"), /* DAT3 */
-        /* SDI0 sleep state */
-        DB8500_PIN_SLEEP("GPIO18_AC2", slpm_out_hi_wkup_pdis, "sdi0"),
-        DB8500_PIN_SLEEP("GPIO19_AC1", slpm_out_hi_wkup_pdis, "sdi0"),
-        DB8500_PIN_SLEEP("GPIO20_AB4", slpm_out_hi_wkup_pdis, "sdi0"),
-        DB8500_PIN_SLEEP("GPIO22_AA3", slpm_in_wkup_pdis, "sdi0"),
-        DB8500_PIN_SLEEP("GPIO23_AA4", slpm_out_lo_wkup_pdis, "sdi0"),
-        DB8500_PIN_SLEEP("GPIO24_AB2", slpm_in_wkup_pdis, "sdi0"),
-        DB8500_PIN_SLEEP("GPIO25_Y4", slpm_in_wkup_pdis, "sdi0"),
-        DB8500_PIN_SLEEP("GPIO26_Y2", slpm_in_wkup_pdis, "sdi0"),
-        DB8500_PIN_SLEEP("GPIO27_AA2", slpm_in_wkup_pdis, "sdi0"),
-        DB8500_PIN_SLEEP("GPIO28_AA1", slpm_in_wkup_pdis, "sdi0"),
-
-        /* Mux in SDI1 (here called MC1) used for SDIO for CW1200 WLAN */
-        DB8500_MUX("mc1_a_1", "mc1", "sdi1"),
-        DB8500_PIN("GPIO208_AH16", out_lo, "sdi1"), /* CLK */
-        DB8500_PIN("GPIO209_AG15", in_nopull, "sdi1"), /* FBCLK */
-        DB8500_PIN("GPIO210_AJ15", in_pu, "sdi1"), /* CMD */
-        DB8500_PIN("GPIO211_AG14", in_pu, "sdi1"), /* DAT0 */
-        DB8500_PIN("GPIO212_AF13", in_pu, "sdi1"), /* DAT1 */
-        DB8500_PIN("GPIO213_AG13", in_pu, "sdi1"), /* DAT2 */
-        DB8500_PIN("GPIO214_AH15", in_pu, "sdi1"), /* DAT3 */
-        /* SDI1 sleep state */
-        DB8500_PIN_SLEEP("GPIO208_AH16", slpm_out_lo_wkup_pdis, "sdi1"), /* CLK */
-        DB8500_PIN_SLEEP("GPIO209_AG15", slpm_in_wkup_pdis, "sdi1"), /* FBCLK */
-        DB8500_PIN_SLEEP("GPIO210_AJ15", slpm_in_wkup_pdis, "sdi1"), /* CMD */
-        DB8500_PIN_SLEEP("GPIO211_AG14", slpm_in_wkup_pdis, "sdi1"), /* DAT0 */
-        DB8500_PIN_SLEEP("GPIO212_AF13", slpm_in_wkup_pdis, "sdi1"), /* DAT1 */
-        DB8500_PIN_SLEEP("GPIO213_AG13", slpm_in_wkup_pdis, "sdi1"), /* DAT2 */
-        DB8500_PIN_SLEEP("GPIO214_AH15", slpm_in_wkup_pdis, "sdi1"), /* DAT3 */
-
-        /* Mux in SDI2 (here called MC2) used for for PoP eMMC */
-        DB8500_MUX("mc2_a_1", "mc2", "sdi2"),
-        DB8500_PIN("GPIO128_A5", out_lo, "sdi2"), /* CLK */
-        DB8500_PIN("GPIO129_B4", in_pu, "sdi2"), /* CMD */
-        DB8500_PIN("GPIO130_C8", in_nopull, "sdi2"), /* FBCLK */
-        DB8500_PIN("GPIO131_A12", in_pu, "sdi2"), /* DAT0 */
-        DB8500_PIN("GPIO132_C10", in_pu, "sdi2"), /* DAT1 */
-        DB8500_PIN("GPIO133_B10", in_pu, "sdi2"), /* DAT2 */
-        DB8500_PIN("GPIO134_B9", in_pu, "sdi2"), /* DAT3 */
-        DB8500_PIN("GPIO135_A9", in_pu, "sdi2"), /* DAT4 */
-        DB8500_PIN("GPIO136_C7", in_pu, "sdi2"), /* DAT5 */
-        DB8500_PIN("GPIO137_A7", in_pu, "sdi2"), /* DAT6 */
-        DB8500_PIN("GPIO138_C5", in_pu, "sdi2"), /* DAT7 */
-        /* SDI2 sleep state */
-        DB8500_PIN_SLEEP("GPIO128_A5", out_lo_wkup_pdis, "sdi2"), /* CLK */
-        DB8500_PIN_SLEEP("GPIO129_B4", in_wkup_pdis_en, "sdi2"), /* CMD */
-        DB8500_PIN_SLEEP("GPIO130_C8", in_wkup_pdis_en, "sdi2"), /* FBCLK */
-        DB8500_PIN_SLEEP("GPIO131_A12", in_wkup_pdis, "sdi2"), /* DAT0 */
-        DB8500_PIN_SLEEP("GPIO132_C10", in_wkup_pdis, "sdi2"), /* DAT1 */
-        DB8500_PIN_SLEEP("GPIO133_B10", in_wkup_pdis, "sdi2"), /* DAT2 */
-        DB8500_PIN_SLEEP("GPIO134_B9", in_wkup_pdis, "sdi2"), /* DAT3 */
-        DB8500_PIN_SLEEP("GPIO135_A9", in_wkup_pdis, "sdi2"), /* DAT4 */
-        DB8500_PIN_SLEEP("GPIO136_C7", in_wkup_pdis, "sdi2"), /* DAT5 */
-        DB8500_PIN_SLEEP("GPIO137_A7", in_wkup_pdis, "sdi2"), /* DAT6 */
-        DB8500_PIN_SLEEP("GPIO138_C5", in_wkup_pdis, "sdi2"), /* DAT7 */
-
-        /* Mux in SDI4 (here called MC4) used for for PCB-mounted eMMC */
-        DB8500_MUX("mc4_a_1", "mc4", "sdi4"),
-        DB8500_PIN("GPIO197_AH24", in_pu, "sdi4"), /* DAT3 */
-        DB8500_PIN("GPIO198_AG25", in_pu, "sdi4"), /* DAT2 */
-        DB8500_PIN("GPIO199_AH23", in_pu, "sdi4"), /* DAT1 */
-        DB8500_PIN("GPIO200_AH26", in_pu, "sdi4"), /* DAT0 */
-        DB8500_PIN("GPIO201_AF24", in_pu, "sdi4"), /* CMD */
-        DB8500_PIN("GPIO202_AF25", in_nopull, "sdi4"), /* FBCLK */
-        DB8500_PIN("GPIO203_AE23", out_lo, "sdi4"), /* CLK */
-        DB8500_PIN("GPIO204_AF23", in_pu, "sdi4"), /* DAT7 */
-        DB8500_PIN("GPIO205_AG23", in_pu, "sdi4"), /* DAT6 */
-        DB8500_PIN("GPIO206_AG24", in_pu, "sdi4"), /* DAT5 */
-        DB8500_PIN("GPIO207_AJ23", in_pu, "sdi4"), /* DAT4 */
-        /*SDI4 sleep state */
-        DB8500_PIN_SLEEP("GPIO197_AH24", slpm_in_wkup_pdis, "sdi4"), /* DAT3 */
-        DB8500_PIN_SLEEP("GPIO198_AG25", slpm_in_wkup_pdis, "sdi4"), /* DAT2 */
-        DB8500_PIN_SLEEP("GPIO199_AH23", slpm_in_wkup_pdis, "sdi4"), /* DAT1 */
-        DB8500_PIN_SLEEP("GPIO200_AH26", slpm_in_wkup_pdis, "sdi4"), /* DAT0 */
-        DB8500_PIN_SLEEP("GPIO201_AF24", slpm_in_wkup_pdis, "sdi4"), /* CMD */
-        DB8500_PIN_SLEEP("GPIO202_AF25", slpm_in_wkup_pdis, "sdi4"), /* FBCLK */
-        DB8500_PIN_SLEEP("GPIO203_AE23", slpm_out_lo_wkup_pdis, "sdi4"), /* CLK */
-        DB8500_PIN_SLEEP("GPIO204_AF23", slpm_in_wkup_pdis, "sdi4"), /* DAT7 */
-        DB8500_PIN_SLEEP("GPIO205_AG23", slpm_in_wkup_pdis, "sdi4"), /* DAT6 */
-        DB8500_PIN_SLEEP("GPIO206_AG24", slpm_in_wkup_pdis, "sdi4"), /* DAT5 */
-        DB8500_PIN_SLEEP("GPIO207_AJ23", slpm_in_wkup_pdis, "sdi4"), /* DAT4 */
-
-        /* Mux in USB pins, drive STP high */
-        /* USB default state */
-        DB8500_MUX("usb_a_1", "usb", "ab8500-usb.0"),
-        DB8500_PIN("GPIO257_AE29", out_hi, "ab8500-usb.0"), /* STP */
-        /* USB sleep state */
-        DB8500_PIN_SLEEP("GPIO256_AF28", slpm_wkup_pdis_en, "ab8500-usb.0"), /* NXT */
-        DB8500_PIN_SLEEP("GPIO257_AE29", slpm_out_hi_wkup_pdis, "ab8500-usb.0"), /* STP */
-        DB8500_PIN_SLEEP("GPIO258_AD29", slpm_wkup_pdis_en, "ab8500-usb.0"), /* XCLK */
-        DB8500_PIN_SLEEP("GPIO259_AC29", slpm_wkup_pdis_en, "ab8500-usb.0"), /* DIR */
-        DB8500_PIN_SLEEP("GPIO260_AD28", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT7 */
-        DB8500_PIN_SLEEP("GPIO261_AD26", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT6 */
-        DB8500_PIN_SLEEP("GPIO262_AE26", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT5 */
-        DB8500_PIN_SLEEP("GPIO263_AG29", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT4 */
-        DB8500_PIN_SLEEP("GPIO264_AE27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT3 */
-        DB8500_PIN_SLEEP("GPIO265_AD27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT2 */
-        DB8500_PIN_SLEEP("GPIO266_AC28", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT1 */
-        DB8500_PIN_SLEEP("GPIO267_AC27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT0 */
-
-        /* Mux in SPI2 pins on the "other C1" altfunction */
-        DB8500_MUX("spi2_oc1_2", "spi2", "spi2"),
-        DB8500_PIN("GPIO216_AG12", gpio_out_hi, "spi2"), /* FRM */
-        DB8500_PIN("GPIO218_AH11", in_pd, "spi2"), /* RXD */
-        DB8500_PIN("GPIO215_AH13", out_lo, "spi2"), /* TXD */
-        DB8500_PIN("GPIO217_AH12", out_lo, "spi2"), /* CLK */
-        /* SPI2 idle state */
-        DB8500_PIN_IDLE("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
-        DB8500_PIN_IDLE("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */
-        DB8500_PIN_IDLE("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */
-        /* SPI2 sleep state */
-        DB8500_PIN_SLEEP("GPIO216_AG12", slpm_in_wkup_pdis, "spi2"), /* FRM */
-        DB8500_PIN_SLEEP("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
-        DB8500_PIN_SLEEP("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */
-        DB8500_PIN_SLEEP("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */
-
-        /* ske default state */
-        DB8500_MUX("kp_a_2", "kp", "nmk-ske-keypad"),
-        DB8500_PIN("GPIO153_B17", in_pd, "nmk-ske-keypad"), /* I7 */
-        DB8500_PIN("GPIO154_C16", in_pd, "nmk-ske-keypad"), /* I6 */
-        DB8500_PIN("GPIO155_C19", in_pd, "nmk-ske-keypad"), /* I5 */
-        DB8500_PIN("GPIO156_C17", in_pd, "nmk-ske-keypad"), /* I4 */
-        DB8500_PIN("GPIO161_D21", in_pd, "nmk-ske-keypad"), /* I3 */
-        DB8500_PIN("GPIO162_D20", in_pd, "nmk-ske-keypad"), /* I2 */
-        DB8500_PIN("GPIO163_C20", in_pd, "nmk-ske-keypad"), /* I1 */
-        DB8500_PIN("GPIO164_B21", in_pd, "nmk-ske-keypad"), /* I0 */
-        DB8500_PIN("GPIO157_A18", out_lo, "nmk-ske-keypad"), /* O7 */
-        DB8500_PIN("GPIO158_C18", out_lo, "nmk-ske-keypad"), /* O6 */
-        DB8500_PIN("GPIO159_B19", out_lo, "nmk-ske-keypad"), /* O5 */
-        DB8500_PIN("GPIO160_B20", out_lo, "nmk-ske-keypad"), /* O4 */
-        DB8500_PIN("GPIO165_C21", out_lo, "nmk-ske-keypad"), /* O3 */
-        DB8500_PIN("GPIO166_A22", out_lo, "nmk-ske-keypad"), /* O2 */
-        DB8500_PIN("GPIO167_B24", out_lo, "nmk-ske-keypad"), /* O1 */
-        DB8500_PIN("GPIO168_C22", out_lo, "nmk-ske-keypad"), /* O0 */
-        /* ske sleep state */
-        DB8500_PIN_SLEEP("GPIO153_B17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I7 */
-        DB8500_PIN_SLEEP("GPIO154_C16", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I6 */
-        DB8500_PIN_SLEEP("GPIO155_C19", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I5 */
-        DB8500_PIN_SLEEP("GPIO156_C17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I4 */
-        DB8500_PIN_SLEEP("GPIO161_D21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I3 */
-        DB8500_PIN_SLEEP("GPIO162_D20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I2 */
-        DB8500_PIN_SLEEP("GPIO163_C20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I1 */
-        DB8500_PIN_SLEEP("GPIO164_B21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I0 */
-        DB8500_PIN_SLEEP("GPIO157_A18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O7 */
-        DB8500_PIN_SLEEP("GPIO158_C18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O6 */
-        DB8500_PIN_SLEEP("GPIO159_B19", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O5 */
-        DB8500_PIN_SLEEP("GPIO160_B20", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O4 */
-        DB8500_PIN_SLEEP("GPIO165_C21", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O3 */
-        DB8500_PIN_SLEEP("GPIO166_A22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O2 */
-        DB8500_PIN_SLEEP("GPIO167_B24", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O1 */
-        DB8500_PIN_SLEEP("GPIO168_C22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O0 */
-
-        /* STM APE pins states */
-        DB8500_MUX_STATE("stmape_c_1", "stmape",
-                "stm", "ape_mipi34"),
-        DB8500_PIN_STATE("GPIO70_G5", in_nopull,
-                "stm", "ape_mipi34"), /* clk */
-        DB8500_PIN_STATE("GPIO71_G4", in_nopull,
-                "stm", "ape_mipi34"), /* dat3 */
-        DB8500_PIN_STATE("GPIO72_H4", in_nopull,
-                "stm", "ape_mipi34"), /* dat2 */
-        DB8500_PIN_STATE("GPIO73_H3", in_nopull,
-                "stm", "ape_mipi34"), /* dat1 */
-        DB8500_PIN_STATE("GPIO74_J3", in_nopull,
-                "stm", "ape_mipi34"), /* dat0 */
-
-        DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
-                "stm", "ape_mipi34_sleep"), /* clk */
-        DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
-                "stm", "ape_mipi34_sleep"), /* dat3 */
-        DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
-                "stm", "ape_mipi34_sleep"), /* dat2 */
-        DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
-                "stm", "ape_mipi34_sleep"), /* dat1 */
-        DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
-                "stm", "ape_mipi34_sleep"), /* dat0 */
-
-        DB8500_MUX_STATE("stmape_oc1_1", "stmape",
-                "stm", "ape_microsd"),
-        DB8500_PIN_STATE("GPIO23_AA4", in_nopull,
-                "stm", "ape_microsd"), /* clk */
-        DB8500_PIN_STATE("GPIO25_Y4", in_nopull,
-                "stm", "ape_microsd"), /* dat0 */
-        DB8500_PIN_STATE("GPIO26_Y2", in_nopull,
-                "stm", "ape_microsd"), /* dat1 */
-        DB8500_PIN_STATE("GPIO27_AA2", in_nopull,
-                "stm", "ape_microsd"), /* dat2 */
-        DB8500_PIN_STATE("GPIO28_AA1", in_nopull,
-                "stm", "ape_microsd"), /* dat3 */
-
-        DB8500_PIN_STATE("GPIO23_AA4", slpm_out_lo_wkup_pdis,
-                "stm", "ape_microsd_sleep"), /* clk */
-        DB8500_PIN_STATE("GPIO25_Y4", slpm_in_wkup_pdis,
-                "stm", "ape_microsd_sleep"), /* dat0 */
-        DB8500_PIN_STATE("GPIO26_Y2", slpm_in_wkup_pdis,
-                "stm", "ape_microsd_sleep"), /* dat1 */
-        DB8500_PIN_STATE("GPIO27_AA2", slpm_in_wkup_pdis,
-                "stm", "ape_microsd_sleep"), /* dat2 */
-        DB8500_PIN_STATE("GPIO28_AA1", slpm_in_wkup_pdis,
-                "stm", "ape_microsd_sleep"), /* dat3 */
-
-        /*  STM Modem pins states */
-        DB8500_MUX_STATE("stmmod_oc3_2", "stmmod",
-                "stm", "mod_mipi34"),
-        DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
-                "stm", "mod_mipi34"),
-        DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
-                "stm", "mod_mipi34"),
-        DB8500_PIN_STATE("GPIO70_G5", in_nopull,
-                "stm", "mod_mipi34"), /* clk */
-        DB8500_PIN_STATE("GPIO71_G4", in_nopull,
-                "stm", "mod_mipi34"), /* dat3 */
-        DB8500_PIN_STATE("GPIO72_H4", in_nopull,
-                "stm", "mod_mipi34"), /* dat2 */
-        DB8500_PIN_STATE("GPIO73_H3", in_nopull,
-                "stm", "mod_mipi34"), /* dat1 */
-        DB8500_PIN_STATE("GPIO74_J3", in_nopull,
-                "stm", "mod_mipi34"), /* dat0 */
-        DB8500_PIN_STATE("GPIO75_H2", in_pu,
-                "stm", "mod_mipi34"), /* uartmod rx */
-        DB8500_PIN_STATE("GPIO76_J2", out_lo,
-                "stm", "mod_mipi34"), /* uartmod tx */
-
-        DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
-                "stm", "mod_mipi34_sleep"), /* clk */
-        DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
-                "stm", "mod_mipi34_sleep"), /* dat3 */
-        DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
-                "stm", "mod_mipi34_sleep"), /* dat2 */
-        DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
-                "stm", "mod_mipi34_sleep"), /* dat1 */
-        DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
-                "stm", "mod_mipi34_sleep"), /* dat0 */
-        DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
-                "stm", "mod_mipi34_sleep"), /* uartmod rx */
-        DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
-                "stm", "mod_mipi34_sleep"), /* uartmod tx */
-
-        DB8500_MUX_STATE("stmmod_b_1", "stmmod",
-                "stm", "mod_microsd"),
-        DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
-                "stm", "mod_microsd"),
-        DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
-                "stm", "mod_microsd"),
-        DB8500_PIN_STATE("GPIO23_AA4", in_nopull,
-                "stm", "mod_microsd"), /* clk */
-        DB8500_PIN_STATE("GPIO25_Y4", in_nopull,
-                "stm", "mod_microsd"), /* dat0 */
-        DB8500_PIN_STATE("GPIO26_Y2", in_nopull,
-                "stm", "mod_microsd"), /* dat1 */
-        DB8500_PIN_STATE("GPIO27_AA2", in_nopull,
-                "stm", "mod_microsd"), /* dat2 */
-        DB8500_PIN_STATE("GPIO28_AA1", in_nopull,
-                "stm", "mod_microsd"), /* dat3 */
-        DB8500_PIN_STATE("GPIO75_H2", in_pu,
-                "stm", "mod_microsd"), /* uartmod rx */
-        DB8500_PIN_STATE("GPIO76_J2", out_lo,
-                "stm", "mod_microsd"), /* uartmod tx */
-
-        DB8500_PIN_STATE("GPIO23_AA4", slpm_out_lo_wkup_pdis,
-                "stm", "mod_microsd_sleep"), /* clk */
-        DB8500_PIN_STATE("GPIO25_Y4", slpm_in_wkup_pdis,
-                "stm", "mod_microsd_sleep"), /* dat0 */
-        DB8500_PIN_STATE("GPIO26_Y2", slpm_in_wkup_pdis,
-                "stm", "mod_microsd_sleep"), /* dat1 */
-        DB8500_PIN_STATE("GPIO27_AA2", slpm_in_wkup_pdis,
-                "stm", "mod_microsd_sleep"), /* dat2 */
-        DB8500_PIN_STATE("GPIO28_AA1", slpm_in_wkup_pdis,
-                "stm", "mod_microsd_sleep"), /* dat3 */
-        DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
-                "stm", "mod_microsd_sleep"), /* uartmod rx */
-        DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
-                "stm", "mod_microsd_sleep"), /* uartmod tx */
-
-        /*  STM dual Modem/APE pins state */
-        DB8500_MUX_STATE("stmmod_oc3_2", "stmmod",
-                "stm", "mod_mipi34_ape_mipi60"),
-        DB8500_MUX_STATE("stmape_c_2", "stmape",
-                "stm", "mod_mipi34_ape_mipi60"),
-        DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
-                "stm", "mod_mipi34_ape_mipi60"),
-        DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
-                "stm", "mod_mipi34_ape_mipi60"),
-        DB8500_PIN_STATE("GPIO70_G5", in_nopull,
-                "stm", "mod_mipi34_ape_mipi60"), /* clk */
-        DB8500_PIN_STATE("GPIO71_G4", in_nopull,
-                "stm", "mod_mipi34_ape_mipi60"), /* dat3 */
-        DB8500_PIN_STATE("GPIO72_H4", in_nopull,
-                "stm", "mod_mipi34_ape_mipi60"), /* dat2 */
-        DB8500_PIN_STATE("GPIO73_H3", in_nopull,
-                "stm", "mod_mipi34_ape_mipi60"), /* dat1 */
-        DB8500_PIN_STATE("GPIO74_J3", in_nopull,
-                "stm", "mod_mipi34_ape_mipi60"), /* dat0 */
-        DB8500_PIN_STATE("GPIO75_H2", in_pu,
-                "stm", "mod_mipi34_ape_mipi60"), /* uartmod rx */
-        DB8500_PIN_STATE("GPIO76_J2", out_lo,
-                "stm", "mod_mipi34_ape_mipi60"), /* uartmod tx */
-        DB8500_PIN_STATE("GPIO155_C19", in_nopull,
-                "stm", "mod_mipi34_ape_mipi60"), /* clk */
-        DB8500_PIN_STATE("GPIO156_C17", in_nopull,
-                "stm", "mod_mipi34_ape_mipi60"), /* dat3 */
-        DB8500_PIN_STATE("GPIO157_A18", in_nopull,
-                "stm", "mod_mipi34_ape_mipi60"), /* dat2 */
-        DB8500_PIN_STATE("GPIO158_C18", in_nopull,
-                "stm", "mod_mipi34_ape_mipi60"), /* dat1 */
-        DB8500_PIN_STATE("GPIO159_B19", in_nopull,
-                "stm", "mod_mipi34_ape_mipi60"), /* dat0 */
-
-        DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
-                "stm", "mod_mipi34_ape_mipi60_sleep"), /* clk */
-        DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
-                "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat3 */
-        DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
-                "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat2 */
-        DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
-                "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat1 */
-        DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
-                "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat0 */
-        DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
-                "stm", "mod_mipi34_ape_mipi60_sleep"), /* uartmod rx */
-        DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
-                "stm", "mod_mipi34_ape_mipi60_sleep"), /* uartmod tx */
-        DB8500_PIN_STATE("GPIO155_C19", slpm_in_wkup_pdis,
-                "stm", "mod_mipi34_ape_mipi60_sleep"), /* clk */
-        DB8500_PIN_STATE("GPIO156_C17", slpm_in_wkup_pdis,
-                "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat3 */
-        DB8500_PIN_STATE("GPIO157_A18", slpm_in_wkup_pdis,
-                "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat2 */
-        DB8500_PIN_STATE("GPIO158_C18", slpm_in_wkup_pdis,
-                "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat1 */
-        DB8500_PIN_STATE("GPIO159_B19", slpm_in_wkup_pdis,
-                "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat0 */
-};
-
-/*
- * These are specifically for the MOP500 and HREFP (pre-v60) version of the
- * board, which utilized a TC35892 GPIO expander instead of using a lot of
- * on-chip pins as the HREFv60 and later does.
- */
-static struct pinctrl_map __initdata mop500_pinmap[] = {
-        /* Mux in SSP0, pull down RXD pin */
-        DB8500_MUX_HOG("ssp0_a_1", "ssp0"),
-        DB8500_PIN_HOG("GPIO145_C13", pd),
-        /*
-         * XENON Flashgun on image processor GPIO (controlled from image
-         * processor firmware), mux in these image processor GPIO lines 0
-         * (XENON_FLASH_ID) and 1 (XENON_READY) on altfunction C and pull up
-         * the pins.
-         */
-        DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"),
-        DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"),
-        DB8500_PIN_HOG("GPIO6_AF6", in_pu),
-        DB8500_PIN_HOG("GPIO7_AG5", in_pu),
-        /* TC35892 IRQ, pull up the line, let the driver mux in the pin */
-        DB8500_PIN_HOG("GPIO217_AH12", gpio_in_pu),
-        /* Mux in UART1 and set the pull-ups */
-        DB8500_MUX_HOG("u1rxtx_a_1", "u1"),
-        DB8500_PIN_HOG("GPIO4_AH6", in_pu), /* RXD */
-        DB8500_PIN_HOG("GPIO5_AG6", out_hi), /* TXD */
-        /*
-         * Runtime stuff: make it possible to mux in the SKE keypad
-         * and bias the pins
-         */
-        /* ske default state */
-        DB8500_MUX("kp_a_2", "kp", "nmk-ske-keypad"),
-        DB8500_PIN("GPIO153_B17", in_pu, "nmk-ske-keypad"), /* I7 */
-        DB8500_PIN("GPIO154_C16", in_pu, "nmk-ske-keypad"), /* I6 */
-        DB8500_PIN("GPIO155_C19", in_pu, "nmk-ske-keypad"), /* I5 */
-        DB8500_PIN("GPIO156_C17", in_pu, "nmk-ske-keypad"), /* I4 */
-        DB8500_PIN("GPIO161_D21", in_pu, "nmk-ske-keypad"), /* I3 */
-        DB8500_PIN("GPIO162_D20", in_pu, "nmk-ske-keypad"), /* I2 */
-        DB8500_PIN("GPIO163_C20", in_pu, "nmk-ske-keypad"), /* I1 */
-        DB8500_PIN("GPIO164_B21", in_pu, "nmk-ske-keypad"), /* I0 */
-        DB8500_PIN("GPIO157_A18", out_lo, "nmk-ske-keypad"), /* O7 */
-        DB8500_PIN("GPIO158_C18", out_lo, "nmk-ske-keypad"), /* O6 */
-        DB8500_PIN("GPIO159_B19", out_lo, "nmk-ske-keypad"), /* O5 */
-        DB8500_PIN("GPIO160_B20", out_lo, "nmk-ske-keypad"), /* O4 */
-        DB8500_PIN("GPIO165_C21", out_lo, "nmk-ske-keypad"), /* O3 */
-        DB8500_PIN("GPIO166_A22", out_lo, "nmk-ske-keypad"), /* O2 */
-        DB8500_PIN("GPIO167_B24", out_lo, "nmk-ske-keypad"), /* O1 */
-        DB8500_PIN("GPIO168_C22", out_lo, "nmk-ske-keypad"), /* O0 */
-        /* ske sleep state */
-        DB8500_PIN_SLEEP("GPIO153_B17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I7 */
-        DB8500_PIN_SLEEP("GPIO154_C16", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I6 */
-        DB8500_PIN_SLEEP("GPIO155_C19", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I5 */
-        DB8500_PIN_SLEEP("GPIO156_C17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I4 */
-        DB8500_PIN_SLEEP("GPIO161_D21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I3 */
-        DB8500_PIN_SLEEP("GPIO162_D20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I2 */
-        DB8500_PIN_SLEEP("GPIO163_C20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I1 */
-        DB8500_PIN_SLEEP("GPIO164_B21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I0 */
-        DB8500_PIN_SLEEP("GPIO157_A18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O7 */
-        DB8500_PIN_SLEEP("GPIO158_C18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O6 */
-        DB8500_PIN_SLEEP("GPIO159_B19", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O5 */
-        DB8500_PIN_SLEEP("GPIO160_B20", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O4 */
-        DB8500_PIN_SLEEP("GPIO165_C21", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O3 */
-        DB8500_PIN_SLEEP("GPIO166_A22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O2 */
-        DB8500_PIN_SLEEP("GPIO167_B24", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O1 */
-        DB8500_PIN_SLEEP("GPIO168_C22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O0 */
-
-        /* Mux in and drive the SDI0 DAT31DIR line high at runtime */
-        DB8500_MUX("mc0dat31dir_a_1", "mc0", "sdi0"),
-        DB8500_PIN("GPIO21_AB3", out_hi, "sdi0"),
-};
-
-/*
- * The HREFv60 series of platforms is using available pins on the DB8500
- * insteaf of the Toshiba I2C GPIO expander, reusing some pins like the SSP0
- * and SSP1 ports (previously connected to the AB8500) as generic GPIO lines.
- */
-static struct pinctrl_map __initdata hrefv60_pinmap[] = {
-        /* Drive WLAN_ENA low */
-        DB8500_PIN_HOG("GPIO85_D5", gpio_out_lo), /* WLAN_ENA */
-        /*
-         * XENON Flashgun on image processor GPIO (controlled from image
-         * processor firmware), mux in these image processor GPIO lines 0
-         * (XENON_FLASH_ID), 1 (XENON_READY) and there is an assistant
-         * LED on IP GPIO 4 (XENON_EN2) on altfunction C, that need bias
-         * from GPIO21 so pull up 0, 1 and drive 4 and GPIO21 low as output.
-         */
-        DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"),
-        DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"),
-        DB8500_MUX_HOG("ipgpio4_c_1", "ipgpio"),
-        DB8500_PIN_HOG("GPIO6_AF6", in_pu), /* XENON_FLASH_ID */
-        DB8500_PIN_HOG("GPIO7_AG5", in_pu), /* XENON_READY */
-        DB8500_PIN_HOG("GPIO21_AB3", gpio_out_lo), /* XENON_EN1 */
-        DB8500_PIN_HOG("GPIO64_F3", out_lo), /* XENON_EN2 */
-        /* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */
-        DB8500_PIN_HOG("GPIO31_V3", gpio_in_pu), /* EN1 */
-        DB8500_PIN_HOG("GPIO32_V2", gpio_in_pd), /* DRDY */
-        /*
-         * Display Interface 1 uses GPIO 65 for RST (reset).
-         * Display Interface 2 uses GPIO 66 for RST (reset).
-         * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset)
-         */
-        DB8500_PIN_HOG("GPIO65_F1", gpio_out_hi), /* DISP1 NO RST */
-        DB8500_PIN_HOG("GPIO66_G3", gpio_out_lo), /* DISP2 RST */
-        /*
-         * Touch screen uses GPIO 143 for RST1, GPIO 146 for RST2 and
-         * GPIO 67 for interrupts. Pull-up the IRQ line and drive both
-         * reset signals low.
-         */
-        DB8500_PIN_HOG("GPIO143_D12", gpio_out_lo), /* TOUCH_RST1 */
-        DB8500_PIN_HOG("GPIO67_G2", gpio_in_pu), /* TOUCH_INT2 */
-        DB8500_PIN_HOG("GPIO146_D13", gpio_out_lo), /* TOUCH_RST2 */
-        /*
-         * Drive D19-D23 for the ETM PTM trace interface low,
-         * (presumably pins are unconnected therefore grounded here,
-         * the "other alt C1" setting enables these pins)
-         */
-        DB8500_PIN_HOG("GPIO70_G5", gpio_out_lo),
-        DB8500_PIN_HOG("GPIO71_G4", gpio_out_lo),
-        DB8500_PIN_HOG("GPIO72_H4", gpio_out_lo),
-        DB8500_PIN_HOG("GPIO73_H3", gpio_out_lo),
-        DB8500_PIN_HOG("GPIO74_J3", gpio_out_lo),
-        /* NAHJ CTRL on GPIO 76 to low, CTRL_INV on GPIO216 to high */
-        DB8500_PIN_HOG("GPIO76_J2", gpio_out_lo), /* CTRL */
-        DB8500_PIN_HOG("GPIO216_AG12", gpio_out_hi), /* CTRL_INV */
-        /* NFC ENA and RESET to low, pulldown IRQ line */
-        DB8500_PIN_HOG("GPIO77_H1", gpio_out_lo), /* NFC_ENA */
-        DB8500_PIN_HOG("GPIO144_B13", gpio_in_pd), /* NFC_IRQ */
-        DB8500_PIN_HOG("GPIO142_C11", gpio_out_lo), /* NFC_RESET */
-        /*
-         * SKE keyboard partly on alt A and partly on "Other alt C1"
-         * Driver KP_O1,2,3,6,7 low and pull up KP_I 0,2,3 for three
-         * rows of 6 keys, then pull up force sensing interrup and
-         * drive reset and force sensing WU low.
-         */
-        DB8500_MUX_HOG("kp_a_1", "kp"),
-        DB8500_MUX_HOG("kp_oc1_1", "kp"),
-        DB8500_PIN_HOG("GPIO90_A3", out_lo), /* KP_O1 */
-        DB8500_PIN_HOG("GPIO87_B3", out_lo), /* KP_O2 */
-        DB8500_PIN_HOG("GPIO86_C6", out_lo), /* KP_O3 */
-        DB8500_PIN_HOG("GPIO96_D8", out_lo), /* KP_O6 */
-        DB8500_PIN_HOG("GPIO94_D7", out_lo), /* KP_O7 */
-        DB8500_PIN_HOG("GPIO93_B7", in_pu), /* KP_I0 */
-        DB8500_PIN_HOG("GPIO89_E6", in_pu), /* KP_I2 */
-        DB8500_PIN_HOG("GPIO88_C4", in_pu), /* KP_I3 */
-        DB8500_PIN_HOG("GPIO91_B6", gpio_in_pu), /* FORCE_SENSING_INT */
-        DB8500_PIN_HOG("GPIO92_D6", gpio_out_lo), /* FORCE_SENSING_RST */
-        DB8500_PIN_HOG("GPIO97_D9", gpio_out_lo), /* FORCE_SENSING_WU */
-        /* DiPro Sensor interrupt */
-        DB8500_PIN_HOG("GPIO139_C9", gpio_in_pu), /* DIPRO_INT */
-        /* Audio Amplifier HF enable */
-        DB8500_PIN_HOG("GPIO149_B14", gpio_out_hi), /* VAUDIO_HF_EN, enable MAX8968 */
-        /* GBF interface, pull low to reset state */
-        DB8500_PIN_HOG("GPIO171_D23", gpio_out_lo), /* GBF_ENA_RESET */
-        /* MSP : HDTV INTERFACE GPIO line */
-        DB8500_PIN_HOG("GPIO192_AJ27", gpio_in_pd),
-        /* Accelerometer interrupt lines */
-        DB8500_PIN_HOG("GPIO82_C1", gpio_in_pu), /* ACC_INT1 */
-        DB8500_PIN_HOG("GPIO83_D3", gpio_in_pu), /* ACC_INT2 */
-        /* SD card detect GPIO pin */
-        DB8500_PIN_HOG("GPIO95_E8", gpio_in_pu),
-        /*
-         * Runtime stuff
-         * Pull up/down of some sensor GPIO pins, for proximity, HAL sensor
-         * etc.
-         */
-        DB8500_PIN("GPIO217_AH12", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"),
-        DB8500_PIN("GPIO145_C13", gpio_in_pd_slpm_gpio_nopull, "gpio-keys.0"),
-        DB8500_PIN("GPIO139_C9", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"),
-};
-
-static struct pinctrl_map __initdata u9500_pinmap[] = {
-        /* Mux in UART1 (just RX/TX) and set the pull-ups */
-        DB8500_MUX_HOG("u1rxtx_a_1", "u1"),
-        DB8500_PIN_HOG("GPIO4_AH6", in_pu),
-        DB8500_PIN_HOG("GPIO5_AG6", out_hi),
-        /* WLAN_IRQ line */
-        DB8500_PIN_HOG("GPIO144_B13", gpio_in_pu),
-        /* HSI */
-        DB8500_MUX_HOG("hsir_a_1", "hsi"),
-        DB8500_MUX_HOG("hsit_a_2", "hsi"),
-        DB8500_PIN_HOG("GPIO219_AG10", in_pd), /* RX FLA0 */
-        DB8500_PIN_HOG("GPIO220_AH10", in_pd), /* RX DAT0 */
-        DB8500_PIN_HOG("GPIO221_AJ11", out_lo), /* RX RDY0 */
-        DB8500_PIN_HOG("GPIO222_AJ9", out_lo), /* TX FLA0 */
-        DB8500_PIN_HOG("GPIO223_AH9", out_lo), /* TX DAT0 */
-        DB8500_PIN_HOG("GPIO224_AG9", in_pd), /* TX RDY0 */
-        DB8500_PIN_HOG("GPIO225_AG8", in_pd), /* CAWAKE0 */
-        DB8500_PIN_HOG("GPIO226_AF8", gpio_out_hi), /* ACWAKE0 */
-};
-
-static struct pinctrl_map __initdata u8500_pinmap[] = {
-        DB8500_PIN_HOG("GPIO226_AF8", gpio_out_lo), /* WLAN_PMU_EN */
-        DB8500_PIN_HOG("GPIO4_AH6", gpio_in_pu), /* WLAN_IRQ */
-};
-
-static struct pinctrl_map __initdata snowball_pinmap[] = {
-        /* Mux in SSP0 connected to AB8500, pull down RXD pin */
-        DB8500_MUX_HOG("ssp0_a_1", "ssp0"),
-        DB8500_PIN_HOG("GPIO145_C13", pd),
-        /* Always drive the MC0 DAT31DIR line high on these boards */
-        DB8500_PIN_HOG("GPIO21_AB3", out_hi),
-        /* Mux in "SM" which is used for the SMSC911x Ethernet adapter */
-        DB8500_MUX_HOG("sm_b_1", "sm"),
-        /* User LED */
-        DB8500_PIN_HOG("GPIO142_C11", gpio_out_hi),
-        /* Drive RSTn_LAN high */
-        DB8500_PIN_HOG("GPIO141_C12", gpio_out_hi),
-        /*  Accelerometer/Magnetometer */
-        DB8500_PIN_HOG("GPIO163_C20", gpio_in_pu), /* ACCEL_IRQ1 */
-        DB8500_PIN_HOG("GPIO164_B21", gpio_in_pu), /* ACCEL_IRQ2 */
-        DB8500_PIN_HOG("GPIO165_C21", gpio_in_pu), /* MAG_DRDY */
-        /* WLAN/GBF */
-        DB8500_PIN_HOG("GPIO161_D21", gpio_out_lo), /* WLAN_PMU_EN */
-        DB8500_PIN_HOG("GPIO171_D23", gpio_out_hi), /* GBF_ENA */
-        DB8500_PIN_HOG("GPIO215_AH13", gpio_out_lo), /* WLAN_ENA */
-        DB8500_PIN_HOG("GPIO216_AG12", gpio_in_pu), /* WLAN_IRQ */
-};
-
-/*
- * passing "pinsfor=" in kernel cmdline allows for custom
- * configuration of GPIOs on u8500 derived boards.
- */
-static int __init early_pinsfor(char *p)
-{
-        pinsfor = PINS_FOR_DEFAULT;
-
-        if (strcmp(p, "u9500-21") == 0)
-                pinsfor = PINS_FOR_U9500;
-
-        return 0;
-}
-early_param("pinsfor", early_pinsfor);
-
-int pins_for_u9500(void)
-{
-        if (pinsfor == PINS_FOR_U9500)
-                return 1;
-
-        return 0;
-}
-
-static void __init mop500_href_family_pinmaps_init(void)
-{
-        switch (pinsfor) {
-        case PINS_FOR_U9500:
-                pinctrl_register_mappings(u9500_pinmap,
-                                          ARRAY_SIZE(u9500_pinmap));
-                break;
-        case PINS_FOR_DEFAULT:
-                pinctrl_register_mappings(u8500_pinmap,
-                                          ARRAY_SIZE(u8500_pinmap));
-        default:
-                break;
-        }
-}
-
 void __init mop500_pinmaps_init(void)
 {
-        pinctrl_register_mappings(mop500_family_pinmap,
-                                  ARRAY_SIZE(mop500_family_pinmap));
-        pinctrl_register_mappings(mop500_pinmap,
-                                  ARRAY_SIZE(mop500_pinmap));
-        mop500_href_family_pinmaps_init();
         if (machine_is_u8520())
                 pinctrl_register_mappings(ab8505_pinmap,
                                           ARRAY_SIZE(ab8505_pinmap));
@@ -1073,23 +280,12 @@ void __init mop500_pinmaps_init(void)
 
 void __init snowball_pinmaps_init(void)
 {
-        pinctrl_register_mappings(mop500_family_pinmap,
-                                  ARRAY_SIZE(mop500_family_pinmap));
-        pinctrl_register_mappings(snowball_pinmap,
-                                  ARRAY_SIZE(snowball_pinmap));
-        pinctrl_register_mappings(u8500_pinmap,
-                                  ARRAY_SIZE(u8500_pinmap));
         pinctrl_register_mappings(ab8500_pinmap,
                                   ARRAY_SIZE(ab8500_pinmap));
 }
 
 void __init hrefv60_pinmaps_init(void)
 {
-        pinctrl_register_mappings(mop500_family_pinmap,
-                                  ARRAY_SIZE(mop500_family_pinmap));
-        pinctrl_register_mappings(hrefv60_pinmap,
-                                  ARRAY_SIZE(hrefv60_pinmap));
-        mop500_href_family_pinmaps_init();
         pinctrl_register_mappings(ab8500_pinmap,
                                   ARRAY_SIZE(ab8500_pinmap));
 }
diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c
index 0dc44c683427..a4e139aa2441 100644
--- a/arch/arm/mach-ux500/board-mop500-regulators.c
+++ b/arch/arm/mach-ux500/board-mop500-regulators.c
@@ -30,20 +30,6 @@ struct regulator_init_data gpio_en_3v3_regulator = {
        .consumer_supplies = gpio_en_3v3_consumers,
 };
 
-static struct regulator_consumer_supply sdi0_reg_consumers[] = {
-        REGULATOR_SUPPLY("vqmmc", "sdi0"),
-};
-
-struct regulator_init_data sdi0_reg_init_data = {
-        .constraints = {
-                .min_uV         = 1800000,
-                .max_uV         = 2900000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE|REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(sdi0_reg_consumers),
-        .consumer_supplies      = sdi0_reg_consumers,
-};
-
 /*
  * TPS61052 regulator
  */
diff --git a/arch/arm/mach-ux500/board-mop500-regulators.h b/arch/arm/mach-ux500/board-mop500-regulators.h
index 039f5132c370..9bece38fe933 100644
--- a/arch/arm/mach-ux500/board-mop500-regulators.h
+++ b/arch/arm/mach-ux500/board-mop500-regulators.h
@@ -18,7 +18,6 @@ extern struct ab8500_regulator_platform_data ab8500_regulator_plat_data;
 extern struct ab8500_regulator_platform_data ab8505_regulator_plat_data;
 extern struct regulator_init_data tps61052_regulator;
 extern struct regulator_init_data gpio_en_3v3_regulator;
-extern struct regulator_init_data sdi0_reg_init_data;
 
 void mop500_regulator_init(void);
 
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 26600a1c5319..fcbf3a13a539 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -14,10 +14,8 @@
 #include <linux/platform_data/dma-ste-dma40.h>
 
 #include <asm/mach-types.h>
-#include "devices.h"
 
 #include "db8500-regs.h"
-#include "devices-db8500.h"
 #include "board-mop500.h"
 #include "ste-dma40-db8500.h"
 
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
deleted file mode 100644
index 514d40b625a4..000000000000
--- a/arch/arm/mach-ux500/board-mop500.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright (C) 2008-2012 ST-Ericsson
- *
- * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2, as
- * published by the Free Software Foundation.
- *
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/platform_data/db8500_thermal.h>
-#include <linux/amba/bus.h>
-#include <linux/amba/pl022.h>
-#include <linux/mfd/abx500/ab8500.h>
-#include <linux/regulator/ab8500.h>
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/driver.h>
-#include <linux/mfd/tps6105x.h>
-#include <linux/platform_data/leds-lp55xx.h>
-#include <linux/input.h>
-#include <linux/delay.h>
-#include <linux/leds.h>
-#include <linux/pinctrl/consumer.h>
-#include <linux/platform_data/pinctrl-nomadik.h>
-#include <linux/platform_data/dma-ste-dma40.h>
-
-#include <asm/mach-types.h>
-
-#include "setup.h"
-#include "devices.h"
-#include "irqs.h"
-
-#include "ste-dma40-db8500.h"
-#include "db8500-regs.h"
-#include "devices-db8500.h"
-#include "board-mop500.h"
-#include "board-mop500-regulators.h"
-
-struct ab8500_platform_data ab8500_platdata = {
-        .irq_base       = MOP500_AB8500_IRQ_BASE,
-        .regulator      = &ab8500_regulator_plat_data,
-};
-
-#ifdef CONFIG_STE_DMA40
-static struct stedma40_chan_cfg ssp0_dma_cfg_rx = {
-        .mode = STEDMA40_MODE_LOGICAL,
-        .dir = DMA_DEV_TO_MEM,
-        .dev_type = DB8500_DMA_DEV8_SSP0,
-};
-
-static struct stedma40_chan_cfg ssp0_dma_cfg_tx = {
-        .mode = STEDMA40_MODE_LOGICAL,
-        .dir = DMA_MEM_TO_DEV,
-        .dev_type = DB8500_DMA_DEV8_SSP0,
-};
-#endif
-
-struct pl022_ssp_controller ssp0_plat = {
-        .bus_id = 0,
-#ifdef CONFIG_STE_DMA40
-        .enable_dma = 1,
-        .dma_filter = stedma40_filter,
-        .dma_rx_param = &ssp0_dma_cfg_rx,
-        .dma_tx_param = &ssp0_dma_cfg_tx,
-#else
-        .enable_dma = 0,
-#endif
-        /* on this platform, gpio 31,142,144,214 &
-         * 224 are connected as chip selects
-         */
-        .num_chipselect = 5,
-};
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index 511d6febbe99..d48e8662c676 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -87,7 +87,6 @@ extern struct msp_i2s_platform_data msp0_platform_data;
 extern struct msp_i2s_platform_data msp1_platform_data;
 extern struct msp_i2s_platform_data msp2_platform_data;
 extern struct msp_i2s_platform_data msp3_platform_data;
-extern struct pl022_ssp_controller ssp0_plat;
 
 void __init mop500_pinmaps_init(void);
 void __init snowball_pinmaps_init(void);
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 12c7e5c03ea4..bc8a6183560d 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -21,21 +21,32 @@
 #include <linux/of.h>
 #include <linux/of_platform.h>
 #include <linux/regulator/machine.h>
-#include <linux/platform_data/pinctrl-nomadik.h>
 #include <linux/random.h>
 
 #include <asm/pmu.h>
 #include <asm/mach/map.h>
 
 #include "setup.h"
-#include "devices.h"
 #include "irqs.h"
 
-#include "devices-db8500.h"
-#include "db8500-regs.h"
+#include "board-mop500-regulators.h"
 #include "board-mop500.h"
+#include "db8500-regs.h"
 #include "id.h"
 
+struct ab8500_platform_data ab8500_platdata = {
+        .irq_base       = MOP500_AB8500_IRQ_BASE,
+        .regulator      = &ab8500_regulator_plat_data,
+};
+
+struct prcmu_pdata db8500_prcmu_pdata = {
+        .ab_platdata    = &ab8500_platdata,
+        .ab_irq         = IRQ_DB8500_AB8500,
+        .irq_base       = IRQ_PRCMU_BASE,
+        .version_offset = DB8500_PRCMU_FW_VERSION_OFFSET,
+        .legacy_offset  = DB8500_PRCMU_LEGACY_OFFSET,
+};
+
 /* minimum static i/o mapping required to boot U8500 platforms */
 static struct map_desc u8500_uart_io_desc[] __initdata = {
         __IO_DEV_DESC(U8500_UART0_BASE, SZ_4K),
@@ -159,17 +170,10 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("stericsson,ux500-hash", 0xa03c2000, "hash1", NULL),
         OF_DEV_AUXDATA("stericsson,snd-soc-mop500", 0, "snd-soc-mop500.0",
                         NULL),
-        /* Requires device name bindings. */
-        OF_DEV_AUXDATA("stericsson,db8500-pinctrl", U8500_PRCMU_BASE,
-                "pinctrl-db8500", NULL),
         {},
 };
 
 static struct of_dev_auxdata u8540_auxdata_lookup[] __initdata = {
-        /* Requires DMA bindings. */
-        OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", NULL),
-        OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", NULL),
-        OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", NULL),
         OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu",
                         &db8500_prcmu_pdata),
         {},
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index f84d4397896b..d11ac4bf336c 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -25,7 +25,6 @@
 #include <asm/mach/map.h>
 
 #include "setup.h"
-#include "devices.h"
 
 #include "board-mop500.h"
 #include "db8500-regs.h"
@@ -64,12 +63,7 @@ void __init ux500_init_irq(void)
         } else
                 ux500_unknown_soc();
 
-#ifdef CONFIG_OF
-        if (of_have_populated_dt())
-                irqchip_init();
-        else
-#endif
-                gic_init(0, 29, dist_base, cpu_base);
+        irqchip_init();
 
         /*
          * Init clocks here so that they are available for system timer
@@ -79,16 +73,11 @@ void __init ux500_init_irq(void)
                 prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1);
                 ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1);
 
-                if (of_have_populated_dt())
-                        u8500_of_clk_init(U8500_CLKRST1_BASE,
-                                          U8500_CLKRST2_BASE,
-                                          U8500_CLKRST3_BASE,
-                                          U8500_CLKRST5_BASE,
-                                          U8500_CLKRST6_BASE);
-                else
-                        u8500_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
-                                       U8500_CLKRST3_BASE, U8500_CLKRST5_BASE,
-                                       U8500_CLKRST6_BASE);
+                u8500_of_clk_init(U8500_CLKRST1_BASE,
+                                  U8500_CLKRST2_BASE,
+                                  U8500_CLKRST3_BASE,
+                                  U8500_CLKRST5_BASE,
+                                  U8500_CLKRST6_BASE);
         } else if (cpu_is_u9540()) {
                 prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1);
                 ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1);
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
deleted file mode 100644
index c59f89d058ff..000000000000
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
- * License terms: GNU General Public License (GPL) version 2
- */
-
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include <linux/amba/bus.h>
-#include <linux/amba/pl022.h>
-#include <linux/mfd/dbx500-prcmu.h>
-
-#include "setup.h"
-#include "irqs.h"
-
-#include "db8500-regs.h"
-#include "devices-db8500.h"
-
-struct prcmu_pdata db8500_prcmu_pdata = {
-        .ab_platdata    = &ab8500_platdata,
-        .ab_irq         = IRQ_DB8500_AB8500,
-        .irq_base       = IRQ_PRCMU_BASE,
-        .version_offset = DB8500_PRCMU_FW_VERSION_OFFSET,
-        .legacy_offset  = DB8500_PRCMU_LEGACY_OFFSET,
-};
diff --git a/arch/arm/mach-ux500/devices-db8500.h b/arch/arm/mach-ux500/devices-db8500.h
deleted file mode 100644
index b8ffc9979bb2..000000000000
--- a/arch/arm/mach-ux500/devices-db8500.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
- * License terms: GNU General Public License (GPL), version 2.
- */
-
-#ifndef __DEVICES_DB8500_H
-#define __DEVICES_DB8500_H
-
-#include "irqs.h"
-#include "db8500-regs.h"
-
-struct platform_device;
-
-extern struct ab8500_platform_data ab8500_platdata;
-extern struct prcmu_pdata db8500_prcmu_pdata;
-
-#endif
diff --git a/arch/arm/mach-ux500/devices.c b/arch/arm/mach-ux500/devices.c
deleted file mode 100644
index 0f9e52b95935..000000000000
--- a/arch/arm/mach-ux500/devices.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
- * License terms: GNU General Public License (GPL) version 2
- */
-
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include <linux/amba/bus.h>
-
-#include "setup.h"
-
-#include "db8500-regs.h"
-
-void __init amba_add_devices(struct amba_device *devs[], int num)
-{
-        int i;
-
-        for (i = 0; i < num; i++) {
-                struct amba_device *d = devs[i];
-                amba_device_register(d, &iomem_resource);
-        }
-}
diff --git a/arch/arm/mach-ux500/devices.h b/arch/arm/mach-ux500/devices.h
deleted file mode 100644
index 5bca7c605cd6..000000000000
--- a/arch/arm/mach-ux500/devices.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License terms: GNU General Public License (GPL) version 2
- */
-
-#ifndef __ASM_ARCH_DEVICES_H__
-#define __ASM_ARCH_DEVICES_H__
-
-struct platform_device;
-struct amba_device;
-
-extern struct amba_device ux500_pl031_device;
-
-#endif
diff --git a/arch/arm/mach-ux500/setup.h b/arch/arm/mach-ux500/setup.h
index b1dd8584bed4..2dea8b59d222 100644
--- a/arch/arm/mach-ux500/setup.h
+++ b/arch/arm/mach-ux500/setup.h
@@ -19,17 +19,11 @@
 void ux500_restart(enum reboot_mode mode, const char *cmd);
 
 void __init ux500_map_io(void);
-extern void __init u8500_map_io(void);
-
-extern struct device * __init u8500_init_devices(void);
 
 extern void __init ux500_init_irq(void);
 
 extern struct device *ux500_soc_device_init(const char *soc_id);
 
-struct amba_device;
-extern void __init amba_add_devices(struct amba_device *devs[], int num);
-
 extern void ux500_timer_init(void);
 
 #define __IO_DEV_DESC(x, sz)    {               \
diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c
index 05a4ff78b3bd..87efda0aa348 100644
--- a/arch/arm/mach-ux500/timer.c
+++ b/arch/arm/mach-ux500/timer.c
@@ -10,40 +10,12 @@
 #include <linux/clocksource.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
-#include <linux/platform_data/clocksource-nomadik-mtu.h>
-
-#include <asm/smp_twd.h>
 
 #include "setup.h"
-#include "irqs.h"
 
 #include "db8500-regs.h"
 #include "id.h"
 
-#ifdef CONFIG_HAVE_ARM_TWD
-static DEFINE_TWD_LOCAL_TIMER(u8500_twd_local_timer,
-                              U8500_TWD_BASE, IRQ_LOCALTIMER);
-
-static void __init ux500_twd_init(void)
-{
-        struct twd_local_timer *twd_local_timer;
-        int err;
-
-        /* Use this to switch local timer base if changed in new ASICs */
-        twd_local_timer = &u8500_twd_local_timer;
-
-        if (of_have_populated_dt())
-                clocksource_of_init();
-        else {
-                err = twd_local_timer_register(twd_local_timer);
-                if (err)
-                        pr_err("twd_local_timer_register failed %d\n", err);
-        }
-}
-#else
-#define ux500_twd_init()        do { } while(0)
-#endif
-
 const static struct of_device_id prcmu_timer_of_match[] __initconst = {
         { .compatible = "stericsson,db8500-prcmu-timer-4", },
         { },
@@ -51,54 +23,26 @@ const static struct of_device_id prcmu_timer_of_match[] __initconst = {
 
 void __init ux500_timer_init(void)
 {
-        void __iomem *mtu_timer_base;
         void __iomem *prcmu_timer_base;
         void __iomem *tmp_base;
         struct device_node *np;
 
-        if (cpu_is_u8500_family() || cpu_is_ux540_family()) {
-                mtu_timer_base = __io_address(U8500_MTU0_BASE);
+        if (cpu_is_u8500_family() || cpu_is_ux540_family())
                 prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE);
-        } else {
+        else
                 ux500_unknown_soc();
-        }
 
-        /* TODO: Once MTU has been DT:ed place code above into else. */
-        if (of_have_populated_dt()) {
-#ifdef CONFIG_OF
-                np = of_find_matching_node(NULL, prcmu_timer_of_match);
-                if (!np)
-#endif
-                        goto dt_fail;
+        np = of_find_matching_node(NULL, prcmu_timer_of_match);
+        if (!np)
+                goto dt_fail;
 
-                tmp_base = of_iomap(np, 0);
-                if (!tmp_base)
-                        goto dt_fail;
+        tmp_base = of_iomap(np, 0);
+        if (!tmp_base)
+                goto dt_fail;
 
-                prcmu_timer_base = tmp_base;
-        }
+        prcmu_timer_base = tmp_base;
 
 dt_fail:
-        /* Doing it the old fashioned way. */
-
-        /*
-         * Here we register the timerblocks active in the system.
-         * Localtimers (twd) is started when both cpu is up and running.
-         * MTU register a clocksource, clockevent and sched_clock.
-         * Since the MTU is located in the VAPE power domain
-         * it will be cleared in sleep which makes it unsuitable.
-         * We however need it as a timer tick (clockevent)
-         * during boot to calibrate delay until twd is started.
-         * RTC-RTT have problems as timer tick during boot since it is
-         * depending on delay which is not yet calibrated. RTC-RTT is in the
-         * always-on powerdomain and is used as clockevent instead of twd when
-         * sleeping.
-         * The PRCMU timer 4 register a clocksource and
-         * sched_clock with higher rating then MTU since is always-on.
-         *
-         */
-        if (!of_have_populated_dt())
-                nmdk_timer_init(mtu_timer_base, IRQ_MTU0);
         clksrc_dbx500_prcmu_init(prcmu_timer_base);
-        ux500_twd_init();
+        clocksource_of_init();
 }
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index ace7309c4369..a3b7c5dd3c16 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_PLAT_SAMSUNG)	+= samsung/
 obj-$(CONFIG_COMMON_CLK_XGENE)  += clk-xgene.o
 obj-$(CONFIG_COMMON_CLK_KEYSTONE)       += keystone/
 obj-$(CONFIG_COMMON_CLK_AT91)   += at91/
+obj-$(CONFIG_ARCH_SHMOBILE_MULTI)       += shmobile/
 
 obj-$(CONFIG_X86)               += x86/
 
diff --git a/drivers/clk/shmobile/Makefile b/drivers/clk/shmobile/Makefile
new file mode 100644
index 000000000000..706adc6ae70c
--- /dev/null
+++ b/drivers/clk/shmobile/Makefile
@@ -0,0 +1,7 @@
+obj-$(CONFIG_ARCH_R8A7790)              += clk-rcar-gen2.o
+obj-$(CONFIG_ARCH_R8A7791)              += clk-rcar-gen2.o
+obj-$(CONFIG_ARCH_SHMOBILE_MULTI)       += clk-div6.o
+obj-$(CONFIG_ARCH_SHMOBILE_MULTI)       += clk-mstp.o
+
+# for emply built-in.o
+obj-n   := dummy
diff --git a/drivers/clk/shmobile/clk-div6.c b/drivers/clk/shmobile/clk-div6.c
new file mode 100644
index 000000000000..aac4756ec52e
--- /dev/null
+++ b/drivers/clk/shmobile/clk-div6.c
@@ -0,0 +1,185 @@
+/*
+ * r8a7790 Common Clock Framework support
+ *
+ * Copyright (C) 2013  Renesas Solutions Corp.
+ *
+ * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#define CPG_DIV6_CKSTP          BIT(8)
+#define CPG_DIV6_DIV(d)         ((d) & 0x3f)
+#define CPG_DIV6_DIV_MASK       0x3f
+
+/**
+ * struct div6_clock - MSTP gating clock
+ * @hw: handle between common and hardware-specific interfaces
+ * @reg: IO-remapped register
+ * @div: divisor value (1-64)
+ */
+struct div6_clock {
+        struct clk_hw hw;
+        void __iomem *reg;
+        unsigned int div;
+};
+
+#define to_div6_clock(_hw) container_of(_hw, struct div6_clock, hw)
+
+static int cpg_div6_clock_enable(struct clk_hw *hw)
+{
+        struct div6_clock *clock = to_div6_clock(hw);
+
+        clk_writel(CPG_DIV6_DIV(clock->div - 1), clock->reg);
+
+        return 0;
+}
+
+static void cpg_div6_clock_disable(struct clk_hw *hw)
+{
+        struct div6_clock *clock = to_div6_clock(hw);
+
+        /* DIV6 clocks require the divisor field to be non-zero when stopping
+         * the clock.
+         */
+        clk_writel(CPG_DIV6_CKSTP | CPG_DIV6_DIV(CPG_DIV6_DIV_MASK),
+                   clock->reg);
+}
+
+static int cpg_div6_clock_is_enabled(struct clk_hw *hw)
+{
+        struct div6_clock *clock = to_div6_clock(hw);
+
+        return !(clk_readl(clock->reg) & CPG_DIV6_CKSTP);
+}
+
+static unsigned long cpg_div6_clock_recalc_rate(struct clk_hw *hw,
+                                                unsigned long parent_rate)
+{
+        struct div6_clock *clock = to_div6_clock(hw);
+        unsigned int div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;
+
+        return parent_rate / div;
+}
+
+static unsigned int cpg_div6_clock_calc_div(unsigned long rate,
+                                            unsigned long parent_rate)
+{
+        unsigned int div;
+
+        div = DIV_ROUND_CLOSEST(parent_rate, rate);
+        return clamp_t(unsigned int, div, 1, 64);
+}
+
+static long cpg_div6_clock_round_rate(struct clk_hw *hw, unsigned long rate,
+                                      unsigned long *parent_rate)
+{
+        unsigned int div = cpg_div6_clock_calc_div(rate, *parent_rate);
+
+        return *parent_rate / div;
+}
+
+static int cpg_div6_clock_set_rate(struct clk_hw *hw, unsigned long rate,
+                                   unsigned long parent_rate)
+{
+        struct div6_clock *clock = to_div6_clock(hw);
+        unsigned int div = cpg_div6_clock_calc_div(rate, parent_rate);
+
+        clock->div = div;
+
+        /* Only program the new divisor if the clock isn't stopped. */
+        if (!(clk_readl(clock->reg) & CPG_DIV6_CKSTP))
+                clk_writel(CPG_DIV6_DIV(clock->div - 1), clock->reg);
+
+        return 0;
+}
+
+static const struct clk_ops cpg_div6_clock_ops = {
+        .enable = cpg_div6_clock_enable,
+        .disable = cpg_div6_clock_disable,
+        .is_enabled = cpg_div6_clock_is_enabled,
+        .recalc_rate = cpg_div6_clock_recalc_rate,
+        .round_rate = cpg_div6_clock_round_rate,
+        .set_rate = cpg_div6_clock_set_rate,
+};
+
+static void __init cpg_div6_clock_init(struct device_node *np)
+{
+        struct clk_init_data init;
+        struct div6_clock *clock;
+        const char *parent_name;
+        const char *name;
+        struct clk *clk;
+        int ret;
+
+        clock = kzalloc(sizeof(*clock), GFP_KERNEL);
+        if (!clock) {
+                pr_err("%s: failed to allocate %s DIV6 clock\n",
+                       __func__, np->name);
+                return;
+        }
+
+        /* Remap the clock register and read the divisor. Disabling the
+         * clock overwrites the divisor, so we need to cache its value for the
+         * enable operation.
+         */
+        clock->reg = of_iomap(np, 0);
+        if (clock->reg == NULL) {
+                pr_err("%s: failed to map %s DIV6 clock register\n",
+                       __func__, np->name);
+                goto error;
+        }
+
+        clock->div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;
+
+        /* Parse the DT properties. */
+        ret = of_property_read_string(np, "clock-output-names", &name);
+        if (ret < 0) {
+                pr_err("%s: failed to get %s DIV6 clock output name\n",
+                       __func__, np->name);
+                goto error;
+        }
+
+        parent_name = of_clk_get_parent_name(np, 0);
+        if (parent_name == NULL) {
+                pr_err("%s: failed to get %s DIV6 clock parent name\n",
+                       __func__, np->name);
+                goto error;
+        }
+
+        /* Register the clock. */
+        init.name = name;
+        init.ops = &cpg_div6_clock_ops;
+        init.flags = CLK_IS_BASIC;
+        init.parent_names = &parent_name;
+        init.num_parents = 1;
+
+        clock->hw.init = &init;
+
+        clk = clk_register(NULL, &clock->hw);
+        if (IS_ERR(clk)) {
+                pr_err("%s: failed to register %s DIV6 clock (%ld)\n",
+                       __func__, np->name, PTR_ERR(clk));
+                goto error;
+        }
+
+        of_clk_add_provider(np, of_clk_src_simple_get, clk);
+
+        return;
+
+error:
+        if (clock->reg)
+                iounmap(clock->reg);
+        kfree(clock);
+}
+CLK_OF_DECLARE(cpg_div6_clk, "renesas,cpg-div6-clock", cpg_div6_clock_init);
diff --git a/drivers/clk/shmobile/clk-mstp.c b/drivers/clk/shmobile/clk-mstp.c
new file mode 100644
index 000000000000..e576b60de20e
--- /dev/null
+++ b/drivers/clk/shmobile/clk-mstp.c
@@ -0,0 +1,229 @@
+/*
+ * R-Car MSTP clocks
+ *
+ * Copyright (C) 2013 Ideas On Board SPRL
+ *
+ * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/spinlock.h>
+
+/*
+ * MSTP clocks. We can't use standard gate clocks as we need to poll on the
+ * status register when enabling the clock.
+ */
+
+#define MSTP_MAX_CLOCKS         32
+
+/**
+ * struct mstp_clock_group - MSTP gating clocks group
+ *
+ * @data: clocks in this group
+ * @smstpcr: module stop control register
+ * @mstpsr: module stop status register (optional)
+ * @lock: protects writes to SMSTPCR
+ */
+struct mstp_clock_group {
+        struct clk_onecell_data data;
+        void __iomem *smstpcr;
+        void __iomem *mstpsr;
+        spinlock_t lock;
+};
+
+/**
+ * struct mstp_clock - MSTP gating clock
+ * @hw: handle between common and hardware-specific interfaces
+ * @bit_index: control bit index
+ * @group: MSTP clocks group
+ */
+struct mstp_clock {
+        struct clk_hw hw;
+        u32 bit_index;
+        struct mstp_clock_group *group;
+};
+
+#define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
+
+static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
+{
+        struct mstp_clock *clock = to_mstp_clock(hw);
+        struct mstp_clock_group *group = clock->group;
+        u32 bitmask = BIT(clock->bit_index);
+        unsigned long flags;
+        unsigned int i;
+        u32 value;
+
+        spin_lock_irqsave(&group->lock, flags);
+
+        value = clk_readl(group->smstpcr);
+        if (enable)
+                value &= ~bitmask;
+        else
+                value |= bitmask;
+        clk_writel(value, group->smstpcr);
+
+        spin_unlock_irqrestore(&group->lock, flags);
+
+        if (!enable || !group->mstpsr)
+                return 0;
+
+        for (i = 1000; i > 0; --i) {
+                if (!(clk_readl(group->mstpsr) & bitmask))
+                        break;
+                cpu_relax();
+        }
+
+        if (!i) {
+                pr_err("%s: failed to enable %p[%d]\n", __func__,
+                       group->smstpcr, clock->bit_index);
+                return -ETIMEDOUT;
+        }
+
+        return 0;
+}
+
+static int cpg_mstp_clock_enable(struct clk_hw *hw)
+{
+        return cpg_mstp_clock_endisable(hw, true);
+}
+
+static void cpg_mstp_clock_disable(struct clk_hw *hw)
+{
+        cpg_mstp_clock_endisable(hw, false);
+}
+
+static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
+{
+        struct mstp_clock *clock = to_mstp_clock(hw);
+        struct mstp_clock_group *group = clock->group;
+        u32 value;
+
+        if (group->mstpsr)
+                value = clk_readl(group->mstpsr);
+        else
+                value = clk_readl(group->smstpcr);
+
+        return !!(value & BIT(clock->bit_index));
+}
+
+static const struct clk_ops cpg_mstp_clock_ops = {
+        .enable = cpg_mstp_clock_enable,
+        .disable = cpg_mstp_clock_disable,
+        .is_enabled = cpg_mstp_clock_is_enabled,
+};
+
+static struct clk * __init
+cpg_mstp_clock_register(const char *name, const char *parent_name,
+                        unsigned int index, struct mstp_clock_group *group)
+{
+        struct clk_init_data init;
+        struct mstp_clock *clock;
+        struct clk *clk;
+
+        clock = kzalloc(sizeof(*clock), GFP_KERNEL);
+        if (!clock) {
+                pr_err("%s: failed to allocate MSTP clock.\n", __func__);
+                return ERR_PTR(-ENOMEM);
+        }
+
+        init.name = name;
+        init.ops = &cpg_mstp_clock_ops;
+        init.flags = CLK_IS_BASIC;
+        init.parent_names = &parent_name;
+        init.num_parents = 1;
+
+        clock->bit_index = index;
+        clock->group = group;
+        clock->hw.init = &init;
+
+        clk = clk_register(NULL, &clock->hw);
+
+        if (IS_ERR(clk))
+                kfree(clock);
+
+        return clk;
+}
+
+static void __init cpg_mstp_clocks_init(struct device_node *np)
+{
+        struct mstp_clock_group *group;
+        struct clk **clks;
+        unsigned int i;
+
+        group = kzalloc(sizeof(*group), GFP_KERNEL);
+        clks = kzalloc(MSTP_MAX_CLOCKS * sizeof(*clks), GFP_KERNEL);
+        if (group == NULL || clks == NULL) {
+                kfree(group);
+                kfree(clks);
+                pr_err("%s: failed to allocate group\n", __func__);
+                return;
+        }
+
+        spin_lock_init(&group->lock);
+        group->data.clks = clks;
+
+        group->smstpcr = of_iomap(np, 0);
+        group->mstpsr = of_iomap(np, 1);
+
+        if (group->smstpcr == NULL) {
+                pr_err("%s: failed to remap SMSTPCR\n", __func__);
+                kfree(group);
+                kfree(clks);
+                return;
+        }
+
+        for (i = 0; i < MSTP_MAX_CLOCKS; ++i) {
+                const char *parent_name;
+                const char *name;
+                u32 clkidx;
+                int ret;
+
+                /* Skip clocks with no name. */
+                ret = of_property_read_string_index(np, "clock-output-names",
+                                                    i, &name);
+                if (ret < 0 || strlen(name) == 0)
+                        continue;
+
+                parent_name = of_clk_get_parent_name(np, i);
+                ret = of_property_read_u32_index(np, "renesas,clock-indices", i,
+                                                 &clkidx);
+                if (parent_name == NULL || ret < 0)
+                        break;
+
+                if (clkidx >= MSTP_MAX_CLOCKS) {
+                        pr_err("%s: invalid clock %s %s index %u)\n",
+                               __func__, np->name, name, clkidx);
+                        continue;
+                }
+
+                clks[clkidx] = cpg_mstp_clock_register(name, parent_name, i,
+                                                       group);
+                if (!IS_ERR(clks[clkidx])) {
+                        group->data.clk_num = max(group->data.clk_num, clkidx);
+                        /*
+                         * Register a clkdev to let board code retrieve the
+                         * clock by name and register aliases for non-DT
+                         * devices.
+                         *
+                         * FIXME: Remove this when all devices that require a
+                         * clock will be instantiated from DT.
+                         */
+                        clk_register_clkdev(clks[clkidx], name, NULL);
+                } else {
+                        pr_err("%s: failed to register %s %s clock (%ld)\n",
+                               __func__, np->name, name, PTR_ERR(clks[clkidx]));
+                }
+        }
+
+        of_clk_add_provider(np, of_clk_src_onecell_get, &group->data);
+}
+CLK_OF_DECLARE(cpg_mstp_clks, "renesas,cpg-mstp-clocks", cpg_mstp_clocks_init);
diff --git a/drivers/clk/shmobile/clk-rcar-gen2.c b/drivers/clk/shmobile/clk-rcar-gen2.c
new file mode 100644
index 000000000000..a59ec217a124
--- /dev/null
+++ b/drivers/clk/shmobile/clk-rcar-gen2.c
@@ -0,0 +1,298 @@
+/*
+ * rcar_gen2 Core CPG Clocks
+ *
+ * Copyright (C) 2013  Ideas On Board SPRL
+ *
+ * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/shmobile.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/math64.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/spinlock.h>
+
+struct rcar_gen2_cpg {
+        struct clk_onecell_data data;
+        spinlock_t lock;
+        void __iomem *reg;
+};
+
+#define CPG_SDCKCR                      0x00000074
+#define CPG_PLL0CR                      0x000000d8
+#define CPG_FRQCRC                      0x000000e0
+#define CPG_FRQCRC_ZFC_MASK             (0x1f << 8)
+#define CPG_FRQCRC_ZFC_SHIFT            8
+
+/* -----------------------------------------------------------------------------
+ * Z Clock
+ *
+ * Traits of this clock:
+ * prepare - clk_prepare only ensures that parents are prepared
+ * enable - clk_enable only ensures that parents are enabled
+ * rate - rate is adjustable.  clk->rate = parent->rate * mult / 32
+ * parent - fixed parent.  No clk_set_parent support
+ */
+
+struct cpg_z_clk {
+        struct clk_hw hw;
+        void __iomem *reg;
+};
+
+#define to_z_clk(_hw)   container_of(_hw, struct cpg_z_clk, hw)
+
+static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
+                                           unsigned long parent_rate)
+{
+        struct cpg_z_clk *zclk = to_z_clk(hw);
+        unsigned int mult;
+        unsigned int val;
+
+        val = (clk_readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK)
+            >> CPG_FRQCRC_ZFC_SHIFT;
+        mult = 32 - val;
+
+        return div_u64((u64)parent_rate * mult, 32);
+}
+
+static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+                                 unsigned long *parent_rate)
+{
+        unsigned long prate  = *parent_rate;
+        unsigned int mult;
+
+        if (!prate)
+                prate = 1;
+
+        mult = div_u64((u64)rate * 32, prate);
+        mult = clamp(mult, 1U, 32U);
+
+        return *parent_rate / 32 * mult;
+}
+
+static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                              unsigned long parent_rate)
+{
+        struct cpg_z_clk *zclk = to_z_clk(hw);
+        unsigned int mult;
+        u32 val;
+
+        mult = div_u64((u64)rate * 32, parent_rate);
+        mult = clamp(mult, 1U, 32U);
+
+        val = clk_readl(zclk->reg);
+        val &= ~CPG_FRQCRC_ZFC_MASK;
+        val |= (32 - mult) << CPG_FRQCRC_ZFC_SHIFT;
+        clk_writel(val, zclk->reg);
+
+        return 0;
+}
+
+static const struct clk_ops cpg_z_clk_ops = {
+        .recalc_rate = cpg_z_clk_recalc_rate,
+        .round_rate = cpg_z_clk_round_rate,
+        .set_rate = cpg_z_clk_set_rate,
+};
+
+static struct clk * __init cpg_z_clk_register(struct rcar_gen2_cpg *cpg)
+{
+        static const char *parent_name = "pll0";
+        struct clk_init_data init;
+        struct cpg_z_clk *zclk;
+        struct clk *clk;
+
+        zclk = kzalloc(sizeof(*zclk), GFP_KERNEL);
+        if (!zclk)
+                return ERR_PTR(-ENOMEM);
+
+        init.name = "z";
+        init.ops = &cpg_z_clk_ops;
+        init.flags = 0;
+        init.parent_names = &parent_name;
+        init.num_parents = 1;
+
+        zclk->reg = cpg->reg + CPG_FRQCRC;
+        zclk->hw.init = &init;
+
+        clk = clk_register(NULL, &zclk->hw);
+        if (IS_ERR(clk))
+                kfree(zclk);
+
+        return clk;
+}
+
+/* -----------------------------------------------------------------------------
+ * CPG Clock Data
+ */
+
+/*
+ *   MD         EXTAL           PLL0    PLL1    PLL3
+ * 14 13 19     (MHz)           *1      *1
+ *---------------------------------------------------
+ * 0  0  0      15 x 1          x172/2  x208/2  x106
+ * 0  0  1      15 x 1          x172/2  x208/2  x88
+ * 0  1  0      20 x 1          x130/2  x156/2  x80
+ * 0  1  1      20 x 1          x130/2  x156/2  x66
+ * 1  0  0      26 / 2          x200/2  x240/2  x122
+ * 1  0  1      26 / 2          x200/2  x240/2  x102
+ * 1  1  0      30 / 2          x172/2  x208/2  x106
+ * 1  1  1      30 / 2          x172/2  x208/2  x88
+ *
+ * *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2)
+ */
+#define CPG_PLL_CONFIG_INDEX(md)        ((((md) & BIT(14)) >> 12) | \
+                                         (((md) & BIT(13)) >> 12) | \
+                                         (((md) & BIT(19)) >> 19))
+struct cpg_pll_config {
+        unsigned int extal_div;
+        unsigned int pll1_mult;
+        unsigned int pll3_mult;
+};
+
+static const struct cpg_pll_config cpg_pll_configs[8] __initconst = {
+        { 1, 208, 106 }, { 1, 208,  88 }, { 1, 156,  80 }, { 1, 156,  66 },
+        { 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208,  88 },
+};
+
+/* SDHI divisors */
+static const struct clk_div_table cpg_sdh_div_table[] = {
+        {  0,  2 }, {  1,  3 }, {  2,  4 }, {  3,  6 },
+        {  4,  8 }, {  5, 12 }, {  6, 16 }, {  7, 18 },
+        {  8, 24 }, { 10, 36 }, { 11, 48 }, {  0,  0 },
+};
+
+static const struct clk_div_table cpg_sd01_div_table[] = {
+        {  5, 12 }, {  6, 16 }, {  7, 18 }, {  8, 24 },
+        { 10, 36 }, { 11, 48 }, { 12, 10 }, {  0,  0 },
+};
+
+/* -----------------------------------------------------------------------------
+ * Initialization
+ */
+
+static u32 cpg_mode __initdata;
+
+static struct clk * __init
+rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg,
+                             const struct cpg_pll_config *config,
+                             const char *name)
+{
+        const struct clk_div_table *table = NULL;
+        const char *parent_name = "main";
+        unsigned int shift;
+        unsigned int mult = 1;
+        unsigned int div = 1;
+
+        if (!strcmp(name, "main")) {
+                parent_name = of_clk_get_parent_name(np, 0);
+                div = config->extal_div;
+        } else if (!strcmp(name, "pll0")) {
+                /* PLL0 is a configurable multiplier clock. Register it as a
+                 * fixed factor clock for now as there's no generic multiplier
+                 * clock implementation and we currently have no need to change
+                 * the multiplier value.
+                 */
+                u32 value = clk_readl(cpg->reg + CPG_PLL0CR);
+                mult = ((value >> 24) & ((1 << 7) - 1)) + 1;
+        } else if (!strcmp(name, "pll1")) {
+                mult = config->pll1_mult / 2;
+        } else if (!strcmp(name, "pll3")) {
+                mult = config->pll3_mult;
+        } else if (!strcmp(name, "lb")) {
+                div = cpg_mode & BIT(18) ? 36 : 24;
+        } else if (!strcmp(name, "qspi")) {
+                div = (cpg_mode & (BIT(3) | BIT(2) | BIT(1))) == BIT(2)
+                    ? 16 : 20;
+        } else if (!strcmp(name, "sdh")) {
+                table = cpg_sdh_div_table;
+                shift = 8;
+        } else if (!strcmp(name, "sd0")) {
+                table = cpg_sd01_div_table;
+                shift = 4;
+        } else if (!strcmp(name, "sd1")) {
+                table = cpg_sd01_div_table;
+                shift = 0;
+        } else if (!strcmp(name, "z")) {
+                return cpg_z_clk_register(cpg);
+        } else {
+                return ERR_PTR(-EINVAL);
+        }
+
+        if (!table)
+                return clk_register_fixed_factor(NULL, name, parent_name, 0,
+                                                 mult, div);
+        else
+                return clk_register_divider_table(NULL, name, parent_name, 0,
+                                                 cpg->reg + CPG_SDCKCR, shift,
+                                                 4, 0, table, &cpg->lock);
+}
+
+static void __init rcar_gen2_cpg_clocks_init(struct device_node *np)
+{
+        const struct cpg_pll_config *config;
+        struct rcar_gen2_cpg *cpg;
+        struct clk **clks;
+        unsigned int i;
+        int num_clks;
+
+        num_clks = of_property_count_strings(np, "clock-output-names");
+        if (num_clks < 0) {
+                pr_err("%s: failed to count clocks\n", __func__);
+                return;
+        }
+
+        cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
+        clks = kzalloc(num_clks * sizeof(*clks), GFP_KERNEL);
+        if (cpg == NULL || clks == NULL) {
+                /* We're leaking memory on purpose, there's no point in cleaning
+                 * up as the system won't boot anyway.
+                 */
+                pr_err("%s: failed to allocate cpg\n", __func__);
+                return;
+        }
+
+        spin_lock_init(&cpg->lock);
+
+        cpg->data.clks = clks;
+        cpg->data.clk_num = num_clks;
+
+        cpg->reg = of_iomap(np, 0);
+        if (WARN_ON(cpg->reg == NULL))
+                return;
+
+        config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+
+        for (i = 0; i < num_clks; ++i) {
+                const char *name;
+                struct clk *clk;
+
+                of_property_read_string_index(np, "clock-output-names", i,
+                                              &name);
+
+                clk = rcar_gen2_cpg_register_clock(np, cpg, config, name);
+                if (IS_ERR(clk))
+                        pr_err("%s: failed to register %s %s clock (%ld)\n",
+                               __func__, np->name, name, PTR_ERR(clk));
+                else
+                        cpg->data.clks[i] = clk;
+        }
+
+        of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
+}
+CLK_OF_DECLARE(rcar_gen2_cpg_clks, "renesas,rcar-gen2-cpg-clocks",
+               rcar_gen2_cpg_clocks_init);
+
+void __init rcar_gen2_clocks_init(u32 mode)
+{
+        cpg_mode = mode;
+
+        of_clk_init(NULL);
+}
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 62b0de6a1837..48f76bc05da0 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -71,6 +71,10 @@ enum {
         MCT_L1_IRQ,
         MCT_L2_IRQ,
         MCT_L3_IRQ,
+        MCT_L4_IRQ,
+        MCT_L5_IRQ,
+        MCT_L6_IRQ,
+        MCT_L7_IRQ,
         MCT_NR_IRQS,
 };
 
diff --git a/drivers/clocksource/nomadik-mtu.c b/drivers/clocksource/nomadik-mtu.c
index 152a3f3875ee..a709cfa49d85 100644
--- a/drivers/clocksource/nomadik-mtu.c
+++ b/drivers/clocksource/nomadik-mtu.c
@@ -20,7 +20,6 @@
 #include <linux/jiffies.h>
 #include <linux/delay.h>
 #include <linux/err.h>
-#include <linux/platform_data/clocksource-nomadik-mtu.h>
 #include <linux/sched_clock.h>
 #include <asm/mach/time.h>
 
@@ -103,7 +102,7 @@ static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
         return 0;
 }
 
-void nmdk_clkevt_reset(void)
+static void nmdk_clkevt_reset(void)
 {
         if (clkevt_periodic) {
                 /* Timer: configure load and background-load, and fire it up */
@@ -144,7 +143,7 @@ static void nmdk_clkevt_mode(enum clock_event_mode mode,
         }
 }
 
-void nmdk_clksrc_reset(void)
+static void nmdk_clksrc_reset(void)
 {
         /* Disable */
         writel(0, mtu_base + MTU_CR(0));
@@ -192,8 +191,8 @@ static struct irqaction nmdk_timer_irq = {
         .dev_id         = &nmdk_clkevt,
 };
 
-static void __init __nmdk_timer_init(void __iomem *base, int irq,
-                                     struct clk *pclk, struct clk *clk)
+static void __init nmdk_timer_init(void __iomem *base, int irq,
+                                   struct clk *pclk, struct clk *clk)
 {
         unsigned long rate;
 
@@ -245,18 +244,6 @@ static void __init __nmdk_timer_init(void __iomem *base, int irq,
         register_current_timer_delay(&mtu_delay_timer);
 }
 
-void __init nmdk_timer_init(void __iomem *base, int irq)
-{
-        struct clk *clk0, *pclk0;
-
-        pclk0 = clk_get_sys("mtu0", "apb_pclk");
-        BUG_ON(IS_ERR(pclk0));
-        clk0 = clk_get_sys("mtu0", NULL);
-        BUG_ON(IS_ERR(clk0));
-
-        __nmdk_timer_init(base, irq, pclk0, clk0);
-}
-
 static void __init nmdk_timer_of_init(struct device_node *node)
 {
         struct clk *pclk;
@@ -280,7 +267,7 @@ static void __init nmdk_timer_of_init(struct device_node *node)
         if (irq <= 0)
                 panic("Can't parse IRQ");
 
-        __nmdk_timer_init(base, irq, pclk, clk);
+        nmdk_timer_init(base, irq, pclk, clk);
 }
 CLOCKSOURCE_OF_DECLARE(nomadik_mtu, "st,nomadik-mtu",
                        nmdk_timer_of_init);
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index b8c031b7de4e..00a2de957b23 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -2409,6 +2409,7 @@ static void d40_set_prio_realtime(struct d40_chan *d40c)
 #define D40_DT_FLAGS_DIR(flags)        ((flags >> 1) & 0x1)
 #define D40_DT_FLAGS_BIG_ENDIAN(flags) ((flags >> 2) & 0x1)
 #define D40_DT_FLAGS_FIXED_CHAN(flags) ((flags >> 3) & 0x1)
+#define D40_DT_FLAGS_HIGH_PRIO(flags)  ((flags >> 4) & 0x1)
 
 static struct dma_chan *d40_xlate(struct of_phandle_args *dma_spec,
                                   struct of_dma *ofdma)
@@ -2446,6 +2447,9 @@ static struct dma_chan *d40_xlate(struct of_phandle_args *dma_spec,
                 cfg.use_fixed_channel = true;
         }
 
+        if (D40_DT_FLAGS_HIGH_PRIO(flags))
+                cfg.high_priority = true;
+
         return dma_request_channel(cap, stedma40_filter, &cfg);
 }
 
diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c
index cd2b1a1c9275..53a11114927f 100644
--- a/drivers/pinctrl/pinctrl-nomadik.c
+++ b/drivers/pinctrl/pinctrl-nomadik.c
@@ -4,7 +4,7 @@
  * Copyright (C) 2008,2009 STMicroelectronics
  * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
  *   Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
- * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org>
+ * Copyright (C) 2011-2013 Linus Walleij <linus.walleij@linaro.org>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -33,7 +33,6 @@
 #include <linux/pinctrl/pinconf.h>
 /* Since we request GPIOs from ourself */
 #include <linux/pinctrl/consumer.h>
-#include <linux/platform_data/pinctrl-nomadik.h>
 #include "pinctrl-nomadik.h"
 #include "core.h"
 
@@ -45,6 +44,221 @@
  * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
  */
 
+/*
+ * pin configurations are represented by 32-bit integers:
+ *
+ *      bit  0.. 8 - Pin Number (512 Pins Maximum)
+ *      bit  9..10 - Alternate Function Selection
+ *      bit 11..12 - Pull up/down state
+ *      bit     13 - Sleep mode behaviour
+ *      bit     14 - Direction
+ *      bit     15 - Value (if output)
+ *      bit 16..18 - SLPM pull up/down state
+ *      bit 19..20 - SLPM direction
+ *      bit 21..22 - SLPM Value (if output)
+ *      bit 23..25 - PDIS value (if input)
+ *      bit     26 - Gpio mode
+ *      bit     27 - Sleep mode
+ *
+ * to facilitate the definition, the following macros are provided
+ *
+ * PIN_CFG_DEFAULT - default config (0):
+ *                   pull up/down = disabled
+ *                   sleep mode = input/wakeup
+ *                   direction = input
+ *                   value = low
+ *                   SLPM direction = same as normal
+ *                   SLPM pull = same as normal
+ *                   SLPM value = same as normal
+ *
+ * PIN_CFG         - default config with alternate function
+ */
+
+typedef unsigned long pin_cfg_t;
+
+#define PIN_NUM_MASK            0x1ff
+#define PIN_NUM(x)              ((x) & PIN_NUM_MASK)
+
+#define PIN_ALT_SHIFT           9
+#define PIN_ALT_MASK            (0x3 << PIN_ALT_SHIFT)
+#define PIN_ALT(x)              (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)
+#define PIN_GPIO                (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT)
+#define PIN_ALT_A               (NMK_GPIO_ALT_A << PIN_ALT_SHIFT)
+#define PIN_ALT_B               (NMK_GPIO_ALT_B << PIN_ALT_SHIFT)
+#define PIN_ALT_C               (NMK_GPIO_ALT_C << PIN_ALT_SHIFT)
+
+#define PIN_PULL_SHIFT          11
+#define PIN_PULL_MASK           (0x3 << PIN_PULL_SHIFT)
+#define PIN_PULL(x)             (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)
+#define PIN_PULL_NONE           (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT)
+#define PIN_PULL_UP             (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT)
+#define PIN_PULL_DOWN           (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT)
+
+#define PIN_SLPM_SHIFT          13
+#define PIN_SLPM_MASK           (0x1 << PIN_SLPM_SHIFT)
+#define PIN_SLPM(x)             (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
+#define PIN_SLPM_MAKE_INPUT     (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
+#define PIN_SLPM_NOCHANGE       (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
+/* These two replace the above in DB8500v2+ */
+#define PIN_SLPM_WAKEUP_ENABLE  (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
+#define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
+#define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE
+
+#define PIN_SLPM_GPIO  PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */
+#define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */
+
+#define PIN_DIR_SHIFT           14
+#define PIN_DIR_MASK            (0x1 << PIN_DIR_SHIFT)
+#define PIN_DIR(x)              (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT)
+#define PIN_DIR_INPUT           (0 << PIN_DIR_SHIFT)
+#define PIN_DIR_OUTPUT          (1 << PIN_DIR_SHIFT)
+
+#define PIN_VAL_SHIFT           15
+#define PIN_VAL_MASK            (0x1 << PIN_VAL_SHIFT)
+#define PIN_VAL(x)              (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT)
+#define PIN_VAL_LOW             (0 << PIN_VAL_SHIFT)
+#define PIN_VAL_HIGH            (1 << PIN_VAL_SHIFT)
+
+#define PIN_SLPM_PULL_SHIFT     16
+#define PIN_SLPM_PULL_MASK      (0x7 << PIN_SLPM_PULL_SHIFT)
+#define PIN_SLPM_PULL(x)        \
+        (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT)
+#define PIN_SLPM_PULL_NONE      \
+        ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT)
+#define PIN_SLPM_PULL_UP        \
+        ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT)
+#define PIN_SLPM_PULL_DOWN      \
+        ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT)
+
+#define PIN_SLPM_DIR_SHIFT      19
+#define PIN_SLPM_DIR_MASK       (0x3 << PIN_SLPM_DIR_SHIFT)
+#define PIN_SLPM_DIR(x)         \
+        (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT)
+#define PIN_SLPM_DIR_INPUT      ((1 + 0) << PIN_SLPM_DIR_SHIFT)
+#define PIN_SLPM_DIR_OUTPUT     ((1 + 1) << PIN_SLPM_DIR_SHIFT)
+
+#define PIN_SLPM_VAL_SHIFT      21
+#define PIN_SLPM_VAL_MASK       (0x3 << PIN_SLPM_VAL_SHIFT)
+#define PIN_SLPM_VAL(x)         \
+        (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT)
+#define PIN_SLPM_VAL_LOW        ((1 + 0) << PIN_SLPM_VAL_SHIFT)
+#define PIN_SLPM_VAL_HIGH       ((1 + 1) << PIN_SLPM_VAL_SHIFT)
+
+#define PIN_SLPM_PDIS_SHIFT             23
+#define PIN_SLPM_PDIS_MASK              (0x3 << PIN_SLPM_PDIS_SHIFT)
+#define PIN_SLPM_PDIS(x)        \
+        (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT)
+#define PIN_SLPM_PDIS_NO_CHANGE         (0 << PIN_SLPM_PDIS_SHIFT)
+#define PIN_SLPM_PDIS_DISABLED          (1 << PIN_SLPM_PDIS_SHIFT)
+#define PIN_SLPM_PDIS_ENABLED           (2 << PIN_SLPM_PDIS_SHIFT)
+
+#define PIN_LOWEMI_SHIFT        25
+#define PIN_LOWEMI_MASK         (0x1 << PIN_LOWEMI_SHIFT)
+#define PIN_LOWEMI(x)           (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT)
+#define PIN_LOWEMI_DISABLED     (0 << PIN_LOWEMI_SHIFT)
+#define PIN_LOWEMI_ENABLED      (1 << PIN_LOWEMI_SHIFT)
+
+#define PIN_GPIOMODE_SHIFT      26
+#define PIN_GPIOMODE_MASK       (0x1 << PIN_GPIOMODE_SHIFT)
+#define PIN_GPIOMODE(x)         (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT)
+#define PIN_GPIOMODE_DISABLED   (0 << PIN_GPIOMODE_SHIFT)
+#define PIN_GPIOMODE_ENABLED    (1 << PIN_GPIOMODE_SHIFT)
+
+#define PIN_SLEEPMODE_SHIFT     27
+#define PIN_SLEEPMODE_MASK      (0x1 << PIN_SLEEPMODE_SHIFT)
+#define PIN_SLEEPMODE(x)        (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT)
+#define PIN_SLEEPMODE_DISABLED  (0 << PIN_SLEEPMODE_SHIFT)
+#define PIN_SLEEPMODE_ENABLED   (1 << PIN_SLEEPMODE_SHIFT)
+
+
+/* Shortcuts.  Use these instead of separate DIR, PULL, and VAL.  */
+#define PIN_INPUT_PULLDOWN      (PIN_DIR_INPUT | PIN_PULL_DOWN)
+#define PIN_INPUT_PULLUP        (PIN_DIR_INPUT | PIN_PULL_UP)
+#define PIN_INPUT_NOPULL        (PIN_DIR_INPUT | PIN_PULL_NONE)
+#define PIN_OUTPUT_LOW          (PIN_DIR_OUTPUT | PIN_VAL_LOW)
+#define PIN_OUTPUT_HIGH         (PIN_DIR_OUTPUT | PIN_VAL_HIGH)
+
+#define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN)
+#define PIN_SLPM_INPUT_PULLUP   (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP)
+#define PIN_SLPM_INPUT_NOPULL   (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE)
+#define PIN_SLPM_OUTPUT_LOW     (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW)
+#define PIN_SLPM_OUTPUT_HIGH    (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH)
+
+#define PIN_CFG_DEFAULT         (0)
+
+#define PIN_CFG(num, alt)               \
+        (PIN_CFG_DEFAULT |\
+         (PIN_NUM(num) | PIN_##alt))
+
+#define PIN_CFG_INPUT(num, alt, pull)           \
+        (PIN_CFG_DEFAULT |\
+         (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull))
+
+#define PIN_CFG_OUTPUT(num, alt, val)           \
+        (PIN_CFG_DEFAULT |\
+         (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
+
+/*
+ * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving
+ * the "gpio" namespace for generic and cross-machine functions
+ */
+
+#define GPIO_BLOCK_SHIFT 5
+#define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT)
+
+/* Register in the logic block */
+#define NMK_GPIO_DAT    0x00
+#define NMK_GPIO_DATS   0x04
+#define NMK_GPIO_DATC   0x08
+#define NMK_GPIO_PDIS   0x0c
+#define NMK_GPIO_DIR    0x10
+#define NMK_GPIO_DIRS   0x14
+#define NMK_GPIO_DIRC   0x18
+#define NMK_GPIO_SLPC   0x1c
+#define NMK_GPIO_AFSLA  0x20
+#define NMK_GPIO_AFSLB  0x24
+#define NMK_GPIO_LOWEMI 0x28
+
+#define NMK_GPIO_RIMSC  0x40
+#define NMK_GPIO_FIMSC  0x44
+#define NMK_GPIO_IS     0x48
+#define NMK_GPIO_IC     0x4c
+#define NMK_GPIO_RWIMSC 0x50
+#define NMK_GPIO_FWIMSC 0x54
+#define NMK_GPIO_WKS    0x58
+/* These appear in DB8540 and later ASICs */
+#define NMK_GPIO_EDGELEVEL 0x5C
+#define NMK_GPIO_LEVEL  0x60
+
+
+/* Pull up/down values */
+enum nmk_gpio_pull {
+        NMK_GPIO_PULL_NONE,
+        NMK_GPIO_PULL_UP,
+        NMK_GPIO_PULL_DOWN,
+};
+
+/* Sleep mode */
+enum nmk_gpio_slpm {
+        NMK_GPIO_SLPM_INPUT,
+        NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT,
+        NMK_GPIO_SLPM_NOCHANGE,
+        NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE,
+};
+
+/*
+ * Platform data to register a block: only the initial gpio/irq number.
+ */
+struct nmk_gpio_platform_data {
+        char *name;
+        int first_gpio;
+        int first_irq;
+        int num_gpio;
+        u32 (*get_secondary_status)(unsigned int bank);
+        void (*set_ioforce)(bool enable);
+        bool supports_sleepmode;
+};
+
 struct nmk_gpio_chip {
         struct gpio_chip chip;
         struct irq_domain *domain;
@@ -1026,7 +1240,7 @@ static const struct irq_domain_ops nmk_gpio_irq_simple_ops = {
 
 static int nmk_gpio_probe(struct platform_device *dev)
 {
-        struct nmk_gpio_platform_data *pdata = dev->dev.platform_data;
+        struct nmk_gpio_platform_data *pdata;
         struct device_node *np = dev->dev.of_node;
         struct nmk_gpio_chip *nmk_chip;
         struct gpio_chip *chip;
@@ -1034,32 +1248,24 @@ static int nmk_gpio_probe(struct platform_device *dev)
         struct clk *clk;
         int secondary_irq;
         void __iomem *base;
-        int irq_start = 0;
         int irq;
         int ret;
 
-        if (!pdata && !np) {
-                dev_err(&dev->dev, "No platform data or device tree found\n");
-                return -ENODEV;
-        }
-
-        if (np) {
-                pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
-                if (!pdata)
-                        return -ENOMEM;
-
-                if (of_get_property(np, "st,supports-sleepmode", NULL))
-                        pdata->supports_sleepmode = true;
+        pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
+        if (!pdata)
+                return -ENOMEM;
 
-                if (of_property_read_u32(np, "gpio-bank", &dev->id)) {
-                        dev_err(&dev->dev, "gpio-bank property not found\n");
-                        return -EINVAL;
-                }
+        if (of_get_property(np, "st,supports-sleepmode", NULL))
+                pdata->supports_sleepmode = true;
 
-                pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP;
-                pdata->num_gpio   = NMK_GPIO_PER_CHIP;
+        if (of_property_read_u32(np, "gpio-bank", &dev->id)) {
+                dev_err(&dev->dev, "gpio-bank property not found\n");
+                return -EINVAL;
         }
 
+        pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP;
+        pdata->num_gpio = NMK_GPIO_PER_CHIP;
+
         irq = platform_get_irq(dev, 0);
         if (irq < 0)
                 return irq;
@@ -1107,10 +1313,7 @@ static int nmk_gpio_probe(struct platform_device *dev)
         clk_enable(nmk_chip->clk);
         nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
         clk_disable(nmk_chip->clk);
-
-#ifdef CONFIG_OF_GPIO
         chip->of_node = np;
-#endif
 
         ret = gpiochip_add(&nmk_chip->chip);
         if (ret)
@@ -1122,10 +1325,8 @@ static int nmk_gpio_probe(struct platform_device *dev)
 
         platform_set_drvdata(dev, nmk_chip);
 
-        if (!np)
-                irq_start = pdata->first_irq;
         nmk_chip->domain = irq_domain_add_simple(np,
-                                NMK_GPIO_PER_CHIP, irq_start,
+                                NMK_GPIO_PER_CHIP, 0,
                                 &nmk_gpio_irq_simple_ops, nmk_chip);
         if (!nmk_chip->domain) {
                 dev_err(&dev->dev, "failed to create irqdomain\n");
@@ -1858,11 +2059,10 @@ static int nmk_pinctrl_resume(struct platform_device *pdev)
 
 static int nmk_pinctrl_probe(struct platform_device *pdev)
 {
-        const struct platform_device_id *platid = platform_get_device_id(pdev);
+        const struct of_device_id *match;
         struct device_node *np = pdev->dev.of_node;
         struct device_node *prcm_np;
         struct nmk_pinctrl *npct;
-        struct resource *res;
         unsigned int version = 0;
         int i;
 
@@ -1870,16 +2070,10 @@ static int nmk_pinctrl_probe(struct platform_device *pdev)
         if (!npct)
                 return -ENOMEM;
 
-        if (platid)
-                version = platid->driver_data;
-        else if (np) {
-                const struct of_device_id *match;
-
-                match = of_match_device(nmk_pinctrl_match, &pdev->dev);
-                if (!match)
-                        return -ENODEV;
-                version = (unsigned int) match->data;
-        }
+        match = of_match_device(nmk_pinctrl_match, &pdev->dev);
+        if (!match)
+                return -ENODEV;
+        version = (unsigned int) match->data;
 
         /* Poke in other ASIC variants here */
         if (version == PINCTRL_NMK_STN8815)
@@ -1889,17 +2083,9 @@ static int nmk_pinctrl_probe(struct platform_device *pdev)
         if (version == PINCTRL_NMK_DB8540)
                 nmk_pinctrl_db8540_init(&npct->soc);
 
-        if (np) {
-                prcm_np = of_parse_phandle(np, "prcm", 0);
-                if (prcm_np)
-                        npct->prcm_base = of_iomap(prcm_np, 0);
-        }
-
-        /* Allow platform passed information to over-write DT. */
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (res)
-                npct->prcm_base = devm_ioremap(&pdev->dev, res->start,
-                                               resource_size(res));
+        prcm_np = of_parse_phandle(np, "prcm", 0);
+        if (prcm_np)
+                npct->prcm_base = of_iomap(prcm_np, 0);
         if (!npct->prcm_base) {
                 if (version == PINCTRL_NMK_STN8815) {
                         dev_info(&pdev->dev,
@@ -1958,13 +2144,6 @@ static struct platform_driver nmk_gpio_driver = {
         .probe = nmk_gpio_probe,
 };
 
-static const struct platform_device_id nmk_pinctrl_id[] = {
-        { "pinctrl-stn8815", PINCTRL_NMK_STN8815 },
-        { "pinctrl-db8500", PINCTRL_NMK_DB8500 },
-        { "pinctrl-db8540", PINCTRL_NMK_DB8540 },
-        { }
-};
-
 static struct platform_driver nmk_pinctrl_driver = {
         .driver = {
                 .owner = THIS_MODULE,
@@ -1972,7 +2151,6 @@ static struct platform_driver nmk_pinctrl_driver = {
                 .of_match_table = nmk_pinctrl_match,
         },
         .probe = nmk_pinctrl_probe,
-        .id_table = nmk_pinctrl_id,
 #ifdef CONFIG_PM
         .suspend = nmk_pinctrl_suspend,
         .resume = nmk_pinctrl_resume,
diff --git a/drivers/pinctrl/pinctrl-nomadik.h b/drivers/pinctrl/pinctrl-nomadik.h
index bcd4191e10ea..d8215f1e70c7 100644
--- a/drivers/pinctrl/pinctrl-nomadik.h
+++ b/drivers/pinctrl/pinctrl-nomadik.h
@@ -1,13 +1,23 @@
 #ifndef PINCTRL_PINCTRL_NOMADIK_H
 #define PINCTRL_PINCTRL_NOMADIK_H
 
-#include <linux/platform_data/pinctrl-nomadik.h>
-
 /* Package definitions */
 #define PINCTRL_NMK_STN8815     0
 #define PINCTRL_NMK_DB8500      1
 #define PINCTRL_NMK_DB8540      2
 
+/* Alternate functions: function C is set in hw by setting both A and B */
+#define NMK_GPIO_ALT_GPIO       0
+#define NMK_GPIO_ALT_A  1
+#define NMK_GPIO_ALT_B  2
+#define NMK_GPIO_ALT_C  (NMK_GPIO_ALT_A | NMK_GPIO_ALT_B)
+
+#define NMK_GPIO_ALT_CX_SHIFT 2
+#define NMK_GPIO_ALT_C1 ((1<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
+#define NMK_GPIO_ALT_C2 ((2<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
+#define NMK_GPIO_ALT_C3 ((3<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
+#define NMK_GPIO_ALT_C4 ((4<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
+
 #define PRCM_GPIOCR_ALTCX(pin_num,\
         altc1_used, altc1_ri, altc1_cb,\
         altc2_used, altc2_ri, altc2_cb,\
diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h
index 420f0b00ae1e..859e9be511d9 100644
--- a/include/dt-bindings/clock/r8a7790-clock.h
+++ b/include/dt-bindings/clock/r8a7790-clock.h
@@ -22,6 +22,9 @@
 #define R8A7790_CLK_SD1                 8
 #define R8A7790_CLK_Z                   9
 
+/* MSTP0 */
+#define R8A7790_CLK_MSIOF0              0
+
 /* MSTP1 */
 #define R8A7790_CLK_TMU1                11
 #define R8A7790_CLK_TMU3                21
@@ -37,8 +40,11 @@
 #define R8A7790_CLK_SCIFA2              2
 #define R8A7790_CLK_SCIFA1              3
 #define R8A7790_CLK_SCIFA0              4
+#define R8A7790_CLK_MSIOF2              5
 #define R8A7790_CLK_SCIFB0              6
 #define R8A7790_CLK_SCIFB1              7
+#define R8A7790_CLK_MSIOF1              8
+#define R8A7790_CLK_MSIOF3              15
 #define R8A7790_CLK_SCIFB2              16
 #define R8A7790_CLK_SYS_DMAC0           18
 #define R8A7790_CLK_SYS_DMAC1           19
@@ -91,6 +97,7 @@
 #define R8A7790_CLK_GPIO0               12
 #define R8A7790_CLK_RCAN1               15
 #define R8A7790_CLK_RCAN0               16
+#define R8A7790_CLK_QSPI_MOD            17
 #define R8A7790_CLK_IICDVFS             26
 #define R8A7790_CLK_I2C3                28
 #define R8A7790_CLK_I2C2                29
diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h
index df1715b77f96..30f82f286e29 100644
--- a/include/dt-bindings/clock/r8a7791-clock.h
+++ b/include/dt-bindings/clock/r8a7791-clock.h
@@ -21,6 +21,9 @@
 #define R8A7791_CLK_SD0                 7
 #define R8A7791_CLK_Z                   8
 
+/* MSTP0 */
+#define R8A7791_CLK_MSIOF0              0
+
 /* MSTP1 */
 #define R8A7791_CLK_TMU1                11
 #define R8A7791_CLK_TMU3                21
@@ -35,8 +38,10 @@
 #define R8A7791_CLK_SCIFA2              2
 #define R8A7791_CLK_SCIFA1              3
 #define R8A7791_CLK_SCIFA0              4
+#define R8A7791_CLK_MSIOF2              5
 #define R8A7791_CLK_SCIFB0              6
 #define R8A7791_CLK_SCIFB1              7
+#define R8A7791_CLK_MSIOF1              8
 #define R8A7791_CLK_SCIFB2              16
 #define R8A7791_CLK_DMAC                18
 
@@ -89,6 +94,7 @@
 #define R8A7791_CLK_GPIO0               12
 #define R8A7791_CLK_RCAN1               15
 #define R8A7791_CLK_RCAN0               16
+#define R8A7791_CLK_QSPI_MOD            17
 #define R8A7791_CLK_I2C5                25
 #define R8A7791_CLK_IICDVFS             26
 #define R8A7791_CLK_I2C4                27
diff --git a/include/dt-bindings/gpio/tegra-gpio.h b/include/dt-bindings/gpio/tegra-gpio.h
index 4d179c00f081..197dc28b676e 100644
--- a/include/dt-bindings/gpio/tegra-gpio.h
+++ b/include/dt-bindings/gpio/tegra-gpio.h
@@ -43,6 +43,7 @@
 #define TEGRA_GPIO_BANK_ID_CC 28
 #define TEGRA_GPIO_BANK_ID_DD 29
 #define TEGRA_GPIO_BANK_ID_EE 30
+#define TEGRA_GPIO_BANK_ID_FF 31
 
 #define TEGRA_GPIO(bank, offset) \
         ((TEGRA_GPIO_BANK_ID_##bank * 8) + offset)
diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra.h b/include/dt-bindings/pinctrl/pinctrl-tegra.h
new file mode 100644
index 000000000000..ebafa498be0f
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pinctrl-tegra.h
@@ -0,0 +1,45 @@
+/*
+ * This header provides constants for Tegra pinctrl bindings.
+ *
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Author: Laxman Dewangan <ldewangan@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_TEGRA_H
+#define _DT_BINDINGS_PINCTRL_TEGRA_H
+
+/*
+ * Enable/disable for diffeent dt properties. This is applicable for
+ * properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain,
+ * nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt.
+ */
+#define TEGRA_PIN_DISABLE                               0
+#define TEGRA_PIN_ENABLE                                1
+
+#define TEGRA_PIN_PULL_NONE                             0
+#define TEGRA_PIN_PULL_DOWN                             1
+#define TEGRA_PIN_PULL_UP                               2
+
+/* Low power mode driver */
+#define TEGRA_PIN_LP_DRIVE_DIV_8                        0
+#define TEGRA_PIN_LP_DRIVE_DIV_4                        1
+#define TEGRA_PIN_LP_DRIVE_DIV_2                        2
+#define TEGRA_PIN_LP_DRIVE_DIV_1                        3
+
+/* Rising/Falling slew rate */
+#define TEGRA_PIN_SLEW_RATE_FASTEST                     0
+#define TEGRA_PIN_SLEW_RATE_FAST                        1
+#define TEGRA_PIN_SLEW_RATE_SLOW                        2
+#define TEGRA_PIN_SLEW_RATE_SLOWEST                     3
+
+#endif
diff --git a/include/linux/clk/shmobile.h b/include/linux/clk/shmobile.h
new file mode 100644
index 000000000000..f9bf080a1123
--- /dev/null
+++ b/include/linux/clk/shmobile.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2013 Ideas On Board SPRL
+ *
+ * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __LINUX_CLK_SHMOBILE_H_
+#define __LINUX_CLK_SHMOBILE_H_
+
+#include <linux/types.h>
+
+void rcar_gen2_clocks_init(u32 mode);
+
+#endif
diff --git a/include/linux/platform_data/clocksource-nomadik-mtu.h b/include/linux/platform_data/clocksource-nomadik-mtu.h
deleted file mode 100644
index 80088973b734..000000000000
--- a/include/linux/platform_data/clocksource-nomadik-mtu.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef __PLAT_MTU_H
-#define __PLAT_MTU_H
-
-void nmdk_timer_init(void __iomem *base, int irq);
-void nmdk_clkevt_reset(void);
-void nmdk_clksrc_reset(void);
-
-#endif /* __PLAT_MTU_H */
-
diff --git a/include/linux/platform_data/pinctrl-nomadik.h b/include/linux/platform_data/pinctrl-nomadik.h
deleted file mode 100644
index abf5bed84df3..000000000000
--- a/include/linux/platform_data/pinctrl-nomadik.h
+++ /dev/null
@@ -1,242 +0,0 @@
-/*
- * Structures and registers for GPIO access in the Nomadik SoC
- *
- * Copyright (C) 2008 STMicroelectronics
- *     Author: Prafulla WADASKAR <prafulla.wadaskar@st.com>
- * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __PLAT_NOMADIK_GPIO
-#define __PLAT_NOMADIK_GPIO
-
-/*
- * pin configurations are represented by 32-bit integers:
- *
- *      bit  0.. 8 - Pin Number (512 Pins Maximum)
- *      bit  9..10 - Alternate Function Selection
- *      bit 11..12 - Pull up/down state
- *      bit     13 - Sleep mode behaviour
- *      bit     14 - Direction
- *      bit     15 - Value (if output)
- *      bit 16..18 - SLPM pull up/down state
- *      bit 19..20 - SLPM direction
- *      bit 21..22 - SLPM Value (if output)
- *      bit 23..25 - PDIS value (if input)
- *      bit     26 - Gpio mode
- *      bit     27 - Sleep mode
- *
- * to facilitate the definition, the following macros are provided
- *
- * PIN_CFG_DEFAULT - default config (0):
- *                   pull up/down = disabled
- *                   sleep mode = input/wakeup
- *                   direction = input
- *                   value = low
- *                   SLPM direction = same as normal
- *                   SLPM pull = same as normal
- *                   SLPM value = same as normal
- *
- * PIN_CFG         - default config with alternate function
- */
-
-typedef unsigned long pin_cfg_t;
-
-#define PIN_NUM_MASK            0x1ff
-#define PIN_NUM(x)              ((x) & PIN_NUM_MASK)
-
-#define PIN_ALT_SHIFT           9
-#define PIN_ALT_MASK            (0x3 << PIN_ALT_SHIFT)
-#define PIN_ALT(x)              (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)
-#define PIN_GPIO                (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT)
-#define PIN_ALT_A               (NMK_GPIO_ALT_A << PIN_ALT_SHIFT)
-#define PIN_ALT_B               (NMK_GPIO_ALT_B << PIN_ALT_SHIFT)
-#define PIN_ALT_C               (NMK_GPIO_ALT_C << PIN_ALT_SHIFT)
-
-#define PIN_PULL_SHIFT          11
-#define PIN_PULL_MASK           (0x3 << PIN_PULL_SHIFT)
-#define PIN_PULL(x)             (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)
-#define PIN_PULL_NONE           (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT)
-#define PIN_PULL_UP             (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT)
-#define PIN_PULL_DOWN           (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT)
-
-#define PIN_SLPM_SHIFT          13
-#define PIN_SLPM_MASK           (0x1 << PIN_SLPM_SHIFT)
-#define PIN_SLPM(x)             (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
-#define PIN_SLPM_MAKE_INPUT     (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
-#define PIN_SLPM_NOCHANGE       (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
-/* These two replace the above in DB8500v2+ */
-#define PIN_SLPM_WAKEUP_ENABLE  (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
-#define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
-#define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE
-
-#define PIN_SLPM_GPIO  PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */
-#define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */
-
-#define PIN_DIR_SHIFT           14
-#define PIN_DIR_MASK            (0x1 << PIN_DIR_SHIFT)
-#define PIN_DIR(x)              (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT)
-#define PIN_DIR_INPUT           (0 << PIN_DIR_SHIFT)
-#define PIN_DIR_OUTPUT          (1 << PIN_DIR_SHIFT)
-
-#define PIN_VAL_SHIFT           15
-#define PIN_VAL_MASK            (0x1 << PIN_VAL_SHIFT)
-#define PIN_VAL(x)              (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT)
-#define PIN_VAL_LOW             (0 << PIN_VAL_SHIFT)
-#define PIN_VAL_HIGH            (1 << PIN_VAL_SHIFT)
-
-#define PIN_SLPM_PULL_SHIFT     16
-#define PIN_SLPM_PULL_MASK      (0x7 << PIN_SLPM_PULL_SHIFT)
-#define PIN_SLPM_PULL(x)        \
-        (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT)
-#define PIN_SLPM_PULL_NONE      \
-        ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT)
-#define PIN_SLPM_PULL_UP        \
-        ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT)
-#define PIN_SLPM_PULL_DOWN      \
-        ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT)
-
-#define PIN_SLPM_DIR_SHIFT      19
-#define PIN_SLPM_DIR_MASK       (0x3 << PIN_SLPM_DIR_SHIFT)
-#define PIN_SLPM_DIR(x)         \
-        (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT)
-#define PIN_SLPM_DIR_INPUT      ((1 + 0) << PIN_SLPM_DIR_SHIFT)
-#define PIN_SLPM_DIR_OUTPUT     ((1 + 1) << PIN_SLPM_DIR_SHIFT)
-
-#define PIN_SLPM_VAL_SHIFT      21
-#define PIN_SLPM_VAL_MASK       (0x3 << PIN_SLPM_VAL_SHIFT)
-#define PIN_SLPM_VAL(x)         \
-        (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT)
-#define PIN_SLPM_VAL_LOW        ((1 + 0) << PIN_SLPM_VAL_SHIFT)
-#define PIN_SLPM_VAL_HIGH       ((1 + 1) << PIN_SLPM_VAL_SHIFT)
-
-#define PIN_SLPM_PDIS_SHIFT             23
-#define PIN_SLPM_PDIS_MASK              (0x3 << PIN_SLPM_PDIS_SHIFT)
-#define PIN_SLPM_PDIS(x)        \
-        (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT)
-#define PIN_SLPM_PDIS_NO_CHANGE         (0 << PIN_SLPM_PDIS_SHIFT)
-#define PIN_SLPM_PDIS_DISABLED          (1 << PIN_SLPM_PDIS_SHIFT)
-#define PIN_SLPM_PDIS_ENABLED           (2 << PIN_SLPM_PDIS_SHIFT)
-
-#define PIN_LOWEMI_SHIFT        25
-#define PIN_LOWEMI_MASK         (0x1 << PIN_LOWEMI_SHIFT)
-#define PIN_LOWEMI(x)           (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT)
-#define PIN_LOWEMI_DISABLED     (0 << PIN_LOWEMI_SHIFT)
-#define PIN_LOWEMI_ENABLED      (1 << PIN_LOWEMI_SHIFT)
-
-#define PIN_GPIOMODE_SHIFT      26
-#define PIN_GPIOMODE_MASK       (0x1 << PIN_GPIOMODE_SHIFT)
-#define PIN_GPIOMODE(x)         (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT)
-#define PIN_GPIOMODE_DISABLED   (0 << PIN_GPIOMODE_SHIFT)
-#define PIN_GPIOMODE_ENABLED    (1 << PIN_GPIOMODE_SHIFT)
-
-#define PIN_SLEEPMODE_SHIFT     27
-#define PIN_SLEEPMODE_MASK      (0x1 << PIN_SLEEPMODE_SHIFT)
-#define PIN_SLEEPMODE(x)        (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT)
-#define PIN_SLEEPMODE_DISABLED  (0 << PIN_SLEEPMODE_SHIFT)
-#define PIN_SLEEPMODE_ENABLED   (1 << PIN_SLEEPMODE_SHIFT)
-
-
-/* Shortcuts.  Use these instead of separate DIR, PULL, and VAL.  */
-#define PIN_INPUT_PULLDOWN      (PIN_DIR_INPUT | PIN_PULL_DOWN)
-#define PIN_INPUT_PULLUP        (PIN_DIR_INPUT | PIN_PULL_UP)
-#define PIN_INPUT_NOPULL        (PIN_DIR_INPUT | PIN_PULL_NONE)
-#define PIN_OUTPUT_LOW          (PIN_DIR_OUTPUT | PIN_VAL_LOW)
-#define PIN_OUTPUT_HIGH         (PIN_DIR_OUTPUT | PIN_VAL_HIGH)
-
-#define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN)
-#define PIN_SLPM_INPUT_PULLUP   (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP)
-#define PIN_SLPM_INPUT_NOPULL   (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE)
-#define PIN_SLPM_OUTPUT_LOW     (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW)
-#define PIN_SLPM_OUTPUT_HIGH    (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH)
-
-#define PIN_CFG_DEFAULT         (0)
-
-#define PIN_CFG(num, alt)               \
-        (PIN_CFG_DEFAULT |\
-         (PIN_NUM(num) | PIN_##alt))
-
-#define PIN_CFG_INPUT(num, alt, pull)           \
-        (PIN_CFG_DEFAULT |\
-         (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull))
-
-#define PIN_CFG_OUTPUT(num, alt, val)           \
-        (PIN_CFG_DEFAULT |\
-         (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
-
-/*
- * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving
- * the "gpio" namespace for generic and cross-machine functions
- */
-
-#define GPIO_BLOCK_SHIFT 5
-#define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT)
-
-/* Register in the logic block */
-#define NMK_GPIO_DAT    0x00
-#define NMK_GPIO_DATS   0x04
-#define NMK_GPIO_DATC   0x08
-#define NMK_GPIO_PDIS   0x0c
-#define NMK_GPIO_DIR    0x10
-#define NMK_GPIO_DIRS   0x14
-#define NMK_GPIO_DIRC   0x18
-#define NMK_GPIO_SLPC   0x1c
-#define NMK_GPIO_AFSLA  0x20
-#define NMK_GPIO_AFSLB  0x24
-#define NMK_GPIO_LOWEMI 0x28
-
-#define NMK_GPIO_RIMSC  0x40
-#define NMK_GPIO_FIMSC  0x44
-#define NMK_GPIO_IS     0x48
-#define NMK_GPIO_IC     0x4c
-#define NMK_GPIO_RWIMSC 0x50
-#define NMK_GPIO_FWIMSC 0x54
-#define NMK_GPIO_WKS    0x58
-/* These appear in DB8540 and later ASICs */
-#define NMK_GPIO_EDGELEVEL 0x5C
-#define NMK_GPIO_LEVEL  0x60
-
-/* Alternate functions: function C is set in hw by setting both A and B */
-#define NMK_GPIO_ALT_GPIO       0
-#define NMK_GPIO_ALT_A  1
-#define NMK_GPIO_ALT_B  2
-#define NMK_GPIO_ALT_C  (NMK_GPIO_ALT_A | NMK_GPIO_ALT_B)
-
-#define NMK_GPIO_ALT_CX_SHIFT 2
-#define NMK_GPIO_ALT_C1 ((1<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
-#define NMK_GPIO_ALT_C2 ((2<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
-#define NMK_GPIO_ALT_C3 ((3<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
-#define NMK_GPIO_ALT_C4 ((4<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
-
-/* Pull up/down values */
-enum nmk_gpio_pull {
-        NMK_GPIO_PULL_NONE,
-        NMK_GPIO_PULL_UP,
-        NMK_GPIO_PULL_DOWN,
-};
-
-/* Sleep mode */
-enum nmk_gpio_slpm {
-        NMK_GPIO_SLPM_INPUT,
-        NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT,
-        NMK_GPIO_SLPM_NOCHANGE,
-        NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE,
-};
-
-/*
- * Platform data to register a block: only the initial gpio/irq number.
- */
-struct nmk_gpio_platform_data {
-        char *name;
-        int first_gpio;
-        int first_irq;
-        int num_gpio;
-        u32 (*get_secondary_status)(unsigned int bank);
-        void (*set_ioforce)(bool enable);
-        bool supports_sleepmode;
-};
-
-#endif /* __PLAT_NOMADIK_GPIO */