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authorLinus Torvalds <torvalds@linux-foundation.org>2014-04-05 18:46:37 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2014-04-05 18:46:37 -0400
commit2bf73dd61a84cdf27e49f48e08739af6ba70ace1 (patch)
tree225876ce1530ba6c3a96621a531f47e963fee691 /arch/arm/mach-integrator/include/mach
parentd2b150d0647e055d7a71b1c33140280550b27dd6 (diff)
parent9dfbff16b422a4bac7ad309847c7bc5d65653392 (diff)
Merge tag 'tags/cleanup2-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC late cleanups from Arnd Bergmann: "These could not be part of the first cleanup branch, because they either came too late in the cycle, or they have dependencies on other branches. Important changes are: - The integrator platform is almost multiplatform capable after some reorganization (Linus Walleij) - Minor cleanups on Zynq (Michal Simek) - Lots of changes for Exynos and other Samsung platforms, including further preparations for multiplatform support and the clocks bindings are rearranged" * tag 'tags/cleanup2-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (54 commits) devicetree: fix newly added exynos sata bindings ARM: EXYNOS: Fix compilation error in cpuidle.c ARM: S5P64X0: Explicitly include linux/serial_s3c.h in mach/pm-core.h ARM: EXYNOS: Remove hardware.h file ARM: SAMSUNG: Remove hardware.h inclusion ARM: S3C24XX: Remove invalid code from hardware.h dt-bindings: clock: Move exynos-audss-clk.h to dt-bindings/clock ARM: dts: Keep some essential LDOs enabled for arndale-octa board ARM: dts: Disable MDMA1 node for arndale-octa board ARM: S3C64XX: Fix build for implicit serial_s3c.h inclusion serial: s3c: Fix build of header without serial_core.h preinclusion ARM: EXYNOS: Allow wake-up using GIC interrupts ARM: EXYNOS: Stop using legacy Samsung PM code ARM: EXYNOS: Remove PM initcalls and useless indirection ARM: EXYNOS: Fix abuse of CONFIG_PM ARM: SAMSUNG: Move s3c_pm_check_* prototypes to plat/pm-common.h ARM: SAMSUNG: Move common save/restore helpers to separate file ARM: SAMSUNG: Move Samsung PM debug code into separate file ARM: SAMSUNG: Consolidate PM debug functions ARM: SAMSUNG: Use debug_ll_addr() to get UART base address ...
Diffstat (limited to 'arch/arm/mach-integrator/include/mach')
-rw-r--r--arch/arm/mach-integrator/include/mach/hardware.h45
-rw-r--r--arch/arm/mach-integrator/include/mach/impd1.h18
-rw-r--r--arch/arm/mach-integrator/include/mach/lm.h23
-rw-r--r--arch/arm/mach-integrator/include/mach/platform.h382
4 files changed, 0 insertions, 468 deletions
diff --git a/arch/arm/mach-integrator/include/mach/hardware.h b/arch/arm/mach-integrator/include/mach/hardware.h
deleted file mode 100644
index 65fed7c0eb84..000000000000
--- a/arch/arm/mach-integrator/include/mach/hardware.h
+++ /dev/null
@@ -1,45 +0,0 @@
1/*
2 * arch/arm/mach-integrator/include/mach/hardware.h
3 *
4 * This file contains the hardware definitions of the Integrator.
5 *
6 * Copyright (C) 1999 ARM Limited.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22#ifndef __ASM_ARCH_HARDWARE_H
23#define __ASM_ARCH_HARDWARE_H
24
25#include <asm/sizes.h>
26
27/*
28 * Where in virtual memory the IO devices (timers, system controllers
29 * and so on)
30 */
31#define IO_BASE 0xF0000000 // VA of IO
32#define IO_SIZE 0x0B000000 // How much?
33#define IO_START INTEGRATOR_HDR_BASE // PA of IO
34
35/* macro to get at IO space when running virtually */
36#ifdef CONFIG_MMU
37#define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
38#else
39#define IO_ADDRESS(x) (x)
40#endif
41
42#define __io_address(n) ((void __iomem *)IO_ADDRESS(n))
43
44#endif
45
diff --git a/arch/arm/mach-integrator/include/mach/impd1.h b/arch/arm/mach-integrator/include/mach/impd1.h
deleted file mode 100644
index d75de4b14237..000000000000
--- a/arch/arm/mach-integrator/include/mach/impd1.h
+++ /dev/null
@@ -1,18 +0,0 @@
1#define IMPD1_OSC1 0x00
2#define IMPD1_OSC2 0x04
3#define IMPD1_LOCK 0x08
4#define IMPD1_LEDS 0x0c
5#define IMPD1_INT 0x10
6#define IMPD1_SW 0x14
7#define IMPD1_CTRL 0x18
8
9#define IMPD1_CTRL_DISP_LCD (0 << 0)
10#define IMPD1_CTRL_DISP_VGA (1 << 0)
11#define IMPD1_CTRL_DISP_LCD1 (2 << 0)
12#define IMPD1_CTRL_DISP_ENABLE (1 << 2)
13#define IMPD1_CTRL_DISP_MASK (7 << 0)
14
15struct device;
16
17void impd1_tweak_control(struct device *dev, u32 mask, u32 val);
18
diff --git a/arch/arm/mach-integrator/include/mach/lm.h b/arch/arm/mach-integrator/include/mach/lm.h
deleted file mode 100644
index 28186b6f2c09..000000000000
--- a/arch/arm/mach-integrator/include/mach/lm.h
+++ /dev/null
@@ -1,23 +0,0 @@
1
2struct lm_device {
3 struct device dev;
4 struct resource resource;
5 unsigned int irq;
6 unsigned int id;
7};
8
9struct lm_driver {
10 struct device_driver drv;
11 int (*probe)(struct lm_device *);
12 void (*remove)(struct lm_device *);
13 int (*suspend)(struct lm_device *, pm_message_t);
14 int (*resume)(struct lm_device *);
15};
16
17int lm_driver_register(struct lm_driver *drv);
18void lm_driver_unregister(struct lm_driver *drv);
19
20int lm_device_register(struct lm_device *dev);
21
22#define lm_get_drvdata(lm) dev_get_drvdata(&(lm)->dev)
23#define lm_set_drvdata(lm,d) dev_set_drvdata(&(lm)->dev, d)
diff --git a/arch/arm/mach-integrator/include/mach/platform.h b/arch/arm/mach-integrator/include/mach/platform.h
deleted file mode 100644
index 306d025d9730..000000000000
--- a/arch/arm/mach-integrator/include/mach/platform.h
+++ /dev/null
@@ -1,382 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
15 */
16/**************************************************************************
17 * * Copyright © ARM Limited 1998. All rights reserved.
18 * ***********************************************************************/
19/* ************************************************************************
20 *
21 * Integrator address map
22 *
23 * ***********************************************************************/
24
25#ifndef __address_h
26#define __address_h 1
27
28/* ========================================================================
29 * Integrator definitions
30 * ========================================================================
31 * ------------------------------------------------------------------------
32 * Memory definitions
33 * ------------------------------------------------------------------------
34 * Integrator memory map
35 *
36 */
37#define INTEGRATOR_BOOT_ROM_LO 0x00000000
38#define INTEGRATOR_BOOT_ROM_HI 0x20000000
39#define INTEGRATOR_BOOT_ROM_BASE INTEGRATOR_BOOT_ROM_HI /* Normal position */
40#define INTEGRATOR_BOOT_ROM_SIZE SZ_512K
41
42/*
43 * New Core Modules have different amounts of SSRAM, the amount of SSRAM
44 * fitted can be found in HDR_STAT.
45 *
46 * The symbol INTEGRATOR_SSRAM_SIZE is kept, however this now refers to
47 * the minimum amount of SSRAM fitted on any core module.
48 *
49 * New Core Modules also alias the SSRAM.
50 *
51 */
52#define INTEGRATOR_SSRAM_BASE 0x00000000
53#define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000
54#define INTEGRATOR_SSRAM_SIZE SZ_256K
55
56#define INTEGRATOR_FLASH_BASE 0x24000000
57#define INTEGRATOR_FLASH_SIZE SZ_32M
58
59#define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000
60#define INTEGRATOR_MBRD_SSRAM_SIZE SZ_512K
61
62/*
63 * SDRAM is a SIMM therefore the size is not known.
64 *
65 */
66#define INTEGRATOR_SDRAM_BASE 0x00040000
67
68#define INTEGRATOR_SDRAM_ALIAS_BASE 0x80000000
69#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000
70#define INTEGRATOR_HDR1_SDRAM_BASE 0x90000000
71#define INTEGRATOR_HDR2_SDRAM_BASE 0xA0000000
72#define INTEGRATOR_HDR3_SDRAM_BASE 0xB0000000
73
74/*
75 * Logic expansion modules
76 *
77 */
78#define INTEGRATOR_LOGIC_MODULES_BASE 0xC0000000
79#define INTEGRATOR_LOGIC_MODULE0_BASE 0xC0000000
80#define INTEGRATOR_LOGIC_MODULE1_BASE 0xD0000000
81#define INTEGRATOR_LOGIC_MODULE2_BASE 0xE0000000
82#define INTEGRATOR_LOGIC_MODULE3_BASE 0xF0000000
83
84/* ------------------------------------------------------------------------
85 * Integrator header card registers
86 * ------------------------------------------------------------------------
87 *
88 */
89#define INTEGRATOR_HDR_ID_OFFSET 0x00
90#define INTEGRATOR_HDR_PROC_OFFSET 0x04
91#define INTEGRATOR_HDR_OSC_OFFSET 0x08
92#define INTEGRATOR_HDR_CTRL_OFFSET 0x0C
93#define INTEGRATOR_HDR_STAT_OFFSET 0x10
94#define INTEGRATOR_HDR_LOCK_OFFSET 0x14
95#define INTEGRATOR_HDR_SDRAM_OFFSET 0x20
96#define INTEGRATOR_HDR_INIT_OFFSET 0x24 /* CM9x6 */
97#define INTEGRATOR_HDR_IC_OFFSET 0x40
98#define INTEGRATOR_HDR_SPDBASE_OFFSET 0x100
99#define INTEGRATOR_HDR_SPDTOP_OFFSET 0x200
100
101#define INTEGRATOR_HDR_BASE 0x10000000
102#define INTEGRATOR_HDR_ID (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_ID_OFFSET)
103#define INTEGRATOR_HDR_PROC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_PROC_OFFSET)
104#define INTEGRATOR_HDR_OSC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_OSC_OFFSET)
105#define INTEGRATOR_HDR_CTRL (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_CTRL_OFFSET)
106#define INTEGRATOR_HDR_STAT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_STAT_OFFSET)
107#define INTEGRATOR_HDR_LOCK (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_LOCK_OFFSET)
108#define INTEGRATOR_HDR_SDRAM (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SDRAM_OFFSET)
109#define INTEGRATOR_HDR_INIT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_INIT_OFFSET)
110#define INTEGRATOR_HDR_IC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_IC_OFFSET)
111#define INTEGRATOR_HDR_SPDBASE (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDBASE_OFFSET)
112#define INTEGRATOR_HDR_SPDTOP (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDTOP_OFFSET)
113
114#define INTEGRATOR_HDR_CTRL_LED 0x01
115#define INTEGRATOR_HDR_CTRL_MBRD_DETECH 0x02
116#define INTEGRATOR_HDR_CTRL_REMAP 0x04
117#define INTEGRATOR_HDR_CTRL_RESET 0x08
118#define INTEGRATOR_HDR_CTRL_HIGHVECTORS 0x10
119#define INTEGRATOR_HDR_CTRL_BIG_ENDIAN 0x20
120#define INTEGRATOR_HDR_CTRL_FASTBUS 0x40
121#define INTEGRATOR_HDR_CTRL_SYNC 0x80
122
123#define INTEGRATOR_HDR_OSC_CORE_10MHz 0x102
124#define INTEGRATOR_HDR_OSC_CORE_15MHz 0x107
125#define INTEGRATOR_HDR_OSC_CORE_20MHz 0x10C
126#define INTEGRATOR_HDR_OSC_CORE_25MHz 0x111
127#define INTEGRATOR_HDR_OSC_CORE_30MHz 0x116
128#define INTEGRATOR_HDR_OSC_CORE_35MHz 0x11B
129#define INTEGRATOR_HDR_OSC_CORE_40MHz 0x120
130#define INTEGRATOR_HDR_OSC_CORE_45MHz 0x125
131#define INTEGRATOR_HDR_OSC_CORE_50MHz 0x12A
132#define INTEGRATOR_HDR_OSC_CORE_55MHz 0x12F
133#define INTEGRATOR_HDR_OSC_CORE_60MHz 0x134
134#define INTEGRATOR_HDR_OSC_CORE_65MHz 0x139
135#define INTEGRATOR_HDR_OSC_CORE_70MHz 0x13E
136#define INTEGRATOR_HDR_OSC_CORE_75MHz 0x143
137#define INTEGRATOR_HDR_OSC_CORE_80MHz 0x148
138#define INTEGRATOR_HDR_OSC_CORE_85MHz 0x14D
139#define INTEGRATOR_HDR_OSC_CORE_90MHz 0x152
140#define INTEGRATOR_HDR_OSC_CORE_95MHz 0x157
141#define INTEGRATOR_HDR_OSC_CORE_100MHz 0x15C
142#define INTEGRATOR_HDR_OSC_CORE_105MHz 0x161
143#define INTEGRATOR_HDR_OSC_CORE_110MHz 0x166
144#define INTEGRATOR_HDR_OSC_CORE_115MHz 0x16B
145#define INTEGRATOR_HDR_OSC_CORE_120MHz 0x170
146#define INTEGRATOR_HDR_OSC_CORE_125MHz 0x175
147#define INTEGRATOR_HDR_OSC_CORE_130MHz 0x17A
148#define INTEGRATOR_HDR_OSC_CORE_135MHz 0x17F
149#define INTEGRATOR_HDR_OSC_CORE_140MHz 0x184
150#define INTEGRATOR_HDR_OSC_CORE_145MHz 0x189
151#define INTEGRATOR_HDR_OSC_CORE_150MHz 0x18E
152#define INTEGRATOR_HDR_OSC_CORE_155MHz 0x193
153#define INTEGRATOR_HDR_OSC_CORE_160MHz 0x198
154#define INTEGRATOR_HDR_OSC_CORE_MASK 0x7FF
155
156#define INTEGRATOR_HDR_OSC_MEM_10MHz 0x10C000
157#define INTEGRATOR_HDR_OSC_MEM_15MHz 0x116000
158#define INTEGRATOR_HDR_OSC_MEM_20MHz 0x120000
159#define INTEGRATOR_HDR_OSC_MEM_25MHz 0x12A000
160#define INTEGRATOR_HDR_OSC_MEM_30MHz 0x134000
161#define INTEGRATOR_HDR_OSC_MEM_33MHz 0x13A000
162#define INTEGRATOR_HDR_OSC_MEM_40MHz 0x148000
163#define INTEGRATOR_HDR_OSC_MEM_50MHz 0x15C000
164#define INTEGRATOR_HDR_OSC_MEM_60MHz 0x170000
165#define INTEGRATOR_HDR_OSC_MEM_66MHz 0x17C000
166#define INTEGRATOR_HDR_OSC_MEM_MASK 0x7FF000
167
168#define INTEGRATOR_HDR_OSC_BUS_MODE_CM7x0 0x0
169#define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x0 0x0800000
170#define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x6 0x1000000
171#define INTEGRATOR_HDR_OSC_BUS_MODE_CM10x00 0x1800000
172#define INTEGRATOR_HDR_OSC_BUS_MODE_MASK 0x1800000
173
174#define INTEGRATOR_HDR_SDRAM_SPD_OK (1 << 5)
175
176
177/* ------------------------------------------------------------------------
178 * Integrator system registers
179 * ------------------------------------------------------------------------
180 *
181 */
182
183/*
184 * System Controller
185 *
186 */
187#define INTEGRATOR_SC_ID_OFFSET 0x00
188#define INTEGRATOR_SC_OSC_OFFSET 0x04
189#define INTEGRATOR_SC_CTRLS_OFFSET 0x08
190#define INTEGRATOR_SC_CTRLC_OFFSET 0x0C
191#define INTEGRATOR_SC_DEC_OFFSET 0x10
192#define INTEGRATOR_SC_ARB_OFFSET 0x14
193#define INTEGRATOR_SC_LOCK_OFFSET 0x1C
194
195#define INTEGRATOR_SC_BASE 0x11000000
196#define INTEGRATOR_SC_ID (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ID_OFFSET)
197#define INTEGRATOR_SC_OSC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_OSC_OFFSET)
198#define INTEGRATOR_SC_CTRLS (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
199#define INTEGRATOR_SC_CTRLC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
200#define INTEGRATOR_SC_DEC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_DEC_OFFSET)
201#define INTEGRATOR_SC_ARB (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ARB_OFFSET)
202#define INTEGRATOR_SC_PCIENABLE (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET)
203#define INTEGRATOR_SC_LOCK (INTEGRATOR_SC_BASE + INTEGRATOR_SC_LOCK_OFFSET)
204
205#define INTEGRATOR_SC_OSC_SYS_10MHz 0x20
206#define INTEGRATOR_SC_OSC_SYS_15MHz 0x34
207#define INTEGRATOR_SC_OSC_SYS_20MHz 0x48
208#define INTEGRATOR_SC_OSC_SYS_25MHz 0x5C
209#define INTEGRATOR_SC_OSC_SYS_33MHz 0x7C
210#define INTEGRATOR_SC_OSC_SYS_MASK 0xFF
211
212#define INTEGRATOR_SC_OSC_PCI_25MHz 0x100
213#define INTEGRATOR_SC_OSC_PCI_33MHz 0x0
214#define INTEGRATOR_SC_OSC_PCI_MASK 0x100
215
216#define INTEGRATOR_SC_CTRL_SOFTRST (1 << 0)
217#define INTEGRATOR_SC_CTRL_nFLVPPEN (1 << 1)
218#define INTEGRATOR_SC_CTRL_nFLWP (1 << 2)
219#define INTEGRATOR_SC_CTRL_URTS0 (1 << 4)
220#define INTEGRATOR_SC_CTRL_UDTR0 (1 << 5)
221#define INTEGRATOR_SC_CTRL_URTS1 (1 << 6)
222#define INTEGRATOR_SC_CTRL_UDTR1 (1 << 7)
223
224/*
225 * External Bus Interface
226 *
227 */
228#define INTEGRATOR_EBI_BASE 0x12000000
229
230#define INTEGRATOR_EBI_CSR0_OFFSET 0x00
231#define INTEGRATOR_EBI_CSR1_OFFSET 0x04
232#define INTEGRATOR_EBI_CSR2_OFFSET 0x08
233#define INTEGRATOR_EBI_CSR3_OFFSET 0x0C
234#define INTEGRATOR_EBI_LOCK_OFFSET 0x20
235
236#define INTEGRATOR_EBI_CSR0 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR0_OFFSET)
237#define INTEGRATOR_EBI_CSR1 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
238#define INTEGRATOR_EBI_CSR2 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR2_OFFSET)
239#define INTEGRATOR_EBI_CSR3 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR3_OFFSET)
240#define INTEGRATOR_EBI_LOCK (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
241
242#define INTEGRATOR_EBI_8_BIT 0x00
243#define INTEGRATOR_EBI_16_BIT 0x01
244#define INTEGRATOR_EBI_32_BIT 0x02
245#define INTEGRATOR_EBI_WRITE_ENABLE 0x04
246#define INTEGRATOR_EBI_SYNC 0x08
247#define INTEGRATOR_EBI_WS_2 0x00
248#define INTEGRATOR_EBI_WS_3 0x10
249#define INTEGRATOR_EBI_WS_4 0x20
250#define INTEGRATOR_EBI_WS_5 0x30
251#define INTEGRATOR_EBI_WS_6 0x40
252#define INTEGRATOR_EBI_WS_7 0x50
253#define INTEGRATOR_EBI_WS_8 0x60
254#define INTEGRATOR_EBI_WS_9 0x70
255#define INTEGRATOR_EBI_WS_10 0x80
256#define INTEGRATOR_EBI_WS_11 0x90
257#define INTEGRATOR_EBI_WS_12 0xA0
258#define INTEGRATOR_EBI_WS_13 0xB0
259#define INTEGRATOR_EBI_WS_14 0xC0
260#define INTEGRATOR_EBI_WS_15 0xD0
261#define INTEGRATOR_EBI_WS_16 0xE0
262#define INTEGRATOR_EBI_WS_17 0xF0
263
264
265#define INTEGRATOR_CT_BASE 0x13000000 /* Counter/Timers */
266#define INTEGRATOR_IC_BASE 0x14000000 /* Interrupt Controller */
267#define INTEGRATOR_RTC_BASE 0x15000000 /* Real Time Clock */
268#define INTEGRATOR_UART0_BASE 0x16000000 /* UART 0 */
269#define INTEGRATOR_UART1_BASE 0x17000000 /* UART 1 */
270#define INTEGRATOR_KBD_BASE 0x18000000 /* Keyboard */
271#define INTEGRATOR_MOUSE_BASE 0x19000000 /* Mouse */
272
273/*
274 * LED's & Switches
275 *
276 */
277#define INTEGRATOR_DBG_ALPHA_OFFSET 0x00
278#define INTEGRATOR_DBG_LEDS_OFFSET 0x04
279#define INTEGRATOR_DBG_SWITCH_OFFSET 0x08
280
281#define INTEGRATOR_DBG_BASE 0x1A000000
282#define INTEGRATOR_DBG_ALPHA (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_ALPHA_OFFSET)
283#define INTEGRATOR_DBG_LEDS (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_LEDS_OFFSET)
284#define INTEGRATOR_DBG_SWITCH (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_SWITCH_OFFSET)
285
286#define INTEGRATOR_AP_GPIO_BASE 0x1B000000 /* GPIO */
287
288#define INTEGRATOR_CP_MMC_BASE 0x1C000000 /* MMC */
289#define INTEGRATOR_CP_AACI_BASE 0x1D000000 /* AACI */
290#define INTEGRATOR_CP_ETH_BASE 0xC8000000 /* Ethernet */
291#define INTEGRATOR_CP_GPIO_BASE 0xC9000000 /* GPIO */
292#define INTEGRATOR_CP_SIC_BASE 0xCA000000 /* SIC */
293#define INTEGRATOR_CP_CTL_BASE 0xCB000000 /* CP system control */
294
295/* ------------------------------------------------------------------------
296 * KMI keyboard/mouse definitions
297 * ------------------------------------------------------------------------
298 */
299/* PS2 Keyboard interface */
300#define KMI0_BASE INTEGRATOR_KBD_BASE
301
302/* PS2 Mouse interface */
303#define KMI1_BASE INTEGRATOR_MOUSE_BASE
304
305/* KMI definitions are now in include/asm-arm/hardware/amba_kmi.h -- rmk */
306
307/* ------------------------------------------------------------------------
308 * Integrator Interrupt Controllers
309 * ------------------------------------------------------------------------
310 *
311 * Offsets from interrupt controller base
312 *
313 * System Controller interrupt controller base is
314 *
315 * INTEGRATOR_IC_BASE + (header_number << 6)
316 *
317 * Core Module interrupt controller base is
318 *
319 * INTEGRATOR_HDR_IC
320 *
321 */
322#define IRQ_STATUS 0
323#define IRQ_RAW_STATUS 0x04
324#define IRQ_ENABLE 0x08
325#define IRQ_ENABLE_SET 0x08
326#define IRQ_ENABLE_CLEAR 0x0C
327
328#define INT_SOFT_SET 0x10
329#define INT_SOFT_CLEAR 0x14
330
331#define FIQ_STATUS 0x20
332#define FIQ_RAW_STATUS 0x24
333#define FIQ_ENABLE 0x28
334#define FIQ_ENABLE_SET 0x28
335#define FIQ_ENABLE_CLEAR 0x2C
336
337
338/* ------------------------------------------------------------------------
339 * Interrupts
340 * ------------------------------------------------------------------------
341 *
342 *
343 * Each Core Module has two interrupts controllers, one on the core module
344 * itself and one in the system controller on the motherboard. The
345 * READ_INT macro in target.s reads both interrupt controllers and returns
346 * a 32 bit bitmask, bits 0 to 23 are interrupts from the system controller
347 * and bits 24 to 31 are from the core module.
348 *
349 * The following definitions relate to the bitmask returned by READ_INT.
350 *
351 */
352
353/* ------------------------------------------------------------------------
354 * LED's
355 * ------------------------------------------------------------------------
356 *
357 */
358#define GREEN_LED 0x01
359#define YELLOW_LED 0x02
360#define RED_LED 0x04
361#define GREEN_LED_2 0x08
362#define ALL_LEDS 0x0F
363
364#define LED_BANK INTEGRATOR_DBG_LEDS
365
366/*
367 * Timer definitions
368 *
369 * Only use timer 1 & 2
370 * (both run at 24MHz and will need the clock divider set to 16).
371 *
372 * Timer 0 runs at bus frequency
373 */
374
375#define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE
376#define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100)
377#define INTEGRATOR_TIMER2_BASE (INTEGRATOR_CT_BASE + 0x200)
378
379#define INTEGRATOR_CSR_BASE 0x10000000
380#define INTEGRATOR_CSR_SIZE 0x10000000
381
382#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 05:59:41 -0500