diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2014-04-05 18:46:37 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2014-04-05 18:46:37 -0400 |
commit | 2bf73dd61a84cdf27e49f48e08739af6ba70ace1 (patch) | |
tree | 225876ce1530ba6c3a96621a531f47e963fee691 | |
parent | d2b150d0647e055d7a71b1c33140280550b27dd6 (diff) | |
parent | 9dfbff16b422a4bac7ad309847c7bc5d65653392 (diff) |
Merge tag 'tags/cleanup2-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC late cleanups from Arnd Bergmann:
"These could not be part of the first cleanup branch, because they
either came too late in the cycle, or they have dependencies on other
branches. Important changes are:
- The integrator platform is almost multiplatform capable after some
reorganization (Linus Walleij)
- Minor cleanups on Zynq (Michal Simek)
- Lots of changes for Exynos and other Samsung platforms, including
further preparations for multiplatform support and the clocks
bindings are rearranged"
* tag 'tags/cleanup2-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (54 commits)
devicetree: fix newly added exynos sata bindings
ARM: EXYNOS: Fix compilation error in cpuidle.c
ARM: S5P64X0: Explicitly include linux/serial_s3c.h in mach/pm-core.h
ARM: EXYNOS: Remove hardware.h file
ARM: SAMSUNG: Remove hardware.h inclusion
ARM: S3C24XX: Remove invalid code from hardware.h
dt-bindings: clock: Move exynos-audss-clk.h to dt-bindings/clock
ARM: dts: Keep some essential LDOs enabled for arndale-octa board
ARM: dts: Disable MDMA1 node for arndale-octa board
ARM: S3C64XX: Fix build for implicit serial_s3c.h inclusion
serial: s3c: Fix build of header without serial_core.h preinclusion
ARM: EXYNOS: Allow wake-up using GIC interrupts
ARM: EXYNOS: Stop using legacy Samsung PM code
ARM: EXYNOS: Remove PM initcalls and useless indirection
ARM: EXYNOS: Fix abuse of CONFIG_PM
ARM: SAMSUNG: Move s3c_pm_check_* prototypes to plat/pm-common.h
ARM: SAMSUNG: Move common save/restore helpers to separate file
ARM: SAMSUNG: Move Samsung PM debug code into separate file
ARM: SAMSUNG: Consolidate PM debug functions
ARM: SAMSUNG: Use debug_ll_addr() to get UART base address
...
92 files changed, 1156 insertions, 1369 deletions
diff --git a/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt b/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt deleted file mode 100644 index 37824fac688e..000000000000 --- a/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt +++ /dev/null | |||
@@ -1,14 +0,0 @@ | |||
1 | * Samsung SATA PHY Controller | ||
2 | |||
3 | SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers. | ||
4 | Each SATA PHY controller should have its own node. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible : compatible list, contains "samsung,exynos5-sata-phy" | ||
8 | - reg : <registers mapping> | ||
9 | |||
10 | Example: | ||
11 | sata@ffe07000 { | ||
12 | compatible = "samsung,exynos5-sata-phy"; | ||
13 | reg = <0xffe07000 0x1000>; | ||
14 | }; | ||
diff --git a/Documentation/devicetree/bindings/ata/exynos-sata.txt b/Documentation/devicetree/bindings/ata/exynos-sata.txt index 0849f1025e34..cb48448247ea 100644 --- a/Documentation/devicetree/bindings/ata/exynos-sata.txt +++ b/Documentation/devicetree/bindings/ata/exynos-sata.txt | |||
@@ -4,14 +4,27 @@ SATA nodes are defined to describe on-chip Serial ATA controllers. | |||
4 | Each SATA controller should have its own node. | 4 | Each SATA controller should have its own node. |
5 | 5 | ||
6 | Required properties: | 6 | Required properties: |
7 | - compatible : compatible list, contains "samsung,exynos5-sata" | 7 | - compatible : compatible list, contains "samsung,exynos5-sata" |
8 | - interrupts : <interrupt mapping for SATA IRQ> | 8 | - interrupts : <interrupt mapping for SATA IRQ> |
9 | - reg : <registers mapping> | 9 | - reg : <registers mapping> |
10 | - samsung,sata-freq : <frequency in MHz> | 10 | - samsung,sata-freq : <frequency in MHz> |
11 | - phys : Must contain exactly one entry as specified | ||
12 | in phy-bindings.txt | ||
13 | - phy-names : Must be "sata-phy" | ||
14 | |||
15 | Optional properties: | ||
16 | - clocks : Must contain an entry for each entry in clock-names. | ||
17 | - clock-names : Shall be "sata" for the external SATA bus clock, | ||
18 | and "sclk_sata" for the internal controller clock. | ||
11 | 19 | ||
12 | Example: | 20 | Example: |
13 | sata@ffe08000 { | 21 | sata@122f0000 { |
14 | compatible = "samsung,exynos5-sata"; | 22 | compatible = "snps,dwc-ahci"; |
15 | reg = <0xffe08000 0x1000>; | 23 | samsung,sata-freq = <66>; |
16 | interrupts = <115>; | 24 | reg = <0x122f0000 0x1ff>; |
17 | }; | 25 | interrupts = <0 115 0>; |
26 | clocks = <&clock 277>, <&clock 143>; | ||
27 | clock-names = "sata", "sclk_sata"; | ||
28 | phys = <&sata_phy>; | ||
29 | phy-names = "sata-phy"; | ||
30 | }; | ||
diff --git a/Documentation/devicetree/bindings/clock/zynq-7000.txt b/Documentation/devicetree/bindings/clock/zynq-7000.txt index 17b4a94916d6..d93746cf2975 100644 --- a/Documentation/devicetree/bindings/clock/zynq-7000.txt +++ b/Documentation/devicetree/bindings/clock/zynq-7000.txt | |||
@@ -14,6 +14,7 @@ for all clock consumers of PS clocks. | |||
14 | Required properties: | 14 | Required properties: |
15 | - #clock-cells : Must be 1 | 15 | - #clock-cells : Must be 1 |
16 | - compatible : "xlnx,ps7-clkc" | 16 | - compatible : "xlnx,ps7-clkc" |
17 | - reg : SLCR offset and size taken via syscon < 0x100 0x100 > | ||
17 | - ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ | 18 | - ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ |
18 | (usually 33 MHz oscillators are used for Zynq platforms) | 19 | (usually 33 MHz oscillators are used for Zynq platforms) |
19 | - clock-output-names : List of strings used to name the clock outputs. Shall be | 20 | - clock-output-names : List of strings used to name the clock outputs. Shall be |
@@ -87,10 +88,11 @@ Clock outputs: | |||
87 | 47: dbg_apb | 88 | 47: dbg_apb |
88 | 89 | ||
89 | Example: | 90 | Example: |
90 | clkc: clkc { | 91 | clkc: clkc@100 { |
91 | #clock-cells = <1>; | 92 | #clock-cells = <1>; |
92 | compatible = "xlnx,ps7-clkc"; | 93 | compatible = "xlnx,ps7-clkc"; |
93 | ps-clk-frequency = <33333333>; | 94 | ps-clk-frequency = <33333333>; |
95 | reg = <0x100 0x100>; | ||
94 | clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", | 96 | clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", |
95 | "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", | 97 | "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", |
96 | "dci", "lqspi", "smc", "pcap", "gem0", "gem1", | 98 | "dci", "lqspi", "smc", "pcap", "gem0", "gem1", |
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt index 28f9edb8f19c..b422e38946d7 100644 --- a/Documentation/devicetree/bindings/phy/samsung-phy.txt +++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt | |||
@@ -74,3 +74,43 @@ phy-consumer@12340000 { | |||
74 | 74 | ||
75 | Refer to DT bindings documentation of particular PHY consumer devices for more | 75 | Refer to DT bindings documentation of particular PHY consumer devices for more |
76 | information about required PHYs and the way of specification. | 76 | information about required PHYs and the way of specification. |
77 | |||
78 | Samsung SATA PHY Controller | ||
79 | --------------------------- | ||
80 | |||
81 | SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers. | ||
82 | Each SATA PHY controller should have its own node. | ||
83 | |||
84 | Required properties: | ||
85 | - compatible : compatible list, contains "samsung,exynos5250-sata-phy" | ||
86 | - reg : offset and length of the SATA PHY register set; | ||
87 | - #phy-cells : must be zero | ||
88 | - clocks : must be exactly one entry | ||
89 | - clock-names : must be "sata_phyctrl" | ||
90 | - samsung,exynos-sataphy-i2c-phandle : a phandle to the I2C device, no arguments | ||
91 | - samsung,syscon-phandle : a phandle to the PMU system controller, no arguments | ||
92 | |||
93 | Example: | ||
94 | sata_phy: sata-phy@12170000 { | ||
95 | compatible = "samsung,exynos5250-sata-phy"; | ||
96 | reg = <0x12170000 0x1ff>; | ||
97 | clocks = <&clock 287>; | ||
98 | clock-names = "sata_phyctrl"; | ||
99 | #phy-cells = <0>; | ||
100 | samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>; | ||
101 | samsung,syscon-phandle = <&pmu_syscon>; | ||
102 | }; | ||
103 | |||
104 | Device-Tree bindings for sataphy i2c client driver | ||
105 | -------------------------------------------------- | ||
106 | |||
107 | Required properties: | ||
108 | compatible: Should be "samsung,exynos-sataphy-i2c" | ||
109 | - reg: I2C address of the sataphy i2c device. | ||
110 | |||
111 | Example: | ||
112 | |||
113 | sata_phy_i2c:sata-phy@38 { | ||
114 | compatible = "samsung,exynos-sataphy-i2c"; | ||
115 | reg = <0x38>; | ||
116 | }; | ||
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 8983919a4421..4a2fc0bf6fc9 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug | |||
@@ -1141,7 +1141,7 @@ config DEBUG_UART_8250_FLOW_CONTROL | |||
1141 | 1141 | ||
1142 | config DEBUG_UNCOMPRESS | 1142 | config DEBUG_UNCOMPRESS |
1143 | bool | 1143 | bool |
1144 | depends on ARCH_MULTIPLATFORM || ARCH_MSM || ARCH_EXYNOS | 1144 | depends on ARCH_MULTIPLATFORM || ARCH_MSM || PLAT_SAMSUNG |
1145 | default y if DEBUG_LL && !DEBUG_OMAP2PLUS_UART && \ | 1145 | default y if DEBUG_LL && !DEBUG_OMAP2PLUS_UART && \ |
1146 | (!DEBUG_TEGRA_UART || !ZBOOT_ROM) | 1146 | (!DEBUG_TEGRA_UART || !ZBOOT_ROM) |
1147 | help | 1147 | help |
@@ -1158,7 +1158,7 @@ config DEBUG_UNCOMPRESS | |||
1158 | config UNCOMPRESS_INCLUDE | 1158 | config UNCOMPRESS_INCLUDE |
1159 | string | 1159 | string |
1160 | default "debug/uncompress.h" if ARCH_MULTIPLATFORM || ARCH_MSM || \ | 1160 | default "debug/uncompress.h" if ARCH_MULTIPLATFORM || ARCH_MSM || \ |
1161 | ARCH_EXYNOS || ARCH_EFM32 | 1161 | PLAT_SAMSUNG || ARCH_EFM32 |
1162 | default "mach/uncompress.h" | 1162 | default "mach/uncompress.h" |
1163 | 1163 | ||
1164 | config EARLY_PRINTK | 1164 | config EARLY_PRINTK |
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 28b5ec79f339..0401f4dba2a2 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi | |||
@@ -86,6 +86,11 @@ | |||
86 | reg = <0x10023CE0 0x20>; | 86 | reg = <0x10023CE0 0x20>; |
87 | }; | 87 | }; |
88 | 88 | ||
89 | pd_gps_alive: gps-alive-power-domain@10023D00 { | ||
90 | compatible = "samsung,exynos4210-pd"; | ||
91 | reg = <0x10023D00 0x20>; | ||
92 | }; | ||
93 | |||
89 | gic: interrupt-controller@10490000 { | 94 | gic: interrupt-controller@10490000 { |
90 | compatible = "arm,cortex-a9-gic"; | 95 | compatible = "arm,cortex-a9-gic"; |
91 | #interrupt-cells = <3>; | 96 | #interrupt-cells = <3>; |
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index 2aa13cb3bbed..72fb11f7ea21 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts | |||
@@ -19,7 +19,7 @@ | |||
19 | 19 | ||
20 | / { | 20 | / { |
21 | model = "Insignal Origen evaluation board based on Exynos4210"; | 21 | model = "Insignal Origen evaluation board based on Exynos4210"; |
22 | compatible = "insignal,origen", "samsung,exynos4210"; | 22 | compatible = "insignal,origen", "samsung,exynos4210", "samsung,exynos4"; |
23 | 23 | ||
24 | memory { | 24 | memory { |
25 | reg = <0x40000000 0x10000000 | 25 | reg = <0x40000000 0x10000000 |
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts index 9c01b718d29d..636d16684750 100644 --- a/arch/arm/boot/dts/exynos4210-smdkv310.dts +++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts | |||
@@ -19,7 +19,7 @@ | |||
19 | 19 | ||
20 | / { | 20 | / { |
21 | model = "Samsung smdkv310 evaluation board based on Exynos4210"; | 21 | model = "Samsung smdkv310 evaluation board based on Exynos4210"; |
22 | compatible = "samsung,smdkv310", "samsung,exynos4210"; | 22 | compatible = "samsung,smdkv310", "samsung,exynos4210", "samsung,exynos4"; |
23 | 23 | ||
24 | memory { | 24 | memory { |
25 | reg = <0x40000000 0x80000000>; | 25 | reg = <0x40000000 0x80000000>; |
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index 63cc571ca307..361cb58052bf 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts | |||
@@ -17,7 +17,7 @@ | |||
17 | 17 | ||
18 | / { | 18 | / { |
19 | model = "Samsung Trats based on Exynos4210"; | 19 | model = "Samsung Trats based on Exynos4210"; |
20 | compatible = "samsung,trats", "samsung,exynos4210"; | 20 | compatible = "samsung,trats", "samsung,exynos4210", "samsung,exynos4"; |
21 | 21 | ||
22 | memory { | 22 | memory { |
23 | reg = <0x40000000 0x10000000 | 23 | reg = <0x40000000 0x10000000 |
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index d2e3f5f5916d..27d3b70ee9e3 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts | |||
@@ -17,7 +17,7 @@ | |||
17 | 17 | ||
18 | / { | 18 | / { |
19 | model = "Samsung Universal C210 based on Exynos4210 rev0"; | 19 | model = "Samsung Universal C210 based on Exynos4210 rev0"; |
20 | compatible = "samsung,universal_c210", "samsung,exynos4210"; | 20 | compatible = "samsung,universal_c210", "samsung,exynos4210", "samsung,exynos4"; |
21 | 21 | ||
22 | memory { | 22 | memory { |
23 | reg = <0x40000000 0x10000000 | 23 | reg = <0x40000000 0x10000000 |
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index cb0e768dc6d4..cacf6140dd2f 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi | |||
@@ -23,7 +23,7 @@ | |||
23 | #include "exynos4210-pinctrl.dtsi" | 23 | #include "exynos4210-pinctrl.dtsi" |
24 | 24 | ||
25 | / { | 25 | / { |
26 | compatible = "samsung,exynos4210"; | 26 | compatible = "samsung,exynos4210", "samsung,exynos4"; |
27 | 27 | ||
28 | aliases { | 28 | aliases { |
29 | pinctrl0 = &pinctrl_0; | 29 | pinctrl0 = &pinctrl_0; |
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi index 94a43f9a05e2..3c00e6ec9302 100644 --- a/arch/arm/boot/dts/exynos4212.dtsi +++ b/arch/arm/boot/dts/exynos4212.dtsi | |||
@@ -20,18 +20,13 @@ | |||
20 | #include "exynos4x12.dtsi" | 20 | #include "exynos4x12.dtsi" |
21 | 21 | ||
22 | / { | 22 | / { |
23 | compatible = "samsung,exynos4212"; | 23 | compatible = "samsung,exynos4212", "samsung,exynos4"; |
24 | 24 | ||
25 | gic: interrupt-controller@10490000 { | 25 | combiner: interrupt-controller@10440000 { |
26 | cpu-offset = <0x8000>; | 26 | samsung,combiner-nr = <18>; |
27 | }; | 27 | }; |
28 | 28 | ||
29 | interrupt-controller@10440000 { | 29 | gic: interrupt-controller@10490000 { |
30 | samsung,combiner-nr = <18>; | 30 | cpu-offset = <0x8000>; |
31 | interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, | ||
32 | <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, | ||
33 | <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, | ||
34 | <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, | ||
35 | <0 107 0>, <0 108 0>; | ||
36 | }; | 31 | }; |
37 | }; | 32 | }; |
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index 12459b01cca3..31db28a4bb33 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts | |||
@@ -16,7 +16,7 @@ | |||
16 | 16 | ||
17 | / { | 17 | / { |
18 | model = "Hardkernel ODROID-X board based on Exynos4412"; | 18 | model = "Hardkernel ODROID-X board based on Exynos4412"; |
19 | compatible = "hardkernel,odroid-x", "samsung,exynos4412"; | 19 | compatible = "hardkernel,odroid-x", "samsung,exynos4412", "samsung,exynos4"; |
20 | 20 | ||
21 | memory { | 21 | memory { |
22 | reg = <0x40000000 0x40000000>; | 22 | reg = <0x40000000 0x40000000>; |
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index 388f03579661..e2c0dcab4d81 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts | |||
@@ -17,7 +17,7 @@ | |||
17 | 17 | ||
18 | / { | 18 | / { |
19 | model = "Insignal Origen evaluation board based on Exynos4412"; | 19 | model = "Insignal Origen evaluation board based on Exynos4412"; |
20 | compatible = "insignal,origen4412", "samsung,exynos4412"; | 20 | compatible = "insignal,origen4412", "samsung,exynos4412", "samsung,exynos4"; |
21 | 21 | ||
22 | memory { | 22 | memory { |
23 | reg = <0x40000000 0x40000000>; | 23 | reg = <0x40000000 0x40000000>; |
diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts index ad316a1ee9e0..ded0b70f7644 100644 --- a/arch/arm/boot/dts/exynos4412-smdk4412.dts +++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts | |||
@@ -17,7 +17,7 @@ | |||
17 | 17 | ||
18 | / { | 18 | / { |
19 | model = "Samsung SMDK evaluation board based on Exynos4412"; | 19 | model = "Samsung SMDK evaluation board based on Exynos4412"; |
20 | compatible = "samsung,smdk4412", "samsung,exynos4412"; | 20 | compatible = "samsung,smdk4412", "samsung,exynos4412", "samsung,exynos4"; |
21 | 21 | ||
22 | memory { | 22 | memory { |
23 | reg = <0x40000000 0x40000000>; | 23 | reg = <0x40000000 0x40000000>; |
diff --git a/arch/arm/boot/dts/exynos4412-tiny4412.dts b/arch/arm/boot/dts/exynos4412-tiny4412.dts index 0a9831256b33..ea6929d9c621 100644 --- a/arch/arm/boot/dts/exynos4412-tiny4412.dts +++ b/arch/arm/boot/dts/exynos4412-tiny4412.dts | |||
@@ -16,7 +16,7 @@ | |||
16 | 16 | ||
17 | / { | 17 | / { |
18 | model = "FriendlyARM TINY4412 board based on Exynos4412"; | 18 | model = "FriendlyARM TINY4412 board based on Exynos4412"; |
19 | compatible = "friendlyarm,tiny4412", "samsung,exynos4412"; | 19 | compatible = "friendlyarm,tiny4412", "samsung,exynos4412", "samsung,exynos4"; |
20 | 20 | ||
21 | memory { | 21 | memory { |
22 | reg = <0x40000000 0x40000000>; | 22 | reg = <0x40000000 0x40000000>; |
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts index 4f851ccf40eb..c16b3159b813 100644 --- a/arch/arm/boot/dts/exynos4412-trats2.dts +++ b/arch/arm/boot/dts/exynos4412-trats2.dts | |||
@@ -17,7 +17,7 @@ | |||
17 | 17 | ||
18 | / { | 18 | / { |
19 | model = "Samsung Trats 2 based on Exynos4412"; | 19 | model = "Samsung Trats 2 based on Exynos4412"; |
20 | compatible = "samsung,trats2", "samsung,exynos4412"; | 20 | compatible = "samsung,trats2", "samsung,exynos4412", "samsung,exynos4"; |
21 | 21 | ||
22 | aliases { | 22 | aliases { |
23 | i2c8 = &i2c_ak8975; | 23 | i2c8 = &i2c_ak8975; |
@@ -106,6 +106,11 @@ | |||
106 | }; | 106 | }; |
107 | }; | 107 | }; |
108 | 108 | ||
109 | adc: adc@126C0000 { | ||
110 | vdd-supply = <&ldo3_reg>; | ||
111 | status = "okay"; | ||
112 | }; | ||
113 | |||
109 | i2c@13890000 { | 114 | i2c@13890000 { |
110 | samsung,i2c-sda-delay = <100>; | 115 | samsung,i2c-sda-delay = <100>; |
111 | samsung,i2c-slave-addr = <0x10>; | 116 | samsung,i2c-slave-addr = <0x10>; |
@@ -589,4 +594,20 @@ | |||
589 | }; | 594 | }; |
590 | }; | 595 | }; |
591 | }; | 596 | }; |
597 | |||
598 | thermistor-ap@0 { | ||
599 | compatible = "ntc,ncp15wb473"; | ||
600 | pullup-uv = <1800000>; /* VCC_1.8V_AP */ | ||
601 | pullup-ohm = <100000>; /* 100K */ | ||
602 | pulldown-ohm = <100000>; /* 100K */ | ||
603 | io-channels = <&adc 1>; /* AP temperature */ | ||
604 | }; | ||
605 | |||
606 | thermistor-battery@1 { | ||
607 | compatible = "ntc,ncp15wb473"; | ||
608 | pullup-uv = <1800000>; /* VCC_1.8V_AP */ | ||
609 | pullup-ohm = <100000>; /* 100K */ | ||
610 | pulldown-ohm = <100000>; /* 100K */ | ||
611 | io-channels = <&adc 2>; /* Battery temperature */ | ||
612 | }; | ||
592 | }; | 613 | }; |
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 87b339c739de..15d3c0ac2f5f 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi | |||
@@ -20,19 +20,13 @@ | |||
20 | #include "exynos4x12.dtsi" | 20 | #include "exynos4x12.dtsi" |
21 | 21 | ||
22 | / { | 22 | / { |
23 | compatible = "samsung,exynos4412"; | 23 | compatible = "samsung,exynos4412", "samsung,exynos4"; |
24 | 24 | ||
25 | gic: interrupt-controller@10490000 { | 25 | combiner: interrupt-controller@10440000 { |
26 | cpu-offset = <0x4000>; | ||
27 | }; | ||
28 | |||
29 | interrupt-controller@10440000 { | ||
30 | samsung,combiner-nr = <20>; | 26 | samsung,combiner-nr = <20>; |
31 | interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, | ||
32 | <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, | ||
33 | <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, | ||
34 | <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, | ||
35 | <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>; | ||
36 | }; | 27 | }; |
37 | 28 | ||
29 | gic: interrupt-controller@10490000 { | ||
30 | cpu-offset = <0x4000>; | ||
31 | }; | ||
38 | }; | 32 | }; |
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index e0eb6bb64c34..c4a9306f8529 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi | |||
@@ -31,6 +31,12 @@ | |||
31 | mshc0 = &mshc_0; | 31 | mshc0 = &mshc_0; |
32 | }; | 32 | }; |
33 | 33 | ||
34 | pmu { | ||
35 | compatible = "arm,cortex-a9-pmu"; | ||
36 | interrupt-parent = <&combiner>; | ||
37 | interrupts = <2 2>, <3 2>, <18 2>, <19 2>; | ||
38 | }; | ||
39 | |||
34 | pd_isp: isp-power-domain@10023CA0 { | 40 | pd_isp: isp-power-domain@10023CA0 { |
35 | compatible = "samsung,exynos4210-pd"; | 41 | compatible = "samsung,exynos4210-pd"; |
36 | reg = <0x10023CA0 0x20>; | 42 | reg = <0x10023CA0 0x20>; |
@@ -62,6 +68,14 @@ | |||
62 | }; | 68 | }; |
63 | }; | 69 | }; |
64 | 70 | ||
71 | combiner: interrupt-controller@10440000 { | ||
72 | interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, | ||
73 | <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, | ||
74 | <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, | ||
75 | <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, | ||
76 | <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>; | ||
77 | }; | ||
78 | |||
65 | pinctrl_0: pinctrl@11400000 { | 79 | pinctrl_0: pinctrl@11400000 { |
66 | compatible = "samsung,exynos4x12-pinctrl"; | 80 | compatible = "samsung,exynos4x12-pinctrl"; |
67 | reg = <0x11400000 0x1000>; | 81 | reg = <0x11400000 0x1000>; |
@@ -80,6 +94,18 @@ | |||
80 | }; | 94 | }; |
81 | }; | 95 | }; |
82 | 96 | ||
97 | adc: adc@126C0000 { | ||
98 | compatible = "samsung,exynos-adc-v1"; | ||
99 | reg = <0x126C0000 0x100>, <0x10020718 0x4>; | ||
100 | interrupt-parent = <&combiner>; | ||
101 | interrupts = <10 3>; | ||
102 | clocks = <&clock CLK_TSADC>; | ||
103 | clock-names = "adc"; | ||
104 | #io-channel-cells = <1>; | ||
105 | io-channel-ranges; | ||
106 | status = "disabled"; | ||
107 | }; | ||
108 | |||
83 | pinctrl_2: pinctrl@03860000 { | 109 | pinctrl_2: pinctrl@03860000 { |
84 | compatible = "samsung,exynos4x12-pinctrl"; | 110 | compatible = "samsung,exynos4x12-pinctrl"; |
85 | reg = <0x03860000 0x1000>; | 111 | reg = <0x03860000 0x1000>; |
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 38b96a4cba6d..090f9830b129 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts | |||
@@ -15,7 +15,7 @@ | |||
15 | 15 | ||
16 | / { | 16 | / { |
17 | model = "Insignal Arndale evaluation board based on EXYNOS5250"; | 17 | model = "Insignal Arndale evaluation board based on EXYNOS5250"; |
18 | compatible = "insignal,arndale", "samsung,exynos5250"; | 18 | compatible = "insignal,arndale", "samsung,exynos5250", "samsung,exynos5"; |
19 | 19 | ||
20 | memory { | 20 | memory { |
21 | reg = <0x40000000 0x80000000>; | 21 | reg = <0x40000000 0x80000000>; |
@@ -375,6 +375,27 @@ | |||
375 | }; | 375 | }; |
376 | }; | 376 | }; |
377 | 377 | ||
378 | i2c@121D0000 { | ||
379 | status = "okay"; | ||
380 | samsung,i2c-sda-delay = <100>; | ||
381 | samsung,i2c-max-bus-freq = <40000>; | ||
382 | samsung,i2c-slave-addr = <0x38>; | ||
383 | |||
384 | sata_phy_i2c:sata-phy@38 { | ||
385 | compatible = "samsung,exynos-sataphy-i2c"; | ||
386 | reg = <0x38>; | ||
387 | }; | ||
388 | }; | ||
389 | |||
390 | sata@122F0000 { | ||
391 | status = "okay"; | ||
392 | }; | ||
393 | |||
394 | sata-phy@12170000 { | ||
395 | status = "okay"; | ||
396 | samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>; | ||
397 | }; | ||
398 | |||
378 | mmc_0: mmc@12200000 { | 399 | mmc_0: mmc@12200000 { |
379 | status = "okay"; | 400 | status = "okay"; |
380 | num-slots = <1>; | 401 | num-slots = <1>; |
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index f76946e97e6a..a794a705d404 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts | |||
@@ -14,7 +14,7 @@ | |||
14 | 14 | ||
15 | / { | 15 | / { |
16 | model = "SAMSUNG SMDK5250 board based on EXYNOS5250"; | 16 | model = "SAMSUNG SMDK5250 board based on EXYNOS5250"; |
17 | compatible = "samsung,smdk5250", "samsung,exynos5250"; | 17 | compatible = "samsung,smdk5250", "samsung,exynos5250", "samsung,exynos5"; |
18 | 18 | ||
19 | aliases { | 19 | aliases { |
20 | }; | 20 | }; |
@@ -242,16 +242,12 @@ | |||
242 | samsung,i2c-slave-addr = <0x38>; | 242 | samsung,i2c-slave-addr = <0x38>; |
243 | status = "okay"; | 243 | status = "okay"; |
244 | 244 | ||
245 | sata-phy { | 245 | sata_phy_i2c:sata-phy@38 { |
246 | compatible = "samsung,sata-phy"; | 246 | compatible = "samsung,exynos-sataphy-i2c"; |
247 | reg = <0x38>; | 247 | reg = <0x38>; |
248 | }; | 248 | }; |
249 | }; | 249 | }; |
250 | 250 | ||
251 | sata@122F0000 { | ||
252 | samsung,sata-freq = <66>; | ||
253 | }; | ||
254 | |||
255 | i2c@12C80000 { | 251 | i2c@12C80000 { |
256 | samsung,i2c-sda-delay = <100>; | 252 | samsung,i2c-sda-delay = <100>; |
257 | samsung,i2c-max-bus-freq = <66000>; | 253 | samsung,i2c-max-bus-freq = <66000>; |
@@ -274,6 +270,15 @@ | |||
274 | }; | 270 | }; |
275 | }; | 271 | }; |
276 | 272 | ||
273 | sata@122F0000 { | ||
274 | status = "okay"; | ||
275 | }; | ||
276 | |||
277 | sata-phy@12170000 { | ||
278 | status = "okay"; | ||
279 | samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>; | ||
280 | }; | ||
281 | |||
277 | mmc@12200000 { | 282 | mmc@12200000 { |
278 | status = "okay"; | 283 | status = "okay"; |
279 | num-slots = <1>; | 284 | num-slots = <1>; |
@@ -310,10 +315,6 @@ | |||
310 | }; | 315 | }; |
311 | }; | 316 | }; |
312 | 317 | ||
313 | spi_0: spi@12d20000 { | ||
314 | status = "disabled"; | ||
315 | }; | ||
316 | |||
317 | spi_1: spi@12d30000 { | 318 | spi_1: spi@12d30000 { |
318 | status = "okay"; | 319 | status = "okay"; |
319 | 320 | ||
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts index b13bf499f5e2..1ce1088a00fb 100644 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ b/arch/arm/boot/dts/exynos5250-snow.dts | |||
@@ -14,7 +14,7 @@ | |||
14 | 14 | ||
15 | / { | 15 | / { |
16 | model = "Google Snow"; | 16 | model = "Google Snow"; |
17 | compatible = "google,snow", "samsung,exynos5250"; | 17 | compatible = "google,snow", "samsung,exynos5250", "samsung,exynos5"; |
18 | 18 | ||
19 | aliases { | 19 | aliases { |
20 | i2c104 = &i2c_104; | 20 | i2c104 = &i2c_104; |
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 987cfbe9634b..37423314a028 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi | |||
@@ -21,10 +21,10 @@ | |||
21 | #include "exynos5.dtsi" | 21 | #include "exynos5.dtsi" |
22 | #include "exynos5250-pinctrl.dtsi" | 22 | #include "exynos5250-pinctrl.dtsi" |
23 | 23 | ||
24 | #include <dt-bindings/clk/exynos-audss-clk.h> | 24 | #include <dt-bindings/clock/exynos-audss-clk.h> |
25 | 25 | ||
26 | / { | 26 | / { |
27 | compatible = "samsung,exynos5250"; | 27 | compatible = "samsung,exynos5250", "samsung,exynos5"; |
28 | 28 | ||
29 | aliases { | 29 | aliases { |
30 | spi0 = &spi_0; | 30 | spi0 = &spi_0; |
@@ -47,6 +47,7 @@ | |||
47 | i2c6 = &i2c_6; | 47 | i2c6 = &i2c_6; |
48 | i2c7 = &i2c_7; | 48 | i2c7 = &i2c_7; |
49 | i2c8 = &i2c_8; | 49 | i2c8 = &i2c_8; |
50 | i2c9 = &i2c_9; | ||
50 | pinctrl0 = &pinctrl_0; | 51 | pinctrl0 = &pinctrl_0; |
51 | pinctrl1 = &pinctrl_1; | 52 | pinctrl1 = &pinctrl_1; |
52 | pinctrl2 = &pinctrl_2; | 53 | pinctrl2 = &pinctrl_2; |
@@ -235,16 +236,25 @@ | |||
235 | }; | 236 | }; |
236 | 237 | ||
237 | sata@122F0000 { | 238 | sata@122F0000 { |
238 | compatible = "samsung,exynos5-sata-ahci"; | 239 | compatible = "snps,dwc-ahci"; |
240 | samsung,sata-freq = <66>; | ||
239 | reg = <0x122F0000 0x1ff>; | 241 | reg = <0x122F0000 0x1ff>; |
240 | interrupts = <0 115 0>; | 242 | interrupts = <0 115 0>; |
241 | clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>; | 243 | clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>; |
242 | clock-names = "sata", "sclk_sata"; | 244 | clock-names = "sata", "sclk_sata"; |
245 | phys = <&sata_phy>; | ||
246 | phy-names = "sata-phy"; | ||
247 | status = "disabled"; | ||
243 | }; | 248 | }; |
244 | 249 | ||
245 | sata-phy@12170000 { | 250 | sata_phy: sata-phy@12170000 { |
246 | compatible = "samsung,exynos5-sata-phy"; | 251 | compatible = "samsung,exynos5250-sata-phy"; |
247 | reg = <0x12170000 0x1ff>; | 252 | reg = <0x12170000 0x1ff>; |
253 | clocks = <&clock 287>; | ||
254 | clock-names = "sata_phyctrl"; | ||
255 | #phy-cells = <0>; | ||
256 | samsung,syscon-phandle = <&pmu_system_controller>; | ||
257 | status = "disabled"; | ||
248 | }; | 258 | }; |
249 | 259 | ||
250 | i2c_0: i2c@12C60000 { | 260 | i2c_0: i2c@12C60000 { |
@@ -362,7 +372,7 @@ | |||
362 | status = "disabled"; | 372 | status = "disabled"; |
363 | }; | 373 | }; |
364 | 374 | ||
365 | i2c@121D0000 { | 375 | i2c_9: i2c@121D0000 { |
366 | compatible = "samsung,exynos5-sata-phy-i2c"; | 376 | compatible = "samsung,exynos5-sata-phy-i2c"; |
367 | reg = <0x121D0000 0x100>; | 377 | reg = <0x121D0000 0x100>; |
368 | #address-cells = <1>; | 378 | #address-cells = <1>; |
@@ -718,4 +728,12 @@ | |||
718 | io-channel-ranges; | 728 | io-channel-ranges; |
719 | status = "disabled"; | 729 | status = "disabled"; |
720 | }; | 730 | }; |
731 | |||
732 | sss@10830000 { | ||
733 | compatible = "samsung,exynos4210-secss"; | ||
734 | reg = <0x10830000 0x10000>; | ||
735 | interrupts = <0 112 0>; | ||
736 | clocks = <&clock 348>; | ||
737 | clock-names = "secss"; | ||
738 | }; | ||
721 | }; | 739 | }; |
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index f509e8fc290f..80a3bf4c5986 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts | |||
@@ -16,7 +16,7 @@ | |||
16 | 16 | ||
17 | / { | 17 | / { |
18 | model = "Insignal Arndale Octa evaluation board based on EXYNOS5420"; | 18 | model = "Insignal Arndale Octa evaluation board based on EXYNOS5420"; |
19 | compatible = "insignal,arndale-octa", "samsung,exynos5420"; | 19 | compatible = "insignal,arndale-octa", "samsung,exynos5420", "samsung,exynos5"; |
20 | 20 | ||
21 | memory { | 21 | memory { |
22 | reg = <0x20000000 0x80000000>; | 22 | reg = <0x20000000 0x80000000>; |
@@ -113,6 +113,7 @@ | |||
113 | regulator-name = "PVDD_APIO_MMCON_1V8"; | 113 | regulator-name = "PVDD_APIO_MMCON_1V8"; |
114 | regulator-min-microvolt = <1800000>; | 114 | regulator-min-microvolt = <1800000>; |
115 | regulator-max-microvolt = <1800000>; | 115 | regulator-max-microvolt = <1800000>; |
116 | regulator-always-on; | ||
116 | }; | 117 | }; |
117 | 118 | ||
118 | ldo4_reg: LDO4 { | 119 | ldo4_reg: LDO4 { |
@@ -150,6 +151,7 @@ | |||
150 | regulator-name = "PVDD_USB_3V3"; | 151 | regulator-name = "PVDD_USB_3V3"; |
151 | regulator-min-microvolt = <3000000>; | 152 | regulator-min-microvolt = <3000000>; |
152 | regulator-max-microvolt = <3000000>; | 153 | regulator-max-microvolt = <3000000>; |
154 | regulator-always-on; | ||
153 | }; | 155 | }; |
154 | 156 | ||
155 | ldo10_reg: LDO10 { | 157 | ldo10_reg: LDO10 { |
@@ -218,6 +220,7 @@ | |||
218 | regulator-name = "PVDD_MIFS_1V1"; | 220 | regulator-name = "PVDD_MIFS_1V1"; |
219 | regulator-min-microvolt = <1200000>; | 221 | regulator-min-microvolt = <1200000>; |
220 | regulator-max-microvolt = <1200000>; | 222 | regulator-max-microvolt = <1200000>; |
223 | regulator-always-on; | ||
221 | }; | 224 | }; |
222 | 225 | ||
223 | ldo24_reg: LDO24 { | 226 | ldo24_reg: LDO24 { |
@@ -361,4 +364,16 @@ | |||
361 | gpio-key,wakeup; | 364 | gpio-key,wakeup; |
362 | }; | 365 | }; |
363 | }; | 366 | }; |
367 | |||
368 | amba { | ||
369 | mdma1: mdma@11C10000 { | ||
370 | /* | ||
371 | * MDMA1 can support both secure and non-secure | ||
372 | * AXI transactions. When this is enabled in the kernel | ||
373 | * for boards that run in secure mode, we are getting | ||
374 | * imprecise external aborts causing the kernel to oops. | ||
375 | */ | ||
376 | status = "disabled"; | ||
377 | }; | ||
378 | }; | ||
364 | }; | 379 | }; |
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index ae1ee0470fca..69104850eb5e 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts | |||
@@ -14,7 +14,7 @@ | |||
14 | 14 | ||
15 | / { | 15 | / { |
16 | model = "Samsung SMDK5420 board based on EXYNOS5420"; | 16 | model = "Samsung SMDK5420 board based on EXYNOS5420"; |
17 | compatible = "samsung,smdk5420", "samsung,exynos5420"; | 17 | compatible = "samsung,smdk5420", "samsung,exynos5420", "samsung,exynos5"; |
18 | 18 | ||
19 | memory { | 19 | memory { |
20 | reg = <0x20000000 0x80000000>; | 20 | reg = <0x20000000 0x80000000>; |
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index e3329afbd8c4..c3a9a66c5767 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi | |||
@@ -17,10 +17,10 @@ | |||
17 | #include "exynos5.dtsi" | 17 | #include "exynos5.dtsi" |
18 | #include "exynos5420-pinctrl.dtsi" | 18 | #include "exynos5420-pinctrl.dtsi" |
19 | 19 | ||
20 | #include <dt-bindings/clk/exynos-audss-clk.h> | 20 | #include <dt-bindings/clock/exynos-audss-clk.h> |
21 | 21 | ||
22 | / { | 22 | / { |
23 | compatible = "samsung,exynos5420"; | 23 | compatible = "samsung,exynos5420", "samsung,exynos5"; |
24 | 24 | ||
25 | aliases { | 25 | aliases { |
26 | mshc0 = &mmc_0; | 26 | mshc0 = &mmc_0; |
@@ -723,4 +723,13 @@ | |||
723 | clock-names = "watchdog"; | 723 | clock-names = "watchdog"; |
724 | samsung,syscon-phandle = <&pmu_system_controller>; | 724 | samsung,syscon-phandle = <&pmu_system_controller>; |
725 | }; | 725 | }; |
726 | |||
727 | sss@10830000 { | ||
728 | compatible = "samsung,exynos4210-secss"; | ||
729 | reg = <0x10830000 0x10000>; | ||
730 | interrupts = <0 112 0>; | ||
731 | clocks = <&clock 471>; | ||
732 | clock-names = "secss"; | ||
733 | samsung,power-domain = <&g2d_pd>; | ||
734 | }; | ||
726 | }; | 735 | }; |
diff --git a/arch/arm/boot/dts/exynos5440-sd5v1.dts b/arch/arm/boot/dts/exynos5440-sd5v1.dts index 777fb1c2c70f..268609a42b2c 100644 --- a/arch/arm/boot/dts/exynos5440-sd5v1.dts +++ b/arch/arm/boot/dts/exynos5440-sd5v1.dts | |||
@@ -14,7 +14,7 @@ | |||
14 | 14 | ||
15 | / { | 15 | / { |
16 | model = "SAMSUNG SD5v1 board based on EXYNOS5440"; | 16 | model = "SAMSUNG SD5v1 board based on EXYNOS5440"; |
17 | compatible = "samsung,sd5v1", "samsung,exynos5440"; | 17 | compatible = "samsung,sd5v1", "samsung,exynos5440", "samsung,exynos5"; |
18 | 18 | ||
19 | chosen { | 19 | chosen { |
20 | bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel earlyprintk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200"; | 20 | bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel earlyprintk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200"; |
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts index d58cb787061a..ff55dac6e219 100644 --- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts +++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts | |||
@@ -14,7 +14,7 @@ | |||
14 | 14 | ||
15 | / { | 15 | / { |
16 | model = "SAMSUNG SSDK5440 board based on EXYNOS5440"; | 16 | model = "SAMSUNG SSDK5440 board based on EXYNOS5440"; |
17 | compatible = "samsung,ssdk5440", "samsung,exynos5440"; | 17 | compatible = "samsung,ssdk5440", "samsung,exynos5440", "samsung,exynos5"; |
18 | 18 | ||
19 | chosen { | 19 | chosen { |
20 | bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel earlyprintk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200"; | 20 | bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel earlyprintk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200"; |
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi index 75c7b89cec2f..84f77c2fe4d4 100644 --- a/arch/arm/boot/dts/exynos5440.dtsi +++ b/arch/arm/boot/dts/exynos5440.dtsi | |||
@@ -13,7 +13,7 @@ | |||
13 | #include "skeleton.dtsi" | 13 | #include "skeleton.dtsi" |
14 | 14 | ||
15 | / { | 15 | / { |
16 | compatible = "samsung,exynos5440"; | 16 | compatible = "samsung,exynos5440", "samsung,exynos5"; |
17 | 17 | ||
18 | interrupt-parent = <&gic>; | 18 | interrupt-parent = <&gic>; |
19 | 19 | ||
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index 286a840e3dce..511180769af5 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi | |||
@@ -129,30 +129,28 @@ | |||
129 | } ; | 129 | } ; |
130 | 130 | ||
131 | slcr: slcr@f8000000 { | 131 | slcr: slcr@f8000000 { |
132 | compatible = "xlnx,zynq-slcr"; | 132 | #address-cells = <1>; |
133 | #size-cells = <1>; | ||
134 | compatible = "xlnx,zynq-slcr", "syscon"; | ||
133 | reg = <0xF8000000 0x1000>; | 135 | reg = <0xF8000000 0x1000>; |
134 | 136 | ranges; | |
135 | clocks { | 137 | clkc: clkc@100 { |
136 | #address-cells = <1>; | 138 | #clock-cells = <1>; |
137 | #size-cells = <0>; | 139 | compatible = "xlnx,ps7-clkc"; |
138 | 140 | ps-clk-frequency = <33333333>; | |
139 | clkc: clkc { | 141 | fclk-enable = <0>; |
140 | #clock-cells = <1>; | 142 | clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", |
141 | compatible = "xlnx,ps7-clkc"; | 143 | "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", |
142 | ps-clk-frequency = <33333333>; | 144 | "dci", "lqspi", "smc", "pcap", "gem0", "gem1", |
143 | fclk-enable = <0>; | 145 | "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", |
144 | clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", | 146 | "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", |
145 | "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", | 147 | "dma", "usb0_aper", "usb1_aper", "gem0_aper", |
146 | "dci", "lqspi", "smc", "pcap", "gem0", "gem1", | 148 | "gem1_aper", "sdio0_aper", "sdio1_aper", |
147 | "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", | 149 | "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", |
148 | "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", | 150 | "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", |
149 | "dma", "usb0_aper", "usb1_aper", "gem0_aper", | 151 | "gpio_aper", "lqspi_aper", "smc_aper", "swdt", |
150 | "gem1_aper", "sdio0_aper", "sdio1_aper", | 152 | "dbg_trc", "dbg_apb"; |
151 | "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", | 153 | reg = <0x100 0x100>; |
152 | "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", | ||
153 | "gpio_aper", "lqspi_aper", "smc_aper", "swdt", | ||
154 | "dbg_trc", "dbg_apb"; | ||
155 | }; | ||
156 | }; | 154 | }; |
157 | }; | 155 | }; |
158 | 156 | ||
diff --git a/arch/arm/include/debug/zynq.S b/arch/arm/include/debug/zynq.S index f9aa9740a73f..0b762fafa758 100644 --- a/arch/arm/include/debug/zynq.S +++ b/arch/arm/include/debug/zynq.S | |||
@@ -42,6 +42,9 @@ | |||
42 | .endm | 42 | .endm |
43 | 43 | ||
44 | .macro waituart,rd,rx | 44 | .macro waituart,rd,rx |
45 | 1001: ldr \rd, [\rx, #UART_SR_OFFSET] | ||
46 | tst \rd, #UART_SR_TXEMPTY | ||
47 | beq 1001b | ||
45 | .endm | 48 | .endm |
46 | 49 | ||
47 | .macro busyuart,rd,rx | 50 | .macro busyuart,rd,rx |
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 8d197dcdd2c0..fc8bf18e222d 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig | |||
@@ -24,7 +24,7 @@ config ARCH_EXYNOS4 | |||
24 | select HAVE_SMP | 24 | select HAVE_SMP |
25 | select MIGHT_HAVE_CACHE_L2X0 | 25 | select MIGHT_HAVE_CACHE_L2X0 |
26 | select PINCTRL | 26 | select PINCTRL |
27 | select PM_GENERIC_DOMAINS if PM | 27 | select PM_GENERIC_DOMAINS if PM_RUNTIME |
28 | select S5P_DEV_MFC | 28 | select S5P_DEV_MFC |
29 | help | 29 | help |
30 | Samsung EXYNOS4 SoCs based systems | 30 | Samsung EXYNOS4 SoCs based systems |
@@ -46,10 +46,8 @@ config CPU_EXYNOS4210 | |||
46 | default y | 46 | default y |
47 | depends on ARCH_EXYNOS4 | 47 | depends on ARCH_EXYNOS4 |
48 | select ARCH_HAS_BANDGAP | 48 | select ARCH_HAS_BANDGAP |
49 | select ARM_CPU_SUSPEND if PM | 49 | select ARM_CPU_SUSPEND if PM_SLEEP |
50 | select PINCTRL_EXYNOS | 50 | select PINCTRL_EXYNOS |
51 | select S5P_PM if PM | ||
52 | select S5P_SLEEP if PM | ||
53 | select SAMSUNG_DMADEV | 51 | select SAMSUNG_DMADEV |
54 | help | 52 | help |
55 | Enable EXYNOS4210 CPU support | 53 | Enable EXYNOS4210 CPU support |
@@ -60,8 +58,6 @@ config SOC_EXYNOS4212 | |||
60 | depends on ARCH_EXYNOS4 | 58 | depends on ARCH_EXYNOS4 |
61 | select ARCH_HAS_BANDGAP | 59 | select ARCH_HAS_BANDGAP |
62 | select PINCTRL_EXYNOS | 60 | select PINCTRL_EXYNOS |
63 | select S5P_PM if PM | ||
64 | select S5P_SLEEP if PM | ||
65 | select SAMSUNG_DMADEV | 61 | select SAMSUNG_DMADEV |
66 | help | 62 | help |
67 | Enable EXYNOS4212 SoC support | 63 | Enable EXYNOS4212 SoC support |
@@ -82,9 +78,7 @@ config SOC_EXYNOS5250 | |||
82 | depends on ARCH_EXYNOS5 | 78 | depends on ARCH_EXYNOS5 |
83 | select ARCH_HAS_BANDGAP | 79 | select ARCH_HAS_BANDGAP |
84 | select PINCTRL_EXYNOS | 80 | select PINCTRL_EXYNOS |
85 | select PM_GENERIC_DOMAINS if PM | 81 | select PM_GENERIC_DOMAINS if PM_RUNTIME |
86 | select S5P_PM if PM | ||
87 | select S5P_SLEEP if PM | ||
88 | select S5P_DEV_MFC | 82 | select S5P_DEV_MFC |
89 | select SAMSUNG_DMADEV | 83 | select SAMSUNG_DMADEV |
90 | help | 84 | help |
@@ -94,9 +88,7 @@ config SOC_EXYNOS5420 | |||
94 | bool "SAMSUNG EXYNOS5420" | 88 | bool "SAMSUNG EXYNOS5420" |
95 | default y | 89 | default y |
96 | depends on ARCH_EXYNOS5 | 90 | depends on ARCH_EXYNOS5 |
97 | select PM_GENERIC_DOMAINS if PM | 91 | select PM_GENERIC_DOMAINS if PM_RUNTIME |
98 | select S5P_PM if PM | ||
99 | select S5P_SLEEP if PM | ||
100 | help | 92 | help |
101 | Enable EXYNOS5420 SoC support | 93 | Enable EXYNOS5420 SoC support |
102 | 94 | ||
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index 8930b66b4abd..a656dbe3b78c 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile | |||
@@ -12,9 +12,9 @@ obj- := | |||
12 | 12 | ||
13 | # Core | 13 | # Core |
14 | 14 | ||
15 | obj-$(CONFIG_ARCH_EXYNOS) += common.o | 15 | obj-$(CONFIG_ARCH_EXYNOS) += exynos.o |
16 | 16 | ||
17 | obj-$(CONFIG_S5P_PM) += pm.o | 17 | obj-$(CONFIG_PM_SLEEP) += pm.o sleep.o |
18 | obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o | 18 | obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o |
19 | obj-$(CONFIG_CPU_IDLE) += cpuidle.o | 19 | obj-$(CONFIG_CPU_IDLE) += cpuidle.o |
20 | 20 | ||
@@ -29,8 +29,3 @@ obj-$(CONFIG_ARCH_EXYNOS) += firmware.o | |||
29 | 29 | ||
30 | plus_sec := $(call as-instr,.arch_extension sec,+sec) | 30 | plus_sec := $(call as-instr,.arch_extension sec,+sec) |
31 | AFLAGS_exynos-smc.o :=-Wa,-march=armv7-a$(plus_sec) | 31 | AFLAGS_exynos-smc.o :=-Wa,-march=armv7-a$(plus_sec) |
32 | |||
33 | # machine support | ||
34 | |||
35 | obj-$(CONFIG_ARCH_EXYNOS4) += mach-exynos4-dt.o | ||
36 | obj-$(CONFIG_ARCH_EXYNOS5) += mach-exynos5-dt.o | ||
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index f76967b1c551..9ef3f83efaff 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h | |||
@@ -19,14 +19,27 @@ void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1); | |||
19 | 19 | ||
20 | struct map_desc; | 20 | struct map_desc; |
21 | void exynos_init_io(void); | 21 | void exynos_init_io(void); |
22 | void exynos4_restart(enum reboot_mode mode, const char *cmd); | 22 | void exynos_restart(enum reboot_mode mode, const char *cmd); |
23 | void exynos5_restart(enum reboot_mode mode, const char *cmd); | ||
24 | void exynos_cpuidle_init(void); | 23 | void exynos_cpuidle_init(void); |
25 | void exynos_cpufreq_init(void); | 24 | void exynos_cpufreq_init(void); |
26 | void exynos_init_late(void); | 25 | void exynos_init_late(void); |
27 | 26 | ||
28 | void exynos_firmware_init(void); | 27 | void exynos_firmware_init(void); |
29 | 28 | ||
29 | #ifdef CONFIG_PINCTRL_EXYNOS | ||
30 | extern u32 exynos_get_eint_wake_mask(void); | ||
31 | #else | ||
32 | static inline u32 exynos_get_eint_wake_mask(void) { return 0xffffffff; } | ||
33 | #endif | ||
34 | |||
35 | #ifdef CONFIG_PM_SLEEP | ||
36 | extern void __init exynos_pm_init(void); | ||
37 | #else | ||
38 | static inline void exynos_pm_init(void) {} | ||
39 | #endif | ||
40 | |||
41 | extern void exynos_cpu_resume(void); | ||
42 | |||
30 | extern struct smp_operations exynos_smp_ops; | 43 | extern struct smp_operations exynos_smp_ops; |
31 | 44 | ||
32 | extern void exynos_cpu_die(unsigned int cpu); | 45 | extern void exynos_cpu_die(unsigned int cpu); |
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c index 93d2decc112d..c57cae0e8779 100644 --- a/arch/arm/mach-exynos/cpuidle.c +++ b/arch/arm/mach-exynos/cpuidle.c | |||
@@ -27,7 +27,6 @@ | |||
27 | #include <plat/cpu.h> | 27 | #include <plat/cpu.h> |
28 | #include <plat/pm.h> | 28 | #include <plat/pm.h> |
29 | 29 | ||
30 | #include <mach/pm-core.h> | ||
31 | #include <mach/map.h> | 30 | #include <mach/map.h> |
32 | 31 | ||
33 | #include "common.h" | 32 | #include "common.h" |
@@ -128,7 +127,7 @@ static int exynos4_enter_core0_aftr(struct cpuidle_device *dev, | |||
128 | /* Set value of power down register for aftr mode */ | 127 | /* Set value of power down register for aftr mode */ |
129 | exynos_sys_powerdown_conf(SYS_AFTR); | 128 | exynos_sys_powerdown_conf(SYS_AFTR); |
130 | 129 | ||
131 | __raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR); | 130 | __raw_writel(virt_to_phys(exynos_cpu_resume), REG_DIRECTGO_ADDR); |
132 | __raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG); | 131 | __raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG); |
133 | 132 | ||
134 | save_cpu_arch_register(); | 133 | save_cpu_arch_register(); |
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/exynos.c index b2f9bb071557..b32a907d021d 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/exynos.c | |||
@@ -1,105 +1,40 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. | 2 | * SAMSUNG EXYNOS Flattened Device Tree enabled machine |
3 | * http://www.samsung.com | ||
4 | * | 3 | * |
5 | * Common Codes for EXYNOS | 4 | * Copyright (c) 2010-2014 Samsung Electronics Co., Ltd. |
5 | * http://www.samsung.com | ||
6 | * | 6 | * |
7 | * This program is free software; you can redistribute it and/or modify | 7 | * This program is free software; you can redistribute it and/or modify |
8 | * it under the terms of the GNU General Public License version 2 as | 8 | * it under the terms of the GNU General Public License version 2 as |
9 | * published by the Free Software Foundation. | 9 | * published by the Free Software Foundation. |
10 | */ | 10 | */ |
11 | 11 | ||
12 | #include <linux/kernel.h> | 12 | #include <linux/init.h> |
13 | #include <linux/bitops.h> | ||
14 | #include <linux/interrupt.h> | ||
15 | #include <linux/irq.h> | ||
16 | #include <linux/irqchip.h> | ||
17 | #include <linux/io.h> | 13 | #include <linux/io.h> |
18 | #include <linux/device.h> | 14 | #include <linux/kernel.h> |
19 | #include <linux/gpio.h> | ||
20 | #include <clocksource/samsung_pwm.h> | ||
21 | #include <linux/sched.h> | ||
22 | #include <linux/serial_core.h> | ||
23 | #include <linux/serial_s3c.h> | 15 | #include <linux/serial_s3c.h> |
24 | #include <linux/of.h> | 16 | #include <linux/of.h> |
25 | #include <linux/of_fdt.h> | ||
26 | #include <linux/of_irq.h> | ||
27 | #include <linux/pm_domain.h> | ||
28 | #include <linux/export.h> | ||
29 | #include <linux/irqdomain.h> | ||
30 | #include <linux/of_address.h> | 17 | #include <linux/of_address.h> |
31 | #include <linux/irqchip/arm-gic.h> | 18 | #include <linux/of_fdt.h> |
32 | #include <linux/irqchip/chained_irq.h> | 19 | #include <linux/of_platform.h> |
33 | #include <linux/platform_device.h> | 20 | #include <linux/platform_device.h> |
21 | #include <linux/pm_domain.h> | ||
34 | 22 | ||
35 | #include <asm/proc-fns.h> | 23 | #include <asm/cacheflush.h> |
36 | #include <asm/exception.h> | ||
37 | #include <asm/hardware/cache-l2x0.h> | 24 | #include <asm/hardware/cache-l2x0.h> |
25 | #include <asm/mach/arch.h> | ||
38 | #include <asm/mach/map.h> | 26 | #include <asm/mach/map.h> |
39 | #include <asm/mach/irq.h> | 27 | #include <asm/memory.h> |
40 | #include <asm/cacheflush.h> | ||
41 | 28 | ||
42 | #include <plat/cpu.h> | 29 | #include <plat/cpu.h> |
43 | #include <plat/pm.h> | ||
44 | 30 | ||
45 | #include "common.h" | 31 | #include "common.h" |
32 | #include "mfc.h" | ||
46 | #include "regs-pmu.h" | 33 | #include "regs-pmu.h" |
47 | 34 | ||
48 | #define L2_AUX_VAL 0x7C470001 | 35 | #define L2_AUX_VAL 0x7C470001 |
49 | #define L2_AUX_MASK 0xC200ffff | 36 | #define L2_AUX_MASK 0xC200ffff |
50 | 37 | ||
51 | static const char name_exynos4210[] = "EXYNOS4210"; | ||
52 | static const char name_exynos4212[] = "EXYNOS4212"; | ||
53 | static const char name_exynos4412[] = "EXYNOS4412"; | ||
54 | static const char name_exynos5250[] = "EXYNOS5250"; | ||
55 | static const char name_exynos5420[] = "EXYNOS5420"; | ||
56 | static const char name_exynos5440[] = "EXYNOS5440"; | ||
57 | |||
58 | static void exynos4_map_io(void); | ||
59 | static void exynos5_map_io(void); | ||
60 | static int exynos_init(void); | ||
61 | |||
62 | static struct cpu_table cpu_ids[] __initdata = { | ||
63 | { | ||
64 | .idcode = EXYNOS4210_CPU_ID, | ||
65 | .idmask = EXYNOS4_CPU_MASK, | ||
66 | .map_io = exynos4_map_io, | ||
67 | .init = exynos_init, | ||
68 | .name = name_exynos4210, | ||
69 | }, { | ||
70 | .idcode = EXYNOS4212_CPU_ID, | ||
71 | .idmask = EXYNOS4_CPU_MASK, | ||
72 | .map_io = exynos4_map_io, | ||
73 | .init = exynos_init, | ||
74 | .name = name_exynos4212, | ||
75 | }, { | ||
76 | .idcode = EXYNOS4412_CPU_ID, | ||
77 | .idmask = EXYNOS4_CPU_MASK, | ||
78 | .map_io = exynos4_map_io, | ||
79 | .init = exynos_init, | ||
80 | .name = name_exynos4412, | ||
81 | }, { | ||
82 | .idcode = EXYNOS5250_SOC_ID, | ||
83 | .idmask = EXYNOS5_SOC_MASK, | ||
84 | .map_io = exynos5_map_io, | ||
85 | .init = exynos_init, | ||
86 | .name = name_exynos5250, | ||
87 | }, { | ||
88 | .idcode = EXYNOS5420_SOC_ID, | ||
89 | .idmask = EXYNOS5_SOC_MASK, | ||
90 | .map_io = exynos5_map_io, | ||
91 | .init = exynos_init, | ||
92 | .name = name_exynos5420, | ||
93 | }, { | ||
94 | .idcode = EXYNOS5440_SOC_ID, | ||
95 | .idmask = EXYNOS5_SOC_MASK, | ||
96 | .init = exynos_init, | ||
97 | .name = name_exynos5440, | ||
98 | }, | ||
99 | }; | ||
100 | |||
101 | /* Initial IO mappings */ | ||
102 | |||
103 | static struct map_desc exynos4_iodesc[] __initdata = { | 38 | static struct map_desc exynos4_iodesc[] __initdata = { |
104 | { | 39 | { |
105 | .virtual = (unsigned long)S3C_VA_SYS, | 40 | .virtual = (unsigned long)S3C_VA_SYS, |
@@ -263,19 +198,11 @@ static struct map_desc exynos5_iodesc[] __initdata = { | |||
263 | }, | 198 | }, |
264 | }; | 199 | }; |
265 | 200 | ||
266 | void exynos4_restart(enum reboot_mode mode, const char *cmd) | 201 | void exynos_restart(enum reboot_mode mode, const char *cmd) |
267 | { | ||
268 | __raw_writel(0x1, S5P_SWRESET); | ||
269 | } | ||
270 | |||
271 | void exynos5_restart(enum reboot_mode mode, const char *cmd) | ||
272 | { | 202 | { |
273 | struct device_node *np; | 203 | struct device_node *np; |
274 | u32 val; | 204 | u32 val = 0x1; |
275 | void __iomem *addr; | 205 | void __iomem *addr = EXYNOS_SWRESET; |
276 | |||
277 | val = 0x1; | ||
278 | addr = EXYNOS_SWRESET; | ||
279 | 206 | ||
280 | if (of_machine_is_compatible("samsung,exynos5440")) { | 207 | if (of_machine_is_compatible("samsung,exynos5440")) { |
281 | u32 status; | 208 | u32 status; |
@@ -315,6 +242,7 @@ void __init exynos_init_late(void) | |||
315 | return; | 242 | return; |
316 | 243 | ||
317 | pm_genpd_poweroff_unused(); | 244 | pm_genpd_poweroff_unused(); |
245 | exynos_pm_init(); | ||
318 | } | 246 | } |
319 | 247 | ||
320 | static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname, | 248 | static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname, |
@@ -345,6 +273,28 @@ static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname, | |||
345 | * | 273 | * |
346 | * register the standard cpu IO areas | 274 | * register the standard cpu IO areas |
347 | */ | 275 | */ |
276 | static void __init exynos_map_io(void) | ||
277 | { | ||
278 | if (soc_is_exynos4()) | ||
279 | iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc)); | ||
280 | |||
281 | if (soc_is_exynos5()) | ||
282 | iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc)); | ||
283 | |||
284 | if (soc_is_exynos4210()) { | ||
285 | if (samsung_rev() == EXYNOS4210_REV_0) | ||
286 | iotable_init(exynos4_iodesc0, | ||
287 | ARRAY_SIZE(exynos4_iodesc0)); | ||
288 | else | ||
289 | iotable_init(exynos4_iodesc1, | ||
290 | ARRAY_SIZE(exynos4_iodesc1)); | ||
291 | iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc)); | ||
292 | } | ||
293 | if (soc_is_exynos4212() || soc_is_exynos4412()) | ||
294 | iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc)); | ||
295 | if (soc_is_exynos5250()) | ||
296 | iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc)); | ||
297 | } | ||
348 | 298 | ||
349 | void __init exynos_init_io(void) | 299 | void __init exynos_init_io(void) |
350 | { | 300 | { |
@@ -355,30 +305,7 @@ void __init exynos_init_io(void) | |||
355 | /* detect cpu id and rev. */ | 305 | /* detect cpu id and rev. */ |
356 | s5p_init_cpu(S5P_VA_CHIPID); | 306 | s5p_init_cpu(S5P_VA_CHIPID); |
357 | 307 | ||
358 | s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); | 308 | exynos_map_io(); |
359 | } | ||
360 | |||
361 | static void __init exynos4_map_io(void) | ||
362 | { | ||
363 | iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc)); | ||
364 | |||
365 | if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0) | ||
366 | iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0)); | ||
367 | else | ||
368 | iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1)); | ||
369 | |||
370 | if (soc_is_exynos4210()) | ||
371 | iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc)); | ||
372 | if (soc_is_exynos4212() || soc_is_exynos4412()) | ||
373 | iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc)); | ||
374 | } | ||
375 | |||
376 | static void __init exynos5_map_io(void) | ||
377 | { | ||
378 | iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc)); | ||
379 | |||
380 | if (soc_is_exynos5250()) | ||
381 | iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc)); | ||
382 | } | 309 | } |
383 | 310 | ||
384 | struct bus_type exynos_subsys = { | 311 | struct bus_type exynos_subsys = { |
@@ -386,10 +313,6 @@ struct bus_type exynos_subsys = { | |||
386 | .dev_name = "exynos-core", | 313 | .dev_name = "exynos-core", |
387 | }; | 314 | }; |
388 | 315 | ||
389 | static struct device exynos4_dev = { | ||
390 | .bus = &exynos_subsys, | ||
391 | }; | ||
392 | |||
393 | static int __init exynos_core_init(void) | 316 | static int __init exynos_core_init(void) |
394 | { | 317 | { |
395 | return subsys_system_register(&exynos_subsys, NULL); | 318 | return subsys_system_register(&exynos_subsys, NULL); |
@@ -412,9 +335,77 @@ static int __init exynos4_l2x0_cache_init(void) | |||
412 | } | 335 | } |
413 | early_initcall(exynos4_l2x0_cache_init); | 336 | early_initcall(exynos4_l2x0_cache_init); |
414 | 337 | ||
415 | static int __init exynos_init(void) | 338 | static void __init exynos_dt_machine_init(void) |
416 | { | 339 | { |
417 | printk(KERN_INFO "EXYNOS: Initializing architecture\n"); | 340 | struct device_node *i2c_np; |
341 | const char *i2c_compat = "samsung,s3c2440-i2c"; | ||
342 | unsigned int tmp; | ||
343 | int id; | ||
344 | |||
345 | /* | ||
346 | * Exynos5's legacy i2c controller and new high speed i2c | ||
347 | * controller have muxed interrupt sources. By default the | ||
348 | * interrupts for 4-channel HS-I2C controller are enabled. | ||
349 | * If node for first four channels of legacy i2c controller | ||
350 | * are available then re-configure the interrupts via the | ||
351 | * system register. | ||
352 | */ | ||
353 | if (soc_is_exynos5()) { | ||
354 | for_each_compatible_node(i2c_np, NULL, i2c_compat) { | ||
355 | if (of_device_is_available(i2c_np)) { | ||
356 | id = of_alias_get_id(i2c_np, "i2c"); | ||
357 | if (id < 4) { | ||
358 | tmp = readl(EXYNOS5_SYS_I2C_CFG); | ||
359 | writel(tmp & ~(0x1 << id), | ||
360 | EXYNOS5_SYS_I2C_CFG); | ||
361 | } | ||
362 | } | ||
363 | } | ||
364 | } | ||
418 | 365 | ||
419 | return device_register(&exynos4_dev); | 366 | exynos_cpuidle_init(); |
367 | exynos_cpufreq_init(); | ||
368 | |||
369 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); | ||
420 | } | 370 | } |
371 | |||
372 | static char const *exynos_dt_compat[] __initconst = { | ||
373 | "samsung,exynos4", | ||
374 | "samsung,exynos4210", | ||
375 | "samsung,exynos4212", | ||
376 | "samsung,exynos4412", | ||
377 | "samsung,exynos5", | ||
378 | "samsung,exynos5250", | ||
379 | "samsung,exynos5420", | ||
380 | "samsung,exynos5440", | ||
381 | NULL | ||
382 | }; | ||
383 | |||
384 | static void __init exynos_reserve(void) | ||
385 | { | ||
386 | #ifdef CONFIG_S5P_DEV_MFC | ||
387 | int i; | ||
388 | char *mfc_mem[] = { | ||
389 | "samsung,mfc-v5", | ||
390 | "samsung,mfc-v6", | ||
391 | "samsung,mfc-v7", | ||
392 | }; | ||
393 | |||
394 | for (i = 0; i < ARRAY_SIZE(mfc_mem); i++) | ||
395 | if (of_scan_flat_dt(s5p_fdt_alloc_mfc_mem, mfc_mem[i])) | ||
396 | break; | ||
397 | #endif | ||
398 | } | ||
399 | |||
400 | DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)") | ||
401 | /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */ | ||
402 | /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ | ||
403 | .smp = smp_ops(exynos_smp_ops), | ||
404 | .map_io = exynos_init_io, | ||
405 | .init_early = exynos_firmware_init, | ||
406 | .init_machine = exynos_dt_machine_init, | ||
407 | .init_late = exynos_init_late, | ||
408 | .dt_compat = exynos_dt_compat, | ||
409 | .restart = exynos_restart, | ||
410 | .reserve = exynos_reserve, | ||
411 | MACHINE_END | ||
diff --git a/arch/arm/mach-exynos/include/mach/hardware.h b/arch/arm/mach-exynos/include/mach/hardware.h deleted file mode 100644 index 5109eb232f23..000000000000 --- a/arch/arm/mach-exynos/include/mach/hardware.h +++ /dev/null | |||
@@ -1,18 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-exynos4/include/mach/hardware.h | ||
2 | * | ||
3 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * EXYNOS4 - Hardware support | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_HARDWARE_H | ||
14 | #define __ASM_ARCH_HARDWARE_H __FILE__ | ||
15 | |||
16 | /* currently nothing here, placeholder */ | ||
17 | |||
18 | #endif /* __ASM_ARCH_HARDWARE_H */ | ||
diff --git a/arch/arm/mach-exynos/include/mach/pm-core.h b/arch/arm/mach-exynos/include/mach/pm-core.h deleted file mode 100644 index dc0697c2fa92..000000000000 --- a/arch/arm/mach-exynos/include/mach/pm-core.h +++ /dev/null | |||
@@ -1,75 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-exynos4/include/mach/pm-core.h | ||
2 | * | ||
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * Based on arch/arm/mach-s3c2410/include/mach/pm-core.h, | ||
7 | * Copyright 2008 Simtec Electronics | ||
8 | * Ben Dooks <ben@simtec.co.uk> | ||
9 | * http://armlinux.simtec.co.uk/ | ||
10 | * | ||
11 | * EXYNOS4210 - PM core support for arch/arm/plat-s5p/pm.c | ||
12 | * | ||
13 | * This program is free software; you can redistribute it and/or modify | ||
14 | * it under the terms of the GNU General Public License version 2 as | ||
15 | * published by the Free Software Foundation. | ||
16 | */ | ||
17 | |||
18 | #ifndef __ASM_ARCH_PM_CORE_H | ||
19 | #define __ASM_ARCH_PM_CORE_H __FILE__ | ||
20 | |||
21 | #include <linux/of.h> | ||
22 | #include <mach/map.h> | ||
23 | |||
24 | #define S5P_EINT_WAKEUP_MASK (S5P_VA_PMU + 0x0604) | ||
25 | #define S5P_WAKEUP_MASK (S5P_VA_PMU + 0x0608) | ||
26 | |||
27 | #ifdef CONFIG_PINCTRL_EXYNOS | ||
28 | extern u32 exynos_get_eint_wake_mask(void); | ||
29 | #else | ||
30 | static inline u32 exynos_get_eint_wake_mask(void) { return 0xffffffff; } | ||
31 | #endif | ||
32 | |||
33 | static inline void s3c_pm_debug_init_uart(void) | ||
34 | { | ||
35 | /* nothing here yet */ | ||
36 | } | ||
37 | |||
38 | static inline void s3c_pm_arch_prepare_irqs(void) | ||
39 | { | ||
40 | __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK); | ||
41 | __raw_writel(s3c_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK); | ||
42 | } | ||
43 | |||
44 | static inline void s3c_pm_arch_stop_clocks(void) | ||
45 | { | ||
46 | /* nothing here yet */ | ||
47 | } | ||
48 | |||
49 | static inline void s3c_pm_arch_show_resume_irqs(void) | ||
50 | { | ||
51 | /* nothing here yet */ | ||
52 | } | ||
53 | |||
54 | static inline void s3c_pm_arch_update_uart(void __iomem *regs, | ||
55 | struct pm_uart_save *save) | ||
56 | { | ||
57 | /* nothing here yet */ | ||
58 | } | ||
59 | |||
60 | static inline void s3c_pm_restored_gpios(void) | ||
61 | { | ||
62 | /* nothing here yet */ | ||
63 | } | ||
64 | |||
65 | static inline void samsung_pm_saved_gpios(void) | ||
66 | { | ||
67 | /* nothing here yet */ | ||
68 | } | ||
69 | |||
70 | /* Compatibility definitions to make plat-samsung/pm.c compile */ | ||
71 | #define IRQ_EINT_BIT(x) 1 | ||
72 | #define s3c_irqwake_intallow 0 | ||
73 | #define s3c_irqwake_eintallow 0 | ||
74 | |||
75 | #endif /* __ASM_ARCH_PM_CORE_H */ | ||
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c deleted file mode 100644 index d3e54b7644d7..000000000000 --- a/arch/arm/mach-exynos/mach-exynos4-dt.c +++ /dev/null | |||
@@ -1,59 +0,0 @@ | |||
1 | /* | ||
2 | * Samsung's EXYNOS4 flattened device tree enabled machine | ||
3 | * | ||
4 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. | ||
5 | * http://www.samsung.com | ||
6 | * Copyright (c) 2010-2011 Linaro Ltd. | ||
7 | * www.linaro.org | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #include <linux/of_platform.h> | ||
15 | #include <linux/of_fdt.h> | ||
16 | |||
17 | #include <asm/mach/arch.h> | ||
18 | #include <plat/mfc.h> | ||
19 | |||
20 | #include "common.h" | ||
21 | |||
22 | static void __init exynos4_dt_machine_init(void) | ||
23 | { | ||
24 | exynos_cpuidle_init(); | ||
25 | exynos_cpufreq_init(); | ||
26 | |||
27 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); | ||
28 | } | ||
29 | |||
30 | static char const *exynos4_dt_compat[] __initdata = { | ||
31 | "samsung,exynos4210", | ||
32 | "samsung,exynos4212", | ||
33 | "samsung,exynos4412", | ||
34 | NULL | ||
35 | }; | ||
36 | |||
37 | static void __init exynos4_reserve(void) | ||
38 | { | ||
39 | #ifdef CONFIG_S5P_DEV_MFC | ||
40 | struct s5p_mfc_dt_meminfo mfc_mem; | ||
41 | |||
42 | /* Reserve memory for MFC only if it's available */ | ||
43 | mfc_mem.compatible = "samsung,mfc-v5"; | ||
44 | if (of_scan_flat_dt(s5p_fdt_find_mfc_mem, &mfc_mem)) | ||
45 | s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize, mfc_mem.loff, | ||
46 | mfc_mem.lsize); | ||
47 | #endif | ||
48 | } | ||
49 | DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)") | ||
50 | /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */ | ||
51 | .smp = smp_ops(exynos_smp_ops), | ||
52 | .map_io = exynos_init_io, | ||
53 | .init_early = exynos_firmware_init, | ||
54 | .init_machine = exynos4_dt_machine_init, | ||
55 | .init_late = exynos_init_late, | ||
56 | .dt_compat = exynos4_dt_compat, | ||
57 | .restart = exynos4_restart, | ||
58 | .reserve = exynos4_reserve, | ||
59 | MACHINE_END | ||
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c deleted file mode 100644 index 37ea261f0f6c..000000000000 --- a/arch/arm/mach-exynos/mach-exynos5-dt.c +++ /dev/null | |||
@@ -1,81 +0,0 @@ | |||
1 | /* | ||
2 | * SAMSUNG EXYNOS5250 Flattened Device Tree enabled machine | ||
3 | * | ||
4 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | ||
5 | * http://www.samsung.com | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | */ | ||
11 | |||
12 | #include <linux/of_platform.h> | ||
13 | #include <linux/of_fdt.h> | ||
14 | #include <linux/io.h> | ||
15 | |||
16 | #include <asm/mach/arch.h> | ||
17 | #include <plat/mfc.h> | ||
18 | |||
19 | #include "common.h" | ||
20 | #include "regs-pmu.h" | ||
21 | |||
22 | static void __init exynos5_dt_machine_init(void) | ||
23 | { | ||
24 | struct device_node *i2c_np; | ||
25 | const char *i2c_compat = "samsung,s3c2440-i2c"; | ||
26 | unsigned int tmp; | ||
27 | |||
28 | /* | ||
29 | * Exynos5's legacy i2c controller and new high speed i2c | ||
30 | * controller have muxed interrupt sources. By default the | ||
31 | * interrupts for 4-channel HS-I2C controller are enabled. | ||
32 | * If node for first four channels of legacy i2c controller | ||
33 | * are available then re-configure the interrupts via the | ||
34 | * system register. | ||
35 | */ | ||
36 | for_each_compatible_node(i2c_np, NULL, i2c_compat) { | ||
37 | if (of_device_is_available(i2c_np)) { | ||
38 | if (of_alias_get_id(i2c_np, "i2c") < 4) { | ||
39 | tmp = readl(EXYNOS5_SYS_I2C_CFG); | ||
40 | writel(tmp & ~(0x1 << of_alias_get_id(i2c_np, "i2c")), | ||
41 | EXYNOS5_SYS_I2C_CFG); | ||
42 | } | ||
43 | } | ||
44 | } | ||
45 | |||
46 | exynos_cpuidle_init(); | ||
47 | exynos_cpufreq_init(); | ||
48 | |||
49 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); | ||
50 | } | ||
51 | |||
52 | static char const *exynos5_dt_compat[] __initdata = { | ||
53 | "samsung,exynos5250", | ||
54 | "samsung,exynos5420", | ||
55 | "samsung,exynos5440", | ||
56 | NULL | ||
57 | }; | ||
58 | |||
59 | static void __init exynos5_reserve(void) | ||
60 | { | ||
61 | #ifdef CONFIG_S5P_DEV_MFC | ||
62 | struct s5p_mfc_dt_meminfo mfc_mem; | ||
63 | |||
64 | /* Reserve memory for MFC only if it's available */ | ||
65 | mfc_mem.compatible = "samsung,mfc-v6"; | ||
66 | if (of_scan_flat_dt(s5p_fdt_find_mfc_mem, &mfc_mem)) | ||
67 | s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize, mfc_mem.loff, | ||
68 | mfc_mem.lsize); | ||
69 | #endif | ||
70 | } | ||
71 | |||
72 | DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)") | ||
73 | /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ | ||
74 | .smp = smp_ops(exynos_smp_ops), | ||
75 | .map_io = exynos_init_io, | ||
76 | .init_machine = exynos5_dt_machine_init, | ||
77 | .init_late = exynos_init_late, | ||
78 | .dt_compat = exynos5_dt_compat, | ||
79 | .restart = exynos5_restart, | ||
80 | .reserve = exynos5_reserve, | ||
81 | MACHINE_END | ||
diff --git a/arch/arm/mach-exynos/mfc.h b/arch/arm/mach-exynos/mfc.h new file mode 100644 index 000000000000..dec93cd5b3c6 --- /dev/null +++ b/arch/arm/mach-exynos/mfc.h | |||
@@ -0,0 +1,16 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2013 Samsung Electronics Co.Ltd | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms of the GNU General Public License as published by the | ||
6 | * Free Software Foundation; either version 2 of the License, or (at your | ||
7 | * option) any later version. | ||
8 | */ | ||
9 | |||
10 | #ifndef __MACH_EXYNOS_MFC_H | ||
11 | #define __MACH_EXYNOS_MFC_H __FILE__ | ||
12 | |||
13 | int __init s5p_fdt_alloc_mfc_mem(unsigned long node, const char *uname, | ||
14 | int depth, void *data); | ||
15 | |||
16 | #endif /* __MACH_EXYNOS_MFC_H */ | ||
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index 8ea02f63fed9..03e5e9f94705 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c | |||
@@ -26,8 +26,6 @@ | |||
26 | #include <asm/smp_scu.h> | 26 | #include <asm/smp_scu.h> |
27 | #include <asm/firmware.h> | 27 | #include <asm/firmware.h> |
28 | 28 | ||
29 | #include <mach/hardware.h> | ||
30 | |||
31 | #include <plat/cpu.h> | 29 | #include <plat/cpu.h> |
32 | 30 | ||
33 | #include "common.h" | 31 | #include "common.h" |
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index ba18214c9aca..15af0ceb0a66 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c | |||
@@ -17,24 +17,35 @@ | |||
17 | #include <linux/suspend.h> | 17 | #include <linux/suspend.h> |
18 | #include <linux/syscore_ops.h> | 18 | #include <linux/syscore_ops.h> |
19 | #include <linux/io.h> | 19 | #include <linux/io.h> |
20 | #include <linux/irqchip/arm-gic.h> | ||
20 | #include <linux/err.h> | 21 | #include <linux/err.h> |
21 | #include <linux/clk.h> | 22 | #include <linux/clk.h> |
22 | 23 | ||
23 | #include <asm/cacheflush.h> | 24 | #include <asm/cacheflush.h> |
24 | #include <asm/hardware/cache-l2x0.h> | 25 | #include <asm/hardware/cache-l2x0.h> |
25 | #include <asm/smp_scu.h> | 26 | #include <asm/smp_scu.h> |
27 | #include <asm/suspend.h> | ||
26 | 28 | ||
27 | #include <plat/cpu.h> | 29 | #include <plat/cpu.h> |
28 | #include <plat/pm.h> | 30 | #include <plat/pm-common.h> |
29 | #include <plat/pll.h> | 31 | #include <plat/pll.h> |
30 | #include <plat/regs-srom.h> | 32 | #include <plat/regs-srom.h> |
31 | 33 | ||
32 | #include <mach/map.h> | 34 | #include <mach/map.h> |
33 | #include <mach/pm-core.h> | ||
34 | 35 | ||
35 | #include "common.h" | 36 | #include "common.h" |
36 | #include "regs-pmu.h" | 37 | #include "regs-pmu.h" |
37 | 38 | ||
39 | /** | ||
40 | * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping | ||
41 | * @hwirq: Hardware IRQ signal of the GIC | ||
42 | * @mask: Mask in PMU wake-up mask register | ||
43 | */ | ||
44 | struct exynos_wkup_irq { | ||
45 | unsigned int hwirq; | ||
46 | u32 mask; | ||
47 | }; | ||
48 | |||
38 | static struct sleep_save exynos5_sys_save[] = { | 49 | static struct sleep_save exynos5_sys_save[] = { |
39 | SAVE_ITEM(EXYNOS5_SYS_I2C_CFG), | 50 | SAVE_ITEM(EXYNOS5_SYS_I2C_CFG), |
40 | }; | 51 | }; |
@@ -48,6 +59,46 @@ static struct sleep_save exynos_core_save[] = { | |||
48 | SAVE_ITEM(S5P_SROM_BC3), | 59 | SAVE_ITEM(S5P_SROM_BC3), |
49 | }; | 60 | }; |
50 | 61 | ||
62 | /* | ||
63 | * GIC wake-up support | ||
64 | */ | ||
65 | |||
66 | static u32 exynos_irqwake_intmask = 0xffffffff; | ||
67 | |||
68 | static const struct exynos_wkup_irq exynos4_wkup_irq[] = { | ||
69 | { 76, BIT(1) }, /* RTC alarm */ | ||
70 | { 77, BIT(2) }, /* RTC tick */ | ||
71 | { /* sentinel */ }, | ||
72 | }; | ||
73 | |||
74 | static const struct exynos_wkup_irq exynos5250_wkup_irq[] = { | ||
75 | { 75, BIT(1) }, /* RTC alarm */ | ||
76 | { 76, BIT(2) }, /* RTC tick */ | ||
77 | { /* sentinel */ }, | ||
78 | }; | ||
79 | |||
80 | static int exynos_irq_set_wake(struct irq_data *data, unsigned int state) | ||
81 | { | ||
82 | const struct exynos_wkup_irq *wkup_irq; | ||
83 | |||
84 | if (soc_is_exynos5250()) | ||
85 | wkup_irq = exynos5250_wkup_irq; | ||
86 | else | ||
87 | wkup_irq = exynos4_wkup_irq; | ||
88 | |||
89 | while (wkup_irq->mask) { | ||
90 | if (wkup_irq->hwirq == data->hwirq) { | ||
91 | if (!state) | ||
92 | exynos_irqwake_intmask |= wkup_irq->mask; | ||
93 | else | ||
94 | exynos_irqwake_intmask &= ~wkup_irq->mask; | ||
95 | return 0; | ||
96 | } | ||
97 | ++wkup_irq; | ||
98 | } | ||
99 | |||
100 | return -ENOENT; | ||
101 | } | ||
51 | 102 | ||
52 | /* For Cortex-A9 Diagnostic and Power control register */ | 103 | /* For Cortex-A9 Diagnostic and Power control register */ |
53 | static unsigned int save_arm_register[2]; | 104 | static unsigned int save_arm_register[2]; |
@@ -72,6 +123,10 @@ static void exynos_pm_prepare(void) | |||
72 | { | 123 | { |
73 | unsigned int tmp; | 124 | unsigned int tmp; |
74 | 125 | ||
126 | /* Set wake-up mask registers */ | ||
127 | __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK); | ||
128 | __raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK); | ||
129 | |||
75 | s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save)); | 130 | s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save)); |
76 | 131 | ||
77 | if (soc_is_exynos5250()) { | 132 | if (soc_is_exynos5250()) { |
@@ -89,41 +144,8 @@ static void exynos_pm_prepare(void) | |||
89 | 144 | ||
90 | /* ensure at least INFORM0 has the resume address */ | 145 | /* ensure at least INFORM0 has the resume address */ |
91 | 146 | ||
92 | __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0); | 147 | __raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0); |
93 | } | ||
94 | |||
95 | static int exynos_pm_add(struct device *dev, struct subsys_interface *sif) | ||
96 | { | ||
97 | pm_cpu_prep = exynos_pm_prepare; | ||
98 | pm_cpu_sleep = exynos_cpu_suspend; | ||
99 | |||
100 | return 0; | ||
101 | } | ||
102 | |||
103 | static struct subsys_interface exynos_pm_interface = { | ||
104 | .name = "exynos_pm", | ||
105 | .subsys = &exynos_subsys, | ||
106 | .add_dev = exynos_pm_add, | ||
107 | }; | ||
108 | |||
109 | static __init int exynos_pm_drvinit(void) | ||
110 | { | ||
111 | unsigned int tmp; | ||
112 | |||
113 | if (soc_is_exynos5440()) | ||
114 | return 0; | ||
115 | |||
116 | s3c_pm_init(); | ||
117 | |||
118 | /* All wakeup disable */ | ||
119 | |||
120 | tmp = __raw_readl(S5P_WAKEUP_MASK); | ||
121 | tmp |= ((0xFF << 8) | (0x1F << 1)); | ||
122 | __raw_writel(tmp, S5P_WAKEUP_MASK); | ||
123 | |||
124 | return subsys_interface_register(&exynos_pm_interface); | ||
125 | } | 148 | } |
126 | arch_initcall(exynos_pm_drvinit); | ||
127 | 149 | ||
128 | static int exynos_pm_suspend(void) | 150 | static int exynos_pm_suspend(void) |
129 | { | 151 | { |
@@ -220,12 +242,80 @@ static struct syscore_ops exynos_pm_syscore_ops = { | |||
220 | .resume = exynos_pm_resume, | 242 | .resume = exynos_pm_resume, |
221 | }; | 243 | }; |
222 | 244 | ||
223 | static __init int exynos_pm_syscore_init(void) | 245 | /* |
246 | * Suspend Ops | ||
247 | */ | ||
248 | |||
249 | static int exynos_suspend_enter(suspend_state_t state) | ||
224 | { | 250 | { |
225 | if (soc_is_exynos5440()) | 251 | int ret; |
226 | return 0; | 252 | |
253 | s3c_pm_debug_init(); | ||
254 | |||
255 | S3C_PMDBG("%s: suspending the system...\n", __func__); | ||
256 | |||
257 | S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__, | ||
258 | exynos_irqwake_intmask, exynos_get_eint_wake_mask()); | ||
259 | |||
260 | if (exynos_irqwake_intmask == -1U | ||
261 | && exynos_get_eint_wake_mask() == -1U) { | ||
262 | pr_err("%s: No wake-up sources!\n", __func__); | ||
263 | pr_err("%s: Aborting sleep\n", __func__); | ||
264 | return -EINVAL; | ||
265 | } | ||
266 | |||
267 | s3c_pm_save_uarts(); | ||
268 | exynos_pm_prepare(); | ||
269 | flush_cache_all(); | ||
270 | s3c_pm_check_store(); | ||
271 | |||
272 | ret = cpu_suspend(0, exynos_cpu_suspend); | ||
273 | if (ret) | ||
274 | return ret; | ||
275 | |||
276 | s3c_pm_restore_uarts(); | ||
277 | |||
278 | S3C_PMDBG("%s: wakeup stat: %08x\n", __func__, | ||
279 | __raw_readl(S5P_WAKEUP_STAT)); | ||
280 | |||
281 | s3c_pm_check_restore(); | ||
282 | |||
283 | S3C_PMDBG("%s: resuming the system...\n", __func__); | ||
227 | 284 | ||
228 | register_syscore_ops(&exynos_pm_syscore_ops); | ||
229 | return 0; | 285 | return 0; |
230 | } | 286 | } |
231 | arch_initcall(exynos_pm_syscore_init); | 287 | |
288 | static int exynos_suspend_prepare(void) | ||
289 | { | ||
290 | s3c_pm_check_prepare(); | ||
291 | |||
292 | return 0; | ||
293 | } | ||
294 | |||
295 | static void exynos_suspend_finish(void) | ||
296 | { | ||
297 | s3c_pm_check_cleanup(); | ||
298 | } | ||
299 | |||
300 | static const struct platform_suspend_ops exynos_suspend_ops = { | ||
301 | .enter = exynos_suspend_enter, | ||
302 | .prepare = exynos_suspend_prepare, | ||
303 | .finish = exynos_suspend_finish, | ||
304 | .valid = suspend_valid_only_mem, | ||
305 | }; | ||
306 | |||
307 | void __init exynos_pm_init(void) | ||
308 | { | ||
309 | u32 tmp; | ||
310 | |||
311 | /* Platform-specific GIC callback */ | ||
312 | gic_arch_extn.irq_set_wake = exynos_irq_set_wake; | ||
313 | |||
314 | /* All wakeup disable */ | ||
315 | tmp = __raw_readl(S5P_WAKEUP_MASK); | ||
316 | tmp |= ((0xFF << 8) | (0x1F << 1)); | ||
317 | __raw_writel(tmp, S5P_WAKEUP_MASK); | ||
318 | |||
319 | register_syscore_ops(&exynos_pm_syscore_ops); | ||
320 | suspend_set_ops(&exynos_suspend_ops); | ||
321 | } | ||
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h index 7c029ce27711..4f6a2560d022 100644 --- a/arch/arm/mach-exynos/regs-pmu.h +++ b/arch/arm/mach-exynos/regs-pmu.h | |||
@@ -26,11 +26,12 @@ | |||
26 | #define S5P_USE_STANDBY_WFI0 (1 << 16) | 26 | #define S5P_USE_STANDBY_WFI0 (1 << 16) |
27 | #define S5P_USE_STANDBY_WFE0 (1 << 24) | 27 | #define S5P_USE_STANDBY_WFE0 (1 << 24) |
28 | 28 | ||
29 | #define S5P_SWRESET S5P_PMUREG(0x0400) | ||
30 | #define EXYNOS_SWRESET S5P_PMUREG(0x0400) | 29 | #define EXYNOS_SWRESET S5P_PMUREG(0x0400) |
31 | #define EXYNOS5440_SWRESET S5P_PMUREG(0x00C4) | 30 | #define EXYNOS5440_SWRESET S5P_PMUREG(0x00C4) |
32 | 31 | ||
33 | #define S5P_WAKEUP_STAT S5P_PMUREG(0x0600) | 32 | #define S5P_WAKEUP_STAT S5P_PMUREG(0x0600) |
33 | #define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604) | ||
34 | #define S5P_WAKEUP_MASK S5P_PMUREG(0x0608) | ||
34 | 35 | ||
35 | #define S5P_INFORM0 S5P_PMUREG(0x0800) | 36 | #define S5P_INFORM0 S5P_PMUREG(0x0800) |
36 | #define S5P_INFORM1 S5P_PMUREG(0x0804) | 37 | #define S5P_INFORM1 S5P_PMUREG(0x0804) |
diff --git a/arch/arm/mach-exynos/sleep.S b/arch/arm/mach-exynos/sleep.S new file mode 100644 index 000000000000..a2613e944e10 --- /dev/null +++ b/arch/arm/mach-exynos/sleep.S | |||
@@ -0,0 +1,85 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. | ||
3 | * http://www.samsung.com | ||
4 | * | ||
5 | * Exynos low-level resume code | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, | ||
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
15 | * GNU General Public License for more details. | ||
16 | */ | ||
17 | |||
18 | #include <linux/linkage.h> | ||
19 | #include <asm/asm-offsets.h> | ||
20 | #include <asm/hardware/cache-l2x0.h> | ||
21 | |||
22 | #define CPU_MASK 0xff0ffff0 | ||
23 | #define CPU_CORTEX_A9 0x410fc090 | ||
24 | |||
25 | /* | ||
26 | * The following code is located into the .data section. This is to | ||
27 | * allow l2x0_regs_phys to be accessed with a relative load while we | ||
28 | * can't rely on any MMU translation. We could have put l2x0_regs_phys | ||
29 | * in the .text section as well, but some setups might insist on it to | ||
30 | * be truly read-only. (Reference from: arch/arm/kernel/sleep.S) | ||
31 | */ | ||
32 | .data | ||
33 | .align | ||
34 | |||
35 | /* | ||
36 | * sleep magic, to allow the bootloader to check for an valid | ||
37 | * image to resume to. Must be the first word before the | ||
38 | * exynos_cpu_resume entry. | ||
39 | */ | ||
40 | |||
41 | .word 0x2bedf00d | ||
42 | |||
43 | /* | ||
44 | * exynos_cpu_resume | ||
45 | * | ||
46 | * resume code entry for bootloader to call | ||
47 | */ | ||
48 | |||
49 | ENTRY(exynos_cpu_resume) | ||
50 | #ifdef CONFIG_CACHE_L2X0 | ||
51 | mrc p15, 0, r0, c0, c0, 0 | ||
52 | ldr r1, =CPU_MASK | ||
53 | and r0, r0, r1 | ||
54 | ldr r1, =CPU_CORTEX_A9 | ||
55 | cmp r0, r1 | ||
56 | bne skip_l2_resume | ||
57 | adr r0, l2x0_regs_phys | ||
58 | ldr r0, [r0] | ||
59 | cmp r0, #0 | ||
60 | beq skip_l2_resume | ||
61 | ldr r1, [r0, #L2X0_R_PHY_BASE] | ||
62 | ldr r2, [r1, #L2X0_CTRL] | ||
63 | tst r2, #0x1 | ||
64 | bne skip_l2_resume | ||
65 | ldr r2, [r0, #L2X0_R_AUX_CTRL] | ||
66 | str r2, [r1, #L2X0_AUX_CTRL] | ||
67 | ldr r2, [r0, #L2X0_R_TAG_LATENCY] | ||
68 | str r2, [r1, #L2X0_TAG_LATENCY_CTRL] | ||
69 | ldr r2, [r0, #L2X0_R_DATA_LATENCY] | ||
70 | str r2, [r1, #L2X0_DATA_LATENCY_CTRL] | ||
71 | ldr r2, [r0, #L2X0_R_PREFETCH_CTRL] | ||
72 | str r2, [r1, #L2X0_PREFETCH_CTRL] | ||
73 | ldr r2, [r0, #L2X0_R_PWR_CTRL] | ||
74 | str r2, [r1, #L2X0_POWER_CTRL] | ||
75 | mov r2, #1 | ||
76 | str r2, [r1, #L2X0_CTRL] | ||
77 | skip_l2_resume: | ||
78 | #endif | ||
79 | b cpu_resume | ||
80 | ENDPROC(exynos_cpu_resume) | ||
81 | #ifdef CONFIG_CACHE_L2X0 | ||
82 | .globl l2x0_regs_phys | ||
83 | l2x0_regs_phys: | ||
84 | .long 0 | ||
85 | #endif | ||
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c index 00ddf20ed91b..e3f3aca43efb 100644 --- a/arch/arm/mach-integrator/core.c +++ b/arch/arm/mach-integrator/core.c | |||
@@ -25,13 +25,11 @@ | |||
25 | #include <linux/of.h> | 25 | #include <linux/of.h> |
26 | #include <linux/of_address.h> | 26 | #include <linux/of_address.h> |
27 | 27 | ||
28 | #include <mach/hardware.h> | ||
29 | #include <mach/platform.h> | ||
30 | |||
31 | #include <asm/mach-types.h> | 28 | #include <asm/mach-types.h> |
32 | #include <asm/mach/time.h> | 29 | #include <asm/mach/time.h> |
33 | #include <asm/pgtable.h> | 30 | #include <asm/pgtable.h> |
34 | 31 | ||
32 | #include "hardware.h" | ||
35 | #include "cm.h" | 33 | #include "cm.h" |
36 | #include "common.h" | 34 | #include "common.h" |
37 | 35 | ||
diff --git a/arch/arm/mach-integrator/include/mach/platform.h b/arch/arm/mach-integrator/hardware.h index 306d025d9730..857ca5f8b9a6 100644 --- a/arch/arm/mach-integrator/include/mach/platform.h +++ b/arch/arm/mach-integrator/hardware.h | |||
@@ -1,4 +1,8 @@ | |||
1 | /* | 1 | /* |
2 | * This file contains the hardware definitions of the Integrator. | ||
3 | * | ||
4 | * Copyright (C) 1998-1999 ARM Limited. | ||
5 | * | ||
2 | * This program is free software; you can redistribute it and/or modify | 6 | * This program is free software; you can redistribute it and/or modify |
3 | * it under the terms of the GNU General Public License as published by | 7 | * it under the terms of the GNU General Public License as published by |
4 | * the Free Software Foundation; either version 2 of the License, or | 8 | * the Free Software Foundation; either version 2 of the License, or |
@@ -13,26 +17,28 @@ | |||
13 | * along with this program; if not, write to the Free Software | 17 | * along with this program; if not, write to the Free Software |
14 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
15 | */ | 19 | */ |
16 | /************************************************************************** | 20 | #ifndef INTEGRATOR_HARDWARE_H |
17 | * * Copyright © ARM Limited 1998. All rights reserved. | 21 | #define INTEGRATOR_HARDWARE_H |
18 | * ***********************************************************************/ | ||
19 | /* ************************************************************************ | ||
20 | * | ||
21 | * Integrator address map | ||
22 | * | ||
23 | * ***********************************************************************/ | ||
24 | 22 | ||
25 | #ifndef __address_h | 23 | /* |
26 | #define __address_h 1 | 24 | * Where in virtual memory the IO devices (timers, system controllers |
25 | * and so on) | ||
26 | */ | ||
27 | #define IO_BASE 0xF0000000 // VA of IO | ||
28 | #define IO_SIZE 0x0B000000 // How much? | ||
29 | #define IO_START INTEGRATOR_HDR_BASE // PA of IO | ||
30 | |||
31 | /* macro to get at IO space when running virtually */ | ||
32 | #ifdef CONFIG_MMU | ||
33 | #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE) | ||
34 | #else | ||
35 | #define IO_ADDRESS(x) (x) | ||
36 | #endif | ||
27 | 37 | ||
28 | /* ======================================================================== | 38 | #define __io_address(n) ((void __iomem *)IO_ADDRESS(n)) |
29 | * Integrator definitions | 39 | |
30 | * ======================================================================== | 40 | /* |
31 | * ------------------------------------------------------------------------ | ||
32 | * Memory definitions | ||
33 | * ------------------------------------------------------------------------ | ||
34 | * Integrator memory map | 41 | * Integrator memory map |
35 | * | ||
36 | */ | 42 | */ |
37 | #define INTEGRATOR_BOOT_ROM_LO 0x00000000 | 43 | #define INTEGRATOR_BOOT_ROM_LO 0x00000000 |
38 | #define INTEGRATOR_BOOT_ROM_HI 0x20000000 | 44 | #define INTEGRATOR_BOOT_ROM_HI 0x20000000 |
@@ -40,13 +46,13 @@ | |||
40 | #define INTEGRATOR_BOOT_ROM_SIZE SZ_512K | 46 | #define INTEGRATOR_BOOT_ROM_SIZE SZ_512K |
41 | 47 | ||
42 | /* | 48 | /* |
43 | * New Core Modules have different amounts of SSRAM, the amount of SSRAM | 49 | * New Core Modules have different amounts of SSRAM, the amount of SSRAM |
44 | * fitted can be found in HDR_STAT. | 50 | * fitted can be found in HDR_STAT. |
45 | * | 51 | * |
46 | * The symbol INTEGRATOR_SSRAM_SIZE is kept, however this now refers to | 52 | * The symbol INTEGRATOR_SSRAM_SIZE is kept, however this now refers to |
47 | * the minimum amount of SSRAM fitted on any core module. | 53 | * the minimum amount of SSRAM fitted on any core module. |
48 | * | 54 | * |
49 | * New Core Modules also alias the SSRAM. | 55 | * New Core Modules also alias the SSRAM. |
50 | * | 56 | * |
51 | */ | 57 | */ |
52 | #define INTEGRATOR_SSRAM_BASE 0x00000000 | 58 | #define INTEGRATOR_SSRAM_BASE 0x00000000 |
@@ -61,7 +67,6 @@ | |||
61 | 67 | ||
62 | /* | 68 | /* |
63 | * SDRAM is a SIMM therefore the size is not known. | 69 | * SDRAM is a SIMM therefore the size is not known. |
64 | * | ||
65 | */ | 70 | */ |
66 | #define INTEGRATOR_SDRAM_BASE 0x00040000 | 71 | #define INTEGRATOR_SDRAM_BASE 0x00040000 |
67 | 72 | ||
@@ -81,10 +86,8 @@ | |||
81 | #define INTEGRATOR_LOGIC_MODULE2_BASE 0xE0000000 | 86 | #define INTEGRATOR_LOGIC_MODULE2_BASE 0xE0000000 |
82 | #define INTEGRATOR_LOGIC_MODULE3_BASE 0xF0000000 | 87 | #define INTEGRATOR_LOGIC_MODULE3_BASE 0xF0000000 |
83 | 88 | ||
84 | /* ------------------------------------------------------------------------ | 89 | /* |
85 | * Integrator header card registers | 90 | * Integrator header card registers |
86 | * ------------------------------------------------------------------------ | ||
87 | * | ||
88 | */ | 91 | */ |
89 | #define INTEGRATOR_HDR_ID_OFFSET 0x00 | 92 | #define INTEGRATOR_HDR_ID_OFFSET 0x00 |
90 | #define INTEGRATOR_HDR_PROC_OFFSET 0x04 | 93 | #define INTEGRATOR_HDR_PROC_OFFSET 0x04 |
@@ -173,16 +176,12 @@ | |||
173 | 176 | ||
174 | #define INTEGRATOR_HDR_SDRAM_SPD_OK (1 << 5) | 177 | #define INTEGRATOR_HDR_SDRAM_SPD_OK (1 << 5) |
175 | 178 | ||
176 | 179 | /* | |
177 | /* ------------------------------------------------------------------------ | 180 | * Integrator system registers |
178 | * Integrator system registers | ||
179 | * ------------------------------------------------------------------------ | ||
180 | * | ||
181 | */ | 181 | */ |
182 | 182 | ||
183 | /* | 183 | /* |
184 | * System Controller | 184 | * System Controller |
185 | * | ||
186 | */ | 185 | */ |
187 | #define INTEGRATOR_SC_ID_OFFSET 0x00 | 186 | #define INTEGRATOR_SC_ID_OFFSET 0x00 |
188 | #define INTEGRATOR_SC_OSC_OFFSET 0x04 | 187 | #define INTEGRATOR_SC_OSC_OFFSET 0x04 |
@@ -223,7 +222,6 @@ | |||
223 | 222 | ||
224 | /* | 223 | /* |
225 | * External Bus Interface | 224 | * External Bus Interface |
226 | * | ||
227 | */ | 225 | */ |
228 | #define INTEGRATOR_EBI_BASE 0x12000000 | 226 | #define INTEGRATOR_EBI_BASE 0x12000000 |
229 | 227 | ||
@@ -272,7 +270,6 @@ | |||
272 | 270 | ||
273 | /* | 271 | /* |
274 | * LED's & Switches | 272 | * LED's & Switches |
275 | * | ||
276 | */ | 273 | */ |
277 | #define INTEGRATOR_DBG_ALPHA_OFFSET 0x00 | 274 | #define INTEGRATOR_DBG_ALPHA_OFFSET 0x00 |
278 | #define INTEGRATOR_DBG_LEDS_OFFSET 0x04 | 275 | #define INTEGRATOR_DBG_LEDS_OFFSET 0x04 |
@@ -292,32 +289,25 @@ | |||
292 | #define INTEGRATOR_CP_SIC_BASE 0xCA000000 /* SIC */ | 289 | #define INTEGRATOR_CP_SIC_BASE 0xCA000000 /* SIC */ |
293 | #define INTEGRATOR_CP_CTL_BASE 0xCB000000 /* CP system control */ | 290 | #define INTEGRATOR_CP_CTL_BASE 0xCB000000 /* CP system control */ |
294 | 291 | ||
295 | /* ------------------------------------------------------------------------ | ||
296 | * KMI keyboard/mouse definitions | ||
297 | * ------------------------------------------------------------------------ | ||
298 | */ | ||
299 | /* PS2 Keyboard interface */ | 292 | /* PS2 Keyboard interface */ |
300 | #define KMI0_BASE INTEGRATOR_KBD_BASE | 293 | #define KMI0_BASE INTEGRATOR_KBD_BASE |
301 | 294 | ||
302 | /* PS2 Mouse interface */ | 295 | /* PS2 Mouse interface */ |
303 | #define KMI1_BASE INTEGRATOR_MOUSE_BASE | 296 | #define KMI1_BASE INTEGRATOR_MOUSE_BASE |
304 | 297 | ||
305 | /* KMI definitions are now in include/asm-arm/hardware/amba_kmi.h -- rmk */ | 298 | /* |
306 | 299 | * Integrator Interrupt Controllers | |
307 | /* ------------------------------------------------------------------------ | ||
308 | * Integrator Interrupt Controllers | ||
309 | * ------------------------------------------------------------------------ | ||
310 | * | 300 | * |
311 | * Offsets from interrupt controller base | ||
312 | * | 301 | * |
313 | * System Controller interrupt controller base is | 302 | * Offsets from interrupt controller base |
303 | * | ||
304 | * System Controller interrupt controller base is | ||
314 | * | 305 | * |
315 | * INTEGRATOR_IC_BASE + (header_number << 6) | 306 | * INTEGRATOR_IC_BASE + (header_number << 6) |
316 | * | 307 | * |
317 | * Core Module interrupt controller base is | 308 | * Core Module interrupt controller base is |
318 | * | 309 | * |
319 | * INTEGRATOR_HDR_IC | 310 | * INTEGRATOR_HDR_IC |
320 | * | ||
321 | */ | 311 | */ |
322 | #define IRQ_STATUS 0 | 312 | #define IRQ_STATUS 0 |
323 | #define IRQ_RAW_STATUS 0x04 | 313 | #define IRQ_RAW_STATUS 0x04 |
@@ -335,25 +325,8 @@ | |||
335 | #define FIQ_ENABLE_CLEAR 0x2C | 325 | #define FIQ_ENABLE_CLEAR 0x2C |
336 | 326 | ||
337 | 327 | ||
338 | /* ------------------------------------------------------------------------ | 328 | /* |
339 | * Interrupts | 329 | * LED's |
340 | * ------------------------------------------------------------------------ | ||
341 | * | ||
342 | * | ||
343 | * Each Core Module has two interrupts controllers, one on the core module | ||
344 | * itself and one in the system controller on the motherboard. The | ||
345 | * READ_INT macro in target.s reads both interrupt controllers and returns | ||
346 | * a 32 bit bitmask, bits 0 to 23 are interrupts from the system controller | ||
347 | * and bits 24 to 31 are from the core module. | ||
348 | * | ||
349 | * The following definitions relate to the bitmask returned by READ_INT. | ||
350 | * | ||
351 | */ | ||
352 | |||
353 | /* ------------------------------------------------------------------------ | ||
354 | * LED's | ||
355 | * ------------------------------------------------------------------------ | ||
356 | * | ||
357 | */ | 330 | */ |
358 | #define GREEN_LED 0x01 | 331 | #define GREEN_LED 0x01 |
359 | #define YELLOW_LED 0x02 | 332 | #define YELLOW_LED 0x02 |
@@ -371,7 +344,6 @@ | |||
371 | * | 344 | * |
372 | * Timer 0 runs at bus frequency | 345 | * Timer 0 runs at bus frequency |
373 | */ | 346 | */ |
374 | |||
375 | #define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE | 347 | #define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE |
376 | #define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100) | 348 | #define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100) |
377 | #define INTEGRATOR_TIMER2_BASE (INTEGRATOR_CT_BASE + 0x200) | 349 | #define INTEGRATOR_TIMER2_BASE (INTEGRATOR_CT_BASE + 0x200) |
@@ -379,4 +351,4 @@ | |||
379 | #define INTEGRATOR_CSR_BASE 0x10000000 | 351 | #define INTEGRATOR_CSR_BASE 0x10000000 |
380 | #define INTEGRATOR_CSR_SIZE 0x10000000 | 352 | #define INTEGRATOR_CSR_SIZE 0x10000000 |
381 | 353 | ||
382 | #endif | 354 | #endif /* INTEGRATOR_HARDWARE_H */ |
diff --git a/arch/arm/mach-integrator/impd1.c b/arch/arm/mach-integrator/impd1.c index d9b784824808..0e870ea818c4 100644 --- a/arch/arm/mach-integrator/impd1.c +++ b/arch/arm/mach-integrator/impd1.c | |||
@@ -25,9 +25,9 @@ | |||
25 | #include <linux/slab.h> | 25 | #include <linux/slab.h> |
26 | #include <linux/irqchip/arm-vic.h> | 26 | #include <linux/irqchip/arm-vic.h> |
27 | 27 | ||
28 | #include <mach/lm.h> | ||
29 | #include <mach/impd1.h> | ||
30 | #include <asm/sizes.h> | 28 | #include <asm/sizes.h> |
29 | #include "lm.h" | ||
30 | #include "impd1.h" | ||
31 | 31 | ||
32 | static int module_id; | 32 | static int module_id; |
33 | 33 | ||
diff --git a/arch/arm/mach-integrator/include/mach/impd1.h b/arch/arm/mach-integrator/impd1.h index d75de4b14237..76de4dc9bee4 100644 --- a/arch/arm/mach-integrator/include/mach/impd1.h +++ b/arch/arm/mach-integrator/impd1.h | |||
@@ -1,6 +1,3 @@ | |||
1 | #define IMPD1_OSC1 0x00 | ||
2 | #define IMPD1_OSC2 0x04 | ||
3 | #define IMPD1_LOCK 0x08 | ||
4 | #define IMPD1_LEDS 0x0c | 1 | #define IMPD1_LEDS 0x0c |
5 | #define IMPD1_INT 0x10 | 2 | #define IMPD1_INT 0x10 |
6 | #define IMPD1_SW 0x14 | 3 | #define IMPD1_SW 0x14 |
@@ -15,4 +12,3 @@ | |||
15 | struct device; | 12 | struct device; |
16 | 13 | ||
17 | void impd1_tweak_control(struct device *dev, u32 mask, u32 val); | 14 | void impd1_tweak_control(struct device *dev, u32 mask, u32 val); |
18 | |||
diff --git a/arch/arm/mach-integrator/include/mach/hardware.h b/arch/arm/mach-integrator/include/mach/hardware.h deleted file mode 100644 index 65fed7c0eb84..000000000000 --- a/arch/arm/mach-integrator/include/mach/hardware.h +++ /dev/null | |||
@@ -1,45 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-integrator/include/mach/hardware.h | ||
3 | * | ||
4 | * This file contains the hardware definitions of the Integrator. | ||
5 | * | ||
6 | * Copyright (C) 1999 ARM Limited. | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License as published by | ||
10 | * the Free Software Foundation; either version 2 of the License, or | ||
11 | * (at your option) any later version. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, | ||
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
16 | * GNU General Public License for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License | ||
19 | * along with this program; if not, write to the Free Software | ||
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
21 | */ | ||
22 | #ifndef __ASM_ARCH_HARDWARE_H | ||
23 | #define __ASM_ARCH_HARDWARE_H | ||
24 | |||
25 | #include <asm/sizes.h> | ||
26 | |||
27 | /* | ||
28 | * Where in virtual memory the IO devices (timers, system controllers | ||
29 | * and so on) | ||
30 | */ | ||
31 | #define IO_BASE 0xF0000000 // VA of IO | ||
32 | #define IO_SIZE 0x0B000000 // How much? | ||
33 | #define IO_START INTEGRATOR_HDR_BASE // PA of IO | ||
34 | |||
35 | /* macro to get at IO space when running virtually */ | ||
36 | #ifdef CONFIG_MMU | ||
37 | #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE) | ||
38 | #else | ||
39 | #define IO_ADDRESS(x) (x) | ||
40 | #endif | ||
41 | |||
42 | #define __io_address(n) ((void __iomem *)IO_ADDRESS(n)) | ||
43 | |||
44 | #endif | ||
45 | |||
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index cc0857cab2e1..dd0cc677d596 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c | |||
@@ -44,23 +44,21 @@ | |||
44 | #include <linux/sched_clock.h> | 44 | #include <linux/sched_clock.h> |
45 | #include <linux/clk-provider.h> | 45 | #include <linux/clk-provider.h> |
46 | 46 | ||
47 | #include <mach/hardware.h> | ||
48 | #include <mach/platform.h> | ||
49 | #include <asm/hardware/arm_timer.h> | 47 | #include <asm/hardware/arm_timer.h> |
50 | #include <asm/setup.h> | 48 | #include <asm/setup.h> |
51 | #include <asm/param.h> /* HZ */ | 49 | #include <asm/param.h> /* HZ */ |
52 | #include <asm/mach-types.h> | 50 | #include <asm/mach-types.h> |
53 | 51 | ||
54 | #include <mach/lm.h> | ||
55 | |||
56 | #include <asm/mach/arch.h> | 52 | #include <asm/mach/arch.h> |
57 | #include <asm/mach/irq.h> | 53 | #include <asm/mach/irq.h> |
58 | #include <asm/mach/map.h> | 54 | #include <asm/mach/map.h> |
59 | #include <asm/mach/time.h> | 55 | #include <asm/mach/time.h> |
60 | 56 | ||
57 | #include "hardware.h" | ||
61 | #include "cm.h" | 58 | #include "cm.h" |
62 | #include "common.h" | 59 | #include "common.h" |
63 | #include "pci_v3.h" | 60 | #include "pci_v3.h" |
61 | #include "lm.h" | ||
64 | 62 | ||
65 | /* Base address to the AP system controller */ | 63 | /* Base address to the AP system controller */ |
66 | void __iomem *ap_syscon_base; | 64 | void __iomem *ap_syscon_base; |
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c index 0ad5f60598c8..a938242b0c95 100644 --- a/arch/arm/mach-integrator/integrator_cp.c +++ b/arch/arm/mach-integrator/integrator_cp.c | |||
@@ -27,22 +27,18 @@ | |||
27 | #include <linux/of_address.h> | 27 | #include <linux/of_address.h> |
28 | #include <linux/of_platform.h> | 28 | #include <linux/of_platform.h> |
29 | #include <linux/sys_soc.h> | 29 | #include <linux/sys_soc.h> |
30 | #include <linux/sched_clock.h> | ||
30 | 31 | ||
31 | #include <mach/hardware.h> | ||
32 | #include <mach/platform.h> | ||
33 | #include <asm/setup.h> | 32 | #include <asm/setup.h> |
34 | #include <asm/mach-types.h> | 33 | #include <asm/mach-types.h> |
35 | |||
36 | #include <mach/lm.h> | ||
37 | |||
38 | #include <asm/mach/arch.h> | 34 | #include <asm/mach/arch.h> |
39 | #include <asm/mach/irq.h> | 35 | #include <asm/mach/irq.h> |
40 | #include <asm/mach/map.h> | 36 | #include <asm/mach/map.h> |
41 | #include <asm/mach/time.h> | 37 | #include <asm/mach/time.h> |
42 | 38 | ||
43 | #include <plat/clcd.h> | 39 | #include <plat/clcd.h> |
44 | #include <plat/sched_clock.h> | ||
45 | 40 | ||
41 | #include "hardware.h" | ||
46 | #include "cm.h" | 42 | #include "cm.h" |
47 | #include "common.h" | 43 | #include "common.h" |
48 | 44 | ||
@@ -229,11 +225,14 @@ static struct clcd_board clcd_data = { | |||
229 | 225 | ||
230 | #define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28) | 226 | #define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28) |
231 | 227 | ||
228 | static u64 notrace intcp_read_sched_clock(void) | ||
229 | { | ||
230 | return readl(REFCOUNTER); | ||
231 | } | ||
232 | |||
232 | static void __init intcp_init_early(void) | 233 | static void __init intcp_init_early(void) |
233 | { | 234 | { |
234 | #ifdef CONFIG_PLAT_VERSATILE_SCHED_CLOCK | 235 | sched_clock_register(intcp_read_sched_clock, 32, 24000000); |
235 | versatile_sched_clock_init(REFCOUNTER, 24000000); | ||
236 | #endif | ||
237 | } | 236 | } |
238 | 237 | ||
239 | static const struct of_device_id fpga_irq_of_match[] __initconst = { | 238 | static const struct of_device_id fpga_irq_of_match[] __initconst = { |
diff --git a/arch/arm/mach-integrator/leds.c b/arch/arm/mach-integrator/leds.c index cb6ac58f5e07..f1dcb57a59e2 100644 --- a/arch/arm/mach-integrator/leds.c +++ b/arch/arm/mach-integrator/leds.c | |||
@@ -11,9 +11,7 @@ | |||
11 | #include <linux/slab.h> | 11 | #include <linux/slab.h> |
12 | #include <linux/leds.h> | 12 | #include <linux/leds.h> |
13 | 13 | ||
14 | #include <mach/hardware.h> | 14 | #include "hardware.h" |
15 | #include <mach/platform.h> | ||
16 | |||
17 | #include "cm.h" | 15 | #include "cm.h" |
18 | 16 | ||
19 | #if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS) | 17 | #if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS) |
diff --git a/arch/arm/mach-integrator/lm.c b/arch/arm/mach-integrator/lm.c index f52c7af31eaa..3f9e9f043168 100644 --- a/arch/arm/mach-integrator/lm.c +++ b/arch/arm/mach-integrator/lm.c | |||
@@ -12,7 +12,7 @@ | |||
12 | #include <linux/device.h> | 12 | #include <linux/device.h> |
13 | #include <linux/slab.h> | 13 | #include <linux/slab.h> |
14 | 14 | ||
15 | #include <mach/lm.h> | 15 | #include "lm.h" |
16 | 16 | ||
17 | #define to_lm_device(d) container_of(d, struct lm_device, dev) | 17 | #define to_lm_device(d) container_of(d, struct lm_device, dev) |
18 | #define to_lm_driver(d) container_of(d, struct lm_driver, drv) | 18 | #define to_lm_driver(d) container_of(d, struct lm_driver, drv) |
diff --git a/arch/arm/mach-integrator/include/mach/lm.h b/arch/arm/mach-integrator/lm.h index 28186b6f2c09..28186b6f2c09 100644 --- a/arch/arm/mach-integrator/include/mach/lm.h +++ b/arch/arm/mach-integrator/lm.h | |||
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c index c5e01b24d9fb..05e1f73a1e8d 100644 --- a/arch/arm/mach-integrator/pci_v3.c +++ b/arch/arm/mach-integrator/pci_v3.c | |||
@@ -34,15 +34,13 @@ | |||
34 | #include <linux/of_pci.h> | 34 | #include <linux/of_pci.h> |
35 | #include <video/vga.h> | 35 | #include <video/vga.h> |
36 | 36 | ||
37 | #include <mach/hardware.h> | ||
38 | #include <mach/platform.h> | ||
39 | |||
40 | #include <asm/mach/map.h> | 37 | #include <asm/mach/map.h> |
41 | #include <asm/signal.h> | 38 | #include <asm/signal.h> |
42 | #include <asm/mach/pci.h> | 39 | #include <asm/mach/pci.h> |
43 | #include <asm/irq_regs.h> | 40 | #include <asm/irq_regs.h> |
44 | 41 | ||
45 | #include "pci_v3.h" | 42 | #include "pci_v3.h" |
43 | #include "hardware.h" | ||
46 | 44 | ||
47 | /* | 45 | /* |
48 | * Where in the memory map does PCI live? | 46 | * Where in the memory map does PCI live? |
diff --git a/arch/arm/mach-s3c24xx/include/mach/hardware.h b/arch/arm/mach-s3c24xx/include/mach/hardware.h index a6cc14a092fc..dedd3837c193 100644 --- a/arch/arm/mach-s3c24xx/include/mach/hardware.h +++ b/arch/arm/mach-s3c24xx/include/mach/hardware.h | |||
@@ -1,5 +1,4 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/hardware.h | 1 | /* |
2 | * | ||
3 | * Copyright (c) 2003 Simtec Electronics | 2 | * Copyright (c) 2003 Simtec Electronics |
4 | * Ben Dooks <ben@simtec.co.uk> | 3 | * Ben Dooks <ben@simtec.co.uk> |
5 | * | 4 | * |
@@ -17,20 +16,9 @@ | |||
17 | 16 | ||
18 | extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg); | 17 | extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg); |
19 | 18 | ||
20 | #ifdef CONFIG_CPU_S3C2440 | ||
21 | |||
22 | extern int s3c2440_set_dsc(unsigned int pin, unsigned int value); | ||
23 | |||
24 | #endif /* CONFIG_CPU_S3C2440 */ | ||
25 | |||
26 | #endif /* __ASSEMBLY__ */ | 19 | #endif /* __ASSEMBLY__ */ |
27 | 20 | ||
28 | #include <asm/sizes.h> | 21 | #include <asm/sizes.h> |
29 | #include <mach/map.h> | 22 | #include <mach/map.h> |
30 | 23 | ||
31 | /* machine specific hardware definitions should go after this */ | ||
32 | |||
33 | /* currently here until moved into config (todo) */ | ||
34 | #define CONFIG_NO_MULTIWORD_IO | ||
35 | |||
36 | #endif /* __ASM_ARCH_HARDWARE_H */ | 24 | #endif /* __ASM_ARCH_HARDWARE_H */ |
diff --git a/arch/arm/mach-s3c24xx/include/mach/uncompress.h b/arch/arm/mach-s3c24xx/include/mach/uncompress.h deleted file mode 100644 index 7d2ce205dce8..000000000000 --- a/arch/arm/mach-s3c24xx/include/mach/uncompress.h +++ /dev/null | |||
@@ -1,57 +0,0 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/uncompress.h | ||
2 | * | ||
3 | * Copyright (c) 2003-2007 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * S3C2410 - uncompress code | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_ARCH_UNCOMPRESS_H | ||
15 | #define __ASM_ARCH_UNCOMPRESS_H | ||
16 | |||
17 | #include <mach/regs-gpio.h> | ||
18 | #include <mach/map.h> | ||
19 | |||
20 | /* working in physical space... */ | ||
21 | #undef S3C2410_GPIOREG | ||
22 | #define S3C2410_GPIOREG(x) ((S3C24XX_PA_GPIO + (x))) | ||
23 | |||
24 | #include <plat/uncompress.h> | ||
25 | |||
26 | static inline int is_arm926(void) | ||
27 | { | ||
28 | unsigned int cpuid; | ||
29 | |||
30 | asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (cpuid)); | ||
31 | |||
32 | return ((cpuid & 0xff0) == 0x260); | ||
33 | } | ||
34 | |||
35 | static void arch_detect_cpu(void) | ||
36 | { | ||
37 | unsigned int cpuid; | ||
38 | |||
39 | cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1); | ||
40 | cpuid &= S3C2410_GSTATUS1_IDMASK; | ||
41 | |||
42 | if (is_arm926() || cpuid == S3C2410_GSTATUS1_2440 || | ||
43 | cpuid == S3C2410_GSTATUS1_2442 || | ||
44 | cpuid == S3C2410_GSTATUS1_2416 || | ||
45 | cpuid == S3C2410_GSTATUS1_2450) { | ||
46 | fifo_mask = S3C2440_UFSTAT_TXMASK; | ||
47 | fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT; | ||
48 | } else { | ||
49 | fifo_mask = S3C2410_UFSTAT_TXMASK; | ||
50 | fifo_max = 15 << S3C2410_UFSTAT_TXSHIFT; | ||
51 | } | ||
52 | |||
53 | uart_base = (volatile u8 *) S3C_PA_UART + | ||
54 | (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT); | ||
55 | } | ||
56 | |||
57 | #endif /* __ASM_ARCH_UNCOMPRESS_H */ | ||
diff --git a/arch/arm/mach-s3c64xx/include/mach/pm-core.h b/arch/arm/mach-s3c64xx/include/mach/pm-core.h index c0537f40a3d8..a30a1e3ffc6a 100644 --- a/arch/arm/mach-s3c64xx/include/mach/pm-core.h +++ b/arch/arm/mach-s3c64xx/include/mach/pm-core.h | |||
@@ -15,6 +15,8 @@ | |||
15 | #ifndef __MACH_S3C64XX_PM_CORE_H | 15 | #ifndef __MACH_S3C64XX_PM_CORE_H |
16 | #define __MACH_S3C64XX_PM_CORE_H __FILE__ | 16 | #define __MACH_S3C64XX_PM_CORE_H __FILE__ |
17 | 17 | ||
18 | #include <linux/serial_s3c.h> | ||
19 | |||
18 | #include <mach/regs-gpio.h> | 20 | #include <mach/regs-gpio.h> |
19 | 21 | ||
20 | static inline void s3c_pm_debug_init_uart(void) | 22 | static inline void s3c_pm_debug_init_uart(void) |
diff --git a/arch/arm/mach-s3c64xx/include/mach/uncompress.h b/arch/arm/mach-s3c64xx/include/mach/uncompress.h deleted file mode 100644 index 1c956738b42d..000000000000 --- a/arch/arm/mach-s3c64xx/include/mach/uncompress.h +++ /dev/null | |||
@@ -1,31 +0,0 @@ | |||
1 | /* arch/arm/mach-s3c6400/include/mach/uncompress.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * Ben Dooks <ben@simtec.co.uk> | ||
7 | * | ||
8 | * S3C6400 - uncompress code | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #ifndef __ASM_ARCH_UNCOMPRESS_H | ||
16 | #define __ASM_ARCH_UNCOMPRESS_H | ||
17 | |||
18 | #include <mach/map.h> | ||
19 | #include <plat/uncompress.h> | ||
20 | |||
21 | static void arch_detect_cpu(void) | ||
22 | { | ||
23 | /* we do not need to do any cpu detection here at the moment. */ | ||
24 | fifo_mask = S3C2440_UFSTAT_TXMASK; | ||
25 | fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT; | ||
26 | |||
27 | uart_base = (volatile u8 *)S3C_PA_UART + | ||
28 | (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT); | ||
29 | } | ||
30 | |||
31 | #endif /* __ASM_ARCH_UNCOMPRESS_H */ | ||
diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c index b5a66986a529..6b37694fa335 100644 --- a/arch/arm/mach-s3c64xx/pm.c +++ b/arch/arm/mach-s3c64xx/pm.c | |||
@@ -332,7 +332,6 @@ static __init int s3c64xx_pm_initcall(void) | |||
332 | { | 332 | { |
333 | pm_cpu_prep = s3c64xx_pm_prepare; | 333 | pm_cpu_prep = s3c64xx_pm_prepare; |
334 | pm_cpu_sleep = s3c64xx_cpu_suspend; | 334 | pm_cpu_sleep = s3c64xx_cpu_suspend; |
335 | pm_uart_udivslot = 1; | ||
336 | 335 | ||
337 | #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK | 336 | #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK |
338 | gpio_request(S3C64XX_GPN(12), "DEBUG_LED0"); | 337 | gpio_request(S3C64XX_GPN(12), "DEBUG_LED0"); |
diff --git a/arch/arm/mach-s5p64x0/include/mach/pm-core.h b/arch/arm/mach-s5p64x0/include/mach/pm-core.h index e52f7545d3aa..1e0eb65b2b82 100644 --- a/arch/arm/mach-s5p64x0/include/mach/pm-core.h +++ b/arch/arm/mach-s5p64x0/include/mach/pm-core.h | |||
@@ -12,6 +12,8 @@ | |||
12 | * published by the Free Software Foundation. | 12 | * published by the Free Software Foundation. |
13 | */ | 13 | */ |
14 | 14 | ||
15 | #include <linux/serial_s3c.h> | ||
16 | |||
15 | #include <mach/regs-gpio.h> | 17 | #include <mach/regs-gpio.h> |
16 | 18 | ||
17 | static inline void s3c_pm_debug_init_uart(void) | 19 | static inline void s3c_pm_debug_init_uart(void) |
diff --git a/arch/arm/mach-s5p64x0/include/mach/uncompress.h b/arch/arm/mach-s5p64x0/include/mach/uncompress.h deleted file mode 100644 index bbcc3f669ee3..000000000000 --- a/arch/arm/mach-s5p64x0/include/mach/uncompress.h +++ /dev/null | |||
@@ -1,34 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5p64x0/include/mach/uncompress.h | ||
2 | * | ||
3 | * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * S5P64X0 - uncompress code | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_UNCOMPRESS_H | ||
14 | #define __ASM_ARCH_UNCOMPRESS_H | ||
15 | |||
16 | #include <mach/map.h> | ||
17 | #include <plat/uncompress.h> | ||
18 | |||
19 | static void arch_detect_cpu(void) | ||
20 | { | ||
21 | unsigned int chipid; | ||
22 | |||
23 | chipid = *(const volatile unsigned int __force *) 0xE0100118; | ||
24 | |||
25 | if ((chipid & 0xff000) == 0x50000) | ||
26 | uart_base = (volatile u8 *)S5P6450_PA_UART(CONFIG_S3C_LOWLEVEL_UART_PORT); | ||
27 | else | ||
28 | uart_base = (volatile u8 *)S5P6440_PA_UART(CONFIG_S3C_LOWLEVEL_UART_PORT); | ||
29 | |||
30 | fifo_mask = S3C2440_UFSTAT_TXMASK; | ||
31 | fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT; | ||
32 | } | ||
33 | |||
34 | #endif /* __ASM_ARCH_UNCOMPRESS_H */ | ||
diff --git a/arch/arm/mach-s5p64x0/pm.c b/arch/arm/mach-s5p64x0/pm.c index 861e15cea691..ec8229cee716 100644 --- a/arch/arm/mach-s5p64x0/pm.c +++ b/arch/arm/mach-s5p64x0/pm.c | |||
@@ -161,7 +161,6 @@ static int s5p64x0_pm_add(struct device *dev, struct subsys_interface *sif) | |||
161 | { | 161 | { |
162 | pm_cpu_prep = s5p64x0_pm_prepare; | 162 | pm_cpu_prep = s5p64x0_pm_prepare; |
163 | pm_cpu_sleep = s5p64x0_cpu_suspend; | 163 | pm_cpu_sleep = s5p64x0_cpu_suspend; |
164 | pm_uart_udivslot = 1; | ||
165 | 164 | ||
166 | return 0; | 165 | return 0; |
167 | } | 166 | } |
diff --git a/arch/arm/mach-s5pc100/include/mach/uncompress.h b/arch/arm/mach-s5pc100/include/mach/uncompress.h deleted file mode 100644 index 720e1339425c..000000000000 --- a/arch/arm/mach-s5pc100/include/mach/uncompress.h +++ /dev/null | |||
@@ -1,30 +0,0 @@ | |||
1 | /* arch/arm/mach-s5pc100/include/mach/uncompress.h | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics Co. | ||
4 | * Byungho Min <bhmin@samsung.com> | ||
5 | * | ||
6 | * S5PC100 - uncompress code | ||
7 | * | ||
8 | * Based on mach-s3c6400/include/mach/uncompress.h | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #ifndef __ASM_ARCH_UNCOMPRESS_H | ||
16 | #define __ASM_ARCH_UNCOMPRESS_H | ||
17 | |||
18 | #include <mach/map.h> | ||
19 | #include <plat/uncompress.h> | ||
20 | |||
21 | static void arch_detect_cpu(void) | ||
22 | { | ||
23 | /* we do not need to do any cpu detection here at the moment. */ | ||
24 | fifo_mask = S3C2440_UFSTAT_TXMASK; | ||
25 | fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT; | ||
26 | |||
27 | uart_base = (volatile u8 *)S5P_PA_UART(CONFIG_S3C_LOWLEVEL_UART_PORT); | ||
28 | } | ||
29 | |||
30 | #endif /* __ASM_ARCH_UNCOMPRESS_H */ | ||
diff --git a/arch/arm/mach-s5pv210/include/mach/uncompress.h b/arch/arm/mach-s5pv210/include/mach/uncompress.h deleted file mode 100644 index 231cb07de058..000000000000 --- a/arch/arm/mach-s5pv210/include/mach/uncompress.h +++ /dev/null | |||
@@ -1,28 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5pv210/include/mach/uncompress.h | ||
2 | * | ||
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com/ | ||
5 | * | ||
6 | * S5PV210 - uncompress code | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_UNCOMPRESS_H | ||
14 | #define __ASM_ARCH_UNCOMPRESS_H | ||
15 | |||
16 | #include <mach/map.h> | ||
17 | #include <plat/uncompress.h> | ||
18 | |||
19 | static void arch_detect_cpu(void) | ||
20 | { | ||
21 | /* we do not need to do any cpu detection here at the moment. */ | ||
22 | fifo_mask = S5PV210_UFSTAT_TXMASK; | ||
23 | fifo_max = 63 << S5PV210_UFSTAT_TXSHIFT; | ||
24 | |||
25 | uart_base = (volatile u8 *)S5P_PA_UART(CONFIG_S3C_LOWLEVEL_UART_PORT); | ||
26 | } | ||
27 | |||
28 | #endif /* __ASM_ARCH_UNCOMPRESS_H */ | ||
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index 0e001a489a79..58c2b844e0a3 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig | |||
@@ -9,5 +9,6 @@ config ARCH_ZYNQ | |||
9 | select ICST | 9 | select ICST |
10 | select CADENCE_TTC_TIMER | 10 | select CADENCE_TTC_TIMER |
11 | select ARM_GLOBAL_TIMER if !CPU_FREQ | 11 | select ARM_GLOBAL_TIMER if !CPU_FREQ |
12 | select MFD_SYSCON | ||
12 | help | 13 | help |
13 | Support for Xilinx Zynq ARM Cortex A9 Platform | 14 | Support for Xilinx Zynq ARM Cortex A9 Platform |
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index a39be8e80856..6fcc584c1a11 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c | |||
@@ -19,6 +19,7 @@ | |||
19 | #include <linux/cpumask.h> | 19 | #include <linux/cpumask.h> |
20 | #include <linux/platform_device.h> | 20 | #include <linux/platform_device.h> |
21 | #include <linux/clk.h> | 21 | #include <linux/clk.h> |
22 | #include <linux/clk-provider.h> | ||
22 | #include <linux/clk/zynq.h> | 23 | #include <linux/clk/zynq.h> |
23 | #include <linux/clocksource.h> | 24 | #include <linux/clocksource.h> |
24 | #include <linux/of_address.h> | 25 | #include <linux/of_address.h> |
@@ -75,11 +76,16 @@ static void __init zynq_init_machine(void) | |||
75 | 76 | ||
76 | platform_device_register(&zynq_cpuidle_device); | 77 | platform_device_register(&zynq_cpuidle_device); |
77 | platform_device_register_full(&devinfo); | 78 | platform_device_register_full(&devinfo); |
79 | |||
80 | zynq_slcr_init(); | ||
78 | } | 81 | } |
79 | 82 | ||
80 | static void __init zynq_timer_init(void) | 83 | static void __init zynq_timer_init(void) |
81 | { | 84 | { |
82 | zynq_slcr_init(); | 85 | zynq_early_slcr_init(); |
86 | |||
87 | zynq_clock_init(); | ||
88 | of_clk_init(NULL); | ||
83 | clocksource_of_init(); | 89 | clocksource_of_init(); |
84 | } | 90 | } |
85 | 91 | ||
diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h index c22c92cea8cb..b097844d3175 100644 --- a/arch/arm/mach-zynq/common.h +++ b/arch/arm/mach-zynq/common.h | |||
@@ -20,6 +20,7 @@ | |||
20 | void zynq_secondary_startup(void); | 20 | void zynq_secondary_startup(void); |
21 | 21 | ||
22 | extern int zynq_slcr_init(void); | 22 | extern int zynq_slcr_init(void); |
23 | extern int zynq_early_slcr_init(void); | ||
23 | extern void zynq_slcr_system_reset(void); | 24 | extern void zynq_slcr_system_reset(void); |
24 | extern void zynq_slcr_cpu_stop(int cpu); | 25 | extern void zynq_slcr_cpu_stop(int cpu); |
25 | extern void zynq_slcr_cpu_start(int cpu); | 26 | extern void zynq_slcr_cpu_start(int cpu); |
@@ -33,7 +34,6 @@ extern int zynq_cpun_start(u32 address, int cpu); | |||
33 | extern struct smp_operations zynq_smp_ops __initdata; | 34 | extern struct smp_operations zynq_smp_ops __initdata; |
34 | #endif | 35 | #endif |
35 | 36 | ||
36 | extern void __iomem *zynq_slcr_base; | ||
37 | extern void __iomem *zynq_scu_base; | 37 | extern void __iomem *zynq_scu_base; |
38 | 38 | ||
39 | /* Hotplug */ | 39 | /* Hotplug */ |
diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c index 1836d5a34606..a37d49a6e657 100644 --- a/arch/arm/mach-zynq/slcr.c +++ b/arch/arm/mach-zynq/slcr.c | |||
@@ -15,7 +15,9 @@ | |||
15 | */ | 15 | */ |
16 | 16 | ||
17 | #include <linux/io.h> | 17 | #include <linux/io.h> |
18 | #include <linux/mfd/syscon.h> | ||
18 | #include <linux/of_address.h> | 19 | #include <linux/of_address.h> |
20 | #include <linux/regmap.h> | ||
19 | #include <linux/clk/zynq.h> | 21 | #include <linux/clk/zynq.h> |
20 | #include "common.h" | 22 | #include "common.h" |
21 | 23 | ||
@@ -29,7 +31,56 @@ | |||
29 | #define SLCR_A9_CPU_CLKSTOP 0x10 | 31 | #define SLCR_A9_CPU_CLKSTOP 0x10 |
30 | #define SLCR_A9_CPU_RST 0x1 | 32 | #define SLCR_A9_CPU_RST 0x1 |
31 | 33 | ||
32 | void __iomem *zynq_slcr_base; | 34 | static void __iomem *zynq_slcr_base; |
35 | static struct regmap *zynq_slcr_regmap; | ||
36 | |||
37 | /** | ||
38 | * zynq_slcr_write - Write to a register in SLCR block | ||
39 | * | ||
40 | * @val: Value to write to the register | ||
41 | * @offset: Register offset in SLCR block | ||
42 | * | ||
43 | * Return: a negative value on error, 0 on success | ||
44 | */ | ||
45 | static int zynq_slcr_write(u32 val, u32 offset) | ||
46 | { | ||
47 | if (!zynq_slcr_regmap) { | ||
48 | writel(val, zynq_slcr_base + offset); | ||
49 | return 0; | ||
50 | } | ||
51 | |||
52 | return regmap_write(zynq_slcr_regmap, offset, val); | ||
53 | } | ||
54 | |||
55 | /** | ||
56 | * zynq_slcr_read - Read a register in SLCR block | ||
57 | * | ||
58 | * @val: Pointer to value to be read from SLCR | ||
59 | * @offset: Register offset in SLCR block | ||
60 | * | ||
61 | * Return: a negative value on error, 0 on success | ||
62 | */ | ||
63 | static int zynq_slcr_read(u32 *val, u32 offset) | ||
64 | { | ||
65 | if (zynq_slcr_regmap) | ||
66 | return regmap_read(zynq_slcr_regmap, offset, val); | ||
67 | |||
68 | *val = readl(zynq_slcr_base + offset); | ||
69 | |||
70 | return 0; | ||
71 | } | ||
72 | |||
73 | /** | ||
74 | * zynq_slcr_unlock - Unlock SLCR registers | ||
75 | * | ||
76 | * Return: a negative value on error, 0 on success | ||
77 | */ | ||
78 | static inline int zynq_slcr_unlock(void) | ||
79 | { | ||
80 | zynq_slcr_write(SLCR_UNLOCK_MAGIC, SLCR_UNLOCK_OFFSET); | ||
81 | |||
82 | return 0; | ||
83 | } | ||
33 | 84 | ||
34 | /** | 85 | /** |
35 | * zynq_slcr_system_reset - Reset the entire system. | 86 | * zynq_slcr_system_reset - Reset the entire system. |
@@ -43,16 +94,16 @@ void zynq_slcr_system_reset(void) | |||
43 | * Note that this seems to require raw i/o | 94 | * Note that this seems to require raw i/o |
44 | * functions or there's a lockup? | 95 | * functions or there's a lockup? |
45 | */ | 96 | */ |
46 | writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET); | 97 | zynq_slcr_unlock(); |
47 | 98 | ||
48 | /* | 99 | /* |
49 | * Clear 0x0F000000 bits of reboot status register to workaround | 100 | * Clear 0x0F000000 bits of reboot status register to workaround |
50 | * the FSBL not loading the bitstream after soft-reboot | 101 | * the FSBL not loading the bitstream after soft-reboot |
51 | * This is a temporary solution until we know more. | 102 | * This is a temporary solution until we know more. |
52 | */ | 103 | */ |
53 | reboot = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET); | 104 | zynq_slcr_read(&reboot, SLCR_REBOOT_STATUS_OFFSET); |
54 | writel(reboot & 0xF0FFFFFF, zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET); | 105 | zynq_slcr_write(reboot & 0xF0FFFFFF, SLCR_REBOOT_STATUS_OFFSET); |
55 | writel(1, zynq_slcr_base + SLCR_PS_RST_CTRL_OFFSET); | 106 | zynq_slcr_write(1, SLCR_PS_RST_CTRL_OFFSET); |
56 | } | 107 | } |
57 | 108 | ||
58 | /** | 109 | /** |
@@ -61,11 +112,13 @@ void zynq_slcr_system_reset(void) | |||
61 | */ | 112 | */ |
62 | void zynq_slcr_cpu_start(int cpu) | 113 | void zynq_slcr_cpu_start(int cpu) |
63 | { | 114 | { |
64 | u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); | 115 | u32 reg; |
116 | |||
117 | zynq_slcr_read(®, SLCR_A9_CPU_RST_CTRL_OFFSET); | ||
65 | reg &= ~(SLCR_A9_CPU_RST << cpu); | 118 | reg &= ~(SLCR_A9_CPU_RST << cpu); |
66 | writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); | 119 | zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET); |
67 | reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu); | 120 | reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu); |
68 | writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); | 121 | zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET); |
69 | } | 122 | } |
70 | 123 | ||
71 | /** | 124 | /** |
@@ -74,19 +127,40 @@ void zynq_slcr_cpu_start(int cpu) | |||
74 | */ | 127 | */ |
75 | void zynq_slcr_cpu_stop(int cpu) | 128 | void zynq_slcr_cpu_stop(int cpu) |
76 | { | 129 | { |
77 | u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); | 130 | u32 reg; |
131 | |||
132 | zynq_slcr_read(®, SLCR_A9_CPU_RST_CTRL_OFFSET); | ||
78 | reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu; | 133 | reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu; |
79 | writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); | 134 | zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET); |
80 | } | 135 | } |
81 | 136 | ||
82 | /** | 137 | /** |
83 | * zynq_slcr_init | 138 | * zynq_slcr_init - Regular slcr driver init |
84 | * Returns 0 on success, negative errno otherwise. | 139 | * |
140 | * Return: 0 on success, negative errno otherwise. | ||
85 | * | 141 | * |
86 | * Called early during boot from platform code to remap SLCR area. | 142 | * Called early during boot from platform code to remap SLCR area. |
87 | */ | 143 | */ |
88 | int __init zynq_slcr_init(void) | 144 | int __init zynq_slcr_init(void) |
89 | { | 145 | { |
146 | zynq_slcr_regmap = syscon_regmap_lookup_by_compatible("xlnx,zynq-slcr"); | ||
147 | if (IS_ERR(zynq_slcr_regmap)) { | ||
148 | pr_err("%s: failed to find zynq-slcr\n", __func__); | ||
149 | return -ENODEV; | ||
150 | } | ||
151 | |||
152 | return 0; | ||
153 | } | ||
154 | |||
155 | /** | ||
156 | * zynq_early_slcr_init - Early slcr init function | ||
157 | * | ||
158 | * Return: 0 on success, negative errno otherwise. | ||
159 | * | ||
160 | * Called very early during boot from platform code to unlock SLCR. | ||
161 | */ | ||
162 | int __init zynq_early_slcr_init(void) | ||
163 | { | ||
90 | struct device_node *np; | 164 | struct device_node *np; |
91 | 165 | ||
92 | np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr"); | 166 | np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr"); |
@@ -101,13 +175,13 @@ int __init zynq_slcr_init(void) | |||
101 | BUG(); | 175 | BUG(); |
102 | } | 176 | } |
103 | 177 | ||
178 | np->data = (__force void *)zynq_slcr_base; | ||
179 | |||
104 | /* unlock the SLCR so that registers can be changed */ | 180 | /* unlock the SLCR so that registers can be changed */ |
105 | writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET); | 181 | zynq_slcr_unlock(); |
106 | 182 | ||
107 | pr_info("%s mapped to %p\n", np->name, zynq_slcr_base); | 183 | pr_info("%s mapped to %p\n", np->name, zynq_slcr_base); |
108 | 184 | ||
109 | zynq_clock_init(zynq_slcr_base); | ||
110 | |||
111 | of_node_put(np); | 185 | of_node_put(np); |
112 | 186 | ||
113 | return 0; | 187 | return 0; |
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index 9267d29549b4..25c826ed3b65 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile | |||
@@ -47,9 +47,11 @@ obj-$(CONFIG_SAMSUNG_DMADEV) += dma-ops.o | |||
47 | 47 | ||
48 | # PM support | 48 | # PM support |
49 | 49 | ||
50 | obj-$(CONFIG_PM_SLEEP) += pm-common.o | ||
50 | obj-$(CONFIG_SAMSUNG_PM) += pm.o | 51 | obj-$(CONFIG_SAMSUNG_PM) += pm.o |
51 | obj-$(CONFIG_SAMSUNG_PM_GPIO) += pm-gpio.o | 52 | obj-$(CONFIG_SAMSUNG_PM_GPIO) += pm-gpio.o |
52 | obj-$(CONFIG_SAMSUNG_PM_CHECK) += pm-check.o | 53 | obj-$(CONFIG_SAMSUNG_PM_CHECK) += pm-check.o |
54 | obj-$(CONFIG_SAMSUNG_PM_DEBUG) += pm-debug.o | ||
53 | 55 | ||
54 | obj-$(CONFIG_SAMSUNG_WAKEMASK) += wakeup-mask.o | 56 | obj-$(CONFIG_SAMSUNG_WAKEMASK) += wakeup-mask.o |
55 | obj-$(CONFIG_SAMSUNG_WDT_RESET) += watchdog-reset.o | 57 | obj-$(CONFIG_SAMSUNG_WDT_RESET) += watchdog-reset.o |
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c index ddfebddb4105..d103ac1a52af 100644 --- a/arch/arm/plat-samsung/clock.c +++ b/arch/arm/plat-samsung/clock.c | |||
@@ -43,7 +43,6 @@ | |||
43 | #include <linux/debugfs.h> | 43 | #include <linux/debugfs.h> |
44 | #endif | 44 | #endif |
45 | 45 | ||
46 | #include <mach/hardware.h> | ||
47 | #include <asm/irq.h> | 46 | #include <asm/irq.h> |
48 | 47 | ||
49 | #include <plat/cpu-freq.h> | 48 | #include <plat/cpu-freq.h> |
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c index c64a39ac1b04..ead4f1c94058 100644 --- a/arch/arm/plat-samsung/devs.c +++ b/arch/arm/plat-samsung/devs.c | |||
@@ -31,6 +31,7 @@ | |||
31 | #include <linux/mtd/partitions.h> | 31 | #include <linux/mtd/partitions.h> |
32 | #include <linux/mmc/host.h> | 32 | #include <linux/mmc/host.h> |
33 | #include <linux/ioport.h> | 33 | #include <linux/ioport.h> |
34 | #include <linux/sizes.h> | ||
34 | #include <linux/platform_data/s3c-hsudc.h> | 35 | #include <linux/platform_data/s3c-hsudc.h> |
35 | #include <linux/platform_data/s3c-hsotg.h> | 36 | #include <linux/platform_data/s3c-hsotg.h> |
36 | #include <linux/platform_data/dma-s3c24xx.h> | 37 | #include <linux/platform_data/dma-s3c24xx.h> |
@@ -42,7 +43,6 @@ | |||
42 | #include <asm/mach/map.h> | 43 | #include <asm/mach/map.h> |
43 | #include <asm/mach/irq.h> | 44 | #include <asm/mach/irq.h> |
44 | 45 | ||
45 | #include <mach/hardware.h> | ||
46 | #include <mach/dma.h> | 46 | #include <mach/dma.h> |
47 | #include <mach/irqs.h> | 47 | #include <mach/irqs.h> |
48 | #include <mach/map.h> | 48 | #include <mach/map.h> |
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index 31164b34d4c4..5992b8dd9b89 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h | |||
@@ -20,6 +20,9 @@ | |||
20 | 20 | ||
21 | extern unsigned long samsung_cpu_id; | 21 | extern unsigned long samsung_cpu_id; |
22 | 22 | ||
23 | #define S3C2410_CPU_ID 0x32410000 | ||
24 | #define S3C2410_CPU_MASK 0xFFFFFFFF | ||
25 | |||
23 | #define S3C24XX_CPU_ID 0x32400000 | 26 | #define S3C24XX_CPU_ID 0x32400000 |
24 | #define S3C24XX_CPU_MASK 0xFFF00000 | 27 | #define S3C24XX_CPU_MASK 0xFFF00000 |
25 | 28 | ||
@@ -56,6 +59,7 @@ static inline int is_samsung_##name(void) \ | |||
56 | return ((samsung_cpu_id & mask) == (id & mask)); \ | 59 | return ((samsung_cpu_id & mask) == (id & mask)); \ |
57 | } | 60 | } |
58 | 61 | ||
62 | IS_SAMSUNG_CPU(s3c2410, S3C2410_CPU_ID, S3C2410_CPU_MASK) | ||
59 | IS_SAMSUNG_CPU(s3c24xx, S3C24XX_CPU_ID, S3C24XX_CPU_MASK) | 63 | IS_SAMSUNG_CPU(s3c24xx, S3C24XX_CPU_ID, S3C24XX_CPU_MASK) |
60 | IS_SAMSUNG_CPU(s3c2412, S3C2412_CPU_ID, S3C2412_CPU_MASK) | 64 | IS_SAMSUNG_CPU(s3c2412, S3C2412_CPU_ID, S3C2412_CPU_MASK) |
61 | IS_SAMSUNG_CPU(s3c6400, S3C6400_CPU_ID, S3C64XX_CPU_MASK) | 65 | IS_SAMSUNG_CPU(s3c6400, S3C6400_CPU_ID, S3C64XX_CPU_MASK) |
@@ -76,8 +80,10 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) | |||
76 | defined(CONFIG_CPU_S3C2442) || defined(CONFIG_CPU_S3C244X) || \ | 80 | defined(CONFIG_CPU_S3C2442) || defined(CONFIG_CPU_S3C244X) || \ |
77 | defined(CONFIG_CPU_S3C2443) | 81 | defined(CONFIG_CPU_S3C2443) |
78 | # define soc_is_s3c24xx() is_samsung_s3c24xx() | 82 | # define soc_is_s3c24xx() is_samsung_s3c24xx() |
83 | # define soc_is_s3c2410() is_samsung_s3c2410() | ||
79 | #else | 84 | #else |
80 | # define soc_is_s3c24xx() 0 | 85 | # define soc_is_s3c24xx() 0 |
86 | # define soc_is_s3c2410() 0 | ||
81 | #endif | 87 | #endif |
82 | 88 | ||
83 | #if defined(CONFIG_CPU_S3C2412) | 89 | #if defined(CONFIG_CPU_S3C2412) |
@@ -160,6 +166,10 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) | |||
160 | # define soc_is_exynos5440() 0 | 166 | # define soc_is_exynos5440() 0 |
161 | #endif | 167 | #endif |
162 | 168 | ||
169 | #define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4212() || \ | ||
170 | soc_is_exynos4412()) | ||
171 | #define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5420()) | ||
172 | |||
163 | #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE } | 173 | #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE } |
164 | 174 | ||
165 | #ifndef KHZ | 175 | #ifndef KHZ |
diff --git a/arch/arm/plat-samsung/include/plat/mfc.h b/arch/arm/plat-samsung/include/plat/mfc.h index e6d7c42d68b6..033654e91e22 100644 --- a/arch/arm/plat-samsung/include/plat/mfc.h +++ b/arch/arm/plat-samsung/include/plat/mfc.h | |||
@@ -32,7 +32,4 @@ struct s5p_mfc_dt_meminfo { | |||
32 | void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize, | 32 | void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize, |
33 | phys_addr_t lbase, unsigned int lsize); | 33 | phys_addr_t lbase, unsigned int lsize); |
34 | 34 | ||
35 | int __init s5p_fdt_find_mfc_mem(unsigned long node, const char *uname, | ||
36 | int depth, void *data); | ||
37 | |||
38 | #endif /* __PLAT_SAMSUNG_MFC_H */ | 35 | #endif /* __PLAT_SAMSUNG_MFC_H */ |
diff --git a/arch/arm/plat-samsung/include/plat/pm-common.h b/arch/arm/plat-samsung/include/plat/pm-common.h new file mode 100644 index 000000000000..8705f9e0e288 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/pm-common.h | |||
@@ -0,0 +1,110 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2013 Samsung Electronics Co., Ltd. | ||
3 | * Tomasz Figa <t.figa@samsung.com> | ||
4 | * Copyright (c) 2004 Simtec Electronics | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * Written by Ben Dooks, <ben@simtec.co.uk> | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __PLAT_SAMSUNG_PM_COMMON_H | ||
14 | #define __PLAT_SAMSUNG_PM_COMMON_H __FILE__ | ||
15 | |||
16 | #include <linux/irq.h> | ||
17 | |||
18 | /* sleep save info */ | ||
19 | |||
20 | /** | ||
21 | * struct sleep_save - save information for shared peripherals. | ||
22 | * @reg: Pointer to the register to save. | ||
23 | * @val: Holder for the value saved from reg. | ||
24 | * | ||
25 | * This describes a list of registers which is used by the pm core and | ||
26 | * other subsystem to save and restore register values over suspend. | ||
27 | */ | ||
28 | struct sleep_save { | ||
29 | void __iomem *reg; | ||
30 | unsigned long val; | ||
31 | }; | ||
32 | |||
33 | #define SAVE_ITEM(x) \ | ||
34 | { .reg = (x) } | ||
35 | |||
36 | /* helper functions to save/restore lists of registers. */ | ||
37 | |||
38 | extern void s3c_pm_do_save(struct sleep_save *ptr, int count); | ||
39 | extern void s3c_pm_do_restore(const struct sleep_save *ptr, int count); | ||
40 | extern void s3c_pm_do_restore_core(const struct sleep_save *ptr, int count); | ||
41 | |||
42 | /* PM debug functions */ | ||
43 | |||
44 | /** | ||
45 | * struct pm_uart_save - save block for core UART | ||
46 | * @ulcon: Save value for S3C2410_ULCON | ||
47 | * @ucon: Save value for S3C2410_UCON | ||
48 | * @ufcon: Save value for S3C2410_UFCON | ||
49 | * @umcon: Save value for S3C2410_UMCON | ||
50 | * @ubrdiv: Save value for S3C2410_UBRDIV | ||
51 | * | ||
52 | * Save block for UART registers to be held over sleep and restored if they | ||
53 | * are needed (say by debug). | ||
54 | */ | ||
55 | struct pm_uart_save { | ||
56 | u32 ulcon; | ||
57 | u32 ucon; | ||
58 | u32 ufcon; | ||
59 | u32 umcon; | ||
60 | u32 ubrdiv; | ||
61 | u32 udivslot; | ||
62 | }; | ||
63 | |||
64 | #ifdef CONFIG_SAMSUNG_PM_DEBUG | ||
65 | /** | ||
66 | * s3c_pm_dbg() - low level debug function for use in suspend/resume. | ||
67 | * @msg: The message to print. | ||
68 | * | ||
69 | * This function is used mainly to debug the resume process before the system | ||
70 | * can rely on printk/console output. It uses the low-level debugging output | ||
71 | * routine printascii() to do its work. | ||
72 | */ | ||
73 | extern void s3c_pm_dbg(const char *msg, ...); | ||
74 | |||
75 | /** | ||
76 | * s3c_pm_debug_init() - suspend/resume low level debug initialization. | ||
77 | * @base: Virtual base of UART to use for suspend/resume debugging. | ||
78 | * | ||
79 | * This function needs to be called before S3C_PMDBG() can be used, to set up | ||
80 | * UART port base address and configuration. | ||
81 | */ | ||
82 | extern void s3c_pm_debug_init(void); | ||
83 | |||
84 | #define S3C_PMDBG(fmt...) s3c_pm_dbg(fmt) | ||
85 | |||
86 | extern void s3c_pm_save_uarts(void); | ||
87 | extern void s3c_pm_restore_uarts(void); | ||
88 | #else | ||
89 | #define S3C_PMDBG(fmt...) pr_debug(fmt) | ||
90 | #define s3c_pm_debug_init() do { } while (0) | ||
91 | |||
92 | static inline void s3c_pm_save_uarts(void) { } | ||
93 | static inline void s3c_pm_restore_uarts(void) { } | ||
94 | #endif | ||
95 | |||
96 | /* suspend memory checking */ | ||
97 | |||
98 | #ifdef CONFIG_SAMSUNG_PM_CHECK | ||
99 | extern void s3c_pm_check_prepare(void); | ||
100 | extern void s3c_pm_check_restore(void); | ||
101 | extern void s3c_pm_check_cleanup(void); | ||
102 | extern void s3c_pm_check_store(void); | ||
103 | #else | ||
104 | #define s3c_pm_check_prepare() do { } while (0) | ||
105 | #define s3c_pm_check_restore() do { } while (0) | ||
106 | #define s3c_pm_check_cleanup() do { } while (0) | ||
107 | #define s3c_pm_check_store() do { } while (0) | ||
108 | #endif | ||
109 | |||
110 | #endif | ||
diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h index ff6063f0d5ea..e17d871b934c 100644 --- a/arch/arm/plat-samsung/include/plat/pm.h +++ b/arch/arm/plat-samsung/include/plat/pm.h | |||
@@ -15,7 +15,7 @@ | |||
15 | * management | 15 | * management |
16 | */ | 16 | */ |
17 | 17 | ||
18 | #include <linux/irq.h> | 18 | #include <plat/pm-common.h> |
19 | 19 | ||
20 | struct device; | 20 | struct device; |
21 | 21 | ||
@@ -54,56 +54,10 @@ extern int (*pm_cpu_sleep)(unsigned long); | |||
54 | 54 | ||
55 | extern unsigned long s3c_pm_flags; | 55 | extern unsigned long s3c_pm_flags; |
56 | 56 | ||
57 | extern unsigned char pm_uart_udivslot; /* true to save UART UDIVSLOT */ | ||
58 | |||
59 | /* from sleep.S */ | 57 | /* from sleep.S */ |
60 | 58 | ||
61 | extern int s3c2410_cpu_suspend(unsigned long); | 59 | extern int s3c2410_cpu_suspend(unsigned long); |
62 | 60 | ||
63 | /* sleep save info */ | ||
64 | |||
65 | /** | ||
66 | * struct sleep_save - save information for shared peripherals. | ||
67 | * @reg: Pointer to the register to save. | ||
68 | * @val: Holder for the value saved from reg. | ||
69 | * | ||
70 | * This describes a list of registers which is used by the pm core and | ||
71 | * other subsystem to save and restore register values over suspend. | ||
72 | */ | ||
73 | struct sleep_save { | ||
74 | void __iomem *reg; | ||
75 | unsigned long val; | ||
76 | }; | ||
77 | |||
78 | #define SAVE_ITEM(x) \ | ||
79 | { .reg = (x) } | ||
80 | |||
81 | /** | ||
82 | * struct pm_uart_save - save block for core UART | ||
83 | * @ulcon: Save value for S3C2410_ULCON | ||
84 | * @ucon: Save value for S3C2410_UCON | ||
85 | * @ufcon: Save value for S3C2410_UFCON | ||
86 | * @umcon: Save value for S3C2410_UMCON | ||
87 | * @ubrdiv: Save value for S3C2410_UBRDIV | ||
88 | * | ||
89 | * Save block for UART registers to be held over sleep and restored if they | ||
90 | * are needed (say by debug). | ||
91 | */ | ||
92 | struct pm_uart_save { | ||
93 | u32 ulcon; | ||
94 | u32 ucon; | ||
95 | u32 ufcon; | ||
96 | u32 umcon; | ||
97 | u32 ubrdiv; | ||
98 | u32 udivslot; | ||
99 | }; | ||
100 | |||
101 | /* helper functions to save/restore lists of registers. */ | ||
102 | |||
103 | extern void s3c_pm_do_save(struct sleep_save *ptr, int count); | ||
104 | extern void s3c_pm_do_restore(const struct sleep_save *ptr, int count); | ||
105 | extern void s3c_pm_do_restore_core(const struct sleep_save *ptr, int count); | ||
106 | |||
107 | #ifdef CONFIG_SAMSUNG_PM | 61 | #ifdef CONFIG_SAMSUNG_PM |
108 | extern int s3c_irq_wake(struct irq_data *data, unsigned int state); | 62 | extern int s3c_irq_wake(struct irq_data *data, unsigned int state); |
109 | extern int s3c_irqext_wake(struct irq_data *data, unsigned int state); | 63 | extern int s3c_irqext_wake(struct irq_data *data, unsigned int state); |
@@ -114,24 +68,6 @@ extern void s3c_cpu_resume(void); | |||
114 | #define s3c_cpu_resume NULL | 68 | #define s3c_cpu_resume NULL |
115 | #endif | 69 | #endif |
116 | 70 | ||
117 | /* PM debug functions */ | ||
118 | |||
119 | #ifdef CONFIG_SAMSUNG_PM_DEBUG | ||
120 | /** | ||
121 | * s3c_pm_dbg() - low level debug function for use in suspend/resume. | ||
122 | * @msg: The message to print. | ||
123 | * | ||
124 | * This function is used mainly to debug the resume process before the system | ||
125 | * can rely on printk/console output. It uses the low-level debugging output | ||
126 | * routine printascii() to do its work. | ||
127 | */ | ||
128 | extern void s3c_pm_dbg(const char *msg, ...); | ||
129 | |||
130 | #define S3C_PMDBG(fmt...) s3c_pm_dbg(fmt) | ||
131 | #else | ||
132 | #define S3C_PMDBG(fmt...) printk(KERN_DEBUG fmt) | ||
133 | #endif | ||
134 | |||
135 | #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK | 71 | #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK |
136 | /** | 72 | /** |
137 | * s3c_pm_debug_smdkled() - Debug PM suspend/resume via SMDK Board LEDs | 73 | * s3c_pm_debug_smdkled() - Debug PM suspend/resume via SMDK Board LEDs |
@@ -144,20 +80,6 @@ extern void s3c_pm_debug_smdkled(u32 set, u32 clear); | |||
144 | static inline void s3c_pm_debug_smdkled(u32 set, u32 clear) { } | 80 | static inline void s3c_pm_debug_smdkled(u32 set, u32 clear) { } |
145 | #endif /* CONFIG_S3C_PM_DEBUG_LED_SMDK */ | 81 | #endif /* CONFIG_S3C_PM_DEBUG_LED_SMDK */ |
146 | 82 | ||
147 | /* suspend memory checking */ | ||
148 | |||
149 | #ifdef CONFIG_SAMSUNG_PM_CHECK | ||
150 | extern void s3c_pm_check_prepare(void); | ||
151 | extern void s3c_pm_check_restore(void); | ||
152 | extern void s3c_pm_check_cleanup(void); | ||
153 | extern void s3c_pm_check_store(void); | ||
154 | #else | ||
155 | #define s3c_pm_check_prepare() do { } while(0) | ||
156 | #define s3c_pm_check_restore() do { } while(0) | ||
157 | #define s3c_pm_check_cleanup() do { } while(0) | ||
158 | #define s3c_pm_check_store() do { } while(0) | ||
159 | #endif | ||
160 | |||
161 | /** | 83 | /** |
162 | * s3c_pm_configure_extint() - ensure pins are correctly set for IRQ | 84 | * s3c_pm_configure_extint() - ensure pins are correctly set for IRQ |
163 | * | 85 | * |
diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h deleted file mode 100644 index 61054fd88d43..000000000000 --- a/arch/arm/plat-samsung/include/plat/uncompress.h +++ /dev/null | |||
@@ -1,175 +0,0 @@ | |||
1 | /* arch/arm/plat-samsung/include/plat/uncompress.h | ||
2 | * | ||
3 | * Copyright 2003, 2007 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * S3C - uncompress code | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_PLAT_UNCOMPRESS_H | ||
15 | #define __ASM_PLAT_UNCOMPRESS_H | ||
16 | |||
17 | typedef unsigned int upf_t; /* cannot include linux/serial_core.h */ | ||
18 | |||
19 | /* uart setup */ | ||
20 | |||
21 | unsigned int fifo_mask; | ||
22 | unsigned int fifo_max; | ||
23 | |||
24 | volatile u8 *uart_base; | ||
25 | |||
26 | /* forward declerations */ | ||
27 | |||
28 | static void arch_detect_cpu(void); | ||
29 | |||
30 | /* defines for UART registers */ | ||
31 | |||
32 | #include <linux/serial_s3c.h> | ||
33 | |||
34 | /* working in physical space... */ | ||
35 | #define S3C_WDOGREG(x) ((S3C_PA_WDT + (x))) | ||
36 | |||
37 | #define S3C2410_WTCON S3C_WDOGREG(0x00) | ||
38 | #define S3C2410_WTDAT S3C_WDOGREG(0x04) | ||
39 | #define S3C2410_WTCNT S3C_WDOGREG(0x08) | ||
40 | |||
41 | #define S3C2410_WTCON_RSTEN (1 << 0) | ||
42 | #define S3C2410_WTCON_ENABLE (1 << 5) | ||
43 | |||
44 | #define S3C2410_WTCON_DIV128 (3 << 3) | ||
45 | |||
46 | #define S3C2410_WTCON_PRESCALE(x) ((x) << 8) | ||
47 | |||
48 | /* how many bytes we allow into the FIFO at a time in FIFO mode */ | ||
49 | #define FIFO_MAX (14) | ||
50 | |||
51 | static __inline__ void | ||
52 | uart_wr(unsigned int reg, unsigned int val) | ||
53 | { | ||
54 | volatile unsigned int *ptr; | ||
55 | |||
56 | ptr = (volatile unsigned int *)(reg + uart_base); | ||
57 | *ptr = val; | ||
58 | } | ||
59 | |||
60 | static __inline__ unsigned int | ||
61 | uart_rd(unsigned int reg) | ||
62 | { | ||
63 | volatile unsigned int *ptr; | ||
64 | |||
65 | ptr = (volatile unsigned int *)(reg + uart_base); | ||
66 | return *ptr; | ||
67 | } | ||
68 | |||
69 | /* we can deal with the case the UARTs are being run | ||
70 | * in FIFO mode, so that we don't hold up our execution | ||
71 | * waiting for tx to happen... | ||
72 | */ | ||
73 | |||
74 | static void putc(int ch) | ||
75 | { | ||
76 | if (!config_enabled(CONFIG_DEBUG_LL)) | ||
77 | return; | ||
78 | |||
79 | if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) { | ||
80 | int level; | ||
81 | |||
82 | while (1) { | ||
83 | level = uart_rd(S3C2410_UFSTAT); | ||
84 | level &= fifo_mask; | ||
85 | |||
86 | if (level < fifo_max) | ||
87 | break; | ||
88 | } | ||
89 | |||
90 | } else { | ||
91 | /* not using fifos */ | ||
92 | |||
93 | while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE) | ||
94 | barrier(); | ||
95 | } | ||
96 | |||
97 | /* write byte to transmission register */ | ||
98 | uart_wr(S3C2410_UTXH, ch); | ||
99 | } | ||
100 | |||
101 | static inline void flush(void) | ||
102 | { | ||
103 | } | ||
104 | |||
105 | #define __raw_writel(d, ad) \ | ||
106 | do { \ | ||
107 | *((volatile unsigned int __force *)(ad)) = (d); \ | ||
108 | } while (0) | ||
109 | |||
110 | #ifdef CONFIG_S3C_BOOT_ERROR_RESET | ||
111 | |||
112 | static void arch_decomp_error(const char *x) | ||
113 | { | ||
114 | putstr("\n\n"); | ||
115 | putstr(x); | ||
116 | putstr("\n\n -- System resetting\n"); | ||
117 | |||
118 | __raw_writel(0x4000, S3C2410_WTDAT); | ||
119 | __raw_writel(0x4000, S3C2410_WTCNT); | ||
120 | __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON); | ||
121 | |||
122 | while(1); | ||
123 | } | ||
124 | |||
125 | #define arch_error arch_decomp_error | ||
126 | #endif | ||
127 | |||
128 | #ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO | ||
129 | static inline void arch_enable_uart_fifo(void) | ||
130 | { | ||
131 | u32 fifocon; | ||
132 | |||
133 | if (!config_enabled(CONFIG_DEBUG_LL)) | ||
134 | return; | ||
135 | |||
136 | fifocon = uart_rd(S3C2410_UFCON); | ||
137 | |||
138 | if (!(fifocon & S3C2410_UFCON_FIFOMODE)) { | ||
139 | fifocon |= S3C2410_UFCON_RESETBOTH; | ||
140 | uart_wr(S3C2410_UFCON, fifocon); | ||
141 | |||
142 | /* wait for fifo reset to complete */ | ||
143 | while (1) { | ||
144 | fifocon = uart_rd(S3C2410_UFCON); | ||
145 | if (!(fifocon & S3C2410_UFCON_RESETBOTH)) | ||
146 | break; | ||
147 | } | ||
148 | |||
149 | uart_wr(S3C2410_UFCON, S3C2410_UFCON_FIFOMODE); | ||
150 | } | ||
151 | } | ||
152 | #else | ||
153 | #define arch_enable_uart_fifo() do { } while(0) | ||
154 | #endif | ||
155 | |||
156 | |||
157 | static void | ||
158 | arch_decomp_setup(void) | ||
159 | { | ||
160 | /* we may need to setup the uart(s) here if we are not running | ||
161 | * on an BAST... the BAST will have left the uarts configured | ||
162 | * after calling linux. | ||
163 | */ | ||
164 | |||
165 | arch_detect_cpu(); | ||
166 | |||
167 | /* Enable the UART FIFOs if they where not enabled and our | ||
168 | * configuration says we should turn them on. | ||
169 | */ | ||
170 | |||
171 | arch_enable_uart_fifo(); | ||
172 | } | ||
173 | |||
174 | |||
175 | #endif /* __ASM_PLAT_UNCOMPRESS_H */ | ||
diff --git a/arch/arm/plat-samsung/init.c b/arch/arm/plat-samsung/init.c index c32df1f202eb..a1f925f3121f 100644 --- a/arch/arm/plat-samsung/init.c +++ b/arch/arm/plat-samsung/init.c | |||
@@ -25,8 +25,6 @@ | |||
25 | #include <linux/platform_device.h> | 25 | #include <linux/platform_device.h> |
26 | #include <linux/of.h> | 26 | #include <linux/of.h> |
27 | 27 | ||
28 | #include <mach/hardware.h> | ||
29 | |||
30 | #include <asm/mach/arch.h> | 28 | #include <asm/mach/arch.h> |
31 | #include <asm/mach/map.h> | 29 | #include <asm/mach/map.h> |
32 | 30 | ||
diff --git a/arch/arm/plat-samsung/pm-check.c b/arch/arm/plat-samsung/pm-check.c index 3cbd62666b1e..04aff2c31b46 100644 --- a/arch/arm/plat-samsung/pm-check.c +++ b/arch/arm/plat-samsung/pm-check.c | |||
@@ -19,7 +19,7 @@ | |||
19 | #include <linux/ioport.h> | 19 | #include <linux/ioport.h> |
20 | #include <linux/slab.h> | 20 | #include <linux/slab.h> |
21 | 21 | ||
22 | #include <plat/pm.h> | 22 | #include <plat/pm-common.h> |
23 | 23 | ||
24 | #if CONFIG_SAMSUNG_PM_CHECK_CHUNKSIZE < 1 | 24 | #if CONFIG_SAMSUNG_PM_CHECK_CHUNKSIZE < 1 |
25 | #error CONFIG_SAMSUNG_PM_CHECK_CHUNKSIZE must be a positive non-zero value | 25 | #error CONFIG_SAMSUNG_PM_CHECK_CHUNKSIZE must be a positive non-zero value |
diff --git a/arch/arm/plat-samsung/pm-common.c b/arch/arm/plat-samsung/pm-common.c new file mode 100644 index 000000000000..515cd53372bd --- /dev/null +++ b/arch/arm/plat-samsung/pm-common.c | |||
@@ -0,0 +1,75 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2013 Samsung Electronics Co., Ltd. | ||
3 | * Tomasz Figa <t.figa@samsung.com> | ||
4 | * Copyright (C) 2008 Openmoko, Inc. | ||
5 | * Copyright (C) 2004-2008 Simtec Electronics | ||
6 | * Ben Dooks <ben@simtec.co.uk> | ||
7 | * http://armlinux.simtec.co.uk/ | ||
8 | * | ||
9 | * Samsung common power management helper functions. | ||
10 | * | ||
11 | * This program is free software; you can redistribute it and/or modify | ||
12 | * it under the terms of the GNU General Public License version 2 as | ||
13 | * published by the Free Software Foundation. | ||
14 | */ | ||
15 | |||
16 | #include <linux/io.h> | ||
17 | #include <linux/kernel.h> | ||
18 | |||
19 | #include <plat/pm-common.h> | ||
20 | |||
21 | /* helper functions to save and restore register state */ | ||
22 | |||
23 | /** | ||
24 | * s3c_pm_do_save() - save a set of registers for restoration on resume. | ||
25 | * @ptr: Pointer to an array of registers. | ||
26 | * @count: Size of the ptr array. | ||
27 | * | ||
28 | * Run through the list of registers given, saving their contents in the | ||
29 | * array for later restoration when we wakeup. | ||
30 | */ | ||
31 | void s3c_pm_do_save(struct sleep_save *ptr, int count) | ||
32 | { | ||
33 | for (; count > 0; count--, ptr++) { | ||
34 | ptr->val = __raw_readl(ptr->reg); | ||
35 | S3C_PMDBG("saved %p value %08lx\n", ptr->reg, ptr->val); | ||
36 | } | ||
37 | } | ||
38 | |||
39 | /** | ||
40 | * s3c_pm_do_restore() - restore register values from the save list. | ||
41 | * @ptr: Pointer to an array of registers. | ||
42 | * @count: Size of the ptr array. | ||
43 | * | ||
44 | * Restore the register values saved from s3c_pm_do_save(). | ||
45 | * | ||
46 | * Note, we do not use S3C_PMDBG() in here, as the system may not have | ||
47 | * restore the UARTs state yet | ||
48 | */ | ||
49 | |||
50 | void s3c_pm_do_restore(const struct sleep_save *ptr, int count) | ||
51 | { | ||
52 | for (; count > 0; count--, ptr++) { | ||
53 | pr_debug("restore %p (restore %08lx, was %08x)\n", | ||
54 | ptr->reg, ptr->val, __raw_readl(ptr->reg)); | ||
55 | |||
56 | __raw_writel(ptr->val, ptr->reg); | ||
57 | } | ||
58 | } | ||
59 | |||
60 | /** | ||
61 | * s3c_pm_do_restore_core() - early restore register values from save list. | ||
62 | * | ||
63 | * This is similar to s3c_pm_do_restore() except we try and minimise the | ||
64 | * side effects of the function in case registers that hardware might need | ||
65 | * to work has been restored. | ||
66 | * | ||
67 | * WARNING: Do not put any debug in here that may effect memory or use | ||
68 | * peripherals, as things may be changing! | ||
69 | */ | ||
70 | |||
71 | void s3c_pm_do_restore_core(const struct sleep_save *ptr, int count) | ||
72 | { | ||
73 | for (; count > 0; count--, ptr++) | ||
74 | __raw_writel(ptr->val, ptr->reg); | ||
75 | } | ||
diff --git a/arch/arm/plat-samsung/pm-debug.c b/arch/arm/plat-samsung/pm-debug.c new file mode 100644 index 000000000000..8f19f66388dd --- /dev/null +++ b/arch/arm/plat-samsung/pm-debug.c | |||
@@ -0,0 +1,97 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2013 Samsung Electronics Co., Ltd. | ||
3 | * Tomasz Figa <t.figa@samsung.com> | ||
4 | * Copyright (C) 2008 Openmoko, Inc. | ||
5 | * Copyright (C) 2004-2008 Simtec Electronics | ||
6 | * Ben Dooks <ben@simtec.co.uk> | ||
7 | * http://armlinux.simtec.co.uk/ | ||
8 | * | ||
9 | * Samsung common power management (suspend to RAM) debug support | ||
10 | * | ||
11 | * This program is free software; you can redistribute it and/or modify | ||
12 | * it under the terms of the GNU General Public License version 2 as | ||
13 | * published by the Free Software Foundation. | ||
14 | */ | ||
15 | |||
16 | #include <linux/serial_core.h> | ||
17 | #include <linux/io.h> | ||
18 | |||
19 | #include <asm/mach/map.h> | ||
20 | |||
21 | #include <plat/cpu.h> | ||
22 | #include <plat/pm-common.h> | ||
23 | |||
24 | #ifdef CONFIG_SAMSUNG_ATAGS | ||
25 | #include <mach/pm-core.h> | ||
26 | #else | ||
27 | static inline void s3c_pm_debug_init_uart(void) {} | ||
28 | static inline void s3c_pm_arch_update_uart(void __iomem *regs, | ||
29 | struct pm_uart_save *save) {} | ||
30 | #endif | ||
31 | |||
32 | static struct pm_uart_save uart_save; | ||
33 | |||
34 | extern void printascii(const char *); | ||
35 | |||
36 | void s3c_pm_dbg(const char *fmt, ...) | ||
37 | { | ||
38 | va_list va; | ||
39 | char buff[256]; | ||
40 | |||
41 | va_start(va, fmt); | ||
42 | vsnprintf(buff, sizeof(buff), fmt, va); | ||
43 | va_end(va); | ||
44 | |||
45 | printascii(buff); | ||
46 | } | ||
47 | |||
48 | void s3c_pm_debug_init(void) | ||
49 | { | ||
50 | /* restart uart clocks so we can use them to output */ | ||
51 | s3c_pm_debug_init_uart(); | ||
52 | } | ||
53 | |||
54 | static inline void __iomem *s3c_pm_uart_base(void) | ||
55 | { | ||
56 | unsigned long paddr; | ||
57 | unsigned long vaddr; | ||
58 | |||
59 | debug_ll_addr(&paddr, &vaddr); | ||
60 | |||
61 | return (void __iomem *)vaddr; | ||
62 | } | ||
63 | |||
64 | void s3c_pm_save_uarts(void) | ||
65 | { | ||
66 | void __iomem *regs = s3c_pm_uart_base(); | ||
67 | struct pm_uart_save *save = &uart_save; | ||
68 | |||
69 | save->ulcon = __raw_readl(regs + S3C2410_ULCON); | ||
70 | save->ucon = __raw_readl(regs + S3C2410_UCON); | ||
71 | save->ufcon = __raw_readl(regs + S3C2410_UFCON); | ||
72 | save->umcon = __raw_readl(regs + S3C2410_UMCON); | ||
73 | save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV); | ||
74 | |||
75 | if (!soc_is_s3c2410()) | ||
76 | save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT); | ||
77 | |||
78 | S3C_PMDBG("UART[%p]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n", | ||
79 | regs, save->ulcon, save->ucon, save->ufcon, save->ubrdiv); | ||
80 | } | ||
81 | |||
82 | void s3c_pm_restore_uarts(void) | ||
83 | { | ||
84 | void __iomem *regs = s3c_pm_uart_base(); | ||
85 | struct pm_uart_save *save = &uart_save; | ||
86 | |||
87 | s3c_pm_arch_update_uart(regs, save); | ||
88 | |||
89 | __raw_writel(save->ulcon, regs + S3C2410_ULCON); | ||
90 | __raw_writel(save->ucon, regs + S3C2410_UCON); | ||
91 | __raw_writel(save->ufcon, regs + S3C2410_UFCON); | ||
92 | __raw_writel(save->umcon, regs + S3C2410_UMCON); | ||
93 | __raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV); | ||
94 | |||
95 | if (!soc_is_s3c2410()) | ||
96 | __raw_writel(save->udivslot, regs + S3C2443_DIVSLOT); | ||
97 | } | ||
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c index ae9baa2d6381..f8c0f9797dcf 100644 --- a/arch/arm/plat-samsung/pm.c +++ b/arch/arm/plat-samsung/pm.c | |||
@@ -17,7 +17,6 @@ | |||
17 | #include <linux/errno.h> | 17 | #include <linux/errno.h> |
18 | #include <linux/delay.h> | 18 | #include <linux/delay.h> |
19 | #include <linux/of.h> | 19 | #include <linux/of.h> |
20 | #include <linux/serial_core.h> | ||
21 | #include <linux/serial_s3c.h> | 20 | #include <linux/serial_s3c.h> |
22 | #include <linux/io.h> | 21 | #include <linux/io.h> |
23 | 22 | ||
@@ -25,7 +24,6 @@ | |||
25 | #include <asm/suspend.h> | 24 | #include <asm/suspend.h> |
26 | 25 | ||
27 | #ifdef CONFIG_SAMSUNG_ATAGS | 26 | #ifdef CONFIG_SAMSUNG_ATAGS |
28 | #include <mach/hardware.h> | ||
29 | #include <mach/map.h> | 27 | #include <mach/map.h> |
30 | #ifndef CONFIG_ARCH_EXYNOS | 28 | #ifndef CONFIG_ARCH_EXYNOS |
31 | #include <mach/regs-clock.h> | 29 | #include <mach/regs-clock.h> |
@@ -43,93 +41,6 @@ | |||
43 | 41 | ||
44 | unsigned long s3c_pm_flags; | 42 | unsigned long s3c_pm_flags; |
45 | 43 | ||
46 | /* Debug code: | ||
47 | * | ||
48 | * This code supports debug output to the low level UARTs for use on | ||
49 | * resume before the console layer is available. | ||
50 | */ | ||
51 | |||
52 | #ifdef CONFIG_SAMSUNG_PM_DEBUG | ||
53 | extern void printascii(const char *); | ||
54 | |||
55 | void s3c_pm_dbg(const char *fmt, ...) | ||
56 | { | ||
57 | va_list va; | ||
58 | char buff[256]; | ||
59 | |||
60 | va_start(va, fmt); | ||
61 | vsnprintf(buff, sizeof(buff), fmt, va); | ||
62 | va_end(va); | ||
63 | |||
64 | printascii(buff); | ||
65 | } | ||
66 | |||
67 | static inline void s3c_pm_debug_init(void) | ||
68 | { | ||
69 | /* restart uart clocks so we can use them to output */ | ||
70 | s3c_pm_debug_init_uart(); | ||
71 | } | ||
72 | |||
73 | #else | ||
74 | #define s3c_pm_debug_init() do { } while(0) | ||
75 | |||
76 | #endif /* CONFIG_SAMSUNG_PM_DEBUG */ | ||
77 | |||
78 | /* Save the UART configurations if we are configured for debug. */ | ||
79 | |||
80 | unsigned char pm_uart_udivslot; | ||
81 | |||
82 | #ifdef CONFIG_SAMSUNG_PM_DEBUG | ||
83 | |||
84 | static struct pm_uart_save uart_save; | ||
85 | |||
86 | static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save) | ||
87 | { | ||
88 | void __iomem *regs = S3C_VA_UARTx(uart); | ||
89 | |||
90 | save->ulcon = __raw_readl(regs + S3C2410_ULCON); | ||
91 | save->ucon = __raw_readl(regs + S3C2410_UCON); | ||
92 | save->ufcon = __raw_readl(regs + S3C2410_UFCON); | ||
93 | save->umcon = __raw_readl(regs + S3C2410_UMCON); | ||
94 | save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV); | ||
95 | |||
96 | if (pm_uart_udivslot) | ||
97 | save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT); | ||
98 | |||
99 | S3C_PMDBG("UART[%d]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n", | ||
100 | uart, save->ulcon, save->ucon, save->ufcon, save->ubrdiv); | ||
101 | } | ||
102 | |||
103 | static void s3c_pm_save_uarts(void) | ||
104 | { | ||
105 | s3c_pm_save_uart(CONFIG_DEBUG_S3C_UART, &uart_save); | ||
106 | } | ||
107 | |||
108 | static void s3c_pm_restore_uart(unsigned int uart, struct pm_uart_save *save) | ||
109 | { | ||
110 | void __iomem *regs = S3C_VA_UARTx(uart); | ||
111 | |||
112 | s3c_pm_arch_update_uart(regs, save); | ||
113 | |||
114 | __raw_writel(save->ulcon, regs + S3C2410_ULCON); | ||
115 | __raw_writel(save->ucon, regs + S3C2410_UCON); | ||
116 | __raw_writel(save->ufcon, regs + S3C2410_UFCON); | ||
117 | __raw_writel(save->umcon, regs + S3C2410_UMCON); | ||
118 | __raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV); | ||
119 | |||
120 | if (pm_uart_udivslot) | ||
121 | __raw_writel(save->udivslot, regs + S3C2443_DIVSLOT); | ||
122 | } | ||
123 | |||
124 | static void s3c_pm_restore_uarts(void) | ||
125 | { | ||
126 | s3c_pm_restore_uart(CONFIG_DEBUG_S3C_UART, &uart_save); | ||
127 | } | ||
128 | #else | ||
129 | static void s3c_pm_save_uarts(void) { } | ||
130 | static void s3c_pm_restore_uarts(void) { } | ||
131 | #endif | ||
132 | |||
133 | /* The IRQ ext-int code goes here, it is too small to currently bother | 44 | /* The IRQ ext-int code goes here, it is too small to currently bother |
134 | * with its own file. */ | 45 | * with its own file. */ |
135 | 46 | ||
@@ -154,62 +65,6 @@ int s3c_irqext_wake(struct irq_data *data, unsigned int state) | |||
154 | return 0; | 65 | return 0; |
155 | } | 66 | } |
156 | 67 | ||
157 | /* helper functions to save and restore register state */ | ||
158 | |||
159 | /** | ||
160 | * s3c_pm_do_save() - save a set of registers for restoration on resume. | ||
161 | * @ptr: Pointer to an array of registers. | ||
162 | * @count: Size of the ptr array. | ||
163 | * | ||
164 | * Run through the list of registers given, saving their contents in the | ||
165 | * array for later restoration when we wakeup. | ||
166 | */ | ||
167 | void s3c_pm_do_save(struct sleep_save *ptr, int count) | ||
168 | { | ||
169 | for (; count > 0; count--, ptr++) { | ||
170 | ptr->val = __raw_readl(ptr->reg); | ||
171 | S3C_PMDBG("saved %p value %08lx\n", ptr->reg, ptr->val); | ||
172 | } | ||
173 | } | ||
174 | |||
175 | /** | ||
176 | * s3c_pm_do_restore() - restore register values from the save list. | ||
177 | * @ptr: Pointer to an array of registers. | ||
178 | * @count: Size of the ptr array. | ||
179 | * | ||
180 | * Restore the register values saved from s3c_pm_do_save(). | ||
181 | * | ||
182 | * Note, we do not use S3C_PMDBG() in here, as the system may not have | ||
183 | * restore the UARTs state yet | ||
184 | */ | ||
185 | |||
186 | void s3c_pm_do_restore(const struct sleep_save *ptr, int count) | ||
187 | { | ||
188 | for (; count > 0; count--, ptr++) { | ||
189 | printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n", | ||
190 | ptr->reg, ptr->val, __raw_readl(ptr->reg)); | ||
191 | |||
192 | __raw_writel(ptr->val, ptr->reg); | ||
193 | } | ||
194 | } | ||
195 | |||
196 | /** | ||
197 | * s3c_pm_do_restore_core() - early restore register values from save list. | ||
198 | * | ||
199 | * This is similar to s3c_pm_do_restore() except we try and minimise the | ||
200 | * side effects of the function in case registers that hardware might need | ||
201 | * to work has been restored. | ||
202 | * | ||
203 | * WARNING: Do not put any debug in here that may effect memory or use | ||
204 | * peripherals, as things may be changing! | ||
205 | */ | ||
206 | |||
207 | void s3c_pm_do_restore_core(const struct sleep_save *ptr, int count) | ||
208 | { | ||
209 | for (; count > 0; count--, ptr++) | ||
210 | __raw_writel(ptr->val, ptr->reg); | ||
211 | } | ||
212 | |||
213 | /* s3c2410_pm_show_resume_irqs | 68 | /* s3c2410_pm_show_resume_irqs |
214 | * | 69 | * |
215 | * print any IRQs asserted at resume time (ie, we woke from) | 70 | * print any IRQs asserted at resume time (ie, we woke from) |
diff --git a/arch/arm/plat-samsung/s5p-dev-mfc.c b/arch/arm/plat-samsung/s5p-dev-mfc.c index ad51f85fbd01..98087b655df0 100644 --- a/arch/arm/plat-samsung/s5p-dev-mfc.c +++ b/arch/arm/plat-samsung/s5p-dev-mfc.c | |||
@@ -122,32 +122,35 @@ device_initcall(s5p_mfc_memory_init); | |||
122 | #endif | 122 | #endif |
123 | 123 | ||
124 | #ifdef CONFIG_OF | 124 | #ifdef CONFIG_OF |
125 | int __init s5p_fdt_find_mfc_mem(unsigned long node, const char *uname, | 125 | int __init s5p_fdt_alloc_mfc_mem(unsigned long node, const char *uname, |
126 | int depth, void *data) | 126 | int depth, void *data) |
127 | { | 127 | { |
128 | __be32 *prop; | 128 | __be32 *prop; |
129 | unsigned long len; | 129 | unsigned long len; |
130 | struct s5p_mfc_dt_meminfo *mfc_mem = data; | 130 | struct s5p_mfc_dt_meminfo mfc_mem; |
131 | 131 | ||
132 | if (!data) | 132 | if (!data) |
133 | return 0; | 133 | return 0; |
134 | 134 | ||
135 | if (!of_flat_dt_is_compatible(node, mfc_mem->compatible)) | 135 | if (!of_flat_dt_is_compatible(node, data)) |
136 | return 0; | 136 | return 0; |
137 | 137 | ||
138 | prop = of_get_flat_dt_prop(node, "samsung,mfc-l", &len); | 138 | prop = of_get_flat_dt_prop(node, "samsung,mfc-l", &len); |
139 | if (!prop || (len != 2 * sizeof(unsigned long))) | 139 | if (!prop || (len != 2 * sizeof(unsigned long))) |
140 | return 0; | 140 | return 0; |
141 | 141 | ||
142 | mfc_mem->loff = be32_to_cpu(prop[0]); | 142 | mfc_mem.loff = be32_to_cpu(prop[0]); |
143 | mfc_mem->lsize = be32_to_cpu(prop[1]); | 143 | mfc_mem.lsize = be32_to_cpu(prop[1]); |
144 | 144 | ||
145 | prop = of_get_flat_dt_prop(node, "samsung,mfc-r", &len); | 145 | prop = of_get_flat_dt_prop(node, "samsung,mfc-r", &len); |
146 | if (!prop || (len != 2 * sizeof(unsigned long))) | 146 | if (!prop || (len != 2 * sizeof(unsigned long))) |
147 | return 0; | 147 | return 0; |
148 | 148 | ||
149 | mfc_mem->roff = be32_to_cpu(prop[0]); | 149 | mfc_mem.roff = be32_to_cpu(prop[0]); |
150 | mfc_mem->rsize = be32_to_cpu(prop[1]); | 150 | mfc_mem.rsize = be32_to_cpu(prop[1]); |
151 | |||
152 | s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize, | ||
153 | mfc_mem.loff, mfc_mem.lsize); | ||
151 | 154 | ||
152 | return 1; | 155 | return 1; |
153 | } | 156 | } |
diff --git a/arch/arm/plat-samsung/s5p-dev-uart.c b/arch/arm/plat-samsung/s5p-dev-uart.c index cafa3deddcc1..8c4487af98c8 100644 --- a/arch/arm/plat-samsung/s5p-dev-uart.c +++ b/arch/arm/plat-samsung/s5p-dev-uart.c | |||
@@ -18,7 +18,6 @@ | |||
18 | 18 | ||
19 | #include <asm/mach/arch.h> | 19 | #include <asm/mach/arch.h> |
20 | #include <asm/mach/irq.h> | 20 | #include <asm/mach/irq.h> |
21 | #include <mach/hardware.h> | ||
22 | #include <mach/map.h> | 21 | #include <mach/map.h> |
23 | 22 | ||
24 | #include <plat/devs.h> | 23 | #include <plat/devs.h> |
diff --git a/arch/arm/plat-samsung/s5p-sleep.S b/arch/arm/plat-samsung/s5p-sleep.S index a030e7301da8..c5001659bdf8 100644 --- a/arch/arm/plat-samsung/s5p-sleep.S +++ b/arch/arm/plat-samsung/s5p-sleep.S | |||
@@ -23,18 +23,7 @@ | |||
23 | 23 | ||
24 | #include <linux/linkage.h> | 24 | #include <linux/linkage.h> |
25 | #include <asm/asm-offsets.h> | 25 | #include <asm/asm-offsets.h> |
26 | #include <asm/hardware/cache-l2x0.h> | ||
27 | 26 | ||
28 | #define CPU_MASK 0xff0ffff0 | ||
29 | #define CPU_CORTEX_A9 0x410fc090 | ||
30 | |||
31 | /* | ||
32 | * The following code is located into the .data section. This is to | ||
33 | * allow l2x0_regs_phys to be accessed with a relative load while we | ||
34 | * can't rely on any MMU translation. We could have put l2x0_regs_phys | ||
35 | * in the .text section as well, but some setups might insist on it to | ||
36 | * be truly read-only. (Reference from: arch/arm/kernel/sleep.S) | ||
37 | */ | ||
38 | .data | 27 | .data |
39 | .align | 28 | .align |
40 | 29 | ||
@@ -53,37 +42,5 @@ | |||
53 | */ | 42 | */ |
54 | 43 | ||
55 | ENTRY(s3c_cpu_resume) | 44 | ENTRY(s3c_cpu_resume) |
56 | #ifdef CONFIG_CACHE_L2X0 | ||
57 | mrc p15, 0, r0, c0, c0, 0 | ||
58 | ldr r1, =CPU_MASK | ||
59 | and r0, r0, r1 | ||
60 | ldr r1, =CPU_CORTEX_A9 | ||
61 | cmp r0, r1 | ||
62 | bne resume_l2on | ||
63 | adr r0, l2x0_regs_phys | ||
64 | ldr r0, [r0] | ||
65 | ldr r1, [r0, #L2X0_R_PHY_BASE] | ||
66 | ldr r2, [r1, #L2X0_CTRL] | ||
67 | tst r2, #0x1 | ||
68 | bne resume_l2on | ||
69 | ldr r2, [r0, #L2X0_R_AUX_CTRL] | ||
70 | str r2, [r1, #L2X0_AUX_CTRL] | ||
71 | ldr r2, [r0, #L2X0_R_TAG_LATENCY] | ||
72 | str r2, [r1, #L2X0_TAG_LATENCY_CTRL] | ||
73 | ldr r2, [r0, #L2X0_R_DATA_LATENCY] | ||
74 | str r2, [r1, #L2X0_DATA_LATENCY_CTRL] | ||
75 | ldr r2, [r0, #L2X0_R_PREFETCH_CTRL] | ||
76 | str r2, [r1, #L2X0_PREFETCH_CTRL] | ||
77 | ldr r2, [r0, #L2X0_R_PWR_CTRL] | ||
78 | str r2, [r1, #L2X0_POWER_CTRL] | ||
79 | mov r2, #1 | ||
80 | str r2, [r1, #L2X0_CTRL] | ||
81 | resume_l2on: | ||
82 | #endif | ||
83 | b cpu_resume | 45 | b cpu_resume |
84 | ENDPROC(s3c_cpu_resume) | 46 | ENDPROC(s3c_cpu_resume) |
85 | #ifdef CONFIG_CACHE_L2X0 | ||
86 | .globl l2x0_regs_phys | ||
87 | l2x0_regs_phys: | ||
88 | .long 0 | ||
89 | #endif | ||
diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c index 884187fbfe00..13eae14c2cc2 100644 --- a/drivers/clk/samsung/clk-exynos-audss.c +++ b/drivers/clk/samsung/clk-exynos-audss.c | |||
@@ -17,7 +17,7 @@ | |||
17 | #include <linux/module.h> | 17 | #include <linux/module.h> |
18 | #include <linux/platform_device.h> | 18 | #include <linux/platform_device.h> |
19 | 19 | ||
20 | #include <dt-bindings/clk/exynos-audss-clk.h> | 20 | #include <dt-bindings/clock/exynos-audss-clk.h> |
21 | 21 | ||
22 | enum exynos_audss_clk_type { | 22 | enum exynos_audss_clk_type { |
23 | TYPE_EXYNOS4210, | 23 | TYPE_EXYNOS4210, |
diff --git a/drivers/clk/versatile/clk-impd1.c b/drivers/clk/versatile/clk-impd1.c index 6d8b8e1a080a..31b44f025f9e 100644 --- a/drivers/clk/versatile/clk-impd1.c +++ b/drivers/clk/versatile/clk-impd1.c | |||
@@ -13,10 +13,12 @@ | |||
13 | #include <linux/io.h> | 13 | #include <linux/io.h> |
14 | #include <linux/platform_data/clk-integrator.h> | 14 | #include <linux/platform_data/clk-integrator.h> |
15 | 15 | ||
16 | #include <mach/impd1.h> | ||
17 | |||
18 | #include "clk-icst.h" | 16 | #include "clk-icst.h" |
19 | 17 | ||
18 | #define IMPD1_OSC1 0x00 | ||
19 | #define IMPD1_OSC2 0x04 | ||
20 | #define IMPD1_LOCK 0x08 | ||
21 | |||
20 | struct impd1_clk { | 22 | struct impd1_clk { |
21 | char *vco1name; | 23 | char *vco1name; |
22 | struct clk *vco1clk; | 24 | struct clk *vco1clk; |
diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c index 09dd0173ea0a..c812b93a52b2 100644 --- a/drivers/clk/zynq/clkc.c +++ b/drivers/clk/zynq/clkc.c | |||
@@ -21,34 +21,35 @@ | |||
21 | #include <linux/clk/zynq.h> | 21 | #include <linux/clk/zynq.h> |
22 | #include <linux/clk-provider.h> | 22 | #include <linux/clk-provider.h> |
23 | #include <linux/of.h> | 23 | #include <linux/of.h> |
24 | #include <linux/of_address.h> | ||
24 | #include <linux/slab.h> | 25 | #include <linux/slab.h> |
25 | #include <linux/string.h> | 26 | #include <linux/string.h> |
26 | #include <linux/io.h> | 27 | #include <linux/io.h> |
27 | 28 | ||
28 | static void __iomem *zynq_slcr_base_priv; | 29 | static void __iomem *zynq_clkc_base; |
29 | 30 | ||
30 | #define SLCR_ARMPLL_CTRL (zynq_slcr_base_priv + 0x100) | 31 | #define SLCR_ARMPLL_CTRL (zynq_clkc_base + 0x00) |
31 | #define SLCR_DDRPLL_CTRL (zynq_slcr_base_priv + 0x104) | 32 | #define SLCR_DDRPLL_CTRL (zynq_clkc_base + 0x04) |
32 | #define SLCR_IOPLL_CTRL (zynq_slcr_base_priv + 0x108) | 33 | #define SLCR_IOPLL_CTRL (zynq_clkc_base + 0x08) |
33 | #define SLCR_PLL_STATUS (zynq_slcr_base_priv + 0x10c) | 34 | #define SLCR_PLL_STATUS (zynq_clkc_base + 0x0c) |
34 | #define SLCR_ARM_CLK_CTRL (zynq_slcr_base_priv + 0x120) | 35 | #define SLCR_ARM_CLK_CTRL (zynq_clkc_base + 0x20) |
35 | #define SLCR_DDR_CLK_CTRL (zynq_slcr_base_priv + 0x124) | 36 | #define SLCR_DDR_CLK_CTRL (zynq_clkc_base + 0x24) |
36 | #define SLCR_DCI_CLK_CTRL (zynq_slcr_base_priv + 0x128) | 37 | #define SLCR_DCI_CLK_CTRL (zynq_clkc_base + 0x28) |
37 | #define SLCR_APER_CLK_CTRL (zynq_slcr_base_priv + 0x12c) | 38 | #define SLCR_APER_CLK_CTRL (zynq_clkc_base + 0x2c) |
38 | #define SLCR_GEM0_CLK_CTRL (zynq_slcr_base_priv + 0x140) | 39 | #define SLCR_GEM0_CLK_CTRL (zynq_clkc_base + 0x40) |
39 | #define SLCR_GEM1_CLK_CTRL (zynq_slcr_base_priv + 0x144) | 40 | #define SLCR_GEM1_CLK_CTRL (zynq_clkc_base + 0x44) |
40 | #define SLCR_SMC_CLK_CTRL (zynq_slcr_base_priv + 0x148) | 41 | #define SLCR_SMC_CLK_CTRL (zynq_clkc_base + 0x48) |
41 | #define SLCR_LQSPI_CLK_CTRL (zynq_slcr_base_priv + 0x14c) | 42 | #define SLCR_LQSPI_CLK_CTRL (zynq_clkc_base + 0x4c) |
42 | #define SLCR_SDIO_CLK_CTRL (zynq_slcr_base_priv + 0x150) | 43 | #define SLCR_SDIO_CLK_CTRL (zynq_clkc_base + 0x50) |
43 | #define SLCR_UART_CLK_CTRL (zynq_slcr_base_priv + 0x154) | 44 | #define SLCR_UART_CLK_CTRL (zynq_clkc_base + 0x54) |
44 | #define SLCR_SPI_CLK_CTRL (zynq_slcr_base_priv + 0x158) | 45 | #define SLCR_SPI_CLK_CTRL (zynq_clkc_base + 0x58) |
45 | #define SLCR_CAN_CLK_CTRL (zynq_slcr_base_priv + 0x15c) | 46 | #define SLCR_CAN_CLK_CTRL (zynq_clkc_base + 0x5c) |
46 | #define SLCR_CAN_MIOCLK_CTRL (zynq_slcr_base_priv + 0x160) | 47 | #define SLCR_CAN_MIOCLK_CTRL (zynq_clkc_base + 0x60) |
47 | #define SLCR_DBG_CLK_CTRL (zynq_slcr_base_priv + 0x164) | 48 | #define SLCR_DBG_CLK_CTRL (zynq_clkc_base + 0x64) |
48 | #define SLCR_PCAP_CLK_CTRL (zynq_slcr_base_priv + 0x168) | 49 | #define SLCR_PCAP_CLK_CTRL (zynq_clkc_base + 0x68) |
49 | #define SLCR_FPGA0_CLK_CTRL (zynq_slcr_base_priv + 0x170) | 50 | #define SLCR_FPGA0_CLK_CTRL (zynq_clkc_base + 0x70) |
50 | #define SLCR_621_TRUE (zynq_slcr_base_priv + 0x1c4) | 51 | #define SLCR_621_TRUE (zynq_clkc_base + 0xc4) |
51 | #define SLCR_SWDT_CLK_SEL (zynq_slcr_base_priv + 0x304) | 52 | #define SLCR_SWDT_CLK_SEL (zynq_clkc_base + 0x204) |
52 | 53 | ||
53 | #define NUM_MIO_PINS 54 | 54 | #define NUM_MIO_PINS 54 |
54 | 55 | ||
@@ -569,8 +570,42 @@ static void __init zynq_clk_setup(struct device_node *np) | |||
569 | 570 | ||
570 | CLK_OF_DECLARE(zynq_clkc, "xlnx,ps7-clkc", zynq_clk_setup); | 571 | CLK_OF_DECLARE(zynq_clkc, "xlnx,ps7-clkc", zynq_clk_setup); |
571 | 572 | ||
572 | void __init zynq_clock_init(void __iomem *slcr_base) | 573 | void __init zynq_clock_init(void) |
573 | { | 574 | { |
574 | zynq_slcr_base_priv = slcr_base; | 575 | struct device_node *np; |
575 | of_clk_init(NULL); | 576 | struct device_node *slcr; |
577 | struct resource res; | ||
578 | |||
579 | np = of_find_compatible_node(NULL, NULL, "xlnx,ps7-clkc"); | ||
580 | if (!np) { | ||
581 | pr_err("%s: clkc node not found\n", __func__); | ||
582 | goto np_err; | ||
583 | } | ||
584 | |||
585 | if (of_address_to_resource(np, 0, &res)) { | ||
586 | pr_err("%s: failed to get resource\n", np->name); | ||
587 | goto np_err; | ||
588 | } | ||
589 | |||
590 | slcr = of_get_parent(np); | ||
591 | |||
592 | if (slcr->data) { | ||
593 | zynq_clkc_base = (__force void __iomem *)slcr->data + res.start; | ||
594 | } else { | ||
595 | pr_err("%s: Unable to get I/O memory\n", np->name); | ||
596 | of_node_put(slcr); | ||
597 | goto np_err; | ||
598 | } | ||
599 | |||
600 | pr_info("%s: clkc starts at %p\n", __func__, zynq_clkc_base); | ||
601 | |||
602 | of_node_put(slcr); | ||
603 | of_node_put(np); | ||
604 | |||
605 | return; | ||
606 | |||
607 | np_err: | ||
608 | of_node_put(np); | ||
609 | BUG(); | ||
610 | return; | ||
576 | } | 611 | } |
diff --git a/include/dt-bindings/clk/exynos-audss-clk.h b/include/dt-bindings/clock/exynos-audss-clk.h index 0ae6f5a75d2a..0ae6f5a75d2a 100644 --- a/include/dt-bindings/clk/exynos-audss-clk.h +++ b/include/dt-bindings/clock/exynos-audss-clk.h | |||
diff --git a/include/linux/clk/zynq.h b/include/linux/clk/zynq.h index e062d317ccce..7a5633b71533 100644 --- a/include/linux/clk/zynq.h +++ b/include/linux/clk/zynq.h | |||
@@ -22,7 +22,7 @@ | |||
22 | 22 | ||
23 | #include <linux/spinlock.h> | 23 | #include <linux/spinlock.h> |
24 | 24 | ||
25 | void zynq_clock_init(void __iomem *slcr); | 25 | void zynq_clock_init(void); |
26 | 26 | ||
27 | struct clk *clk_register_zynq_pll(const char *name, const char *parent, | 27 | struct clk *clk_register_zynq_pll(const char *name, const char *parent, |
28 | void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index, | 28 | void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index, |
diff --git a/include/linux/serial_s3c.h b/include/linux/serial_s3c.h index 907d9d1d56cf..e6fc9567690b 100644 --- a/include/linux/serial_s3c.h +++ b/include/linux/serial_s3c.h | |||
@@ -233,6 +233,8 @@ | |||
233 | 233 | ||
234 | #ifndef __ASSEMBLY__ | 234 | #ifndef __ASSEMBLY__ |
235 | 235 | ||
236 | #include <linux/serial_core.h> | ||
237 | |||
236 | /* configuration structure for per-machine configurations for the | 238 | /* configuration structure for per-machine configurations for the |
237 | * serial port | 239 | * serial port |
238 | * | 240 | * |