Merge tag 'tags/cleanup2-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC late cleanups from Arnd Bergmann: "These could not be part of the first cleanup branch, because they either came too late in the cycle, or they have dependencies on other branches. Important changes are: - The integrator platform is almost multiplatform capable after some reorganization (Linus Walleij) - Minor cleanups on Zynq (Michal Simek) - Lots of changes for Exynos and other Samsung platforms, including further preparations for multiplatform support and the clocks bindings are rearranged" * tag 'tags/cleanup2-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (54 commits) devicetree: fix newly added exynos sata bindings ARM: EXYNOS: Fix compilation error in cpuidle.c ARM: S5P64X0: Explicitly include linux/serial_s3c.h in mach/pm-core.h ARM: EXYNOS: Remove hardware.h file ARM: SAMSUNG: Remove hardware.h inclusion ARM: S3C24XX: Remove invalid code from hardware.h dt-bindings: clock: Move exynos-audss-clk.h to dt-bindings/clock ARM: dts: Keep some essential LDOs enabled for arndale-octa board ARM: dts: Disable MDMA1 node for arndale-octa board ARM: S3C64XX: Fix build for implicit serial_s3c.h inclusion serial: s3c: Fix build of header without serial_core.h preinclusion ARM: EXYNOS: Allow wake-up using GIC interrupts ARM: EXYNOS: Stop using legacy Samsung PM code ARM: EXYNOS: Remove PM initcalls and useless indirection ARM: EXYNOS: Fix abuse of CONFIG_PM ARM: SAMSUNG: Move s3c_pm_check_* prototypes to plat/pm-common.h ARM: SAMSUNG: Move common save/restore helpers to separate file ARM: SAMSUNG: Move Samsung PM debug code into separate file ARM: SAMSUNG: Consolidate PM debug functions ARM: SAMSUNG: Use debug_ll_addr() to get UART base address ...
author: Linus Torvalds <torvalds@linux-foundation.org> 2014-04-05 18:46:37 -0400
committer: Linus Torvalds <torvalds@linux-foundation.org> 2014-04-05 18:46:37 -0400
commit: 2bf73dd61a84cdf27e49f48e08739af6ba70ace1 (patch)
tree: 225876ce1530ba6c3a96621a531f47e963fee691
parent: d2b150d0647e055d7a71b1c33140280550b27dd6 (diff)
parent: 9dfbff16b422a4bac7ad309847c7bc5d65653392 (diff)
92 files changed, 1156 insertions, 1369 deletions
diff --git a/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt b/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
deleted file mode 100644
index 37824fac688e..000000000000
--- a/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-* Samsung SATA PHY Controller
-SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
-Each SATA PHY controller should have its own node.
-Required properties:
- compatible        : compatible list, contains "samsung,exynos5-sata-phy"
- reg               : <registers mapping>
-Example:
-        sata@ffe07000 {
-                compatible = "samsung,exynos5-sata-phy";
-                reg = <0xffe07000 0x1000>;
-        };
diff --git a/Documentation/devicetree/bindings/ata/exynos-sata.txt b/Documentation/devicetree/bindings/ata/exynos-sata.txt
index 0849f1025e34..cb48448247ea 100644
--- a/Documentation/devicetree/bindings/ata/exynos-sata.txt
+++ b/Documentation/devicetree/bindings/ata/exynos-sata.txt
@@ -4,14 +4,27 @@ SATA nodes are defined to describe on-chip Serial ATA controllers.
 Each SATA controller should have its own node.
 Required properties:
- compatible        : compatible list, contains "samsung,exynos5-sata"
+- compatible            : compatible list, contains "samsung,exynos5-sata"
- interrupts        : <interrupt mapping for SATA IRQ>
+- interrupts            : <interrupt mapping for SATA IRQ>
- reg               : <registers mapping>
+- reg                   : <registers mapping>
- samsung,sata-freq : <frequency in MHz>
+- samsung,sata-freq     : <frequency in MHz>
+- phys                  : Must contain exactly one entry as specified
+                          in phy-bindings.txt
+- phy-names             : Must be "sata-phy"
+Optional properties:
+- clocks                : Must contain an entry for each entry in clock-names.
+- clock-names           : Shall be "sata" for the external SATA bus clock,
+                          and "sclk_sata" for the internal controller clock.
 Example:
-        sata@ffe08000 {
+        sata@122f0000 {
-                compatible = "samsung,exynos5-sata";
+                compatible = "snps,dwc-ahci";
-                reg = <0xffe08000 0x1000>;
+                samsung,sata-freq = <66>;
-                interrupts = <115>;
+                reg = <0x122f0000 0x1ff>;
-        };
+                interrupts = <0 115 0>;
+                clocks = <&clock 277>, <&clock 143>;
+                clock-names = "sata", "sclk_sata";
+                phys = <&sata_phy>;
+                phy-names = "sata-phy";
+        };
diff --git a/Documentation/devicetree/bindings/clock/zynq-7000.txt b/Documentation/devicetree/bindings/clock/zynq-7000.txt
index 17b4a94916d6..d93746cf2975 100644
--- a/Documentation/devicetree/bindings/clock/zynq-7000.txt
+++ b/Documentation/devicetree/bindings/clock/zynq-7000.txt
@@ -14,6 +14,7 @@ for all clock consumers of PS clocks.
 Required properties:
 - #clock-cells : Must be 1
 - compatible : "xlnx,ps7-clkc"
+ - reg : SLCR offset and size taken via syscon < 0x100 0x100 >
 - ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ
                      (usually 33 MHz oscillators are used for Zynq platforms)
 - clock-output-names : List of strings used to name the clock outputs. Shall be
@@ -87,10 +88,11 @@ Clock outputs:
 47: dbg_apb
 Example:
-        clkc: clkc {
+        clkc: clkc@100 {
                #clock-cells = <1>;
                compatible = "xlnx,ps7-clkc";
                ps-clk-frequency = <33333333>;
+                reg = <0x100 0x100>;
                clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
                                "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
                                "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index 28f9edb8f19c..b422e38946d7 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -74,3 +74,43 @@ phy-consumer@12340000 {
 Refer to DT bindings documentation of particular PHY consumer devices for more
 information about required PHYs and the way of specification.
+Samsung SATA PHY Controller
+---------------------------
+SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
+Each SATA PHY controller should have its own node.
+Required properties:
+- compatible        : compatible list, contains "samsung,exynos5250-sata-phy"
+- reg : offset and length of the SATA PHY register set;
+- #phy-cells : must be zero
+- clocks : must be exactly one entry
+- clock-names : must be "sata_phyctrl"
+- samsung,exynos-sataphy-i2c-phandle : a phandle to the I2C device, no arguments
+- samsung,syscon-phandle : a phandle to the PMU system controller, no arguments
+Example:
+        sata_phy: sata-phy@12170000 {
+                compatible = "samsung,exynos5250-sata-phy";
+                reg = <0x12170000 0x1ff>;
+                clocks = <&clock 287>;
+                clock-names = "sata_phyctrl";
+                #phy-cells = <0>;
+                samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
+                samsung,syscon-phandle = <&pmu_syscon>;
+        };
+Device-Tree bindings for sataphy i2c client driver
+--------------------------------------------------
+Required properties:
+compatible: Should be "samsung,exynos-sataphy-i2c"
+- reg: I2C address of the sataphy i2c device.
+Example:
+        sata_phy_i2c:sata-phy@38 {
+                compatible = "samsung,exynos-sataphy-i2c";
+                reg = <0x38>;
+        };
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 8983919a4421..4a2fc0bf6fc9 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -1141,7 +1141,7 @@ config DEBUG_UART_8250_FLOW_CONTROL
 config DEBUG_UNCOMPRESS
        bool
-        depends on ARCH_MULTIPLATFORM || ARCH_MSM || ARCH_EXYNOS
+        depends on ARCH_MULTIPLATFORM || ARCH_MSM || PLAT_SAMSUNG
        default y if DEBUG_LL && !DEBUG_OMAP2PLUS_UART && \
                     (!DEBUG_TEGRA_UART || !ZBOOT_ROM)
        help
@@ -1158,7 +1158,7 @@ config DEBUG_UNCOMPRESS
 config UNCOMPRESS_INCLUDE
        string
        default "debug/uncompress.h" if ARCH_MULTIPLATFORM || ARCH_MSM || \
-                                        ARCH_EXYNOS || ARCH_EFM32
+                                        PLAT_SAMSUNG || ARCH_EFM32
        default "mach/uncompress.h"
 config EARLY_PRINTK
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 28b5ec79f339..0401f4dba2a2 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -86,6 +86,11 @@
                reg = <0x10023CE0 0x20>;
        };
+        pd_gps_alive: gps-alive-power-domain@10023D00 {
+                compatible = "samsung,exynos4210-pd";
+                reg = <0x10023D00 0x20>;
+        };
        gic: interrupt-controller@10490000 {
                compatible = "arm,cortex-a9-gic";
                #interrupt-cells = <3>;
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index 2aa13cb3bbed..72fb11f7ea21 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -19,7 +19,7 @@
 / {
        model = "Insignal Origen evaluation board based on Exynos4210";
-        compatible = "insignal,origen", "samsung,exynos4210";
+        compatible = "insignal,origen", "samsung,exynos4210", "samsung,exynos4";
        memory {
                reg = <0x40000000 0x10000000
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 9c01b718d29d..636d16684750 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -19,7 +19,7 @@
 / {
        model = "Samsung smdkv310 evaluation board based on Exynos4210";
-        compatible = "samsung,smdkv310", "samsung,exynos4210";
+        compatible = "samsung,smdkv310", "samsung,exynos4210", "samsung,exynos4";
        memory {
                reg = <0x40000000 0x80000000>;
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index 63cc571ca307..361cb58052bf 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -17,7 +17,7 @@
 / {
        model = "Samsung Trats based on Exynos4210";
-        compatible = "samsung,trats", "samsung,exynos4210";
+        compatible = "samsung,trats", "samsung,exynos4210", "samsung,exynos4";
        memory {
                reg =  <0x40000000 0x10000000
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index d2e3f5f5916d..27d3b70ee9e3 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -17,7 +17,7 @@
 / {
        model = "Samsung Universal C210 based on Exynos4210 rev0";
-        compatible = "samsung,universal_c210", "samsung,exynos4210";
+        compatible = "samsung,universal_c210", "samsung,exynos4210", "samsung,exynos4";
        memory {
                reg =  <0x40000000 0x10000000
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index cb0e768dc6d4..cacf6140dd2f 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -23,7 +23,7 @@
 #include "exynos4210-pinctrl.dtsi"
 / {
-        compatible = "samsung,exynos4210";
+        compatible = "samsung,exynos4210", "samsung,exynos4";
        aliases {
                pinctrl0 = &pinctrl_0;
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
index 94a43f9a05e2..3c00e6ec9302 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -20,18 +20,13 @@
 #include "exynos4x12.dtsi"
 / {
-        compatible = "samsung,exynos4212";
+        compatible = "samsung,exynos4212", "samsung,exynos4";
-        gic: interrupt-controller@10490000 {
+        combiner: interrupt-controller@10440000 {
-                cpu-offset = <0x8000>;
+                samsung,combiner-nr = <18>;
        };
-        interrupt-controller@10440000 {
+        gic: interrupt-controller@10490000 {
-                samsung,combiner-nr = <18>;
+                cpu-offset = <0x8000>;
-                interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
-                             <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
-                             <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
-                             <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
-                             <0 107 0>, <0 108 0>;
        };
 };
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 12459b01cca3..31db28a4bb33 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -16,7 +16,7 @@
 / {
        model = "Hardkernel ODROID-X board based on Exynos4412";
-        compatible = "hardkernel,odroid-x", "samsung,exynos4412";
+        compatible = "hardkernel,odroid-x", "samsung,exynos4412", "samsung,exynos4";
        memory {
                reg = <0x40000000 0x40000000>;
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
index 388f03579661..e2c0dcab4d81 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -17,7 +17,7 @@
 / {
        model = "Insignal Origen evaluation board based on Exynos4412";
-        compatible = "insignal,origen4412", "samsung,exynos4412";
+        compatible = "insignal,origen4412", "samsung,exynos4412", "samsung,exynos4";
        memory {
                reg = <0x40000000 0x40000000>;
diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts
index ad316a1ee9e0..ded0b70f7644 100644
--- a/arch/arm/boot/dts/exynos4412-smdk4412.dts
+++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts
@@ -17,7 +17,7 @@
 / {
        model = "Samsung SMDK evaluation board based on Exynos4412";
-        compatible = "samsung,smdk4412", "samsung,exynos4412";
+        compatible = "samsung,smdk4412", "samsung,exynos4412", "samsung,exynos4";
        memory {
                reg = <0x40000000 0x40000000>;
diff --git a/arch/arm/boot/dts/exynos4412-tiny4412.dts b/arch/arm/boot/dts/exynos4412-tiny4412.dts
index 0a9831256b33..ea6929d9c621 100644
--- a/arch/arm/boot/dts/exynos4412-tiny4412.dts
+++ b/arch/arm/boot/dts/exynos4412-tiny4412.dts
@@ -16,7 +16,7 @@
 / {
        model = "FriendlyARM TINY4412 board based on Exynos4412";
-        compatible = "friendlyarm,tiny4412", "samsung,exynos4412";
+        compatible = "friendlyarm,tiny4412", "samsung,exynos4412", "samsung,exynos4";
        memory {
                reg = <0x40000000 0x40000000>;
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
index 4f851ccf40eb..c16b3159b813 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -17,7 +17,7 @@
 / {
        model = "Samsung Trats 2 based on Exynos4412";
-        compatible = "samsung,trats2", "samsung,exynos4412";
+        compatible = "samsung,trats2", "samsung,exynos4412", "samsung,exynos4";
        aliases {
                i2c8 = &i2c_ak8975;
@@ -106,6 +106,11 @@
                };
        };
+        adc: adc@126C0000 {
+                vdd-supply = <&ldo3_reg>;
+                status = "okay";
+        };
        i2c@13890000 {
                samsung,i2c-sda-delay = <100>;
                samsung,i2c-slave-addr = <0x10>;
@@ -589,4 +594,20 @@
                        };
                };
        };
+        thermistor-ap@0 {
+                compatible = "ntc,ncp15wb473";
+                pullup-uv = <1800000>;   /* VCC_1.8V_AP */
+                pullup-ohm = <100000>;   /* 100K */
+                pulldown-ohm = <100000>; /* 100K */
+                io-channels = <&adc 1>;  /* AP temperature */
+        };
+        thermistor-battery@1 {
+                compatible = "ntc,ncp15wb473";
+                pullup-uv = <1800000>;   /* VCC_1.8V_AP */
+                pullup-ohm = <100000>;   /* 100K */
+                pulldown-ohm = <100000>; /* 100K */
+                io-channels = <&adc 2>;  /* Battery temperature */
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index 87b339c739de..15d3c0ac2f5f 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -20,19 +20,13 @@
 #include "exynos4x12.dtsi"
 / {
-        compatible = "samsung,exynos4412";
+        compatible = "samsung,exynos4412", "samsung,exynos4";
-        gic: interrupt-controller@10490000 {
+        combiner: interrupt-controller@10440000 {
-                cpu-offset = <0x4000>;
-        };
-        interrupt-controller@10440000 {
                samsung,combiner-nr = <20>;
-                interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
-                             <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
-                             <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
-                             <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
-                             <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
        };
+        gic: interrupt-controller@10490000 {
+                cpu-offset = <0x4000>;
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index e0eb6bb64c34..c4a9306f8529 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -31,6 +31,12 @@
                mshc0 = &mshc_0;
        };
+        pmu {
+                compatible = "arm,cortex-a9-pmu";
+                interrupt-parent = <&combiner>;
+                interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
+        };
        pd_isp: isp-power-domain@10023CA0 {
                compatible = "samsung,exynos4210-pd";
                reg = <0x10023CA0 0x20>;
@@ -62,6 +68,14 @@
                };
        };
+        combiner: interrupt-controller@10440000 {
+                interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+                             <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+                             <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+                             <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
+                             <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
+        };
        pinctrl_0: pinctrl@11400000 {
                compatible = "samsung,exynos4x12-pinctrl";
                reg = <0x11400000 0x1000>;
@@ -80,6 +94,18 @@
                };
        };
+        adc: adc@126C0000 {
+                compatible = "samsung,exynos-adc-v1";
+                reg = <0x126C0000 0x100>, <0x10020718 0x4>;
+                interrupt-parent = <&combiner>;
+                interrupts = <10 3>;
+                clocks = <&clock CLK_TSADC>;
+                clock-names = "adc";
+                #io-channel-cells = <1>;
+                io-channel-ranges;
+                status = "disabled";
+        };
        pinctrl_2: pinctrl@03860000 {
                compatible = "samsung,exynos4x12-pinctrl";
                reg = <0x03860000 0x1000>;
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index 38b96a4cba6d..090f9830b129 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -15,7 +15,7 @@
 / {
        model = "Insignal Arndale evaluation board based on EXYNOS5250";
-        compatible = "insignal,arndale", "samsung,exynos5250";
+        compatible = "insignal,arndale", "samsung,exynos5250", "samsung,exynos5";
        memory {
                reg = <0x40000000 0x80000000>;
@@ -375,6 +375,27 @@
                };
        };
+        i2c@121D0000 {
+                status = "okay";
+                samsung,i2c-sda-delay = <100>;
+                samsung,i2c-max-bus-freq = <40000>;
+                samsung,i2c-slave-addr = <0x38>;
+                sata_phy_i2c:sata-phy@38 {
+                        compatible = "samsung,exynos-sataphy-i2c";
+                        reg = <0x38>;
+                };
+        };
+        sata@122F0000 {
+                status = "okay";
+        };
+        sata-phy@12170000 {
+                status = "okay";
+                samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
+        };
        mmc_0: mmc@12200000 {
                status = "okay";
                num-slots = <1>;
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index f76946e97e6a..a794a705d404 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -14,7 +14,7 @@
 / {
        model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
-        compatible = "samsung,smdk5250", "samsung,exynos5250";
+        compatible = "samsung,smdk5250", "samsung,exynos5250", "samsung,exynos5";
        aliases {
        };
@@ -242,16 +242,12 @@
                samsung,i2c-slave-addr = <0x38>;
                status = "okay";
-                sata-phy {
+                sata_phy_i2c:sata-phy@38 {
-                        compatible = "samsung,sata-phy";
+                        compatible = "samsung,exynos-sataphy-i2c";
                        reg = <0x38>;
                };
        };
-        sata@122F0000 {
-                samsung,sata-freq = <66>;
-        };
        i2c@12C80000 {
                samsung,i2c-sda-delay = <100>;
                samsung,i2c-max-bus-freq = <66000>;
@@ -274,6 +270,15 @@
                };
        };
+        sata@122F0000 {
+                status = "okay";
+        };
+        sata-phy@12170000 {
+                status = "okay";
+                samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
+        };
        mmc@12200000 {
                status = "okay";
                num-slots = <1>;
@@ -310,10 +315,6 @@
                };
        };
-        spi_0: spi@12d20000 {
-                status = "disabled";
-        };
        spi_1: spi@12d30000 {
                status = "okay";
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index b13bf499f5e2..1ce1088a00fb 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -14,7 +14,7 @@
 / {
        model = "Google Snow";
-        compatible = "google,snow", "samsung,exynos5250";
+        compatible = "google,snow", "samsung,exynos5250", "samsung,exynos5";
        aliases {
                i2c104 = &i2c_104;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 987cfbe9634b..37423314a028 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -21,10 +21,10 @@
 #include "exynos5.dtsi"
 #include "exynos5250-pinctrl.dtsi"
-#include <dt-bindings/clk/exynos-audss-clk.h>
+#include <dt-bindings/clock/exynos-audss-clk.h>
 / {
-        compatible = "samsung,exynos5250";
+        compatible = "samsung,exynos5250", "samsung,exynos5";
        aliases {
                spi0 = &spi_0;
@@ -47,6 +47,7 @@
                i2c6 = &i2c_6;
                i2c7 = &i2c_7;
                i2c8 = &i2c_8;
+                i2c9 = &i2c_9;
                pinctrl0 = &pinctrl_0;
                pinctrl1 = &pinctrl_1;
                pinctrl2 = &pinctrl_2;
@@ -235,16 +236,25 @@
        };
        sata@122F0000 {
-                compatible = "samsung,exynos5-sata-ahci";
+                compatible = "snps,dwc-ahci";
+                samsung,sata-freq = <66>;
                reg = <0x122F0000 0x1ff>;
                interrupts = <0 115 0>;
                clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
                clock-names = "sata", "sclk_sata";
+                phys = <&sata_phy>;
+                phy-names = "sata-phy";
+                status = "disabled";
        };
-        sata-phy@12170000 {
+        sata_phy: sata-phy@12170000 {
-                compatible = "samsung,exynos5-sata-phy";
+                compatible = "samsung,exynos5250-sata-phy";
                reg = <0x12170000 0x1ff>;
+                clocks = <&clock 287>;
+                clock-names = "sata_phyctrl";
+                #phy-cells = <0>;
+                samsung,syscon-phandle = <&pmu_system_controller>;
+                status = "disabled";
        };
        i2c_0: i2c@12C60000 {
@@ -362,7 +372,7 @@
                status = "disabled";
        };
-        i2c@121D0000 {
+        i2c_9: i2c@121D0000 {
                compatible = "samsung,exynos5-sata-phy-i2c";
                reg = <0x121D0000 0x100>;
                #address-cells = <1>;
@@ -718,4 +728,12 @@
                io-channel-ranges;
                status = "disabled";
        };
+        sss@10830000 {
+                compatible = "samsung,exynos4210-secss";
+                reg = <0x10830000 0x10000>;
+                interrupts = <0 112 0>;
+                clocks = <&clock 348>;
+                clock-names = "secss";
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index f509e8fc290f..80a3bf4c5986 100644
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -16,7 +16,7 @@
 / {
        model = "Insignal Arndale Octa evaluation board based on EXYNOS5420";
-        compatible = "insignal,arndale-octa", "samsung,exynos5420";
+        compatible = "insignal,arndale-octa", "samsung,exynos5420", "samsung,exynos5";
        memory {
                reg = <0x20000000 0x80000000>;
@@ -113,6 +113,7 @@
                                        regulator-name = "PVDD_APIO_MMCON_1V8";
                                        regulator-min-microvolt = <1800000>;
                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
                                };
                                ldo4_reg: LDO4 {
@@ -150,6 +151,7 @@
                                        regulator-name = "PVDD_USB_3V3";
                                        regulator-min-microvolt = <3000000>;
                                        regulator-max-microvolt = <3000000>;
+                                        regulator-always-on;
                                };
                                ldo10_reg: LDO10 {
@@ -218,6 +220,7 @@
                                        regulator-name = "PVDD_MIFS_1V1";
                                        regulator-min-microvolt = <1200000>;
                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
                                };
                                ldo24_reg: LDO24 {
@@ -361,4 +364,16 @@
                        gpio-key,wakeup;
                };
        };
+        amba {
+                mdma1: mdma@11C10000 {
+                        /*
+                         * MDMA1 can support both secure and non-secure
+                         * AXI transactions. When this is enabled in the kernel
+                         * for boards that run in secure mode, we are getting
+                         * imprecise external aborts causing the kernel to oops.
+                         */
+                        status = "disabled";
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index ae1ee0470fca..69104850eb5e 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -14,7 +14,7 @@
 / {
        model = "Samsung SMDK5420 board based on EXYNOS5420";
-        compatible = "samsung,smdk5420", "samsung,exynos5420";
+        compatible = "samsung,smdk5420", "samsung,exynos5420", "samsung,exynos5";
        memory {
                reg = <0x20000000 0x80000000>;
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index e3329afbd8c4..c3a9a66c5767 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -17,10 +17,10 @@
 #include "exynos5.dtsi"
 #include "exynos5420-pinctrl.dtsi"
-#include <dt-bindings/clk/exynos-audss-clk.h>
+#include <dt-bindings/clock/exynos-audss-clk.h>
 / {
-        compatible = "samsung,exynos5420";
+        compatible = "samsung,exynos5420", "samsung,exynos5";
        aliases {
                mshc0 = &mmc_0;
@@ -723,4 +723,13 @@
                clock-names = "watchdog";
                samsung,syscon-phandle = <&pmu_system_controller>;
        };
+        sss@10830000 {
+                compatible = "samsung,exynos4210-secss";
+                reg = <0x10830000 0x10000>;
+                interrupts = <0 112 0>;
+                clocks = <&clock 471>;
+                clock-names = "secss";
+                samsung,power-domain = <&g2d_pd>;
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5440-sd5v1.dts b/arch/arm/boot/dts/exynos5440-sd5v1.dts
index 777fb1c2c70f..268609a42b2c 100644
--- a/arch/arm/boot/dts/exynos5440-sd5v1.dts
+++ b/arch/arm/boot/dts/exynos5440-sd5v1.dts
@@ -14,7 +14,7 @@
 / {
        model = "SAMSUNG SD5v1 board based on EXYNOS5440";
-        compatible = "samsung,sd5v1", "samsung,exynos5440";
+        compatible = "samsung,sd5v1", "samsung,exynos5440", "samsung,exynos5";
        chosen {
                bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel earlyprintk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200";
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
index d58cb787061a..ff55dac6e219 100644
--- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
+++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
@@ -14,7 +14,7 @@
 / {
        model = "SAMSUNG SSDK5440 board based on EXYNOS5440";
-        compatible = "samsung,ssdk5440", "samsung,exynos5440";
+        compatible = "samsung,ssdk5440", "samsung,exynos5440", "samsung,exynos5";
        chosen {
                bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel earlyprintk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200";
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index 75c7b89cec2f..84f77c2fe4d4 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -13,7 +13,7 @@
 #include "skeleton.dtsi"
 / {
-        compatible = "samsung,exynos5440";
+        compatible = "samsung,exynos5440", "samsung,exynos5";
        interrupt-parent = <&gic>;
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 286a840e3dce..511180769af5 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -129,30 +129,28 @@
                } ;
                slcr: slcr@f8000000 {
-                        compatible = "xlnx,zynq-slcr";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "xlnx,zynq-slcr", "syscon";
                        reg = <0xF8000000 0x1000>;
+                        ranges;
-                        clocks {
+                        clkc: clkc@100 {
-                                #address-cells = <1>;
+                                #clock-cells = <1>;
-                                #size-cells = <0>;
+                                compatible = "xlnx,ps7-clkc";
+                                ps-clk-frequency = <33333333>;
-                                clkc: clkc {
+                                fclk-enable = <0>;
-                                        #clock-cells = <1>;
+                                clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
-                                        compatible = "xlnx,ps7-clkc";
+                                                "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
-                                        ps-clk-frequency = <33333333>;
+                                                "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
-                                        fclk-enable = <0>;
+                                                "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
-                                        clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
+                                                "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
-                                                        "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
+                                                "dma", "usb0_aper", "usb1_aper", "gem0_aper",
-                                                        "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
+                                                "gem1_aper", "sdio0_aper", "sdio1_aper",
-                                                        "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
+                                                "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
-                                                        "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
+                                                "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
-                                                        "dma", "usb0_aper", "usb1_aper", "gem0_aper",
+                                                "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
-                                                        "gem1_aper", "sdio0_aper", "sdio1_aper",
+                                                "dbg_trc", "dbg_apb";
-                                                        "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
+                                reg = <0x100 0x100>;
-                                                        "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
-                                                        "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
-                                                        "dbg_trc", "dbg_apb";
-                                };
                        };
                };
diff --git a/arch/arm/include/debug/zynq.S b/arch/arm/include/debug/zynq.S
index f9aa9740a73f..0b762fafa758 100644
--- a/arch/arm/include/debug/zynq.S
+++ b/arch/arm/include/debug/zynq.S
@@ -42,6 +42,9 @@
                .endm
                .macro  waituart,rd,rx
+1001:           ldr     \rd, [\rx, #UART_SR_OFFSET]
+                tst     \rd, #UART_SR_TXEMPTY
+                beq     1001b
                .endm
                .macro  busyuart,rd,rx
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 8d197dcdd2c0..fc8bf18e222d 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -24,7 +24,7 @@ config ARCH_EXYNOS4
        select HAVE_SMP
        select MIGHT_HAVE_CACHE_L2X0
        select PINCTRL
-        select PM_GENERIC_DOMAINS if PM
+        select PM_GENERIC_DOMAINS if PM_RUNTIME
        select S5P_DEV_MFC
        help
          Samsung EXYNOS4 SoCs based systems
@@ -46,10 +46,8 @@ config CPU_EXYNOS4210
        default y
        depends on ARCH_EXYNOS4
        select ARCH_HAS_BANDGAP
-        select ARM_CPU_SUSPEND if PM
+        select ARM_CPU_SUSPEND if PM_SLEEP
        select PINCTRL_EXYNOS
-        select S5P_PM if PM
-        select S5P_SLEEP if PM
        select SAMSUNG_DMADEV
        help
          Enable EXYNOS4210 CPU support
@@ -60,8 +58,6 @@ config SOC_EXYNOS4212
        depends on ARCH_EXYNOS4
        select ARCH_HAS_BANDGAP
        select PINCTRL_EXYNOS
-        select S5P_PM if PM
-        select S5P_SLEEP if PM
        select SAMSUNG_DMADEV
        help
          Enable EXYNOS4212 SoC support
@@ -82,9 +78,7 @@ config SOC_EXYNOS5250
        depends on ARCH_EXYNOS5
        select ARCH_HAS_BANDGAP
        select PINCTRL_EXYNOS
-        select PM_GENERIC_DOMAINS if PM
+        select PM_GENERIC_DOMAINS if PM_RUNTIME
-        select S5P_PM if PM
-        select S5P_SLEEP if PM
        select S5P_DEV_MFC
        select SAMSUNG_DMADEV
        help
@@ -94,9 +88,7 @@ config SOC_EXYNOS5420
        bool "SAMSUNG EXYNOS5420"
        default y
        depends on ARCH_EXYNOS5
-        select PM_GENERIC_DOMAINS if PM
+        select PM_GENERIC_DOMAINS if PM_RUNTIME
-        select S5P_PM if PM
-        select S5P_SLEEP if PM
        help
          Enable EXYNOS5420 SoC support
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 8930b66b4abd..a656dbe3b78c 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -12,9 +12,9 @@ obj-				:=
 # Core
-obj-$(CONFIG_ARCH_EXYNOS)       += common.o
+obj-$(CONFIG_ARCH_EXYNOS)       += exynos.o
-obj-$(CONFIG_S5P_PM)            += pm.o
+obj-$(CONFIG_PM_SLEEP)          += pm.o sleep.o
 obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
 obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
@@ -29,8 +29,3 @@ obj-$(CONFIG_ARCH_EXYNOS)	+= firmware.o
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_exynos-smc.o             :=-Wa,-march=armv7-a$(plus_sec)
-# machine support
-obj-$(CONFIG_ARCH_EXYNOS4)      += mach-exynos4-dt.o
-obj-$(CONFIG_ARCH_EXYNOS5)      += mach-exynos5-dt.o
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index f76967b1c551..9ef3f83efaff 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -19,14 +19,27 @@ void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1);
 struct map_desc;
 void exynos_init_io(void);
-void exynos4_restart(enum reboot_mode mode, const char *cmd);
+void exynos_restart(enum reboot_mode mode, const char *cmd);
-void exynos5_restart(enum reboot_mode mode, const char *cmd);
 void exynos_cpuidle_init(void);
 void exynos_cpufreq_init(void);
 void exynos_init_late(void);
 void exynos_firmware_init(void);
+#ifdef CONFIG_PINCTRL_EXYNOS
+extern u32 exynos_get_eint_wake_mask(void);
+#else
+static inline u32 exynos_get_eint_wake_mask(void) { return 0xffffffff; }
+#endif
+#ifdef CONFIG_PM_SLEEP
+extern void __init exynos_pm_init(void);
+#else
+static inline void exynos_pm_init(void) {}
+#endif
+extern void exynos_cpu_resume(void);
 extern struct smp_operations exynos_smp_ops;
 extern void exynos_cpu_die(unsigned int cpu);
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 93d2decc112d..c57cae0e8779 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -27,7 +27,6 @@
 #include <plat/cpu.h>
 #include <plat/pm.h>
-#include <mach/pm-core.h>
 #include <mach/map.h>
 #include "common.h"
@@ -128,7 +127,7 @@ static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
        /* Set value of power down register for aftr mode */
        exynos_sys_powerdown_conf(SYS_AFTR);
-        __raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR);
+        __raw_writel(virt_to_phys(exynos_cpu_resume), REG_DIRECTGO_ADDR);
        __raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);
        save_cpu_arch_register();
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/exynos.c
index b2f9bb071557..b32a907d021d 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -1,105 +1,40 @@
 /*
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ * SAMSUNG EXYNOS Flattened Device Tree enabled machine
- *              http://www.samsung.com
 *
- * Common Codes for EXYNOS
+ * Copyright (c) 2010-2014 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
-#include <linux/kernel.h>
+#include <linux/init.h>
-#include <linux/bitops.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/irqchip.h>
 #include <linux/io.h>
-#include <linux/device.h>
+#include <linux/kernel.h>
-#include <linux/gpio.h>
-#include <clocksource/samsung_pwm.h>
-#include <linux/sched.h>
-#include <linux/serial_core.h>
 #include <linux/serial_s3c.h>
 #include <linux/of.h>
-#include <linux/of_fdt.h>
-#include <linux/of_irq.h>
-#include <linux/pm_domain.h>
-#include <linux/export.h>
-#include <linux/irqdomain.h>
 #include <linux/of_address.h>
-#include <linux/irqchip/arm-gic.h>
+#include <linux/of_fdt.h>
-#include <linux/irqchip/chained_irq.h>
+#include <linux/of_platform.h>
 #include <linux/platform_device.h>
+#include <linux/pm_domain.h>
-#include <asm/proc-fns.h>
+#include <asm/cacheflush.h>
-#include <asm/exception.h>
 #include <asm/hardware/cache-l2x0.h>
+#include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <asm/mach/irq.h>
+#include <asm/memory.h>
-#include <asm/cacheflush.h>
 #include <plat/cpu.h>
-#include <plat/pm.h>
 #include "common.h"
+#include "mfc.h"
 #include "regs-pmu.h"
 #define L2_AUX_VAL 0x7C470001
 #define L2_AUX_MASK 0xC200ffff
-static const char name_exynos4210[] = "EXYNOS4210";
-static const char name_exynos4212[] = "EXYNOS4212";
-static const char name_exynos4412[] = "EXYNOS4412";
-static const char name_exynos5250[] = "EXYNOS5250";
-static const char name_exynos5420[] = "EXYNOS5420";
-static const char name_exynos5440[] = "EXYNOS5440";
-static void exynos4_map_io(void);
-static void exynos5_map_io(void);
-static int exynos_init(void);
-static struct cpu_table cpu_ids[] __initdata = {
-        {
-                .idcode         = EXYNOS4210_CPU_ID,
-                .idmask         = EXYNOS4_CPU_MASK,
-                .map_io         = exynos4_map_io,
-                .init           = exynos_init,
-                .name           = name_exynos4210,
-        }, {
-                .idcode         = EXYNOS4212_CPU_ID,
-                .idmask         = EXYNOS4_CPU_MASK,
-                .map_io         = exynos4_map_io,
-                .init           = exynos_init,
-                .name           = name_exynos4212,
-        }, {
-                .idcode         = EXYNOS4412_CPU_ID,
-                .idmask         = EXYNOS4_CPU_MASK,
-                .map_io         = exynos4_map_io,
-                .init           = exynos_init,
-                .name           = name_exynos4412,
-        }, {
-                .idcode         = EXYNOS5250_SOC_ID,
-                .idmask         = EXYNOS5_SOC_MASK,
-                .map_io         = exynos5_map_io,
-                .init           = exynos_init,
-                .name           = name_exynos5250,
-        }, {
-                .idcode         = EXYNOS5420_SOC_ID,
-                .idmask         = EXYNOS5_SOC_MASK,
-                .map_io         = exynos5_map_io,
-                .init           = exynos_init,
-                .name           = name_exynos5420,
-        }, {
-                .idcode         = EXYNOS5440_SOC_ID,
-                .idmask         = EXYNOS5_SOC_MASK,
-                .init           = exynos_init,
-                .name           = name_exynos5440,
-        },
-};
-/* Initial IO mappings */
 static struct map_desc exynos4_iodesc[] __initdata = {
        {
                .virtual        = (unsigned long)S3C_VA_SYS,
@@ -263,19 +198,11 @@ static struct map_desc exynos5_iodesc[] __initdata = {
        },
 };
-void exynos4_restart(enum reboot_mode mode, const char *cmd)
+void exynos_restart(enum reboot_mode mode, const char *cmd)
-{
-        __raw_writel(0x1, S5P_SWRESET);
-}
-void exynos5_restart(enum reboot_mode mode, const char *cmd)
 {
        struct device_node *np;
-        u32 val;
+        u32 val = 0x1;
-        void __iomem *addr;
+        void __iomem *addr = EXYNOS_SWRESET;
-        val = 0x1;
-        addr = EXYNOS_SWRESET;
        if (of_machine_is_compatible("samsung,exynos5440")) {
                u32 status;
@@ -315,6 +242,7 @@ void __init exynos_init_late(void)
                return;
        pm_genpd_poweroff_unused();
+        exynos_pm_init();
 }
 static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
@@ -345,6 +273,28 @@ static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
 *
 * register the standard cpu IO areas
 */
+static void __init exynos_map_io(void)
+{
+        if (soc_is_exynos4())
+                iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
+        if (soc_is_exynos5())
+                iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
+        if (soc_is_exynos4210()) {
+                if (samsung_rev() == EXYNOS4210_REV_0)
+                        iotable_init(exynos4_iodesc0,
+                                                ARRAY_SIZE(exynos4_iodesc0));
+                else
+                        iotable_init(exynos4_iodesc1,
+                                                ARRAY_SIZE(exynos4_iodesc1));
+                iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
+        }
+        if (soc_is_exynos4212() || soc_is_exynos4412())
+                iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
+        if (soc_is_exynos5250())
+                iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
+}
 void __init exynos_init_io(void)
 {
@@ -355,30 +305,7 @@ void __init exynos_init_io(void)
        /* detect cpu id and rev. */
        s5p_init_cpu(S5P_VA_CHIPID);
-        s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
+        exynos_map_io();
-}
-static void __init exynos4_map_io(void)
-{
-        iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
-        if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
-                iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
-        else
-                iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
-        if (soc_is_exynos4210())
-                iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
-        if (soc_is_exynos4212() || soc_is_exynos4412())
-                iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
-}
-static void __init exynos5_map_io(void)
-{
-        iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
-        if (soc_is_exynos5250())
-                iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
 }
 struct bus_type exynos_subsys = {
@@ -386,10 +313,6 @@ struct bus_type exynos_subsys = {
        .dev_name       = "exynos-core",
 };
-static struct device exynos4_dev = {
-        .bus    = &exynos_subsys,
-};
 static int __init exynos_core_init(void)
 {
        return subsys_system_register(&exynos_subsys, NULL);
@@ -412,9 +335,77 @@ static int __init exynos4_l2x0_cache_init(void)
 }
 early_initcall(exynos4_l2x0_cache_init);
-static int __init exynos_init(void)
+static void __init exynos_dt_machine_init(void)
 {
-        printk(KERN_INFO "EXYNOS: Initializing architecture\n");
+        struct device_node *i2c_np;
+        const char *i2c_compat = "samsung,s3c2440-i2c";
+        unsigned int tmp;
+        int id;
+        /*
+         * Exynos5's legacy i2c controller and new high speed i2c
+         * controller have muxed interrupt sources. By default the
+         * interrupts for 4-channel HS-I2C controller are enabled.
+         * If node for first four channels of legacy i2c controller
+         * are available then re-configure the interrupts via the
+         * system register.
+         */
+        if (soc_is_exynos5()) {
+                for_each_compatible_node(i2c_np, NULL, i2c_compat) {
+                        if (of_device_is_available(i2c_np)) {
+                                id = of_alias_get_id(i2c_np, "i2c");
+                                if (id < 4) {
+                                        tmp = readl(EXYNOS5_SYS_I2C_CFG);
+                                        writel(tmp & ~(0x1 << id),
+                                                        EXYNOS5_SYS_I2C_CFG);
+                                }
+                        }
+                }
+        }
-        return device_register(&exynos4_dev);
+        exynos_cpuidle_init();
+        exynos_cpufreq_init();
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
+static char const *exynos_dt_compat[] __initconst = {
+        "samsung,exynos4",
+        "samsung,exynos4210",
+        "samsung,exynos4212",
+        "samsung,exynos4412",
+        "samsung,exynos5",
+        "samsung,exynos5250",
+        "samsung,exynos5420",
+        "samsung,exynos5440",
+        NULL
+};
+static void __init exynos_reserve(void)
+{
+#ifdef CONFIG_S5P_DEV_MFC
+        int i;
+        char *mfc_mem[] = {
+                "samsung,mfc-v5",
+                "samsung,mfc-v6",
+                "samsung,mfc-v7",
+        };
+        for (i = 0; i < ARRAY_SIZE(mfc_mem); i++)
+                if (of_scan_flat_dt(s5p_fdt_alloc_mfc_mem, mfc_mem[i]))
+                        break;
+#endif
+}
+DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)")
+        /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
+        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
+        .smp            = smp_ops(exynos_smp_ops),
+        .map_io         = exynos_init_io,
+        .init_early     = exynos_firmware_init,
+        .init_machine   = exynos_dt_machine_init,
+        .init_late      = exynos_init_late,
+        .dt_compat      = exynos_dt_compat,
+        .restart        = exynos_restart,
+        .reserve        = exynos_reserve,
+MACHINE_END
diff --git a/arch/arm/mach-exynos/include/mach/hardware.h b/arch/arm/mach-exynos/include/mach/hardware.h
deleted file mode 100644
index 5109eb232f23..000000000000
--- a/arch/arm/mach-exynos/include/mach/hardware.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/hardware.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 - Hardware support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H __FILE__
-/* currently nothing here, placeholder */
-#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-exynos/include/mach/pm-core.h b/arch/arm/mach-exynos/include/mach/pm-core.h
deleted file mode 100644
index dc0697c2fa92..000000000000
--- a/arch/arm/mach-exynos/include/mach/pm-core.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/pm-core.h
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Based on arch/arm/mach-s3c2410/include/mach/pm-core.h,
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * EXYNOS4210 - PM core support for arch/arm/plat-s5p/pm.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_PM_CORE_H
-#define __ASM_ARCH_PM_CORE_H __FILE__
-#include <linux/of.h>
-#include <mach/map.h>
-#define S5P_EINT_WAKEUP_MASK                    (S5P_VA_PMU + 0x0604)
-#define S5P_WAKEUP_MASK                         (S5P_VA_PMU + 0x0608)
-#ifdef CONFIG_PINCTRL_EXYNOS
-extern u32 exynos_get_eint_wake_mask(void);
-#else
-static inline u32 exynos_get_eint_wake_mask(void) { return 0xffffffff; }
-#endif
-static inline void s3c_pm_debug_init_uart(void)
-{
-        /* nothing here yet */
-}
-static inline void s3c_pm_arch_prepare_irqs(void)
-{
-        __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
-        __raw_writel(s3c_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
-}
-static inline void s3c_pm_arch_stop_clocks(void)
-{
-        /* nothing here yet */
-}
-static inline void s3c_pm_arch_show_resume_irqs(void)
-{
-        /* nothing here yet */
-}
-static inline void s3c_pm_arch_update_uart(void __iomem *regs,
-                                           struct pm_uart_save *save)
-{
-        /* nothing here yet */
-}
-static inline void s3c_pm_restored_gpios(void)
-{
-        /* nothing here yet */
-}
-static inline void samsung_pm_saved_gpios(void)
-{
-        /* nothing here yet */
-}
-/* Compatibility definitions to make plat-samsung/pm.c compile */
-#define IRQ_EINT_BIT(x)         1
-#define s3c_irqwake_intallow    0
-#define s3c_irqwake_eintallow   0
-#endif /* __ASM_ARCH_PM_CORE_H */
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
deleted file mode 100644
index d3e54b7644d7..000000000000
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Samsung's EXYNOS4 flattened device tree enabled machine
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- * Copyright (c) 2010-2011 Linaro Ltd.
- *              www.linaro.org
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/of_platform.h>
-#include <linux/of_fdt.h>
-#include <asm/mach/arch.h>
-#include <plat/mfc.h>
-#include "common.h"
-static void __init exynos4_dt_machine_init(void)
-{
-        exynos_cpuidle_init();
-        exynos_cpufreq_init();
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-static char const *exynos4_dt_compat[] __initdata = {
-        "samsung,exynos4210",
-        "samsung,exynos4212",
-        "samsung,exynos4412",
-        NULL
-};
-static void __init exynos4_reserve(void)
-{
-#ifdef CONFIG_S5P_DEV_MFC
-        struct s5p_mfc_dt_meminfo mfc_mem;
-        /* Reserve memory for MFC only if it's available */
-        mfc_mem.compatible = "samsung,mfc-v5";
-        if (of_scan_flat_dt(s5p_fdt_find_mfc_mem, &mfc_mem))
-                s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize, mfc_mem.loff,
-                                mfc_mem.lsize);
-#endif
-}
-DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
-        /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
-        .smp            = smp_ops(exynos_smp_ops),
-        .map_io         = exynos_init_io,
-        .init_early     = exynos_firmware_init,
-        .init_machine   = exynos4_dt_machine_init,
-        .init_late      = exynos_init_late,
-        .dt_compat      = exynos4_dt_compat,
-        .restart        = exynos4_restart,
-        .reserve        = exynos4_reserve,
-MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
deleted file mode 100644
index 37ea261f0f6c..000000000000
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * SAMSUNG EXYNOS5250 Flattened Device Tree enabled machine
- *
- * Copyright (c) 2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/of_platform.h>
-#include <linux/of_fdt.h>
-#include <linux/io.h>
-#include <asm/mach/arch.h>
-#include <plat/mfc.h>
-#include "common.h"
-#include "regs-pmu.h"
-static void __init exynos5_dt_machine_init(void)
-{
-        struct device_node *i2c_np;
-        const char *i2c_compat = "samsung,s3c2440-i2c";
-        unsigned int tmp;
-        /*
-         * Exynos5's legacy i2c controller and new high speed i2c
-         * controller have muxed interrupt sources. By default the
-         * interrupts for 4-channel HS-I2C controller are enabled.
-         * If node for first four channels of legacy i2c controller
-         * are available then re-configure the interrupts via the
-         * system register.
-         */
-        for_each_compatible_node(i2c_np, NULL, i2c_compat) {
-                if (of_device_is_available(i2c_np)) {
-                        if (of_alias_get_id(i2c_np, "i2c") < 4) {
-                                tmp = readl(EXYNOS5_SYS_I2C_CFG);
-                                writel(tmp & ~(0x1 << of_alias_get_id(i2c_np, "i2c")),
-                                                EXYNOS5_SYS_I2C_CFG);
-                        }
-                }
-        }
-        exynos_cpuidle_init();
-        exynos_cpufreq_init();
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-static char const *exynos5_dt_compat[] __initdata = {
-        "samsung,exynos5250",
-        "samsung,exynos5420",
-        "samsung,exynos5440",
-        NULL
-};
-static void __init exynos5_reserve(void)
-{
-#ifdef CONFIG_S5P_DEV_MFC
-        struct s5p_mfc_dt_meminfo mfc_mem;
-        /* Reserve memory for MFC only if it's available */
-        mfc_mem.compatible = "samsung,mfc-v6";
-        if (of_scan_flat_dt(s5p_fdt_find_mfc_mem, &mfc_mem))
-                s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize, mfc_mem.loff,
-                                mfc_mem.lsize);
-#endif
-}
-DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
-        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
-        .smp            = smp_ops(exynos_smp_ops),
-        .map_io         = exynos_init_io,
-        .init_machine   = exynos5_dt_machine_init,
-        .init_late      = exynos_init_late,
-        .dt_compat      = exynos5_dt_compat,
-        .restart        = exynos5_restart,
-        .reserve        = exynos5_reserve,
-MACHINE_END
diff --git a/arch/arm/mach-exynos/mfc.h b/arch/arm/mach-exynos/mfc.h
new file mode 100644
index 000000000000..dec93cd5b3c6
--- /dev/null
+++ b/arch/arm/mach-exynos/mfc.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics Co.Ltd
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#ifndef __MACH_EXYNOS_MFC_H
+#define __MACH_EXYNOS_MFC_H __FILE__
+int __init s5p_fdt_alloc_mfc_mem(unsigned long node, const char *uname,
+                                int depth, void *data);
+#endif /* __MACH_EXYNOS_MFC_H */
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 8ea02f63fed9..03e5e9f94705 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -26,8 +26,6 @@
 #include <asm/smp_scu.h>
 #include <asm/firmware.h>
-#include <mach/hardware.h>
 #include <plat/cpu.h>
 #include "common.h"
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index ba18214c9aca..15af0ceb0a66 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -17,24 +17,35 @@
 #include <linux/suspend.h>
 #include <linux/syscore_ops.h>
 #include <linux/io.h>
+#include <linux/irqchip/arm-gic.h>
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <asm/cacheflush.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/smp_scu.h>
+#include <asm/suspend.h>
 #include <plat/cpu.h>
-#include <plat/pm.h>
+#include <plat/pm-common.h>
 #include <plat/pll.h>
 #include <plat/regs-srom.h>
 #include <mach/map.h>
-#include <mach/pm-core.h>
 #include "common.h"
 #include "regs-pmu.h"
+/**
+ * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping
+ * @hwirq: Hardware IRQ signal of the GIC
+ * @mask: Mask in PMU wake-up mask register
+ */
+struct exynos_wkup_irq {
+        unsigned int hwirq;
+        u32 mask;
+};
 static struct sleep_save exynos5_sys_save[] = {
        SAVE_ITEM(EXYNOS5_SYS_I2C_CFG),
 };
@@ -48,6 +59,46 @@ static struct sleep_save exynos_core_save[] = {
        SAVE_ITEM(S5P_SROM_BC3),
 };
+/*
+ * GIC wake-up support
+ */
+static u32 exynos_irqwake_intmask = 0xffffffff;
+static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
+        { 76, BIT(1) }, /* RTC alarm */
+        { 77, BIT(2) }, /* RTC tick */
+        { /* sentinel */ },
+};
+static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
+        { 75, BIT(1) }, /* RTC alarm */
+        { 76, BIT(2) }, /* RTC tick */
+        { /* sentinel */ },
+};
+static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
+{
+        const struct exynos_wkup_irq *wkup_irq;
+        if (soc_is_exynos5250())
+                wkup_irq = exynos5250_wkup_irq;
+        else
+                wkup_irq = exynos4_wkup_irq;
+        while (wkup_irq->mask) {
+                if (wkup_irq->hwirq == data->hwirq) {
+                        if (!state)
+                                exynos_irqwake_intmask |= wkup_irq->mask;
+                        else
+                                exynos_irqwake_intmask &= ~wkup_irq->mask;
+                        return 0;
+                }
+                ++wkup_irq;
+        }
+        return -ENOENT;
+}
 /* For Cortex-A9 Diagnostic and Power control register */
 static unsigned int save_arm_register[2];
@@ -72,6 +123,10 @@ static void exynos_pm_prepare(void)
 {
        unsigned int tmp;
+        /* Set wake-up mask registers */
+        __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
+        __raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
        s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
        if (soc_is_exynos5250()) {
@@ -89,41 +144,8 @@ static void exynos_pm_prepare(void)
        /* ensure at least INFORM0 has the resume address */
-        __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);
+        __raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
-}
-static int exynos_pm_add(struct device *dev, struct subsys_interface *sif)
-{
-        pm_cpu_prep = exynos_pm_prepare;
-        pm_cpu_sleep = exynos_cpu_suspend;
-        return 0;
-}
-static struct subsys_interface exynos_pm_interface = {
-        .name           = "exynos_pm",
-        .subsys         = &exynos_subsys,
-        .add_dev        = exynos_pm_add,
-};
-static __init int exynos_pm_drvinit(void)
-{
-        unsigned int tmp;
-        if (soc_is_exynos5440())
-                return 0;
-        s3c_pm_init();
-        /* All wakeup disable */
-        tmp = __raw_readl(S5P_WAKEUP_MASK);
-        tmp |= ((0xFF << 8) | (0x1F << 1));
-        __raw_writel(tmp, S5P_WAKEUP_MASK);
-        return subsys_interface_register(&exynos_pm_interface);
 }
-arch_initcall(exynos_pm_drvinit);
 static int exynos_pm_suspend(void)
 {
@@ -220,12 +242,80 @@ static struct syscore_ops exynos_pm_syscore_ops = {
        .resume         = exynos_pm_resume,
 };
-static __init int exynos_pm_syscore_init(void)
+/*
+ * Suspend Ops
+ */
+static int exynos_suspend_enter(suspend_state_t state)
 {
-        if (soc_is_exynos5440())
+        int ret;
-                return 0;
+        s3c_pm_debug_init();
+        S3C_PMDBG("%s: suspending the system...\n", __func__);
+        S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
+                        exynos_irqwake_intmask, exynos_get_eint_wake_mask());
+        if (exynos_irqwake_intmask == -1U
+            && exynos_get_eint_wake_mask() == -1U) {
+                pr_err("%s: No wake-up sources!\n", __func__);
+                pr_err("%s: Aborting sleep\n", __func__);
+                return -EINVAL;
+        }
+        s3c_pm_save_uarts();
+        exynos_pm_prepare();
+        flush_cache_all();
+        s3c_pm_check_store();
+        ret = cpu_suspend(0, exynos_cpu_suspend);
+        if (ret)
+                return ret;
+        s3c_pm_restore_uarts();
+        S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
+                        __raw_readl(S5P_WAKEUP_STAT));
+        s3c_pm_check_restore();
+        S3C_PMDBG("%s: resuming the system...\n", __func__);
-        register_syscore_ops(&exynos_pm_syscore_ops);
        return 0;
 }
-arch_initcall(exynos_pm_syscore_init);
+static int exynos_suspend_prepare(void)
+{
+        s3c_pm_check_prepare();
+        return 0;
+}
+static void exynos_suspend_finish(void)
+{
+        s3c_pm_check_cleanup();
+}
+static const struct platform_suspend_ops exynos_suspend_ops = {
+        .enter          = exynos_suspend_enter,
+        .prepare        = exynos_suspend_prepare,
+        .finish         = exynos_suspend_finish,
+        .valid          = suspend_valid_only_mem,
+};
+void __init exynos_pm_init(void)
+{
+        u32 tmp;
+        /* Platform-specific GIC callback */
+        gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
+        /* All wakeup disable */
+        tmp = __raw_readl(S5P_WAKEUP_MASK);
+        tmp |= ((0xFF << 8) | (0x1F << 1));
+        __raw_writel(tmp, S5P_WAKEUP_MASK);
+        register_syscore_ops(&exynos_pm_syscore_ops);
+        suspend_set_ops(&exynos_suspend_ops);
+}
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 7c029ce27711..4f6a2560d022 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -26,11 +26,12 @@
 #define S5P_USE_STANDBY_WFI0                    (1 << 16)
 #define S5P_USE_STANDBY_WFE0                    (1 << 24)
-#define S5P_SWRESET                             S5P_PMUREG(0x0400)
 #define EXYNOS_SWRESET                          S5P_PMUREG(0x0400)
 #define EXYNOS5440_SWRESET                      S5P_PMUREG(0x00C4)
 #define S5P_WAKEUP_STAT                         S5P_PMUREG(0x0600)
+#define S5P_EINT_WAKEUP_MASK                    S5P_PMUREG(0x0604)
+#define S5P_WAKEUP_MASK                         S5P_PMUREG(0x0608)
 #define S5P_INFORM0                             S5P_PMUREG(0x0800)
 #define S5P_INFORM1                             S5P_PMUREG(0x0804)
diff --git a/arch/arm/mach-exynos/sleep.S b/arch/arm/mach-exynos/sleep.S
new file mode 100644
index 000000000000..a2613e944e10
--- /dev/null
+++ b/arch/arm/mach-exynos/sleep.S
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Exynos low-level resume code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/linkage.h>
+#include <asm/asm-offsets.h>
+#include <asm/hardware/cache-l2x0.h>
+#define CPU_MASK        0xff0ffff0
+#define CPU_CORTEX_A9   0x410fc090
+        /*
+         * The following code is located into the .data section. This is to
+         * allow l2x0_regs_phys to be accessed with a relative load while we
+         * can't rely on any MMU translation. We could have put l2x0_regs_phys
+         * in the .text section as well, but some setups might insist on it to
+         * be truly read-only. (Reference from: arch/arm/kernel/sleep.S)
+         */
+        .data
+        .align
+        /*
+         * sleep magic, to allow the bootloader to check for an valid
+         * image to resume to. Must be the first word before the
+         * exynos_cpu_resume entry.
+         */
+        .word   0x2bedf00d
+        /*
+         * exynos_cpu_resume
+         *
+         * resume code entry for bootloader to call
+         */
+ENTRY(exynos_cpu_resume)
+#ifdef CONFIG_CACHE_L2X0
+        mrc     p15, 0, r0, c0, c0, 0
+        ldr     r1, =CPU_MASK
+        and     r0, r0, r1
+        ldr     r1, =CPU_CORTEX_A9
+        cmp     r0, r1
+        bne     skip_l2_resume
+        adr     r0, l2x0_regs_phys
+        ldr     r0, [r0]
+        cmp     r0, #0
+        beq     skip_l2_resume
+        ldr     r1, [r0, #L2X0_R_PHY_BASE]
+        ldr     r2, [r1, #L2X0_CTRL]
+        tst     r2, #0x1
+        bne     skip_l2_resume
+        ldr     r2, [r0, #L2X0_R_AUX_CTRL]
+        str     r2, [r1, #L2X0_AUX_CTRL]
+        ldr     r2, [r0, #L2X0_R_TAG_LATENCY]
+        str     r2, [r1, #L2X0_TAG_LATENCY_CTRL]
+        ldr     r2, [r0, #L2X0_R_DATA_LATENCY]
+        str     r2, [r1, #L2X0_DATA_LATENCY_CTRL]
+        ldr     r2, [r0, #L2X0_R_PREFETCH_CTRL]
+        str     r2, [r1, #L2X0_PREFETCH_CTRL]
+        ldr     r2, [r0, #L2X0_R_PWR_CTRL]
+        str     r2, [r1, #L2X0_POWER_CTRL]
+        mov     r2, #1
+        str     r2, [r1, #L2X0_CTRL]
+skip_l2_resume:
+#endif
+        b       cpu_resume
+ENDPROC(exynos_cpu_resume)
+#ifdef CONFIG_CACHE_L2X0
+        .globl l2x0_regs_phys
+l2x0_regs_phys:
+        .long   0
+#endif
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 00ddf20ed91b..e3f3aca43efb 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -25,13 +25,11 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
-#include <mach/hardware.h>
-#include <mach/platform.h>
 #include <asm/mach-types.h>
 #include <asm/mach/time.h>
 #include <asm/pgtable.h>
+#include "hardware.h"
 #include "cm.h"
 #include "common.h"
diff --git a/arch/arm/mach-integrator/include/mach/platform.h b/arch/arm/mach-integrator/hardware.h
index 306d025d9730..857ca5f8b9a6 100644
--- a/arch/arm/mach-integrator/include/mach/platform.h
+++ b/arch/arm/mach-integrator/hardware.h
@@ -1,4 +1,8 @@
 /*
+ *  This file contains the hardware definitions of the Integrator.
+ *
+ *  Copyright (C) 1998-1999 ARM Limited.
+ *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
@@ -13,26 +17,28 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
-/**************************************************************************
+#ifndef INTEGRATOR_HARDWARE_H
- * * Copyright © ARM Limited 1998.  All rights reserved.
+#define INTEGRATOR_HARDWARE_H
- * ***********************************************************************/
-/* ************************************************************************
- *
- *   Integrator address map
- *
- * ***********************************************************************/
-#ifndef __address_h
+/*
-#define __address_h                     1
+ * Where in virtual memory the IO devices (timers, system controllers
+ * and so on)
+ */
+#define IO_BASE                 0xF0000000                 // VA of IO
+#define IO_SIZE                 0x0B000000                 // How much?
+#define IO_START                INTEGRATOR_HDR_BASE        // PA of IO
+/* macro to get at IO space when running virtually */
+#ifdef CONFIG_MMU
+#define IO_ADDRESS(x)   (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
+#else
+#define IO_ADDRESS(x)   (x)
+#endif
-/* ========================================================================
+#define __io_address(n)         ((void __iomem *)IO_ADDRESS(n))
- *  Integrator definitions
- * ========================================================================
+/*
- * ------------------------------------------------------------------------
- *  Memory definitions
- * ------------------------------------------------------------------------
 *  Integrator memory map
- *
 */
 #define INTEGRATOR_BOOT_ROM_LO          0x00000000
 #define INTEGRATOR_BOOT_ROM_HI          0x20000000
@@ -40,13 +46,13 @@
 #define INTEGRATOR_BOOT_ROM_SIZE        SZ_512K
 /*
- *  New Core Modules have different amounts of SSRAM, the amount of SSRAM
+ * New Core Modules have different amounts of SSRAM, the amount of SSRAM
- *  fitted can be found in HDR_STAT.
+ * fitted can be found in HDR_STAT.
 *
- *  The symbol INTEGRATOR_SSRAM_SIZE is kept, however this now refers to
+ * The symbol INTEGRATOR_SSRAM_SIZE is kept, however this now refers to
- *  the minimum amount of SSRAM fitted on any core module.
+ * the minimum amount of SSRAM fitted on any core module.
 *
- *  New Core Modules also alias the SSRAM.
+ * New Core Modules also alias the SSRAM.
 *
 */
 #define INTEGRATOR_SSRAM_BASE           0x00000000
@@ -61,7 +67,6 @@
 /*
 *  SDRAM is a SIMM therefore the size is not known.
- *
 */
 #define INTEGRATOR_SDRAM_BASE           0x00040000
@@ -81,10 +86,8 @@
 #define INTEGRATOR_LOGIC_MODULE2_BASE   0xE0000000
 #define INTEGRATOR_LOGIC_MODULE3_BASE   0xF0000000
-/* ------------------------------------------------------------------------
+/*
- *  Integrator header card registers
+ * Integrator header card registers
- * ------------------------------------------------------------------------
- *
 */
 #define INTEGRATOR_HDR_ID_OFFSET        0x00
 #define INTEGRATOR_HDR_PROC_OFFSET      0x04
@@ -173,16 +176,12 @@
 #define INTEGRATOR_HDR_SDRAM_SPD_OK     (1 << 5)
+/*
-/* ------------------------------------------------------------------------
+ * Integrator system registers
- *  Integrator system registers
- * ------------------------------------------------------------------------
- *
 */
 /*
 *  System Controller
- *
 */
 #define INTEGRATOR_SC_ID_OFFSET         0x00
 #define INTEGRATOR_SC_OSC_OFFSET        0x04
@@ -223,7 +222,6 @@
 /*
 *  External Bus Interface
- *
 */
 #define INTEGRATOR_EBI_BASE             0x12000000
@@ -272,7 +270,6 @@
 /*
 *  LED's & Switches
- *
 */
 #define INTEGRATOR_DBG_ALPHA_OFFSET     0x00
 #define INTEGRATOR_DBG_LEDS_OFFSET      0x04
@@ -292,32 +289,25 @@
 #define INTEGRATOR_CP_SIC_BASE          0xCA000000      /* SIC */
 #define INTEGRATOR_CP_CTL_BASE          0xCB000000      /* CP system control */
-/* ------------------------------------------------------------------------
- *  KMI keyboard/mouse definitions
- * ------------------------------------------------------------------------
- */
 /* PS2 Keyboard interface */
 #define KMI0_BASE                       INTEGRATOR_KBD_BASE
 /* PS2 Mouse interface */
 #define KMI1_BASE                       INTEGRATOR_MOUSE_BASE
-/* KMI definitions are now in include/asm-arm/hardware/amba_kmi.h -- rmk */
+/*
+ * Integrator Interrupt Controllers
-/* ------------------------------------------------------------------------
- *  Integrator Interrupt Controllers
- * ------------------------------------------------------------------------
 *
- *  Offsets from interrupt controller base
 *
- *  System Controller interrupt controller base is
+ * Offsets from interrupt controller base
+ *
+ * System Controller interrupt controller base is
 *
 *      INTEGRATOR_IC_BASE + (header_number << 6)
 *
- *  Core Module interrupt controller base is
+ * Core Module interrupt controller base is
 *
 *      INTEGRATOR_HDR_IC
- *
 */
 #define IRQ_STATUS                      0
 #define IRQ_RAW_STATUS                  0x04
@@ -335,25 +325,8 @@
 #define FIQ_ENABLE_CLEAR                0x2C
-/* ------------------------------------------------------------------------
+/*
- *  Interrupts
+ * LED's
- * ------------------------------------------------------------------------
- *
- *
- *  Each Core Module has two interrupts controllers, one on the core module
- *  itself and one in the system controller on the motherboard.  The
- *  READ_INT macro in target.s reads both interrupt controllers and returns
- *  a 32 bit bitmask, bits 0 to 23 are interrupts from the system controller
- *  and bits 24 to 31 are from the core module.
- *
- *  The following definitions relate to the bitmask returned by READ_INT.
- *
- */
-/* ------------------------------------------------------------------------
- *  LED's
- * ------------------------------------------------------------------------
- *
 */
 #define GREEN_LED                       0x01
 #define YELLOW_LED                      0x02
@@ -371,7 +344,6 @@
 *
 *  Timer 0 runs at bus frequency
 */
 #define INTEGRATOR_TIMER0_BASE          INTEGRATOR_CT_BASE
 #define INTEGRATOR_TIMER1_BASE          (INTEGRATOR_CT_BASE + 0x100)
 #define INTEGRATOR_TIMER2_BASE          (INTEGRATOR_CT_BASE + 0x200)
@@ -379,4 +351,4 @@
 #define INTEGRATOR_CSR_BASE             0x10000000
 #define INTEGRATOR_CSR_SIZE             0x10000000
-#endif
+#endif /* INTEGRATOR_HARDWARE_H */
diff --git a/arch/arm/mach-integrator/impd1.c b/arch/arm/mach-integrator/impd1.c
index d9b784824808..0e870ea818c4 100644
--- a/arch/arm/mach-integrator/impd1.c
+++ b/arch/arm/mach-integrator/impd1.c
@@ -25,9 +25,9 @@
 #include <linux/slab.h>
 #include <linux/irqchip/arm-vic.h>
-#include <mach/lm.h>
-#include <mach/impd1.h>
 #include <asm/sizes.h>
+#include "lm.h"
+#include "impd1.h"
 static int module_id;
diff --git a/arch/arm/mach-integrator/include/mach/impd1.h b/arch/arm/mach-integrator/impd1.h
index d75de4b14237..76de4dc9bee4 100644
--- a/arch/arm/mach-integrator/include/mach/impd1.h
+++ b/arch/arm/mach-integrator/impd1.h
@@ -1,6 +1,3 @@
-#define IMPD1_OSC1      0x00
-#define IMPD1_OSC2      0x04
-#define IMPD1_LOCK      0x08
 #define IMPD1_LEDS      0x0c
 #define IMPD1_INT       0x10
 #define IMPD1_SW        0x14
@@ -15,4 +12,3 @@
 struct device;
 void impd1_tweak_control(struct device *dev, u32 mask, u32 val);
diff --git a/arch/arm/mach-integrator/include/mach/hardware.h b/arch/arm/mach-integrator/include/mach/hardware.h
deleted file mode 100644
index 65fed7c0eb84..000000000000
--- a/arch/arm/mach-integrator/include/mach/hardware.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- *  arch/arm/mach-integrator/include/mach/hardware.h
- *
- *  This file contains the hardware definitions of the Integrator.
- *
- *  Copyright (C) 1999 ARM Limited.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-#include <asm/sizes.h>
-/*
- * Where in virtual memory the IO devices (timers, system controllers
- * and so on)
- */
-#define IO_BASE                 0xF0000000                 // VA of IO 
-#define IO_SIZE                 0x0B000000                 // How much?
-#define IO_START                INTEGRATOR_HDR_BASE        // PA of IO
-/* macro to get at IO space when running virtually */
-#ifdef CONFIG_MMU
-#define IO_ADDRESS(x)   (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
-#else
-#define IO_ADDRESS(x)   (x)
-#endif
-#define __io_address(n)         ((void __iomem *)IO_ADDRESS(n))
-#endif
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index cc0857cab2e1..dd0cc677d596 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -44,23 +44,21 @@
 #include <linux/sched_clock.h>
 #include <linux/clk-provider.h>
-#include <mach/hardware.h>
-#include <mach/platform.h>
 #include <asm/hardware/arm_timer.h>
 #include <asm/setup.h>
 #include <asm/param.h>          /* HZ */
 #include <asm/mach-types.h>
-#include <mach/lm.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
+#include "hardware.h"
 #include "cm.h"
 #include "common.h"
 #include "pci_v3.h"
+#include "lm.h"
 /* Base address to the AP system controller */
 void __iomem *ap_syscon_base;
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 0ad5f60598c8..a938242b0c95 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -27,22 +27,18 @@
 #include <linux/of_address.h>
 #include <linux/of_platform.h>
 #include <linux/sys_soc.h>
+#include <linux/sched_clock.h>
-#include <mach/hardware.h>
-#include <mach/platform.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
-#include <mach/lm.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <plat/clcd.h>
-#include <plat/sched_clock.h>
+#include "hardware.h"
 #include "cm.h"
 #include "common.h"
@@ -229,11 +225,14 @@ static struct clcd_board clcd_data = {
 #define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)
+static u64 notrace intcp_read_sched_clock(void)
+{
+        return readl(REFCOUNTER);
+}
 static void __init intcp_init_early(void)
 {
-#ifdef CONFIG_PLAT_VERSATILE_SCHED_CLOCK
+        sched_clock_register(intcp_read_sched_clock, 32, 24000000);
-        versatile_sched_clock_init(REFCOUNTER, 24000000);
-#endif
 }
 static const struct of_device_id fpga_irq_of_match[] __initconst = {
diff --git a/arch/arm/mach-integrator/leds.c b/arch/arm/mach-integrator/leds.c
index cb6ac58f5e07..f1dcb57a59e2 100644
--- a/arch/arm/mach-integrator/leds.c
+++ b/arch/arm/mach-integrator/leds.c
@@ -11,9 +11,7 @@
 #include <linux/slab.h>
 #include <linux/leds.h>
-#include <mach/hardware.h>
+#include "hardware.h"
-#include <mach/platform.h>
 #include "cm.h"
 #if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
diff --git a/arch/arm/mach-integrator/lm.c b/arch/arm/mach-integrator/lm.c
index f52c7af31eaa..3f9e9f043168 100644
--- a/arch/arm/mach-integrator/lm.c
+++ b/arch/arm/mach-integrator/lm.c
@@ -12,7 +12,7 @@
 #include <linux/device.h>
 #include <linux/slab.h>
-#include <mach/lm.h>
+#include "lm.h"
 #define to_lm_device(d) container_of(d, struct lm_device, dev)
 #define to_lm_driver(d) container_of(d, struct lm_driver, drv)
diff --git a/arch/arm/mach-integrator/include/mach/lm.h b/arch/arm/mach-integrator/lm.h
index 28186b6f2c09..28186b6f2c09 100644
--- a/arch/arm/mach-integrator/include/mach/lm.h
+++ b/arch/arm/mach-integrator/lm.h
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index c5e01b24d9fb..05e1f73a1e8d 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -34,15 +34,13 @@
 #include <linux/of_pci.h>
 #include <video/vga.h>
-#include <mach/hardware.h>
-#include <mach/platform.h>
 #include <asm/mach/map.h>
 #include <asm/signal.h>
 #include <asm/mach/pci.h>
 #include <asm/irq_regs.h>
 #include "pci_v3.h"
+#include "hardware.h"
 /*
 * Where in the memory map does PCI live?
diff --git a/arch/arm/mach-s3c24xx/include/mach/hardware.h b/arch/arm/mach-s3c24xx/include/mach/hardware.h
index a6cc14a092fc..dedd3837c193 100644
--- a/arch/arm/mach-s3c24xx/include/mach/hardware.h
+++ b/arch/arm/mach-s3c24xx/include/mach/hardware.h
@@ -1,5 +1,4 @@
-/* arch/arm/mach-s3c2410/include/mach/hardware.h
+/*
- *
 * Copyright (c) 2003 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
@@ -17,20 +16,9 @@
 extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg);
-#ifdef CONFIG_CPU_S3C2440
-extern int s3c2440_set_dsc(unsigned int pin, unsigned int value);
-#endif /* CONFIG_CPU_S3C2440 */
 #endif /* __ASSEMBLY__ */
 #include <asm/sizes.h>
 #include <mach/map.h>
-/* machine specific hardware definitions should go after this */
-/* currently here until moved into config (todo) */
-#define CONFIG_NO_MULTIWORD_IO
 #endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/uncompress.h b/arch/arm/mach-s3c24xx/include/mach/uncompress.h
deleted file mode 100644
index 7d2ce205dce8..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/uncompress.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/uncompress.h
- *
- * Copyright (c) 2003-2007 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - uncompress code
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-#include <mach/regs-gpio.h>
-#include <mach/map.h>
-/* working in physical space... */
-#undef S3C2410_GPIOREG
-#define S3C2410_GPIOREG(x) ((S3C24XX_PA_GPIO + (x)))
-#include <plat/uncompress.h>
-static inline int is_arm926(void)
-{
-        unsigned int cpuid;
-        asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (cpuid));
-        return ((cpuid & 0xff0) == 0x260);
-}
-static void arch_detect_cpu(void)
-{
-        unsigned int cpuid;
-        cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1);
-        cpuid &= S3C2410_GSTATUS1_IDMASK;
-        if (is_arm926() || cpuid == S3C2410_GSTATUS1_2440 ||
-            cpuid == S3C2410_GSTATUS1_2442 ||
-            cpuid == S3C2410_GSTATUS1_2416 ||
-            cpuid == S3C2410_GSTATUS1_2450) {
-                fifo_mask = S3C2440_UFSTAT_TXMASK;
-                fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
-        } else {
-                fifo_mask = S3C2410_UFSTAT_TXMASK;
-                fifo_max = 15 << S3C2410_UFSTAT_TXSHIFT;
-        }
-        uart_base = (volatile u8 *) S3C_PA_UART +
-                (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
-}
-#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/pm-core.h b/arch/arm/mach-s3c64xx/include/mach/pm-core.h
index c0537f40a3d8..a30a1e3ffc6a 100644
--- a/arch/arm/mach-s3c64xx/include/mach/pm-core.h
+++ b/arch/arm/mach-s3c64xx/include/mach/pm-core.h
@@ -15,6 +15,8 @@
 #ifndef __MACH_S3C64XX_PM_CORE_H
 #define __MACH_S3C64XX_PM_CORE_H __FILE__
+#include <linux/serial_s3c.h>
 #include <mach/regs-gpio.h>
 static inline void s3c_pm_debug_init_uart(void)
diff --git a/arch/arm/mach-s3c64xx/include/mach/uncompress.h b/arch/arm/mach-s3c64xx/include/mach/uncompress.h
deleted file mode 100644
index 1c956738b42d..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/uncompress.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* arch/arm/mach-s3c6400/include/mach/uncompress.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C6400 - uncompress code
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-#include <mach/map.h>
-#include <plat/uncompress.h>
-static void arch_detect_cpu(void)
-{
-        /* we do not need to do any cpu detection here at the moment. */
-        fifo_mask = S3C2440_UFSTAT_TXMASK;
-        fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
-        uart_base = (volatile u8 *)S3C_PA_UART +
-                (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
-}
-#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c
index b5a66986a529..6b37694fa335 100644
--- a/arch/arm/mach-s3c64xx/pm.c
+++ b/arch/arm/mach-s3c64xx/pm.c
@@ -332,7 +332,6 @@ static __init int s3c64xx_pm_initcall(void)
 {
        pm_cpu_prep = s3c64xx_pm_prepare;
        pm_cpu_sleep = s3c64xx_cpu_suspend;
-        pm_uart_udivslot = 1;
 #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
        gpio_request(S3C64XX_GPN(12), "DEBUG_LED0");
diff --git a/arch/arm/mach-s5p64x0/include/mach/pm-core.h b/arch/arm/mach-s5p64x0/include/mach/pm-core.h
index e52f7545d3aa..1e0eb65b2b82 100644
--- a/arch/arm/mach-s5p64x0/include/mach/pm-core.h
+++ b/arch/arm/mach-s5p64x0/include/mach/pm-core.h
@@ -12,6 +12,8 @@
 * published by the Free Software Foundation.
 */
+#include <linux/serial_s3c.h>
 #include <mach/regs-gpio.h>
 static inline void s3c_pm_debug_init_uart(void)
diff --git a/arch/arm/mach-s5p64x0/include/mach/uncompress.h b/arch/arm/mach-s5p64x0/include/mach/uncompress.h
deleted file mode 100644
index bbcc3f669ee3..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/uncompress.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/include/mach/uncompress.h
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * S5P64X0 - uncompress code
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-#include <mach/map.h>
-#include <plat/uncompress.h>
-static void arch_detect_cpu(void)
-{
-        unsigned int chipid;
-        chipid = *(const volatile unsigned int __force *) 0xE0100118;
-        if ((chipid & 0xff000) == 0x50000)
-                uart_base = (volatile u8 *)S5P6450_PA_UART(CONFIG_S3C_LOWLEVEL_UART_PORT);
-        else
-                uart_base = (volatile u8 *)S5P6440_PA_UART(CONFIG_S3C_LOWLEVEL_UART_PORT);
-        fifo_mask = S3C2440_UFSTAT_TXMASK;
-        fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
-}
-#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s5p64x0/pm.c b/arch/arm/mach-s5p64x0/pm.c
index 861e15cea691..ec8229cee716 100644
--- a/arch/arm/mach-s5p64x0/pm.c
+++ b/arch/arm/mach-s5p64x0/pm.c
@@ -161,7 +161,6 @@ static int s5p64x0_pm_add(struct device *dev, struct subsys_interface *sif)
 {
        pm_cpu_prep = s5p64x0_pm_prepare;
        pm_cpu_sleep = s5p64x0_cpu_suspend;
-        pm_uart_udivslot = 1;
        return 0;
 }
diff --git a/arch/arm/mach-s5pc100/include/mach/uncompress.h b/arch/arm/mach-s5pc100/include/mach/uncompress.h
deleted file mode 100644
index 720e1339425c..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/uncompress.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* arch/arm/mach-s5pc100/include/mach/uncompress.h
- *
- * Copyright 2009 Samsung Electronics Co.
- *      Byungho Min <bhmin@samsung.com>
- *
- * S5PC100 - uncompress code
- *
- * Based on mach-s3c6400/include/mach/uncompress.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-#include <mach/map.h>
-#include <plat/uncompress.h>
-static void arch_detect_cpu(void)
-{
-        /* we do not need to do any cpu detection here at the moment. */
-        fifo_mask = S3C2440_UFSTAT_TXMASK;
-        fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
-        uart_base = (volatile u8 *)S5P_PA_UART(CONFIG_S3C_LOWLEVEL_UART_PORT);
-}
-#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/uncompress.h b/arch/arm/mach-s5pv210/include/mach/uncompress.h
deleted file mode 100644
index 231cb07de058..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/uncompress.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/include/mach/uncompress.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5PV210 - uncompress code
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-#include <mach/map.h>
-#include <plat/uncompress.h>
-static void arch_detect_cpu(void)
-{
-        /* we do not need to do any cpu detection here at the moment. */
-        fifo_mask = S5PV210_UFSTAT_TXMASK;
-        fifo_max = 63 << S5PV210_UFSTAT_TXSHIFT;
-        uart_base = (volatile u8 *)S5P_PA_UART(CONFIG_S3C_LOWLEVEL_UART_PORT);
-}
-#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index 0e001a489a79..58c2b844e0a3 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -9,5 +9,6 @@ config ARCH_ZYNQ
        select ICST
        select CADENCE_TTC_TIMER
        select ARM_GLOBAL_TIMER if !CPU_FREQ
+        select MFD_SYSCON
        help
          Support for Xilinx Zynq ARM Cortex A9 Platform
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index a39be8e80856..6fcc584c1a11 100644
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -19,6 +19,7 @@
 #include <linux/cpumask.h>
 #include <linux/platform_device.h>
 #include <linux/clk.h>
+#include <linux/clk-provider.h>
 #include <linux/clk/zynq.h>
 #include <linux/clocksource.h>
 #include <linux/of_address.h>
@@ -75,11 +76,16 @@ static void __init zynq_init_machine(void)
        platform_device_register(&zynq_cpuidle_device);
        platform_device_register_full(&devinfo);
+        zynq_slcr_init();
 }
 static void __init zynq_timer_init(void)
 {
-        zynq_slcr_init();
+        zynq_early_slcr_init();
+        zynq_clock_init();
+        of_clk_init(NULL);
        clocksource_of_init();
 }
diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h
index c22c92cea8cb..b097844d3175 100644
--- a/arch/arm/mach-zynq/common.h
+++ b/arch/arm/mach-zynq/common.h
@@ -20,6 +20,7 @@
 void zynq_secondary_startup(void);
 extern int zynq_slcr_init(void);
+extern int zynq_early_slcr_init(void);
 extern void zynq_slcr_system_reset(void);
 extern void zynq_slcr_cpu_stop(int cpu);
 extern void zynq_slcr_cpu_start(int cpu);
@@ -33,7 +34,6 @@ extern int zynq_cpun_start(u32 address, int cpu);
 extern struct smp_operations zynq_smp_ops __initdata;
 #endif
-extern void __iomem *zynq_slcr_base;
 extern void __iomem *zynq_scu_base;
 /* Hotplug */
diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c
index 1836d5a34606..a37d49a6e657 100644
--- a/arch/arm/mach-zynq/slcr.c
+++ b/arch/arm/mach-zynq/slcr.c
@@ -15,7 +15,9 @@
 */
 #include <linux/io.h>
+#include <linux/mfd/syscon.h>
 #include <linux/of_address.h>
+#include <linux/regmap.h>
 #include <linux/clk/zynq.h>
 #include "common.h"
@@ -29,7 +31,56 @@
 #define SLCR_A9_CPU_CLKSTOP             0x10
 #define SLCR_A9_CPU_RST                 0x1
-void __iomem *zynq_slcr_base;
+static void __iomem *zynq_slcr_base;
+static struct regmap *zynq_slcr_regmap;
+/**
+ * zynq_slcr_write - Write to a register in SLCR block
+ *
+ * @val:        Value to write to the register
+ * @offset:     Register offset in SLCR block
+ *
+ * Return:      a negative value on error, 0 on success
+ */
+static int zynq_slcr_write(u32 val, u32 offset)
+{
+        if (!zynq_slcr_regmap) {
+                writel(val, zynq_slcr_base + offset);
+                return 0;
+        }
+        return regmap_write(zynq_slcr_regmap, offset, val);
+}
+/**
+ * zynq_slcr_read - Read a register in SLCR block
+ *
+ * @val:        Pointer to value to be read from SLCR
+ * @offset:     Register offset in SLCR block
+ *
+ * Return:      a negative value on error, 0 on success
+ */
+static int zynq_slcr_read(u32 *val, u32 offset)
+{
+        if (zynq_slcr_regmap)
+                return regmap_read(zynq_slcr_regmap, offset, val);
+        *val = readl(zynq_slcr_base + offset);
+        return 0;
+}
+/**
+ * zynq_slcr_unlock - Unlock SLCR registers
+ *
+ * Return:      a negative value on error, 0 on success
+ */
+static inline int zynq_slcr_unlock(void)
+{
+        zynq_slcr_write(SLCR_UNLOCK_MAGIC, SLCR_UNLOCK_OFFSET);
+        return 0;
+}
 /**
 * zynq_slcr_system_reset - Reset the entire system.
@@ -43,16 +94,16 @@ void zynq_slcr_system_reset(void)
         * Note that this seems to require raw i/o
         * functions or there's a lockup?
         */
-        writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET);
+        zynq_slcr_unlock();
        /*
         * Clear 0x0F000000 bits of reboot status register to workaround
         * the FSBL not loading the bitstream after soft-reboot
         * This is a temporary solution until we know more.
         */
-        reboot = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
+        zynq_slcr_read(&reboot, SLCR_REBOOT_STATUS_OFFSET);
-        writel(reboot & 0xF0FFFFFF, zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
+        zynq_slcr_write(reboot & 0xF0FFFFFF, SLCR_REBOOT_STATUS_OFFSET);
-        writel(1, zynq_slcr_base + SLCR_PS_RST_CTRL_OFFSET);
+        zynq_slcr_write(1, SLCR_PS_RST_CTRL_OFFSET);
 }
 /**
@@ -61,11 +112,13 @@ void zynq_slcr_system_reset(void)
 */
 void zynq_slcr_cpu_start(int cpu)
 {
-        u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
+        u32 reg;
+        zynq_slcr_read(&reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
        reg &= ~(SLCR_A9_CPU_RST << cpu);
-        writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
+        zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
        reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu);
-        writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
+        zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
 }
 /**
@@ -74,19 +127,40 @@ void zynq_slcr_cpu_start(int cpu)
 */
 void zynq_slcr_cpu_stop(int cpu)
 {
-        u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
+        u32 reg;
+        zynq_slcr_read(&reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
        reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu;
-        writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
+        zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
 }
 /**
- * zynq_slcr_init
+ * zynq_slcr_init - Regular slcr driver init
- * Returns 0 on success, negative errno otherwise.
+ *
+ * Return:      0 on success, negative errno otherwise.
 *
 * Called early during boot from platform code to remap SLCR area.
 */
 int __init zynq_slcr_init(void)
 {
+        zynq_slcr_regmap = syscon_regmap_lookup_by_compatible("xlnx,zynq-slcr");
+        if (IS_ERR(zynq_slcr_regmap)) {
+                pr_err("%s: failed to find zynq-slcr\n", __func__);
+                return -ENODEV;
+        }
+        return 0;
+}
+/**
+ * zynq_early_slcr_init - Early slcr init function
+ *
+ * Return:      0 on success, negative errno otherwise.
+ *
+ * Called very early during boot from platform code to unlock SLCR.
+ */
+int __init zynq_early_slcr_init(void)
+{
        struct device_node *np;
        np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr");
@@ -101,13 +175,13 @@ int __init zynq_slcr_init(void)
                BUG();
        }
+        np->data = (__force void *)zynq_slcr_base;
        /* unlock the SLCR so that registers can be changed */
-        writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET);
+        zynq_slcr_unlock();
        pr_info("%s mapped to %p\n", np->name, zynq_slcr_base);
-        zynq_clock_init(zynq_slcr_base);
        of_node_put(np);
        return 0;
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 9267d29549b4..25c826ed3b65 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -47,9 +47,11 @@ obj-$(CONFIG_SAMSUNG_DMADEV)	+= dma-ops.o
 # PM support
+obj-$(CONFIG_PM_SLEEP)          += pm-common.o
 obj-$(CONFIG_SAMSUNG_PM)        += pm.o
 obj-$(CONFIG_SAMSUNG_PM_GPIO)   += pm-gpio.o
 obj-$(CONFIG_SAMSUNG_PM_CHECK)  += pm-check.o
+obj-$(CONFIG_SAMSUNG_PM_DEBUG)  += pm-debug.o
 obj-$(CONFIG_SAMSUNG_WAKEMASK)  += wakeup-mask.o
 obj-$(CONFIG_SAMSUNG_WDT_RESET) += watchdog-reset.o
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
index ddfebddb4105..d103ac1a52af 100644
--- a/arch/arm/plat-samsung/clock.c
+++ b/arch/arm/plat-samsung/clock.c
@@ -43,7 +43,6 @@
 #include <linux/debugfs.h>
 #endif
-#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <plat/cpu-freq.h>
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index c64a39ac1b04..ead4f1c94058 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -31,6 +31,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mmc/host.h>
 #include <linux/ioport.h>
+#include <linux/sizes.h>
 #include <linux/platform_data/s3c-hsudc.h>
 #include <linux/platform_data/s3c-hsotg.h>
 #include <linux/platform_data/dma-s3c24xx.h>
@@ -42,7 +43,6 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include <mach/hardware.h>
 #include <mach/dma.h>
 #include <mach/irqs.h>
 #include <mach/map.h>
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 31164b34d4c4..5992b8dd9b89 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -20,6 +20,9 @@
 extern unsigned long samsung_cpu_id;
+#define S3C2410_CPU_ID          0x32410000
+#define S3C2410_CPU_MASK        0xFFFFFFFF
 #define S3C24XX_CPU_ID          0x32400000
 #define S3C24XX_CPU_MASK        0xFFF00000
@@ -56,6 +59,7 @@ static inline int is_samsung_##name(void)	\
        return ((samsung_cpu_id & mask) == (id & mask));        \
 }
+IS_SAMSUNG_CPU(s3c2410, S3C2410_CPU_ID, S3C2410_CPU_MASK)
 IS_SAMSUNG_CPU(s3c24xx, S3C24XX_CPU_ID, S3C24XX_CPU_MASK)
 IS_SAMSUNG_CPU(s3c2412, S3C2412_CPU_ID, S3C2412_CPU_MASK)
 IS_SAMSUNG_CPU(s3c6400, S3C6400_CPU_ID, S3C64XX_CPU_MASK)
@@ -76,8 +80,10 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
    defined(CONFIG_CPU_S3C2442) || defined(CONFIG_CPU_S3C244X) || \
    defined(CONFIG_CPU_S3C2443)
 # define soc_is_s3c24xx()       is_samsung_s3c24xx()
+# define soc_is_s3c2410()       is_samsung_s3c2410()
 #else
 # define soc_is_s3c24xx()       0
+# define soc_is_s3c2410()       0
 #endif
 #if defined(CONFIG_CPU_S3C2412)
@@ -160,6 +166,10 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
 # define soc_is_exynos5440()    0
 #endif
+#define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4212() || \
+                          soc_is_exynos4412())
+#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5420())
 #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
 #ifndef KHZ
diff --git a/arch/arm/plat-samsung/include/plat/mfc.h b/arch/arm/plat-samsung/include/plat/mfc.h
index e6d7c42d68b6..033654e91e22 100644
--- a/arch/arm/plat-samsung/include/plat/mfc.h
+++ b/arch/arm/plat-samsung/include/plat/mfc.h
@@ -32,7 +32,4 @@ struct s5p_mfc_dt_meminfo {
 void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
                                phys_addr_t lbase, unsigned int lsize);
-int __init s5p_fdt_find_mfc_mem(unsigned long node, const char *uname,
-                                int depth, void *data);
 #endif /* __PLAT_SAMSUNG_MFC_H */
diff --git a/arch/arm/plat-samsung/include/plat/pm-common.h b/arch/arm/plat-samsung/include/plat/pm-common.h
new file mode 100644
index 000000000000..8705f9e0e288
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/pm-common.h
@@ -0,0 +1,110 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ *      Tomasz Figa <t.figa@samsung.com>
+ * Copyright (c) 2004 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Written by Ben Dooks, <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#ifndef __PLAT_SAMSUNG_PM_COMMON_H
+#define __PLAT_SAMSUNG_PM_COMMON_H __FILE__
+#include <linux/irq.h>
+/* sleep save info */
+/**
+ * struct sleep_save - save information for shared peripherals.
+ * @reg: Pointer to the register to save.
+ * @val: Holder for the value saved from reg.
+ *
+ * This describes a list of registers which is used by the pm core and
+ * other subsystem to save and restore register values over suspend.
+ */
+struct sleep_save {
+        void __iomem    *reg;
+        unsigned long   val;
+};
+#define SAVE_ITEM(x) \
+        { .reg = (x) }
+/* helper functions to save/restore lists of registers. */
+extern void s3c_pm_do_save(struct sleep_save *ptr, int count);
+extern void s3c_pm_do_restore(const struct sleep_save *ptr, int count);
+extern void s3c_pm_do_restore_core(const struct sleep_save *ptr, int count);
+/* PM debug functions */
+/**
+ * struct pm_uart_save - save block for core UART
+ * @ulcon: Save value for S3C2410_ULCON
+ * @ucon: Save value for S3C2410_UCON
+ * @ufcon: Save value for S3C2410_UFCON
+ * @umcon: Save value for S3C2410_UMCON
+ * @ubrdiv: Save value for S3C2410_UBRDIV
+ *
+ * Save block for UART registers to be held over sleep and restored if they
+ * are needed (say by debug).
+*/
+struct pm_uart_save {
+        u32     ulcon;
+        u32     ucon;
+        u32     ufcon;
+        u32     umcon;
+        u32     ubrdiv;
+        u32     udivslot;
+};
+#ifdef CONFIG_SAMSUNG_PM_DEBUG
+/**
+ * s3c_pm_dbg() - low level debug function for use in suspend/resume.
+ * @msg: The message to print.
+ *
+ * This function is used mainly to debug the resume process before the system
+ * can rely on printk/console output. It uses the low-level debugging output
+ * routine printascii() to do its work.
+ */
+extern void s3c_pm_dbg(const char *msg, ...);
+/**
+ * s3c_pm_debug_init() - suspend/resume low level debug initialization.
+ * @base: Virtual base of UART to use for suspend/resume debugging.
+ *
+ * This function needs to be called before S3C_PMDBG() can be used, to set up
+ * UART port base address and configuration.
+ */
+extern void s3c_pm_debug_init(void);
+#define S3C_PMDBG(fmt...) s3c_pm_dbg(fmt)
+extern void s3c_pm_save_uarts(void);
+extern void s3c_pm_restore_uarts(void);
+#else
+#define S3C_PMDBG(fmt...) pr_debug(fmt)
+#define s3c_pm_debug_init() do { } while (0)
+static inline void s3c_pm_save_uarts(void) { }
+static inline void s3c_pm_restore_uarts(void) { }
+#endif
+/* suspend memory checking */
+#ifdef CONFIG_SAMSUNG_PM_CHECK
+extern void s3c_pm_check_prepare(void);
+extern void s3c_pm_check_restore(void);
+extern void s3c_pm_check_cleanup(void);
+extern void s3c_pm_check_store(void);
+#else
+#define s3c_pm_check_prepare() do { } while (0)
+#define s3c_pm_check_restore() do { } while (0)
+#define s3c_pm_check_cleanup() do { } while (0)
+#define s3c_pm_check_store()   do { } while (0)
+#endif
+#endif
diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h
index ff6063f0d5ea..e17d871b934c 100644
--- a/arch/arm/plat-samsung/include/plat/pm.h
+++ b/arch/arm/plat-samsung/include/plat/pm.h
@@ -15,7 +15,7 @@
 * management
 */
-#include <linux/irq.h>
+#include <plat/pm-common.h>
 struct device;
@@ -54,56 +54,10 @@ extern int (*pm_cpu_sleep)(unsigned long);
 extern unsigned long s3c_pm_flags;
-extern unsigned char pm_uart_udivslot;  /* true to save UART UDIVSLOT */
 /* from sleep.S */
 extern int s3c2410_cpu_suspend(unsigned long);
-/* sleep save info */
-/**
- * struct sleep_save - save information for shared peripherals.
- * @reg: Pointer to the register to save.
- * @val: Holder for the value saved from reg.
- *
- * This describes a list of registers which is used by the pm core and
- * other subsystem to save and restore register values over suspend.
- */
-struct sleep_save {
-        void __iomem    *reg;
-        unsigned long   val;
-};
-#define SAVE_ITEM(x) \
-        { .reg = (x) }
-/**
- * struct pm_uart_save - save block for core UART
- * @ulcon: Save value for S3C2410_ULCON
- * @ucon: Save value for S3C2410_UCON
- * @ufcon: Save value for S3C2410_UFCON
- * @umcon: Save value for S3C2410_UMCON
- * @ubrdiv: Save value for S3C2410_UBRDIV
- *
- * Save block for UART registers to be held over sleep and restored if they
- * are needed (say by debug).
-*/
-struct pm_uart_save {
-        u32     ulcon;
-        u32     ucon;
-        u32     ufcon;
-        u32     umcon;
-        u32     ubrdiv;
-        u32     udivslot;
-};
-/* helper functions to save/restore lists of registers. */
-extern void s3c_pm_do_save(struct sleep_save *ptr, int count);
-extern void s3c_pm_do_restore(const struct sleep_save *ptr, int count);
-extern void s3c_pm_do_restore_core(const struct sleep_save *ptr, int count);
 #ifdef CONFIG_SAMSUNG_PM
 extern int s3c_irq_wake(struct irq_data *data, unsigned int state);
 extern int s3c_irqext_wake(struct irq_data *data, unsigned int state);
@@ -114,24 +68,6 @@ extern void s3c_cpu_resume(void);
 #define s3c_cpu_resume NULL
 #endif
-/* PM debug functions */
-#ifdef CONFIG_SAMSUNG_PM_DEBUG
-/**
- * s3c_pm_dbg() - low level debug function for use in suspend/resume.
- * @msg: The message to print.
- *
- * This function is used mainly to debug the resume process before the system
- * can rely on printk/console output. It uses the low-level debugging output
- * routine printascii() to do its work.
- */
-extern void s3c_pm_dbg(const char *msg, ...);
-#define S3C_PMDBG(fmt...) s3c_pm_dbg(fmt)
-#else
-#define S3C_PMDBG(fmt...) printk(KERN_DEBUG fmt)
-#endif
 #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
 /**
 * s3c_pm_debug_smdkled() - Debug PM suspend/resume via SMDK Board LEDs
@@ -144,20 +80,6 @@ extern void s3c_pm_debug_smdkled(u32 set, u32 clear);
 static inline void s3c_pm_debug_smdkled(u32 set, u32 clear) { }
 #endif /* CONFIG_S3C_PM_DEBUG_LED_SMDK */
-/* suspend memory checking */
-#ifdef CONFIG_SAMSUNG_PM_CHECK
-extern void s3c_pm_check_prepare(void);
-extern void s3c_pm_check_restore(void);
-extern void s3c_pm_check_cleanup(void);
-extern void s3c_pm_check_store(void);
-#else
-#define s3c_pm_check_prepare() do { } while(0)
-#define s3c_pm_check_restore() do { } while(0)
-#define s3c_pm_check_cleanup() do { } while(0)
-#define s3c_pm_check_store()   do { } while(0)
-#endif
 /**
 * s3c_pm_configure_extint() - ensure pins are correctly set for IRQ
 *
diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h
deleted file mode 100644
index 61054fd88d43..000000000000
--- a/arch/arm/plat-samsung/include/plat/uncompress.h
+++ /dev/null
@@ -1,175 +0,0 @@
-/* arch/arm/plat-samsung/include/plat/uncompress.h
- *
- * Copyright 2003, 2007 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C - uncompress code
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_PLAT_UNCOMPRESS_H
-#define __ASM_PLAT_UNCOMPRESS_H
-typedef unsigned int upf_t;     /* cannot include linux/serial_core.h */
-/* uart setup */
-unsigned int fifo_mask;
-unsigned int fifo_max;
-volatile u8 *uart_base;
-/* forward declerations */
-static void arch_detect_cpu(void);
-/* defines for UART registers */
-#include <linux/serial_s3c.h>
-/* working in physical space... */
-#define S3C_WDOGREG(x)  ((S3C_PA_WDT + (x)))
-#define S3C2410_WTCON   S3C_WDOGREG(0x00)
-#define S3C2410_WTDAT   S3C_WDOGREG(0x04)
-#define S3C2410_WTCNT   S3C_WDOGREG(0x08)
-#define S3C2410_WTCON_RSTEN     (1 << 0)
-#define S3C2410_WTCON_ENABLE    (1 << 5)
-#define S3C2410_WTCON_DIV128    (3 << 3)
-#define S3C2410_WTCON_PRESCALE(x)       ((x) << 8)
-/* how many bytes we allow into the FIFO at a time in FIFO mode */
-#define FIFO_MAX         (14)
-static __inline__ void
-uart_wr(unsigned int reg, unsigned int val)
-{
-        volatile unsigned int *ptr;
-        ptr = (volatile unsigned int *)(reg + uart_base);
-        *ptr = val;
-}
-static __inline__ unsigned int
-uart_rd(unsigned int reg)
-{
-        volatile unsigned int *ptr;
-        ptr = (volatile unsigned int *)(reg + uart_base);
-        return *ptr;
-}
-/* we can deal with the case the UARTs are being run
- * in FIFO mode, so that we don't hold up our execution
- * waiting for tx to happen...
-*/
-static void putc(int ch)
-{
-        if (!config_enabled(CONFIG_DEBUG_LL))
-                return;
-        if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
-                int level;
-                while (1) {
-                        level = uart_rd(S3C2410_UFSTAT);
-                        level &= fifo_mask;
-                        if (level < fifo_max)
-                                break;
-                }
-        } else {
-                /* not using fifos */
-                while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
-                        barrier();
-        }
-        /* write byte to transmission register */
-        uart_wr(S3C2410_UTXH, ch);
-}
-static inline void flush(void)
-{
-}
-#define __raw_writel(d, ad)                     \
-        do {                                                    \
-                *((volatile unsigned int __force *)(ad)) = (d); \
-        } while (0)
-#ifdef CONFIG_S3C_BOOT_ERROR_RESET
-static void arch_decomp_error(const char *x)
-{
-        putstr("\n\n");
-        putstr(x);
-        putstr("\n\n -- System resetting\n");
-        __raw_writel(0x4000, S3C2410_WTDAT);
-        __raw_writel(0x4000, S3C2410_WTCNT);
-        __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
-        while(1);
-}
-#define arch_error arch_decomp_error
-#endif
-#ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO
-static inline void arch_enable_uart_fifo(void)
-{
-        u32 fifocon;
-        if (!config_enabled(CONFIG_DEBUG_LL))
-                return;
-        fifocon = uart_rd(S3C2410_UFCON);
-        if (!(fifocon & S3C2410_UFCON_FIFOMODE)) {
-                fifocon |= S3C2410_UFCON_RESETBOTH;
-                uart_wr(S3C2410_UFCON, fifocon);
-                /* wait for fifo reset to complete */
-                while (1) {
-                        fifocon = uart_rd(S3C2410_UFCON);
-                        if (!(fifocon & S3C2410_UFCON_RESETBOTH))
-                                break;
-                }
-                uart_wr(S3C2410_UFCON, S3C2410_UFCON_FIFOMODE);
-        }
-}
-#else
-#define arch_enable_uart_fifo() do { } while(0)
-#endif
-static void
-arch_decomp_setup(void)
-{
-        /* we may need to setup the uart(s) here if we are not running
-         * on an BAST... the BAST will have left the uarts configured
-         * after calling linux.
-         */
-        arch_detect_cpu();
-        /* Enable the UART FIFOs if they where not enabled and our
-         * configuration says we should turn them on.
-         */
-        arch_enable_uart_fifo();
-}
-#endif /* __ASM_PLAT_UNCOMPRESS_H */
diff --git a/arch/arm/plat-samsung/init.c b/arch/arm/plat-samsung/init.c
index c32df1f202eb..a1f925f3121f 100644
--- a/arch/arm/plat-samsung/init.c
+++ b/arch/arm/plat-samsung/init.c
@@ -25,8 +25,6 @@
 #include <linux/platform_device.h>
 #include <linux/of.h>
-#include <mach/hardware.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/plat-samsung/pm-check.c b/arch/arm/plat-samsung/pm-check.c
index 3cbd62666b1e..04aff2c31b46 100644
--- a/arch/arm/plat-samsung/pm-check.c
+++ b/arch/arm/plat-samsung/pm-check.c
@@ -19,7 +19,7 @@
 #include <linux/ioport.h>
 #include <linux/slab.h>
-#include <plat/pm.h>
+#include <plat/pm-common.h>
 #if CONFIG_SAMSUNG_PM_CHECK_CHUNKSIZE < 1
 #error CONFIG_SAMSUNG_PM_CHECK_CHUNKSIZE must be a positive non-zero value
diff --git a/arch/arm/plat-samsung/pm-common.c b/arch/arm/plat-samsung/pm-common.c
new file mode 100644
index 000000000000..515cd53372bd
--- /dev/null
+++ b/arch/arm/plat-samsung/pm-common.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ *      Tomasz Figa <t.figa@samsung.com>
+ * Copyright (C) 2008 Openmoko, Inc.
+ * Copyright (C) 2004-2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * Samsung common power management helper functions.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <plat/pm-common.h>
+/* helper functions to save and restore register state */
+/**
+ * s3c_pm_do_save() - save a set of registers for restoration on resume.
+ * @ptr: Pointer to an array of registers.
+ * @count: Size of the ptr array.
+ *
+ * Run through the list of registers given, saving their contents in the
+ * array for later restoration when we wakeup.
+ */
+void s3c_pm_do_save(struct sleep_save *ptr, int count)
+{
+        for (; count > 0; count--, ptr++) {
+                ptr->val = __raw_readl(ptr->reg);
+                S3C_PMDBG("saved %p value %08lx\n", ptr->reg, ptr->val);
+        }
+}
+/**
+ * s3c_pm_do_restore() - restore register values from the save list.
+ * @ptr: Pointer to an array of registers.
+ * @count: Size of the ptr array.
+ *
+ * Restore the register values saved from s3c_pm_do_save().
+ *
+ * Note, we do not use S3C_PMDBG() in here, as the system may not have
+ * restore the UARTs state yet
+*/
+void s3c_pm_do_restore(const struct sleep_save *ptr, int count)
+{
+        for (; count > 0; count--, ptr++) {
+                pr_debug("restore %p (restore %08lx, was %08x)\n",
+                                ptr->reg, ptr->val, __raw_readl(ptr->reg));
+                __raw_writel(ptr->val, ptr->reg);
+        }
+}
+/**
+ * s3c_pm_do_restore_core() - early restore register values from save list.
+ *
+ * This is similar to s3c_pm_do_restore() except we try and minimise the
+ * side effects of the function in case registers that hardware might need
+ * to work has been restored.
+ *
+ * WARNING: Do not put any debug in here that may effect memory or use
+ * peripherals, as things may be changing!
+*/
+void s3c_pm_do_restore_core(const struct sleep_save *ptr, int count)
+{
+        for (; count > 0; count--, ptr++)
+                __raw_writel(ptr->val, ptr->reg);
+}
diff --git a/arch/arm/plat-samsung/pm-debug.c b/arch/arm/plat-samsung/pm-debug.c
new file mode 100644
index 000000000000..8f19f66388dd
--- /dev/null
+++ b/arch/arm/plat-samsung/pm-debug.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ *      Tomasz Figa <t.figa@samsung.com>
+ * Copyright (C) 2008 Openmoko, Inc.
+ * Copyright (C) 2004-2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * Samsung common power management (suspend to RAM) debug support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/serial_core.h>
+#include <linux/io.h>
+#include <asm/mach/map.h>
+#include <plat/cpu.h>
+#include <plat/pm-common.h>
+#ifdef CONFIG_SAMSUNG_ATAGS
+#include <mach/pm-core.h>
+#else
+static inline void s3c_pm_debug_init_uart(void) {}
+static inline void s3c_pm_arch_update_uart(void __iomem *regs,
+                                           struct pm_uart_save *save) {}
+#endif
+static struct pm_uart_save uart_save;
+extern void printascii(const char *);
+void s3c_pm_dbg(const char *fmt, ...)
+{
+        va_list va;
+        char buff[256];
+        va_start(va, fmt);
+        vsnprintf(buff, sizeof(buff), fmt, va);
+        va_end(va);
+        printascii(buff);
+}
+void s3c_pm_debug_init(void)
+{
+        /* restart uart clocks so we can use them to output */
+        s3c_pm_debug_init_uart();
+}
+static inline void __iomem *s3c_pm_uart_base(void)
+{
+        unsigned long paddr;
+        unsigned long vaddr;
+        debug_ll_addr(&paddr, &vaddr);
+        return (void __iomem *)vaddr;
+}
+void s3c_pm_save_uarts(void)
+{
+        void __iomem *regs = s3c_pm_uart_base();
+        struct pm_uart_save *save = &uart_save;
+        save->ulcon = __raw_readl(regs + S3C2410_ULCON);
+        save->ucon = __raw_readl(regs + S3C2410_UCON);
+        save->ufcon = __raw_readl(regs + S3C2410_UFCON);
+        save->umcon = __raw_readl(regs + S3C2410_UMCON);
+        save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV);
+        if (!soc_is_s3c2410())
+                save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT);
+        S3C_PMDBG("UART[%p]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n",
+                  regs, save->ulcon, save->ucon, save->ufcon, save->ubrdiv);
+}
+void s3c_pm_restore_uarts(void)
+{
+        void __iomem *regs = s3c_pm_uart_base();
+        struct pm_uart_save *save = &uart_save;
+        s3c_pm_arch_update_uart(regs, save);
+        __raw_writel(save->ulcon, regs + S3C2410_ULCON);
+        __raw_writel(save->ucon,  regs + S3C2410_UCON);
+        __raw_writel(save->ufcon, regs + S3C2410_UFCON);
+        __raw_writel(save->umcon, regs + S3C2410_UMCON);
+        __raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV);
+        if (!soc_is_s3c2410())
+                __raw_writel(save->udivslot, regs + S3C2443_DIVSLOT);
+}
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
index ae9baa2d6381..f8c0f9797dcf 100644
--- a/arch/arm/plat-samsung/pm.c
+++ b/arch/arm/plat-samsung/pm.c
@@ -17,7 +17,6 @@
 #include <linux/errno.h>
 #include <linux/delay.h>
 #include <linux/of.h>
-#include <linux/serial_core.h>
 #include <linux/serial_s3c.h>
 #include <linux/io.h>
@@ -25,7 +24,6 @@
 #include <asm/suspend.h>
 #ifdef CONFIG_SAMSUNG_ATAGS
-#include <mach/hardware.h>
 #include <mach/map.h>
 #ifndef CONFIG_ARCH_EXYNOS
 #include <mach/regs-clock.h>
@@ -43,93 +41,6 @@
 unsigned long s3c_pm_flags;
-/* Debug code:
- *
- * This code supports debug output to the low level UARTs for use on
- * resume before the console layer is available.
-*/
-#ifdef CONFIG_SAMSUNG_PM_DEBUG
-extern void printascii(const char *);
-void s3c_pm_dbg(const char *fmt, ...)
-{
-        va_list va;
-        char buff[256];
-        va_start(va, fmt);
-        vsnprintf(buff, sizeof(buff), fmt, va);
-        va_end(va);
-        printascii(buff);
-}
-static inline void s3c_pm_debug_init(void)
-{
-        /* restart uart clocks so we can use them to output */
-        s3c_pm_debug_init_uart();
-}
-#else
-#define s3c_pm_debug_init() do { } while(0)
-#endif /* CONFIG_SAMSUNG_PM_DEBUG */
-/* Save the UART configurations if we are configured for debug. */
-unsigned char pm_uart_udivslot;
-#ifdef CONFIG_SAMSUNG_PM_DEBUG
-static struct pm_uart_save uart_save;
-static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save)
-{
-        void __iomem *regs = S3C_VA_UARTx(uart);
-        save->ulcon = __raw_readl(regs + S3C2410_ULCON);
-        save->ucon = __raw_readl(regs + S3C2410_UCON);
-        save->ufcon = __raw_readl(regs + S3C2410_UFCON);
-        save->umcon = __raw_readl(regs + S3C2410_UMCON);
-        save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV);
-        if (pm_uart_udivslot)
-                save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT);
-        S3C_PMDBG("UART[%d]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n",
-                  uart, save->ulcon, save->ucon, save->ufcon, save->ubrdiv);
-}
-static void s3c_pm_save_uarts(void)
-{
-        s3c_pm_save_uart(CONFIG_DEBUG_S3C_UART, &uart_save);
-}
-static void s3c_pm_restore_uart(unsigned int uart, struct pm_uart_save *save)
-{
-        void __iomem *regs = S3C_VA_UARTx(uart);
-        s3c_pm_arch_update_uart(regs, save);
-        __raw_writel(save->ulcon, regs + S3C2410_ULCON);
-        __raw_writel(save->ucon,  regs + S3C2410_UCON);
-        __raw_writel(save->ufcon, regs + S3C2410_UFCON);
-        __raw_writel(save->umcon, regs + S3C2410_UMCON);
-        __raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV);
-        if (pm_uart_udivslot)
-                __raw_writel(save->udivslot, regs + S3C2443_DIVSLOT);
-}
-static void s3c_pm_restore_uarts(void)
-{
-        s3c_pm_restore_uart(CONFIG_DEBUG_S3C_UART, &uart_save);
-}
-#else
-static void s3c_pm_save_uarts(void) { }
-static void s3c_pm_restore_uarts(void) { }
-#endif
 /* The IRQ ext-int code goes here, it is too small to currently bother
 * with its own file. */
@@ -154,62 +65,6 @@ int s3c_irqext_wake(struct irq_data *data, unsigned int state)
        return 0;
 }
-/* helper functions to save and restore register state */
-/**
- * s3c_pm_do_save() - save a set of registers for restoration on resume.
- * @ptr: Pointer to an array of registers.
- * @count: Size of the ptr array.
- *
- * Run through the list of registers given, saving their contents in the
- * array for later restoration when we wakeup.
- */
-void s3c_pm_do_save(struct sleep_save *ptr, int count)
-{
-        for (; count > 0; count--, ptr++) {
-                ptr->val = __raw_readl(ptr->reg);
-                S3C_PMDBG("saved %p value %08lx\n", ptr->reg, ptr->val);
-        }
-}
-/**
- * s3c_pm_do_restore() - restore register values from the save list.
- * @ptr: Pointer to an array of registers.
- * @count: Size of the ptr array.
- *
- * Restore the register values saved from s3c_pm_do_save().
- *
- * Note, we do not use S3C_PMDBG() in here, as the system may not have
- * restore the UARTs state yet
-*/
-void s3c_pm_do_restore(const struct sleep_save *ptr, int count)
-{
-        for (; count > 0; count--, ptr++) {
-                printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n",
-                       ptr->reg, ptr->val, __raw_readl(ptr->reg));
-                __raw_writel(ptr->val, ptr->reg);
-        }
-}
-/**
- * s3c_pm_do_restore_core() - early restore register values from save list.
- *
- * This is similar to s3c_pm_do_restore() except we try and minimise the
- * side effects of the function in case registers that hardware might need
- * to work has been restored.
- *
- * WARNING: Do not put any debug in here that may effect memory or use
- * peripherals, as things may be changing!
-*/
-void s3c_pm_do_restore_core(const struct sleep_save *ptr, int count)
-{
-        for (; count > 0; count--, ptr++)
-                __raw_writel(ptr->val, ptr->reg);
-}
 /* s3c2410_pm_show_resume_irqs
 *
 * print any IRQs asserted at resume time (ie, we woke from)
diff --git a/arch/arm/plat-samsung/s5p-dev-mfc.c b/arch/arm/plat-samsung/s5p-dev-mfc.c
index ad51f85fbd01..98087b655df0 100644
--- a/arch/arm/plat-samsung/s5p-dev-mfc.c
+++ b/arch/arm/plat-samsung/s5p-dev-mfc.c
@@ -122,32 +122,35 @@ device_initcall(s5p_mfc_memory_init);
 #endif
 #ifdef CONFIG_OF
-int __init s5p_fdt_find_mfc_mem(unsigned long node, const char *uname,
+int __init s5p_fdt_alloc_mfc_mem(unsigned long node, const char *uname,
                                int depth, void *data)
 {
        __be32 *prop;
        unsigned long len;
-        struct s5p_mfc_dt_meminfo *mfc_mem = data;
+        struct s5p_mfc_dt_meminfo mfc_mem;
        if (!data)
                return 0;
-        if (!of_flat_dt_is_compatible(node, mfc_mem->compatible))
+        if (!of_flat_dt_is_compatible(node, data))
                return 0;
        prop = of_get_flat_dt_prop(node, "samsung,mfc-l", &len);
        if (!prop || (len != 2 * sizeof(unsigned long)))
                return 0;
-        mfc_mem->loff = be32_to_cpu(prop[0]);
+        mfc_mem.loff = be32_to_cpu(prop[0]);
-        mfc_mem->lsize = be32_to_cpu(prop[1]);
+        mfc_mem.lsize = be32_to_cpu(prop[1]);
        prop = of_get_flat_dt_prop(node, "samsung,mfc-r", &len);
        if (!prop || (len != 2 * sizeof(unsigned long)))
                return 0;
-        mfc_mem->roff = be32_to_cpu(prop[0]);
+        mfc_mem.roff = be32_to_cpu(prop[0]);
-        mfc_mem->rsize = be32_to_cpu(prop[1]);
+        mfc_mem.rsize = be32_to_cpu(prop[1]);
+        s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize,
+                        mfc_mem.loff, mfc_mem.lsize);
        return 1;
 }
diff --git a/arch/arm/plat-samsung/s5p-dev-uart.c b/arch/arm/plat-samsung/s5p-dev-uart.c
index cafa3deddcc1..8c4487af98c8 100644
--- a/arch/arm/plat-samsung/s5p-dev-uart.c
+++ b/arch/arm/plat-samsung/s5p-dev-uart.c
@@ -18,7 +18,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
-#include <mach/hardware.h>
 #include <mach/map.h>
 #include <plat/devs.h>
diff --git a/arch/arm/plat-samsung/s5p-sleep.S b/arch/arm/plat-samsung/s5p-sleep.S
index a030e7301da8..c5001659bdf8 100644
--- a/arch/arm/plat-samsung/s5p-sleep.S
+++ b/arch/arm/plat-samsung/s5p-sleep.S
@@ -23,18 +23,7 @@
 #include <linux/linkage.h>
 #include <asm/asm-offsets.h>
-#include <asm/hardware/cache-l2x0.h>
-#define CPU_MASK        0xff0ffff0
-#define CPU_CORTEX_A9   0x410fc090
-/*
- *       The following code is located into the .data section. This is to
- *       allow l2x0_regs_phys to be accessed with a relative load while we
- *       can't rely on any MMU translation. We could have put l2x0_regs_phys
- *       in the .text section as well, but some setups might insist on it to
- *       be truly read-only. (Reference from: arch/arm/kernel/sleep.S)
- */
        .data
        .align
@@ -53,37 +42,5 @@
         */
 ENTRY(s3c_cpu_resume)
-#ifdef CONFIG_CACHE_L2X0
-        mrc     p15, 0, r0, c0, c0, 0
-        ldr     r1, =CPU_MASK
-        and     r0, r0, r1
-        ldr     r1, =CPU_CORTEX_A9
-        cmp     r0, r1
-        bne     resume_l2on
-        adr     r0, l2x0_regs_phys
-        ldr     r0, [r0]
-        ldr     r1, [r0, #L2X0_R_PHY_BASE]
-        ldr     r2, [r1, #L2X0_CTRL]
-        tst     r2, #0x1
-        bne     resume_l2on
-        ldr     r2, [r0, #L2X0_R_AUX_CTRL]
-        str     r2, [r1, #L2X0_AUX_CTRL]
-        ldr     r2, [r0, #L2X0_R_TAG_LATENCY]
-        str     r2, [r1, #L2X0_TAG_LATENCY_CTRL]
-        ldr     r2, [r0, #L2X0_R_DATA_LATENCY]
-        str     r2, [r1, #L2X0_DATA_LATENCY_CTRL]
-        ldr     r2, [r0, #L2X0_R_PREFETCH_CTRL]
-        str     r2, [r1, #L2X0_PREFETCH_CTRL]
-        ldr     r2, [r0, #L2X0_R_PWR_CTRL]
-        str     r2, [r1, #L2X0_POWER_CTRL]
-        mov     r2, #1
-        str     r2, [r1, #L2X0_CTRL]
-resume_l2on:
-#endif
        b       cpu_resume
 ENDPROC(s3c_cpu_resume)
-#ifdef CONFIG_CACHE_L2X0
-        .globl l2x0_regs_phys
-l2x0_regs_phys:
-        .long   0
-#endif
diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c
index 884187fbfe00..13eae14c2cc2 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -17,7 +17,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
-#include <dt-bindings/clk/exynos-audss-clk.h>
+#include <dt-bindings/clock/exynos-audss-clk.h>
 enum exynos_audss_clk_type {
        TYPE_EXYNOS4210,
diff --git a/drivers/clk/versatile/clk-impd1.c b/drivers/clk/versatile/clk-impd1.c
index 6d8b8e1a080a..31b44f025f9e 100644
--- a/drivers/clk/versatile/clk-impd1.c
+++ b/drivers/clk/versatile/clk-impd1.c
@@ -13,10 +13,12 @@
 #include <linux/io.h>
 #include <linux/platform_data/clk-integrator.h>
-#include <mach/impd1.h>
 #include "clk-icst.h"
+#define IMPD1_OSC1      0x00
+#define IMPD1_OSC2      0x04
+#define IMPD1_LOCK      0x08
 struct impd1_clk {
        char *vco1name;
        struct clk *vco1clk;
diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c
index 09dd0173ea0a..c812b93a52b2 100644
--- a/drivers/clk/zynq/clkc.c
+++ b/drivers/clk/zynq/clkc.c
@@ -21,34 +21,35 @@
 #include <linux/clk/zynq.h>
 #include <linux/clk-provider.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
 #include <linux/slab.h>
 #include <linux/string.h>
 #include <linux/io.h>
-static void __iomem *zynq_slcr_base_priv;
+static void __iomem *zynq_clkc_base;
-#define SLCR_ARMPLL_CTRL                (zynq_slcr_base_priv + 0x100)
+#define SLCR_ARMPLL_CTRL                (zynq_clkc_base + 0x00)
-#define SLCR_DDRPLL_CTRL                (zynq_slcr_base_priv + 0x104)
+#define SLCR_DDRPLL_CTRL                (zynq_clkc_base + 0x04)
-#define SLCR_IOPLL_CTRL                 (zynq_slcr_base_priv + 0x108)
+#define SLCR_IOPLL_CTRL                 (zynq_clkc_base + 0x08)
-#define SLCR_PLL_STATUS                 (zynq_slcr_base_priv + 0x10c)
+#define SLCR_PLL_STATUS                 (zynq_clkc_base + 0x0c)
-#define SLCR_ARM_CLK_CTRL               (zynq_slcr_base_priv + 0x120)
+#define SLCR_ARM_CLK_CTRL               (zynq_clkc_base + 0x20)
-#define SLCR_DDR_CLK_CTRL               (zynq_slcr_base_priv + 0x124)
+#define SLCR_DDR_CLK_CTRL               (zynq_clkc_base + 0x24)
-#define SLCR_DCI_CLK_CTRL               (zynq_slcr_base_priv + 0x128)
+#define SLCR_DCI_CLK_CTRL               (zynq_clkc_base + 0x28)
-#define SLCR_APER_CLK_CTRL              (zynq_slcr_base_priv + 0x12c)
+#define SLCR_APER_CLK_CTRL              (zynq_clkc_base + 0x2c)
-#define SLCR_GEM0_CLK_CTRL              (zynq_slcr_base_priv + 0x140)
+#define SLCR_GEM0_CLK_CTRL              (zynq_clkc_base + 0x40)
-#define SLCR_GEM1_CLK_CTRL              (zynq_slcr_base_priv + 0x144)
+#define SLCR_GEM1_CLK_CTRL              (zynq_clkc_base + 0x44)
-#define SLCR_SMC_CLK_CTRL               (zynq_slcr_base_priv + 0x148)
+#define SLCR_SMC_CLK_CTRL               (zynq_clkc_base + 0x48)
-#define SLCR_LQSPI_CLK_CTRL             (zynq_slcr_base_priv + 0x14c)
+#define SLCR_LQSPI_CLK_CTRL             (zynq_clkc_base + 0x4c)
-#define SLCR_SDIO_CLK_CTRL              (zynq_slcr_base_priv + 0x150)
+#define SLCR_SDIO_CLK_CTRL              (zynq_clkc_base + 0x50)
-#define SLCR_UART_CLK_CTRL              (zynq_slcr_base_priv + 0x154)
+#define SLCR_UART_CLK_CTRL              (zynq_clkc_base + 0x54)
-#define SLCR_SPI_CLK_CTRL               (zynq_slcr_base_priv + 0x158)
+#define SLCR_SPI_CLK_CTRL               (zynq_clkc_base + 0x58)
-#define SLCR_CAN_CLK_CTRL               (zynq_slcr_base_priv + 0x15c)
+#define SLCR_CAN_CLK_CTRL               (zynq_clkc_base + 0x5c)
-#define SLCR_CAN_MIOCLK_CTRL            (zynq_slcr_base_priv + 0x160)
+#define SLCR_CAN_MIOCLK_CTRL            (zynq_clkc_base + 0x60)
-#define SLCR_DBG_CLK_CTRL               (zynq_slcr_base_priv + 0x164)
+#define SLCR_DBG_CLK_CTRL               (zynq_clkc_base + 0x64)
-#define SLCR_PCAP_CLK_CTRL              (zynq_slcr_base_priv + 0x168)
+#define SLCR_PCAP_CLK_CTRL              (zynq_clkc_base + 0x68)
-#define SLCR_FPGA0_CLK_CTRL             (zynq_slcr_base_priv + 0x170)
+#define SLCR_FPGA0_CLK_CTRL             (zynq_clkc_base + 0x70)
-#define SLCR_621_TRUE                   (zynq_slcr_base_priv + 0x1c4)
+#define SLCR_621_TRUE                   (zynq_clkc_base + 0xc4)
-#define SLCR_SWDT_CLK_SEL               (zynq_slcr_base_priv + 0x304)
+#define SLCR_SWDT_CLK_SEL               (zynq_clkc_base + 0x204)
 #define NUM_MIO_PINS    54
@@ -569,8 +570,42 @@ static void __init zynq_clk_setup(struct device_node *np)
 CLK_OF_DECLARE(zynq_clkc, "xlnx,ps7-clkc", zynq_clk_setup);
-void __init zynq_clock_init(void __iomem *slcr_base)
+void __init zynq_clock_init(void)
 {
-        zynq_slcr_base_priv = slcr_base;
+        struct device_node *np;
-        of_clk_init(NULL);
+        struct device_node *slcr;
+        struct resource res;
+        np = of_find_compatible_node(NULL, NULL, "xlnx,ps7-clkc");
+        if (!np) {
+                pr_err("%s: clkc node not found\n", __func__);
+                goto np_err;
+        }
+        if (of_address_to_resource(np, 0, &res)) {
+                pr_err("%s: failed to get resource\n", np->name);
+                goto np_err;
+        }
+        slcr = of_get_parent(np);
+        if (slcr->data) {
+                zynq_clkc_base = (__force void __iomem *)slcr->data + res.start;
+        } else {
+                pr_err("%s: Unable to get I/O memory\n", np->name);
+                of_node_put(slcr);
+                goto np_err;
+        }
+        pr_info("%s: clkc starts at %p\n", __func__, zynq_clkc_base);
+        of_node_put(slcr);
+        of_node_put(np);
+        return;
+np_err:
+        of_node_put(np);
+        BUG();
+        return;
 }
diff --git a/include/dt-bindings/clk/exynos-audss-clk.h b/include/dt-bindings/clock/exynos-audss-clk.h
index 0ae6f5a75d2a..0ae6f5a75d2a 100644
--- a/include/dt-bindings/clk/exynos-audss-clk.h
+++ b/include/dt-bindings/clock/exynos-audss-clk.h
diff --git a/include/linux/clk/zynq.h b/include/linux/clk/zynq.h
index e062d317ccce..7a5633b71533 100644
--- a/include/linux/clk/zynq.h
+++ b/include/linux/clk/zynq.h
@@ -22,7 +22,7 @@
 #include <linux/spinlock.h>
-void zynq_clock_init(void __iomem *slcr);
+void zynq_clock_init(void);
 struct clk *clk_register_zynq_pll(const char *name, const char *parent,
                void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index,
diff --git a/include/linux/serial_s3c.h b/include/linux/serial_s3c.h
index 907d9d1d56cf..e6fc9567690b 100644
--- a/include/linux/serial_s3c.h
+++ b/include/linux/serial_s3c.h
@@ -233,6 +233,8 @@
 #ifndef __ASSEMBLY__
+#include <linux/serial_core.h>
 /* configuration structure for per-machine configurations for the
 * serial port
 *
author	Linus Torvalds <torvalds@linux-foundation.org>	2014-04-05 18:46:37 -0400
committer	Linus Torvalds <torvalds@linux-foundation.org>	2014-04-05 18:46:37 -0400
commit	2bf73dd61a84cdf27e49f48e08739af6ba70ace1 (patch)
tree	225876ce1530ba6c3a96621a531f47e963fee691
parent	d2b150d0647e055d7a71b1c33140280550b27dd6 (diff)
parent	9dfbff16b422a4bac7ad309847c7bc5d65653392 (diff)