diff options
author | Arnd Bergmann <arnd@arndb.de> | 2012-02-27 12:22:36 -0500 |
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committer | Arnd Bergmann <arnd@arndb.de> | 2012-02-29 07:03:08 -0500 |
commit | 7eca30aef7961e68ad74c0ef920546c2be7f6579 (patch) | |
tree | d7161459a86134bee58b8a0980a15b66839467aa /arch/arm/mach-imx/mm-imx5.c | |
parent | d65b4e98d7ea3038b767b70fe8be959b2913f16d (diff) | |
parent | d5e5a7f987458f42f24a557a0f4e35f94c43fc09 (diff) |
Merge branch 'at91-3.4-base2+cleanup' of git://github.com/at91linux/linux-at91 into at91/staging/base2+cleanup
* 'at91-3.4-base2+cleanup' of git://github.com/at91linux/linux-at91: (20 commits)
ARM: at91: properly sort dtb files in Makefile.boot
ARM: at91: add at91sam9g25ek.dts in Makefile.boot
ARM: at91/board-dt: drop default console
Atmel: move console default platform_device to serial driver
ARM: at91: merge SRAM Memory banks thanks to mirroring
ARM: at91: finally drop at91_sys_read/write
ARM: at91/rtc-at91sam9: pass the GPBR to use via resources
ARM: at91:rtc/rtc-at91sam9: ioremap register bank
ARM: at91/rtc-at91sam9: each SoC can select the RTT device to use
ARM: at91/PMC: make register base soc independent
ARM: at91/PMC: move assignment out of printf
ARM: at91/pm_slowclock: add runtime detection of memory contoller
ARM: at91: make sdram/ddr register base soc independent
ARM: at91: move at91rm9200 sdramc defines to at91rm9200_sdramc.h
ARM: at91/pm_slowclock: function slow_clock() accepts parameters
ARM: at91/pm_slowclock: rename register to named define
ARM: at91/ST: remove not needed casts
ARM: at91: make ST (System Timer) soc independent
ARM: at91: make matrix register base soc independent
ARM: at91/at91x40: remove use of at91_sys_read/write
Based on top of the at91/9x5, rmk/for-armsoc, at91/device-board,
at91/pm_cleanup and at91/base.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-imx/mm-imx5.c')
-rw-r--r-- | arch/arm/mach-imx/mm-imx5.c | 28 |
1 files changed, 11 insertions, 17 deletions
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c index bc17dfea3817..49549a72dc7d 100644 --- a/arch/arm/mach-imx/mm-imx5.c +++ b/arch/arm/mach-imx/mm-imx5.c | |||
@@ -26,23 +26,17 @@ static struct clk *gpc_dvfs_clk; | |||
26 | 26 | ||
27 | static void imx5_idle(void) | 27 | static void imx5_idle(void) |
28 | { | 28 | { |
29 | if (!need_resched()) { | 29 | /* gpc clock is needed for SRPG */ |
30 | /* gpc clock is needed for SRPG */ | 30 | if (gpc_dvfs_clk == NULL) { |
31 | if (gpc_dvfs_clk == NULL) { | 31 | gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs"); |
32 | gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs"); | 32 | if (IS_ERR(gpc_dvfs_clk)) |
33 | if (IS_ERR(gpc_dvfs_clk)) | 33 | return; |
34 | goto err0; | ||
35 | } | ||
36 | clk_enable(gpc_dvfs_clk); | ||
37 | mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); | ||
38 | if (tzic_enable_wake()) | ||
39 | goto err1; | ||
40 | cpu_do_idle(); | ||
41 | err1: | ||
42 | clk_disable(gpc_dvfs_clk); | ||
43 | } | 34 | } |
44 | err0: | 35 | clk_enable(gpc_dvfs_clk); |
45 | local_irq_enable(); | 36 | mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); |
37 | if (tzic_enable_wake() != 0) | ||
38 | cpu_do_idle(); | ||
39 | clk_disable(gpc_dvfs_clk); | ||
46 | } | 40 | } |
47 | 41 | ||
48 | /* | 42 | /* |
@@ -108,7 +102,7 @@ void __init imx51_init_early(void) | |||
108 | mxc_set_cpu_type(MXC_CPU_MX51); | 102 | mxc_set_cpu_type(MXC_CPU_MX51); |
109 | mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR)); | 103 | mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR)); |
110 | mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR)); | 104 | mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR)); |
111 | pm_idle = imx5_idle; | 105 | arm_pm_idle = imx5_idle; |
112 | } | 106 | } |
113 | 107 | ||
114 | void __init imx53_init_early(void) | 108 | void __init imx53_init_early(void) |