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authorLinus Torvalds <torvalds@linux-foundation.org>2011-01-15 15:33:40 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2011-01-15 15:33:40 -0500
commit16c1020362083b320868c0deef492249089c3cd3 (patch)
treeff200df3502e6010745713275d69fd0a07e399cf /arch/arm/mach-gemini
parent65e5d002b5ad220db2bf9557f53de5a98f7dab86 (diff)
parentbbba75606963c82febf7bd2761ea848ac5d1a1bb (diff)
Merge branch 'devel-stable' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel-stable' of master.kernel.org:/home/rmk/linux-2.6-arm: (161 commits) ARM: pxa: fix building issue of missing physmap.h ARM: mmp: PXA910 drive strength FAST using wrong value ARM: mmp: MMP2 drive strength FAST using wrong value ARM: pxa: fix recursive calls in pxa_low_gpio_chip AT91: Support for gsia18s board AT91: Acme Systems FOX Board G20 board files AT91: board-sam9m10g45ek.c: Remove duplicate inclusion of mach/hardware.h ARM: pxa: fix suspend/resume array index miscalculation ARM: pxa: use cpu_has_ipr() consistently in irq.c ARM: pxa: remove unused variable in clock-pxa3xx.c ARM: pxa: fix warning in zeus.c ARM: sa1111: fix typo in sa1111_retrigger_lowirq() ARM mxs: clkdev related compile fixes ARM i.MX mx31_3ds: Fix MC13783 regulator names ARM: plat-stmp3xxx: irq_data conversion. ARM: plat-spear: irq_data conversion. ARM: plat-orion: irq_data conversion. ARM: plat-omap: irq_data conversion. ARM: plat-nomadik: irq_data conversion. ARM: plat-mxc: irq_data conversion. ... Fix up trivial conflict in arch/arm/plat-omap/gpio.c (Lennert Buytenhek's irq_data conversion clashing with some omap irq updates)
Diffstat (limited to 'arch/arm/mach-gemini')
-rw-r--r--arch/arm/mach-gemini/gpio.c26
-rw-r--r--arch/arm/mach-gemini/irq.c20
2 files changed, 23 insertions, 23 deletions
diff --git a/arch/arm/mach-gemini/gpio.c b/arch/arm/mach-gemini/gpio.c
index fe3bd5ac8b10..fa3d333f21e1 100644
--- a/arch/arm/mach-gemini/gpio.c
+++ b/arch/arm/mach-gemini/gpio.c
@@ -54,33 +54,33 @@ static void _set_gpio_irqenable(unsigned int base, unsigned int index,
54 __raw_writel(reg, base + GPIO_INT_EN); 54 __raw_writel(reg, base + GPIO_INT_EN);
55} 55}
56 56
57static void gpio_ack_irq(unsigned int irq) 57static void gpio_ack_irq(struct irq_data *d)
58{ 58{
59 unsigned int gpio = irq_to_gpio(irq); 59 unsigned int gpio = irq_to_gpio(d->irq);
60 unsigned int base = GPIO_BASE(gpio / 32); 60 unsigned int base = GPIO_BASE(gpio / 32);
61 61
62 __raw_writel(1 << (gpio % 32), base + GPIO_INT_CLR); 62 __raw_writel(1 << (gpio % 32), base + GPIO_INT_CLR);
63} 63}
64 64
65static void gpio_mask_irq(unsigned int irq) 65static void gpio_mask_irq(struct irq_data *d)
66{ 66{
67 unsigned int gpio = irq_to_gpio(irq); 67 unsigned int gpio = irq_to_gpio(d->irq);
68 unsigned int base = GPIO_BASE(gpio / 32); 68 unsigned int base = GPIO_BASE(gpio / 32);
69 69
70 _set_gpio_irqenable(base, gpio % 32, 0); 70 _set_gpio_irqenable(base, gpio % 32, 0);
71} 71}
72 72
73static void gpio_unmask_irq(unsigned int irq) 73static void gpio_unmask_irq(struct irq_data *d)
74{ 74{
75 unsigned int gpio = irq_to_gpio(irq); 75 unsigned int gpio = irq_to_gpio(d->irq);
76 unsigned int base = GPIO_BASE(gpio / 32); 76 unsigned int base = GPIO_BASE(gpio / 32);
77 77
78 _set_gpio_irqenable(base, gpio % 32, 1); 78 _set_gpio_irqenable(base, gpio % 32, 1);
79} 79}
80 80
81static int gpio_set_irq_type(unsigned int irq, unsigned int type) 81static int gpio_set_irq_type(struct irq_data *d, unsigned int type)
82{ 82{
83 unsigned int gpio = irq_to_gpio(irq); 83 unsigned int gpio = irq_to_gpio(d->irq);
84 unsigned int gpio_mask = 1 << (gpio % 32); 84 unsigned int gpio_mask = 1 << (gpio % 32);
85 unsigned int base = GPIO_BASE(gpio / 32); 85 unsigned int base = GPIO_BASE(gpio / 32);
86 unsigned int reg_both, reg_level, reg_type; 86 unsigned int reg_both, reg_level, reg_type;
@@ -120,7 +120,7 @@ static int gpio_set_irq_type(unsigned int irq, unsigned int type)
120 __raw_writel(reg_level, base + GPIO_INT_LEVEL); 120 __raw_writel(reg_level, base + GPIO_INT_LEVEL);
121 __raw_writel(reg_both, base + GPIO_INT_BOTH_EDGE); 121 __raw_writel(reg_both, base + GPIO_INT_BOTH_EDGE);
122 122
123 gpio_ack_irq(irq); 123 gpio_ack_irq(d->irq);
124 124
125 return 0; 125 return 0;
126} 126}
@@ -146,10 +146,10 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
146 146
147static struct irq_chip gpio_irq_chip = { 147static struct irq_chip gpio_irq_chip = {
148 .name = "GPIO", 148 .name = "GPIO",
149 .ack = gpio_ack_irq, 149 .irq_ack = gpio_ack_irq,
150 .mask = gpio_mask_irq, 150 .irq_mask = gpio_mask_irq,
151 .unmask = gpio_unmask_irq, 151 .irq_unmask = gpio_unmask_irq,
152 .set_type = gpio_set_irq_type, 152 .irq_set_type = gpio_set_irq_type,
153}; 153};
154 154
155static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset, 155static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
diff --git a/arch/arm/mach-gemini/irq.c b/arch/arm/mach-gemini/irq.c
index 9e613ca8120d..96bc227dd849 100644
--- a/arch/arm/mach-gemini/irq.c
+++ b/arch/arm/mach-gemini/irq.c
@@ -32,34 +32,34 @@
32#define FIQ_LEVEL(base_addr) (base_addr + 0x30) 32#define FIQ_LEVEL(base_addr) (base_addr + 0x30)
33#define FIQ_STATUS(base_addr) (base_addr + 0x34) 33#define FIQ_STATUS(base_addr) (base_addr + 0x34)
34 34
35static void gemini_ack_irq(unsigned int irq) 35static void gemini_ack_irq(struct irq_data *d)
36{ 36{
37 __raw_writel(1 << irq, IRQ_CLEAR(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); 37 __raw_writel(1 << d->irq, IRQ_CLEAR(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
38} 38}
39 39
40static void gemini_mask_irq(unsigned int irq) 40static void gemini_mask_irq(struct irq_data *d)
41{ 41{
42 unsigned int mask; 42 unsigned int mask;
43 43
44 mask = __raw_readl(IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); 44 mask = __raw_readl(IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
45 mask &= ~(1 << irq); 45 mask &= ~(1 << d->irq);
46 __raw_writel(mask, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); 46 __raw_writel(mask, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
47} 47}
48 48
49static void gemini_unmask_irq(unsigned int irq) 49static void gemini_unmask_irq(struct irq_data *d)
50{ 50{
51 unsigned int mask; 51 unsigned int mask;
52 52
53 mask = __raw_readl(IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); 53 mask = __raw_readl(IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
54 mask |= (1 << irq); 54 mask |= (1 << d->irq);
55 __raw_writel(mask, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); 55 __raw_writel(mask, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
56} 56}
57 57
58static struct irq_chip gemini_irq_chip = { 58static struct irq_chip gemini_irq_chip = {
59 .name = "INTC", 59 .name = "INTC",
60 .ack = gemini_ack_irq, 60 .irq_ack = gemini_ack_irq,
61 .mask = gemini_mask_irq, 61 .irq_mask = gemini_mask_irq,
62 .unmask = gemini_unmask_irq, 62 .irq_unmask = gemini_unmask_irq,
63}; 63};
64 64
65static struct resource irq_resource = { 65static struct resource irq_resource = {