Merge branch 'late/soc' into devel-late

* late/soc:
  ARM: vexpress: Remove twice included header files
  ARM: vexpress: Device Tree updates
  ARM: EXYNOS: Support suspend and resume for EXYNOS5250
  ARM: EXYNOS: Add Clock register list for save and restore
  ARM: EXYNOS: Add PMU table for EXYNOS5250
  ARM: EXYNOS: Rename of function for pm.c
  ARM: EXYNOS: Remove GIC save & restore function
  ARM: dts: Add node for interrupt combiner controller on EXYNOS5250
  ARM: S3C24XX: add support for second irq set of S3C2416

10 files changed, 470 insertions, 175 deletions

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 43ebe9094411..573be57d3d28 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -62,6 +62,8 @@ config SOC_EXYNOS5250
         default y
         depends on ARCH_EXYNOS5
         select SAMSUNG_DMADEV
+        select S5P_PM if PM
+        select S5P_SLEEP if PM
         help
           Enable EXYNOS5250 SoC support
 
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 440a637c76f1..9b58024f7d43 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -22,7 +22,7 @@ obj-$(CONFIG_PM)		+= pm.o
 obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
 obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
 
-obj-$(CONFIG_ARCH_EXYNOS4)      += pmu.o
+obj-$(CONFIG_ARCH_EXYNOS)       += pmu.o
 
 obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
 
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 5aa460b01fdf..fefa336be2b4 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -30,7 +30,56 @@
 
 #ifdef CONFIG_PM_SLEEP
 static struct sleep_save exynos5_clock_save[] = {
-        /* will be implemented */
+        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_TOP),
+        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_GSCL),
+        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_DISP1_0),
+        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_FSYS),
+        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_MAUDIO),
+        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC0),
+        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC1),
+        SAVE_ITEM(EXYNOS5_CLKGATE_IP_GSCL),
+        SAVE_ITEM(EXYNOS5_CLKGATE_IP_DISP1),
+        SAVE_ITEM(EXYNOS5_CLKGATE_IP_MFC),
+        SAVE_ITEM(EXYNOS5_CLKGATE_IP_G3D),
+        SAVE_ITEM(EXYNOS5_CLKGATE_IP_GEN),
+        SAVE_ITEM(EXYNOS5_CLKGATE_IP_FSYS),
+        SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIC),
+        SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIS),
+        SAVE_ITEM(EXYNOS5_CLKGATE_BLOCK),
+        SAVE_ITEM(EXYNOS5_CLKDIV_TOP0),
+        SAVE_ITEM(EXYNOS5_CLKDIV_TOP1),
+        SAVE_ITEM(EXYNOS5_CLKDIV_GSCL),
+        SAVE_ITEM(EXYNOS5_CLKDIV_DISP1_0),
+        SAVE_ITEM(EXYNOS5_CLKDIV_GEN),
+        SAVE_ITEM(EXYNOS5_CLKDIV_MAUDIO),
+        SAVE_ITEM(EXYNOS5_CLKDIV_FSYS0),
+        SAVE_ITEM(EXYNOS5_CLKDIV_FSYS1),
+        SAVE_ITEM(EXYNOS5_CLKDIV_FSYS2),
+        SAVE_ITEM(EXYNOS5_CLKDIV_FSYS3),
+        SAVE_ITEM(EXYNOS5_CLKDIV_PERIC0),
+        SAVE_ITEM(EXYNOS5_CLKDIV_PERIC1),
+        SAVE_ITEM(EXYNOS5_CLKDIV_PERIC2),
+        SAVE_ITEM(EXYNOS5_CLKDIV_PERIC3),
+        SAVE_ITEM(EXYNOS5_CLKDIV_PERIC4),
+        SAVE_ITEM(EXYNOS5_CLKDIV_PERIC5),
+        SAVE_ITEM(EXYNOS5_SCLK_DIV_ISP),
+        SAVE_ITEM(EXYNOS5_CLKSRC_TOP0),
+        SAVE_ITEM(EXYNOS5_CLKSRC_TOP1),
+        SAVE_ITEM(EXYNOS5_CLKSRC_TOP2),
+        SAVE_ITEM(EXYNOS5_CLKSRC_TOP3),
+        SAVE_ITEM(EXYNOS5_CLKSRC_GSCL),
+        SAVE_ITEM(EXYNOS5_CLKSRC_DISP1_0),
+        SAVE_ITEM(EXYNOS5_CLKSRC_MAUDIO),
+        SAVE_ITEM(EXYNOS5_CLKSRC_FSYS),
+        SAVE_ITEM(EXYNOS5_CLKSRC_PERIC0),
+        SAVE_ITEM(EXYNOS5_CLKSRC_PERIC1),
+        SAVE_ITEM(EXYNOS5_SCLK_SRC_ISP),
+        SAVE_ITEM(EXYNOS5_EPLL_CON0),
+        SAVE_ITEM(EXYNOS5_EPLL_CON1),
+        SAVE_ITEM(EXYNOS5_EPLL_CON2),
+        SAVE_ITEM(EXYNOS5_VPLL_CON0),
+        SAVE_ITEM(EXYNOS5_VPLL_CON1),
+        SAVE_ITEM(EXYNOS5_VPLL_CON2),
 };
 #endif
 
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 26dac2893b8e..cff0595d0d35 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -100,7 +100,7 @@ static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
         exynos4_set_wakeupmask();
 
         /* Set value of power down register for aftr mode */
-        exynos4_sys_powerdown_conf(SYS_AFTR);
+        exynos_sys_powerdown_conf(SYS_AFTR);
 
         __raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR);
         __raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);
diff --git a/arch/arm/mach-exynos/include/mach/pm-core.h b/arch/arm/mach-exynos/include/mach/pm-core.h
index 9d8da51e35ca..a67ecfaf1216 100644
--- a/arch/arm/mach-exynos/include/mach/pm-core.h
+++ b/arch/arm/mach-exynos/include/mach/pm-core.h
@@ -33,7 +33,7 @@ static inline void s3c_pm_arch_prepare_irqs(void)
         __raw_writel(tmp, S5P_WAKEUP_MASK);
 
         __raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK);
-        __raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK);
+        __raw_writel(s3c_irqwake_eintmask & 0xFFFFFFFE, S5P_EINT_WAKEUP_MASK);
 }
 
 static inline void s3c_pm_arch_stop_clocks(void)
diff --git a/arch/arm/mach-exynos/include/mach/pmu.h b/arch/arm/mach-exynos/include/mach/pmu.h
index e76b7faba66b..7c27c2d4bf44 100644
--- a/arch/arm/mach-exynos/include/mach/pmu.h
+++ b/arch/arm/mach-exynos/include/mach/pmu.h
@@ -23,12 +23,12 @@ enum sys_powerdown {
 };
 
 extern unsigned long l2x0_regs_phys;
-struct exynos4_pmu_conf {
+struct exynos_pmu_conf {
         void __iomem *reg;
         unsigned int val[NUM_SYS_POWERDOWN];
 };
 
-extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode);
+extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
 extern void s3c_cpu_resume(void);
 
 #endif /* __ASM_ARCH_PMU_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index b78b5f3ad9c0..8c9b38c9c504 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -274,36 +274,51 @@
 
 #define EXYNOS5_CLKDIV_ACP                      EXYNOS_CLKREG(0x08500)
 
-#define EXYNOS5_CLKSRC_TOP2                     EXYNOS_CLKREG(0x10218)
 #define EXYNOS5_EPLL_CON0                       EXYNOS_CLKREG(0x10130)
 #define EXYNOS5_EPLL_CON1                       EXYNOS_CLKREG(0x10134)
+#define EXYNOS5_EPLL_CON2                       EXYNOS_CLKREG(0x10138)
 #define EXYNOS5_VPLL_CON0                       EXYNOS_CLKREG(0x10140)
 #define EXYNOS5_VPLL_CON1                       EXYNOS_CLKREG(0x10144)
+#define EXYNOS5_VPLL_CON2                       EXYNOS_CLKREG(0x10148)
 #define EXYNOS5_CPLL_CON0                       EXYNOS_CLKREG(0x10120)
 
 #define EXYNOS5_CLKSRC_TOP0                     EXYNOS_CLKREG(0x10210)
+#define EXYNOS5_CLKSRC_TOP1                     EXYNOS_CLKREG(0x10214)
+#define EXYNOS5_CLKSRC_TOP2                     EXYNOS_CLKREG(0x10218)
 #define EXYNOS5_CLKSRC_TOP3                     EXYNOS_CLKREG(0x1021C)
 #define EXYNOS5_CLKSRC_GSCL                     EXYNOS_CLKREG(0x10220)
 #define EXYNOS5_CLKSRC_DISP1_0                  EXYNOS_CLKREG(0x1022C)
+#define EXYNOS5_CLKSRC_MAUDIO                   EXYNOS_CLKREG(0x10240)
 #define EXYNOS5_CLKSRC_FSYS                     EXYNOS_CLKREG(0x10244)
 #define EXYNOS5_CLKSRC_PERIC0                   EXYNOS_CLKREG(0x10250)
+#define EXYNOS5_CLKSRC_PERIC1                   EXYNOS_CLKREG(0x10254)
+#define EXYNOS5_SCLK_SRC_ISP                    EXYNOS_CLKREG(0x10270)
 
 #define EXYNOS5_CLKSRC_MASK_TOP                 EXYNOS_CLKREG(0x10310)
 #define EXYNOS5_CLKSRC_MASK_GSCL                EXYNOS_CLKREG(0x10320)
 #define EXYNOS5_CLKSRC_MASK_DISP1_0             EXYNOS_CLKREG(0x1032C)
+#define EXYNOS5_CLKSRC_MASK_MAUDIO              EXYNOS_CLKREG(0x10334)
 #define EXYNOS5_CLKSRC_MASK_FSYS                EXYNOS_CLKREG(0x10340)
 #define EXYNOS5_CLKSRC_MASK_PERIC0              EXYNOS_CLKREG(0x10350)
+#define EXYNOS5_CLKSRC_MASK_PERIC1              EXYNOS_CLKREG(0x10354)
 
 #define EXYNOS5_CLKDIV_TOP0                     EXYNOS_CLKREG(0x10510)
 #define EXYNOS5_CLKDIV_TOP1                     EXYNOS_CLKREG(0x10514)
 #define EXYNOS5_CLKDIV_GSCL                     EXYNOS_CLKREG(0x10520)
 #define EXYNOS5_CLKDIV_DISP1_0                  EXYNOS_CLKREG(0x1052C)
 #define EXYNOS5_CLKDIV_GEN                      EXYNOS_CLKREG(0x1053C)
+#define EXYNOS5_CLKDIV_MAUDIO                   EXYNOS_CLKREG(0x10544)
 #define EXYNOS5_CLKDIV_FSYS0                    EXYNOS_CLKREG(0x10548)
 #define EXYNOS5_CLKDIV_FSYS1                    EXYNOS_CLKREG(0x1054C)
 #define EXYNOS5_CLKDIV_FSYS2                    EXYNOS_CLKREG(0x10550)
 #define EXYNOS5_CLKDIV_FSYS3                    EXYNOS_CLKREG(0x10554)
 #define EXYNOS5_CLKDIV_PERIC0                   EXYNOS_CLKREG(0x10558)
+#define EXYNOS5_CLKDIV_PERIC1                   EXYNOS_CLKREG(0x1055C)
+#define EXYNOS5_CLKDIV_PERIC2                   EXYNOS_CLKREG(0x10560)
+#define EXYNOS5_CLKDIV_PERIC3                   EXYNOS_CLKREG(0x10564)
+#define EXYNOS5_CLKDIV_PERIC4                   EXYNOS_CLKREG(0x10568)
+#define EXYNOS5_CLKDIV_PERIC5                   EXYNOS_CLKREG(0x1056C)
+#define EXYNOS5_SCLK_DIV_ISP                    EXYNOS_CLKREG(0x10580)
 
 #define EXYNOS5_CLKGATE_IP_ACP                  EXYNOS_CLKREG(0x08800)
 #define EXYNOS5_CLKGATE_IP_ISP0                 EXYNOS_CLKREG(0x0C800)
@@ -311,6 +326,7 @@
 #define EXYNOS5_CLKGATE_IP_GSCL                 EXYNOS_CLKREG(0x10920)
 #define EXYNOS5_CLKGATE_IP_DISP1                EXYNOS_CLKREG(0x10928)
 #define EXYNOS5_CLKGATE_IP_MFC                  EXYNOS_CLKREG(0x1092C)
+#define EXYNOS5_CLKGATE_IP_G3D                  EXYNOS_CLKREG(0x10930)
 #define EXYNOS5_CLKGATE_IP_GEN                  EXYNOS_CLKREG(0x10934)
 #define EXYNOS5_CLKGATE_IP_FSYS                 EXYNOS_CLKREG(0x10944)
 #define EXYNOS5_CLKGATE_IP_GPS                  EXYNOS_CLKREG(0x1094C)
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index 4dbb8629b200..43a99e6f56ab 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -1,9 +1,8 @@
-/* linux/arch/arm/mach-exynos4/include/mach/regs-pmu.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+/*
+ * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
  *
- * EXYNOS4 - Power management unit definition
+ * EXYNOS - Power management unit definition
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -229,4 +228,138 @@
 #define S5P_DIS_IRQ_CORE3                       S5P_PMUREG(0x1034)
 #define S5P_DIS_IRQ_CENTRAL3                    S5P_PMUREG(0x1038)
 
+/* For EXYNOS5 */
+
+#define EXYNOS5_USB_CFG                                         S5P_PMUREG(0x0230)
+
+#define EXYNOS5_ARM_CORE0_SYS_PWR_REG                           S5P_PMUREG(0x1000)
+#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG             S5P_PMUREG(0x1004)
+#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG           S5P_PMUREG(0x1008)
+#define EXYNOS5_ARM_CORE1_SYS_PWR_REG                           S5P_PMUREG(0x1010)
+#define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG             S5P_PMUREG(0x1014)
+#define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG           S5P_PMUREG(0x1018)
+#define EXYNOS5_FSYS_ARM_SYS_PWR_REG                            S5P_PMUREG(0x1040)
+#define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG            S5P_PMUREG(0x1048)
+#define EXYNOS5_ISP_ARM_SYS_PWR_REG                             S5P_PMUREG(0x1050)
+#define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG               S5P_PMUREG(0x1054)
+#define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG             S5P_PMUREG(0x1058)
+#define EXYNOS5_ARM_COMMON_SYS_PWR_REG                          S5P_PMUREG(0x1080)
+#define EXYNOS5_ARM_L2_SYS_PWR_REG                              S5P_PMUREG(0x10C0)
+#define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG                        S5P_PMUREG(0x1100)
+#define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG                        S5P_PMUREG(0x1104)
+#define EXYNOS5_CMU_RESET_SYS_PWR_REG                           S5P_PMUREG(0x110C)
+#define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG                 S5P_PMUREG(0x1120)
+#define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG                 S5P_PMUREG(0x1124)
+#define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG                    S5P_PMUREG(0x112C)
+#define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG                      S5P_PMUREG(0x1130)
+#define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG                       S5P_PMUREG(0x1134)
+#define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG                      S5P_PMUREG(0x1138)
+#define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG                         S5P_PMUREG(0x1140)
+#define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG                         S5P_PMUREG(0x1144)
+#define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG                         S5P_PMUREG(0x1148)
+#define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG                         S5P_PMUREG(0x114C)
+#define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG                         S5P_PMUREG(0x1150)
+#define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG                         S5P_PMUREG(0x1154)
+#define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG                     S5P_PMUREG(0x1164)
+#define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG                     S5P_PMUREG(0x1170)
+#define EXYNOS5_TOP_BUS_SYS_PWR_REG                             S5P_PMUREG(0x1180)
+#define EXYNOS5_TOP_RETENTION_SYS_PWR_REG                       S5P_PMUREG(0x1184)
+#define EXYNOS5_TOP_PWR_SYS_PWR_REG                             S5P_PMUREG(0x1188)
+#define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG                      S5P_PMUREG(0x1190)
+#define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG                S5P_PMUREG(0x1194)
+#define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG                      S5P_PMUREG(0x1198)
+#define EXYNOS5_LOGIC_RESET_SYS_PWR_REG                         S5P_PMUREG(0x11A0)
+#define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG                         S5P_PMUREG(0x11A4)
+#define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG                  S5P_PMUREG(0x11B0)
+#define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG                  S5P_PMUREG(0x11B4)
+#define EXYNOS5_USBOTG_MEM_SYS_PWR_REG                          S5P_PMUREG(0x11C0)
+#define EXYNOS5_G2D_MEM_SYS_PWR_REG                             S5P_PMUREG(0x11C8)
+#define EXYNOS5_USBDRD_MEM_SYS_PWR_REG                          S5P_PMUREG(0x11CC)
+#define EXYNOS5_SDMMC_MEM_SYS_PWR_REG                           S5P_PMUREG(0x11D0)
+#define EXYNOS5_CSSYS_MEM_SYS_PWR_REG                           S5P_PMUREG(0x11D4)
+#define EXYNOS5_SECSS_MEM_SYS_PWR_REG                           S5P_PMUREG(0x11D8)
+#define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG                         S5P_PMUREG(0x11DC)
+#define EXYNOS5_INTRAM_MEM_SYS_PWR_REG                          S5P_PMUREG(0x11E0)
+#define EXYNOS5_INTROM_MEM_SYS_PWR_REG                          S5P_PMUREG(0x11E4)
+#define EXYNOS5_JPEG_MEM_SYS_PWR_REG                            S5P_PMUREG(0x11E8)
+#define EXYNOS5_HSI_MEM_SYS_PWR_REG                             S5P_PMUREG(0x11EC)
+#define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG                          S5P_PMUREG(0x11F4)
+#define EXYNOS5_SATA_MEM_SYS_PWR_REG                            S5P_PMUREG(0x11FC)
+#define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG                  S5P_PMUREG(0x1200)
+#define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG                   S5P_PMUREG(0x1204)
+#define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG                S5P_PMUREG(0x1208)
+#define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG                  S5P_PMUREG(0x1220)
+#define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG                  S5P_PMUREG(0x1224)
+#define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG                  S5P_PMUREG(0x1228)
+#define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG                  S5P_PMUREG(0x122C)
+#define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG                  S5P_PMUREG(0x1230)
+#define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG                  S5P_PMUREG(0x1234)
+#define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG                   S5P_PMUREG(0x1238)
+#define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG           S5P_PMUREG(0x123C)
+#define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG                       S5P_PMUREG(0x1240)
+#define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG                S5P_PMUREG(0x1250)
+#define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG                         S5P_PMUREG(0x1260)
+#define EXYNOS5_XUSBXTI_SYS_PWR_REG                             S5P_PMUREG(0x1280)
+#define EXYNOS5_XXTI_SYS_PWR_REG                                S5P_PMUREG(0x1284)
+#define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG                       S5P_PMUREG(0x12C0)
+#define EXYNOS5_GPIO_MODE_SYS_PWR_REG                           S5P_PMUREG(0x1300)
+#define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG                    S5P_PMUREG(0x1320)
+#define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG                       S5P_PMUREG(0x1340)
+#define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG                       S5P_PMUREG(0x1344)
+#define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG                   S5P_PMUREG(0x1348)
+#define EXYNOS5_GSCL_SYS_PWR_REG                                S5P_PMUREG(0x1400)
+#define EXYNOS5_ISP_SYS_PWR_REG                                 S5P_PMUREG(0x1404)
+#define EXYNOS5_MFC_SYS_PWR_REG                                 S5P_PMUREG(0x1408)
+#define EXYNOS5_G3D_SYS_PWR_REG                                 S5P_PMUREG(0x140C)
+#define EXYNOS5_DISP1_SYS_PWR_REG                               S5P_PMUREG(0x1414)
+#define EXYNOS5_MAU_SYS_PWR_REG                                 S5P_PMUREG(0x1418)
+#define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG                    S5P_PMUREG(0x1480)
+#define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG                     S5P_PMUREG(0x1484)
+#define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG                     S5P_PMUREG(0x1488)
+#define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG                     S5P_PMUREG(0x148C)
+#define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG                   S5P_PMUREG(0x1494)
+#define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG                     S5P_PMUREG(0x1498)
+#define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG                     S5P_PMUREG(0x14C0)
+#define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG                      S5P_PMUREG(0x14C4)
+#define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG                      S5P_PMUREG(0x14C8)
+#define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG                      S5P_PMUREG(0x14CC)
+#define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG                    S5P_PMUREG(0x14D4)
+#define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG                      S5P_PMUREG(0x14D8)
+#define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG                      S5P_PMUREG(0x1580)
+#define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG                       S5P_PMUREG(0x1584)
+#define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG                       S5P_PMUREG(0x1588)
+#define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG                       S5P_PMUREG(0x158C)
+#define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG                     S5P_PMUREG(0x1594)
+#define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG                       S5P_PMUREG(0x1598)
+
+#define EXYNOS5_ARM_CORE0_OPTION                                S5P_PMUREG(0x2008)
+#define EXYNOS5_ARM_CORE1_OPTION                                S5P_PMUREG(0x2088)
+#define EXYNOS5_FSYS_ARM_OPTION                                 S5P_PMUREG(0x2208)
+#define EXYNOS5_ISP_ARM_OPTION                                  S5P_PMUREG(0x2288)
+#define EXYNOS5_ARM_COMMON_OPTION                               S5P_PMUREG(0x2408)
+#define EXYNOS5_TOP_PWR_OPTION                                  S5P_PMUREG(0x2C48)
+#define EXYNOS5_TOP_PWR_SYSMEM_OPTION                           S5P_PMUREG(0x2CC8)
+#define EXYNOS5_JPEG_MEM_OPTION                                 S5P_PMUREG(0x2F48)
+#define EXYNOS5_GSCL_STATUS                                     S5P_PMUREG(0x4004)
+#define EXYNOS5_ISP_STATUS                                      S5P_PMUREG(0x4024)
+#define EXYNOS5_GSCL_OPTION                                     S5P_PMUREG(0x4008)
+#define EXYNOS5_ISP_OPTION                                      S5P_PMUREG(0x4028)
+#define EXYNOS5_MFC_OPTION                                      S5P_PMUREG(0x4048)
+#define EXYNOS5_G3D_CONFIGURATION                               S5P_PMUREG(0x4060)
+#define EXYNOS5_G3D_STATUS                                      S5P_PMUREG(0x4064)
+#define EXYNOS5_G3D_OPTION                                      S5P_PMUREG(0x4068)
+#define EXYNOS5_DISP1_OPTION                                    S5P_PMUREG(0x40A8)
+#define EXYNOS5_MAU_OPTION                                      S5P_PMUREG(0x40C8)
+
+#define EXYNOS5_USE_SC_FEEDBACK                                 (1 << 1)
+#define EXYNOS5_USE_SC_COUNTER                                  (1 << 0)
+
+#define EXYNOS5_MANUAL_L2RSTDISABLE_CONTROL                     (1 << 2)
+#define EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN                  (1 << 7)
+
+#define EXYNOS5_OPTION_USE_STANDBYWFE                           (1 << 24)
+#define EXYNOS5_OPTION_USE_STANDBYWFI                           (1 << 16)
+
+#define EXYNOS5_OPTION_USE_RETENTION                            (1 << 4)
+
 #endif /* __ASM_ARCH_REGS_PMU_H */
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 563dea9a6dbb..c06c992943a1 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -1,9 +1,8 @@
-/* linux/arch/arm/mach-exynos4/pm.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+/*
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
  *
- * EXYNOS4210 - Power Management support
+ * EXYNOS - Power Management support
  *
  * Based on arch/arm/mach-s3c2410/pm.c
  * Copyright (c) 2006 Simtec Electronics
@@ -63,90 +62,7 @@ static struct sleep_save exynos4_vpll_save[] = {
         SAVE_ITEM(EXYNOS4_VPLL_CON1),
 };
 
-static struct sleep_save exynos4_core_save[] = {
-        /* GIC side */
-        SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),
-        SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),
-        SAVE_ITEM(S5P_VA_GIC_CPU + 0x008),
-        SAVE_ITEM(S5P_VA_GIC_CPU + 0x00C),
-        SAVE_ITEM(S5P_VA_GIC_CPU + 0x014),
-        SAVE_ITEM(S5P_VA_GIC_CPU + 0x018),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x000),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x004),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x100),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x104),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x108),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x300),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x304),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x308),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x400),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x404),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x408),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x40C),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x410),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x414),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x418),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x41C),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x420),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x424),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x428),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x42C),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x430),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x434),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x438),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x43C),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x440),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x444),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x448),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x44C),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x450),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x454),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x458),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x45C),
-
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x800),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x804),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x808),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x80C),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x810),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x814),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x818),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x81C),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x820),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x824),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x828),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x82C),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x830),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x834),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x838),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x83C),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x840),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x844),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x848),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x84C),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x850),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x854),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x858),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0x85C),
-
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0xC00),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0xC04),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0xC08),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0xC0C),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0xC10),
-        SAVE_ITEM(S5P_VA_GIC_DIST + 0xC14),
-
-        SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x000),
-        SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x010),
-        SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x020),
-        SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x030),
-        SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x040),
-        SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x050),
-        SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x060),
-        SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x070),
-        SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x080),
-        SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x090),
-
+static struct sleep_save exynos_core_save[] = {
         /* SROM side */
         SAVE_ITEM(S5P_SROM_BW),
         SAVE_ITEM(S5P_SROM_BC0),
@@ -159,9 +75,11 @@ static struct sleep_save exynos4_core_save[] = {
 /* For Cortex-A9 Diagnostic and Power control register */
 static unsigned int save_arm_register[2];
 
-static int exynos4_cpu_suspend(unsigned long arg)
+static int exynos_cpu_suspend(unsigned long arg)
 {
+#ifdef CONFIG_CACHE_L2X0
         outer_flush_all();
+#endif
 
         /* issue the standby signal into the pm unit. */
         cpu_do_idle();
@@ -170,19 +88,25 @@ static int exynos4_cpu_suspend(unsigned long arg)
         panic("sleep resumed to originator?");
 }
 
-static void exynos4_pm_prepare(void)
+static void exynos_pm_prepare(void)
 {
-        u32 tmp;
+        unsigned int tmp;
 
-        s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
-        s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
-        s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
+        s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 
-        tmp = __raw_readl(S5P_INFORM1);
+        if (!soc_is_exynos5250()) {
+                s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
+                s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
+        } else {
+                /* Disable USE_RETENTION of JPEG_MEM_OPTION */
+                tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
+                tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
+                __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
+        }
 
         /* Set value of power down register for sleep mode */
 
-        exynos4_sys_powerdown_conf(SYS_SLEEP);
+        exynos_sys_powerdown_conf(SYS_SLEEP);
         __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
 
         /* ensure at least INFORM0 has the resume address */
@@ -191,17 +115,18 @@ static void exynos4_pm_prepare(void)
 
         /* Before enter central sequence mode, clock src register have to set */
 
-        s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
+        if (!soc_is_exynos5250())
+                s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
 
         if (soc_is_exynos4210())
                 s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));
 
 }
 
-static int exynos4_pm_add(struct device *dev, struct subsys_interface *sif)
+static int exynos_pm_add(struct device *dev, struct subsys_interface *sif)
 {
-        pm_cpu_prep = exynos4_pm_prepare;
-        pm_cpu_sleep = exynos4_cpu_suspend;
+        pm_cpu_prep = exynos_pm_prepare;
+        pm_cpu_sleep = exynos_cpu_suspend;
 
         return 0;
 }
@@ -273,13 +198,13 @@ static void exynos4_restore_pll(void)
         } while (epll_wait || vpll_wait);
 }
 
-static struct subsys_interface exynos4_pm_interface = {
-        .name           = "exynos4_pm",
+static struct subsys_interface exynos_pm_interface = {
+        .name           = "exynos_pm",
         .subsys         = &exynos_subsys,
-        .add_dev        = exynos4_pm_add,
+        .add_dev        = exynos_pm_add,
 };
 
-static __init int exynos4_pm_drvinit(void)
+static __init int exynos_pm_drvinit(void)
 {
         struct clk *pll_base;
         unsigned int tmp;
@@ -292,18 +217,20 @@ static __init int exynos4_pm_drvinit(void)
         tmp |= ((0xFF << 8) | (0x1F << 1));
         __raw_writel(tmp, S5P_WAKEUP_MASK);
 
-        pll_base = clk_get(NULL, "xtal");
+        if (!soc_is_exynos5250()) {
+                pll_base = clk_get(NULL, "xtal");
 
-        if (!IS_ERR(pll_base)) {
-                pll_base_rate = clk_get_rate(pll_base);
-                clk_put(pll_base);
+                if (!IS_ERR(pll_base)) {
+                        pll_base_rate = clk_get_rate(pll_base);
+                        clk_put(pll_base);
+                }
         }
 
-        return subsys_interface_register(&exynos4_pm_interface);
+        return subsys_interface_register(&exynos_pm_interface);
 }
-arch_initcall(exynos4_pm_drvinit);
+arch_initcall(exynos_pm_drvinit);
 
-static int exynos4_pm_suspend(void)
+static int exynos_pm_suspend(void)
 {
         unsigned long tmp;
 
@@ -313,27 +240,27 @@ static int exynos4_pm_suspend(void)
         tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
         __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 
-        if (soc_is_exynos4212() || soc_is_exynos4412()) {
-                tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION);
-                tmp &= ~(S5P_USE_STANDBYWFI_ISP_ARM |
-                         S5P_USE_STANDBYWFE_ISP_ARM);
-                __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
-        }
+        /* Setting SEQ_OPTION register */
+
+        tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
+        __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
 
-        /* Save Power control register */
-        asm ("mrc p15, 0, %0, c15, c0, 0"
-             : "=r" (tmp) : : "cc");
-        save_arm_register[0] = tmp;
+        if (!soc_is_exynos5250()) {
+                /* Save Power control register */
+                asm ("mrc p15, 0, %0, c15, c0, 0"
+                     : "=r" (tmp) : : "cc");
+                save_arm_register[0] = tmp;
 
-        /* Save Diagnostic register */
-        asm ("mrc p15, 0, %0, c15, c0, 1"
-             : "=r" (tmp) : : "cc");
-        save_arm_register[1] = tmp;
+                /* Save Diagnostic register */
+                asm ("mrc p15, 0, %0, c15, c0, 1"
+                     : "=r" (tmp) : : "cc");
+                save_arm_register[1] = tmp;
+        }
 
         return 0;
 }
 
-static void exynos4_pm_resume(void)
+static void exynos_pm_resume(void)
 {
         unsigned long tmp;
 
@@ -350,17 +277,19 @@ static void exynos4_pm_resume(void)
                 /* No need to perform below restore code */
                 goto early_wakeup;
         }
-        /* Restore Power control register */
-        tmp = save_arm_register[0];
-        asm volatile ("mcr p15, 0, %0, c15, c0, 0"
-                      : : "r" (tmp)
-                      : "cc");
-
-        /* Restore Diagnostic register */
-        tmp = save_arm_register[1];
-        asm volatile ("mcr p15, 0, %0, c15, c0, 1"
-                      : : "r" (tmp)
-                      : "cc");
+        if (!soc_is_exynos5250()) {
+                /* Restore Power control register */
+                tmp = save_arm_register[0];
+                asm volatile ("mcr p15, 0, %0, c15, c0, 0"
+                              : : "r" (tmp)
+                              : "cc");
+
+                /* Restore Diagnostic register */
+                tmp = save_arm_register[1];
+                asm volatile ("mcr p15, 0, %0, c15, c0, 1"
+                              : : "r" (tmp)
+                              : "cc");
+        }
 
         /* For release retention */
 
@@ -372,26 +301,28 @@ static void exynos4_pm_resume(void)
         __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
         __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
 
-        s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
+        s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 
-        exynos4_restore_pll();
+        if (!soc_is_exynos5250()) {
+                exynos4_restore_pll();
 
 #ifdef CONFIG_SMP
-        scu_enable(S5P_VA_SCU);
+                scu_enable(S5P_VA_SCU);
 #endif
+        }
 
 early_wakeup:
         return;
 }
 
-static struct syscore_ops exynos4_pm_syscore_ops = {
-        .suspend        = exynos4_pm_suspend,
-        .resume         = exynos4_pm_resume,
+static struct syscore_ops exynos_pm_syscore_ops = {
+        .suspend        = exynos_pm_suspend,
+        .resume         = exynos_pm_resume,
 };
 
-static __init int exynos4_pm_syscore_init(void)
+static __init int exynos_pm_syscore_init(void)
 {
-        register_syscore_ops(&exynos4_pm_syscore_ops);
+        register_syscore_ops(&exynos_pm_syscore_ops);
         return 0;
 }
-arch_initcall(exynos4_pm_syscore_init);
+arch_initcall(exynos_pm_syscore_init);
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index 77c6815eebee..4aacb66f7161 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -1,9 +1,8 @@
-/* linux/arch/arm/mach-exynos4/pmu.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+/*
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com/
  *
- * EXYNOS4210 - CPU PMU(Power Management Unit) support
+ * EXYNOS - CPU PMU(Power Management Unit) support
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -12,13 +11,14 @@
 
 #include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/bug.h>
 
 #include <mach/regs-clock.h>
 #include <mach/pmu.h>
 
-static struct exynos4_pmu_conf *exynos4_pmu_config;
+static struct exynos_pmu_conf *exynos_pmu_config;
 
-static struct exynos4_pmu_conf exynos4210_pmu_config[] = {
+static struct exynos_pmu_conf exynos4210_pmu_config[] = {
         /* { .reg = address, .val = { AFTR, LPA, SLEEP } */
         { S5P_ARM_CORE0_LOWPWR,                 { 0x0, 0x0, 0x2 } },
         { S5P_DIS_IRQ_CORE0,                    { 0x0, 0x0, 0x0 } },
@@ -94,7 +94,7 @@ static struct exynos4_pmu_conf exynos4210_pmu_config[] = {
         { PMU_TABLE_END,},
 };
 
-static struct exynos4_pmu_conf exynos4x12_pmu_config[] = {
+static struct exynos_pmu_conf exynos4x12_pmu_config[] = {
         { S5P_ARM_CORE0_LOWPWR,                 { 0x0, 0x0, 0x2 } },
         { S5P_DIS_IRQ_CORE0,                    { 0x0, 0x0, 0x0 } },
         { S5P_DIS_IRQ_CENTRAL0,                 { 0x0, 0x0, 0x0 } },
@@ -202,7 +202,7 @@ static struct exynos4_pmu_conf exynos4x12_pmu_config[] = {
         { PMU_TABLE_END,},
 };
 
-static struct exynos4_pmu_conf exynos4412_pmu_config[] = {
+static struct exynos_pmu_conf exynos4412_pmu_config[] = {
         { S5P_ARM_CORE2_LOWPWR,                 { 0x0, 0x0, 0x2 } },
         { S5P_DIS_IRQ_CORE2,                    { 0x0, 0x0, 0x0 } },
         { S5P_DIS_IRQ_CENTRAL2,                 { 0x0, 0x0, 0x0 } },
@@ -212,13 +212,174 @@ static struct exynos4_pmu_conf exynos4412_pmu_config[] = {
         { PMU_TABLE_END,},
 };
 
-void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
+static struct exynos_pmu_conf exynos5250_pmu_config[] = {
+        /* { .reg = address, .val = { AFTR, LPA, SLEEP } */
+        { EXYNOS5_ARM_CORE0_SYS_PWR_REG,                { 0x0, 0x0, 0x2} },
+        { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG,  { 0x0, 0x0, 0x0} },
+        { EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG,        { 0x0, 0x0, 0x0} },
+        { EXYNOS5_ARM_CORE1_SYS_PWR_REG,                { 0x0, 0x0, 0x2} },
+        { EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG,  { 0x0, 0x0, 0x0} },
+        { EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG,        { 0x0, 0x0, 0x0} },
+        { EXYNOS5_FSYS_ARM_SYS_PWR_REG,                 { 0x1, 0x0, 0x0} },
+        { EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
+        { EXYNOS5_ISP_ARM_SYS_PWR_REG,                  { 0x1, 0x0, 0x0} },
+        { EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG,    { 0x0, 0x0, 0x0} },
+        { EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG,  { 0x0, 0x0, 0x0} },
+        { EXYNOS5_ARM_COMMON_SYS_PWR_REG,               { 0x0, 0x0, 0x2} },
+        { EXYNOS5_ARM_L2_SYS_PWR_REG,                   { 0x3, 0x3, 0x3} },
+        { EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG,             { 0x1, 0x0, 0x1} },
+        { EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG,             { 0x1, 0x0, 0x1} },
+        { EXYNOS5_CMU_RESET_SYS_PWR_REG,                { 0x1, 0x1, 0x0} },
+        { EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG,      { 0x1, 0x0, 0x1} },
+        { EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG,      { 0x1, 0x0, 0x1} },
+        { EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG,         { 0x1, 0x1, 0x0} },
+        { EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG,           { 0x1, 0x1, 0x1} },
+        { EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG,            { 0x1, 0x1, 0x1} },
+        { EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG,           { 0x1, 0x1, 0x1} },
+        { EXYNOS5_APLL_SYSCLK_SYS_PWR_REG,              { 0x1, 0x0, 0x0} },
+        { EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG,              { 0x1, 0x0, 0x0} },
+        { EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG,              { 0x1, 0x0, 0x0} },
+        { EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG,              { 0x1, 0x1, 0x0} },
+        { EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG,              { 0x1, 0x0, 0x0} },
+        { EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG,              { 0x1, 0x0, 0x0} },
+        { EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
+        { EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
+        { EXYNOS5_TOP_BUS_SYS_PWR_REG,                  { 0x3, 0x0, 0x0} },
+        { EXYNOS5_TOP_RETENTION_SYS_PWR_REG,            { 0x1, 0x0, 0x1} },
+        { EXYNOS5_TOP_PWR_SYS_PWR_REG,                  { 0x3, 0x0, 0x3} },
+        { EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG,           { 0x3, 0x0, 0x0} },
+        { EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG,     { 0x1, 0x0, 0x1} },
+        { EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG,           { 0x3, 0x0, 0x3} },
+        { EXYNOS5_LOGIC_RESET_SYS_PWR_REG,              { 0x1, 0x1, 0x0} },
+        { EXYNOS5_OSCCLK_GATE_SYS_PWR_REG,              { 0x1, 0x0, 0x1} },
+        { EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG,       { 0x1, 0x1, 0x0} },
+        { EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG,       { 0x1, 0x0, 0x1} },
+        { EXYNOS5_USBOTG_MEM_SYS_PWR_REG,               { 0x3, 0x0, 0x0} },
+        { EXYNOS5_G2D_MEM_SYS_PWR_REG,                  { 0x3, 0x0, 0x0} },
+        { EXYNOS5_USBDRD_MEM_SYS_PWR_REG,               { 0x3, 0x0, 0x0} },
+        { EXYNOS5_SDMMC_MEM_SYS_PWR_REG,                { 0x3, 0x0, 0x0} },
+        { EXYNOS5_CSSYS_MEM_SYS_PWR_REG,                { 0x3, 0x0, 0x0} },
+        { EXYNOS5_SECSS_MEM_SYS_PWR_REG,                { 0x3, 0x0, 0x0} },
+        { EXYNOS5_ROTATOR_MEM_SYS_PWR_REG,              { 0x3, 0x0, 0x0} },
+        { EXYNOS5_INTRAM_MEM_SYS_PWR_REG,               { 0x3, 0x0, 0x0} },
+        { EXYNOS5_INTROM_MEM_SYS_PWR_REG,               { 0x3, 0x0, 0x0} },
+        { EXYNOS5_JPEG_MEM_SYS_PWR_REG,                 { 0x3, 0x0, 0x0} },
+        { EXYNOS5_HSI_MEM_SYS_PWR_REG,                  { 0x3, 0x0, 0x0} },
+        { EXYNOS5_MCUIOP_MEM_SYS_PWR_REG,               { 0x3, 0x0, 0x0} },
+        { EXYNOS5_SATA_MEM_SYS_PWR_REG,                 { 0x3, 0x0, 0x0} },
+        { EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG,       { 0x1, 0x0, 0x0} },
+        { EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG,        { 0x1, 0x1, 0x0} },
+        { EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG,       { 0x1, 0x0, 0x0} },
+        { EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG,       { 0x1, 0x0, 0x0} },
+        { EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG,       { 0x1, 0x0, 0x0} },
+        { EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG,       { 0x1, 0x0, 0x0} },
+        { EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG,       { 0x1, 0x0, 0x0} },
+        { EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG,       { 0x1, 0x0, 0x0} },
+        { EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG,        { 0x1, 0x0, 0x0} },
+        { EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG,        { 0x1, 0x0, 0x0} },
+        { EXYNOS5_PAD_ISOLATION_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
+        { EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG,     { 0x1, 0x0, 0x0} },
+        { EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG,              { 0x1, 0x0, 0x0} },
+        { EXYNOS5_XUSBXTI_SYS_PWR_REG,                  { 0x1, 0x1, 0x1} },
+        { EXYNOS5_XXTI_SYS_PWR_REG,                     { 0x1, 0x1, 0x0} },
+        { EXYNOS5_EXT_REGULATOR_SYS_PWR_REG,            { 0x1, 0x1, 0x0} },
+        { EXYNOS5_GPIO_MODE_SYS_PWR_REG,                { 0x1, 0x0, 0x0} },
+        { EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG,         { 0x1, 0x0, 0x0} },
+        { EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG,            { 0x1, 0x1, 0x0} },
+        { EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG,            { 0x1, 0x1, 0x1} },
+        { EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG,        { 0x1, 0x0, 0x1} },
+        { EXYNOS5_GSCL_SYS_PWR_REG,                     { 0x7, 0x0, 0x0} },
+        { EXYNOS5_ISP_SYS_PWR_REG,                      { 0x7, 0x0, 0x0} },
+        { EXYNOS5_MFC_SYS_PWR_REG,                      { 0x7, 0x0, 0x0} },
+        { EXYNOS5_G3D_SYS_PWR_REG,                      { 0x7, 0x0, 0x0} },
+        { EXYNOS5_DISP1_SYS_PWR_REG,                    { 0x7, 0x0, 0x0} },
+        { EXYNOS5_MAU_SYS_PWR_REG,                      { 0x7, 0x7, 0x0} },
+        { EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG,         { 0x1, 0x0, 0x0} },
+        { EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
+        { EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
+        { EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
+        { EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG,        { 0x1, 0x0, 0x0} },
+        { EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG,          { 0x1, 0x1, 0x0} },
+        { EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
+        { EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG,           { 0x1, 0x0, 0x0} },
+        { EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG,           { 0x1, 0x0, 0x0} },
+        { EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG,           { 0x1, 0x0, 0x0} },
+        { EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG,         { 0x1, 0x0, 0x0} },
+        { EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG,           { 0x1, 0x1, 0x0} },
+        { EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG,           { 0x1, 0x0, 0x0} },
+        { EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
+        { EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
+        { EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
+        { EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
+        { EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG,            { 0x1, 0x1, 0x0} },
+        { PMU_TABLE_END,},
+};
+
+void __iomem *exynos5_list_both_cnt_feed[] = {
+        EXYNOS5_ARM_CORE0_OPTION,
+        EXYNOS5_ARM_CORE1_OPTION,
+        EXYNOS5_ARM_COMMON_OPTION,
+        EXYNOS5_GSCL_OPTION,
+        EXYNOS5_ISP_OPTION,
+        EXYNOS5_MFC_OPTION,
+        EXYNOS5_G3D_OPTION,
+        EXYNOS5_DISP1_OPTION,
+        EXYNOS5_MAU_OPTION,
+        EXYNOS5_TOP_PWR_OPTION,
+        EXYNOS5_TOP_PWR_SYSMEM_OPTION,
+};
+
+void __iomem *exynos5_list_diable_wfi_wfe[] = {
+        EXYNOS5_ARM_CORE1_OPTION,
+        EXYNOS5_FSYS_ARM_OPTION,
+        EXYNOS5_ISP_ARM_OPTION,
+};
+
+static void exynos5_init_pmu(void)
 {
         unsigned int i;
+        unsigned int tmp;
+
+        /*
+         * Enable both SC_FEEDBACK and SC_COUNTER
+         */
+        for (i = 0 ; i < ARRAY_SIZE(exynos5_list_both_cnt_feed) ; i++) {
+                tmp = __raw_readl(exynos5_list_both_cnt_feed[i]);
+                tmp |= (EXYNOS5_USE_SC_FEEDBACK |
+                        EXYNOS5_USE_SC_COUNTER);
+                __raw_writel(tmp, exynos5_list_both_cnt_feed[i]);
+        }
+
+        /*
+         * SKIP_DEACTIVATE_ACEACP_IN_PWDN_BITFIELD Enable
+         * MANUAL_L2RSTDISABLE_CONTROL_BITFIELD Enable
+         */
+        tmp = __raw_readl(EXYNOS5_ARM_COMMON_OPTION);
+        tmp |= (EXYNOS5_MANUAL_L2RSTDISABLE_CONTROL |
+                EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN);
+        __raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION);
+
+        /*
+         * Disable WFI/WFE on XXX_OPTION
+         */
+        for (i = 0 ; i < ARRAY_SIZE(exynos5_list_diable_wfi_wfe) ; i++) {
+                tmp = __raw_readl(exynos5_list_diable_wfi_wfe[i]);
+                tmp &= ~(EXYNOS5_OPTION_USE_STANDBYWFE |
+                         EXYNOS5_OPTION_USE_STANDBYWFI);
+                __raw_writel(tmp, exynos5_list_diable_wfi_wfe[i]);
+        }
+}
+
+void exynos_sys_powerdown_conf(enum sys_powerdown mode)
+{
+        unsigned int i;
+
+        if (soc_is_exynos5250())
+                exynos5_init_pmu();
 
-        for (i = 0; (exynos4_pmu_config[i].reg != PMU_TABLE_END) ; i++)
-                __raw_writel(exynos4_pmu_config[i].val[mode],
-                                exynos4_pmu_config[i].reg);
+        for (i = 0; (exynos_pmu_config[i].reg != PMU_TABLE_END) ; i++)
+                __raw_writel(exynos_pmu_config[i].val[mode],
+                                exynos_pmu_config[i].reg);
 
         if (soc_is_exynos4412()) {
                 for (i = 0; exynos4412_pmu_config[i].reg != PMU_TABLE_END ; i++)
@@ -227,20 +388,23 @@ void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
         }
 }
 
-static int __init exynos4_pmu_init(void)
+static int __init exynos_pmu_init(void)
 {
-        exynos4_pmu_config = exynos4210_pmu_config;
+        exynos_pmu_config = exynos4210_pmu_config;
 
         if (soc_is_exynos4210()) {
-                exynos4_pmu_config = exynos4210_pmu_config;
+                exynos_pmu_config = exynos4210_pmu_config;
                 pr_info("EXYNOS4210 PMU Initialize\n");
         } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
-                exynos4_pmu_config = exynos4x12_pmu_config;
+                exynos_pmu_config = exynos4x12_pmu_config;
                 pr_info("EXYNOS4x12 PMU Initialize\n");
+        } else if (soc_is_exynos5250()) {
+                exynos_pmu_config = exynos5250_pmu_config;
+                pr_info("EXYNOS5250 PMU Initialize\n");
         } else {
-                pr_info("EXYNOS4: PMU not supported\n");
+                pr_info("EXYNOS: PMU not supported\n");
         }
 
         return 0;
 }
-arch_initcall(exynos4_pmu_init);
+arch_initcall(exynos_pmu_init);