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-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi16
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts13
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca5s.dts13
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca9.dts9
-rw-r--r--arch/arm/mach-exynos/Kconfig2
-rw-r--r--arch/arm/mach-exynos/Makefile2
-rw-r--r--arch/arm/mach-exynos/clock-exynos5.c51
-rw-r--r--arch/arm/mach-exynos/cpuidle.c2
-rw-r--r--arch/arm/mach-exynos/include/mach/pm-core.h2
-rw-r--r--arch/arm/mach-exynos/include/mach/pmu.h4
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-clock.h18
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-pmu.h141
-rw-r--r--arch/arm/mach-exynos/pm.c223
-rw-r--r--arch/arm/mach-exynos/pmu.c200
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/irqs.h15
-rw-r--r--arch/arm/mach-s3c24xx/irq-s3c2416.c98
-rw-r--r--arch/arm/mach-s3c24xx/s3c2416.c1
-rw-r--r--arch/arm/mach-vexpress/v2m.c2
-rw-r--r--arch/arm/plat-samsung/include/plat/s3c2416.h3
19 files changed, 630 insertions, 185 deletions
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 5ca0cdb76413..4272b2949228 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -30,6 +30,22 @@
30 reg = <0x10481000 0x1000>, <0x10482000 0x2000>; 30 reg = <0x10481000 0x1000>, <0x10482000 0x2000>;
31 }; 31 };
32 32
33 combiner:interrupt-controller@10440000 {
34 compatible = "samsung,exynos4210-combiner";
35 #interrupt-cells = <2>;
36 interrupt-controller;
37 samsung,combiner-nr = <32>;
38 reg = <0x10440000 0x1000>;
39 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
40 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
41 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
42 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
43 <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
44 <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
45 <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
46 <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
47 };
48
33 watchdog { 49 watchdog {
34 compatible = "samsung,s3c2410-wdt"; 50 compatible = "samsung,s3c2410-wdt";
35 reg = <0x101D0000 0x100>; 51 reg = <0x101D0000 0x100>;
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
index 941b161ab78c..7e1091d91af8 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
@@ -73,7 +73,10 @@
73 #address-cells = <0>; 73 #address-cells = <0>;
74 interrupt-controller; 74 interrupt-controller;
75 reg = <0x2c001000 0x1000>, 75 reg = <0x2c001000 0x1000>,
76 <0x2c002000 0x100>; 76 <0x2c002000 0x1000>,
77 <0x2c004000 0x2000>,
78 <0x2c006000 0x2000>;
79 interrupts = <1 9 0xf04>;
77 }; 80 };
78 81
79 memory-controller@7ffd0000 { 82 memory-controller@7ffd0000 {
@@ -93,6 +96,14 @@
93 <0 91 4>; 96 <0 91 4>;
94 }; 97 };
95 98
99 timer {
100 compatible = "arm,armv7-timer";
101 interrupts = <1 13 0xf08>,
102 <1 14 0xf08>,
103 <1 11 0xf08>,
104 <1 10 0xf08>;
105 };
106
96 pmu { 107 pmu {
97 compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu"; 108 compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
98 interrupts = <0 68 4>, 109 interrupts = <0 68 4>,
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
index 6905e66d4748..18917a0f8604 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
@@ -77,13 +77,18 @@
77 77
78 timer@2c000600 { 78 timer@2c000600 {
79 compatible = "arm,cortex-a5-twd-timer"; 79 compatible = "arm,cortex-a5-twd-timer";
80 reg = <0x2c000600 0x38>; 80 reg = <0x2c000600 0x20>;
81 interrupts = <1 2 0x304>, 81 interrupts = <1 13 0x304>;
82 <1 3 0x304>; 82 };
83
84 watchdog@2c000620 {
85 compatible = "arm,cortex-a5-twd-wdt";
86 reg = <0x2c000620 0x20>;
87 interrupts = <1 14 0x304>;
83 }; 88 };
84 89
85 gic: interrupt-controller@2c001000 { 90 gic: interrupt-controller@2c001000 {
86 compatible = "arm,corex-a5-gic", "arm,cortex-a9-gic"; 91 compatible = "arm,cortex-a5-gic", "arm,cortex-a9-gic";
87 #interrupt-cells = <3>; 92 #interrupt-cells = <3>;
88 #address-cells = <0>; 93 #address-cells = <0>;
89 interrupt-controller; 94 interrupt-controller;
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
index da778693be54..3f0c736d31d6 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
@@ -105,8 +105,13 @@
105 timer@1e000600 { 105 timer@1e000600 {
106 compatible = "arm,cortex-a9-twd-timer"; 106 compatible = "arm,cortex-a9-twd-timer";
107 reg = <0x1e000600 0x20>; 107 reg = <0x1e000600 0x20>;
108 interrupts = <1 2 0xf04>, 108 interrupts = <1 13 0xf04>;
109 <1 3 0xf04>; 109 };
110
111 watchdog@1e000620 {
112 compatible = "arm,cortex-a9-twd-wdt";
113 reg = <0x1e000620 0x20>;
114 interrupts = <1 14 0xf04>;
110 }; 115 };
111 116
112 gic: interrupt-controller@1e001000 { 117 gic: interrupt-controller@1e001000 {
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 43ebe9094411..573be57d3d28 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -62,6 +62,8 @@ config SOC_EXYNOS5250
62 default y 62 default y
63 depends on ARCH_EXYNOS5 63 depends on ARCH_EXYNOS5
64 select SAMSUNG_DMADEV 64 select SAMSUNG_DMADEV
65 select S5P_PM if PM
66 select S5P_SLEEP if PM
65 help 67 help
66 Enable EXYNOS5250 SoC support 68 Enable EXYNOS5250 SoC support
67 69
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 440a637c76f1..9b58024f7d43 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -22,7 +22,7 @@ obj-$(CONFIG_PM) += pm.o
22obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o 22obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
23obj-$(CONFIG_CPU_IDLE) += cpuidle.o 23obj-$(CONFIG_CPU_IDLE) += cpuidle.o
24 24
25obj-$(CONFIG_ARCH_EXYNOS4) += pmu.o 25obj-$(CONFIG_ARCH_EXYNOS) += pmu.o
26 26
27obj-$(CONFIG_SMP) += platsmp.o headsmp.o 27obj-$(CONFIG_SMP) += platsmp.o headsmp.o
28 28
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 5aa460b01fdf..fefa336be2b4 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -30,7 +30,56 @@
30 30
31#ifdef CONFIG_PM_SLEEP 31#ifdef CONFIG_PM_SLEEP
32static struct sleep_save exynos5_clock_save[] = { 32static struct sleep_save exynos5_clock_save[] = {
33 /* will be implemented */ 33 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_TOP),
34 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_GSCL),
35 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_DISP1_0),
36 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_FSYS),
37 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_MAUDIO),
38 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC0),
39 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC1),
40 SAVE_ITEM(EXYNOS5_CLKGATE_IP_GSCL),
41 SAVE_ITEM(EXYNOS5_CLKGATE_IP_DISP1),
42 SAVE_ITEM(EXYNOS5_CLKGATE_IP_MFC),
43 SAVE_ITEM(EXYNOS5_CLKGATE_IP_G3D),
44 SAVE_ITEM(EXYNOS5_CLKGATE_IP_GEN),
45 SAVE_ITEM(EXYNOS5_CLKGATE_IP_FSYS),
46 SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIC),
47 SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIS),
48 SAVE_ITEM(EXYNOS5_CLKGATE_BLOCK),
49 SAVE_ITEM(EXYNOS5_CLKDIV_TOP0),
50 SAVE_ITEM(EXYNOS5_CLKDIV_TOP1),
51 SAVE_ITEM(EXYNOS5_CLKDIV_GSCL),
52 SAVE_ITEM(EXYNOS5_CLKDIV_DISP1_0),
53 SAVE_ITEM(EXYNOS5_CLKDIV_GEN),
54 SAVE_ITEM(EXYNOS5_CLKDIV_MAUDIO),
55 SAVE_ITEM(EXYNOS5_CLKDIV_FSYS0),
56 SAVE_ITEM(EXYNOS5_CLKDIV_FSYS1),
57 SAVE_ITEM(EXYNOS5_CLKDIV_FSYS2),
58 SAVE_ITEM(EXYNOS5_CLKDIV_FSYS3),
59 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC0),
60 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC1),
61 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC2),
62 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC3),
63 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC4),
64 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC5),
65 SAVE_ITEM(EXYNOS5_SCLK_DIV_ISP),
66 SAVE_ITEM(EXYNOS5_CLKSRC_TOP0),
67 SAVE_ITEM(EXYNOS5_CLKSRC_TOP1),
68 SAVE_ITEM(EXYNOS5_CLKSRC_TOP2),
69 SAVE_ITEM(EXYNOS5_CLKSRC_TOP3),
70 SAVE_ITEM(EXYNOS5_CLKSRC_GSCL),
71 SAVE_ITEM(EXYNOS5_CLKSRC_DISP1_0),
72 SAVE_ITEM(EXYNOS5_CLKSRC_MAUDIO),
73 SAVE_ITEM(EXYNOS5_CLKSRC_FSYS),
74 SAVE_ITEM(EXYNOS5_CLKSRC_PERIC0),
75 SAVE_ITEM(EXYNOS5_CLKSRC_PERIC1),
76 SAVE_ITEM(EXYNOS5_SCLK_SRC_ISP),
77 SAVE_ITEM(EXYNOS5_EPLL_CON0),
78 SAVE_ITEM(EXYNOS5_EPLL_CON1),
79 SAVE_ITEM(EXYNOS5_EPLL_CON2),
80 SAVE_ITEM(EXYNOS5_VPLL_CON0),
81 SAVE_ITEM(EXYNOS5_VPLL_CON1),
82 SAVE_ITEM(EXYNOS5_VPLL_CON2),
34}; 83};
35#endif 84#endif
36 85
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 26dac2893b8e..cff0595d0d35 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -100,7 +100,7 @@ static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
100 exynos4_set_wakeupmask(); 100 exynos4_set_wakeupmask();
101 101
102 /* Set value of power down register for aftr mode */ 102 /* Set value of power down register for aftr mode */
103 exynos4_sys_powerdown_conf(SYS_AFTR); 103 exynos_sys_powerdown_conf(SYS_AFTR);
104 104
105 __raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR); 105 __raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR);
106 __raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG); 106 __raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);
diff --git a/arch/arm/mach-exynos/include/mach/pm-core.h b/arch/arm/mach-exynos/include/mach/pm-core.h
index 9d8da51e35ca..a67ecfaf1216 100644
--- a/arch/arm/mach-exynos/include/mach/pm-core.h
+++ b/arch/arm/mach-exynos/include/mach/pm-core.h
@@ -33,7 +33,7 @@ static inline void s3c_pm_arch_prepare_irqs(void)
33 __raw_writel(tmp, S5P_WAKEUP_MASK); 33 __raw_writel(tmp, S5P_WAKEUP_MASK);
34 34
35 __raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK); 35 __raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK);
36 __raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK); 36 __raw_writel(s3c_irqwake_eintmask & 0xFFFFFFFE, S5P_EINT_WAKEUP_MASK);
37} 37}
38 38
39static inline void s3c_pm_arch_stop_clocks(void) 39static inline void s3c_pm_arch_stop_clocks(void)
diff --git a/arch/arm/mach-exynos/include/mach/pmu.h b/arch/arm/mach-exynos/include/mach/pmu.h
index e76b7faba66b..7c27c2d4bf44 100644
--- a/arch/arm/mach-exynos/include/mach/pmu.h
+++ b/arch/arm/mach-exynos/include/mach/pmu.h
@@ -23,12 +23,12 @@ enum sys_powerdown {
23}; 23};
24 24
25extern unsigned long l2x0_regs_phys; 25extern unsigned long l2x0_regs_phys;
26struct exynos4_pmu_conf { 26struct exynos_pmu_conf {
27 void __iomem *reg; 27 void __iomem *reg;
28 unsigned int val[NUM_SYS_POWERDOWN]; 28 unsigned int val[NUM_SYS_POWERDOWN];
29}; 29};
30 30
31extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode); 31extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
32extern void s3c_cpu_resume(void); 32extern void s3c_cpu_resume(void);
33 33
34#endif /* __ASM_ARCH_PMU_H */ 34#endif /* __ASM_ARCH_PMU_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index b78b5f3ad9c0..8c9b38c9c504 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -274,36 +274,51 @@
274 274
275#define EXYNOS5_CLKDIV_ACP EXYNOS_CLKREG(0x08500) 275#define EXYNOS5_CLKDIV_ACP EXYNOS_CLKREG(0x08500)
276 276
277#define EXYNOS5_CLKSRC_TOP2 EXYNOS_CLKREG(0x10218)
278#define EXYNOS5_EPLL_CON0 EXYNOS_CLKREG(0x10130) 277#define EXYNOS5_EPLL_CON0 EXYNOS_CLKREG(0x10130)
279#define EXYNOS5_EPLL_CON1 EXYNOS_CLKREG(0x10134) 278#define EXYNOS5_EPLL_CON1 EXYNOS_CLKREG(0x10134)
279#define EXYNOS5_EPLL_CON2 EXYNOS_CLKREG(0x10138)
280#define EXYNOS5_VPLL_CON0 EXYNOS_CLKREG(0x10140) 280#define EXYNOS5_VPLL_CON0 EXYNOS_CLKREG(0x10140)
281#define EXYNOS5_VPLL_CON1 EXYNOS_CLKREG(0x10144) 281#define EXYNOS5_VPLL_CON1 EXYNOS_CLKREG(0x10144)
282#define EXYNOS5_VPLL_CON2 EXYNOS_CLKREG(0x10148)
282#define EXYNOS5_CPLL_CON0 EXYNOS_CLKREG(0x10120) 283#define EXYNOS5_CPLL_CON0 EXYNOS_CLKREG(0x10120)
283 284
284#define EXYNOS5_CLKSRC_TOP0 EXYNOS_CLKREG(0x10210) 285#define EXYNOS5_CLKSRC_TOP0 EXYNOS_CLKREG(0x10210)
286#define EXYNOS5_CLKSRC_TOP1 EXYNOS_CLKREG(0x10214)
287#define EXYNOS5_CLKSRC_TOP2 EXYNOS_CLKREG(0x10218)
285#define EXYNOS5_CLKSRC_TOP3 EXYNOS_CLKREG(0x1021C) 288#define EXYNOS5_CLKSRC_TOP3 EXYNOS_CLKREG(0x1021C)
286#define EXYNOS5_CLKSRC_GSCL EXYNOS_CLKREG(0x10220) 289#define EXYNOS5_CLKSRC_GSCL EXYNOS_CLKREG(0x10220)
287#define EXYNOS5_CLKSRC_DISP1_0 EXYNOS_CLKREG(0x1022C) 290#define EXYNOS5_CLKSRC_DISP1_0 EXYNOS_CLKREG(0x1022C)
291#define EXYNOS5_CLKSRC_MAUDIO EXYNOS_CLKREG(0x10240)
288#define EXYNOS5_CLKSRC_FSYS EXYNOS_CLKREG(0x10244) 292#define EXYNOS5_CLKSRC_FSYS EXYNOS_CLKREG(0x10244)
289#define EXYNOS5_CLKSRC_PERIC0 EXYNOS_CLKREG(0x10250) 293#define EXYNOS5_CLKSRC_PERIC0 EXYNOS_CLKREG(0x10250)
294#define EXYNOS5_CLKSRC_PERIC1 EXYNOS_CLKREG(0x10254)
295#define EXYNOS5_SCLK_SRC_ISP EXYNOS_CLKREG(0x10270)
290 296
291#define EXYNOS5_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x10310) 297#define EXYNOS5_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x10310)
292#define EXYNOS5_CLKSRC_MASK_GSCL EXYNOS_CLKREG(0x10320) 298#define EXYNOS5_CLKSRC_MASK_GSCL EXYNOS_CLKREG(0x10320)
293#define EXYNOS5_CLKSRC_MASK_DISP1_0 EXYNOS_CLKREG(0x1032C) 299#define EXYNOS5_CLKSRC_MASK_DISP1_0 EXYNOS_CLKREG(0x1032C)
300#define EXYNOS5_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x10334)
294#define EXYNOS5_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x10340) 301#define EXYNOS5_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x10340)
295#define EXYNOS5_CLKSRC_MASK_PERIC0 EXYNOS_CLKREG(0x10350) 302#define EXYNOS5_CLKSRC_MASK_PERIC0 EXYNOS_CLKREG(0x10350)
303#define EXYNOS5_CLKSRC_MASK_PERIC1 EXYNOS_CLKREG(0x10354)
296 304
297#define EXYNOS5_CLKDIV_TOP0 EXYNOS_CLKREG(0x10510) 305#define EXYNOS5_CLKDIV_TOP0 EXYNOS_CLKREG(0x10510)
298#define EXYNOS5_CLKDIV_TOP1 EXYNOS_CLKREG(0x10514) 306#define EXYNOS5_CLKDIV_TOP1 EXYNOS_CLKREG(0x10514)
299#define EXYNOS5_CLKDIV_GSCL EXYNOS_CLKREG(0x10520) 307#define EXYNOS5_CLKDIV_GSCL EXYNOS_CLKREG(0x10520)
300#define EXYNOS5_CLKDIV_DISP1_0 EXYNOS_CLKREG(0x1052C) 308#define EXYNOS5_CLKDIV_DISP1_0 EXYNOS_CLKREG(0x1052C)
301#define EXYNOS5_CLKDIV_GEN EXYNOS_CLKREG(0x1053C) 309#define EXYNOS5_CLKDIV_GEN EXYNOS_CLKREG(0x1053C)
310#define EXYNOS5_CLKDIV_MAUDIO EXYNOS_CLKREG(0x10544)
302#define EXYNOS5_CLKDIV_FSYS0 EXYNOS_CLKREG(0x10548) 311#define EXYNOS5_CLKDIV_FSYS0 EXYNOS_CLKREG(0x10548)
303#define EXYNOS5_CLKDIV_FSYS1 EXYNOS_CLKREG(0x1054C) 312#define EXYNOS5_CLKDIV_FSYS1 EXYNOS_CLKREG(0x1054C)
304#define EXYNOS5_CLKDIV_FSYS2 EXYNOS_CLKREG(0x10550) 313#define EXYNOS5_CLKDIV_FSYS2 EXYNOS_CLKREG(0x10550)
305#define EXYNOS5_CLKDIV_FSYS3 EXYNOS_CLKREG(0x10554) 314#define EXYNOS5_CLKDIV_FSYS3 EXYNOS_CLKREG(0x10554)
306#define EXYNOS5_CLKDIV_PERIC0 EXYNOS_CLKREG(0x10558) 315#define EXYNOS5_CLKDIV_PERIC0 EXYNOS_CLKREG(0x10558)
316#define EXYNOS5_CLKDIV_PERIC1 EXYNOS_CLKREG(0x1055C)
317#define EXYNOS5_CLKDIV_PERIC2 EXYNOS_CLKREG(0x10560)
318#define EXYNOS5_CLKDIV_PERIC3 EXYNOS_CLKREG(0x10564)
319#define EXYNOS5_CLKDIV_PERIC4 EXYNOS_CLKREG(0x10568)
320#define EXYNOS5_CLKDIV_PERIC5 EXYNOS_CLKREG(0x1056C)
321#define EXYNOS5_SCLK_DIV_ISP EXYNOS_CLKREG(0x10580)
307 322
308#define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800) 323#define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800)
309#define EXYNOS5_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x0C800) 324#define EXYNOS5_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x0C800)
@@ -311,6 +326,7 @@
311#define EXYNOS5_CLKGATE_IP_GSCL EXYNOS_CLKREG(0x10920) 326#define EXYNOS5_CLKGATE_IP_GSCL EXYNOS_CLKREG(0x10920)
312#define EXYNOS5_CLKGATE_IP_DISP1 EXYNOS_CLKREG(0x10928) 327#define EXYNOS5_CLKGATE_IP_DISP1 EXYNOS_CLKREG(0x10928)
313#define EXYNOS5_CLKGATE_IP_MFC EXYNOS_CLKREG(0x1092C) 328#define EXYNOS5_CLKGATE_IP_MFC EXYNOS_CLKREG(0x1092C)
329#define EXYNOS5_CLKGATE_IP_G3D EXYNOS_CLKREG(0x10930)
314#define EXYNOS5_CLKGATE_IP_GEN EXYNOS_CLKREG(0x10934) 330#define EXYNOS5_CLKGATE_IP_GEN EXYNOS_CLKREG(0x10934)
315#define EXYNOS5_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x10944) 331#define EXYNOS5_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x10944)
316#define EXYNOS5_CLKGATE_IP_GPS EXYNOS_CLKREG(0x1094C) 332#define EXYNOS5_CLKGATE_IP_GPS EXYNOS_CLKREG(0x1094C)
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index 4dbb8629b200..43a99e6f56ab 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -1,9 +1,8 @@
1/* linux/arch/arm/mach-exynos4/include/mach/regs-pmu.h 1/*
2 * 2 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 3 * http://www.samsung.com
5 * 4 *
6 * EXYNOS4 - Power management unit definition 5 * EXYNOS - Power management unit definition
7 * 6 *
8 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
@@ -229,4 +228,138 @@
229#define S5P_DIS_IRQ_CORE3 S5P_PMUREG(0x1034) 228#define S5P_DIS_IRQ_CORE3 S5P_PMUREG(0x1034)
230#define S5P_DIS_IRQ_CENTRAL3 S5P_PMUREG(0x1038) 229#define S5P_DIS_IRQ_CENTRAL3 S5P_PMUREG(0x1038)
231 230
231/* For EXYNOS5 */
232
233#define EXYNOS5_USB_CFG S5P_PMUREG(0x0230)
234
235#define EXYNOS5_ARM_CORE0_SYS_PWR_REG S5P_PMUREG(0x1000)
236#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1004)
237#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1008)
238#define EXYNOS5_ARM_CORE1_SYS_PWR_REG S5P_PMUREG(0x1010)
239#define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1014)
240#define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1018)
241#define EXYNOS5_FSYS_ARM_SYS_PWR_REG S5P_PMUREG(0x1040)
242#define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1048)
243#define EXYNOS5_ISP_ARM_SYS_PWR_REG S5P_PMUREG(0x1050)
244#define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1054)
245#define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1058)
246#define EXYNOS5_ARM_COMMON_SYS_PWR_REG S5P_PMUREG(0x1080)
247#define EXYNOS5_ARM_L2_SYS_PWR_REG S5P_PMUREG(0x10C0)
248#define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG S5P_PMUREG(0x1100)
249#define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG S5P_PMUREG(0x1104)
250#define EXYNOS5_CMU_RESET_SYS_PWR_REG S5P_PMUREG(0x110C)
251#define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1120)
252#define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1124)
253#define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x112C)
254#define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG S5P_PMUREG(0x1130)
255#define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG S5P_PMUREG(0x1134)
256#define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG S5P_PMUREG(0x1138)
257#define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1140)
258#define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1144)
259#define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1148)
260#define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x114C)
261#define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1150)
262#define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1154)
263#define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1164)
264#define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1170)
265#define EXYNOS5_TOP_BUS_SYS_PWR_REG S5P_PMUREG(0x1180)
266#define EXYNOS5_TOP_RETENTION_SYS_PWR_REG S5P_PMUREG(0x1184)
267#define EXYNOS5_TOP_PWR_SYS_PWR_REG S5P_PMUREG(0x1188)
268#define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1190)
269#define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1194)
270#define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1198)
271#define EXYNOS5_LOGIC_RESET_SYS_PWR_REG S5P_PMUREG(0x11A0)
272#define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG S5P_PMUREG(0x11A4)
273#define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x11B0)
274#define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x11B4)
275#define EXYNOS5_USBOTG_MEM_SYS_PWR_REG S5P_PMUREG(0x11C0)
276#define EXYNOS5_G2D_MEM_SYS_PWR_REG S5P_PMUREG(0x11C8)
277#define EXYNOS5_USBDRD_MEM_SYS_PWR_REG S5P_PMUREG(0x11CC)
278#define EXYNOS5_SDMMC_MEM_SYS_PWR_REG S5P_PMUREG(0x11D0)
279#define EXYNOS5_CSSYS_MEM_SYS_PWR_REG S5P_PMUREG(0x11D4)
280#define EXYNOS5_SECSS_MEM_SYS_PWR_REG S5P_PMUREG(0x11D8)
281#define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG S5P_PMUREG(0x11DC)
282#define EXYNOS5_INTRAM_MEM_SYS_PWR_REG S5P_PMUREG(0x11E0)
283#define EXYNOS5_INTROM_MEM_SYS_PWR_REG S5P_PMUREG(0x11E4)
284#define EXYNOS5_JPEG_MEM_SYS_PWR_REG S5P_PMUREG(0x11E8)
285#define EXYNOS5_HSI_MEM_SYS_PWR_REG S5P_PMUREG(0x11EC)
286#define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG S5P_PMUREG(0x11F4)
287#define EXYNOS5_SATA_MEM_SYS_PWR_REG S5P_PMUREG(0x11FC)
288#define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG S5P_PMUREG(0x1200)
289#define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG S5P_PMUREG(0x1204)
290#define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG S5P_PMUREG(0x1208)
291#define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG S5P_PMUREG(0x1220)
292#define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG S5P_PMUREG(0x1224)
293#define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG S5P_PMUREG(0x1228)
294#define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG S5P_PMUREG(0x122C)
295#define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG S5P_PMUREG(0x1230)
296#define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG S5P_PMUREG(0x1234)
297#define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG S5P_PMUREG(0x1238)
298#define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x123C)
299#define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG S5P_PMUREG(0x1240)
300#define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1250)
301#define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG S5P_PMUREG(0x1260)
302#define EXYNOS5_XUSBXTI_SYS_PWR_REG S5P_PMUREG(0x1280)
303#define EXYNOS5_XXTI_SYS_PWR_REG S5P_PMUREG(0x1284)
304#define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG S5P_PMUREG(0x12C0)
305#define EXYNOS5_GPIO_MODE_SYS_PWR_REG S5P_PMUREG(0x1300)
306#define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1320)
307#define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG S5P_PMUREG(0x1340)
308#define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG S5P_PMUREG(0x1344)
309#define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG S5P_PMUREG(0x1348)
310#define EXYNOS5_GSCL_SYS_PWR_REG S5P_PMUREG(0x1400)
311#define EXYNOS5_ISP_SYS_PWR_REG S5P_PMUREG(0x1404)
312#define EXYNOS5_MFC_SYS_PWR_REG S5P_PMUREG(0x1408)
313#define EXYNOS5_G3D_SYS_PWR_REG S5P_PMUREG(0x140C)
314#define EXYNOS5_DISP1_SYS_PWR_REG S5P_PMUREG(0x1414)
315#define EXYNOS5_MAU_SYS_PWR_REG S5P_PMUREG(0x1418)
316#define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG S5P_PMUREG(0x1480)
317#define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG S5P_PMUREG(0x1484)
318#define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG S5P_PMUREG(0x1488)
319#define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG S5P_PMUREG(0x148C)
320#define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG S5P_PMUREG(0x1494)
321#define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG S5P_PMUREG(0x1498)
322#define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG S5P_PMUREG(0x14C0)
323#define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG S5P_PMUREG(0x14C4)
324#define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG S5P_PMUREG(0x14C8)
325#define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG S5P_PMUREG(0x14CC)
326#define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG S5P_PMUREG(0x14D4)
327#define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG S5P_PMUREG(0x14D8)
328#define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG S5P_PMUREG(0x1580)
329#define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG S5P_PMUREG(0x1584)
330#define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG S5P_PMUREG(0x1588)
331#define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG S5P_PMUREG(0x158C)
332#define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG S5P_PMUREG(0x1594)
333#define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG S5P_PMUREG(0x1598)
334
335#define EXYNOS5_ARM_CORE0_OPTION S5P_PMUREG(0x2008)
336#define EXYNOS5_ARM_CORE1_OPTION S5P_PMUREG(0x2088)
337#define EXYNOS5_FSYS_ARM_OPTION S5P_PMUREG(0x2208)
338#define EXYNOS5_ISP_ARM_OPTION S5P_PMUREG(0x2288)
339#define EXYNOS5_ARM_COMMON_OPTION S5P_PMUREG(0x2408)
340#define EXYNOS5_TOP_PWR_OPTION S5P_PMUREG(0x2C48)
341#define EXYNOS5_TOP_PWR_SYSMEM_OPTION S5P_PMUREG(0x2CC8)
342#define EXYNOS5_JPEG_MEM_OPTION S5P_PMUREG(0x2F48)
343#define EXYNOS5_GSCL_STATUS S5P_PMUREG(0x4004)
344#define EXYNOS5_ISP_STATUS S5P_PMUREG(0x4024)
345#define EXYNOS5_GSCL_OPTION S5P_PMUREG(0x4008)
346#define EXYNOS5_ISP_OPTION S5P_PMUREG(0x4028)
347#define EXYNOS5_MFC_OPTION S5P_PMUREG(0x4048)
348#define EXYNOS5_G3D_CONFIGURATION S5P_PMUREG(0x4060)
349#define EXYNOS5_G3D_STATUS S5P_PMUREG(0x4064)
350#define EXYNOS5_G3D_OPTION S5P_PMUREG(0x4068)
351#define EXYNOS5_DISP1_OPTION S5P_PMUREG(0x40A8)
352#define EXYNOS5_MAU_OPTION S5P_PMUREG(0x40C8)
353
354#define EXYNOS5_USE_SC_FEEDBACK (1 << 1)
355#define EXYNOS5_USE_SC_COUNTER (1 << 0)
356
357#define EXYNOS5_MANUAL_L2RSTDISABLE_CONTROL (1 << 2)
358#define EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN (1 << 7)
359
360#define EXYNOS5_OPTION_USE_STANDBYWFE (1 << 24)
361#define EXYNOS5_OPTION_USE_STANDBYWFI (1 << 16)
362
363#define EXYNOS5_OPTION_USE_RETENTION (1 << 4)
364
232#endif /* __ASM_ARCH_REGS_PMU_H */ 365#endif /* __ASM_ARCH_REGS_PMU_H */
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 563dea9a6dbb..c06c992943a1 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -1,9 +1,8 @@
1/* linux/arch/arm/mach-exynos4/pm.c 1/*
2 * 2 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 3 * http://www.samsung.com
5 * 4 *
6 * EXYNOS4210 - Power Management support 5 * EXYNOS - Power Management support
7 * 6 *
8 * Based on arch/arm/mach-s3c2410/pm.c 7 * Based on arch/arm/mach-s3c2410/pm.c
9 * Copyright (c) 2006 Simtec Electronics 8 * Copyright (c) 2006 Simtec Electronics
@@ -63,90 +62,7 @@ static struct sleep_save exynos4_vpll_save[] = {
63 SAVE_ITEM(EXYNOS4_VPLL_CON1), 62 SAVE_ITEM(EXYNOS4_VPLL_CON1),
64}; 63};
65 64
66static struct sleep_save exynos4_core_save[] = { 65static struct sleep_save exynos_core_save[] = {
67 /* GIC side */
68 SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),
69 SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),
70 SAVE_ITEM(S5P_VA_GIC_CPU + 0x008),
71 SAVE_ITEM(S5P_VA_GIC_CPU + 0x00C),
72 SAVE_ITEM(S5P_VA_GIC_CPU + 0x014),
73 SAVE_ITEM(S5P_VA_GIC_CPU + 0x018),
74 SAVE_ITEM(S5P_VA_GIC_DIST + 0x000),
75 SAVE_ITEM(S5P_VA_GIC_DIST + 0x004),
76 SAVE_ITEM(S5P_VA_GIC_DIST + 0x100),
77 SAVE_ITEM(S5P_VA_GIC_DIST + 0x104),
78 SAVE_ITEM(S5P_VA_GIC_DIST + 0x108),
79 SAVE_ITEM(S5P_VA_GIC_DIST + 0x300),
80 SAVE_ITEM(S5P_VA_GIC_DIST + 0x304),
81 SAVE_ITEM(S5P_VA_GIC_DIST + 0x308),
82 SAVE_ITEM(S5P_VA_GIC_DIST + 0x400),
83 SAVE_ITEM(S5P_VA_GIC_DIST + 0x404),
84 SAVE_ITEM(S5P_VA_GIC_DIST + 0x408),
85 SAVE_ITEM(S5P_VA_GIC_DIST + 0x40C),
86 SAVE_ITEM(S5P_VA_GIC_DIST + 0x410),
87 SAVE_ITEM(S5P_VA_GIC_DIST + 0x414),
88 SAVE_ITEM(S5P_VA_GIC_DIST + 0x418),
89 SAVE_ITEM(S5P_VA_GIC_DIST + 0x41C),
90 SAVE_ITEM(S5P_VA_GIC_DIST + 0x420),
91 SAVE_ITEM(S5P_VA_GIC_DIST + 0x424),
92 SAVE_ITEM(S5P_VA_GIC_DIST + 0x428),
93 SAVE_ITEM(S5P_VA_GIC_DIST + 0x42C),
94 SAVE_ITEM(S5P_VA_GIC_DIST + 0x430),
95 SAVE_ITEM(S5P_VA_GIC_DIST + 0x434),
96 SAVE_ITEM(S5P_VA_GIC_DIST + 0x438),
97 SAVE_ITEM(S5P_VA_GIC_DIST + 0x43C),
98 SAVE_ITEM(S5P_VA_GIC_DIST + 0x440),
99 SAVE_ITEM(S5P_VA_GIC_DIST + 0x444),
100 SAVE_ITEM(S5P_VA_GIC_DIST + 0x448),
101 SAVE_ITEM(S5P_VA_GIC_DIST + 0x44C),
102 SAVE_ITEM(S5P_VA_GIC_DIST + 0x450),
103 SAVE_ITEM(S5P_VA_GIC_DIST + 0x454),
104 SAVE_ITEM(S5P_VA_GIC_DIST + 0x458),
105 SAVE_ITEM(S5P_VA_GIC_DIST + 0x45C),
106
107 SAVE_ITEM(S5P_VA_GIC_DIST + 0x800),
108 SAVE_ITEM(S5P_VA_GIC_DIST + 0x804),
109 SAVE_ITEM(S5P_VA_GIC_DIST + 0x808),
110 SAVE_ITEM(S5P_VA_GIC_DIST + 0x80C),
111 SAVE_ITEM(S5P_VA_GIC_DIST + 0x810),
112 SAVE_ITEM(S5P_VA_GIC_DIST + 0x814),
113 SAVE_ITEM(S5P_VA_GIC_DIST + 0x818),
114 SAVE_ITEM(S5P_VA_GIC_DIST + 0x81C),
115 SAVE_ITEM(S5P_VA_GIC_DIST + 0x820),
116 SAVE_ITEM(S5P_VA_GIC_DIST + 0x824),
117 SAVE_ITEM(S5P_VA_GIC_DIST + 0x828),
118 SAVE_ITEM(S5P_VA_GIC_DIST + 0x82C),
119 SAVE_ITEM(S5P_VA_GIC_DIST + 0x830),
120 SAVE_ITEM(S5P_VA_GIC_DIST + 0x834),
121 SAVE_ITEM(S5P_VA_GIC_DIST + 0x838),
122 SAVE_ITEM(S5P_VA_GIC_DIST + 0x83C),
123 SAVE_ITEM(S5P_VA_GIC_DIST + 0x840),
124 SAVE_ITEM(S5P_VA_GIC_DIST + 0x844),
125 SAVE_ITEM(S5P_VA_GIC_DIST + 0x848),
126 SAVE_ITEM(S5P_VA_GIC_DIST + 0x84C),
127 SAVE_ITEM(S5P_VA_GIC_DIST + 0x850),
128 SAVE_ITEM(S5P_VA_GIC_DIST + 0x854),
129 SAVE_ITEM(S5P_VA_GIC_DIST + 0x858),
130 SAVE_ITEM(S5P_VA_GIC_DIST + 0x85C),
131
132 SAVE_ITEM(S5P_VA_GIC_DIST + 0xC00),
133 SAVE_ITEM(S5P_VA_GIC_DIST + 0xC04),
134 SAVE_ITEM(S5P_VA_GIC_DIST + 0xC08),
135 SAVE_ITEM(S5P_VA_GIC_DIST + 0xC0C),
136 SAVE_ITEM(S5P_VA_GIC_DIST + 0xC10),
137 SAVE_ITEM(S5P_VA_GIC_DIST + 0xC14),
138
139 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x000),
140 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x010),
141 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x020),
142 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x030),
143 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x040),
144 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x050),
145 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x060),
146 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x070),
147 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x080),
148 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x090),
149
150 /* SROM side */ 66 /* SROM side */
151 SAVE_ITEM(S5P_SROM_BW), 67 SAVE_ITEM(S5P_SROM_BW),
152 SAVE_ITEM(S5P_SROM_BC0), 68 SAVE_ITEM(S5P_SROM_BC0),
@@ -159,9 +75,11 @@ static struct sleep_save exynos4_core_save[] = {
159/* For Cortex-A9 Diagnostic and Power control register */ 75/* For Cortex-A9 Diagnostic and Power control register */
160static unsigned int save_arm_register[2]; 76static unsigned int save_arm_register[2];
161 77
162static int exynos4_cpu_suspend(unsigned long arg) 78static int exynos_cpu_suspend(unsigned long arg)
163{ 79{
80#ifdef CONFIG_CACHE_L2X0
164 outer_flush_all(); 81 outer_flush_all();
82#endif
165 83
166 /* issue the standby signal into the pm unit. */ 84 /* issue the standby signal into the pm unit. */
167 cpu_do_idle(); 85 cpu_do_idle();
@@ -170,19 +88,25 @@ static int exynos4_cpu_suspend(unsigned long arg)
170 panic("sleep resumed to originator?"); 88 panic("sleep resumed to originator?");
171} 89}
172 90
173static void exynos4_pm_prepare(void) 91static void exynos_pm_prepare(void)
174{ 92{
175 u32 tmp; 93 unsigned int tmp;
176 94
177 s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); 95 s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
178 s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
179 s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
180 96
181 tmp = __raw_readl(S5P_INFORM1); 97 if (!soc_is_exynos5250()) {
98 s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
99 s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
100 } else {
101 /* Disable USE_RETENTION of JPEG_MEM_OPTION */
102 tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
103 tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
104 __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
105 }
182 106
183 /* Set value of power down register for sleep mode */ 107 /* Set value of power down register for sleep mode */
184 108
185 exynos4_sys_powerdown_conf(SYS_SLEEP); 109 exynos_sys_powerdown_conf(SYS_SLEEP);
186 __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1); 110 __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
187 111
188 /* ensure at least INFORM0 has the resume address */ 112 /* ensure at least INFORM0 has the resume address */
@@ -191,17 +115,18 @@ static void exynos4_pm_prepare(void)
191 115
192 /* Before enter central sequence mode, clock src register have to set */ 116 /* Before enter central sequence mode, clock src register have to set */
193 117
194 s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc)); 118 if (!soc_is_exynos5250())
119 s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
195 120
196 if (soc_is_exynos4210()) 121 if (soc_is_exynos4210())
197 s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc)); 122 s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));
198 123
199} 124}
200 125
201static int exynos4_pm_add(struct device *dev, struct subsys_interface *sif) 126static int exynos_pm_add(struct device *dev, struct subsys_interface *sif)
202{ 127{
203 pm_cpu_prep = exynos4_pm_prepare; 128 pm_cpu_prep = exynos_pm_prepare;
204 pm_cpu_sleep = exynos4_cpu_suspend; 129 pm_cpu_sleep = exynos_cpu_suspend;
205 130
206 return 0; 131 return 0;
207} 132}
@@ -273,13 +198,13 @@ static void exynos4_restore_pll(void)
273 } while (epll_wait || vpll_wait); 198 } while (epll_wait || vpll_wait);
274} 199}
275 200
276static struct subsys_interface exynos4_pm_interface = { 201static struct subsys_interface exynos_pm_interface = {
277 .name = "exynos4_pm", 202 .name = "exynos_pm",
278 .subsys = &exynos_subsys, 203 .subsys = &exynos_subsys,
279 .add_dev = exynos4_pm_add, 204 .add_dev = exynos_pm_add,
280}; 205};
281 206
282static __init int exynos4_pm_drvinit(void) 207static __init int exynos_pm_drvinit(void)
283{ 208{
284 struct clk *pll_base; 209 struct clk *pll_base;
285 unsigned int tmp; 210 unsigned int tmp;
@@ -292,18 +217,20 @@ static __init int exynos4_pm_drvinit(void)
292 tmp |= ((0xFF << 8) | (0x1F << 1)); 217 tmp |= ((0xFF << 8) | (0x1F << 1));
293 __raw_writel(tmp, S5P_WAKEUP_MASK); 218 __raw_writel(tmp, S5P_WAKEUP_MASK);
294 219
295 pll_base = clk_get(NULL, "xtal"); 220 if (!soc_is_exynos5250()) {
221 pll_base = clk_get(NULL, "xtal");
296 222
297 if (!IS_ERR(pll_base)) { 223 if (!IS_ERR(pll_base)) {
298 pll_base_rate = clk_get_rate(pll_base); 224 pll_base_rate = clk_get_rate(pll_base);
299 clk_put(pll_base); 225 clk_put(pll_base);
226 }
300 } 227 }
301 228
302 return subsys_interface_register(&exynos4_pm_interface); 229 return subsys_interface_register(&exynos_pm_interface);
303} 230}
304arch_initcall(exynos4_pm_drvinit); 231arch_initcall(exynos_pm_drvinit);
305 232
306static int exynos4_pm_suspend(void) 233static int exynos_pm_suspend(void)
307{ 234{
308 unsigned long tmp; 235 unsigned long tmp;
309 236
@@ -313,27 +240,27 @@ static int exynos4_pm_suspend(void)
313 tmp &= ~S5P_CENTRAL_LOWPWR_CFG; 240 tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
314 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); 241 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
315 242
316 if (soc_is_exynos4212() || soc_is_exynos4412()) { 243 /* Setting SEQ_OPTION register */
317 tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION); 244
318 tmp &= ~(S5P_USE_STANDBYWFI_ISP_ARM | 245 tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
319 S5P_USE_STANDBYWFE_ISP_ARM); 246 __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
320 __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
321 }
322 247
323 /* Save Power control register */ 248 if (!soc_is_exynos5250()) {
324 asm ("mrc p15, 0, %0, c15, c0, 0" 249 /* Save Power control register */
325 : "=r" (tmp) : : "cc"); 250 asm ("mrc p15, 0, %0, c15, c0, 0"
326 save_arm_register[0] = tmp; 251 : "=r" (tmp) : : "cc");
252 save_arm_register[0] = tmp;
327 253
328 /* Save Diagnostic register */ 254 /* Save Diagnostic register */
329 asm ("mrc p15, 0, %0, c15, c0, 1" 255 asm ("mrc p15, 0, %0, c15, c0, 1"
330 : "=r" (tmp) : : "cc"); 256 : "=r" (tmp) : : "cc");
331 save_arm_register[1] = tmp; 257 save_arm_register[1] = tmp;
258 }
332 259
333 return 0; 260 return 0;
334} 261}
335 262
336static void exynos4_pm_resume(void) 263static void exynos_pm_resume(void)
337{ 264{
338 unsigned long tmp; 265 unsigned long tmp;
339 266
@@ -350,17 +277,19 @@ static void exynos4_pm_resume(void)
350 /* No need to perform below restore code */ 277 /* No need to perform below restore code */
351 goto early_wakeup; 278 goto early_wakeup;
352 } 279 }
353 /* Restore Power control register */ 280 if (!soc_is_exynos5250()) {
354 tmp = save_arm_register[0]; 281 /* Restore Power control register */
355 asm volatile ("mcr p15, 0, %0, c15, c0, 0" 282 tmp = save_arm_register[0];
356 : : "r" (tmp) 283 asm volatile ("mcr p15, 0, %0, c15, c0, 0"
357 : "cc"); 284 : : "r" (tmp)
358 285 : "cc");
359 /* Restore Diagnostic register */ 286
360 tmp = save_arm_register[1]; 287 /* Restore Diagnostic register */
361 asm volatile ("mcr p15, 0, %0, c15, c0, 1" 288 tmp = save_arm_register[1];
362 : : "r" (tmp) 289 asm volatile ("mcr p15, 0, %0, c15, c0, 1"
363 : "cc"); 290 : : "r" (tmp)
291 : "cc");
292 }
364 293
365 /* For release retention */ 294 /* For release retention */
366 295
@@ -372,26 +301,28 @@ static void exynos4_pm_resume(void)
372 __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION); 301 __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
373 __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION); 302 __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
374 303
375 s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); 304 s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
376 305
377 exynos4_restore_pll(); 306 if (!soc_is_exynos5250()) {
307 exynos4_restore_pll();
378 308
379#ifdef CONFIG_SMP 309#ifdef CONFIG_SMP
380 scu_enable(S5P_VA_SCU); 310 scu_enable(S5P_VA_SCU);
381#endif 311#endif
312 }
382 313
383early_wakeup: 314early_wakeup:
384 return; 315 return;
385} 316}
386 317
387static struct syscore_ops exynos4_pm_syscore_ops = { 318static struct syscore_ops exynos_pm_syscore_ops = {
388 .suspend = exynos4_pm_suspend, 319 .suspend = exynos_pm_suspend,
389 .resume = exynos4_pm_resume, 320 .resume = exynos_pm_resume,
390}; 321};
391 322
392static __init int exynos4_pm_syscore_init(void) 323static __init int exynos_pm_syscore_init(void)
393{ 324{
394 register_syscore_ops(&exynos4_pm_syscore_ops); 325 register_syscore_ops(&exynos_pm_syscore_ops);
395 return 0; 326 return 0;
396} 327}
397arch_initcall(exynos4_pm_syscore_init); 328arch_initcall(exynos_pm_syscore_init);
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index 77c6815eebee..4aacb66f7161 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -1,9 +1,8 @@
1/* linux/arch/arm/mach-exynos4/pmu.c 1/*
2 * 2 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 3 * http://www.samsung.com/
5 * 4 *
6 * EXYNOS4210 - CPU PMU(Power Management Unit) support 5 * EXYNOS - CPU PMU(Power Management Unit) support
7 * 6 *
8 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
@@ -12,13 +11,14 @@
12 11
13#include <linux/io.h> 12#include <linux/io.h>
14#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/bug.h>
15 15
16#include <mach/regs-clock.h> 16#include <mach/regs-clock.h>
17#include <mach/pmu.h> 17#include <mach/pmu.h>
18 18
19static struct exynos4_pmu_conf *exynos4_pmu_config; 19static struct exynos_pmu_conf *exynos_pmu_config;
20 20
21static struct exynos4_pmu_conf exynos4210_pmu_config[] = { 21static struct exynos_pmu_conf exynos4210_pmu_config[] = {
22 /* { .reg = address, .val = { AFTR, LPA, SLEEP } */ 22 /* { .reg = address, .val = { AFTR, LPA, SLEEP } */
23 { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } }, 23 { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
24 { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } }, 24 { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
@@ -94,7 +94,7 @@ static struct exynos4_pmu_conf exynos4210_pmu_config[] = {
94 { PMU_TABLE_END,}, 94 { PMU_TABLE_END,},
95}; 95};
96 96
97static struct exynos4_pmu_conf exynos4x12_pmu_config[] = { 97static struct exynos_pmu_conf exynos4x12_pmu_config[] = {
98 { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } }, 98 { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
99 { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } }, 99 { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
100 { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } }, 100 { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } },
@@ -202,7 +202,7 @@ static struct exynos4_pmu_conf exynos4x12_pmu_config[] = {
202 { PMU_TABLE_END,}, 202 { PMU_TABLE_END,},
203}; 203};
204 204
205static struct exynos4_pmu_conf exynos4412_pmu_config[] = { 205static struct exynos_pmu_conf exynos4412_pmu_config[] = {
206 { S5P_ARM_CORE2_LOWPWR, { 0x0, 0x0, 0x2 } }, 206 { S5P_ARM_CORE2_LOWPWR, { 0x0, 0x0, 0x2 } },
207 { S5P_DIS_IRQ_CORE2, { 0x0, 0x0, 0x0 } }, 207 { S5P_DIS_IRQ_CORE2, { 0x0, 0x0, 0x0 } },
208 { S5P_DIS_IRQ_CENTRAL2, { 0x0, 0x0, 0x0 } }, 208 { S5P_DIS_IRQ_CENTRAL2, { 0x0, 0x0, 0x0 } },
@@ -212,13 +212,174 @@ static struct exynos4_pmu_conf exynos4412_pmu_config[] = {
212 { PMU_TABLE_END,}, 212 { PMU_TABLE_END,},
213}; 213};
214 214
215void exynos4_sys_powerdown_conf(enum sys_powerdown mode) 215static struct exynos_pmu_conf exynos5250_pmu_config[] = {
216 /* { .reg = address, .val = { AFTR, LPA, SLEEP } */
217 { EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
218 { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
219 { EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
220 { EXYNOS5_ARM_CORE1_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
221 { EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
222 { EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
223 { EXYNOS5_FSYS_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
224 { EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
225 { EXYNOS5_ISP_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
226 { EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
227 { EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
228 { EXYNOS5_ARM_COMMON_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
229 { EXYNOS5_ARM_L2_SYS_PWR_REG, { 0x3, 0x3, 0x3} },
230 { EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
231 { EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
232 { EXYNOS5_CMU_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
233 { EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
234 { EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
235 { EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
236 { EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
237 { EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
238 { EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
239 { EXYNOS5_APLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
240 { EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
241 { EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
242 { EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
243 { EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
244 { EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
245 { EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
246 { EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
247 { EXYNOS5_TOP_BUS_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
248 { EXYNOS5_TOP_RETENTION_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
249 { EXYNOS5_TOP_PWR_SYS_PWR_REG, { 0x3, 0x0, 0x3} },
250 { EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
251 { EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
252 { EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG, { 0x3, 0x0, 0x3} },
253 { EXYNOS5_LOGIC_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
254 { EXYNOS5_OSCCLK_GATE_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
255 { EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
256 { EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
257 { EXYNOS5_USBOTG_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
258 { EXYNOS5_G2D_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
259 { EXYNOS5_USBDRD_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
260 { EXYNOS5_SDMMC_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
261 { EXYNOS5_CSSYS_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
262 { EXYNOS5_SECSS_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
263 { EXYNOS5_ROTATOR_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
264 { EXYNOS5_INTRAM_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
265 { EXYNOS5_INTROM_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
266 { EXYNOS5_JPEG_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
267 { EXYNOS5_HSI_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
268 { EXYNOS5_MCUIOP_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
269 { EXYNOS5_SATA_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
270 { EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
271 { EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
272 { EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
273 { EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
274 { EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
275 { EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
276 { EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
277 { EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
278 { EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
279 { EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
280 { EXYNOS5_PAD_ISOLATION_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
281 { EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
282 { EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
283 { EXYNOS5_XUSBXTI_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
284 { EXYNOS5_XXTI_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
285 { EXYNOS5_EXT_REGULATOR_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
286 { EXYNOS5_GPIO_MODE_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
287 { EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
288 { EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
289 { EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
290 { EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
291 { EXYNOS5_GSCL_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
292 { EXYNOS5_ISP_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
293 { EXYNOS5_MFC_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
294 { EXYNOS5_G3D_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
295 { EXYNOS5_DISP1_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
296 { EXYNOS5_MAU_SYS_PWR_REG, { 0x7, 0x7, 0x0} },
297 { EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
298 { EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
299 { EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
300 { EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
301 { EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
302 { EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
303 { EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
304 { EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
305 { EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
306 { EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
307 { EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
308 { EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
309 { EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
310 { EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
311 { EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
312 { EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
313 { EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
314 { EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
315 { PMU_TABLE_END,},
316};
317
318void __iomem *exynos5_list_both_cnt_feed[] = {
319 EXYNOS5_ARM_CORE0_OPTION,
320 EXYNOS5_ARM_CORE1_OPTION,
321 EXYNOS5_ARM_COMMON_OPTION,
322 EXYNOS5_GSCL_OPTION,
323 EXYNOS5_ISP_OPTION,
324 EXYNOS5_MFC_OPTION,
325 EXYNOS5_G3D_OPTION,
326 EXYNOS5_DISP1_OPTION,
327 EXYNOS5_MAU_OPTION,
328 EXYNOS5_TOP_PWR_OPTION,
329 EXYNOS5_TOP_PWR_SYSMEM_OPTION,
330};
331
332void __iomem *exynos5_list_diable_wfi_wfe[] = {
333 EXYNOS5_ARM_CORE1_OPTION,
334 EXYNOS5_FSYS_ARM_OPTION,
335 EXYNOS5_ISP_ARM_OPTION,
336};
337
338static void exynos5_init_pmu(void)
216{ 339{
217 unsigned int i; 340 unsigned int i;
341 unsigned int tmp;
342
343 /*
344 * Enable both SC_FEEDBACK and SC_COUNTER
345 */
346 for (i = 0 ; i < ARRAY_SIZE(exynos5_list_both_cnt_feed) ; i++) {
347 tmp = __raw_readl(exynos5_list_both_cnt_feed[i]);
348 tmp |= (EXYNOS5_USE_SC_FEEDBACK |
349 EXYNOS5_USE_SC_COUNTER);
350 __raw_writel(tmp, exynos5_list_both_cnt_feed[i]);
351 }
352
353 /*
354 * SKIP_DEACTIVATE_ACEACP_IN_PWDN_BITFIELD Enable
355 * MANUAL_L2RSTDISABLE_CONTROL_BITFIELD Enable
356 */
357 tmp = __raw_readl(EXYNOS5_ARM_COMMON_OPTION);
358 tmp |= (EXYNOS5_MANUAL_L2RSTDISABLE_CONTROL |
359 EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN);
360 __raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION);
361
362 /*
363 * Disable WFI/WFE on XXX_OPTION
364 */
365 for (i = 0 ; i < ARRAY_SIZE(exynos5_list_diable_wfi_wfe) ; i++) {
366 tmp = __raw_readl(exynos5_list_diable_wfi_wfe[i]);
367 tmp &= ~(EXYNOS5_OPTION_USE_STANDBYWFE |
368 EXYNOS5_OPTION_USE_STANDBYWFI);
369 __raw_writel(tmp, exynos5_list_diable_wfi_wfe[i]);
370 }
371}
372
373void exynos_sys_powerdown_conf(enum sys_powerdown mode)
374{
375 unsigned int i;
376
377 if (soc_is_exynos5250())
378 exynos5_init_pmu();
218 379
219 for (i = 0; (exynos4_pmu_config[i].reg != PMU_TABLE_END) ; i++) 380 for (i = 0; (exynos_pmu_config[i].reg != PMU_TABLE_END) ; i++)
220 __raw_writel(exynos4_pmu_config[i].val[mode], 381 __raw_writel(exynos_pmu_config[i].val[mode],
221 exynos4_pmu_config[i].reg); 382 exynos_pmu_config[i].reg);
222 383
223 if (soc_is_exynos4412()) { 384 if (soc_is_exynos4412()) {
224 for (i = 0; exynos4412_pmu_config[i].reg != PMU_TABLE_END ; i++) 385 for (i = 0; exynos4412_pmu_config[i].reg != PMU_TABLE_END ; i++)
@@ -227,20 +388,23 @@ void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
227 } 388 }
228} 389}
229 390
230static int __init exynos4_pmu_init(void) 391static int __init exynos_pmu_init(void)
231{ 392{
232 exynos4_pmu_config = exynos4210_pmu_config; 393 exynos_pmu_config = exynos4210_pmu_config;
233 394
234 if (soc_is_exynos4210()) { 395 if (soc_is_exynos4210()) {
235 exynos4_pmu_config = exynos4210_pmu_config; 396 exynos_pmu_config = exynos4210_pmu_config;
236 pr_info("EXYNOS4210 PMU Initialize\n"); 397 pr_info("EXYNOS4210 PMU Initialize\n");
237 } else if (soc_is_exynos4212() || soc_is_exynos4412()) { 398 } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
238 exynos4_pmu_config = exynos4x12_pmu_config; 399 exynos_pmu_config = exynos4x12_pmu_config;
239 pr_info("EXYNOS4x12 PMU Initialize\n"); 400 pr_info("EXYNOS4x12 PMU Initialize\n");
401 } else if (soc_is_exynos5250()) {
402 exynos_pmu_config = exynos5250_pmu_config;
403 pr_info("EXYNOS5250 PMU Initialize\n");
240 } else { 404 } else {
241 pr_info("EXYNOS4: PMU not supported\n"); 405 pr_info("EXYNOS: PMU not supported\n");
242 } 406 }
243 407
244 return 0; 408 return 0;
245} 409}
246arch_initcall(exynos4_pmu_init); 410arch_initcall(exynos_pmu_init);
diff --git a/arch/arm/mach-s3c24xx/include/mach/irqs.h b/arch/arm/mach-s3c24xx/include/mach/irqs.h
index e53b2177319e..b7a9f4d469e8 100644
--- a/arch/arm/mach-s3c24xx/include/mach/irqs.h
+++ b/arch/arm/mach-s3c24xx/include/mach/irqs.h
@@ -134,6 +134,17 @@
134#define IRQ_S32416_WDT S3C2410_IRQSUB(27) 134#define IRQ_S32416_WDT S3C2410_IRQSUB(27)
135#define IRQ_S32416_AC97 S3C2410_IRQSUB(28) 135#define IRQ_S32416_AC97 S3C2410_IRQSUB(28)
136 136
137/* second interrupt-register of s3c2416/s3c2450 */
138
139#define S3C2416_IRQ(x) S3C2410_IRQ((x) + 54 + 29)
140#define IRQ_S3C2416_2D S3C2416_IRQ(0)
141#define IRQ_S3C2416_IIC1 S3C2416_IRQ(1)
142#define IRQ_S3C2416_RESERVED2 S3C2416_IRQ(2)
143#define IRQ_S3C2416_RESERVED3 S3C2416_IRQ(3)
144#define IRQ_S3C2416_PCM0 S3C2416_IRQ(4)
145#define IRQ_S3C2416_PCM1 S3C2416_IRQ(5)
146#define IRQ_S3C2416_I2S0 S3C2416_IRQ(6)
147#define IRQ_S3C2416_I2S1 S3C2416_IRQ(7)
137 148
138/* extra irqs for s3c2440 */ 149/* extra irqs for s3c2440 */
139 150
@@ -175,7 +186,9 @@
175#define IRQ_S3C2443_WDT S3C2410_IRQSUB(27) 186#define IRQ_S3C2443_WDT S3C2410_IRQSUB(27)
176#define IRQ_S3C2443_AC97 S3C2410_IRQSUB(28) 187#define IRQ_S3C2443_AC97 S3C2410_IRQSUB(28)
177 188
178#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416) 189#if defined(CONFIG_CPU_S3C2416)
190#define NR_IRQS (IRQ_S3C2416_I2S1 + 1)
191#elif defined(CONFIG_CPU_S3C2443)
179#define NR_IRQS (IRQ_S3C2443_AC97+1) 192#define NR_IRQS (IRQ_S3C2443_AC97+1)
180#else 193#else
181#define NR_IRQS (IRQ_S3C2440_AC97+1) 194#define NR_IRQS (IRQ_S3C2440_AC97+1)
diff --git a/arch/arm/mach-s3c24xx/irq-s3c2416.c b/arch/arm/mach-s3c24xx/irq-s3c2416.c
index fd49f35e448e..23ec97370f32 100644
--- a/arch/arm/mach-s3c24xx/irq-s3c2416.c
+++ b/arch/arm/mach-s3c24xx/irq-s3c2416.c
@@ -27,6 +27,7 @@
27#include <linux/ioport.h> 27#include <linux/ioport.h>
28#include <linux/device.h> 28#include <linux/device.h>
29#include <linux/io.h> 29#include <linux/io.h>
30#include <linux/syscore_ops.h>
30 31
31#include <mach/hardware.h> 32#include <mach/hardware.h>
32#include <asm/irq.h> 33#include <asm/irq.h>
@@ -192,6 +193,43 @@ static struct irq_chip s3c2416_irq_uart3 = {
192 .irq_ack = s3c2416_irq_uart3_ack, 193 .irq_ack = s3c2416_irq_uart3_ack,
193}; 194};
194 195
196/* second interrupt register */
197
198static inline void s3c2416_irq_ack_second(struct irq_data *data)
199{
200 unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D);
201
202 __raw_writel(bitval, S3C2416_SRCPND2);
203 __raw_writel(bitval, S3C2416_INTPND2);
204}
205
206static void s3c2416_irq_mask_second(struct irq_data *data)
207{
208 unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D);
209 unsigned long mask;
210
211 mask = __raw_readl(S3C2416_INTMSK2);
212 mask |= bitval;
213 __raw_writel(mask, S3C2416_INTMSK2);
214}
215
216static void s3c2416_irq_unmask_second(struct irq_data *data)
217{
218 unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D);
219 unsigned long mask;
220
221 mask = __raw_readl(S3C2416_INTMSK2);
222 mask &= ~bitval;
223 __raw_writel(mask, S3C2416_INTMSK2);
224}
225
226struct irq_chip s3c2416_irq_second = {
227 .irq_ack = s3c2416_irq_ack_second,
228 .irq_mask = s3c2416_irq_mask_second,
229 .irq_unmask = s3c2416_irq_unmask_second,
230};
231
232
195/* IRQ initialisation code */ 233/* IRQ initialisation code */
196 234
197static int __init s3c2416_add_sub(unsigned int base, 235static int __init s3c2416_add_sub(unsigned int base,
@@ -213,6 +251,42 @@ static int __init s3c2416_add_sub(unsigned int base,
213 return 0; 251 return 0;
214} 252}
215 253
254static void __init s3c2416_irq_add_second(void)
255{
256 unsigned long pend;
257 unsigned long last;
258 int irqno;
259 int i;
260
261 /* first, clear all interrupts pending... */
262 last = 0;
263 for (i = 0; i < 4; i++) {
264 pend = __raw_readl(S3C2416_INTPND2);
265
266 if (pend == 0 || pend == last)
267 break;
268
269 __raw_writel(pend, S3C2416_SRCPND2);
270 __raw_writel(pend, S3C2416_INTPND2);
271 printk(KERN_INFO "irq: clearing pending status %08x\n",
272 (int)pend);
273 last = pend;
274 }
275
276 for (irqno = IRQ_S3C2416_2D; irqno <= IRQ_S3C2416_I2S1; irqno++) {
277 switch (irqno) {
278 case IRQ_S3C2416_RESERVED2:
279 case IRQ_S3C2416_RESERVED3:
280 /* no IRQ here */
281 break;
282 default:
283 irq_set_chip_and_handler(irqno, &s3c2416_irq_second,
284 handle_edge_irq);
285 set_irq_flags(irqno, IRQF_VALID);
286 }
287 }
288}
289
216static int __init s3c2416_irq_add(struct device *dev, 290static int __init s3c2416_irq_add(struct device *dev,
217 struct subsys_interface *sif) 291 struct subsys_interface *sif)
218{ 292{
@@ -232,6 +306,8 @@ static int __init s3c2416_irq_add(struct device *dev,
232 &s3c2416_irq_wdtac97, 306 &s3c2416_irq_wdtac97,
233 IRQ_S3C2443_WDT, IRQ_S3C2443_AC97); 307 IRQ_S3C2443_WDT, IRQ_S3C2443_AC97);
234 308
309 s3c2416_irq_add_second();
310
235 return 0; 311 return 0;
236} 312}
237 313
@@ -248,3 +324,25 @@ static int __init s3c2416_irq_init(void)
248 324
249arch_initcall(s3c2416_irq_init); 325arch_initcall(s3c2416_irq_init);
250 326
327#ifdef CONFIG_PM
328static struct sleep_save irq_save[] = {
329 SAVE_ITEM(S3C2416_INTMSK2),
330};
331
332int s3c2416_irq_suspend(void)
333{
334 s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
335
336 return 0;
337}
338
339void s3c2416_irq_resume(void)
340{
341 s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
342}
343
344struct syscore_ops s3c2416_irq_syscore_ops = {
345 .suspend = s3c2416_irq_suspend,
346 .resume = s3c2416_irq_resume,
347};
348#endif
diff --git a/arch/arm/mach-s3c24xx/s3c2416.c b/arch/arm/mach-s3c24xx/s3c2416.c
index 7743fade50df..ed5a95ece9eb 100644
--- a/arch/arm/mach-s3c24xx/s3c2416.c
+++ b/arch/arm/mach-s3c24xx/s3c2416.c
@@ -106,6 +106,7 @@ int __init s3c2416_init(void)
106 register_syscore_ops(&s3c2416_pm_syscore_ops); 106 register_syscore_ops(&s3c2416_pm_syscore_ops);
107#endif 107#endif
108 register_syscore_ops(&s3c24xx_irq_syscore_ops); 108 register_syscore_ops(&s3c24xx_irq_syscore_ops);
109 register_syscore_ops(&s3c2416_irq_syscore_ops);
109 110
110 return device_register(&s3c2416_dev); 111 return device_register(&s3c2416_dev);
111} 112}
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 04dd092211b8..fde26adaef32 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -14,7 +14,6 @@
14#include <linux/ata_platform.h> 14#include <linux/ata_platform.h>
15#include <linux/smsc911x.h> 15#include <linux/smsc911x.h>
16#include <linux/spinlock.h> 16#include <linux/spinlock.h>
17#include <linux/device.h>
18#include <linux/usb/isp1760.h> 17#include <linux/usb/isp1760.h>
19#include <linux/clkdev.h> 18#include <linux/clkdev.h>
20#include <linux/mtd/physmap.h> 19#include <linux/mtd/physmap.h>
@@ -31,7 +30,6 @@
31#include <asm/hardware/gic.h> 30#include <asm/hardware/gic.h>
32#include <asm/hardware/timer-sp.h> 31#include <asm/hardware/timer-sp.h>
33#include <asm/hardware/sp810.h> 32#include <asm/hardware/sp810.h>
34#include <asm/hardware/gic.h>
35 33
36#include <mach/ct-ca9x4.h> 34#include <mach/ct-ca9x4.h>
37#include <mach/motherboard.h> 35#include <mach/motherboard.h>
diff --git a/arch/arm/plat-samsung/include/plat/s3c2416.h b/arch/arm/plat-samsung/include/plat/s3c2416.h
index de2b5bdc5ebd..7178e338e25e 100644
--- a/arch/arm/plat-samsung/include/plat/s3c2416.h
+++ b/arch/arm/plat-samsung/include/plat/s3c2416.h
@@ -24,6 +24,9 @@ extern void s3c2416_init_clocks(int xtal);
24extern int s3c2416_baseclk_add(void); 24extern int s3c2416_baseclk_add(void);
25 25
26extern void s3c2416_restart(char mode, const char *cmd); 26extern void s3c2416_restart(char mode, const char *cmd);
27
28extern struct syscore_ops s3c2416_irq_syscore_ops;
29
27#else 30#else
28#define s3c2416_init_clocks NULL 31#define s3c2416_init_clocks NULL
29#define s3c2416_init_uarts NULL 32#define s3c2416_init_uarts NULL
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-11 07:16:50 -0400