19 files changed, 630 insertions, 185 deletions

diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 5ca0cdb76413..4272b2949228 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -30,6 +30,22 @@
                 reg = <0x10481000 0x1000>, <0x10482000 0x2000>;
         };
 
+        combiner:interrupt-controller@10440000 {
+                compatible = "samsung,exynos4210-combiner";
+                #interrupt-cells = <2>;
+                interrupt-controller;
+                samsung,combiner-nr = <32>;
+                reg = <0x10440000 0x1000>;
+                interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+                             <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+                             <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+                             <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
+                             <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
+                             <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
+                             <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
+                             <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
+        };
+
         watchdog {
                 compatible = "samsung,s3c2410-wdt";
                 reg = <0x101D0000 0x100>;
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
index 941b161ab78c..7e1091d91af8 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
@@ -73,7 +73,10 @@
                 #address-cells = <0>;
                 interrupt-controller;
                 reg = <0x2c001000 0x1000>,
-                      <0x2c002000 0x100>;
+                      <0x2c002000 0x1000>,
+                      <0x2c004000 0x2000>,
+                      <0x2c006000 0x2000>;
+                interrupts = <1 9 0xf04>;
         };
 
         memory-controller@7ffd0000 {
@@ -93,6 +96,14 @@
                              <0 91 4>;
         };
 
+        timer {
+                compatible = "arm,armv7-timer";
+                interrupts = <1 13 0xf08>,
+                             <1 14 0xf08>,
+                             <1 11 0xf08>,
+                             <1 10 0xf08>;
+        };
+
         pmu {
                 compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
                 interrupts = <0 68 4>,
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
index 6905e66d4748..18917a0f8604 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
@@ -77,13 +77,18 @@
 
         timer@2c000600 {
                 compatible = "arm,cortex-a5-twd-timer";
-                reg = <0x2c000600 0x38>;
-                interrupts = <1 2 0x304>,
-                             <1 3 0x304>;
+                reg = <0x2c000600 0x20>;
+                interrupts = <1 13 0x304>;
+        };
+
+        watchdog@2c000620 {
+                compatible = "arm,cortex-a5-twd-wdt";
+                reg = <0x2c000620 0x20>;
+                interrupts = <1 14 0x304>;
         };
 
         gic: interrupt-controller@2c001000 {
-                compatible = "arm,corex-a5-gic", "arm,cortex-a9-gic";
+                compatible = "arm,cortex-a5-gic", "arm,cortex-a9-gic";
                 #interrupt-cells = <3>;
                 #address-cells = <0>;
                 interrupt-controller;
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
index da778693be54..3f0c736d31d6 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
@@ -105,8 +105,13 @@
         timer@1e000600 {
                 compatible = "arm,cortex-a9-twd-timer";
                 reg = <0x1e000600 0x20>;
-                interrupts = <1 2 0xf04>,
-                             <1 3 0xf04>;
+                interrupts = <1 13 0xf04>;
+        };
+
+        watchdog@1e000620 {
+                compatible = "arm,cortex-a9-twd-wdt";
+                reg = <0x1e000620 0x20>;
+                interrupts = <1 14 0xf04>;
         };
 
         gic: interrupt-controller@1e001000 {
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 43ebe9094411..573be57d3d28 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -62,6 +62,8 @@ config SOC_EXYNOS5250
         default y
         depends on ARCH_EXYNOS5
         select SAMSUNG_DMADEV
+        select S5P_PM if PM
+        select S5P_SLEEP if PM
         help
           Enable EXYNOS5250 SoC support
 
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 440a637c76f1..9b58024f7d43 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -22,7 +22,7 @@ obj-$(CONFIG_PM)		+= pm.o
 obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
 obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
 
-obj-$(CONFIG_ARCH_EXYNOS4)      += pmu.o
+obj-$(CONFIG_ARCH_EXYNOS)       += pmu.o
 
 obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
 
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 5aa460b01fdf..fefa336be2b4 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -30,7 +30,56 @@
 
 #ifdef CONFIG_PM_SLEEP
 static struct sleep_save exynos5_clock_save[] = {
-        /* will be implemented */
+        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_TOP),
+        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_GSCL),
+        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_DISP1_0),
+        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_FSYS),
+        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_MAUDIO),
+        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC0),
+        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC1),
+        SAVE_ITEM(EXYNOS5_CLKGATE_IP_GSCL),
+        SAVE_ITEM(EXYNOS5_CLKGATE_IP_DISP1),
+        SAVE_ITEM(EXYNOS5_CLKGATE_IP_MFC),
+        SAVE_ITEM(EXYNOS5_CLKGATE_IP_G3D),
+        SAVE_ITEM(EXYNOS5_CLKGATE_IP_GEN),
+        SAVE_ITEM(EXYNOS5_CLKGATE_IP_FSYS),
+        SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIC),
+        SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIS),
+        SAVE_ITEM(EXYNOS5_CLKGATE_BLOCK),
+        SAVE_ITEM(EXYNOS5_CLKDIV_TOP0),
+        SAVE_ITEM(EXYNOS5_CLKDIV_TOP1),