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authorTomasz Figa <t.figa@samsung.com>2013-06-14 20:04:58 -0400
committerKukjin Kim <kgene.kim@samsung.com>2013-06-14 20:33:13 -0400
commit3c70348c7c4b2580e6282145ae867337bfe681e0 (patch)
tree169f37e0c122ca48bd90b1b13ec81127bde32ad6 /arch/arm/mach-exynos
parentd243997f125e92123932f0a2efaa63f1a76b3482 (diff)
ARM: EXYNOS: Remove legacy timer initialization code
This patch removes legacy timer initialization code that was used to set up system timers when booting with ATAGS, which is not supported on Exynos any more. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-exynos')
-rw-r--r--arch/arm/mach-exynos/common.c39
1 files changed, 2 insertions, 37 deletions
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 9626ce4f1346..b1d0afa3c723 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -299,13 +299,6 @@ static struct map_desc exynos5440_iodesc0[] __initdata = {
299 }, 299 },
300}; 300};
301 301
302static struct samsung_pwm_variant exynos4_pwm_variant = {
303 .bits = 32,
304 .div_base = 0,
305 .has_tint_cstat = true,
306 .tclk_mask = 0,
307};
308
309void exynos4_restart(char mode, const char *cmd) 302void exynos4_restart(char mode, const char *cmd)
310{ 303{
311 __raw_writel(0x1, S5P_SWRESET); 304 __raw_writel(0x1, S5P_SWRESET);
@@ -451,38 +444,10 @@ static void __init exynos5440_map_io(void)
451 iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0)); 444 iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
452} 445}
453 446
454void __init exynos_set_timer_source(u8 channels)
455{
456 exynos4_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
457 exynos4_pwm_variant.output_mask &= ~channels;
458}
459
460void __init exynos_init_time(void) 447void __init exynos_init_time(void)
461{ 448{
462 unsigned int timer_irqs[SAMSUNG_PWM_NUM] = { 449 of_clk_init(NULL);
463 EXYNOS4_IRQ_TIMER0_VIC, EXYNOS4_IRQ_TIMER1_VIC, 450 clocksource_of_init();
464 EXYNOS4_IRQ_TIMER2_VIC, EXYNOS4_IRQ_TIMER3_VIC,
465 EXYNOS4_IRQ_TIMER4_VIC,
466 };
467
468 if (of_have_populated_dt()) {
469 of_clk_init(NULL);
470 clocksource_of_init();
471 } else {
472 /* todo: remove after migrating legacy E4 platforms to dt */
473#ifdef CONFIG_ARCH_EXYNOS4
474 exynos4_clk_init(NULL, !soc_is_exynos4210(), S5P_VA_CMU, readl(S5P_VA_CHIPID + 8) & 1);
475 exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
476#endif
477#ifdef CONFIG_CLKSRC_SAMSUNG_PWM
478 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
479 samsung_pwm_clocksource_init(S3C_VA_TIMER,
480 timer_irqs, &exynos4_pwm_variant);
481 else
482#endif
483 mct_init(S5P_VA_SYSTIMER, EXYNOS4_IRQ_MCT_G0,
484 EXYNOS4_IRQ_MCT_L0, EXYNOS4_IRQ_MCT_L1);
485 }
486} 451}
487 452
488void __init exynos4_init_irq(void) 453void __init exynos4_init_irq(void)