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authorKukjin Kim <kgene.kim@samsung.com>2011-02-14 02:22:36 -0500
committerKukjin Kim <kgene.kim@samsung.com>2011-02-21 23:51:15 -0500
commit3db3ae5eb94eb8579991174fe66999261b66018d (patch)
tree5a5dea5a697c1fc13d325b14b642e562cf794136 /arch/arm/mach-exynos4
parent3c31336dc5b7ea5b6d6168a8c38c46dd54d65e95 (diff)
ARM: EXYNOS4: Update device support
This patch updates device support of EXYNOS4 according to the change of ARCH name, EXYNOS4. Cc: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-exynos4')
-rw-r--r--arch/arm/mach-exynos4/dev-audio.c367
-rw-r--r--arch/arm/mach-exynos4/dev-pd.c139
-rw-r--r--arch/arm/mach-exynos4/dev-sysmmu.c189
-rw-r--r--arch/arm/mach-exynos4/setup-i2c1.c23
-rw-r--r--arch/arm/mach-exynos4/setup-i2c2.c23
-rw-r--r--arch/arm/mach-exynos4/setup-i2c3.c23
-rw-r--r--arch/arm/mach-exynos4/setup-i2c4.c23
-rw-r--r--arch/arm/mach-exynos4/setup-i2c5.c23
-rw-r--r--arch/arm/mach-exynos4/setup-i2c6.c23
-rw-r--r--arch/arm/mach-exynos4/setup-i2c7.c23
-rw-r--r--arch/arm/mach-exynos4/setup-sdhci-gpio.c152
-rw-r--r--arch/arm/mach-exynos4/setup-sdhci.c69
12 files changed, 1077 insertions, 0 deletions
diff --git a/arch/arm/mach-exynos4/dev-audio.c b/arch/arm/mach-exynos4/dev-audio.c
new file mode 100644
index 000000000000..1eed5f9f7bd3
--- /dev/null
+++ b/arch/arm/mach-exynos4/dev-audio.c
@@ -0,0 +1,367 @@
1/* linux/arch/arm/mach-exynos4/dev-audio.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright (c) 2010 Samsung Electronics Co. Ltd
7 * Jaswinder Singh <jassi.brar@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/platform_device.h>
15#include <linux/dma-mapping.h>
16#include <linux/gpio.h>
17
18#include <plat/gpio-cfg.h>
19#include <plat/audio.h>
20
21#include <mach/map.h>
22#include <mach/dma.h>
23#include <mach/irqs.h>
24
25static const char *rclksrc[] = {
26 [0] = "busclk",
27 [1] = "i2sclk",
28};
29
30static int exynos4_cfg_i2s(struct platform_device *pdev)
31{
32 /* configure GPIO for i2s port */
33 switch (pdev->id) {
34 case 0:
35 s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 7, S3C_GPIO_SFN(2));
36 break;
37 case 1:
38 s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(2));
39 break;
40 case 2:
41 s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(4));
42 break;
43 default:
44 printk(KERN_ERR "Invalid Device %d\n", pdev->id);
45 return -EINVAL;
46 }
47
48 return 0;
49}
50
51static struct s3c_audio_pdata i2sv5_pdata = {
52 .cfg_gpio = exynos4_cfg_i2s,
53 .type = {
54 .i2s = {
55 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
56 | QUIRK_NEED_RSTCLR,
57 .src_clk = rclksrc,
58 },
59 },
60};
61
62static struct resource exynos4_i2s0_resource[] = {
63 [0] = {
64 .start = EXYNOS4_PA_I2S0,
65 .end = EXYNOS4_PA_I2S0 + 0x100 - 1,
66 .flags = IORESOURCE_MEM,
67 },
68 [1] = {
69 .start = DMACH_I2S0_TX,
70 .end = DMACH_I2S0_TX,
71 .flags = IORESOURCE_DMA,
72 },
73 [2] = {
74 .start = DMACH_I2S0_RX,
75 .end = DMACH_I2S0_RX,
76 .flags = IORESOURCE_DMA,
77 },
78 [3] = {
79 .start = DMACH_I2S0S_TX,
80 .end = DMACH_I2S0S_TX,
81 .flags = IORESOURCE_DMA,
82 },
83};
84
85struct platform_device exynos4_device_i2s0 = {
86 .name = "samsung-i2s",
87 .id = 0,
88 .num_resources = ARRAY_SIZE(exynos4_i2s0_resource),
89 .resource = exynos4_i2s0_resource,
90 .dev = {
91 .platform_data = &i2sv5_pdata,
92 },
93};
94
95static const char *rclksrc_v3[] = {
96 [0] = "sclk_i2s",
97 [1] = "no_such_clock",
98};
99
100static struct s3c_audio_pdata i2sv3_pdata = {
101 .cfg_gpio = exynos4_cfg_i2s,
102 .type = {
103 .i2s = {
104 .quirks = QUIRK_NO_MUXPSR,
105 .src_clk = rclksrc_v3,
106 },
107 },
108};
109
110static struct resource exynos4_i2s1_resource[] = {
111 [0] = {
112 .start = EXYNOS4_PA_I2S1,
113 .end = EXYNOS4_PA_I2S1 + 0x100 - 1,
114 .flags = IORESOURCE_MEM,
115 },
116 [1] = {
117 .start = DMACH_I2S1_TX,
118 .end = DMACH_I2S1_TX,
119 .flags = IORESOURCE_DMA,
120 },
121 [2] = {
122 .start = DMACH_I2S1_RX,
123 .end = DMACH_I2S1_RX,
124 .flags = IORESOURCE_DMA,
125 },
126};
127
128struct platform_device exynos4_device_i2s1 = {
129 .name = "samsung-i2s",
130 .id = 1,
131 .num_resources = ARRAY_SIZE(exynos4_i2s1_resource),
132 .resource = exynos4_i2s1_resource,
133 .dev = {
134 .platform_data = &i2sv3_pdata,
135 },
136};
137
138static struct resource exynos4_i2s2_resource[] = {
139 [0] = {
140 .start = EXYNOS4_PA_I2S2,
141 .end = EXYNOS4_PA_I2S2 + 0x100 - 1,
142 .flags = IORESOURCE_MEM,
143 },
144 [1] = {
145 .start = DMACH_I2S2_TX,
146 .end = DMACH_I2S2_TX,
147 .flags = IORESOURCE_DMA,
148 },
149 [2] = {
150 .start = DMACH_I2S2_RX,
151 .end = DMACH_I2S2_RX,
152 .flags = IORESOURCE_DMA,
153 },
154};
155
156struct platform_device exynos4_device_i2s2 = {
157 .name = "samsung-i2s",
158 .id = 2,
159 .num_resources = ARRAY_SIZE(exynos4_i2s2_resource),
160 .resource = exynos4_i2s2_resource,
161 .dev = {
162 .platform_data = &i2sv3_pdata,
163 },
164};
165
166/* PCM Controller platform_devices */
167
168static int exynos4_pcm_cfg_gpio(struct platform_device *pdev)
169{
170 switch (pdev->id) {
171 case 0:
172 s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 5, S3C_GPIO_SFN(3));
173 break;
174 case 1:
175 s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(3));
176 break;
177 case 2:
178 s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(3));
179 break;
180 default:
181 printk(KERN_DEBUG "Invalid PCM Controller number!");
182 return -EINVAL;
183 }
184
185 return 0;
186}
187
188static struct s3c_audio_pdata s3c_pcm_pdata = {
189 .cfg_gpio = exynos4_pcm_cfg_gpio,
190};
191
192static struct resource exynos4_pcm0_resource[] = {
193 [0] = {
194 .start = EXYNOS4_PA_PCM0,
195 .end = EXYNOS4_PA_PCM0 + 0x100 - 1,
196 .flags = IORESOURCE_MEM,
197 },
198 [1] = {
199 .start = DMACH_PCM0_TX,
200 .end = DMACH_PCM0_TX,
201 .flags = IORESOURCE_DMA,
202 },
203 [2] = {
204 .start = DMACH_PCM0_RX,
205 .end = DMACH_PCM0_RX,
206 .flags = IORESOURCE_DMA,
207 },
208};
209
210struct platform_device exynos4_device_pcm0 = {
211 .name = "samsung-pcm",
212 .id = 0,
213 .num_resources = ARRAY_SIZE(exynos4_pcm0_resource),
214 .resource = exynos4_pcm0_resource,
215 .dev = {
216 .platform_data = &s3c_pcm_pdata,
217 },
218};
219
220static struct resource exynos4_pcm1_resource[] = {
221 [0] = {
222 .start = EXYNOS4_PA_PCM1,
223 .end = EXYNOS4_PA_PCM1 + 0x100 - 1,
224 .flags = IORESOURCE_MEM,
225 },
226 [1] = {
227 .start = DMACH_PCM1_TX,
228 .end = DMACH_PCM1_TX,
229 .flags = IORESOURCE_DMA,
230 },
231 [2] = {
232 .start = DMACH_PCM1_RX,
233 .end = DMACH_PCM1_RX,
234 .flags = IORESOURCE_DMA,
235 },
236};
237
238struct platform_device exynos4_device_pcm1 = {
239 .name = "samsung-pcm",
240 .id = 1,
241 .num_resources = ARRAY_SIZE(exynos4_pcm1_resource),
242 .resource = exynos4_pcm1_resource,
243 .dev = {
244 .platform_data = &s3c_pcm_pdata,
245 },
246};
247
248static struct resource exynos4_pcm2_resource[] = {
249 [0] = {
250 .start = EXYNOS4_PA_PCM2,
251 .end = EXYNOS4_PA_PCM2 + 0x100 - 1,
252 .flags = IORESOURCE_MEM,
253 },
254 [1] = {
255 .start = DMACH_PCM2_TX,
256 .end = DMACH_PCM2_TX,
257 .flags = IORESOURCE_DMA,
258 },
259 [2] = {
260 .start = DMACH_PCM2_RX,
261 .end = DMACH_PCM2_RX,
262 .flags = IORESOURCE_DMA,
263 },
264};
265
266struct platform_device exynos4_device_pcm2 = {
267 .name = "samsung-pcm",
268 .id = 2,
269 .num_resources = ARRAY_SIZE(exynos4_pcm2_resource),
270 .resource = exynos4_pcm2_resource,
271 .dev = {
272 .platform_data = &s3c_pcm_pdata,
273 },
274};
275
276/* AC97 Controller platform devices */
277
278static int exynos4_ac97_cfg_gpio(struct platform_device *pdev)
279{
280 return s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(4));
281}
282
283static struct resource exynos4_ac97_resource[] = {
284 [0] = {
285 .start = EXYNOS4_PA_AC97,
286 .end = EXYNOS4_PA_AC97 + 0x100 - 1,
287 .flags = IORESOURCE_MEM,
288 },
289 [1] = {
290 .start = DMACH_AC97_PCMOUT,
291 .end = DMACH_AC97_PCMOUT,
292 .flags = IORESOURCE_DMA,
293 },
294 [2] = {
295 .start = DMACH_AC97_PCMIN,
296 .end = DMACH_AC97_PCMIN,
297 .flags = IORESOURCE_DMA,
298 },
299 [3] = {
300 .start = DMACH_AC97_MICIN,
301 .end = DMACH_AC97_MICIN,
302 .flags = IORESOURCE_DMA,
303 },
304 [4] = {
305 .start = IRQ_AC97,
306 .end = IRQ_AC97,
307 .flags = IORESOURCE_IRQ,
308 },
309};
310
311static struct s3c_audio_pdata s3c_ac97_pdata = {
312 .cfg_gpio = exynos4_ac97_cfg_gpio,
313};
314
315static u64 exynos4_ac97_dmamask = DMA_BIT_MASK(32);
316
317struct platform_device exynos4_device_ac97 = {
318 .name = "samsung-ac97",
319 .id = -1,
320 .num_resources = ARRAY_SIZE(exynos4_ac97_resource),
321 .resource = exynos4_ac97_resource,
322 .dev = {
323 .platform_data = &s3c_ac97_pdata,
324 .dma_mask = &exynos4_ac97_dmamask,
325 .coherent_dma_mask = DMA_BIT_MASK(32),
326 },
327};
328
329/* S/PDIF Controller platform_device */
330
331static int exynos4_spdif_cfg_gpio(struct platform_device *pdev)
332{
333 s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(3));
334
335 return 0;
336}
337
338static struct resource exynos4_spdif_resource[] = {
339 [0] = {
340 .start = EXYNOS4_PA_SPDIF,
341 .end = EXYNOS4_PA_SPDIF + 0x100 - 1,
342 .flags = IORESOURCE_MEM,
343 },
344 [1] = {
345 .start = DMACH_SPDIF,
346 .end = DMACH_SPDIF,
347 .flags = IORESOURCE_DMA,
348 },
349};
350
351static struct s3c_audio_pdata samsung_spdif_pdata = {
352 .cfg_gpio = exynos4_spdif_cfg_gpio,
353};
354
355static u64 exynos4_spdif_dmamask = DMA_BIT_MASK(32);
356
357struct platform_device exynos4_device_spdif = {
358 .name = "samsung-spdif",
359 .id = -1,
360 .num_resources = ARRAY_SIZE(exynos4_spdif_resource),
361 .resource = exynos4_spdif_resource,
362 .dev = {
363 .platform_data = &samsung_spdif_pdata,
364 .dma_mask = &exynos4_spdif_dmamask,
365 .coherent_dma_mask = DMA_BIT_MASK(32),
366 },
367};
diff --git a/arch/arm/mach-exynos4/dev-pd.c b/arch/arm/mach-exynos4/dev-pd.c
new file mode 100644
index 000000000000..3273f25d6a75
--- /dev/null
+++ b/arch/arm/mach-exynos4/dev-pd.c
@@ -0,0 +1,139 @@
1/* linux/arch/arm/mach-exynos4/dev-pd.c
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - Power Domain support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/io.h>
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
16#include <linux/delay.h>
17
18#include <mach/regs-pmu.h>
19
20#include <plat/pd.h>
21
22static int exynos4_pd_enable(struct device *dev)
23{
24 struct samsung_pd_info *pdata = dev->platform_data;
25 u32 timeout;
26
27 __raw_writel(S5P_INT_LOCAL_PWR_EN, pdata->base);
28
29 /* Wait max 1ms */
30 timeout = 10;
31 while ((__raw_readl(pdata->base + 0x4) & S5P_INT_LOCAL_PWR_EN)
32 != S5P_INT_LOCAL_PWR_EN) {
33 if (timeout == 0) {
34 printk(KERN_ERR "Power domain %s enable failed.\n",
35 dev_name(dev));
36 return -ETIMEDOUT;
37 }
38 timeout--;
39 udelay(100);
40 }
41
42 return 0;
43}
44
45static int exynos4_pd_disable(struct device *dev)
46{
47 struct samsung_pd_info *pdata = dev->platform_data;
48 u32 timeout;
49
50 __raw_writel(0, pdata->base);
51
52 /* Wait max 1ms */
53 timeout = 10;
54 while (__raw_readl(pdata->base + 0x4) & S5P_INT_LOCAL_PWR_EN) {
55 if (timeout == 0) {
56 printk(KERN_ERR "Power domain %s disable failed.\n",
57 dev_name(dev));
58 return -ETIMEDOUT;
59 }
60 timeout--;
61 udelay(100);
62 }
63
64 return 0;
65}
66
67struct platform_device exynos4_device_pd[] = {
68 {
69 .name = "samsung-pd",
70 .id = 0,
71 .dev = {
72 .platform_data = &(struct samsung_pd_info) {
73 .enable = exynos4_pd_enable,
74 .disable = exynos4_pd_disable,
75 .base = S5P_PMU_MFC_CONF,
76 },
77 },
78 }, {
79 .name = "samsung-pd",
80 .id = 1,
81 .dev = {
82 .platform_data = &(struct samsung_pd_info) {
83 .enable = exynos4_pd_enable,
84 .disable = exynos4_pd_disable,
85 .base = S5P_PMU_G3D_CONF,
86 },
87 },
88 }, {
89 .name = "samsung-pd",
90 .id = 2,
91 .dev = {
92 .platform_data = &(struct samsung_pd_info) {
93 .enable = exynos4_pd_enable,
94 .disable = exynos4_pd_disable,
95 .base = S5P_PMU_LCD0_CONF,
96 },
97 },
98 }, {
99 .name = "samsung-pd",
100 .id = 3,
101 .dev = {
102 .platform_data = &(struct samsung_pd_info) {
103 .enable = exynos4_pd_enable,
104 .disable = exynos4_pd_disable,
105 .base = S5P_PMU_LCD1_CONF,
106 },
107 },
108 }, {
109 .name = "samsung-pd",
110 .id = 4,
111 .dev = {
112 .platform_data = &(struct samsung_pd_info) {
113 .enable = exynos4_pd_enable,
114 .disable = exynos4_pd_disable,
115 .base = S5P_PMU_TV_CONF,
116 },
117 },
118 }, {
119 .name = "samsung-pd",
120 .id = 5,
121 .dev = {
122 .platform_data = &(struct samsung_pd_info) {
123 .enable = exynos4_pd_enable,
124 .disable = exynos4_pd_disable,
125 .base = S5P_PMU_CAM_CONF,
126 },
127 },
128 }, {
129 .name = "samsung-pd",
130 .id = 6,
131 .dev = {
132 .platform_data = &(struct samsung_pd_info) {
133 .enable = exynos4_pd_enable,
134 .disable = exynos4_pd_disable,
135 .base = S5P_PMU_GPS_CONF,
136 },
137 },
138 },
139};
diff --git a/arch/arm/mach-exynos4/dev-sysmmu.c b/arch/arm/mach-exynos4/dev-sysmmu.c
new file mode 100644
index 000000000000..a10790a614ec
--- /dev/null
+++ b/arch/arm/mach-exynos4/dev-sysmmu.c
@@ -0,0 +1,189 @@
1/* linux/arch/arm/mach-exynos4/dev-sysmmu.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - System MMU support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/platform_device.h>
14#include <linux/dma-mapping.h>
15
16#include <mach/map.h>
17#include <mach/irqs.h>
18
19static struct resource exynos4_sysmmu_resource[] = {
20 [0] = {
21 .start = EXYNOS4_PA_SYSMMU_MDMA,
22 .end = EXYNOS4_PA_SYSMMU_MDMA + SZ_64K - 1,
23 .flags = IORESOURCE_MEM,
24 },
25 [1] = {
26 .start = IRQ_SYSMMU_MDMA0_0,
27 .end = IRQ_SYSMMU_MDMA0_0,
28 .flags = IORESOURCE_IRQ,
29 },
30 [2] = {
31 .start = EXYNOS4_PA_SYSMMU_SSS,
32 .end = EXYNOS4_PA_SYSMMU_SSS + SZ_64K - 1,
33 .flags = IORESOURCE_MEM,
34 },
35 [3] = {
36 .start = IRQ_SYSMMU_SSS_0,
37 .end = IRQ_SYSMMU_SSS_0,
38 .flags = IORESOURCE_IRQ,
39 },
40 [4] = {
41 .start = EXYNOS4_PA_SYSMMU_FIMC0,
42 .end = EXYNOS4_PA_SYSMMU_FIMC0 + SZ_64K - 1,
43 .flags = IORESOURCE_MEM,
44 },
45 [5] = {
46 .start = IRQ_SYSMMU_FIMC0_0,
47 .end = IRQ_SYSMMU_FIMC0_0,
48 .flags = IORESOURCE_IRQ,
49 },
50 [6] = {
51 .start = EXYNOS4_PA_SYSMMU_FIMC1,
52 .end = EXYNOS4_PA_SYSMMU_FIMC1 + SZ_64K - 1,
53 .flags = IORESOURCE_MEM,
54 },
55 [7] = {
56 .start = IRQ_SYSMMU_FIMC1_0,
57 .end = IRQ_SYSMMU_FIMC1_0,
58 .flags = IORESOURCE_IRQ,
59 },
60 [8] = {
61 .start = EXYNOS4_PA_SYSMMU_FIMC2,
62 .end = EXYNOS4_PA_SYSMMU_FIMC2 + SZ_64K - 1,
63 .flags = IORESOURCE_MEM,
64 },
65 [9] = {
66 .start = IRQ_SYSMMU_FIMC2_0,
67 .end = IRQ_SYSMMU_FIMC2_0,
68 .flags = IORESOURCE_IRQ,
69 },
70 [10] = {
71 .start = EXYNOS4_PA_SYSMMU_FIMC3,
72 .end = EXYNOS4_PA_SYSMMU_FIMC3 + SZ_64K - 1,
73 .flags = IORESOURCE_MEM,
74 },
75 [11] = {
76 .start = IRQ_SYSMMU_FIMC3_0,
77 .end = IRQ_SYSMMU_FIMC3_0,
78 .flags = IORESOURCE_IRQ,
79 },
80 [12] = {
81 .start = EXYNOS4_PA_SYSMMU_JPEG,
82 .end = EXYNOS4_PA_SYSMMU_JPEG + SZ_64K - 1,
83 .flags = IORESOURCE_MEM,
84 },
85 [13] = {
86 .start = IRQ_SYSMMU_JPEG_0,
87 .end = IRQ_SYSMMU_JPEG_0,
88 .flags = IORESOURCE_IRQ,
89 },
90 [14] = {
91 .start = EXYNOS4_PA_SYSMMU_FIMD0,
92 .end = EXYNOS4_PA_SYSMMU_FIMD0 + SZ_64K - 1,
93 .flags = IORESOURCE_MEM,
94 },
95 [15] = {
96 .start = IRQ_SYSMMU_LCD0_M0_0,
97 .end = IRQ_SYSMMU_LCD0_M0_0,
98 .flags = IORESOURCE_IRQ,
99 },
100 [16] = {
101 .start = EXYNOS4_PA_SYSMMU_FIMD1,
102 .end = EXYNOS4_PA_SYSMMU_FIMD1 + SZ_64K - 1,
103 .flags = IORESOURCE_MEM,
104 },
105 [17] = {
106 .start = IRQ_SYSMMU_LCD1_M1_0,
107 .end = IRQ_SYSMMU_LCD1_M1_0,
108 .flags = IORESOURCE_IRQ,
109 },
110 [18] = {
111 .start = EXYNOS4_PA_SYSMMU_PCIe,
112 .end = EXYNOS4_PA_SYSMMU_PCIe + SZ_64K - 1,
113 .flags = IORESOURCE_MEM,
114 },
115 [19] = {
116 .start = IRQ_SYSMMU_PCIE_0,
117 .end = IRQ_SYSMMU_PCIE_0,
118 .flags = IORESOURCE_IRQ,
119 },
120 [20] = {
121 .start = EXYNOS4_PA_SYSMMU_G2D,
122 .end = EXYNOS4_PA_SYSMMU_G2D + SZ_64K - 1,
123 .flags = IORESOURCE_MEM,
124 },
125 [21] = {
126 .start = IRQ_SYSMMU_2D_0,
127 .end = IRQ_SYSMMU_2D_0,
128 .flags = IORESOURCE_IRQ,
129 },
130 [22] = {
131 .start = EXYNOS4_PA_SYSMMU_ROTATOR,
132 .end = EXYNOS4_PA_SYSMMU_ROTATOR + SZ_64K - 1,
133 .flags = IORESOURCE_MEM,
134 },
135 [23] = {
136 .start = IRQ_SYSMMU_ROTATOR_0,
137 .end = IRQ_SYSMMU_ROTATOR_0,
138 .flags = IORESOURCE_IRQ,
139 },
140 [24] = {
141 .start = EXYNOS4_PA_SYSMMU_MDMA2,
142 .end = EXYNOS4_PA_SYSMMU_MDMA2 + SZ_64K - 1,
143 .flags = IORESOURCE_MEM,
144 },
145 [25] = {
146 .start = IRQ_SYSMMU_MDMA1_0,
147 .end = IRQ_SYSMMU_MDMA1_0,
148 .flags = IORESOURCE_IRQ,
149 },
150 [26] = {
151 .start = EXYNOS4_PA_SYSMMU_TV,
152 .end = EXYNOS4_PA_SYSMMU_TV + SZ_64K - 1,
153 .flags = IORESOURCE_MEM,
154 },
155 [27] = {
156 .start = IRQ_SYSMMU_TV_M0_0,
157 .end = IRQ_SYSMMU_TV_M0_0,
158 .flags = IORESOURCE_IRQ,
159 },
160 [28] = {
161 .start = EXYNOS4_PA_SYSMMU_MFC_L,
162 .end = EXYNOS4_PA_SYSMMU_MFC_L + SZ_64K - 1,
163 .flags = IORESOURCE_MEM,
164 },
165 [29] = {
166 .start = IRQ_SYSMMU_MFC_M0_0,
167 .end = IRQ_SYSMMU_MFC_M0_0,
168 .flags = IORESOURCE_IRQ,
169 },
170 [30] = {
171 .start = EXYNOS4_PA_SYSMMU_MFC_R,
172 .end = EXYNOS4_PA_SYSMMU_MFC_R + SZ_64K - 1,
173 .flags = IORESOURCE_MEM,
174 },
175 [31] = {
176 .start = IRQ_SYSMMU_MFC_M1_0,
177 .end = IRQ_SYSMMU_MFC_M1_0,
178 .flags = IORESOURCE_IRQ,
179 },
180};
181
182struct platform_device exynos4_device_sysmmu = {
183 .name = "s5p-sysmmu",
184 .id = 32,
185 .num_resources = ARRAY_SIZE(exynos4_sysmmu_resource),
186 .resource = exynos4_sysmmu_resource,
187};
188
189EXPORT_SYMBOL(exynos4_device_sysmmu);
diff --git a/arch/arm/mach-exynos4/setup-i2c1.c b/arch/arm/mach-exynos4/setup-i2c1.c
new file mode 100644
index 000000000000..fd7235a43f6e
--- /dev/null
+++ b/arch/arm/mach-exynos4/setup-i2c1.c
@@ -0,0 +1,23 @@
1/*
2 * linux/arch/arm/mach-exynos4/setup-i2c1.c
3 *
4 * Copyright (C) 2010 Samsung Electronics Co., Ltd.
5 *
6 * I2C1 GPIO configuration.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13struct platform_device; /* don't need the contents */
14
15#include <linux/gpio.h>
16#include <plat/iic.h>
17#include <plat/gpio-cfg.h>
18
19void s3c_i2c1_cfg_gpio(struct platform_device *dev)
20{
21 s3c_gpio_cfgall_range(EXYNOS4_GPD1(2), 2,
22 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
23}
diff --git a/arch/arm/mach-exynos4/setup-i2c2.c b/arch/arm/mach-exynos4/setup-i2c2.c
new file mode 100644
index 000000000000..2694b19e8b37
--- /dev/null
+++ b/arch/arm/mach-exynos4/setup-i2c2.c
@@ -0,0 +1,23 @@
1/*
2 * linux/arch/arm/mach-exynos4/setup-i2c2.c
3 *
4 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
5 *
6 * I2C2 GPIO configuration.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13struct platform_device; /* don't need the contents */
14
15#include <linux/gpio.h>
16#include <plat/iic.h>
17#include <plat/gpio-cfg.h>
18
19void s3c_i2c2_cfg_gpio(struct platform_device *dev)
20{
21 s3c_gpio_cfgall_range(EXYNOS4_GPA0(6), 2,
22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
23}
diff --git a/arch/arm/mach-exynos4/setup-i2c3.c b/arch/arm/mach-exynos4/setup-i2c3.c
new file mode 100644
index 000000000000..379bd306993f
--- /dev/null
+++ b/arch/arm/mach-exynos4/setup-i2c3.c
@@ -0,0 +1,23 @@
1/*
2 * linux/arch/arm/mach-exynos4/setup-i2c3.c
3 *
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
5 *
6 * I2C3 GPIO configuration.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13struct platform_device; /* don't need the contents */
14
15#include <linux/gpio.h>
16#include <plat/iic.h>
17#include <plat/gpio-cfg.h>
18
19void s3c_i2c3_cfg_gpio(struct platform_device *dev)
20{
21 s3c_gpio_cfgall_range(EXYNOS4_GPA1(2), 2,
22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
23}
diff --git a/arch/arm/mach-exynos4/setup-i2c4.c b/arch/arm/mach-exynos4/setup-i2c4.c
new file mode 100644
index 000000000000..9f3c04855b76
--- /dev/null
+++ b/arch/arm/mach-exynos4/setup-i2c4.c
@@ -0,0 +1,23 @@
1/*
2 * linux/arch/arm/mach-exynos4/setup-i2c4.c
3 *
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
5 *
6 * I2C4 GPIO configuration.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13struct platform_device; /* don't need the contents */
14
15#include <linux/gpio.h>
16#include <plat/iic.h>
17#include <plat/gpio-cfg.h>
18
19void s3c_i2c4_cfg_gpio(struct platform_device *dev)
20{
21 s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2,
22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
23}
diff --git a/arch/arm/mach-exynos4/setup-i2c5.c b/arch/arm/mach-exynos4/setup-i2c5.c
new file mode 100644
index 000000000000..77e1a1e57c76
--- /dev/null
+++ b/arch/arm/mach-exynos4/setup-i2c5.c
@@ -0,0 +1,23 @@
1/*
2 * linux/arch/arm/mach-exynos4/setup-i2c5.c
3 *
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
5 *
6 * I2C5 GPIO configuration.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13struct platform_device; /* don't need the contents */
14
15#include <linux/gpio.h>
16#include <plat/iic.h>
17#include <plat/gpio-cfg.h>
18
19void s3c_i2c5_cfg_gpio(struct platform_device *dev)
20{
21 s3c_gpio_cfgall_range(EXYNOS4_GPB(6), 2,
22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
23}
diff --git a/arch/arm/mach-exynos4/setup-i2c6.c b/arch/arm/mach-exynos4/setup-i2c6.c
new file mode 100644
index 000000000000..284d12b7af0e
--- /dev/null
+++ b/arch/arm/mach-exynos4/setup-i2c6.c
@@ -0,0 +1,23 @@
1/*
2 * linux/arch/arm/mach-exynos4/setup-i2c6.c
3 *
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
5 *
6 * I2C6 GPIO configuration.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13struct platform_device; /* don't need the contents */
14
15#include <linux/gpio.h>
16#include <plat/iic.h>
17#include <plat/gpio-cfg.h>
18
19void s3c_i2c6_cfg_gpio(struct platform_device *dev)
20{
21 s3c_gpio_cfgall_range(EXYNOS4_GPC1(3), 2,
22 S3C_GPIO_SFN(4), S3C_GPIO_PULL_UP);
23}
diff --git a/arch/arm/mach-exynos4/setup-i2c7.c b/arch/arm/mach-exynos4/setup-i2c7.c
new file mode 100644
index 000000000000..b7611ee359a2
--- /dev/null
+++ b/arch/arm/mach-exynos4/setup-i2c7.c
@@ -0,0 +1,23 @@
1/*
2 * linux/arch/arm/mach-exynos4/setup-i2c7.c
3 *
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
5 *
6 * I2C7 GPIO configuration.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13struct platform_device; /* don't need the contents */
14
15#include <linux/gpio.h>
16#include <plat/iic.h>
17#include <plat/gpio-cfg.h>
18
19void s3c_i2c7_cfg_gpio(struct platform_device *dev)
20{
21 s3c_gpio_cfgall_range(EXYNOS4_GPD0(2), 2,
22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
23}
diff --git a/arch/arm/mach-exynos4/setup-sdhci-gpio.c b/arch/arm/mach-exynos4/setup-sdhci-gpio.c
new file mode 100644
index 000000000000..1b3d3a2de95c
--- /dev/null
+++ b/arch/arm/mach-exynos4/setup-sdhci-gpio.c
@@ -0,0 +1,152 @@
1/* linux/arch/arm/mach-exynos4/setup-sdhci-gpio.c
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/platform_device.h>
17#include <linux/io.h>
18#include <linux/gpio.h>
19#include <linux/mmc/host.h>
20#include <linux/mmc/card.h>
21
22#include <plat/gpio-cfg.h>
23#include <plat/regs-sdhci.h>
24#include <plat/sdhci.h>
25
26void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
27{
28 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
29 unsigned int gpio;
30
31 /* Set all the necessary GPK0[0:1] pins to special-function 2 */
32 for (gpio = EXYNOS4_GPK0(0); gpio < EXYNOS4_GPK0(2); gpio++) {
33 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
34 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
35 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
36 }
37
38 switch (width) {
39 case 8:
40 for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) {
41 /* Data pin GPK1[3:6] to special-funtion 3 */
42 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
43 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
44 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
45 }
46 case 4:
47 for (gpio = EXYNOS4_GPK0(3); gpio <= EXYNOS4_GPK0(6); gpio++) {
48 /* Data pin GPK0[3:6] to special-funtion 2 */
49 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
50 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
51 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
52 }
53 default:
54 break;
55 }
56
57 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
58 s3c_gpio_cfgpin(EXYNOS4_GPK0(2), S3C_GPIO_SFN(2));
59 s3c_gpio_setpull(EXYNOS4_GPK0(2), S3C_GPIO_PULL_UP);
60 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
61 }
62}
63
64void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
65{
66 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
67 unsigned int gpio;
68
69 /* Set all the necessary GPK1[0:1] pins to special-function 2 */
70 for (gpio = EXYNOS4_GPK1(0); gpio < EXYNOS4_GPK1(2); gpio++) {
71 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
72 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
73 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
74 }
75
76 for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) {
77 /* Data pin GPK1[3:6] to special-function 2 */
78 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
79 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
80 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
81 }
82
83 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
84 s3c_gpio_cfgpin(EXYNOS4_GPK1(2), S3C_GPIO_SFN(2));
85 s3c_gpio_setpull(EXYNOS4_GPK1(2), S3C_GPIO_PULL_UP);
86 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
87 }
88}
89
90void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
91{
92 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
93 unsigned int gpio;
94
95 /* Set all the necessary GPK2[0:1] pins to special-function 2 */
96 for (gpio = EXYNOS4_GPK2(0); gpio < EXYNOS4_GPK2(2); gpio++) {
97 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
98 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
99 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
100 }
101
102 switch (width) {
103 case 8:
104 for (gpio = EXYNOS4_GPK3(3); gpio <= EXYNOS4_GPK3(6); gpio++) {
105 /* Data pin GPK3[3:6] to special-function 3 */
106 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
107 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
108 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
109 }
110 case 4:
111 for (gpio = EXYNOS4_GPK2(3); gpio <= EXYNOS4_GPK2(6); gpio++) {
112 /* Data pin GPK2[3:6] to special-function 2 */
113 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
114 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
115 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
116 }
117 default:
118 break;
119 }
120
121 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
122 s3c_gpio_cfgpin(EXYNOS4_GPK2(2), S3C_GPIO_SFN(2));
123 s3c_gpio_setpull(EXYNOS4_GPK2(2), S3C_GPIO_PULL_UP);
124 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
125 }
126}
127
128void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
129{
130 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
131 unsigned int gpio;
132
133 /* Set all the necessary GPK3[0:1] pins to special-function 2 */
134 for (gpio = EXYNOS4_GPK3(0); gpio < EXYNOS4_GPK3(2); gpio++) {
135 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
136 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
137 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
138 }
139
140 for (gpio = EXYNOS4_GPK3(3); gpio <= EXYNOS4_GPK3(6); gpio++) {
141 /* Data pin GPK3[3:6] to special-function 2 */
142 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
143 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
144 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
145 }
146
147 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
148 s3c_gpio_cfgpin(EXYNOS4_GPK3(2), S3C_GPIO_SFN(2));
149 s3c_gpio_setpull(EXYNOS4_GPK3(2), S3C_GPIO_PULL_UP);
150 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
151 }
152}
diff --git a/arch/arm/mach-exynos4/setup-sdhci.c b/arch/arm/mach-exynos4/setup-sdhci.c
new file mode 100644
index 000000000000..85f9433d4836
--- /dev/null
+++ b/arch/arm/mach-exynos4/setup-sdhci.c
@@ -0,0 +1,69 @@
1/* linux/arch/arm/mach-exynos4/setup-sdhci.c
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - Helper functions for settign up SDHCI device(s) (HSMMC)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/platform_device.h>
17#include <linux/io.h>
18
19#include <linux/mmc/card.h>
20#include <linux/mmc/host.h>
21
22#include <plat/regs-sdhci.h>
23
24/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
25
26char *exynos4_hsmmc_clksrcs[4] = {
27 [0] = NULL,
28 [1] = NULL,
29 [2] = "sclk_mmc", /* mmc_bus */
30 [3] = NULL,
31};
32
33void exynos4_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r,
34 struct mmc_ios *ios, struct mmc_card *card)
35{
36 u32 ctrl2, ctrl3;
37
38 /* don't need to alter anything acording to card-type */
39
40 ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
41
42 /* select base clock source to HCLK */
43
44 ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
45
46 /*
47 * clear async mode, enable conflict mask, rx feedback ctrl, SD
48 * clk hold and no use debounce count
49 */
50
51 ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
52 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
53 S3C_SDHCI_CTRL2_ENFBCLKRX |
54 S3C_SDHCI_CTRL2_DFCNT_NONE |
55 S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
56
57 /* Tx and Rx feedback clock delay control */
58
59 if (ios->clock < 25 * 1000000)
60 ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
61 S3C_SDHCI_CTRL3_FCSEL2 |
62 S3C_SDHCI_CTRL3_FCSEL1 |
63 S3C_SDHCI_CTRL3_FCSEL0);
64 else
65 ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
66
67 writel(ctrl2, r + S3C_SDHCI_CONTROL2);
68 writel(ctrl3, r + S3C_SDHCI_CONTROL3);
69}
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-27 23:18:26 -0400