From 3db3ae5eb94eb8579991174fe66999261b66018d Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Mon, 14 Feb 2011 16:22:36 +0900 Subject: ARM: EXYNOS4: Update device support This patch updates device support of EXYNOS4 according to the change of ARCH name, EXYNOS4. Cc: Ben Dooks Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos4/dev-audio.c | 367 +++++++++++++++++++++++++++++++ arch/arm/mach-exynos4/dev-pd.c | 139 ++++++++++++ arch/arm/mach-exynos4/dev-sysmmu.c | 189 ++++++++++++++++ arch/arm/mach-exynos4/setup-i2c1.c | 23 ++ arch/arm/mach-exynos4/setup-i2c2.c | 23 ++ arch/arm/mach-exynos4/setup-i2c3.c | 23 ++ arch/arm/mach-exynos4/setup-i2c4.c | 23 ++ arch/arm/mach-exynos4/setup-i2c5.c | 23 ++ arch/arm/mach-exynos4/setup-i2c6.c | 23 ++ arch/arm/mach-exynos4/setup-i2c7.c | 23 ++ arch/arm/mach-exynos4/setup-sdhci-gpio.c | 152 +++++++++++++ arch/arm/mach-exynos4/setup-sdhci.c | 69 ++++++ 12 files changed, 1077 insertions(+) create mode 100644 arch/arm/mach-exynos4/dev-audio.c create mode 100644 arch/arm/mach-exynos4/dev-pd.c create mode 100644 arch/arm/mach-exynos4/dev-sysmmu.c create mode 100644 arch/arm/mach-exynos4/setup-i2c1.c create mode 100644 arch/arm/mach-exynos4/setup-i2c2.c create mode 100644 arch/arm/mach-exynos4/setup-i2c3.c create mode 100644 arch/arm/mach-exynos4/setup-i2c4.c create mode 100644 arch/arm/mach-exynos4/setup-i2c5.c create mode 100644 arch/arm/mach-exynos4/setup-i2c6.c create mode 100644 arch/arm/mach-exynos4/setup-i2c7.c create mode 100644 arch/arm/mach-exynos4/setup-sdhci-gpio.c create mode 100644 arch/arm/mach-exynos4/setup-sdhci.c (limited to 'arch/arm/mach-exynos4') diff --git a/arch/arm/mach-exynos4/dev-audio.c b/arch/arm/mach-exynos4/dev-audio.c new file mode 100644 index 000000000000..1eed5f9f7bd3 --- /dev/null +++ b/arch/arm/mach-exynos4/dev-audio.c @@ -0,0 +1,367 @@ +/* linux/arch/arm/mach-exynos4/dev-audio.c + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Copyright (c) 2010 Samsung Electronics Co. Ltd + * Jaswinder Singh + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include + +#include +#include + +#include +#include +#include + +static const char *rclksrc[] = { + [0] = "busclk", + [1] = "i2sclk", +}; + +static int exynos4_cfg_i2s(struct platform_device *pdev) +{ + /* configure GPIO for i2s port */ + switch (pdev->id) { + case 0: + s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 7, S3C_GPIO_SFN(2)); + break; + case 1: + s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(2)); + break; + case 2: + s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(4)); + break; + default: + printk(KERN_ERR "Invalid Device %d\n", pdev->id); + return -EINVAL; + } + + return 0; +} + +static struct s3c_audio_pdata i2sv5_pdata = { + .cfg_gpio = exynos4_cfg_i2s, + .type = { + .i2s = { + .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI + | QUIRK_NEED_RSTCLR, + .src_clk = rclksrc, + }, + }, +}; + +static struct resource exynos4_i2s0_resource[] = { + [0] = { + .start = EXYNOS4_PA_I2S0, + .end = EXYNOS4_PA_I2S0 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_I2S0_TX, + .end = DMACH_I2S0_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_I2S0_RX, + .end = DMACH_I2S0_RX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = DMACH_I2S0S_TX, + .end = DMACH_I2S0S_TX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device exynos4_device_i2s0 = { + .name = "samsung-i2s", + .id = 0, + .num_resources = ARRAY_SIZE(exynos4_i2s0_resource), + .resource = exynos4_i2s0_resource, + .dev = { + .platform_data = &i2sv5_pdata, + }, +}; + +static const char *rclksrc_v3[] = { + [0] = "sclk_i2s", + [1] = "no_such_clock", +}; + +static struct s3c_audio_pdata i2sv3_pdata = { + .cfg_gpio = exynos4_cfg_i2s, + .type = { + .i2s = { + .quirks = QUIRK_NO_MUXPSR, + .src_clk = rclksrc_v3, + }, + }, +}; + +static struct resource exynos4_i2s1_resource[] = { + [0] = { + .start = EXYNOS4_PA_I2S1, + .end = EXYNOS4_PA_I2S1 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_I2S1_TX, + .end = DMACH_I2S1_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_I2S1_RX, + .end = DMACH_I2S1_RX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device exynos4_device_i2s1 = { + .name = "samsung-i2s", + .id = 1, + .num_resources = ARRAY_SIZE(exynos4_i2s1_resource), + .resource = exynos4_i2s1_resource, + .dev = { + .platform_data = &i2sv3_pdata, + }, +}; + +static struct resource exynos4_i2s2_resource[] = { + [0] = { + .start = EXYNOS4_PA_I2S2, + .end = EXYNOS4_PA_I2S2 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_I2S2_TX, + .end = DMACH_I2S2_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_I2S2_RX, + .end = DMACH_I2S2_RX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device exynos4_device_i2s2 = { + .name = "samsung-i2s", + .id = 2, + .num_resources = ARRAY_SIZE(exynos4_i2s2_resource), + .resource = exynos4_i2s2_resource, + .dev = { + .platform_data = &i2sv3_pdata, + }, +}; + +/* PCM Controller platform_devices */ + +static int exynos4_pcm_cfg_gpio(struct platform_device *pdev) +{ + switch (pdev->id) { + case 0: + s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 5, S3C_GPIO_SFN(3)); + break; + case 1: + s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(3)); + break; + case 2: + s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(3)); + break; + default: + printk(KERN_DEBUG "Invalid PCM Controller number!"); + return -EINVAL; + } + + return 0; +} + +static struct s3c_audio_pdata s3c_pcm_pdata = { + .cfg_gpio = exynos4_pcm_cfg_gpio, +}; + +static struct resource exynos4_pcm0_resource[] = { + [0] = { + .start = EXYNOS4_PA_PCM0, + .end = EXYNOS4_PA_PCM0 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_PCM0_TX, + .end = DMACH_PCM0_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_PCM0_RX, + .end = DMACH_PCM0_RX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device exynos4_device_pcm0 = { + .name = "samsung-pcm", + .id = 0, + .num_resources = ARRAY_SIZE(exynos4_pcm0_resource), + .resource = exynos4_pcm0_resource, + .dev = { + .platform_data = &s3c_pcm_pdata, + }, +}; + +static struct resource exynos4_pcm1_resource[] = { + [0] = { + .start = EXYNOS4_PA_PCM1, + .end = EXYNOS4_PA_PCM1 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_PCM1_TX, + .end = DMACH_PCM1_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_PCM1_RX, + .end = DMACH_PCM1_RX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device exynos4_device_pcm1 = { + .name = "samsung-pcm", + .id = 1, + .num_resources = ARRAY_SIZE(exynos4_pcm1_resource), + .resource = exynos4_pcm1_resource, + .dev = { + .platform_data = &s3c_pcm_pdata, + }, +}; + +static struct resource exynos4_pcm2_resource[] = { + [0] = { + .start = EXYNOS4_PA_PCM2, + .end = EXYNOS4_PA_PCM2 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_PCM2_TX, + .end = DMACH_PCM2_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_PCM2_RX, + .end = DMACH_PCM2_RX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device exynos4_device_pcm2 = { + .name = "samsung-pcm", + .id = 2, + .num_resources = ARRAY_SIZE(exynos4_pcm2_resource), + .resource = exynos4_pcm2_resource, + .dev = { + .platform_data = &s3c_pcm_pdata, + }, +}; + +/* AC97 Controller platform devices */ + +static int exynos4_ac97_cfg_gpio(struct platform_device *pdev) +{ + return s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(4)); +} + +static struct resource exynos4_ac97_resource[] = { + [0] = { + .start = EXYNOS4_PA_AC97, + .end = EXYNOS4_PA_AC97 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_AC97_PCMOUT, + .end = DMACH_AC97_PCMOUT, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_AC97_PCMIN, + .end = DMACH_AC97_PCMIN, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = DMACH_AC97_MICIN, + .end = DMACH_AC97_MICIN, + .flags = IORESOURCE_DMA, + }, + [4] = { + .start = IRQ_AC97, + .end = IRQ_AC97, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct s3c_audio_pdata s3c_ac97_pdata = { + .cfg_gpio = exynos4_ac97_cfg_gpio, +}; + +static u64 exynos4_ac97_dmamask = DMA_BIT_MASK(32); + +struct platform_device exynos4_device_ac97 = { + .name = "samsung-ac97", + .id = -1, + .num_resources = ARRAY_SIZE(exynos4_ac97_resource), + .resource = exynos4_ac97_resource, + .dev = { + .platform_data = &s3c_ac97_pdata, + .dma_mask = &exynos4_ac97_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +/* S/PDIF Controller platform_device */ + +static int exynos4_spdif_cfg_gpio(struct platform_device *pdev) +{ + s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(3)); + + return 0; +} + +static struct resource exynos4_spdif_resource[] = { + [0] = { + .start = EXYNOS4_PA_SPDIF, + .end = EXYNOS4_PA_SPDIF + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_SPDIF, + .end = DMACH_SPDIF, + .flags = IORESOURCE_DMA, + }, +}; + +static struct s3c_audio_pdata samsung_spdif_pdata = { + .cfg_gpio = exynos4_spdif_cfg_gpio, +}; + +static u64 exynos4_spdif_dmamask = DMA_BIT_MASK(32); + +struct platform_device exynos4_device_spdif = { + .name = "samsung-spdif", + .id = -1, + .num_resources = ARRAY_SIZE(exynos4_spdif_resource), + .resource = exynos4_spdif_resource, + .dev = { + .platform_data = &samsung_spdif_pdata, + .dma_mask = &exynos4_spdif_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; diff --git a/arch/arm/mach-exynos4/dev-pd.c b/arch/arm/mach-exynos4/dev-pd.c new file mode 100644 index 000000000000..3273f25d6a75 --- /dev/null +++ b/arch/arm/mach-exynos4/dev-pd.c @@ -0,0 +1,139 @@ +/* linux/arch/arm/mach-exynos4/dev-pd.c + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS4 - Power Domain support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include + +#include + +#include + +static int exynos4_pd_enable(struct device *dev) +{ + struct samsung_pd_info *pdata = dev->platform_data; + u32 timeout; + + __raw_writel(S5P_INT_LOCAL_PWR_EN, pdata->base); + + /* Wait max 1ms */ + timeout = 10; + while ((__raw_readl(pdata->base + 0x4) & S5P_INT_LOCAL_PWR_EN) + != S5P_INT_LOCAL_PWR_EN) { + if (timeout == 0) { + printk(KERN_ERR "Power domain %s enable failed.\n", + dev_name(dev)); + return -ETIMEDOUT; + } + timeout--; + udelay(100); + } + + return 0; +} + +static int exynos4_pd_disable(struct device *dev) +{ + struct samsung_pd_info *pdata = dev->platform_data; + u32 timeout; + + __raw_writel(0, pdata->base); + + /* Wait max 1ms */ + timeout = 10; + while (__raw_readl(pdata->base + 0x4) & S5P_INT_LOCAL_PWR_EN) { + if (timeout == 0) { + printk(KERN_ERR "Power domain %s disable failed.\n", + dev_name(dev)); + return -ETIMEDOUT; + } + timeout--; + udelay(100); + } + + return 0; +} + +struct platform_device exynos4_device_pd[] = { + { + .name = "samsung-pd", + .id = 0, + .dev = { + .platform_data = &(struct samsung_pd_info) { + .enable = exynos4_pd_enable, + .disable = exynos4_pd_disable, + .base = S5P_PMU_MFC_CONF, + }, + }, + }, { + .name = "samsung-pd", + .id = 1, + .dev = { + .platform_data = &(struct samsung_pd_info) { + .enable = exynos4_pd_enable, + .disable = exynos4_pd_disable, + .base = S5P_PMU_G3D_CONF, + }, + }, + }, { + .name = "samsung-pd", + .id = 2, + .dev = { + .platform_data = &(struct samsung_pd_info) { + .enable = exynos4_pd_enable, + .disable = exynos4_pd_disable, + .base = S5P_PMU_LCD0_CONF, + }, + }, + }, { + .name = "samsung-pd", + .id = 3, + .dev = { + .platform_data = &(struct samsung_pd_info) { + .enable = exynos4_pd_enable, + .disable = exynos4_pd_disable, + .base = S5P_PMU_LCD1_CONF, + }, + }, + }, { + .name = "samsung-pd", + .id = 4, + .dev = { + .platform_data = &(struct samsung_pd_info) { + .enable = exynos4_pd_enable, + .disable = exynos4_pd_disable, + .base = S5P_PMU_TV_CONF, + }, + }, + }, { + .name = "samsung-pd", + .id = 5, + .dev = { + .platform_data = &(struct samsung_pd_info) { + .enable = exynos4_pd_enable, + .disable = exynos4_pd_disable, + .base = S5P_PMU_CAM_CONF, + }, + }, + }, { + .name = "samsung-pd", + .id = 6, + .dev = { + .platform_data = &(struct samsung_pd_info) { + .enable = exynos4_pd_enable, + .disable = exynos4_pd_disable, + .base = S5P_PMU_GPS_CONF, + }, + }, + }, +}; diff --git a/arch/arm/mach-exynos4/dev-sysmmu.c b/arch/arm/mach-exynos4/dev-sysmmu.c new file mode 100644 index 000000000000..a10790a614ec --- /dev/null +++ b/arch/arm/mach-exynos4/dev-sysmmu.c @@ -0,0 +1,189 @@ +/* linux/arch/arm/mach-exynos4/dev-sysmmu.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS4 - System MMU support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include + +#include +#include + +static struct resource exynos4_sysmmu_resource[] = { + [0] = { + .start = EXYNOS4_PA_SYSMMU_MDMA, + .end = EXYNOS4_PA_SYSMMU_MDMA + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_SYSMMU_MDMA0_0, + .end = IRQ_SYSMMU_MDMA0_0, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = EXYNOS4_PA_SYSMMU_SSS, + .end = EXYNOS4_PA_SYSMMU_SSS + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [3] = { + .start = IRQ_SYSMMU_SSS_0, + .end = IRQ_SYSMMU_SSS_0, + .flags = IORESOURCE_IRQ, + }, + [4] = { + .start = EXYNOS4_PA_SYSMMU_FIMC0, + .end = EXYNOS4_PA_SYSMMU_FIMC0 + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [5] = { + .start = IRQ_SYSMMU_FIMC0_0, + .end = IRQ_SYSMMU_FIMC0_0, + .flags = IORESOURCE_IRQ, + }, + [6] = { + .start = EXYNOS4_PA_SYSMMU_FIMC1, + .end = EXYNOS4_PA_SYSMMU_FIMC1 + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [7] = { + .start = IRQ_SYSMMU_FIMC1_0, + .end = IRQ_SYSMMU_FIMC1_0, + .flags = IORESOURCE_IRQ, + }, + [8] = { + .start = EXYNOS4_PA_SYSMMU_FIMC2, + .end = EXYNOS4_PA_SYSMMU_FIMC2 + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [9] = { + .start = IRQ_SYSMMU_FIMC2_0, + .end = IRQ_SYSMMU_FIMC2_0, + .flags = IORESOURCE_IRQ, + }, + [10] = { + .start = EXYNOS4_PA_SYSMMU_FIMC3, + .end = EXYNOS4_PA_SYSMMU_FIMC3 + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [11] = { + .start = IRQ_SYSMMU_FIMC3_0, + .end = IRQ_SYSMMU_FIMC3_0, + .flags = IORESOURCE_IRQ, + }, + [12] = { + .start = EXYNOS4_PA_SYSMMU_JPEG, + .end = EXYNOS4_PA_SYSMMU_JPEG + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [13] = { + .start = IRQ_SYSMMU_JPEG_0, + .end = IRQ_SYSMMU_JPEG_0, + .flags = IORESOURCE_IRQ, + }, + [14] = { + .start = EXYNOS4_PA_SYSMMU_FIMD0, + .end = EXYNOS4_PA_SYSMMU_FIMD0 + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [15] = { + .start = IRQ_SYSMMU_LCD0_M0_0, + .end = IRQ_SYSMMU_LCD0_M0_0, + .flags = IORESOURCE_IRQ, + }, + [16] = { + .start = EXYNOS4_PA_SYSMMU_FIMD1, + .end = EXYNOS4_PA_SYSMMU_FIMD1 + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [17] = { + .start = IRQ_SYSMMU_LCD1_M1_0, + .end = IRQ_SYSMMU_LCD1_M1_0, + .flags = IORESOURCE_IRQ, + }, + [18] = { + .start = EXYNOS4_PA_SYSMMU_PCIe, + .end = EXYNOS4_PA_SYSMMU_PCIe + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [19] = { + .start = IRQ_SYSMMU_PCIE_0, + .end = IRQ_SYSMMU_PCIE_0, + .flags = IORESOURCE_IRQ, + }, + [20] = { + .start = EXYNOS4_PA_SYSMMU_G2D, + .end = EXYNOS4_PA_SYSMMU_G2D + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [21] = { + .start = IRQ_SYSMMU_2D_0, + .end = IRQ_SYSMMU_2D_0, + .flags = IORESOURCE_IRQ, + }, + [22] = { + .start = EXYNOS4_PA_SYSMMU_ROTATOR, + .end = EXYNOS4_PA_SYSMMU_ROTATOR + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [23] = { + .start = IRQ_SYSMMU_ROTATOR_0, + .end = IRQ_SYSMMU_ROTATOR_0, + .flags = IORESOURCE_IRQ, + }, + [24] = { + .start = EXYNOS4_PA_SYSMMU_MDMA2, + .end = EXYNOS4_PA_SYSMMU_MDMA2 + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [25] = { + .start = IRQ_SYSMMU_MDMA1_0, + .end = IRQ_SYSMMU_MDMA1_0, + .flags = IORESOURCE_IRQ, + }, + [26] = { + .start = EXYNOS4_PA_SYSMMU_TV, + .end = EXYNOS4_PA_SYSMMU_TV + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [27] = { + .start = IRQ_SYSMMU_TV_M0_0, + .end = IRQ_SYSMMU_TV_M0_0, + .flags = IORESOURCE_IRQ, + }, + [28] = { + .start = EXYNOS4_PA_SYSMMU_MFC_L, + .end = EXYNOS4_PA_SYSMMU_MFC_L + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [29] = { + .start = IRQ_SYSMMU_MFC_M0_0, + .end = IRQ_SYSMMU_MFC_M0_0, + .flags = IORESOURCE_IRQ, + }, + [30] = { + .start = EXYNOS4_PA_SYSMMU_MFC_R, + .end = EXYNOS4_PA_SYSMMU_MFC_R + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [31] = { + .start = IRQ_SYSMMU_MFC_M1_0, + .end = IRQ_SYSMMU_MFC_M1_0, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device exynos4_device_sysmmu = { + .name = "s5p-sysmmu", + .id = 32, + .num_resources = ARRAY_SIZE(exynos4_sysmmu_resource), + .resource = exynos4_sysmmu_resource, +}; + +EXPORT_SYMBOL(exynos4_device_sysmmu); diff --git a/arch/arm/mach-exynos4/setup-i2c1.c b/arch/arm/mach-exynos4/setup-i2c1.c new file mode 100644 index 000000000000..fd7235a43f6e --- /dev/null +++ b/arch/arm/mach-exynos4/setup-i2c1.c @@ -0,0 +1,23 @@ +/* + * linux/arch/arm/mach-exynos4/setup-i2c1.c + * + * Copyright (C) 2010 Samsung Electronics Co., Ltd. + * + * I2C1 GPIO configuration. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +struct platform_device; /* don't need the contents */ + +#include +#include +#include + +void s3c_i2c1_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgall_range(EXYNOS4_GPD1(2), 2, + S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); +} diff --git a/arch/arm/mach-exynos4/setup-i2c2.c b/arch/arm/mach-exynos4/setup-i2c2.c new file mode 100644 index 000000000000..2694b19e8b37 --- /dev/null +++ b/arch/arm/mach-exynos4/setup-i2c2.c @@ -0,0 +1,23 @@ +/* + * linux/arch/arm/mach-exynos4/setup-i2c2.c + * + * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. + * + * I2C2 GPIO configuration. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +struct platform_device; /* don't need the contents */ + +#include +#include +#include + +void s3c_i2c2_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgall_range(EXYNOS4_GPA0(6), 2, + S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); +} diff --git a/arch/arm/mach-exynos4/setup-i2c3.c b/arch/arm/mach-exynos4/setup-i2c3.c new file mode 100644 index 000000000000..379bd306993f --- /dev/null +++ b/arch/arm/mach-exynos4/setup-i2c3.c @@ -0,0 +1,23 @@ +/* + * linux/arch/arm/mach-exynos4/setup-i2c3.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * + * I2C3 GPIO configuration. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +struct platform_device; /* don't need the contents */ + +#include +#include +#include + +void s3c_i2c3_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgall_range(EXYNOS4_GPA1(2), 2, + S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); +} diff --git a/arch/arm/mach-exynos4/setup-i2c4.c b/arch/arm/mach-exynos4/setup-i2c4.c new file mode 100644 index 000000000000..9f3c04855b76 --- /dev/null +++ b/arch/arm/mach-exynos4/setup-i2c4.c @@ -0,0 +1,23 @@ +/* + * linux/arch/arm/mach-exynos4/setup-i2c4.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * + * I2C4 GPIO configuration. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +struct platform_device; /* don't need the contents */ + +#include +#include +#include + +void s3c_i2c4_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2, + S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); +} diff --git a/arch/arm/mach-exynos4/setup-i2c5.c b/arch/arm/mach-exynos4/setup-i2c5.c new file mode 100644 index 000000000000..77e1a1e57c76 --- /dev/null +++ b/arch/arm/mach-exynos4/setup-i2c5.c @@ -0,0 +1,23 @@ +/* + * linux/arch/arm/mach-exynos4/setup-i2c5.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * + * I2C5 GPIO configuration. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +struct platform_device; /* don't need the contents */ + +#include +#include +#include + +void s3c_i2c5_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgall_range(EXYNOS4_GPB(6), 2, + S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); +} diff --git a/arch/arm/mach-exynos4/setup-i2c6.c b/arch/arm/mach-exynos4/setup-i2c6.c new file mode 100644 index 000000000000..284d12b7af0e --- /dev/null +++ b/arch/arm/mach-exynos4/setup-i2c6.c @@ -0,0 +1,23 @@ +/* + * linux/arch/arm/mach-exynos4/setup-i2c6.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * + * I2C6 GPIO configuration. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +struct platform_device; /* don't need the contents */ + +#include +#include +#include + +void s3c_i2c6_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgall_range(EXYNOS4_GPC1(3), 2, + S3C_GPIO_SFN(4), S3C_GPIO_PULL_UP); +} diff --git a/arch/arm/mach-exynos4/setup-i2c7.c b/arch/arm/mach-exynos4/setup-i2c7.c new file mode 100644 index 000000000000..b7611ee359a2 --- /dev/null +++ b/arch/arm/mach-exynos4/setup-i2c7.c @@ -0,0 +1,23 @@ +/* + * linux/arch/arm/mach-exynos4/setup-i2c7.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * + * I2C7 GPIO configuration. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +struct platform_device; /* don't need the contents */ + +#include +#include +#include + +void s3c_i2c7_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgall_range(EXYNOS4_GPD0(2), 2, + S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); +} diff --git a/arch/arm/mach-exynos4/setup-sdhci-gpio.c b/arch/arm/mach-exynos4/setup-sdhci-gpio.c new file mode 100644 index 000000000000..1b3d3a2de95c --- /dev/null +++ b/arch/arm/mach-exynos4/setup-sdhci-gpio.c @@ -0,0 +1,152 @@ +/* linux/arch/arm/mach-exynos4/setup-sdhci-gpio.c + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS4 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) +{ + struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; + unsigned int gpio; + + /* Set all the necessary GPK0[0:1] pins to special-function 2 */ + for (gpio = EXYNOS4_GPK0(0); gpio < EXYNOS4_GPK0(2); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + + switch (width) { + case 8: + for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) { + /* Data pin GPK1[3:6] to special-funtion 3 */ + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + case 4: + for (gpio = EXYNOS4_GPK0(3); gpio <= EXYNOS4_GPK0(6); gpio++) { + /* Data pin GPK0[3:6] to special-funtion 2 */ + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + default: + break; + } + + if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { + s3c_gpio_cfgpin(EXYNOS4_GPK0(2), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(EXYNOS4_GPK0(2), S3C_GPIO_PULL_UP); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } +} + +void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) +{ + struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; + unsigned int gpio; + + /* Set all the necessary GPK1[0:1] pins to special-function 2 */ + for (gpio = EXYNOS4_GPK1(0); gpio < EXYNOS4_GPK1(2); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + + for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) { + /* Data pin GPK1[3:6] to special-function 2 */ + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + + if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { + s3c_gpio_cfgpin(EXYNOS4_GPK1(2), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(EXYNOS4_GPK1(2), S3C_GPIO_PULL_UP); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } +} + +void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) +{ + struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; + unsigned int gpio; + + /* Set all the necessary GPK2[0:1] pins to special-function 2 */ + for (gpio = EXYNOS4_GPK2(0); gpio < EXYNOS4_GPK2(2); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + + switch (width) { + case 8: + for (gpio = EXYNOS4_GPK3(3); gpio <= EXYNOS4_GPK3(6); gpio++) { + /* Data pin GPK3[3:6] to special-function 3 */ + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + case 4: + for (gpio = EXYNOS4_GPK2(3); gpio <= EXYNOS4_GPK2(6); gpio++) { + /* Data pin GPK2[3:6] to special-function 2 */ + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + default: + break; + } + + if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { + s3c_gpio_cfgpin(EXYNOS4_GPK2(2), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(EXYNOS4_GPK2(2), S3C_GPIO_PULL_UP); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } +} + +void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width) +{ + struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; + unsigned int gpio; + + /* Set all the necessary GPK3[0:1] pins to special-function 2 */ + for (gpio = EXYNOS4_GPK3(0); gpio < EXYNOS4_GPK3(2); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + + for (gpio = EXYNOS4_GPK3(3); gpio <= EXYNOS4_GPK3(6); gpio++) { + /* Data pin GPK3[3:6] to special-function 2 */ + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + + if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { + s3c_gpio_cfgpin(EXYNOS4_GPK3(2), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(EXYNOS4_GPK3(2), S3C_GPIO_PULL_UP); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } +} diff --git a/arch/arm/mach-exynos4/setup-sdhci.c b/arch/arm/mach-exynos4/setup-sdhci.c new file mode 100644 index 000000000000..85f9433d4836 --- /dev/null +++ b/arch/arm/mach-exynos4/setup-sdhci.c @@ -0,0 +1,69 @@ +/* linux/arch/arm/mach-exynos4/setup-sdhci.c + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS4 - Helper functions for settign up SDHCI device(s) (HSMMC) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include + +#include +#include + +#include + +/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ + +char *exynos4_hsmmc_clksrcs[4] = { + [0] = NULL, + [1] = NULL, + [2] = "sclk_mmc", /* mmc_bus */ + [3] = NULL, +}; + +void exynos4_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r, + struct mmc_ios *ios, struct mmc_card *card) +{ + u32 ctrl2, ctrl3; + + /* don't need to alter anything acording to card-type */ + + ctrl2 = readl(r + S3C_SDHCI_CONTROL2); + + /* select base clock source to HCLK */ + + ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK; + + /* + * clear async mode, enable conflict mask, rx feedback ctrl, SD + * clk hold and no use debounce count + */ + + ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | + S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | + S3C_SDHCI_CTRL2_ENFBCLKRX | + S3C_SDHCI_CTRL2_DFCNT_NONE | + S3C_SDHCI_CTRL2_ENCLKOUTHOLD); + + /* Tx and Rx feedback clock delay control */ + + if (ios->clock < 25 * 1000000) + ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 | + S3C_SDHCI_CTRL3_FCSEL2 | + S3C_SDHCI_CTRL3_FCSEL1 | + S3C_SDHCI_CTRL3_FCSEL0); + else + ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); + + writel(ctrl2, r + S3C_SDHCI_CONTROL2); + writel(ctrl3, r + S3C_SDHCI_CONTROL3); +} -- cgit v1.2.2