diff options
author | Cyril Chemparathy <cyril@ti.com> | 2010-05-07 17:06:35 -0400 |
---|---|---|
committer | Kevin Hilman <khilman@deeprootsystems.com> | 2010-05-13 13:05:26 -0400 |
commit | 1bcd38ad2de4c1cd30387c588dfb28d637d4111d (patch) | |
tree | c8702d5bf18d3956a8a661d8aef62b79dff34cb8 /arch/arm/mach-davinci/time.c | |
parent | 3347db8392486a1b52aab980cc445cf505c36d45 (diff) |
Davinci: timer - use ioremap()
This patch eliminates IO_ADDRESS() usage for Davinci timer definitions. The
timer code has correspondingly been modified to ioremap() MMRs instead.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-davinci/time.c')
-rw-r--r-- | arch/arm/mach-davinci/time.c | 22 |
1 files changed, 14 insertions, 8 deletions
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c index e5c598a387be..0f21c36e65dd 100644 --- a/arch/arm/mach-davinci/time.c +++ b/arch/arm/mach-davinci/time.c | |||
@@ -197,32 +197,36 @@ static void __init timer_init(void) | |||
197 | { | 197 | { |
198 | struct davinci_soc_info *soc_info = &davinci_soc_info; | 198 | struct davinci_soc_info *soc_info = &davinci_soc_info; |
199 | struct davinci_timer_instance *dtip = soc_info->timer_info->timers; | 199 | struct davinci_timer_instance *dtip = soc_info->timer_info->timers; |
200 | void __iomem *base[2]; | ||
200 | int i; | 201 | int i; |
201 | 202 | ||
202 | /* Global init of each 64-bit timer as a whole */ | 203 | /* Global init of each 64-bit timer as a whole */ |
203 | for(i=0; i<2; i++) { | 204 | for(i=0; i<2; i++) { |
204 | u32 tgcr; | 205 | u32 tgcr; |
205 | void __iomem *base = dtip[i].base; | 206 | |
207 | base[i] = ioremap(dtip[i].base, SZ_4K); | ||
208 | if (WARN_ON(!base[i])) | ||
209 | continue; | ||
206 | 210 | ||
207 | /* Disabled, Internal clock source */ | 211 | /* Disabled, Internal clock source */ |
208 | __raw_writel(0, base + TCR); | 212 | __raw_writel(0, base[i] + TCR); |
209 | 213 | ||
210 | /* reset both timers, no pre-scaler for timer34 */ | 214 | /* reset both timers, no pre-scaler for timer34 */ |
211 | tgcr = 0; | 215 | tgcr = 0; |
212 | __raw_writel(tgcr, base + TGCR); | 216 | __raw_writel(tgcr, base[i] + TGCR); |
213 | 217 | ||
214 | /* Set both timers to unchained 32-bit */ | 218 | /* Set both timers to unchained 32-bit */ |
215 | tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT; | 219 | tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT; |
216 | __raw_writel(tgcr, base + TGCR); | 220 | __raw_writel(tgcr, base[i] + TGCR); |
217 | 221 | ||
218 | /* Unreset timers */ | 222 | /* Unreset timers */ |
219 | tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) | | 223 | tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) | |
220 | (TGCR_UNRESET << TGCR_TIM34RS_SHIFT); | 224 | (TGCR_UNRESET << TGCR_TIM34RS_SHIFT); |
221 | __raw_writel(tgcr, base + TGCR); | 225 | __raw_writel(tgcr, base[i] + TGCR); |
222 | 226 | ||
223 | /* Init both counters to zero */ | 227 | /* Init both counters to zero */ |
224 | __raw_writel(0, base + TIM12); | 228 | __raw_writel(0, base[i] + TIM12); |
225 | __raw_writel(0, base + TIM34); | 229 | __raw_writel(0, base[i] + TIM34); |
226 | } | 230 | } |
227 | 231 | ||
228 | /* Init of each timer as a 32-bit timer */ | 232 | /* Init of each timer as a 32-bit timer */ |
@@ -231,7 +235,9 @@ static void __init timer_init(void) | |||
231 | int timer = ID_TO_TIMER(t->id); | 235 | int timer = ID_TO_TIMER(t->id); |
232 | u32 irq; | 236 | u32 irq; |
233 | 237 | ||
234 | t->base = dtip[timer].base; | 238 | t->base = base[timer]; |
239 | if (!t->base) | ||
240 | continue; | ||
235 | 241 | ||
236 | if (IS_TIMER_BOT(t->id)) { | 242 | if (IS_TIMER_BOT(t->id)) { |
237 | t->enamode_shift = 6; | 243 | t->enamode_shift = 6; |