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authorCyril Chemparathy <cyril@ti.com>2010-05-07 17:06:35 -0400
committerKevin Hilman <khilman@deeprootsystems.com>2010-05-13 13:05:26 -0400
commit1bcd38ad2de4c1cd30387c588dfb28d637d4111d (patch)
treec8702d5bf18d3956a8a661d8aef62b79dff34cb8 /arch/arm
parent3347db8392486a1b52aab980cc445cf505c36d45 (diff)
Davinci: timer - use ioremap()
This patch eliminates IO_ADDRESS() usage for Davinci timer definitions. The timer code has correspondingly been modified to ioremap() MMRs instead. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-davinci/da830.c4
-rw-r--r--arch/arm/mach-davinci/da850.c8
-rw-r--r--arch/arm/mach-davinci/devices.c4
-rw-r--r--arch/arm/mach-davinci/include/mach/common.h2
-rw-r--r--arch/arm/mach-davinci/time.c22
5 files changed, 23 insertions, 17 deletions
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index c5600b89f628..8a2510c5236f 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -1159,14 +1159,14 @@ static struct davinci_id da830_ids[] = {
1159 1159
1160static struct davinci_timer_instance da830_timer_instance[2] = { 1160static struct davinci_timer_instance da830_timer_instance[2] = {
1161 { 1161 {
1162 .base = IO_ADDRESS(DA8XX_TIMER64P0_BASE), 1162 .base = DA8XX_TIMER64P0_BASE,
1163 .bottom_irq = IRQ_DA8XX_TINT12_0, 1163 .bottom_irq = IRQ_DA8XX_TINT12_0,
1164 .top_irq = IRQ_DA8XX_TINT34_0, 1164 .top_irq = IRQ_DA8XX_TINT34_0,
1165 .cmp_off = DA830_CMP12_0, 1165 .cmp_off = DA830_CMP12_0,
1166 .cmp_irq = IRQ_DA830_T12CMPINT0_0, 1166 .cmp_irq = IRQ_DA830_T12CMPINT0_0,
1167 }, 1167 },
1168 { 1168 {
1169 .base = IO_ADDRESS(DA8XX_TIMER64P1_BASE), 1169 .base = DA8XX_TIMER64P1_BASE,
1170 .bottom_irq = IRQ_DA8XX_TINT12_1, 1170 .bottom_irq = IRQ_DA8XX_TINT12_1,
1171 .top_irq = IRQ_DA8XX_TINT34_1, 1171 .top_irq = IRQ_DA8XX_TINT34_1,
1172 .cmp_off = DA830_CMP12_0, 1172 .cmp_off = DA830_CMP12_0,
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index fcf701628590..ebfa5ca29a81 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -800,22 +800,22 @@ static struct davinci_id da850_ids[] = {
800 800
801static struct davinci_timer_instance da850_timer_instance[4] = { 801static struct davinci_timer_instance da850_timer_instance[4] = {
802 { 802 {
803 .base = IO_ADDRESS(DA8XX_TIMER64P0_BASE), 803 .base = DA8XX_TIMER64P0_BASE,
804 .bottom_irq = IRQ_DA8XX_TINT12_0, 804 .bottom_irq = IRQ_DA8XX_TINT12_0,
805 .top_irq = IRQ_DA8XX_TINT34_0, 805 .top_irq = IRQ_DA8XX_TINT34_0,
806 }, 806 },
807 { 807 {
808 .base = IO_ADDRESS(DA8XX_TIMER64P1_BASE), 808 .base = DA8XX_TIMER64P1_BASE,
809 .bottom_irq = IRQ_DA8XX_TINT12_1, 809 .bottom_irq = IRQ_DA8XX_TINT12_1,
810 .top_irq = IRQ_DA8XX_TINT34_1, 810 .top_irq = IRQ_DA8XX_TINT34_1,
811 }, 811 },
812 { 812 {
813 .base = IO_ADDRESS(DA850_TIMER64P2_BASE), 813 .base = DA850_TIMER64P2_BASE,
814 .bottom_irq = IRQ_DA850_TINT12_2, 814 .bottom_irq = IRQ_DA850_TINT12_2,
815 .top_irq = IRQ_DA850_TINT34_2, 815 .top_irq = IRQ_DA850_TINT34_2,
816 }, 816 },
817 { 817 {
818 .base = IO_ADDRESS(DA850_TIMER64P3_BASE), 818 .base = DA850_TIMER64P3_BASE,
819 .bottom_irq = IRQ_DA850_TINT12_3, 819 .bottom_irq = IRQ_DA850_TINT12_3,
820 .top_irq = IRQ_DA850_TINT34_3, 820 .top_irq = IRQ_DA850_TINT34_3,
821 }, 821 },
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index d9c82ee434e0..8b7201e4c79c 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -297,12 +297,12 @@ static void davinci_init_wdt(void)
297 297
298struct davinci_timer_instance davinci_timer_instance[2] = { 298struct davinci_timer_instance davinci_timer_instance[2] = {
299 { 299 {
300 .base = IO_ADDRESS(DAVINCI_TIMER0_BASE), 300 .base = DAVINCI_TIMER0_BASE,
301 .bottom_irq = IRQ_TINT0_TINT12, 301 .bottom_irq = IRQ_TINT0_TINT12,
302 .top_irq = IRQ_TINT0_TINT34, 302 .top_irq = IRQ_TINT0_TINT34,
303 }, 303 },
304 { 304 {
305 .base = IO_ADDRESS(DAVINCI_TIMER1_BASE), 305 .base = DAVINCI_TIMER1_BASE,
306 .bottom_irq = IRQ_TINT1_TINT12, 306 .bottom_irq = IRQ_TINT1_TINT12,
307 .top_irq = IRQ_TINT1_TINT34, 307 .top_irq = IRQ_TINT1_TINT34,
308 }, 308 },
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 1078458bdd54..2e1546401397 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -24,7 +24,7 @@ extern void __iomem *davinci_intc_base;
24extern int davinci_intc_type; 24extern int davinci_intc_type;
25 25
26struct davinci_timer_instance { 26struct davinci_timer_instance {
27 void __iomem *base; 27 u32 base;
28 u32 bottom_irq; 28 u32 bottom_irq;
29 u32 top_irq; 29 u32 top_irq;
30 unsigned long cmp_off; 30 unsigned long cmp_off;
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index e5c598a387be..0f21c36e65dd 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -197,32 +197,36 @@ static void __init timer_init(void)
197{ 197{
198 struct davinci_soc_info *soc_info = &davinci_soc_info; 198 struct davinci_soc_info *soc_info = &davinci_soc_info;
199 struct davinci_timer_instance *dtip = soc_info->timer_info->timers; 199 struct davinci_timer_instance *dtip = soc_info->timer_info->timers;
200 void __iomem *base[2];
200 int i; 201 int i;
201 202
202 /* Global init of each 64-bit timer as a whole */ 203 /* Global init of each 64-bit timer as a whole */
203 for(i=0; i<2; i++) { 204 for(i=0; i<2; i++) {
204 u32 tgcr; 205 u32 tgcr;
205 void __iomem *base = dtip[i].base; 206
207 base[i] = ioremap(dtip[i].base, SZ_4K);
208 if (WARN_ON(!base[i]))
209 continue;
206 210
207 /* Disabled, Internal clock source */ 211 /* Disabled, Internal clock source */
208 __raw_writel(0, base + TCR); 212 __raw_writel(0, base[i] + TCR);
209 213
210 /* reset both timers, no pre-scaler for timer34 */ 214 /* reset both timers, no pre-scaler for timer34 */
211 tgcr = 0; 215 tgcr = 0;
212 __raw_writel(tgcr, base + TGCR); 216 __raw_writel(tgcr, base[i] + TGCR);
213 217
214 /* Set both timers to unchained 32-bit */ 218 /* Set both timers to unchained 32-bit */
215 tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT; 219 tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT;
216 __raw_writel(tgcr, base + TGCR); 220 __raw_writel(tgcr, base[i] + TGCR);
217 221
218 /* Unreset timers */ 222 /* Unreset timers */
219 tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) | 223 tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
220 (TGCR_UNRESET << TGCR_TIM34RS_SHIFT); 224 (TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
221 __raw_writel(tgcr, base + TGCR); 225 __raw_writel(tgcr, base[i] + TGCR);
222 226
223 /* Init both counters to zero */ 227 /* Init both counters to zero */
224 __raw_writel(0, base + TIM12); 228 __raw_writel(0, base[i] + TIM12);
225 __raw_writel(0, base + TIM34); 229 __raw_writel(0, base[i] + TIM34);
226 } 230 }
227 231
228 /* Init of each timer as a 32-bit timer */ 232 /* Init of each timer as a 32-bit timer */
@@ -231,7 +235,9 @@ static void __init timer_init(void)
231 int timer = ID_TO_TIMER(t->id); 235 int timer = ID_TO_TIMER(t->id);
232 u32 irq; 236 u32 irq;
233 237
234 t->base = dtip[timer].base; 238 t->base = base[timer];
239 if (!t->base)
240 continue;
235 241
236 if (IS_TIMER_BOT(t->id)) { 242 if (IS_TIMER_BOT(t->id)) {
237 t->enamode_shift = 6; 243 t->enamode_shift = 6;