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authorMark A. Greer <mgreer@mvista.com>2009-04-15 15:40:00 -0400
committerKevin Hilman <khilman@deeprootsystems.com>2009-05-26 11:18:09 -0400
commit673dd36f0d0cf8893d6b46d524ad80e81076b885 (patch)
tree50bd5c954e1b006c171c9effe72ac70e0a8203b4 /arch/arm/mach-davinci/dm644x.c
parent0e585952ac6a06b3c77d6b8eadb9c359766a700d (diff)
davinci: Move interrupt ctlr info to SoC infrastructure
Use the SoC infrastructure to hold the interrupt controller information (i.e., base address, default priorities, interrupt controller type, and the number of IRQs). The interrupt controller base, although initially put in the soc_info structure's intc_base field, is eventually put in the global 'davinci_intc_base' so the low-level interrupt code can access it without a dereference. These changes enable the SoC default irq priorities to be put in the SoC-specific files, and the interrupt controller to be at any base address. Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-davinci/dm644x.c')
-rw-r--r--arch/arm/mach-davinci/dm644x.c72
1 files changed, 72 insertions, 0 deletions
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index b7c17dd6795b..5c6a7b175786 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -390,6 +390,74 @@ MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false)
390#endif 390#endif
391}; 391};
392 392
393/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
394static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
395 [IRQ_VDINT0] = 2,
396 [IRQ_VDINT1] = 6,
397 [IRQ_VDINT2] = 6,
398 [IRQ_HISTINT] = 6,
399 [IRQ_H3AINT] = 6,
400 [IRQ_PRVUINT] = 6,
401 [IRQ_RSZINT] = 6,
402 [7] = 7,
403 [IRQ_VENCINT] = 6,
404 [IRQ_ASQINT] = 6,
405 [IRQ_IMXINT] = 6,
406 [IRQ_VLCDINT] = 6,
407 [IRQ_USBINT] = 4,
408 [IRQ_EMACINT] = 4,
409 [14] = 7,
410 [15] = 7,
411 [IRQ_CCINT0] = 5, /* dma */
412 [IRQ_CCERRINT] = 5, /* dma */
413 [IRQ_TCERRINT0] = 5, /* dma */
414 [IRQ_TCERRINT] = 5, /* dma */
415 [IRQ_PSCIN] = 7,
416 [21] = 7,
417 [IRQ_IDE] = 4,
418 [23] = 7,
419 [IRQ_MBXINT] = 7,
420 [IRQ_MBRINT] = 7,
421 [IRQ_MMCINT] = 7,
422 [IRQ_SDIOINT] = 7,
423 [28] = 7,
424 [IRQ_DDRINT] = 7,
425 [IRQ_AEMIFINT] = 7,
426 [IRQ_VLQINT] = 4,
427 [IRQ_TINT0_TINT12] = 2, /* clockevent */
428 [IRQ_TINT0_TINT34] = 2, /* clocksource */
429 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
430 [IRQ_TINT1_TINT34] = 7, /* system tick */
431 [IRQ_PWMINT0] = 7,
432 [IRQ_PWMINT1] = 7,
433 [IRQ_PWMINT2] = 7,
434 [IRQ_I2C] = 3,
435 [IRQ_UARTINT0] = 3,
436 [IRQ_UARTINT1] = 3,
437 [IRQ_UARTINT2] = 3,
438 [IRQ_SPINT0] = 3,
439 [IRQ_SPINT1] = 3,
440 [45] = 7,
441 [IRQ_DSP2ARM0] = 4,
442 [IRQ_DSP2ARM1] = 4,
443 [IRQ_GPIO0] = 7,
444 [IRQ_GPIO1] = 7,
445 [IRQ_GPIO2] = 7,
446 [IRQ_GPIO3] = 7,
447 [IRQ_GPIO4] = 7,
448 [IRQ_GPIO5] = 7,
449 [IRQ_GPIO6] = 7,
450 [IRQ_GPIO7] = 7,
451 [IRQ_GPIOBNK0] = 7,
452 [IRQ_GPIOBNK1] = 7,
453 [IRQ_GPIOBNK2] = 7,
454 [IRQ_GPIOBNK3] = 7,
455 [IRQ_GPIOBNK4] = 7,
456 [IRQ_COMMTX] = 7,
457 [IRQ_COMMRX] = 7,
458 [IRQ_EMUINT] = 7,
459};
460
393/*----------------------------------------------------------------------*/ 461/*----------------------------------------------------------------------*/
394 462
395static const s8 dma_chan_dm644x_no_event[] = { 463static const s8 dma_chan_dm644x_no_event[] = {
@@ -503,6 +571,10 @@ static struct davinci_soc_info davinci_soc_info_dm644x = {
503 .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE), 571 .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
504 .pinmux_pins = dm644x_pins, 572 .pinmux_pins = dm644x_pins,
505 .pinmux_pins_num = ARRAY_SIZE(dm644x_pins), 573 .pinmux_pins_num = ARRAY_SIZE(dm644x_pins),
574 .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
575 .intc_type = DAVINCI_INTC_TYPE_AINTC,
576 .intc_irq_prios = dm644x_default_priorities,
577 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
506}; 578};
507 579
508void __init dm644x_init(void) 580void __init dm644x_init(void)