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-rw-r--r--arch/arm/mach-davinci/common.c3
-rw-r--r--arch/arm/mach-davinci/dm355.c69
-rw-r--r--arch/arm/mach-davinci/dm644x.c72
-rw-r--r--arch/arm/mach-davinci/dm646x.c71
-rw-r--r--arch/arm/mach-davinci/include/mach/common.h5
-rw-r--r--arch/arm/mach-davinci/include/mach/entry-macro.S3
-rw-r--r--arch/arm/mach-davinci/include/mach/irqs.h3
-rw-r--r--arch/arm/mach-davinci/irq.c217
8 files changed, 229 insertions, 214 deletions
diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c
index 2e5b888e6ca6..d72d517d090c 100644
--- a/arch/arm/mach-davinci/common.c
+++ b/arch/arm/mach-davinci/common.c
@@ -22,6 +22,8 @@
22struct davinci_soc_info davinci_soc_info; 22struct davinci_soc_info davinci_soc_info;
23EXPORT_SYMBOL(davinci_soc_info); 23EXPORT_SYMBOL(davinci_soc_info);
24 24
25void __iomem *davinci_intc_base;
26
25static struct davinci_id * __init davinci_get_id(u32 jtag_id) 27static struct davinci_id * __init davinci_get_id(u32 jtag_id)
26{ 28{
27 int i; 29 int i;
@@ -84,6 +86,7 @@ void __init davinci_common_init(struct davinci_soc_info *soc_info)
84 goto err; 86 goto err;
85 } 87 }
86 88
89 davinci_intc_base = davinci_soc_info.intc_base;
87 return; 90 return;
88 91
89err: 92err:
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index f735ed9d2d10..e8c01ffe818a 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -470,6 +470,71 @@ EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false)
470#endif 470#endif
471}; 471};
472 472
473static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
474 [IRQ_DM355_CCDC_VDINT0] = 2,
475 [IRQ_DM355_CCDC_VDINT1] = 6,
476 [IRQ_DM355_CCDC_VDINT2] = 6,
477 [IRQ_DM355_IPIPE_HST] = 6,
478 [IRQ_DM355_H3AINT] = 6,
479 [IRQ_DM355_IPIPE_SDR] = 6,
480 [IRQ_DM355_IPIPEIFINT] = 6,
481 [IRQ_DM355_OSDINT] = 7,
482 [IRQ_DM355_VENCINT] = 6,
483 [IRQ_ASQINT] = 6,
484 [IRQ_IMXINT] = 6,
485 [IRQ_USBINT] = 4,
486 [IRQ_DM355_RTOINT] = 4,
487 [IRQ_DM355_UARTINT2] = 7,
488 [IRQ_DM355_TINT6] = 7,
489 [IRQ_CCINT0] = 5, /* dma */
490 [IRQ_CCERRINT] = 5, /* dma */
491 [IRQ_TCERRINT0] = 5, /* dma */
492 [IRQ_TCERRINT] = 5, /* dma */
493 [IRQ_DM355_SPINT2_1] = 7,
494 [IRQ_DM355_TINT7] = 4,
495 [IRQ_DM355_SDIOINT0] = 7,
496 [IRQ_MBXINT] = 7,
497 [IRQ_MBRINT] = 7,
498 [IRQ_MMCINT] = 7,
499 [IRQ_DM355_MMCINT1] = 7,
500 [IRQ_DM355_PWMINT3] = 7,
501 [IRQ_DDRINT] = 7,
502 [IRQ_AEMIFINT] = 7,
503 [IRQ_DM355_SDIOINT1] = 4,
504 [IRQ_TINT0_TINT12] = 2, /* clockevent */
505 [IRQ_TINT0_TINT34] = 2, /* clocksource */
506 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
507 [IRQ_TINT1_TINT34] = 7, /* system tick */
508 [IRQ_PWMINT0] = 7,
509 [IRQ_PWMINT1] = 7,
510 [IRQ_PWMINT2] = 7,
511 [IRQ_I2C] = 3,
512 [IRQ_UARTINT0] = 3,
513 [IRQ_UARTINT1] = 3,
514 [IRQ_DM355_SPINT0_0] = 3,
515 [IRQ_DM355_SPINT0_1] = 3,
516 [IRQ_DM355_GPIO0] = 3,
517 [IRQ_DM355_GPIO1] = 7,
518 [IRQ_DM355_GPIO2] = 4,
519 [IRQ_DM355_GPIO3] = 4,
520 [IRQ_DM355_GPIO4] = 7,
521 [IRQ_DM355_GPIO5] = 7,
522 [IRQ_DM355_GPIO6] = 7,
523 [IRQ_DM355_GPIO7] = 7,
524 [IRQ_DM355_GPIO8] = 7,
525 [IRQ_DM355_GPIO9] = 7,
526 [IRQ_DM355_GPIOBNK0] = 7,
527 [IRQ_DM355_GPIOBNK1] = 7,
528 [IRQ_DM355_GPIOBNK2] = 7,
529 [IRQ_DM355_GPIOBNK3] = 7,
530 [IRQ_DM355_GPIOBNK4] = 7,
531 [IRQ_DM355_GPIOBNK5] = 7,
532 [IRQ_DM355_GPIOBNK6] = 7,
533 [IRQ_COMMTX] = 7,
534 [IRQ_COMMRX] = 7,
535 [IRQ_EMUINT] = 7,
536};
537
473/*----------------------------------------------------------------------*/ 538/*----------------------------------------------------------------------*/
474 539
475static const s8 dma_chan_dm355_no_event[] = { 540static const s8 dma_chan_dm355_no_event[] = {
@@ -563,6 +628,10 @@ static struct davinci_soc_info davinci_soc_info_dm355 = {
563 .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE), 628 .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
564 .pinmux_pins = dm355_pins, 629 .pinmux_pins = dm355_pins,
565 .pinmux_pins_num = ARRAY_SIZE(dm355_pins), 630 .pinmux_pins_num = ARRAY_SIZE(dm355_pins),
631 .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
632 .intc_type = DAVINCI_INTC_TYPE_AINTC,
633 .intc_irq_prios = dm355_default_priorities,
634 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
566}; 635};
567 636
568void __init dm355_init(void) 637void __init dm355_init(void)
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index b7c17dd6795b..5c6a7b175786 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -390,6 +390,74 @@ MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false)
390#endif 390#endif
391}; 391};
392 392
393/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
394static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
395 [IRQ_VDINT0] = 2,
396 [IRQ_VDINT1] = 6,
397 [IRQ_VDINT2] = 6,
398 [IRQ_HISTINT] = 6,
399 [IRQ_H3AINT] = 6,
400 [IRQ_PRVUINT] = 6,
401 [IRQ_RSZINT] = 6,
402 [7] = 7,
403 [IRQ_VENCINT] = 6,
404 [IRQ_ASQINT] = 6,
405 [IRQ_IMXINT] = 6,
406 [IRQ_VLCDINT] = 6,
407 [IRQ_USBINT] = 4,
408 [IRQ_EMACINT] = 4,
409 [14] = 7,
410 [15] = 7,
411 [IRQ_CCINT0] = 5, /* dma */
412 [IRQ_CCERRINT] = 5, /* dma */
413 [IRQ_TCERRINT0] = 5, /* dma */
414 [IRQ_TCERRINT] = 5, /* dma */
415 [IRQ_PSCIN] = 7,
416 [21] = 7,
417 [IRQ_IDE] = 4,
418 [23] = 7,
419 [IRQ_MBXINT] = 7,
420 [IRQ_MBRINT] = 7,
421 [IRQ_MMCINT] = 7,
422 [IRQ_SDIOINT] = 7,
423 [28] = 7,
424 [IRQ_DDRINT] = 7,
425 [IRQ_AEMIFINT] = 7,
426 [IRQ_VLQINT] = 4,
427 [IRQ_TINT0_TINT12] = 2, /* clockevent */
428 [IRQ_TINT0_TINT34] = 2, /* clocksource */
429 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
430 [IRQ_TINT1_TINT34] = 7, /* system tick */
431 [IRQ_PWMINT0] = 7,
432 [IRQ_PWMINT1] = 7,
433 [IRQ_PWMINT2] = 7,
434 [IRQ_I2C] = 3,
435 [IRQ_UARTINT0] = 3,
436 [IRQ_UARTINT1] = 3,
437 [IRQ_UARTINT2] = 3,
438 [IRQ_SPINT0] = 3,
439 [IRQ_SPINT1] = 3,
440 [45] = 7,
441 [IRQ_DSP2ARM0] = 4,
442 [IRQ_DSP2ARM1] = 4,
443 [IRQ_GPIO0] = 7,
444 [IRQ_GPIO1] = 7,
445 [IRQ_GPIO2] = 7,
446 [IRQ_GPIO3] = 7,
447 [IRQ_GPIO4] = 7,
448 [IRQ_GPIO5] = 7,
449 [IRQ_GPIO6] = 7,
450 [IRQ_GPIO7] = 7,
451 [IRQ_GPIOBNK0] = 7,
452 [IRQ_GPIOBNK1] = 7,
453 [IRQ_GPIOBNK2] = 7,
454 [IRQ_GPIOBNK3] = 7,
455 [IRQ_GPIOBNK4] = 7,
456 [IRQ_COMMTX] = 7,
457 [IRQ_COMMRX] = 7,
458 [IRQ_EMUINT] = 7,
459};
460
393/*----------------------------------------------------------------------*/ 461/*----------------------------------------------------------------------*/
394 462
395static const s8 dma_chan_dm644x_no_event[] = { 463static const s8 dma_chan_dm644x_no_event[] = {
@@ -503,6 +571,10 @@ static struct davinci_soc_info davinci_soc_info_dm644x = {
503 .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE), 571 .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
504 .pinmux_pins = dm644x_pins, 572 .pinmux_pins = dm644x_pins,
505 .pinmux_pins_num = ARRAY_SIZE(dm644x_pins), 573 .pinmux_pins_num = ARRAY_SIZE(dm644x_pins),
574 .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
575 .intc_type = DAVINCI_INTC_TYPE_AINTC,
576 .intc_irq_prios = dm644x_default_priorities,
577 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
506}; 578};
507 579
508void __init dm644x_init(void) 580void __init dm644x_init(void)
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 299d8d9d26e0..beb522e8a1a5 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -358,6 +358,73 @@ MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true)
358#endif 358#endif
359}; 359};
360 360
361static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
362 [IRQ_DM646X_VP_VERTINT0] = 7,
363 [IRQ_DM646X_VP_VERTINT1] = 7,
364 [IRQ_DM646X_VP_VERTINT2] = 7,
365 [IRQ_DM646X_VP_VERTINT3] = 7,
366 [IRQ_DM646X_VP_ERRINT] = 7,
367 [IRQ_DM646X_RESERVED_1] = 7,
368 [IRQ_DM646X_RESERVED_2] = 7,
369 [IRQ_DM646X_WDINT] = 7,
370 [IRQ_DM646X_CRGENINT0] = 7,
371 [IRQ_DM646X_CRGENINT1] = 7,
372 [IRQ_DM646X_TSIFINT0] = 7,
373 [IRQ_DM646X_TSIFINT1] = 7,
374 [IRQ_DM646X_VDCEINT] = 7,
375 [IRQ_DM646X_USBINT] = 7,
376 [IRQ_DM646X_USBDMAINT] = 7,
377 [IRQ_DM646X_PCIINT] = 7,
378 [IRQ_CCINT0] = 7, /* dma */
379 [IRQ_CCERRINT] = 7, /* dma */
380 [IRQ_TCERRINT0] = 7, /* dma */
381 [IRQ_TCERRINT] = 7, /* dma */
382 [IRQ_DM646X_TCERRINT2] = 7,
383 [IRQ_DM646X_TCERRINT3] = 7,
384 [IRQ_DM646X_IDE] = 7,
385 [IRQ_DM646X_HPIINT] = 7,
386 [IRQ_DM646X_EMACRXTHINT] = 7,
387 [IRQ_DM646X_EMACRXINT] = 7,
388 [IRQ_DM646X_EMACTXINT] = 7,
389 [IRQ_DM646X_EMACMISCINT] = 7,
390 [IRQ_DM646X_MCASP0TXINT] = 7,
391 [IRQ_DM646X_MCASP0RXINT] = 7,
392 [IRQ_AEMIFINT] = 7,
393 [IRQ_DM646X_RESERVED_3] = 7,
394 [IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */
395 [IRQ_TINT0_TINT34] = 7, /* clocksource */
396 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
397 [IRQ_TINT1_TINT34] = 7, /* system tick */
398 [IRQ_PWMINT0] = 7,
399 [IRQ_PWMINT1] = 7,
400 [IRQ_DM646X_VLQINT] = 7,
401 [IRQ_I2C] = 7,
402 [IRQ_UARTINT0] = 7,
403 [IRQ_UARTINT1] = 7,
404 [IRQ_DM646X_UARTINT2] = 7,
405 [IRQ_DM646X_SPINT0] = 7,
406 [IRQ_DM646X_SPINT1] = 7,
407 [IRQ_DM646X_DSP2ARMINT] = 7,
408 [IRQ_DM646X_RESERVED_4] = 7,
409 [IRQ_DM646X_PSCINT] = 7,
410 [IRQ_DM646X_GPIO0] = 7,
411 [IRQ_DM646X_GPIO1] = 7,
412 [IRQ_DM646X_GPIO2] = 7,
413 [IRQ_DM646X_GPIO3] = 7,
414 [IRQ_DM646X_GPIO4] = 7,
415 [IRQ_DM646X_GPIO5] = 7,
416 [IRQ_DM646X_GPIO6] = 7,
417 [IRQ_DM646X_GPIO7] = 7,
418 [IRQ_DM646X_GPIOBNK0] = 7,
419 [IRQ_DM646X_GPIOBNK1] = 7,
420 [IRQ_DM646X_GPIOBNK2] = 7,
421 [IRQ_DM646X_DDRINT] = 7,
422 [IRQ_DM646X_AEMIFINT] = 7,
423 [IRQ_COMMTX] = 7,
424 [IRQ_COMMRX] = 7,
425 [IRQ_EMUINT] = 7,
426};
427
361/*----------------------------------------------------------------------*/ 428/*----------------------------------------------------------------------*/
362 429
363static const s8 dma_chan_dm646x_no_event[] = { 430static const s8 dma_chan_dm646x_no_event[] = {
@@ -483,6 +550,10 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
483 .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE), 550 .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
484 .pinmux_pins = dm646x_pins, 551 .pinmux_pins = dm646x_pins,
485 .pinmux_pins_num = ARRAY_SIZE(dm646x_pins), 552 .pinmux_pins_num = ARRAY_SIZE(dm646x_pins),
553 .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
554 .intc_type = DAVINCI_INTC_TYPE_AINTC,
555 .intc_irq_prios = dm646x_default_priorities,
556 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
486}; 557};
487 558
488void __init dm646x_init(void) 559void __init dm646x_init(void)
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index c00d375946d1..838ae13595a4 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -17,6 +17,7 @@ struct sys_timer;
17extern struct sys_timer davinci_timer; 17extern struct sys_timer davinci_timer;
18 18
19extern void davinci_irq_init(void); 19extern void davinci_irq_init(void);
20extern void __iomem *davinci_intc_base;
20 21
21/* parameters describe VBUS sourcing for host mode */ 22/* parameters describe VBUS sourcing for host mode */
22extern void setup_usb(unsigned mA, unsigned potpgt_msec); 23extern void setup_usb(unsigned mA, unsigned potpgt_msec);
@@ -39,6 +40,10 @@ struct davinci_soc_info {
39 void __iomem *pinmux_base; 40 void __iomem *pinmux_base;
40 const struct mux_config *pinmux_pins; 41 const struct mux_config *pinmux_pins;
41 unsigned long pinmux_pins_num; 42 unsigned long pinmux_pins_num;
43 void __iomem *intc_base;
44 int intc_type;
45 u8 *intc_irq_prios;
46 unsigned long intc_irq_num;
42}; 47};
43 48
44extern struct davinci_soc_info davinci_soc_info; 49extern struct davinci_soc_info davinci_soc_info;
diff --git a/arch/arm/mach-davinci/include/mach/entry-macro.S b/arch/arm/mach-davinci/include/mach/entry-macro.S
index 0ebb44545050..ed78851fe4ae 100644
--- a/arch/arm/mach-davinci/include/mach/entry-macro.S
+++ b/arch/arm/mach-davinci/include/mach/entry-macro.S
@@ -15,7 +15,8 @@
15 .endm 15 .endm
16 16
17 .macro get_irqnr_preamble, base, tmp 17 .macro get_irqnr_preamble, base, tmp
18 ldr \base, =IO_ADDRESS(DAVINCI_ARM_INTC_BASE) 18 ldr \base, =davinci_intc_base
19 ldr \base, [\base]
19 .endm 20 .endm
20 21
21 .macro arch_ret_to_user, tmp1, tmp2 22 .macro arch_ret_to_user, tmp1, tmp2
diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h
index 18066074c995..bc5d6aaa69a3 100644
--- a/arch/arm/mach-davinci/include/mach/irqs.h
+++ b/arch/arm/mach-davinci/include/mach/irqs.h
@@ -30,6 +30,9 @@
30/* Base address */ 30/* Base address */
31#define DAVINCI_ARM_INTC_BASE 0x01C48000 31#define DAVINCI_ARM_INTC_BASE 0x01C48000
32 32
33#define DAVINCI_INTC_TYPE_AINTC 0
34#define DAVINCI_INTC_TYPE_CP_INTC 1
35
33/* Interrupt lines */ 36/* Interrupt lines */
34#define IRQ_VDINT0 0 37#define IRQ_VDINT0 0
35#define IRQ_VDINT1 1 38#define IRQ_VDINT1 1
diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c
index 5a324c90e291..af92ffee8471 100644
--- a/arch/arm/mach-davinci/irq.c
+++ b/arch/arm/mach-davinci/irq.c
@@ -26,6 +26,7 @@
26 26
27#include <mach/hardware.h> 27#include <mach/hardware.h>
28#include <mach/cputype.h> 28#include <mach/cputype.h>
29#include <mach/common.h>
29#include <asm/mach/irq.h> 30#include <asm/mach/irq.h>
30 31
31#define IRQ_BIT(irq) ((irq) & 0x1f) 32#define IRQ_BIT(irq) ((irq) & 0x1f)
@@ -41,18 +42,14 @@
41#define IRQ_INTPRI0_REG_OFFSET 0x0030 42#define IRQ_INTPRI0_REG_OFFSET 0x0030
42#define IRQ_INTPRI7_REG_OFFSET 0x004C 43#define IRQ_INTPRI7_REG_OFFSET 0x004C
43 44
44const u8 *davinci_def_priorities;
45
46#define INTC_BASE IO_ADDRESS(DAVINCI_ARM_INTC_BASE)
47
48static inline unsigned int davinci_irq_readl(int offset) 45static inline unsigned int davinci_irq_readl(int offset)
49{ 46{
50 return __raw_readl(INTC_BASE + offset); 47 return __raw_readl(davinci_intc_base + offset);
51} 48}
52 49
53static inline void davinci_irq_writel(unsigned long value, int offset) 50static inline void davinci_irq_writel(unsigned long value, int offset)
54{ 51{
55 __raw_writel(value, INTC_BASE + offset); 52 __raw_writel(value, davinci_intc_base + offset);
56} 53}
57 54
58/* Disable interrupt */ 55/* Disable interrupt */
@@ -113,217 +110,11 @@ static struct irq_chip davinci_irq_chip_0 = {
113 .unmask = davinci_unmask_irq, 110 .unmask = davinci_unmask_irq,
114}; 111};
115 112
116/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
117static const u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] __initdata = {
118 [IRQ_VDINT0] = 2,
119 [IRQ_VDINT1] = 6,
120 [IRQ_VDINT2] = 6,
121 [IRQ_HISTINT] = 6,
122 [IRQ_H3AINT] = 6,
123 [IRQ_PRVUINT] = 6,
124 [IRQ_RSZINT] = 6,
125 [7] = 7,
126 [IRQ_VENCINT] = 6,
127 [IRQ_ASQINT] = 6,
128 [IRQ_IMXINT] = 6,
129 [IRQ_VLCDINT] = 6,
130 [IRQ_USBINT] = 4,
131 [IRQ_EMACINT] = 4,
132 [14] = 7,
133 [15] = 7,
134 [IRQ_CCINT0] = 5, /* dma */
135 [IRQ_CCERRINT] = 5, /* dma */
136 [IRQ_TCERRINT0] = 5, /* dma */
137 [IRQ_TCERRINT] = 5, /* dma */
138 [IRQ_PSCIN] = 7,
139 [21] = 7,
140 [IRQ_IDE] = 4,
141 [23] = 7,
142 [IRQ_MBXINT] = 7,
143 [IRQ_MBRINT] = 7,
144 [IRQ_MMCINT] = 7,
145 [IRQ_SDIOINT] = 7,
146 [28] = 7,
147 [IRQ_DDRINT] = 7,
148 [IRQ_AEMIFINT] = 7,
149 [IRQ_VLQINT] = 4,
150 [IRQ_TINT0_TINT12] = 2, /* clockevent */
151 [IRQ_TINT0_TINT34] = 2, /* clocksource */
152 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
153 [IRQ_TINT1_TINT34] = 7, /* system tick */
154 [IRQ_PWMINT0] = 7,
155 [IRQ_PWMINT1] = 7,
156 [IRQ_PWMINT2] = 7,
157 [IRQ_I2C] = 3,
158 [IRQ_UARTINT0] = 3,
159 [IRQ_UARTINT1] = 3,
160 [IRQ_UARTINT2] = 3,
161 [IRQ_SPINT0] = 3,
162 [IRQ_SPINT1] = 3,
163 [45] = 7,
164 [IRQ_DSP2ARM0] = 4,
165 [IRQ_DSP2ARM1] = 4,
166 [IRQ_GPIO0] = 7,
167 [IRQ_GPIO1] = 7,
168 [IRQ_GPIO2] = 7,
169 [IRQ_GPIO3] = 7,
170 [IRQ_GPIO4] = 7,
171 [IRQ_GPIO5] = 7,
172 [IRQ_GPIO6] = 7,
173 [IRQ_GPIO7] = 7,
174 [IRQ_GPIOBNK0] = 7,
175 [IRQ_GPIOBNK1] = 7,
176 [IRQ_GPIOBNK2] = 7,
177 [IRQ_GPIOBNK3] = 7,
178 [IRQ_GPIOBNK4] = 7,
179 [IRQ_COMMTX] = 7,
180 [IRQ_COMMRX] = 7,
181 [IRQ_EMUINT] = 7,
182};
183
184static const u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
185 [IRQ_DM646X_VP_VERTINT0] = 7,
186 [IRQ_DM646X_VP_VERTINT1] = 7,
187 [IRQ_DM646X_VP_VERTINT2] = 7,
188 [IRQ_DM646X_VP_VERTINT3] = 7,
189 [IRQ_DM646X_VP_ERRINT] = 7,
190 [IRQ_DM646X_RESERVED_1] = 7,
191 [IRQ_DM646X_RESERVED_2] = 7,
192 [IRQ_DM646X_WDINT] = 7,
193 [IRQ_DM646X_CRGENINT0] = 7,
194 [IRQ_DM646X_CRGENINT1] = 7,
195 [IRQ_DM646X_TSIFINT0] = 7,
196 [IRQ_DM646X_TSIFINT1] = 7,
197 [IRQ_DM646X_VDCEINT] = 7,
198 [IRQ_DM646X_USBINT] = 7,
199 [IRQ_DM646X_USBDMAINT] = 7,
200 [IRQ_DM646X_PCIINT] = 7,
201 [IRQ_CCINT0] = 7, /* dma */
202 [IRQ_CCERRINT] = 7, /* dma */
203 [IRQ_TCERRINT0] = 7, /* dma */
204 [IRQ_TCERRINT] = 7, /* dma */
205 [IRQ_DM646X_TCERRINT2] = 7,
206 [IRQ_DM646X_TCERRINT3] = 7,
207 [IRQ_DM646X_IDE] = 7,
208 [IRQ_DM646X_HPIINT] = 7,
209 [IRQ_DM646X_EMACRXTHINT] = 7,
210 [IRQ_DM646X_EMACRXINT] = 7,
211 [IRQ_DM646X_EMACTXINT] = 7,
212 [IRQ_DM646X_EMACMISCINT] = 7,
213 [IRQ_DM646X_MCASP0TXINT] = 7,
214 [IRQ_DM646X_MCASP0RXINT] = 7,
215 [IRQ_AEMIFINT] = 7,
216 [IRQ_DM646X_RESERVED_3] = 7,
217 [IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */
218 [IRQ_TINT0_TINT34] = 7, /* clocksource */
219 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
220 [IRQ_TINT1_TINT34] = 7, /* system tick */
221 [IRQ_PWMINT0] = 7,
222 [IRQ_PWMINT1] = 7,
223 [IRQ_DM646X_VLQINT] = 7,
224 [IRQ_I2C] = 7,
225 [IRQ_UARTINT0] = 7,
226 [IRQ_UARTINT1] = 7,
227 [IRQ_DM646X_UARTINT2] = 7,
228 [IRQ_DM646X_SPINT0] = 7,
229 [IRQ_DM646X_SPINT1] = 7,
230 [IRQ_DM646X_DSP2ARMINT] = 7,
231 [IRQ_DM646X_RESERVED_4] = 7,
232 [IRQ_DM646X_PSCINT] = 7,
233 [IRQ_DM646X_GPIO0] = 7,
234 [IRQ_DM646X_GPIO1] = 7,
235 [IRQ_DM646X_GPIO2] = 7,
236 [IRQ_DM646X_GPIO3] = 7,
237 [IRQ_DM646X_GPIO4] = 7,
238 [IRQ_DM646X_GPIO5] = 7,
239 [IRQ_DM646X_GPIO6] = 7,
240 [IRQ_DM646X_GPIO7] = 7,
241 [IRQ_DM646X_GPIOBNK0] = 7,
242 [IRQ_DM646X_GPIOBNK1] = 7,
243 [IRQ_DM646X_GPIOBNK2] = 7,
244 [IRQ_DM646X_DDRINT] = 7,
245 [IRQ_DM646X_AEMIFINT] = 7,
246 [IRQ_COMMTX] = 7,
247 [IRQ_COMMRX] = 7,
248 [IRQ_EMUINT] = 7,
249};
250
251static const u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
252 [IRQ_DM355_CCDC_VDINT0] = 2,
253 [IRQ_DM355_CCDC_VDINT1] = 6,
254 [IRQ_DM355_CCDC_VDINT2] = 6,
255 [IRQ_DM355_IPIPE_HST] = 6,
256 [IRQ_DM355_H3AINT] = 6,
257 [IRQ_DM355_IPIPE_SDR] = 6,
258 [IRQ_DM355_IPIPEIFINT] = 6,
259 [IRQ_DM355_OSDINT] = 7,
260 [IRQ_DM355_VENCINT] = 6,
261 [IRQ_ASQINT] = 6,
262 [IRQ_IMXINT] = 6,
263 [IRQ_USBINT] = 4,
264 [IRQ_DM355_RTOINT] = 4,
265 [IRQ_DM355_UARTINT2] = 7,
266 [IRQ_DM355_TINT6] = 7,
267 [IRQ_CCINT0] = 5, /* dma */
268 [IRQ_CCERRINT] = 5, /* dma */
269 [IRQ_TCERRINT0] = 5, /* dma */
270 [IRQ_TCERRINT] = 5, /* dma */
271 [IRQ_DM355_SPINT2_1] = 7,
272 [IRQ_DM355_TINT7] = 4,
273 [IRQ_DM355_SDIOINT0] = 7,
274 [IRQ_MBXINT] = 7,
275 [IRQ_MBRINT] = 7,
276 [IRQ_MMCINT] = 7,
277 [IRQ_DM355_MMCINT1] = 7,
278 [IRQ_DM355_PWMINT3] = 7,
279 [IRQ_DDRINT] = 7,
280 [IRQ_AEMIFINT] = 7,
281 [IRQ_DM355_SDIOINT1] = 4,
282 [IRQ_TINT0_TINT12] = 2, /* clockevent */
283 [IRQ_TINT0_TINT34] = 2, /* clocksource */
284 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
285 [IRQ_TINT1_TINT34] = 7, /* system tick */
286 [IRQ_PWMINT0] = 7,
287 [IRQ_PWMINT1] = 7,
288 [IRQ_PWMINT2] = 7,
289 [IRQ_I2C] = 3,
290 [IRQ_UARTINT0] = 3,
291 [IRQ_UARTINT1] = 3,
292 [IRQ_DM355_SPINT0_0] = 3,
293 [IRQ_DM355_SPINT0_1] = 3,
294 [IRQ_DM355_GPIO0] = 3,
295 [IRQ_DM355_GPIO1] = 7,
296 [IRQ_DM355_GPIO2] = 4,
297 [IRQ_DM355_GPIO3] = 4,
298 [IRQ_DM355_GPIO4] = 7,
299 [IRQ_DM355_GPIO5] = 7,
300 [IRQ_DM355_GPIO6] = 7,
301 [IRQ_DM355_GPIO7] = 7,
302 [IRQ_DM355_GPIO8] = 7,
303 [IRQ_DM355_GPIO9] = 7,
304 [IRQ_DM355_GPIOBNK0] = 7,
305 [IRQ_DM355_GPIOBNK1] = 7,
306 [IRQ_DM355_GPIOBNK2] = 7,
307 [IRQ_DM355_GPIOBNK3] = 7,
308 [IRQ_DM355_GPIOBNK4] = 7,
309 [IRQ_DM355_GPIOBNK5] = 7,
310 [IRQ_DM355_GPIOBNK6] = 7,
311 [IRQ_COMMTX] = 7,
312 [IRQ_COMMRX] = 7,
313 [IRQ_EMUINT] = 7,
314};
315
316/* ARM Interrupt Controller Initialization */ 113/* ARM Interrupt Controller Initialization */
317void __init davinci_irq_init(void) 114void __init davinci_irq_init(void)
318{ 115{
319 unsigned i; 116 unsigned i;
320 117 const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios;
321 if (cpu_is_davinci_dm644x())
322 davinci_def_priorities = dm644x_default_priorities;
323 else if (cpu_is_davinci_dm646x())
324 davinci_def_priorities = dm646x_default_priorities;
325 else if (cpu_is_davinci_dm355())
326 davinci_def_priorities = dm355_default_priorities;
327 118
328 /* Clear all interrupt requests */ 119 /* Clear all interrupt requests */
329 davinci_irq_writel(~0x0, FIQ_REG0_OFFSET); 120 davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-25 00:54:51 -0500