diff options
author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2011-11-14 01:24:53 -0500 |
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committer | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2011-11-28 09:50:39 -0500 |
commit | d28bdfc5c80fb64bf50824920bf9b554732dec74 (patch) | |
tree | 2f2ce017d27c0094a8a1561d532f73f50a4156fe /arch/arm/mach-at91/include/mach/at91sam9rl.h | |
parent | be6d4321720cd56623c1d5be311bde65c2c91229 (diff) |
ARM: at91: make rm9200 rtc drivers soc independent
switch the rtc drivers to resource and pass it via platform_device
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch/arm/mach-at91/include/mach/at91sam9rl.h')
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91sam9rl.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h index c466e8c898ad..2bb359e60b97 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9rl.h +++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h | |||
@@ -75,7 +75,6 @@ | |||
75 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | 75 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) |
76 | #define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) | 76 | #define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) |
77 | #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) | 77 | #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) |
78 | #define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) | ||
79 | 78 | ||
80 | #define AT91SAM9RL_BASE_DMA 0xffffe600 | 79 | #define AT91SAM9RL_BASE_DMA 0xffffe600 |
81 | #define AT91SAM9RL_BASE_ECC 0xffffe800 | 80 | #define AT91SAM9RL_BASE_ECC 0xffffe800 |
@@ -89,6 +88,7 @@ | |||
89 | #define AT91SAM9RL_BASE_RTT 0xfffffd20 | 88 | #define AT91SAM9RL_BASE_RTT 0xfffffd20 |
90 | #define AT91SAM9RL_BASE_PIT 0xfffffd30 | 89 | #define AT91SAM9RL_BASE_PIT 0xfffffd30 |
91 | #define AT91SAM9RL_BASE_WDT 0xfffffd40 | 90 | #define AT91SAM9RL_BASE_WDT 0xfffffd40 |
91 | #define AT91SAM9RL_BASE_RTC 0xfffffe00 | ||
92 | 92 | ||
93 | #define AT91_USART0 AT91SAM9RL_BASE_US0 | 93 | #define AT91_USART0 AT91SAM9RL_BASE_US0 |
94 | #define AT91_USART1 AT91SAM9RL_BASE_US1 | 94 | #define AT91_USART1 AT91SAM9RL_BASE_US1 |