diff options
| author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2012-02-12 23:58:53 -0500 |
|---|---|---|
| committer | Nicolas Ferre <nicolas.ferre@atmel.com> | 2012-02-23 08:57:56 -0500 |
| commit | f363c407b42c467d06675c852e55f26adb959915 (patch) | |
| tree | 695ffaf47ee7db5adfa9dd23976b5df77bd738c5 /arch/arm/mach-at91/include/mach/at91rm9200_mc.h | |
| parent | 1a269ade22bb65d0afc0d20e0a19602453fae04a (diff) | |
ARM: at91: make sdram/ddr register base soc independent
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch/arm/mach-at91/include/mach/at91rm9200_mc.h')
| -rw-r--r-- | arch/arm/mach-at91/include/mach/at91rm9200_mc.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h b/arch/arm/mach-at91/include/mach/at91rm9200_mc.h index 0eb031b70451..aeaadfb452af 100644 --- a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h +++ b/arch/arm/mach-at91/include/mach/at91rm9200_mc.h | |||
| @@ -17,10 +17,10 @@ | |||
| 17 | #define AT91RM9200_MC_H | 17 | #define AT91RM9200_MC_H |
| 18 | 18 | ||
| 19 | /* Memory Controller */ | 19 | /* Memory Controller */ |
| 20 | #define AT91_MC_RCR (AT91_MC + 0x00) /* MC Remap Control Register */ | 20 | #define AT91_MC_RCR 0x00 /* MC Remap Control Register */ |
| 21 | #define AT91_MC_RCB (1 << 0) /* Remap Command Bit */ | 21 | #define AT91_MC_RCB (1 << 0) /* Remap Command Bit */ |
| 22 | 22 | ||
| 23 | #define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */ | 23 | #define AT91_MC_ASR 0x04 /* MC Abort Status Register */ |
| 24 | #define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */ | 24 | #define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */ |
| 25 | #define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */ | 25 | #define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */ |
| 26 | #define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */ | 26 | #define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */ |
| @@ -40,16 +40,16 @@ | |||
| 40 | #define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */ | 40 | #define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */ |
| 41 | #define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */ | 41 | #define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */ |
| 42 | 42 | ||
| 43 | #define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */ | 43 | #define AT91_MC_AASR 0x08 /* MC Abort Address Status Register */ |
| 44 | 44 | ||
| 45 | #define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */ | 45 | #define AT91_MC_MPR 0x0c /* MC Master Priority Register */ |
| 46 | #define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */ | 46 | #define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */ |
| 47 | #define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */ | 47 | #define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */ |
| 48 | #define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */ | 48 | #define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */ |
| 49 | #define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */ | 49 | #define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */ |
| 50 | 50 | ||
| 51 | /* External Bus Interface (EBI) registers */ | 51 | /* External Bus Interface (EBI) registers */ |
| 52 | #define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */ | 52 | #define AT91_EBI_CSA 0x60 /* Chip Select Assignment Register */ |
| 53 | #define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */ | 53 | #define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */ |
| 54 | #define AT91_EBI_CS0A_SMC (0 << 0) | 54 | #define AT91_EBI_CS0A_SMC (0 << 0) |
| 55 | #define AT91_EBI_CS0A_BFC (1 << 0) | 55 | #define AT91_EBI_CS0A_BFC (1 << 0) |
| @@ -66,7 +66,7 @@ | |||
| 66 | #define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */ | 66 | #define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */ |
| 67 | 67 | ||
| 68 | /* Static Memory Controller (SMC) registers */ | 68 | /* Static Memory Controller (SMC) registers */ |
| 69 | #define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */ | 69 | #define AT91_SMC_CSR(n) (0x70 + ((n) * 4)) /* SMC Chip Select Register */ |
| 70 | #define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */ | 70 | #define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */ |
| 71 | #define AT91_SMC_NWS_(x) ((x) << 0) | 71 | #define AT91_SMC_NWS_(x) ((x) << 0) |
| 72 | #define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */ | 72 | #define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */ |
| @@ -88,7 +88,7 @@ | |||
| 88 | #define AT91_SMC_RWHOLD_(x) ((x) << 28) | 88 | #define AT91_SMC_RWHOLD_(x) ((x) << 28) |
| 89 | 89 | ||
| 90 | /* Burst Flash Controller register */ | 90 | /* Burst Flash Controller register */ |
| 91 | #define AT91_BFC_MR (AT91_MC + 0xc0) /* Mode Register */ | 91 | #define AT91_BFC_MR 0xc0 /* Mode Register */ |
| 92 | #define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */ | 92 | #define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */ |
| 93 | #define AT91_BFC_BFCOM_DISABLED (0 << 0) | 93 | #define AT91_BFC_BFCOM_DISABLED (0 << 0) |
| 94 | #define AT91_BFC_BFCOM_ASYNC (1 << 0) | 94 | #define AT91_BFC_BFCOM_ASYNC (1 << 0) |