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authorJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2012-02-12 23:58:53 -0500
committerNicolas Ferre <nicolas.ferre@atmel.com>2012-02-23 08:57:56 -0500
commitf363c407b42c467d06675c852e55f26adb959915 (patch)
tree695ffaf47ee7db5adfa9dd23976b5df77bd738c5 /arch/arm/mach-at91/include
parent1a269ade22bb65d0afc0d20e0a19602453fae04a (diff)
ARM: at91: make sdram/ddr register base soc independent
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch/arm/mach-at91/include')
-rw-r--r--arch/arm/mach-at91/include/mach/at91_ramc.h31
-rw-r--r--arch/arm/mach-at91/include/mach/at91rm9200.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91rm9200_mc.h14
-rw-r--r--arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h18
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9260.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9261.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9263.h4
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h6
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9_sdramc.h6
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9g45.h4
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9rl.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9x5.h2
12 files changed, 56 insertions, 37 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91_ramc.h b/arch/arm/mach-at91/include/mach/at91_ramc.h
new file mode 100644
index 000000000000..3155499e2ea3
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_ramc.h
@@ -0,0 +1,31 @@
1/*
2 * Header file for the Atmel RAM Controller
3 *
4 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Under GPLv2 only
7 */
8
9#ifndef __AT91_RAMC_H__
10#define __AT91_RAMC_H__
11
12#ifndef __ASSEMBLY__
13extern void __iomem *at91_ramc_base[];
14
15#define at91_ramc_read(id, field) \
16 __raw_readl(at91_ramc_base[id] + field)
17
18#define at91_ramc_write(id, field, value) \
19 __raw_writel(value, at91_ramc_base[id] + field)
20#else
21.extern at91_ramc_base
22#endif
23
24#ifdef CONFIG_ARCH_AT91RM9200
25#include <mach/at91rm9200_mc.h>
26#else
27#include <mach/at91sam9_ddrsdr.h>
28#include <mach/at91sam9_sdramc.h>
29#endif
30
31#endif /* __AT91_RAMC_H__ */
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h
index 0d0b9b3d2fe4..32d57be47986 100644
--- a/arch/arm/mach-at91/include/mach/at91rm9200.h
+++ b/arch/arm/mach-at91/include/mach/at91rm9200.h
@@ -80,7 +80,6 @@
80 * System Peripherals (offset from AT91_BASE_SYS) 80 * System Peripherals (offset from AT91_BASE_SYS)
81 */ 81 */
82#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) /* Power Management Controller */ 82#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) /* Power Management Controller */
83#define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */
84 83
85#define AT91RM9200_BASE_DBGU AT91_BASE_DBGU0 /* Debug Unit */ 84#define AT91RM9200_BASE_DBGU AT91_BASE_DBGU0 /* Debug Unit */
86#define AT91RM9200_BASE_PIOA 0xfffff400 /* PIO Controller A */ 85#define AT91RM9200_BASE_PIOA 0xfffff400 /* PIO Controller A */
@@ -89,6 +88,7 @@
89#define AT91RM9200_BASE_PIOD 0xfffffa00 /* PIO Controller D */ 88#define AT91RM9200_BASE_PIOD 0xfffffa00 /* PIO Controller D */
90#define AT91RM9200_BASE_ST 0xfffffd00 /* System Timer */ 89#define AT91RM9200_BASE_ST 0xfffffd00 /* System Timer */
91#define AT91RM9200_BASE_RTC 0xfffffe00 /* Real-Time Clock */ 90#define AT91RM9200_BASE_RTC 0xfffffe00 /* Real-Time Clock */
91#define AT91RM9200_BASE_MC 0xffffff00 /* Memory Controllers */
92 92
93#define AT91_USART0 AT91RM9200_BASE_US0 93#define AT91_USART0 AT91RM9200_BASE_US0
94#define AT91_USART1 AT91RM9200_BASE_US1 94#define AT91_USART1 AT91RM9200_BASE_US1
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h b/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
index 0eb031b70451..aeaadfb452af 100644
--- a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
+++ b/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
@@ -17,10 +17,10 @@
17#define AT91RM9200_MC_H 17#define AT91RM9200_MC_H
18 18
19/* Memory Controller */ 19/* Memory Controller */
20#define AT91_MC_RCR (AT91_MC + 0x00) /* MC Remap Control Register */ 20#define AT91_MC_RCR 0x00 /* MC Remap Control Register */
21#define AT91_MC_RCB (1 << 0) /* Remap Command Bit */ 21#define AT91_MC_RCB (1 << 0) /* Remap Command Bit */
22 22
23#define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */ 23#define AT91_MC_ASR 0x04 /* MC Abort Status Register */
24#define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */ 24#define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */
25#define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */ 25#define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */
26#define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */ 26#define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */
@@ -40,16 +40,16 @@
40#define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */ 40#define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */
41#define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */ 41#define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */
42 42
43#define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */ 43#define AT91_MC_AASR 0x08 /* MC Abort Address Status Register */
44 44
45#define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */ 45#define AT91_MC_MPR 0x0c /* MC Master Priority Register */
46#define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */ 46#define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */
47#define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */ 47#define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */
48#define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */ 48#define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */
49#define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */ 49#define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */
50 50
51/* External Bus Interface (EBI) registers */ 51/* External Bus Interface (EBI) registers */
52#define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */ 52#define AT91_EBI_CSA 0x60 /* Chip Select Assignment Register */
53#define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */ 53#define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */
54#define AT91_EBI_CS0A_SMC (0 << 0) 54#define AT91_EBI_CS0A_SMC (0 << 0)
55#define AT91_EBI_CS0A_BFC (1 << 0) 55#define AT91_EBI_CS0A_BFC (1 << 0)
@@ -66,7 +66,7 @@
66#define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */ 66#define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */
67 67
68/* Static Memory Controller (SMC) registers */ 68/* Static Memory Controller (SMC) registers */
69#define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */ 69#define AT91_SMC_CSR(n) (0x70 + ((n) * 4)) /* SMC Chip Select Register */
70#define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */ 70#define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */
71#define AT91_SMC_NWS_(x) ((x) << 0) 71#define AT91_SMC_NWS_(x) ((x) << 0)
72#define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */ 72#define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */
@@ -88,7 +88,7 @@
88#define AT91_SMC_RWHOLD_(x) ((x) << 28) 88#define AT91_SMC_RWHOLD_(x) ((x) << 28)
89 89
90/* Burst Flash Controller register */ 90/* Burst Flash Controller register */
91#define AT91_BFC_MR (AT91_MC + 0xc0) /* Mode Register */ 91#define AT91_BFC_MR 0xc0 /* Mode Register */
92#define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */ 92#define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */
93#define AT91_BFC_BFCOM_DISABLED (0 << 0) 93#define AT91_BFC_BFCOM_DISABLED (0 << 0)
94#define AT91_BFC_BFCOM_ASYNC (1 << 0) 94#define AT91_BFC_BFCOM_ASYNC (1 << 0)
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h b/arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
index 7ad3597e6c4b..aa047f458f1b 100644
--- a/arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
+++ b/arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
@@ -17,7 +17,7 @@
17#define AT91RM9200_SDRAMC_H 17#define AT91RM9200_SDRAMC_H
18 18
19/* SDRAM Controller registers */ 19/* SDRAM Controller registers */
20#define AT91RM9200_SDRAMC_MR (AT91_MC + 0x90) /* Mode Register */ 20#define AT91RM9200_SDRAMC_MR 0x90 /* Mode Register */
21#define AT91RM9200_SDRAMC_MODE (0xf << 0) /* Command Mode */ 21#define AT91RM9200_SDRAMC_MODE (0xf << 0) /* Command Mode */
22#define AT91RM9200_SDRAMC_MODE_NORMAL (0 << 0) 22#define AT91RM9200_SDRAMC_MODE_NORMAL (0 << 0)
23#define AT91RM9200_SDRAMC_MODE_NOP (1 << 0) 23#define AT91RM9200_SDRAMC_MODE_NOP (1 << 0)
@@ -28,10 +28,10 @@
28#define AT91RM9200_SDRAMC_DBW_32 (0 << 4) 28#define AT91RM9200_SDRAMC_DBW_32 (0 << 4)
29#define AT91RM9200_SDRAMC_DBW_16 (1 << 4) 29#define AT91RM9200_SDRAMC_DBW_16 (1 << 4)
30 30
31#define AT91RM9200_SDRAMC_TR (AT91_MC + 0x94) /* Refresh Timer Register */ 31#define AT91RM9200_SDRAMC_TR 0x94 /* Refresh Timer Register */
32#define AT91RM9200_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */ 32#define AT91RM9200_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */
33 33
34#define AT91RM9200_SDRAMC_CR (AT91_MC + 0x98) /* Configuration Register */ 34#define AT91RM9200_SDRAMC_CR 0x98 /* Configuration Register */
35#define AT91RM9200_SDRAMC_NC (3 << 0) /* Number of Column Bits */ 35#define AT91RM9200_SDRAMC_NC (3 << 0) /* Number of Column Bits */
36#define AT91RM9200_SDRAMC_NC_8 (0 << 0) 36#define AT91RM9200_SDRAMC_NC_8 (0 << 0)
37#define AT91RM9200_SDRAMC_NC_9 (1 << 0) 37#define AT91RM9200_SDRAMC_NC_9 (1 << 0)
@@ -53,11 +53,11 @@
53#define AT91RM9200_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */ 53#define AT91RM9200_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */
54#define AT91RM9200_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */ 54#define AT91RM9200_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */
55 55
56#define AT91RM9200_SDRAMC_SRR (AT91_MC + 0x9c) /* Self Refresh Register */ 56#define AT91RM9200_SDRAMC_SRR 0x9c /* Self Refresh Register */
57#define AT91RM9200_SDRAMC_LPR (AT91_MC + 0xa0) /* Low Power Register */ 57#define AT91RM9200_SDRAMC_LPR 0xa0 /* Low Power Register */
58#define AT91RM9200_SDRAMC_IER (AT91_MC + 0xa4) /* Interrupt Enable Register */ 58#define AT91RM9200_SDRAMC_IER 0xa4 /* Interrupt Enable Register */
59#define AT91RM9200_SDRAMC_IDR (AT91_MC + 0xa8) /* Interrupt Disable Register */ 59#define AT91RM9200_SDRAMC_IDR 0xa8 /* Interrupt Disable Register */
60#define AT91RM9200_SDRAMC_IMR (AT91_MC + 0xac) /* Interrupt Mask Register */ 60#define AT91RM9200_SDRAMC_IMR 0xac /* Interrupt Mask Register */
61#define AT91RM9200_SDRAMC_ISR (AT91_MC + 0xb0) /* Interrupt Status Register */ 61#define AT91RM9200_SDRAMC_ISR 0xb0 /* Interrupt Status Register */
62 62
63#endif 63#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index 2bde6496cd41..c5b6b3b71060 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -80,11 +80,11 @@
80/* 80/*
81 * System Peripherals (offset from AT91_BASE_SYS) 81 * System Peripherals (offset from AT91_BASE_SYS)
82 */ 82 */
83#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
84#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 83#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
85#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) 84#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
86 85
87#define AT91SAM9260_BASE_ECC 0xffffe800 86#define AT91SAM9260_BASE_ECC 0xffffe800
87#define AT91SAM9260_BASE_SDRAMC 0xffffea00
88#define AT91SAM9260_BASE_SMC 0xffffec00 88#define AT91SAM9260_BASE_SMC 0xffffec00
89#define AT91SAM9260_BASE_MATRIX 0xffffee00 89#define AT91SAM9260_BASE_MATRIX 0xffffee00
90#define AT91SAM9260_BASE_DBGU AT91_BASE_DBGU0 90#define AT91SAM9260_BASE_DBGU AT91_BASE_DBGU0
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index 6dcff277c023..a269cef51aec 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -65,12 +65,12 @@
65/* 65/*
66 * System Peripherals (offset from AT91_BASE_SYS) 66 * System Peripherals (offset from AT91_BASE_SYS)
67 */ 67 */
68#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
69#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 68#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
70#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) 69#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
71 70
72#define AT91SAM9261_BASE_SMC 0xffffec00 71#define AT91SAM9261_BASE_SMC 0xffffec00
73#define AT91SAM9261_BASE_MATRIX 0xffffee00 72#define AT91SAM9261_BASE_MATRIX 0xffffee00
73#define AT91SAM9261_BASE_SDRAMC 0xffffea00
74#define AT91SAM9261_BASE_DBGU AT91_BASE_DBGU0 74#define AT91SAM9261_BASE_DBGU AT91_BASE_DBGU0
75#define AT91SAM9261_BASE_PIOA 0xfffff400 75#define AT91SAM9261_BASE_PIOA 0xfffff400
76#define AT91SAM9261_BASE_PIOB 0xfffff600 76#define AT91SAM9261_BASE_PIOB 0xfffff600
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
index fe73bfa265e4..bccba0b679c2 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
@@ -74,14 +74,14 @@
74/* 74/*
75 * System Peripherals (offset from AT91_BASE_SYS) 75 * System Peripherals (offset from AT91_BASE_SYS)
76 */ 76 */
77#define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS)
78#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS)
79#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 77#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
80#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) 78#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
81 79
82#define AT91SAM9263_BASE_ECC0 0xffffe000 80#define AT91SAM9263_BASE_ECC0 0xffffe000
81#define AT91SAM9263_BASE_SDRAMC0 0xffffe200
83#define AT91SAM9263_BASE_SMC0 0xffffe400 82#define AT91SAM9263_BASE_SMC0 0xffffe400
84#define AT91SAM9263_BASE_ECC1 0xffffe600 83#define AT91SAM9263_BASE_ECC1 0xffffe600
84#define AT91SAM9263_BASE_SDRAMC1 0xffffe800
85#define AT91SAM9263_BASE_SMC1 0xffffea00 85#define AT91SAM9263_BASE_SMC1 0xffffea00
86#define AT91SAM9263_BASE_MATRIX 0xffffec00 86#define AT91SAM9263_BASE_MATRIX 0xffffec00
87#define AT91SAM9263_BASE_DBGU AT91_BASE_DBGU1 87#define AT91SAM9263_BASE_DBGU AT91_BASE_DBGU1
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
index 5d4a9f846584..0210797abf2e 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
@@ -121,10 +121,4 @@
121#define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */ 121#define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */
122#define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */ 122#define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */
123 123
124/* Register access macros */
125#define at91_ramc_read(num, reg) \
126 at91_sys_read(AT91_DDRSDRC##num + reg)
127#define at91_ramc_write(num, reg, value) \
128 at91_sys_write(AT91_DDRSDRC##num + reg, value)
129
130#endif 124#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
index 100f5a592926..3d085a9a7450 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
@@ -82,10 +82,4 @@
82#define AT91_SDRAMC_MD_SDRAM 0 82#define AT91_SDRAMC_MD_SDRAM 0
83#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 83#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
84 84
85/* Register access macros */
86#define at91_ramc_read(num, reg) \
87 at91_sys_read(AT91_SDRAMC##num + reg)
88#define at91_ramc_write(num, reg, value) \
89 at91_sys_write(AT91_SDRAMC##num + reg, value)
90
91#endif 85#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index c8fe455f631b..dfc4570fffe2 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -86,12 +86,12 @@
86/* 86/*
87 * System Peripherals (offset from AT91_BASE_SYS) 87 * System Peripherals (offset from AT91_BASE_SYS)
88 */ 88 */
89#define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS)
90#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
91#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 89#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
92#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) 90#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
93 91
94#define AT91SAM9G45_BASE_ECC 0xffffe200 92#define AT91SAM9G45_BASE_ECC 0xffffe200
93#define AT91SAM9G45_BASE_DDRSDRC1 0xffffe400
94#define AT91SAM9G45_BASE_DDRSDRC0 0xffffe600
95#define AT91SAM9G45_BASE_DMA 0xffffec00 95#define AT91SAM9G45_BASE_DMA 0xffffec00
96#define AT91SAM9G45_BASE_SMC 0xffffe800 96#define AT91SAM9G45_BASE_SMC 0xffffe800
97#define AT91SAM9G45_BASE_MATRIX 0xffffea00 97#define AT91SAM9G45_BASE_MATRIX 0xffffea00
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h
index 51edc25b466f..de960dc1da05 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9rl.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h
@@ -69,13 +69,13 @@
69/* 69/*
70 * System Peripherals (offset from AT91_BASE_SYS) 70 * System Peripherals (offset from AT91_BASE_SYS)
71 */ 71 */
72#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
73#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 72#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
74#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) 73#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
75#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) 74#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
76 75
77#define AT91SAM9RL_BASE_DMA 0xffffe600 76#define AT91SAM9RL_BASE_DMA 0xffffe600
78#define AT91SAM9RL_BASE_ECC 0xffffe800 77#define AT91SAM9RL_BASE_ECC 0xffffe800
78#define AT91SAM9RL_BASE_SDRAMC 0xffffea00
79#define AT91SAM9RL_BASE_SMC 0xffffec00 79#define AT91SAM9RL_BASE_SMC 0xffffec00
80#define AT91SAM9RL_BASE_MATRIX 0xffffee00 80#define AT91SAM9RL_BASE_MATRIX 0xffffee00
81#define AT91SAM9RL_BASE_DBGU AT91_BASE_DBGU0 81#define AT91SAM9RL_BASE_DBGU AT91_BASE_DBGU0
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
index 8476871a2f9f..96f25f556abf 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
@@ -57,7 +57,7 @@
57/* 57/*
58 * System Peripherals (offset from AT91_BASE_SYS) 58 * System Peripherals (offset from AT91_BASE_SYS)
59 */ 59 */
60#define AT91_DDRSDRC0 (0xffffe800 - AT91_BASE_SYS) 60#define AT91SAM9X5_BASE_DDRSDRC0 0xffffe800
61#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 61#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
62 62
63/* 63/*
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-10 03:32:49 -0400