diff options
| author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2012-02-12 23:58:53 -0500 |
|---|---|---|
| committer | Nicolas Ferre <nicolas.ferre@atmel.com> | 2012-02-23 08:57:56 -0500 |
| commit | f363c407b42c467d06675c852e55f26adb959915 (patch) | |
| tree | 695ffaf47ee7db5adfa9dd23976b5df77bd738c5 /arch/arm/mach-at91/include/mach/at91rm9200.h | |
| parent | 1a269ade22bb65d0afc0d20e0a19602453fae04a (diff) | |
ARM: at91: make sdram/ddr register base soc independent
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch/arm/mach-at91/include/mach/at91rm9200.h')
| -rw-r--r-- | arch/arm/mach-at91/include/mach/at91rm9200.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h index 0d0b9b3d2fe4..32d57be47986 100644 --- a/arch/arm/mach-at91/include/mach/at91rm9200.h +++ b/arch/arm/mach-at91/include/mach/at91rm9200.h | |||
| @@ -80,7 +80,6 @@ | |||
| 80 | * System Peripherals (offset from AT91_BASE_SYS) | 80 | * System Peripherals (offset from AT91_BASE_SYS) |
| 81 | */ | 81 | */ |
| 82 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) /* Power Management Controller */ | 82 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) /* Power Management Controller */ |
| 83 | #define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */ | ||
| 84 | 83 | ||
| 85 | #define AT91RM9200_BASE_DBGU AT91_BASE_DBGU0 /* Debug Unit */ | 84 | #define AT91RM9200_BASE_DBGU AT91_BASE_DBGU0 /* Debug Unit */ |
| 86 | #define AT91RM9200_BASE_PIOA 0xfffff400 /* PIO Controller A */ | 85 | #define AT91RM9200_BASE_PIOA 0xfffff400 /* PIO Controller A */ |
| @@ -89,6 +88,7 @@ | |||
| 89 | #define AT91RM9200_BASE_PIOD 0xfffffa00 /* PIO Controller D */ | 88 | #define AT91RM9200_BASE_PIOD 0xfffffa00 /* PIO Controller D */ |
| 90 | #define AT91RM9200_BASE_ST 0xfffffd00 /* System Timer */ | 89 | #define AT91RM9200_BASE_ST 0xfffffd00 /* System Timer */ |
| 91 | #define AT91RM9200_BASE_RTC 0xfffffe00 /* Real-Time Clock */ | 90 | #define AT91RM9200_BASE_RTC 0xfffffe00 /* Real-Time Clock */ |
| 91 | #define AT91RM9200_BASE_MC 0xffffff00 /* Memory Controllers */ | ||
| 92 | 92 | ||
| 93 | #define AT91_USART0 AT91RM9200_BASE_US0 | 93 | #define AT91_USART0 AT91RM9200_BASE_US0 |
| 94 | #define AT91_USART1 AT91RM9200_BASE_US1 | 94 | #define AT91_USART1 AT91RM9200_BASE_US1 |