Merge remote-tracking branch 'linus/master' into testing

33 files changed, 1105 insertions, 502 deletions

diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 5f3338eacad2..86d10dd47dc4 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -15,14 +15,20 @@ CFLAGS_REMOVE_return_address.o = -pg
 
 # Object file lists.
 
-obj-y           := elf.o entry-armv.o entry-common.o irq.o opcodes.o \
-                   process.o ptrace.o return_address.o sched_clock.o \
+obj-y           := elf.o entry-common.o irq.o opcodes.o \
+                   process.o ptrace.o return_address.o \
                    setup.o signal.o stacktrace.o sys_arm.o time.o traps.o
 
 obj-$(CONFIG_ATAGS)             += atags_parse.o
 obj-$(CONFIG_ATAGS_PROC)        += atags_proc.o
 obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) += atags_compat.o
 
+ifeq ($(CONFIG_CPU_V7M),y)
+obj-y           += entry-v7m.o
+else
+obj-y           += entry-armv.o
+endif
+
 obj-$(CONFIG_OC_ETM)            += etm.o
 obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
 obj-$(CONFIG_ISA_DMA_API)       += dma.o
@@ -32,7 +38,10 @@ obj-$(CONFIG_ARTHUR)		+= arthur.o
 obj-$(CONFIG_ISA_DMA)           += dma-isa.o
 obj-$(CONFIG_PCI)               += bios32.o isa.o
 obj-$(CONFIG_ARM_CPU_SUSPEND)   += sleep.o suspend.o
-obj-$(CONFIG_SMP)               += smp.o smp_tlb.o
+obj-$(CONFIG_SMP)               += smp.o
+ifdef CONFIG_MMU
+obj-$(CONFIG_SMP)               += smp_tlb.o
+endif
 obj-$(CONFIG_HAVE_ARM_SCU)      += smp_scu.o
 obj-$(CONFIG_HAVE_ARM_TWD)      += smp_twd.o
 obj-$(CONFIG_ARM_ARCH_TIMER)    += arch_timer.o
@@ -82,6 +91,9 @@ obj-$(CONFIG_DEBUG_LL)	+= debug.o
 obj-$(CONFIG_EARLY_PRINTK)      += early_printk.o
 
 obj-$(CONFIG_ARM_VIRT_EXT)      += hyp-stub.o
-obj-$(CONFIG_ARM_PSCI)          += psci.o
+ifeq ($(CONFIG_ARM_PSCI),y)
+obj-y                           += psci.o
+obj-$(CONFIG_SMP)               += psci_smp.o
+endif
 
 extra-y := $(head-y) vmlinux.lds
diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
index 59dcdced6e30..221f07b11ccb 100644
--- a/arch/arm/kernel/arch_timer.c
+++ b/arch/arm/kernel/arch_timer.c
@@ -11,9 +11,9 @@
 #include <linux/init.h>
 #include <linux/types.h>
 #include <linux/errno.h>
+#include <linux/sched_clock.h>
 
 #include <asm/delay.h>
-#include <asm/sched_clock.h>
 
 #include <clocksource/arm_arch_timer.h>
 
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index ee68cce6b48e..ded041711beb 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -23,6 +23,7 @@
 #include <asm/thread_info.h>
 #include <asm/memory.h>
 #include <asm/procinfo.h>
+#include <asm/suspend.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <linux/kbuild.h>
 
@@ -145,6 +146,11 @@ int main(void)
 #ifdef MULTI_CACHE
   DEFINE(CACHE_FLUSH_KERN_ALL,  offsetof(struct cpu_cache_fns, flush_kern_all));
 #endif
+#ifdef CONFIG_ARM_CPU_SUSPEND
+  DEFINE(SLEEP_SAVE_SP_SZ,      sizeof(struct sleep_save_sp));
+  DEFINE(SLEEP_SAVE_SP_PHYS,    offsetof(struct sleep_save_sp, save_ptr_stash_phys));
+  DEFINE(SLEEP_SAVE_SP_VIRT,    offsetof(struct sleep_save_sp, save_ptr_stash));
+#endif
   BLANK();
   DEFINE(DMA_BIDIRECTIONAL,     DMA_BIDIRECTIONAL);
   DEFINE(DMA_TO_DEVICE,         DMA_TO_DEVICE);
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index b2ed73c45489..261fcc826169 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -445,7 +445,8 @@ static int pcibios_init_resources(int busnr, struct pci_sys_data *sys)
         return 0;
 }
 
-static void pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
+static void pcibios_init_hw(struct device *parent, struct hw_pci *hw,
+                            struct list_head *head)
 {
         struct pci_sys_data *sys = NULL;
         int ret;
@@ -480,7 +481,7 @@ static void pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
                         if (hw->scan)
                                 sys->bus = hw->scan(nr, sys);
                         else
-                                sys->bus = pci_scan_root_bus(NULL, sys->busnr,
+                                sys->bus = pci_scan_root_bus(parent, sys->busnr,
                                                 hw->ops, sys, &sys->resources);
 
                         if (!sys->bus)
@@ -497,7 +498,7 @@ static void pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
         }
 }
 
-void pci_common_init(struct hw_pci *hw)
+void pci_common_init_dev(struct device *parent, struct hw_pci *hw)
 {
         struct pci_sys_data *sys;
         LIST_HEAD(head);
@@ -505,7 +506,7 @@ void pci_common_init(struct hw_pci *hw)
         pci_add_flags(PCI_REASSIGN_ALL_RSRC);
         if (hw->preinit)
                 hw->preinit();
-        pcibios_init_hw(hw, &head);
+        pcibios_init_hw(parent, hw, &head);
         if (hw->postinit)
                 hw->postinit();
 
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 582b405befc5..d40d0ef389db 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -685,15 +685,16 @@ ENTRY(__switch_to)
  UNWIND(.fnstart        )
  UNWIND(.cantunwind     )
         add     ip, r1, #TI_CPU_SAVE
-        ldr     r3, [r2, #TI_TP_VALUE]
  ARM(   stmia   ip!, {r4 - sl, fp, sp, lr} )    @ Store most regs on stack
  THUMB( stmia   ip!, {r4 - sl, fp}         )    @ Store most regs on stack
  THUMB( str     sp, [ip], #4               )
  THUMB( str     lr, [ip], #4               )
+        ldr     r4, [r2, #TI_TP_VALUE]
+        ldr     r5, [r2, #TI_TP_VALUE + 4]
 #ifdef CONFIG_CPU_USE_DOMAINS
         ldr     r6, [r2, #TI_CPU_DOMAIN]
 #endif
-        set_tls r3, r4, r5
+        switch_tls r1, r4, r5, r3, r7
 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
         ldr     r7, [r2, #TI_TASK]
         ldr     r8, =__stack_chk_guard
@@ -741,6 +742,18 @@ ENDPROC(__switch_to)
 #endif
         .endm
 
+        .macro  kuser_pad, sym, size
+        .if     (. - \sym) & 3
+        .rept   4 - (. - \sym) & 3
+        .byte   0
+        .endr
+        .endif
+        .rept   (\size - (. - \sym)) / 4
+        .word   0xe7fddef1
+        .endr
+        .endm
+
+#ifdef CONFIG_KUSER_HELPERS
         .align  5
         .globl  __kuser_helper_start
 __kuser_helper_start:
@@ -831,18 +844,13 @@ kuser_cmpxchg64_fixup:
 #error "incoherent kernel configuration"
 #endif
 
-        /* pad to next slot */
-        .rept   (16 - (. - __kuser_cmpxchg64)/4)
-        .word   0
-        .endr
-
-        .align  5
+        kuser_pad __kuser_cmpxchg64, 64
 
 __kuser_memory_barrier:                         @ 0xffff0fa0
         smp_dmb arm
         usr_ret lr
 
-        .align  5
+        kuser_pad __kuser_memory_barrier, 32
 
 __kuser_cmpxchg:                                @ 0xffff0fc0
 
@@ -915,13 +923,14 @@ kuser_cmpxchg32_fixup:
 
 #endif
 
-        .align  5
+        kuser_pad __kuser_cmpxchg, 32
 
 __kuser_get_tls:                                @ 0xffff0fe0
         ldr     r0, [pc, #(16 - 8)]     @ read TLS, set in kuser_get_tls_init
         usr_ret lr
         mrc     p15, 0, r0, c13, c0, 3  @ 0xffff0fe8 hardware TLS code
-        .rep    4
+        kuser_pad __kuser_get_tls, 16
+        .rep    3
         .word   0                       @ 0xffff0ff0 software TLS value, then
         .endr                           @ pad up to __kuser_helper_version
 
@@ -931,14 +940,16 @@ __kuser_helper_version:				@ 0xffff0ffc
         .globl  __kuser_helper_end
 __kuser_helper_end:
 
+#endif
+
  THUMB( .thumb  )
 
 /*
  * Vector stubs.
  *
- * This code is copied to 0xffff0200 so we can use branches in the
- * vectors, rather than ldr's.  Note that this code must not
- * exceed 0x300 bytes.
+ * This code is copied to 0xffff1000 so we can use branches in the
+ * vectors, rather than ldr's.  Note that this code must not exceed
+ * a page size.
  *
  * Common stub entry macro:
  *   Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
@@ -985,8 +996,17 @@ ENDPROC(vector_\name)
 1:
         .endm
 
-        .globl  __stubs_start
+        .section .stubs, "ax", %progbits
 __stubs_start:
+        @ This must be the first word
+        .word   vector_swi
+
+vector_rst:
+ ARM(   swi     SYS_ERROR0      )
+ THUMB( svc     #0              )
+ THUMB( nop                     )
+        b       vector_und
+
 /*
  * Interrupt dispatcher
  */
@@ -1081,6 +1101,16 @@ __stubs_start:
         .align  5
 
 /*=============================================================================
+ * Address exception handler
+ *-----------------------------------------------------------------------------
+ * These aren't too critical.
+ * (they're not supposed to happen, and won't happen in 32-bit data mode).
+ */
+
+vector_addrexcptn:
+        b       vector_addrexcptn
+
+/*=============================================================================
  * Undefined FIQs
  *-----------------------------------------------------------------------------
  * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
@@ -1093,45 +1123,19 @@ __stubs_start:
 vector_fiq:
         subs    pc, lr, #4
 
-/*=============================================================================
- * Address exception handler
- *-----------------------------------------------------------------------------
- * These aren't too critical.
- * (they're not supposed to happen, and won't happen in 32-bit data mode).
- */
-
-vector_addrexcptn:
-        b       vector_addrexcptn
-
-/*
- * We group all the following data together to optimise
- * for CPUs with separate I & D caches.
- */
-        .align  5
-
-.LCvswi:
-        .word   vector_swi
-
-        .globl  __stubs_end
-__stubs_end:
-
-        .equ    stubs_offset, __vectors_start + 0x200 - __stubs_start
+        .globl  vector_fiq_offset
+        .equ    vector_fiq_offset, vector_fiq
 
-        .globl  __vectors_start
+        .section .vectors, "ax", %progbits
 __vectors_start:
- ARM(   swi     SYS_ERROR0      )
- THUMB( svc     #0              )
- THUMB( nop                     )
-        W(b)    vector_und + stubs_offset
-        W(ldr)  pc, .LCvswi + stubs_offset
-        W(b)    vector_pabt + stubs_offset
-        W(b)    vector_dabt + stubs_offset
-        W(b)    vector_addrexcptn + stubs_offset
-        W(b)    vector_irq + stubs_offset
-        W(b)    vector_fiq + stubs_offset
-
-        .globl  __vectors_end
-__vectors_end:
+        W(b)    vector_rst
+        W(b)    vector_und
+        W(ldr)  pc, __vectors_start + 0x1000
+        W(b)    vector_pabt
+        W(b)    vector_dabt
+        W(b)    vector_addrexcptn
+        W(b)    vector_irq
+        W(b)    vector_fiq
 
         .data
 
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index bc5bc0a97131..94104bf69719 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -350,6 +350,9 @@ ENDPROC(ftrace_stub)
 
         .align  5
 ENTRY(vector_swi)
+#ifdef CONFIG_CPU_V7M
+        v7m_exception_entry
+#else
         sub     sp, sp, #S_FRAME_SIZE
         stmia   sp, {r0 - r12}                  @ Calling r0 - r12
  ARM(   add     r8, sp, #S_PC           )
@@ -360,8 +363,19 @@ ENTRY(vector_swi)
         str     lr, [sp, #S_PC]                 @ Save calling PC
         str     r8, [sp, #S_PSR]                @ Save CPSR
         str     r0, [sp, #S_OLD_R0]             @ Save OLD_R0
+#endif
         zero_fp
 
+#ifdef CONFIG_ALIGNMENT_TRAP
+        ldr     ip, __cr_alignment
+        ldr     ip, [ip]
+        mcr     p15, 0, ip, c1, c0              @ update control register
+#endif
+
+        enable_irq
+        ct_user_exit
+        get_thread_info tsk
+
         /*
          * Get the system call number.
          */
@@ -375,9 +389,9 @@ ENTRY(vector_swi)
 #ifdef CONFIG_ARM_THUMB
         tst     r8, #PSR_T_BIT
         movne   r10, #0                         @ no thumb OABI emulation
-        ldreq   r10, [lr, #-4]                  @ get SWI instruction
+ USER(  ldreq   r10, [lr, #-4]          )       @ get SWI instruction
 #else
-        ldr     r10, [lr, #-4]                  @ get SWI instruction
+ USER(  ldr     r10, [lr, #-4]          )       @ get SWI instruction
 #endif
 #ifdef CONFIG_CPU_ENDIAN_BE8
         rev     r10, r10                        @ little endian instruction
@@ -392,22 +406,13 @@ ENTRY(vector_swi)
         /* Legacy ABI only, possibly thumb mode. */
         tst     r8, #PSR_T_BIT                  @ this is SPSR from save_user_regs
         addne   scno, r7, #__NR_SYSCALL_BASE    @ put OS number in
-        ldreq   scno, [lr, #-4]
+ USER(  ldreq   scno, [lr, #-4]         )
 
 #else
         /* Legacy ABI only. */
-        ldr     scno, [lr, #-4]                 @ get SWI instruction
+ USER(  ldr     scno, [lr, #-4]         )       @ get SWI instruction
 #endif
 
-#ifdef CONFIG_ALIGNMENT_TRAP
-        ldr     ip, __cr_alignment
-        ldr     ip, [ip]
-        mcr     p15, 0, ip, c1, c0              @ update control register
-#endif
-        enable_irq
-        ct_user_exit
-
-        get_thread_info tsk
         adr     tbl, sys_call_table             @ load syscall table pointer
 
 #if defined(CONFIG_OABI_COMPAT)
@@ -442,6 +447,21 @@ local_restart:
         eor     r0, scno, #__NR_SYSCALL_BASE    @ put OS number back
         bcs     arm_syscall     
         b       sys_ni_syscall                  @ not private func
+
+#if defined(CONFIG_OABI_COMPAT) || !defined(CONFIG_AEABI)
+        /*
+         * We failed to handle a fault trying to access the page
+         * containing the swi instruction, but we're not really in a
+         * position to return -EFAULT. Instead, return back to the
+         * instruction and re-enter the user fault handling path trying
+         * to page it in. This will likely result in sending SEGV to the
+         * current task.
+         */
+9001:
+        sub     lr, lr, #4
+        str     lr, [sp, #S_PC]
+        b       ret_fast_syscall
+#endif
 ENDPROC(vector_swi)
 
         /*
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index 160f3376ba6d..de23a9beed13 100644
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
@@ -5,6 +5,7 @@
 #include <asm/asm-offsets.h>
 #include <asm/errno.h>
 #include <asm/thread_info.h>
+#include <asm/v7m.h>
 
 @ Bad Abort numbers
 @ -----------------
@@ -44,6 +45,116 @@
 #endif
         .endm
 
+#ifdef CONFIG_CPU_V7M
+/*
+ * ARMv7-M exception entry/exit macros.
+ *
+ * xPSR, ReturnAddress(), LR (R14), R12, R3, R2, R1, and R0 are
+ * automatically saved on the current stack (32 words) before
+ * switching to the exception stack (SP_main).
+ *
+ * If exception is taken while in user mode, SP_main is
+ * empty. Otherwise, SP_main is aligned to 64 bit automatically
+ * (CCR.STKALIGN set).
+ *
+ * Linux assumes that the interrupts are disabled when entering an
+ * exception handler and it may BUG if this is not the case. Interrupts
+ * are disabled during entry and reenabled in the exit macro.
+ *
+ * v7m_exception_slow_exit is used when returning from SVC or PendSV.
+ * When returning to kernel mode, we don't return from exception.
+ */
+        .macro  v7m_exception_entry
+        @ determine the location of the registers saved by the core during
+        @ exception entry. Depending on the mode the cpu was in when the
+        @ exception happend that is either on the main or the process stack.
+        @ Bit 2 of EXC_RETURN stored in the lr register specifies which stack
+        @ was used.
+        tst     lr, #EXC_RET_STACK_MASK
+        mrsne   r12, psp
+        moveq   r12, sp
+
+        @ we cannot rely on r0-r3 and r12 matching the value saved in the
+        @ exception frame because of tail-chaining. So these have to be
+        @ reloaded.
+        ldmia   r12!, {r0-r3}
+
+        @ Linux expects to have irqs off. Do it here before taking stack space
+        cpsid   i
+
+        sub     sp, #S_FRAME_SIZE-S_IP
+        stmdb   sp!, {r0-r11}
+
+        @ load saved r12, lr, return address and xPSR.
+        @ r0-r7 are used for signals and never touched from now on. Clobbering
+        @ r8-r12 is OK.
+        mov     r9, r12
+        ldmia   r9!, {r8, r10-r12}
+
+        @ calculate the original stack pointer value.
+        @ r9 currently points to the memory location just above the auto saved
+        @ xPSR.
+        @ The cpu might automatically 8-byte align the stack. Bit 9
+        @ of the saved xPSR specifies if stack aligning took place. In this case
+        @ another 32-bit value is included in the stack.
+
+        tst     r12, V7M_xPSR_FRAMEPTRALIGN
+        addne   r9, r9, #4
+
+        @ store saved r12 using str to have a register to hold the base for stm
+        str     r8, [sp, #S_IP]
+        add     r8, sp, #S_SP
+        @ store r13-r15, xPSR
+        stmia   r8!, {r9-r12}
+        @ store old_r0
+        str     r0, [r8]
+        .endm
+
+        /*
+         * PENDSV and SVCALL are configured to have the same exception
+         * priorities. As a kernel thread runs at SVCALL execution priority it
+         * can never be preempted and so we will never have to return to a
+         * kernel thread here.
+         */
+        .macro  v7m_exception_slow_exit ret_r0
+        cpsid   i
+        ldr     lr, =EXC_RET_THREADMODE_PROCESSSTACK
+
+        @ read original r12, sp, lr, pc and xPSR
+        add     r12, sp, #S_IP
+        ldmia   r12, {r1-r5}
+
+        @ an exception frame is always 8-byte aligned. To tell the hardware if
+        @ the sp to be restored is aligned or not set bit 9 of the saved xPSR
+        @ accordingly.
+        tst     r2, #4
+        subne   r2, r2, #4
+        orrne   r5, V7M_xPSR_FRAMEPTRALIGN
+        biceq   r5, V7M_xPSR_FRAMEPTRALIGN
+
+        @ write basic exception frame
+        stmdb   r2!, {r1, r3-r5}
+        ldmia   sp, {r1, r3-r5}
+        .if     \ret_r0
+        stmdb   r2!, {r0, r3-r5}
+        .else
+        stmdb   r2!, {r1, r3-r5}
+        .endif
+
+        @ restore process sp
+        msr     psp, r2
+
+        @ restore original r4-r11
+        ldmia   sp!, {r0-r11}
+
+        @ restore main sp
+        add     sp, sp, #S_FRAME_SIZE-S_IP
+
+        cpsie   i
+        bx      lr
+        .endm
+#endif  /* CONFIG_CPU_V7M */
+
         @
         @ Store/load the USER SP and LR registers by switching to the SYS
         @ mode. Useful in Thumb-2 mode where "stm/ldm rd, {sp, lr}^" is not
@@ -165,6 +276,18 @@
         rfeia   sp!
         .endm
 
+#ifdef CONFIG_CPU_V7M
+        /*
+         * Note we don't need to do clrex here as clearing the local monitor is
+         * part of each exception entry and exit sequence.
+         */
+        .macro  restore_user_regs, fast = 0, offset = 0
+        .if     \offset
+        add     sp, #\offset
+        .endif
+        v7m_exception_slow_exit ret_r0 = \fast
+        .endm
+#else   /* ifdef CONFIG_CPU_V7M */
         .macro  restore_user_regs, fast = 0, offset = 0
         clrex                                   @ clear the exclusive monitor
         mov     r2, sp
@@ -181,6 +304,7 @@
         add     sp, sp, #S_FRAME_SIZE - S_SP
         movs    pc, lr                          @ return & move spsr_svc into cpsr
         .endm
+#endif  /* ifdef CONFIG_CPU_V7M / else */
 
         .macro  get_thread_info, rd
         mov     \rd, sp
diff --git a/arch/arm/kernel/entry-v7m.S b/arch/arm/kernel/entry-v7m.S
new file mode 100644
index 000000000000..52b26432c9a9
--- /dev/null
+++ b/arch/arm/kernel/entry-v7m.S
@@ -0,0 +1,143 @@
+/*
+ * linux/arch/arm/kernel/entry-v7m.S
+ *
+ * Copyright (C) 2008 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Low-level vector interface routines for the ARMv7-M architecture
+ */
+#include <asm/memory.h>
+#include <asm/glue.h>
+#include <asm/thread_notify.h>
+#include <asm/v7m.h>
+
+#include <mach/entry-macro.S>
+
+#include "entry-header.S"
+
+#ifdef CONFIG_TRACE_IRQFLAGS
+#error "CONFIG_TRACE_IRQFLAGS not supported on the current ARMv7M implementation"
+#endif
+
+__invalid_entry:
+        v7m_exception_entry
+        adr     r0, strerr
+        mrs     r1, ipsr
+        mov     r2, lr
+        bl      printk
+        mov     r0, sp
+        bl      show_regs
+1:      b       1b
+ENDPROC(__invalid_entry)
+
+strerr: .asciz  "\nUnhandled exception: IPSR = %08lx LR = %08lx\n"
+
+        .align  2
+__irq_entry:
+        v7m_exception_entry
+
+        @
+        @ Invoke the IRQ handler
+        @
+        mrs     r0, ipsr
+        ldr     r1, =V7M_xPSR_EXCEPTIONNO
+        and     r0, r1
+        sub     r0, #16
+        mov     r1, sp
+        stmdb   sp!, {lr}
+        @ routine called with r0 = irq number, r1 = struct pt_regs *
+        bl      nvic_handle_irq
+
+        pop     {lr}
+        @
+        @ Check for any pending work if returning to user
+        @
+        ldr     r1, =BASEADDR_V7M_SCB
+        ldr     r0, [r1, V7M_SCB_ICSR]
+        tst     r0, V7M_SCB_ICSR_RETTOBASE
+        beq     2f
+
+        get_thread_info tsk
+        ldr     r2, [tsk, #TI_FLAGS]
+        tst     r2, #_TIF_WORK_MASK
+        beq     2f                      @ no work pending
+        mov     r0, #V7M_SCB_ICSR_PENDSVSET
+        str     r0, [r1, V7M_SCB_ICSR]  @ raise PendSV
+
+2:
+        @ registers r0-r3 and r12 are automatically restored on exception
+        @ return. r4-r7 were not clobbered in v7m_exception_entry so for
+        @ correctness they don't need to be restored. So only r8-r11 must be
+        @ restored here. The easiest way to do so is to restore r0-r7, too.
+        ldmia   sp!, {r0-r11}
+        add     sp, #S_FRAME_SIZE-S_IP
+        cpsie   i
+        bx      lr
+ENDPROC(__irq_entry)
+
+__pendsv_entry:
+        v7m_exception_entry
+
+        ldr     r1, =BASEADDR_V7M_SCB
+        mov     r0, #V7M_SCB_ICSR_PENDSVCLR
+        str     r0, [r1, V7M_SCB_ICSR]  @ clear PendSV
+
+        @ execute the pending work, including reschedule
+        get_thread_info tsk
+        mov     why, #0
+        b       ret_to_user
+ENDPROC(__pendsv_entry)
+
+/*
+ * Register switch for ARMv7-M processors.
+ * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
+ * previous and next are guaranteed not to be the same.
+ */
+ENTRY(__switch_to)
+        .fnstart
+        .cantunwind
+        add     ip, r1, #TI_CPU_SAVE
+        stmia   ip!, {r4 - r11}         @ Store most regs on stack
+        str     sp, [ip], #4
+        str     lr, [ip], #4
+        mov     r5, r0
+        add     r4, r2, #TI_CPU_SAVE
+        ldr     r0, =thread_notify_head
+        mov     r1, #THREAD_NOTIFY_SWITCH
+        bl      atomic_notifier_call_chain
+        mov     ip, r4
+        mov     r0, r5
+        ldmia   ip!, {r4 - r11}         @ Load all regs saved previously
+        ldr     sp, [ip]
+        ldr     pc, [ip, #4]!
+        .fnend
+ENDPROC(__switch_to)
+
+        .data
+        .align  8
+/*
+ * Vector table (64 words => 256 bytes natural alignment)
+ */
+ENTRY(vector_table)
+        .long   0                       @ 0 - Reset stack pointer
+        .long   __invalid_entry         @ 1 - Reset
+        .long   __invalid_entry         @ 2 - NMI
+        .long   __invalid_entry         @ 3 - HardFault
+        .long   __invalid_entry         @ 4 - MemManage
+        .long   __invalid_entry         @ 5 - BusFault
+        .long   __invalid_entry         @ 6 - UsageFault
+        .long   __invalid_entry         @ 7 - Reserved
+        .long   __invalid_entry         @ 8 - Reserved
+        .long   __invalid_entry         @ 9 - Reserved
+        .long   __invalid_entry         @ 10 - Reserved
+        .long   vector_swi              @ 11 - SVCall
+        .long   __invalid_entry         @ 12 - Debug Monitor
+        .long   __invalid_entry         @ 13 - Reserved
+        .long   __pendsv_entry          @ 14 - PendSV
+        .long   __invalid_entry         @ 15 - SysTick
+        .rept   64 - 16
+        .long   __irq_entry             @ 16..64 - External Interrupts
+        .endr
diff --git a/arch/arm/kernel/fiq.c b/arch/arm/kernel/fiq.c
index 2adda11f712f..25442f451148 100644
--- a/arch/arm/kernel/fiq.c
+++ b/arch/arm/kernel/fiq.c
@@ -47,6 +47,11 @@
 #include <asm/irq.h>
 #include <asm/traps.h>
 
+#define FIQ_OFFSET ({                                   \
+                extern void *vector_fiq_offset;         \
+                (unsigned)&vector_fiq_offset;           \
+        })
+
 static unsigned long no_fiq_insn;
 
 /* Default reacquire function
@@ -80,13 +85,16 @@ int show_fiq_list(struct seq_file *p, int prec)
 void set_fiq_handler(void *start, unsigned int length)
 {
 #if defined(CONFIG_CPU_USE_DOMAINS)
-        memcpy((void *)0xffff001c, start, length);
+        void *base = (void *)0xffff0000;
 #else
-        memcpy(vectors_page + 0x1c, start, length);
+        void *base = vectors_page;
 #endif
-        flush_icache_range(0xffff001c, 0xffff001c + length);
+        unsigned offset = FIQ_OFFSET;
+
+        memcpy(base + offset, start, length);
+        flush_icache_range(0xffff0000 + offset, 0xffff0000 + offset + length);
         if (!vectors_high())
-                flush_icache_range(0x1c, 0x1c + length);
+                flush_icache_range(offset, offset + length);
 }
 
 int claim_fiq(struct fiq_handler *f)
@@ -144,6 +152,7 @@ EXPORT_SYMBOL(disable_fiq);
 
 void __init init_FIQ(int start)
 {
-        no_fiq_insn = *(unsigned long *)0xffff001c;
+        unsigned offset = FIQ_OFFSET;
+        no_fiq_insn = *(unsigned long *)(0xffff0000 + offset);
         fiq_start = start;
 }
diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S
index 5b391a689b47..47cd974e57ea 100644
--- a/arch/arm/kernel/head-common.S
+++ b/arch/arm/kernel/head-common.S
@@ -133,6 +133,9 @@ ENTRY(lookup_processor_type)
         ldmfd   sp!, {r4 - r6, r9, pc}
 ENDPROC(lookup_processor_type)
 
+        __FINIT
+        .text
+
 /*
  * Read processor ID register (CP#15, CR0), and look up in the linker-built
  * supported processor list.  Note that we can't use the absolute addresses
@@ -146,7 +149,6 @@ ENDPROC(lookup_processor_type)
  *      r5 = proc_info pointer in physical address space
  *      r9 = cpuid (preserved)
  */
-        __CPUINIT
 __lookup_processor_type:
         adr     r3, __lookup_processor_type_data
         ldmia   r3, {r4 - r6}
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index 6a2e09c952c7..14235ba64a90 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -17,8 +17,12 @@
 #include <asm/assembler.h>
 #include <asm/ptrace.h>
 #include <asm/asm-offsets.h>
+#include <asm/memory.h>
 #include <asm/cp15.h>
 #include <asm/thread_info.h>
+#include <asm/v7m.h>
+#include <asm/mpu.h>
+#include <asm/page.h>
 
 /*
  * Kernel startup entry point.
@@ -50,21 +54,86 @@ ENTRY(stext)
 
         setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
                                                 @ and irqs disabled
-#ifndef CONFIG_CPU_CP15
-        ldr     r9, =CONFIG_PROCESSOR_ID
-#else
+#if defined(CONFIG_CPU_CP15)
         mrc     p15, 0, r9, c0, c0              @ get processor id
+#elif defined(CONFIG_CPU_V7M)
+        ldr     r9, =BASEADDR_V7M_SCB
+        ldr     r9, [r9, V7M_SCB_CPUID]
+#else
+        ldr     r9, =CONFIG_PROCESSOR_ID
 #endif
         bl      __lookup_processor_type         @ r5=procinfo r9=cpuid
         movs    r10, r5                         @ invalid processor (r5=0)?
         beq     __error_p                               @ yes, error 'p'
 
-        adr     lr, BSYM(__after_proc_init)     @ return (PIC) address
+#ifdef CONFIG_ARM_MPU
+        /* Calculate the size of a region covering just the kernel */
+        ldr     r5, =PHYS_OFFSET                @ Region start: PHYS_OFFSET
+        ldr     r6, =(_end)                     @ Cover whole kernel
+        sub     r6, r6, r5                      @ Minimum size of region to map
+        clz     r6, r6                          @ Region size must be 2^N...
+        rsb     r6, r6, #31                     @ ...so round up region size
+        lsl     r6, r6, #MPU_RSR_SZ             @ Put size in right field
+        orr     r6, r6, #(1 << MPU_RSR_EN)      @ Set region enabled bit
+        bl      __setup_mpu
+#endif
+        ldr     r13, =__mmap_switched           @ address to jump to after
+                                                @ initialising sctlr
+        adr     lr, BSYM(1f)                    @ return (PIC) address
  ARM(   add     pc, r10, #PROCINFO_INITFUNC     )
  THUMB( add     r12, r10, #PROCINFO_INITFUNC    )
  THUMB( mov     pc, r12                         )
+ 1:     b       __after_proc_init
 ENDPROC(stext)
 
+#ifdef CONFIG_SMP
+        .text
+ENTRY(secondary_startup)
+        /*
+         * Common entry point for secondary CPUs.
+         *
+         * Ensure that we're in SVC mode, and IRQs are disabled.  Lookup
+         * the processor type - there is no need to check the machine type
+         * as it has already been validated by the primary processor.
+         */
+        setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9
+#ifndef CONFIG_CPU_CP15
+        ldr     r9, =CONFIG_PROCESSOR_ID
+#else
+        mrc     p15, 0, r9, c0, c0              @ get processor id
+#endif
+        bl      __lookup_processor_type         @ r5=procinfo r9=cpuid
+        movs    r10, r5                         @ invalid processor?
+        beq     __error_p                       @ yes, error 'p'
+
+        adr     r4, __secondary_data
+        ldmia   r4, {r7, r12}
+
+#ifdef CONFIG_ARM_MPU
+        /* Use MPU region info supplied by __cpu_up */
+        ldr     r6, [r7]                        @ get secondary_data.mpu_szr
+        bl      __setup_mpu                     @ Initialize the MPU
+#endif
+
+        adr     lr, BSYM(__after_proc_init)     @ return address
+        mov     r13, r12                        @ __secondary_switched address
+ ARM(   add     pc, r10, #PROCINFO_INITFUNC     )
+ THUMB( add     r12, r10, #PROCINFO_INITFUNC    )
+ THUMB( mov     pc, r12                         )
+ENDPROC(secondary_startup)
+
+ENTRY(__secondary_switched)
+        ldr     sp, [r7, #8]                    @ set up the stack pointer
+        mov     fp, #0
+        b       secondary_start_kernel
+ENDPROC(__secondary_switched)
+
+        .type   __secondary_data, %object
+__secondary_data:
+        .long   secondary_data
+        .long   __secondary_switched
+#endif /* CONFIG_SMP */
+
 /*
  * Set the Control Register and Read the process ID.
  */
@@ -95,10 +164,97 @@ __after_proc_init:
 #endif
         mcr     p15, 0, r0, c1, c0, 0           @ write control reg
 #endif /* CONFIG_CPU_CP15 */
-
-        b       __mmap_switched                 @ clear the BSS and jump
-                                                @ to start_kernel
+        mov     pc, r13
 ENDPROC(__after_proc_init)
         .ltorg
 
+#ifdef CONFIG_ARM_MPU
+
+
+/* Set which MPU region should be programmed */
+.macro set_region_nr tmp, rgnr
+        mov     \tmp, \rgnr                     @ Use static region numbers
+        mcr     p15, 0, \tmp, c6, c2, 0         @ Write RGNR
+.endm
+
+/* Setup a single MPU region, either D or I side (D-side for unified) */
+.macro setup_region bar, acr, sr, side = MPU_DATA_SIDE
+        mcr     p15, 0, \bar, c6, c1, (0 + \side)       @ I/DRBAR
+        mcr     p15, 0, \acr, c6, c1, (4 + \side)       @ I/DRACR
+        mcr     p15, 0, \sr, c6, c1, (2 + \side)                @ I/DRSR
+.endm
+
+/*
+ * Setup the MPU and initial MPU Regions. We create the following regions:
+ * Region 0: Use this for probing the MPU details, so leave disabled.
+ * Region 1: Background region - covers the whole of RAM as strongly ordered
+ * Region 2: Normal, Shared, cacheable for RAM. From PHYS_OFFSET, size from r6
+ * Region 3: Normal, shared, inaccessible from PL0 to protect the vectors page
+ *
+ * r6: Value to be written to DRSR (and IRSR if required) for MPU_RAM_REGION
+*/
+
+ENTRY(__setup_mpu)
+
+        /* Probe for v7 PMSA compliance */
+        mrc     p15, 0, r0, c0, c1, 4           @ Read ID_MMFR0
+        and     r0, r0, #(MMFR0_PMSA)           @ PMSA field
+        teq     r0, #(MMFR0_PMSAv7)             @ PMSA v7
+        bne     __error_p                       @ Fail: ARM_MPU on NOT v7 PMSA
+
+        /* Determine whether the D/I-side memory map is unified. We set the
+         * flags here and continue to use them for the rest of this function */
+        mrc     p15, 0, r0, c0, c0, 4           @ MPUIR
+        ands    r5, r0, #MPUIR_DREGION_SZMASK   @ 0 size d region => No MPU
+        beq     __error_p                       @ Fail: ARM_MPU and no MPU
+        tst     r0, #MPUIR_nU                   @ MPUIR_nU = 0 for unified
+
+        /* Setup second region first to free up r6 */
+        set_region_nr r0, #MPU_RAM_REGION
+        isb
+        /* Full access from PL0, PL1, shared for CONFIG_SMP, cacheable */
+        ldr     r0, =PHYS_OFFSET                @ RAM starts at PHYS_OFFSET
+        ldr     r5,=(MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL)
+
+        setup_region r0, r5, r6, MPU_DATA_SIDE  @ PHYS_OFFSET, shared, enabled
+        beq     1f                              @ Memory-map not unified
+        setup_region r0, r5, r6, MPU_INSTR_SIDE @ PHYS_OFFSET, shared, enabled
+1:      isb
+
+        /* First/background region */
+        set_region_nr r0, #MPU_BG_REGION
+        isb
+        /* Execute Never,  strongly ordered, inaccessible to PL0, rw PL1  */
+        mov     r0, #0                          @ BG region starts at 0x0
+        ldr     r5,=(MPU_ACR_XN | MPU_RGN_STRONGLY_ORDERED | MPU_AP_PL1RW_PL0NA)
+        mov     r6, #MPU_RSR_ALL_MEM            @ 4GB region, enabled
+
+        setup_region r0, r5, r6, MPU_DATA_SIDE  @ 0x0, BG region, enabled
+        beq     2f                              @ Memory-map not unified
+        setup_region r0, r5, r6, MPU_INSTR_SIDE @ 0x0, BG region, enabled
+2:      isb
+
+        /* Vectors region */
+        set_region_nr r0, #MPU_VECTORS_REGION
+        isb
+        /* Shared, inaccessible to PL0, rw PL1 */
+        mov     r0, #CONFIG_VECTORS_BASE        @ Cover from VECTORS_BASE
+        ldr     r5,=(MPU_AP_PL1RW_PL0NA | MPU_RGN_NORMAL)
+        /* Writing N to bits 5:1 (RSR_SZ) --> region size 2^N+1 */
+        mov     r6, #(((PAGE_SHIFT - 1) << MPU_RSR_SZ) | 1 << MPU_RSR_EN)
+
+        setup_region r0, r5, r6, MPU_DATA_SIDE  @ VECTORS_BASE, PL0 NA, enabled
+        beq     3f                              @ Memory-map not unified
+        setup_region r0, r5, r6, MPU_INSTR_SIDE @ VECTORS_BASE, PL0 NA, enabled
+3:      isb
+
+        /* Enable the MPU */
+        mrc     p15, 0, r0, c1, c0, 0           @ Read SCTLR
+        bic     r0, r0, #CR_BR                  @ Disable the 'default mem-map'
+        orr     r0, r0, #CR_M                   @ Set SCTRL.M (MPU on)
+        mcr     p15, 0, r0, c1, c0, 0           @ Enable MPU
+        isb
+        mov pc,lr
+ENDPROC(__setup_mpu)
+#endif
 #include "head-common.S"
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 8bac553fe213..2c7cc1e03473 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -156,7 +156,7 @@ ENDPROC(stext)
  *
  * Returns:
  *  r0, r3, r5-r7 corrupted
- *  r4 = physical page table address
+ *  r4 = page table (see ARCH_PGD_SHIFT in asm/memory.h)
  */
 __create_page_tables:
         pgtbl   r4, r8                          @ page table address
@@ -331,6 +331,7 @@ __create_page_tables:
 #endif
 #ifdef CONFIG_ARM_LPAE
         sub     r4, r4, #0x1000         @ point to the PGD table
+        mov     r4, r4, lsr #ARCH_PGD_SHIFT
 #endif
         mov     pc, lr
 ENDPROC(__create_page_tables)
@@ -342,7 +343,7 @@ __turn_mmu_on_loc:
         .long   __turn_mmu_on_end
 
 #if defined(CONFIG_SMP)
-        __CPUINIT
+        .text
 ENTRY(secondary_startup)
         /*
          * Common entry point for secondary CPUs.
@@ -408,7 +409,7 @@ __secondary_data:
  *  r0  = cp#15 control register
  *  r1  = machine ID
  *  r2  = atags or dtb pointer
- *  r4  = page table pointer
+ *  r4  = page table (see ARCH_PGD_SHIFT in asm/memory.h)
  *  r9  = processor ID
  *  r13 = *virtual* address to jump to upon completion
  */
@@ -427,10 +428,7 @@ __enable_mmu:
 #ifdef CONFIG_CPU_ICACHE_DISABLE
         bic     r0, r0, #CR_I
 #endif
-#ifdef CONFIG_ARM_LPAE
-        mov     r5, #0
-        mcrr    p15, 0, r4, r5, c2              @ load TTBR0
-#else
+#ifndef CONFIG_ARM_LPAE
         mov     r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
                       domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
                       domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index 1fd749ee4a1b..7b95de601357 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -1020,7 +1020,7 @@ out_mdbgen:
                 cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu));
 }
 
-static int __cpuinit dbg_reset_notify(struct notifier_block *self,
+static int dbg_reset_notify(struct notifier_block *self,
                                       unsigned long action, void *cpu)
 {
         if ((action & ~CPU_TASKS_FROZEN) == CPU_ONLINE)
@@ -1029,7 +1029,7 @@ static int __cpuinit dbg_reset_notify(struct notifier_block *self,
         return NOTIFY_OK;
 }
 
-static struct notifier_block __cpuinitdata dbg_reset_nb = {
+static struct notifier_block dbg_reset_nb = {
         .notifier_call = dbg_reset_notify,
 };
 
diff --git a/arch/arm/kernel/hyp-stub.S b/arch/arm/kernel/hyp-stub.S
index 1315c4ccfa56..797b1a6a4906 100644
--- a/arch/arm/kernel/hyp-stub.S
+++ b/arch/arm/kernel/hyp-stub.S
@@ -56,8 +56,8 @@ ENTRY(__boot_cpu_mode)
         ldr     \reg3, [\reg2]
         ldr     \reg1, [\reg2, \reg3]
         cmp     \mode, \reg1            @ matches primary CPU boot mode?
-        orrne   r7, r7, #BOOT_CPU_MODE_MISMATCH
-        strne   r7, [r5, r6]            @ record what happened and give up
+        orrne   \reg1, \reg1, #BOOT_CPU_MODE_MISMATCH
+        strne   \reg1, [\reg2, \reg3]   @ record what happened and give up
         .endm
 
 #else   /* ZIMAGE */
@@ -153,6 +153,13 @@ THUMB(	orr	r7, #(1 << 30)	)	@ HSCTLR.TE
         mrc     p15, 4, r7, c14, c1, 0  @ CNTHCTL
         orr     r7, r7, #3              @ PL1PCEN | PL1PCTEN
         mcr     p15, 4, r7, c14, c1, 0  @ CNTHCTL
+        mov     r7, #0
+        mcrr    p15, 4, r7, r7, c14     @ CNTVOFF
+
+        @ Disable virtual timer in case it was counting
+        mrc     p15, 0, r7, c14, c3, 1  @ CNTV_CTL
+        bic     r7, #1                  @ Clear ENABLE
+        mcr     p15, 0, r7, c14, c3, 1  @ CNTV_CTL
 1:
 #endif
 
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index 1e9be5d25e56..85c3fb6c93c2 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -288,24 +288,16 @@ int module_finalize(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs,
 
                 if (strcmp(".ARM.exidx.init.text", secname) == 0)
                         maps[ARM_SEC_INIT].unw_sec = s;
-                else if (strcmp(".ARM.exidx.devinit.text", secname) == 0)
-                        maps[ARM_SEC_DEVINIT].unw_sec = s;
                 else if (strcmp(".ARM.exidx", secname) == 0)
                         maps[ARM_SEC_CORE].unw_sec = s;
                 else if (strcmp(".ARM.exidx.exit.text", secname) == 0)
                         maps[ARM_SEC_EXIT].unw_sec = s;
-                else if (strcmp(".ARM.exidx.devexit.text", secname) == 0)
-                        maps[ARM_SEC_DEVEXIT].unw_sec = s;
                 else if (strcmp(".init.text", secname) == 0)
                         maps[ARM_SEC_INIT].txt_sec = s;
-                else if (strcmp(".devinit.text", secname) == 0)
-                        maps[ARM_SEC_DEVINIT].txt_sec = s;
                 else if (strcmp(".text", secname) == 0)
                         maps[ARM_SEC_CORE].txt_sec = s;
                 else if (strcmp(".exit.text", secname) == 0)
                         maps[ARM_SEC_EXIT].txt_sec = s;
-                else if (strcmp(".devexit.text", secname) == 0)
-                        maps[ARM_SEC_DEVEXIT].txt_sec = s;
         }
 
         for (i = 0; i < ARM_SEC_MAX; i++)
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 8c3094d0f7b7..21f77906602c 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -53,7 +53,12 @@ armpmu_map_cache_event(const unsigned (*cache_map)
 static int
 armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
 {
-        int mapping = (*event_map)[config];
+        int mapping;
+
+        if (config >= PERF_COUNT_HW_MAX)
+                return -ENOENT;
+
+        mapping = (*event_map)[config];
         return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
 }
 
@@ -569,6 +574,7 @@ perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
                 return;
         }
 
+        perf_callchain_store(entry, regs->ARM_pc);
         tail = (struct frame_tail __user *)regs->ARM_fp - 1;
 
         while ((entry->nr < PERF_MAX_STACK_DEPTH) &&
diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c
index 1f2740e3dbc0..aebe0e99c153 100644
--- a/arch/arm/kernel/perf_event_cpu.c
+++ b/arch/arm/kernel/perf_event_cpu.c
@@ -157,8 +157,8 @@ static void cpu_pmu_init(struct arm_pmu *cpu_pmu)
  * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
  * junk values out of them.
  */
-static int __cpuinit cpu_pmu_notify(struct notifier_block *b,
-                                    unsigned long action, void *hcpu)
+static int cpu_pmu_notify(struct notifier_block *b, unsigned long action,
+                          void *hcpu)
 {
         if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
                 return NOTIFY_DONE;
@@ -171,7 +171,7 @@ static int __cpuinit cpu_pmu_notify(struct notifier_block *b,
         return NOTIFY_OK;
 }
 
-static struct notifier_block __cpuinitdata cpu_pmu_hotplug_notifier = {
+static struct notifier_block cpu_pmu_hotplug_notifier = {
         .notifier_call = cpu_pmu_notify,
 };
 
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 6e8931ccf13e..536c85fe72a8 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -32,6 +32,7 @@
 #include <linux/hw_breakpoint.h>
 #include <linux/cpuidle.h>
 #include <linux/leds.h>
+#include <linux/reboot.h>
 
 #include <asm/cacheflush.h>
 #include <asm/idmap.h>
@@ -39,6 +40,7 @@
 #include <asm/thread_notify.h>
 #include <asm/stacktrace.h>
 #include <asm/mach/time.h>
+#include <asm/tls.h>
 
 #ifdef CONFIG_CC_STACKPROTECTOR
 #include <linux/stackprotector.h>
@@ -112,7 +114,7 @@ void soft_restart(unsigned long addr)
         BUG();
 }
 
-static void null_restart(char mode, const char *cmd)
+static void null_restart(enum reboot_mode reboot_mode, const char *cmd)
 {
 }
 
@@ -122,7 +124,7 @@ static void null_restart(char mode, const char *cmd)
 void (*pm_power_off)(void);
 EXPORT_SYMBOL(pm_power_off);
 
-void (*arm_pm_restart)(char str, const char *cmd) = null_restart;
+void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd) = null_restart;
 EXPORT_SYMBOL_GPL(arm_pm_restart);
 
 /*
@@ -174,16 +176,6 @@ void arch_cpu_idle(void)
                 default_idle();
 }
 
-static char reboot_mode = 'h';
-
-int __init reboot_setup(char *str)
-{
-        reboot_mode = str[0];
-        return 1;
-}
-
-__setup("reboot=", reboot_setup);
-
 /*
  * Called by kexec, immediately prior to machine_kexec().
  *
@@ -205,6 +197,7 @@ void machine_shutdown(void)
  */
 void machine_halt(void)
 {
+        local_irq_disable();
         smp_send_stop();
 
         local_irq_disable();
@@ -219,6 +212,7 @@ void machine_halt(void)
  */
 void machine_power_off(void)
 {
+        local_irq_disable();
         smp_send_stop();
 
         if (pm_power_off)
@@ -238,6 +232,7 @@ void machine_power_off(void)
  */
 void machine_restart(char *cmd)
 {
+        local_irq_disable();
         smp_send_stop();
 
         arm_pm_restart(reboot_mode, cmd);
@@ -374,7 +369,8 @@ copy_thread(unsigned long clone_flags, unsigned long stack_start,
         clear_ptrace_hw_breakpoint(p);
 
         if (clone_flags & CLONE_SETTLS)
-                thread->tp_value = childregs->ARM_r3;
+                thread->tp_value[0] = childregs->ARM_r3;
+        thread->tp_value[1] = get_tpuser();
 
         thread_notify(THREAD_NOTIFY_COPY, thread);
 
@@ -433,10 +429,11 @@ unsigned long arch_randomize_brk(struct mm_struct *mm)
 }
 
 #ifdef CONFIG_MMU
+#ifdef CONFIG_KUSER_HELPERS
 /*
  * The vectors page is always readable from user space for the
- * atomic helpers and the signal restart code. Insert it into the
- * gate_vma so that it is visible through ptrace and /proc/<pid>/mem.
+ * atomic helpers. Insert it into the gate_vma so that it is visible
+ * through ptrace and /proc/<pid>/mem.
  */
 static struct vm_area_struct gate_vma = {
         .vm_start       = 0xffff0000,
@@ -465,9 +462,48 @@ int in_gate_area_no_mm(unsigned long addr)
 {
         return in_gate_area(NULL, addr);
 }
+#define is_gate_vma(vma)        ((vma) = &gate_vma)
+#else
+#define is_gate_vma(vma)        0
+#endif
 
 const char *arch_vma_name(struct vm_area_struct *vma)
 {
-        return (vma == &gate_vma) ? "[vectors]" : NULL;
+        return is_gate_vma(vma) ? "[vectors]" :
+                (vma->vm_mm && vma->vm_start == vma->vm_mm->context.sigpage) ?
+                 "[sigpage]" : NULL;
+}
+
+static struct page *signal_page;
+extern struct page *get_signal_page(void);
+
+int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
+{
+        struct mm_struct *mm = current->mm;
+        unsigned long addr;
+        int ret;
+
+        if (!signal_page)
+                signal_page = get_signal_page();
+        if (!signal_page)
+                return -ENOMEM;
+
+        down_write(&mm->mmap_sem);
+        addr = get_unmapped_area(NULL, 0, PAGE_SIZE, 0, 0);
+        if (IS_ERR_VALUE(addr)) {
+                ret = addr;
+                goto up_fail;
+        }
+
+        ret = install_special_mapping(mm, addr, PAGE_SIZE,
+                VM_READ | VM_EXEC | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC,
+                &signal_page);
+
+        if (ret == 0)
+                mm->context.sigpage = addr;
+
+ up_fail:
+        up_write(&mm->mmap_sem);
+        return ret;
 }
 #endif
diff --git a/arch/arm/kernel/psci.c b/arch/arm/kernel/psci.c
index 36531643cc2c..46931880093d 100644
--- a/arch/arm/kernel/psci.c
+++ b/arch/arm/kernel/psci.c
@@ -158,7 +158,7 @@ static const struct of_device_id psci_of_match[] __initconst = {
         {},
 };
 
-static int __init psci_init(void)
+void __init psci_init(void)
 {
         struct device_node *np;
         const char *method;
@@ -166,7 +166,7 @@ static int __init psci_init(void)
 
         np = of_find_matching_node(NULL, psci_of_match);
         if (!np)
-                return 0;
+                return;
 
         pr_info("probing function IDs from device-tree\n");
 
@@ -206,6 +206,5 @@ static int __init psci_init(void)
 
 out_put_node:
         of_node_put(np);
-        return 0;
+        return;
 }
-early_initcall(psci_init);
diff --git a/arch/arm/kernel/psci_smp.c b/arch/arm/kernel/psci_smp.c
new file mode 100644
index 000000000000..70ded3fb42d9
--- /dev/null
+++ b/arch/arm/kernel/psci_smp.c
@@ -0,0 +1,83 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2012 ARM Limited
+ *
+ * Author: Will Deacon <will.deacon@arm.com>
+ */
+
+#include <linux/init.h>
+#include <linux/irqchip/arm-gic.h>
+#include <linux/smp.h>
+#include <linux/of.h>
+
+#include <asm/psci.h>
+#include <asm/smp_plat.h>
+
+/*
+ * psci_smp assumes that the following is true about PSCI:
+ *
+ * cpu_suspend   Suspend the execution on a CPU
+ * @state        we don't currently describe affinity levels, so just pass 0.
+ * @entry_point  the first instruction to be executed on return
+ * returns 0  success, < 0 on failure
+ *
+ * cpu_off       Power down a CPU
+ * @state        we don't currently describe affinity levels, so just pass 0.
+ * no return on successful call
+ *
+ * cpu_on        Power up a CPU
+ * @cpuid        cpuid of target CPU, as from MPIDR
+ * @entry_point  the first instruction to be executed on return
+ * returns 0  success, < 0 on failure
+ *
+ * migrate       Migrate the context to a different CPU
+ * @cpuid        cpuid of target CPU, as from MPIDR
+ * returns 0  success, < 0 on failure
+ *
+ */
+
+extern void secondary_startup(void);
+
+static int psci_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        if (psci_ops.cpu_on)
+                return psci_ops.cpu_on(cpu_logical_map(cpu),
+                                       __pa(secondary_startup));
+        return -ENODEV;
+}
+
+#ifdef CONFIG_HOTPLUG_CPU
+void __ref psci_cpu_die(unsigned int cpu)
+{
+       const struct psci_power_state ps = {
+               .type = PSCI_POWER_STATE_TYPE_POWER_DOWN,
+       };
+
+       if (psci_ops.cpu_off)
+               psci_ops.cpu_off(ps);
+
+       /* We should never return */
+       panic("psci: cpu %d failed to shutdown\n", cpu);
+}
+#endif
+
+bool __init psci_smp_available(void)
+{
+        /* is cpu_on available at least? */
+        return (psci_ops.cpu_on != NULL);
+}
+
+struct smp_operations __initdata psci_smp_ops = {
+        .smp_boot_secondary     = psci_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_die                = psci_cpu_die,
+#endif
+};
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 03deeffd9f6d..0dd3b79b15c3 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -849,7 +849,7 @@ long arch_ptrace(struct task_struct *child, long request,
 #endif
 
                 case PTRACE_GET_THREAD_AREA:
-                        ret = put_user(task_thread_info(child)->tp_value,
+                        ret = put_user(task_thread_info(child)->tp_value[0],
                                        datap);
                         break;
 
@@ -886,20 +886,12 @@ long arch_ptrace(struct task_struct *child, long request,
 
 #ifdef CONFIG_HAVE_HW_BREAKPOINT
                 case PTRACE_GETHBPREGS:
-                        if (ptrace_get_breakpoints(child) < 0)
-                                return -ESRCH;
-
                         ret = ptrace_gethbpregs(child, addr,
                                                 (unsigned long __user *)data);
-                        ptrace_put_breakpoints(child);
                         break;
                 case PTRACE_SETHBPREGS:
-                        if (ptrace_get_breakpoints(child) < 0)
-                                return -ESRCH;
-
                         ret = ptrace_sethbpregs(child, addr,
                                                 (unsigned long __user *)data);
-                        ptrace_put_breakpoints(child);
                         break;
 #endif
 
diff --git a/arch/arm/kernel/sched_clock.c b/arch/arm/kernel/sched_clock.c
deleted file mode 100644
index e8edcaa0e432..000000000000
--- a/arch/arm/kernel/sched_clock.c
+++ /dev/null
@@ -1,217 +0,0 @@
-/*
- * sched_clock.c: support for extending counters to full 64-bit ns counter
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/clocksource.h>
-#include <linux/init.h>
-#include <linux/jiffies.h>
-#include <linux/kernel.h>
-#include <linux/moduleparam.h>
-#include <linux/sched.h>
-#include <linux/syscore_ops.h>
-#include <linux/timer.h>
-
-#include <asm/sched_clock.h>
-
-struct clock_data {
-        u64 epoch_ns;
-        u32 epoch_cyc;
-        u32 epoch_cyc_copy;
-        unsigned long rate;
-        u32 mult;
-        u32 shift;
-        bool suspended;
-        bool needs_suspend;
-};
-
-static void sched_clock_poll(unsigned long wrap_ticks);
-static DEFINE_TIMER(sched_clock_timer, sched_clock_poll, 0, 0);
-static int irqtime = -1;
-
-core_param(irqtime, irqtime, int, 0400);
-
-static struct clock_data cd = {
-        .mult   = NSEC_PER_SEC / HZ,
-};
-
-static u32 __read_mostly sched_clock_mask = 0xffffffff;
-
-static u32 notrace jiffy_sched_clock_read(void)
-{
-        return (u32)(jiffies - INITIAL_JIFFIES);
-}
-
-static u32 __read_mostly (*read_sched_clock)(void) = jiffy_sched_clock_read;
-
-static inline u64 notrace cyc_to_ns(u64 cyc, u32 mult, u32 shift)
-{
-        return (cyc * mult) >> shift;
-}
-
-static unsigned long long notrace cyc_to_sched_clock(u32 cyc, u32 mask)
-{
-        u64 epoch_ns;
-        u32 epoch_cyc;
-
-        if (cd.suspended)
-                return cd.epoch_ns;
-
-        /*
-         * Load the epoch_cyc and epoch_ns atomically.  We do this by
-         * ensuring that we always write epoch_cyc, epoch_ns and
-         * epoch_cyc_copy in strict order, and read them in strict order.
-         * If epoch_cyc and epoch_cyc_copy are not equal, then we're in
-         * the middle of an update, and we should repeat the load.
-         */
-        do {
-                epoch_cyc = cd.epoch_cyc;
-                smp_rmb();
-                epoch_ns = cd.epoch_ns;
-                smp_rmb();
-        } while (epoch_cyc != cd.epoch_cyc_copy);
-
-        return epoch_ns + cyc_to_ns((cyc - epoch_cyc) & mask, cd.mult, cd.shift);
-}
-
-/*
- * Atomically update the sched_clock epoch.
- */
-static void notrace update_sched_clock(void)
-{
-        unsigned long flags;
-        u32 cyc;
-        u64 ns;
-
-        cyc = read_sched_clock();
-        ns = cd.epoch_ns +
-                cyc_to_ns((cyc - cd.epoch_cyc) & sched_clock_mask,
-                          cd.mult, cd.shift);
-        /*
-         * Write epoch_cyc and epoch_ns in a way that the update is
-         * detectable in cyc_to_fixed_sched_clock().
-         */
-        raw_local_irq_save(flags);
-        cd.epoch_cyc_copy = cyc;
-        smp_wmb();
-        cd.epoch_ns = ns;
-        smp_wmb();
-        cd.epoch_cyc = cyc;
-        raw_local_irq_restore(flags);
-}
-
-static void sched_clock_poll(unsigned long wrap_ticks)
-{
-        mod_timer(&sched_clock_timer, round_jiffies(jiffies + wrap_ticks));
-        update_sched_clock();
-}
-
-void __init setup_sched_clock(u32 (*read)(void), int bits, unsigned long rate)
-{
-        unsigned long r, w;
-        u64 res, wrap;
-        char r_unit;
-
-        if (cd.rate > rate)
-                return;
-
-        BUG_ON(bits > 32);
-        WARN_ON(!irqs_disabled());
-        read_sched_clock = read;
-        sched_clock_mask = (1 << bits) - 1;
-        cd.rate = rate;
-
-        /* calculate the mult/shift to convert counter ticks to ns. */
-        clocks_calc_mult_shift(&cd.mult, &cd.shift, rate, NSEC_PER_SEC, 0);
-
-        r = rate;
-        if (r >= 4000000) {
-                r /= 1000000;
-                r_unit = 'M';
-        } else if (r >= 1000) {
-                r /= 1000;
-                r_unit = 'k';
-        } else
-                r_unit = ' ';
-
-        /* calculate how many ns until we wrap */
-        wrap = cyc_to_ns((1ULL << bits) - 1, cd.mult, cd.shift);
-        do_div(wrap, NSEC_PER_MSEC);
-        w = wrap;
-
-        /* calculate the ns resolution of this counter */
-        res = cyc_to_ns(1ULL, cd.mult, cd.shift);
-        pr_info("sched_clock: %u bits at %lu%cHz, resolution %lluns, wraps every %lums\n",
-                bits, r, r_unit, res, w);
-
-        /*
-         * Start the timer to keep sched_clock() properly updated and
-         * sets the initial epoch.
-         */
-        sched_clock_timer.data = msecs_to_jiffies(w - (w / 10));
-        update_sched_clock();
-
-        /*
-         * Ensure that sched_clock() starts off at 0ns
-         */
-        cd.epoch_ns = 0;
-
-        /* Enable IRQ time accounting if we have a fast enough sched_clock */
-        if (irqtime > 0 || (irqtime == -1 && rate >= 1000000))
-                enable_sched_clock_irqtime();
-
-        pr_debug("Registered %pF as sched_clock source\n", read);
-}
-
-static unsigned long long notrace sched_clock_32(void)
-{
-        u32 cyc = read_sched_clock();
-        return cyc_to_sched_clock(cyc, sched_clock_mask);
-}
-
-unsigned long long __read_mostly (*sched_clock_func)(void) = sched_clock_32;
-
-unsigned long long notrace sched_clock(void)
-{
-        return sched_clock_func();
-}
-
-void __init sched_clock_postinit(void)
-{
-        /*
-         * If no sched_clock function has been provided at that point,
-         * make it the final one one.
-         */
-        if (read_sched_clock == jiffy_sched_clock_read)
-                setup_sched_clock(jiffy_sched_clock_read, 32, HZ);
-
-        sched_clock_poll(sched_clock_timer.data);
-}
-
-static int sched_clock_suspend(void)
-{
-        sched_clock_poll(sched_clock_timer.data);
-        cd.suspended = true;
-        return 0;
-}
-
-static void sched_clock_resume(void)
-{
-        cd.epoch_cyc = read_sched_clock();
-        cd.epoch_cyc_copy = cd.epoch_cyc;
-        cd.suspended = false;
-}
-
-static struct syscore_ops sched_clock_ops = {
-        .suspend = sched_clock_suspend,
-        .resume = sched_clock_resume,
-};
-
-static int __init sched_clock_syscore_init(void)
-{
-        register_syscore_ops(&sched_clock_ops);
-        return 0;
-}
-device_initcall(sched_clock_syscore_init);
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index b4b1d397592b..afc2489ee13b 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -37,6 +37,7 @@
 #include <asm/cputype.h>
 #include <asm/elf.h>
 #include <asm/procinfo.h>
+#include <asm/psci.h>
 #include <asm/sections.h>
 #include <asm/setup.h>
 #include <asm/smp_plat.h>
@@ -73,7 +74,7 @@ __setup("fpe=", fpe_setup);
 
 extern void paging_init(struct machine_desc *desc);
 extern void sanity_check_meminfo(void);
-extern void reboot_setup(char *str);
+extern enum reboot_mode reboot_mode;
 extern void setup_dma_zone(struct machine_desc *desc);
 
 unsigned int processor_id;
@@ -128,7 +129,9 @@ struct stack {
         u32 und[3];
 } ____cacheline_aligned;
 
+#ifndef CONFIG_CPU_V7M
 static struct stack stacks[NR_CPUS];
+#endif
 
 char elf_platform[ELF_PLATFORM_SIZE];
 EXPORT_SYMBOL(elf_platform);
@@ -207,7 +210,7 @@ static const char *proc_arch[] = {
         "5TEJ",
         "6TEJ",
         "7",
-        "?(11)",
+        "7M",
         "?(12)",
         "?(13)",
         "?(14)",
@@ -216,6 +219,12 @@ static const char *proc_arch[] = {
         "?(17)",
 };
 
+#ifdef CONFIG_CPU_V7M
+static int __get_cpu_architecture(void)
+{
+        return CPU_ARCH_ARMv7M;
+}
+#else
 static int __get_cpu_architecture(void)
 {
         int cpu_arch;
@@ -248,6 +257,7 @@ static int __get_cpu_architecture(void)
 
         return cpu_arch;
 }
+#endif
 
 int __pure cpu_architecture(void)
 {
@@ -293,7 +303,9 @@ static void __init cacheid_init(void)
 {
         unsigned int arch = cpu_architecture();
 
-        if (arch >= CPU_ARCH_ARMv6) {
+        if (arch == CPU_ARCH_ARMv7M) {
+                cacheid = 0;
+        } else if (arch >= CPU_ARCH_ARMv6) {
                 unsigned int cachetype = read_cpuid_cachetype();
                 if ((cachetype & (7 << 29)) == 4 << 29) {
                         /* ARMv7 register format */
@@ -355,7 +367,7 @@ void __init early_print(const char *str, ...)
 
 static void __init cpuid_init_hwcaps(void)
 {
-        unsigned int divide_instrs;
+        unsigned int divide_instrs, vmsa;
 
         if (cpu_architecture() < CPU_ARCH_ARMv7)
                 return;
@@ -368,6 +380,11 @@ static void __init cpuid_init_hwcaps(void)
         case 1:
                 elf_hwcap |= HWCAP_IDIVT;
         }
+
+        /* LPAE implies atomic ldrd/strd instructions */
+        vmsa = (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xf) >> 0;
+        if (vmsa >= 5)
+                elf_hwcap |= HWCAP_LPAE;
 }
 
 static void __init feat_v6_fixup(void)
@@ -392,6 +409,7 @@ static void __init feat_v6_fixup(void)
  */
 void notrace cpu_init(void)
 {
+#ifndef CONFIG_CPU_V7M
         unsigned int cpu = smp_processor_id();
         struct stack *stk = &stacks[cpu];
 
@@ -442,6 +460,7 @@ void notrace cpu_init(void)
               "I" (offsetof(struct stack, und[0])),
               PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
             : "r14");
+#endif
 }
 
 u32 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
@@ -456,9 +475,82 @@ void __init smp_setup_processor_id(void)
         for (i = 1; i < nr_cpu_ids; ++i)
                 cpu_logical_map(i) = i == cpu ? 0 : i;
 
+        /*
+         * clear __my_cpu_offset on boot CPU to avoid hang caused by
+         * using percpu variable early, for example, lockdep will
+         * access percpu variable inside lock_release
+         */
+        set_my_cpu_offset(0);
+
         printk(KERN_INFO "Booting Linux on physical CPU 0x%x\n", mpidr);
 }
 
+struct mpidr_hash mpidr_hash;
+#ifdef CONFIG_SMP
+/**
+ * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
+ *                        level in order to build a linear index from an
+ *                        MPIDR value. Resulting algorithm is a collision
+ *                        free hash carried out through shifting and ORing
+ */
+static void __init smp_build_mpidr_hash(void)
+{
+        u32 i, affinity;
+        u32 fs[3], bits[3], ls, mask = 0;
+        /*
+         * Pre-scan the list of MPIDRS and filter out bits that do
+         * not contribute to affinity levels, ie they never toggle.
+         */
+        for_each_possible_cpu(i)
+                mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
+        pr_debug("mask of set bits 0x%x\n", mask);
+        /*
+         * Find and stash the last and first bit set at all affinity levels to
+         * check how many bits are required to represent them.
+         */
+        for (i = 0; i < 3; i++) {
+                affinity = MPIDR_AFFINITY_LEVEL(mask, i);
+                /*
+                 * Find the MSB bit and LSB bits position
+                 * to determine how many bits are required
+                 * to express the affinity level.
+                 */
+                ls = fls(affinity);
+                fs[i] = affinity ? ffs(affinity) - 1 : 0;
+                bits[i] = ls - fs[i];
+        }
+        /*
+         * An index can be created from the MPIDR by isolating the
+         * significant bits at each affinity level and by shifting
+         * them in order to compress the 24 bits values space to a
+         * compressed set of values. This is equivalent to hashing
+         * the MPIDR through shifting and ORing. It is a collision free
+         * hash though not minimal since some levels might contain a number
+         * of CPUs that is not an exact power of 2 and their bit
+         * representation might contain holes, eg MPIDR[7:0] = {0x2, 0x80}.
+         */
+        mpidr_hash.shift_aff[0] = fs[0];
+        mpidr_hash.shift_aff[1] = MPIDR_LEVEL_BITS + fs[1] - bits[0];
+        mpidr_hash.shift_aff[2] = 2*MPIDR_LEVEL_BITS + fs[2] -
+                                                (bits[1] + bits[0]);
+        mpidr_hash.mask = mask;
+        mpidr_hash.bits = bits[2] + bits[1] + bits[0];
+        pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] mask[0x%x] bits[%u]\n",
+                                mpidr_hash.shift_aff[0],
+                                mpidr_hash.shift_aff[1],
+                                mpidr_hash.shift_aff[2],
+                                mpidr_hash.mask,
+                                mpidr_hash.bits);
+        /*
+         * 4x is an arbitrary value used to warn on a hash table much bigger
+         * than expected on most systems.
+         */
+        if (mpidr_hash_size() > 4 * num_possible_cpus())
+                pr_warn("Large number of MPIDR hash buckets detected\n");
+        sync_cache_w(&mpidr_hash);
+}
+#endif
+
 static void __init setup_processor(void)
 {
         struct proc_info_list *list;
@@ -744,6 +836,8 @@ static int __init meminfo_cmp(const void *_a, const void *_b)
 void __init hyp_mode_check(void)
 {
 #ifdef CONFIG_ARM_VIRT_EXT
+        sync_boot_mode();
+
         if (is_hyp_mode_available()) {
                 pr_info("CPU: All CPU(s) started in HYP mode.\n");
                 pr_info("CPU: Virtualization extensions available.\n");
@@ -769,8 +863,8 @@ void __init setup_arch(char **cmdline_p)
 
         setup_dma_zone(mdesc);
 
-        if (mdesc->restart_mode)
-                reboot_setup(&mdesc->restart_mode);
+        if (mdesc->reboot_mode != REBOOT_HARD)
+                reboot_mode = mdesc->reboot_mode;
 
         init_mm.start_code = (unsigned long) _text;
         init_mm.end_code   = (unsigned long) _etext;
@@ -796,10 +890,17 @@ void __init setup_arch(char **cmdline_p)
         unflatten_device_tree();
 
         arm_dt_init_cpu_maps();
+        psci_init();
 #ifdef CONFIG_SMP
         if (is_smp()) {
-                smp_set_ops(mdesc->smp);
+                if (!mdesc->smp_init || !mdesc->smp_init()) {
+                        if (psci_smp_available())
+                                smp_set_ops(&psci_smp_ops);
+                        else if (mdesc->smp)
+                                smp_set_ops(mdesc->smp);
+                }
                 smp_init_cpus();
+                smp_build_mpidr_hash();
         }
 #endif
 
@@ -872,6 +973,8 @@ static const char *hwcap_str[] = {
         "vfpv4",
         "idiva",
         "idivt",
+        "vfpd32",
+        "lpae",
         NULL
 };
 
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
index 296786bdbb73..ab3304225272 100644
--- a/arch/arm/kernel/signal.c
+++ b/arch/arm/kernel/signal.c
@@ -8,6 +8,7 @@
  * published by the Free Software Foundation.
  */
 #include <linux/errno.h>
+#include <linux/random.h>
 #include <linux/signal.h>
 #include <linux/personality.h>
 #include <linux/uaccess.h>
@@ -15,12 +16,11 @@
 
 #include <asm/elf.h>
 #include <asm/cacheflush.h>
+#include <asm/traps.h>
 #include <asm/ucontext.h>
 #include <asm/unistd.h>
 #include <asm/vfp.h>
 
-#include "signal.h"
-
 /*
  * For ARM syscalls, we encode the syscall number into the instruction.
  */
@@ -40,11 +40,13 @@
 #define SWI_THUMB_SIGRETURN     (0xdf00 << 16 | 0x2700 | (__NR_sigreturn - __NR_SYSCALL_BASE))
 #define SWI_THUMB_RT_SIGRETURN  (0xdf00 << 16 | 0x2700 | (__NR_rt_sigreturn - __NR_SYSCALL_BASE))
 
-const unsigned long sigreturn_codes[7] = {
+static const unsigned long sigreturn_codes[7] = {
         MOV_R7_NR_SIGRETURN,    SWI_SYS_SIGRETURN,    SWI_THUMB_SIGRETURN,
         MOV_R7_NR_RT_SIGRETURN, SWI_SYS_RT_SIGRETURN, SWI_THUMB_RT_SIGRETURN,
 };
 
+static unsigned long signal_return_offset;
+
 #ifdef CONFIG_CRUNCH
 static int preserve_crunch_context(struct crunch_sigframe __user *frame)
 {
@@ -392,17 +394,28 @@ setup_return(struct pt_regs *regs, struct ksignal *ksig,
                 if (ksig->ka.sa.sa_flags & SA_SIGINFO)
                         idx += 3;
 
+                /*
+                 * Put the sigreturn code on the stack no matter which return
+                 * mechanism we use in order to remain ABI compliant
+                 */
                 if (__put_user(sigreturn_codes[idx],   rc) ||
                     __put_user(sigreturn_codes[idx+1], rc+1))
                         return 1;
 
+#ifdef CONFIG_MMU
                 if (cpsr & MODE32_BIT) {
+                        struct mm_struct *mm = current->mm;
+
                         /*
-                         * 32-bit code can use the new high-page
-                         * signal return code support.
+                         * 32-bit code can use the signal return page
+                         * except when the MPU has protected the vectors
+                         * page from PL0
                          */
-                        retcode = KERN_SIGRETURN_CODE + (idx << 2) + thumb;
-                } else {
+                        retcode = mm->context.sigpage + signal_return_offset +
+                                  (idx << 2) + thumb;
+                } else
+#endif
+                {
                         /*
                          * Ensure that the instruction cache sees
                          * the return code written onto the stack.
@@ -603,3 +616,33 @@ do_work_pending(struct pt_regs *regs, unsigned int thread_flags, int syscall)
         } while (thread_flags & _TIF_WORK_MASK);
         return 0;
 }
+
+struct page *get_signal_page(void)
+{
+        unsigned long ptr;
+        unsigned offset;
+        struct page *page;
+        void *addr;
+
+        page = alloc_pages(GFP_KERNEL, 0);
+
+        if (!page)
+                return NULL;
+
+        addr = page_address(page);
+
+        /* Give the signal return code some randomness */
+        offset = 0x200 + (get_random_int() & 0x7fc);
+        signal_return_offset = offset;
+
+        /*
+         * Copy signal return handlers into the vector page, and
+         * set sigreturn to be a pointer to these.
+         */
+        memcpy(addr + offset, sigreturn_codes, sizeof(sigreturn_codes));
+
+        ptr = (unsigned long)addr + offset;
+        flush_icache_range(ptr, ptr + sizeof(sigreturn_codes));
+
+        return page;
+}
diff --git a/arch/arm/kernel/signal.h b/arch/arm/kernel/signal.h
deleted file mode 100644
index 5ff067b7c752..000000000000
--- a/arch/arm/kernel/signal.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- *  linux/arch/arm/kernel/signal.h
- *
- *  Copyright (C) 2005-2009 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#define KERN_SIGRETURN_CODE     (CONFIG_VECTORS_BASE + 0x00000500)
-
-extern const unsigned long sigreturn_codes[7];
diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
index 987dcf33415c..db1536b8b30b 100644
--- a/arch/arm/kernel/sleep.S
+++ b/arch/arm/kernel/sleep.S
@@ -7,6 +7,49 @@
         .text
 
 /*
+ * Implementation of MPIDR hash algorithm through shifting
+ * and OR'ing.
+ *
+ * @dst: register containing hash result
+ * @rs0: register containing affinity level 0 bit shift
+ * @rs1: register containing affinity level 1 bit shift
+ * @rs2: register containing affinity level 2 bit shift
+ * @mpidr: register containing MPIDR value
+ * @mask: register containing MPIDR mask
+ *
+ * Pseudo C-code:
+ *
+ *u32 dst;
+ *
+ *compute_mpidr_hash(u32 rs0, u32 rs1, u32 rs2, u32 mpidr, u32 mask) {
+ *      u32 aff0, aff1, aff2;
+ *      u32 mpidr_masked = mpidr & mask;
+ *      aff0 = mpidr_masked & 0xff;
+ *      aff1 = mpidr_masked & 0xff00;
+ *      aff2 = mpidr_masked & 0xff0000;
+ *      dst = (aff0 >> rs0 | aff1 >> rs1 | aff2 >> rs2);
+ *}
+ * Input registers: rs0, rs1, rs2, mpidr, mask
+ * Output register: dst
+ * Note: input and output registers must be disjoint register sets
+         (eg: a macro instance with mpidr = r1 and dst = r1 is invalid)
+ */
+        .macro compute_mpidr_hash dst, rs0, rs1, rs2, mpidr, mask
+        and     \mpidr, \mpidr, \mask                   @ mask out MPIDR bits
+        and     \dst, \mpidr, #0xff                     @ mask=aff0
+ ARM(   mov     \dst, \dst, lsr \rs0            )       @ dst=aff0>>rs0
+ THUMB( lsr     \dst, \dst, \rs0                )
+        and     \mask, \mpidr, #0xff00                  @ mask = aff1
+ ARM(   orr     \dst, \dst, \mask, lsr \rs1     )       @ dst|=(aff1>>rs1)
+ THUMB( lsr     \mask, \mask, \rs1              )
+ THUMB( orr     \dst, \dst, \mask               )
+        and     \mask, \mpidr, #0xff0000                @ mask = aff2
+ ARM(   orr     \dst, \dst, \mask, lsr \rs2     )       @ dst|=(aff2>>rs2)
+ THUMB( lsr     \mask, \mask, \rs2              )
+ THUMB( orr     \dst, \dst, \mask               )
+        .endm
+
+/*
  * Save CPU state for a suspend.  This saves the CPU general purpose
  * registers, and allocates space on the kernel stack to save the CPU
  * specific registers and some other data for resume.
@@ -29,12 +72,18 @@ ENTRY(__cpu_suspend)
         mov     r1, r4                  @ size of save block
         mov     r2, r5                  @ virtual SP
         ldr     r3, =sleep_save_sp
-#ifdef CONFIG_SMP
-        ALT_SMP(mrc p15, 0, lr, c0, c0, 5)
-        ALT_UP(mov lr, #0)
-        and     lr, lr, #15
+        ldr     r3, [r3, #SLEEP_SAVE_SP_VIRT]
+        ALT_SMP(mrc p15, 0, r9, c0, c0, 5)
+        ALT_UP_B(1f)
+        ldr     r8, =mpidr_hash
+        /*
+         * This ldmia relies on the memory layout of the mpidr_hash
+         * struct mpidr_hash.
+         */
+        ldmia   r8, {r4-r7}     @ r4 = mpidr mask (r5,r6,r7) = l[0,1,2] shifts
+        compute_mpidr_hash      lr, r5, r6, r7, r9, r4
         add     r3, r3, lr, lsl #2
-#endif
+1:
         bl      __cpu_suspend_save
         adr     lr, BSYM(cpu_suspend_abort)
         ldmfd   sp!, {r0, pc}           @ call suspend fn
@@ -81,15 +130,23 @@ ENDPROC(cpu_resume_after_mmu)
         .data
         .align
 ENTRY(cpu_resume)
-#ifdef CONFIG_SMP
-        adr     r0, sleep_save_sp
-        ALT_SMP(mrc p15, 0, r1, c0, c0, 5)
-        ALT_UP(mov r1, #0)
-        and     r1, r1, #15
-        ldr     r0, [r0, r1, lsl #2]    @ stack phys addr
-#else
-        ldr     r0, sleep_save_sp       @ stack phys addr
-#endif
+        mov     r1, #0
+        ALT_SMP(mrc p15, 0, r0, c0, c0, 5)
+        ALT_UP_B(1f)
+        adr     r2, mpidr_hash_ptr
+        ldr     r3, [r2]
+        add     r2, r2, r3              @ r2 = struct mpidr_hash phys address
+        /*
+         * This ldmia relies on the memory layout of the mpidr_hash
+         * struct mpidr_hash.
+         */
+        ldmia   r2, { r3-r6 }   @ r3 = mpidr mask (r4,r5,r6) = l[0,1,2] shifts
+        compute_mpidr_hash      r1, r4, r5, r6, r0, r3
+1:
+        adr     r0, _sleep_save_sp
+        ldr     r0, [r0, #SLEEP_SAVE_SP_PHYS]
+        ldr     r0, [r0, r1, lsl #2]
+
         setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1  @ set SVC, irqs off
         @ load phys pgd, stack, resume fn
   ARM(  ldmia   r0!, {r1, sp, pc}       )
@@ -98,7 +155,11 @@ THUMB(	mov	sp, r2			)
 THUMB(  bx      r3                      )
 ENDPROC(cpu_resume)
 
-sleep_save_sp:
-        .rept   CONFIG_NR_CPUS
-        .long   0                               @ preserve stack phys ptr here
-        .endr
+        .align 2
+mpidr_hash_ptr:
+        .long   mpidr_hash - .                  @ mpidr_hash struct offset
+
+        .type   sleep_save_sp, #object
+ENTRY(sleep_save_sp)
+_sleep_save_sp:
+        .space  SLEEP_SAVE_SP_SZ                @ struct sleep_save_sp
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 5919eb451bb9..c2b4f8f0be9a 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -45,6 +45,7 @@
 #include <asm/smp_plat.h>
 #include <asm/virt.h>
 #include <asm/mach/arch.h>
+#include <asm/mpu.h>
 
 /*
  * as from 2.5, kernels no longer have an init_tasks structure
@@ -57,7 +58,7 @@ struct secondary_data secondary_data;
  * control for which core is the next to come out of the secondary
  * boot "holding pen"
  */
-volatile int __cpuinitdata pen_release = -1;
+volatile int pen_release = -1;
 
 enum ipi_msg_type {
         IPI_WAKEUP,
@@ -78,7 +79,14 @@ void __init smp_set_ops(struct smp_operations *ops)
                 smp_ops = *ops;
 };
 
-int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
+static unsigned long get_arch_pgd(pgd_t *pgd)
+{
+        phys_addr_t pgdir = virt_to_phys(pgd);
+        BUG_ON(pgdir & ARCH_PGD_MASK);
+        return pgdir >> ARCH_PGD_SHIFT;
+}
+
+int __cpu_up(unsigned int cpu, struct task_struct *idle)
 {
         int ret;
 
@@ -87,8 +95,14 @@ int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
          * its stack and the page tables.
          */
         secondary_data.stack = task_stack_page(idle) + THREAD_START_SP;
-        secondary_data.pgdir = virt_to_phys(idmap_pgd);
-        secondary_data.swapper_pg_dir = virt_to_phys(swapper_pg_dir);
+#ifdef CONFIG_ARM_MPU
+        secondary_data.mpu_rgn_szr = mpu_rgn_info.rgns[MPU_RAM_REGION].drsr;
+#endif
+
+#ifdef CONFIG_MMU
+        secondary_data.pgdir = get_arch_pgd(idmap_pgd);
+        secondary_data.swapper_pg_dir = get_arch_pgd(swapper_pg_dir);
+#endif
         __cpuc_flush_dcache_area(&secondary_data, sizeof(secondary_data));
         outer_clean_range(__pa(&secondary_data), __pa(&secondary_data + 1));
 
@@ -112,9 +126,8 @@ int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
                 pr_err("CPU%u: failed to boot: %d\n", cpu, ret);
         }
 
-        secondary_data.stack = NULL;
-        secondary_data.pgdir = 0;
 
+        memset(&secondary_data, 0, sizeof(secondary_data));
         return ret;
 }
 
@@ -125,7 +138,7 @@ void __init smp_init_cpus(void)
                 smp_ops.smp_init_cpus();
 }
 
-int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+int boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         if (smp_ops.smp_boot_secondary)
                 return smp_ops.smp_boot_secondary(cpu, idle);
@@ -157,7 +170,7 @@ static int platform_cpu_disable(unsigned int cpu)
 /*
  * __cpu_disable runs on the processor to be shutdown.
  */
-int __cpuinit __cpu_disable(void)
+int __cpu_disable(void)
 {
         unsigned int cpu = smp_processor_id();
         int ret;
@@ -203,7 +216,7 @@ static DECLARE_COMPLETION(cpu_died);
  * called on the thread which is asking for a CPU to be shutdown -
  * waits until shutdown has completed, or it is timed out.
  */
-void __cpuinit __cpu_die(unsigned int cpu)
+void __cpu_die(unsigned int cpu)
 {
         if (!wait_for_completion_timeout(&cpu_died, msecs_to_jiffies(5000))) {
                 pr_err("CPU%u: cpu didn't die\n", cpu);
@@ -293,7 +306,7 @@ void __ref cpu_die(void)
  * Called by both boot and secondaries to move global data into
  * per-processor storage.
  */
-static void __cpuinit smp_store_cpu_info(unsigned int cpuid)
+static void smp_store_cpu_info(unsigned int cpuid)
 {
         struct cpuinfo_arm *cpu_info = &per_cpu(cpu_data, cpuid);
 
@@ -309,7 +322,7 @@ static void percpu_timer_setup(void);
  * This is the secondary CPU boot entry.  We're using this CPUs
  * idle thread stack, but a set of temporary page tables.
  */
-asmlinkage void __cpuinit secondary_start_kernel(void)
+asmlinkage void secondary_start_kernel(void)
 {
         struct mm_struct *mm = &init_mm;
         unsigned int cpu;
@@ -508,7 +521,7 @@ static void broadcast_timer_set_mode(enum clock_event_mode mode,
 {
 }
 
-static void __cpuinit broadcast_timer_setup(struct clock_event_device *evt)
+static void broadcast_timer_setup(struct clock_event_device *evt)
 {
         evt->name       = "dummy_timer";
         evt->features   = CLOCK_EVT_FEAT_ONESHOT |
@@ -537,7 +550,7 @@ int local_timer_register(struct local_timer_ops *ops)
 }
 #endif
 
-static void __cpuinit percpu_timer_setup(void)
+static void percpu_timer_setup(void)
 {
         unsigned int cpu = smp_processor_id();
         struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu);
diff --git a/arch/arm/kernel/smp_tlb.c b/arch/arm/kernel/smp_tlb.c
index 9a52a07aa40e..c2edfff573c2 100644
--- a/arch/arm/kernel/smp_tlb.c
+++ b/arch/arm/kernel/smp_tlb.c
@@ -70,23 +70,6 @@ static inline void ipi_flush_bp_all(void *ignored)
         local_flush_bp_all();
 }
 
-#ifdef CONFIG_ARM_ERRATA_798181
-static int erratum_a15_798181(void)
-{
-        unsigned int midr = read_cpuid_id();
-
-        /* Cortex-A15 r0p0..r3p2 affected */
-        if ((midr & 0xff0ffff0) != 0x410fc0f0 || midr > 0x413fc0f2)
-                return 0;
-        return 1;
-}
-#else
-static int erratum_a15_798181(void)
-{
-        return 0;
-}
-#endif
-
 static void ipi_flush_tlb_a15_erratum(void *arg)
 {
         dmb();
@@ -103,7 +86,7 @@ static void broadcast_tlb_a15_erratum(void)
 
 static void broadcast_tlb_mm_a15_erratum(struct mm_struct *mm)
 {
-        int cpu, this_cpu;
+        int this_cpu;
         cpumask_t mask = { CPU_BITS_NONE };
 
         if (!erratum_a15_798181())
@@ -111,21 +94,7 @@ static void broadcast_tlb_mm_a15_erratum(struct mm_struct *mm)
 
         dummy_flush_tlb_a15_erratum();
         this_cpu = get_cpu();
-        for_each_online_cpu(cpu) {
-                if (cpu == this_cpu)
-                        continue;
-                /*
-                 * We only need to send an IPI if the other CPUs are running
-                 * the same ASID as the one being invalidated. There is no
-                 * need for locking around the active_asids check since the
-                 * switch_mm() function has at least one dmb() (as required by
-                 * this workaround) in case a context switch happens on
-                 * another CPU after the condition below.
-                 */
-                if (atomic64_read(&mm->context.id) ==
-                    atomic64_read(&per_cpu(active_asids, cpu)))
-                        cpumask_set_cpu(cpu, &mask);
-        }
+        a15_erratum_get_cpumask(this_cpu, mm, &mask);
         smp_call_function_many(&mask, ipi_flush_tlb_a15_erratum, NULL, 1);
         put_cpu();
 }
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index 90525d9d290b..25956204ef23 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -120,7 +120,7 @@ static int twd_rate_change(struct notifier_block *nb,
          * changing cpu.
          */
         if (flags == POST_RATE_CHANGE)
-                smp_call_function(twd_update_frequency,
+                on_each_cpu(twd_update_frequency,
                                   (void *)&cnd->new_rate, 1);
 
         return NOTIFY_OK;
@@ -187,7 +187,7 @@ core_initcall(twd_cpufreq_init);
 
 #endif
 
-static void __cpuinit twd_calibrate_rate(void)
+static void twd_calibrate_rate(void)
 {
         unsigned long count;
         u64 waitjiffies;
@@ -265,7 +265,7 @@ static void twd_get_clock(struct device_node *np)
 /*
  * Setup the local clock events for a CPU.
  */
-static int __cpuinit twd_timer_setup(struct clock_event_device *clk)
+static int twd_timer_setup(struct clock_event_device *clk)
 {
         struct clock_event_device **this_cpu_clk;
         int cpu = smp_processor_id();
@@ -308,7 +308,7 @@ static int __cpuinit twd_timer_setup(struct clock_event_device *clk)
         return 0;
 }
 
-static struct local_timer_ops twd_lt_ops __cpuinitdata = {
+static struct local_timer_ops twd_lt_ops = {
         .setup  = twd_timer_setup,
         .stop   = twd_timer_stop,
 };
diff --git a/arch/arm/kernel/suspend.c b/arch/arm/kernel/suspend.c
index c59c97ea8268..41cf3cbf756d 100644
--- a/arch/arm/kernel/suspend.c
+++ b/arch/arm/kernel/suspend.c
@@ -1,15 +1,54 @@
 #include <linux/init.h>
+#include <linux/slab.h>
 
+#include <asm/cacheflush.h>
 #include <asm/idmap.h>
 #include <asm/pgalloc.h>
 #include <asm/pgtable.h>
 #include <asm/memory.h>
+#include <asm/smp_plat.h>
 #include <asm/suspend.h>
 #include <asm/tlbflush.h>
 
 extern int __cpu_suspend(unsigned long, int (*)(unsigned long));
 extern void cpu_resume_mmu(void);
 
+#ifdef CONFIG_MMU
+/*
+ * Hide the first two arguments to __cpu_suspend - these are an implementation
+ * detail which platform code shouldn't have to know about.
+ */
+int cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
+{
+        struct mm_struct *mm = current->active_mm;
+        int ret;
+
+        if (!idmap_pgd)
+                return -EINVAL;
+
+        /*
+         * Provide a temporary page table with an identity mapping for
+         * the MMU-enable code, required for resuming.  On successful
+         * resume (indicated by a zero return code), we need to switch
+         * back to the correct page tables.
+         */
+        ret = __cpu_suspend(arg, fn);
+        if (ret == 0) {
+                cpu_switch_mm(mm->pgd, mm);
+                local_flush_bp_all();
+                local_flush_tlb_all();
+        }
+
+        return ret;
+}
+#else
+int cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
+{
+        return __cpu_suspend(arg, fn);
+}
+#define idmap_pgd       NULL
+#endif
+
 /*
  * This is called by __cpu_suspend() to save the state, and do whatever
  * flushing is required to ensure that when the CPU goes to sleep we have
@@ -47,30 +86,19 @@ void __cpu_suspend_save(u32 *ptr, u32 ptrsz, u32 sp, u32 *save_ptr)
                           virt_to_phys(save_ptr) + sizeof(*save_ptr));
 }
 
-/*
- * Hide the first two arguments to __cpu_suspend - these are an implementation
- * detail which platform code shouldn't have to know about.
- */
-int cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
-{
-        struct mm_struct *mm = current->active_mm;
-        int ret;
-
-        if (!idmap_pgd)
-                return -EINVAL;
+extern struct sleep_save_sp sleep_save_sp;
 
-        /*
-         * Provide a temporary page table with an identity mapping for
-         * the MMU-enable code, required for resuming.  On successful
-         * resume (indicated by a zero return code), we need to switch
-         * back to the correct page tables.
-         */
-        ret = __cpu_suspend(arg, fn);
-        if (ret == 0) {
-                cpu_switch_mm(mm->pgd, mm);
-                local_flush_bp_all();
-                local_flush_tlb_all();
-        }
+static int cpu_suspend_alloc_sp(void)
+{
+        void *ctx_ptr;
+        /* ctx_ptr is an array of physical addresses */
+        ctx_ptr = kcalloc(mpidr_hash_size(), sizeof(u32), GFP_KERNEL);
 
-        return ret;
+        if (WARN_ON(!ctx_ptr))
+                return -ENOMEM;
+        sleep_save_sp.save_ptr_stash = ctx_ptr;
+        sleep_save_sp.save_ptr_stash_phys = virt_to_phys(ctx_ptr);
+        sync_cache_w(&sleep_save_sp);
+        return 0;
 }
+early_initcall(cpu_suspend_alloc_sp);
diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c
index abff4e9aaee0..98aee3258398 100644
--- a/arch/arm/kernel/time.c
+++ b/arch/arm/kernel/time.c
@@ -24,9 +24,9 @@
 #include <linux/timer.h>
 #include <linux/clocksource.h>
 #include <linux/irq.h>
+#include <linux/sched_clock.h>
 
 #include <asm/thread_info.h>
-#include <asm/sched_clock.h>
 #include <asm/stacktrace.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
@@ -120,6 +120,4 @@ void __init time_init(void)
                 machine_desc->init_time();
         else
                 clocksource_of_init();
-
-        sched_clock_postinit();
 }
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 18b32e8e4497..ab517fcce21b 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -35,8 +35,6 @@
 #include <asm/tls.h>
 #include <asm/system_misc.h>
 
-#include "signal.h"
-
 static const char *handler[]= { "prefetch abort", "data abort", "address exception", "interrupt" };
 
 void *vectors_page;
@@ -581,7 +579,7 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
                 return regs->ARM_r0;
 
         case NR(set_tls):
-                thread->tp_value = regs->ARM_r0;
+                thread->tp_value[0] = regs->ARM_r0;
                 if (tls_emu)
                         return 0;
                 if (has_tls_reg) {
@@ -699,7 +697,7 @@ static int get_tp_trap(struct pt_regs *regs, unsigned int instr)
         int reg = (instr >> 12) & 15;
         if (reg == 15)
                 return 1;
-        regs->uregs[reg] = current_thread_info()->tp_value;
+        regs->uregs[reg] = current_thread_info()->tp_value[0];
         regs->ARM_pc += 4;
         return 0;
 }
@@ -800,47 +798,63 @@ void __init trap_init(void)
         return;
 }
 
-static void __init kuser_get_tls_init(unsigned long vectors)
+#ifdef CONFIG_KUSER_HELPERS
+static void __init kuser_init(void *vectors)
 {
+        extern char __kuser_helper_start[], __kuser_helper_end[];
+        int kuser_sz = __kuser_helper_end - __kuser_helper_start;
+
+        memcpy(vectors + 0x1000 - kuser_sz, __kuser_helper_start, kuser_sz);
+
         /*
          * vectors + 0xfe0 = __kuser_get_tls
          * vectors + 0xfe8 = hardware TLS instruction at 0xffff0fe8
          */
         if (tls_emu || has_tls_reg)
-                memcpy((void *)vectors + 0xfe0, (void *)vectors + 0xfe8, 4);
+                memcpy(vectors + 0xfe0, vectors + 0xfe8, 4);
 }
+#else
+static void __init kuser_init(void *vectors)
+{
+}
+#endif
 
 void __init early_trap_init(void *vectors_base)
 {
+#ifndef CONFIG_CPU_V7M
         unsigned long vectors = (unsigned long)vectors_base;
         extern char __stubs_start[], __stubs_end[];
         extern char __vectors_start[], __vectors_end[];
-        extern char __kuser_helper_start[], __kuser_helper_end[];
-        int kuser_sz = __kuser_helper_end - __kuser_helper_start;
+        unsigned i;
 
         vectors_page = vectors_base;
 
         /*
+         * Poison the vectors page with an undefined instruction.  This
+         * instruction is chosen to be undefined for both ARM and Thumb
+         * ISAs.  The Thumb version is an undefined instruction with a
+         * branch back to the undefined instruction.
+         */
+        for (i = 0; i < PAGE_SIZE / sizeof(u32); i++)
+                ((u32 *)vectors_base)[i] = 0xe7fddef1;
+
+        /*
          * Copy the vectors, stubs and kuser helpers (in entry-armv.S)
          * into the vector page, mapped at 0xffff0000, and ensure these
          * are visible to the instruction stream.
          */
         memcpy((void *)vectors, __vectors_start, __vectors_end - __vectors_start);
-        memcpy((void *)vectors + 0x200, __stubs_start, __stubs_end - __stubs_start);
-        memcpy((void *)vectors + 0x1000 - kuser_sz, __kuser_helper_start, kuser_sz);
+        memcpy((void *)vectors + 0x1000, __stubs_start, __stubs_end - __stubs_start);
 
-        /*
-         * Do processor specific fixups for the kuser helpers
-         */
-        kuser_get_tls_init(vectors);
+        kuser_init(vectors_base);
 
+        flush_icache_range(vectors, vectors + PAGE_SIZE * 2);
+        modify_domain(DOMAIN_USER, DOMAIN_CLIENT);
+#else /* ifndef CONFIG_CPU_V7M */
         /*
-         * Copy signal return handlers into the vector page, and
-         * set sigreturn to be a pointer to these.
+         * on V7-M there is no need to copy the vector table to a dedicated
+         * memory area. The address is configurable and so a table in the kernel
+         * image can be used.
          */
-        memcpy((void *)(vectors + KERN_SIGRETURN_CODE - CONFIG_VECTORS_BASE),
-               sigreturn_codes, sizeof(sigreturn_codes));
-
-        flush_icache_range(vectors, vectors + PAGE_SIZE);
-        modify_domain(DOMAIN_USER, DOMAIN_CLIENT);
+#endif
 }
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index a871b8e00fca..7bcee5c9b604 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -70,10 +70,6 @@ SECTIONS
                 ARM_EXIT_DISCARD(EXIT_TEXT)
                 ARM_EXIT_DISCARD(EXIT_DATA)
                 EXIT_CALL
-#ifndef CONFIG_HOTPLUG
-                *(.ARM.exidx.devexit.text)
-                *(.ARM.extab.devexit.text)
-#endif
 #ifndef CONFIG_MMU
                 *(.fixup)
                 *(__ex_table)
@@ -152,6 +148,23 @@ SECTIONS
         . = ALIGN(PAGE_SIZE);
         __init_begin = .;
 #endif
+        /*
+         * The vectors and stubs are relocatable code, and the
+         * only thing that matters is their relative offsets
+         */
+        __vectors_start = .;
+        .vectors 0 : AT(__vectors_start) {
+                *(.vectors)
+        }
+        . = __vectors_start + SIZEOF(.vectors);
+        __vectors_end = .;
+
+        __stubs_start = .;
+        .stubs 0x1000 : AT(__stubs_start) {
+                *(.stubs)
+        }
+        . = __stubs_start + SIZEOF(.stubs);
+        __stubs_end = .;
 
         INIT_TEXT_SECTION(8)
         .exit.text : {