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authorArnd Bergmann <arnd@arndb.de>2012-03-19 16:46:32 -0400
committerArnd Bergmann <arnd@arndb.de>2012-03-20 05:41:43 -0400
commitb2f1df8d2fc14bf7e6d9d967043d4b60c2efd8dc (patch)
tree065282434bde6ef9b4357c042705c5fcef3782ea /arch/arm/include/asm/hardware
parentc0206e228e34d8b414fcc63db45b831843adea06 (diff)
parent5cd9eb2736a572a9ef2689829f47ffd4262adc00 (diff)
Merge branch 'renesas/timer' into next/timer
Conflicts: arch/arm/mach-shmobile/timer.c This resolves a nonobvious merge conflict between renesas timer changes in the global timer changes with those from the renesas soc branch and last minute bug fixes that went into v3.3. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/include/asm/hardware')
-rw-r--r--arch/arm/include/asm/hardware/pl330.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/include/asm/hardware/pl330.h b/arch/arm/include/asm/hardware/pl330.h
index 575fa8186ca0..c1821385abfa 100644
--- a/arch/arm/include/asm/hardware/pl330.h
+++ b/arch/arm/include/asm/hardware/pl330.h
@@ -41,7 +41,7 @@ enum pl330_dstcachectrl {
41 DCCTRL1, /* Bufferable only */ 41 DCCTRL1, /* Bufferable only */
42 DCCTRL2, /* Cacheable, but do not allocate */ 42 DCCTRL2, /* Cacheable, but do not allocate */
43 DCCTRL3, /* Cacheable and bufferable, but do not allocate */ 43 DCCTRL3, /* Cacheable and bufferable, but do not allocate */
44 DINVALID1 = 8, 44 DINVALID1, /* AWCACHE = 0x1000 */
45 DINVALID2, 45 DINVALID2,
46 DCCTRL6, /* Cacheable write-through, allocate on writes only */ 46 DCCTRL6, /* Cacheable write-through, allocate on writes only */
47 DCCTRL7, /* Cacheable write-back, allocate on writes only */ 47 DCCTRL7, /* Cacheable write-back, allocate on writes only */