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authorLee Jones <lee.jones@linaro.org>2014-07-11 07:54:00 -0400
committerMaxime Coquelin <maxime.coquelin@st.com>2014-10-31 04:59:06 -0400
commitd436a609444b05beeced27cc30be88205c716d59 (patch)
treebf44d7e80b791ca94ac30ce5f573ccd517cc6c18 /arch/arm/boot
parent0f6c28b7a49b14c91dd1ece6495b30508d5bb797 (diff)
ARM: DT: STi: STiH416: Add DT node for MiPHY365x
The MiPHY365x is a Generic PHY which can serve various SATA or PCIe devices. It has 2 ports which it can use for either; both SATA, both PCIe or one of each in any configuration. Acked-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/stih416-b2020.dts10
-rw-r--r--arch/arm/boot/dts/stih416-b2020e.dts10
-rw-r--r--arch/arm/boot/dts/stih416.dtsi22
3 files changed, 42 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/stih416-b2020.dts b/arch/arm/boot/dts/stih416-b2020.dts
index d42ff1dcd89f..7ce798be5e01 100644
--- a/arch/arm/boot/dts/stih416-b2020.dts
+++ b/arch/arm/boot/dts/stih416-b2020.dts
@@ -19,5 +19,15 @@
19 bus-width = <8>; 19 bus-width = <8>;
20 non-removable; 20 non-removable;
21 }; 21 };
22
23 miphy365x_phy: miphy365x@fe382000 {
24 phy_port0: port@fe382000 {
25 st,sata-gen = <3>;
26 };
27
28 phy_port1: port@fe38a000 {
29 st,pcie-tx-pol-inv;
30 };
31 };
22 }; 32 };
23}; 33};
diff --git a/arch/arm/boot/dts/stih416-b2020e.dts b/arch/arm/boot/dts/stih416-b2020e.dts
index a0434b6ae772..fa59224115bb 100644
--- a/arch/arm/boot/dts/stih416-b2020e.dts
+++ b/arch/arm/boot/dts/stih416-b2020e.dts
@@ -37,5 +37,15 @@
37 bus-width = <8>; 37 bus-width = <8>;
38 non-removable; 38 non-removable;
39 }; 39 };
40
41 miphy365x_phy: miphy365x@fe382000 {
42 phy_port0: port@fe382000 {
43 st,sata-gen = <3>;
44 };
45
46 phy_port1: port@fe38a000 {
47 st,pcie-tx-pol-inv;
48 };
49 };
40 }; 50 };
41}; 51};
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index 28091548d915..a54f6832a9ac 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -9,6 +9,8 @@
9#include "stih41x.dtsi" 9#include "stih41x.dtsi"
10#include "stih416-clock.dtsi" 10#include "stih416-clock.dtsi"
11#include "stih416-pinctrl.dtsi" 11#include "stih416-pinctrl.dtsi"
12
13#include <dt-bindings/phy/phy-miphy365x.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/reset-controller/stih416-resets.h> 15#include <dt-bindings/reset-controller/stih416-resets.h>
14/ { 16/ {
@@ -278,5 +280,25 @@
278 clock-names = "mmc"; 280 clock-names = "mmc";
279 clocks = <&clk_s_a1_ls 8>; 281 clocks = <&clk_s_a1_ls 8>;
280 }; 282 };
283
284 miphy365x_phy: miphy365x@fe382000 {
285 compatible = "st,miphy365x-phy";
286 st,syscfg = <&syscfg_rear>;
287 #address-cells = <1>;
288 #size-cells = <1>;
289 ranges;
290
291 phy_port0: port@fe382000 {
292 #phy-cells = <1>;
293 reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
294 reg-names = "sata", "pcie", "syscfg";
295 };
296
297 phy_port1: port@fe38a000 {
298 #phy-cells = <1>;
299 reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;
300 reg-names = "sata", "pcie", "syscfg";
301 };
302 };
281 }; 303 };
282}; 304};