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-rw-r--r--arch/arm/boot/dts/stih416.dtsi22
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index 28091548d915..a54f6832a9ac 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -9,6 +9,8 @@
9#include "stih41x.dtsi" 9#include "stih41x.dtsi"
10#include "stih416-clock.dtsi" 10#include "stih416-clock.dtsi"
11#include "stih416-pinctrl.dtsi" 11#include "stih416-pinctrl.dtsi"
12
13#include <dt-bindings/phy/phy-miphy365x.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/reset-controller/stih416-resets.h> 15#include <dt-bindings/reset-controller/stih416-resets.h>
14/ { 16/ {
@@ -278,5 +280,25 @@
278 clock-names = "mmc"; 280 clock-names = "mmc";
279 clocks = <&clk_s_a1_ls 8>; 281 clocks = <&clk_s_a1_ls 8>;
280 }; 282 };
283
284 miphy365x_phy: miphy365x@fe382000 {
285 compatible = "st,miphy365x-phy";
286 st,syscfg = <&syscfg_rear>;
287 #address-cells = <1>;
288 #size-cells = <1>;
289 ranges;
290
291 phy_port0: port@fe382000 {
292 #phy-cells = <1>;
293 reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
294 reg-names = "sata", "pcie", "syscfg";
295 };
296
297 phy_port1: port@fe38a000 {
298 #phy-cells = <1>;
299 reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;
300 reg-names = "sata", "pcie", "syscfg";
301 };
302 };
281 }; 303 };
282}; 304};