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authorOlof Johansson <olof@lixom.net>2015-04-01 19:29:08 -0400
committerOlof Johansson <olof@lixom.net>2015-04-01 19:29:31 -0400
commitd36d520ae669ab95e6113f3a5e52493dfaa59f8d (patch)
tree1c68428a8f4b46db0a844684a41dbfde406af319 /arch/arm/boot/dts
parent369237ab1fe5539091320f47781d6fe2db0241b9 (diff)
parent914d7d148411997c2f76f689338d27c362300b7a (diff)
Merge tag 'renesas-r8a73a4-ccf-and-multiplatform-for-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/multiplatform
Merge "Renesas ARM Based SoC r8a73a4 CCF and Multiplatform Updates for v4.1" from Simon Horman: * Add CCF and them multiplatform support to r8a73a4 SoC and its ape6evm board. * Then remove legacy r8a73a4 SoC and ape6evm board code. ---------------------------------------------------------------- Geert Uytterhoeven (6): ARM: shmobile: r8a73a4 dtsi: Add Bus State Controller node ARM: shmobile: ape6evm dts: Move Ethernet node to BSC ARM: shmobile: r8a73a4: Move pfc node to work around probe ordering bug ARM: shmobile: ape6evm dts: Drop console= bootargs parameter PM / Domains: R-Mobile SYSC: Document R-Mobile APE6 (r8a73a4) binding ARM: shmobile: r8a73a4 dtsi: Add PM domain support Laurent Pinchart (1): ARM: shmobile: r8a73a4: Remove legacy code Simon Horman (1): ARM: shmobile: r8a73a4: ape6evm: Remove legacy platform Ulrich Hecht (5): ARM: shmobile: r8a73a4: Add CPG register bits header ARM: shmobile: r8a73a4: Common clock framework DT description ARM: shmobile: ape6evm: Disable legacy clock initialization ARM: shmobile: r8a73a4: Add MSTP clock assignments to DT ARM: shmobile: ape6evm-reference: Remove board C code and DT file Documentation/devicetree/bindings/arm/shmobile.txt | 2 - .../bindings/power/renesas,sysc-rmobile.txt | 1 + MAINTAINERS | 1 - arch/arm/boot/dts/Makefile | 2 - arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts | 156 ----- arch/arm/boot/dts/r8a73a4-ape6evm.dts | 37 +- arch/arm/boot/dts/r8a73a4.dtsi | 557 ++++++++++++++++- arch/arm/configs/ape6evm_defconfig | 109 ---- arch/arm/mach-shmobile/Kconfig | 25 - arch/arm/mach-shmobile/Makefile | 3 - arch/arm/mach-shmobile/Makefile.boot | 2 - arch/arm/mach-shmobile/board-ape6evm-reference.c | 60 -- arch/arm/mach-shmobile/board-ape6evm.c | 306 ---------- arch/arm/mach-shmobile/clock-r8a73a4.c | 659 --------------------- arch/arm/mach-shmobile/r8a73a4.h | 17 - arch/arm/mach-shmobile/setup-r8a73a4.c | 273 +-------- include/dt-bindings/clock/r8a73a4-clock.h | 62 ++ 17 files changed, 615 insertions(+), 1657 deletions(-) delete mode 100644 arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts delete mode 100644 arch/arm/configs/ape6evm_defconfig delete mode 100644 arch/arm/mach-shmobile/board-ape6evm-reference.c delete mode 100644 arch/arm/mach-shmobile/board-ape6evm.c delete mode 100644 arch/arm/mach-shmobile/clock-r8a73a4.c delete mode 100644 arch/arm/mach-shmobile/r8a73a4.h create mode 100644 include/dt-bindings/clock/r8a73a4-clock.h * tag 'renesas-r8a73a4-ccf-and-multiplatform-for-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: r8a73a4: Remove legacy code ARM: shmobile: r8a73a4 dtsi: Add PM domain support PM / Domains: R-Mobile SYSC: Document R-Mobile APE6 (r8a73a4) binding ARM: shmobile: ape6evm dts: Drop console= bootargs parameter ARM: shmobile: r8a73a4: ape6evm: Remove legacy platform ARM: shmobile: ape6evm-reference: Remove board C code and DT file ARM: shmobile: r8a73a4: Move pfc node to work around probe ordering bug ARM: shmobile: ape6evm dts: Move Ethernet node to BSC ARM: shmobile: r8a73a4 dtsi: Add Bus State Controller node ARM: shmobile: r8a73a4: Add MSTP clock assignments to DT ARM: shmobile: ape6evm: Disable legacy clock initialization ARM: shmobile: r8a73a4: Common clock framework DT description ARM: shmobile: r8a73a4: Add CPG register bits header Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/boot/dts')
-rw-r--r--arch/arm/boot/dts/Makefile2
-rw-r--r--arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts156
-rw-r--r--arch/arm/boot/dts/r8a73a4-ape6evm.dts37
-rw-r--r--arch/arm/boot/dts/r8a73a4.dtsi557
4 files changed, 550 insertions, 202 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 16f4a6761f5e..5d258e00c5e7 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -464,8 +464,6 @@ dtb-$(CONFIG_ARCH_S5PV210) += \
464 s5pv210-smdkv210.dtb \ 464 s5pv210-smdkv210.dtb \
465 s5pv210-torbreck.dtb 465 s5pv210-torbreck.dtb
466dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += \ 466dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += \
467 r8a73a4-ape6evm.dtb \
468 r8a73a4-ape6evm-reference.dtb \
469 r8a7740-armadillo800eva.dtb \ 467 r8a7740-armadillo800eva.dtb \
470 r8a7778-bockw.dtb \ 468 r8a7778-bockw.dtb \
471 r8a7778-bockw-reference.dtb \ 469 r8a7778-bockw-reference.dtb \
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
deleted file mode 100644
index b3d8f844b57a..000000000000
--- a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
+++ /dev/null
@@ -1,156 +0,0 @@
1/*
2 * Device Tree Source for the APE6EVM board
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/dts-v1/;
12#include "r8a73a4.dtsi"
13#include <dt-bindings/gpio/gpio.h>
14
15/ {
16 model = "APE6EVM";
17 compatible = "renesas,ape6evm-reference", "renesas,r8a73a4";
18
19 aliases {
20 serial0 = &scifa0;
21 };
22
23 chosen {
24 bootargs = "ignore_loglevel rw";
25 stdout-path = &scifa0;
26 };
27
28 memory@40000000 {
29 device_type = "memory";
30 reg = <0 0x40000000 0 0x40000000>;
31 };
32
33 memory@200000000 {
34 device_type = "memory";
35 reg = <2 0x00000000 0 0x40000000>;
36 };
37
38 vcc_mmc0: regulator@0 {
39 compatible = "regulator-fixed";
40 regulator-name = "MMC0 Vcc";
41 regulator-min-microvolt = <2800000>;
42 regulator-max-microvolt = <2800000>;
43 regulator-always-on;
44 };
45
46 vcc_sdhi0: regulator@1 {
47 compatible = "regulator-fixed";
48
49 regulator-name = "SDHI0 Vcc";
50 regulator-min-microvolt = <3300000>;
51 regulator-max-microvolt = <3300000>;
52
53 gpio = <&pfc 76 GPIO_ACTIVE_HIGH>;
54 enable-active-high;
55 };
56
57 /* Common 3.3V rail, used by several devices on APE6EVM */
58 ape6evm_fixed_3v3: regulator@2 {
59 compatible = "regulator-fixed";
60 regulator-name = "3V3";
61 regulator-min-microvolt = <3300000>;
62 regulator-max-microvolt = <3300000>;
63 regulator-always-on;
64 };
65
66 lbsc {
67 compatible = "simple-bus";
68 #address-cells = <1>;
69 #size-cells = <1>;
70 ranges = <0 0 0 0x20000000>;
71 };
72};
73
74&i2c5 {
75 status = "okay";
76 vdd_dvfs: max8973@1b {
77 compatible = "maxim,max8973";
78 reg = <0x1b>;
79
80 regulator-min-microvolt = <935000>;
81 regulator-max-microvolt = <1200000>;
82 regulator-boot-on;
83 regulator-always-on;
84 };
85};
86
87&cpu0 {
88 cpu0-supply = <&vdd_dvfs>;
89 operating-points = <
90 /* kHz uV */
91 1950000 1115000
92 1462500 995000
93 >;
94 voltage-tolerance = <1>; /* 1% */
95};
96
97&cmt1 {
98 status = "okay";
99};
100
101&pfc {
102 scifa0_pins: serial0 {
103 renesas,groups = "scifa0_data";
104 renesas,function = "scifa0";
105 };
106
107 mmc0_pins: mmc {
108 renesas,groups = "mmc0_data8", "mmc0_ctrl";
109 renesas,function = "mmc0";
110 };
111
112 sdhi0_pins: sd0 {
113 renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
114 renesas,function = "sdhi0";
115 };
116
117 sdhi1_pins: sd1 {
118 renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
119 renesas,function = "sdhi1";
120 };
121};
122
123&mmcif0 {
124 vmmc-supply = <&vcc_mmc0>;
125 bus-width = <8>;
126 non-removable;
127 pinctrl-names = "default";
128 pinctrl-0 = <&mmc0_pins>;
129 status = "okay";
130};
131
132&scifa0 {
133 pinctrl-0 = <&scifa0_pins>;
134 pinctrl-names = "default";
135
136 status = "okay";
137};
138
139&sdhi0 {
140 vmmc-supply = <&vcc_sdhi0>;
141 bus-width = <4>;
142 toshiba,mmc-wrprotect-disable;
143 pinctrl-names = "default";
144 pinctrl-0 = <&sdhi0_pins>;
145 status = "okay";
146};
147
148&sdhi1 {
149 vmmc-supply = <&ape6evm_fixed_3v3>;
150 bus-width = <4>;
151 broken-cd;
152 toshiba,mmc-wrprotect-disable;
153 pinctrl-names = "default";
154 pinctrl-0 = <&sdhi1_pins>;
155 status = "okay";
156};
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
index 0d50bef01234..f9e81512201a 100644
--- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts
+++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
@@ -22,7 +22,7 @@
22 }; 22 };
23 23
24 chosen { 24 chosen {
25 bootargs = "console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw"; 25 bootargs = "ignore_loglevel root=/dev/nfs ip=dhcp rw";
26 stdout-path = &scifa0; 26 stdout-path = &scifa0;
27 }; 27 };
28 28
@@ -72,26 +72,6 @@
72 regulator-always-on; 72 regulator-always-on;
73 }; 73 };
74 74
75 lbsc {
76 compatible = "simple-bus";
77 #address-cells = <1>;
78 #size-cells = <1>;
79 ranges = <0 0 0 0x20000000>;
80
81 ethernet@8000000 {
82 compatible = "smsc,lan9220", "smsc,lan9115";
83 reg = <0x08000000 0x1000>;
84 interrupt-parent = <&irqc1>;
85 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
86 phy-mode = "mii";
87 reg-io-width = <4>;
88 smsc,irq-active-high;
89 smsc,irq-push-pull;
90 vdd33a-supply = <&ape6evm_fixed_3v3>;
91 vddvario-supply = <&ape6evm_fixed_1v8>;
92 };
93 };
94
95 leds { 75 leds {
96 compatible = "gpio-leds"; 76 compatible = "gpio-leds";
97 led1 { 77 led1 {
@@ -184,6 +164,21 @@
184 voltage-tolerance = <1>; /* 1% */ 164 voltage-tolerance = <1>; /* 1% */
185}; 165};
186 166
167&bsc {
168 ethernet@8000000 {
169 compatible = "smsc,lan9220", "smsc,lan9115";
170 reg = <0x08000000 0x1000>;
171 interrupt-parent = <&irqc1>;
172 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
173 phy-mode = "mii";
174 reg-io-width = <4>;
175 smsc,irq-active-high;
176 smsc,irq-push-pull;
177 vdd33a-supply = <&ape6evm_fixed_3v3>;
178 vddvario-supply = <&ape6evm_fixed_1v8>;
179 };
180};
181
187&cmt1 { 182&cmt1 {
188 status = "okay"; 183 status = "okay";
189}; 184};
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 38136d9f6d95..0fd889f88109 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -9,6 +9,7 @@
9 * kind, whether express or implied. 9 * kind, whether express or implied.
10 */ 10 */
11 11
12#include <dt-bindings/clock/r8a73a4-clock.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/interrupt-controller/irq.h>
14 15
@@ -27,9 +28,15 @@
27 compatible = "arm,cortex-a15"; 28 compatible = "arm,cortex-a15";
28 reg = <0>; 29 reg = <0>;
29 clock-frequency = <1500000000>; 30 clock-frequency = <1500000000>;
31 power-domains = <&pd_a2sl>;
30 }; 32 };
31 }; 33 };
32 34
35 ptm {
36 compatible = "arm,coresight-etm3x";
37 power-domains = <&pd_d4>;
38 };
39
33 timer { 40 timer {
34 compatible = "arm,armv7-timer"; 41 compatible = "arm,armv7-timer";
35 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 42 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
@@ -41,11 +48,13 @@
41 dbsc1: memory-controller@e6790000 { 48 dbsc1: memory-controller@e6790000 {
42 compatible = "renesas,dbsc-r8a73a4"; 49 compatible = "renesas,dbsc-r8a73a4";
43 reg = <0 0xe6790000 0 0x10000>; 50 reg = <0 0xe6790000 0 0x10000>;
51 power-domains = <&pd_a3bc>;
44 }; 52 };
45 53
46 dbsc2: memory-controller@e67a0000 { 54 dbsc2: memory-controller@e67a0000 {
47 compatible = "renesas,dbsc-r8a73a4"; 55 compatible = "renesas,dbsc-r8a73a4";
48 reg = <0 0xe67a0000 0 0x10000>; 56 reg = <0 0xe67a0000 0 0x10000>;
57 power-domains = <&pd_a3bc>;
49 }; 58 };
50 59
51 dmac: dma-multiplexer { 60 dmac: dma-multiplexer {
@@ -87,38 +96,19 @@
87 "ch8", "ch9", "ch10", "ch11", 96 "ch8", "ch9", "ch10", "ch11",
88 "ch12", "ch13", "ch14", "ch15", 97 "ch12", "ch13", "ch14", "ch15",
89 "ch16", "ch17", "ch18", "ch19"; 98 "ch16", "ch17", "ch18", "ch19";
99 clocks = <&mstp2_clks R8A73A4_CLK_DMAC>;
100 power-domains = <&pd_a3sp>;
90 }; 101 };
91 }; 102 };
92 103
93 pfc: pfc@e6050000 {
94 compatible = "renesas,pfc-r8a73a4";
95 reg = <0 0xe6050000 0 0x9000>;
96 gpio-controller;
97 #gpio-cells = <2>;
98 interrupts-extended =
99 <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>,
100 <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>,
101 <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>,
102 <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>,
103 <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>,
104 <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>,
105 <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>,
106 <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>,
107 <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>,
108 <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>,
109 <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>,
110 <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>,
111 <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>,
112 <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>,
113 <&irqc1 24 0>, <&irqc1 25 0>;
114 };
115
116 i2c5: i2c@e60b0000 { 104 i2c5: i2c@e60b0000 {
117 #address-cells = <1>; 105 #address-cells = <1>;
118 #size-cells = <0>; 106 #size-cells = <0>;
119 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 107 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
120 reg = <0 0xe60b0000 0 0x428>; 108 reg = <0 0xe60b0000 0 0x428>;
121 interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>; 109 interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>;
110 clocks = <&mstp4_clks R8A73A4_CLK_IIC5>;
111 power-domains = <&pd_a3sp>;
122 112
123 status = "disabled"; 113 status = "disabled";
124 }; 114 };
@@ -127,6 +117,9 @@
127 compatible = "renesas,cmt-48-r8a73a4", "renesas,cmt-48-gen2"; 117 compatible = "renesas,cmt-48-r8a73a4", "renesas,cmt-48-gen2";
128 reg = <0 0xe6130000 0 0x1004>; 118 reg = <0 0xe6130000 0 0x1004>;
129 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; 119 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
120 clocks = <&mstp3_clks R8A73A4_CLK_CMT1>;
121 clock-names = "fck";
122 power-domains = <&pd_c5>;
130 123
131 renesas,channels-mask = <0xff>; 124 renesas,channels-mask = <0xff>;
132 125
@@ -170,6 +163,7 @@
170 <0 29 IRQ_TYPE_LEVEL_HIGH>, 163 <0 29 IRQ_TYPE_LEVEL_HIGH>,
171 <0 30 IRQ_TYPE_LEVEL_HIGH>, 164 <0 30 IRQ_TYPE_LEVEL_HIGH>,
172 <0 31 IRQ_TYPE_LEVEL_HIGH>; 165 <0 31 IRQ_TYPE_LEVEL_HIGH>;
166 power-domains = <&pd_c4>;
173 }; 167 };
174 168
175 irqc1: interrupt-controller@e61c0200 { 169 irqc1: interrupt-controller@e61c0200 {
@@ -203,6 +197,31 @@
203 <0 55 IRQ_TYPE_LEVEL_HIGH>, 197 <0 55 IRQ_TYPE_LEVEL_HIGH>,
204 <0 56 IRQ_TYPE_LEVEL_HIGH>, 198 <0 56 IRQ_TYPE_LEVEL_HIGH>,
205 <0 57 IRQ_TYPE_LEVEL_HIGH>; 199 <0 57 IRQ_TYPE_LEVEL_HIGH>;
200 power-domains = <&pd_c4>;
201 };
202
203 pfc: pfc@e6050000 {
204 compatible = "renesas,pfc-r8a73a4";
205 reg = <0 0xe6050000 0 0x9000>;
206 gpio-controller;
207 #gpio-cells = <2>;
208 interrupts-extended =
209 <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>,
210 <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>,
211 <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>,
212 <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>,
213 <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>,
214 <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>,
215 <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>,
216 <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>,
217 <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>,
218 <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>,
219 <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>,
220 <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>,
221 <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>,
222 <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>,
223 <&irqc1 24 0>, <&irqc1 25 0>;
224 power-domains = <&pd_c5>;
206 }; 225 };
207 226
208 thermal@e61f0000 { 227 thermal@e61f0000 {
@@ -210,6 +229,8 @@
210 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, 229 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
211 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; 230 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
212 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; 231 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
232 clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>;
233 power-domains = <&pd_c5>;
213 }; 234 };
214 235
215 i2c0: i2c@e6500000 { 236 i2c0: i2c@e6500000 {
@@ -218,6 +239,8 @@
218 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 239 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
219 reg = <0 0xe6500000 0 0x428>; 240 reg = <0 0xe6500000 0 0x428>;
220 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; 241 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&mstp3_clks R8A73A4_CLK_IIC0>;
243 power-domains = <&pd_a3sp>;
221 status = "disabled"; 244 status = "disabled";
222 }; 245 };
223 246
@@ -227,6 +250,8 @@
227 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 250 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
228 reg = <0 0xe6510000 0 0x428>; 251 reg = <0 0xe6510000 0 0x428>;
229 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; 252 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&mstp3_clks R8A73A4_CLK_IIC1>;
254 power-domains = <&pd_a3sp>;
230 status = "disabled"; 255 status = "disabled";
231 }; 256 };
232 257
@@ -236,6 +261,8 @@
236 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 261 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
237 reg = <0 0xe6520000 0 0x428>; 262 reg = <0 0xe6520000 0 0x428>;
238 interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>; 263 interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&mstp3_clks R8A73A4_CLK_IIC2>;
265 power-domains = <&pd_a3sp>;
239 status = "disabled"; 266 status = "disabled";
240 }; 267 };
241 268
@@ -245,6 +272,8 @@
245 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 272 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
246 reg = <0 0xe6530000 0 0x428>; 273 reg = <0 0xe6530000 0 0x428>;
247 interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>; 274 interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>;
275 clocks = <&mstp4_clks R8A73A4_CLK_IIC3>;
276 power-domains = <&pd_a3sp>;
248 status = "disabled"; 277 status = "disabled";
249 }; 278 };
250 279
@@ -254,6 +283,8 @@
254 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 283 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
255 reg = <0 0xe6540000 0 0x428>; 284 reg = <0 0xe6540000 0 0x428>;
256 interrupts = <0 178 IRQ_TYPE_LEVEL_HIGH>; 285 interrupts = <0 178 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&mstp4_clks R8A73A4_CLK_IIC4>;
287 power-domains = <&pd_a3sp>;
257 status = "disabled"; 288 status = "disabled";
258 }; 289 };
259 290
@@ -263,6 +294,8 @@
263 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 294 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
264 reg = <0 0xe6550000 0 0x428>; 295 reg = <0 0xe6550000 0 0x428>;
265 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; 296 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&mstp3_clks R8A73A4_CLK_IIC6>;
298 power-domains = <&pd_a3sp>;
266 status = "disabled"; 299 status = "disabled";
267 }; 300 };
268 301
@@ -272,6 +305,8 @@
272 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 305 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
273 reg = <0 0xe6560000 0 0x428>; 306 reg = <0 0xe6560000 0 0x428>;
274 interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>; 307 interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>;
308 clocks = <&mstp3_clks R8A73A4_CLK_IIC7>;
309 power-domains = <&pd_a3sp>;
275 status = "disabled"; 310 status = "disabled";
276 }; 311 };
277 312
@@ -281,6 +316,8 @@
281 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 316 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
282 reg = <0 0xe6570000 0 0x428>; 317 reg = <0 0xe6570000 0 0x428>;
283 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; 318 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
319 clocks = <&mstp5_clks R8A73A4_CLK_IIC8>;
320 power-domains = <&pd_a3sp>;
284 status = "disabled"; 321 status = "disabled";
285 }; 322 };
286 323
@@ -288,6 +325,9 @@
288 compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 325 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
289 reg = <0 0xe6c20000 0 0x100>; 326 reg = <0 0xe6c20000 0 0x100>;
290 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; 327 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>;
329 clock-names = "sci_ick";
330 power-domains = <&pd_a3sp>;
291 status = "disabled"; 331 status = "disabled";
292 }; 332 };
293 333
@@ -295,6 +335,9 @@
295 compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 335 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
296 reg = <0 0xe6c30000 0 0x100>; 336 reg = <0 0xe6c30000 0 0x100>;
297 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; 337 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>;
339 clock-names = "sci_ick";
340 power-domains = <&pd_a3sp>;
298 status = "disabled"; 341 status = "disabled";
299 }; 342 };
300 343
@@ -302,6 +345,9 @@
302 compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; 345 compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
303 reg = <0 0xe6c40000 0 0x100>; 346 reg = <0 0xe6c40000 0 0x100>;
304 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; 347 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>;
349 clock-names = "sci_ick";
350 power-domains = <&pd_a3sp>;
305 status = "disabled"; 351 status = "disabled";
306 }; 352 };
307 353
@@ -309,6 +355,9 @@
309 compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; 355 compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
310 reg = <0 0xe6c50000 0 0x100>; 356 reg = <0 0xe6c50000 0 0x100>;
311 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; 357 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>;
359 clock-names = "sci_ick";
360 power-domains = <&pd_a3sp>;
312 status = "disabled"; 361 status = "disabled";
313 }; 362 };
314 363
@@ -316,6 +365,9 @@
316 compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 365 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
317 reg = <0 0xe6ce0000 0 0x100>; 366 reg = <0 0xe6ce0000 0 0x100>;
318 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; 367 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>;
369 clock-names = "sci_ick";
370 power-domains = <&pd_a3sp>;
319 status = "disabled"; 371 status = "disabled";
320 }; 372 };
321 373
@@ -323,6 +375,9 @@
323 compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 375 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
324 reg = <0 0xe6cf0000 0 0x100>; 376 reg = <0 0xe6cf0000 0 0x100>;
325 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; 377 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>;
379 clock-names = "sci_ick";
380 power-domains = <&pd_c4>;
326 status = "disabled"; 381 status = "disabled";
327 }; 382 };
328 383
@@ -330,6 +385,8 @@
330 compatible = "renesas,sdhi-r8a73a4"; 385 compatible = "renesas,sdhi-r8a73a4";
331 reg = <0 0xee100000 0 0x100>; 386 reg = <0 0xee100000 0 0x100>;
332 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; 387 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>;
389 power-domains = <&pd_a3sp>;
333 cap-sd-highspeed; 390 cap-sd-highspeed;
334 status = "disabled"; 391 status = "disabled";
335 }; 392 };
@@ -338,6 +395,8 @@
338 compatible = "renesas,sdhi-r8a73a4"; 395 compatible = "renesas,sdhi-r8a73a4";
339 reg = <0 0xee120000 0 0x100>; 396 reg = <0 0xee120000 0 0x100>;
340 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; 397 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>;
399 power-domains = <&pd_a3sp>;
341 cap-sd-highspeed; 400 cap-sd-highspeed;
342 status = "disabled"; 401 status = "disabled";
343 }; 402 };
@@ -346,6 +405,8 @@
346 compatible = "renesas,sdhi-r8a73a4"; 405 compatible = "renesas,sdhi-r8a73a4";
347 reg = <0 0xee140000 0 0x100>; 406 reg = <0 0xee140000 0 0x100>;
348 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; 407 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>;
409 power-domains = <&pd_a3sp>;
349 cap-sd-highspeed; 410 cap-sd-highspeed;
350 status = "disabled"; 411 status = "disabled";
351 }; 412 };
@@ -354,6 +415,8 @@
354 compatible = "renesas,sh-mmcif"; 415 compatible = "renesas,sh-mmcif";
355 reg = <0 0xee200000 0 0x80>; 416 reg = <0 0xee200000 0 0x80>;
356 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; 417 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>;
419 power-domains = <&pd_a3sp>;
357 reg-io-width = <4>; 420 reg-io-width = <4>;
358 status = "disabled"; 421 status = "disabled";
359 }; 422 };
@@ -362,6 +425,8 @@
362 compatible = "renesas,sh-mmcif"; 425 compatible = "renesas,sh-mmcif";
363 reg = <0 0xee220000 0 0x80>; 426 reg = <0 0xee220000 0 0x80>;
364 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; 427 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>;
429 power-domains = <&pd_a3sp>;
365 reg-io-width = <4>; 430 reg-io-width = <4>;
366 status = "disabled"; 431 status = "disabled";
367 }; 432 };
@@ -377,4 +442,450 @@
377 <0 0xf1006000 0 0x2000>; 442 <0 0xf1006000 0 0x2000>;
378 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 443 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
379 }; 444 };
445
446 bsc: bus@fec10000 {
447 compatible = "renesas,bsc-r8a73a4", "renesas,bsc",
448 "simple-pm-bus";
449 #address-cells = <1>;
450 #size-cells = <1>;
451 ranges = <0 0 0 0x20000000>;
452 reg = <0 0xfec10000 0 0x400>;
453 clocks = <&zb_clk>;
454 power-domains = <&pd_c4>;
455 };
456
457 clocks {
458 #address-cells = <2>;
459 #size-cells = <2>;
460 ranges;
461
462 /* External root clocks */
463 extalr_clk: extalr_clk {
464 compatible = "fixed-clock";
465 #clock-cells = <0>;
466 clock-frequency = <32768>;
467 clock-output-names = "extalr";
468 };
469 extal1_clk: extal1_clk {
470 compatible = "fixed-clock";
471 #clock-cells = <0>;
472 clock-frequency = <25000000>;
473 clock-output-names = "extal1";
474 };
475 extal2_clk: extal2_clk {
476 compatible = "fixed-clock";
477 #clock-cells = <0>;
478 clock-frequency = <48000000>;
479 clock-output-names = "extal2";
480 };
481 fsiack_clk: fsiack_clk {
482 compatible = "fixed-clock";
483 #clock-cells = <0>;
484 /* This value must be overridden by the board. */
485 clock-frequency = <0>;
486 clock-output-names = "fsiack";
487 };
488 fsibck_clk: fsibck_clk {
489 compatible = "fixed-clock";
490 #clock-cells = <0>;
491 /* This value must be overridden by the board. */
492 clock-frequency = <0>;
493 clock-output-names = "fsibck";
494 };
495
496 /* Special CPG clocks */
497 cpg_clocks: cpg_clocks@e6150000 {
498 compatible = "renesas,r8a73a4-cpg-clocks";
499 reg = <0 0xe6150000 0 0x10000>;
500 clocks = <&extal1_clk>, <&extal2_clk>;
501 #clock-cells = <1>;
502 clock-output-names = "main", "pll0", "pll1", "pll2",
503 "pll2s", "pll2h", "z", "z2",
504 "i", "m3", "b", "m1", "m2",
505 "zx", "zs", "hp";
506 };
507
508 /* Variable factor clocks (DIV6) */
509 zb_clk: zb_clk@e6150010 {
510 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
511 reg = <0 0xe6150010 0 4>;
512 clocks = <&pll1_div2_clk>, <0>,
513 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
514 #clock-cells = <0>;
515 clock-output-names = "zb";
516 };
517 sdhi0_clk: sdhi0_clk@e6150074 {
518 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
519 reg = <0 0xe6150074 0 4>;
520 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
521 <0>, <&extal2_clk>;
522 #clock-cells = <0>;
523 clock-output-names = "sdhi0ck";
524 };
525 sdhi1_clk: sdhi1_clk@e6150078 {
526 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
527 reg = <0 0xe6150078 0 4>;
528 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
529 <0>, <&extal2_clk>;
530 #clock-cells = <0>;
531 clock-output-names = "sdhi1ck";
532 };
533 sdhi2_clk: sdhi2_clk@e615007c {
534 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
535 reg = <0 0xe615007c 0 4>;
536 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
537 <0>, <&extal2_clk>;
538 #clock-cells = <0>;
539 clock-output-names = "sdhi2ck";
540 };
541 mmc0_clk: mmc0_clk@e6150240 {
542 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
543 reg = <0 0xe6150240 0 4>;
544 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
545 <0>, <&extal2_clk>;
546 #clock-cells = <0>;
547 clock-output-names = "mmc0";
548 };
549 mmc1_clk: mmc1_clk@e6150244 {
550 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
551 reg = <0 0xe6150244 0 4>;
552 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
553 <0>, <&extal2_clk>;
554 #clock-cells = <0>;
555 clock-output-names = "mmc1";
556 };
557 vclk1_clk: vclk1_clk@e6150008 {
558 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
559 reg = <0 0xe6150008 0 4>;
560 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
561 <0>, <&extal2_clk>, <&main_div2_clk>,
562 <&extalr_clk>, <0>, <0>;
563 #clock-cells = <0>;
564 clock-output-names = "vclk1";
565 };
566 vclk2_clk: vclk2_clk@e615000c {
567 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
568 reg = <0 0xe615000c 0 4>;
569 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
570 <0>, <&extal2_clk>, <&main_div2_clk>,
571 <&extalr_clk>, <0>, <0>;
572 #clock-cells = <0>;
573 clock-output-names = "vclk2";
574 };
575 vclk3_clk: vclk3_clk@e615001c {
576 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
577 reg = <0 0xe615001c 0 4>;
578 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
579 <0>, <&extal2_clk>, <&main_div2_clk>,
580 <&extalr_clk>, <0>, <0>;
581 #clock-cells = <0>;
582 clock-output-names = "vclk3";
583 };
584 vclk4_clk: vclk4_clk@e6150014 {
585 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
586 reg = <0 0xe6150014 0 4>;
587 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
588 <0>, <&extal2_clk>, <&main_div2_clk>,
589 <&extalr_clk>, <0>, <0>;
590 #clock-cells = <0>;
591 clock-output-names = "vclk4";
592 };
593 vclk5_clk: vclk5_clk@e6150034 {
594 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
595 reg = <0 0xe6150034 0 4>;
596 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
597 <0>, <&extal2_clk>, <&main_div2_clk>,
598 <&extalr_clk>, <0>, <0>;
599 #clock-cells = <0>;
600 clock-output-names = "vclk5";
601 };
602 fsia_clk: fsia_clk@e6150018 {
603 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
604 reg = <0 0xe6150018 0 4>;
605 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
606 <&fsiack_clk>, <0>;
607 #clock-cells = <0>;
608 clock-output-names = "fsia";
609 };
610 fsib_clk: fsib_clk@e6150090 {
611 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
612 reg = <0 0xe6150090 0 4>;
613 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
614 <&fsibck_clk>, <0>;
615 #clock-cells = <0>;
616 clock-output-names = "fsib";
617 };
618 mp_clk: mp_clk@e6150080 {
619 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
620 reg = <0 0xe6150080 0 4>;
621 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
622 <&extal2_clk>, <&extal2_clk>;
623 #clock-cells = <0>;
624 clock-output-names = "mp";
625 };
626 m4_clk: m4_clk@e6150098 {
627 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
628 reg = <0 0xe6150098 0 4>;
629 clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>;
630 #clock-cells = <0>;
631 clock-output-names = "m4";
632 };
633 hsi_clk: hsi_clk@e615026c {
634 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
635 reg = <0 0xe615026c 0 4>;
636 clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>,
637 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
638 #clock-cells = <0>;
639 clock-output-names = "hsi";
640 };
641 spuv_clk: spuv_clk@e6150094 {
642 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
643 reg = <0 0xe6150094 0 4>;
644 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
645 <&extal2_clk>, <&extal2_clk>;
646 #clock-cells = <0>;
647 clock-output-names = "spuv";
648 };
649
650 /* Fixed factor clocks */
651 main_div2_clk: main_div2_clk {
652 compatible = "fixed-factor-clock";
653 clocks = <&cpg_clocks R8A73A4_CLK_MAIN>;
654 #clock-cells = <0>;
655 clock-div = <2>;
656 clock-mult = <1>;
657 clock-output-names = "main_div2";
658 };
659 pll0_div2_clk: pll0_div2_clk {
660 compatible = "fixed-factor-clock";
661 clocks = <&cpg_clocks R8A73A4_CLK_PLL0>;
662 #clock-cells = <0>;
663 clock-div = <2>;
664 clock-mult = <1>;
665 clock-output-names = "pll0_div2";
666 };
667 pll1_div2_clk: pll1_div2_clk {
668 compatible = "fixed-factor-clock";
669 clocks = <&cpg_clocks R8A73A4_CLK_PLL1>;
670 #clock-cells = <0>;
671 clock-div = <2>;
672 clock-mult = <1>;
673 clock-output-names = "pll1_div2";
674 };
675 extal1_div2_clk: extal1_div2_clk {
676 compatible = "fixed-factor-clock";
677 clocks = <&extal1_clk>;
678 #clock-cells = <0>;
679 clock-div = <2>;
680 clock-mult = <1>;
681 clock-output-names = "extal1_div2";
682 };
683
684 /* Gate clocks */
685 mstp2_clks: mstp2_clks@e6150138 {
686 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
687 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
688 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
689 <&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
690 #clock-cells = <1>;
691 clock-indices = <
692 R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1
693 R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1
694 R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3
695 R8A73A4_CLK_DMAC
696 >;
697 clock-output-names =
698 "scifa0", "scifa1", "scifb0", "scifb1",
699 "scifb2", "scifb3", "dmac";
700 };
701 mstp3_clks: mstp3_clks@e615013c {
702 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
703 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
704 clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>,
705 <&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>,
706 <&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>,
707 <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks
708 R8A73A4_CLK_HP>, <&cpg_clocks
709 R8A73A4_CLK_HP>, <&extalr_clk>;
710 #clock-cells = <1>;
711 clock-indices = <
712 R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1
713 R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1
714 R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0
715 R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7
716 R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1
717 R8A73A4_CLK_CMT1
718 >;
719 clock-output-names =
720 "iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0",
721 "mmcif0", "iic6", "iic7", "iic0", "iic1",
722 "cmt1";
723 };
724 mstp4_clks: mstp4_clks@e6150140 {
725 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
726 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
727 clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_HP>,
728 <&cpg_clocks R8A73A4_CLK_HP>;
729 #clock-cells = <1>;
730 clock-indices = <
731 R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4
732 R8A73A4_CLK_IIC3
733 >;
734 clock-output-names =
735 "iic5", "iic4", "iic3";
736 };
737 mstp5_clks: mstp5_clks@e6150144 {
738 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
739 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
740 clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
741 #clock-cells = <1>;
742 clock-indices = <
743 R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8
744 >;
745 clock-output-names =
746 "thermal", "iic8";
747 };
748 };
749
750 sysc: system-controller@e6180000 {
751 compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile";
752 reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>;
753
754 pm-domains {
755 pd_c5: c5 {
756 #address-cells = <1>;
757 #size-cells = <0>;
758 #power-domain-cells = <0>;
759
760 pd_c4: c4@0 {
761 reg = <0>;
762 #address-cells = <1>;
763 #size-cells = <0>;
764 #power-domain-cells = <0>;
765
766 pd_a3sg: a3sg@16 {
767 reg = <16>;
768 #power-domain-cells = <0>;
769 };
770
771 pd_a3ex: a3ex@17 {
772 reg = <17>;
773 #power-domain-cells = <0>;
774 };
775
776 pd_a3sp: a3sp@18 {
777 reg = <18>;
778 #address-cells = <1>;
779 #size-cells = <0>;
780 #power-domain-cells = <0>;
781
782 pd_a2us: a2us@19 {
783 reg = <19>;
784 #power-domain-cells = <0>;
785 };
786 };
787
788 pd_a3sm: a3sm@20 {
789 reg = <20>;
790 #address-cells = <1>;
791 #size-cells = <0>;
792 #power-domain-cells = <0>;
793
794 pd_a2sl: a2sl@21 {
795 reg = <21>;
796 #power-domain-cells = <0>;
797 };
798 };
799
800 pd_a3km: a3km@22 {
801 reg = <22>;
802 #address-cells = <1>;
803 #size-cells = <0>;
804 #power-domain-cells = <0>;
805
806 pd_a2kl: a2kl@23 {
807 reg = <23>;
808 #power-domain-cells = <0>;
809 };
810 };
811 };
812
813 pd_c4ma: c4ma@1 {
814 reg = <1>;
815 #power-domain-cells = <0>;
816 };
817
818 pd_c4cl: c4cl@2 {
819 reg = <2>;
820 #power-domain-cells = <0>;
821 };
822
823 pd_d4: d4@3 {
824 reg = <3>;
825 #power-domain-cells = <0>;
826 };
827
828 pd_a4bc: a4bc@4 {
829 reg = <4>;
830 #address-cells = <1>;
831 #size-cells = <0>;
832 #power-domain-cells = <0>;
833
834 pd_a3bc: a3bc@5 {
835 reg = <5>;
836 #power-domain-cells = <0>;
837 };
838 };
839
840 pd_a4l: a4l@6 {
841 reg = <6>;
842 #power-domain-cells = <0>;
843 };
844
845 pd_a4lc: a4lc@7 {
846 reg = <7>;
847 #power-domain-cells = <0>;
848 };
849
850 pd_a4mp: a4mp@8 {
851 reg = <8>;
852 #address-cells = <1>;
853 #size-cells = <0>;
854 #power-domain-cells = <0>;
855
856 pd_a3mp: a3mp@9 {
857 reg = <9>;
858 #power-domain-cells = <0>;
859 };
860
861 pd_a3vc: a3vc@10 {
862 reg = <10>;
863 #power-domain-cells = <0>;
864 };
865 };
866
867 pd_a4sf: a4sf@11 {
868 reg = <11>;
869 #power-domain-cells = <0>;
870 };
871
872 pd_a3r: a3r@12 {
873 reg = <12>;
874 #address-cells = <1>;
875 #size-cells = <0>;
876 #power-domain-cells = <0>;
877
878 pd_a2rv: a2rv@13 {
879 reg = <13>;
880 #power-domain-cells = <0>;
881 };
882
883 pd_a2is: a2is@14 {
884 reg = <14>;
885 #power-domain-cells = <0>;
886 };
887 };
888 };
889 };
890 };
380}; 891};
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-31 19:27:30 -0400