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authorArnd Bergmann <arnd@arndb.de>2015-03-11 16:14:55 -0400
committerArnd Bergmann <arnd@arndb.de>2015-03-11 16:14:55 -0400
commit369237ab1fe5539091320f47781d6fe2db0241b9 (patch)
treedde849f93c9d7f9b9cef8128030dbaa939f77265 /arch/arm/boot/dts
parent605e0f904bb6b9ba13f8d7918f3c016ac00b86bc (diff)
parent3915d36fabf143dffdf91c5372d3b0a23722af52 (diff)
Merge tag 'renesas-r8a7778-ccf-and-multiplatform-for-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/multiplatform
Pull "Renesas ARM Based SoC r8a7778 CCF and Multiplatform Updates for v4.1" from Simon Horman: * Add CCF and them multiplatform support to r8a7778 SoC and its bockw board. * tag 'renesas-r8a7778-ccf-and-multiplatform-for-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (21 commits) ARM: shmobile: r8a7778: enable multiplatform target ARM: shmobile: bockw: add sound to DT ARM: shmobile: r8a7778: add sound to DT ARM: shmobile: bockw: add devices hooked up to i2c0 to DT DT: i2c: add trivial binding for OKI ML86V7667 video decoder ARM: shmobile: r8a7778: common clock framework CPG driver ARM: shmobile: bockw dts: set extal clock frequency ARM: shmobile: bockw dts: Move Ethernet node to BSC ARM: shmobile: r8a7778 dtsi: Add Bus State Controller node ARM: shmobile: bockw: add USB, VIN pin descriptions to DT ARM: shmobile: r8a7778: add internal ethernet controller to DT ARM: shmobile: r8a7778: add MSTP clock assignments to DT ARM: shmobile: r8a7778: implement SoC and board CCF support ARM: shmobile: r8a7778: Common clock framework DT description ARM: shmobile: r8a7778: add CPG register bits header ARM: shmobile: r8a7778: synchronize dts with reference platform drivers: bus: Add Simple Power-Managed Bus Driver drivers: bus: Add Renesas Bus State Controller (BSC) DT Bindings drivers: bus: Add Simple Power-Managed Bus DT Bindings drivers: bus: Sort Makefile entries alphabetically ...
Diffstat (limited to 'arch/arm/boot/dts')
-rw-r--r--arch/arm/boot/dts/Makefile1
-rw-r--r--arch/arm/boot/dts/r8a7778-bockw.dts174
-rw-r--r--arch/arm/boot/dts/r8a7778.dtsi293
3 files changed, 468 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 0d467b877ec7..16f4a6761f5e 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -477,6 +477,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
477 r7s72100-genmai.dtb \ 477 r7s72100-genmai.dtb \
478 r8a73a4-ape6evm.dtb \ 478 r8a73a4-ape6evm.dtb \
479 r8a7740-armadillo800eva.dtb \ 479 r8a7740-armadillo800eva.dtb \
480 r8a7778-bockw.dtb \
480 r8a7779-marzen.dtb \ 481 r8a7779-marzen.dtb \
481 r8a7790-lager.dtb \ 482 r8a7790-lager.dtb \
482 r8a7791-henninger.dtb \ 483 r8a7791-henninger.dtb \
diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/r8a7778-bockw.dts
index 46a884d45175..787fa6f9f46d 100644
--- a/arch/arm/boot/dts/r8a7778-bockw.dts
+++ b/arch/arm/boot/dts/r8a7778-bockw.dts
@@ -16,17 +16,191 @@
16 16
17/dts-v1/; 17/dts-v1/;
18#include "r8a7778.dtsi" 18#include "r8a7778.dtsi"
19#include <dt-bindings/interrupt-controller/irq.h>
20#include <dt-bindings/gpio/gpio.h>
19 21
20/ { 22/ {
21 model = "bockw"; 23 model = "bockw";
22 compatible = "renesas,bockw", "renesas,r8a7778"; 24 compatible = "renesas,bockw", "renesas,r8a7778";
23 25
26 aliases {
27 serial0 = &scif0;
28 };
29
24 chosen { 30 chosen {
25 bootargs = "console=ttySC0,115200 ignore_loglevel ip=dhcp root=/dev/nfs rw"; 31 bootargs = "console=ttySC0,115200 ignore_loglevel ip=dhcp root=/dev/nfs rw";
32 stdout-path = &scif0;
26 }; 33 };
27 34
28 memory { 35 memory {
29 device_type = "memory"; 36 device_type = "memory";
30 reg = <0x60000000 0x10000000>; 37 reg = <0x60000000 0x10000000>;
31 }; 38 };
39
40 fixedregulator3v3: fixedregulator@0 {
41 compatible = "regulator-fixed";
42 regulator-name = "fixed-3.3V";
43 regulator-min-microvolt = <3300000>;
44 regulator-max-microvolt = <3300000>;
45 regulator-boot-on;
46 regulator-always-on;
47 };
48
49 sound {
50 compatible = "simple-audio-card";
51
52 simple-audio-card,format = "left_j";
53 simple-audio-card,bitclock-master = <&sndcodec>;
54 simple-audio-card,frame-master = <&sndcodec>;
55
56 sndcpu: simple-audio-card,cpu {
57 sound-dai = <&rcar_sound>;
58 };
59
60 sndcodec: simple-audio-card,codec {
61 sound-dai = <&ak4643>;
62 system-clock-frequency = <11289600>;
63 };
64 };
65};
66
67&bsc {
68 ethernet@18300000 {
69 compatible = "smsc,lan9220", "smsc,lan9115";
70 reg = <0x18300000 0x1000>;
71
72 phy-mode = "mii";
73 interrupt-parent = <&irqpin>;
74 interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
75 reg-io-width = <4>;
76 vddvario-supply = <&fixedregulator3v3>;
77 vdd33a-supply = <&fixedregulator3v3>;
78 };
79};
80
81&extal_clk {
82 clock-frequency = <33333333>;
83};
84
85&i2c0 {
86 status = "okay";
87
88 ak4643: sound-codec@12 {
89 compatible = "asahi-kasei,ak4643";
90 #sound-dai-cells = <0>;
91 reg = <0x12>;
92 };
93
94 camera@41 {
95 compatible = "oki,ml86v7667";
96 reg = <0x41>;
97 };
98
99 camera@43 {
100 compatible = "oki,ml86v7667";
101 reg = <0x43>;
102 };
103
104 rx8581: rtc@51 {
105 compatible = "epson,rx8581";
106 reg = <0x51>;
107 };
108};
109
110&mmcif {
111 pinctrl-0 = <&mmc_pins>;
112 pinctrl-names = "default";
113
114 vmmc-supply = <&fixedregulator3v3>;
115 bus-width = <8>;
116 broken-cd;
117 status = "okay";
118};
119
120&irqpin {
121 status = "okay";
122};
123
124&tmu0 {
125 status = "okay";
126};
127
128&pfc {
129 scif0_pins: serial0 {
130 renesas,groups = "scif0_data_a", "scif0_ctrl";
131 renesas,function = "scif0";
132 };
133
134 mmc_pins: mmc {
135 renesas,groups = "mmc_data8", "mmc_ctrl";
136 renesas,function = "mmc";
137 };
138
139 sdhi0_pins: sd0 {
140 renesas,groups = "sdhi0_data4", "sdhi0_ctrl",
141 "sdhi0_cd";
142 renesas,function = "sdhi0";
143 };
144
145 hspi0_pins: hspi0 {
146 renesas,groups = "hspi0_a";
147 renesas,function = "hspi0";
148 };
149
150 usb0_pins: usb0 {
151 renesas,groups = "usb0";
152 renesas,function = "usb0";
153 };
154
155 usb1_pins: usb1 {
156 renesas,groups = "usb1";
157 renesas,function = "usb1";
158 };
159
160 vin0_pins: vin0 {
161 renesas,groups = "vin0_data8", "vin0_clk";
162 renesas,function = "vin0";
163 };
164
165 vin1_pins: vin1 {
166 renesas,groups = "vin1_data8", "vin1_clk";
167 renesas,function = "vin1";
168 };
169};
170
171&sdhi0 {
172 pinctrl-0 = <&sdhi0_pins>;
173 pinctrl-names = "default";
174
175 vmmc-supply = <&fixedregulator3v3>;
176 bus-width = <4>;
177 status = "okay";
178 wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
179};
180
181&hspi0 {
182 pinctrl-0 = <&hspi0_pins>;
183 pinctrl-names = "default";
184 status = "okay";
185
186 flash: flash@0 {
187 #address-cells = <1>;
188 #size-cells = <1>;
189 compatible = "spansion,s25fl008k";
190 reg = <0>;
191 spi-max-frequency = <104000000>;
192 m25p,fast-read;
193
194 partition@0 {
195 label = "data(spi)";
196 reg = <0x00000000 0x00100000>;
197 };
198 };
199};
200
201&scif0 {
202 pinctrl-0 = <&scif0_pins>;
203 pinctrl-names = "default";
204
205 status = "okay";
32}; 206};
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index ef8533910029..868f97309533 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -16,6 +16,7 @@
16 16
17/include/ "skeleton.dtsi" 17/include/ "skeleton.dtsi"
18 18
19#include <dt-bindings/clock/r8a7778-clock.h>
19#include <dt-bindings/interrupt-controller/irq.h> 20#include <dt-bindings/interrupt-controller/irq.h>
20 21
21/ { 22/ {
@@ -40,6 +41,24 @@
40 spi2 = &hspi2; 41 spi2 = &hspi2;
41 }; 42 };
42 43
44 bsc: bus@1c000000 {
45 compatible = "simple-bus";
46 #address-cells = <1>;
47 #size-cells = <1>;
48 ranges = <0 0 0x1c000000>;
49 };
50
51 ether: ethernet@fde00000 {
52 compatible = "renesas,ether-r8a7778";
53 reg = <0xfde00000 0x400>;
54 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
55 clocks = <&mstp1_clks R8A7778_CLK_ETHER>;
56 phy-mode = "rmii";
57 #address-cells = <1>;
58 #size-cells = <0>;
59 status = "disabled";
60 };
61
43 gic: interrupt-controller@fe438000 { 62 gic: interrupt-controller@fe438000 {
44 compatible = "arm,cortex-a9-gic"; 63 compatible = "arm,cortex-a9-gic";
45 #interrupt-cells = <3>; 64 #interrupt-cells = <3>;
@@ -132,6 +151,7 @@
132 compatible = "renesas,i2c-r8a7778"; 151 compatible = "renesas,i2c-r8a7778";
133 reg = <0xffc70000 0x1000>; 152 reg = <0xffc70000 0x1000>;
134 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; 153 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
154 clocks = <&mstp0_clks R8A7778_CLK_I2C0>;
135 status = "disabled"; 155 status = "disabled";
136 }; 156 };
137 157
@@ -141,6 +161,7 @@
141 compatible = "renesas,i2c-r8a7778"; 161 compatible = "renesas,i2c-r8a7778";
142 reg = <0xffc71000 0x1000>; 162 reg = <0xffc71000 0x1000>;
143 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; 163 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
164 clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
144 status = "disabled"; 165 status = "disabled";
145 }; 166 };
146 167
@@ -150,6 +171,7 @@
150 compatible = "renesas,i2c-r8a7778"; 171 compatible = "renesas,i2c-r8a7778";
151 reg = <0xffc72000 0x1000>; 172 reg = <0xffc72000 0x1000>;
152 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>; 173 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
174 clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
153 status = "disabled"; 175 status = "disabled";
154 }; 176 };
155 177
@@ -159,6 +181,7 @@
159 compatible = "renesas,i2c-r8a7778"; 181 compatible = "renesas,i2c-r8a7778";
160 reg = <0xffc73000 0x1000>; 182 reg = <0xffc73000 0x1000>;
161 interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>; 183 interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
184 clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
162 status = "disabled"; 185 status = "disabled";
163 }; 186 };
164 187
@@ -168,6 +191,8 @@
168 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, 191 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
169 <0 33 IRQ_TYPE_LEVEL_HIGH>, 192 <0 33 IRQ_TYPE_LEVEL_HIGH>,
170 <0 34 IRQ_TYPE_LEVEL_HIGH>; 193 <0 34 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
195 clock-names = "fck";
171 196
172 #renesas,channels = <3>; 197 #renesas,channels = <3>;
173 198
@@ -180,6 +205,8 @@
180 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>, 205 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>,
181 <0 37 IRQ_TYPE_LEVEL_HIGH>, 206 <0 37 IRQ_TYPE_LEVEL_HIGH>,
182 <0 38 IRQ_TYPE_LEVEL_HIGH>; 207 <0 38 IRQ_TYPE_LEVEL_HIGH>;
208 clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
209 clock-names = "fck";
183 210
184 #renesas,channels = <3>; 211 #renesas,channels = <3>;
185 212
@@ -192,16 +219,75 @@
192 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>, 219 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>,
193 <0 41 IRQ_TYPE_LEVEL_HIGH>, 220 <0 41 IRQ_TYPE_LEVEL_HIGH>,
194 <0 42 IRQ_TYPE_LEVEL_HIGH>; 221 <0 42 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
223 clock-names = "fck";
195 224
196 #renesas,channels = <3>; 225 #renesas,channels = <3>;
197 226
198 status = "disabled"; 227 status = "disabled";
199 }; 228 };
200 229
230 rcar_sound: sound@ffd90000 {
231 #sound-dai-cells = <1>;
232 compatible = "renesas,rcar_sound-r8a7778", "renesas,rcar_sound-gen1";
233 reg = <0xffd90000 0x1000>, /* SRU */
234 <0xffd91000 0x1240>, /* SSI */
235 <0xfffe0000 0x24>; /* ADG */
236 clocks = <&mstp3_clks R8A7778_CLK_SSI8>,
237 <&mstp3_clks R8A7778_CLK_SSI7>,
238 <&mstp3_clks R8A7778_CLK_SSI6>,
239 <&mstp3_clks R8A7778_CLK_SSI5>,
240 <&mstp3_clks R8A7778_CLK_SSI4>,
241 <&mstp0_clks R8A7778_CLK_SSI3>,
242 <&mstp0_clks R8A7778_CLK_SSI2>,
243 <&mstp0_clks R8A7778_CLK_SSI1>,
244 <&mstp0_clks R8A7778_CLK_SSI0>,
245 <&mstp5_clks R8A7778_CLK_SRU_SRC8>,
246 <&mstp5_clks R8A7778_CLK_SRU_SRC7>,
247 <&mstp5_clks R8A7778_CLK_SRU_SRC6>,
248 <&mstp5_clks R8A7778_CLK_SRU_SRC5>,
249 <&mstp5_clks R8A7778_CLK_SRU_SRC4>,
250 <&mstp5_clks R8A7778_CLK_SRU_SRC3>,
251 <&mstp5_clks R8A7778_CLK_SRU_SRC2>,
252 <&mstp5_clks R8A7778_CLK_SRU_SRC1>,
253 <&mstp5_clks R8A7778_CLK_SRU_SRC0>,
254 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
255 <&cpg_clocks R8A7778_CLK_S1>;
256 clock-names = "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4",
257 "ssi.3", "ssi.2", "ssi.1", "ssi.0",
258 "src.8", "src.7", "src.6", "src.5", "src.4",
259 "src.3", "src.2", "src.1", "src.0",
260 "clk_a", "clk_b", "clk_c", "clk_i";
261
262 status = "disabled";
263
264 rcar_sound,src {
265 src3: src@3 { };
266 src4: src@4 { };
267 src5: src@5 { };
268 src6: src@6 { };
269 src7: src@7 { };
270 src8: src@8 { };
271 src9: src@9 { };
272 };
273
274 rcar_sound,ssi {
275 ssi3: ssi@3 { interrupts = <0 0x85 IRQ_TYPE_LEVEL_HIGH>; };
276 ssi4: ssi@4 { interrupts = <0 0x85 IRQ_TYPE_LEVEL_HIGH>; };
277 ssi5: ssi@5 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
278 ssi6: ssi@6 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
279 ssi7: ssi@7 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
280 ssi8: ssi@8 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
281 ssi9: ssi@9 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
282 };
283 };
284
201 scif0: serial@ffe40000 { 285 scif0: serial@ffe40000 {
202 compatible = "renesas,scif-r8a7778", "renesas,scif"; 286 compatible = "renesas,scif-r8a7778", "renesas,scif";
203 reg = <0xffe40000 0x100>; 287 reg = <0xffe40000 0x100>;
204 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>; 288 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&mstp0_clks R8A7778_CLK_SCIF0>;
290 clock-names = "sci_ick";
205 status = "disabled"; 291 status = "disabled";
206 }; 292 };
207 293
@@ -209,6 +295,8 @@
209 compatible = "renesas,scif-r8a7778", "renesas,scif"; 295 compatible = "renesas,scif-r8a7778", "renesas,scif";
210 reg = <0xffe41000 0x100>; 296 reg = <0xffe41000 0x100>;
211 interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>; 297 interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>;
298 clocks = <&mstp0_clks R8A7778_CLK_SCIF1>;
299 clock-names = "sci_ick";
212 status = "disabled"; 300 status = "disabled";
213 }; 301 };
214 302
@@ -216,6 +304,8 @@
216 compatible = "renesas,scif-r8a7778", "renesas,scif"; 304 compatible = "renesas,scif-r8a7778", "renesas,scif";
217 reg = <0xffe42000 0x100>; 305 reg = <0xffe42000 0x100>;
218 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; 306 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
307 clocks = <&mstp0_clks R8A7778_CLK_SCIF2>;
308 clock-names = "sci_ick";
219 status = "disabled"; 309 status = "disabled";
220 }; 310 };
221 311
@@ -223,6 +313,8 @@
223 compatible = "renesas,scif-r8a7778", "renesas,scif"; 313 compatible = "renesas,scif-r8a7778", "renesas,scif";
224 reg = <0xffe43000 0x100>; 314 reg = <0xffe43000 0x100>;
225 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; 315 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&mstp0_clks R8A7778_CLK_SCIF3>;
317 clock-names = "sci_ick";
226 status = "disabled"; 318 status = "disabled";
227 }; 319 };
228 320
@@ -230,6 +322,8 @@
230 compatible = "renesas,scif-r8a7778", "renesas,scif"; 322 compatible = "renesas,scif-r8a7778", "renesas,scif";
231 reg = <0xffe44000 0x100>; 323 reg = <0xffe44000 0x100>;
232 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; 324 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&mstp0_clks R8A7778_CLK_SCIF4>;
326 clock-names = "sci_ick";
233 status = "disabled"; 327 status = "disabled";
234 }; 328 };
235 329
@@ -237,6 +331,8 @@
237 compatible = "renesas,scif-r8a7778", "renesas,scif"; 331 compatible = "renesas,scif-r8a7778", "renesas,scif";
238 reg = <0xffe45000 0x100>; 332 reg = <0xffe45000 0x100>;
239 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; 333 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&mstp0_clks R8A7778_CLK_SCIF5>;
335 clock-names = "sci_ick";
240 status = "disabled"; 336 status = "disabled";
241 }; 337 };
242 338
@@ -244,6 +340,7 @@
244 compatible = "renesas,sh-mmcif"; 340 compatible = "renesas,sh-mmcif";
245 reg = <0xffe4e000 0x100>; 341 reg = <0xffe4e000 0x100>;
246 interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>; 342 interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
343 clocks = <&mstp3_clks R8A7778_CLK_MMC>;
247 status = "disabled"; 344 status = "disabled";
248 }; 345 };
249 346
@@ -251,6 +348,7 @@
251 compatible = "renesas,sdhi-r8a7778"; 348 compatible = "renesas,sdhi-r8a7778";
252 reg = <0xffe4c000 0x100>; 349 reg = <0xffe4c000 0x100>;
253 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>; 350 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
351 clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
254 status = "disabled"; 352 status = "disabled";
255 }; 353 };
256 354
@@ -258,6 +356,7 @@
258 compatible = "renesas,sdhi-r8a7778"; 356 compatible = "renesas,sdhi-r8a7778";
259 reg = <0xffe4d000 0x100>; 357 reg = <0xffe4d000 0x100>;
260 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; 358 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&mstp3_clks R8A7778_CLK_SDHI1>;
261 status = "disabled"; 360 status = "disabled";
262 }; 361 };
263 362
@@ -265,6 +364,7 @@
265 compatible = "renesas,sdhi-r8a7778"; 364 compatible = "renesas,sdhi-r8a7778";
266 reg = <0xffe4f000 0x100>; 365 reg = <0xffe4f000 0x100>;
267 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; 366 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&mstp3_clks R8A7778_CLK_SDHI2>;
268 status = "disabled"; 368 status = "disabled";
269 }; 369 };
270 370
@@ -272,6 +372,7 @@
272 compatible = "renesas,hspi-r8a7778", "renesas,hspi"; 372 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
273 reg = <0xfffc7000 0x18>; 373 reg = <0xfffc7000 0x18>;
274 interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>; 374 interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
375 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
275 #address-cells = <1>; 376 #address-cells = <1>;
276 #size-cells = <0>; 377 #size-cells = <0>;
277 status = "disabled"; 378 status = "disabled";
@@ -281,6 +382,7 @@
281 compatible = "renesas,hspi-r8a7778", "renesas,hspi"; 382 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
282 reg = <0xfffc8000 0x18>; 383 reg = <0xfffc8000 0x18>;
283 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; 384 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
385 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
284 #address-cells = <1>; 386 #address-cells = <1>;
285 #size-cells = <0>; 387 #size-cells = <0>;
286 status = "disabled"; 388 status = "disabled";
@@ -290,8 +392,199 @@
290 compatible = "renesas,hspi-r8a7778", "renesas,hspi"; 392 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
291 reg = <0xfffc6000 0x18>; 393 reg = <0xfffc6000 0x18>;
292 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; 394 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
395 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
293 #address-cells = <1>; 396 #address-cells = <1>;
294 #size-cells = <0>; 397 #size-cells = <0>;
295 status = "disabled"; 398 status = "disabled";
296 }; 399 };
400
401 clocks {
402 #address-cells = <1>;
403 #size-cells = <1>;
404 ranges;
405
406 /* External input clock */
407 extal_clk: extal_clk {
408 compatible = "fixed-clock";
409 #clock-cells = <0>;
410 clock-frequency = <0>;
411 clock-output-names = "extal";
412 };
413
414 /* Special CPG clocks */
415 cpg_clocks: cpg_clocks@ffc80000 {
416 compatible = "renesas,r8a7778-cpg-clocks";
417 reg = <0xffc80000 0x80>;
418 #clock-cells = <1>;
419 clocks = <&extal_clk>;
420 clock-output-names = "plla", "pllb", "b",
421 "out", "p", "s", "s1";
422 };
423
424 /* Audio clocks; frequencies are set by boards if applicable. */
425 audio_clk_a: audio_clk_a {
426 compatible = "fixed-clock";
427 #clock-cells = <0>;
428 clock-output-names = "audio_clk_a";
429 };
430 audio_clk_b: audio_clk_b {
431 compatible = "fixed-clock";
432 #clock-cells = <0>;
433 clock-output-names = "audio_clk_b";
434 };
435 audio_clk_c: audio_clk_c {
436 compatible = "fixed-clock";
437 #clock-cells = <0>;
438 clock-output-names = "audio_clk_c";
439 };
440
441 /* Fixed ratio clocks */
442 g_clk: g_clk {
443 compatible = "fixed-factor-clock";
444 clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
445 #clock-cells = <0>;
446 clock-div = <12>;
447 clock-mult = <1>;
448 clock-output-names = "g";
449 };
450 i_clk: i_clk {
451 compatible = "fixed-factor-clock";
452 clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
453 #clock-cells = <0>;
454 clock-div = <1>;
455 clock-mult = <1>;
456 clock-output-names = "i";
457 };
458 s3_clk: s3_clk {
459 compatible = "fixed-factor-clock";
460 clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
461 #clock-cells = <0>;
462 clock-div = <4>;
463 clock-mult = <1>;
464 clock-output-names = "s3";
465 };
466 s4_clk: s4_clk {
467 compatible = "fixed-factor-clock";
468 clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
469 #clock-cells = <0>;
470 clock-div = <8>;
471 clock-mult = <1>;
472 clock-output-names = "s4";
473 };
474 z_clk: z_clk {
475 compatible = "fixed-factor-clock";
476 clocks = <&cpg_clocks R8A7778_CLK_PLLB>;
477 #clock-cells = <0>;
478 clock-div = <1>;
479 clock-mult = <1>;
480 clock-output-names = "z";
481 };
482
483 /* Gate clocks */
484 mstp0_clks: mstp0_clks@ffc80030 {
485 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
486 reg = <0xffc80030 4>;
487 clocks = <&cpg_clocks R8A7778_CLK_P>,
488 <&cpg_clocks R8A7778_CLK_P>,
489 <&cpg_clocks R8A7778_CLK_P>,
490 <&cpg_clocks R8A7778_CLK_P>,
491 <&cpg_clocks R8A7778_CLK_P>,
492 <&cpg_clocks R8A7778_CLK_P>,
493 <&cpg_clocks R8A7778_CLK_P>,
494 <&cpg_clocks R8A7778_CLK_P>,
495 <&cpg_clocks R8A7778_CLK_P>,
496 <&cpg_clocks R8A7778_CLK_P>,
497 <&cpg_clocks R8A7778_CLK_P>,
498 <&cpg_clocks R8A7778_CLK_P>,
499 <&cpg_clocks R8A7778_CLK_P>,
500 <&cpg_clocks R8A7778_CLK_P>,
501 <&cpg_clocks R8A7778_CLK_P>,
502 <&cpg_clocks R8A7778_CLK_P>,
503 <&cpg_clocks R8A7778_CLK_P>,
504 <&cpg_clocks R8A7778_CLK_P>,
505 <&cpg_clocks R8A7778_CLK_S>;
506 #clock-cells = <1>;
507 clock-indices = <
508 R8A7778_CLK_I2C0 R8A7778_CLK_I2C1
509 R8A7778_CLK_I2C2 R8A7778_CLK_I2C3
510 R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1
511 R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3
512 R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5
513 R8A7778_CLK_TMU0 R8A7778_CLK_TMU1
514 R8A7778_CLK_TMU2 R8A7778_CLK_SSI0
515 R8A7778_CLK_SSI1 R8A7778_CLK_SSI2
516 R8A7778_CLK_SSI3 R8A7778_CLK_SRU
517 R8A7778_CLK_HSPI
518 >;
519 clock-output-names =
520 "i2c0", "i2c1", "i2c2", "i2c3", "scif0",
521 "scif1", "scif2", "scif3", "scif4", "scif5",
522 "tmu0", "tmu1", "tmu2", "ssi0", "ssi1",
523 "ssi2", "ssi3", "sru", "hspi";
524 };
525 mstp1_clks: mstp1_clks@ffc80034 {
526 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
527 reg = <0xffc80034 4>, <0xffc80044 4>;
528 clocks = <&cpg_clocks R8A7778_CLK_P>,
529 <&cpg_clocks R8A7778_CLK_S>,
530 <&cpg_clocks R8A7778_CLK_S>,
531 <&cpg_clocks R8A7778_CLK_P>;
532 #clock-cells = <1>;
533 clock-indices = <
534 R8A7778_CLK_ETHER R8A7778_CLK_VIN0
535 R8A7778_CLK_VIN1 R8A7778_CLK_USB
536 >;
537 clock-output-names =
538 "ether", "vin0", "vin1", "usb";
539 };
540 mstp3_clks: mstp3_clks@ffc8003c {
541 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
542 reg = <0xffc8003c 4>;
543 clocks = <&s4_clk>,
544 <&cpg_clocks R8A7778_CLK_P>,
545 <&cpg_clocks R8A7778_CLK_P>,
546 <&cpg_clocks R8A7778_CLK_P>,
547 <&cpg_clocks R8A7778_CLK_P>,
548 <&cpg_clocks R8A7778_CLK_P>,
549 <&cpg_clocks R8A7778_CLK_P>,
550 <&cpg_clocks R8A7778_CLK_P>,
551 <&cpg_clocks R8A7778_CLK_P>;
552 #clock-cells = <1>;
553 clock-indices = <
554 R8A7778_CLK_MMC R8A7778_CLK_SDHI0
555 R8A7778_CLK_SDHI1 R8A7778_CLK_SDHI2
556 R8A7778_CLK_SSI4 R8A7778_CLK_SSI5
557 R8A7778_CLK_SSI6 R8A7778_CLK_SSI7
558 R8A7778_CLK_SSI8
559 >;
560 clock-output-names =
561 "mmc", "sdhi0", "sdhi1", "sdhi2", "ssi4",
562 "ssi5", "ssi6", "ssi7", "ssi8";
563 };
564 mstp5_clks: mstp5_clks@ffc80054 {
565 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
566 reg = <0xffc80054 4>;
567 clocks = <&cpg_clocks R8A7778_CLK_P>,
568 <&cpg_clocks R8A7778_CLK_P>,
569 <&cpg_clocks R8A7778_CLK_P>,
570 <&cpg_clocks R8A7778_CLK_P>,
571 <&cpg_clocks R8A7778_CLK_P>,
572 <&cpg_clocks R8A7778_CLK_P>,
573 <&cpg_clocks R8A7778_CLK_P>,
574 <&cpg_clocks R8A7778_CLK_P>,
575 <&cpg_clocks R8A7778_CLK_P>;
576 #clock-cells = <1>;
577 clock-indices = <
578 R8A7778_CLK_SRU_SRC0 R8A7778_CLK_SRU_SRC1
579 R8A7778_CLK_SRU_SRC2 R8A7778_CLK_SRU_SRC3
580 R8A7778_CLK_SRU_SRC4 R8A7778_CLK_SRU_SRC5
581 R8A7778_CLK_SRU_SRC6 R8A7778_CLK_SRU_SRC7
582 R8A7778_CLK_SRU_SRC8
583 >;
584 clock-output-names =
585 "sru-src0", "sru-src1", "sru-src2",
586 "sru-src3", "sru-src4", "sru-src5",
587 "sru-src6", "sru-src7", "sru-src8";
588 };
589 };
297}; 590};
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-31 19:27:45 -0400