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authorLinus Torvalds <torvalds@linux-foundation.org>2015-02-17 12:36:52 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2015-02-17 12:36:52 -0500
commita233bb742aed62fc6164073d9835135f639b8828 (patch)
tree4cec22b707a29a52f9946da6393c9580221d0a6e /arch/arm/boot/dts
parent878ba61aa98cbb97a513757800e77613f856a029 (diff)
parent880c0d140deb12d5be39a96375fcc42ad357f17d (diff)
Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC DT updates from Olof Johansson: "DT changes continue to be the bulk of our merge window contents. We continue to have a large set of changes across the board as new platforms and drivers are added. Some of the new platforms are: - Alphascale ASM9260 - Marvell Armada 388 - CSR Atlas7 - TI Davinci DM816x - Hisilicon HiP01 - ST STiH418 There have also been some sweeping changes, including relicensing of DTS contents from GPL to GPLv2+/X11 so that the same files can be reused in other non-GPL projects more easily. There's also been changes to the DT Makefile to make it a little less conflict-ridden and churny down the road" * tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (330 commits) ARM: dts: Add PPMU node for exynos4412-trats2 ARM: dts: Add PPMU node for exynos3250-monk and exynos3250-rinato ARM: dts: Add PPMU dt node for exynos4 and exynos4210 ARM: dts: Add PPMU dt node for exynos3250 ARM: dts: add mipi dsi device node for exynos4415 ARM: dts: add fimd device node for exynos4415 ARM: dts: Add syscon phandle to the video-phy node for Exynos4 ARM: dts: Add sound nodes for exynos4412-trats2 ARM: dts: Fix CLK_MOUT_CAMn parent clocks assignment for exynos4412-trats2 ARM: dts: Fix CLK_UART_ISP_SCLK clock assignment in exynos4x12.dtsi ARM: dts: Add max77693 charger node for exynos4412-trats2 ARM: dts: Switch max77686 regulators to GPIO control for exynos4412-trats2 ARM: dts: Add suspend configuration for max77686 regulators for exynos4412-trats2 ARM: dts: Add Maxim 77693 fuel gauge node for exynos4412-trats2 ARM: dts: am57xx-beagle-x15: Fix USB2 mode ARM: dts: am57xx-beagle-x15: Add extcon nodes for USB ARM: dts: dra72-evm: Add extcon nodes for USB ARM: dts: dra7-evm: Add extcon nodes for USB ARM: dts: rockchip: move the hdmi ddc-i2c-bus property to the actual boards ARM: dts: rockchip: enable vops and hdmi output on rk3288-firefly and -evb ...
Diffstat (limited to 'arch/arm/boot/dts')
-rw-r--r--arch/arm/boot/dts/Makefile356
-rw-r--r--arch/arm/boot/dts/alphascale-asm9260-devkit.dts13
-rw-r--r--arch/arm/boot/dts/alphascale-asm9260.dtsi63
-rw-r--r--arch/arm/boot/dts/am4372.dtsi16
-rw-r--r--arch/arm/boot/dts/am437x-gp-evm.dts106
-rw-r--r--arch/arm/boot/dts/am437x-idk-evm.dts405
-rw-r--r--arch/arm/boot/dts/am437x-sk-evm.dts217
-rw-r--r--arch/arm/boot/dts/am43x-epos-evm.dts53
-rw-r--r--arch/arm/boot/dts/am57xx-beagle-x15.dts157
-rw-r--r--arch/arm/boot/dts/armada-370-db.dts40
-rw-r--r--arch/arm/boot/dts/armada-370-mirabox.dts40
-rw-r--r--arch/arm/boot/dts/armada-370-netgear-rn102.dts41
-rw-r--r--arch/arm/boot/dts/armada-370-netgear-rn104.dts41
-rw-r--r--arch/arm/boot/dts/armada-370-rd.dts40
-rw-r--r--arch/arm/boot/dts/armada-370-synology-ds213j.dts41
-rw-r--r--arch/arm/boot/dts/armada-370-xp.dtsi40
-rw-r--r--arch/arm/boot/dts/armada-370.dtsi40
-rw-r--r--arch/arm/boot/dts/armada-375-db.dts40
-rw-r--r--arch/arm/boot/dts/armada-375.dtsi42
-rw-r--r--arch/arm/boot/dts/armada-380.dtsi43
-rw-r--r--arch/arm/boot/dts/armada-385-db-ap.dts178
-rw-r--r--arch/arm/boot/dts/armada-385-rd.dts97
-rw-r--r--arch/arm/boot/dts/armada-385.dtsi43
-rw-r--r--arch/arm/boot/dts/armada-388-db.dts (renamed from arch/arm/boot/dts/armada-385-db.dts)49
-rw-r--r--arch/arm/boot/dts/armada-388-gp.dts414
-rw-r--r--arch/arm/boot/dts/armada-388-rd.dts132
-rw-r--r--arch/arm/boot/dts/armada-388.dtsi70
-rw-r--r--arch/arm/boot/dts/armada-38x.dtsi136
-rw-r--r--arch/arm/boot/dts/armada-xp-axpwifiap.dts46
-rw-r--r--arch/arm/boot/dts/armada-xp-db.dts40
-rw-r--r--arch/arm/boot/dts/armada-xp-gp.dts40
-rw-r--r--arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts41
-rw-r--r--arch/arm/boot/dts/armada-xp-matrix.dts40
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78230.dtsi40
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78260.dtsi40
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78460.dtsi40
-rw-r--r--arch/arm/boot/dts/armada-xp-netgear-rn2120.dts41
-rw-r--r--arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts40
-rw-r--r--arch/arm/boot/dts/armada-xp-synology-ds414.dts41
-rw-r--r--arch/arm/boot/dts/armada-xp.dtsi40
-rw-r--r--arch/arm/boot/dts/at91sam9263.dtsi21
-rw-r--r--arch/arm/boot/dts/at91sam9n12ek.dts2
-rw-r--r--arch/arm/boot/dts/at91sam9x5ek.dtsi9
-rw-r--r--arch/arm/boot/dts/atlas7-evb.dts110
-rw-r--r--arch/arm/boot/dts/atlas7.dtsi813
-rw-r--r--arch/arm/boot/dts/axp209.dtsi97
-rw-r--r--arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts68
-rw-r--r--arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts60
-rw-r--r--arch/arm/boot/dts/bcm4708-netgear-r6250.dts1
-rw-r--r--arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts1
-rw-r--r--arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts1
-rw-r--r--arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts68
-rw-r--r--arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts37
-rw-r--r--arch/arm/boot/dts/berlin2.dtsi2
-rw-r--r--arch/arm/boot/dts/berlin2cd.dtsi7
-rw-r--r--arch/arm/boot/dts/berlin2q.dtsi10
-rw-r--r--arch/arm/boot/dts/cx92755.dtsi113
-rw-r--r--arch/arm/boot/dts/cx92755_equinox.dts74
-rw-r--r--arch/arm/boot/dts/dm8168-evm.dts129
-rw-r--r--arch/arm/boot/dts/dm816x-clocks.dtsi250
-rw-r--r--arch/arm/boot/dts/dm816x.dtsi392
-rw-r--r--arch/arm/boot/dts/dra7-evm.dts31
-rw-r--r--arch/arm/boot/dts/dra7.dtsi2
-rw-r--r--arch/arm/boot/dts/dra72-evm.dts108
-rw-r--r--arch/arm/boot/dts/exynos3250-monk.dts63
-rw-r--r--arch/arm/boot/dts/exynos3250-rinato.dts133
-rw-r--r--arch/arm/boot/dts/exynos3250.dtsi106
-rw-r--r--arch/arm/boot/dts/exynos4.dtsi134
-rw-r--r--arch/arm/boot/dts/exynos4210-trats.dts1
-rw-r--r--arch/arm/boot/dts/exynos4210-universal_c210.dts1
-rw-r--r--arch/arm/boot/dts/exynos4210.dtsi9
-rw-r--r--arch/arm/boot/dts/exynos4412-odroid-common.dtsi1
-rw-r--r--arch/arm/boot/dts/exynos4412-trats2.dts212
-rw-r--r--arch/arm/boot/dts/exynos4415.dtsi34
-rw-r--r--arch/arm/boot/dts/exynos4x12.dtsi9
-rw-r--r--arch/arm/boot/dts/exynos5250-snow.dts16
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi12
-rw-r--r--arch/arm/boot/dts/exynos5420-peach-pit.dts100
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi27
-rw-r--r--arch/arm/boot/dts/exynos5422-odroidxu3.dts371
-rw-r--r--arch/arm/boot/dts/exynos5800-peach-pi.dts101
-rw-r--r--arch/arm/boot/dts/hip01-ca9x2.dts51
-rw-r--r--arch/arm/boot/dts/hip01.dtsi110
-rw-r--r--arch/arm/boot/dts/imx27-apf27dev.dts21
-rw-r--r--arch/arm/boot/dts/imx27.dtsi2
-rw-r--r--arch/arm/boot/dts/imx28-evk.dts1
-rw-r--r--arch/arm/boot/dts/imx51-apf51dev.dts14
-rw-r--r--arch/arm/boot/dts/imx53.dtsi11
-rw-r--r--arch/arm/boot/dts/imx6dl-udoo.dts18
-rw-r--r--arch/arm/boot/dts/imx6dl.dtsi2
-rw-r--r--arch/arm/boot/dts/imx6q-udoo.dts124
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi4
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabrelite.dtsi33
-rw-r--r--arch/arm/boot/dts/imx6qdl-udoo.dtsi134
-rw-r--r--arch/arm/boot/dts/imx6qdl.dtsi5
-rw-r--r--arch/arm/boot/dts/imx6sx-sabreauto.dts146
-rw-r--r--arch/arm/boot/dts/imx6sx-sdb.dts39
-rw-r--r--arch/arm/boot/dts/kirkwood-6192.dtsi2
-rw-r--r--arch/arm/boot/dts/kirkwood-blackarmor-nas220.dts173
-rw-r--r--arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts8
-rw-r--r--arch/arm/boot/dts/kirkwood-pogo_e02.dts134
-rw-r--r--arch/arm/boot/dts/marco-evb.dts54
-rw-r--r--arch/arm/boot/dts/marco.dtsi757
-rw-r--r--arch/arm/boot/dts/mt6589-aquaris5.dts12
-rw-r--r--arch/arm/boot/dts/mt6589.dtsi52
-rw-r--r--arch/arm/boot/dts/mt6592.dtsi51
-rw-r--r--arch/arm/boot/dts/mt8127-moose.dts4
-rw-r--r--arch/arm/boot/dts/mt8127.dtsi52
-rw-r--r--arch/arm/boot/dts/mt8135-evbp1.dts4
-rw-r--r--arch/arm/boot/dts/mt8135.dtsi54
-rw-r--r--arch/arm/boot/dts/omap3-cm-t3x.dtsi58
-rw-r--r--arch/arm/boot/dts/omap3-cm-t3x30.dtsi3
-rw-r--r--arch/arm/boot/dts/omap3-gta04.dtsi99
-rw-r--r--arch/arm/boot/dts/omap3-n900.dts3
-rw-r--r--arch/arm/boot/dts/omap3-n950-n9.dtsi5
-rw-r--r--arch/arm/boot/dts/omap3-sbc-t3517.dts4
-rw-r--r--arch/arm/boot/dts/omap3-sbc-t3530.dts10
-rw-r--r--arch/arm/boot/dts/omap3-sbc-t3730.dts5
-rw-r--r--arch/arm/boot/dts/qcom-apq8064-ifc6410.dts12
-rw-r--r--arch/arm/boot/dts/qcom-ipq8064.dtsi2
-rw-r--r--arch/arm/boot/dts/r7s72100-genmai.dts2
-rw-r--r--arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts2
-rw-r--r--arch/arm/boot/dts/r8a73a4-ape6evm.dts173
-rw-r--r--arch/arm/boot/dts/r8a73a4.dtsi10
-rw-r--r--arch/arm/boot/dts/r8a7740-armadillo800eva.dts4
-rw-r--r--arch/arm/boot/dts/r8a7740.dtsi115
-rw-r--r--arch/arm/boot/dts/r8a7779.dtsi39
-rw-r--r--arch/arm/boot/dts/r8a7790-lager.dts15
-rw-r--r--arch/arm/boot/dts/r8a7790.dtsi62
-rw-r--r--arch/arm/boot/dts/r8a7791-henninger.dts4
-rw-r--r--arch/arm/boot/dts/r8a7791-koelsch.dts19
-rw-r--r--arch/arm/boot/dts/r8a7791.dtsi69
-rw-r--r--arch/arm/boot/dts/r8a7794-alt.dts4
-rw-r--r--arch/arm/boot/dts/r8a7794.dtsi82
-rw-r--r--arch/arm/boot/dts/rk3066a-rayeager.dts468
-rw-r--r--arch/arm/boot/dts/rk3288-evb-act8846.dts27
-rw-r--r--arch/arm/boot/dts/rk3288-evb-rk808.dts54
-rw-r--r--arch/arm/boot/dts/rk3288-evb.dtsi25
-rw-r--r--arch/arm/boot/dts/rk3288-firefly-beta.dts71
-rw-r--r--arch/arm/boot/dts/rk3288-firefly.dts71
-rw-r--r--arch/arm/boot/dts/rk3288-firefly.dtsi490
-rw-r--r--arch/arm/boot/dts/rk3288.dtsi111
-rw-r--r--arch/arm/boot/dts/s5pv210-aquila.dts1
-rw-r--r--arch/arm/boot/dts/s5pv210-goni.dts1
-rw-r--r--arch/arm/boot/dts/s5pv210-smdkv210.dts1
-rw-r--r--arch/arm/boot/dts/sama5d3xmb.dtsi2
-rw-r--r--arch/arm/boot/dts/sama5d4.dtsi15
-rw-r--r--arch/arm/boot/dts/sh73a0-kzm9g-reference.dts2
-rw-r--r--arch/arm/boot/dts/sh73a0.dtsi18
-rw-r--r--arch/arm/boot/dts/stih407-b2120.dts3
-rw-r--r--arch/arm/boot/dts/stih407-family.dtsi53
-rw-r--r--arch/arm/boot/dts/stih407.dtsi151
-rw-r--r--arch/arm/boot/dts/stih410.dtsi138
-rw-r--r--arch/arm/boot/dts/stih418-b2199.dts78
-rw-r--r--arch/arm/boot/dts/stih418-clock.dtsi348
-rw-r--r--arch/arm/boot/dts/stih418.dtsi99
-rw-r--r--arch/arm/boot/dts/stihxxx-b2120.dtsi13
-rw-r--r--arch/arm/boot/dts/sun4i-a10-a1000.dts23
-rw-r--r--arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts10
-rw-r--r--arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts100
-rw-r--r--arch/arm/boot/dts/sun4i-a10-cubieboard.dts58
-rw-r--r--arch/arm/boot/dts/sun4i-a10-hackberry.dts21
-rw-r--r--arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts105
-rw-r--r--arch/arm/boot/dts/sun4i-a10-inet97fv2.dts8
-rw-r--r--arch/arm/boot/dts/sun4i-a10-marsboard.dts183
-rw-r--r--arch/arm/boot/dts/sun4i-a10-mini-xplus.dts11
-rw-r--r--arch/arm/boot/dts/sun4i-a10-mk802.dts109
-rw-r--r--arch/arm/boot/dts/sun4i-a10-mk802ii.dts113
-rw-r--r--arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts21
-rw-r--r--arch/arm/boot/dts/sun4i-a10-pcduino.dts68
-rw-r--r--arch/arm/boot/dts/sun4i-a10.dtsi204
-rw-r--r--arch/arm/boot/dts/sun5i-a10s-mk802.dts125
-rw-r--r--arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts72
-rw-r--r--arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts25
-rw-r--r--arch/arm/boot/dts/sun5i-a10s.dtsi68
-rw-r--r--arch/arm/boot/dts/sun5i-a13-hsg-h702.dts59
-rw-r--r--arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts25
-rw-r--r--arch/arm/boot/dts/sun5i-a13-olinuxino.dts75
-rw-r--r--arch/arm/boot/dts/sun5i-a13.dtsi112
-rw-r--r--arch/arm/boot/dts/sun6i-a31-app4-evb1.dts13
-rw-r--r--arch/arm/boot/dts/sun6i-a31-colombus.dts21
-rw-r--r--arch/arm/boot/dts/sun6i-a31-hummingbird.dts185
-rw-r--r--arch/arm/boot/dts/sun6i-a31-m9.dts31
-rw-r--r--arch/arm/boot/dts/sun6i-a31.dtsi182
-rw-r--r--arch/arm/boot/dts/sun6i-a31s-cs908.dts104
-rw-r--r--arch/arm/boot/dts/sun6i-a31s.dtsi58
-rw-r--r--arch/arm/boot/dts/sun7i-a20-bananapi.dts28
-rw-r--r--arch/arm/boot/dts/sun7i-a20-bananapro.dts262
-rw-r--r--arch/arm/boot/dts/sun7i-a20-cubieboard2.dts101
-rw-r--r--arch/arm/boot/dts/sun7i-a20-cubietruck.dts125
-rw-r--r--arch/arm/boot/dts/sun7i-a20-hummingbird.dts38
-rw-r--r--arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts40
-rw-r--r--arch/arm/boot/dts/sun7i-a20-m3.dts18
-rw-r--r--arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts24
-rw-r--r--arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts24
-rw-r--r--arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts79
-rw-r--r--arch/arm/boot/dts/sun7i-a20-pcduino3.dts21
-rw-r--r--arch/arm/boot/dts/sun7i-a20.dtsi347
-rw-r--r--arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts59
-rw-r--r--arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts33
-rw-r--r--arch/arm/boot/dts/sun8i-a23.dtsi100
-rw-r--r--arch/arm/boot/dts/sun9i-a80-optimus.dts112
-rw-r--r--arch/arm/boot/dts/sun9i-a80.dtsi192
-rw-r--r--arch/arm/boot/dts/sunxi-common-regulators.dtsi65
-rw-r--r--arch/arm/boot/dts/tegra124-nyan-big.dts2
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi10
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu.dtsi2
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi2
-rw-r--r--arch/arm/boot/dts/vf-colibri-eval-v3.dtsi2
-rw-r--r--arch/arm/boot/dts/vf-colibri.dtsi3
-rw-r--r--arch/arm/boot/dts/vf500.dtsi23
-rw-r--r--arch/arm/boot/dts/vf610-twr.dts2
-rw-r--r--arch/arm/boot/dts/vfxxx.dtsi48
-rw-r--r--arch/arm/boot/dts/zynq-7000.dtsi32
-rw-r--r--arch/arm/boot/dts/zynq-zc702.dts224
-rw-r--r--arch/arm/boot/dts/zynq-zc706.dts194
-rw-r--r--arch/arm/boot/dts/zynq-zed.dts15
217 files changed, 14304 insertions, 2403 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 19cb6fcecf89..a1c776b8dcec 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1,83 +1,91 @@
1ifeq ($(CONFIG_OF),y) 1ifeq ($(CONFIG_OF),y)
2 2
3dtb-$(CONFIG_MACH_ASM9260) += \
4 alphascale-asm9260-devkit.dtb
3# Keep at91 dtb files sorted alphabetically for each SoC 5# Keep at91 dtb files sorted alphabetically for each SoC
4# rm9200 6dtb-$(CONFIG_SOC_SAM_V4_V5) += \
5dtb-$(CONFIG_ARCH_AT91) += at91rm9200ek.dtb 7 at91rm9200ek.dtb \
6dtb-$(CONFIG_ARCH_AT91) += mpa1600.dtb 8 mpa1600.dtb \
7# sam9260 9 animeo_ip.dtb \
8dtb-$(CONFIG_ARCH_AT91) += animeo_ip.dtb 10 at91-qil_a9260.dtb \
9dtb-$(CONFIG_ARCH_AT91) += at91-qil_a9260.dtb 11 aks-cdu.dtb \
10dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb 12 ethernut5.dtb \
11dtb-$(CONFIG_ARCH_AT91) += ethernut5.dtb 13 evk-pro3.dtb \
12dtb-$(CONFIG_ARCH_AT91) += evk-pro3.dtb 14 tny_a9260.dtb \
13dtb-$(CONFIG_ARCH_AT91) += tny_a9260.dtb 15 usb_a9260.dtb \
14dtb-$(CONFIG_ARCH_AT91) += usb_a9260.dtb 16 at91sam9261ek.dtb \
15# sam9261 17 at91sam9263ek.dtb \
16dtb-$(CONFIG_ARCH_AT91) += at91sam9261ek.dtb 18 tny_a9263.dtb \
17# sam9263 19 usb_a9263.dtb \
18dtb-$(CONFIG_ARCH_AT91) += at91sam9263ek.dtb 20 at91-foxg20.dtb \
19dtb-$(CONFIG_ARCH_AT91) += tny_a9263.dtb 21 at91sam9g20ek.dtb \
20dtb-$(CONFIG_ARCH_AT91) += usb_a9263.dtb 22 at91sam9g20ek_2mmc.dtb \
21# sam9g20 23 kizbox.dtb \
22dtb-$(CONFIG_ARCH_AT91) += at91-foxg20.dtb 24 tny_a9g20.dtb \
23dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek.dtb 25 usb_a9g20.dtb \
24dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek_2mmc.dtb 26 usb_a9g20_lpw.dtb \
25dtb-$(CONFIG_ARCH_AT91) += kizbox.dtb 27 at91sam9m10g45ek.dtb \
26dtb-$(CONFIG_ARCH_AT91) += tny_a9g20.dtb 28 pm9g45.dtb \
27dtb-$(CONFIG_ARCH_AT91) += usb_a9g20.dtb 29 at91sam9n12ek.dtb \
28dtb-$(CONFIG_ARCH_AT91) += usb_a9g20_lpw.dtb 30 at91sam9rlek.dtb \
29# sam9g45 31 at91-ariag25.dtb \
30dtb-$(CONFIG_ARCH_AT91) += at91sam9m10g45ek.dtb 32 at91-cosino_mega2560.dtb \
31dtb-$(CONFIG_ARCH_AT91) += pm9g45.dtb 33 at91sam9g15ek.dtb \
32# sam9n12 34 at91sam9g25ek.dtb \
33dtb-$(CONFIG_ARCH_AT91) += at91sam9n12ek.dtb 35 at91sam9g35ek.dtb \
34# sam9rl 36 at91sam9x25ek.dtb \
35dtb-$(CONFIG_ARCH_AT91) += at91sam9rlek.dtb 37 at91sam9x35ek.dtb
36# sam9x5 38dtb-$(CONFIG_SOC_SAM_V7) += \
37dtb-$(CONFIG_ARCH_AT91) += at91-ariag25.dtb 39 at91-sama5d3_xplained.dtb \
38dtb-$(CONFIG_ARCH_AT91) += at91-cosino_mega2560.dtb 40 sama5d31ek.dtb \
39dtb-$(CONFIG_ARCH_AT91) += at91sam9g15ek.dtb 41 sama5d33ek.dtb \
40dtb-$(CONFIG_ARCH_AT91) += at91sam9g25ek.dtb 42 sama5d34ek.dtb \
41dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb 43 sama5d35ek.dtb \
42dtb-$(CONFIG_ARCH_AT91) += at91sam9x25ek.dtb 44 sama5d36ek.dtb \
43dtb-$(CONFIG_ARCH_AT91) += at91sam9x35ek.dtb 45 at91-sama5d4ek.dtb
44# sama5d3 46dtb-$(CONFIG_ARCH_ATLAS6) += \
45dtb-$(CONFIG_ARCH_AT91) += at91-sama5d3_xplained.dtb 47 atlas6-evb.dtb
46dtb-$(CONFIG_ARCH_AT91) += sama5d31ek.dtb 48dtb-$(CONFIG_ARCH_ATLAS7) += \
47dtb-$(CONFIG_ARCH_AT91) += sama5d33ek.dtb 49 atlas7-evb.dtb
48dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb 50dtb-$(CONFIG_ARCH_AXXIA) += \
49dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb 51 axm5516-amarillo.dtb
50dtb-$(CONFIG_ARCH_AT91) += sama5d36ek.dtb 52dtb-$(CONFIG_ARCH_BCM2835) += \
51# sama5d4 53 bcm2835-rpi-b.dtb \
52dtb-$(CONFIG_ARCH_AT91) += at91-sama5d4ek.dtb 54 bcm2835-rpi-b-plus.dtb
53
54dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
55dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb
56dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
57dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b-plus.dtb
58dtb-$(CONFIG_ARCH_BCM_5301X) += \ 55dtb-$(CONFIG_ARCH_BCM_5301X) += \
59 bcm4708-buffalo-wzr-1750dhp.dtb \ 56 bcm4708-buffalo-wzr-1750dhp.dtb \
57 bcm4708-luxul-xwc-1000.dtb \
60 bcm4708-netgear-r6250.dtb \ 58 bcm4708-netgear-r6250.dtb \
61 bcm4708-netgear-r6300-v2.dtb \ 59 bcm4708-netgear-r6300-v2.dtb \
62 bcm47081-asus-rt-n18u.dtb \ 60 bcm47081-asus-rt-n18u.dtb \
63 bcm47081-buffalo-wzr-600dhp2.dtb 61 bcm47081-buffalo-wzr-600dhp2.dtb \
64dtb-$(CONFIG_ARCH_BCM_63XX) += bcm963138dvt.dtb 62 bcm47081-buffalo-wzr-900dhp.dtb
65dtb-$(CONFIG_ARCH_BCM_CYGNUS) += bcm911360_entphn.dtb \ 63dtb-$(CONFIG_ARCH_BCM_63XX) += \
64 bcm963138dvt.dtb
65dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
66 bcm911360_entphn.dtb \
66 bcm911360k.dtb \ 67 bcm911360k.dtb \
67 bcm958300k.dtb 68 bcm958300k.dtb
68dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \ 69dtb-$(CONFIG_ARCH_BCM_MOBILE) += \
70 bcm28155-ap.dtb \
69 bcm21664-garnet.dtb 71 bcm21664-garnet.dtb
70dtb-$(CONFIG_ARCH_BERLIN) += \ 72dtb-$(CONFIG_ARCH_BERLIN) += \
71 berlin2-sony-nsz-gs7.dtb \ 73 berlin2-sony-nsz-gs7.dtb \
72 berlin2cd-google-chromecast.dtb \ 74 berlin2cd-google-chromecast.dtb \
73 berlin2q-marvell-dmp.dtb 75 berlin2q-marvell-dmp.dtb
74dtb-$(CONFIG_ARCH_BRCMSTB) += \ 76dtb-$(CONFIG_ARCH_BRCMSTB) += \
75 bcm7445-bcm97445svmb.dtb 77 bcm7445-bcm97445svmb.dtb
76dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \ 78dtb-$(CONFIG_ARCH_DAVINCI) += \
79 da850-enbw-cmc.dtb \
77 da850-evm.dtb 80 da850-evm.dtb
78dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb 81dtb-$(CONFIG_ARCH_DIGICOLOR) += \
79dtb-$(CONFIG_ARCH_EXYNOS) += exynos3250-monk.dtb \ 82 cx92755_equinox.dtb
80 exynos3250-rinato.dtb \ 83dtb-$(CONFIG_ARCH_EFM32) += \
84 efm32gg-dk3750.dtb
85dtb-$(CONFIG_ARCH_EXYNOS3) += \
86 exynos3250-monk.dtb \
87 exynos3250-rinato.dtb
88dtb-$(CONFIG_ARCH_EXYNOS4) += \
81 exynos4210-origen.dtb \ 89 exynos4210-origen.dtb \
82 exynos4210-smdkv310.dtb \ 90 exynos4210-smdkv310.dtb \
83 exynos4210-trats.dtb \ 91 exynos4210-trats.dtb \
@@ -88,7 +96,8 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos3250-monk.dtb \
88 exynos4412-origen.dtb \ 96 exynos4412-origen.dtb \
89 exynos4412-smdk4412.dtb \ 97 exynos4412-smdk4412.dtb \
90 exynos4412-tiny4412.dtb \ 98 exynos4412-tiny4412.dtb \
91 exynos4412-trats2.dtb \ 99 exynos4412-trats2.dtb
100dtb-$(CONFIG_ARCH_EXYNOS5) += \
92 exynos5250-arndale.dtb \ 101 exynos5250-arndale.dtb \
93 exynos5250-smdk5250.dtb \ 102 exynos5250-smdk5250.dtb \
94 exynos5250-snow.dtb \ 103 exynos5250-snow.dtb \
@@ -98,20 +107,31 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos3250-monk.dtb \
98 exynos5420-arndale-octa.dtb \ 107 exynos5420-arndale-octa.dtb \
99 exynos5420-peach-pit.dtb \ 108 exynos5420-peach-pit.dtb \
100 exynos5420-smdk5420.dtb \ 109 exynos5420-smdk5420.dtb \
110 exynos5422-odroidxu3.dtb \
101 exynos5440-sd5v1.dtb \ 111 exynos5440-sd5v1.dtb \
102 exynos5440-ssdk5440.dtb \ 112 exynos5440-ssdk5440.dtb \
103 exynos5800-peach-pi.dtb 113 exynos5800-peach-pi.dtb
104dtb-$(CONFIG_ARCH_HI3xxx) += hi3620-hi4511.dtb 114dtb-$(CONFIG_ARCH_HI3xxx) += \
105dtb-$(CONFIG_ARCH_HIX5HD2) += hisi-x5hd2-dkb.dtb 115 hi3620-hi4511.dtb
106dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \ 116dtb-$(CONFIG_ARCH_HIX5HD2) += \
117 hisi-x5hd2-dkb.dtb
118dtb-$(CONFIG_ARCH_HIGHBANK) += \
119 highbank.dtb \
107 ecx-2000.dtb 120 ecx-2000.dtb
108dtb-$(CONFIG_ARCH_HIP04) += hip04-d01.dtb 121dtb-$(CONFIG_ARCH_HIP01) += \
109dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \ 122 hip01-ca9x2.dtb
123dtb-$(CONFIG_ARCH_HIP04) += \
124 hip04-d01.dtb
125dtb-$(CONFIG_ARCH_INTEGRATOR) += \
126 integratorap.dtb \
110 integratorcp.dtb 127 integratorcp.dtb
111dtb-$(CONFIG_ARCH_KEYSTONE) += k2hk-evm.dtb \ 128dtb-$(CONFIG_ARCH_KEYSTONE) += \
129 k2hk-evm.dtb \
112 k2l-evm.dtb \ 130 k2l-evm.dtb \
113 k2e-evm.dtb 131 k2e-evm.dtb
114dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \ 132dtb-$(CONFIG_MACH_KIRKWOOD) += \
133 kirkwood-b3.dtb \
134 kirkwood-blackarmor-nas220.dtb \
115 kirkwood-cloudbox.dtb \ 135 kirkwood-cloudbox.dtb \
116 kirkwood-d2net.dtb \ 136 kirkwood-d2net.dtb \
117 kirkwood-db-88f6281.dtb \ 137 kirkwood-db-88f6281.dtb \
@@ -160,6 +180,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \
160 kirkwood-openrd-base.dtb \ 180 kirkwood-openrd-base.dtb \
161 kirkwood-openrd-client.dtb \ 181 kirkwood-openrd-client.dtb \
162 kirkwood-openrd-ultimate.dtb \ 182 kirkwood-openrd-ultimate.dtb \
183 kirkwood-pogo_e02.dtb \
163 kirkwood-rd88f6192.dtb \ 184 kirkwood-rd88f6192.dtb \
164 kirkwood-rd88f6281-z0.dtb \ 185 kirkwood-rd88f6281-z0.dtb \
165 kirkwood-rd88f6281-a.dtb \ 186 kirkwood-rd88f6281-a.dtb \
@@ -174,37 +195,47 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \
174 kirkwood-ts219-6282.dtb \ 195 kirkwood-ts219-6282.dtb \
175 kirkwood-ts419-6281.dtb \ 196 kirkwood-ts419-6281.dtb \
176 kirkwood-ts419-6282.dtb 197 kirkwood-ts419-6282.dtb
177dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb 198dtb-$(CONFIG_ARCH_LPC32XX) += \
178dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb 199 ea3250.dtb phy3250.dtb
179dtb-$(CONFIG_MACH_MESON6) += meson6-atv1200.dtb 200dtb-$(CONFIG_MACH_MESON6) += \
180dtb-$(CONFIG_ARCH_MMP) += pxa168-aspenite.dtb \ 201 meson6-atv1200.dtb
202dtb-$(CONFIG_ARCH_MMP) += \
203 pxa168-aspenite.dtb \
181 pxa910-dkb.dtb \ 204 pxa910-dkb.dtb \
182 mmp2-brownstone.dtb 205 mmp2-brownstone.dtb
183dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb 206dtb-$(CONFIG_ARCH_MOXART) += \
184dtb-$(CONFIG_ARCH_MXC) += \ 207 moxart-uc7112lx.dtb
208dtb-$(CONFIG_SOC_IMX1) += \
185 imx1-ads.dtb \ 209 imx1-ads.dtb \
186 imx1-apf9328.dtb \ 210 imx1-apf9328.dtb
211dtb-$(CONFIG_SOC_IMX25) += \
187 imx25-eukrea-mbimxsd25-baseboard.dtb \ 212 imx25-eukrea-mbimxsd25-baseboard.dtb \
188 imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dtb \ 213 imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dtb \
189 imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dtb \ 214 imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dtb \
190 imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dtb \ 215 imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dtb \
191 imx25-karo-tx25.dtb \ 216 imx25-karo-tx25.dtb \
192 imx25-pdk.dtb \ 217 imx25-pdk.dtb
218dtb-$(CONFIG_SOC_IMX31) += \
193 imx27-apf27.dtb \ 219 imx27-apf27.dtb \
194 imx27-apf27dev.dtb \ 220 imx27-apf27dev.dtb \
195 imx27-eukrea-mbimxsd27-baseboard.dtb \ 221 imx27-eukrea-mbimxsd27-baseboard.dtb \
196 imx27-pdk.dtb \ 222 imx27-pdk.dtb \
197 imx27-phytec-phycore-rdk.dtb \ 223 imx27-phytec-phycore-rdk.dtb \
198 imx27-phytec-phycard-s-rdk.dtb \ 224 imx27-phytec-phycard-s-rdk.dtb
199 imx31-bug.dtb \ 225dtb-$(CONFIG_SOC_IMX31) += \
226 imx31-bug.dtb
227dtb-$(CONFIG_SOC_IMX35) += \
200 imx35-eukrea-mbimxsd35-baseboard.dtb \ 228 imx35-eukrea-mbimxsd35-baseboard.dtb \
201 imx35-pdk.dtb \ 229 imx35-pdk.dtb
202 imx50-evk.dtb \ 230dtb-$(CONFIG_SOC_IMX50) += \
231 imx50-evk.dtb
232dtb-$(CONFIG_SOC_IMX51) += \
203 imx51-apf51.dtb \ 233 imx51-apf51.dtb \
204 imx51-apf51dev.dtb \ 234 imx51-apf51dev.dtb \
205 imx51-babbage.dtb \ 235 imx51-babbage.dtb \
206 imx51-digi-connectcore-jsk.dtb \ 236 imx51-digi-connectcore-jsk.dtb \
207 imx51-eukrea-mbimxsd51-baseboard.dtb \ 237 imx51-eukrea-mbimxsd51-baseboard.dtb
238dtb-$(CONFIG_SOC_IMX53) += \
208 imx53-ard.dtb \ 239 imx53-ard.dtb \
209 imx53-m53evk.dtb \ 240 imx53-m53evk.dtb \
210 imx53-mba53.dtb \ 241 imx53-mba53.dtb \
@@ -213,7 +244,8 @@ dtb-$(CONFIG_ARCH_MXC) += \
213 imx53-smd.dtb \ 244 imx53-smd.dtb \
214 imx53-tx53-x03x.dtb \ 245 imx53-tx53-x03x.dtb \
215 imx53-tx53-x13x.dtb \ 246 imx53-tx53-x13x.dtb \
216 imx53-voipac-bsb.dtb \ 247 imx53-voipac-bsb.dtb
248dtb-$(CONFIG_SOC_IMX6Q) += \
217 imx6dl-aristainetos_4.dtb \ 249 imx6dl-aristainetos_4.dtb \
218 imx6dl-aristainetos_7.dtb \ 250 imx6dl-aristainetos_7.dtb \
219 imx6dl-cubox-i.dtb \ 251 imx6dl-cubox-i.dtb \
@@ -234,6 +266,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
234 imx6dl-tx6dl-comtft.dtb \ 266 imx6dl-tx6dl-comtft.dtb \
235 imx6dl-tx6u-801x.dtb \ 267 imx6dl-tx6u-801x.dtb \
236 imx6dl-tx6u-811x.dtb \ 268 imx6dl-tx6u-811x.dtb \
269 imx6dl-udoo.dtb \
237 imx6dl-wandboard.dtb \ 270 imx6dl-wandboard.dtb \
238 imx6dl-wandboard-revb1.dtb \ 271 imx6dl-wandboard-revb1.dtb \
239 imx6q-arm2.dtb \ 272 imx6q-arm2.dtb \
@@ -257,23 +290,29 @@ dtb-$(CONFIG_ARCH_MXC) += \
257 imx6q-sabresd.dtb \ 290 imx6q-sabresd.dtb \
258 imx6q-sbc6x.dtb \ 291 imx6q-sbc6x.dtb \
259 imx6q-tbs2910.dtb \ 292 imx6q-tbs2910.dtb \
260 imx6q-udoo.dtb \
261 imx6q-wandboard.dtb \
262 imx6q-wandboard-revb1.dtb \
263 imx6q-tx6q-1010.dtb \ 293 imx6q-tx6q-1010.dtb \
264 imx6q-tx6q-1010-comtft.dtb \ 294 imx6q-tx6q-1010-comtft.dtb \
265 imx6q-tx6q-1020.dtb \ 295 imx6q-tx6q-1020.dtb \
266 imx6q-tx6q-1020-comtft.dtb \ 296 imx6q-tx6q-1020-comtft.dtb \
267 imx6q-tx6q-1110.dtb \ 297 imx6q-tx6q-1110.dtb \
268 imx6sl-evk.dtb \ 298 imx6q-udoo.dtb \
269 imx6sx-sdb.dtb \ 299 imx6q-wandboard.dtb \
300 imx6q-wandboard-revb1.dtb
301dtb-$(CONFIG_SOC_IMX6SL) += \
302 imx6sl-evk.dtb
303dtb-$(CONFIG_SOC_IMX6SX) += \
304 imx6sx-sabreauto.dtb \
305 imx6sx-sdb.dtb
306dtb-$(CONFIG_SOC_LS1021A) += \
270 ls1021a-qds.dtb \ 307 ls1021a-qds.dtb \
271 ls1021a-twr.dtb \ 308 ls1021a-twr.dtb
309dtb-$(CONFIG_SOC_VF610) += \
272 vf500-colibri-eval-v3.dtb \ 310 vf500-colibri-eval-v3.dtb \
273 vf610-colibri-eval-v3.dtb \ 311 vf610-colibri-eval-v3.dtb \
274 vf610-cosmic.dtb \ 312 vf610-cosmic.dtb \
275 vf610-twr.dtb 313 vf610-twr.dtb
276dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ 314dtb-$(CONFIG_ARCH_MXS) += \
315 imx23-evk.dtb \
277 imx23-olinuxino.dtb \ 316 imx23-olinuxino.dtb \
278 imx23-stmp378x_devb.dtb \ 317 imx23-stmp378x_devb.dtb \
279 imx28-apf28.dtb \ 318 imx28-apf28.dtb \
@@ -294,17 +333,21 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
294 imx28-m28evk.dtb \ 333 imx28-m28evk.dtb \
295 imx28-sps1.dtb \ 334 imx28-sps1.dtb \
296 imx28-tx28.dtb 335 imx28-tx28.dtb
297dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb \ 336dtb-$(CONFIG_ARCH_NOMADIK) += \
337 ste-nomadik-s8815.dtb \
298 ste-nomadik-nhk15.dtb 338 ste-nomadik-nhk15.dtb
299dtb-$(CONFIG_ARCH_NSPIRE) += nspire-cx.dtb \ 339dtb-$(CONFIG_ARCH_NSPIRE) += \
340 nspire-cx.dtb \
300 nspire-tp.dtb \ 341 nspire-tp.dtb \
301 nspire-clp.dtb 342 nspire-clp.dtb
302dtb-$(CONFIG_ARCH_OMAP2) += omap2420-h4.dtb \ 343dtb-$(CONFIG_ARCH_OMAP2) += \
344 omap2420-h4.dtb \
303 omap2420-n800.dtb \ 345 omap2420-n800.dtb \
304 omap2420-n810.dtb \ 346 omap2420-n810.dtb \
305 omap2420-n810-wimax.dtb \ 347 omap2420-n810-wimax.dtb \
306 omap2430-sdp.dtb 348 omap2430-sdp.dtb
307dtb-$(CONFIG_ARCH_OMAP3) += am3517-craneboard.dtb \ 349dtb-$(CONFIG_ARCH_OMAP3) += \
350 am3517-craneboard.dtb \
308 am3517-evm.dtb \ 351 am3517-evm.dtb \
309 am3517_mt_ventoux.dtb \ 352 am3517_mt_ventoux.dtb \
310 omap3430-sdp.dtb \ 353 omap3430-sdp.dtb \
@@ -348,7 +391,10 @@ dtb-$(CONFIG_ARCH_OMAP3) += am3517-craneboard.dtb \
348 omap3-sbc-t3730.dtb \ 391 omap3-sbc-t3730.dtb \
349 omap3-thunder.dtb \ 392 omap3-thunder.dtb \
350 omap3-zoom3.dtb 393 omap3-zoom3.dtb
351dtb-$(CONFIG_SOC_AM33XX) += am335x-base0033.dtb \ 394dtb-$(CONFIG_SOC_TI81XX) += \
395 dm8168-evm.dtb
396dtb-$(CONFIG_SOC_AM33XX) += \
397 am335x-base0033.dtb \
352 am335x-bone.dtb \ 398 am335x-bone.dtb \
353 am335x-boneblack.dtb \ 399 am335x-boneblack.dtb \
354 am335x-evm.dtb \ 400 am335x-evm.dtb \
@@ -356,7 +402,8 @@ dtb-$(CONFIG_SOC_AM33XX) += am335x-base0033.dtb \
356 am335x-nano.dtb \ 402 am335x-nano.dtb \
357 am335x-pepper.dtb \ 403 am335x-pepper.dtb \
358 am335x-lxm.dtb 404 am335x-lxm.dtb
359dtb-$(CONFIG_ARCH_OMAP4) += omap4-duovero-parlor.dtb \ 405dtb-$(CONFIG_ARCH_OMAP4) += \
406 omap4-duovero-parlor.dtb \
360 omap4-panda.dtb \ 407 omap4-panda.dtb \
361 omap4-panda-a4.dtb \ 408 omap4-panda-a4.dtb \
362 omap4-panda-es.dtb \ 409 omap4-panda-es.dtb \
@@ -364,20 +411,26 @@ dtb-$(CONFIG_ARCH_OMAP4) += omap4-duovero-parlor.dtb \
364 omap4-sdp-es23plus.dtb \ 411 omap4-sdp-es23plus.dtb \
365 omap4-var-dvk-om44.dtb \ 412 omap4-var-dvk-om44.dtb \
366 omap4-var-stk-om44.dtb 413 omap4-var-stk-om44.dtb
367dtb-$(CONFIG_SOC_AM43XX) += am43x-epos-evm.dtb \ 414dtb-$(CONFIG_SOC_AM43XX) += \
415 am43x-epos-evm.dtb \
368 am437x-sk-evm.dtb \ 416 am437x-sk-evm.dtb \
417 am437x-idk-evm.dtb \
369 am437x-gp-evm.dtb 418 am437x-gp-evm.dtb
370dtb-$(CONFIG_SOC_OMAP5) += omap5-cm-t54.dtb \ 419dtb-$(CONFIG_SOC_OMAP5) += \
420 omap5-cm-t54.dtb \
371 omap5-sbc-t54.dtb \ 421 omap5-sbc-t54.dtb \
372 omap5-uevm.dtb 422 omap5-uevm.dtb
373dtb-$(CONFIG_SOC_DRA7XX) += dra7-evm.dtb \ 423dtb-$(CONFIG_SOC_DRA7XX) += \
424 dra7-evm.dtb \
374 am57xx-beagle-x15.dtb \ 425 am57xx-beagle-x15.dtb \
375 dra72-evm.dtb 426 dra72-evm.dtb
376dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-d2-network.dtb \ 427dtb-$(CONFIG_ARCH_ORION5X) += \
428 orion5x-lacie-d2-network.dtb \
377 orion5x-lacie-ethernet-disk-mini-v2.dtb \ 429 orion5x-lacie-ethernet-disk-mini-v2.dtb \
378 orion5x-maxtor-shared-storage-2.dtb \ 430 orion5x-maxtor-shared-storage-2.dtb \
379 orion5x-rd88f5182-nas.dtb 431 orion5x-rd88f5182-nas.dtb
380dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb 432dtb-$(CONFIG_ARCH_PRIMA2) += \
433 prima2-evb.dtb
381dtb-$(CONFIG_ARCH_QCOM) += \ 434dtb-$(CONFIG_ARCH_QCOM) += \
382 qcom-apq8064-cm-qs600.dtb \ 435 qcom-apq8064-cm-qs600.dtb \
383 qcom-apq8064-ifc6410.dtb \ 436 qcom-apq8064-ifc6410.dtb \
@@ -388,17 +441,24 @@ dtb-$(CONFIG_ARCH_QCOM) += \
388 qcom-msm8660-surf.dtb \ 441 qcom-msm8660-surf.dtb \
389 qcom-msm8960-cdp.dtb \ 442 qcom-msm8960-cdp.dtb \
390 qcom-msm8974-sony-xperia-honami.dtb 443 qcom-msm8974-sony-xperia-honami.dtb
391dtb-$(CONFIG_ARCH_REALVIEW) += arm-realview-pb1176.dtb 444dtb-$(CONFIG_ARCH_REALVIEW) += \
445 arm-realview-pb1176.dtb
392dtb-$(CONFIG_ARCH_ROCKCHIP) += \ 446dtb-$(CONFIG_ARCH_ROCKCHIP) += \
393 rk3066a-bqcurie2.dtb \ 447 rk3066a-bqcurie2.dtb \
394 rk3066a-marsboard.dtb \ 448 rk3066a-marsboard.dtb \
449 rk3066a-rayeager.dtb \
395 rk3188-radxarock.dtb \ 450 rk3188-radxarock.dtb \
396 rk3288-evb-act8846.dtb \ 451 rk3288-evb-act8846.dtb \
397 rk3288-evb-rk808.dtb 452 rk3288-evb-rk808.dtb \
398dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb 453 rk3288-firefly-beta.dtb \
399dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \ 454 rk3288-firefly.dtb
455dtb-$(CONFIG_ARCH_S3C24XX) += \
456 s3c2416-smdk2416.dtb
457dtb-$(CONFIG_ARCH_S3C64XX) += \
458 s3c6410-mini6410.dtb \
400 s3c6410-smdk6410.dtb 459 s3c6410-smdk6410.dtb
401dtb-$(CONFIG_ARCH_S5PV210) += s5pv210-aquila.dtb \ 460dtb-$(CONFIG_ARCH_S5PV210) += \
461 s5pv210-aquila.dtb \
402 s5pv210-goni.dtb \ 462 s5pv210-goni.dtb \
403 s5pv210-smdkc110.dtb \ 463 s5pv210-smdkc110.dtb \
404 s5pv210-smdkv210.dtb \ 464 s5pv210-smdkv210.dtb \
@@ -413,44 +473,58 @@ dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += \
413 sh7372-mackerel.dtb \ 473 sh7372-mackerel.dtb \
414 sh73a0-kzm9g.dtb \ 474 sh73a0-kzm9g.dtb \
415 sh73a0-kzm9g-reference.dtb 475 sh73a0-kzm9g-reference.dtb
416dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \ 476dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
477 emev2-kzm9d.dtb \
417 r7s72100-genmai.dtb \ 478 r7s72100-genmai.dtb \
479 r8a73a4-ape6evm.dtb \
418 r8a7740-armadillo800eva.dtb \ 480 r8a7740-armadillo800eva.dtb \
419 r8a7779-marzen.dtb \ 481 r8a7779-marzen.dtb \
420 r8a7790-lager.dtb \ 482 r8a7790-lager.dtb \
421 r8a7791-henninger.dtb \ 483 r8a7791-henninger.dtb \
422 r8a7791-koelsch.dtb \ 484 r8a7791-koelsch.dtb \
423 r8a7794-alt.dtb 485 r8a7794-alt.dtb
424dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \ 486dtb-$(CONFIG_ARCH_SOCFPGA) += \
487 socfpga_arria5_socdk.dtb \
425 socfpga_arria10_socdk.dtb \ 488 socfpga_arria10_socdk.dtb \
426 socfpga_cyclone5_socdk.dtb \ 489 socfpga_cyclone5_socdk.dtb \
427 socfpga_cyclone5_sockit.dtb \ 490 socfpga_cyclone5_sockit.dtb \
428 socfpga_cyclone5_socrates.dtb \ 491 socfpga_cyclone5_socrates.dtb \
429 socfpga_vt.dtb 492 socfpga_vt.dtb
430dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \ 493dtb-$(CONFIG_ARCH_SPEAR13XX) += \
494 spear1310-evb.dtb \
431 spear1340-evb.dtb 495 spear1340-evb.dtb
432dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \ 496dtb-$(CONFIG_ARCH_SPEAR3XX) += \
497 spear300-evb.dtb \
433 spear310-evb.dtb \ 498 spear310-evb.dtb \
434 spear320-evb.dtb \ 499 spear320-evb.dtb \
435 spear320-hmi.dtb 500 spear320-hmi.dtb
436dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb 501dtb-$(CONFIG_ARCH_SPEAR6XX) += \
437dtb-$(CONFIG_ARCH_STI)+= stih407-b2120.dtb \ 502 spear600-evb.dtb
503dtb-$(CONFIG_ARCH_STI) += \
504 stih407-b2120.dtb \
438 stih410-b2120.dtb \ 505 stih410-b2120.dtb \
439 stih415-b2000.dtb \ 506 stih415-b2000.dtb \
440 stih415-b2020.dtb \ 507 stih415-b2020.dtb \
441 stih416-b2000.dtb \ 508 stih416-b2000.dtb \
442 stih416-b2020.dtb \ 509 stih416-b2020.dtb \
443 stih416-b2020e.dtb 510 stih416-b2020e.dtb \
511 stih418-b2199.dtb
444dtb-$(CONFIG_MACH_SUN4I) += \ 512dtb-$(CONFIG_MACH_SUN4I) += \
445 sun4i-a10-a1000.dtb \ 513 sun4i-a10-a1000.dtb \
446 sun4i-a10-ba10-tvbox.dtb \ 514 sun4i-a10-ba10-tvbox.dtb \
515 sun4i-a10-chuwi-v7-cw0825.dtb \
447 sun4i-a10-cubieboard.dtb \ 516 sun4i-a10-cubieboard.dtb \
517 sun4i-a10-marsboard.dtb \
448 sun4i-a10-mini-xplus.dtb \ 518 sun4i-a10-mini-xplus.dtb \
519 sun4i-a10-mk802.dtb \
520 sun4i-a10-mk802ii.dtb \
449 sun4i-a10-hackberry.dtb \ 521 sun4i-a10-hackberry.dtb \
522 sun4i-a10-hyundai-a7hd.dtb \
450 sun4i-a10-inet97fv2.dtb \ 523 sun4i-a10-inet97fv2.dtb \
451 sun4i-a10-olinuxino-lime.dtb \ 524 sun4i-a10-olinuxino-lime.dtb \
452 sun4i-a10-pcduino.dtb 525 sun4i-a10-pcduino.dtb
453dtb-$(CONFIG_MACH_SUN5I) += \ 526dtb-$(CONFIG_MACH_SUN5I) += \
527 sun5i-a10s-mk802.dtb \
454 sun5i-a10s-olinuxino-micro.dtb \ 528 sun5i-a10s-olinuxino-micro.dtb \
455 sun5i-a10s-r7-tv-dongle.dtb \ 529 sun5i-a10s-r7-tv-dongle.dtb \
456 sun5i-a13-hsg-h702.dtb \ 530 sun5i-a13-hsg-h702.dtb \
@@ -460,9 +534,11 @@ dtb-$(CONFIG_MACH_SUN6I) += \
460 sun6i-a31-app4-evb1.dtb \ 534 sun6i-a31-app4-evb1.dtb \
461 sun6i-a31-colombus.dtb \ 535 sun6i-a31-colombus.dtb \
462 sun6i-a31-hummingbird.dtb \ 536 sun6i-a31-hummingbird.dtb \
463 sun6i-a31-m9.dtb 537 sun6i-a31-m9.dtb \
538 sun6i-a31s-cs908.dtb
464dtb-$(CONFIG_MACH_SUN7I) += \ 539dtb-$(CONFIG_MACH_SUN7I) += \
465 sun7i-a20-bananapi.dtb \ 540 sun7i-a20-bananapi.dtb \
541 sun7i-a20-bananapro.dtb \
466 sun7i-a20-cubieboard2.dtb \ 542 sun7i-a20-cubieboard2.dtb \
467 sun7i-a20-cubietruck.dtb \ 543 sun7i-a20-cubietruck.dtb \
468 sun7i-a20-hummingbird.dtb \ 544 sun7i-a20-hummingbird.dtb \
@@ -473,10 +549,12 @@ dtb-$(CONFIG_MACH_SUN7I) += \
473 sun7i-a20-olinuxino-micro.dtb \ 549 sun7i-a20-olinuxino-micro.dtb \
474 sun7i-a20-pcduino3.dtb 550 sun7i-a20-pcduino3.dtb
475dtb-$(CONFIG_MACH_SUN8I) += \ 551dtb-$(CONFIG_MACH_SUN8I) += \
476 sun8i-a23-ippo-q8h-v5.dtb 552 sun8i-a23-ippo-q8h-v5.dtb \
553 sun8i-a23-ippo-q8h-v1.2.dtb
477dtb-$(CONFIG_MACH_SUN9I) += \ 554dtb-$(CONFIG_MACH_SUN9I) += \
478 sun9i-a80-optimus.dtb 555 sun9i-a80-optimus.dtb
479dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ 556dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
557 tegra20-harmony.dtb \
480 tegra20-iris-512.dtb \ 558 tegra20-iris-512.dtb \
481 tegra20-medcom-wide.dtb \ 559 tegra20-medcom-wide.dtb \
482 tegra20-paz00.dtb \ 560 tegra20-paz00.dtb \
@@ -485,34 +563,43 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
485 tegra20-tec.dtb \ 563 tegra20-tec.dtb \
486 tegra20-trimslice.dtb \ 564 tegra20-trimslice.dtb \
487 tegra20-ventana.dtb \ 565 tegra20-ventana.dtb \
488 tegra20-whistler.dtb \ 566 tegra20-whistler.dtb
567dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \
489 tegra30-apalis-eval.dtb \ 568 tegra30-apalis-eval.dtb \
490 tegra30-beaver.dtb \ 569 tegra30-beaver.dtb \
491 tegra30-cardhu-a02.dtb \ 570 tegra30-cardhu-a02.dtb \
492 tegra30-cardhu-a04.dtb \ 571 tegra30-cardhu-a04.dtb \
493 tegra30-colibri-eval-v3.dtb \ 572 tegra30-colibri-eval-v3.dtb
573dtb-$(CONFIG_ARCH_TEGRA_114_SOC) += \
494 tegra114-dalmore.dtb \ 574 tegra114-dalmore.dtb \
495 tegra114-roth.dtb \ 575 tegra114-roth.dtb \
496 tegra114-tn7.dtb \ 576 tegra114-tn7.dtb
577dtb-$(CONFIG_ARCH_TEGRA_124_SOC) += \
497 tegra124-jetson-tk1.dtb \ 578 tegra124-jetson-tk1.dtb \
498 tegra124-nyan-big.dtb \ 579 tegra124-nyan-big.dtb \
499 tegra124-venice2.dtb 580 tegra124-venice2.dtb
500dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb 581dtb-$(CONFIG_ARCH_U300) += \
501dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \ 582 ste-u300.dtb
583dtb-$(CONFIG_ARCH_U8500) += \
584 ste-snowball.dtb \
502 ste-hrefprev60-stuib.dtb \ 585 ste-hrefprev60-stuib.dtb \
503 ste-hrefprev60-tvk.dtb \ 586 ste-hrefprev60-tvk.dtb \
504 ste-hrefv60plus-stuib.dtb \ 587 ste-hrefv60plus-stuib.dtb \
505 ste-hrefv60plus-tvk.dtb \ 588 ste-hrefv60plus-tvk.dtb \
506 ste-ccu8540.dtb \ 589 ste-ccu8540.dtb \
507 ste-ccu9540.dtb 590 ste-ccu9540.dtb
508dtb-$(CONFIG_ARCH_VERSATILE) += versatile-ab.dtb \ 591dtb-$(CONFIG_ARCH_VERSATILE) += \
592 versatile-ab.dtb \
509 versatile-pb.dtb 593 versatile-pb.dtb
510dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \ 594dtb-$(CONFIG_ARCH_VEXPRESS) += \
595 vexpress-v2p-ca5s.dtb \
511 vexpress-v2p-ca9.dtb \ 596 vexpress-v2p-ca9.dtb \
512 vexpress-v2p-ca15-tc1.dtb \ 597 vexpress-v2p-ca15-tc1.dtb \
513 vexpress-v2p-ca15_a7.dtb 598 vexpress-v2p-ca15_a7.dtb
514dtb-$(CONFIG_ARCH_VIRT) += xenvm-4.2.dtb 599dtb-$(CONFIG_ARCH_VIRT) += \
515dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \ 600 xenvm-4.2.dtb
601dtb-$(CONFIG_ARCH_VT8500) += \
602 vt8500-bv07.dtb \
516 wm8505-ref.dtb \ 603 wm8505-ref.dtb \
517 wm8650-mid.dtb \ 604 wm8650-mid.dtb \
518 wm8750-apc8750.dtb \ 605 wm8750-apc8750.dtb \
@@ -533,8 +620,10 @@ dtb-$(CONFIG_MACH_ARMADA_370) += \
533dtb-$(CONFIG_MACH_ARMADA_375) += \ 620dtb-$(CONFIG_MACH_ARMADA_375) += \
534 armada-375-db.dtb 621 armada-375-db.dtb
535dtb-$(CONFIG_MACH_ARMADA_38X) += \ 622dtb-$(CONFIG_MACH_ARMADA_38X) += \
536 armada-385-db.dtb \ 623 armada-385-db-ap.dtb \
537 armada-385-rd.dtb 624 armada-388-db.dtb \
625 armada-388-gp.dtb \
626 armada-388-rd.dtb
538dtb-$(CONFIG_MACH_ARMADA_XP) += \ 627dtb-$(CONFIG_MACH_ARMADA_XP) += \
539 armada-xp-axpwifiap.dtb \ 628 armada-xp-axpwifiap.dtb \
540 armada-xp-db.dtb \ 629 armada-xp-db.dtb \
@@ -544,17 +633,18 @@ dtb-$(CONFIG_MACH_ARMADA_XP) += \
544 armada-xp-netgear-rn2120.dtb \ 633 armada-xp-netgear-rn2120.dtb \
545 armada-xp-openblocks-ax3-4.dtb \ 634 armada-xp-openblocks-ax3-4.dtb \
546 armada-xp-synology-ds414.dtb 635 armada-xp-synology-ds414.dtb
547dtb-$(CONFIG_MACH_DOVE) += dove-cm-a510.dtb \ 636dtb-$(CONFIG_MACH_DOVE) += \
637 dove-cm-a510.dtb \
548 dove-cubox.dtb \ 638 dove-cubox.dtb \
549 dove-cubox-es.dtb \ 639 dove-cubox-es.dtb \
550 dove-d2plug.dtb \ 640 dove-d2plug.dtb \
551 dove-d3plug.dtb \ 641 dove-d3plug.dtb \
552 dove-dove-db.dtb 642 dove-dove-db.dtb
553dtb-$(CONFIG_ARCH_MEDIATEK) += mt6589-aquaris5.dtb \ 643dtb-$(CONFIG_ARCH_MEDIATEK) += \
644 mt6589-aquaris5.dtb \
554 mt6592-evb.dtb \ 645 mt6592-evb.dtb \
555 mt8127-moose.dtb \ 646 mt8127-moose.dtb \
556 mt8135-evbp1.dtb 647 mt8135-evbp1.dtb
557
558endif 648endif
559 649
560always := $(dtb-y) 650always := $(dtb-y)
diff --git a/arch/arm/boot/dts/alphascale-asm9260-devkit.dts b/arch/arm/boot/dts/alphascale-asm9260-devkit.dts
new file mode 100644
index 000000000000..c77e2c902fb6
--- /dev/null
+++ b/arch/arm/boot/dts/alphascale-asm9260-devkit.dts
@@ -0,0 +1,13 @@
1/*
2 * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
3 *
4 * Licensed under the X11 license or the GPL v2 (or later)
5 */
6
7/dts-v1/;
8#include "alphascale-asm9260.dtsi"
9
10/ {
11 model = "Alphascale asm9260 Development Kit";
12 compatible = "alphascale,asm9260devkit", "alphascale,asm9260";
13};
diff --git a/arch/arm/boot/dts/alphascale-asm9260.dtsi b/arch/arm/boot/dts/alphascale-asm9260.dtsi
new file mode 100644
index 000000000000..907fc7bfc418
--- /dev/null
+++ b/arch/arm/boot/dts/alphascale-asm9260.dtsi
@@ -0,0 +1,63 @@
1/*
2 * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
3 *
4 * Licensed under the X11 license or the GPL v2 (or later)
5 */
6
7#include "skeleton.dtsi"
8#include <dt-bindings/clock/alphascale,asm9260.h>
9
10/ {
11 interrupt-parent = <&icoll>;
12
13 memory {
14 device_type = "memory";
15 reg = <0x20000000 0x2000000>;
16 };
17
18 cpus {
19 #address-cells = <0>;
20 #size-cells = <0>;
21
22 cpu {
23 compatible = "arm,arm926ej-s";
24 device_type = "cpu";
25 clocks = <&acc CLKID_SYS_CPU>;
26 };
27 };
28
29 osc24m: oscillator {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <24000000>;
33 clock-accuracy = <30000>;
34 };
35
36 soc {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "simple-bus";
40 ranges;
41
42 acc: clock-controller@80040000 {
43 compatible = "alphascale,asm9260-clock-controller";
44 #clock-cells = <1>;
45 clocks = <&osc24m>;
46 reg = <0x80040000 0x204>;
47 };
48
49 icoll: interrupt-controller@80054000 {
50 compatible = "alphascale,asm9260-icoll";
51 interrupt-controller;
52 #interrupt-cells = <1>;
53 reg = <0x80054000 0x200>;
54 };
55
56 timer0: timer@80088000 {
57 compatible = "alphascale,asm9260-timer";
58 reg = <0x80088000 0x4000>;
59 clocks = <&acc CLKID_AHB_TIMER0>;
60 interrupts = <29>;
61 };
62 };
63};
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index b62a1cd776cd..1943fc333e7c 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -948,6 +948,22 @@
948 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 948 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
949 status = "disabled"; 949 status = "disabled";
950 }; 950 };
951
952 vpfe0: vpfe@48326000 {
953 compatible = "ti,am437x-vpfe";
954 reg = <0x48326000 0x2000>;
955 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
956 ti,hwmods = "vpfe0";
957 status = "disabled";
958 };
959
960 vpfe1: vpfe@48328000 {
961 compatible = "ti,am437x-vpfe";
962 reg = <0x48328000 0x2000>;
963 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
964 ti,hwmods = "vpfe1";
965 status = "disabled";
966 };
951 }; 967 };
952}; 968};
953 969
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
index 7eaae4cf9f89..f84d9715a4a9 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -268,6 +268,78 @@
268 0x184 (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */ 268 0x184 (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */
269 >; 269 >;
270 }; 270 };
271
272 vpfe0_pins_default: vpfe0_pins_default {
273 pinctrl-single,pins = <
274 0x1B0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/
275 0x1B4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/
276 0x1C0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/
277 0x1C4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/
278 0x1C8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/
279 0x208 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/
280 0x20C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/
281 0x210 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/
282 0x214 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/
283 0x218 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/
284 0x21C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/
285 0x220 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/
286 0x224 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/
287 >;
288 };
289
290 vpfe0_pins_sleep: vpfe0_pins_sleep {
291 pinctrl-single,pins = <
292 0x1B0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/
293 0x1B4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/
294 0x1C0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_pclk mode 0*/
295 0x1C4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data8 mode 0*/
296 0x1C8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data9 mode 0*/
297 0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data0 mode 0*/
298 0x20C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data1 mode 0*/
299 0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data2 mode 0*/
300 0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data3 mode 0*/
301 0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data4 mode 0*/
302 0x21C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data5 mode 0*/
303 0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data6 mode 0*/
304 0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data7 mode 0*/
305 >;
306 };
307
308 vpfe1_pins_default: vpfe1_pins_default {
309 pinctrl-single,pins = <
310 0x1CC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/
311 0x1D0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/
312 0x1D4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0*/
313 0x1D8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0*/
314 0x1DC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0*/
315 0x1E8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0*/
316 0x1EC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0*/
317 0x1F0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0*/
318 0x1F4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0*/
319 0x1F8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0*/
320 0x1FC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0*/
321 0x200 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0*/
322 0x204 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0*/
323 >;
324 };
325
326 vpfe1_pins_sleep: vpfe1_pins_sleep {
327 pinctrl-single,pins = <
328 0x1CC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/
329 0x1D0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/
330 0x1D4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_hd mode 0*/
331 0x1D8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_vd mode 0*/
332 0x1DC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_pclk mode 0*/
333 0x1E8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data0 mode 0*/
334 0x1EC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data1 mode 0*/
335 0x1F0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data2 mode 0*/
336 0x1F4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data3 mode 0*/
337 0x1F8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data4 mode 0*/
338 0x1FC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data5 mode 0*/
339 0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data6 mode 0*/
340 0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/
341 >;
342 };
271}; 343};
272 344
273&i2c0 { 345&i2c0 {
@@ -545,3 +617,37 @@
545 pinctrl-0 = <&dcan1_default>; 617 pinctrl-0 = <&dcan1_default>;
546 status = "okay"; 618 status = "okay";
547}; 619};
620
621&vpfe0 {
622 status = "okay";
623 pinctrl-names = "default", "sleep";
624 pinctrl-0 = <&vpfe0_pins_default>;
625 pinctrl-1 = <&vpfe0_pins_sleep>;
626
627 port {
628 vpfe0_ep: endpoint {
629 /* remote-endpoint = <&sensor>; add once we have it */
630 ti,am437x-vpfe-interface = <0>;
631 bus-width = <8>;
632 hsync-active = <0>;
633 vsync-active = <0>;
634 };
635 };
636};
637
638&vpfe1 {
639 status = "okay";
640 pinctrl-names = "default", "sleep";
641 pinctrl-0 = <&vpfe1_pins_default>;
642 pinctrl-1 = <&vpfe1_pins_sleep>;
643
644 port {
645 vpfe1_ep: endpoint {
646 /* remote-endpoint = <&sensor>; add once we have it */
647 ti,am437x-vpfe-interface = <0>;
648 bus-width = <8>;
649 hsync-active = <0>;
650 vsync-active = <0>;
651 };
652 };
653};
diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts b/arch/arm/boot/dts/am437x-idk-evm.dts
new file mode 100644
index 000000000000..f9a17e2ca8cb
--- /dev/null
+++ b/arch/arm/boot/dts/am437x-idk-evm.dts
@@ -0,0 +1,405 @@
1/*
2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/dts-v1/;
10
11#include "am4372.dtsi"
12#include <dt-bindings/pinctrl/am43xx.h>
13#include <dt-bindings/pwm/pwm.h>
14#include <dt-bindings/gpio/gpio.h>
15#include <dt-bindings/input/input.h>
16
17/ {
18 model = "TI AM437x Industrial Development Kit";
19 compatible = "ti,am437x-idk-evm","ti,am4372","ti,am43";
20
21 v24_0d: fixed-regulator-v24_0d {
22 compatible = "regulator-fixed";
23 regulator-name = "V24_0D";
24 regulator-min-microvolt = <24000000>;
25 regulator-max-microvolt = <24000000>;
26 regulator-always-on;
27 regulator-boot-on;
28 };
29
30 v3_3d: fixed-regulator-v3_3d {
31 compatible = "regulator-fixed";
32 regulator-name = "V3_3D";
33 regulator-min-microvolt = <3300000>;
34 regulator-max-microvolt = <3300000>;
35 regulator-always-on;
36 regulator-boot-on;
37 vin-supply = <&v24_0d>;
38 };
39
40 vdd_corereg: fixed-regulator-vdd_corereg {
41 compatible = "regulator-fixed";
42 regulator-name = "VDD_COREREG";
43 regulator-min-microvolt = <1100000>;
44 regulator-max-microvolt = <1100000>;
45 regulator-always-on;
46 regulator-boot-on;
47 vin-supply = <&v24_0d>;
48 };
49
50 vdd_core: fixed-regulator-vdd_core {
51 compatible = "regulator-fixed";
52 regulator-name = "VDD_CORE";
53 regulator-min-microvolt = <1100000>;
54 regulator-max-microvolt = <1100000>;
55 regulator-always-on;
56 regulator-boot-on;
57 vin-supply = <&vdd_corereg>;
58 };
59
60 v1_8dreg: fixed-regulator-v1_8dreg{
61 compatible = "regulator-fixed";
62 regulator-name = "V1_8DREG";
63 regulator-min-microvolt = <1800000>;
64 regulator-max-microvolt = <1800000>;
65 regulator-always-on;
66 regulator-boot-on;
67 vin-supply = <&v24_0d>;
68 };
69
70 v1_8d: fixed-regulator-v1_8d{
71 compatible = "regulator-fixed";
72 regulator-name = "V1_8D";
73 regulator-min-microvolt = <1800000>;
74 regulator-max-microvolt = <1800000>;
75 regulator-always-on;
76 regulator-boot-on;
77 vin-supply = <&v1_8dreg>;
78 };
79
80 v1_5dreg: fixed-regulator-v1_5dreg{
81 compatible = "regulator-fixed";
82 regulator-name = "V1_5DREG";
83 regulator-min-microvolt = <1500000>;
84 regulator-max-microvolt = <1500000>;
85 regulator-always-on;
86 regulator-boot-on;
87 vin-supply = <&v24_0d>;
88 };
89
90 v1_5d: fixed-regulator-v1_5d{
91 compatible = "regulator-fixed";
92 regulator-name = "V1_5D";
93 regulator-min-microvolt = <1500000>;
94 regulator-max-microvolt = <1500000>;
95 regulator-always-on;
96 regulator-boot-on;
97 vin-supply = <&v1_5dreg>;
98 };
99
100 gpio_keys: gpio_keys {
101 compatible = "gpio-keys";
102 pinctrl-names = "default";
103 pinctrl-0 = <&gpio_keys_pins_default>;
104 #address-cells = <1>;
105 #size-cells = <0>;
106
107 switch@0 {
108 label = "power-button";
109 linux,code = <KEY_POWER>;
110 gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
111 };
112 };
113};
114
115&am43xx_pinmux {
116 gpio_keys_pins_default: gpio_keys_pins_default {
117 pinctrl-single,pins = <
118 0x1b8 (PIN_INPUT | MUX_MODE7) /* cam0_field.gpio4_2 */
119 >;
120 };
121
122 i2c0_pins_default: i2c0_pins_default {
123 pinctrl-single,pins = <
124 0x188 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
125 0x18c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
126 >;
127 };
128
129 i2c0_pins_sleep: i2c0_pins_sleep {
130 pinctrl-single,pins = <
131 0x188 (PIN_INPUT_PULLDOWN | MUX_MODE7)
132 0x18c (PIN_INPUT_PULLDOWN | MUX_MODE7)
133 >;
134 };
135
136 i2c1_pins_default: i2c1_pins_default {
137 pinctrl-single,pins = <
138 0x15c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
139 0x158 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
140 >;
141 };
142
143 i2c1_pins_sleep: i2c1_pins_sleep {
144 pinctrl-single,pins = <
145 0x15c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_cs0.i2c1_scl */
146 0x158 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d1.i2c1_sda */
147 >;
148 };
149
150 mmc1_pins_default: pinmux_mmc1_pins_default {
151 pinctrl-single,pins = <
152 0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
153 0x104 (PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
154 0x1f0 (PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
155 0x1f4 (PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
156 0x1f8 (PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
157 0x1fc (PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
158 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
159 >;
160 };
161
162 mmc1_pins_sleep: pinmux_mmc1_pins_sleep {
163 pinctrl-single,pins = <
164 0x100 (PIN_INPUT_PULLDOWN | MUX_MODE7)
165 0x104 (PIN_INPUT_PULLDOWN | MUX_MODE7)
166 0x1f0 (PIN_INPUT_PULLDOWN | MUX_MODE7)
167 0x1f4 (PIN_INPUT_PULLDOWN | MUX_MODE7)
168 0x1f8 (PIN_INPUT_PULLDOWN | MUX_MODE7)
169 0x1fc (PIN_INPUT_PULLDOWN | MUX_MODE7)
170 0x160 (PIN_INPUT_PULLDOWN | MUX_MODE7)
171 >;
172 };
173
174 ecap0_pins_default: backlight_pins_default {
175 pinctrl-single,pins = <
176 0x164 (PIN_OUTPUT | MUX_MODE0) /* ecap0_in_pwm0_out.ecap0_in_pwm0_out */
177 >;
178 };
179
180 cpsw_default: cpsw_default {
181 pinctrl-single,pins = <
182 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
183 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
184 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
185 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
186 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */
187 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */
188 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
189 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
190 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
191 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
192 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */
193 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */
194 >;
195 };
196
197 cpsw_sleep: cpsw_sleep {
198 pinctrl-single,pins = <
199 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
200 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
201 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
202 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
203 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
204 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
205 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
206 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
207 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
208 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
209 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
210 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
211 >;
212 };
213
214 davinci_mdio_default: davinci_mdio_default {
215 pinctrl-single,pins = <
216 /* MDIO */
217 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
218 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
219 >;
220 };
221
222 davinci_mdio_sleep: davinci_mdio_sleep {
223 pinctrl-single,pins = <
224 /* MDIO reset value */
225 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
226 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
227 >;
228 };
229
230 qspi_pins_default: qspi_pins_default {
231 pinctrl-single,pins = <
232 0x7c (PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_csn0.qspi_csn */
233 0x88 (PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */
234 0x90 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */
235 0x94 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */
236 0x98 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wen.qspi_d2 */
237 0x9c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */
238 >;
239 };
240
241 qspi_pins_sleep: qspi_pins_sleep{
242 pinctrl-single,pins = <
243 0x7c (PIN_INPUT_PULLDOWN | MUX_MODE7)
244 0x88 (PIN_INPUT_PULLDOWN | MUX_MODE7)
245 0x90 (PIN_INPUT_PULLDOWN | MUX_MODE7)
246 0x94 (PIN_INPUT_PULLDOWN | MUX_MODE7)
247 0x98 (PIN_INPUT_PULLDOWN | MUX_MODE7)
248 0x9c (PIN_INPUT_PULLDOWN | MUX_MODE7)
249 >;
250 };
251};
252
253&i2c0 {
254 status = "okay";
255 pinctrl-names = "default", "sleep";
256 pinctrl-0 = <&i2c0_pins_default>;
257 pinctrl-1 = <&i2c0_pins_default>;
258 clock-frequency = <400000>;
259
260 at24@50 {
261 compatible = "at24,24c256";
262 pagesize = <64>;
263 reg = <0x50>;
264 };
265};
266
267&i2c1 {
268 status = "okay";
269 pinctrl-names = "default", "sleep";
270 pinctrl-0 = <&i2c1_pins_default>;
271 pinctrl-1 = <&i2c1_pins_default>;
272 clock-frequency = <400000>;
273
274 tps: tps62362@60 {
275 compatible = "ti,tps62362";
276 regulator-name = "VDD_MPU";
277 regulator-min-microvolt = <950000>;
278 regulator-max-microvolt = <1330000>;
279 regulator-boot-on;
280 regulator-always-on;
281 ti,vsel0-state-high;
282 ti,vsel1-state-high;
283 vin-supply = <&v3_3d>;
284 };
285};
286
287&epwmss0 {
288 status = "okay";
289};
290
291&ecap0 {
292 status = "okay";
293 pinctrl-names = "default";
294 pinctrl-0 = <&ecap0_pins_default>;
295};
296
297&gpio0 {
298 status = "okay";
299};
300
301&gpio1 {
302 status = "okay";
303};
304
305&gpio4 {
306 status = "okay";
307};
308
309&gpio5 {
310 status = "okay";
311};
312
313&mmc1 {
314 status = "okay";
315 pinctrl-names = "default", "sleep";
316 pinctrl-0 = <&mmc1_pins_default>;
317 pinctrl-1 = <&mmc1_pins_sleep>;
318 vmmc-supply = <&v3_3d>;
319 bus-width = <4>;
320 cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
321};
322
323&qspi {
324 status = "okay";
325 pinctrl-names = "default", "sleep";
326 pinctrl-0 = <&qspi_pins_default>;
327 pinctrl-1 = <&qspi_pins_sleep>;
328
329 spi-max-frequency = <48000000>;
330 m25p80@0 {
331 compatible = "mx66l51235l";
332 spi-max-frequency = <48000000>;
333 reg = <0>;
334 spi-cpol;
335 spi-cpha;
336 spi-tx-bus-width = <1>;
337 spi-rx-bus-width = <4>;
338 #address-cells = <1>;
339 #size-cells = <1>;
340
341 /*
342 * MTD partition table. The ROM checks the first 512KiB for a
343 * valid file to boot(XIP).
344 */
345 partition@0 {
346 label = "QSPI.U_BOOT";
347 reg = <0x00000000 0x000080000>;
348 };
349 partition@1 {
350 label = "QSPI.U_BOOT.backup";
351 reg = <0x00080000 0x00080000>;
352 };
353 partition@2 {
354 label = "QSPI.U-BOOT-SPL_OS";
355 reg = <0x00100000 0x00010000>;
356 };
357 partition@3 {
358 label = "QSPI.U_BOOT_ENV";
359 reg = <0x00110000 0x00010000>;
360 };
361 partition@4 {
362 label = "QSPI.U-BOOT-ENV.backup";
363 reg = <0x00120000 0x00010000>;
364 };
365 partition@5 {
366 label = "QSPI.KERNEL";
367 reg = <0x00130000 0x0800000>;
368 };
369 partition@6 {
370 label = "QSPI.FILESYSTEM";
371 reg = <0x00930000 0x36D0000>;
372 };
373 };
374};
375
376&mac {
377 pinctrl-names = "default", "sleep";
378 pinctrl-0 = <&cpsw_default>;
379 pinctrl-1 = <&cpsw_sleep>;
380 status = "okay";
381};
382
383&davinci_mdio {
384 pinctrl-names = "default", "sleep";
385 pinctrl-0 = <&davinci_mdio_default>;
386 pinctrl-1 = <&davinci_mdio_sleep>;
387 status = "okay";
388};
389
390&cpsw_emac0 {
391 phy_id = <&davinci_mdio>, <0>;
392 phy-mode = "rgmii";
393};
394
395&rtc {
396 status = "okay";
397};
398
399&wdt {
400 status = "okay";
401};
402
403&cpu {
404 cpu0-supply = <&tps>;
405};
diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts
index 53bbfc90b26a..832d24318f62 100644
--- a/arch/arm/boot/dts/am437x-sk-evm.dts
+++ b/arch/arm/boot/dts/am437x-sk-evm.dts
@@ -153,20 +153,26 @@
153 153
154 i2c0_pins: i2c0_pins { 154 i2c0_pins: i2c0_pins {
155 pinctrl-single,pins = < 155 pinctrl-single,pins = <
156 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ 156 0x188 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
157 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ 157 0x18c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
158 >; 158 >;
159 }; 159 };
160 160
161 i2c1_pins: i2c1_pins { 161 i2c1_pins: i2c1_pins {
162 pinctrl-single,pins = < 162 pinctrl-single,pins = <
163 0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */ 163 0x15c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
164 0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */ 164 0x158 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
165 >; 165 >;
166 }; 166 };
167 167
168 mmc1_pins: pinmux_mmc1_pins { 168 mmc1_pins: pinmux_mmc1_pins {
169 pinctrl-single,pins = < 169 pinctrl-single,pins = <
170 0x0f0 (PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
171 0x0f4 (PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
172 0x0f8 (PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
173 0x0fc (PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
174 0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
175 0x104 (PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
170 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ 176 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
171 >; 177 >;
172 }; 178 };
@@ -184,35 +190,75 @@
184 >; 190 >;
185 }; 191 };
186 192
193 vpfe0_pins_default: vpfe0_pins_default {
194 pinctrl-single,pins = <
195 0x1b0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/
196 0x1b4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/
197 0x1b8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_field mode 0*/
198 0x1bc (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_wen mode 0*/
199 0x1c0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/
200 0x1c4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/
201 0x1c8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/
202 0x208 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/
203 0x20c (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/
204 0x210 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/
205 0x214 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/
206 0x218 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/
207 0x21c (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/
208 0x220 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/
209 0x224 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/
210 >;
211 };
212
213 vpfe0_pins_sleep: vpfe0_pins_sleep {
214 pinctrl-single,pins = <
215 0x1b0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
216 0x1b4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
217 0x1b8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
218 0x1bc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
219 0x1c0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
220 0x1c4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
221 0x1c8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
222 0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
223 0x20c (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
224 0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
225 0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
226 0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
227 0x21c (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
228 0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
229 0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
230 >;
231 };
232
187 cpsw_default: cpsw_default { 233 cpsw_default: cpsw_default {
188 pinctrl-single,pins = < 234 pinctrl-single,pins = <
189 /* Slave 1 */ 235 /* Slave 1 */
190 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ 236 0x12c (PIN_OUTPUT | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
191 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ 237 0x114 (PIN_OUTPUT | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
192 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ 238 0x128 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
193 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ 239 0x124 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
194 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */ 240 0x120 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */
195 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */ 241 0x11c (PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */
196 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ 242 0x130 (PIN_INPUT | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
197 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ 243 0x118 (PIN_INPUT | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
198 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ 244 0x140 (PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
199 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ 245 0x13c (PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
200 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */ 246 0x138 (PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */
201 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */ 247 0x134 (PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */
202 248
203 /* Slave 2 */ 249 /* Slave 2 */
204 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ 250 0x58 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
205 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ 251 0x40 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
206 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ 252 0x54 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
207 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ 253 0x50 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
208 0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ 254 0x4c (PIN_OUTPUT | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
209 0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ 255 0x48 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
210 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ 256 0x5c (PIN_INPUT | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
211 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rtcl */ 257 0x44 (PIN_INPUT | MUX_MODE2) /* gpmc_a1.rgmii2_rtcl */
212 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ 258 0x6c (PIN_INPUT | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
213 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ 259 0x68 (PIN_INPUT | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
214 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ 260 0x64 (PIN_INPUT | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
215 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ 261 0x60 (PIN_INPUT | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
216 >; 262 >;
217 }; 263 };
218 264
@@ -251,8 +297,8 @@
251 davinci_mdio_default: davinci_mdio_default { 297 davinci_mdio_default: davinci_mdio_default {
252 pinctrl-single,pins = < 298 pinctrl-single,pins = <
253 /* MDIO */ 299 /* MDIO */
254 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ 300 0x148 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
255 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ 301 0x14c (PIN_OUTPUT | MUX_MODE0) /* mdio_clk.mdio_clk */
256 >; 302 >;
257 }; 303 };
258 304
@@ -266,46 +312,46 @@
266 312
267 dss_pins: dss_pins { 313 dss_pins: dss_pins {
268 pinctrl-single,pins = < 314 pinctrl-single,pins = <
269 0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /* gpmc ad 8 -> DSS DATA 23 */ 315 0x020 (PIN_OUTPUT | MUX_MODE1) /* gpmc ad 8 -> DSS DATA 23 */
270 0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1) 316 0x024 (PIN_OUTPUT | MUX_MODE1)
271 0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1) 317 0x028 (PIN_OUTPUT | MUX_MODE1)
272 0x02c (PIN_OUTPUT_PULLUP | MUX_MODE1) 318 0x02c (PIN_OUTPUT | MUX_MODE1)
273 0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1) 319 0x030 (PIN_OUTPUT | MUX_MODE1)
274 0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1) 320 0x034 (PIN_OUTPUT | MUX_MODE1)
275 0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1) 321 0x038 (PIN_OUTPUT | MUX_MODE1)
276 0x03c (PIN_OUTPUT_PULLUP | MUX_MODE1) /* gpmc ad 15 -> DSS DATA 16 */ 322 0x03c (PIN_OUTPUT | MUX_MODE1) /* gpmc ad 15 -> DSS DATA 16 */
277 0x0a0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ 323 0x0a0 (PIN_OUTPUT | MUX_MODE0) /* DSS DATA 0 */
278 0x0a4 (PIN_OUTPUT_PULLUP | MUX_MODE0) 324 0x0a4 (PIN_OUTPUT | MUX_MODE0)
279 0x0a8 (PIN_OUTPUT_PULLUP | MUX_MODE0) 325 0x0a8 (PIN_OUTPUT | MUX_MODE0)
280 0x0ac (PIN_OUTPUT_PULLUP | MUX_MODE0) 326 0x0ac (PIN_OUTPUT | MUX_MODE0)
281 0x0b0 (PIN_OUTPUT_PULLUP | MUX_MODE0) 327 0x0b0 (PIN_OUTPUT | MUX_MODE0)
282 0x0b4 (PIN_OUTPUT_PULLUP | MUX_MODE0) 328 0x0b4 (PIN_OUTPUT | MUX_MODE0)
283 0x0b8 (PIN_OUTPUT_PULLUP | MUX_MODE0) 329 0x0b8 (PIN_OUTPUT | MUX_MODE0)
284 0x0bc (PIN_OUTPUT_PULLUP | MUX_MODE0) 330 0x0bc (PIN_OUTPUT | MUX_MODE0)
285 0x0c0 (PIN_OUTPUT_PULLUP | MUX_MODE0) 331 0x0c0 (PIN_OUTPUT | MUX_MODE0)
286 0x0c4 (PIN_OUTPUT_PULLUP | MUX_MODE0) 332 0x0c4 (PIN_OUTPUT | MUX_MODE0)
287 0x0c8 (PIN_OUTPUT_PULLUP | MUX_MODE0) 333 0x0c8 (PIN_OUTPUT | MUX_MODE0)
288 0x0cc (PIN_OUTPUT_PULLUP | MUX_MODE0) 334 0x0cc (PIN_OUTPUT | MUX_MODE0)
289 0x0d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) 335 0x0d0 (PIN_OUTPUT | MUX_MODE0)
290 0x0d4 (PIN_OUTPUT_PULLUP | MUX_MODE0) 336 0x0d4 (PIN_OUTPUT | MUX_MODE0)
291 0x0d8 (PIN_OUTPUT_PULLUP | MUX_MODE0) 337 0x0d8 (PIN_OUTPUT | MUX_MODE0)
292 0x0dc (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ 338 0x0dc (PIN_OUTPUT | MUX_MODE0) /* DSS DATA 15 */
293 0x0e0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ 339 0x0e0 (PIN_OUTPUT | MUX_MODE0) /* DSS VSYNC */
294 0x0e4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ 340 0x0e4 (PIN_OUTPUT | MUX_MODE0) /* DSS HSYNC */
295 0x0e8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ 341 0x0e8 (PIN_OUTPUT | MUX_MODE0) /* DSS PCLK */
296 0x0ec (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ 342 0x0ec (PIN_OUTPUT | MUX_MODE0) /* DSS AC BIAS EN */
297 343
298 >; 344 >;
299 }; 345 };
300 346
301 qspi_pins: qspi_pins { 347 qspi_pins: qspi_pins {
302 pinctrl-single,pins = < 348 pinctrl-single,pins = <
303 0x7c (PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_csn0.qspi_csn */ 349 0x7c (PIN_OUTPUT | MUX_MODE3) /* gpmc_csn0.qspi_csn */
304 0x88 (PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */ 350 0x88 (PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */
305 0x90 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */ 351 0x90 (PIN_INPUT | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */
306 0x94 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */ 352 0x94 (PIN_INPUT | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */
307 0x98 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wen.qspi_d2 */ 353 0x98 (PIN_INPUT | MUX_MODE3) /* gpmc_wen.qspi_d2 */
308 0x9c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */ 354 0x9c (PIN_INPUT | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */
309 >; 355 >;
310 }; 356 };
311 357
@@ -323,6 +369,18 @@
323 0x1c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpcm_ad7.gpio1_7 */ 369 0x1c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpcm_ad7.gpio1_7 */
324 >; 370 >;
325 }; 371 };
372
373 usb1_pins: usb1_pins {
374 pinctrl-single,pins = <
375 0x2c0 (PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */
376 >;
377 };
378
379 usb2_pins: usb2_pins {
380 pinctrl-single,pins = <
381 0x2c4 (PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */
382 >;
383 };
326}; 384};
327 385
328&i2c0 { 386&i2c0 {
@@ -386,6 +444,11 @@
386 regulator-always-on; 444 regulator-always-on;
387 }; 445 };
388 446
447 power-button {
448 compatible = "ti,tps65218-pwrbutton";
449 status = "okay";
450 interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
451 };
389 }; 452 };
390 453
391 at24@50 { 454 at24@50 {
@@ -479,6 +542,8 @@
479&usb1 { 542&usb1 {
480 dr_mode = "peripheral"; 543 dr_mode = "peripheral";
481 status = "okay"; 544 status = "okay";
545 pinctrl-names = "default";
546 pinctrl-0 = <&usb1_pins>;
482}; 547};
483 548
484&usb2_phy2 { 549&usb2_phy2 {
@@ -488,6 +553,8 @@
488&usb2 { 553&usb2 {
489 dr_mode = "host"; 554 dr_mode = "host";
490 status = "okay"; 555 status = "okay";
556 pinctrl-names = "default";
557 pinctrl-0 = <&usb2_pins>;
491}; 558};
492 559
493&qspi { 560&qspi {
@@ -610,3 +677,25 @@
610&wdt { 677&wdt {
611 status = "okay"; 678 status = "okay";
612}; 679};
680
681&cpu {
682 cpu0-supply = <&dcdc2>;
683};
684
685&vpfe0 {
686 status = "okay";
687 pinctrl-names = "default", "sleep";
688 pinctrl-0 = <&vpfe0_pins_default>;
689 pinctrl-1 = <&vpfe0_pins_sleep>;
690
691 /* Camera port */
692 port {
693 vpfe0_ep: endpoint {
694 /* remote-endpoint = <&sensor>; add once we have it */
695 ti,am437x-vpfe-interface = <0>;
696 bus-width = <8>;
697 hsync-active = <0>;
698 vsync-active = <0>;
699 };
700 };
701};
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index 662261d6b2ca..257c099c347e 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -243,6 +243,42 @@
243 0x08C (PIN_OUTPUT_PULLUP | MUX_MODE7) 243 0x08C (PIN_OUTPUT_PULLUP | MUX_MODE7)
244 >; 244 >;
245 }; 245 };
246
247 vpfe1_pins_default: vpfe1_pins_default {
248 pinctrl-single,pins = <
249 0x1cc (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0 */
250 0x1d0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0 */
251 0x1d4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0 */
252 0x1d8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0 */
253 0x1dc (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0 */
254 0x1e8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0 */
255 0x1ec (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0 */
256 0x1f0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0 */
257 0x1f4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0 */
258 0x1f8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0 */
259 0x1fc (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0 */
260 0x200 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0 */
261 0x204 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0 */
262 >;
263 };
264
265 vpfe1_pins_sleep: vpfe1_pins_sleep {
266 pinctrl-single,pins = <
267 0x1cc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
268 0x1d0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
269 0x1d4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
270 0x1d8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
271 0x1dc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
272 0x1e8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
273 0x1ec (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
274 0x1f0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
275 0x1f4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
276 0x1f8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
277 0x1fc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
278 0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
279 0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
280 >;
281 };
246 }; 282 };
247 283
248 matrix_keypad: matrix_keypad@0 { 284 matrix_keypad: matrix_keypad@0 {
@@ -634,3 +670,20 @@
634 }; 670 };
635 }; 671 };
636}; 672};
673
674&vpfe1 {
675 status = "okay";
676 pinctrl-names = "default", "sleep";
677 pinctrl-0 = <&vpfe1_pins_default>;
678 pinctrl-1 = <&vpfe1_pins_sleep>;
679
680 port {
681 vpfe1_ep: endpoint {
682 /* remote-endpoint = <&sensor>; add once we have it */
683 ti,am437x-vpfe-interface = <0>;
684 bus-width = <8>;
685 hsync-active = <0>;
686 vsync-active = <0>;
687 };
688 };
689};
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index 49edbda68cd5..03750af3b49a 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -80,6 +80,28 @@
80 default-state = "off"; 80 default-state = "off";
81 }; 81 };
82 }; 82 };
83
84 gpio_fan: gpio_fan {
85 /* Based on 5v 500mA AFB02505HHB */
86 compatible = "gpio-fan";
87 gpios = <&tps659038_gpio 1 GPIO_ACTIVE_HIGH>;
88 gpio-fan,speed-map = <0 0>,
89 <13000 1>;
90 };
91
92 extcon_usb1: extcon_usb1 {
93 compatible = "linux,extcon-usb-gpio";
94 id-gpio = <&gpio7 25 GPIO_ACTIVE_HIGH>;
95 pinctrl-names = "default";
96 pinctrl-0 = <&extcon_usb1_pins>;
97 };
98
99 extcon_usb2: extcon_usb2 {
100 compatible = "linux,extcon-usb-gpio";
101 id-gpio = <&gpio7 24 GPIO_ACTIVE_HIGH>;
102 pinctrl-names = "default";
103 pinctrl-0 = <&extcon_usb2_pins>;
104 };
83}; 105};
84 106
85&dra7_pmx_core { 107&dra7_pmx_core {
@@ -140,6 +162,86 @@
140 >; 162 >;
141 }; 163 };
142 164
165 cpsw_pins_default: cpsw_pins_default {
166 pinctrl-single,pins = <
167 /* Slave 1 */
168 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tclk */
169 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tctl */
170 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td3 */
171 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td2 */
172 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td1 */
173 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td0 */
174 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii1_rclk */
175 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii1_rctl */
176 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd3 */
177 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd2 */
178 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd1 */
179 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii1_rd0 */
180
181 /* Slave 2 */
182 0x198 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tclk */
183 0x19c (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tctl */
184 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td3 */
185 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td2 */
186 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td1 */
187 0x1ac (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td0 */
188 0x1b0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rclk */
189 0x1b4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rctl */
190 0x1b8 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd3 */
191 0x1bc (PIN_INPUT | MUX_MODE3) /* rgmii2_rd2 */
192 0x1c0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd1 */
193 0x1c4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd0 */
194 >;
195
196 };
197
198 cpsw_pins_sleep: cpsw_pins_sleep {
199 pinctrl-single,pins = <
200 /* Slave 1 */
201 0x250 (PIN_INPUT | MUX_MODE15)
202 0x254 (PIN_INPUT | MUX_MODE15)
203 0x258 (PIN_INPUT | MUX_MODE15)
204 0x25c (PIN_INPUT | MUX_MODE15)
205 0x260 (PIN_INPUT | MUX_MODE15)
206 0x264 (PIN_INPUT | MUX_MODE15)
207 0x268 (PIN_INPUT | MUX_MODE15)
208 0x26c (PIN_INPUT | MUX_MODE15)
209 0x270 (PIN_INPUT | MUX_MODE15)
210 0x274 (PIN_INPUT | MUX_MODE15)
211 0x278 (PIN_INPUT | MUX_MODE15)
212 0x27c (PIN_INPUT | MUX_MODE15)
213
214 /* Slave 2 */
215 0x198 (PIN_INPUT | MUX_MODE15)
216 0x19c (PIN_INPUT | MUX_MODE15)
217 0x1a0 (PIN_INPUT | MUX_MODE15)
218 0x1a4 (PIN_INPUT | MUX_MODE15)
219 0x1a8 (PIN_INPUT | MUX_MODE15)
220 0x1ac (PIN_INPUT | MUX_MODE15)
221 0x1b0 (PIN_INPUT | MUX_MODE15)
222 0x1b4 (PIN_INPUT | MUX_MODE15)
223 0x1b8 (PIN_INPUT | MUX_MODE15)
224 0x1bc (PIN_INPUT | MUX_MODE15)
225 0x1c0 (PIN_INPUT | MUX_MODE15)
226 0x1c4 (PIN_INPUT | MUX_MODE15)
227 >;
228 };
229
230 davinci_mdio_pins_default: davinci_mdio_pins_default {
231 pinctrl-single,pins = <
232 /* MDIO */
233 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_mclk */
234 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_d */
235 >;
236 };
237
238 davinci_mdio_pins_sleep: davinci_mdio_pins_sleep {
239 pinctrl-single,pins = <
240 0x23c (PIN_INPUT | MUX_MODE15)
241 0x240 (PIN_INPUT | MUX_MODE15)
242 >;
243 };
244
143 tps659038_pins_default: tps659038_pins_default { 245 tps659038_pins_default: tps659038_pins_default {
144 pinctrl-single,pins = < 246 pinctrl-single,pins = <
145 0x418 (PIN_INPUT_PULLUP | MUX_MODE14) /* wakeup0.gpio1_0 */ 247 0x418 (PIN_INPUT_PULLUP | MUX_MODE14) /* wakeup0.gpio1_0 */
@@ -164,6 +266,17 @@
164 >; 266 >;
165 }; 267 };
166 268
269 extcon_usb1_pins: extcon_usb1_pins {
270 pinctrl-single,pins = <
271 0x3ec (PIN_INPUT_PULLUP | MUX_MODE14) /* uart1_rtsn.gpio7_25 */
272 >;
273 };
274
275 extcon_usb2_pins: extcon_usb2_pins {
276 pinctrl-single,pins = <
277 0x3e8 (PIN_INPUT_PULLUP | MUX_MODE14) /* uart1_ctsn.gpio7_24 */
278 >;
279 };
167}; 280};
168 281
169&i2c1 { 282&i2c1 {
@@ -314,6 +427,12 @@
314 wakeup-source; 427 wakeup-source;
315 ti,palmas-long-press-seconds = <12>; 428 ti,palmas-long-press-seconds = <12>;
316 }; 429 };
430
431 tps659038_gpio: tps659038_gpio {
432 compatible = "ti,palmas-gpio";
433 gpio-controller;
434 #gpio-cells = <2>;
435 };
317 }; 436 };
318 437
319 tmp102: tmp102@48 { 438 tmp102: tmp102@48 {
@@ -365,6 +484,32 @@
365 pinctrl-0 = <&uart3_pins_default>; 484 pinctrl-0 = <&uart3_pins_default>;
366}; 485};
367 486
487&mac {
488 status = "okay";
489 pinctrl-names = "default", "sleep";
490 pinctrl-0 = <&cpsw_pins_default>;
491 pinctrl-1 = <&cpsw_pins_sleep>;
492 dual_emac;
493};
494
495&cpsw_emac0 {
496 phy_id = <&davinci_mdio>, <1>;
497 phy-mode = "rgmii";
498 dual_emac_res_vlan = <1>;
499};
500
501&cpsw_emac1 {
502 phy_id = <&davinci_mdio>, <2>;
503 phy-mode = "rgmii";
504 dual_emac_res_vlan = <2>;
505};
506
507&davinci_mdio {
508 pinctrl-names = "default", "sleep";
509 pinctrl-0 = <&davinci_mdio_pins_default>;
510 pinctrl-1 = <&davinci_mdio_pins_sleep>;
511};
512
368&mmc1 { 513&mmc1 {
369 status = "okay"; 514 status = "okay";
370 515
@@ -403,3 +548,15 @@
403 pinctrl-names = "default"; 548 pinctrl-names = "default";
404 pinctrl-0 = <&usb1_pins>; 549 pinctrl-0 = <&usb1_pins>;
405}; 550};
551
552&omap_dwc3_1 {
553 extcon = <&extcon_usb1>;
554};
555
556&omap_dwc3_2 {
557 extcon = <&extcon_usb2>;
558};
559
560&usb2 {
561 dr_mode = "peripheral";
562};
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index 70b1943a86b1..e993c46bd472 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -8,9 +8,43 @@
8 * Gregory CLEMENT <gregory.clement@free-electrons.com> 8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * 10 *
11 * This file is licensed under the terms of the GNU General Public 11 * This file is dual-licensed: you can use it either under the terms
12 * License version 2. This program is licensed "as is" without any 12 * of the GPL or the X11 license, at your option. Note that this dual
13 * warranty of any kind, whether express or implied. 13 * licensing only applies to this file, and not this project as a
14 * whole.
15 *
16 * a) This file is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of the
19 * License, or (at your option) any later version.
20 *
21 * This file is distributed in the hope that it will be useful
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * Or, alternatively
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
14 */ 48 */
15 49
16/dts-v1/; 50/dts-v1/;
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index e1b0eb6b091f..b10ceb488efe 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -3,9 +3,43 @@
3 * 3 *
4 * Gregory CLEMENT <gregory.clement@free-electrons.com> 4 * Gregory CLEMENT <gregory.clement@free-electrons.com>
5 * 5 *
6 * This file is licensed under the terms of the GNU General Public 6 * This file is dual-licensed: you can use it either under the terms
7 * License version 2. This program is licensed "as is" without any 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * warranty of any kind, whether express or implied. 8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
9 */ 43 */
10 44
11/dts-v1/; 45/dts-v1/;
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
index 1c83b7ce0982..3f8cc3845a5e 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
@@ -3,10 +3,43 @@
3 * 3 *
4 * Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org> 4 * Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org>
5 * 5 *
6 * This program is free software; you can redistribute it and/or 6 * This file is dual-licensed: you can use it either under the terms
7 * modify it under the terms of the GNU General Public License 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * as published by the Free Software Foundation; either version 8 * licensing only applies to this file, and not this project as a
9 * 2 of the License, or (at your option) any later version. 9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
10 */ 43 */
11 44
12/dts-v1/; 45/dts-v1/;
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
index 5fbfe02964dc..99eb8a014ac6 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
@@ -3,10 +3,43 @@
3 * 3 *
4 * Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org> 4 * Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org>
5 * 5 *
6 * This program is free software; you can redistribute it and/or 6 * This file is dual-licensed: you can use it either under the terms
7 * modify it under the terms of the GNU General Public License 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * as published by the Free Software Foundation; either version 8 * licensing only applies to this file, and not this project as a
9 * 2 of the License, or (at your option) any later version. 9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
10 */ 43 */
11 44
12/dts-v1/; 45/dts-v1/;
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index 394308951ed9..6ae36a38beb2 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -6,9 +6,43 @@
6 * 6 *
7 * Copyright (C) 2013 Florian Fainelli <florian@openwrt.org> 7 * Copyright (C) 2013 Florian Fainelli <florian@openwrt.org>
8 * 8 *
9 * This file is licensed under the terms of the GNU General Public 9 * This file is dual-licensed: you can use it either under the terms
10 * License version 2. This program is licensed "as is" without any 10 * of the GPL or the X11 license, at your option. Note that this dual
11 * warranty of any kind, whether express or implied. 11 * licensing only applies to this file, and not this project as a
12 * whole.
13 *
14 * a) This file is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of the
17 * License, or (at your option) any later version.
18 *
19 * This file is distributed in the hope that it will be useful
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * Or, alternatively
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
12 * 46 *
13 * Note: this Device Tree assumes that the bootloader has remapped the 47 * Note: this Device Tree assumes that the bootloader has remapped the
14 * internal registers to 0xf1000000 (instead of the default 48 * internal registers to 0xf1000000 (instead of the default
diff --git a/arch/arm/boot/dts/armada-370-synology-ds213j.dts b/arch/arm/boot/dts/armada-370-synology-ds213j.dts
index 70fecde76ccb..59f74e66963f 100644
--- a/arch/arm/boot/dts/armada-370-synology-ds213j.dts
+++ b/arch/arm/boot/dts/armada-370-synology-ds213j.dts
@@ -3,10 +3,43 @@
3 * 3 *
4 * Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org> 4 * Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org>
5 * 5 *
6 * This program is free software; you can redistribute it and/or 6 * This file is dual-licensed: you can use it either under the terms
7 * modify it under the terms of the GNU General Public License 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * as published by the Free Software Foundation; either version 8 * licensing only applies to this file, and not this project as a
9 * 2 of the License, or (at your option) any later version. 9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
10 * 43 *
11 * Note: this Device Tree assumes that the bootloader has remapped the 44 * Note: this Device Tree assumes that the bootloader has remapped the
12 * internal registers to 0xf1000000 (instead of the old 0xd0000000). 45 * internal registers to 0xf1000000 (instead of the old 0xd0000000).
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 1af428602748..8a322ad57e5f 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -8,9 +8,43 @@
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk> 9 * Ben Dooks <ben.dooks@codethink.co.uk>
10 * 10 *
11 * This file is licensed under the terms of the GNU General Public 11 * This file is dual-licensed: you can use it either under the terms
12 * License version 2. This program is licensed "as is" without any 12 * of the GPL or the X11 license, at your option. Note that this dual
13 * warranty of any kind, whether express or implied. 13 * licensing only applies to this file, and not this project as a
14 * whole.
15 *
16 * a) This file is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of the
19 * License, or (at your option) any later version.
20 *
21 * This file is distributed in the hope that it will be useful
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * Or, alternatively
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
14 * 48 *
15 * This file contains the definitions that are common to the Armada 49 * This file contains the definitions that are common to the Armada
16 * 370 and Armada XP SoC. 50 * 370 and Armada XP SoC.
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index fdb3c12a6139..27397f151def 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -7,9 +7,43 @@
7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * 9 *
10 * This file is licensed under the terms of the GNU General Public 10 * This file is dual-licensed: you can use it either under the terms
11 * License version 2. This program is licensed "as is" without any 11 * of the GPL or the X11 license, at your option. Note that this dual
12 * warranty of any kind, whether express or implied. 12 * licensing only applies to this file, and not this project as a
13 * whole.
14 *
15 * a) This file is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of the
18 * License, or (at your option) any later version.
19 *
20 * This file is distributed in the hope that it will be useful
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * Or, alternatively
26 *
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
34 * conditions:
35 *
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
38 *
39 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 * OTHER DEALINGS IN THE SOFTWARE.
13 * 47 *
14 * Contains definitions specific to the Armada 370 SoC that are not 48 * Contains definitions specific to the Armada 370 SoC that are not
15 * common to all Armada SoCs. 49 * common to all Armada SoCs.
diff --git a/arch/arm/boot/dts/armada-375-db.dts b/arch/arm/boot/dts/armada-375-db.dts
index 929ae00b4063..0440891425c0 100644
--- a/arch/arm/boot/dts/armada-375-db.dts
+++ b/arch/arm/boot/dts/armada-375-db.dts
@@ -7,9 +7,43 @@
7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * 9 *
10 * This file is licensed under the terms of the GNU General Public 10 * This file is dual-licensed: you can use it either under the terms
11 * License version 2. This program is licensed "as is" without any 11 * of the GPL or the X11 license, at your option. Note that this dual
12 * warranty of any kind, whether express or implied. 12 * licensing only applies to this file, and not this project as a
13 * whole.
14 *
15 * a) This file is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of the
18 * License, or (at your option) any later version.
19 *
20 * This file is distributed in the hope that it will be useful
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * Or, alternatively
26 *
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
34 * conditions:
35 *
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
38 *
39 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 * OTHER DEALINGS IN THE SOFTWARE.
13 */ 47 */
14 48
15/dts-v1/; 49/dts-v1/;
diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi
index 50096d3427eb..ba3c57e0af72 100644
--- a/arch/arm/boot/dts/armada-375.dtsi
+++ b/arch/arm/boot/dts/armada-375.dtsi
@@ -6,9 +6,43 @@
6 * Gregory CLEMENT <gregory.clement@free-electrons.com> 6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 * 8 *
9 * This file is licensed under the terms of the GNU General Public 9 * This file is dual-licensed: you can use it either under the terms
10 * License version 2. This program is licensed "as is" without any 10 * of the GPL or the X11 license, at your option. Note that this dual
11 * warranty of any kind, whether express or implied. 11 * licensing only applies to this file, and not this project as a
12 * whole.
13 *
14 * a) This file is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of the
17 * License, or (at your option) any later version.
18 *
19 * This file is distributed in the hope that it will be useful
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * Or, alternatively
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
12 */ 46 */
13 47
14#include "skeleton.dtsi" 48#include "skeleton.dtsi"
@@ -63,7 +97,7 @@
63 }; 97 };
64 98
65 soc { 99 soc {
66 compatible = "marvell,armada375-mbus", "marvell,armada370-mbus", "simple-bus"; 100 compatible = "marvell,armada375-mbus", "simple-bus";
67 #address-cells = <2>; 101 #address-cells = <2>;
68 #size-cells = <1>; 102 #size-cells = <1>;
69 controller = <&mbusc>; 103 controller = <&mbusc>;
diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi
index 4173a8ab34e7..5102d19cc8f4 100644
--- a/arch/arm/boot/dts/armada-380.dtsi
+++ b/arch/arm/boot/dts/armada-380.dtsi
@@ -7,9 +7,43 @@
7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * 9 *
10 * This file is licensed under the terms of the GNU General Public 10 * This file is dual-licensed: you can use it either under the terms
11 * License version 2. This program is licensed "as is" without any 11 * of the GPL or the X11 license, at your option. Note that this dual
12 * warranty of any kind, whether express or implied. 12 * licensing only applies to this file, and not this project as a
13 * whole.
14 *
15 * a) This file is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of the
18 * License, or (at your option) any later version.
19 *
20 * This file is distributed in the hope that it will be useful
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * Or, alternatively
26 *
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
34 * conditions:
35 *
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
38 *
39 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 * OTHER DEALINGS IN THE SOFTWARE.
13 */ 47 */
14 48
15#include "armada-38x.dtsi" 49#include "armada-38x.dtsi"
@@ -32,9 +66,8 @@
32 66
33 soc { 67 soc {
34 internal-regs { 68 internal-regs {
35 pinctrl { 69 pinctrl@18000 {
36 compatible = "marvell,mv88f6810-pinctrl"; 70 compatible = "marvell,mv88f6810-pinctrl";
37 reg = <0x18000 0x20>;
38 }; 71 };
39 }; 72 };
40 73
diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts b/arch/arm/boot/dts/armada-385-db-ap.dts
new file mode 100644
index 000000000000..57b9119fb3e0
--- /dev/null
+++ b/arch/arm/boot/dts/armada-385-db-ap.dts
@@ -0,0 +1,178 @@
1/*
2 * Device Tree file for Marvell Armada 385 Access Point Development board
3 * (DB-88F6820-AP)
4 *
5 * Copyright (C) 2014 Marvell
6 *
7 * Nadav Haklai <nadavh@marvell.com>
8 *
9 * This file is dual-licensed: you can use it either under the terms
10 * of the GPL or the X11 license, at your option. Note that this dual
11 * licensing only applies to this file, and not this project as a
12 * whole.
13 *
14 * a) This file is licensed under the terms of the GNU General Public
15 * License version 2. This program is licensed "as is" without
16 * any warranty of any kind, whether express or implied.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42/dts-v1/;
43#include "armada-385.dtsi"
44
45#include <dt-bindings/gpio/gpio.h>
46
47/ {
48 model = "Marvell Armada 385 Access Point Development Board";
49 compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada38x";
50
51 chosen {
52 bootargs = "console=ttyS0,115200";
53 stdout-path = &uart1;
54 };
55
56 memory {
57 device_type = "memory";
58 reg = <0x00000000 0x80000000>; /* 2GB */
59 };
60
61 soc {
62 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
63 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
64
65 internal-regs {
66 spi1: spi@10680 {
67 pinctrl-names = "default";
68 pinctrl-0 = <&spi1_pins>;
69 status = "okay";
70
71 spi-flash@0 {
72 #address-cells = <1>;
73 #size-cells = <1>;
74 compatible = "st,m25p128";
75 reg = <0>; /* Chip select 0 */
76 spi-max-frequency = <54000000>;
77 };
78 };
79
80 i2c0: i2c@11000 {
81 pinctrl-names = "default";
82 pinctrl-0 = <&i2c0_pins>;
83 status = "okay";
84
85 /*
86 * This bus is wired to two EEPROM
87 * sockets, one of which holding the
88 * board ID used by the bootloader.
89 * Erasing this EEPROM's content will
90 * brick the board.
91 * Use this bus with caution.
92 */
93 };
94
95 mdio@72004 {
96 pinctrl-names = "default";
97 pinctrl-0 = <&mdio_pins>;
98
99 phy0: ethernet-phy@1 {
100 reg = <1>;
101 };
102
103 phy1: ethernet-phy@4 {
104 reg = <4>;
105 };
106
107 phy2: ethernet-phy@6 {
108 reg = <6>;
109 };
110 };
111
112 /* UART0 is exposed through the JP8 connector */
113 uart0: serial@12000 {
114 pinctrl-names = "default";
115 pinctrl-0 = <&uart0_pins>;
116 status = "okay";
117 };
118
119 /*
120 * UART1 is exposed through a FTDI chip
121 * wired to the mini-USB connector
122 */
123 uart1: serial@12100 {
124 pinctrl-names = "default";
125 pinctrl-0 = <&uart1_pins>;
126 status = "okay";
127 };
128
129 ethernet@30000 {
130 status = "okay";
131 phy = <&phy2>;
132 phy-mode = "sgmii";
133 };
134
135 ethernet@34000 {
136 status = "okay";
137 phy = <&phy1>;
138 phy-mode = "sgmii";
139 };
140
141 ethernet@70000 {
142 pinctrl-names = "default";
143
144 /*
145 * The Reference Clock 0 is used to
146 * provide a clock to the PHY
147 */
148 pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
149 status = "okay";
150 phy = <&phy0>;
151 phy-mode = "rgmii-id";
152 };
153 };
154
155 pcie-controller {
156 status = "okay";
157
158 /*
159 * The three PCIe units are accessible through
160 * standard mini-PCIe slots on the board.
161 */
162 pcie@1,0 {
163 /* Port 0, Lane 0 */
164 status = "okay";
165 };
166
167 pcie@2,0 {
168 /* Port 1, Lane 0 */
169 status = "okay";
170 };
171
172 pcie@3,0 {
173 /* Port 2, Lane 0 */
174 status = "okay";
175 };
176 };
177 };
178};
diff --git a/arch/arm/boot/dts/armada-385-rd.dts b/arch/arm/boot/dts/armada-385-rd.dts
deleted file mode 100644
index aaca2861dc87..000000000000
--- a/arch/arm/boot/dts/armada-385-rd.dts
+++ /dev/null
@@ -1,97 +0,0 @@
1/*
2 * Device Tree file for Marvell Armada 385 Reference Design board
3 * (RD-88F6820-AP)
4 *
5 * Copyright (C) 2014 Marvell
6 *
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15/dts-v1/;
16#include "armada-385.dtsi"
17
18/ {
19 model = "Marvell Armada 385 Reference Design";
20 compatible = "marvell,a385-rd", "marvell,armada385", "marvell,armada380";
21
22 chosen {
23 bootargs = "console=ttyS0,115200 earlyprintk";
24 };
25
26 memory {
27 device_type = "memory";
28 reg = <0x00000000 0x10000000>; /* 256 MB */
29 };
30
31 soc {
32 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
33 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
34
35 internal-regs {
36 spi@10600 {
37 status = "okay";
38
39 spi-flash@0 {
40 #address-cells = <1>;
41 #size-cells = <1>;
42 compatible = "st,m25p128";
43 reg = <0>; /* Chip select 0 */
44 spi-max-frequency = <108000000>;
45 };
46 };
47
48 i2c@11000 {
49 status = "okay";
50 clock-frequency = <100000>;
51 };
52
53 serial@12000 {
54 status = "okay";
55 };
56
57 ethernet@30000 {
58 status = "okay";
59 phy = <&phy0>;
60 phy-mode = "rgmii-id";
61 };
62
63 ethernet@70000 {
64 status = "okay";
65 phy = <&phy1>;
66 phy-mode = "rgmii-id";
67 };
68
69
70 mdio {
71 phy0: ethernet-phy@0 {
72 reg = <0>;
73 };
74
75 phy1: ethernet-phy@1 {
76 reg = <1>;
77 };
78 };
79
80 usb3@f0000 {
81 status = "okay";
82 };
83 };
84
85 pcie-controller {
86 status = "okay";
87 /*
88 * One PCIe units is accessible through
89 * standard PCIe slot on the board.
90 */
91 pcie@1,0 {
92 /* Port 0, Lane 0 */
93 status = "okay";
94 };
95 };
96 };
97};
diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi
index 6283d7912f71..8e67d2c083dd 100644
--- a/arch/arm/boot/dts/armada-385.dtsi
+++ b/arch/arm/boot/dts/armada-385.dtsi
@@ -7,9 +7,43 @@
7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * 9 *
10 * This file is licensed under the terms of the GNU General Public 10 * This file is dual-licensed: you can use it either under the terms
11 * License version 2. This program is licensed "as is" without any 11 * of the GPL or the X11 license, at your option. Note that this dual
12 * warranty of any kind, whether express or implied. 12 * licensing only applies to this file, and not this project as a
13 * whole.
14 *
15 * a) This file is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of the
18 * License, or (at your option) any later version.
19 *
20 * This file is distributed in the hope that it will be useful
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * Or, alternatively
26 *
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
34 * conditions:
35 *
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
38 *
39 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 * OTHER DEALINGS IN THE SOFTWARE.
13 */ 47 */
14 48
15#include "armada-38x.dtsi" 49#include "armada-38x.dtsi"
@@ -37,9 +71,8 @@
37 71
38 soc { 72 soc {
39 internal-regs { 73 internal-regs {
40 pinctrl { 74 pinctrl@18000 {
41 compatible = "marvell,mv88f6820-pinctrl"; 75 compatible = "marvell,mv88f6820-pinctrl";
42 reg = <0x18000 0x20>;
43 }; 76 };
44 }; 77 };
45 78
diff --git a/arch/arm/boot/dts/armada-385-db.dts b/arch/arm/boot/dts/armada-388-db.dts
index 2aaa9d2ac284..16512efcd32c 100644
--- a/arch/arm/boot/dts/armada-385-db.dts
+++ b/arch/arm/boot/dts/armada-388-db.dts
@@ -1,22 +1,57 @@
1/* 1/*
2 * Device Tree file for Marvell Armada 385 evaluation board 2 * Device Tree file for Marvell Armada 388 evaluation board
3 * (DB-88F6820) 3 * (DB-88F6820)
4 * 4 *
5 * Copyright (C) 2014 Marvell 5 * Copyright (C) 2014 Marvell
6 * 6 *
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 * 8 *
9 * This file is licensed under the terms of the GNU General Public 9 * This file is dual-licensed: you can use it either under the terms
10 * License version 2. This program is licensed "as is" without any 10 * of the GPL or the X11 license, at your option. Note that this dual
11 * warranty of any kind, whether express or implied. 11 * licensing only applies to this file, and not this project as a
12 * whole.
13 *
14 * a) This file is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of the
17 * License, or (at your option) any later version.
18 *
19 * This file is distributed in the hope that it will be useful
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * Or, alternatively
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
12 */ 46 */
13 47
14/dts-v1/; 48/dts-v1/;
15#include "armada-385.dtsi" 49#include "armada-388.dtsi"
16 50
17/ { 51/ {
18 model = "Marvell Armada 385 Development Board"; 52 model = "Marvell Armada 385 Development Board";
19 compatible = "marvell,a385-db", "marvell,armada385", "marvell,armada380"; 53 compatible = "marvell,a385-db", "marvell,armada388",
54 "marvell,armada385", "marvell,armada380";
20 55
21 chosen { 56 chosen {
22 bootargs = "console=ttyS0,115200 earlyprintk"; 57 bootargs = "console=ttyS0,115200 earlyprintk";
@@ -74,7 +109,7 @@
74 phy-mode = "rgmii-id"; 109 phy-mode = "rgmii-id";
75 }; 110 };
76 111
77 mdio { 112 mdio@72004 {
78 phy0: ethernet-phy@0 { 113 phy0: ethernet-phy@0 {
79 reg = <0>; 114 reg = <0>;
80 }; 115 };
diff --git a/arch/arm/boot/dts/armada-388-gp.dts b/arch/arm/boot/dts/armada-388-gp.dts
new file mode 100644
index 000000000000..590b383db323
--- /dev/null
+++ b/arch/arm/boot/dts/armada-388-gp.dts
@@ -0,0 +1,414 @@
1/*
2 * Device Tree file for Marvell Armada 385 development board
3 * (RD-88F6820-GP)
4 *
5 * Copyright (C) 2014 Marvell
6 *
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 *
9 * This file is dual-licensed: you can use it either under the terms
10 * of the GPL or the X11 license, at your option. Note that this dual
11 * licensing only applies to this file, and not this project as a
12 * whole.
13 *
14 * a) This file is licensed under the terms of the GNU General Public
15 * License version 2. This program is licensed "as is" without
16 * any warranty of any kind, whether express or implied.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42/dts-v1/;
43#include "armada-388.dtsi"
44#include <dt-bindings/gpio/gpio.h>
45
46/ {
47 model = "Marvell Armada 385 GP";
48 compatible = "marvell,a385-gp", "marvell,armada388", "marvell,armada380";
49
50 chosen {
51 bootargs = "console=ttyS0,115200";
52 stdout-path = &uart0;
53 };
54
55 memory {
56 device_type = "memory";
57 reg = <0x00000000 0x80000000>; /* 2 GB */
58 };
59
60 soc {
61 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
62 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
63
64 internal-regs {
65 spi@10600 {
66 pinctrl-names = "default";
67 pinctrl-0 = <&spi0_pins>;
68 status = "okay";
69
70 spi-flash@0 {
71 #address-cells = <1>;
72 #size-cells = <1>;
73 compatible = "st,m25p128";
74 reg = <0>; /* Chip select 0 */
75 spi-max-frequency = <50000000>;
76 m25p,fast-read;
77 };
78 };
79
80 i2c@11000 {
81 pinctrl-names = "default";
82 pinctrl-0 = <&i2c0_pins>;
83 status = "okay";
84 clock-frequency = <100000>;
85 /*
86 * The EEPROM located at adresse 54 is needed
87 * for the boot - DO NOT ERASE IT -
88 */
89
90 expander0: pca9555@20 {
91 compatible = "nxp,pca9555";
92 pinctrl-names = "default";
93 pinctrl-0 = <&pca0_pins>;
94 interrupt-parent = <&gpio0>;
95 interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
96 gpio-controller;
97 #gpio-cells = <2>;
98 interrupt-controller;
99 #interrupt-cells = <2>;
100 reg = <0x20>;
101 };
102
103 expander1: pca9555@21 {
104 compatible = "nxp,pca9555";
105 pinctrl-names = "default";
106 interrupt-parent = <&gpio0>;
107 interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
108 gpio-controller;
109 #gpio-cells = <2>;
110 interrupt-controller;
111 #interrupt-cells = <2>;
112 reg = <0x21>;
113 };
114
115 };
116
117 serial@12000 {
118 /*
119 * Exported on the micro USB connector CON16
120 * through an FTDI
121 */
122
123 pinctrl-names = "default";
124 pinctrl-0 = <&uart0_pins>;
125 status = "okay";
126 };
127
128 /* GE1 CON15 */
129 ethernet@30000 {
130 pinctrl-names = "default";
131 pinctrl-0 = <&ge1_rgmii_pins>;
132 status = "okay";
133 phy = <&phy1>;
134 phy-mode = "rgmii-id";
135 };
136
137 /* CON4 */
138 usb@50000 {
139 vcc-supply = <&reg_usb2_0_vbus>;
140 status = "okay";
141 };
142
143 /* GE0 CON1 */
144 ethernet@70000 {
145 pinctrl-names = "default";
146 /*
147 * The Reference Clock 0 is used to provide a
148 * clock to the PHY
149 */
150 pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
151 status = "okay";
152 phy = <&phy0>;
153 phy-mode = "rgmii-id";
154 };
155
156
157 mdio@72004 {
158 pinctrl-names = "default";
159 pinctrl-0 = <&mdio_pins>;
160
161 phy0: ethernet-phy@1 {
162 reg = <1>;
163 };
164
165 phy1: ethernet-phy@0 {
166 reg = <0>;
167 };
168 };
169
170 sata@a8000 {
171 pinctrl-names = "default";
172 pinctrl-0 = <&sata0_pins>, <&sata1_pins>;
173 status = "okay";
174 #address-cells = <1>;
175 #size-cells = <0>;
176
177 sata0: sata-port@0 {
178 reg = <0>;
179 target-supply = <&reg_5v_sata0>;
180 };
181
182 sata1: sata-port@1 {
183 reg = <1>;
184 target-supply = <&reg_5v_sata1>;
185 };
186 };
187
188 sata@e0000 {
189 pinctrl-names = "default";
190 pinctrl-0 = <&sata2_pins>, <&sata3_pins>;
191 status = "okay";
192 #address-cells = <1>;
193 #size-cells = <0>;
194
195 sata2: sata-port@0 {
196 reg = <0>;
197 target-supply = <&reg_5v_sata2>;
198 };
199
200 sata3: sata-port@1 {
201 reg = <1>;
202 target-supply = <&reg_5v_sata3>;
203 };
204 };
205
206 sdhci@d8000 {
207 pinctrl-names = "default";
208 pinctrl-0 = <&sdhci_pins>;
209 cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;
210 no-1-8-v;
211 wp-inverted;
212 bus-width = <8>;
213 status = "okay";
214 };
215
216 /* CON5 */
217 usb3@f0000 {
218 vcc-supply = <&reg_usb2_1_vbus>;
219 status = "okay";
220 };
221
222 /* CON7 */
223 usb3@f8000 {
224 vcc-supply = <&reg_usb3_vbus>;
225 status = "okay";
226 };
227 };
228
229 pcie-controller {
230 status = "okay";
231 /*
232 * One PCIe units is accessible through
233 * standard PCIe slot on the board.
234 */
235 pcie@1,0 {
236 /* Port 0, Lane 0 */
237 status = "okay";
238 };
239
240 /*
241 * The two other PCIe units are accessible
242 * through mini PCIe slot on the board.
243 */
244 pcie@2,0 {
245 /* Port 1, Lane 0 */
246 status = "okay";
247 };
248 pcie@3,0 {
249 /* Port 2, Lane 0 */
250 status = "okay";
251 };
252 };
253
254 gpio-fan {
255 compatible = "gpio-fan";
256 gpios = <&expander1 3 GPIO_ACTIVE_HIGH>;
257 gpio-fan,speed-map = < 0 0
258 3000 1>;
259 };
260 };
261
262 reg_usb3_vbus: usb3-vbus {
263 compatible = "regulator-fixed";
264 regulator-name = "usb3-vbus";
265 regulator-min-microvolt = <5000000>;
266 regulator-max-microvolt = <5000000>;
267 enable-active-high;
268 regulator-always-on;
269 gpio = <&expander1 15 GPIO_ACTIVE_HIGH>;
270 };
271
272 reg_usb2_0_vbus: v5-vbus0 {
273 compatible = "regulator-fixed";
274 regulator-name = "v5.0-vbus0";
275 regulator-min-microvolt = <5000000>;
276 regulator-max-microvolt = <5000000>;
277 enable-active-high;
278 regulator-always-on;
279 gpio = <&expander1 14 GPIO_ACTIVE_HIGH>;
280 };
281
282 reg_usb2_1_vbus: v5-vbus1 {
283 compatible = "regulator-fixed";
284 regulator-name = "v5.0-vbus1";
285 regulator-min-microvolt = <5000000>;
286 regulator-max-microvolt = <5000000>;
287 enable-active-high;
288 regulator-always-on;
289 gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
290 };
291
292 reg_usb2_1_vbus: v5-vbus1 {
293 compatible = "regulator-fixed";
294 regulator-name = "v5.0-vbus1";
295 regulator-min-microvolt = <5000000>;
296 regulator-max-microvolt = <5000000>;
297 enable-active-high;
298 regulator-always-on;
299 gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
300 };
301
302 reg_sata0: pwr-sata0 {
303 compatible = "regulator-fixed";
304 regulator-name = "pwr_en_sata0";
305 enable-active-high;
306 regulator-always-on;
307
308 };
309
310 reg_5v_sata0: v5-sata0 {
311 compatible = "regulator-fixed";
312 regulator-name = "v5.0-sata0";
313 regulator-min-microvolt = <5000000>;
314 regulator-max-microvolt = <5000000>;
315 regulator-always-on;
316 vin-supply = <&reg_sata0>;
317 };
318
319 reg_12v_sata0: v12-sata0 {
320 compatible = "regulator-fixed";
321 regulator-name = "v12.0-sata0";
322 regulator-min-microvolt = <12000000>;
323 regulator-max-microvolt = <12000000>;
324 regulator-always-on;
325 vin-supply = <&reg_sata0>;
326 };
327
328 reg_sata1: pwr-sata1 {
329 regulator-name = "pwr_en_sata1";
330 compatible = "regulator-fixed";
331 regulator-min-microvolt = <12000000>;
332 regulator-max-microvolt = <12000000>;
333 enable-active-high;
334 regulator-always-on;
335 gpio = <&expander0 3 GPIO_ACTIVE_HIGH>;
336 };
337
338 reg_5v_sata1: v5-sata1 {
339 compatible = "regulator-fixed";
340 regulator-name = "v5.0-sata1";
341 regulator-min-microvolt = <5000000>;
342 regulator-max-microvolt = <5000000>;
343 regulator-always-on;
344 vin-supply = <&reg_sata1>;
345 };
346
347 reg_12v_sata1: v12-sata1 {
348 compatible = "regulator-fixed";
349 regulator-name = "v12.0-sata1";
350 regulator-min-microvolt = <12000000>;
351 regulator-max-microvolt = <12000000>;
352 regulator-always-on;
353 vin-supply = <&reg_sata1>;
354 };
355
356 reg_sata2: pwr-sata2 {
357 compatible = "regulator-fixed";
358 regulator-name = "pwr_en_sata2";
359 enable-active-high;
360 regulator-always-on;
361 gpio = <&expander0 11 GPIO_ACTIVE_HIGH>;
362 };
363
364 reg_5v_sata2: v5-sata2 {
365 compatible = "regulator-fixed";
366 regulator-name = "v5.0-sata2";
367 regulator-min-microvolt = <5000000>;
368 regulator-max-microvolt = <5000000>;
369 regulator-always-on;
370 vin-supply = <&reg_sata2>;
371 };
372
373 reg_12v_sata2: v12-sata2 {
374 compatible = "regulator-fixed";
375 regulator-name = "v12.0-sata2";
376 regulator-min-microvolt = <12000000>;
377 regulator-max-microvolt = <12000000>;
378 regulator-always-on;
379 vin-supply = <&reg_sata2>;
380 };
381
382 reg_sata3: pwr-sata3 {
383 compatible = "regulator-fixed";
384 regulator-name = "pwr_en_sata3";
385 enable-active-high;
386 regulator-always-on;
387 gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
388 };
389
390 reg_5v_sata3: v5-sata3 {
391 compatible = "regulator-fixed";
392 regulator-name = "v5.0-sata3";
393 regulator-min-microvolt = <5000000>;
394 regulator-max-microvolt = <5000000>;
395 regulator-always-on;
396 vin-supply = <&reg_sata3>;
397 };
398
399 reg_12v_sata3: v12-sata3 {
400 compatible = "regulator-fixed";
401 regulator-name = "v12.0-sata3";
402 regulator-min-microvolt = <12000000>;
403 regulator-max-microvolt = <12000000>;
404 regulator-always-on;
405 vin-supply = <&reg_sata3>;
406 };
407};
408
409&pinctrl {
410 pca0_pins: pca0_pins {
411 marvell,pins = "mpp18";
412 marvell,function = "gpio";
413 };
414};
diff --git a/arch/arm/boot/dts/armada-388-rd.dts b/arch/arm/boot/dts/armada-388-rd.dts
new file mode 100644
index 000000000000..d99baac72081
--- /dev/null
+++ b/arch/arm/boot/dts/armada-388-rd.dts
@@ -0,0 +1,132 @@
1/*
2 * Device Tree file for Marvell Armada 388 Reference Design board
3 * (RD-88F6820-AP)
4 *
5 * Copyright (C) 2014 Marvell
6 *
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 *
10 * This file is dual-licensed: you can use it either under the terms
11 * of the GPL or the X11 license, at your option. Note that this dual
12 * licensing only applies to this file, and not this project as a
13 * whole.
14 *
15 * a) This file is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of the
18 * License, or (at your option) any later version.
19 *
20 * This file is distributed in the hope that it will be useful
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * Or, alternatively
26 *
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
34 * conditions:
35 *
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
38 *
39 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 * OTHER DEALINGS IN THE SOFTWARE.
47 */
48
49/dts-v1/;
50#include "armada-388.dtsi"
51
52/ {
53 model = "Marvell Armada 385 Reference Design";
54 compatible = "marvell,a385-rd", "marvell,armada388",
55 "marvell,armada385","marvell,armada380";
56
57 chosen {
58 bootargs = "console=ttyS0,115200 earlyprintk";
59 };
60
61 memory {
62 device_type = "memory";
63 reg = <0x00000000 0x10000000>; /* 256 MB */
64 };
65
66 soc {
67 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
68 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
69
70 internal-regs {
71 spi@10600 {
72 status = "okay";
73
74 spi-flash@0 {
75 #address-cells = <1>;
76 #size-cells = <1>;
77 compatible = "st,m25p128";
78 reg = <0>; /* Chip select 0 */
79 spi-max-frequency = <108000000>;
80 };
81 };
82
83 i2c@11000 {
84 status = "okay";
85 clock-frequency = <100000>;
86 };
87
88 serial@12000 {
89 status = "okay";
90 };
91
92 ethernet@30000 {
93 status = "okay";
94 phy = <&phy0>;
95 phy-mode = "rgmii-id";
96 };
97
98 ethernet@70000 {
99 status = "okay";
100 phy = <&phy1>;
101 phy-mode = "rgmii-id";
102 };
103
104
105 mdio@72004 {
106 phy0: ethernet-phy@0 {
107 reg = <0>;
108 };
109
110 phy1: ethernet-phy@1 {
111 reg = <1>;
112 };
113 };
114
115 usb3@f0000 {
116 status = "okay";
117 };
118 };
119
120 pcie-controller {
121 status = "okay";
122 /*
123 * One PCIe units is accessible through
124 * standard PCIe slot on the board.
125 */
126 pcie@1,0 {
127 /* Port 0, Lane 0 */
128 status = "okay";
129 };
130 };
131 };
132};
diff --git a/arch/arm/boot/dts/armada-388.dtsi b/arch/arm/boot/dts/armada-388.dtsi
new file mode 100644
index 000000000000..564fa5937e25
--- /dev/null
+++ b/arch/arm/boot/dts/armada-388.dtsi
@@ -0,0 +1,70 @@
1/*
2 * Device Tree Include file for Marvell Armada 388 SoC.
3 *
4 * Copyright (C) 2015 Marvell
5 *
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 *
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPL or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This file is licensed under the terms of the GNU General Public
14 * License version 2. This program is licensed "as is" without
15 * any warranty of any kind, whether express or implied.
16 *
17 * Or, alternatively,
18 *
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
26 * conditions:
27 *
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
30 *
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
39 *
40 *
41 * The main difference with the Armada 385 is that the 388 can handle two more
42 * SATA ports. So we can reuse the dtsi of the Armada 385, override the pinctrl
43 * property and the name of the SoC, and add the second SATA host which control
44 * the 2 other ports.
45 */
46
47#include "armada-385.dtsi"
48
49/ {
50 model = "Marvell Armada 388 family SoC";
51 compatible = "marvell,armada388", "marvell,armada385",
52 "marvell,armada380";
53
54 soc {
55 internal-regs {
56 pinctrl@18000 {
57 compatible = "marvell,mv88f6828-pinctrl";
58 };
59
60 sata@e0000 {
61 compatible = "marvell,armada-380-ahci";
62 reg = <0xe0000 0x2000>;
63 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
64 clocks = <&gateclk 30>;
65 status = "disabled";
66 };
67
68 };
69 };
70};
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index 2a9f4caac643..1dff30a81e24 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -7,9 +7,43 @@
7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * 9 *
10 * This file is licensed under the terms of the GNU General Public 10 * This file is dual-licensed: you can use it either under the terms
11 * License version 2. This program is licensed "as is" without any 11 * of the GPL or the X11 license, at your option. Note that this dual
12 * warranty of any kind, whether express or implied. 12 * licensing only applies to this file, and not this project as a
13 * whole.
14 *
15 * a) This file is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of the
18 * License, or (at your option) any later version.
19 *
20 * This file is distributed in the hope that it will be useful
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * Or, alternatively
26 *
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
34 * conditions:
35 *
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
38 *
39 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 * OTHER DEALINGS IN THE SOFTWARE.
13 */ 47 */
14 48
15#include "skeleton.dtsi" 49#include "skeleton.dtsi"
@@ -31,8 +65,7 @@
31 }; 65 };
32 66
33 soc { 67 soc {
34 compatible = "marvell,armada380-mbus", "marvell,armada370-mbus", 68 compatible = "marvell,armada380-mbus", "simple-bus";
35 "simple-bus";
36 #address-cells = <2>; 69 #address-cells = <2>;
37 #size-cells = <1>; 70 #size-cells = <1>;
38 controller = <&mbusc>; 71 controller = <&mbusc>;
@@ -173,7 +206,7 @@
173 status = "disabled"; 206 status = "disabled";
174 }; 207 };
175 208
176 serial@12000 { 209 uart0: serial@12000 {
177 compatible = "snps,dw-apb-uart"; 210 compatible = "snps,dw-apb-uart";
178 reg = <0x12000 0x100>; 211 reg = <0x12000 0x100>;
179 reg-shift = <2>; 212 reg-shift = <2>;
@@ -193,9 +226,94 @@
193 status = "disabled"; 226 status = "disabled";
194 }; 227 };
195 228
196 pinctrl { 229 pinctrl: pinctrl@18000 {
197 compatible = "marvell,mv88f6820-pinctrl";
198 reg = <0x18000 0x20>; 230 reg = <0x18000 0x20>;
231
232 ge0_rgmii_pins: ge-rgmii-pins-0 {
233 marvell,pins = "mpp6", "mpp7", "mpp8",
234 "mpp9", "mpp10", "mpp11",
235 "mpp12", "mpp13", "mpp14",
236 "mpp15", "mpp16", "mpp17";
237 marvell,function = "ge0";
238 };
239
240 ge1_rgmii_pins: ge-rgmii-pins-1 {
241 marvell,pins = "mpp21", "mpp27", "mpp28",
242 "mpp29", "mpp30", "mpp31",
243 "mpp32", "mpp37", "mpp38",
244 "mpp39", "mpp40", "mpp41";
245 marvell,function = "ge1";
246 };
247
248 i2c0_pins: i2c-pins-0 {
249 marvell,pins = "mpp2", "mpp3";
250 marvell,function = "i2c0";
251 };
252
253 mdio_pins: mdio-pins {
254 marvell,pins = "mpp4", "mpp5";
255 marvell,function = "ge";
256 };
257
258 ref_clk0_pins: ref-clk-pins-0 {
259 marvell,pins = "mpp45";
260 marvell,function = "ref";
261 };
262
263 ref_clk1_pins: ref-clk-pins-1 {
264 marvell,pins = "mpp46";
265 marvell,function = "ref";
266 };
267
268 spi0_pins: spi-pins-0 {
269 marvell,pins = "mpp22", "mpp23", "mpp24",
270 "mpp25";
271 marvell,function = "spi0";
272 };
273
274 spi1_pins: spi-pins-1 {
275 marvell,pins = "mpp56", "mpp57", "mpp58",
276 "mpp59";
277 marvell,function = "spi1";
278 };
279
280 uart0_pins: uart-pins-0 {
281 marvell,pins = "mpp0", "mpp1";
282 marvell,function = "ua0";
283 };
284
285 uart1_pins: uart-pins-1 {
286 marvell,pins = "mpp19", "mpp20";
287 marvell,function = "ua1";
288 };
289
290 sdhci_pins: sdhci-pins {
291 marvell,pins = "mpp48", "mpp49", "mpp50",
292 "mpp52", "mpp53", "mpp54",
293 "mpp55", "mpp57", "mpp58",
294 "mpp59";
295 marvell,function = "sd0";
296 };
297
298 sata0_pins: sata-pins-0 {
299 marvell,pins = "mpp20";
300 marvell,function = "sata0";
301 };
302
303 sata1_pins: sata-pins-1 {
304 marvell,pins = "mpp19";
305 marvell,function = "sata1";
306 };
307
308 sata2_pins: sata-pins-2 {
309 marvell,pins = "mpp47";
310 marvell,function = "sata2";
311 };
312
313 sata3_pins: sata-pins-3 {
314 marvell,pins = "mpp44";
315 marvell,function = "sata3";
316 };
199 }; 317 };
200 318
201 gpio0: gpio@18100 { 319 gpio0: gpio@18100 {
@@ -373,7 +491,7 @@
373 status = "disabled"; 491 status = "disabled";
374 }; 492 };
375 493
376 mdio { 494 mdio@72004 {
377 #address-cells = <1>; 495 #address-cells = <1>;
378 #size-cells = <0>; 496 #size-cells = <0>;
379 compatible = "marvell,orion-mdio"; 497 compatible = "marvell,orion-mdio";
diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
index ca0200e20751..c1fbab243609 100644
--- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts
+++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
@@ -3,16 +3,50 @@
3 * 3 *
4 * Note: this board is shipped with a new generation boot loader that 4 * Note: this board is shipped with a new generation boot loader that
5 * remaps internal registers at 0xf1000000. Therefore, if earlyprintk 5 * remaps internal registers at 0xf1000000. Therefore, if earlyprintk
6 * is used, the CONFIG_DEBUG_MVEBU_UART_ALTERNATE option should be 6 * is used, the CONFIG_DEBUG_MVEBU_UART0_ALTERNATE option or the
7 * used. 7 * CONFIG_DEBUG_MVEBU_UART1_ALTERNATE option should be used.
8 * 8 *
9 * Copyright (C) 2013 Marvell 9 * Copyright (C) 2013 Marvell
10 * 10 *
11 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 11 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 * 12 *
13 * This file is licensed under the terms of the GNU General Public 13 * This file is dual-licensed: you can use it either under the terms
14 * License version 2. This program is licensed "as is" without any 14 * of the GPL or the X11 license, at your option. Note that this dual
15 * warranty of any kind, whether express or implied. 15 * licensing only applies to this file, and not this project as a
16 * whole.
17 *
18 * a) This file is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of the
21 * License, or (at your option) any later version.
22 *
23 * This file is distributed in the hope that it will be useful
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * Or, alternatively
29 *
30 * b) Permission is hereby granted, free of charge, to any person
31 * obtaining a copy of this software and associated documentation
32 * files (the "Software"), to deal in the Software without
33 * restriction, including without limitation the rights to use
34 * copy, modify, merge, publish, distribute, sublicense, and/or
35 * sell copies of the Software, and to permit persons to whom the
36 * Software is furnished to do so, subject to the following
37 * conditions:
38 *
39 * The above copyright notice and this permission notice shall be
40 * included in all copies or substantial portions of the Software.
41 *
42 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
43 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
44 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
45 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
46 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
47 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
48 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
49 * OTHER DEALINGS IN THE SOFTWARE.
16 */ 50 */
17 51
18/dts-v1/; 52/dts-v1/;
@@ -60,10 +94,12 @@
60 }; 94 };
61 95
62 internal-regs { 96 internal-regs {
97 /* UART0 */
63 serial@12000 { 98 serial@12000 {
64 status = "okay"; 99 status = "okay";
65 }; 100 };
66 101
102 /* UART1 */
67 serial@12100 { 103 serial@12100 {
68 status = "okay"; 104 status = "okay";
69 }; 105 };
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index 42ddb2864365..48bdafe17526 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -8,9 +8,43 @@
8 * Gregory CLEMENT <gregory.clement@free-electrons.com> 8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * 10 *
11 * This file is licensed under the terms of the GNU General Public 11 * This file is dual-licensed: you can use it either under the terms
12 * License version 2. This program is licensed "as is" without any 12 * of the GPL or the X11 license, at your option. Note that this dual
13 * warranty of any kind, whether express or implied. 13 * licensing only applies to this file, and not this project as a
14 * whole.
15 *
16 * a) This file is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of the
19 * License, or (at your option) any later version.
20 *
21 * This file is distributed in the hope that it will be useful
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * Or, alternatively
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
14 * 48 *
15 * Note: this Device Tree assumes that the bootloader has remapped the 49 * Note: this Device Tree assumes that the bootloader has remapped the
16 * internal registers to 0xf1000000 (instead of the default 50 * internal registers to 0xf1000000 (instead of the default
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index ea8673647494..206aebba01be 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -8,9 +8,43 @@
8 * Gregory CLEMENT <gregory.clement@free-electrons.com> 8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * 10 *
11 * This file is licensed under the terms of the GNU General Public 11 * This file is dual-licensed: you can use it either under the terms
12 * License version 2. This program is licensed "as is" without any 12 * of the GPL or the X11 license, at your option. Note that this dual
13 * warranty of any kind, whether express or implied. 13 * licensing only applies to this file, and not this project as a
14 * whole.
15 *
16 * a) This file is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of the
19 * License, or (at your option) any later version.
20 *
21 * This file is distributed in the hope that it will be useful
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * Or, alternatively
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
14 * 48 *
15 * Note: this Device Tree assumes that the bootloader has remapped the 49 * Note: this Device Tree assumes that the bootloader has remapped the
16 * internal registers to 0xf1000000 (instead of the default 50 * internal registers to 0xf1000000 (instead of the default
diff --git a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
index a2ef93c1eb10..5fb3c8b687cf 100644
--- a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
+++ b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
@@ -3,10 +3,43 @@
3 * 3 *
4 * Copyright (C) 2014, Benoit Masson <yahoo@perenite.com> 4 * Copyright (C) 2014, Benoit Masson <yahoo@perenite.com>
5 * 5 *
6 * This program is free software; you can redistribute it and/or 6 * This file is dual-licensed: you can use it either under the terms
7 * modify it under the terms of the GNU General Public License 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * as published by the Free Software Foundation; either version 8 * licensing only applies to this file, and not this project as a
9 * 2 of the License, or (at your option) any later version. 9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
10 */ 43 */
11 44
12/dts-v1/; 45/dts-v1/;
diff --git a/arch/arm/boot/dts/armada-xp-matrix.dts b/arch/arm/boot/dts/armada-xp-matrix.dts
index 7e291e2ef4b3..56f958eb1ede 100644
--- a/arch/arm/boot/dts/armada-xp-matrix.dts
+++ b/arch/arm/boot/dts/armada-xp-matrix.dts
@@ -5,9 +5,43 @@
5 * 5 *
6 * Lior Amsalem <alior@marvell.com> 6 * Lior Amsalem <alior@marvell.com>
7 * 7 *
8 * This file is licensed under the terms of the GNU General Public 8 * This file is dual-licensed: you can use it either under the terms
9 * License version 2. This program is licensed "as is" without any 9 * of the GPL or the X11 license, at your option. Note that this dual
10 * warranty of any kind, whether express or implied. 10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This file is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
17 *
18 * This file is distributed in the hope that it will be useful
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * Or, alternatively
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
11 */ 45 */
12 46
13/dts-v1/; 47/dts-v1/;
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index 281ccd24295c..6e6d0f04bf2b 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -5,9 +5,43 @@
5 * 5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 * 7 *
8 * This file is licensed under the terms of the GNU General Public 8 * This file is dual-licensed: you can use it either under the terms
9 * License version 2. This program is licensed "as is" without any 9 * of the GPL or the X11 license, at your option. Note that this dual
10 * warranty of any kind, whether express or implied. 10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This file is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
17 *
18 * This file is distributed in the hope that it will be useful
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * Or, alternatively
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
11 * 45 *
12 * Contains definitions specific to the Armada XP MV78230 SoC that are not 46 * Contains definitions specific to the Armada XP MV78230 SoC that are not
13 * common to all Armada XP SoCs. 47 * common to all Armada XP SoCs.
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index d7a8d0b0f385..4a7cbed79b07 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -5,9 +5,43 @@
5 * 5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 * 7 *
8 * This file is licensed under the terms of the GNU General Public 8 * This file is dual-licensed: you can use it either under the terms
9 * License version 2. This program is licensed "as is" without any 9 * of the GPL or the X11 license, at your option. Note that this dual
10 * warranty of any kind, whether express or implied. 10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This file is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
17 *
18 * This file is distributed in the hope that it will be useful
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * Or, alternatively
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
11 * 45 *
12 * Contains definitions specific to the Armada XP MV78260 SoC that are not 46 * Contains definitions specific to the Armada XP MV78260 SoC that are not
13 * common to all Armada XP SoCs. 47 * common to all Armada XP SoCs.
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index 9c40c130d11a..36ce63a96cc9 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -5,9 +5,43 @@
5 * 5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 * 7 *
8 * This file is licensed under the terms of the GNU General Public 8 * This file is dual-licensed: you can use it either under the terms
9 * License version 2. This program is licensed "as is" without any 9 * of the GPL or the X11 license, at your option. Note that this dual
10 * warranty of any kind, whether express or implied. 10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This file is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
17 *
18 * This file is distributed in the hope that it will be useful
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * Or, alternatively
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
11 * 45 *
12 * Contains definitions specific to the Armada XP MV78460 SoC that are not 46 * Contains definitions specific to the Armada XP MV78460 SoC that are not
13 * common to all Armada XP SoCs. 47 * common to all Armada XP SoCs.
diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
index fc8bdfcd2348..99cb9a8401b4 100644
--- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
+++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
@@ -3,10 +3,43 @@
3 * 3 *
4 * Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org> 4 * Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org>
5 * 5 *
6 * This program is free software; you can redistribute it and/or 6 * This file is dual-licensed: you can use it either under the terms
7 * modify it under the terms of the GNU General Public License 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * as published by the Free Software Foundation; either version 8 * licensing only applies to this file, and not this project as a
9 * 2 of the License, or (at your option) any later version. 9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
10 */ 43 */
11 44
12/dts-v1/; 45/dts-v1/;
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 6f6b0916df48..0c76d9f05fd0 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -5,9 +5,43 @@
5 * 5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 * 7 *
8 * This file is licensed under the terms of the GNU General Public 8 * This file is dual-licensed: you can use it either under the terms
9 * License version 2. This program is licensed "as is" without any 9 * of the GPL or the X11 license, at your option. Note that this dual
10 * warranty of any kind, whether express or implied. 10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This file is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
17 *
18 * This file is distributed in the hope that it will be useful
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * Or, alternatively
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
11 */ 45 */
12 46
13/dts-v1/; 47/dts-v1/;
diff --git a/arch/arm/boot/dts/armada-xp-synology-ds414.dts b/arch/arm/boot/dts/armada-xp-synology-ds414.dts
index 749fdba5a642..e9fb225169aa 100644
--- a/arch/arm/boot/dts/armada-xp-synology-ds414.dts
+++ b/arch/arm/boot/dts/armada-xp-synology-ds414.dts
@@ -3,10 +3,43 @@
3 * 3 *
4 * Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org> 4 * Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org>
5 * 5 *
6 * This program is free software; you can redistribute it and/or 6 * This file is dual-licensed: you can use it either under the terms
7 * modify it under the terms of the GNU General Public License 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * as published by the Free Software Foundation; either version 8 * licensing only applies to this file, and not this project as a
9 * 2 of the License, or (at your option) any later version. 9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
10 * 43 *
11 * Note: this Device Tree assumes that the bootloader has remapped the 44 * Note: this Device Tree assumes that the bootloader has remapped the
12 * internal registers to 0xf1000000 (instead of the old 0xd0000000). 45 * internal registers to 0xf1000000 (instead of the old 0xd0000000).
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 62c3ba958b39..82917236a2fb 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -8,9 +8,43 @@
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk> 9 * Ben Dooks <ben.dooks@codethink.co.uk>
10 * 10 *
11 * This file is licensed under the terms of the GNU General Public 11 * This file is dual-licensed: you can use it either under the terms
12 * License version 2. This program is licensed "as is" without any 12 * of the GPL or the X11 license, at your option. Note that this dual
13 * warranty of any kind, whether express or implied. 13 * licensing only applies to this file, and not this project as a
14 * whole.
15 *
16 * a) This file is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of the
19 * License, or (at your option) any later version.
20 *
21 * This file is distributed in the hope that it will be useful
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * Or, alternatively
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
14 * 48 *
15 * Contains definitions specific to the Armada XP SoC that are not 49 * Contains definitions specific to the Armada XP SoC that are not
16 * common to all Armada SoCs. 50 * common to all Armada SoCs.
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index e087a93bea26..1f67bb4c144e 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -695,6 +695,16 @@
695 }; 695 };
696 }; 696 };
697 697
698 ac97 {
699 pinctrl_ac97: ac97-0 {
700 atmel,pins =
701 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A AC97FS pin */
702 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A AC97CK pin */
703 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A AC97TX pin */
704 AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A AC97RX pin */
705 };
706 };
707
698 pioA: gpio@fffff200 { 708 pioA: gpio@fffff200 {
699 compatible = "atmel,at91rm9200-gpio"; 709 compatible = "atmel,at91rm9200-gpio";
700 reg = <0xfffff200 0x200>; 710 reg = <0xfffff200 0x200>;
@@ -823,6 +833,17 @@
823 status = "disabled"; 833 status = "disabled";
824 }; 834 };
825 835
836 ac97: sound@fffa0000 {
837 compatible = "atmel,at91sam9263-ac97c";
838 reg = <0xfffa0000 0x4000>;
839 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 5>;
840 pinctrl-names = "default";
841 pinctrl-0 = <&pinctrl_ac97>;
842 clocks = <&ac97_clk>;
843 clock-names = "ac97_clk";
844 status = "disabled";
845 };
846
826 macb0: ethernet@fffbc000 { 847 macb0: ethernet@fffbc000 {
827 compatible = "cdns,at32ap7000-macb", "cdns,macb"; 848 compatible = "cdns,at32ap7000-macb", "cdns,macb";
828 reg = <0xfffbc000 0x100>; 849 reg = <0xfffbc000 0x100>;
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index 13bb24ea971a..9575c0d895c9 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -54,7 +54,7 @@
54 status = "okay"; 54 status = "okay";
55 55
56 wm8904: codec@1a { 56 wm8904: codec@1a {
57 compatible = "wm8904"; 57 compatible = "wlf,wm8904";
58 reg = <0x1a>; 58 reg = <0x1a>;
59 clocks = <&pck0>; 59 clocks = <&pck0>;
60 clock-names = "mclk"; 60 clock-names = "mclk";
diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi
index 3a9f6fa4a36a..bd16bd360272 100644
--- a/arch/arm/boot/dts/at91sam9x5ek.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi
@@ -53,6 +53,8 @@
53 }; 53 };
54 54
55 usb2: gadget@f803c000 { 55 usb2: gadget@f803c000 {
56 pinctrl-names = "default";
57 pinctrl-0 = <&pinctrl_board_usb2>;
56 atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>; 58 atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>;
57 status = "okay"; 59 status = "okay";
58 }; 60 };
@@ -80,6 +82,13 @@
80 <AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD14 gpio CD pin pull up and deglitch */ 82 <AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD14 gpio CD pin pull up and deglitch */
81 }; 83 };
82 }; 84 };
85
86 usb2 {
87 pinctrl_board_usb2: usb2-board {
88 atmel,pins =
89 <AT91_PIOB 16 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; /* PB16 gpio vbus sense, deglitch */
90 };
91 };
83 }; 92 };
84 93
85 spi0: spi@f0000000 { 94 spi0: spi@f0000000 {
diff --git a/arch/arm/boot/dts/atlas7-evb.dts b/arch/arm/boot/dts/atlas7-evb.dts
new file mode 100644
index 000000000000..49cf59a95572
--- /dev/null
+++ b/arch/arm/boot/dts/atlas7-evb.dts
@@ -0,0 +1,110 @@
1/*
2 * DTS file for CSR SiRFatlas7 Evaluation Board
3 *
4 * Copyright (c) 2014 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9/dts-v1/;
10
11/include/ "atlas7.dtsi"
12
13/ {
14 model = "CSR SiRFatlas7 Evaluation Board";
15 compatible = "sirf,atlas7-cb", "sirf,atlas7";
16
17 chosen {
18 bootargs = "console=ttySiRF1,115200 earlyprintk";
19 };
20
21 memory {
22 device_type = "memory";
23 reg = <0x40000000 0x20000000>;
24 };
25
26 reserved-memory {
27 #address-cells = <1>;
28 #size-cells = <1>;
29 ranges;
30
31 vpp_reserved: vpp_mem@5e800000 {
32 compatible = "sirf,reserved-memory";
33 reg = <0x5e800000 0x800000>;
34 };
35
36 nanddisk_reserved: nanddisk@46000000 {
37 reg = <0x46000000 0x200000>;
38 no-map;
39 };
40 };
41
42
43 noc {
44 mediam {
45 nand@17050000 {
46 memory-region = <&nanddisk_reserved>;
47 };
48 };
49
50 gnssm {
51 spi1: spi@18200000 {
52 status = "okay";
53 spiflash: macronix@0{
54 status = "okay";
55 compatible = "macronix,mx25l6405d";
56 reg = <0>;
57 spi-max-frequency = <37500000>;
58 spi-cpha;
59 spi-cpol;
60 #address-cells = <1>;
61 #size-cells = <1>;
62 partitions@0 {
63 label = "myspiboot";
64 reg = <0x0 0x800000>;
65 };
66 };
67 };
68 };
69
70 btm {
71 uart6: uart@11000000 {
72 status = "okay";
73 sirf,uart-has-rtscts;
74 };
75 };
76
77 disp-iobg {
78 vpp@13110000 {
79 memory-region = <&vpp_reserved>;
80 };
81 };
82
83 display0: display@0 {
84 compatible = "lvds-panel";
85 source = "lvds.0";
86
87 bl-gpios = <&gpio_1 63 0>;
88 data-lines = <24>;
89
90 display-timings {
91 native-mode = <&timing0>;
92 timing0: timing0 {
93 clock-frequency = <60000000>;
94 hactive = <1024>;
95 vactive = <600>;
96 hfront-porch = <220>;
97 hback-porch = <100>;
98 hsync-len = <1>;
99 vback-porch = <10>;
100 vfront-porch = <25>;
101 vsync-len = <1>;
102 hsync-active = <0>;
103 vsync-active = <0>;
104 de-active = <1>;
105 pixelclk-active = <1>;
106 };
107 };
108 };
109 };
110};
diff --git a/arch/arm/boot/dts/atlas7.dtsi b/arch/arm/boot/dts/atlas7.dtsi
new file mode 100644
index 000000000000..a753178abc85
--- /dev/null
+++ b/arch/arm/boot/dts/atlas7.dtsi
@@ -0,0 +1,813 @@
1/*
2 * DTS file for CSR SiRFatlas7 SoC
3 *
4 * Copyright (c) 2014 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9/include/ "skeleton.dtsi"
10/ {
11 compatible = "sirf,atlas7";
12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&gic>;
15 aliases {
16 serial0 = &uart0;
17 serial1 = &uart1;
18 serial2 = &uart2;
19 serial3 = &uart3;
20 serial4 = &uart4;
21 serial5 = &uart5;
22 serial6 = &uart6;
23 serial9 = &usp2;
24 };
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 cpu@0 {
30 device_type = "cpu";
31 compatible = "arm,cortex-a7";
32 reg = <0>;
33 };
34 cpu@1 {
35 device_type = "cpu";
36 compatible = "arm,cortex-a7";
37 reg = <1>;
38 };
39 };
40
41 noc {
42 compatible = "simple-bus";
43 #address-cells = <1>;
44 #size-cells = <1>;
45 ranges = <0x10000000 0x10000000 0xc0000000>;
46
47 gic: interrupt-controller@10301000 {
48 compatible = "arm,cortex-a9-gic";
49 interrupt-controller;
50 #interrupt-cells = <3>;
51 reg = <0x10301000 0x1000>,
52 <0x10302000 0x0100>;
53 };
54
55 pmu_regulator: pmu_regulator@10E30020 {
56 compatible = "sirf,atlas7-pmu-ldo";
57 reg = <0x10E30020 0x4>;
58 ldo: ldo {
59 regulator-name = "ldo";
60 };
61 };
62
63 atlas7_codec: atlas7_codec@10E30000 {
64 #sound-dai-cells = <0>;
65 compatible = "sirf,atlas7-codec";
66 reg = <0x10E30000 0x400>;
67 clocks = <&car 62>;
68 ldo-supply = <&ldo>;
69 };
70
71 atlas7_iacc: atlas7_iacc@10D01000 {
72 #sound-dai-cells = <0>;
73 compatible = "sirf,atlas7-iacc";
74 reg = <0x10D01000 0x100>;
75 dmas = <&dmac3 0>, <&dmac3 7>, <&dmac3 8>,
76 <&dmac3 3>, <&dmac3 9>;
77 dma-names = "rx", "tx0", "tx1", "tx2", "tx3";
78 clocks = <&car 62>;
79 };
80
81 ipc@13240000 {
82 compatible = "sirf,atlas7-ipc";
83 ranges = <0x13240000 0x13240000 0x00010000>;
84 #address-cells = <1>;
85 #size-cells = <1>;
86
87 hwspinlock {
88 compatible = "sirf,hwspinlock";
89 reg = <0x13240000 0x00010000>;
90
91 num-spinlocks = <30>;
92 };
93
94 ns_m3_rproc@0 {
95 compatible = "sirf,ns2m30-rproc";
96 reg = <0x13240000 0x00010000>;
97 interrupts = <0 123 0>;
98 };
99
100 ns_m3_rproc@1 {
101 compatible = "sirf,ns2m31-rproc";
102 reg = <0x13240000 0x00010000>;
103 interrupts = <0 126 0>;
104 };
105
106 ns_kal_rproc@0 {
107 compatible = "sirf,ns2kal0-rproc";
108 reg = <0x13240000 0x00010000>;
109 interrupts = <0 124 0>;
110 };
111
112 ns_kal_rproc@1 {
113 compatible = "sirf,ns2kal1-rproc";
114 reg = <0x13240000 0x00010000>;
115 interrupts = <0 127 0>;
116 };
117 };
118
119 pinctrl: ioc@18880000 {
120 compatible = "sirf,atlas7-ioc";
121 reg = <0x18880000 0x1000>,
122 <0x10E40000 0x1000>;
123 };
124
125 pmipc {
126 compatible = "arteris, flexnoc", "simple-bus";
127 #address-cells = <1>;
128 #size-cells = <1>;
129 ranges = <0x13240000 0x13240000 0x00010000>;
130 pmipc@0x13240000 {
131 compatible = "sirf,atlas7-pmipc";
132 reg = <0x13240000 0x00010000>;
133 };
134 };
135
136 dramfw {
137 compatible = "arteris, flexnoc", "simple-bus";
138 #address-cells = <1>;
139 #size-cells = <1>;
140 ranges = <0x10830000 0x10830000 0x18000>;
141 dramfw@10820000 {
142 compatible = "sirf,nocfw-dramfw";
143 reg = <0x10830000 0x18000>;
144 };
145 };
146
147 spramfw {
148 compatible = "arteris, flexnoc", "simple-bus";
149 #address-cells = <1>;
150 #size-cells = <1>;
151 ranges = <0x10250000 0x10250000 0x3000>;
152 spramfw@10820000 {
153 compatible = "sirf,nocfw-spramfw";
154 reg = <0x10250000 0x3000>;
155 };
156 };
157
158 cpum {
159 compatible = "arteris, flexnoc", "simple-bus";
160 #address-cells = <1>;
161 #size-cells = <1>;
162 ranges = <0x10200000 0x10200000 0x3000>;
163 cpum@10200000 {
164 compatible = "sirf,nocfw-cpum";
165 reg = <0x10200000 0x3000>;
166 };
167 };
168
169 cgum {
170 compatible = "arteris, flexnoc", "simple-bus";
171 #address-cells = <1>;
172 #size-cells = <1>;
173 ranges = <0x18641000 0x18641000 0x3000>,
174 <0x18620000 0x18620000 0x1000>;
175
176 cgum@18641000 {
177 compatible = "sirf,nocfw-cgum";
178 reg = <0x18641000 0x3000>;
179 };
180
181 car: clock-controller@18620000 {
182 compatible = "sirf,atlas7-car";
183 reg = <0x18620000 0x1000>;
184 #clock-cells = <1>;
185 #reset-cells = <1>;
186 };
187 };
188
189 gnssm {
190 compatible = "arteris, flexnoc", "simple-bus";
191 #address-cells = <1>;
192 #size-cells = <1>;
193 ranges = <0x18000000 0x18000000 0x0000ffff>,
194 <0x18010000 0x18010000 0x1000>,
195 <0x18020000 0x18020000 0x1000>,
196 <0x18030000 0x18030000 0x1000>,
197 <0x18040000 0x18040000 0x1000>,
198 <0x18050000 0x18050000 0x1000>,
199 <0x18060000 0x18060000 0x1000>,
200 <0x18100000 0x18100000 0x3000>,
201 <0x18250000 0x18250000 0x10000>,
202 <0x18200000 0x18200000 0x1000>;
203
204 dmac0: dma-controller@18000000 {
205 cell-index = <0>;
206 compatible = "sirf,atlas7-dmac";
207 reg = <0x18000000 0x1000>;
208 interrupts = <0 12 0>;
209 clocks = <&car 89>;
210 dma-channels = <16>;
211 #dma-cells = <1>;
212 };
213
214 gnssmfw@0x18100000 {
215 compatible = "sirf,nocfw-gnssm";
216 reg = <0x18100000 0x3000>;
217 };
218
219 uart0: uart@18010000 {
220 cell-index = <0>;
221 compatible = "sirf,atlas7-uart";
222 reg = <0x18010000 0x1000>;
223 interrupts = <0 17 0>;
224 clocks = <&car 90>;
225 fifosize = <128>;
226 dmas = <&dmac0 3>, <&dmac0 2>;
227 dma-names = "rx", "tx";
228 };
229
230 uart1: uart@18020000 {
231 cell-index = <1>;
232 compatible = "sirf,atlas7-uart";
233 reg = <0x18020000 0x1000>;
234 interrupts = <0 18 0>;
235 clocks = <&car 88>;
236 fifosize = <32>;
237 };
238
239 uart2: uart@18030000 {
240 cell-index = <2>;
241 compatible = "sirf,atlas7-uart";
242 reg = <0x18030000 0x1000>;
243 interrupts = <0 19 0>;
244 clocks = <&car 91>;
245 fifosize = <128>;
246 dmas = <&dmac0 6>, <&dmac0 7>;
247 dma-names = "rx", "tx";
248 status = "disabled";
249 };
250 uart3: uart@18040000 {
251 cell-index = <3>;
252 compatible = "sirf,atlas7-uart";
253 reg = <0x18040000 0x1000>;
254 interrupts = <0 66 0>;
255 clocks = <&car 92>;
256 fifosize = <128>;
257 dmas = <&dmac0 4>, <&dmac0 5>;
258 dma-names = "rx", "tx";
259 status = "disabled";
260 };
261 uart4: uart@18050000 {
262 cell-index = <4>;
263 compatible = "sirf,atlas7-uart";
264 reg = <0x18050000 0x1000>;
265 interrupts = <0 69 0>;
266 clocks = <&car 93>;
267 fifosize = <128>;
268 dmas = <&dmac0 0>, <&dmac0 1>;
269 dma-names = "rx", "tx";
270 status = "disabled";
271 };
272 uart5: uart@18060000 {
273 cell-index = <5>;
274 compatible = "sirf,atlas7-uart";
275 reg = <0x18060000 0x1000>;
276 interrupts = <0 71 0>;
277 clocks = <&car 94>;
278 fifosize = <128>;
279 dmas = <&dmac0 8>, <&dmac0 9>;
280 dma-names = "rx", "tx";
281 status = "disabled";
282 };
283 dspub@18250000 {
284 compatible = "dx,cc44p";
285 reg = <0x18250000 0x10000>;
286 interrupts = <0 27 0>;
287 };
288
289 spi1: spi@18200000 {
290 compatible = "sirf,prima2-spi";
291 reg = <0x18200000 0x1000>;
292 interrupts = <0 16 0>;
293 clocks = <&car 95>;
294 #address-cells = <1>;
295 #size-cells = <0>;
296 dmas = <&dmac0 12>, <&dmac0 13>;
297 dma-names = "rx", "tx";
298 status = "disabled";
299 };
300 };
301
302
303 gpum {
304 compatible = "arteris, flexnoc", "simple-bus";
305 #address-cells = <1>;
306 #size-cells = <1>;
307 ranges = <0x13000000 0x13000000 0x3000>;
308 gpum@0x13000000 {
309 compatible = "sirf,nocfw-gpum";
310 reg = <0x13000000 0x3000>;
311 };
312 };
313
314 mediam {
315 compatible = "arteris, flexnoc", "simple-bus";
316 #address-cells = <1>;
317 #size-cells = <1>;
318 ranges = <0x16000000 0x16000000 0x00200000>,
319 <0x17020000 0x17020000 0x1000>,
320 <0x17030000 0x17030000 0x1000>,
321 <0x17040000 0x17040000 0x1000>,
322 <0x17050000 0x17050000 0x10000>,
323 <0x17060000 0x17060000 0x200>,
324 <0x17060200 0x17060200 0x100>,
325 <0x17070000 0x17070000 0x200>,
326 <0x17070200 0x17070200 0x100>,
327 <0x170A0000 0x170A0000 0x3000>;
328
329 mediam@170A0000 {
330 compatible = "sirf,nocfw-mediam";
331 reg = <0x170A0000 0x3000>;
332 };
333
334 gpio_0: gpio_mediam@17040000 {
335 #gpio-cells = <2>;
336 #interrupt-cells = <2>;
337 compatible = "sirf,atlas7-gpio";
338 reg = <0x17040000 0x1000>;
339 interrupts = <0 13 0>, <0 14 0>;
340 clocks = <&car 107>;
341 clock-names = "gpio0_io";
342 gpio-controller;
343 interrupt-controller;
344 };
345
346 nand@17050000 {
347 compatible = "sirf,atlas7-nand";
348 reg = <0x17050000 0x10000>;
349 interrupts = <0 41 0>;
350 clocks = <&car 108>, <&car 112>;
351 clock-names = "nand_io", "nand_nand";
352 };
353
354 sd0: sdhci@16000000 {
355 cell-index = <0>;
356 compatible = "sirf,atlas7-sdhc";
357 reg = <0x16000000 0x100000>;
358 interrupts = <0 38 0>;
359 clocks = <&car 109>, <&car 111>;
360 clock-names = "core", "iface";
361 wp-inverted;
362 non-removable;
363 status = "disabled";
364 bus-width = <8>;
365 };
366
367 sd1: sdhci@16100000 {
368 cell-index = <1>;
369 compatible = "sirf,atlas7-sdhc";
370 reg = <0x16100000 0x100000>;
371 interrupts = <0 38 0>;
372 clocks = <&car 109>, <&car 111>;
373 clock-names = "core", "iface";
374 non-removable;
375 status = "disabled";
376 bus-width = <8>;
377 };
378
379 usb0: usb@17060000 {
380 cell-index = <0>;
381 compatible = "sirf,atlas7-usb";
382 reg = <0x17060000 0x200>;
383 interrupts = <0 10 0>;
384 clocks = <&car 113>;
385 sirf,usbphy = <&usbphy0>;
386 phy_type = "utmi";
387 dr_mode = "otg";
388 maximum-speed = "high-speed";
389 status = "okay";
390 };
391
392 usb1: usb@17070000 {
393 cell-index = <1>;
394 compatible = "sirf,atlas7-usb";
395 reg = <0x17070000 0x200>;
396 interrupts = <0 11 0>;
397 clocks = <&car 114>;
398 sirf,usbphy = <&usbphy1>;
399 phy_type = "utmi";
400 dr_mode = "host";
401 maximum-speed = "high-speed";
402 status = "okay";
403 };
404
405 usbphy0: usbphy@0 {
406 compatible = "sirf,atlas7-usbphy";
407 reg = <0x17060200 0x100>;
408 clocks = <&car 115>;
409 status = "okay";
410 };
411
412 usbphy1: usbphy@1 {
413 compatible = "sirf,atlas7-usbphy";
414 reg = <0x17070200 0x100>;
415 clocks = <&car 116>;
416 status = "okay";
417 };
418
419 i2c0: i2c@17020000 {
420 cell-index = <0>;
421 compatible = "sirf,prima2-i2c";
422 reg = <0x17020000 0x1000>;
423 interrupts = <0 24 0>;
424 clocks = <&car 105>;
425 #address-cells = <1>;
426 #size-cells = <0>;
427 };
428
429 };
430
431 vdifm {
432 compatible = "arteris, flexnoc", "simple-bus";
433 #address-cells = <1>;
434 #size-cells = <1>;
435 ranges = <0x13290000 0x13290000 0x3000>,
436 <0x13300000 0x13300000 0x1000>,
437 <0x14200000 0x14200000 0x600000>;
438
439 vdifm@13290000 {
440 compatible = "sirf,nocfw-vdifm";
441 reg = <0x13290000 0x3000>;
442 };
443
444 gpio_1: gpio_vdifm@13300000 {
445 #gpio-cells = <2>;
446 #interrupt-cells = <2>;
447 compatible = "sirf,atlas7-gpio";
448 reg = <0x13300000 0x1000>;
449 interrupts = <0 43 0>, <0 44 0>, <0 45 0>;
450 clocks = <&car 84>;
451 clock-names = "gpio1_io";
452 gpio-controller;
453 interrupt-controller;
454 };
455
456 sd2: sdhci@14200000 {
457 cell-index = <2>;
458 compatible = "sirf,atlas7-sdhc";
459 reg = <0x14200000 0x100000>;
460 interrupts = <0 23 0>;
461 clocks = <&car 70>, <&car 75>;
462 clock-names = "core", "iface";
463 status = "disabled";
464 bus-width = <4>;
465 sd-uhs-sdr50;
466 vqmmc-supply = <&vqmmc>;
467 vqmmc: vqmmc@2 {
468 regulator-min-microvolt = <1650000>;
469 regulator-max-microvolt = <1950000>;
470 regulator-name = "vqmmc-ldo";
471 regulator-type = "voltage";
472 regulator-boot-on;
473 regulator-allow-bypass;
474 };
475 };
476
477 sd3: sdhci@14300000 {
478 cell-index = <3>;
479 compatible = "sirf,atlas7-sdhc";
480 reg = <0x14300000 0x100000>;
481 interrupts = <0 23 0>;
482 clocks = <&car 76>, <&car 81>;
483 clock-names = "core", "iface";
484 status = "disabled";
485 bus-width = <4>;
486 };
487
488 sd5: sdhci@14500000 {
489 cell-index = <5>;
490 compatible = "sirf,atlas7-sdhc";
491 reg = <0x14500000 0x100000>;
492 interrupts = <0 39 0>;
493 clocks = <&car 71>, <&car 76>;
494 clock-names = "core", "iface";
495 status = "disabled";
496 bus-width = <4>;
497 loop-dma;
498 };
499
500 sd6: sdhci@14600000 {
501 cell-index = <6>;
502 compatible = "sirf,atlas7-sdhc";
503 reg = <0x14600000 0x100000>;
504 interrupts = <0 98 0>;
505 clocks = <&car 72>, <&car 77>;
506 clock-names = "core", "iface";
507 status = "disabled";
508 bus-width = <4>;
509 };
510
511 sd7: sdhci@14700000 {
512 cell-index = <7>;
513 compatible = "sirf,atlas7-sdhc";
514 reg = <0x14700000 0x100000>;
515 interrupts = <0 98 0>;
516 clocks = <&car 72>, <&car 77>;
517 clock-names = "core", "iface";
518 status = "disabled";
519 bus-width = <4>;
520 };
521 };
522
523 audiom {
524 compatible = "arteris, flexnoc", "simple-bus";
525 #address-cells = <1>;
526 #size-cells = <1>;
527 ranges = <0x10d50000 0x10d50000 0x0000ffff>,
528 <0x10d60000 0x10d60000 0x0000ffff>,
529 <0x10d80000 0x10d80000 0x0000ffff>,
530 <0x10d90000 0x10d90000 0x0000ffff>,
531 <0x10ED0000 0x10ED0000 0x3000>,
532 <0x10dc8000 0x10dc8000 0x1000>,
533 <0x10dc0000 0x10dc0000 0x1000>,
534 <0x10db0000 0x10db0000 0x4000>,
535 <0x10d40000 0x10d40000 0x1000>,
536 <0x10d30000 0x10d30000 0x1000>;
537
538 timer@10dc0000 {
539 compatible = "sirf,atlas7-tick";
540 reg = <0x10dc0000 0x1000>;
541 interrupts = <0 0 0>,
542 <0 1 0>,
543 <0 2 0>,
544 <0 49 0>,
545 <0 50 0>,
546 <0 51 0>;
547 clocks = <&car 47>;
548 };
549
550 timerb@10dc8000 {
551 compatible = "sirf,atlas7-tick";
552 reg = <0x10dc8000 0x1000>;
553 interrupts = <0 74 0>,
554 <0 75 0>,
555 <0 76 0>,
556 <0 77 0>,
557 <0 78 0>,
558 <0 79 0>;
559 clocks = <&car 47>;
560 };
561
562 vip0@10db0000 {
563 compatible = "sirf,atlas7-vip0";
564 reg = <0x10db0000 0x2000>;
565 interrupts = <0 85 0>;
566 sirf,vip_cma_size = <0xC00000>;
567 };
568
569 cvd@10db2000 {
570 compatible = "sirf,cvd";
571 reg = <0x10db2000 0x2000>;
572 clocks = <&car 46>;
573 };
574
575 dmac2: dma-controller@10d50000 {
576 cell-index = <2>;
577 compatible = "sirf,atlas7-dmac";
578 reg = <0x10d50000 0xffff>;
579 interrupts = <0 55 0>;
580 clocks = <&car 60>;
581 dma-channels = <16>;
582 #dma-cells = <1>;
583 };
584
585 dmac3: dma-controller@10d60000 {
586 cell-index = <3>;
587 compatible = "sirf,atlas7-dmac";
588 reg = <0x10d60000 0xffff>;
589 interrupts = <0 56 0>;
590 clocks = <&car 61>;
591 dma-channels = <16>;
592 #dma-cells = <1>;
593 };
594
595 adc: adc@10d80000 {
596 compatible = "sirf,atlas7-adc";
597 reg = <0x10d80000 0xffff>;
598 interrupts = <0 34 0>;
599 clocks = <&car 49>;
600 #io-channel-cells = <1>;
601 };
602
603 pulsec@10d90000 {
604 compatible = "sirf,prima2-pulsec";
605 reg = <0x10d90000 0xffff>;
606 interrupts = <0 42 0>;
607 clocks = <&car 54>;
608 };
609
610 audiom@10ED0000 {
611 compatible = "sirf,nocfw-audiom";
612 reg = <0x10ED0000 0x3000>;
613 interrupts = <0 102 0>;
614 };
615
616 usp1: usp@10d30000 {
617 cell-index = <1>;
618 reg = <0x10d30000 0x1000>;
619 fifosize = <512>;
620 clocks = <&car 58>;
621 dmas = <&dmac2 6>, <&dmac2 7>;
622 dma-names = "rx", "tx";
623 };
624
625 usp2: usp@10d40000 {
626 cell-index = <2>;
627 reg = <0x10d40000 0x1000>;
628 interrupts = <0 22 0>;
629 clocks = <&car 59>;
630 dmas = <&dmac2 12>, <&dmac2 13>;
631 dma-names = "rx", "tx";
632 #address-cells = <1>;
633 #size-cells = <0>;
634 status = "disabled";
635 };
636 };
637
638 ddrm {
639 compatible = "arteris, flexnoc", "simple-bus";
640 #address-cells = <1>;
641 #size-cells = <1>;
642 ranges = <0x10820000 0x10820000 0x3000>,
643 <0x10800000 0x10800000 0x2000>;
644 ddrm@10820000 {
645 compatible = "sirf,nocfw-ddrm";
646 reg = <0x10820000 0x3000>;
647 interrupts = <0 105 0>;
648 };
649
650 memory-controller@0x10800000 {
651 compatible = "sirf,atlas7-memc";
652 reg = <0x10800000 0x2000>;
653 };
654
655 };
656
657 btm {
658 compatible = "arteris, flexnoc", "simple-bus";
659 #address-cells = <1>;
660 #size-cells = <1>;
661 ranges = <0x11002000 0x11002000 0x0000ffff>,
662 <0x11010000 0x11010000 0x3000>,
663 <0x11000000 0x11000000 0x1000>,
664 <0x11001000 0x11001000 0x1000>;
665
666 dmac4: dma-controller@11002000 {
667 cell-index = <4>;
668 compatible = "sirf,atlas7-dmac";
669 reg = <0x11002000 0x1000>;
670 interrupts = <0 99 0>;
671 clocks = <&car 130>;
672 dma-channels = <16>;
673 #dma-cells = <1>;
674 };
675 uart6: uart@11000000 {
676 cell-index = <6>;
677 compatible = "sirf,atlas7-bt-uart",
678 "sirf,atlas7-uart";
679 reg = <0x11000000 0x1000>;
680 interrupts = <0 100 0>;
681 clocks = <&car 131>, <&car 133>, <&car 134>;
682 clock-names = "uart", "general", "noc";
683 fifosize = <128>;
684 dmas = <&dmac4 12>, <&dmac4 13>;
685 dma-names = "rx", "tx";
686 status = "disabled";
687 };
688
689 usp3: usp@11001000 {
690 compatible = "sirf,atlas7-bt-usp",
691 "sirf,prima2-usp-pcm";
692 cell-index = <3>;
693 reg = <0x11001000 0x1000>;
694 fifosize = <512>;
695 clocks = <&car 132>, <&car 129>, <&car 133>,
696 <&car 134>, <&car 135>;
697 clock-names = "usp3_io", "a7ca_btss", "a7ca_io",
698 "noc_btm_io", "thbtm_io";
699 dmas = <&dmac4 0>, <&dmac4 1>;
700 dma-names = "rx", "tx";
701 };
702
703 btm@11010000 {
704 compatible = "sirf,nocfw-btm";
705 reg = <0x11010000 0x3000>;
706 };
707 };
708
709 rtcm {
710 compatible = "arteris, flexnoc", "simple-bus";
711 #address-cells = <1>;
712 #size-cells = <1>;
713 ranges = <0x18810000 0x18810000 0x3000>,
714 <0x18840000 0x18840000 0x1000>,
715 <0x18890000 0x18890000 0x1000>,
716 <0x188B0000 0x188B0000 0x10000>,
717 <0x188D0000 0x188D0000 0x1000>;
718 rtcm@18810000 {
719 compatible = "sirf,nocfw-rtcm";
720 reg = <0x18810000 0x3000>;
721 interrupts = <0 109 0>;
722 };
723
724 gpio_2: gpio_rtcm@18890000 {
725 #gpio-cells = <2>;
726 #interrupt-cells = <2>;
727 compatible = "sirf,atlas7-gpio";
728 reg = <0x18890000 0x1000>;
729 interrupts = <0 47 0>;
730 gpio-controller;
731 interrupt-controller;
732 };
733
734 rtc-iobg@18840000 {
735 compatible = "sirf,prima2-rtciobg",
736 "sirf-prima2-rtciobg-bus",
737 "simple-bus";
738 #address-cells = <1>;
739 #size-cells = <1>;
740 reg = <0x18840000 0x1000>;
741
742 sysrtc@2000 {
743 compatible = "sirf,prima2-sysrtc";
744 reg = <0x2000 0x100>;
745 interrupts = <0 52 0>;
746 };
747 pwrc@3000 {
748 compatible = "sirf,atlas7-pwrc";
749 reg = <0x3000 0x100>;
750 };
751 };
752
753 qspi: flash@188B0000 {
754 cell-index = <0>;
755 compatible = "sirf,atlas7-qspi-nor";
756 reg = <0x188B0000 0x10000>;
757 interrupts = <0 15 0>;
758 #address-cells = <1>;
759 #size-cells = <0>;
760 };
761
762 retain@0x188D0000 {
763 compatible = "sirf,atlas7-retain";
764 reg = <0x188D0000 0x1000>;
765 };
766
767 };
768 disp-iobg {
769 /* lcdc0 */
770 compatible = "simple-bus";
771 #address-cells = <1>;
772 #size-cells = <1>;
773 ranges = <0x13100000 0x13100000 0x20000>,
774 <0x10e10000 0x10e10000 0x10000>;
775
776 lcd@13100000 {
777 compatible = "sirf,atlas7-lcdc";
778 reg = <0x13100000 0x10000>;
779 interrupts = <0 30 0>;
780 clocks = <&car 79>;
781 };
782 vpp@13110000 {
783 compatible = "sirf,atlas7-vpp";
784 reg = <0x13110000 0x10000>;
785 interrupts = <0 31 0>;
786 clocks = <&car 78>;
787 resets = <&car 29>;
788 };
789 lvds@10e10000 {
790 compatible = "sirf,atlas7-lvdsc";
791 reg = <0x10e10000 0x10000>;
792 interrupts = <0 64 0>;
793 clocks = <&car 54>;
794 resets = <&car 29>;
795 };
796
797 };
798
799 graphics-iobg {
800 compatible = "simple-bus";
801 #address-cells = <1>;
802 #size-cells = <1>;
803 ranges = <0x12000000 0x12000000 0x1000000>;
804
805 graphics@12000000 {
806 compatible = "powervr,sgx531";
807 reg = <0x12000000 0x1000000>;
808 interrupts = <0 6 0>;
809 clocks = <&car 126>;
810 };
811 };
812 };
813};
diff --git a/arch/arm/boot/dts/axp209.dtsi b/arch/arm/boot/dts/axp209.dtsi
new file mode 100644
index 000000000000..c20cf537f5a5
--- /dev/null
+++ b/arch/arm/boot/dts/axp209.dtsi
@@ -0,0 +1,97 @@
1/*
2 * Copyright 2015 Chen-Yu Tsai
3 *
4 * Chen-Yu Tsai <wens@csie.org>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
48 */
49
50/*
51 * AXP202/209 Integrated Power Management Chip
52 * http://www.x-powers.com/product/AXP20X.php
53 * http://dl.linux-sunxi.org/AXP/AXP209%20Datasheet%20v1.0_cn.pdf
54 */
55
56&axp209 {
57 compatible = "x-powers,axp209";
58 interrupt-controller;
59 #interrupt-cells = <1>;
60
61 regulators {
62 /* Default work frequency for buck regulators */
63 x-powers,dcdc-freq = <1500>;
64
65 reg_dcdc2: dcdc2 {
66 regulator-name = "dcdc2";
67 };
68
69 reg_dcdc3: dcdc3 {
70 regulator-name = "dcdc3";
71 };
72
73 reg_ldo1: ldo1 {
74 /* LDO1 is a fixed output regulator */
75 regulator-always-on;
76 regulator-min-microvolt = <1300000>;
77 regulator-max-microvolt = <1300000>;
78 regulator-name = "ldo1";
79 };
80
81 reg_ldo2: ldo2 {
82 regulator-name = "ldo2";
83 };
84
85 reg_ldo3: ldo3 {
86 regulator-name = "ldo3";
87 };
88
89 reg_ldo4: ldo4 {
90 regulator-name = "ldo4";
91 };
92
93 reg_ldo5: ldo5 {
94 regulator-name = "ldo5";
95 };
96 };
97};
diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
index 5fc0fae03092..b359c1e6178e 100644
--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
+++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
@@ -23,11 +23,77 @@
23 reg = <0x00000000 0x08000000>; 23 reg = <0x00000000 0x08000000>;
24 }; 24 };
25 25
26 spi {
27 compatible = "spi-gpio";
28 num-chipselects = <1>;
29 gpio-sck = <&chipcommon 7 0>;
30 gpio-mosi = <&chipcommon 4 0>;
31 cs-gpios = <&chipcommon 6 0>;
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 hc595: gpio_spi@0 {
36 compatible = "fairchild,74hc595";
37 reg = <0>;
38 registers-number = <1>;
39 spi-max-frequency = <100000>;
40
41 gpio-controller;
42 #gpio-cells = <2>;
43
44 };
45 };
46
47 leds {
48 compatible = "gpio-leds";
49
50 power0 {
51 label = "bcm53xx:red:power";
52 gpios = <&hc595 1 GPIO_ACTIVE_HIGH>;
53 linux,default-trigger = "default-off";
54 };
55
56 power1 {
57 label = "bcm53xx:white:power";
58 gpios = <&hc595 2 GPIO_ACTIVE_HIGH>;
59 linux,default-trigger = "default-on";
60 };
61
62 router0 {
63 label = "bcm53xx:blue:router";
64 gpios = <&hc595 3 GPIO_ACTIVE_HIGH>;
65 linux,default-trigger = "default-on";
66 };
67
68 router1 {
69 label = "bcm53xx:amber:router";
70 gpios = <&hc595 4 GPIO_ACTIVE_HIGH>;
71 linux,default-trigger = "default-off";
72 };
73
74 wan {
75 label = "bcm53xx:blue:wan";
76 gpios = <&hc595 5 GPIO_ACTIVE_HIGH>;
77 linux,default-trigger = "default-on";
78 };
79
80 wireless0 {
81 label = "bcm53xx:blue:wireless";
82 gpios = <&hc595 6 GPIO_ACTIVE_HIGH>;
83 linux,default-trigger = "default-off";
84 };
85
86 wireless1 {
87 label = "bcm53xx:amber:wireless";
88 gpios = <&hc595 7 GPIO_ACTIVE_HIGH>;
89 linux,default-trigger = "default-off";
90 };
91 };
92
26 gpio-keys { 93 gpio-keys {
27 compatible = "gpio-keys"; 94 compatible = "gpio-keys";
28 #address-cells = <1>; 95 #address-cells = <1>;
29 #size-cells = <0>; 96 #size-cells = <0>;
30 poll-interval = <200>;
31 97
32 restart { 98 restart {
33 label = "Reset"; 99 label = "Reset";
diff --git a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts
new file mode 100644
index 000000000000..946c728c4eb7
--- /dev/null
+++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts
@@ -0,0 +1,60 @@
1/*
2 * Broadcom BCM470X / BCM5301X ARM platform code.
3 * DTS for Luxul XWC-1000
4 *
5 * Copyright 2014 Luxul Inc.
6 *
7 * Licensed under the GNU/GPL. See COPYING for details.
8 */
9
10/dts-v1/;
11
12#include "bcm4708.dtsi"
13
14/ {
15 compatible = "luxul,xwc-1000", "brcm,bcm4708";
16 model = "Luxul XWC-1000 (BCM4708)";
17
18 chosen {
19 bootargs = "console=ttyS0,115200";
20 };
21
22 memory {
23 reg = <0x00000000 0x08000000>;
24 };
25
26 axi@18000000 {
27 nand@28000 {
28 reg = <0x00028000 0x1000>;
29 #address-cells = <1>;
30 #size-cells = <1>;
31
32 partition@0 {
33 label = "ubi";
34 reg = <0x00000000 0x08000000>;
35 };
36 };
37 };
38
39 leds {
40 compatible = "gpio-leds";
41
42 status {
43 label = "bcm53xx:green:status";
44 gpios = <&chipcommon 0 GPIO_ACTIVE_HIGH>;
45 linux,default-trigger = "timer";
46 };
47 };
48
49 gpio-keys {
50 compatible = "gpio-keys";
51 #address-cells = <1>;
52 #size-cells = <0>;
53
54 restart {
55 label = "Reset";
56 linux,code = <KEY_RESTART>;
57 gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
58 };
59 };
60};
diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
index 4ed7de1058b7..f18c9d9b2f2c 100644
--- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
+++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
@@ -71,7 +71,6 @@
71 compatible = "gpio-keys"; 71 compatible = "gpio-keys";
72 #address-cells = <1>; 72 #address-cells = <1>;
73 #size-cells = <0>; 73 #size-cells = <0>;
74 poll-interval = <200>;
75 74
76 wps { 75 wps {
77 label = "WPS"; 76 label = "WPS";
diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts
index 12fc2a01e6ab..39910428246a 100644
--- a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts
+++ b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts
@@ -61,7 +61,6 @@
61 compatible = "gpio-keys"; 61 compatible = "gpio-keys";
62 #address-cells = <1>; 62 #address-cells = <1>;
63 #size-cells = <0>; 63 #size-cells = <0>;
64 poll-interval = <200>;
65 64
66 wps { 65 wps {
67 label = "WPS"; 66 label = "WPS";
diff --git a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts
index fb76378bd511..0ee85ea10bb2 100644
--- a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts
+++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts
@@ -61,7 +61,6 @@
61 compatible = "gpio-keys"; 61 compatible = "gpio-keys";
62 #address-cells = <1>; 62 #address-cells = <1>;
63 #size-cells = <0>; 63 #size-cells = <0>;
64 poll-interval = <200>;
65 64
66 restart { 65 restart {
67 label = "Reset"; 66 label = "Reset";
diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
index bbb414fbad65..db9131e03268 100644
--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
+++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
@@ -23,11 +23,77 @@
23 reg = <0x00000000 0x08000000>; 23 reg = <0x00000000 0x08000000>;
24 }; 24 };
25 25
26 spi {
27 compatible = "spi-gpio";
28 num-chipselects = <1>;
29 gpio-sck = <&chipcommon 7 0>;
30 gpio-mosi = <&chipcommon 4 0>;
31 cs-gpios = <&chipcommon 6 0>;
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 hc595: gpio_spi@0 {
36 compatible = "fairchild,74hc595";
37 reg = <0>;
38 registers-number = <1>;
39 spi-max-frequency = <100000>;
40
41 gpio-controller;
42 #gpio-cells = <2>;
43
44 };
45 };
46
47 leds {
48 compatible = "gpio-leds";
49
50 power0 {
51 label = "bcm53xx:green:power";
52 gpios = <&hc595 1 GPIO_ACTIVE_HIGH>;
53 linux,default-trigger = "default-on";
54 };
55
56 power1 {
57 label = "bcm53xx:red:power";
58 gpios = <&hc595 2 GPIO_ACTIVE_HIGH>;
59 linux,default-trigger = "default-off";
60 };
61
62 router0 {
63 label = "bcm53xx:green:router";
64 gpios = <&hc595 3 GPIO_ACTIVE_HIGH>;
65 linux,default-trigger = "default-on";
66 };
67
68 router1 {
69 label = "bcm53xx:amber:router";
70 gpios = <&hc595 4 GPIO_ACTIVE_HIGH>;
71 linux,default-trigger = "default-off";
72 };
73
74 wan {
75 label = "bcm53xx:green:wan";
76 gpios = <&hc595 5 GPIO_ACTIVE_HIGH>;
77 linux,default-trigger = "default-on";
78 };
79
80 wireless0 {
81 label = "bcm53xx:green:wireless";
82 gpios = <&hc595 6 GPIO_ACTIVE_HIGH>;
83 linux,default-trigger = "default-off";
84 };
85
86 wireless1 {
87 label = "bcm53xx:amber:wireless";
88 gpios = <&hc595 7 GPIO_ACTIVE_HIGH>;
89 linux,default-trigger = "default-off";
90 };
91 };
92
26 gpio-keys { 93 gpio-keys {
27 compatible = "gpio-keys"; 94 compatible = "gpio-keys";
28 #address-cells = <1>; 95 #address-cells = <1>;
29 #size-cells = <0>; 96 #size-cells = <0>;
30 poll-interval = <200>;
31 97
32 aoss { 98 aoss {
33 label = "AOSS"; 99 label = "AOSS";
diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts
new file mode 100644
index 000000000000..7d6868acb1c6
--- /dev/null
+++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts
@@ -0,0 +1,37 @@
1/*
2 * Broadcom BCM470X / BCM5301X ARM platform code.
3 * DTS for Buffalo WZR-900DHP
4 *
5 * Copyright (C) 2015 Rafał Miłecki <zajec5@gmail.com>
6 *
7 * Licensed under the GNU/GPL. See COPYING for details.
8 */
9
10/dts-v1/;
11
12#include "bcm47081.dtsi"
13
14/ {
15 compatible = "buffalo,wzr-900dhp", "brcm,bcm47081", "brcm,bcm4708";
16 model = "Buffalo WZR-900DHP (BCM47081)";
17
18 chosen {
19 bootargs = "console=ttyS0,115200";
20 };
21
22 memory {
23 reg = <0x00000000 0x08000000>;
24 };
25
26 gpio-keys {
27 compatible = "gpio-keys";
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 restart {
32 label = "Reset";
33 linux,code = <KEY_RESTART>;
34 gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
35 };
36 };
37};
diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
index 015a06c67c91..63d00a63cfa6 100644
--- a/arch/arm/boot/dts/berlin2.dtsi
+++ b/arch/arm/boot/dts/berlin2.dtsi
@@ -104,7 +104,7 @@
104 local-timer@ad0600 { 104 local-timer@ad0600 {
105 compatible = "arm,cortex-a9-twd-timer"; 105 compatible = "arm,cortex-a9-twd-timer";
106 reg = <0xad0600 0x20>; 106 reg = <0xad0600 0x20>;
107 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; 107 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
108 clocks = <&chip CLKID_TWD>; 108 clocks = <&chip CLKID_TWD>;
109 }; 109 };
110 110
diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi
index 230df3b1770e..81b670ac494a 100644
--- a/arch/arm/boot/dts/berlin2cd.dtsi
+++ b/arch/arm/boot/dts/berlin2cd.dtsi
@@ -45,6 +45,11 @@
45 45
46 ranges = <0 0xf7000000 0x1000000>; 46 ranges = <0 0xf7000000 0x1000000>;
47 47
48 pmu {
49 compatible = "arm,cortex-a9-pmu";
50 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
51 };
52
48 sdhci0: sdhci@ab0000 { 53 sdhci0: sdhci@ab0000 {
49 compatible = "mrvl,pxav3-mmc"; 54 compatible = "mrvl,pxav3-mmc";
50 reg = <0xab0000 0x200>; 55 reg = <0xab0000 0x200>;
@@ -71,7 +76,7 @@
71 local-timer@ad0600 { 76 local-timer@ad0600 {
72 compatible = "arm,cortex-a9-twd-timer"; 77 compatible = "arm,cortex-a9-twd-timer";
73 reg = <0xad0600 0x20>; 78 reg = <0xad0600 0x20>;
74 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; 79 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
75 clocks = <&chip CLKID_TWD>; 80 clocks = <&chip CLKID_TWD>;
76 }; 81 };
77 82
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
index e2f61f27944e..be5397288d24 100644
--- a/arch/arm/boot/dts/berlin2q.dtsi
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -63,6 +63,14 @@
63 ranges = <0 0xf7000000 0x1000000>; 63 ranges = <0 0xf7000000 0x1000000>;
64 interrupt-parent = <&gic>; 64 interrupt-parent = <&gic>;
65 65
66 pmu {
67 compatible = "arm,cortex-a9-pmu";
68 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
69 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
70 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
71 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
72 };
73
66 sdhci0: sdhci@ab0000 { 74 sdhci0: sdhci@ab0000 {
67 compatible = "mrvl,pxav3-mmc"; 75 compatible = "mrvl,pxav3-mmc";
68 reg = <0xab0000 0x200>; 76 reg = <0xab0000 0x200>;
@@ -105,7 +113,7 @@
105 compatible = "arm,cortex-a9-twd-timer"; 113 compatible = "arm,cortex-a9-twd-timer";
106 reg = <0xad0600 0x20>; 114 reg = <0xad0600 0x20>;
107 clocks = <&chip CLKID_TWD>; 115 clocks = <&chip CLKID_TWD>;
108 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; 116 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
109 }; 117 };
110 118
111 gic: interrupt-controller@ad1000 { 119 gic: interrupt-controller@ad1000 {
diff --git a/arch/arm/boot/dts/cx92755.dtsi b/arch/arm/boot/dts/cx92755.dtsi
new file mode 100644
index 000000000000..490c08075e67
--- /dev/null
+++ b/arch/arm/boot/dts/cx92755.dtsi
@@ -0,0 +1,113 @@
1/*
2 * Device Tree Include file for the Conexant Digicolor CX92755 SoC
3 *
4 * Author: Baruch Siach <baruch@tkos.co.il>
5 *
6 * Copyright (C) 2014 Paradox Innovation Ltd.
7 *
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPL or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This file is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
17 *
18 * This file is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * Or, alternatively,
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
45 */
46
47#include "skeleton.dtsi"
48
49/ {
50 compatible = "cnxt,cx92755";
51
52 interrupt-parent = <&intc>;
53
54 cpus {
55 #address-cells = <1>;
56 #size-cells = <0>;
57 cpu@0 {
58 device_type = "cpu";
59 compatible = "arm,cortex-a8";
60 reg = <0x0>;
61 };
62 };
63
64 main_clk: main_clk {
65 compatible = "fixed-clock";
66 #clock-cells = <0>;
67 clock-frequency = <200000000>;
68 };
69
70 intc: interrupt-controller@f0000040 {
71 compatible = "cnxt,cx92755-ic";
72 interrupt-controller;
73 #interrupt-cells = <1>;
74 reg = <0xf0000040 0x40>;
75 syscon = <&uc_regs>;
76 };
77
78 timer@f0000fc0 {
79 compatible = "cnxt,cx92755-timer";
80 reg = <0xf0000fc0 0x40>;
81 interrupts = <19>, <31>, <34>, <35>, <52>, <53>, <54>, <55>;
82 clocks = <&main_clk>;
83 };
84
85 uc_regs: syscon@f00003a0 {
86 compatible = "cnxt,cx92755-uc", "syscon";
87 reg = <0xf00003a0 0x10>;
88 };
89
90 uart0: uart@f0000740 {
91 compatible = "cnxt,cx92755-usart";
92 reg = <0xf0000740 0x20>;
93 clocks = <&main_clk>;
94 interrupts = <44>;
95 status = "disabled";
96 };
97
98 uart1: uart@f0000760 {
99 compatible = "cnxt,cx92755-usart";
100 reg = <0xf0000760 0x20>;
101 clocks = <&main_clk>;
102 interrupts = <45>;
103 status = "disabled";
104 };
105
106 uart2: uart@f0000780 {
107 compatible = "cnxt,cx92755-usart";
108 reg = <0xf0000780 0x20>;
109 clocks = <&main_clk>;
110 interrupts = <46>;
111 status = "disabled";
112 };
113};
diff --git a/arch/arm/boot/dts/cx92755_equinox.dts b/arch/arm/boot/dts/cx92755_equinox.dts
new file mode 100644
index 000000000000..f33bf5635d47
--- /dev/null
+++ b/arch/arm/boot/dts/cx92755_equinox.dts
@@ -0,0 +1,74 @@
1/*
2 * Device Tree file for the Conexant Equinox CX92755 EVK
3 *
4 * Author: Baruch Siach <baruch@tkos.co.il>
5 *
6 * Copyright (C) 2014 Paradox Innovation Ltd.
7 *
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPL or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This file is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
17 *
18 * This file is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * Or, alternatively,
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
45 */
46
47/dts-v1/;
48
49#include "cx92755.dtsi"
50
51/ {
52 model = "Conexant Equinox CX92755 EVK";
53 compatible = "cnxt,equinox", "cnxt,cx92755";
54
55 aliases {
56 serial0 = &uart0;
57 serial1 = &uart1;
58 serial2 = &uart2;
59 };
60
61 memory@0 {
62 reg = <0 0x8000000>;
63 device_type = "memory";
64 };
65
66 chosen {
67 bootargs = "console=ttyS0,115200";
68 stdout-path = &uart0;
69 };
70};
71
72&uart0 {
73 status = "okay";
74};
diff --git a/arch/arm/boot/dts/dm8168-evm.dts b/arch/arm/boot/dts/dm8168-evm.dts
new file mode 100644
index 000000000000..857d0289ad4d
--- /dev/null
+++ b/arch/arm/boot/dts/dm8168-evm.dts
@@ -0,0 +1,129 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
5 */
6/dts-v1/;
7
8#include "dm816x.dtsi"
9
10/ {
11 model = "DM8168 EVM";
12 compatible = "ti,dm8168-evm", "ti,dm8168";
13
14 memory {
15 device_type = "memory";
16 reg = <0x80000000 0x40000000 /* 1 GB */
17 0xc0000000 0x40000000>; /* 1 GB */
18 };
19
20 /* FDC6331L controlled by SD_POW pin */
21 vmmcsd_fixed: fixedregulator@0 {
22 compatible = "regulator-fixed";
23 regulator-name = "vmmcsd_fixed";
24 regulator-min-microvolt = <3300000>;
25 regulator-max-microvolt = <3300000>;
26 };
27};
28
29&dm816x_pinmux {
30 mcspi1_pins: pinmux_mcspi1_pins {
31 pinctrl-single,pins = <
32 DM816X_IOPAD(0x0a94, PIN_INPUT | MUX_MODE0) /* SPI_SCLK */
33 DM816X_IOPAD(0x0a98, PIN_OUTPUT | MUX_MODE0) /* SPI_SCS0 */
34 DM816X_IOPAD(0x0aa8, PIN_INPUT | MUX_MODE0) /* SPI_D0 */
35 DM816X_IOPAD(0x0aac, PIN_INPUT | MUX_MODE0) /* SPI_D1 */
36 >;
37 };
38};
39
40&i2c1 {
41 extgpio0: pcf8575@20 {
42 compatible = "nxp,pcf8575";
43 reg = <0x20>;
44 gpio-controller;
45 #gpio-cells = <2>;
46 };
47};
48
49&i2c2 {
50 extgpio1: pcf8575@20 {
51 compatible = "nxp,pcf8575";
52 reg = <0x20>;
53 gpio-controller;
54 #gpio-cells = <2>;
55 };
56};
57
58&gpmc {
59 ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */
60
61 nand@0,0 {
62 linux,mtd-name= "micron,mt29f2g16aadwp";
63 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
64 #address-cells = <1>;
65 #size-cells = <1>;
66 ti,nand-ecc-opt = "bch8";
67 nand-bus-width = <16>;
68 gpmc,device-width = <2>;
69 gpmc,sync-clk-ps = <0>;
70 gpmc,cs-on-ns = <0>;
71 gpmc,cs-rd-off-ns = <44>;
72 gpmc,cs-wr-off-ns = <44>;
73 gpmc,adv-on-ns = <6>;
74 gpmc,adv-rd-off-ns = <34>;
75 gpmc,adv-wr-off-ns = <44>;
76 gpmc,we-on-ns = <0>;
77 gpmc,we-off-ns = <40>;
78 gpmc,oe-on-ns = <0>;
79 gpmc,oe-off-ns = <54>;
80 gpmc,access-ns = <64>;
81 gpmc,rd-cycle-ns = <82>;
82 gpmc,wr-cycle-ns = <82>;
83 gpmc,wait-on-read = "true";
84 gpmc,wait-on-write = "true";
85 gpmc,bus-turnaround-ns = <0>;
86 gpmc,cycle2cycle-delay-ns = <0>;
87 gpmc,clk-activation-ns = <0>;
88 gpmc,wait-monitoring-ns = <0>;
89 gpmc,wr-access-ns = <40>;
90 gpmc,wr-data-mux-bus-ns = <0>;
91 partition@0 {
92 label = "X-Loader";
93 reg = <0 0x80000>;
94 };
95 partition@0x80000 {
96 label = "U-Boot";
97 reg = <0x80000 0x1c0000>;
98 };
99 partition@0x1c0000 {
100 label = "Environment";
101 reg = <0x240000 0x40000>;
102 };
103 partition@0x280000 {
104 label = "Kernel";
105 reg = <0x280000 0x500000>;
106 };
107 partition@0x780000 {
108 label = "Filesystem";
109 reg = <0x780000 0xf880000>;
110 };
111 };
112};
113
114&mcspi1 {
115 pinctrl-names = "default";
116 pinctrl-0 = <&mcspi1_pins>;
117
118 m25p80@0 {
119 compatible = "w25x32";
120 spi-max-frequency = <48000000>;
121 reg = <0>;
122 #address-cells = <1>;
123 #size-cells = <1>;
124 };
125};
126
127&mmc1 {
128 vmmc-supply = <&vmmcsd_fixed>;
129};
diff --git a/arch/arm/boot/dts/dm816x-clocks.dtsi b/arch/arm/boot/dts/dm816x-clocks.dtsi
new file mode 100644
index 000000000000..50d9d338fbe9
--- /dev/null
+++ b/arch/arm/boot/dts/dm816x-clocks.dtsi
@@ -0,0 +1,250 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
5 */
6
7&scrm {
8 main_fapll: main_fapll {
9 #clock-cells = <1>;
10 compatible = "ti,dm816-fapll-clock";
11 reg = <0x400 0x40>;
12 clocks = <&sys_clkin_ck &sys_clkin_ck>;
13 clock-indices = <1>, <2>, <3>, <4>, <5>,
14 <6>, <7>;
15 clock-output-names = "main_pll_clk1",
16 "main_pll_clk2",
17 "main_pll_clk3",
18 "main_pll_clk4",
19 "main_pll_clk5",
20 "main_pll_clk6",
21 "main_pll_clk7";
22 };
23
24 ddr_fapll: ddr_fapll {
25 #clock-cells = <1>;
26 compatible = "ti,dm816-fapll-clock";
27 reg = <0x440 0x30>;
28 clocks = <&sys_clkin_ck &sys_clkin_ck>;
29 clock-indices = <1>, <2>, <3>, <4>;
30 clock-output-names = "ddr_pll_clk1",
31 "ddr_pll_clk2",
32 "ddr_pll_clk3",
33 "ddr_pll_clk4";
34 };
35
36 video_fapll: video_fapll {
37 #clock-cells = <1>;
38 compatible = "ti,dm816-fapll-clock";
39 reg = <0x470 0x30>;
40 clocks = <&sys_clkin_ck &sys_clkin_ck>;
41 clock-indices = <1>, <2>, <3>;
42 clock-output-names = "video_pll_clk1",
43 "video_pll_clk2",
44 "video_pll_clk3";
45 };
46
47 audio_fapll: audio_fapll {
48 #clock-cells = <1>;
49 compatible = "ti,dm816-fapll-clock";
50 reg = <0x4a0 0x30>;
51 clocks = <&main_fapll 7>, < &sys_clkin_ck>;
52 clock-indices = <1>, <2>, <3>, <4>, <5>;
53 clock-output-names = "audio_pll_clk1",
54 "audio_pll_clk2",
55 "audio_pll_clk3",
56 "audio_pll_clk4",
57 "audio_pll_clk5";
58 };
59};
60
61&scrm_clocks {
62 secure_32k_ck: secure_32k_ck {
63 #clock-cells = <0>;
64 compatible = "fixed-clock";
65 clock-frequency = <32768>;
66 };
67
68 sys_32k_ck: sys_32k_ck {
69 #clock-cells = <0>;
70 compatible = "fixed-clock";
71 clock-frequency = <32768>;
72 };
73
74 tclkin_ck: tclkin_ck {
75 #clock-cells = <0>;
76 compatible = "fixed-clock";
77 clock-frequency = <32768>;
78 };
79
80 sys_clkin_ck: sys_clkin_ck {
81 #clock-cells = <0>;
82 compatible = "fixed-clock";
83 clock-frequency = <27000000>;
84 };
85};
86
87/* 0x48180000 */
88&prcm_clocks {
89 clkout_pre_ck: clkout_pre_ck {
90 #clock-cells = <0>;
91 compatible = "ti,mux-clock";
92 clocks = <&main_fapll 5 &ddr_fapll 1 &video_fapll 1
93 &audio_fapll 1>;
94 reg = <0x100>;
95 };
96
97 clkout_div_ck: clkout_div_ck {
98 #clock-cells = <0>;
99 compatible = "ti,divider-clock";
100 clocks = <&clkout_pre_ck>;
101 ti,bit-shift = <3>;
102 ti,max-div = <8>;
103 reg = <0x100>;
104 };
105
106 clkout_ck: clkout_ck {
107 #clock-cells = <0>;
108 compatible = "ti,gate-clock";
109 clocks = <&clkout_div_ck>;
110 ti,bit-shift = <7>;
111 reg = <0x100>;
112 };
113
114 /* CM_DPLL clocks p1795 */
115 sysclk1_ck: sysclk1_ck {
116 #clock-cells = <0>;
117 compatible = "ti,divider-clock";
118 clocks = <&main_fapll 1>;
119 ti,max-div = <7>;
120 reg = <0x0300>;
121 };
122
123 sysclk2_ck: sysclk2_ck {
124 #clock-cells = <0>;
125 compatible = "ti,divider-clock";
126 clocks = <&main_fapll 2>;
127 ti,max-div = <7>;
128 reg = <0x0304>;
129 };
130
131 sysclk3_ck: sysclk3_ck {
132 #clock-cells = <0>;
133 compatible = "ti,divider-clock";
134 clocks = <&main_fapll 3>;
135 ti,max-div = <7>;
136 reg = <0x0308>;
137 };
138
139 sysclk4_ck: sysclk4_ck {
140 #clock-cells = <0>;
141 compatible = "ti,divider-clock";
142 clocks = <&main_fapll 4>;
143 ti,max-div = <1>;
144 reg = <0x030c>;
145 };
146
147 sysclk5_ck: sysclk5_ck {
148 #clock-cells = <0>;
149 compatible = "ti,divider-clock";
150 clocks = <&sysclk4_ck>;
151 ti,max-div = <1>;
152 reg = <0x0310>;
153 };
154
155 sysclk6_ck: sysclk6_ck {
156 #clock-cells = <0>;
157 compatible = "ti,divider-clock";
158 clocks = <&main_fapll 4>;
159 ti,dividers = <2>, <4>;
160 reg = <0x0314>;
161 };
162
163 sysclk10_ck: sysclk10_ck {
164 #clock-cells = <0>;
165 compatible = "ti,divider-clock";
166 clocks = <&ddr_fapll 2>;
167 ti,max-div = <7>;
168 reg = <0x0324>;
169 };
170
171 sysclk24_ck: sysclk24_ck {
172 #clock-cells = <0>;
173 compatible = "ti,divider-clock";
174 clocks = <&main_fapll 5>;
175 ti,max-div = <7>;
176 reg = <0x03b4>;
177 };
178
179 mpu_ck: mpu_ck {
180 #clock-cells = <0>;
181 compatible = "ti,gate-clock";
182 clocks = <&sysclk2_ck>;
183 ti,bit-shift = <1>;
184 reg = <0x15dc>;
185 };
186
187 audio_pll_a_ck: audio_pll_a_ck {
188 #clock-cells = <0>;
189 compatible = "ti,divider-clock";
190 clocks = <&audio_fapll 1>;
191 ti,max-div = <7>;
192 reg = <0x035c>;
193 };
194
195 sysclk18_ck: sysclk18_ck {
196 #clock-cells = <0>;
197 compatible = "ti,mux-clock";
198 clocks = <&sys_32k_ck>, <&audio_pll_a_ck>;
199 reg = <0x0378>;
200 };
201
202 timer1_fck: timer1_fck {
203 #clock-cells = <0>;
204 compatible = "ti,mux-clock";
205 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
206 reg = <0x0390>;
207 };
208
209 timer2_fck: timer2_fck {
210 #clock-cells = <0>;
211 compatible = "ti,mux-clock";
212 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
213 reg = <0x0394>;
214 };
215
216 timer3_fck: timer3_fck {
217 #clock-cells = <0>;
218 compatible = "ti,mux-clock";
219 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
220 reg = <0x0398>;
221 };
222
223 timer4_fck: timer4_fck {
224 #clock-cells = <0>;
225 compatible = "ti,mux-clock";
226 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
227 reg = <0x039c>;
228 };
229
230 timer5_fck: timer5_fck {
231 #clock-cells = <0>;
232 compatible = "ti,mux-clock";
233 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
234 reg = <0x03a0>;
235 };
236
237 timer6_fck: timer6_fck {
238 #clock-cells = <0>;
239 compatible = "ti,mux-clock";
240 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
241 reg = <0x03a4>;
242 };
243
244 timer7_fck: timer7_fck {
245 #clock-cells = <0>;
246 compatible = "ti,mux-clock";
247 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
248 reg = <0x03a8>;
249 };
250};
diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi
new file mode 100644
index 000000000000..d98d0f7de380
--- /dev/null
+++ b/arch/arm/boot/dts/dm816x.dtsi
@@ -0,0 +1,392 @@
1/*
2 * This file is licensed under the terms of the GNU General Public License
3 * version 2. This program is licensed "as is" without any warranty of any
4 * kind, whether express or implied.
5 */
6
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/pinctrl/omap.h>
9
10#include "skeleton.dtsi"
11
12/ {
13 compatible = "ti,dm816";
14 interrupt-parent = <&intc>;
15
16 aliases {
17 i2c0 = &i2c1;
18 i2c1 = &i2c2;
19 serial0 = &uart1;
20 serial1 = &uart2;
21 serial2 = &uart3;
22 ethernet0 = &eth0;
23 ethernet1 = &eth1;
24 };
25
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
29 cpu@0 {
30 compatible = "arm,cortex-a8";
31 device_type = "cpu";
32 reg = <0>;
33 };
34 };
35
36 pmu {
37 compatible = "arm,cortex-a8-pmu";
38 interrupts = <3>;
39 };
40
41 /*
42 * The soc node represents the soc top level view. It is used for IPs
43 * that are not memory mapped in the MPU view or for the MPU itself.
44 */
45 soc {
46 compatible = "ti,omap-infra";
47 mpu {
48 compatible = "ti,omap3-mpu";
49 ti,hwmods = "mpu";
50 };
51 };
52
53 /*
54 * XXX: Use a flat representation of the dm816x interconnect.
55 * The real dm816x interconnect network is quite complex. Since
56 * it will not bring real advantage to represent that in DT
57 * for the moment, just use a fake OCP bus entry to represent
58 * the whole bus hierarchy.
59 */
60 ocp {
61 compatible = "ti,omap3-l3-smx", "simple-bus";
62 reg = <0x44000000 0x10000>;
63 interrupts = <9 10>;
64 #address-cells = <1>;
65 #size-cells = <1>;
66 ranges;
67 ti,hwmods = "l3_main";
68
69 prcm: prcm@48180000 {
70 compatible = "ti,dm816-prcm";
71 reg = <0x48180000 0x4000>;
72
73 prcm_clocks: clocks {
74 #address-cells = <1>;
75 #size-cells = <0>;
76 };
77
78 prcm_clockdomains: clockdomains {
79 };
80 };
81
82 scrm: scrm@48140000 {
83 compatible = "ti,dm816-scrm", "simple-bus";
84 reg = <0x48140000 0x21000>;
85 #address-cells = <1>;
86 #size-cells = <1>;
87 ranges = <0 0x48140000 0x21000>;
88
89 dm816x_pinmux: pinmux@800 {
90 compatible = "pinctrl-single";
91 reg = <0x800 0x50a>;
92 #address-cells = <1>;
93 #size-cells = <0>;
94 pinctrl-single,register-width = <16>;
95 pinctrl-single,function-mask = <0xf>;
96 };
97
98 /* Device Configuration Registers */
99 scm_conf: syscon@600 {
100 compatible = "syscon";
101 reg = <0x600 0x110>;
102 #address-cells = <1>;
103 #size-cells = <1>;
104 };
105
106 scrm_clocks: clocks {
107 #address-cells = <1>;
108 #size-cells = <0>;
109 };
110
111 scrm_clockdomains: clockdomains {
112 };
113 };
114
115 edma: edma@49000000 {
116 compatible = "ti,edma3";
117 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2", "tptc3";
118 reg = <0x49000000 0x10000>,
119 <0x44e10f90 0x40>;
120 interrupts = <12 13 14>;
121 #dma-cells = <1>;
122 };
123
124 elm: elm@48080000 {
125 compatible = "ti,816-elm";
126 ti,hwmods = "elm";
127 reg = <0x48080000 0x2000>;
128 interrupts = <4>;
129 };
130
131 gpio1: gpio@48032000 {
132 compatible = "ti,omap3-gpio";
133 ti,hwmods = "gpio1";
134 reg = <0x48032000 0x1000>;
135 interrupts = <97>;
136 };
137
138 gpio2: gpio@4804c000 {
139 compatible = "ti,omap3-gpio";
140 ti,hwmods = "gpio2";
141 reg = <0x4804c000 0x1000>;
142 interrupts = <99>;
143 };
144
145 gpmc: gpmc@50000000 {
146 compatible = "ti,am3352-gpmc";
147 ti,hwmods = "gpmc";
148 reg = <0x50000000 0x2000>;
149 #address-cells = <2>;
150 #size-cells = <1>;
151 interrupts = <100>;
152 gpmc,num-cs = <6>;
153 gpmc,num-waitpins = <2>;
154 };
155
156 i2c1: i2c@48028000 {
157 compatible = "ti,omap4-i2c";
158 ti,hwmods = "i2c1";
159 reg = <0x48028000 0x1000>;
160 #address-cells = <1>;
161 #size-cells = <0>;
162 interrupts = <70>;
163 dmas = <&edma 58 &edma 59>;
164 dma-names = "tx", "rx";
165 };
166
167 i2c2: i2c@4802a000 {
168 compatible = "ti,omap4-i2c";
169 ti,hwmods = "i2c2";
170 reg = <0x4802a000 0x1000>;
171 #address-cells = <1>;
172 #size-cells = <0>;
173 interrupts = <71>;
174 dmas = <&edma 60 &edma 61>;
175 dma-names = "tx", "rx";
176 };
177
178 intc: interrupt-controller@48200000 {
179 compatible = "ti,dm816-intc";
180 interrupt-controller;
181 #interrupt-cells = <1>;
182 reg = <0x48200000 0x1000>;
183 };
184
185 mailbox: mailbox@480c8000 {
186 compatible = "ti,omap4-mailbox";
187 reg = <0x480c8000 0x2000>;
188 interrupts = <77>;
189 ti,hwmods = "mailbox";
190 ti,mbox-num-users = <4>;
191 ti,mbox-num-fifos = <12>;
192 mbox_dsp: mbox_dsp {
193 ti,mbox-tx = <3 0 0>;
194 ti,mbox-rx = <0 0 0>;
195 };
196 };
197
198 mdio: mdio@4a100800 {
199 compatible = "ti,davinci_mdio";
200 #address-cells = <1>;
201 #size-cells = <0>;
202 reg = <0x4a100800 0x100>;
203 ti,hwmods = "davinci_mdio";
204 bus_freq = <1000000>;
205 phy0: ethernet-phy@0 {
206 reg = <1>;
207 };
208 phy1: ethernet-phy@1 {
209 reg = <2>;
210 };
211 };
212
213 eth0: ethernet@4a100000 {
214 compatible = "ti,dm816-emac";
215 ti,hwmods = "emac0";
216 reg = <0x4a100000 0x800
217 0x4a100900 0x3700>;
218 clocks = <&sysclk24_ck>;
219 syscon = <&scm_conf>;
220 ti,davinci-ctrl-reg-offset = <0>;
221 ti,davinci-ctrl-mod-reg-offset = <0x900>;
222 ti,davinci-ctrl-ram-offset = <0x2000>;
223 ti,davinci-ctrl-ram-size = <0x2000>;
224 interrupts = <40 41 42 43>;
225 phy-handle = <&phy0>;
226 };
227
228 eth1: ethernet@4a120000 {
229 compatible = "ti,dm816-emac";
230 ti,hwmods = "emac1";
231 reg = <0x4a120000 0x4000>;
232 clocks = <&sysclk24_ck>;
233 syscon = <&scm_conf>;
234 ti,davinci-ctrl-reg-offset = <0>;
235 ti,davinci-ctrl-mod-reg-offset = <0x900>;
236 ti,davinci-ctrl-ram-offset = <0x2000>;
237 ti,davinci-ctrl-ram-size = <0x2000>;
238 interrupts = <44 45 46 47>;
239 phy-handle = <&phy1>;
240 };
241
242 mcspi1: spi@48030000 {
243 compatible = "ti,omap4-mcspi";
244 reg = <0x48030000 0x1000>;
245 #address-cells = <1>;
246 #size-cells = <0>;
247 interrupts = <65>;
248 ti,spi-num-cs = <4>;
249 ti,hwmods = "mcspi1";
250 dmas = <&edma 16 &edma 17
251 &edma 18 &edma 19>;
252 dma-names = "tx0", "rx0", "tx1", "rx1";
253 };
254
255 mmc1: mmc@48060000 {
256 compatible = "ti,omap4-hsmmc";
257 reg = <0x48060000 0x11000>;
258 ti,hwmods = "mmc1";
259 interrupts = <64>;
260 dmas = <&edma 24 &edma 25>;
261 dma-names = "tx", "rx";
262 };
263
264 timer1: timer@4802e000 {
265 compatible = "ti,dm816-timer";
266 reg = <0x4802e000 0x2000>;
267 interrupts = <67>;
268 ti,hwmods = "timer1";
269 ti,timer-alwon;
270 };
271
272 timer2: timer@48040000 {
273 compatible = "ti,dm816-timer";
274 reg = <0x48040000 0x2000>;
275 interrupts = <68>;
276 ti,hwmods = "timer2";
277 };
278
279 timer3: timer@48042000 {
280 compatible = "ti,dm816-timer";
281 reg = <0x48042000 0x2000>;
282 interrupts = <69>;
283 ti,hwmods = "timer3";
284 };
285
286 timer4: timer@48044000 {
287 compatible = "ti,dm816-timer";
288 reg = <0x48044000 0x2000>;
289 interrupts = <92>;
290 ti,hwmods = "timer4";
291 };
292
293 timer5: timer@48046000 {
294 compatible = "ti,dm816-timer";
295 reg = <0x48046000 0x2000>;
296 interrupts = <93>;
297 ti,hwmods = "timer5";
298 };
299
300 timer6: timer@48048000 {
301 compatible = "ti,dm816-timer";
302 reg = <0x48048000 0x2000>;
303 interrupts = <94>;
304 ti,hwmods = "timer6";
305 };
306
307 timer7: timer@4804a000 {
308 compatible = "ti,dm816-timer";
309 reg = <0x4804a000 0x2000>;
310 interrupts = <95>;
311 ti,hwmods = "timer7";
312 };
313
314 uart1: uart@48020000 {
315 compatible = "ti,omap3-uart";
316 ti,hwmods = "uart1";
317 reg = <0x48020000 0x2000>;
318 clock-frequency = <48000000>;
319 interrupts = <72>;
320 dmas = <&edma 26 &edma 27>;
321 dma-names = "tx", "rx";
322 };
323
324 uart2: uart@48022000 {
325 compatible = "ti,omap3-uart";
326 ti,hwmods = "uart2";
327 reg = <0x48022000 0x2000>;
328 clock-frequency = <48000000>;
329 interrupts = <73>;
330 dmas = <&edma 28 &edma 29>;
331 dma-names = "tx", "rx";
332 };
333
334 uart3: uart@48024000 {
335 compatible = "ti,omap3-uart";
336 ti,hwmods = "uart3";
337 reg = <0x48024000 0x2000>;
338 clock-frequency = <48000000>;
339 interrupts = <74>;
340 dmas = <&edma 30 &edma 31>;
341 dma-names = "tx", "rx";
342 };
343
344 /* NOTE: USB needs a transceiver driver for phys to work */
345 usb: usb_otg_hs@47401000 {
346 compatible = "ti,am33xx-usb";
347 reg = <0x47401000 0x400000>;
348 ranges;
349 #address-cells = <1>;
350 #size-cells = <1>;
351 ti,hwmods = "usb_otg_hs";
352
353 usb0: usb@47401000 {
354 compatible = "ti,musb-am33xx";
355 reg = <0x47401400 0x400
356 0x47401000 0x200>;
357 reg-names = "mc", "control";
358 interrupts = <18>;
359 interrupt-names = "mc";
360 dr_mode = "otg";
361 mentor,multipoint = <1>;
362 mentor,num-eps = <16>;
363 mentor,ram-bits = <12>;
364 mentor,power = <500>;
365 };
366
367 usb1: usb@47401800 {
368 compatible = "ti,musb-am33xx";
369 status = "disabled";
370 reg = <0x47401c00 0x400
371 0x47401800 0x200>;
372 reg-names = "mc", "control";
373 interrupts = <19>;
374 interrupt-names = "mc";
375 dr_mode = "otg";
376 mentor,multipoint = <1>;
377 mentor,num-eps = <16>;
378 mentor,ram-bits = <12>;
379 mentor,power = <500>;
380 };
381 };
382
383 wd_timer2: wd_timer@480c2000 {
384 compatible = "ti,omap3-wdt";
385 ti,hwmods = "wd_timer";
386 reg = <0x480c2000 0x1000>;
387 interrupts = <0>;
388 };
389 };
390};
391
392#include "dm816x-clocks.dtsi"
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index ad4118f7e1a6..746cddb1b8f5 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -26,6 +26,16 @@
26 regulator-max-microvolt = <3300000>; 26 regulator-max-microvolt = <3300000>;
27 }; 27 };
28 28
29 extcon_usb1: extcon_usb1 {
30 compatible = "linux,extcon-usb-gpio";
31 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
32 };
33
34 extcon_usb2: extcon_usb2 {
35 compatible = "linux,extcon-usb-gpio";
36 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
37 };
38
29 vtt_fixed: fixedregulator-vtt { 39 vtt_fixed: fixedregulator-vtt {
30 compatible = "regulator-fixed"; 40 compatible = "regulator-fixed";
31 regulator-name = "vtt_fixed"; 41 regulator-name = "vtt_fixed";
@@ -391,6 +401,19 @@
391 }; 401 };
392 }; 402 };
393 }; 403 };
404
405 pcf_gpio_21: gpio@21 {
406 compatible = "ti,pcf8575";
407 reg = <0x21>;
408 lines-initial-states = <0x1408>;
409 gpio-controller;
410 #gpio-cells = <2>;
411 interrupt-parent = <&gpio6>;
412 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
413 interrupt-controller;
414 #interrupt-cells = <2>;
415 };
416
394}; 417};
395 418
396&i2c2 { 419&i2c2 {
@@ -520,6 +543,14 @@
520 }; 543 };
521}; 544};
522 545
546&omap_dwc3_1 {
547 extcon = <&extcon_usb1>;
548};
549
550&omap_dwc3_2 {
551 extcon = <&extcon_usb2>;
552};
553
523&usb1 { 554&usb1 {
524 dr_mode = "peripheral"; 555 dr_mode = "peripheral";
525 pinctrl-names = "default"; 556 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 63f8b007bdc5..5827fedafd43 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1111,7 +1111,6 @@
1111 "wkupclk", "refclk", 1111 "wkupclk", "refclk",
1112 "div-clk", "phy-div"; 1112 "div-clk", "phy-div";
1113 #phy-cells = <0>; 1113 #phy-cells = <0>;
1114 id = <1>;
1115 ti,hwmods = "pcie1-phy"; 1114 ti,hwmods = "pcie1-phy";
1116 }; 1115 };
1117 1116
@@ -1132,7 +1131,6 @@
1132 "div-clk", "phy-div"; 1131 "div-clk", "phy-div";
1133 #phy-cells = <0>; 1132 #phy-cells = <0>;
1134 ti,hwmods = "pcie2-phy"; 1133 ti,hwmods = "pcie2-phy";
1135 id = <2>;
1136 status = "disabled"; 1134 status = "disabled";
1137 }; 1135 };
1138 }; 1136 };
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index 89085d066c65..4d8711713610 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -8,6 +8,7 @@
8/dts-v1/; 8/dts-v1/;
9 9
10#include "dra72x.dtsi" 10#include "dra72x.dtsi"
11#include <dt-bindings/gpio/gpio.h>
11 12
12/ { 13/ {
13 model = "TI DRA722"; 14 model = "TI DRA722";
@@ -24,6 +25,16 @@
24 regulator-min-microvolt = <3300000>; 25 regulator-min-microvolt = <3300000>;
25 regulator-max-microvolt = <3300000>; 26 regulator-max-microvolt = <3300000>;
26 }; 27 };
28
29 extcon_usb1: extcon_usb1 {
30 compatible = "linux,extcon-usb-gpio";
31 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
32 };
33
34 extcon_usb2: extcon_usb2 {
35 compatible = "linux,extcon-usb-gpio";
36 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
37 };
27}; 38};
28 39
29&dra7_pmx_core { 40&dra7_pmx_core {
@@ -121,6 +132,18 @@
121 0x418 (MUX_MODE15) /* wakeup0.off */ 132 0x418 (MUX_MODE15) /* wakeup0.off */
122 >; 133 >;
123 }; 134 };
135
136 qspi1_pins: pinmux_qspi1_pins {
137 pinctrl-single,pins = <
138 0x74 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
139 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
140 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
141 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
142 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
143 0x88 (PIN_OUTPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
144 0xb8 (PIN_OUTPUT | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
145 >;
146 };
124}; 147};
125 148
126&i2c1 { 149&i2c1 {
@@ -243,6 +266,18 @@
243 ti,palmas-long-press-seconds = <6>; 266 ti,palmas-long-press-seconds = <6>;
244 }; 267 };
245 }; 268 };
269
270 pcf_gpio_21: gpio@21 {
271 compatible = "ti,pcf8575";
272 reg = <0x21>;
273 lines-initial-states = <0x1408>;
274 gpio-controller;
275 #gpio-cells = <2>;
276 interrupt-parent = <&gpio6>;
277 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
278 interrupt-controller;
279 #interrupt-cells = <2>;
280 };
246}; 281};
247 282
248&uart1 { 283&uart1 {
@@ -345,6 +380,14 @@
345 phy-supply = <&ldo4_reg>; 380 phy-supply = <&ldo4_reg>;
346}; 381};
347 382
383&omap_dwc3_1 {
384 extcon = <&extcon_usb1>;
385};
386
387&omap_dwc3_2 {
388 extcon = <&extcon_usb2>;
389};
390
348&usb1 { 391&usb1 {
349 dr_mode = "peripheral"; 392 dr_mode = "peripheral";
350 pinctrl-names = "default"; 393 pinctrl-names = "default";
@@ -461,3 +504,68 @@
461 pinctrl-0 = <&dcan1_pins_default>; 504 pinctrl-0 = <&dcan1_pins_default>;
462 pinctrl-1 = <&dcan1_pins_sleep>; 505 pinctrl-1 = <&dcan1_pins_sleep>;
463}; 506};
507
508&qspi {
509 status = "okay";
510 pinctrl-names = "default";
511 pinctrl-0 = <&qspi1_pins>;
512
513 spi-max-frequency = <48000000>;
514 m25p80@0 {
515 compatible = "s25fl256s1";
516 spi-max-frequency = <48000000>;
517 reg = <0>;
518 spi-tx-bus-width = <1>;
519 spi-rx-bus-width = <4>;
520 spi-cpol;
521 spi-cpha;
522 #address-cells = <1>;
523 #size-cells = <1>;
524
525 /* MTD partition table.
526 * The ROM checks the first four physical blocks
527 * for a valid file to boot and the flash here is
528 * 64KiB block size.
529 */
530 partition@0 {
531 label = "QSPI.SPL";
532 reg = <0x00000000 0x000010000>;
533 };
534 partition@1 {
535 label = "QSPI.SPL.backup1";
536 reg = <0x00010000 0x00010000>;
537 };
538 partition@2 {
539 label = "QSPI.SPL.backup2";
540 reg = <0x00020000 0x00010000>;
541 };
542 partition@3 {
543 label = "QSPI.SPL.backup3";
544 reg = <0x00030000 0x00010000>;
545 };
546 partition@4 {
547 label = "QSPI.u-boot";
548 reg = <0x00040000 0x00100000>;
549 };
550 partition@5 {
551 label = "QSPI.u-boot-spl-os";
552 reg = <0x00140000 0x00080000>;
553 };
554 partition@6 {
555 label = "QSPI.u-boot-env";
556 reg = <0x001c0000 0x00010000>;
557 };
558 partition@7 {
559 label = "QSPI.u-boot-env.backup1";
560 reg = <0x001d0000 0x0010000>;
561 };
562 partition@8 {
563 label = "QSPI.kernel";
564 reg = <0x001e0000 0x0800000>;
565 };
566 partition@9 {
567 label = "QSPI.file-system";
568 reg = <0x009e0000 0x01620000>;
569 };
570 };
571};
diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts
index 24822aa98057..1d483c1c8b48 100644
--- a/arch/arm/boot/dts/exynos3250-monk.dts
+++ b/arch/arm/boot/dts/exynos3250-monk.dts
@@ -15,6 +15,7 @@
15/dts-v1/; 15/dts-v1/;
16#include "exynos3250.dtsi" 16#include "exynos3250.dtsi"
17#include <dt-bindings/input/input.h> 17#include <dt-bindings/input/input.h>
18#include <dt-bindings/gpio/gpio.h>
18 19
19/ { 20/ {
20 model = "Samsung Monk board"; 21 model = "Samsung Monk board";
@@ -37,9 +38,7 @@
37 compatible = "gpio-keys"; 38 compatible = "gpio-keys";
38 39
39 power_key { 40 power_key {
40 interrupt-parent = <&gpx2>; 41 gpios = <&gpx2 7 GPIO_ACTIVE_LOW>;
41 interrupts = <7 0>;
42 gpios = <&gpx2 7 1>;
43 linux,code = <KEY_POWER>; 42 linux,code = <KEY_POWER>;
44 label = "power key"; 43 label = "power key";
45 debounce-interval = <10>; 44 debounce-interval = <10>;
@@ -109,6 +108,13 @@
109 }; 108 };
110 }; 109 };
111 }; 110 };
111
112 haptics {
113 compatible = "regulator-haptic";
114 haptic-supply = <&motor_reg>;
115 min-microvolt = <1100000>;
116 max-microvolt = <2700000>;
117 };
112}; 118};
113 119
114&adc { 120&adc {
@@ -134,6 +140,17 @@
134 }; 140 };
135}; 141};
136 142
143&exynos_usbphy {
144 status = "okay";
145};
146
147&hsotg {
148 vusb_d-supply = <&ldo15_reg>;
149 vusb_a-supply = <&ldo12_reg>;
150 dr_mode = "peripheral";
151 status = "okay";
152};
153
137&i2c_0 { 154&i2c_0 {
138 #address-cells = <1>; 155 #address-cells = <1>;
139 #size-cells = <0>; 156 #size-cells = <0>;
@@ -420,6 +437,46 @@
420 status = "okay"; 437 status = "okay";
421}; 438};
422 439
440&ppmu_dmc0 {
441 status = "okay";
442
443 events {
444 ppmu_dmc0_3: ppmu-event3-dmc0 {
445 event-name = "ppmu-event3-dmc0";
446 };
447 };
448};
449
450&ppmu_dmc1 {
451 status = "okay";
452
453 events {
454 ppmu_dmc1_3: ppmu-event3-dmc1 {
455 event-name = "ppmu-event3-dmc1";
456 };
457 };
458};
459
460&ppmu_leftbus {
461 status = "okay";
462
463 events {
464 ppmu_leftbus_3: ppmu-event3-leftbus {
465 event-name = "ppmu-event3-leftbus";
466 };
467 };
468};
469
470&ppmu_rightbus {
471 status = "okay";
472
473 events {
474 ppmu_rightbus_3: ppmu-event3-rightbus {
475 event-name = "ppmu-event3-rightbus";
476 };
477 };
478};
479
423&xusbxti { 480&xusbxti {
424 clock-frequency = <24000000>; 481 clock-frequency = <24000000>;
425}; 482};
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts
index 80aa8b4c4a3d..0b9906880c0c 100644
--- a/arch/arm/boot/dts/exynos3250-rinato.dts
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -15,6 +15,7 @@
15/dts-v1/; 15/dts-v1/;
16#include "exynos3250.dtsi" 16#include "exynos3250.dtsi"
17#include <dt-bindings/input/input.h> 17#include <dt-bindings/input/input.h>
18#include <dt-bindings/gpio/gpio.h>
18 19
19/ { 20/ {
20 model = "Samsung Rinato board"; 21 model = "Samsung Rinato board";
@@ -37,9 +38,7 @@
37 compatible = "gpio-keys"; 38 compatible = "gpio-keys";
38 39
39 power_key { 40 power_key {
40 interrupt-parent = <&gpx2>; 41 gpios = <&gpx2 7 GPIO_ACTIVE_LOW>;
41 interrupts = <7 0>;
42 gpios = <&gpx2 7 1>;
43 linux,code = <KEY_POWER>; 42 linux,code = <KEY_POWER>;
44 label = "power key"; 43 label = "power key";
45 debounce-interval = <10>; 44 debounce-interval = <10>;
@@ -100,6 +99,13 @@
100 }; 99 };
101 }; 100 };
102 }; 101 };
102
103 haptics {
104 compatible = "regulator-haptic";
105 haptic-supply = <&motor_reg>;
106 min-microvolt = <1100000>;
107 max-microvolt = <2700000>;
108 };
103}; 109};
104 110
105&adc { 111&adc {
@@ -125,6 +131,87 @@
125 }; 131 };
126}; 132};
127 133
134&exynos_usbphy {
135 status = "okay";
136};
137
138&hsotg {
139 vusb_d-supply = <&ldo15_reg>;
140 vusb_a-supply = <&ldo12_reg>;
141 dr_mode = "peripheral";
142 status = "okay";
143};
144
145&dsi_0 {
146 vddcore-supply = <&ldo6_reg>;
147 vddio-supply = <&ldo6_reg>;
148 samsung,pll-clock-frequency = <24000000>;
149 status = "okay";
150
151 ports {
152 #address-cells = <1>;
153 #size-cells = <0>;
154
155 port@1 {
156 reg = <1>;
157
158 dsi_out: endpoint {
159 remote-endpoint = <&dsi_in>;
160 samsung,burst-clock-frequency = <250000000>;
161 samsung,esc-clock-frequency = <20000000>;
162 };
163 };
164 };
165
166 panel@0 {
167 compatible = "samsung,s6e63j0x03";
168 reg = <0>;
169 vdd3-supply = <&ldo16_reg>;
170 vci-supply = <&ldo20_reg>;
171 reset-gpios = <&gpe0 1 0>;
172 te-gpios = <&gpx0 6 0>;
173 power-on-delay= <30>;
174 power-off-delay= <120>;
175 reset-delay = <5>;
176 init-delay = <100>;
177 flip-horizontal;
178 flip-vertical;
179 panel-width-mm = <29>;
180 panel-height-mm = <29>;
181
182 display-timings {
183 timing-0 {
184 clock-frequency = <0>;
185 hactive = <320>;
186 vactive = <320>;
187 hfront-porch = <1>;
188 hback-porch = <1>;
189 hsync-len = <1>;
190 vfront-porch = <150>;
191 vback-porch = <1>;
192 vsync-len = <2>;
193 };
194 };
195
196 port {
197 dsi_in: endpoint {
198 remote-endpoint = <&dsi_out>;
199 };
200 };
201 };
202};
203
204&fimd {
205 status = "okay";
206
207 i80-if-timings {
208 cs-setup = <0>;
209 wr-setup = <0>;
210 wr-act = <1>;
211 wr-hold = <0>;
212 };
213};
214
128&i2c_0 { 215&i2c_0 {
129 #address-cells = <1>; 216 #address-cells = <1>;
130 #size-cells = <0>; 217 #size-cells = <0>;
@@ -523,6 +610,46 @@
523 status = "okay"; 610 status = "okay";
524}; 611};
525 612
613&ppmu_dmc0 {
614 status = "okay";
615
616 events {
617 ppmu_dmc0_3: ppmu-event3-dmc0 {
618 event-name = "ppmu-event3-dmc0";
619 };
620 };
621};
622
623&ppmu_dmc1 {
624 status = "okay";
625
626 events {
627 ppmu_dmc1_3: ppmu-event3-dmc1 {
628 event-name = "ppmu-event3-dmc1";
629 };
630 };
631};
632
633&ppmu_leftbus {
634 status = "okay";
635
636 events {
637 ppmu_leftbus_3: ppmu-event3-leftbus {
638 event-name = "ppmu-event3-leftbus";
639 };
640 };
641};
642
643&ppmu_rightbus {
644 status = "okay";
645
646 events {
647 ppmu_rightbus_3: ppmu-event3-rightbus {
648 event-name = "ppmu-event3-rightbus";
649 };
650 };
651};
652
526&xusbxti { 653&xusbxti {
527 clock-frequency = <24000000>; 654 clock-frequency = <24000000>;
528}; 655};
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 22465494b796..277b48b0b6f9 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -141,26 +141,31 @@
141 pd_cam: cam-power-domain@10023C00 { 141 pd_cam: cam-power-domain@10023C00 {
142 compatible = "samsung,exynos4210-pd"; 142 compatible = "samsung,exynos4210-pd";
143 reg = <0x10023C00 0x20>; 143 reg = <0x10023C00 0x20>;
144 #power-domain-cells = <0>;
144 }; 145 };
145 146
146 pd_mfc: mfc-power-domain@10023C40 { 147 pd_mfc: mfc-power-domain@10023C40 {
147 compatible = "samsung,exynos4210-pd"; 148 compatible = "samsung,exynos4210-pd";
148 reg = <0x10023C40 0x20>; 149 reg = <0x10023C40 0x20>;
150 #power-domain-cells = <0>;
149 }; 151 };
150 152
151 pd_g3d: g3d-power-domain@10023C60 { 153 pd_g3d: g3d-power-domain@10023C60 {
152 compatible = "samsung,exynos4210-pd"; 154 compatible = "samsung,exynos4210-pd";
153 reg = <0x10023C60 0x20>; 155 reg = <0x10023C60 0x20>;
156 #power-domain-cells = <0>;
154 }; 157 };
155 158
156 pd_lcd0: lcd0-power-domain@10023C80 { 159 pd_lcd0: lcd0-power-domain@10023C80 {
157 compatible = "samsung,exynos4210-pd"; 160 compatible = "samsung,exynos4210-pd";
158 reg = <0x10023C80 0x20>; 161 reg = <0x10023C80 0x20>;
162 #power-domain-cells = <0>;
159 }; 163 };
160 164
161 pd_isp: isp-power-domain@10023CA0 { 165 pd_isp: isp-power-domain@10023CA0 {
162 compatible = "samsung,exynos4210-pd"; 166 compatible = "samsung,exynos4210-pd";
163 reg = <0x10023CA0 0x20>; 167 reg = <0x10023CA0 0x20>;
168 #power-domain-cells = <0>;
164 }; 169 };
165 170
166 cmu: clock-controller@10030000 { 171 cmu: clock-controller@10030000 {
@@ -235,7 +240,7 @@
235 interrupts = <0 84 0>, <0 85 0>, <0 86 0>; 240 interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
236 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>; 241 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
237 clock-names = "sclk_fimd", "fimd"; 242 clock-names = "sclk_fimd", "fimd";
238 samsung,power-domain = <&pd_lcd0>; 243 power-domains = <&pd_lcd0>;
239 samsung,sysreg = <&sys_reg>; 244 samsung,sysreg = <&sys_reg>;
240 status = "disabled"; 245 status = "disabled";
241 }; 246 };
@@ -245,7 +250,7 @@
245 reg = <0x11C80000 0x10000>; 250 reg = <0x11C80000 0x10000>;
246 interrupts = <0 83 0>; 251 interrupts = <0 83 0>;
247 samsung,phy-type = <0>; 252 samsung,phy-type = <0>;
248 samsung,power-domain = <&pd_lcd0>; 253 power-domains = <&pd_lcd0>;
249 phys = <&mipi_phy 1>; 254 phys = <&mipi_phy 1>;
250 phy-names = "dsim"; 255 phy-names = "dsim";
251 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>; 256 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
@@ -255,6 +260,17 @@
255 status = "disabled"; 260 status = "disabled";
256 }; 261 };
257 262
263 hsotg: hsotg@12480000 {
264 compatible = "snps,dwc2";
265 reg = <0x12480000 0x20000>;
266 interrupts = <0 141 0>;
267 clocks = <&cmu CLK_USBOTG>;
268 clock-names = "otg";
269 phys = <&exynos_usbphy 0>;
270 phy-names = "usb2-phy";
271 status = "disabled";
272 };
273
258 mshc_0: mshc@12510000 { 274 mshc_0: mshc@12510000 {
259 compatible = "samsung,exynos5250-dw-mshc"; 275 compatible = "samsung,exynos5250-dw-mshc";
260 reg = <0x12510000 0x1000>; 276 reg = <0x12510000 0x1000>;
@@ -279,6 +295,16 @@
279 status = "disabled"; 295 status = "disabled";
280 }; 296 };
281 297
298 exynos_usbphy: exynos-usbphy@125B0000 {
299 compatible = "samsung,exynos3250-usb2-phy";
300 reg = <0x125B0000 0x100>;
301 samsung,pmureg-phandle = <&pmu_system_controller>;
302 clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
303 clock-names = "phy", "ref";
304 #phy-cells = <1>;
305 status = "disabled";
306 };
307
282 amba { 308 amba {
283 compatible = "arm,amba-bus"; 309 compatible = "arm,amba-bus";
284 #address-cells = <1>; 310 #address-cells = <1>;
@@ -327,7 +353,7 @@
327 interrupts = <0 102 0>; 353 interrupts = <0 102 0>;
328 clock-names = "mfc", "sclk_mfc"; 354 clock-names = "mfc", "sclk_mfc";
329 clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>; 355 clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
330 samsung,power-domain = <&pd_mfc>; 356 power-domains = <&pd_mfc>;
331 status = "disabled"; 357 status = "disabled";
332 }; 358 };
333 359
@@ -515,6 +541,80 @@
515 compatible = "arm,cortex-a7-pmu"; 541 compatible = "arm,cortex-a7-pmu";
516 interrupts = <0 18 0>, <0 19 0>; 542 interrupts = <0 18 0>, <0 19 0>;
517 }; 543 };
544
545 ppmu_dmc0: ppmu_dmc0@106a0000 {
546 compatible = "samsung,exynos-ppmu";
547 reg = <0x106a0000 0x2000>;
548 status = "disabled";
549 };
550
551 ppmu_dmc1: ppmu_dmc1@106b0000 {
552 compatible = "samsung,exynos-ppmu";
553 reg = <0x106b0000 0x2000>;
554 status = "disabled";
555 };
556
557 ppmu_cpu: ppmu_cpu@106c0000 {
558 compatible = "samsung,exynos-ppmu";
559 reg = <0x106c0000 0x2000>;
560 status = "disabled";
561 };
562
563 ppmu_rightbus: ppmu_rightbus@112a0000 {
564 compatible = "samsung,exynos-ppmu";
565 reg = <0x112a0000 0x2000>;
566 clocks = <&cmu CLK_PPMURIGHT>;
567 clock-names = "ppmu";
568 status = "disabled";
569 };
570
571 ppmu_leftbus: ppmu_leftbus0@116a0000 {
572 compatible = "samsung,exynos-ppmu";
573 reg = <0x116a0000 0x2000>;
574 clocks = <&cmu CLK_PPMULEFT>;
575 clock-names = "ppmu";
576 status = "disabled";
577 };
578
579 ppmu_camif: ppmu_camif@11ac0000 {
580 compatible = "samsung,exynos-ppmu";
581 reg = <0x11ac0000 0x2000>;
582 clocks = <&cmu CLK_PPMUCAMIF>;
583 clock-names = "ppmu";
584 status = "disabled";
585 };
586
587 ppmu_lcd0: ppmu_lcd0@11e40000 {
588 compatible = "samsung,exynos-ppmu";
589 reg = <0x11e40000 0x2000>;
590 clocks = <&cmu CLK_PPMULCD0>;
591 clock-names = "ppmu";
592 status = "disabled";
593 };
594
595 ppmu_fsys: ppmu_fsys@12630000 {
596 compatible = "samsung,exynos-ppmu";
597 reg = <0x12630000 0x2000>;
598 clocks = <&cmu CLK_PPMUFILE>;
599 clock-names = "ppmu";
600 status = "disabled";
601 };
602
603 ppmu_g3d: ppmu_g3d@13220000 {
604 compatible = "samsung,exynos-ppmu";
605 reg = <0x13220000 0x2000>;
606 clocks = <&cmu CLK_PPMUG3D>;
607 clock-names = "ppmu";
608 status = "disabled";
609 };
610
611 ppmu_mfc: ppmu_mfc@13660000 {
612 compatible = "samsung,exynos-ppmu";
613 reg = <0x13660000 0x2000>;
614 clocks = <&cmu CLK_PPMUMFC_L>;
615 clock-names = "ppmu";
616 status = "disabled";
617 };
518 }; 618 };
519}; 619};
520 620
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index cb6001085f1a..76173cacd450 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -79,41 +79,49 @@
79 compatible = "samsung,s5pv210-mipi-video-phy"; 79 compatible = "samsung,s5pv210-mipi-video-phy";
80 reg = <0x10020710 8>; 80 reg = <0x10020710 8>;
81 #phy-cells = <1>; 81 #phy-cells = <1>;
82 syscon = <&pmu_system_controller>;
82 }; 83 };
83 84
84 pd_mfc: mfc-power-domain@10023C40 { 85 pd_mfc: mfc-power-domain@10023C40 {
85 compatible = "samsung,exynos4210-pd"; 86 compatible = "samsung,exynos4210-pd";
86 reg = <0x10023C40 0x20>; 87 reg = <0x10023C40 0x20>;
88 #power-domain-cells = <0>;
87 }; 89 };
88 90
89 pd_g3d: g3d-power-domain@10023C60 { 91 pd_g3d: g3d-power-domain@10023C60 {
90 compatible = "samsung,exynos4210-pd"; 92 compatible = "samsung,exynos4210-pd";
91 reg = <0x10023C60 0x20>; 93 reg = <0x10023C60 0x20>;
94 #power-domain-cells = <0>;
92 }; 95 };
93 96
94 pd_lcd0: lcd0-power-domain@10023C80 { 97 pd_lcd0: lcd0-power-domain@10023C80 {
95 compatible = "samsung,exynos4210-pd"; 98 compatible = "samsung,exynos4210-pd";
96 reg = <0x10023C80 0x20>; 99 reg = <0x10023C80 0x20>;
100 #power-domain-cells = <0>;
97 }; 101 };
98 102
99 pd_tv: tv-power-domain@10023C20 { 103 pd_tv: tv-power-domain@10023C20 {
100 compatible = "samsung,exynos4210-pd"; 104 compatible = "samsung,exynos4210-pd";
101 reg = <0x10023C20 0x20>; 105 reg = <0x10023C20 0x20>;
106 #power-domain-cells = <0>;
102 }; 107 };
103 108
104 pd_cam: cam-power-domain@10023C00 { 109 pd_cam: cam-power-domain@10023C00 {
105 compatible = "samsung,exynos4210-pd"; 110 compatible = "samsung,exynos4210-pd";
106 reg = <0x10023C00 0x20>; 111 reg = <0x10023C00 0x20>;
112 #power-domain-cells = <0>;
107 }; 113 };
108 114
109 pd_gps: gps-power-domain@10023CE0 { 115 pd_gps: gps-power-domain@10023CE0 {
110 compatible = "samsung,exynos4210-pd"; 116 compatible = "samsung,exynos4210-pd";
111 reg = <0x10023CE0 0x20>; 117 reg = <0x10023CE0 0x20>;
118 #power-domain-cells = <0>;
112 }; 119 };
113 120
114 pd_gps_alive: gps-alive-power-domain@10023D00 { 121 pd_gps_alive: gps-alive-power-domain@10023D00 {
115 compatible = "samsung,exynos4210-pd"; 122 compatible = "samsung,exynos4210-pd";
116 reg = <0x10023D00 0x20>; 123 reg = <0x10023D00 0x20>;
124 #power-domain-cells = <0>;
117 }; 125 };
118 126
119 gic: interrupt-controller@10490000 { 127 gic: interrupt-controller@10490000 {
@@ -150,7 +158,7 @@
150 compatible = "samsung,exynos4210-mipi-dsi"; 158 compatible = "samsung,exynos4210-mipi-dsi";
151 reg = <0x11C80000 0x10000>; 159 reg = <0x11C80000 0x10000>;
152 interrupts = <0 79 0>; 160 interrupts = <0 79 0>;
153 samsung,power-domain = <&pd_lcd0>; 161 power-domains = <&pd_lcd0>;
154 phys = <&mipi_phy 1>; 162 phys = <&mipi_phy 1>;
155 phy-names = "dsim"; 163 phy-names = "dsim";
156 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>; 164 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
@@ -175,7 +183,7 @@
175 interrupts = <0 84 0>; 183 interrupts = <0 84 0>;
176 clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>; 184 clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>;
177 clock-names = "fimc", "sclk_fimc"; 185 clock-names = "fimc", "sclk_fimc";
178 samsung,power-domain = <&pd_cam>; 186 power-domains = <&pd_cam>;
179 samsung,sysreg = <&sys_reg>; 187 samsung,sysreg = <&sys_reg>;
180 status = "disabled"; 188 status = "disabled";
181 }; 189 };
@@ -186,7 +194,7 @@
186 interrupts = <0 85 0>; 194 interrupts = <0 85 0>;
187 clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>; 195 clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>;
188 clock-names = "fimc", "sclk_fimc"; 196 clock-names = "fimc", "sclk_fimc";
189 samsung,power-domain = <&pd_cam>; 197 power-domains = <&pd_cam>;
190 samsung,sysreg = <&sys_reg>; 198 samsung,sysreg = <&sys_reg>;
191 status = "disabled"; 199 status = "disabled";
192 }; 200 };
@@ -197,7 +205,7 @@
197 interrupts = <0 86 0>; 205 interrupts = <0 86 0>;
198 clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>; 206 clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>;
199 clock-names = "fimc", "sclk_fimc"; 207 clock-names = "fimc", "sclk_fimc";
200 samsung,power-domain = <&pd_cam>; 208 power-domains = <&pd_cam>;
201 samsung,sysreg = <&sys_reg>; 209 samsung,sysreg = <&sys_reg>;
202 status = "disabled"; 210 status = "disabled";
203 }; 211 };
@@ -208,7 +216,7 @@
208 interrupts = <0 87 0>; 216 interrupts = <0 87 0>;
209 clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>; 217 clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>;
210 clock-names = "fimc", "sclk_fimc"; 218 clock-names = "fimc", "sclk_fimc";
211 samsung,power-domain = <&pd_cam>; 219 power-domains = <&pd_cam>;
212 samsung,sysreg = <&sys_reg>; 220 samsung,sysreg = <&sys_reg>;
213 status = "disabled"; 221 status = "disabled";
214 }; 222 };
@@ -220,7 +228,7 @@
220 clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>; 228 clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>;
221 clock-names = "csis", "sclk_csis"; 229 clock-names = "csis", "sclk_csis";
222 bus-width = <4>; 230 bus-width = <4>;
223 samsung,power-domain = <&pd_cam>; 231 power-domains = <&pd_cam>;
224 phys = <&mipi_phy 0>; 232 phys = <&mipi_phy 0>;
225 phy-names = "csis"; 233 phy-names = "csis";
226 status = "disabled"; 234 status = "disabled";
@@ -235,7 +243,7 @@
235 clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>; 243 clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>;
236 clock-names = "csis", "sclk_csis"; 244 clock-names = "csis", "sclk_csis";
237 bus-width = <2>; 245 bus-width = <2>;
238 samsung,power-domain = <&pd_cam>; 246 power-domains = <&pd_cam>;
239 phys = <&mipi_phy 2>; 247 phys = <&mipi_phy 2>;
240 phy-names = "csis"; 248 phy-names = "csis";
241 status = "disabled"; 249 status = "disabled";
@@ -400,7 +408,7 @@
400 compatible = "samsung,mfc-v5"; 408 compatible = "samsung,mfc-v5";
401 reg = <0x13400000 0x10000>; 409 reg = <0x13400000 0x10000>;
402 interrupts = <0 94 0>; 410 interrupts = <0 94 0>;
403 samsung,power-domain = <&pd_mfc>; 411 power-domains = <&pd_mfc>;
404 clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>; 412 clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
405 clock-names = "mfc", "sclk_mfc"; 413 clock-names = "mfc", "sclk_mfc";
406 status = "disabled"; 414 status = "disabled";
@@ -650,8 +658,116 @@
650 interrupts = <11 0>, <11 1>, <11 2>; 658 interrupts = <11 0>, <11 1>, <11 2>;
651 clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>; 659 clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
652 clock-names = "sclk_fimd", "fimd"; 660 clock-names = "sclk_fimd", "fimd";
653 samsung,power-domain = <&pd_lcd0>; 661 power-domains = <&pd_lcd0>;
654 samsung,sysreg = <&sys_reg>; 662 samsung,sysreg = <&sys_reg>;
655 status = "disabled"; 663 status = "disabled";
656 }; 664 };
665
666 ppmu_dmc0: ppmu_dmc0@106a0000 {
667 compatible = "samsung,exynos-ppmu";
668 reg = <0x106a0000 0x2000>;
669 clocks = <&clock CLK_PPMUDMC0>;
670 clock-names = "ppmu";
671 status = "disabled";
672 };
673
674 ppmu_dmc1: ppmu_dmc1@106b0000 {
675 compatible = "samsung,exynos-ppmu";
676 reg = <0x106b0000 0x2000>;
677 clocks = <&clock CLK_PPMUDMC1>;
678 clock-names = "ppmu";
679 status = "disabled";
680 };
681
682 ppmu_cpu: ppmu_cpu@106c0000 {
683 compatible = "samsung,exynos-ppmu";
684 reg = <0x106c0000 0x2000>;
685 clocks = <&clock CLK_PPMUCPU>;
686 clock-names = "ppmu";
687 status = "disabled";
688 };
689
690 ppmu_acp: ppmu_acp@10ae0000 {
691 compatible = "samsung,exynos-ppmu";
692 reg = <0x106e0000 0x2000>;
693 status = "disabled";
694 };
695
696 ppmu_rightbus: ppmu_rightbus@112a0000 {
697 compatible = "samsung,exynos-ppmu";
698 reg = <0x112a0000 0x2000>;
699 clocks = <&clock CLK_PPMURIGHT>;
700 clock-names = "ppmu";
701 status = "disabled";
702 };
703
704 ppmu_leftbus: ppmu_leftbus0@116a0000 {
705 compatible = "samsung,exynos-ppmu";
706 reg = <0x116a0000 0x2000>;
707 clocks = <&clock CLK_PPMULEFT>;
708 clock-names = "ppmu";
709 status = "disabled";
710 };
711
712 ppmu_camif: ppmu_camif@11ac0000 {
713 compatible = "samsung,exynos-ppmu";
714 reg = <0x11ac0000 0x2000>;
715 clocks = <&clock CLK_PPMUCAMIF>;
716 clock-names = "ppmu";
717 status = "disabled";
718 };
719
720 ppmu_lcd0: ppmu_lcd0@11e40000 {
721 compatible = "samsung,exynos-ppmu";
722 reg = <0x11e40000 0x2000>;
723 clocks = <&clock CLK_PPMULCD0>;
724 clock-names = "ppmu";
725 status = "disabled";
726 };
727
728 ppmu_fsys: ppmu_g3d@12630000 {
729 compatible = "samsung,exynos-ppmu";
730 reg = <0x12630000 0x2000>;
731 status = "disabled";
732 };
733
734 ppmu_image: ppmu_image@12aa0000 {
735 compatible = "samsung,exynos-ppmu";
736 reg = <0x12aa0000 0x2000>;
737 clocks = <&clock CLK_PPMUIMAGE>;
738 clock-names = "ppmu";
739 status = "disabled";
740 };
741
742 ppmu_tv: ppmu_tv@12e40000 {
743 compatible = "samsung,exynos-ppmu";
744 reg = <0x12e40000 0x2000>;
745 clocks = <&clock CLK_PPMUTV>;
746 clock-names = "ppmu";
747 status = "disabled";
748 };
749
750 ppmu_g3d: ppmu_g3d@13220000 {
751 compatible = "samsung,exynos-ppmu";
752 reg = <0x13220000 0x2000>;
753 clocks = <&clock CLK_PPMUG3D>;
754 clock-names = "ppmu";
755 status = "disabled";
756 };
757
758 ppmu_mfc_left: ppmu_mfc_left@13660000 {
759 compatible = "samsung,exynos-ppmu";
760 reg = <0x13660000 0x2000>;
761 clocks = <&clock CLK_PPMUMFC_L>;
762 clock-names = "ppmu";
763 status = "disabled";
764 };
765
766 ppmu_mfc_right: ppmu_mfc_right@13670000 {
767 compatible = "samsung,exynos-ppmu";
768 reg = <0x13670000 0x2000>;
769 clocks = <&clock CLK_PPMUMFC_R>;
770 clock-names = "ppmu";
771 status = "disabled";
772 };
657}; 773};
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index a406df3d6df8..3d6652a4b6cb 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -92,6 +92,7 @@
92 hsotg@12480000 { 92 hsotg@12480000 {
93 vusb_d-supply = <&vusb_reg>; 93 vusb_d-supply = <&vusb_reg>;
94 vusb_a-supply = <&vusbdac_reg>; 94 vusb_a-supply = <&vusbdac_reg>;
95 dr_mode = "peripheral";
95 status = "okay"; 96 status = "okay";
96 }; 97 };
97 98
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index 6effb13f98a6..b57e6b82ea20 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -72,6 +72,7 @@
72 hsotg@12480000 { 72 hsotg@12480000 {
73 vusb_d-supply = <&ldo3_reg>; 73 vusb_d-supply = <&ldo3_reg>;
74 vusb_a-supply = <&ldo8_reg>; 74 vusb_a-supply = <&ldo8_reg>;
75 dr_mode = "peripheral";
75 status = "okay"; 76 status = "okay";
76 }; 77 };
77 78
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 8e45ea44317e..67c832c9dcf1 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -79,6 +79,7 @@
79 pd_lcd1: lcd1-power-domain@10023CA0 { 79 pd_lcd1: lcd1-power-domain@10023CA0 {
80 compatible = "samsung,exynos4210-pd"; 80 compatible = "samsung,exynos4210-pd";
81 reg = <0x10023CA0 0x20>; 81 reg = <0x10023CA0 0x20>;
82 #power-domain-cells = <0>;
82 }; 83 };
83 84
84 l2c: l2-cache-controller@10502000 { 85 l2c: l2-cache-controller@10502000 {
@@ -201,4 +202,12 @@
201 samsung,lcd-wb; 202 samsung,lcd-wb;
202 }; 203 };
203 }; 204 };
205
206 ppmu_lcd1: ppmu_lcd1@12240000 {
207 compatible = "samsung,exynos-ppmu";
208 reg = <0x12240000 0x2000>;
209 clocks = <&clock CLK_PPMULCD1>;
210 clock-names = "ppmu";
211 status = "disabled";
212 };
204}; 213};
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index 2c43d1859308..de80b5bba204 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -402,6 +402,7 @@
402 }; 402 };
403 403
404 hsotg@12480000 { 404 hsotg@12480000 {
405 dr_mode = "peripheral";
405 status = "okay"; 406 status = "okay";
406 vusb_d-supply = <&ldo15_reg>; 407 vusb_d-supply = <&ldo15_reg>;
407 vusb_a-supply = <&ldo12_reg>; 408 vusb_a-supply = <&ldo12_reg>;
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
index 5fbb01335a0f..21f748083586 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -15,6 +15,7 @@
15/dts-v1/; 15/dts-v1/;
16#include "exynos4412.dtsi" 16#include "exynos4412.dtsi"
17#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/gpio/gpio.h>
18#include <dt-bindings/interrupt-controller/irq.h>
18 19
19/ { 20/ {
20 model = "Samsung Trats 2 based on Exynos4412"; 21 model = "Samsung Trats 2 based on Exynos4412";
@@ -24,6 +25,7 @@
24 i2c9 = &i2c_ak8975; 25 i2c9 = &i2c_ak8975;
25 i2c10 = &i2c_cm36651; 26 i2c10 = &i2c_cm36651;
26 i2c11 = &i2c_max77693; 27 i2c11 = &i2c_max77693;
28 i2c12 = &i2c_max77693_fuel;
27 }; 29 };
28 30
29 memory { 31 memory {
@@ -57,15 +59,6 @@
57 #address-cells = <1>; 59 #address-cells = <1>;
58 #size-cells = <0>; 60 #size-cells = <0>;
59 61
60 vemmc_reg: regulator-0 {
61 compatible = "regulator-fixed";
62 regulator-name = "VMEM_VDD_2.8V";
63 regulator-min-microvolt = <2800000>;
64 regulator-max-microvolt = <2800000>;
65 gpio = <&gpk0 2 0>;
66 enable-active-high;
67 };
68
69 cam_io_reg: voltage-regulator-1 { 62 cam_io_reg: voltage-regulator-1 {
70 compatible = "regulator-fixed"; 63 compatible = "regulator-fixed";
71 regulator-name = "CAM_SENSOR_A"; 64 regulator-name = "CAM_SENSOR_A";
@@ -93,16 +86,6 @@
93 enable-active-high; 86 enable-active-high;
94 }; 87 };
95 88
96 cam_isp_core_reg: voltage-regulator-4 {
97 compatible = "regulator-fixed";
98 regulator-name = "CAM_ISP_CORE_1.2V_EN";
99 regulator-min-microvolt = <1200000>;
100 regulator-max-microvolt = <1200000>;
101 gpio = <&gpm0 3 0>;
102 enable-active-high;
103 regulator-always-on;
104 };
105
106 ps_als_reg: voltage-regulator-5 { 89 ps_als_reg: voltage-regulator-5 {
107 compatible = "regulator-fixed"; 90 compatible = "regulator-fixed";
108 regulator-name = "LED_A_3.0V"; 91 regulator-name = "LED_A_3.0V";
@@ -204,6 +187,25 @@
204 }; 187 };
205 }; 188 };
206 189
190 i2c@138A0000 {
191 samsung,i2c-sda-delay = <100>;
192 samsung,i2c-slave-addr = <0x10>;
193 samsung,i2c-max-bus-freq = <100000>;
194 pinctrl-0 = <&i2c4_bus>;
195 pinctrl-names = "default";
196 status = "okay";
197
198 wm1811: wm1811@1a {
199 compatible = "wlf,wm1811";
200 reg = <0x1a>;
201 clocks = <&pmu_system_controller 0>;
202 clock-names = "MCLK1";
203 DCVDD-supply = <&ldo3_reg>;
204 DBVDD1-supply = <&ldo3_reg>;
205 wlf,ldo1ena = <&gpj0 4 0>;
206 };
207 };
208
207 i2c@138D0000 { 209 i2c@138D0000 {
208 samsung,i2c-sda-delay = <100>; 210 samsung,i2c-sda-delay = <100>;
209 samsung,i2c-slave-addr = <0x10>; 211 samsung,i2c-slave-addr = <0x10>;
@@ -226,7 +228,6 @@
226 regulator-min-microvolt = <1000000>; 228 regulator-min-microvolt = <1000000>;
227 regulator-max-microvolt = <1000000>; 229 regulator-max-microvolt = <1000000>;
228 regulator-always-on; 230 regulator-always-on;
229 regulator-mem-on;
230 }; 231 };
231 232
232 ldo2_reg: ldo2 { 233 ldo2_reg: ldo2 {
@@ -235,7 +236,9 @@
235 regulator-min-microvolt = <1200000>; 236 regulator-min-microvolt = <1200000>;
236 regulator-max-microvolt = <1200000>; 237 regulator-max-microvolt = <1200000>;
237 regulator-always-on; 238 regulator-always-on;
238 regulator-mem-on; 239 regulator-state-mem {
240 regulator-on-in-suspend;
241 };
239 }; 242 };
240 243
241 ldo3_reg: ldo3 { 244 ldo3_reg: ldo3 {
@@ -244,7 +247,6 @@
244 regulator-min-microvolt = <1800000>; 247 regulator-min-microvolt = <1800000>;
245 regulator-max-microvolt = <1800000>; 248 regulator-max-microvolt = <1800000>;
246 regulator-always-on; 249 regulator-always-on;
247 regulator-mem-on;
248 }; 250 };
249 251
250 ldo4_reg: ldo4 { 252 ldo4_reg: ldo4 {
@@ -253,7 +255,6 @@
253 regulator-min-microvolt = <2800000>; 255 regulator-min-microvolt = <2800000>;
254 regulator-max-microvolt = <2800000>; 256 regulator-max-microvolt = <2800000>;
255 regulator-always-on; 257 regulator-always-on;
256 regulator-mem-on;
257 }; 258 };
258 259
259 ldo5_reg: ldo5 { 260 ldo5_reg: ldo5 {
@@ -262,7 +263,6 @@
262 regulator-min-microvolt = <1800000>; 263 regulator-min-microvolt = <1800000>;
263 regulator-max-microvolt = <1800000>; 264 regulator-max-microvolt = <1800000>;
264 regulator-always-on; 265 regulator-always-on;
265 regulator-mem-on;
266 }; 266 };
267 267
268 ldo6_reg: ldo6 { 268 ldo6_reg: ldo6 {
@@ -271,7 +271,9 @@
271 regulator-min-microvolt = <1000000>; 271 regulator-min-microvolt = <1000000>;
272 regulator-max-microvolt = <1000000>; 272 regulator-max-microvolt = <1000000>;
273 regulator-always-on; 273 regulator-always-on;
274 regulator-mem-on; 274 regulator-state-mem {
275 regulator-on-in-suspend;
276 };
275 }; 277 };
276 278
277 ldo7_reg: ldo7 { 279 ldo7_reg: ldo7 {
@@ -280,7 +282,9 @@
280 regulator-min-microvolt = <1000000>; 282 regulator-min-microvolt = <1000000>;
281 regulator-max-microvolt = <1000000>; 283 regulator-max-microvolt = <1000000>;
282 regulator-always-on; 284 regulator-always-on;
283 regulator-mem-on; 285 regulator-state-mem {
286 regulator-on-in-suspend;
287 };
284 }; 288 };
285 289
286 ldo8_reg: ldo8 { 290 ldo8_reg: ldo8 {
@@ -288,7 +292,9 @@
288 regulator-name = "VMIPI_1.0V"; 292 regulator-name = "VMIPI_1.0V";
289 regulator-min-microvolt = <1000000>; 293 regulator-min-microvolt = <1000000>;
290 regulator-max-microvolt = <1000000>; 294 regulator-max-microvolt = <1000000>;
291 regulator-mem-off; 295 regulator-state-mem {
296 regulator-off-in-suspend;
297 };
292 }; 298 };
293 299
294 ldo9_reg: ldo9 { 300 ldo9_reg: ldo9 {
@@ -296,7 +302,6 @@
296 regulator-name = "CAM_ISP_MIPI_1.2V"; 302 regulator-name = "CAM_ISP_MIPI_1.2V";
297 regulator-min-microvolt = <1200000>; 303 regulator-min-microvolt = <1200000>;
298 regulator-max-microvolt = <1200000>; 304 regulator-max-microvolt = <1200000>;
299 regulator-mem-idle;
300 }; 305 };
301 306
302 ldo10_reg: ldo10 { 307 ldo10_reg: ldo10 {
@@ -304,7 +309,9 @@
304 regulator-name = "VMIPI_1.8V"; 309 regulator-name = "VMIPI_1.8V";
305 regulator-min-microvolt = <1800000>; 310 regulator-min-microvolt = <1800000>;
306 regulator-max-microvolt = <1800000>; 311 regulator-max-microvolt = <1800000>;
307 regulator-mem-off; 312 regulator-state-mem {
313 regulator-off-in-suspend;
314 };
308 }; 315 };
309 316
310 ldo11_reg: ldo11 { 317 ldo11_reg: ldo11 {
@@ -313,7 +320,9 @@
313 regulator-min-microvolt = <1950000>; 320 regulator-min-microvolt = <1950000>;
314 regulator-max-microvolt = <1950000>; 321 regulator-max-microvolt = <1950000>;
315 regulator-always-on; 322 regulator-always-on;
316 regulator-mem-off; 323 regulator-state-mem {
324 regulator-off-in-suspend;
325 };
317 }; 326 };
318 327
319 ldo12_reg: ldo12 { 328 ldo12_reg: ldo12 {
@@ -321,7 +330,9 @@
321 regulator-name = "VUOTG_3.0V"; 330 regulator-name = "VUOTG_3.0V";
322 regulator-min-microvolt = <3000000>; 331 regulator-min-microvolt = <3000000>;
323 regulator-max-microvolt = <3000000>; 332 regulator-max-microvolt = <3000000>;
324 regulator-mem-off; 333 regulator-state-mem {
334 regulator-off-in-suspend;
335 };
325 }; 336 };
326 337
327 ldo13_reg: ldo13 { 338 ldo13_reg: ldo13 {
@@ -329,7 +340,6 @@
329 regulator-name = "NFC_AVDD_1.8V"; 340 regulator-name = "NFC_AVDD_1.8V";
330 regulator-min-microvolt = <1800000>; 341 regulator-min-microvolt = <1800000>;
331 regulator-max-microvolt = <1800000>; 342 regulator-max-microvolt = <1800000>;
332 regulator-mem-idle;
333 }; 343 };
334 344
335 ldo14_reg: ldo14 { 345 ldo14_reg: ldo14 {
@@ -338,7 +348,9 @@
338 regulator-min-microvolt = <1950000>; 348 regulator-min-microvolt = <1950000>;
339 regulator-max-microvolt = <1950000>; 349 regulator-max-microvolt = <1950000>;
340 regulator-always-on; 350 regulator-always-on;
341 regulator-mem-off; 351 regulator-state-mem {
352 regulator-off-in-suspend;
353 };
342 }; 354 };
343 355
344 ldo15_reg: ldo15 { 356 ldo15_reg: ldo15 {
@@ -346,7 +358,9 @@
346 regulator-name = "VHSIC_1.0V"; 358 regulator-name = "VHSIC_1.0V";
347 regulator-min-microvolt = <1000000>; 359 regulator-min-microvolt = <1000000>;
348 regulator-max-microvolt = <1000000>; 360 regulator-max-microvolt = <1000000>;
349 regulator-mem-off; 361 regulator-state-mem {
362 regulator-on-in-suspend;
363 };
350 }; 364 };
351 365
352 ldo16_reg: ldo16 { 366 ldo16_reg: ldo16 {
@@ -354,7 +368,9 @@
354 regulator-name = "VHSIC_1.8V"; 368 regulator-name = "VHSIC_1.8V";
355 regulator-min-microvolt = <1800000>; 369 regulator-min-microvolt = <1800000>;
356 regulator-max-microvolt = <1800000>; 370 regulator-max-microvolt = <1800000>;
357 regulator-mem-off; 371 regulator-state-mem {
372 regulator-on-in-suspend;
373 };
358 }; 374 };
359 375
360 ldo17_reg: ldo17 { 376 ldo17_reg: ldo17 {
@@ -362,7 +378,6 @@
362 regulator-name = "CAM_SENSOR_CORE_1.2V"; 378 regulator-name = "CAM_SENSOR_CORE_1.2V";
363 regulator-min-microvolt = <1200000>; 379 regulator-min-microvolt = <1200000>;
364 regulator-max-microvolt = <1200000>; 380 regulator-max-microvolt = <1200000>;
365 regulator-mem-idle;
366 }; 381 };
367 382
368 ldo18_reg: ldo18 { 383 ldo18_reg: ldo18 {
@@ -370,7 +385,6 @@
370 regulator-name = "CAM_ISP_SEN_IO_1.8V"; 385 regulator-name = "CAM_ISP_SEN_IO_1.8V";
371 regulator-min-microvolt = <1800000>; 386 regulator-min-microvolt = <1800000>;
372 regulator-max-microvolt = <1800000>; 387 regulator-max-microvolt = <1800000>;
373 regulator-mem-idle;
374 }; 388 };
375 389
376 ldo19_reg: ldo19 { 390 ldo19_reg: ldo19 {
@@ -378,7 +392,6 @@
378 regulator-name = "VT_CAM_1.8V"; 392 regulator-name = "VT_CAM_1.8V";
379 regulator-min-microvolt = <1800000>; 393 regulator-min-microvolt = <1800000>;
380 regulator-max-microvolt = <1800000>; 394 regulator-max-microvolt = <1800000>;
381 regulator-mem-idle;
382 }; 395 };
383 396
384 ldo20_reg: ldo20 { 397 ldo20_reg: ldo20 {
@@ -386,7 +399,6 @@
386 regulator-name = "VDDQ_PRE_1.8V"; 399 regulator-name = "VDDQ_PRE_1.8V";
387 regulator-min-microvolt = <1800000>; 400 regulator-min-microvolt = <1800000>;
388 regulator-max-microvolt = <1800000>; 401 regulator-max-microvolt = <1800000>;
389 regulator-mem-idle;
390 }; 402 };
391 403
392 ldo21_reg: ldo21 { 404 ldo21_reg: ldo21 {
@@ -394,7 +406,7 @@
394 regulator-name = "VTF_2.8V"; 406 regulator-name = "VTF_2.8V";
395 regulator-min-microvolt = <2800000>; 407 regulator-min-microvolt = <2800000>;
396 regulator-max-microvolt = <2800000>; 408 regulator-max-microvolt = <2800000>;
397 regulator-mem-idle; 409 maxim,ena-gpios = <&gpy2 0 GPIO_ACTIVE_HIGH>;
398 }; 410 };
399 411
400 ldo22_reg: ldo22 { 412 ldo22_reg: ldo22 {
@@ -402,6 +414,7 @@
402 regulator-name = "VMEM_VDD_2.8V"; 414 regulator-name = "VMEM_VDD_2.8V";
403 regulator-min-microvolt = <2800000>; 415 regulator-min-microvolt = <2800000>;
404 regulator-max-microvolt = <2800000>; 416 regulator-max-microvolt = <2800000>;
417 maxim,ena-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>;
405 }; 418 };
406 419
407 ldo23_reg: ldo23 { 420 ldo23_reg: ldo23 {
@@ -409,7 +422,6 @@
409 regulator-name = "TSP_AVDD_3.3V"; 422 regulator-name = "TSP_AVDD_3.3V";
410 regulator-min-microvolt = <3300000>; 423 regulator-min-microvolt = <3300000>;
411 regulator-max-microvolt = <3300000>; 424 regulator-max-microvolt = <3300000>;
412 regulator-mem-idle;
413 }; 425 };
414 426
415 ldo24_reg: ldo24 { 427 ldo24_reg: ldo24 {
@@ -417,7 +429,6 @@
417 regulator-name = "TSP_VDD_1.8V"; 429 regulator-name = "TSP_VDD_1.8V";
418 regulator-min-microvolt = <1800000>; 430 regulator-min-microvolt = <1800000>;
419 regulator-max-microvolt = <1800000>; 431 regulator-max-microvolt = <1800000>;
420 regulator-mem-idle;
421 }; 432 };
422 433
423 ldo25_reg: ldo25 { 434 ldo25_reg: ldo25 {
@@ -425,7 +436,6 @@
425 regulator-name = "LCD_VCC_3.3V"; 436 regulator-name = "LCD_VCC_3.3V";
426 regulator-min-microvolt = <2800000>; 437 regulator-min-microvolt = <2800000>;
427 regulator-max-microvolt = <2800000>; 438 regulator-max-microvolt = <2800000>;
428 regulator-mem-idle;
429 }; 439 };
430 440
431 ldo26_reg: ldo26 { 441 ldo26_reg: ldo26 {
@@ -433,7 +443,6 @@
433 regulator-name = "MOTOR_VCC_3.0V"; 443 regulator-name = "MOTOR_VCC_3.0V";
434 regulator-min-microvolt = <3000000>; 444 regulator-min-microvolt = <3000000>;
435 regulator-max-microvolt = <3000000>; 445 regulator-max-microvolt = <3000000>;
436 regulator-mem-idle;
437 }; 446 };
438 447
439 buck1_reg: buck1 { 448 buck1_reg: buck1 {
@@ -443,7 +452,9 @@
443 regulator-max-microvolt = <1100000>; 452 regulator-max-microvolt = <1100000>;
444 regulator-always-on; 453 regulator-always-on;
445 regulator-boot-on; 454 regulator-boot-on;
446 regulator-mem-off; 455 regulator-state-mem {
456 regulator-off-in-suspend;
457 };
447 }; 458 };
448 459
449 buck2_reg: buck2 { 460 buck2_reg: buck2 {
@@ -453,7 +464,9 @@
453 regulator-max-microvolt = <1500000>; 464 regulator-max-microvolt = <1500000>;
454 regulator-always-on; 465 regulator-always-on;
455 regulator-boot-on; 466 regulator-boot-on;
456 regulator-mem-off; 467 regulator-state-mem {
468 regulator-on-in-suspend;
469 };
457 }; 470 };
458 471
459 buck3_reg: buck3 { 472 buck3_reg: buck3 {
@@ -463,7 +476,9 @@
463 regulator-max-microvolt = <1150000>; 476 regulator-max-microvolt = <1150000>;
464 regulator-always-on; 477 regulator-always-on;
465 regulator-boot-on; 478 regulator-boot-on;
466 regulator-mem-off; 479 regulator-state-mem {
480 regulator-off-in-suspend;
481 };
467 }; 482 };
468 483
469 buck4_reg: buck4 { 484 buck4_reg: buck4 {
@@ -472,7 +487,9 @@
472 regulator-min-microvolt = <850000>; 487 regulator-min-microvolt = <850000>;
473 regulator-max-microvolt = <1150000>; 488 regulator-max-microvolt = <1150000>;
474 regulator-boot-on; 489 regulator-boot-on;
475 regulator-mem-off; 490 regulator-state-mem {
491 regulator-off-in-suspend;
492 };
476 }; 493 };
477 494
478 buck5_reg: buck5 { 495 buck5_reg: buck5 {
@@ -504,6 +521,7 @@
504 regulator-name = "VMEM_VDDF_3.0V"; 521 regulator-name = "VMEM_VDDF_3.0V";
505 regulator-min-microvolt = <2850000>; 522 regulator-min-microvolt = <2850000>;
506 regulator-max-microvolt = <2850000>; 523 regulator-max-microvolt = <2850000>;
524 maxim,ena-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>;
507 }; 525 };
508 526
509 buck9_reg: buck9 { 527 buck9_reg: buck9 {
@@ -511,7 +529,7 @@
511 regulator-name = "CAM_ISP_CORE_1.2V"; 529 regulator-name = "CAM_ISP_CORE_1.2V";
512 regulator-min-microvolt = <1000000>; 530 regulator-min-microvolt = <1000000>;
513 regulator-max-microvolt = <1200000>; 531 regulator-max-microvolt = <1200000>;
514 regulator-mem-off; 532 maxim,ena-gpios = <&gpm0 3 GPIO_ACTIVE_HIGH>;
515 }; 533 };
516 }; 534 };
517 }; 535 };
@@ -550,6 +568,32 @@
550 haptic-supply = <&ldo26_reg>; 568 haptic-supply = <&ldo26_reg>;
551 pwms = <&pwm 0 38022 0>; 569 pwms = <&pwm 0 38022 0>;
552 }; 570 };
571
572 charger {
573 compatible = "maxim,max77693-charger";
574
575 maxim,constant-microvolt = <4350000>;
576 maxim,min-system-microvolt = <3600000>;
577 maxim,thermal-regulation-celsius = <100>;
578 maxim,battery-overcurrent-microamp = <3500000>;
579 maxim,charge-input-threshold-microvolt = <4300000>;
580 };
581 };
582 };
583
584 i2c_max77693_fuel: i2c-gpio-3 {
585 compatible = "i2c-gpio";
586 gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>, <&gpf1 4 GPIO_ACTIVE_HIGH>;
587 i2c-gpio,delay-us = <2>;
588 #address-cells = <1>;
589 #size-cells = <0>;
590 status = "okay";
591
592 max77693-fuel-gauge@36 {
593 compatible = "maxim,max17047";
594 interrupt-parent = <&gpx2>;
595 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
596 reg = <0x36>;
553 }; 597 };
554 }; 598 };
555 599
@@ -558,7 +602,7 @@
558 broken-cd; 602 broken-cd;
559 non-removable; 603 non-removable;
560 card-detect-delay = <200>; 604 card-detect-delay = <200>;
561 vmmc-supply = <&vemmc_reg>; 605 vmmc-supply = <&ldo22_reg>;
562 clock-frequency = <400000000>; 606 clock-frequency = <400000000>;
563 samsung,dw-mshc-ciu-div = <0>; 607 samsung,dw-mshc-ciu-div = <0>;
564 samsung,dw-mshc-sdr-timing = <2 3>; 608 samsung,dw-mshc-sdr-timing = <2 3>;
@@ -722,8 +766,8 @@
722 status = "okay"; 766 status = "okay";
723 assigned-clocks = <&clock CLK_MOUT_CAM0>, 767 assigned-clocks = <&clock CLK_MOUT_CAM0>,
724 <&clock CLK_MOUT_CAM1>; 768 <&clock CLK_MOUT_CAM1>;
725 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>, 769 assigned-clock-parents = <&clock CLK_XUSBXTI>,
726 <&clock CLK_MOUT_MPLL_USER_T>; 770 <&clock CLK_XUSBXTI>;
727 771
728 fimc_0: fimc@11800000 { 772 fimc_0: fimc@11800000 {
729 status = "okay"; 773 status = "okay";
@@ -839,6 +883,24 @@
839 }; 883 };
840 }; 884 };
841 885
886 i2s0: i2s@03830000 {
887 pinctrl-0 = <&i2s0_bus>;
888 pinctrl-names = "default";
889 status = "okay";
890 };
891
892 sound {
893 compatible = "samsung,trats2-audio";
894 samsung,i2s-controller = <&i2s0>;
895 samsung,model = "Trats2";
896 samsung,audio-codec = <&wm1811>;
897 samsung,audio-routing =
898 "SPK", "SPKOUTLN",
899 "SPK", "SPKOUTLP",
900 "SPK", "SPKOUTRN",
901 "SPK", "SPKOUTRP";
902 };
903
842 exynos-usbphy@125B0000 { 904 exynos-usbphy@125B0000 {
843 status = "okay"; 905 status = "okay";
844 }; 906 };
@@ -846,6 +908,7 @@
846 hsotg@12480000 { 908 hsotg@12480000 {
847 vusb_d-supply = <&ldo15_reg>; 909 vusb_d-supply = <&ldo15_reg>;
848 vusb_a-supply = <&ldo12_reg>; 910 vusb_a-supply = <&ldo12_reg>;
911 dr_mode = "peripheral";
849 status = "okay"; 912 status = "okay";
850 }; 913 };
851 914
@@ -866,6 +929,51 @@
866 }; 929 };
867}; 930};
868 931
932&pmu_system_controller {
933 assigned-clocks = <&pmu_system_controller 0>;
934 assigned-clock-parents = <&clock CLK_XUSBXTI>;
935};
936
937&ppmu_dmc0 {
938 status = "okay";
939
940 events {
941 ppmu_dmc0_3: ppmu-event3-dmc0 {
942 event-name = "ppmu-event3-dmc0";
943 };
944 };
945};
946
947&ppmu_dmc1 {
948 status = "okay";
949
950 events {
951 ppmu_dmc1_3: ppmu-event3-dmc1 {
952 event-name = "ppmu-event3-dmc1";
953 };
954 };
955};
956
957&ppmu_leftbus {
958 status = "okay";
959
960 events {
961 ppmu_leftbus_3: ppmu-event3-leftbus {
962 event-name = "ppmu-event3-leftbus";
963 };
964 };
965};
966
967&ppmu_rightbus {
968 status = "okay";
969
970 events {
971 ppmu_rightbus_3: ppmu-event3-rightbus {
972 event-name = "ppmu-event3-rightbus";
973 };
974 };
975};
976
869&pinctrl_0 { 977&pinctrl_0 {
870 pinctrl-names = "default"; 978 pinctrl-names = "default";
871 pinctrl-0 = <&sleep0>; 979 pinctrl-0 = <&sleep0>;
diff --git a/arch/arm/boot/dts/exynos4415.dtsi b/arch/arm/boot/dts/exynos4415.dtsi
index c1c9b37340d9..5caea996e090 100644
--- a/arch/arm/boot/dts/exynos4415.dtsi
+++ b/arch/arm/boot/dts/exynos4415.dtsi
@@ -131,36 +131,43 @@
131 pd_cam: cam-power-domain@10024000 { 131 pd_cam: cam-power-domain@10024000 {
132 compatible = "samsung,exynos4210-pd"; 132 compatible = "samsung,exynos4210-pd";
133 reg = <0x10024000 0x20>; 133 reg = <0x10024000 0x20>;
134 #power-domain-cells = <0>;
134 }; 135 };
135 136
136 pd_tv: tv-power-domain@10024020 { 137 pd_tv: tv-power-domain@10024020 {
137 compatible = "samsung,exynos4210-pd"; 138 compatible = "samsung,exynos4210-pd";
138 reg = <0x10024020 0x20>; 139 reg = <0x10024020 0x20>;
140 #power-domain-cells = <0>;
139 }; 141 };
140 142
141 pd_mfc: mfc-power-domain@10024040 { 143 pd_mfc: mfc-power-domain@10024040 {
142 compatible = "samsung,exynos4210-pd"; 144 compatible = "samsung,exynos4210-pd";
143 reg = <0x10024040 0x20>; 145 reg = <0x10024040 0x20>;
146 #power-domain-cells = <0>;
144 }; 147 };
145 148
146 pd_g3d: g3d-power-domain@10024060 { 149 pd_g3d: g3d-power-domain@10024060 {
147 compatible = "samsung,exynos4210-pd"; 150 compatible = "samsung,exynos4210-pd";
148 reg = <0x10024060 0x20>; 151 reg = <0x10024060 0x20>;
152 #power-domain-cells = <0>;
149 }; 153 };
150 154
151 pd_lcd0: lcd0-power-domain@10024080 { 155 pd_lcd0: lcd0-power-domain@10024080 {
152 compatible = "samsung,exynos4210-pd"; 156 compatible = "samsung,exynos4210-pd";
153 reg = <0x10024080 0x20>; 157 reg = <0x10024080 0x20>;
158 #power-domain-cells = <0>;
154 }; 159 };
155 160
156 pd_isp0: isp0-power-domain@100240A0 { 161 pd_isp0: isp0-power-domain@100240A0 {
157 compatible = "samsung,exynos4210-pd"; 162 compatible = "samsung,exynos4210-pd";
158 reg = <0x100240A0 0x20>; 163 reg = <0x100240A0 0x20>;
164 #power-domain-cells = <0>;
159 }; 165 };
160 166
161 pd_isp1: isp1-power-domain@100240E0 { 167 pd_isp1: isp1-power-domain@100240E0 {
162 compatible = "samsung,exynos4210-pd"; 168 compatible = "samsung,exynos4210-pd";
163 reg = <0x100240E0 0x20>; 169 reg = <0x100240E0 0x20>;
170 #power-domain-cells = <0>;
164 }; 171 };
165 172
166 cmu: clock-controller@10030000 { 173 cmu: clock-controller@10030000 {
@@ -234,6 +241,33 @@
234 interrupts = <0 240 0>; 241 interrupts = <0 240 0>;
235 }; 242 };
236 243
244 fimd: fimd@11C00000 {
245 compatible = "samsung,exynos4415-fimd";
246 reg = <0x11C00000 0x30000>;
247 interrupt-names = "fifo", "vsync", "lcd_sys";
248 interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
249 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
250 clock-names = "sclk_fimd", "fimd";
251 samsung,power-domain = <&pd_lcd0>;
252 samsung,sysreg = <&sysreg_system_controller>;
253 status = "disabled";
254 };
255
256 dsi_0: dsi@11C80000 {
257 compatible = "samsung,exynos4415-mipi-dsi";
258 reg = <0x11C80000 0x10000>;
259 interrupts = <0 83 0>;
260 samsung,phy-type = <0>;
261 samsung,power-domain = <&pd_lcd0>;
262 phys = <&mipi_phy 1>;
263 phy-names = "dsim";
264 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
265 clock-names = "bus_clk", "pll_clk";
266 #address-cells = <1>;
267 #size-cells = <0>;
268 status = "disabled";
269 };
270
237 hsotg: hsotg@12480000 { 271 hsotg: hsotg@12480000 {
238 compatible = "samsung,s3c6400-hsotg"; 272 compatible = "samsung,s3c6400-hsotg";
239 reg = <0x12480000 0x20000>; 273 reg = <0x12480000 0x20000>;
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index 8bc97c415c9a..f5e0ae780d6c 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -52,6 +52,7 @@
52 pd_isp: isp-power-domain@10023CA0 { 52 pd_isp: isp-power-domain@10023CA0 {
53 compatible = "samsung,exynos4210-pd"; 53 compatible = "samsung,exynos4210-pd";
54 reg = <0x10023CA0 0x20>; 54 reg = <0x10023CA0 0x20>;
55 #power-domain-cells = <0>;
55 }; 56 };
56 57
57 l2c: l2-cache-controller@10502000 { 58 l2c: l2-cache-controller@10502000 {
@@ -209,7 +210,7 @@
209 compatible = "samsung,exynos4212-fimc-lite"; 210 compatible = "samsung,exynos4212-fimc-lite";
210 reg = <0x12390000 0x1000>; 211 reg = <0x12390000 0x1000>;
211 interrupts = <0 105 0>; 212 interrupts = <0 105 0>;
212 samsung,power-domain = <&pd_isp>; 213 power-domains = <&pd_isp>;
213 clocks = <&clock CLK_FIMC_LITE0>; 214 clocks = <&clock CLK_FIMC_LITE0>;
214 clock-names = "flite"; 215 clock-names = "flite";
215 status = "disabled"; 216 status = "disabled";
@@ -219,7 +220,7 @@
219 compatible = "samsung,exynos4212-fimc-lite"; 220 compatible = "samsung,exynos4212-fimc-lite";
220 reg = <0x123A0000 0x1000>; 221 reg = <0x123A0000 0x1000>;
221 interrupts = <0 106 0>; 222 interrupts = <0 106 0>;
222 samsung,power-domain = <&pd_isp>; 223 power-domains = <&pd_isp>;
223 clocks = <&clock CLK_FIMC_LITE1>; 224 clocks = <&clock CLK_FIMC_LITE1>;
224 clock-names = "flite"; 225 clock-names = "flite";
225 status = "disabled"; 226 status = "disabled";
@@ -229,7 +230,7 @@
229 compatible = "samsung,exynos4212-fimc-is", "simple-bus"; 230 compatible = "samsung,exynos4212-fimc-is", "simple-bus";
230 reg = <0x12000000 0x260000>; 231 reg = <0x12000000 0x260000>;
231 interrupts = <0 90 0>, <0 95 0>; 232 interrupts = <0 90 0>, <0 95 0>;
232 samsung,power-domain = <&pd_isp>; 233 power-domains = <&pd_isp>;
233 clocks = <&clock CLK_FIMC_LITE0>, 234 clocks = <&clock CLK_FIMC_LITE0>,
234 <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>, 235 <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>,
235 <&clock CLK_PPMUISPMX>, 236 <&clock CLK_PPMUISPMX>,
@@ -239,7 +240,7 @@
239 <&clock CLK_DIV_ISP0>,<&clock CLK_DIV_ISP1>, 240 <&clock CLK_DIV_ISP0>,<&clock CLK_DIV_ISP1>,
240 <&clock CLK_DIV_MCUISP0>, 241 <&clock CLK_DIV_MCUISP0>,
241 <&clock CLK_DIV_MCUISP1>, 242 <&clock CLK_DIV_MCUISP1>,
242 <&clock CLK_SCLK_UART_ISP>, 243 <&clock CLK_UART_ISP_SCLK>,
243 <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>, 244 <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>,
244 <&clock CLK_ACLK400_MCUISP>, 245 <&clock CLK_ACLK400_MCUISP>,
245 <&clock CLK_DIV_ACLK400_MCUISP>; 246 <&clock CLK_DIV_ACLK400_MCUISP>;
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index effaf2af41bc..b9aeec430527 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -33,6 +33,8 @@
33 33
34 gpio-keys { 34 gpio-keys {
35 compatible = "gpio-keys"; 35 compatible = "gpio-keys";
36 pinctrl-names = "default";
37 pinctrl-0 = <&power_key_irq &lid_irq>;
36 38
37 power { 39 power {
38 label = "Power"; 40 label = "Power";
@@ -540,6 +542,13 @@
540}; 542};
541 543
542&pinctrl_0 { 544&pinctrl_0 {
545 power_key_irq: power-key-irq {
546 samsung,pins = "gpx1-3";
547 samsung,pin-function = <0xf>;
548 samsung,pin-pud = <0>;
549 samsung,pin-drv = <0>;
550 };
551
543 ec_irq: ec-irq { 552 ec_irq: ec-irq {
544 samsung,pins = "gpx1-6"; 553 samsung,pins = "gpx1-6";
545 samsung,pin-function = <0>; 554 samsung,pin-function = <0>;
@@ -575,6 +584,13 @@
575 samsung,pin-drv = <0>; 584 samsung,pin-drv = <0>;
576 }; 585 };
577 586
587 lid_irq: lid-irq {
588 samsung,pins = "gpx3-5";
589 samsung,pin-function = <0xf>;
590 samsung,pin-pud = <0>;
591 samsung,pin-drv = <0>;
592 };
593
578 hdmi_hpd_irq: hdmi-hpd-irq { 594 hdmi_hpd_irq: hdmi-hpd-irq {
579 samsung,pins = "gpx3-7"; 595 samsung,pins = "gpx3-7";
580 samsung,pin-function = <0>; 596 samsung,pin-function = <0>;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index d75c89d7666a..9bb1b0b738f5 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -93,11 +93,13 @@
93 pd_gsc: gsc-power-domain@10044000 { 93 pd_gsc: gsc-power-domain@10044000 {
94 compatible = "samsung,exynos4210-pd"; 94 compatible = "samsung,exynos4210-pd";
95 reg = <0x10044000 0x20>; 95 reg = <0x10044000 0x20>;
96 #power-domain-cells = <0>;
96 }; 97 };
97 98
98 pd_mfc: mfc-power-domain@10044040 { 99 pd_mfc: mfc-power-domain@10044040 {
99 compatible = "samsung,exynos4210-pd"; 100 compatible = "samsung,exynos4210-pd";
100 reg = <0x10044040 0x20>; 101 reg = <0x10044040 0x20>;
102 #power-domain-cells = <0>;
101 }; 103 };
102 104
103 clock: clock-controller@10010000 { 105 clock: clock-controller@10010000 {
@@ -222,7 +224,7 @@
222 compatible = "samsung,mfc-v6"; 224 compatible = "samsung,mfc-v6";
223 reg = <0x11000000 0x10000>; 225 reg = <0x11000000 0x10000>;
224 interrupts = <0 96 0>; 226 interrupts = <0 96 0>;
225 samsung,power-domain = <&pd_mfc>; 227 power-domains = <&pd_mfc>;
226 clocks = <&clock CLK_MFC>; 228 clocks = <&clock CLK_MFC>;
227 clock-names = "mfc"; 229 clock-names = "mfc";
228 }; 230 };
@@ -682,7 +684,7 @@
682 compatible = "samsung,exynos5-gsc"; 684 compatible = "samsung,exynos5-gsc";
683 reg = <0x13e00000 0x1000>; 685 reg = <0x13e00000 0x1000>;
684 interrupts = <0 85 0>; 686 interrupts = <0 85 0>;
685 samsung,power-domain = <&pd_gsc>; 687 power-domains = <&pd_gsc>;
686 clocks = <&clock CLK_GSCL0>; 688 clocks = <&clock CLK_GSCL0>;
687 clock-names = "gscl"; 689 clock-names = "gscl";
688 }; 690 };
@@ -691,7 +693,7 @@
691 compatible = "samsung,exynos5-gsc"; 693 compatible = "samsung,exynos5-gsc";
692 reg = <0x13e10000 0x1000>; 694 reg = <0x13e10000 0x1000>;
693 interrupts = <0 86 0>; 695 interrupts = <0 86 0>;
694 samsung,power-domain = <&pd_gsc>; 696 power-domains = <&pd_gsc>;
695 clocks = <&clock CLK_GSCL1>; 697 clocks = <&clock CLK_GSCL1>;
696 clock-names = "gscl"; 698 clock-names = "gscl";
697 }; 699 };
@@ -700,7 +702,7 @@
700 compatible = "samsung,exynos5-gsc"; 702 compatible = "samsung,exynos5-gsc";
701 reg = <0x13e20000 0x1000>; 703 reg = <0x13e20000 0x1000>;
702 interrupts = <0 87 0>; 704 interrupts = <0 87 0>;
703 samsung,power-domain = <&pd_gsc>; 705 power-domains = <&pd_gsc>;
704 clocks = <&clock CLK_GSCL2>; 706 clocks = <&clock CLK_GSCL2>;
705 clock-names = "gscl"; 707 clock-names = "gscl";
706 }; 708 };
@@ -709,7 +711,7 @@
709 compatible = "samsung,exynos5-gsc"; 711 compatible = "samsung,exynos5-gsc";
710 reg = <0x13e30000 0x1000>; 712 reg = <0x13e30000 0x1000>;
711 interrupts = <0 88 0>; 713 interrupts = <0 88 0>;
712 samsung,power-domain = <&pd_gsc>; 714 power-domains = <&pd_gsc>;
713 clocks = <&clock CLK_GSCL3>; 715 clocks = <&clock CLK_GSCL3>;
714 clock-names = "gscl"; 716 clock-names = "gscl";
715 }; 717 };
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 9a050e19a4dc..c47bb70665c1 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -13,6 +13,7 @@
13#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/clock/maxim,max77802.h> 15#include <dt-bindings/clock/maxim,max77802.h>
16#include <dt-bindings/regulator/maxim,max77802.h>
16#include "exynos5420.dtsi" 17#include "exynos5420.dtsi"
17 18
18/ { 19/ {
@@ -53,7 +54,7 @@
53 compatible = "gpio-keys"; 54 compatible = "gpio-keys";
54 55
55 pinctrl-names = "default"; 56 pinctrl-names = "default";
56 pinctrl-0 = <&power_key_irq>; 57 pinctrl-0 = <&power_key_irq &lid_irq>;
57 58
58 power { 59 power {
59 label = "Power"; 60 label = "Power";
@@ -61,6 +62,15 @@
61 linux,code = <KEY_POWER>; 62 linux,code = <KEY_POWER>;
62 gpio-key,wakeup; 63 gpio-key,wakeup;
63 }; 64 };
65
66 lid-switch {
67 label = "Lid";
68 gpios = <&gpx3 4 GPIO_ACTIVE_LOW>;
69 linux,input-type = <5>; /* EV_SW */
70 linux,code = <0>; /* SW_LID */
71 debounce-interval = <1>;
72 gpio-key,wakeup;
73 };
64 }; 74 };
65 75
66 memory { 76 memory {
@@ -192,6 +202,9 @@
192 regulator-always-on; 202 regulator-always-on;
193 regulator-boot-on; 203 regulator-boot-on;
194 regulator-ramp-delay = <12500>; 204 regulator-ramp-delay = <12500>;
205 regulator-state-mem {
206 regulator-off-in-suspend;
207 };
195 }; 208 };
196 209
197 buck2_reg: BUCK2 { 210 buck2_reg: BUCK2 {
@@ -201,6 +214,9 @@
201 regulator-always-on; 214 regulator-always-on;
202 regulator-boot-on; 215 regulator-boot-on;
203 regulator-ramp-delay = <12500>; 216 regulator-ramp-delay = <12500>;
217 regulator-state-mem {
218 regulator-off-in-suspend;
219 };
204 }; 220 };
205 221
206 buck3_reg: BUCK3 { 222 buck3_reg: BUCK3 {
@@ -210,6 +226,9 @@
210 regulator-always-on; 226 regulator-always-on;
211 regulator-boot-on; 227 regulator-boot-on;
212 regulator-ramp-delay = <12500>; 228 regulator-ramp-delay = <12500>;
229 regulator-state-mem {
230 regulator-off-in-suspend;
231 };
213 }; 232 };
214 233
215 buck4_reg: BUCK4 { 234 buck4_reg: BUCK4 {
@@ -219,6 +238,9 @@
219 regulator-always-on; 238 regulator-always-on;
220 regulator-boot-on; 239 regulator-boot-on;
221 regulator-ramp-delay = <12500>; 240 regulator-ramp-delay = <12500>;
241 regulator-state-mem {
242 regulator-off-in-suspend;
243 };
222 }; 244 };
223 245
224 buck5_reg: BUCK5 { 246 buck5_reg: BUCK5 {
@@ -227,6 +249,9 @@
227 regulator-max-microvolt = <1200000>; 249 regulator-max-microvolt = <1200000>;
228 regulator-always-on; 250 regulator-always-on;
229 regulator-boot-on; 251 regulator-boot-on;
252 regulator-state-mem {
253 regulator-off-in-suspend;
254 };
230 }; 255 };
231 256
232 buck6_reg: BUCK6 { 257 buck6_reg: BUCK6 {
@@ -236,6 +261,9 @@
236 regulator-always-on; 261 regulator-always-on;
237 regulator-boot-on; 262 regulator-boot-on;
238 regulator-ramp-delay = <12500>; 263 regulator-ramp-delay = <12500>;
264 regulator-state-mem {
265 regulator-off-in-suspend;
266 };
239 }; 267 };
240 268
241 buck7_reg: BUCK7 { 269 buck7_reg: BUCK7 {
@@ -244,6 +272,9 @@
244 regulator-max-microvolt = <1350000>; 272 regulator-max-microvolt = <1350000>;
245 regulator-always-on; 273 regulator-always-on;
246 regulator-boot-on; 274 regulator-boot-on;
275 regulator-state-mem {
276 regulator-on-in-suspend;
277 };
247 }; 278 };
248 279
249 buck8_reg: BUCK8 { 280 buck8_reg: BUCK8 {
@@ -252,6 +283,9 @@
252 regulator-max-microvolt = <2850000>; 283 regulator-max-microvolt = <2850000>;
253 regulator-always-on; 284 regulator-always-on;
254 regulator-boot-on; 285 regulator-boot-on;
286 regulator-state-mem {
287 regulator-off-in-suspend;
288 };
255 }; 289 };
256 290
257 buck9_reg: BUCK9 { 291 buck9_reg: BUCK9 {
@@ -260,6 +294,9 @@
260 regulator-max-microvolt = <2000000>; 294 regulator-max-microvolt = <2000000>;
261 regulator-always-on; 295 regulator-always-on;
262 regulator-boot-on; 296 regulator-boot-on;
297 regulator-state-mem {
298 regulator-on-in-suspend;
299 };
263 }; 300 };
264 301
265 buck10_reg: BUCK10 { 302 buck10_reg: BUCK10 {
@@ -268,6 +305,9 @@
268 regulator-max-microvolt = <1800000>; 305 regulator-max-microvolt = <1800000>;
269 regulator-always-on; 306 regulator-always-on;
270 regulator-boot-on; 307 regulator-boot-on;
308 regulator-state-mem {
309 regulator-on-in-suspend;
310 };
271 }; 311 };
272 312
273 ldo1_reg: LDO1 { 313 ldo1_reg: LDO1 {
@@ -275,6 +315,10 @@
275 regulator-min-microvolt = <1000000>; 315 regulator-min-microvolt = <1000000>;
276 regulator-max-microvolt = <1000000>; 316 regulator-max-microvolt = <1000000>;
277 regulator-always-on; 317 regulator-always-on;
318 regulator-state-mem {
319 regulator-on-in-suspend;
320 regulator-mode = <MAX77802_OPMODE_LP>;
321 };
278 }; 322 };
279 323
280 ldo2_reg: LDO2 { 324 ldo2_reg: LDO2 {
@@ -288,6 +332,10 @@
288 regulator-min-microvolt = <1800000>; 332 regulator-min-microvolt = <1800000>;
289 regulator-max-microvolt = <1800000>; 333 regulator-max-microvolt = <1800000>;
290 regulator-always-on; 334 regulator-always-on;
335 regulator-state-mem {
336 regulator-on-in-suspend;
337 regulator-mode = <MAX77802_OPMODE_LP>;
338 };
291 }; 339 };
292 340
293 vqmmc_sdcard: ldo4_reg: LDO4 { 341 vqmmc_sdcard: ldo4_reg: LDO4 {
@@ -295,6 +343,9 @@
295 regulator-min-microvolt = <1800000>; 343 regulator-min-microvolt = <1800000>;
296 regulator-max-microvolt = <2800000>; 344 regulator-max-microvolt = <2800000>;
297 regulator-always-on; 345 regulator-always-on;
346 regulator-state-mem {
347 regulator-off-in-suspend;
348 };
298 }; 349 };
299 350
300 ldo5_reg: LDO5 { 351 ldo5_reg: LDO5 {
@@ -302,6 +353,9 @@
302 regulator-min-microvolt = <1800000>; 353 regulator-min-microvolt = <1800000>;
303 regulator-max-microvolt = <1800000>; 354 regulator-max-microvolt = <1800000>;
304 regulator-always-on; 355 regulator-always-on;
356 regulator-state-mem {
357 regulator-off-in-suspend;
358 };
305 }; 359 };
306 360
307 ldo6_reg: LDO6 { 361 ldo6_reg: LDO6 {
@@ -309,6 +363,9 @@
309 regulator-min-microvolt = <1800000>; 363 regulator-min-microvolt = <1800000>;
310 regulator-max-microvolt = <1800000>; 364 regulator-max-microvolt = <1800000>;
311 regulator-always-on; 365 regulator-always-on;
366 regulator-state-mem {
367 regulator-off-in-suspend;
368 };
312 }; 369 };
313 370
314 ldo7_reg: LDO7 { 371 ldo7_reg: LDO7 {
@@ -322,6 +379,9 @@
322 regulator-min-microvolt = <1000000>; 379 regulator-min-microvolt = <1000000>;
323 regulator-max-microvolt = <1000000>; 380 regulator-max-microvolt = <1000000>;
324 regulator-always-on; 381 regulator-always-on;
382 regulator-state-mem {
383 regulator-off-in-suspend;
384 };
325 }; 385 };
326 386
327 ldo9_reg: LDO9 { 387 ldo9_reg: LDO9 {
@@ -329,6 +389,10 @@
329 regulator-min-microvolt = <1800000>; 389 regulator-min-microvolt = <1800000>;
330 regulator-max-microvolt = <1800000>; 390 regulator-max-microvolt = <1800000>;
331 regulator-always-on; 391 regulator-always-on;
392 regulator-state-mem {
393 regulator-on-in-suspend;
394 regulator-mode = <MAX77802_OPMODE_LP>;
395 };
332 }; 396 };
333 397
334 ldo10_reg: LDO10 { 398 ldo10_reg: LDO10 {
@@ -336,6 +400,9 @@
336 regulator-min-microvolt = <1800000>; 400 regulator-min-microvolt = <1800000>;
337 regulator-max-microvolt = <1800000>; 401 regulator-max-microvolt = <1800000>;
338 regulator-always-on; 402 regulator-always-on;
403 regulator-state-mem {
404 regulator-off-in-suspend;
405 };
339 }; 406 };
340 407
341 ldo11_reg: LDO11 { 408 ldo11_reg: LDO11 {
@@ -343,6 +410,10 @@
343 regulator-min-microvolt = <1800000>; 410 regulator-min-microvolt = <1800000>;
344 regulator-max-microvolt = <1800000>; 411 regulator-max-microvolt = <1800000>;
345 regulator-always-on; 412 regulator-always-on;
413 regulator-state-mem {
414 regulator-on-in-suspend;
415 regulator-mode = <MAX77802_OPMODE_LP>;
416 };
346 }; 417 };
347 418
348 ldo12_reg: LDO12 { 419 ldo12_reg: LDO12 {
@@ -350,6 +421,9 @@
350 regulator-min-microvolt = <3000000>; 421 regulator-min-microvolt = <3000000>;
351 regulator-max-microvolt = <3000000>; 422 regulator-max-microvolt = <3000000>;
352 regulator-always-on; 423 regulator-always-on;
424 regulator-state-mem {
425 regulator-off-in-suspend;
426 };
353 }; 427 };
354 428
355 ldo13_reg: LDO13 { 429 ldo13_reg: LDO13 {
@@ -357,6 +431,10 @@
357 regulator-min-microvolt = <1800000>; 431 regulator-min-microvolt = <1800000>;
358 regulator-max-microvolt = <1800000>; 432 regulator-max-microvolt = <1800000>;
359 regulator-always-on; 433 regulator-always-on;
434 regulator-state-mem {
435 regulator-on-in-suspend;
436 regulator-mode = <MAX77802_OPMODE_LP>;
437 };
360 }; 438 };
361 439
362 ldo14_reg: LDO14 { 440 ldo14_reg: LDO14 {
@@ -364,6 +442,9 @@
364 regulator-min-microvolt = <1800000>; 442 regulator-min-microvolt = <1800000>;
365 regulator-max-microvolt = <1800000>; 443 regulator-max-microvolt = <1800000>;
366 regulator-always-on; 444 regulator-always-on;
445 regulator-state-mem {
446 regulator-off-in-suspend;
447 };
367 }; 448 };
368 449
369 ldo15_reg: LDO15 { 450 ldo15_reg: LDO15 {
@@ -371,6 +452,9 @@
371 regulator-min-microvolt = <1000000>; 452 regulator-min-microvolt = <1000000>;
372 regulator-max-microvolt = <1000000>; 453 regulator-max-microvolt = <1000000>;
373 regulator-always-on; 454 regulator-always-on;
455 regulator-state-mem {
456 regulator-off-in-suspend;
457 };
374 }; 458 };
375 459
376 ldo17_reg: LDO17 { 460 ldo17_reg: LDO17 {
@@ -378,6 +462,9 @@
378 regulator-min-microvolt = <900000>; 462 regulator-min-microvolt = <900000>;
379 regulator-max-microvolt = <1400000>; 463 regulator-max-microvolt = <1400000>;
380 regulator-always-on; 464 regulator-always-on;
465 regulator-state-mem {
466 regulator-off-in-suspend;
467 };
381 }; 468 };
382 469
383 ldo18_reg: LDO18 { 470 ldo18_reg: LDO18 {
@@ -451,6 +538,9 @@
451 regulator-min-microvolt = <1000000>; 538 regulator-min-microvolt = <1000000>;
452 regulator-max-microvolt = <1000000>; 539 regulator-max-microvolt = <1000000>;
453 regulator-always-on; 540 regulator-always-on;
541 regulator-state-mem {
542 regulator-off-in-suspend;
543 };
454 }; 544 };
455 545
456 ldo32_reg: LDO32 { 546 ldo32_reg: LDO32 {
@@ -658,6 +748,13 @@
658 samsung,pin-drv = <0>; 748 samsung,pin-drv = <0>;
659 }; 749 };
660 750
751 lid_irq: lid-irq {
752 samsung,pins = "gpx3-4";
753 samsung,pin-function = <0xf>;
754 samsung,pin-pud = <0>;
755 samsung,pin-drv = <0>;
756 };
757
661 hdmi_hpd_irq: hdmi-hpd-irq { 758 hdmi_hpd_irq: hdmi-hpd-irq {
662 samsung,pins = "gpx3-7"; 759 samsung,pins = "gpx3-7";
663 samsung,pin-function = <0>; 760 samsung,pin-function = <0>;
@@ -815,6 +912,7 @@
815 }; 912 };
816 tps65090_fet5: fet5 { 913 tps65090_fet5: fet5 {
817 regulator-name = "camout"; 914 regulator-name = "camout";
915 regulator-always-on;
818 }; 916 };
819 tps65090_fet6: fet6 { 917 tps65090_fet6: fet6 {
820 regulator-name = "lcd_vdd"; 918 regulator-name = "lcd_vdd";
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 6d38f8bfd0e6..9dc2e9773b30 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -178,7 +178,7 @@
178 interrupts = <0 96 0>; 178 interrupts = <0 96 0>;
179 clocks = <&clock CLK_MFC>; 179 clocks = <&clock CLK_MFC>;
180 clock-names = "mfc"; 180 clock-names = "mfc";
181 samsung,power-domain = <&mfc_pd>; 181 power-domains = <&mfc_pd>;
182 }; 182 };
183 183
184 mmc_0: mmc@12200000 { 184 mmc_0: mmc@12200000 {
@@ -250,11 +250,13 @@
250 gsc_pd: power-domain@10044000 { 250 gsc_pd: power-domain@10044000 {
251 compatible = "samsung,exynos4210-pd"; 251 compatible = "samsung,exynos4210-pd";
252 reg = <0x10044000 0x20>; 252 reg = <0x10044000 0x20>;
253 #power-domain-cells = <0>;
253 }; 254 };
254 255
255 isp_pd: power-domain@10044020 { 256 isp_pd: power-domain@10044020 {
256 compatible = "samsung,exynos4210-pd"; 257 compatible = "samsung,exynos4210-pd";
257 reg = <0x10044020 0x20>; 258 reg = <0x10044020 0x20>;
259 #power-domain-cells = <0>;
258 }; 260 };
259 261
260 mfc_pd: power-domain@10044060 { 262 mfc_pd: power-domain@10044060 {
@@ -263,11 +265,27 @@
263 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>, 265 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
264 <&clock CLK_MOUT_USER_ACLK333>; 266 <&clock CLK_MOUT_USER_ACLK333>;
265 clock-names = "oscclk", "pclk0", "clk0"; 267 clock-names = "oscclk", "pclk0", "clk0";
268 #power-domain-cells = <0>;
266 }; 269 };
267 270
268 msc_pd: power-domain@10044120 { 271 msc_pd: power-domain@10044120 {
269 compatible = "samsung,exynos4210-pd"; 272 compatible = "samsung,exynos4210-pd";
270 reg = <0x10044120 0x20>; 273 reg = <0x10044120 0x20>;
274 #power-domain-cells = <0>;
275 };
276
277 disp_pd: power-domain@100440C0 {
278 compatible = "samsung,exynos4210-pd";
279 reg = <0x100440C0 0x20>;
280 #power-domain-cells = <0>;
281 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK200>,
282 <&clock CLK_MOUT_USER_ACLK200_DISP1>,
283 <&clock CLK_MOUT_SW_ACLK300>,
284 <&clock CLK_MOUT_USER_ACLK300_DISP1>,
285 <&clock CLK_MOUT_SW_ACLK400>,
286 <&clock CLK_MOUT_USER_ACLK400_DISP1>;
287 clock-names = "oscclk", "pclk0", "clk0",
288 "pclk1", "clk1", "pclk2", "clk2";
271 }; 289 };
272 290
273 pinctrl_0: pinctrl@13400000 { 291 pinctrl_0: pinctrl@13400000 {
@@ -537,6 +555,7 @@
537 fimd: fimd@14400000 { 555 fimd: fimd@14400000 {
538 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; 556 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
539 clock-names = "sclk_fimd", "fimd"; 557 clock-names = "sclk_fimd", "fimd";
558 power-domains = <&disp_pd>;
540 }; 559 };
541 560
542 adc: adc@12D10000 { 561 adc: adc@12D10000 {
@@ -710,6 +729,7 @@
710 phy = <&hdmiphy>; 729 phy = <&hdmiphy>;
711 samsung,syscon-phandle = <&pmu_system_controller>; 730 samsung,syscon-phandle = <&pmu_system_controller>;
712 status = "disabled"; 731 status = "disabled";
732 power-domains = <&disp_pd>;
713 }; 733 };
714 734
715 hdmiphy: hdmiphy@145D0000 { 735 hdmiphy: hdmiphy@145D0000 {
@@ -722,6 +742,7 @@
722 interrupts = <0 94 0>; 742 interrupts = <0 94 0>;
723 clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>; 743 clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
724 clock-names = "mixer", "sclk_hdmi"; 744 clock-names = "mixer", "sclk_hdmi";
745 power-domains = <&disp_pd>;
725 }; 746 };
726 747
727 gsc_0: video-scaler@13e00000 { 748 gsc_0: video-scaler@13e00000 {
@@ -730,7 +751,7 @@
730 interrupts = <0 85 0>; 751 interrupts = <0 85 0>;
731 clocks = <&clock CLK_GSCL0>; 752 clocks = <&clock CLK_GSCL0>;
732 clock-names = "gscl"; 753 clock-names = "gscl";
733 samsung,power-domain = <&gsc_pd>; 754 power-domains = <&gsc_pd>;
734 }; 755 };
735 756
736 gsc_1: video-scaler@13e10000 { 757 gsc_1: video-scaler@13e10000 {
@@ -739,7 +760,7 @@
739 interrupts = <0 86 0>; 760 interrupts = <0 86 0>;
740 clocks = <&clock CLK_GSCL1>; 761 clocks = <&clock CLK_GSCL1>;
741 clock-names = "gscl"; 762 clock-names = "gscl";
742 samsung,power-domain = <&gsc_pd>; 763 power-domains = <&gsc_pd>;
743 }; 764 };
744 765
745 pmu_system_controller: system-controller@10040000 { 766 pmu_system_controller: system-controller@10040000 {
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
new file mode 100644
index 000000000000..a519c863248d
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
@@ -0,0 +1,371 @@
1/*
2 * Hardkernel Odroid XU3 board device tree source
3 *
4 * Copyright (c) 2014 Collabora Ltd.
5 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/dts-v1/;
14#include "exynos5800.dtsi"
15
16/ {
17 model = "Hardkernel Odroid XU3";
18 compatible = "hardkernel,odroid-xu3", "samsung,exynos5800", "samsung,exynos5";
19
20 memory {
21 reg = <0x40000000 0x7EA00000>;
22 };
23
24 chosen {
25 linux,stdout-path = &serial_2;
26 };
27
28 fimd@14400000 {
29 status = "okay";
30 };
31
32 firmware@02073000 {
33 compatible = "samsung,secure-firmware";
34 reg = <0x02073000 0x1000>;
35 };
36
37 fixed-rate-clocks {
38 oscclk {
39 compatible = "samsung,exynos5420-oscclk";
40 clock-frequency = <24000000>;
41 };
42 };
43
44 hsi2c_4: i2c@12CA0000 {
45 status = "okay";
46
47 s2mps11_pmic@66 {
48 compatible = "samsung,s2mps11-pmic";
49 reg = <0x66>;
50 s2mps11,buck2-ramp-delay = <12>;
51 s2mps11,buck34-ramp-delay = <12>;
52 s2mps11,buck16-ramp-delay = <12>;
53 s2mps11,buck6-ramp-enable = <1>;
54 s2mps11,buck2-ramp-enable = <1>;
55 s2mps11,buck3-ramp-enable = <1>;
56 s2mps11,buck4-ramp-enable = <1>;
57
58 s2mps11_osc: clocks {
59 #clock-cells = <1>;
60 clock-output-names = "s2mps11_ap",
61 "s2mps11_cp", "s2mps11_bt";
62 };
63
64 regulators {
65 ldo1_reg: LDO1 {
66 regulator-name = "vdd_ldo1";
67 regulator-min-microvolt = <1000000>;
68 regulator-max-microvolt = <1000000>;
69 regulator-always-on;
70 };
71
72 ldo3_reg: LDO3 {
73 regulator-name = "vdd_ldo3";
74 regulator-min-microvolt = <1800000>;
75 regulator-max-microvolt = <1800000>;
76 regulator-always-on;
77 };
78
79 ldo5_reg: LDO5 {
80 regulator-name = "vdd_ldo5";
81 regulator-min-microvolt = <1800000>;
82 regulator-max-microvolt = <1800000>;
83 regulator-always-on;
84 };
85
86 ldo6_reg: LDO6 {
87 regulator-name = "vdd_ldo6";
88 regulator-min-microvolt = <1000000>;
89 regulator-max-microvolt = <1000000>;
90 regulator-always-on;
91 };
92
93 ldo7_reg: LDO7 {
94 regulator-name = "vdd_ldo7";
95 regulator-min-microvolt = <1800000>;
96 regulator-max-microvolt = <1800000>;
97 regulator-always-on;
98 };
99
100 ldo8_reg: LDO8 {
101 regulator-name = "vdd_ldo8";
102 regulator-min-microvolt = <1800000>;
103 regulator-max-microvolt = <1800000>;
104 regulator-always-on;
105 };
106
107 ldo9_reg: LDO9 {
108 regulator-name = "vdd_ldo9";
109 regulator-min-microvolt = <3000000>;
110 regulator-max-microvolt = <3000000>;
111 regulator-always-on;
112 };
113
114 ldo10_reg: LDO10 {
115 regulator-name = "vdd_ldo10";
116 regulator-min-microvolt = <1800000>;
117 regulator-max-microvolt = <1800000>;
118 regulator-always-on;
119 };
120
121 ldo11_reg: LDO11 {
122 regulator-name = "vdd_ldo11";
123 regulator-min-microvolt = <1000000>;
124 regulator-max-microvolt = <1000000>;
125 regulator-always-on;
126 };
127
128 ldo12_reg: LDO12 {
129 regulator-name = "vdd_ldo12";
130 regulator-min-microvolt = <1800000>;
131 regulator-max-microvolt = <1800000>;
132 regulator-always-on;
133 };
134
135 ldo13_reg: LDO13 {
136 regulator-name = "vdd_ldo13";
137 regulator-min-microvolt = <2800000>;
138 regulator-max-microvolt = <2800000>;
139 regulator-always-on;
140 };
141
142 ldo15_reg: LDO15 {
143 regulator-name = "vdd_ldo15";
144 regulator-min-microvolt = <3100000>;
145 regulator-max-microvolt = <3100000>;
146 regulator-always-on;
147 };
148
149 ldo16_reg: LDO16 {
150 regulator-name = "vdd_ldo16";
151 regulator-min-microvolt = <2200000>;
152 regulator-max-microvolt = <2200000>;
153 regulator-always-on;
154 };
155
156 ldo17_reg: LDO17 {
157 regulator-name = "tsp_avdd";
158 regulator-min-microvolt = <3300000>;
159 regulator-max-microvolt = <3300000>;
160 regulator-always-on;
161 };
162
163 ldo19_reg: LDO19 {
164 regulator-name = "vdd_sd";
165 regulator-min-microvolt = <2800000>;
166 regulator-max-microvolt = <2800000>;
167 regulator-always-on;
168 };
169
170 ldo24_reg: LDO24 {
171 regulator-name = "tsp_io";
172 regulator-min-microvolt = <2800000>;
173 regulator-max-microvolt = <2800000>;
174 regulator-always-on;
175 };
176
177 ldo26_reg: LDO26 {
178 regulator-name = "vdd_ldo26";
179 regulator-min-microvolt = <3000000>;
180 regulator-max-microvolt = <3000000>;
181 regulator-always-on;
182 };
183
184 buck1_reg: BUCK1 {
185 regulator-name = "vdd_mif";
186 regulator-min-microvolt = <800000>;
187 regulator-max-microvolt = <1300000>;
188 regulator-always-on;
189 regulator-boot-on;
190 };
191
192 buck2_reg: BUCK2 {
193 regulator-name = "vdd_arm";
194 regulator-min-microvolt = <800000>;
195 regulator-max-microvolt = <1500000>;
196 regulator-always-on;
197 regulator-boot-on;
198 };
199
200 buck3_reg: BUCK3 {
201 regulator-name = "vdd_int";
202 regulator-min-microvolt = <800000>;
203 regulator-max-microvolt = <1400000>;
204 regulator-always-on;
205 regulator-boot-on;
206 };
207
208 buck4_reg: BUCK4 {
209 regulator-name = "vdd_g3d";
210 regulator-min-microvolt = <800000>;
211 regulator-max-microvolt = <1400000>;
212 regulator-always-on;
213 regulator-boot-on;
214 };
215
216 buck5_reg: BUCK5 {
217 regulator-name = "vdd_mem";
218 regulator-min-microvolt = <800000>;
219 regulator-max-microvolt = <1400000>;
220 regulator-always-on;
221 regulator-boot-on;
222 };
223
224 buck6_reg: BUCK6 {
225 regulator-name = "vdd_kfc";
226 regulator-min-microvolt = <800000>;
227 regulator-max-microvolt = <1500000>;
228 regulator-always-on;
229 regulator-boot-on;
230 };
231
232 buck7_reg: BUCK7 {
233 regulator-name = "vdd_1.0v_ldo";
234 regulator-min-microvolt = <800000>;
235 regulator-max-microvolt = <1500000>;
236 regulator-always-on;
237 regulator-boot-on;
238 };
239
240 buck8_reg: BUCK8 {
241 regulator-name = "vdd_1.8v_ldo";
242 regulator-min-microvolt = <800000>;
243 regulator-max-microvolt = <1500000>;
244 regulator-always-on;
245 regulator-boot-on;
246 };
247
248 buck9_reg: BUCK9 {
249 regulator-name = "vdd_2.8v_ldo";
250 regulator-min-microvolt = <3000000>;
251 regulator-max-microvolt = <3750000>;
252 regulator-always-on;
253 regulator-boot-on;
254 };
255
256 buck10_reg: BUCK10 {
257 regulator-name = "vdd_vmem";
258 regulator-min-microvolt = <2850000>;
259 regulator-max-microvolt = <2850000>;
260 regulator-always-on;
261 regulator-boot-on;
262 };
263 };
264 };
265 };
266
267 i2c_2: i2c@12C80000 {
268 samsung,i2c-sda-delay = <100>;
269 samsung,i2c-max-bus-freq = <66000>;
270 status = "okay";
271
272 hdmiddc@50 {
273 compatible = "samsung,exynos4210-hdmiddc";
274 reg = <0x50>;
275 };
276 };
277
278 rtc@101E0000 {
279 status = "okay";
280 };
281};
282
283&hdmi {
284 status = "okay";
285 hpd-gpio = <&gpx3 7 0>;
286 pinctrl-names = "default";
287 pinctrl-0 = <&hdmi_hpd_irq>;
288
289 vdd_osc-supply = <&ldo7_reg>;
290 vdd_pll-supply = <&ldo6_reg>;
291 vdd-supply = <&ldo6_reg>;
292};
293
294&mfc {
295 samsung,mfc-r = <0x43000000 0x800000>;
296 samsung,mfc-l = <0x51000000 0x800000>;
297};
298
299&mmc_0 {
300 status = "okay";
301 broken-cd;
302 card-detect-delay = <200>;
303 samsung,dw-mshc-ciu-div = <3>;
304 samsung,dw-mshc-sdr-timing = <0 4>;
305 samsung,dw-mshc-ddr-timing = <0 2>;
306 pinctrl-names = "default";
307 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
308 bus-width = <8>;
309 cap-mmc-highspeed;
310};
311
312&mmc_2 {
313 status = "okay";
314 card-detect-delay = <200>;
315 samsung,dw-mshc-ciu-div = <3>;
316 samsung,dw-mshc-sdr-timing = <0 4>;
317 samsung,dw-mshc-ddr-timing = <0 2>;
318 pinctrl-names = "default";
319 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
320 bus-width = <4>;
321 cap-sd-highspeed;
322};
323
324&pinctrl_0 {
325 hdmi_hpd_irq: hdmi-hpd-irq {
326 samsung,pins = "gpx3-7";
327 samsung,pin-function = <0>;
328 samsung,pin-pud = <1>;
329 samsung,pin-drv = <0>;
330 };
331};
332
333&usbdrd_dwc3_0 {
334 dr_mode = "host";
335};
336
337&usbdrd_dwc3_1 {
338 dr_mode = "otg";
339};
340
341&i2c_0 {
342 status = "okay";
343
344 /* A15 cluster: VDD_ARM */
345 ina231@40 {
346 compatible = "ti,ina231";
347 reg = <0x40>;
348 shunt-resistor = <10000>;
349 };
350
351 /* memory: VDD_MEM */
352 ina231@41 {
353 compatible = "ti,ina231";
354 reg = <0x41>;
355 shunt-resistor = <10000>;
356 };
357
358 /* GPU: VDD_G3D */
359 ina231@44 {
360 compatible = "ti,ina231";
361 reg = <0x44>;
362 shunt-resistor = <10000>;
363 };
364
365 /* A7 cluster: VDD_KFC */
366 ina231@45 {
367 compatible = "ti,ina231";
368 reg = <0x45>;
369 shunt-resistor = <10000>;
370 };
371};
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index e8fdda827fc9..06737c60d333 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -13,6 +13,7 @@
13#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/clock/maxim,max77802.h> 15#include <dt-bindings/clock/maxim,max77802.h>
16#include <dt-bindings/regulator/maxim,max77802.h>
16#include "exynos5800.dtsi" 17#include "exynos5800.dtsi"
17 18
18/ { 19/ {
@@ -52,7 +53,7 @@
52 compatible = "gpio-keys"; 53 compatible = "gpio-keys";
53 54
54 pinctrl-names = "default"; 55 pinctrl-names = "default";
55 pinctrl-0 = <&power_key_irq>; 56 pinctrl-0 = <&power_key_irq &lid_irq>;
56 57
57 power { 58 power {
58 label = "Power"; 59 label = "Power";
@@ -60,6 +61,16 @@
60 linux,code = <KEY_POWER>; 61 linux,code = <KEY_POWER>;
61 gpio-key,wakeup; 62 gpio-key,wakeup;
62 }; 63 };
64
65 lid-switch {
66 label = "Lid";
67 gpios = <&gpx3 4 GPIO_ACTIVE_LOW>;
68 linux,input-type = <5>; /* EV_SW */
69 linux,code = <0>; /* SW_LID */
70 debounce-interval = <1>;
71 gpio-key,wakeup;
72 };
73
63 }; 74 };
64 75
65 memory { 76 memory {
@@ -191,6 +202,9 @@
191 regulator-always-on; 202 regulator-always-on;
192 regulator-boot-on; 203 regulator-boot-on;
193 regulator-ramp-delay = <12500>; 204 regulator-ramp-delay = <12500>;
205 regulator-state-mem {
206 regulator-off-in-suspend;
207 };
194 }; 208 };
195 209
196 buck2_reg: BUCK2 { 210 buck2_reg: BUCK2 {
@@ -200,6 +214,9 @@
200 regulator-always-on; 214 regulator-always-on;
201 regulator-boot-on; 215 regulator-boot-on;
202 regulator-ramp-delay = <12500>; 216 regulator-ramp-delay = <12500>;
217 regulator-state-mem {
218 regulator-off-in-suspend;
219 };
203 }; 220 };
204 221
205 buck3_reg: BUCK3 { 222 buck3_reg: BUCK3 {
@@ -209,6 +226,9 @@
209 regulator-always-on; 226 regulator-always-on;
210 regulator-boot-on; 227 regulator-boot-on;
211 regulator-ramp-delay = <12500>; 228 regulator-ramp-delay = <12500>;
229 regulator-state-mem {
230 regulator-off-in-suspend;
231 };
212 }; 232 };
213 233
214 buck4_reg: BUCK4 { 234 buck4_reg: BUCK4 {
@@ -218,6 +238,9 @@
218 regulator-always-on; 238 regulator-always-on;
219 regulator-boot-on; 239 regulator-boot-on;
220 regulator-ramp-delay = <12500>; 240 regulator-ramp-delay = <12500>;
241 regulator-state-mem {
242 regulator-off-in-suspend;
243 };
221 }; 244 };
222 245
223 buck5_reg: BUCK5 { 246 buck5_reg: BUCK5 {
@@ -226,6 +249,9 @@
226 regulator-max-microvolt = <1200000>; 249 regulator-max-microvolt = <1200000>;
227 regulator-always-on; 250 regulator-always-on;
228 regulator-boot-on; 251 regulator-boot-on;
252 regulator-state-mem {
253 regulator-off-in-suspend;
254 };
229 }; 255 };
230 256
231 buck6_reg: BUCK6 { 257 buck6_reg: BUCK6 {
@@ -235,6 +261,9 @@
235 regulator-always-on; 261 regulator-always-on;
236 regulator-boot-on; 262 regulator-boot-on;
237 regulator-ramp-delay = <12500>; 263 regulator-ramp-delay = <12500>;
264 regulator-state-mem {
265 regulator-off-in-suspend;
266 };
238 }; 267 };
239 268
240 buck7_reg: BUCK7 { 269 buck7_reg: BUCK7 {
@@ -243,6 +272,9 @@
243 regulator-max-microvolt = <1350000>; 272 regulator-max-microvolt = <1350000>;
244 regulator-always-on; 273 regulator-always-on;
245 regulator-boot-on; 274 regulator-boot-on;
275 regulator-state-mem {
276 regulator-on-in-suspend;
277 };
246 }; 278 };
247 279
248 buck8_reg: BUCK8 { 280 buck8_reg: BUCK8 {
@@ -251,6 +283,9 @@
251 regulator-max-microvolt = <2850000>; 283 regulator-max-microvolt = <2850000>;
252 regulator-always-on; 284 regulator-always-on;
253 regulator-boot-on; 285 regulator-boot-on;
286 regulator-state-mem {
287 regulator-off-in-suspend;
288 };
254 }; 289 };
255 290
256 buck9_reg: BUCK9 { 291 buck9_reg: BUCK9 {
@@ -259,6 +294,9 @@
259 regulator-max-microvolt = <2000000>; 294 regulator-max-microvolt = <2000000>;
260 regulator-always-on; 295 regulator-always-on;
261 regulator-boot-on; 296 regulator-boot-on;
297 regulator-state-mem {
298 regulator-on-in-suspend;
299 };
262 }; 300 };
263 301
264 buck10_reg: BUCK10 { 302 buck10_reg: BUCK10 {
@@ -267,6 +305,9 @@
267 regulator-max-microvolt = <1800000>; 305 regulator-max-microvolt = <1800000>;
268 regulator-always-on; 306 regulator-always-on;
269 regulator-boot-on; 307 regulator-boot-on;
308 regulator-state-mem {
309 regulator-on-in-suspend;
310 };
270 }; 311 };
271 312
272 ldo1_reg: LDO1 { 313 ldo1_reg: LDO1 {
@@ -274,6 +315,10 @@
274 regulator-min-microvolt = <1000000>; 315 regulator-min-microvolt = <1000000>;
275 regulator-max-microvolt = <1000000>; 316 regulator-max-microvolt = <1000000>;
276 regulator-always-on; 317 regulator-always-on;
318 regulator-state-mem {
319 regulator-on-in-suspend;
320 regulator-mode = <MAX77802_OPMODE_LP>;
321 };
277 }; 322 };
278 323
279 ldo2_reg: LDO2 { 324 ldo2_reg: LDO2 {
@@ -287,6 +332,10 @@
287 regulator-min-microvolt = <1800000>; 332 regulator-min-microvolt = <1800000>;
288 regulator-max-microvolt = <1800000>; 333 regulator-max-microvolt = <1800000>;
289 regulator-always-on; 334 regulator-always-on;
335 regulator-state-mem {
336 regulator-on-in-suspend;
337 regulator-mode = <MAX77802_OPMODE_LP>;
338 };
290 }; 339 };
291 340
292 vqmmc_sdcard: ldo4_reg: LDO4 { 341 vqmmc_sdcard: ldo4_reg: LDO4 {
@@ -294,6 +343,9 @@
294 regulator-min-microvolt = <1800000>; 343 regulator-min-microvolt = <1800000>;
295 regulator-max-microvolt = <2800000>; 344 regulator-max-microvolt = <2800000>;
296 regulator-always-on; 345 regulator-always-on;
346 regulator-state-mem {
347 regulator-off-in-suspend;
348 };
297 }; 349 };
298 350
299 ldo5_reg: LDO5 { 351 ldo5_reg: LDO5 {
@@ -301,6 +353,9 @@
301 regulator-min-microvolt = <1800000>; 353 regulator-min-microvolt = <1800000>;
302 regulator-max-microvolt = <1800000>; 354 regulator-max-microvolt = <1800000>;
303 regulator-always-on; 355 regulator-always-on;
356 regulator-state-mem {
357 regulator-off-in-suspend;
358 };
304 }; 359 };
305 360
306 ldo6_reg: LDO6 { 361 ldo6_reg: LDO6 {
@@ -308,6 +363,9 @@
308 regulator-min-microvolt = <1800000>; 363 regulator-min-microvolt = <1800000>;
309 regulator-max-microvolt = <1800000>; 364 regulator-max-microvolt = <1800000>;
310 regulator-always-on; 365 regulator-always-on;
366 regulator-state-mem {
367 regulator-off-in-suspend;
368 };
311 }; 369 };
312 370
313 ldo7_reg: LDO7 { 371 ldo7_reg: LDO7 {
@@ -321,6 +379,9 @@
321 regulator-min-microvolt = <1000000>; 379 regulator-min-microvolt = <1000000>;
322 regulator-max-microvolt = <1000000>; 380 regulator-max-microvolt = <1000000>;
323 regulator-always-on; 381 regulator-always-on;
382 regulator-state-mem {
383 regulator-off-in-suspend;
384 };
324 }; 385 };
325 386
326 ldo9_reg: LDO9 { 387 ldo9_reg: LDO9 {
@@ -328,6 +389,10 @@
328 regulator-min-microvolt = <1800000>; 389 regulator-min-microvolt = <1800000>;
329 regulator-max-microvolt = <1800000>; 390 regulator-max-microvolt = <1800000>;
330 regulator-always-on; 391 regulator-always-on;
392 regulator-state-mem {
393 regulator-on-in-suspend;
394 regulator-mode = <MAX77802_OPMODE_LP>;
395 };
331 }; 396 };
332 397
333 ldo10_reg: LDO10 { 398 ldo10_reg: LDO10 {
@@ -335,6 +400,9 @@
335 regulator-min-microvolt = <1800000>; 400 regulator-min-microvolt = <1800000>;
336 regulator-max-microvolt = <1800000>; 401 regulator-max-microvolt = <1800000>;
337 regulator-always-on; 402 regulator-always-on;
403 regulator-state-mem {
404 regulator-off-in-suspend;
405 };
338 }; 406 };
339 407
340 ldo11_reg: LDO11 { 408 ldo11_reg: LDO11 {
@@ -342,6 +410,10 @@
342 regulator-min-microvolt = <1800000>; 410 regulator-min-microvolt = <1800000>;
343 regulator-max-microvolt = <1800000>; 411 regulator-max-microvolt = <1800000>;
344 regulator-always-on; 412 regulator-always-on;
413 regulator-state-mem {
414 regulator-on-in-suspend;
415 regulator-mode = <MAX77802_OPMODE_LP>;
416 };
345 }; 417 };
346 418
347 ldo12_reg: LDO12 { 419 ldo12_reg: LDO12 {
@@ -349,6 +421,9 @@
349 regulator-min-microvolt = <3000000>; 421 regulator-min-microvolt = <3000000>;
350 regulator-max-microvolt = <3000000>; 422 regulator-max-microvolt = <3000000>;
351 regulator-always-on; 423 regulator-always-on;
424 regulator-state-mem {
425 regulator-off-in-suspend;
426 };
352 }; 427 };
353 428
354 ldo13_reg: LDO13 { 429 ldo13_reg: LDO13 {
@@ -356,6 +431,10 @@
356 regulator-min-microvolt = <1800000>; 431 regulator-min-microvolt = <1800000>;
357 regulator-max-microvolt = <1800000>; 432 regulator-max-microvolt = <1800000>;
358 regulator-always-on; 433 regulator-always-on;
434 regulator-state-mem {
435 regulator-on-in-suspend;
436 regulator-mode = <MAX77802_OPMODE_LP>;
437 };
359 }; 438 };
360 439
361 ldo14_reg: LDO14 { 440 ldo14_reg: LDO14 {
@@ -363,6 +442,9 @@
363 regulator-min-microvolt = <1800000>; 442 regulator-min-microvolt = <1800000>;
364 regulator-max-microvolt = <1800000>; 443 regulator-max-microvolt = <1800000>;
365 regulator-always-on; 444 regulator-always-on;
445 regulator-state-mem {
446 regulator-off-in-suspend;
447 };
366 }; 448 };
367 449
368 ldo15_reg: LDO15 { 450 ldo15_reg: LDO15 {
@@ -370,6 +452,9 @@
370 regulator-min-microvolt = <1000000>; 452 regulator-min-microvolt = <1000000>;
371 regulator-max-microvolt = <1000000>; 453 regulator-max-microvolt = <1000000>;
372 regulator-always-on; 454 regulator-always-on;
455 regulator-state-mem {
456 regulator-off-in-suspend;
457 };
373 }; 458 };
374 459
375 ldo17_reg: LDO17 { 460 ldo17_reg: LDO17 {
@@ -377,6 +462,9 @@
377 regulator-min-microvolt = <900000>; 462 regulator-min-microvolt = <900000>;
378 regulator-max-microvolt = <1400000>; 463 regulator-max-microvolt = <1400000>;
379 regulator-always-on; 464 regulator-always-on;
465 regulator-state-mem {
466 regulator-off-in-suspend;
467 };
380 }; 468 };
381 469
382 ldo18_reg: LDO18 { 470 ldo18_reg: LDO18 {
@@ -450,6 +538,9 @@
450 regulator-min-microvolt = <1000000>; 538 regulator-min-microvolt = <1000000>;
451 regulator-max-microvolt = <1000000>; 539 regulator-max-microvolt = <1000000>;
452 regulator-always-on; 540 regulator-always-on;
541 regulator-state-mem {
542 regulator-off-in-suspend;
543 };
453 }; 544 };
454 545
455 ldo32_reg: LDO32 { 546 ldo32_reg: LDO32 {
@@ -646,6 +737,13 @@
646 samsung,pin-drv = <0>; 737 samsung,pin-drv = <0>;
647 }; 738 };
648 739
740 lid_irq: lid-irq {
741 samsung,pins = "gpx3-4";
742 samsung,pin-function = <0xf>;
743 samsung,pin-pud = <0>;
744 samsung,pin-drv = <0>;
745 };
746
649 hdmi_hpd_irq: hdmi-hpd-irq { 747 hdmi_hpd_irq: hdmi-hpd-irq {
650 samsung,pins = "gpx3-7"; 748 samsung,pins = "gpx3-7";
651 samsung,pin-function = <0>; 749 samsung,pin-function = <0>;
@@ -803,6 +901,7 @@
803 }; 901 };
804 tps65090_fet5: fet5 { 902 tps65090_fet5: fet5 {
805 regulator-name = "camout"; 903 regulator-name = "camout";
904 regulator-always-on;
806 }; 905 };
807 tps65090_fet6: fet6 { 906 tps65090_fet6: fet6 {
808 regulator-name = "lcd_vdd"; 907 regulator-name = "lcd_vdd";
diff --git a/arch/arm/boot/dts/hip01-ca9x2.dts b/arch/arm/boot/dts/hip01-ca9x2.dts
new file mode 100644
index 000000000000..eca5e42770fe
--- /dev/null
+++ b/arch/arm/boot/dts/hip01-ca9x2.dts
@@ -0,0 +1,51 @@
1/*
2 * Hisilicon Ltd. HiP01 SoC
3 *
4 * Copyright (C) 2014 Hisilicon Ltd.
5 * Copyright (C) 2014 Huawei Ltd.
6 *
7 * Author: Wang Long <long.wanglong@huawei.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14/dts-v1/;
15
16/* First 8KB reserved for secondary core boot */
17/memreserve/ 0x80000000 0x00002000;
18
19#include "hip01.dtsi"
20
21/ {
22 model = "Hisilicon HIP01 Development Board";
23 compatible = "hisilicon,hip01-ca9x2", "hisilicon,hip01";
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28 enable-method = "hisilicon,hip01-smp";
29
30 cpu@0 {
31 device_type = "cpu";
32 compatible = "arm,cortex-a9";
33 reg = <0>;
34 };
35
36 cpu@1 {
37 device_type = "cpu";
38 compatible = "arm,cortex-a9";
39 reg = <1>;
40 };
41 };
42
43 memory {
44 device_type = "memory";
45 reg = <0x80000000 0x80000000>;
46 };
47};
48
49&uart0 {
50 status = "okay";
51};
diff --git a/arch/arm/boot/dts/hip01.dtsi b/arch/arm/boot/dts/hip01.dtsi
new file mode 100644
index 000000000000..33130f8461c3
--- /dev/null
+++ b/arch/arm/boot/dts/hip01.dtsi
@@ -0,0 +1,110 @@
1/*
2 * Hisilicon Ltd. HiP01 SoC
3 *
4 * Copyright (c) 2014 Hisilicon Ltd.
5 * Copyright (c) 2014 Huawei Ltd.
6 *
7 * Author: Wang Long <long.wanglong@huawei.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include "skeleton.dtsi"
15
16/ {
17 interrupt-parent = <&gic>;
18 #address-cells = <1>;
19 #size-cells = <1>;
20
21 gic: interrupt-controller@1e001000 {
22 compatible = "arm,cortex-a9-gic";
23 #interrupt-cells = <3>;
24 #address-cells = <0>;
25 interrupt-controller;
26 reg = <0x1a001000 0x1000>, <0x1a000100 0x1000>;
27 };
28
29 hisi_refclk144mhz: refclk144mkhz {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <144000000>;
33 clock-output-names = "hisi:refclk144khz";
34 };
35
36 soc {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "simple-bus";
40 interrupt-parent = <&gic>;
41 ranges = <0 0x10000000 0x20000000>;
42
43 amba {
44 #address-cells = <1>;
45 #size-cells = <1>;
46 compatible = "arm,amba-bus";
47 ranges;
48
49 uart0: uart@10001000 {
50 compatible = "snps,dw-apb-uart";
51 reg = <0x10001000 0x1000>;
52 clocks = <&hisi_refclk144mhz>;
53 clock-names = "apb_pclk";
54 reg-shift = <2>;
55 interrupts = <0 32 4>;
56 status = "disabled";
57 };
58
59 uart1: uart@10002000 {
60 compatible = "snps,dw-apb-uart";
61 reg = <0x10002000 0x1000>;
62 clocks = <&hisi_refclk144mhz>;
63 clock-names = "apb_pclk";
64 reg-shift = <2>;
65 interrupts = <0 33 4>;
66 status = "disabled";
67 };
68
69 uart2: uart@10003000 {
70 compatible = "snps,dw-apb-uart";
71 reg = <0x10003000 0x1000>;
72 clocks = <&hisi_refclk144mhz>;
73 clock-names = "apb_pclk";
74 reg-shift = <2>;
75 interrupts = <0 34 4>;
76 status = "disabled";
77 };
78
79 uart3: uart@10006000 {
80 compatible = "snps,dw-apb-uart";
81 reg = <0x10006000 0x1000>;
82 clocks = <&hisi_refclk144mhz>;
83 clock-names = "apb_pclk";
84 reg-shift = <2>;
85 interrupts = <0 4 4>;
86 status = "disabled";
87 };
88 };
89
90 system-controller@10000000 {
91 compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
92 reg = <0x10000000 0x1000>;
93 reboot-offset = <0x4>;
94 };
95
96 global_timer@0a000200 {
97 compatible = "arm,cortex-a9-global-timer";
98 reg = <0x0a000200 0x100>;
99 interrupts = <1 11 0xf04>;
100 clocks = <&hisi_refclk144mhz>;
101 };
102
103 local_timer@0a000600 {
104 compatible = "arm,cortex-a9-twd-timer";
105 reg = <0x0a000600 0x100>;
106 interrupts = <1 13 0xf04>;
107 clocks = <&hisi_refclk144mhz>;
108 };
109 };
110};
diff --git a/arch/arm/boot/dts/imx27-apf27dev.dts b/arch/arm/boot/dts/imx27-apf27dev.dts
index da306c5dd678..bba3f41b89ef 100644
--- a/arch/arm/boot/dts/imx27-apf27dev.dts
+++ b/arch/arm/boot/dts/imx27-apf27dev.dts
@@ -59,6 +59,21 @@
59 linux,default-trigger = "heartbeat"; 59 linux,default-trigger = "heartbeat";
60 }; 60 };
61 }; 61 };
62
63 regulators {
64 compatible = "simple-bus";
65 #address-cells = <1>;
66 #size-cells = <0>;
67
68 reg_max5821: regulator@0 {
69 compatible = "regulator-fixed";
70 reg = <0>;
71 regulator-name = "max5821-reg";
72 regulator-min-microvolt = <2500000>;
73 regulator-max-microvolt = <2500000>;
74 regulator-always-on;
75 };
76 };
62}; 77};
63 78
64&cspi1 { 79&cspi1 {
@@ -107,6 +122,12 @@
107 compatible = "dallas,ds1374"; 122 compatible = "dallas,ds1374";
108 reg = <0x68>; 123 reg = <0x68>;
109 }; 124 };
125
126 max5821@38 {
127 compatible = "maxim,max5821";
128 reg = <0x38>;
129 vref-supply = <&reg_max5821>;
130 };
110}; 131};
111 132
112&i2c2 { 133&i2c2 {
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 107d713e1cbe..4b063b68db44 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -464,7 +464,7 @@
464 }; 464 };
465 465
466 coda: coda@10023000 { 466 coda: coda@10023000 {
467 compatible = "fsl,imx27-vpu"; 467 compatible = "fsl,imx27-vpu", "cnm,codadx6";
468 reg = <0x10023000 0x0200>; 468 reg = <0x10023000 0x0200>;
469 interrupts = <53>; 469 interrupts = <53>;
470 clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>, 470 clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>,
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index 0e13b4b10a92..279249b8c3f3 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -182,7 +182,6 @@
182 }; 182 };
183 183
184 lradc@80050000 { 184 lradc@80050000 {
185 fsl,lradc-touchscreen-wires = <4>;
186 status = "okay"; 185 status = "okay";
187 fsl,lradc-touchscreen-wires = <4>; 186 fsl,lradc-touchscreen-wires = <4>;
188 fsl,ave-ctrl = <4>; 187 fsl,ave-ctrl = <4>;
diff --git a/arch/arm/boot/dts/imx51-apf51dev.dts b/arch/arm/boot/dts/imx51-apf51dev.dts
index c5a9a24c280a..93d3ea12328c 100644
--- a/arch/arm/boot/dts/imx51-apf51dev.dts
+++ b/arch/arm/boot/dts/imx51-apf51dev.dts
@@ -16,6 +16,14 @@
16 model = "Armadeus Systems APF51Dev docking/development board"; 16 model = "Armadeus Systems APF51Dev docking/development board";
17 compatible = "armadeus,imx51-apf51dev", "armadeus,imx51-apf51", "fsl,imx51"; 17 compatible = "armadeus,imx51-apf51dev", "armadeus,imx51-apf51", "fsl,imx51";
18 18
19 backlight@bl1{
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_backlight>;
22 compatible = "gpio-backlight";
23 gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
24 default-on;
25 };
26
19 display@di1 { 27 display@di1 {
20 compatible = "fsl,imx-parallel-display"; 28 compatible = "fsl,imx-parallel-display";
21 interface-pix-fmt = "bgr666"; 29 interface-pix-fmt = "bgr666";
@@ -114,6 +122,12 @@
114 pinctrl-0 = <&pinctrl_hog>; 122 pinctrl-0 = <&pinctrl_hog>;
115 123
116 imx51-apf51dev { 124 imx51-apf51dev {
125 pinctrl_backlight: bl1grp {
126 fsl,pins = <
127 MX51_PAD_DI1_D1_CS__GPIO3_4 0x1F5
128 >;
129 };
130
117 pinctrl_hog: hoggrp { 131 pinctrl_hog: hoggrp {
118 fsl,pins = < 132 fsl,pins = <
119 MX51_PAD_EIM_EB2__GPIO2_22 0x0C5 133 MX51_PAD_EIM_EB2__GPIO2_22 0x0C5
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index a30bddfdbdb6..ff4fa7ecacd8 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -756,7 +756,7 @@
756 }; 756 };
757 757
758 vpu: vpu@63ff4000 { 758 vpu: vpu@63ff4000 {
759 compatible = "fsl,imx53-vpu"; 759 compatible = "fsl,imx53-vpu", "cnm,coda7541";
760 reg = <0x63ff4000 0x1000>; 760 reg = <0x63ff4000 0x1000>;
761 interrupts = <9>; 761 interrupts = <9>;
762 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>, 762 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
@@ -765,6 +765,15 @@
765 resets = <&src 1>; 765 resets = <&src 1>;
766 iram = <&ocram>; 766 iram = <&ocram>;
767 }; 767 };
768
769 sahara: crypto@63ff8000 {
770 compatible = "fsl,imx53-sahara";
771 reg = <0x63ff8000 0x4000>;
772 interrupts = <19 20>;
773 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
774 <&clks IMX5_CLK_SAHARA_IPG_GATE>;
775 clock-names = "ipg", "ahb";
776 };
768 }; 777 };
769 778
770 ocram: sram@f8000000 { 779 ocram: sram@f8000000 {
diff --git a/arch/arm/boot/dts/imx6dl-udoo.dts b/arch/arm/boot/dts/imx6dl-udoo.dts
new file mode 100644
index 000000000000..e3713f00e819
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-udoo.dts
@@ -0,0 +1,18 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11/dts-v1/;
12#include "imx6dl.dtsi"
13#include "imx6qdl-udoo.dtsi"
14
15/ {
16 model = "Udoo i.MX6 Dual-lite Board";
17 compatible = "udoo,imx6dl-udoo", "fsl,imx6dl";
18};
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 1ac2fe732867..f94bf72832af 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -28,7 +28,7 @@
28 next-level-cache = <&L2>; 28 next-level-cache = <&L2>;
29 operating-points = < 29 operating-points = <
30 /* kHz uV */ 30 /* kHz uV */
31 996000 1275000 31 996000 1250000
32 792000 1175000 32 792000 1175000
33 396000 1075000 33 396000 1075000
34 >; 34 >;
diff --git a/arch/arm/boot/dts/imx6q-udoo.dts b/arch/arm/boot/dts/imx6q-udoo.dts
index e3bff2ac00db..c3e64ff3d544 100644
--- a/arch/arm/boot/dts/imx6q-udoo.dts
+++ b/arch/arm/boot/dts/imx6q-udoo.dts
@@ -8,137 +8,15 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 * 9 *
10 */ 10 */
11
12/dts-v1/; 11/dts-v1/;
13#include "imx6q.dtsi" 12#include "imx6q.dtsi"
13#include "imx6qdl-udoo.dtsi"
14 14
15/ { 15/ {
16 model = "Udoo i.MX6 Quad Board"; 16 model = "Udoo i.MX6 Quad Board";
17 compatible = "udoo,imx6q-udoo", "fsl,imx6q"; 17 compatible = "udoo,imx6q-udoo", "fsl,imx6q";
18
19 chosen {
20 stdout-path = &uart2;
21 };
22
23 memory {
24 reg = <0x10000000 0x40000000>;
25 };
26
27 regulators {
28 compatible = "simple-bus";
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 reg_usb_h1_vbus: regulator@0 {
33 compatible = "regulator-fixed";
34 reg = <0>;
35 regulator-name = "usb_h1_vbus";
36 regulator-min-microvolt = <5000000>;
37 regulator-max-microvolt = <5000000>;
38 enable-active-high;
39 startup-delay-us = <2>; /* USB2415 requires a POR of 1 us minimum */
40 gpio = <&gpio7 12 0>;
41 };
42 };
43};
44
45&fec {
46 pinctrl-names = "default";
47 pinctrl-0 = <&pinctrl_enet>;
48 phy-mode = "rgmii";
49 status = "okay";
50};
51
52&hdmi {
53 ddc-i2c-bus = <&i2c2>;
54 status = "okay";
55};
56
57&i2c2 {
58 clock-frequency = <100000>;
59 pinctrl-names = "default";
60 pinctrl-0 = <&pinctrl_i2c2>;
61 status = "okay";
62};
63
64&iomuxc {
65 imx6q-udoo {
66 pinctrl_enet: enetgrp {
67 fsl,pins = <
68 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
69 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
70 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
71 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
72 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
73 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
74 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
75 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
76 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
77 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
78 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
79 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
80 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
81 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
82 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
83 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
84 >;
85 };
86
87 pinctrl_i2c2: i2c2grp {
88 fsl,pins = <
89 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
90 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
91 >;
92 };
93
94 pinctrl_uart2: uart2grp {
95 fsl,pins = <
96 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
97 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
98 >;
99 };
100
101 pinctrl_usbh: usbhgrp {
102 fsl,pins = <
103 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000
104 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0
105 >;
106 };
107
108 pinctrl_usdhc3: usdhc3grp {
109 fsl,pins = <
110 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
111 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
112 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
113 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
114 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
115 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
116 >;
117 };
118 };
119}; 18};
120 19
121&sata { 20&sata {
122 status = "okay"; 21 status = "okay";
123}; 22};
124
125&uart2 {
126 pinctrl-names = "default";
127 pinctrl-0 = <&pinctrl_uart2>;
128 status = "okay";
129};
130
131&usbh1 {
132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_usbh>;
134 vbus-supply = <&reg_usb_h1_vbus>;
135 clocks = <&clks 201>;
136 status = "okay";
137};
138
139&usdhc3 {
140 pinctrl-names = "default";
141 pinctrl-0 = <&pinctrl_usdhc3>;
142 non-removable;
143 status = "okay";
144};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 85f72e6b5bad..93ec79bb6b35 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -31,7 +31,7 @@
31 1200000 1275000 31 1200000 1275000
32 996000 1250000 32 996000 1250000
33 852000 1250000 33 852000 1250000
34 792000 1150000 34 792000 1175000
35 396000 975000 35 396000 975000
36 >; 36 >;
37 fsl,soc-operating-points = < 37 fsl,soc-operating-points = <
@@ -95,6 +95,8 @@
95 clocks = <&clks IMX6Q_CLK_ECSPI5>, 95 clocks = <&clks IMX6Q_CLK_ECSPI5>,
96 <&clks IMX6Q_CLK_ECSPI5>; 96 <&clks IMX6Q_CLK_ECSPI5>;
97 clock-names = "ipg", "per"; 97 clock-names = "ipg", "per";
98 dmas = <&sdma 11 7 1>, <&sdma 12 7 2>;
99 dma-names = "rx", "tx";
98 status = "disabled"; 100 status = "disabled";
99 }; 101 };
100 }; 102 };
diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
index 0a36129152e0..0b28a9d5241e 100644
--- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
@@ -173,6 +173,11 @@
173 status = "okay"; 173 status = "okay";
174}; 174};
175 175
176&hdmi {
177 ddc-i2c-bus = <&i2c2>;
178 status = "okay";
179};
180
176&i2c1 { 181&i2c1 {
177 clock-frequency = <100000>; 182 clock-frequency = <100000>;
178 pinctrl-names = "default"; 183 pinctrl-names = "default";
@@ -188,6 +193,20 @@
188 }; 193 };
189}; 194};
190 195
196&i2c2 {
197 clock-frequency = <100000>;
198 pinctrl-names = "default";
199 pinctrl-0 = <&pinctrl_i2c2>;
200 status = "okay";
201};
202
203&i2c3 {
204 clock-frequency = <100000>;
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_i2c3>;
207 status = "okay";
208};
209
191&iomuxc { 210&iomuxc {
192 pinctrl-names = "default"; 211 pinctrl-names = "default";
193 pinctrl-0 = <&pinctrl_hog>; 212 pinctrl-0 = <&pinctrl_hog>;
@@ -265,6 +284,20 @@
265 >; 284 >;
266 }; 285 };
267 286
287 pinctrl_i2c2: i2c2grp {
288 fsl,pins = <
289 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
290 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
291 >;
292 };
293
294 pinctrl_i2c3: i2c3grp {
295 fsl,pins = <
296 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
297 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
298 >;
299 };
300
268 pinctrl_pwm1: pwm1grp { 301 pinctrl_pwm1: pwm1grp {
269 fsl,pins = < 302 fsl,pins = <
270 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 303 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
diff --git a/arch/arm/boot/dts/imx6qdl-udoo.dtsi b/arch/arm/boot/dts/imx6qdl-udoo.dtsi
new file mode 100644
index 000000000000..1211da894ee9
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-udoo.dtsi
@@ -0,0 +1,134 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12/ {
13 chosen {
14 stdout-path = &uart2;
15 };
16
17 memory {
18 reg = <0x10000000 0x40000000>;
19 };
20
21 regulators {
22 compatible = "simple-bus";
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 reg_usb_h1_vbus: regulator@0 {
27 compatible = "regulator-fixed";
28 reg = <0>;
29 regulator-name = "usb_h1_vbus";
30 regulator-min-microvolt = <5000000>;
31 regulator-max-microvolt = <5000000>;
32 enable-active-high;
33 startup-delay-us = <2>; /* USB2415 requires a POR of 1 us minimum */
34 gpio = <&gpio7 12 0>;
35 };
36 };
37};
38
39&fec {
40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_enet>;
42 phy-mode = "rgmii";
43 status = "okay";
44};
45
46&hdmi {
47 ddc-i2c-bus = <&i2c2>;
48 status = "okay";
49};
50
51&i2c2 {
52 clock-frequency = <100000>;
53 pinctrl-names = "default";
54 pinctrl-0 = <&pinctrl_i2c2>;
55 status = "okay";
56};
57
58&iomuxc {
59 imx6q-udoo {
60 pinctrl_enet: enetgrp {
61 fsl,pins = <
62 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
63 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
64 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
65 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
66 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
67 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
68 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
69 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
70 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
71 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
72 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
73 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
74 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
75 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
76 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
77 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
78 >;
79 };
80
81 pinctrl_i2c2: i2c2grp {
82 fsl,pins = <
83 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
84 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
85 >;
86 };
87
88 pinctrl_uart2: uart2grp {
89 fsl,pins = <
90 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
91 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
92 >;
93 };
94
95 pinctrl_usbh: usbhgrp {
96 fsl,pins = <
97 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000
98 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0
99 >;
100 };
101
102 pinctrl_usdhc3: usdhc3grp {
103 fsl,pins = <
104 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
105 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
106 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
107 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
108 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
109 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
110 >;
111 };
112 };
113};
114
115&uart2 {
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_uart2>;
118 status = "okay";
119};
120
121&usbh1 {
122 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_usbh>;
124 vbus-supply = <&reg_usb_h1_vbus>;
125 clocks = <&clks 201>;
126 status = "okay";
127};
128
129&usdhc3 {
130 pinctrl-names = "default";
131 pinctrl-0 = <&pinctrl_usdhc3>;
132 non-removable;
133 status = "okay";
134};
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 2109d0763c1b..d6c69ec44314 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -339,9 +339,8 @@
339 <0 3 IRQ_TYPE_LEVEL_HIGH>; 339 <0 3 IRQ_TYPE_LEVEL_HIGH>;
340 interrupt-names = "bit", "jpeg"; 340 interrupt-names = "bit", "jpeg";
341 clocks = <&clks IMX6QDL_CLK_VPU_AXI>, 341 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
342 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>, 342 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
343 <&clks IMX6QDL_CLK_OCRAM>; 343 clock-names = "per", "ahb";
344 clock-names = "per", "ahb", "ocram";
345 resets = <&src 1>; 344 resets = <&src 1>;
346 iram = <&ocram>; 345 iram = <&ocram>;
347 }; 346 };
diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts b/arch/arm/boot/dts/imx6sx-sabreauto.dts
new file mode 100644
index 000000000000..e3c0b63c2205
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts
@@ -0,0 +1,146 @@
1/*
2 * Copyright (C) 2014 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/dts-v1/;
10
11#include "imx6sx.dtsi"
12
13/ {
14 model = "Freescale i.MX6 SoloX Sabre Auto Board";
15 compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx";
16
17 memory {
18 reg = <0x80000000 0x80000000>;
19 };
20
21 regulators {
22 compatible = "simple-bus";
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 vcc_sd3: regulator@0 {
27 compatible = "regulator-fixed";
28 reg = <0>;
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_vcc_sd3>;
31 regulator-name = "VCC_SD3";
32 regulator-min-microvolt = <3000000>;
33 regulator-max-microvolt = <3000000>;
34 gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
35 enable-active-high;
36 };
37 };
38};
39
40&uart1 {
41 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_uart1>;
43 status = "okay";
44};
45
46&usdhc3 {
47 pinctrl-names = "default", "state_100mhz", "state_200mhz";
48 pinctrl-0 = <&pinctrl_usdhc3>;
49 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
50 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
51 bus-width = <8>;
52 cd-gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>;
53 wp-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
54 keep-power-in-suspend;
55 enable-sdio-wakeup;
56 vmmc-supply = <&vcc_sd3>;
57 status = "okay";
58};
59
60&usdhc4 {
61 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_usdhc4>;
63 bus-width = <8>;
64 cd-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
65 no-1-8-v;
66 keep-power-in-suspend;
67 enable-sdio-wakup;
68 status = "okay";
69};
70
71&iomuxc {
72 imx6x-sabreauto {
73 pinctrl_uart1: uart1grp {
74 fsl,pins = <
75 MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
76 MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
77 >;
78 };
79
80 pinctrl_usdhc3: usdhc3grp {
81 fsl,pins = <
82 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
83 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
84 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
85 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
86 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
87 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
88 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
89 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
90 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
91 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
92 MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
93 MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
94 >;
95 };
96
97 pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
98 fsl,pins = <
99 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
100 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
101 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
102 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
103 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
104 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
105 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
106 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
107 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
108 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
109 >;
110 };
111
112 pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
113 fsl,pins = <
114 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
115 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
116 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
117 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
118 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
119 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
120 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
121 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
122 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
123 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
124 >;
125 };
126
127 pinctrl_usdhc4: usdhc4grp {
128 fsl,pins = <
129 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
130 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
131 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
132 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
133 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
134 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
135 MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
136 MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
137 >;
138 };
139
140 pinctrl_vcc_sd3: vccsd3grp {
141 fsl,pins = <
142 MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
143 >;
144 };
145 };
146};
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts
index c108bb451337..32f07d6b4042 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb.dts
@@ -355,6 +355,28 @@
355 status = "okay"; 355 status = "okay";
356}; 356};
357 357
358&qspi2 {
359 pinctrl-names = "default";
360 pinctrl-0 = <&pinctrl_qspi2>;
361 status = "okay";
362
363 flash0: s25fl128s@0 {
364 reg = <0>;
365 #address-cells = <1>;
366 #size-cells = <1>;
367 compatible = "spansion,s25fl128s";
368 spi-max-frequency = <66000000>;
369 };
370
371 flash1: s25fl128s@1 {
372 reg = <1>;
373 #address-cells = <1>;
374 #size-cells = <1>;
375 compatible = "spansion,s25fl128s";
376 spi-max-frequency = <66000000>;
377 };
378};
379
358&ssi2 { 380&ssi2 {
359 status = "okay"; 381 status = "okay";
360}; 382};
@@ -539,6 +561,23 @@
539 >; 561 >;
540 }; 562 };
541 563
564 pinctrl_qspi2: qspi2grp {
565 fsl,pins = <
566 MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1
567 MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70f1
568 MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70f1
569 MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70f1
570 MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70f1
571 MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70f1
572 MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70f1
573 MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70f1
574 MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70f1
575 MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70f1
576 MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70f1
577 MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70f1
578 >;
579 };
580
542 pinctrl_vcc_sd3: vccsd3grp { 581 pinctrl_vcc_sd3: vccsd3grp {
543 fsl,pins = < 582 fsl,pins = <
544 MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 583 MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
diff --git a/arch/arm/boot/dts/kirkwood-6192.dtsi b/arch/arm/boot/dts/kirkwood-6192.dtsi
index dd81508b919b..9e6e9e2691d5 100644
--- a/arch/arm/boot/dts/kirkwood-6192.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6192.dtsi
@@ -66,6 +66,8 @@
66 interrupts = <21>; 66 interrupts = <21>;
67 clocks = <&gate_clk 14>, <&gate_clk 15>; 67 clocks = <&gate_clk 14>, <&gate_clk 15>;
68 clock-names = "0", "1"; 68 clock-names = "0", "1";
69 phys = <&sata_phy0>, <&sata_phy1>;
70 phy-names = "port0", "port1";
69 status = "disabled"; 71 status = "disabled";
70 }; 72 };
71 73
diff --git a/arch/arm/boot/dts/kirkwood-blackarmor-nas220.dts b/arch/arm/boot/dts/kirkwood-blackarmor-nas220.dts
new file mode 100644
index 000000000000..fa02a9aff05e
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-blackarmor-nas220.dts
@@ -0,0 +1,173 @@
1/*
2 * Device Tree file for Seagate Blackarmor NAS220
3 *
4 * Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com>
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9/dts-v1/;
10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/input/input.h>
13#include "kirkwood.dtsi"
14#include "kirkwood-6192.dtsi"
15
16/ {
17 model = "Seagate Blackarmor NAS220";
18 compatible = "seagate,blackarmor-nas220","marvell,kirkwood-88f6192",
19 "marvell,kirkwood";
20
21 memory { /* 128 MB */
22 device_type = "memory";
23 reg = <0x00000000 0x8000000>;
24 };
25
26 chosen {
27 bootargs = "console=ttyS0,115200n8";
28 stdout-path = &uart0;
29 };
30
31 gpio_poweroff {
32 compatible = "gpio-poweroff";
33 gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
34 };
35
36 gpio_keys {
37 compatible = "gpio-keys";
38
39 button@1{
40 label = "Reset";
41 linux,code = <KEY_POWER>;
42 gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
43 };
44
45 button@2{
46 label = "Power";
47 linux,code = <KEY_SLEEP>;
48 gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
49 };
50 };
51
52 gpio-leds {
53 compatible = "gpio-leds";
54
55 blue-power {
56 label = "nas220:blue:power";
57 gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
58 linux,default-trigger = "default-on";
59 };
60 };
61
62 regulators {
63 compatible = "simple-bus";
64 #address-cells = <1>;
65 #size-cells = <0>;
66 pinctrl-0 = <&pmx_power_sata0 &pmx_power_sata1>;
67 pinctrl-names = "default";
68
69 sata0_power: regulator@1 {
70 compatible = "regulator-fixed";
71 reg = <1>;
72 regulator-name = "SATA0 Power";
73 regulator-min-microvolt = <5000000>;
74 regulator-max-microvolt = <5000000>;
75 enable-active-high;
76 regulator-always-on;
77 regulator-boot-on;
78 gpio = <&gpio0 24 GPIO_ACTIVE_LOW>;
79 };
80
81 sata1_power: regulator@2 {
82 compatible = "regulator-fixed";
83 reg = <2>;
84 regulator-name = "SATA1 Power";
85 regulator-min-microvolt = <5000000>;
86 regulator-max-microvolt = <5000000>;
87 enable-active-high;
88 regulator-always-on;
89 regulator-boot-on;
90 gpio = <&gpio0 28 GPIO_ACTIVE_LOW>;
91 };
92 };
93};
94
95/*
96 * Serial port routed to connector CN5
97 *
98 * pin 1 - TX (CPU's TX)
99 * pin 4 - RX (CPU's RX)
100 * pin 6 - GND
101 */
102&uart0 {
103 status = "okay";
104};
105
106&pinctrl {
107 pinctrl-0 = <&pmx_button_reset &pmx_button_power>;
108 pinctrl-names = "default";
109
110 pmx_act_sata0: pmx-act-sata0 {
111 marvell,pins = "mpp15";
112 marvell,function = "sata0";
113 };
114
115 pmx_act_sata1: pmx-act-sata1 {
116 marvell,pins = "mpp16";
117 marvell,function = "sata1";
118 };
119
120 pmx_power_sata0: pmx-power-sata0 {
121 marvell,pins = "mpp24";
122 marvell,function = "gpio";
123 };
124
125 pmx_power_sata1: pmx-power-sata1 {
126 marvell,pins = "mpp28";
127 marvell,function = "gpio";
128 };
129
130 pmx_button_reset: pmx-button-reset {
131 marvell,pins = "mpp29";
132 marvell,function = "gpio";
133 };
134
135 pmx_button_power: pmx-button-power {
136 marvell,pins = "mpp26";
137 marvell,function = "gpio";
138 };
139};
140
141&sata {
142 status = "okay";
143 nr-ports = <2>;
144};
145
146&i2c0 {
147 status = "okay";
148
149 adt7476: thermal@2e {
150 compatible = "adi,adt7476";
151 reg = <0x2e>;
152 };
153};
154
155&nand {
156 status = "okay";
157};
158
159&mdio {
160 status = "okay";
161
162 ethphy0: ethernet-phy@8 {
163 reg = <8>;
164 };
165};
166
167&eth0 {
168 status = "okay";
169
170 ethernet0-port@0 {
171 phy-handle = <&ethphy0>;
172 };
173};
diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
index 05291f3990d0..8474bffec0ca 100644
--- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
+++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
@@ -169,6 +169,10 @@
169 gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; 169 gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
170 }; 170 };
171 }; 171 };
172 gpio-poweroff {
173 compatible = "gpio-poweroff";
174 gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
175 };
172}; 176};
173 177
174&nand { 178&nand {
@@ -192,8 +196,8 @@
192 }; 196 };
193 197
194 partition@400000 { 198 partition@400000 {
195 label = "uInitrd"; 199 label = "rootfs";
196 reg = <0x540000 0x1000000>; 200 reg = <0x400000 0x1C00000>;
197 }; 201 };
198}; 202};
199 203
diff --git a/arch/arm/boot/dts/kirkwood-pogo_e02.dts b/arch/arm/boot/dts/kirkwood-pogo_e02.dts
new file mode 100644
index 000000000000..a190080c9c4f
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-pogo_e02.dts
@@ -0,0 +1,134 @@
1/*
2 * kirkwood-pogo_e02.dts - Device tree file for Pogoplug E02
3 *
4 * Copyright (C) 2015 Christoph Junghans <ottxor@gentoo.org>
5 *
6 * based on information of dts files from
7 * Arch Linux ARM by Oleg Rakhmanov <moonman.ca@gmail.com>
8 * OpenWrt by Felix Kaechele <heffer@fedoraproject.org>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15/dts-v1/;
16
17#include "kirkwood.dtsi"
18#include "kirkwood-6281.dtsi"
19
20/ {
21 model = "Cloud Engines Pogoplug E02";
22 compatible = "cloudengines,pogoe02", "marvell,kirkwood-88f6281",
23 "marvell,kirkwood";
24
25 memory {
26 device_type = "memory";
27 reg = <0x00000000 0x10000000>;
28 };
29
30 chosen {
31 bootargs = "console=ttyS0,115200n8";
32 stdout-path = &uart0;
33 };
34
35 gpio-leds {
36 compatible = "gpio-leds";
37
38 health {
39 label = "pogo_e02:green:health";
40 gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
41 default-state = "keep";
42 };
43 fault {
44 label = "pogo_e02:orange:fault";
45 gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
46 };
47 };
48
49 regulators {
50 compatible = "simple-bus";
51 #address-cells = <1>;
52 #size-cells = <0>;
53 pinctrl-0 = <&pmx_usb_power_enable>;
54 pinctrl-names = "default";
55
56 usb_power: regulator@1 {
57 compatible = "regulator-fixed";
58 reg = <1>;
59 regulator-name = "USB Power";
60 regulator-min-microvolt = <5000000>;
61 regulator-max-microvolt = <5000000>;
62 enable-active-high;
63 regulator-always-on;
64 regulator-boot-on;
65 gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>;
66 };
67 };
68};
69
70&pinctrl {
71 pinctrl-0 = < &pmx_usb_power_enable &pmx_led_orange
72 &pmx_led_green >;
73 pinctrl-names = "default";
74
75 pmx_usb_power_enable: pmx-usb-power-enable {
76 marvell,pins = "mpp29";
77 marvell,function = "gpio";
78 };
79
80 pmx_led_green: pmx-led-green {
81 marvell,pins = "mpp48";
82 marvell,function = "gpio";
83 };
84
85 pmx_led_orange: pmx-led-orange {
86 marvell,pins = "mpp49";
87 marvell,function = "gpio";
88 };
89};
90
91&uart0 {
92 status = "okay";
93};
94
95&nand {
96 chip-delay = <40>;
97 status = "okay";
98
99 partition@0 {
100 label = "u-boot";
101 reg = <0x0000000 0x100000>;
102 read-only;
103 };
104
105 partition@100000 {
106 label = "uImage";
107 reg = <0x0100000 0x400000>;
108 };
109
110 partition@500000 {
111 label = "pogoplug";
112 reg = <0x0500000 0x2000000>;
113 };
114
115 partition@2500000 {
116 label = "root";
117 reg = <0x02500000 0x5b00000>;
118 };
119};
120
121&mdio {
122 status = "okay";
123
124 ethphy0: ethernet-phy@0 {
125 reg = <0>;
126 };
127};
128
129&eth0 {
130 status = "okay";
131 ethernet0-port@0 {
132 phy-handle = <&ethphy0>;
133 };
134};
diff --git a/arch/arm/boot/dts/marco-evb.dts b/arch/arm/boot/dts/marco-evb.dts
deleted file mode 100644
index 5130aeacfca5..000000000000
--- a/arch/arm/boot/dts/marco-evb.dts
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * DTS file for CSR SiRFmarco Evaluation Board
3 *
4 * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9/dts-v1/;
10
11/include/ "marco.dtsi"
12
13/ {
14 model = "CSR SiRFmarco Evaluation Board";
15 compatible = "sirf,marco-cb", "sirf,marco";
16
17 memory {
18 reg = <0x40000000 0x60000000>;
19 };
20
21 axi {
22 peri-iobg {
23 uart1: uart@cc060000 {
24 status = "okay";
25 };
26 uart2: uart@cc070000 {
27 status = "okay";
28 };
29 i2c0: i2c@cc0e0000 {
30 status = "okay";
31 fpga-cpld@4d {
32 compatible = "sirf,fpga-cpld";
33 reg = <0x4d>;
34 };
35 };
36 spi1: spi@cc170000 {
37 status = "okay";
38 pinctrl-names = "default";
39 pinctrl-0 = <&spi1_pins_a>;
40 spi@0 {
41 compatible = "spidev";
42 reg = <0>;
43 spi-max-frequency = <1000000>;
44 };
45 };
46 pci-iobg {
47 sd0: sdhci@cd000000 {
48 bus-width = <8>;
49 status = "okay";
50 };
51 };
52 };
53 };
54};
diff --git a/arch/arm/boot/dts/marco.dtsi b/arch/arm/boot/dts/marco.dtsi
deleted file mode 100644
index fb354225740a..000000000000
--- a/arch/arm/boot/dts/marco.dtsi
+++ /dev/null
@@ -1,757 +0,0 @@
1/*
2 * DTS file for CSR SiRFmarco SoC
3 *
4 * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9/include/ "skeleton.dtsi"
10/ {
11 compatible = "sirf,marco";
12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&gic>;
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 cpu@0 {
21 device_type = "cpu";
22 compatible = "arm,cortex-a9";
23 reg = <0>;
24 };
25 cpu@1 {
26 device_type = "cpu";
27 compatible = "arm,cortex-a9";
28 reg = <1>;
29 };
30 };
31
32 axi {
33 compatible = "simple-bus";
34 #address-cells = <1>;
35 #size-cells = <1>;
36 ranges = <0x40000000 0x40000000 0xa0000000>;
37
38 l2-cache-controller@c0030000 {
39 compatible = "arm,pl310-cache";
40 reg = <0xc0030000 0x1000>;
41 interrupts = <0 59 0>;
42 arm,tag-latency = <1 1 1>;
43 arm,data-latency = <1 1 1>;
44 arm,filter-ranges = <0x40000000 0x80000000>;
45 };
46
47 gic: interrupt-controller@c0011000 {
48 compatible = "arm,cortex-a9-gic";
49 interrupt-controller;
50 #interrupt-cells = <3>;
51 reg = <0xc0011000 0x1000>,
52 <0xc0010100 0x0100>;
53 };
54
55 rstc-iobg {
56 compatible = "simple-bus";
57 #address-cells = <1>;
58 #size-cells = <1>;
59 ranges = <0xc2000000 0xc2000000 0x1000000>;
60
61 rstc: reset-controller@c2000000 {
62 compatible = "sirf,marco-rstc";
63 reg = <0xc2000000 0x10000>;
64 #reset-cells = <1>;
65 };
66 };
67
68 sys-iobg {
69 compatible = "simple-bus";
70 #address-cells = <1>;
71 #size-cells = <1>;
72 ranges = <0xc3000000 0xc3000000 0x1000000>;
73
74 clock-controller@c3000000 {
75 compatible = "sirf,marco-clkc";
76 reg = <0xc3000000 0x1000>;
77 interrupts = <0 3 0>;
78 };
79
80 rsc-controller@c3010000 {
81 compatible = "sirf,marco-rsc";
82 reg = <0xc3010000 0x1000>;
83 };
84 };
85
86 mem-iobg {
87 compatible = "simple-bus";
88 #address-cells = <1>;
89 #size-cells = <1>;
90 ranges = <0xc4000000 0xc4000000 0x1000000>;
91
92 memory-controller@c4000000 {
93 compatible = "sirf,marco-memc";
94 reg = <0xc4000000 0x10000>;
95 interrupts = <0 27 0>;
96 };
97 };
98
99 disp-iobg0 {
100 compatible = "simple-bus";
101 #address-cells = <1>;
102 #size-cells = <1>;
103 ranges = <0xc5000000 0xc5000000 0x1000000>;
104
105 display0@c5000000 {
106 compatible = "sirf,marco-lcd";
107 reg = <0xc5000000 0x10000>;
108 interrupts = <0 30 0>;
109 };
110
111 vpp0@c5010000 {
112 compatible = "sirf,marco-vpp";
113 reg = <0xc5010000 0x10000>;
114 interrupts = <0 31 0>;
115 };
116 };
117
118 disp-iobg1 {
119 compatible = "simple-bus";
120 #address-cells = <1>;
121 #size-cells = <1>;
122 ranges = <0xc6000000 0xc6000000 0x1000000>;
123
124 display1@c6000000 {
125 compatible = "sirf,marco-lcd";
126 reg = <0xc6000000 0x10000>;
127 interrupts = <0 62 0>;
128 };
129
130 vpp1@c6010000 {
131 compatible = "sirf,marco-vpp";
132 reg = <0xc6010000 0x10000>;
133 interrupts = <0 63 0>;
134 };
135 };
136
137 graphics-iobg {
138 compatible = "simple-bus";
139 #address-cells = <1>;
140 #size-cells = <1>;
141 ranges = <0xc8000000 0xc8000000 0x1000000>;
142
143 graphics@c8000000 {
144 compatible = "powervr,sgx540";
145 reg = <0xc8000000 0x1000000>;
146 interrupts = <0 6 0>;
147 };
148 };
149
150 multimedia-iobg {
151 compatible = "simple-bus";
152 #address-cells = <1>;
153 #size-cells = <1>;
154 ranges = <0xc9000000 0xc9000000 0x1000000>;
155
156 multimedia@a0000000 {
157 compatible = "sirf,marco-video-codec";
158 reg = <0xc9000000 0x1000000>;
159 interrupts = <0 5 0>;
160 };
161 };
162
163 dsp-iobg {
164 compatible = "simple-bus";
165 #address-cells = <1>;
166 #size-cells = <1>;
167 ranges = <0xca000000 0xca000000 0x2000000>;
168
169 dspif@ca000000 {
170 compatible = "sirf,marco-dspif";
171 reg = <0xca000000 0x10000>;
172 interrupts = <0 9 0>;
173 };
174
175 gps@ca010000 {
176 compatible = "sirf,marco-gps";
177 reg = <0xca010000 0x10000>;
178 interrupts = <0 7 0>;
179 };
180
181 dsp@cb000000 {
182 compatible = "sirf,marco-dsp";
183 reg = <0xcb000000 0x1000000>;
184 interrupts = <0 8 0>;
185 };
186 };
187
188 peri-iobg {
189 compatible = "simple-bus";
190 #address-cells = <1>;
191 #size-cells = <1>;
192 ranges = <0xcc000000 0xcc000000 0x2000000>;
193
194 timer@cc020000 {
195 compatible = "sirf,marco-tick";
196 reg = <0xcc020000 0x1000>;
197 interrupts = <0 0 0>,
198 <0 1 0>,
199 <0 2 0>,
200 <0 49 0>,
201 <0 50 0>,
202 <0 51 0>;
203 };
204
205 nand@cc030000 {
206 compatible = "sirf,marco-nand";
207 reg = <0xcc030000 0x10000>;
208 interrupts = <0 41 0>;
209 };
210
211 audio@cc040000 {
212 compatible = "sirf,marco-audio";
213 reg = <0xcc040000 0x10000>;
214 interrupts = <0 35 0>;
215 };
216
217 uart0: uart@cc050000 {
218 cell-index = <0>;
219 compatible = "sirf,marco-uart";
220 reg = <0xcc050000 0x1000>;
221 interrupts = <0 17 0>;
222 fifosize = <128>;
223 status = "disabled";
224 };
225
226 uart1: uart@cc060000 {
227 cell-index = <1>;
228 compatible = "sirf,marco-uart";
229 reg = <0xcc060000 0x1000>;
230 interrupts = <0 18 0>;
231 fifosize = <32>;
232 status = "disabled";
233 };
234
235 uart2: uart@cc070000 {
236 cell-index = <2>;
237 compatible = "sirf,marco-uart";
238 reg = <0xcc070000 0x1000>;
239 interrupts = <0 19 0>;
240 fifosize = <128>;
241 status = "disabled";
242 };
243
244 uart3: uart@cc190000 {
245 cell-index = <3>;
246 compatible = "sirf,marco-uart";
247 reg = <0xcc190000 0x1000>;
248 interrupts = <0 66 0>;
249 fifosize = <128>;
250 status = "disabled";
251 };
252
253 uart4: uart@cc1a0000 {
254 cell-index = <4>;
255 compatible = "sirf,marco-uart";
256 reg = <0xcc1a0000 0x1000>;
257 interrupts = <0 69 0>;
258 fifosize = <128>;
259 status = "disabled";
260 };
261
262 usp0: usp@cc080000 {
263 cell-index = <0>;
264 compatible = "sirf,marco-usp";
265 reg = <0xcc080000 0x10000>;
266 interrupts = <0 20 0>;
267 status = "disabled";
268 };
269
270 usp1: usp@cc090000 {
271 cell-index = <1>;
272 compatible = "sirf,marco-usp";
273 reg = <0xcc090000 0x10000>;
274 interrupts = <0 21 0>;
275 status = "disabled";
276 };
277
278 usp2: usp@cc0a0000 {
279 cell-index = <2>;
280 compatible = "sirf,marco-usp";
281 reg = <0xcc0a0000 0x10000>;
282 interrupts = <0 22 0>;
283 status = "disabled";
284 };
285
286 dmac0: dma-controller@cc0b0000 {
287 cell-index = <0>;
288 compatible = "sirf,marco-dmac";
289 reg = <0xcc0b0000 0x10000>;
290 interrupts = <0 12 0>;
291 };
292
293 dmac1: dma-controller@cc160000 {
294 cell-index = <1>;
295 compatible = "sirf,marco-dmac";
296 reg = <0xcc160000 0x10000>;
297 interrupts = <0 13 0>;
298 };
299
300 vip@cc0c0000 {
301 compatible = "sirf,marco-vip";
302 reg = <0xcc0c0000 0x10000>;
303 };
304
305 spi0: spi@cc0d0000 {
306 cell-index = <0>;
307 compatible = "sirf,marco-spi";
308 reg = <0xcc0d0000 0x10000>;
309 interrupts = <0 15 0>;
310 sirf,spi-num-chipselects = <1>;
311 cs-gpios = <&gpio 0 0>;
312 sirf,spi-dma-rx-channel = <25>;
313 sirf,spi-dma-tx-channel = <20>;
314 #address-cells = <1>;
315 #size-cells = <0>;
316 status = "disabled";
317 };
318
319 spi1: spi@cc170000 {
320 cell-index = <1>;
321 compatible = "sirf,marco-spi";
322 reg = <0xcc170000 0x10000>;
323 interrupts = <0 16 0>;
324 sirf,spi-num-chipselects = <1>;
325 cs-gpios = <&gpio 0 0>;
326 sirf,spi-dma-rx-channel = <12>;
327 sirf,spi-dma-tx-channel = <13>;
328 #address-cells = <1>;
329 #size-cells = <0>;
330 status = "disabled";
331 };
332
333 i2c0: i2c@cc0e0000 {
334 cell-index = <0>;
335 compatible = "sirf,marco-i2c";
336 reg = <0xcc0e0000 0x10000>;
337 interrupts = <0 24 0>;
338 #address-cells = <1>;
339 #size-cells = <0>;
340 status = "disabled";
341 };
342
343 i2c1: i2c@cc0f0000 {
344 cell-index = <1>;
345 compatible = "sirf,marco-i2c";
346 reg = <0xcc0f0000 0x10000>;
347 interrupts = <0 25 0>;
348 #address-cells = <1>;
349 #size-cells = <0>;
350 status = "disabled";
351 };
352
353 tsc@cc110000 {
354 compatible = "sirf,marco-tsc";
355 reg = <0xcc110000 0x10000>;
356 interrupts = <0 33 0>;
357 };
358
359 gpio: pinctrl@cc120000 {
360 #gpio-cells = <2>;
361 #interrupt-cells = <2>;
362 compatible = "sirf,marco-pinctrl";
363 reg = <0xcc120000 0x10000>;
364 interrupts = <0 43 0>,
365 <0 44 0>,
366 <0 45 0>,
367 <0 46 0>,
368 <0 47 0>;
369 gpio-controller;
370 interrupt-controller;
371
372 lcd_16pins_a: lcd0_0 {
373 lcd {
374 sirf,pins = "lcd_16bitsgrp";
375 sirf,function = "lcd_16bits";
376 };
377 };
378 lcd_18pins_a: lcd0_1 {
379 lcd {
380 sirf,pins = "lcd_18bitsgrp";
381 sirf,function = "lcd_18bits";
382 };
383 };
384 lcd_24pins_a: lcd0_2 {
385 lcd {
386 sirf,pins = "lcd_24bitsgrp";
387 sirf,function = "lcd_24bits";
388 };
389 };
390 lcdrom_pins_a: lcdrom0_0 {
391 lcd {
392 sirf,pins = "lcdromgrp";
393 sirf,function = "lcdrom";
394 };
395 };
396 uart0_pins_a: uart0_0 {
397 uart {
398 sirf,pins = "uart0grp";
399 sirf,function = "uart0";
400 };
401 };
402 uart1_pins_a: uart1_0 {
403 uart {
404 sirf,pins = "uart1grp";
405 sirf,function = "uart1";
406 };
407 };
408 uart2_pins_a: uart2_0 {
409 uart {
410 sirf,pins = "uart2grp";
411 sirf,function = "uart2";
412 };
413 };
414 uart2_noflow_pins_a: uart2_1 {
415 uart {
416 sirf,pins = "uart2_nostreamctrlgrp";
417 sirf,function = "uart2_nostreamctrl";
418 };
419 };
420 spi0_pins_a: spi0_0 {
421 spi {
422 sirf,pins = "spi0grp";
423 sirf,function = "spi0";
424 };
425 };
426 spi1_pins_a: spi1_0 {
427 spi {
428 sirf,pins = "spi1grp";
429 sirf,function = "spi1";
430 };
431 };
432 i2c0_pins_a: i2c0_0 {
433 i2c {
434 sirf,pins = "i2c0grp";
435 sirf,function = "i2c0";
436 };
437 };
438 i2c1_pins_a: i2c1_0 {
439 i2c {
440 sirf,pins = "i2c1grp";
441 sirf,function = "i2c1";
442 };
443 };
444 pwm0_pins_a: pwm0_0 {
445 pwm {
446 sirf,pins = "pwm0grp";
447 sirf,function = "pwm0";
448 };
449 };
450 pwm1_pins_a: pwm1_0 {
451 pwm {
452 sirf,pins = "pwm1grp";
453 sirf,function = "pwm1";
454 };
455 };
456 pwm2_pins_a: pwm2_0 {
457 pwm {
458 sirf,pins = "pwm2grp";
459 sirf,function = "pwm2";
460 };
461 };
462 pwm3_pins_a: pwm3_0 {
463 pwm {
464 sirf,pins = "pwm3grp";
465 sirf,function = "pwm3";
466 };
467 };
468 gps_pins_a: gps_0 {
469 gps {
470 sirf,pins = "gpsgrp";
471 sirf,function = "gps";
472 };
473 };
474 vip_pins_a: vip_0 {
475 vip {
476 sirf,pins = "vipgrp";
477 sirf,function = "vip";
478 };
479 };
480 sdmmc0_pins_a: sdmmc0_0 {
481 sdmmc0 {
482 sirf,pins = "sdmmc0grp";
483 sirf,function = "sdmmc0";
484 };
485 };
486 sdmmc1_pins_a: sdmmc1_0 {
487 sdmmc1 {
488 sirf,pins = "sdmmc1grp";
489 sirf,function = "sdmmc1";
490 };
491 };
492 sdmmc2_pins_a: sdmmc2_0 {
493 sdmmc2 {
494 sirf,pins = "sdmmc2grp";
495 sirf,function = "sdmmc2";
496 };
497 };
498 sdmmc3_pins_a: sdmmc3_0 {
499 sdmmc3 {
500 sirf,pins = "sdmmc3grp";
501 sirf,function = "sdmmc3";
502 };
503 };
504 sdmmc4_pins_a: sdmmc4_0 {
505 sdmmc4 {
506 sirf,pins = "sdmmc4grp";
507 sirf,function = "sdmmc4";
508 };
509 };
510 sdmmc5_pins_a: sdmmc5_0 {
511 sdmmc5 {
512 sirf,pins = "sdmmc5grp";
513 sirf,function = "sdmmc5";
514 };
515 };
516 i2s_pins_a: i2s_0 {
517 i2s {
518 sirf,pins = "i2sgrp";
519 sirf,function = "i2s";
520 };
521 };
522 ac97_pins_a: ac97_0 {
523 ac97 {
524 sirf,pins = "ac97grp";
525 sirf,function = "ac97";
526 };
527 };
528 nand_pins_a: nand_0 {
529 nand {
530 sirf,pins = "nandgrp";
531 sirf,function = "nand";
532 };
533 };
534 usp0_pins_a: usp0_0 {
535 usp0 {
536 sirf,pins = "usp0grp";
537 sirf,function = "usp0";
538 };
539 };
540 usp1_pins_a: usp1_0 {
541 usp1 {
542 sirf,pins = "usp1grp";
543 sirf,function = "usp1";
544 };
545 };
546 usp2_pins_a: usp2_0 {
547 usp2 {
548 sirf,pins = "usp2grp";
549 sirf,function = "usp2";
550 };
551 };
552 usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus_0 {
553 usb0_utmi_drvbus {
554 sirf,pins = "usb0_utmi_drvbusgrp";
555 sirf,function = "usb0_utmi_drvbus";
556 };
557 };
558 usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus_0 {
559 usb1_utmi_drvbus {
560 sirf,pins = "usb1_utmi_drvbusgrp";
561 sirf,function = "usb1_utmi_drvbus";
562 };
563 };
564 warm_rst_pins_a: warm_rst_0 {
565 warm_rst {
566 sirf,pins = "warm_rstgrp";
567 sirf,function = "warm_rst";
568 };
569 };
570 pulse_count_pins_a: pulse_count_0 {
571 pulse_count {
572 sirf,pins = "pulse_countgrp";
573 sirf,function = "pulse_count";
574 };
575 };
576 cko0_rst_pins_a: cko0_rst_0 {
577 cko0_rst {
578 sirf,pins = "cko0_rstgrp";
579 sirf,function = "cko0_rst";
580 };
581 };
582 cko1_rst_pins_a: cko1_rst_0 {
583 cko1_rst {
584 sirf,pins = "cko1_rstgrp";
585 sirf,function = "cko1_rst";
586 };
587 };
588 };
589
590 pwm@cc130000 {
591 compatible = "sirf,marco-pwm";
592 reg = <0xcc130000 0x10000>;
593 };
594
595 efusesys@cc140000 {
596 compatible = "sirf,marco-efuse";
597 reg = <0xcc140000 0x10000>;
598 };
599
600 pulsec@cc150000 {
601 compatible = "sirf,marco-pulsec";
602 reg = <0xcc150000 0x10000>;
603 interrupts = <0 48 0>;
604 };
605
606 pci-iobg {
607 compatible = "sirf,marco-pciiobg", "simple-bus";
608 #address-cells = <1>;
609 #size-cells = <1>;
610 ranges = <0xcd000000 0xcd000000 0x1000000>;
611
612 sd0: sdhci@cd000000 {
613 cell-index = <0>;
614 compatible = "sirf,marco-sdhc";
615 reg = <0xcd000000 0x100000>;
616 interrupts = <0 38 0>;
617 status = "disabled";
618 };
619
620 sd1: sdhci@cd100000 {
621 cell-index = <1>;
622 compatible = "sirf,marco-sdhc";
623 reg = <0xcd100000 0x100000>;
624 interrupts = <0 38 0>;
625 status = "disabled";
626 };
627
628 sd2: sdhci@cd200000 {
629 cell-index = <2>;
630 compatible = "sirf,marco-sdhc";
631 reg = <0xcd200000 0x100000>;
632 interrupts = <0 23 0>;
633 status = "disabled";
634 };
635
636 sd3: sdhci@cd300000 {
637 cell-index = <3>;
638 compatible = "sirf,marco-sdhc";
639 reg = <0xcd300000 0x100000>;
640 interrupts = <0 23 0>;
641 status = "disabled";
642 };
643
644 sd4: sdhci@cd400000 {
645 cell-index = <4>;
646 compatible = "sirf,marco-sdhc";
647 reg = <0xcd400000 0x100000>;
648 interrupts = <0 39 0>;
649 status = "disabled";
650 };
651
652 sd5: sdhci@cd500000 {
653 cell-index = <5>;
654 compatible = "sirf,marco-sdhc";
655 reg = <0xcd500000 0x100000>;
656 interrupts = <0 39 0>;
657 status = "disabled";
658 };
659
660 pci-copy@cd900000 {
661 compatible = "sirf,marco-pcicp";
662 reg = <0xcd900000 0x100000>;
663 interrupts = <0 40 0>;
664 };
665
666 rom-interface@cda00000 {
667 compatible = "sirf,marco-romif";
668 reg = <0xcda00000 0x100000>;
669 };
670 };
671 };
672
673 rtc-iobg {
674 compatible = "sirf,marco-rtciobg", "sirf-marco-rtciobg-bus";
675 #address-cells = <1>;
676 #size-cells = <1>;
677 reg = <0xc1000000 0x10000>;
678
679 gpsrtc@1000 {
680 compatible = "sirf,marco-gpsrtc";
681 reg = <0x1000 0x1000>;
682 interrupts = <0 55 0>,
683 <0 56 0>,
684 <0 57 0>;
685 };
686
687 sysrtc@2000 {
688 compatible = "sirf,marco-sysrtc";
689 reg = <0x2000 0x1000>;
690 interrupts = <0 52 0>,
691 <0 53 0>,
692 <0 54 0>;
693 };
694
695 pwrc@3000 {
696 compatible = "sirf,marco-pwrc";
697 reg = <0x3000 0x1000>;
698 interrupts = <0 32 0>;
699 };
700 };
701
702 uus-iobg {
703 compatible = "simple-bus";
704 #address-cells = <1>;
705 #size-cells = <1>;
706 ranges = <0xce000000 0xce000000 0x1000000>;
707
708 usb0: usb@ce000000 {
709 compatible = "chipidea,ci13611a-marco";
710 reg = <0xce000000 0x10000>;
711 interrupts = <0 10 0>;
712 };
713
714 usb1: usb@ce010000 {
715 compatible = "chipidea,ci13611a-marco";
716 reg = <0xce010000 0x10000>;
717 interrupts = <0 11 0>;
718 };
719
720 security@ce020000 {
721 compatible = "sirf,marco-security";
722 reg = <0xce020000 0x10000>;
723 interrupts = <0 42 0>;
724 };
725 };
726
727 can-iobg {
728 compatible = "simple-bus";
729 #address-cells = <1>;
730 #size-cells = <1>;
731 ranges = <0xd0000000 0xd0000000 0x1000000>;
732
733 can0: can@d0000000 {
734 compatible = "sirf,marco-can";
735 reg = <0xd0000000 0x10000>;
736 };
737
738 can1: can@d0010000 {
739 compatible = "sirf,marco-can";
740 reg = <0xd0010000 0x10000>;
741 };
742 };
743
744 lvds-iobg {
745 compatible = "simple-bus";
746 #address-cells = <1>;
747 #size-cells = <1>;
748 ranges = <0xd1000000 0xd1000000 0x1000000>;
749
750 lvds@d1000000 {
751 compatible = "sirf,marco-lvds";
752 reg = <0xd1000000 0x10000>;
753 interrupts = <0 64 0>;
754 };
755 };
756 };
757};
diff --git a/arch/arm/boot/dts/mt6589-aquaris5.dts b/arch/arm/boot/dts/mt6589-aquaris5.dts
index 0da047013120..594a6f3bebda 100644
--- a/arch/arm/boot/dts/mt6589-aquaris5.dts
+++ b/arch/arm/boot/dts/mt6589-aquaris5.dts
@@ -21,10 +21,20 @@
21 compatible = "mundoreader,bq-aquaris5", "mediatek,mt6589"; 21 compatible = "mundoreader,bq-aquaris5", "mediatek,mt6589";
22 22
23 chosen { 23 chosen {
24 bootargs = "earlyprintk"; 24 bootargs = "console=ttyS0,921600n8 earlyprintk";
25 stdout-path = &uart0;
25 }; 26 };
26 27
27 memory { 28 memory {
28 reg = <0x80000000 0x40000000>; 29 reg = <0x80000000 0x40000000>;
29 }; 30 };
31
32};
33
34&uart0 {
35 status = "okay";
36};
37
38&uart3 {
39 status = "okay";
30}; 40};
diff --git a/arch/arm/boot/dts/mt6589.dtsi b/arch/arm/boot/dts/mt6589.dtsi
index e3c7600ddb38..106b61b10030 100644
--- a/arch/arm/boot/dts/mt6589.dtsi
+++ b/arch/arm/boot/dts/mt6589.dtsi
@@ -19,7 +19,7 @@
19 19
20/ { 20/ {
21 compatible = "mediatek,mt6589"; 21 compatible = "mediatek,mt6589";
22 interrupt-parent = <&gic>; 22 interrupt-parent = <&sysirq>;
23 23
24 cpus { 24 cpus {
25 #address-cells = <1>; 25 #address-cells = <1>;
@@ -65,6 +65,12 @@
65 clock-frequency = <32000>; 65 clock-frequency = <32000>;
66 #clock-cells = <0>; 66 #clock-cells = <0>;
67 }; 67 };
68
69 uart_clk: dummy26m {
70 compatible = "fixed-clock";
71 clock-frequency = <26000000>;
72 #clock-cells = <0>;
73 };
68 }; 74 };
69 75
70 soc { 76 soc {
@@ -76,19 +82,61 @@
76 timer: timer@10008000 { 82 timer: timer@10008000 {
77 compatible = "mediatek,mt6577-timer"; 83 compatible = "mediatek,mt6577-timer";
78 reg = <0x10008000 0x80>; 84 reg = <0x10008000 0x80>;
79 interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>; 85 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
80 clocks = <&system_clk>, <&rtc_clk>; 86 clocks = <&system_clk>, <&rtc_clk>;
81 clock-names = "system-clk", "rtc-clk"; 87 clock-names = "system-clk", "rtc-clk";
82 }; 88 };
83 89
90 sysirq: interrupt-controller@10200100 {
91 compatible = "mediatek,mt6589-sysirq",
92 "mediatek,mt6577-sysirq";
93 interrupt-controller;
94 #interrupt-cells = <3>;
95 interrupt-parent = <&gic>;
96 reg = <0x10200100 0x1c>;
97 };
98
84 gic: interrupt-controller@10211000 { 99 gic: interrupt-controller@10211000 {
85 compatible = "arm,cortex-a7-gic"; 100 compatible = "arm,cortex-a7-gic";
86 interrupt-controller; 101 interrupt-controller;
87 #interrupt-cells = <3>; 102 #interrupt-cells = <3>;
103 interrupt-parent = <&gic>;
88 reg = <0x10211000 0x1000>, 104 reg = <0x10211000 0x1000>,
89 <0x10212000 0x1000>, 105 <0x10212000 0x1000>,
90 <0x10214000 0x2000>, 106 <0x10214000 0x2000>,
91 <0x10216000 0x2000>; 107 <0x10216000 0x2000>;
92 }; 108 };
109
110 uart0: serial@11006000 {
111 compatible = "mediatek,mt6577-uart";
112 reg = <0x11006000 0x400>;
113 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
114 clocks = <&uart_clk>;
115 status = "disabled";
116 };
117
118 uart1: serial@11007000 {
119 compatible = "mediatek,mt6577-uart";
120 reg = <0x11007000 0x400>;
121 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
122 clocks = <&uart_clk>;
123 status = "disabled";
124 };
125
126 uart2: serial@11008000 {
127 compatible = "mediatek,mt6577-uart";
128 reg = <0x11008000 0x400>;
129 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
130 clocks = <&uart_clk>;
131 status = "disabled";
132 };
133
134 uart3: serial@11009000 {
135 compatible = "mediatek,mt6577-uart";
136 reg = <0x11009000 0x400>;
137 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
138 clocks = <&uart_clk>;
139 status = "disabled";
140 };
93 }; 141 };
94}; 142};
diff --git a/arch/arm/boot/dts/mt6592.dtsi b/arch/arm/boot/dts/mt6592.dtsi
index 31e5a0979d78..c69201ffff72 100644
--- a/arch/arm/boot/dts/mt6592.dtsi
+++ b/arch/arm/boot/dts/mt6592.dtsi
@@ -18,7 +18,7 @@
18 18
19/ { 19/ {
20 compatible = "mediatek,mt6592"; 20 compatible = "mediatek,mt6592";
21 interrupt-parent = <&gic>; 21 interrupt-parent = <&sysirq>;
22 22
23 cpus { 23 cpus {
24 #address-cells = <1>; 24 #address-cells = <1>;
@@ -78,21 +78,66 @@
78 #clock-cells = <0>; 78 #clock-cells = <0>;
79 }; 79 };
80 80
81 uart_clk: dummy26m {
82 compatible = "fixed-clock";
83 clock-frequency = <26000000>;
84 #clock-cells = <0>;
85 };
86
81 timer: timer@10008000 { 87 timer: timer@10008000 {
82 compatible = "mediatek,mt6577-timer"; 88 compatible = "mediatek,mt6577-timer";
83 reg = <0x10008000 0x80>; 89 reg = <0x10008000 0x80>;
84 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 90 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
85 clocks = <&system_clk>, <&rtc_clk>; 91 clocks = <&system_clk>, <&rtc_clk>;
86 clock-names = "system-clk", "rtc-clk"; 92 clock-names = "system-clk", "rtc-clk";
87 }; 93 };
88 94
95 sysirq: interrupt-controller@10200220 {
96 compatible = "mediatek,mt6592-sysirq", "mediatek,mt6577-sysirq";
97 interrupt-controller;
98 #interrupt-cells = <3>;
99 interrupt-parent = <&gic>;
100 reg = <0x10200220 0x1c>;
101 };
102
89 gic: interrupt-controller@10211000 { 103 gic: interrupt-controller@10211000 {
90 compatible = "arm,cortex-a7-gic"; 104 compatible = "arm,cortex-a7-gic";
91 interrupt-controller; 105 interrupt-controller;
92 #interrupt-cells = <3>; 106 #interrupt-cells = <3>;
107 interrupt-parent = <&gic>;
93 reg = <0x10211000 0x1000>, 108 reg = <0x10211000 0x1000>,
94 <0x10212000 0x1000>; 109 <0x10212000 0x1000>;
95 }; 110 };
96 111
97}; 112 uart0: serial@11002000 {
113 compatible = "mediatek,mt6577-uart";
114 reg = <0x11002000 0x400>;
115 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
116 clocks = <&uart_clk>;
117 status = "disabled";
118 };
119
120 uart1: serial@11003000 {
121 compatible = "mediatek,mt6577-uart";
122 reg = <0x11003000 0x400>;
123 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
124 clocks = <&uart_clk>;
125 status = "disabled";
126 };
98 127
128 uart2: serial@11004000 {
129 compatible = "mediatek,mt6577-uart";
130 reg = <0x11004000 0x400>;
131 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
132 clocks = <&uart_clk>;
133 status = "disabled";
134 };
135
136 uart3: serial@11005000 {
137 compatible = "mediatek,mt6577-uart";
138 reg = <0x11005000 0x400>;
139 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
140 clocks = <&uart_clk>;
141 status = "disabled";
142 };
143};
diff --git a/arch/arm/boot/dts/mt8127-moose.dts b/arch/arm/boot/dts/mt8127-moose.dts
index 13cba0e77e08..073e295a1cb4 100644
--- a/arch/arm/boot/dts/mt8127-moose.dts
+++ b/arch/arm/boot/dts/mt8127-moose.dts
@@ -23,3 +23,7 @@
23 reg = <0 0x80000000 0 0x40000000>; 23 reg = <0 0x80000000 0 0x40000000>;
24 }; 24 };
25}; 25};
26
27&uart0 {
28 status = "okay";
29};
diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mt8127.dtsi
index b24c0a2f3c44..aaa786233d93 100644
--- a/arch/arm/boot/dts/mt8127.dtsi
+++ b/arch/arm/boot/dts/mt8127.dtsi
@@ -18,7 +18,7 @@
18 18
19/ { 19/ {
20 compatible = "mediatek,mt8127"; 20 compatible = "mediatek,mt8127";
21 interrupt-parent = <&gic>; 21 interrupt-parent = <&sysirq>;
22 22
23 cpus { 23 cpus {
24 #address-cells = <1>; 24 #address-cells = <1>;
@@ -64,6 +64,12 @@
64 clock-frequency = <32000>; 64 clock-frequency = <32000>;
65 #clock-cells = <0>; 65 #clock-cells = <0>;
66 }; 66 };
67
68 uart_clk: dummy26m {
69 compatible = "fixed-clock";
70 clock-frequency = <26000000>;
71 #clock-cells = <0>;
72 };
67 }; 73 };
68 74
69 soc { 75 soc {
@@ -76,19 +82,61 @@
76 compatible = "mediatek,mt8127-timer", 82 compatible = "mediatek,mt8127-timer",
77 "mediatek,mt6577-timer"; 83 "mediatek,mt6577-timer";
78 reg = <0 0x10008000 0 0x80>; 84 reg = <0 0x10008000 0 0x80>;
79 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 85 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
80 clocks = <&system_clk>, <&rtc_clk>; 86 clocks = <&system_clk>, <&rtc_clk>;
81 clock-names = "system-clk", "rtc-clk"; 87 clock-names = "system-clk", "rtc-clk";
82 }; 88 };
83 89
90 sysirq: interrupt-controller@10200100 {
91 compatible = "mediatek,mt8127-sysirq",
92 "mediatek,mt6577-sysirq";
93 interrupt-controller;
94 #interrupt-cells = <3>;
95 interrupt-parent = <&gic>;
96 reg = <0 0x10200100 0 0x1c>;
97 };
98
84 gic: interrupt-controller@10211000 { 99 gic: interrupt-controller@10211000 {
85 compatible = "arm,cortex-a7-gic"; 100 compatible = "arm,cortex-a7-gic";
86 interrupt-controller; 101 interrupt-controller;
87 #interrupt-cells = <3>; 102 #interrupt-cells = <3>;
103 interrupt-parent = <&gic>;
88 reg = <0 0x10211000 0 0x1000>, 104 reg = <0 0x10211000 0 0x1000>,
89 <0 0x10212000 0 0x1000>, 105 <0 0x10212000 0 0x1000>,
90 <0 0x10214000 0 0x2000>, 106 <0 0x10214000 0 0x2000>,
91 <0 0x10216000 0 0x2000>; 107 <0 0x10216000 0 0x2000>;
92 }; 108 };
109
110 uart0: serial@11006000 {
111 compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
112 reg = <0 0x11002000 0 0x400>;
113 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
114 clocks = <&uart_clk>;
115 status = "disabled";
116 };
117
118 uart1: serial@11007000 {
119 compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
120 reg = <0 0x11003000 0 0x400>;
121 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
122 clocks = <&uart_clk>;
123 status = "disabled";
124 };
125
126 uart2: serial@11008000 {
127 compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
128 reg = <0 0x11004000 0 0x400>;
129 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
130 clocks = <&uart_clk>;
131 status = "disabled";
132 };
133
134 uart3: serial@11009000 {
135 compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
136 reg = <0 0x11005000 0 0x400>;
137 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
138 clocks = <&uart_clk>;
139 status = "disabled";
140 };
93 }; 141 };
94}; 142};
diff --git a/arch/arm/boot/dts/mt8135-evbp1.dts b/arch/arm/boot/dts/mt8135-evbp1.dts
index a5adf9742308..36677382bdd8 100644
--- a/arch/arm/boot/dts/mt8135-evbp1.dts
+++ b/arch/arm/boot/dts/mt8135-evbp1.dts
@@ -23,3 +23,7 @@
23 reg = <0 0x80000000 0 0x40000000>; 23 reg = <0 0x80000000 0 0x40000000>;
24 }; 24 };
25}; 25};
26
27&uart3 {
28 status = "okay";
29};
diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
index 7d56a986358e..a161e99ffcc4 100644
--- a/arch/arm/boot/dts/mt8135.dtsi
+++ b/arch/arm/boot/dts/mt8135.dtsi
@@ -18,7 +18,7 @@
18 18
19/ { 19/ {
20 compatible = "mediatek,mt8135"; 20 compatible = "mediatek,mt8135";
21 interrupt-parent = <&gic>; 21 interrupt-parent = <&sysirq>;
22 22
23 cpu-map { 23 cpu-map {
24 cluster0 { 24 cluster0 {
@@ -86,6 +86,13 @@
86 clock-frequency = <32000>; 86 clock-frequency = <32000>;
87 #clock-cells = <0>; 87 #clock-cells = <0>;
88 }; 88 };
89
90 uart_clk: dummy26m {
91 compatible = "fixed-clock";
92 clock-frequency = <26000000>;
93 #clock-cells = <0>;
94 };
95
89 }; 96 };
90 97
91 soc { 98 soc {
@@ -98,19 +105,62 @@
98 compatible = "mediatek,mt8135-timer", 105 compatible = "mediatek,mt8135-timer",
99 "mediatek,mt6577-timer"; 106 "mediatek,mt6577-timer";
100 reg = <0 0x10008000 0 0x80>; 107 reg = <0 0x10008000 0 0x80>;
101 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 108 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
102 clocks = <&system_clk>, <&rtc_clk>; 109 clocks = <&system_clk>, <&rtc_clk>;
103 clock-names = "system-clk", "rtc-clk"; 110 clock-names = "system-clk", "rtc-clk";
104 }; 111 };
105 112
113 sysirq: interrupt-controller@10200030 {
114 compatible = "mediatek,mt8135-sysirq",
115 "mediatek,mt6577-sysirq";
116 interrupt-controller;
117 #interrupt-cells = <3>;
118 interrupt-parent = <&gic>;
119 reg = <0 0x10200030 0 0x1c>;
120 };
121
106 gic: interrupt-controller@10211000 { 122 gic: interrupt-controller@10211000 {
107 compatible = "arm,cortex-a15-gic"; 123 compatible = "arm,cortex-a15-gic";
108 interrupt-controller; 124 interrupt-controller;
109 #interrupt-cells = <3>; 125 #interrupt-cells = <3>;
126 interrupt-parent = <&gic>;
110 reg = <0 0x10211000 0 0x1000>, 127 reg = <0 0x10211000 0 0x1000>,
111 <0 0x10212000 0 0x1000>, 128 <0 0x10212000 0 0x1000>,
112 <0 0x10214000 0 0x2000>, 129 <0 0x10214000 0 0x2000>,
113 <0 0x10216000 0 0x2000>; 130 <0 0x10216000 0 0x2000>;
114 }; 131 };
132
133 uart0: serial@11006000 {
134 compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
135 reg = <0 0x11006000 0 0x400>;
136 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
137 clocks = <&uart_clk>;
138 status = "disabled";
139 };
140
141 uart1: serial@11007000 {
142 compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
143 reg = <0 0x11007000 0 0x400>;
144 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
145 clocks = <&uart_clk>;
146 status = "disabled";
147 };
148
149 uart2: serial@11008000 {
150 compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
151 reg = <0 0x11008000 0 0x400>;
152 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
153 clocks = <&uart_clk>;
154 status = "disabled";
155 };
156
157 uart3: serial@11009000 {
158 compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
159 reg = <0 0x11009000 0 0x400>;
160 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
161 clocks = <&uart_clk>;
162 status = "disabled";
163 };
164
115 }; 165 };
116}; 166};
diff --git a/arch/arm/boot/dts/omap3-cm-t3x.dtsi b/arch/arm/boot/dts/omap3-cm-t3x.dtsi
index 6ea6d460db30..4d091ca43e25 100644
--- a/arch/arm/boot/dts/omap3-cm-t3x.dtsi
+++ b/arch/arm/boot/dts/omap3-cm-t3x.dtsi
@@ -259,3 +259,61 @@
259 pinctrl-names = "default"; 259 pinctrl-names = "default";
260 pinctrl-0 = <&mcbsp2_pins>; 260 pinctrl-0 = <&mcbsp2_pins>;
261}; 261};
262
263&gpmc {
264 ranges = <0 0 0x00000000 0x01000000>;
265
266 nand@0,0 {
267 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
268 nand-bus-width = <8>;
269 gpmc,device-width = <1>;
270 ti,nand-ecc-opt = "sw";
271
272 gpmc,cs-on-ns = <0>;
273 gpmc,cs-rd-off-ns = <120>;
274 gpmc,cs-wr-off-ns = <120>;
275
276 gpmc,adv-on-ns = <0>;
277 gpmc,adv-rd-off-ns = <120>;
278 gpmc,adv-wr-off-ns = <120>;
279
280 gpmc,we-on-ns = <6>;
281 gpmc,we-off-ns = <90>;
282
283 gpmc,oe-on-ns = <6>;
284 gpmc,oe-off-ns = <90>;
285
286 gpmc,page-burst-access-ns = <6>;
287 gpmc,access-ns = <72>;
288 gpmc,cycle2cycle-delay-ns = <60>;
289
290 gpmc,rd-cycle-ns = <120>;
291 gpmc,wr-cycle-ns = <120>;
292 gpmc,wr-access-ns = <186>;
293 gpmc,wr-data-mux-bus-ns = <90>;
294
295 #address-cells = <1>;
296 #size-cells = <1>;
297
298 partition@0 {
299 label = "xloader";
300 reg = <0 0x80000>;
301 };
302 partition@0x80000 {
303 label = "uboot";
304 reg = <0x80000 0x1e0000>;
305 };
306 partition@0x260000 {
307 label = "uboot environment";
308 reg = <0x260000 0x40000>;
309 };
310 partition@0x2a0000 {
311 label = "linux";
312 reg = <0x2a0000 0x400000>;
313 };
314 partition@0x6a0000 {
315 label = "rootfs";
316 reg = <0x6a0000 0x1f880000>;
317 };
318 };
319};
diff --git a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
index 9a4a3ab9af78..d9e92b654f85 100644
--- a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
+++ b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
@@ -50,7 +50,8 @@
50#include "omap-gpmc-smsc911x.dtsi" 50#include "omap-gpmc-smsc911x.dtsi"
51 51
52&gpmc { 52&gpmc {
53 ranges = <5 0 0x2c000000 0x01000000>; 53 ranges = <5 0 0x2c000000 0x01000000>, /* CM-T3x30 SMSC9x Eth */
54 <0 0 0x00000000 0x01000000>; /* CM-T3x NAND */
54 55
55 smsc1: ethernet@gpmc { 56 smsc1: ethernet@gpmc {
56 compatible = "smsc,lan9221", "smsc,lan9115"; 57 compatible = "smsc,lan9221", "smsc,lan9115";
diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi
index 655d6e920a86..fb3a69604ed5 100644
--- a/arch/arm/boot/dts/omap3-gta04.dtsi
+++ b/arch/arm/boot/dts/omap3-gta04.dtsi
@@ -83,6 +83,41 @@
83 compatible = "usb-nop-xceiv"; 83 compatible = "usb-nop-xceiv";
84 reset-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; 84 reset-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
85 }; 85 };
86
87 tv0: connector@1 {
88 compatible = "svideo-connector";
89 label = "tv";
90
91 port {
92 tv_connector_in: endpoint {
93 remote-endpoint = <&opa_out>;
94 };
95 };
96 };
97
98 tv_amp: opa362 {
99 compatible = "ti,opa362";
100 enable-gpios = <&gpio1 23 0>;
101
102 ports {
103 #address-cells = <1>;
104 #size-cells = <0>;
105
106 port@0 {
107 reg = <0>;
108 opa_in: endpoint@0 {
109 remote-endpoint = <&venc_out>;
110 };
111 };
112
113 port@1 {
114 reg = <1>;
115 opa_out: endpoint@0 {
116 remote-endpoint = <&tv_connector_in>;
117 };
118 };
119 };
120 };
86}; 121};
87 122
88&omap3_pmx_core { 123&omap3_pmx_core {
@@ -202,11 +237,18 @@
202 reg = <0x48>; 237 reg = <0x48>;
203 interrupts = <7>; /* SYS_NIRQ cascaded to intc */ 238 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
204 interrupt-parent = <&intc>; 239 interrupt-parent = <&intc>;
205 };
206 240
207 twl_audio: audio { 241 twl_audio: audio {
208 compatible = "ti,twl4030-audio"; 242 compatible = "ti,twl4030-audio";
209 codec { 243 ti,enable-vibra = <1>;
244 codec {
245 ti,ramp_delay_value = <3>;
246 };
247 };
248
249 twl_power: power {
250 compatible = "ti,twl4030-power";
251 ti,use_poweroff;
210 }; 252 };
211 }; 253 };
212}; 254};
@@ -222,15 +264,23 @@
222 compatible = "bosch,bmp085"; 264 compatible = "bosch,bmp085";
223 reg = <0x77>; 265 reg = <0x77>;
224 interrupt-parent = <&gpio4>; 266 interrupt-parent = <&gpio4>;
225 interrupts = <17 IRQ_TYPE_EDGE_RISING>; 267 interrupts = <17 IRQ_TYPE_EDGE_RISING>; /* GPIO_113 */
226 }; 268 };
227 269
228 /* accelerometer */ 270 /* accelerometer */
229 bma180@41 { 271 bma180@41 {
230 compatible = "bosch,bma180"; 272 compatible = "bosch,bma180";
231 reg = <0x41>; 273 reg = <0x41>;
232 interrupt-parent = <&gpio3>; 274 interrupt-parent = <&gpio4>;
233 interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; 275 interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; /* GPIO_115 */
276 };
277
278 /* gyroscope */
279 itg3200@68 {
280 compatible = "invensense,itg3200";
281 reg = <0x68>;
282 interrupt-parent = <&gpio2>;
283 interrupts = <24 0>; /* GPIO_56 */
234 }; 284 };
235 285
236 /* leds */ 286 /* leds */
@@ -281,7 +331,7 @@
281 compatible = "ti,tsc2007"; 331 compatible = "ti,tsc2007";
282 reg = <0x48>; 332 reg = <0x48>;
283 interrupt-parent = <&gpio6>; 333 interrupt-parent = <&gpio6>;
284 interrupts = <0 IRQ_TYPE_EDGE_FALLING>; 334 interrupts = <0 IRQ_TYPE_EDGE_FALLING>; /* GPIO_160 */
285 gpios = <&gpio6 0 GPIO_ACTIVE_LOW>; 335 gpios = <&gpio6 0 GPIO_ACTIVE_LOW>;
286 ti,x-plate-ohms = <600>; 336 ti,x-plate-ohms = <600>;
287 }; 337 };
@@ -320,12 +370,17 @@
320 vmmc-supply = <&vaux4>; 370 vmmc-supply = <&vaux4>;
321 bus-width = <4>; 371 bus-width = <4>;
322 ti,non-removable; 372 ti,non-removable;
373 cap-power-off-card;
323}; 374};
324 375
325&mmc3 { 376&mmc3 {
326 status = "disabled"; 377 status = "disabled";
327}; 378};
328 379
380&twl_keypad {
381 status = "disabled";
382};
383
329&uart1 { 384&uart1 {
330 pinctrl-names = "default"; 385 pinctrl-names = "default";
331 pinctrl-0 = <&uart1_pins>; 386 pinctrl-0 = <&uart1_pins>;
@@ -342,8 +397,8 @@
342}; 397};
343 398
344&charger { 399&charger {
345 bb_uvolt = <3200000>; 400 ti,bb-uvolt = <3200000>;
346 bb_uamp = <150>; 401 ti,bb-uamp = <150>;
347}; 402};
348 403
349/* spare */ 404/* spare */
@@ -377,16 +432,12 @@
377 regulator-max-microvolt = <3150000>; 432 regulator-max-microvolt = <3150000>;
378}; 433};
379 434
380/* Needed to power the DPI pins */
381&vpll2 {
382 regulator-always-on;
383};
384
385&dss { 435&dss {
386 pinctrl-names = "default"; 436 pinctrl-names = "default";
387 pinctrl-0 = < &dss_dpi_pins >; 437 pinctrl-0 = < &dss_dpi_pins >;
388 438
389 status = "okay"; 439 status = "okay";
440 vdds_dsi-supply = <&vpll2>;
390 441
391 port { 442 port {
392 dpi_out: endpoint { 443 dpi_out: endpoint {
@@ -396,6 +447,20 @@
396 }; 447 };
397}; 448};
398 449
450&venc {
451 status = "okay";
452
453 vdda-supply = <&vdac>;
454
455 port {
456 venc_out: endpoint {
457 remote-endpoint = <&opa_in>;
458 ti,channels = <2>;
459 ti,invert-polarity;
460 };
461 };
462};
463
399&gpmc { 464&gpmc {
400 ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ 465 ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
401 466
@@ -449,3 +514,7 @@
449 }; 514 };
450 }; 515 };
451}; 516};
517
518&mcbsp2 {
519 status = "okay";
520};
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index b550c41b46f1..60403273f83e 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -307,7 +307,7 @@
307 regulator-name = "V28"; 307 regulator-name = "V28";
308 regulator-min-microvolt = <2800000>; 308 regulator-min-microvolt = <2800000>;
309 regulator-max-microvolt = <2800000>; 309 regulator-max-microvolt = <2800000>;
310 regulator-always-on; /* due battery cover sensor */ 310 regulator-always-on; /* due to battery cover sensor */
311}; 311};
312 312
313&vaux2 { 313&vaux2 {
@@ -365,7 +365,6 @@
365 regulator-name = "VIO"; 365 regulator-name = "VIO";
366 regulator-min-microvolt = <1800000>; 366 regulator-min-microvolt = <1800000>;
367 regulator-max-microvolt = <1800000>; 367 regulator-max-microvolt = <1800000>;
368
369}; 368};
370 369
371&vintana1 { 370&vintana1 {
diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi
index 1e49dfe7e212..c41db94ee9c2 100644
--- a/arch/arm/boot/dts/omap3-n950-n9.dtsi
+++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi
@@ -60,6 +60,11 @@
60 60
61&twl { 61&twl {
62 compatible = "ti,twl5031"; 62 compatible = "ti,twl5031";
63
64 twl_power: power {
65 compatible = "ti,twl4030-power";
66 ti,use_poweroff;
67 };
63}; 68};
64 69
65&twl_gpio { 70&twl_gpio {
diff --git a/arch/arm/boot/dts/omap3-sbc-t3517.dts b/arch/arm/boot/dts/omap3-sbc-t3517.dts
index 17986536c61f..c2d5c28a1a70 100644
--- a/arch/arm/boot/dts/omap3-sbc-t3517.dts
+++ b/arch/arm/boot/dts/omap3-sbc-t3517.dts
@@ -69,3 +69,7 @@
69 }; 69 };
70}; 70};
71 71
72&gpmc {
73 ranges = <4 0 0x2d000000 0x01000000>, /* SB-T35 SMSC9x Eth */
74 <0 0 0x00000000 0x01000000>; /* CM-T3x NAND */
75};
diff --git a/arch/arm/boot/dts/omap3-sbc-t3530.dts b/arch/arm/boot/dts/omap3-sbc-t3530.dts
index c994f0f7e38a..834bc786cd12 100644
--- a/arch/arm/boot/dts/omap3-sbc-t3530.dts
+++ b/arch/arm/boot/dts/omap3-sbc-t3530.dts
@@ -26,14 +26,10 @@
26 }; 26 };
27}; 27};
28 28
29/*
30 * The following ranges correspond to SMSC9x eth chips on CM-T3530 CoM and
31 * SB-T35 baseboard respectively.
32 * This setting includes both chips in SBC-T3530 board device tree.
33 */
34&gpmc { 29&gpmc {
35 ranges = <5 0 0x2c000000 0x01000000>, 30 ranges = <5 0 0x2c000000 0x01000000>, /* CM-T3x30 SMSC9x Eth */
36 <4 0 0x2d000000 0x01000000>; 31 <4 0 0x2d000000 0x01000000>, /* SB-T35 SMSC9x Eth */
32 <0 0 0x00000000 0x01000000>; /* CM-T3x NAND */
37}; 33};
38 34
39&mmc1 { 35&mmc1 {
diff --git a/arch/arm/boot/dts/omap3-sbc-t3730.dts b/arch/arm/boot/dts/omap3-sbc-t3730.dts
index 5bdddf29341d..73c7bf4a4a08 100644
--- a/arch/arm/boot/dts/omap3-sbc-t3730.dts
+++ b/arch/arm/boot/dts/omap3-sbc-t3730.dts
@@ -27,8 +27,9 @@
27}; 27};
28 28
29&gpmc { 29&gpmc {
30 ranges = <5 0 0x2c000000 0x01000000>, 30 ranges = <5 0 0x2c000000 0x01000000>, /* CM-T3x30 SMSC9x Eth */
31 <4 0 0x2d000000 0x01000000>; 31 <4 0 0x2d000000 0x01000000>, /* SB-T35 SMSC9x Eth */
32 <0 0 0x00000000 0x01000000>; /* CM-T3x NAND */
32}; 33};
33 34
34&dss { 35&dss {
diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
index b396c8311b27..e641001ca2a7 100644
--- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
@@ -1,4 +1,5 @@
1#include "qcom-apq8064-v2.0.dtsi" 1#include "qcom-apq8064-v2.0.dtsi"
2#include <dt-bindings/gpio/gpio.h>
2 3
3/ { 4/ {
4 model = "Qualcomm APQ8064/IFC6410"; 5 model = "Qualcomm APQ8064/IFC6410";
@@ -12,6 +13,14 @@
12 function = "gsbi1"; 13 function = "gsbi1";
13 }; 14 };
14 }; 15 };
16
17 card_detect: card_detect {
18 mux {
19 pins = "gpio26";
20 function = "gpio";
21 bias-disable;
22 };
23 };
15 }; 24 };
16 25
17 gsbi@12440000 { 26 gsbi@12440000 {
@@ -49,6 +58,9 @@
49 /* External micro SD card */ 58 /* External micro SD card */
50 sdcc3: sdcc@12180000 { 59 sdcc3: sdcc@12180000 {
51 status = "okay"; 60 status = "okay";
61 pinctrl-names = "default";
62 pinctrl-0 = <&card_detect>;
63 cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>;
52 }; 64 };
53 /* WLAN */ 65 /* WLAN */
54 sdcc4: sdcc@121c0000 { 66 sdcc4: sdcc@121c0000 {
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 63b2146f563b..cb225dafe97c 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -74,7 +74,7 @@
74 #gpio-cells = <2>; 74 #gpio-cells = <2>;
75 interrupt-controller; 75 interrupt-controller;
76 #interrupt-cells = <2>; 76 #interrupt-cells = <2>;
77 interrupts = <0 32 0x4>; 77 interrupts = <0 16 0x4>;
78 }; 78 };
79 79
80 intc: interrupt-controller@2000000 { 80 intc: interrupt-controller@2000000 {
diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts
index 1518c5bcca33..a9da7a89fc4b 100644
--- a/arch/arm/boot/dts/r7s72100-genmai.dts
+++ b/arch/arm/boot/dts/r7s72100-genmai.dts
@@ -45,7 +45,7 @@
45}; 45};
46 46
47&mtu2 { 47&mtu2 {
48 status = "ok"; 48 status = "okay";
49}; 49};
50 50
51&i2c2 { 51&i2c2 {
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
index 84e05f713c54..b3d8f844b57a 100644
--- a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
+++ b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
@@ -67,7 +67,7 @@
67 compatible = "simple-bus"; 67 compatible = "simple-bus";
68 #address-cells = <1>; 68 #address-cells = <1>;
69 #size-cells = <1>; 69 #size-cells = <1>;
70 ranges = <0 0 0 0x80000000>; 70 ranges = <0 0 0 0x20000000>;
71 }; 71 };
72}; 72};
73 73
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
index ce085fa444a1..0d50bef01234 100644
--- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts
+++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
@@ -10,14 +10,20 @@
10 10
11/dts-v1/; 11/dts-v1/;
12#include "r8a73a4.dtsi" 12#include "r8a73a4.dtsi"
13#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/input/input.h>
14 15
15/ { 16/ {
16 model = "APE6EVM"; 17 model = "APE6EVM";
17 compatible = "renesas,ape6evm", "renesas,r8a73a4"; 18 compatible = "renesas,ape6evm", "renesas,r8a73a4";
18 19
20 aliases {
21 serial0 = &scifa0;
22 };
23
19 chosen { 24 chosen {
20 bootargs = "console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw"; 25 bootargs = "console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw";
26 stdout-path = &scifa0;
21 }; 27 };
22 28
23 memory@40000000 { 29 memory@40000000 {
@@ -30,7 +36,35 @@
30 reg = <2 0x00000000 0 0x40000000>; 36 reg = <2 0x00000000 0 0x40000000>;
31 }; 37 };
32 38
33 ape6evm_fixed_3v3: fixedregulator@0 { 39 vcc_mmc0: regulator@0 {
40 compatible = "regulator-fixed";
41 regulator-name = "MMC0 Vcc";
42 regulator-min-microvolt = <2800000>;
43 regulator-max-microvolt = <2800000>;
44 regulator-always-on;
45 };
46
47 vcc_sdhi0: regulator@1 {
48 compatible = "regulator-fixed";
49
50 regulator-name = "SDHI0 Vcc";
51 regulator-min-microvolt = <3300000>;
52 regulator-max-microvolt = <3300000>;
53
54 gpio = <&pfc 76 GPIO_ACTIVE_HIGH>;
55 enable-active-high;
56 };
57
58 /* Common 1.8V and 3.3V rails, used by several devices on APE6EVM */
59 ape6evm_fixed_1v8: regulator@2 {
60 compatible = "regulator-fixed";
61 regulator-name = "1V8";
62 regulator-min-microvolt = <1800000>;
63 regulator-max-microvolt = <1800000>;
64 regulator-always-on;
65 };
66
67 ape6evm_fixed_3v3: regulator@3 {
34 compatible = "regulator-fixed"; 68 compatible = "regulator-fixed";
35 regulator-name = "3V3"; 69 regulator-name = "3V3";
36 regulator-min-microvolt = <3300000>; 70 regulator-min-microvolt = <3300000>;
@@ -39,11 +73,13 @@
39 }; 73 };
40 74
41 lbsc { 75 lbsc {
76 compatible = "simple-bus";
42 #address-cells = <1>; 77 #address-cells = <1>;
43 #size-cells = <1>; 78 #size-cells = <1>;
79 ranges = <0 0 0 0x20000000>;
44 80
45 ethernet@8000000 { 81 ethernet@8000000 {
46 compatible = "smsc,lan9118", "smsc,lan9115"; 82 compatible = "smsc,lan9220", "smsc,lan9115";
47 reg = <0x08000000 0x1000>; 83 reg = <0x08000000 0x1000>;
48 interrupt-parent = <&irqc1>; 84 interrupt-parent = <&irqc1>;
49 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 85 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
@@ -52,7 +88,75 @@
52 smsc,irq-active-high; 88 smsc,irq-active-high;
53 smsc,irq-push-pull; 89 smsc,irq-push-pull;
54 vdd33a-supply = <&ape6evm_fixed_3v3>; 90 vdd33a-supply = <&ape6evm_fixed_3v3>;
55 vddvario-supply = <&ape6evm_fixed_3v3>; 91 vddvario-supply = <&ape6evm_fixed_1v8>;
92 };
93 };
94
95 leds {
96 compatible = "gpio-leds";
97 led1 {
98 gpios = <&pfc 28 GPIO_ACTIVE_LOW>;
99 label = "GNSS_EN";
100 };
101 led2 {
102 gpios = <&pfc 126 GPIO_ACTIVE_LOW>;
103 label = "NFC_NRST";
104 };
105 led3 {
106 gpios = <&pfc 132 GPIO_ACTIVE_LOW>;
107 label = "GNSS_NRST";
108 };
109 led4 {
110 gpios = <&pfc 232 GPIO_ACTIVE_LOW>;
111 label = "BT_WAKEUP";
112 };
113 led5 {
114 gpios = <&pfc 250 GPIO_ACTIVE_LOW>;
115 label = "STROBE";
116 };
117 led6 {
118 gpios = <&pfc 288 GPIO_ACTIVE_LOW>;
119 label = "BBRESETOUT";
120 };
121 };
122
123 keyboard {
124 compatible = "gpio-keys";
125
126 zero-key {
127 gpios = <&pfc 324 GPIO_ACTIVE_LOW>;
128 linux,code = <KEY_0>;
129 label = "S16";
130 };
131
132 menu-key {
133 gpios = <&pfc 325 GPIO_ACTIVE_LOW>;
134 linux,code = <KEY_MENU>;
135 label = "S17";
136 };
137
138 home-key {
139 gpios = <&pfc 326 GPIO_ACTIVE_LOW>;
140 linux,code = <KEY_HOME>;
141 label = "S18";
142 };
143
144 back-key {
145 gpios = <&pfc 327 GPIO_ACTIVE_LOW>;
146 linux,code = <KEY_BACK>;
147 label = "S19";
148 };
149
150 volup-key {
151 gpios = <&pfc 328 GPIO_ACTIVE_LOW>;
152 linux,code = <KEY_VOLUMEUP>;
153 label = "S20";
154 };
155
156 voldown-key {
157 gpios = <&pfc 329 GPIO_ACTIVE_LOW>;
158 linux,code = <KEY_VOLUMEDOWN>;
159 label = "S21";
56 }; 160 };
57 }; 161 };
58}; 162};
@@ -79,3 +183,64 @@
79 >; 183 >;
80 voltage-tolerance = <1>; /* 1% */ 184 voltage-tolerance = <1>; /* 1% */
81}; 185};
186
187&cmt1 {
188 status = "okay";
189};
190
191&pfc {
192 scifa0_pins: serial0 {
193 renesas,groups = "scifa0_data";
194 renesas,function = "scifa0";
195 };
196
197 mmc0_pins: mmc {
198 renesas,groups = "mmc0_data8", "mmc0_ctrl";
199 renesas,function = "mmc0";
200 };
201
202 sdhi0_pins: sd0 {
203 renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
204 renesas,function = "sdhi0";
205 };
206
207 sdhi1_pins: sd1 {
208 renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
209 renesas,function = "sdhi1";
210 };
211};
212
213&mmcif0 {
214 vmmc-supply = <&vcc_mmc0>;
215 bus-width = <8>;
216 non-removable;
217 pinctrl-names = "default";
218 pinctrl-0 = <&mmc0_pins>;
219 status = "okay";
220};
221
222&scifa0 {
223 pinctrl-0 = <&scifa0_pins>;
224 pinctrl-names = "default";
225
226 status = "okay";
227};
228
229&sdhi0 {
230 vmmc-supply = <&vcc_sdhi0>;
231 bus-width = <4>;
232 toshiba,mmc-wrprotect-disable;
233 pinctrl-names = "default";
234 pinctrl-0 = <&sdhi0_pins>;
235 status = "okay";
236};
237
238&sdhi1 {
239 vmmc-supply = <&ape6evm_fixed_3v3>;
240 bus-width = <4>;
241 broken-cd;
242 toshiba,mmc-wrprotect-disable;
243 pinctrl-names = "default";
244 pinctrl-0 = <&sdhi1_pins>;
245 status = "okay";
246};
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 5ac57babc3b9..38136d9f6d95 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -38,6 +38,16 @@
38 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 38 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
39 }; 39 };
40 40
41 dbsc1: memory-controller@e6790000 {
42 compatible = "renesas,dbsc-r8a73a4";
43 reg = <0 0xe6790000 0 0x10000>;
44 };
45
46 dbsc2: memory-controller@e67a0000 {
47 compatible = "renesas,dbsc-r8a73a4";
48 reg = <0 0xe67a0000 0 0x10000>;
49 };
50
41 dmac: dma-multiplexer { 51 dmac: dma-multiplexer {
42 compatible = "renesas,shdma-mux"; 52 compatible = "renesas,shdma-mux";
43 #dma-cells = <1>; 53 #dma-cells = <1>;
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
index d4af4d86c6b0..9bd0cb439f44 100644
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
@@ -172,7 +172,7 @@
172 pinctrl-names = "default"; 172 pinctrl-names = "default";
173 173
174 phy-handle = <&phy0>; 174 phy-handle = <&phy0>;
175 status = "ok"; 175 status = "okay";
176 176
177 phy0: ethernet-phy@0 { 177 phy0: ethernet-phy@0 {
178 reg = <0>; 178 reg = <0>;
@@ -193,7 +193,7 @@
193}; 193};
194 194
195&cmt1 { 195&cmt1 {
196 status = "ok"; 196 status = "okay";
197}; 197};
198 198
199&i2c0 { 199&i2c0 {
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index a8a674bafa67..8a092605d641 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -25,6 +25,7 @@
25 device_type = "cpu"; 25 device_type = "cpu";
26 reg = <0x0>; 26 reg = <0x0>;
27 clock-frequency = <800000000>; 27 clock-frequency = <800000000>;
28 power-domains = <&pd_a3sm>;
28 }; 29 };
29 }; 30 };
30 31
@@ -36,17 +37,29 @@
36 <0xc2000000 0x1000>; 37 <0xc2000000 0x1000>;
37 }; 38 };
38 39
40 dbsc3: memory-controller@fe400000 {
41 compatible = "renesas,dbsc3-r8a7740";
42 reg = <0xfe400000 0x400>;
43 power-domains = <&pd_a4s>;
44 };
45
39 pmu { 46 pmu {
40 compatible = "arm,cortex-a9-pmu"; 47 compatible = "arm,cortex-a9-pmu";
41 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; 48 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
42 }; 49 };
43 50
51 ptm {
52 compatible = "arm,coresight-etm3x";
53 power-domains = <&pd_d4>;
54 };
55
44 cmt1: timer@e6138000 { 56 cmt1: timer@e6138000 {
45 compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48"; 57 compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48";
46 reg = <0xe6138000 0x170>; 58 reg = <0xe6138000 0x170>;
47 interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>; 59 interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
48 clocks = <&mstp3_clks R8A7740_CLK_CMT1>; 60 clocks = <&mstp3_clks R8A7740_CLK_CMT1>;
49 clock-names = "fck"; 61 clock-names = "fck";
62 power-domains = <&pd_c5>;
50 63
51 renesas,channels-mask = <0x3f>; 64 renesas,channels-mask = <0x3f>;
52 65
@@ -72,6 +85,7 @@
72 0 149 IRQ_TYPE_LEVEL_HIGH 85 0 149 IRQ_TYPE_LEVEL_HIGH
73 0 149 IRQ_TYPE_LEVEL_HIGH>; 86 0 149 IRQ_TYPE_LEVEL_HIGH>;
74 clocks = <&mstp2_clks R8A7740_CLK_INTCA>; 87 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
88 power-domains = <&pd_a4s>;
75 }; 89 };
76 90
77 /* irqpin1: IRQ8 - IRQ15 */ 91 /* irqpin1: IRQ8 - IRQ15 */
@@ -93,6 +107,7 @@
93 0 149 IRQ_TYPE_LEVEL_HIGH 107 0 149 IRQ_TYPE_LEVEL_HIGH
94 0 149 IRQ_TYPE_LEVEL_HIGH>; 108 0 149 IRQ_TYPE_LEVEL_HIGH>;
95 clocks = <&mstp2_clks R8A7740_CLK_INTCA>; 109 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
110 power-domains = <&pd_a4s>;
96 }; 111 };
97 112
98 /* irqpin2: IRQ16 - IRQ23 */ 113 /* irqpin2: IRQ16 - IRQ23 */
@@ -114,6 +129,7 @@
114 0 149 IRQ_TYPE_LEVEL_HIGH 129 0 149 IRQ_TYPE_LEVEL_HIGH
115 0 149 IRQ_TYPE_LEVEL_HIGH>; 130 0 149 IRQ_TYPE_LEVEL_HIGH>;
116 clocks = <&mstp2_clks R8A7740_CLK_INTCA>; 131 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
132 power-domains = <&pd_a4s>;
117 }; 133 };
118 134
119 /* irqpin3: IRQ24 - IRQ31 */ 135 /* irqpin3: IRQ24 - IRQ31 */
@@ -135,6 +151,7 @@
135 0 149 IRQ_TYPE_LEVEL_HIGH 151 0 149 IRQ_TYPE_LEVEL_HIGH
136 0 149 IRQ_TYPE_LEVEL_HIGH>; 152 0 149 IRQ_TYPE_LEVEL_HIGH>;
137 clocks = <&mstp2_clks R8A7740_CLK_INTCA>; 153 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
154 power-domains = <&pd_a4s>;
138 }; 155 };
139 156
140 ether: ethernet@e9a00000 { 157 ether: ethernet@e9a00000 {
@@ -143,6 +160,7 @@
143 <0xe9a01800 0x800>; 160 <0xe9a01800 0x800>;
144 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; 161 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
145 clocks = <&mstp3_clks R8A7740_CLK_GETHER>; 162 clocks = <&mstp3_clks R8A7740_CLK_GETHER>;
163 power-domains = <&pd_a4s>;
146 phy-mode = "mii"; 164 phy-mode = "mii";
147 #address-cells = <1>; 165 #address-cells = <1>;
148 #size-cells = <0>; 166 #size-cells = <0>;
@@ -159,6 +177,7 @@
159 0 203 IRQ_TYPE_LEVEL_HIGH 177 0 203 IRQ_TYPE_LEVEL_HIGH
160 0 204 IRQ_TYPE_LEVEL_HIGH>; 178 0 204 IRQ_TYPE_LEVEL_HIGH>;
161 clocks = <&mstp1_clks R8A7740_CLK_IIC0>; 179 clocks = <&mstp1_clks R8A7740_CLK_IIC0>;
180 power-domains = <&pd_a4r>;
162 status = "disabled"; 181 status = "disabled";
163 }; 182 };
164 183
@@ -172,6 +191,7 @@
172 0 72 IRQ_TYPE_LEVEL_HIGH 191 0 72 IRQ_TYPE_LEVEL_HIGH
173 0 73 IRQ_TYPE_LEVEL_HIGH>; 192 0 73 IRQ_TYPE_LEVEL_HIGH>;
174 clocks = <&mstp3_clks R8A7740_CLK_IIC1>; 193 clocks = <&mstp3_clks R8A7740_CLK_IIC1>;
194 power-domains = <&pd_a3sp>;
175 status = "disabled"; 195 status = "disabled";
176 }; 196 };
177 197
@@ -181,6 +201,7 @@
181 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; 201 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
182 clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>; 202 clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
183 clock-names = "sci_ick"; 203 clock-names = "sci_ick";
204 power-domains = <&pd_a3sp>;
184 status = "disabled"; 205 status = "disabled";
185 }; 206 };
186 207
@@ -190,6 +211,7 @@
190 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>; 211 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
191 clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>; 212 clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>;
192 clock-names = "sci_ick"; 213 clock-names = "sci_ick";
214 power-domains = <&pd_a3sp>;
193 status = "disabled"; 215 status = "disabled";
194 }; 216 };
195 217
@@ -199,6 +221,7 @@
199 interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>; 221 interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>; 222 clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>;
201 clock-names = "sci_ick"; 223 clock-names = "sci_ick";
224 power-domains = <&pd_a3sp>;
202 status = "disabled"; 225 status = "disabled";
203 }; 226 };
204 227
@@ -208,6 +231,7 @@
208 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; 231 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>; 232 clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>;
210 clock-names = "sci_ick"; 233 clock-names = "sci_ick";
234 power-domains = <&pd_a3sp>;
211 status = "disabled"; 235 status = "disabled";
212 }; 236 };
213 237
@@ -217,6 +241,7 @@
217 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; 241 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>; 242 clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>;
219 clock-names = "sci_ick"; 243 clock-names = "sci_ick";
244 power-domains = <&pd_a3sp>;
220 status = "disabled"; 245 status = "disabled";
221 }; 246 };
222 247
@@ -226,6 +251,7 @@
226 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; 251 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>; 252 clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>;
228 clock-names = "sci_ick"; 253 clock-names = "sci_ick";
254 power-domains = <&pd_a3sp>;
229 status = "disabled"; 255 status = "disabled";
230 }; 256 };
231 257
@@ -235,6 +261,7 @@
235 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; 261 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
236 clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>; 262 clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>;
237 clock-names = "sci_ick"; 263 clock-names = "sci_ick";
264 power-domains = <&pd_a3sp>;
238 status = "disabled"; 265 status = "disabled";
239 }; 266 };
240 267
@@ -244,6 +271,7 @@
244 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; 271 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>; 272 clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>;
246 clock-names = "sci_ick"; 273 clock-names = "sci_ick";
274 power-domains = <&pd_a3sp>;
247 status = "disabled"; 275 status = "disabled";
248 }; 276 };
249 277
@@ -253,6 +281,7 @@
253 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; 281 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&mstp2_clks R8A7740_CLK_SCIFB>; 282 clocks = <&mstp2_clks R8A7740_CLK_SCIFB>;
255 clock-names = "sci_ick"; 283 clock-names = "sci_ick";
284 power-domains = <&pd_a3sp>;
256 status = "disabled"; 285 status = "disabled";
257 }; 286 };
258 287
@@ -271,12 +300,14 @@
271 <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, 300 <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
272 <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, 301 <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
273 <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; 302 <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
303 power-domains = <&pd_c5>;
274 }; 304 };
275 305
276 tpu: pwm@e6600000 { 306 tpu: pwm@e6600000 {
277 compatible = "renesas,tpu-r8a7740", "renesas,tpu"; 307 compatible = "renesas,tpu-r8a7740", "renesas,tpu";
278 reg = <0xe6600000 0x100>; 308 reg = <0xe6600000 0x100>;
279 clocks = <&mstp3_clks R8A7740_CLK_TPU0>; 309 clocks = <&mstp3_clks R8A7740_CLK_TPU0>;
310 power-domains = <&pd_a3sp>;
280 status = "disabled"; 311 status = "disabled";
281 #pwm-cells = <3>; 312 #pwm-cells = <3>;
282 }; 313 };
@@ -287,6 +318,7 @@
287 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH 318 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH
288 0 57 IRQ_TYPE_LEVEL_HIGH>; 319 0 57 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&mstp3_clks R8A7740_CLK_MMC>; 320 clocks = <&mstp3_clks R8A7740_CLK_MMC>;
321 power-domains = <&pd_a3sp>;
290 status = "disabled"; 322 status = "disabled";
291 }; 323 };
292 324
@@ -297,6 +329,7 @@
297 0 118 IRQ_TYPE_LEVEL_HIGH 329 0 118 IRQ_TYPE_LEVEL_HIGH
298 0 119 IRQ_TYPE_LEVEL_HIGH>; 330 0 119 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&mstp3_clks R8A7740_CLK_SDHI0>; 331 clocks = <&mstp3_clks R8A7740_CLK_SDHI0>;
332 power-domains = <&pd_a3sp>;
300 cap-sd-highspeed; 333 cap-sd-highspeed;
301 cap-sdio-irq; 334 cap-sdio-irq;
302 status = "disabled"; 335 status = "disabled";
@@ -309,6 +342,7 @@
309 0 122 IRQ_TYPE_LEVEL_HIGH 342 0 122 IRQ_TYPE_LEVEL_HIGH
310 0 123 IRQ_TYPE_LEVEL_HIGH>; 343 0 123 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&mstp3_clks R8A7740_CLK_SDHI1>; 344 clocks = <&mstp3_clks R8A7740_CLK_SDHI1>;
345 power-domains = <&pd_a3sp>;
312 cap-sd-highspeed; 346 cap-sd-highspeed;
313 cap-sdio-irq; 347 cap-sdio-irq;
314 status = "disabled"; 348 status = "disabled";
@@ -321,6 +355,7 @@
321 0 126 IRQ_TYPE_LEVEL_HIGH 355 0 126 IRQ_TYPE_LEVEL_HIGH
322 0 127 IRQ_TYPE_LEVEL_HIGH>; 356 0 127 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&mstp4_clks R8A7740_CLK_SDHI2>; 357 clocks = <&mstp4_clks R8A7740_CLK_SDHI2>;
358 power-domains = <&pd_a3sp>;
324 cap-sd-highspeed; 359 cap-sd-highspeed;
325 cap-sdio-irq; 360 cap-sdio-irq;
326 status = "disabled"; 361 status = "disabled";
@@ -332,6 +367,7 @@
332 reg = <0xfe1f0000 0x400>; 367 reg = <0xfe1f0000 0x400>;
333 interrupts = <0 9 0x4>; 368 interrupts = <0 9 0x4>;
334 clocks = <&mstp3_clks R8A7740_CLK_FSI>; 369 clocks = <&mstp3_clks R8A7740_CLK_FSI>;
370 power-domains = <&pd_a4mp>;
335 status = "disabled"; 371 status = "disabled";
336 }; 372 };
337 373
@@ -343,6 +379,7 @@
343 <0 200 IRQ_TYPE_LEVEL_HIGH>; 379 <0 200 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&mstp1_clks R8A7740_CLK_TMU0>; 380 clocks = <&mstp1_clks R8A7740_CLK_TMU0>;
345 clock-names = "fck"; 381 clock-names = "fck";
382 power-domains = <&pd_a4r>;
346 383
347 #renesas,channels = <3>; 384 #renesas,channels = <3>;
348 385
@@ -357,6 +394,7 @@
357 <0 172 IRQ_TYPE_LEVEL_HIGH>; 394 <0 172 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&mstp1_clks R8A7740_CLK_TMU1>; 395 clocks = <&mstp1_clks R8A7740_CLK_TMU1>;
359 clock-names = "fck"; 396 clock-names = "fck";
397 power-domains = <&pd_a4r>;
360 398
361 #renesas,channels = <3>; 399 #renesas,channels = <3>;
362 400
@@ -453,7 +491,7 @@
453 reg = <0xe6150080 4>; 491 reg = <0xe6150080 4>;
454 clocks = <&sub_clk>, <&sub_clk>; 492 clocks = <&sub_clk>, <&sub_clk>;
455 #clock-cells = <1>; 493 #clock-cells = <1>;
456 renesas,clock-indices = < 494 clock-indices = <
457 R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2 495 R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2
458 >; 496 >;
459 clock-output-names = 497 clock-output-names =
@@ -468,7 +506,7 @@
468 <&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>, 506 <&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>,
469 <&cpg_clocks R8A7740_CLK_B>; 507 <&cpg_clocks R8A7740_CLK_B>;
470 #clock-cells = <1>; 508 #clock-cells = <1>;
471 renesas,clock-indices = < 509 clock-indices = <
472 R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0 510 R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0
473 R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1 511 R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1
474 R8A7740_CLK_LCDC0 512 R8A7740_CLK_LCDC0
@@ -489,7 +527,7 @@
489 <&sub_clk>, <&sub_clk>, <&sub_clk>, 527 <&sub_clk>, <&sub_clk>, <&sub_clk>,
490 <&sub_clk>; 528 <&sub_clk>;
491 #clock-cells = <1>; 529 #clock-cells = <1>;
492 renesas,clock-indices = < 530 clock-indices = <
493 R8A7740_CLK_SCIFA6 R8A7740_CLK_INTCA 531 R8A7740_CLK_SCIFA6 R8A7740_CLK_INTCA
494 R8A7740_CLK_SCIFA7 532 R8A7740_CLK_SCIFA7
495 R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2 533 R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2
@@ -518,7 +556,7 @@
518 <&cpg_clocks R8A7740_CLK_HP>, 556 <&cpg_clocks R8A7740_CLK_HP>,
519 <&cpg_clocks R8A7740_CLK_HP>; 557 <&cpg_clocks R8A7740_CLK_HP>;
520 #clock-cells = <1>; 558 #clock-cells = <1>;
521 renesas,clock-indices = < 559 clock-indices = <
522 R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1 560 R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1
523 R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1 561 R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1
524 R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0 562 R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0
@@ -535,7 +573,7 @@
535 <&cpg_clocks R8A7740_CLK_HP>, 573 <&cpg_clocks R8A7740_CLK_HP>,
536 <&cpg_clocks R8A7740_CLK_HP>; 574 <&cpg_clocks R8A7740_CLK_HP>;
537 #clock-cells = <1>; 575 #clock-cells = <1>;
538 renesas,clock-indices = < 576 clock-indices = <
539 R8A7740_CLK_USBH R8A7740_CLK_SDHI2 577 R8A7740_CLK_USBH R8A7740_CLK_SDHI2
540 R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY 578 R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY
541 >; 579 >;
@@ -543,4 +581,71 @@
543 "usbhost", "sdhi2", "usbfunc", "usphy"; 581 "usbhost", "sdhi2", "usbfunc", "usphy";
544 }; 582 };
545 }; 583 };
584
585 sysc: system-controller@e6180000 {
586 compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile";
587 reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
588
589 pm-domains {
590 pd_c5: c5 {
591 #address-cells = <1>;
592 #size-cells = <0>;
593 #power-domain-cells = <0>;
594
595 pd_a4lc: a4lc@1 {
596 reg = <1>;
597 #power-domain-cells = <0>;
598 };
599
600 pd_a4mp: a4mp@2 {
601 reg = <2>;
602 #power-domain-cells = <0>;
603 };
604
605 pd_d4: d4@3 {
606 reg = <3>;
607 #power-domain-cells = <0>;
608 };
609
610 pd_a4r: a4r@5 {
611 reg = <5>;
612 #address-cells = <1>;
613 #size-cells = <0>;
614 #power-domain-cells = <0>;
615
616 pd_a3rv: a3rv@6 {
617 reg = <6>;
618 #power-domain-cells = <0>;
619 };
620 };
621
622 pd_a4s: a4s@10 {
623 reg = <10>;
624 #address-cells = <1>;
625 #size-cells = <0>;
626 #power-domain-cells = <0>;
627
628 pd_a3sp: a3sp@11 {
629 reg = <11>;
630 #power-domain-cells = <0>;
631 };
632
633 pd_a3sm: a3sm@12 {
634 reg = <12>;
635 #power-domain-cells = <0>;
636 };
637
638 pd_a3sg: a3sg@13 {
639 reg = <13>;
640 #power-domain-cells = <0>;
641 };
642 };
643
644 pd_a4su: a4su@20 {
645 reg = <20>;
646 #power-domain-cells = <0>;
647 };
648 };
649 };
650 };
546}; 651};
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index ede9a29e4bc6..5c2219b9f3eb 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -12,6 +12,7 @@
12/include/ "skeleton.dtsi" 12/include/ "skeleton.dtsi"
13 13
14#include <dt-bindings/clock/r8a7779-clock.h> 14#include <dt-bindings/clock/r8a7779-clock.h>
15#include <dt-bindings/interrupt-controller/arm-gic.h>
15#include <dt-bindings/interrupt-controller/irq.h> 16#include <dt-bindings/interrupt-controller/irq.h>
16 17
17/ { 18/ {
@@ -62,6 +63,14 @@
62 <0xf0000100 0x100>; 63 <0xf0000100 0x100>;
63 }; 64 };
64 65
66 timer@f0000600 {
67 compatible = "arm,cortex-a9-twd-timer";
68 reg = <0xf0000600 0x20>;
69 interrupts = <GIC_PPI 13
70 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
71 clocks = <&cpg_clocks R8A7779_CLK_ZS>;
72 };
73
65 gpio0: gpio@ffc40000 { 74 gpio0: gpio@ffc40000 {
66 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 75 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
67 reg = <0xffc40000 0x2c>; 76 reg = <0xffc40000 0x2c>;
@@ -200,7 +209,7 @@
200 compatible = "renesas,scif-r8a7779", "renesas,scif"; 209 compatible = "renesas,scif-r8a7779", "renesas,scif";
201 reg = <0xffe40000 0x100>; 210 reg = <0xffe40000 0x100>;
202 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; 211 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
203 clocks = <&cpg_clocks R8A7779_CLK_P>; 212 clocks = <&mstp0_clks R8A7779_CLK_SCIF0>;
204 clock-names = "sci_ick"; 213 clock-names = "sci_ick";
205 status = "disabled"; 214 status = "disabled";
206 }; 215 };
@@ -209,7 +218,7 @@
209 compatible = "renesas,scif-r8a7779", "renesas,scif"; 218 compatible = "renesas,scif-r8a7779", "renesas,scif";
210 reg = <0xffe41000 0x100>; 219 reg = <0xffe41000 0x100>;
211 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; 220 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
212 clocks = <&cpg_clocks R8A7779_CLK_P>; 221 clocks = <&mstp0_clks R8A7779_CLK_SCIF1>;
213 clock-names = "sci_ick"; 222 clock-names = "sci_ick";
214 status = "disabled"; 223 status = "disabled";
215 }; 224 };
@@ -218,7 +227,7 @@
218 compatible = "renesas,scif-r8a7779", "renesas,scif"; 227 compatible = "renesas,scif-r8a7779", "renesas,scif";
219 reg = <0xffe42000 0x100>; 228 reg = <0xffe42000 0x100>;
220 interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>; 229 interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>;
221 clocks = <&cpg_clocks R8A7779_CLK_P>; 230 clocks = <&mstp0_clks R8A7779_CLK_SCIF2>;
222 clock-names = "sci_ick"; 231 clock-names = "sci_ick";
223 status = "disabled"; 232 status = "disabled";
224 }; 233 };
@@ -227,7 +236,7 @@
227 compatible = "renesas,scif-r8a7779", "renesas,scif"; 236 compatible = "renesas,scif-r8a7779", "renesas,scif";
228 reg = <0xffe43000 0x100>; 237 reg = <0xffe43000 0x100>;
229 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>; 238 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&cpg_clocks R8A7779_CLK_P>; 239 clocks = <&mstp0_clks R8A7779_CLK_SCIF3>;
231 clock-names = "sci_ick"; 240 clock-names = "sci_ick";
232 status = "disabled"; 241 status = "disabled";
233 }; 242 };
@@ -236,7 +245,7 @@
236 compatible = "renesas,scif-r8a7779", "renesas,scif"; 245 compatible = "renesas,scif-r8a7779", "renesas,scif";
237 reg = <0xffe44000 0x100>; 246 reg = <0xffe44000 0x100>;
238 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; 247 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
239 clocks = <&cpg_clocks R8A7779_CLK_P>; 248 clocks = <&mstp0_clks R8A7779_CLK_SCIF4>;
240 clock-names = "sci_ick"; 249 clock-names = "sci_ick";
241 status = "disabled"; 250 status = "disabled";
242 }; 251 };
@@ -245,7 +254,7 @@
245 compatible = "renesas,scif-r8a7779", "renesas,scif"; 254 compatible = "renesas,scif-r8a7779", "renesas,scif";
246 reg = <0xffe45000 0x100>; 255 reg = <0xffe45000 0x100>;
247 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>; 256 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
248 clocks = <&cpg_clocks R8A7779_CLK_P>; 257 clocks = <&mstp0_clks R8A7779_CLK_SCIF5>;
249 clock-names = "sci_ick"; 258 clock-names = "sci_ick";
250 status = "disabled"; 259 status = "disabled";
251 }; 260 };
@@ -464,18 +473,18 @@
464 <&cpg_clocks R8A7779_CLK_P>, 473 <&cpg_clocks R8A7779_CLK_P>,
465 <&cpg_clocks R8A7779_CLK_S>, 474 <&cpg_clocks R8A7779_CLK_S>,
466 <&cpg_clocks R8A7779_CLK_S>, 475 <&cpg_clocks R8A7779_CLK_S>,
467 <&cpg_clocks R8A7779_CLK_S1>, 476 <&cpg_clocks R8A7779_CLK_P>,
468 <&cpg_clocks R8A7779_CLK_S1>, 477 <&cpg_clocks R8A7779_CLK_P>,
469 <&cpg_clocks R8A7779_CLK_S1>, 478 <&cpg_clocks R8A7779_CLK_P>,
470 <&cpg_clocks R8A7779_CLK_S1>, 479 <&cpg_clocks R8A7779_CLK_P>,
471 <&cpg_clocks R8A7779_CLK_S1>, 480 <&cpg_clocks R8A7779_CLK_P>,
472 <&cpg_clocks R8A7779_CLK_S1>, 481 <&cpg_clocks R8A7779_CLK_P>,
473 <&cpg_clocks R8A7779_CLK_P>, 482 <&cpg_clocks R8A7779_CLK_P>,
474 <&cpg_clocks R8A7779_CLK_P>, 483 <&cpg_clocks R8A7779_CLK_P>,
475 <&cpg_clocks R8A7779_CLK_P>, 484 <&cpg_clocks R8A7779_CLK_P>,
476 <&cpg_clocks R8A7779_CLK_P>; 485 <&cpg_clocks R8A7779_CLK_P>;
477 #clock-cells = <1>; 486 #clock-cells = <1>;
478 renesas,clock-indices = < 487 clock-indices = <
479 R8A7779_CLK_HSPI R8A7779_CLK_TMU2 488 R8A7779_CLK_HSPI R8A7779_CLK_TMU2
480 R8A7779_CLK_TMU1 R8A7779_CLK_TMU0 489 R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
481 R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0 490 R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
@@ -506,7 +515,7 @@
506 <&cpg_clocks R8A7779_CLK_P>, 515 <&cpg_clocks R8A7779_CLK_P>,
507 <&cpg_clocks R8A7779_CLK_S>; 516 <&cpg_clocks R8A7779_CLK_S>;
508 #clock-cells = <1>; 517 #clock-cells = <1>;
509 renesas,clock-indices = < 518 clock-indices = <
510 R8A7779_CLK_USB01 R8A7779_CLK_USB2 519 R8A7779_CLK_USB01 R8A7779_CLK_USB2
511 R8A7779_CLK_DU R8A7779_CLK_VIN2 520 R8A7779_CLK_DU R8A7779_CLK_VIN2
512 R8A7779_CLK_VIN1 R8A7779_CLK_VIN0 521 R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
@@ -527,7 +536,7 @@
527 clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>, 536 clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
528 <&s4_clk>, <&s4_clk>; 537 <&s4_clk>, <&s4_clk>;
529 #clock-cells = <1>; 538 #clock-cells = <1>;
530 renesas,clock-indices = < 539 clock-indices = <
531 R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2 540 R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
532 R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0 541 R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
533 R8A7779_CLK_MMC1 R8A7779_CLK_MMC0 542 R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 4118030f366d..0c3b6783b72a 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -355,7 +355,7 @@
355 355
356 phy-handle = <&phy1>; 356 phy-handle = <&phy1>;
357 renesas,ether-link-active-low; 357 renesas,ether-link-active-low;
358 status = "ok"; 358 status = "okay";
359 359
360 phy1: ethernet-phy@1 { 360 phy1: ethernet-phy@1 {
361 reg = <1>; 361 reg = <1>;
@@ -366,7 +366,7 @@
366}; 366};
367 367
368&cmt0 { 368&cmt0 {
369 status = "ok"; 369 status = "okay";
370}; 370};
371 371
372&mmcif1 { 372&mmcif1 {
@@ -397,6 +397,8 @@
397 spi-max-frequency = <30000000>; 397 spi-max-frequency = <30000000>;
398 spi-tx-bus-width = <4>; 398 spi-tx-bus-width = <4>;
399 spi-rx-bus-width = <4>; 399 spi-rx-bus-width = <4>;
400 spi-cpha;
401 spi-cpol;
400 m25p,fast-read; 402 m25p,fast-read;
401 403
402 partition@0 { 404 partition@0 {
@@ -470,17 +472,17 @@
470}; 472};
471 473
472&iic0 { 474&iic0 {
473 status = "ok"; 475 status = "okay";
474}; 476};
475 477
476&iic1 { 478&iic1 {
477 status = "ok"; 479 status = "okay";
478 pinctrl-0 = <&iic1_pins>; 480 pinctrl-0 = <&iic1_pins>;
479 pinctrl-names = "default"; 481 pinctrl-names = "default";
480}; 482};
481 483
482&iic2 { 484&iic2 {
483 status = "ok"; 485 status = "okay";
484 pinctrl-0 = <&iic2_pins>; 486 pinctrl-0 = <&iic2_pins>;
485 pinctrl-names = "default"; 487 pinctrl-names = "default";
486 488
@@ -562,7 +564,7 @@
562 pinctrl-0 = <&vin1_pins>; 564 pinctrl-0 = <&vin1_pins>;
563 pinctrl-names = "default"; 565 pinctrl-names = "default";
564 566
565 status = "ok"; 567 status = "okay";
566 568
567 port { 569 port {
568 #address-cells = <1>; 570 #address-cells = <1>;
@@ -579,6 +581,7 @@
579 pinctrl-0 = <&sound_pins &sound_clk_pins>; 581 pinctrl-0 = <&sound_pins &sound_clk_pins>;
580 pinctrl-names = "default"; 582 pinctrl-names = "default";
581 583
584 /* Single DAI */
582 #sound-dai-cells = <0>; 585 #sound-dai-cells = <0>;
583 586
584 status = "okay"; 587 status = "okay";
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index af7e255f629e..4b38fc920114 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -1054,7 +1054,7 @@
1054 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; 1054 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1055 clocks = <&mp_clk>; 1055 clocks = <&mp_clk>;
1056 #clock-cells = <1>; 1056 #clock-cells = <1>;
1057 renesas,clock-indices = <R8A7790_CLK_MSIOF0>; 1057 clock-indices = <R8A7790_CLK_MSIOF0>;
1058 clock-output-names = "msiof0"; 1058 clock-output-names = "msiof0";
1059 }; 1059 };
1060 mstp1_clks: mstp1_clks@e6150134 { 1060 mstp1_clks: mstp1_clks@e6150134 {
@@ -1065,7 +1065,7 @@
1065 <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, 1065 <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
1066 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; 1066 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
1067 #clock-cells = <1>; 1067 #clock-cells = <1>;
1068 renesas,clock-indices = < 1068 clock-indices = <
1069 R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1 1069 R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1
1070 R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1 1070 R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1
1071 R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC 1071 R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC
@@ -1087,7 +1087,7 @@
1087 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>, 1087 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>,
1088 <&zs_clk>; 1088 <&zs_clk>;
1089 #clock-cells = <1>; 1089 #clock-cells = <1>;
1090 renesas,clock-indices = < 1090 clock-indices = <
1091 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0 1091 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
1092 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1 1092 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
1093 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2 1093 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
@@ -1106,7 +1106,7 @@
1106 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>, 1106 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1107 <&hp_clk>, <&hp_clk>; 1107 <&hp_clk>, <&hp_clk>;
1108 #clock-cells = <1>; 1108 #clock-cells = <1>;
1109 renesas,clock-indices = < 1109 clock-indices = <
1110 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 1110 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
1111 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0 1111 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
1112 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1 1112 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
@@ -1123,8 +1123,10 @@
1123 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; 1123 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1124 clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>; 1124 clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>;
1125 #clock-cells = <1>; 1125 #clock-cells = <1>;
1126 renesas,clock-indices = <R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1 1126 clock-indices = <
1127 R8A7790_CLK_THERMAL R8A7790_CLK_PWM>; 1127 R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1
1128 R8A7790_CLK_THERMAL R8A7790_CLK_PWM
1129 >;
1128 clock-output-names = "audmac0", "audmac1", "thermal", "pwm"; 1130 clock-output-names = "audmac0", "audmac1", "thermal", "pwm";
1129 }; 1131 };
1130 mstp7_clks: mstp7_clks@e615014c { 1132 mstp7_clks: mstp7_clks@e615014c {
@@ -1134,7 +1136,7 @@
1134 <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, 1136 <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
1135 <&zx_clk>; 1137 <&zx_clk>;
1136 #clock-cells = <1>; 1138 #clock-cells = <1>;
1137 renesas,clock-indices = < 1139 clock-indices = <
1138 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1 1140 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
1139 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0 1141 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
1140 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0 1142 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
@@ -1147,16 +1149,17 @@
1147 mstp8_clks: mstp8_clks@e6150990 { 1149 mstp8_clks: mstp8_clks@e6150990 {
1148 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; 1150 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1149 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; 1151 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1150 clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, 1152 clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
1151 <&zs_clk>, <&zs_clk>; 1153 <&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>;
1152 #clock-cells = <1>; 1154 #clock-cells = <1>;
1153 renesas,clock-indices = < 1155 clock-indices = <
1154 R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 R8A7790_CLK_VIN1 1156 R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2
1155 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER R8A7790_CLK_SATA1 1157 R8A7790_CLK_VIN1 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER
1156 R8A7790_CLK_SATA0 1158 R8A7790_CLK_SATA1 R8A7790_CLK_SATA0
1157 >; 1159 >;
1158 clock-output-names = 1160 clock-output-names =
1159 "vin3", "vin2", "vin1", "vin0", "ether", "sata1", "sata0"; 1161 "mlb", "vin3", "vin2", "vin1", "vin0", "ether",
1162 "sata1", "sata0";
1160 }; 1163 };
1161 mstp9_clks: mstp9_clks@e6150994 { 1164 mstp9_clks: mstp9_clks@e6150994 {
1162 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; 1165 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -1166,7 +1169,7 @@
1166 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>, 1169 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>,
1167 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; 1170 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
1168 #clock-cells = <1>; 1171 #clock-cells = <1>;
1169 renesas,clock-indices = < 1172 clock-indices = <
1170 R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3 1173 R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3
1171 R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0 1174 R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0
1172 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS 1175 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS
@@ -1397,8 +1400,13 @@
1397 }; 1400 };
1398 1401
1399 rcar_sound: rcar_sound@ec500000 { 1402 rcar_sound: rcar_sound@ec500000 {
1400 #sound-dai-cells = <1>; 1403 /*
1401 compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2", "renesas,rcar_sound"; 1404 * #sound-dai-cells is required
1405 *
1406 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1407 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1408 */
1409 compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2";
1402 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1410 reg = <0 0xec500000 0 0x1000>, /* SCU */
1403 <0 0xec5a0000 0 0x100>, /* ADG */ 1411 <0 0xec5a0000 0 0x100>, /* ADG */
1404 <0 0xec540000 0 0x1000>, /* SSIU */ 1412 <0 0xec540000 0 0x1000>, /* SSIU */
@@ -1432,16 +1440,16 @@
1432 }; 1440 };
1433 1441
1434 rcar_sound,src { 1442 rcar_sound,src {
1435 src0: src@0 { }; 1443 src0: src@0 { interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; };
1436 src1: src@1 { }; 1444 src1: src@1 { interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>; };
1437 src2: src@2 { }; 1445 src2: src@2 { interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>; };
1438 src3: src@3 { }; 1446 src3: src@3 { interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>; };
1439 src4: src@4 { }; 1447 src4: src@4 { interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>; };
1440 src5: src@5 { }; 1448 src5: src@5 { interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>; };
1441 src6: src@6 { }; 1449 src6: src@6 { interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>; };
1442 src7: src@7 { }; 1450 src7: src@7 { interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>; };
1443 src8: src@8 { }; 1451 src8: src@8 { interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>; };
1444 src9: src@9 { }; 1452 src9: src@9 { interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>; };
1445 }; 1453 };
1446 1454
1447 rcar_sound,ssi { 1455 rcar_sound,ssi {
diff --git a/arch/arm/boot/dts/r8a7791-henninger.dts b/arch/arm/boot/dts/r8a7791-henninger.dts
index 740e38678032..d2ebf11f9881 100644
--- a/arch/arm/boot/dts/r8a7791-henninger.dts
+++ b/arch/arm/boot/dts/r8a7791-henninger.dts
@@ -156,7 +156,7 @@
156 156
157 phy-handle = <&phy1>; 157 phy-handle = <&phy1>;
158 renesas,ether-link-active-low; 158 renesas,ether-link-active-low;
159 status = "ok"; 159 status = "okay";
160 160
161 phy1: ethernet-phy@1 { 161 phy1: ethernet-phy@1 {
162 reg = <1>; 162 reg = <1>;
@@ -293,7 +293,7 @@
293 293
294/* composite video input */ 294/* composite video input */
295&vin0 { 295&vin0 {
296 status = "ok"; 296 status = "okay";
297 pinctrl-0 = <&vin0_pins>; 297 pinctrl-0 = <&vin0_pins>;
298 pinctrl-names = "default"; 298 pinctrl-names = "default";
299 299
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index bf58c79a6554..a3c27807f6c5 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -366,7 +366,7 @@
366 366
367 phy-handle = <&phy1>; 367 phy-handle = <&phy1>;
368 renesas,ether-link-active-low; 368 renesas,ether-link-active-low;
369 status = "ok"; 369 status = "okay";
370 370
371 phy1: ethernet-phy@1 { 371 phy1: ethernet-phy@1 {
372 reg = <1>; 372 reg = <1>;
@@ -377,7 +377,7 @@
377}; 377};
378 378
379&cmt0 { 379&cmt0 {
380 status = "ok"; 380 status = "okay";
381}; 381};
382 382
383&sata0 { 383&sata0 {
@@ -444,6 +444,8 @@
444 spi-max-frequency = <30000000>; 444 spi-max-frequency = <30000000>;
445 spi-tx-bus-width = <4>; 445 spi-tx-bus-width = <4>;
446 spi-rx-bus-width = <4>; 446 spi-rx-bus-width = <4>;
447 spi-cpha;
448 spi-cpol;
447 m25p,fast-read; 449 m25p,fast-read;
448 450
449 partition@0 { 451 partition@0 {
@@ -452,13 +454,13 @@
452 read-only; 454 read-only;
453 }; 455 };
454 partition@80000 { 456 partition@80000 {
455 label = "bootenv"; 457 label = "user";
456 reg = <0x00080000 0x00080000>; 458 reg = <0x00080000 0x00580000>;
457 read-only; 459 read-only;
458 }; 460 };
459 partition@100000 { 461 partition@600000 {
460 label = "data"; 462 label = "flash";
461 reg = <0x00100000 0x03f00000>; 463 reg = <0x00600000 0x03a00000>;
462 }; 464 };
463 }; 465 };
464}; 466};
@@ -563,7 +565,7 @@
563 565
564/* composite video input */ 566/* composite video input */
565&vin1 { 567&vin1 {
566 status = "ok"; 568 status = "okay";
567 pinctrl-0 = <&vin1_pins>; 569 pinctrl-0 = <&vin1_pins>;
568 pinctrl-names = "default"; 570 pinctrl-names = "default";
569 571
@@ -582,6 +584,7 @@
582 pinctrl-0 = <&sound_pins &sound_clk_pins>; 584 pinctrl-0 = <&sound_pins &sound_clk_pins>;
583 pinctrl-names = "default"; 585 pinctrl-names = "default";
584 586
587 /* Single DAI */
585 #sound-dai-cells = <0>; 588 #sound-dai-cells = <0>;
586 589
587 status = "okay"; 590 status = "okay";
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 77c0beeb8d7c..e35812a0d8d4 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -78,7 +78,7 @@
78 <0 0xf1002000 0 0x1000>, 78 <0 0xf1002000 0 0x1000>,
79 <0 0xf1004000 0 0x2000>, 79 <0 0xf1004000 0 0x2000>,
80 <0 0xf1006000 0 0x2000>; 80 <0 0xf1006000 0 0x2000>;
81 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 81 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
82 }; 82 };
83 83
84 gpio0: gpio@e6050000 { 84 gpio0: gpio@e6050000 {
@@ -186,10 +186,10 @@
186 186
187 timer { 187 timer {
188 compatible = "arm,armv7-timer"; 188 compatible = "arm,armv7-timer";
189 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 189 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
190 <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 190 <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
191 <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 191 <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
192 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 192 <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
193 }; 193 };
194 194
195 cmt0: timer@ffca0000 { 195 cmt0: timer@ffca0000 {
@@ -1062,7 +1062,7 @@
1062 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; 1062 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1063 clocks = <&mp_clk>; 1063 clocks = <&mp_clk>;
1064 #clock-cells = <1>; 1064 #clock-cells = <1>;
1065 renesas,clock-indices = <R8A7791_CLK_MSIOF0>; 1065 clock-indices = <R8A7791_CLK_MSIOF0>;
1066 clock-output-names = "msiof0"; 1066 clock-output-names = "msiof0";
1067 }; 1067 };
1068 mstp1_clks: mstp1_clks@e6150134 { 1068 mstp1_clks: mstp1_clks@e6150134 {
@@ -1073,7 +1073,7 @@
1073 <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>, 1073 <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>,
1074 <&zs_clk>; 1074 <&zs_clk>;
1075 #clock-cells = <1>; 1075 #clock-cells = <1>;
1076 renesas,clock-indices = < 1076 clock-indices = <
1077 R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU 1077 R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU
1078 R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG 1078 R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG
1079 R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0 1079 R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0
@@ -1093,7 +1093,7 @@
1093 <&mp_clk>, <&mp_clk>, <&mp_clk>, 1093 <&mp_clk>, <&mp_clk>, <&mp_clk>,
1094 <&zs_clk>, <&zs_clk>; 1094 <&zs_clk>, <&zs_clk>;
1095 #clock-cells = <1>; 1095 #clock-cells = <1>;
1096 renesas,clock-indices = < 1096 clock-indices = <
1097 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0 1097 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
1098 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1 1098 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
1099 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2 1099 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
@@ -1111,7 +1111,7 @@
1111 <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>, 1111 <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1112 <&hp_clk>, <&hp_clk>; 1112 <&hp_clk>, <&hp_clk>;
1113 #clock-cells = <1>; 1113 #clock-cells = <1>;
1114 renesas,clock-indices = < 1114 clock-indices = <
1115 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0 1115 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
1116 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1 1116 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
1117 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1 1117 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
@@ -1127,8 +1127,10 @@
1127 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; 1127 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1128 clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>; 1128 clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>;
1129 #clock-cells = <1>; 1129 #clock-cells = <1>;
1130 renesas,clock-indices = <R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1 1130 clock-indices = <
1131 R8A7791_CLK_THERMAL R8A7791_CLK_PWM>; 1131 R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1
1132 R8A7791_CLK_THERMAL R8A7791_CLK_PWM
1133 >;
1132 clock-output-names = "audmac0", "audmac1", "thermal", "pwm"; 1134 clock-output-names = "audmac0", "audmac1", "thermal", "pwm";
1133 }; 1135 };
1134 mstp7_clks: mstp7_clks@e615014c { 1136 mstp7_clks: mstp7_clks@e615014c {
@@ -1138,7 +1140,7 @@
1138 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, 1140 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1139 <&zx_clk>, <&zx_clk>, <&zx_clk>; 1141 <&zx_clk>, <&zx_clk>, <&zx_clk>;
1140 #clock-cells = <1>; 1142 #clock-cells = <1>;
1141 renesas,clock-indices = < 1143 clock-indices = <
1142 R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5 1144 R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
1143 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0 1145 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
1144 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1 1146 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
@@ -1152,15 +1154,17 @@
1152 mstp8_clks: mstp8_clks@e6150990 { 1154 mstp8_clks: mstp8_clks@e6150990 {
1153 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1155 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1154 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; 1156 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1155 clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>, 1157 clocks = <&zg_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>,
1156 <&zs_clk>; 1158 <&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>;
1157 #clock-cells = <1>; 1159 #clock-cells = <1>;
1158 renesas,clock-indices = < 1160 clock-indices = <
1161 R8A7791_CLK_IPMMU_SGX R8A7791_CLK_MLB
1159 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0 1162 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
1160 R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0 1163 R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
1161 >; 1164 >;
1162 clock-output-names = 1165 clock-output-names =
1163 "vin2", "vin1", "vin0", "ether", "sata1", "sata0"; 1166 "ipmmu_sgx", "mlb", "vin2", "vin1", "vin0", "ether",
1167 "sata1", "sata0";
1164 }; 1168 };
1165 mstp9_clks: mstp9_clks@e6150994 { 1169 mstp9_clks: mstp9_clks@e6150994 {
1166 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1170 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -1171,7 +1175,7 @@
1171 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, 1175 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1172 <&hp_clk>, <&hp_clk>; 1176 <&hp_clk>, <&hp_clk>;
1173 #clock-cells = <1>; 1177 #clock-cells = <1>;
1174 renesas,clock-indices = < 1178 clock-indices = <
1175 R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4 1179 R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4
1176 R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0 1180 R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0
1177 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5 1181 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
@@ -1221,7 +1225,7 @@
1221 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; 1225 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1222 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; 1226 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1223 #clock-cells = <1>; 1227 #clock-cells = <1>;
1224 renesas,clock-indices = < 1228 clock-indices = <
1225 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5 1229 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
1226 >; 1230 >;
1227 clock-output-names = "scifa3", "scifa4", "scifa5"; 1231 clock-output-names = "scifa3", "scifa4", "scifa5";
@@ -1381,8 +1385,13 @@
1381 }; 1385 };
1382 1386
1383 rcar_sound: rcar_sound@ec500000 { 1387 rcar_sound: rcar_sound@ec500000 {
1384 #sound-dai-cells = <1>; 1388 /*
1385 compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2", "renesas,rcar_sound"; 1389 * #sound-dai-cells is required
1390 *
1391 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1392 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1393 */
1394 compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2";
1386 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1395 reg = <0 0xec500000 0 0x1000>, /* SCU */
1387 <0 0xec5a0000 0 0x100>, /* ADG */ 1396 <0 0xec5a0000 0 0x100>, /* ADG */
1388 <0 0xec540000 0 0x1000>, /* SSIU */ 1397 <0 0xec540000 0 0x1000>, /* SSIU */
@@ -1416,16 +1425,16 @@
1416 }; 1425 };
1417 1426
1418 rcar_sound,src { 1427 rcar_sound,src {
1419 src0: src@0 { }; 1428 src0: src@0 { interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; };
1420 src1: src@1 { }; 1429 src1: src@1 { interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>; };
1421 src2: src@2 { }; 1430 src2: src@2 { interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>; };
1422 src3: src@3 { }; 1431 src3: src@3 { interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>; };
1423 src4: src@4 { }; 1432 src4: src@4 { interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>; };
1424 src5: src@5 { }; 1433 src5: src@5 { interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>; };
1425 src6: src@6 { }; 1434 src6: src@6 { interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>; };
1426 src7: src@7 { }; 1435 src7: src@7 { interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>; };
1427 src8: src@8 { }; 1436 src8: src@8 { interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>; };
1428 src9: src@9 { }; 1437 src9: src@9 { interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>; };
1429 }; 1438 };
1430 1439
1431 rcar_sound,ssi { 1440 rcar_sound,ssi {
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index f2cf7576bf3f..0d848e605071 100644
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -40,9 +40,9 @@
40}; 40};
41 41
42&cmt0 { 42&cmt0 {
43 status = "ok"; 43 status = "okay";
44}; 44};
45 45
46&scif2 { 46&scif2 {
47 status = "ok"; 47 status = "okay";
48}; 48};
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 19c9de3f2a5a..8f78da5ef10b 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -47,7 +47,7 @@
47 <0 0xf1002000 0 0x1000>, 47 <0 0xf1002000 0 0x1000>,
48 <0 0xf1004000 0 0x2000>, 48 <0 0xf1004000 0 0x2000>,
49 <0 0xf1006000 0 0x2000>; 49 <0 0xf1006000 0 0x2000>;
50 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 50 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
51 }; 51 };
52 52
53 cmt0: timer@ffca0000 { 53 cmt0: timer@ffca0000 {
@@ -84,10 +84,10 @@
84 84
85 timer { 85 timer {
86 compatible = "arm,armv7-timer"; 86 compatible = "arm,armv7-timer";
87 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 87 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
88 <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 88 <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
89 <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 89 <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
90 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 90 <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
91 }; 91 };
92 92
93 irqc0: interrupt-controller@e61c0000 { 93 irqc0: interrupt-controller@e61c0000 {
@@ -293,6 +293,28 @@
293 clock-output-names = "main", "pll0", "pll1", "pll3", 293 clock-output-names = "main", "pll0", "pll1", "pll3",
294 "lb", "qspi", "sdh", "sd0", "z"; 294 "lb", "qspi", "sdh", "sd0", "z";
295 }; 295 };
296 /* Variable factor clocks */
297 sd1_clk: sd2_clk@e6150078 {
298 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
299 reg = <0 0xe6150078 0 4>;
300 clocks = <&pll1_div2_clk>;
301 #clock-cells = <0>;
302 clock-output-names = "sd1";
303 };
304 sd2_clk: sd3_clk@e615007c {
305 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
306 reg = <0 0xe615007c 0 4>;
307 clocks = <&pll1_div2_clk>;
308 #clock-cells = <0>;
309 clock-output-names = "sd2";
310 };
311 mmc0_clk: mmc0_clk@e6150240 {
312 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
313 reg = <0 0xe6150240 0 4>;
314 clocks = <&pll1_div2_clk>;
315 #clock-cells = <0>;
316 clock-output-names = "mmc0";
317 };
296 318
297 /* Fixed factor clocks */ 319 /* Fixed factor clocks */
298 pll1_div2_clk: pll1_div2_clk { 320 pll1_div2_clk: pll1_div2_clk {
@@ -455,7 +477,7 @@
455 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; 477 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
456 clocks = <&mp_clk>; 478 clocks = <&mp_clk>;
457 #clock-cells = <1>; 479 #clock-cells = <1>;
458 renesas,clock-indices = <R8A7794_CLK_MSIOF0>; 480 clock-indices = <R8A7794_CLK_MSIOF0>;
459 clock-output-names = "msiof0"; 481 clock-output-names = "msiof0";
460 }; 482 };
461 mstp1_clks: mstp1_clks@e6150134 { 483 mstp1_clks: mstp1_clks@e6150134 {
@@ -465,7 +487,7 @@
465 <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>, 487 <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
466 <&zs_clk>, <&zs_clk>; 488 <&zs_clk>, <&zs_clk>;
467 #clock-cells = <1>; 489 #clock-cells = <1>;
468 renesas,clock-indices = < 490 clock-indices = <
469 R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1 491 R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
470 R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0 492 R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
471 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0 493 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
@@ -479,41 +501,51 @@
479 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 501 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
480 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; 502 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
481 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, 503 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
482 <&mp_clk>, <&mp_clk>, <&mp_clk>; 504 <&mp_clk>, <&mp_clk>, <&mp_clk>,
505 <&zs_clk>, <&zs_clk>;
483 #clock-cells = <1>; 506 #clock-cells = <1>;
484 renesas,clock-indices = < 507 clock-indices = <
485 R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0 508 R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
486 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1 509 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
487 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2 510 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
511 R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0
488 >; 512 >;
489 clock-output-names = 513 clock-output-names =
490 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", 514 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
491 "scifb1", "msiof1", "scifb2"; 515 "scifb1", "msiof1", "scifb2",
516 "sys-dmac1", "sys-dmac0";
492 }; 517 };
493 mstp3_clks: mstp3_clks@e615013c { 518 mstp3_clks: mstp3_clks@e615013c {
494 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 519 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
495 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; 520 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
496 clocks = <&rclk_clk>; 521 clocks = <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
522 <&mmc0_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>;
497 #clock-cells = <1>; 523 #clock-cells = <1>;
498 renesas,clock-indices = < 524 clock-indices = <
499 R8A7794_CLK_CMT1 525 R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
526 R8A7794_CLK_MMCIF0 R8A7794_CLK_CMT1
527 R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1
500 >; 528 >;
501 clock-output-names = 529 clock-output-names =
502 "cmt1"; 530 "sdhi2", "sdhi1", "sdhi0",
531 "mmcif0", "cmt1", "usbdmac0", "usbdmac1";
503 }; 532 };
504 mstp7_clks: mstp7_clks@e615014c { 533 mstp7_clks: mstp7_clks@e615014c {
505 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 534 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
506 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; 535 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
507 clocks = <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, 536 clocks = <&mp_clk>, <&mp_clk>,
537 <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
508 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>; 538 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>;
509 #clock-cells = <1>; 539 #clock-cells = <1>;
510 renesas,clock-indices = < 540 clock-indices = <
541 R8A7794_CLK_EHCI R8A7794_CLK_HSUSB
511 R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5 542 R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
512 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0 543 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
513 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1 544 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
514 R8A7794_CLK_SCIF0 545 R8A7794_CLK_SCIF0
515 >; 546 >;
516 clock-output-names = 547 clock-output-names =
548 "ehci", "hsusb",
517 "hscif2", "scif5", "scif4", "hscif1", "hscif0", 549 "hscif2", "scif5", "scif4", "hscif1", "hscif0",
518 "scif3", "scif2", "scif1", "scif0"; 550 "scif3", "scif2", "scif1", "scif0";
519 }; 551 };
@@ -522,18 +554,32 @@
522 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; 554 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
523 clocks = <&zg_clk>, <&zg_clk>, <&p_clk>; 555 clocks = <&zg_clk>, <&zg_clk>, <&p_clk>;
524 #clock-cells = <1>; 556 #clock-cells = <1>;
525 renesas,clock-indices = < 557 clock-indices = <
526 R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 R8A7794_CLK_ETHER 558 R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 R8A7794_CLK_ETHER
527 >; 559 >;
528 clock-output-names = 560 clock-output-names =
529 "vin1", "vin0", "ether"; 561 "vin1", "vin0", "ether";
530 }; 562 };
563 mstp9_clks: mstp9_clks@e6150994 {
564 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
565 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
566 clocks = <&cpg_clocks R8A7794_CLK_QSPI>, <&hp_clk>, <&hp_clk>,
567 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
568 #clock-cells = <1>;
569 clock-indices = <
570 R8A7794_CLK_QSPI_MOD R8A7794_CLK_I2C5 R8A7794_CLK_I2C4
571 R8A7794_CLK_I2C3 R8A7794_CLK_I2C2 R8A7794_CLK_I2C1
572 R8A7794_CLK_I2C0
573 >;
574 clock-output-names =
575 "qspi_mod", "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
576 };
531 mstp11_clks: mstp11_clks@e615099c { 577 mstp11_clks: mstp11_clks@e615099c {
532 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 578 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
533 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; 579 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
534 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; 580 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
535 #clock-cells = <1>; 581 #clock-cells = <1>;
536 renesas,clock-indices = < 582 clock-indices = <
537 R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5 583 R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
538 >; 584 >;
539 clock-output-names = "scifa3", "scifa4", "scifa5"; 585 clock-output-names = "scifa3", "scifa4", "scifa5";
diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts
new file mode 100644
index 000000000000..3ac151102c2f
--- /dev/null
+++ b/arch/arm/boot/dts/rk3066a-rayeager.dts
@@ -0,0 +1,468 @@
1/*
2 * Copyright (c) 2014, 2015 FUKAUMI Naoki <naobsd@gmail.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43/dts-v1/;
44#include "rk3066a.dtsi"
45
46/ {
47 model = "Rayeager PX2";
48 compatible = "chipspark,rayeager-px2", "rockchip,rk3066a";
49
50 memory {
51 reg = <0x60000000 0x40000000>;
52 };
53
54 ir: ir-receiver {
55 compatible = "gpio-ir-receiver";
56 gpios = <&gpio6 1 GPIO_ACTIVE_LOW>;
57 pinctrl-names = "default";
58 pinctrl-0 = <&ir_int>;
59 };
60
61 keys: gpio-keys {
62 compatible = "gpio-keys";
63 #address-cells = <1>;
64 #size-cells = <0>;
65
66 button@0 {
67 gpio-key,wakeup = <1>;
68 gpios = <&gpio6 2 GPIO_ACTIVE_LOW>;
69 label = "GPIO Power";
70 linux,code = <116>;
71 pinctrl-names = "default";
72 pinctrl-0 = <&pwr_key>;
73 };
74 };
75
76 vsys: vsys-regulator {
77 compatible = "regulator-fixed";
78 regulator-name = "vsys";
79 regulator-min-microvolt = <5000000>;
80 regulator-max-microvolt = <5000000>;
81 regulator-always-on;
82 regulator-boot-on;
83 };
84
85 /* input for 5V_STDBY is VSYS or DC5V, selectable by jumper J4 */
86 vcc_stdby: 5v-stdby-regulator {
87 compatible = "regulator-fixed";
88 regulator-name = "5v_stdby";
89 regulator-min-microvolt = <5000000>;
90 regulator-max-microvolt = <5000000>;
91 regulator-always-on;
92 regulator-boot-on;
93 };
94
95 vcc_emmc: emmc-regulator {
96 compatible = "regulator-fixed";
97 regulator-name = "emmc_vccq";
98 regulator-min-microvolt = <3000000>;
99 regulator-max-microvolt = <3000000>;
100 vin-supply = <&vsys>;
101 };
102
103 vcc_sata: sata-regulator {
104 compatible = "regulator-fixed";
105 enable-active-high;
106 gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>;
107 pinctrl-names = "default";
108 pinctrl-0 = <&sata_pwr>;
109 regulator-name = "usb_5v";
110 regulator-min-microvolt = <5000000>;
111 regulator-max-microvolt = <5000000>;
112 regulator-always-on;
113 vin-supply = <&vcc_stdby>;
114 };
115
116 vcc_sd: sdmmc-regulator {
117 compatible = "regulator-fixed";
118 gpio = <&gpio3 7 GPIO_ACTIVE_LOW>;
119 pinctrl-names = "default";
120 pinctrl-0 = <&sdmmc_pwr>;
121 regulator-name = "vcc_sd";
122 regulator-min-microvolt = <3300000>;
123 regulator-max-microvolt = <3300000>;
124 startup-delay-us = <100000>;
125 vin-supply = <&vcc_io>;
126 };
127
128 vcc_host: usb-host-regulator {
129 compatible = "regulator-fixed";
130 enable-active-high;
131 gpio = <&gpio0 6 GPIO_ACTIVE_HIGH>;
132 pinctrl-names = "default";
133 pinctrl-0 = <&host_drv>;
134 regulator-name = "host-pwr";
135 regulator-min-microvolt = <5000000>;
136 regulator-max-microvolt = <5000000>;
137 regulator-always-on;
138 vin-supply = <&vcc_stdby>;
139 };
140
141 vcc_otg: usb-otg-regulator {
142 compatible = "regulator-fixed";
143 enable-active-high;
144 gpio = <&gpio0 5 GPIO_ACTIVE_HIGH>;
145 pinctrl-names = "default";
146 pinctrl-0 = <&otg_drv>;
147 regulator-name = "vcc_otg";
148 regulator-min-microvolt = <5000000>;
149 regulator-max-microvolt = <5000000>;
150 regulator-always-on;
151 vin-supply = <&vcc_stdby>;
152 };
153};
154
155&cpu0 {
156 cpu0-supply = <&vdd_arm>;
157};
158
159&emac {
160 pinctrl-names = "default";
161 pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&rmii_rst>;
162 phy = <&phy0>;
163 phy-supply = <&vcc_rmii>;
164 status = "okay";
165
166 phy0: ethernet-phy@0 {
167 reg = <0>;
168 };
169};
170
171&emmc {
172 broken-cd;
173 bus-width = <8>;
174 cap-mmc-highspeed;
175 disable-wp;
176 non-removable;
177 num-slots = <1>;
178 pinctrl-names = "default";
179 pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_rst>;
180 vmmc-supply = <&vcc_emmc>;
181 vqmmc-supply = <&vcc_emmc>;
182 status = "okay";
183};
184
185&i2c0 {
186 clock-frequency = <400000>;
187 status = "okay";
188
189 ak8963: ak8963@0d {
190 compatible = "asahi-kasei,ak8975";
191 reg = <0x0d>;
192 interrupt-parent = <&gpio4>;
193 interrupts = <17 IRQ_TYPE_EDGE_RISING>;
194 pinctrl-names = "default";
195 pinctrl-0 = <&comp_int>;
196 };
197
198 mma8452: mma8452@1d {
199 compatible = "fsl,mma8452";
200 reg = <0x1d>;
201 interrupt-parent = <&gpio4>;
202 interrupts = <16 IRQ_TYPE_EDGE_RISING>;
203 pinctrl-names = "default";
204 pinctrl-0 = <&gsensor_int>;
205 };
206};
207
208&i2c1 {
209 clock-frequency = <400000>;
210 status = "okay";
211
212 tps: tps@2d {
213 reg = <0x2d>;
214 interrupt-parent = <&gpio6>;
215 interrupts = <4 IRQ_TYPE_EDGE_RISING>;
216 pinctrl-names = "default";
217 pinctrl-0 = <&pmic_int>, <&pwr_hold>;
218
219 vcc1-supply = <&vsys>;
220 vcc2-supply = <&vsys>;
221 vcc3-supply = <&vsys>;
222 vcc4-supply = <&vsys>;
223 vcc5-supply = <&vcc_io>;
224 vcc6-supply = <&vcc_io>;
225 vcc7-supply = <&vsys>;
226 vccio-supply = <&vsys>;
227
228 regulators {
229 vcc_rtc: regulator@0 {
230 regulator-name = "vcc_rtc";
231 regulator-always-on;
232 };
233
234 vcc_io: regulator@1 {
235 regulator-name = "vcc_io";
236 regulator-min-microvolt = <3300000>;
237 regulator-max-microvolt = <3300000>;
238 regulator-always-on;
239 };
240
241 vdd_arm: regulator@2 {
242 regulator-name = "vdd_arm";
243 regulator-min-microvolt = <600000>;
244 regulator-max-microvolt = <1500000>;
245 regulator-always-on;
246 regulator-boot-on;
247 };
248
249 vcc_ddr: regulator@3 {
250 regulator-name = "vcc_ddr";
251 regulator-min-microvolt = <600000>;
252 regulator-max-microvolt = <1500000>;
253 regulator-always-on;
254 regulator-boot-on;
255 };
256
257 vcc18: regulator@5 {
258 regulator-name = "vcc18";
259 regulator-min-microvolt = <1800000>;
260 regulator-max-microvolt = <1800000>;
261 regulator-always-on;
262 };
263
264 vdd_11: regulator@6 {
265 regulator-name = "vdd_11";
266 regulator-min-microvolt = <1100000>;
267 regulator-max-microvolt = <1100000>;
268 regulator-always-on;
269 };
270
271 vcc_25: regulator@7 {
272 regulator-name = "vcc_25";
273 regulator-min-microvolt = <2500000>;
274 regulator-max-microvolt = <2500000>;
275 regulator-always-on;
276 };
277
278 vccio_wl: regulator@8 {
279 regulator-name = "vccio_wl";
280 regulator-min-microvolt = <1800000>;
281 regulator-max-microvolt = <1800000>;
282 };
283
284 vcc25_hdmi: regulator@9 {
285 regulator-name = "vcc25_hdmi";
286 regulator-min-microvolt = <2500000>;
287 regulator-max-microvolt = <2500000>;
288 };
289
290 vcca_33: regulator@10 {
291 regulator-name = "vcca_33";
292 regulator-min-microvolt = <3300000>;
293 regulator-max-microvolt = <3300000>;
294 };
295
296 vcc_rmii: regulator@11 {
297 regulator-name = "vcc_rmii";
298 regulator-min-microvolt = <3300000>;
299 regulator-max-microvolt = <3300000>;
300 };
301
302 vcc28_cif: regulator@12 {
303 regulator-name = "vcc28_cif";
304 regulator-min-microvolt = <2800000>;
305 regulator-max-microvolt = <2800000>;
306 };
307 };
308 };
309};
310
311#include "tps65910.dtsi"
312
313&i2c2 {
314 status = "okay";
315};
316
317&i2c3 {
318 status = "okay";
319};
320
321&i2c4 {
322 status = "okay";
323};
324
325&mmc0 {
326 bus-width = <4>;
327 disable-wp;
328 num-slots = <1>;
329 pinctrl-names = "default";
330 pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
331 vmmc-supply = <&vcc_sd>;
332 status = "okay";
333};
334
335&mmc1 {
336 broken-cd;
337 bus-width = <4>;
338 disable-wp;
339 non-removable;
340 num-slots = <1>;
341 pinctrl-names = "default";
342 pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_bus4>;
343 vmmc-supply = <&vccio_wl>;
344 status = "okay";
345};
346
347&pinctrl {
348 pcfg_output_high: pcfg-output-high {
349 output-high;
350 };
351
352 ak8963 {
353 comp_int: comp-int {
354 rockchip,pins = <4 17 RK_FUNC_GPIO &pcfg_pull_default>;
355 };
356 };
357
358 emac {
359 rmii_rst: rmii-rst {
360 rockchip,pins = <1 30 RK_FUNC_GPIO &pcfg_output_high>;
361 };
362 };
363
364 ir {
365 ir_int: ir-int {
366 rockchip,pins = <6 1 RK_FUNC_GPIO &pcfg_pull_default>;
367 };
368 };
369
370 keys {
371 pwr_key: pwr-key {
372 rockchip,pins = <6 2 RK_FUNC_GPIO &pcfg_pull_default>;
373 };
374 };
375
376 mma8452 {
377 gsensor_int: gsensor-int {
378 rockchip,pins = <4 16 RK_FUNC_GPIO &pcfg_pull_default>;
379 };
380 };
381
382 mmc {
383 sdmmc_pwr: sdmmc-pwr {
384 rockchip,pins = <3 7 RK_FUNC_GPIO &pcfg_pull_default>;
385 };
386 };
387
388 usb_host {
389 host_drv: host-drv {
390 rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_default>;
391 };
392
393 hub_rst: hub-rst {
394 rockchip,pins = <1 31 RK_FUNC_GPIO &pcfg_output_high>;
395 };
396
397 sata_pwr: sata-pwr {
398 rockchip,pins = <4 22 RK_FUNC_GPIO &pcfg_pull_default>;
399 };
400
401 sata_reset: sata-reset {
402 rockchip,pins = <0 13 RK_FUNC_GPIO &pcfg_output_high>;
403 };
404 };
405
406 usb_otg {
407 otg_drv: otg-drv {
408 rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_default>;
409 };
410 };
411
412 tps {
413 pmic_int: pmic-int {
414 rockchip,pins = <6 4 RK_FUNC_GPIO &pcfg_pull_default>;
415 };
416
417 pwr_hold: pwr-hold {
418 rockchip,pins = <6 8 RK_FUNC_GPIO &pcfg_output_high>;
419 };
420 };
421};
422
423&pwm1 {
424 status = "okay";
425};
426
427&pwm2 {
428 status = "okay";
429};
430
431&saradc {
432 vref-supply = <&vcc_25>;
433 status = "okay";
434};
435
436&spi0 {
437 status = "okay";
438};
439
440&uart0 {
441 pinctrl-names = "default";
442 pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>;
443 status = "okay";
444};
445
446&uart2 {
447 status = "okay";
448};
449
450&uart3 {
451 pinctrl-names = "default";
452 pinctrl-0 = <&uart3_xfer>, <&uart3_cts>, <&uart3_rts>;
453 status = "okay";
454};
455
456&usb_host {
457 pinctrl-names = "default";
458 pinctrl-0 = <&hub_rst>, <&sata_reset>;
459 status = "okay";
460};
461
462&usb_otg {
463 status = "okay";
464};
465
466&wdt {
467 status = "okay";
468};
diff --git a/arch/arm/boot/dts/rk3288-evb-act8846.dts b/arch/arm/boot/dts/rk3288-evb-act8846.dts
index a76dd44adb53..d7b8bbc0c25f 100644
--- a/arch/arm/boot/dts/rk3288-evb-act8846.dts
+++ b/arch/arm/boot/dts/rk3288-evb-act8846.dts
@@ -17,7 +17,34 @@
17 compatible = "rockchip,rk3288-evb-act8846", "rockchip,rk3288"; 17 compatible = "rockchip,rk3288-evb-act8846", "rockchip,rk3288";
18}; 18};
19 19
20&cpu0 {
21 cpu0-supply = <&vdd_cpu>;
22};
23
20&i2c0 { 24&i2c0 {
25 clock-frequency = <400000>;
26
27 vdd_cpu: syr827@40 {
28 compatible = "silergy,syr827";
29 fcs,suspend-voltage-selector = <1>;
30 reg = <0x40>;
31 regulator-name = "vdd_cpu";
32 regulator-min-microvolt = <850000>;
33 regulator-max-microvolt = <1350000>;
34 regulator-always-on;
35 regulator-boot-on;
36 };
37
38 vdd_gpu: syr828@41 {
39 compatible = "silergy,syr828";
40 fcs,suspend-voltage-selector = <1>;
41 reg = <0x41>;
42 regulator-name = "vdd_gpu";
43 regulator-min-microvolt = <850000>;
44 regulator-max-microvolt = <1350000>;
45 regulator-always-on;
46 };
47
21 hym8563@51 { 48 hym8563@51 {
22 compatible = "haoyu,hym8563"; 49 compatible = "haoyu,hym8563";
23 reg = <0x51>; 50 reg = <0x51>;
diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts b/arch/arm/boot/dts/rk3288-evb-rk808.dts
index e1d3eeb8f094..a1c294bf7fed 100644
--- a/arch/arm/boot/dts/rk3288-evb-rk808.dts
+++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts
@@ -30,7 +30,6 @@
30 30
31&i2c0 { 31&i2c0 {
32 clock-frequency = <400000>; 32 clock-frequency = <400000>;
33 status = "okay";
34 33
35 rk808: pmic@1b { 34 rk808: pmic@1b {
36 compatible = "rockchip,rk808"; 35 compatible = "rockchip,rk808";
@@ -38,7 +37,7 @@
38 interrupt-parent = <&gpio0>; 37 interrupt-parent = <&gpio0>;
39 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 38 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
40 pinctrl-names = "default"; 39 pinctrl-names = "default";
41 pinctrl-0 = <&pmic_int>; 40 pinctrl-0 = <&pmic_int &global_pwroff>;
42 rockchip,system-power-controller; 41 rockchip,system-power-controller;
43 wakeup-source; 42 wakeup-source;
44 #clock-cells = <1>; 43 #clock-cells = <1>;
@@ -57,6 +56,9 @@
57 regulator-min-microvolt = <750000>; 56 regulator-min-microvolt = <750000>;
58 regulator-max-microvolt = <1350000>; 57 regulator-max-microvolt = <1350000>;
59 regulator-name = "vdd_arm"; 58 regulator-name = "vdd_arm";
59 regulator-state-mem {
60 regulator-off-in-suspend;
61 };
60 }; 62 };
61 63
62 vdd_gpu: DCDC_REG2 { 64 vdd_gpu: DCDC_REG2 {
@@ -65,12 +67,19 @@
65 regulator-min-microvolt = <850000>; 67 regulator-min-microvolt = <850000>;
66 regulator-max-microvolt = <1250000>; 68 regulator-max-microvolt = <1250000>;
67 regulator-name = "vdd_gpu"; 69 regulator-name = "vdd_gpu";
70 regulator-state-mem {
71 regulator-on-in-suspend;
72 regulator-suspend-microvolt = <1000000>;
73 };
68 }; 74 };
69 75
70 vcc_ddr: DCDC_REG3 { 76 vcc_ddr: DCDC_REG3 {
71 regulator-always-on; 77 regulator-always-on;
72 regulator-boot-on; 78 regulator-boot-on;
73 regulator-name = "vcc_ddr"; 79 regulator-name = "vcc_ddr";
80 regulator-state-mem {
81 regulator-on-in-suspend;
82 };
74 }; 83 };
75 84
76 vcc_io: DCDC_REG4 { 85 vcc_io: DCDC_REG4 {
@@ -79,6 +88,10 @@
79 regulator-min-microvolt = <3300000>; 88 regulator-min-microvolt = <3300000>;
80 regulator-max-microvolt = <3300000>; 89 regulator-max-microvolt = <3300000>;
81 regulator-name = "vcc_io"; 90 regulator-name = "vcc_io";
91 regulator-state-mem {
92 regulator-on-in-suspend;
93 regulator-suspend-microvolt = <3300000>;
94 };
82 }; 95 };
83 96
84 vccio_pmu: LDO_REG1 { 97 vccio_pmu: LDO_REG1 {
@@ -87,6 +100,10 @@
87 regulator-min-microvolt = <3300000>; 100 regulator-min-microvolt = <3300000>;
88 regulator-max-microvolt = <3300000>; 101 regulator-max-microvolt = <3300000>;
89 regulator-name = "vccio_pmu"; 102 regulator-name = "vccio_pmu";
103 regulator-state-mem {
104 regulator-on-in-suspend;
105 regulator-suspend-microvolt = <3300000>;
106 };
90 }; 107 };
91 108
92 vcc_tp: LDO_REG2 { 109 vcc_tp: LDO_REG2 {
@@ -95,6 +112,9 @@
95 regulator-min-microvolt = <3300000>; 112 regulator-min-microvolt = <3300000>;
96 regulator-max-microvolt = <3300000>; 113 regulator-max-microvolt = <3300000>;
97 regulator-name = "vcc_tp"; 114 regulator-name = "vcc_tp";
115 regulator-state-mem {
116 regulator-off-in-suspend;
117 };
98 }; 118 };
99 119
100 vdd_10: LDO_REG3 { 120 vdd_10: LDO_REG3 {
@@ -103,6 +123,10 @@
103 regulator-min-microvolt = <1000000>; 123 regulator-min-microvolt = <1000000>;
104 regulator-max-microvolt = <1000000>; 124 regulator-max-microvolt = <1000000>;
105 regulator-name = "vdd_10"; 125 regulator-name = "vdd_10";
126 regulator-state-mem {
127 regulator-on-in-suspend;
128 regulator-suspend-microvolt = <1000000>;
129 };
106 }; 130 };
107 131
108 vcc18_lcd: LDO_REG4 { 132 vcc18_lcd: LDO_REG4 {
@@ -111,6 +135,10 @@
111 regulator-min-microvolt = <1800000>; 135 regulator-min-microvolt = <1800000>;
112 regulator-max-microvolt = <1800000>; 136 regulator-max-microvolt = <1800000>;
113 regulator-name = "vcc18_lcd"; 137 regulator-name = "vcc18_lcd";
138 regulator-state-mem {
139 regulator-on-in-suspend;
140 regulator-suspend-microvolt = <1800000>;
141 };
114 }; 142 };
115 143
116 vccio_sd: LDO_REG5 { 144 vccio_sd: LDO_REG5 {
@@ -119,6 +147,10 @@
119 regulator-min-microvolt = <1800000>; 147 regulator-min-microvolt = <1800000>;
120 regulator-max-microvolt = <3300000>; 148 regulator-max-microvolt = <3300000>;
121 regulator-name = "vccio_sd"; 149 regulator-name = "vccio_sd";
150 regulator-state-mem {
151 regulator-on-in-suspend;
152 regulator-suspend-microvolt = <3300000>;
153 };
122 }; 154 };
123 155
124 vdd10_lcd: LDO_REG6 { 156 vdd10_lcd: LDO_REG6 {
@@ -127,6 +159,10 @@
127 regulator-min-microvolt = <1000000>; 159 regulator-min-microvolt = <1000000>;
128 regulator-max-microvolt = <1000000>; 160 regulator-max-microvolt = <1000000>;
129 regulator-name = "vdd10_lcd"; 161 regulator-name = "vdd10_lcd";
162 regulator-state-mem {
163 regulator-on-in-suspend;
164 regulator-suspend-microvolt = <1000000>;
165 };
130 }; 166 };
131 167
132 vcc_18: LDO_REG7 { 168 vcc_18: LDO_REG7 {
@@ -135,6 +171,10 @@
135 regulator-min-microvolt = <1800000>; 171 regulator-min-microvolt = <1800000>;
136 regulator-max-microvolt = <1800000>; 172 regulator-max-microvolt = <1800000>;
137 regulator-name = "vcc_18"; 173 regulator-name = "vcc_18";
174 regulator-state-mem {
175 regulator-on-in-suspend;
176 regulator-suspend-microvolt = <1800000>;
177 };
138 }; 178 };
139 179
140 vcca_codec: LDO_REG8 { 180 vcca_codec: LDO_REG8 {
@@ -143,18 +183,28 @@
143 regulator-min-microvolt = <3300000>; 183 regulator-min-microvolt = <3300000>;
144 regulator-max-microvolt = <3300000>; 184 regulator-max-microvolt = <3300000>;
145 regulator-name = "vcca_codec"; 185 regulator-name = "vcca_codec";
186 regulator-state-mem {
187 regulator-on-in-suspend;
188 regulator-suspend-microvolt = <3300000>;
189 };
146 }; 190 };
147 191
148 vcc_wl: SWITCH_REG1 { 192 vcc_wl: SWITCH_REG1 {
149 regulator-always-on; 193 regulator-always-on;
150 regulator-boot-on; 194 regulator-boot-on;
151 regulator-name = "vcc_wl"; 195 regulator-name = "vcc_wl";
196 regulator-state-mem {
197 regulator-on-in-suspend;
198 };
152 }; 199 };
153 200
154 vcc_lcd: SWITCH_REG2 { 201 vcc_lcd: SWITCH_REG2 {
155 regulator-always-on; 202 regulator-always-on;
156 regulator-boot-on; 203 regulator-boot-on;
157 regulator-name = "vcc_lcd"; 204 regulator-name = "vcc_lcd";
205 regulator-state-mem {
206 regulator-on-in-suspend;
207 };
158 }; 208 };
159 }; 209 };
160 }; 210 };
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi
index 1c08eb0ecdb9..5e895a514a0b 100644
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -117,6 +117,11 @@
117 status = "okay"; 117 status = "okay";
118}; 118};
119 119
120&hdmi {
121 ddc-i2c-bus = <&i2c5>;
122 status = "okay";
123};
124
120&sdmmc { 125&sdmmc {
121 bus-width = <4>; 126 bus-width = <4>;
122 cap-mmc-highspeed; 127 cap-mmc-highspeed;
@@ -133,6 +138,10 @@
133 status = "okay"; 138 status = "okay";
134}; 139};
135 140
141&i2c5 {
142 status = "okay";
143};
144
136&wdt { 145&wdt {
137 status = "okay"; 146 status = "okay";
138}; 147};
@@ -236,3 +245,19 @@
236&usb_host1 { 245&usb_host1 {
237 status = "okay"; 246 status = "okay";
238}; 247};
248
249&vopb {
250 status = "okay";
251};
252
253&vopb_mmu {
254 status = "okay";
255};
256
257&vopl {
258 status = "okay";
259};
260
261&vopl_mmu {
262 status = "okay";
263};
diff --git a/arch/arm/boot/dts/rk3288-firefly-beta.dts b/arch/arm/boot/dts/rk3288-firefly-beta.dts
new file mode 100644
index 000000000000..75d77e38e0d6
--- /dev/null
+++ b/arch/arm/boot/dts/rk3288-firefly-beta.dts
@@ -0,0 +1,71 @@
1/*
2 * Copyright (c) 2014, 2015 FUKAUMI Naoki <naobsd@gmail.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43/dts-v1/;
44#include "rk3288-firefly.dtsi"
45
46/ {
47 model = "Firefly-RK3288 Beta";
48 compatible = "firefly,firefly-rk3288-beta", "rockchip,rk3288";
49};
50
51&ir {
52 gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
53};
54
55&pinctrl {
56 act8846 {
57 pmic_vsel: pmic-vsel {
58 rockchip,pins = <7 1 RK_FUNC_GPIO &pcfg_output_low>;
59 };
60 };
61
62 ir {
63 ir_int: ir-int {
64 rockchip,pins = <7 5 RK_FUNC_GPIO &pcfg_pull_up>;
65 };
66 };
67};
68
69&pwm0 {
70 status = "okay";
71};
diff --git a/arch/arm/boot/dts/rk3288-firefly.dts b/arch/arm/boot/dts/rk3288-firefly.dts
new file mode 100644
index 000000000000..c07fe92dc69f
--- /dev/null
+++ b/arch/arm/boot/dts/rk3288-firefly.dts
@@ -0,0 +1,71 @@
1/*
2 * Copyright (c) 2014, 2015 FUKAUMI Naoki <naobsd@gmail.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43/dts-v1/;
44#include "rk3288-firefly.dtsi"
45
46/ {
47 model = "Firefly-RK3288";
48 compatible = "firefly,firefly-rk3288", "rockchip,rk3288";
49};
50
51&ir {
52 gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
53};
54
55&pinctrl {
56 act8846 {
57 pmic_vsel: pmic-vsel {
58 rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_output_low>;
59 };
60 };
61
62 ir {
63 ir_int: ir-int {
64 rockchip,pins = <7 0 RK_FUNC_GPIO &pcfg_pull_up>;
65 };
66 };
67};
68
69&pwm1 {
70 status = "okay";
71};
diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi
new file mode 100644
index 000000000000..e6f873abbe0d
--- /dev/null
+++ b/arch/arm/boot/dts/rk3288-firefly.dtsi
@@ -0,0 +1,490 @@
1/*
2 * Copyright (c) 2014, 2015 FUKAUMI Naoki <naobsd@gmail.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include "rk3288.dtsi"
44
45/ {
46 memory {
47 reg = <0 0x80000000>;
48 };
49
50 ext_gmac: external-gmac-clock {
51 compatible = "fixed-clock";
52 #clock-cells = <0>;
53 clock-frequency = <125000000>;
54 clock-output-names = "ext_gmac";
55 };
56
57 ir: ir-receiver {
58 compatible = "gpio-ir-receiver";
59 pinctrl-names = "default";
60 pinctrl-0 = <&ir_int>;
61 };
62
63 keys: gpio-keys {
64 compatible = "gpio-keys";
65 #address-cells = <1>;
66 #size-cells = <0>;
67
68 button@0 {
69 gpio-key,wakeup = <1>;
70 gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
71 label = "GPIO Power";
72 linux,code = <116>;
73 pinctrl-names = "default";
74 pinctrl-0 = <&pwr_key>;
75 };
76 };
77
78 leds {
79 compatible = "gpio-leds";
80
81 work {
82 gpios = <&gpio8 1 GPIO_ACTIVE_LOW>;
83 label = "firefly:blue:user";
84 linux,default-trigger = "rc-feedback";
85 pinctrl-names = "default";
86 pinctrl-0 = <&work_led>;
87 };
88
89 power {
90 gpios = <&gpio8 2 GPIO_ACTIVE_LOW>;
91 label = "firefly:green:power";
92 linux,default-trigger = "default-on";
93 pinctrl-names = "default";
94 pinctrl-0 = <&power_led>;
95 };
96 };
97
98 vcc_sys: vsys-regulator {
99 compatible = "regulator-fixed";
100 regulator-name = "vcc_sys";
101 regulator-min-microvolt = <5000000>;
102 regulator-max-microvolt = <5000000>;
103 regulator-always-on;
104 regulator-boot-on;
105 };
106
107 vcc_sd: sdmmc-regulator {
108 compatible = "regulator-fixed";
109 gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
110 pinctrl-names = "default";
111 pinctrl-0 = <&sdmmc_pwr>;
112 regulator-name = "vcc_sd";
113 regulator-min-microvolt = <3300000>;
114 regulator-max-microvolt = <3300000>;
115 startup-delay-us = <100000>;
116 vin-supply = <&vcc_io>;
117 };
118
119 vcc_flash: flash-regulator {
120 compatible = "regulator-fixed";
121 regulator-name = "vcc_flash";
122 regulator-min-microvolt = <1800000>;
123 regulator-max-microvolt = <1800000>;
124 vin-supply = <&vcc_io>;
125 };
126
127 vcc_5v: usb-regulator {
128 compatible = "regulator-fixed";
129 regulator-name = "vcc_5v";
130 regulator-min-microvolt = <5000000>;
131 regulator-max-microvolt = <5000000>;
132 regulator-always-on;
133 regulator-boot-on;
134 vin-supply = <&vcc_sys>;
135 };
136
137 vcc_host_5v: usb-host-regulator {
138 compatible = "regulator-fixed";
139 enable-active-high;
140 gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
141 pinctrl-names = "default";
142 pinctrl-0 = <&host_vbus_drv>;
143 regulator-name = "vcc_host_5v";
144 regulator-min-microvolt = <5000000>;
145 regulator-max-microvolt = <5000000>;
146 regulator-always-on;
147 vin-supply = <&vcc_5v>;
148 };
149
150 vcc_otg_5v: usb-otg-regulator {
151 compatible = "regulator-fixed";
152 enable-active-high;
153 gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
154 pinctrl-names = "default";
155 pinctrl-0 = <&otg_vbus_drv>;
156 regulator-name = "vcc_otg_5v";
157 regulator-min-microvolt = <5000000>;
158 regulator-max-microvolt = <5000000>;
159 regulator-always-on;
160 vin-supply = <&vcc_5v>;
161 };
162};
163
164&cpu0 {
165 cpu0-supply = <&vdd_cpu>;
166};
167
168&emmc {
169 broken-cd;
170 bus-width = <8>;
171 cap-mmc-highspeed;
172 disable-wp;
173 non-removable;
174 num-slots = <1>;
175 pinctrl-names = "default";
176 pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>;
177 vmmc-supply = <&vcc_io>;
178 vqmmc-supply = <&vcc_flash>;
179 status = "okay";
180};
181
182&hdmi {
183 ddc-i2c-bus = <&i2c5>;
184 status = "okay";
185};
186
187&i2c0 {
188 clock-frequency = <400000>;
189 status = "okay";
190
191 vdd_cpu: syr827@40 {
192 compatible = "silergy,syr827";
193 fcs,suspend-voltage-selector = <1>;
194 reg = <0x40>;
195 regulator-name = "vdd_cpu";
196 regulator-min-microvolt = <850000>;
197 regulator-max-microvolt = <1350000>;
198 regulator-always-on;
199 regulator-boot-on;
200 vin-supply = <&vcc_sys>;
201 };
202
203 vdd_gpu: syr828@41 {
204 compatible = "silergy,syr828";
205 fcs,suspend-voltage-selector = <1>;
206 reg = <0x41>;
207 regulator-name = "vdd_gpu";
208 regulator-min-microvolt = <850000>;
209 regulator-max-microvolt = <1350000>;
210 regulator-always-on;
211 vin-supply = <&vcc_sys>;
212 };
213
214 hym8563: hym8563@51 {
215 compatible = "haoyu,hym8563";
216 reg = <0x51>;
217 #clock-cells = <0>;
218 clock-frequency = <32768>;
219 clock-output-names = "xin32k";
220 interrupt-parent = <&gpio7>;
221 interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
222 pinctrl-names = "default";
223 pinctrl-0 = <&rtc_int>;
224 };
225
226 act8846: act8846@5a {
227 compatible = "active-semi,act8846";
228 reg = <0x5a>;
229 pinctrl-names = "default";
230 pinctrl-0 = <&pmic_vsel>, <&pwr_hold>;
231 system-power-controller;
232
233 regulators {
234 vcc_ddr: REG1 {
235 regulator-name = "vcc_ddr";
236 regulator-min-microvolt = <1200000>;
237 regulator-max-microvolt = <1200000>;
238 regulator-always-on;
239 };
240
241 vcc_io: REG2 {
242 regulator-name = "vcc_io";
243 regulator-min-microvolt = <3300000>;
244 regulator-max-microvolt = <3300000>;
245 regulator-always-on;
246 };
247
248 vdd_log: REG3 {
249 regulator-name = "vdd_log";
250 regulator-min-microvolt = <1100000>;
251 regulator-max-microvolt = <1100000>;
252 regulator-always-on;
253 };
254
255 vcc_20: REG4 {
256 regulator-name = "vcc_20";
257 regulator-min-microvolt = <2000000>;
258 regulator-max-microvolt = <2000000>;
259 regulator-always-on;
260 };
261
262 vccio_sd: REG5 {
263 regulator-name = "vccio_sd";
264 regulator-min-microvolt = <3300000>;
265 regulator-max-microvolt = <3300000>;
266 regulator-always-on;
267 };
268
269 vdd10_lcd: REG6 {
270 regulator-name = "vdd10_lcd";
271 regulator-min-microvolt = <1000000>;
272 regulator-max-microvolt = <1000000>;
273 regulator-always-on;
274 };
275
276 vcca_18: REG7 {
277 regulator-name = "vcca_18";
278 regulator-min-microvolt = <1800000>;
279 regulator-max-microvolt = <1800000>;
280 };
281
282 vcca_33: REG8 {
283 regulator-name = "vcca_33";
284 regulator-min-microvolt = <3300000>;
285 regulator-max-microvolt = <3300000>;
286 };
287
288 vcc_lan: REG9 {
289 regulator-name = "vcc_lan";
290 regulator-min-microvolt = <3300000>;
291 regulator-max-microvolt = <3300000>;
292 };
293
294 vdd_10: REG10 {
295 regulator-name = "vdd_10";
296 regulator-min-microvolt = <1000000>;
297 regulator-max-microvolt = <1000000>;
298 regulator-always-on;
299 };
300
301 vcc_18: REG11 {
302 regulator-name = "vcc_18";
303 regulator-min-microvolt = <1800000>;
304 regulator-max-microvolt = <1800000>;
305 regulator-always-on;
306 };
307
308 vcc18_lcd: REG12 {
309 regulator-name = "vcc18_lcd";
310 regulator-min-microvolt = <1800000>;
311 regulator-max-microvolt = <1800000>;
312 regulator-always-on;
313 };
314 };
315 };
316};
317
318&i2c1 {
319 status = "okay";
320};
321
322&i2c2 {
323 status = "okay";
324};
325
326&i2c4 {
327 status = "okay";
328};
329
330&i2c5 {
331 status = "okay";
332};
333
334&pinctrl {
335 pcfg_output_high: pcfg-output-high {
336 output-high;
337 };
338
339 pcfg_output_low: pcfg-output-low {
340 output-low;
341 };
342
343 act8846 {
344 pwr_hold: pwr-hold {
345 rockchip,pins = <0 1 RK_FUNC_GPIO &pcfg_output_high>;
346 };
347 };
348
349 gmac {
350 phy_int: phy-int {
351 rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>;
352 };
353
354 phy_pmeb: phy-pmeb {
355 rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>;
356 };
357
358 phy_rst: phy-rst {
359 rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>;
360 };
361 };
362
363 hym8563 {
364 rtc_int: rtc-int {
365 rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_up>;
366 };
367 };
368
369 keys {
370 pwr_key: pwr-key {
371 rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
372 };
373 };
374
375 leds {
376 power_led: power-led {
377 rockchip,pins = <8 2 RK_FUNC_GPIO &pcfg_pull_none>;
378 };
379
380 work_led: work-led {
381 rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_none>;
382 };
383 };
384
385 sdmmc {
386 sdmmc_pwr: sdmmc-pwr {
387 rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
388 };
389 };
390
391 usb_host {
392 host_vbus_drv: host-vbus-drv {
393 rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
394 };
395
396 usbhub_rst: usbhub-rst {
397 rockchip,pins = <8 3 RK_FUNC_GPIO &pcfg_output_high>;
398 };
399 };
400
401 usb_otg {
402 otg_vbus_drv: otg-vbus-drv {
403 rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>;
404 };
405 };
406};
407
408&saradc {
409 vref-supply = <&vcc_18>;
410 status = "okay";
411};
412
413&sdio0 {
414 broken-cd;
415 bus-width = <4>;
416 disable-wp;
417 non-removable;
418 num-slots = <1>;
419 pinctrl-names = "default";
420 pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>;
421 vmmc-supply = <&vcc_18>;
422 status = "okay";
423};
424
425&sdmmc {
426 bus-width = <4>;
427 cap-mmc-highspeed;
428 cap-sd-highspeed;
429 card-detect-delay = <200>;
430 disable-wp;
431 num-slots = <1>;
432 pinctrl-names = "default";
433 pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
434 vmmc-supply = <&vcc_sd>;
435 status = "okay";
436};
437
438&spi0 {
439 pinctrl-names = "default";
440 pinctrl-0 = <&spi0_clk>, <&spi0_cs0>, <&spi0_tx>, <&spi0_rx>, <&spi0_cs1>;
441 status = "okay";
442};
443
444&uart0 {
445 pinctrl-names = "default";
446 pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>;
447 status = "okay";
448};
449
450&uart1 {
451 status = "okay";
452};
453
454&uart2 {
455 status = "okay";
456};
457
458&uart3 {
459 status = "okay";
460};
461
462&usb_host1 {
463 pinctrl-names = "default";
464 pinctrl-0 = <&usbhub_rst>;
465 status = "okay";
466};
467
468&usb_otg {
469 status = "okay";
470};
471
472&vopb {
473 status = "okay";
474};
475
476&vopb_mmu {
477 status = "okay";
478};
479
480&vopl {
481 status = "okay";
482};
483
484&vopl_mmu {
485 status = "okay";
486};
487
488&wdt {
489 status = "okay";
490};
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 910dcad2088a..d771f687a13b 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -149,8 +149,22 @@
149 clock-frequency = <24000000>; 149 clock-frequency = <24000000>;
150 }; 150 };
151 151
152 timer: timer@ff810000 {
153 compatible = "rockchip,rk3288-timer";
154 reg = <0xff810000 0x20>;
155 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
156 clocks = <&xin24m>, <&cru PCLK_TIMER>;
157 clock-names = "timer", "pclk";
158 };
159
160 display-subsystem {
161 compatible = "rockchip,display-subsystem";
162 ports = <&vopl_out>, <&vopb_out>;
163 };
164
152 sdmmc: dwmmc@ff0c0000 { 165 sdmmc: dwmmc@ff0c0000 {
153 compatible = "rockchip,rk3288-dw-mshc"; 166 compatible = "rockchip,rk3288-dw-mshc";
167 clock-freq-min-max = <400000 150000000>;
154 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 168 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
155 clock-names = "biu", "ciu"; 169 clock-names = "biu", "ciu";
156 fifo-depth = <0x100>; 170 fifo-depth = <0x100>;
@@ -161,6 +175,7 @@
161 175
162 sdio0: dwmmc@ff0d0000 { 176 sdio0: dwmmc@ff0d0000 {
163 compatible = "rockchip,rk3288-dw-mshc"; 177 compatible = "rockchip,rk3288-dw-mshc";
178 clock-freq-min-max = <400000 150000000>;
164 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>; 179 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
165 clock-names = "biu", "ciu"; 180 clock-names = "biu", "ciu";
166 fifo-depth = <0x100>; 181 fifo-depth = <0x100>;
@@ -171,6 +186,7 @@
171 186
172 sdio1: dwmmc@ff0e0000 { 187 sdio1: dwmmc@ff0e0000 {
173 compatible = "rockchip,rk3288-dw-mshc"; 188 compatible = "rockchip,rk3288-dw-mshc";
189 clock-freq-min-max = <400000 150000000>;
174 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>; 190 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
175 clock-names = "biu", "ciu"; 191 clock-names = "biu", "ciu";
176 fifo-depth = <0x100>; 192 fifo-depth = <0x100>;
@@ -181,6 +197,7 @@
181 197
182 emmc: dwmmc@ff0f0000 { 198 emmc: dwmmc@ff0f0000 {
183 compatible = "rockchip,rk3288-dw-mshc"; 199 compatible = "rockchip,rk3288-dw-mshc";
200 clock-freq-min-max = <400000 150000000>;
184 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; 201 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
185 clock-names = "biu", "ciu"; 202 clock-names = "biu", "ciu";
186 fifo-depth = <0x100>; 203 fifo-depth = <0x100>;
@@ -518,6 +535,11 @@
518 }; 535 };
519 }; 536 };
520 537
538 sram@ff720000 {
539 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
540 reg = <0xff720000 0x1000>;
541 };
542
521 pmu: power-management@ff730000 { 543 pmu: power-management@ff730000 {
522 compatible = "rockchip,rk3288-pmu", "syscon"; 544 compatible = "rockchip,rk3288-pmu", "syscon";
523 reg = <0xff730000 0x100>; 545 reg = <0xff730000 0x100>;
@@ -554,6 +576,7 @@
554 wdt: watchdog@ff800000 { 576 wdt: watchdog@ff800000 {
555 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; 577 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
556 reg = <0xff800000 0x100>; 578 reg = <0xff800000 0x100>;
579 clocks = <&cru PCLK_WDT>;
557 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 580 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
558 status = "disabled"; 581 status = "disabled";
559 }; 582 };
@@ -573,6 +596,28 @@
573 status = "disabled"; 596 status = "disabled";
574 }; 597 };
575 598
599 vopb: vop@ff930000 {
600 compatible = "rockchip,rk3288-vop";
601 reg = <0xff930000 0x19c>;
602 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
604 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
605 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
606 reset-names = "axi", "ahb", "dclk";
607 iommus = <&vopb_mmu>;
608 status = "disabled";
609
610 vopb_out: port {
611 #address-cells = <1>;
612 #size-cells = <0>;
613
614 vopb_out_hdmi: endpoint@0 {
615 reg = <0>;
616 remote-endpoint = <&hdmi_in_vopb>;
617 };
618 };
619 };
620
576 vopb_mmu: iommu@ff930300 { 621 vopb_mmu: iommu@ff930300 {
577 compatible = "rockchip,iommu"; 622 compatible = "rockchip,iommu";
578 reg = <0xff930300 0x100>; 623 reg = <0xff930300 0x100>;
@@ -582,6 +627,28 @@
582 status = "disabled"; 627 status = "disabled";
583 }; 628 };
584 629
630 vopl: vop@ff940000 {
631 compatible = "rockchip,rk3288-vop";
632 reg = <0xff940000 0x19c>;
633 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
635 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
636 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
637 reset-names = "axi", "ahb", "dclk";
638 iommus = <&vopl_mmu>;
639 status = "disabled";
640
641 vopl_out: port {
642 #address-cells = <1>;
643 #size-cells = <0>;
644
645 vopl_out_hdmi: endpoint@0 {
646 reg = <0>;
647 remote-endpoint = <&hdmi_in_vopl>;
648 };
649 };
650 };
651
585 vopl_mmu: iommu@ff940300 { 652 vopl_mmu: iommu@ff940300 {
586 compatible = "rockchip,iommu"; 653 compatible = "rockchip,iommu";
587 reg = <0xff940300 0x100>; 654 reg = <0xff940300 0x100>;
@@ -591,6 +658,32 @@
591 status = "disabled"; 658 status = "disabled";
592 }; 659 };
593 660
661 hdmi: hdmi@ff980000 {
662 compatible = "rockchip,rk3288-dw-hdmi";
663 reg = <0xff980000 0x20000>;
664 reg-io-width = <4>;
665 rockchip,grf = <&grf>;
666 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
667 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
668 clock-names = "iahb", "isfr";
669 status = "disabled";
670
671 ports {
672 hdmi_in: port {
673 #address-cells = <1>;
674 #size-cells = <0>;
675 hdmi_in_vopb: endpoint@0 {
676 reg = <0>;
677 remote-endpoint = <&vopb_out_hdmi>;
678 };
679 hdmi_in_vopl: endpoint@1 {
680 reg = <1>;
681 remote-endpoint = <&vopl_out_hdmi>;
682 };
683 };
684 };
685 };
686
594 gic: interrupt-controller@ffc01000 { 687 gic: interrupt-controller@ffc01000 {
595 compatible = "arm,gic-400"; 688 compatible = "arm,gic-400";
596 interrupt-controller; 689 interrupt-controller;
@@ -746,6 +839,24 @@
746 drive-strength = <12>; 839 drive-strength = <12>;
747 }; 840 };
748 841
842 sleep {
843 global_pwroff: global-pwroff {
844 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
845 };
846
847 ddrio_pwroff: ddrio-pwroff {
848 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
849 };
850
851 ddr0_retention: ddr0-retention {
852 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
853 };
854
855 ddr1_retention: ddr1-retention {
856 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
857 };
858 };
859
749 i2c0 { 860 i2c0 {
750 i2c0_xfer: i2c0-xfer { 861 i2c0_xfer: i2c0-xfer {
751 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>, 862 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
diff --git a/arch/arm/boot/dts/s5pv210-aquila.dts b/arch/arm/boot/dts/s5pv210-aquila.dts
index aa31b84a707a..f00cea7aca2f 100644
--- a/arch/arm/boot/dts/s5pv210-aquila.dts
+++ b/arch/arm/boot/dts/s5pv210-aquila.dts
@@ -355,6 +355,7 @@
355&hsotg { 355&hsotg {
356 vusb_a-supply = <&ldo3_reg>; 356 vusb_a-supply = <&ldo3_reg>;
357 vusb_d-supply = <&ldo8_reg>; 357 vusb_d-supply = <&ldo8_reg>;
358 dr_mode = "peripheral";
358 status = "okay"; 359 status = "okay";
359}; 360};
360 361
diff --git a/arch/arm/boot/dts/s5pv210-goni.dts b/arch/arm/boot/dts/s5pv210-goni.dts
index 6387c77a6f7b..a3d4643b202e 100644
--- a/arch/arm/boot/dts/s5pv210-goni.dts
+++ b/arch/arm/boot/dts/s5pv210-goni.dts
@@ -333,6 +333,7 @@
333&hsotg { 333&hsotg {
334 vusb_a-supply = <&ldo3_reg>; 334 vusb_a-supply = <&ldo3_reg>;
335 vusb_d-supply = <&ldo8_reg>; 335 vusb_d-supply = <&ldo8_reg>;
336 dr_mode = "peripheral";
336 status = "okay"; 337 status = "okay";
337}; 338};
338 339
diff --git a/arch/arm/boot/dts/s5pv210-smdkv210.dts b/arch/arm/boot/dts/s5pv210-smdkv210.dts
index cb8521899ec8..da7d210df670 100644
--- a/arch/arm/boot/dts/s5pv210-smdkv210.dts
+++ b/arch/arm/boot/dts/s5pv210-smdkv210.dts
@@ -181,6 +181,7 @@
181}; 181};
182 182
183&hsotg { 183&hsotg {
184 dr_mode = "peripheral";
184 status = "okay"; 185 status = "okay";
185}; 186};
186 187
diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi
index be2ccc53abb5..83bee7a3a617 100644
--- a/arch/arm/boot/dts/sama5d3xmb.dtsi
+++ b/arch/arm/boot/dts/sama5d3xmb.dtsi
@@ -45,7 +45,7 @@
45 */ 45 */
46 i2c0: i2c@f0014000 { 46 i2c0: i2c@f0014000 {
47 wm8904: wm8904@1a { 47 wm8904: wm8904@1a {
48 compatible = "wm8904"; 48 compatible = "wlf,wm8904";
49 reg = <0x1a>; 49 reg = <0x1a>;
50 clocks = <&pck0>; 50 clocks = <&pck0>;
51 clock-names = "mclk"; 51 clock-names = "mclk";
diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
index 2a31d66164ac..d986b41b9654 100644
--- a/arch/arm/boot/dts/sama5d4.dtsi
+++ b/arch/arm/boot/dts/sama5d4.dtsi
@@ -62,6 +62,7 @@
62 gpio0 = &pioA; 62 gpio0 = &pioA;
63 gpio1 = &pioB; 63 gpio1 = &pioB;
64 gpio2 = &pioC; 64 gpio2 = &pioC;
65 gpio3 = &pioD;
65 gpio4 = &pioE; 66 gpio4 = &pioE;
66 tcb0 = &tcb0; 67 tcb0 = &tcb0;
67 tcb1 = &tcb1; 68 tcb1 = &tcb1;
@@ -272,7 +273,7 @@
272 }; 273 };
273 274
274 nand0: nand@80000000 { 275 nand0: nand@80000000 {
275 compatible = "atmel,at91rm9200-nand"; 276 compatible = "atmel,sama5d4-nand", "atmel,at91rm9200-nand";
276 #address-cells = <1>; 277 #address-cells = <1>;
277 #size-cells = <1>; 278 #size-cells = <1>;
278 ranges; 279 ranges;
@@ -1121,6 +1122,18 @@
1121 clocks = <&pioC_clk>; 1122 clocks = <&pioC_clk>;
1122 }; 1123 };
1123 1124
1125 pioD: gpio@fc068000 {
1126 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1127 reg = <0xfc068000 0x100>;
1128 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
1129 #gpio-cells = <2>;
1130 gpio-controller;
1131 interrupt-controller;
1132 #interrupt-cells = <2>;
1133 clocks = <&pioD_clk>;
1134 status = "disabled";
1135 };
1136
1124 pioE: gpio@fc06d000 { 1137 pioE: gpio@fc06d000 {
1125 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 1138 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1126 reg = <0xfc06d000 0x100>; 1139 reg = <0xfc06d000 0x100>;
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
index 939be1299ca6..863dc4c7d7f6 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
@@ -179,7 +179,7 @@
179}; 179};
180 180
181&cmt1 { 181&cmt1 {
182 status = "ok"; 182 status = "okay";
183}; 183};
184 184
185&i2c0 { 185&i2c0 {
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index d8def5a529da..37c8a761aeab 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -42,6 +42,22 @@
42 <0xf0000100 0x100>; 42 <0xf0000100 0x100>;
43 }; 43 };
44 44
45 sbsc2: memory-controller@fb400000 {
46 compatible = "renesas,sbsc-sh73a0";
47 reg = <0xfb400000 0x400>;
48 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>,
49 <0 38 IRQ_TYPE_LEVEL_HIGH>;
50 interrupt-names = "sec", "temp";
51 };
52
53 sbsc1: memory-controller@fe400000 {
54 compatible = "renesas,sbsc-sh73a0";
55 reg = <0xfe400000 0x400>;
56 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>,
57 <0 36 IRQ_TYPE_LEVEL_HIGH>;
58 interrupt-names = "sec", "temp";
59 };
60
45 pmu { 61 pmu {
46 compatible = "arm,cortex-a9-pmu"; 62 compatible = "arm,cortex-a9-pmu";
47 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>, 63 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>,
@@ -317,7 +333,7 @@
317 333
318 sh_fsi2: sound@ec230000 { 334 sh_fsi2: sound@ec230000 {
319 #sound-dai-cells = <1>; 335 #sound-dai-cells = <1>;
320 compatible = "renesas,sh_fsi2"; 336 compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
321 reg = <0xec230000 0x400>; 337 reg = <0xec230000 0x400>;
322 interrupts = <0 146 0x4>; 338 interrupts = <0 146 0x4>;
323 status = "disabled"; 339 status = "disabled";
diff --git a/arch/arm/boot/dts/stih407-b2120.dts b/arch/arm/boot/dts/stih407-b2120.dts
index 261d5e2c48d2..af487145cd89 100644
--- a/arch/arm/boot/dts/stih407-b2120.dts
+++ b/arch/arm/boot/dts/stih407-b2120.dts
@@ -7,9 +7,8 @@
7 * published by the Free Software Foundation. 7 * published by the Free Software Foundation.
8 */ 8 */
9/dts-v1/; 9/dts-v1/;
10#include "stih407-clock.dtsi"
11#include "stih407-family.dtsi"
12#include "stihxxx-b2120.dtsi" 10#include "stihxxx-b2120.dtsi"
11#include "stih407.dtsi"
13/ { 12/ {
14 model = "STiH407 B2120"; 13 model = "STiH407 B2120";
15 compatible = "st,stih407-b2120", "st,stih407"; 14 compatible = "st,stih407-b2120", "st,stih407";
diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
index d4a8f843cdc8..c06a54681912 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -283,5 +283,58 @@
283 <&picophyreset STIH407_PICOPHY0_RESET>; 283 <&picophyreset STIH407_PICOPHY0_RESET>;
284 reset-names = "global", "port"; 284 reset-names = "global", "port";
285 }; 285 };
286
287 miphy28lp_phy: miphy28lp@9b22000 {
288 compatible = "st,miphy28lp-phy";
289 st,syscfg = <&syscfg_core>;
290 #address-cells = <1>;
291 #size-cells = <1>;
292 ranges;
293
294 phy_port0: port@9b22000 {
295 reg = <0x9b22000 0xff>,
296 <0x9b09000 0xff>,
297 <0x9b04000 0xff>;
298 reg-names = "sata-up",
299 "pcie-up",
300 "pipew";
301
302 st,syscfg = <0x114 0x818 0xe0 0xec>;
303 #phy-cells = <1>;
304
305 reset-names = "miphy-sw-rst";
306 resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
307 };
308
309 phy_port1: port@9b2a000 {
310 reg = <0x9b2a000 0xff>,
311 <0x9b19000 0xff>,
312 <0x9b14000 0xff>;
313 reg-names = "sata-up",
314 "pcie-up",
315 "pipew";
316
317 st,syscfg = <0x118 0x81c 0xe4 0xf0>;
318
319 #phy-cells = <1>;
320
321 reset-names = "miphy-sw-rst";
322 resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
323 };
324
325 phy_port2: port@8f95000 {
326 reg = <0x8f95000 0xff>,
327 <0x8f90000 0xff>;
328 reg-names = "pipew",
329 "usb3-up";
330
331 st,syscfg = <0x11c 0x820>;
332
333 #phy-cells = <1>;
334
335 reset-names = "miphy-sw-rst";
336 resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
337 };
338 };
286 }; 339 };
287}; 340};
diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi
new file mode 100644
index 000000000000..3efa3b2ebe90
--- /dev/null
+++ b/arch/arm/boot/dts/stih407.dtsi
@@ -0,0 +1,151 @@
1/*
2 * Copyright (C) 2015 STMicroelectronics Limited.
3 * Author: Gabriel Fernandez <gabriel.fernandez@linaro.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9#include "stih407-clock.dtsi"
10#include "stih407-family.dtsi"
11/ {
12 soc {
13 /* Display */
14 vtg_main: sti-vtg-main@8d02800 {
15 compatible = "st,vtg";
16 reg = <0x8d02800 0x200>;
17 interrupts = <GIC_SPI 108 IRQ_TYPE_NONE>;
18 };
19
20 vtg_aux: sti-vtg-aux@8d00200 {
21 compatible = "st,vtg";
22 reg = <0x8d00200 0x100>;
23 interrupts = <GIC_SPI 109 IRQ_TYPE_NONE>;
24 };
25
26 sti-display-subsystem {
27 compatible = "st,sti-display-subsystem";
28 #address-cells = <1>;
29 #size-cells = <1>;
30
31 assigned-clocks = <&clk_s_d2_quadfs 0>,
32 <&clk_s_d2_quadfs 0>,
33 <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
34 <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
35 <&clk_s_d2_flexgen CLK_PIX_GDP1>,
36 <&clk_s_d2_flexgen CLK_PIX_GDP2>,
37 <&clk_s_d2_flexgen CLK_PIX_GDP3>,
38 <&clk_s_d2_flexgen CLK_PIX_GDP4>;
39
40 assigned-clock-parents = <0>,
41 <0>,
42 <&clk_s_d2_quadfs 0>,
43 <&clk_s_d2_quadfs 0>,
44 <&clk_s_d2_quadfs 0>,
45 <&clk_s_d2_quadfs 0>,
46 <&clk_s_d2_quadfs 0>,
47 <&clk_s_d2_quadfs 0>;
48
49 assigned-clock-rates = <297000000>, <297000000>;
50
51 ranges;
52
53 sti-compositor@9d11000 {
54 compatible = "st,stih407-compositor";
55 reg = <0x9d11000 0x1000>;
56
57 clock-names = "compo_main",
58 "compo_aux",
59 "pix_main",
60 "pix_aux",
61 "pix_gdp1",
62 "pix_gdp2",
63 "pix_gdp3",
64 "pix_gdp4",
65 "main_parent",
66 "aux_parent";
67
68 clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
69 <&clk_s_c0_flexgen CLK_COMPO_DVP>,
70 <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
71 <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
72 <&clk_s_d2_flexgen CLK_PIX_GDP1>,
73 <&clk_s_d2_flexgen CLK_PIX_GDP2>,
74 <&clk_s_d2_flexgen CLK_PIX_GDP3>,
75 <&clk_s_d2_flexgen CLK_PIX_GDP4>,
76 <&clk_s_d2_quadfs 0>,
77 <&clk_s_d2_quadfs 1>;
78
79 reset-names = "compo-main", "compo-aux";
80 resets = <&softreset STIH407_COMPO_SOFTRESET>,
81 <&softreset STIH407_COMPO_SOFTRESET>;
82 st,vtg = <&vtg_main>, <&vtg_aux>;
83 };
84
85 sti-tvout@8d08000 {
86 compatible = "st,stih407-tvout";
87 reg = <0x8d08000 0x1000>;
88 reg-names = "tvout-reg";
89 reset-names = "tvout";
90 resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
91 #address-cells = <1>;
92 #size-cells = <1>;
93 assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
94 <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
95 <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
96 <&clk_s_d0_flexgen CLK_PCM_0>,
97 <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
98 <&clk_s_d2_flexgen CLK_HDDAC>;
99
100 assigned-clock-parents = <&clk_s_d2_quadfs 0>,
101 <&clk_tmdsout_hdmi>,
102 <&clk_s_d2_quadfs 0>,
103 <&clk_s_d0_quadfs 0>,
104 <&clk_s_d2_quadfs 0>,
105 <&clk_s_d2_quadfs 0>;
106 ranges;
107
108 sti-hdmi@8d04000 {
109 compatible = "st,stih407-hdmi";
110 reg = <0x8d04000 0x1000>;
111 reg-names = "hdmi-reg";
112 interrupts = <GIC_SPI 106 IRQ_TYPE_NONE>;
113 interrupt-names = "irq";
114 clock-names = "pix",
115 "tmds",
116 "phy",
117 "audio",
118 "main_parent",
119 "aux_parent";
120
121 clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
122 <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
123 <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
124 <&clk_s_d0_flexgen CLK_PCM_0>,
125 <&clk_s_d2_quadfs 0>,
126 <&clk_s_d2_quadfs 1>;
127
128 hdmi,hpd-gpio = <&pio5 3>;
129 reset-names = "hdmi";
130 resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
131 ddc = <&hdmiddc>;
132
133 };
134
135 sti-hda@8d02000 {
136 compatible = "st,stih407-hda";
137 reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
138 reg-names = "hda-reg", "video-dacs-ctrl";
139 clock-names = "pix",
140 "hddac",
141 "main_parent",
142 "aux_parent";
143 clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
144 <&clk_s_d2_flexgen CLK_HDDAC>,
145 <&clk_s_d2_quadfs 0>,
146 <&clk_s_d2_quadfs 1>;
147 };
148 };
149 };
150 };
151};
diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi
index 37995f4739d2..208b5e89036a 100644
--- a/arch/arm/boot/dts/stih410.dtsi
+++ b/arch/arm/boot/dts/stih410.dtsi
@@ -80,5 +80,143 @@
80 phys = <&usb2_picophy2>; 80 phys = <&usb2_picophy2>;
81 phy-names = "usb"; 81 phy-names = "usb";
82 }; 82 };
83
84 /* Display */
85 vtg_main: sti-vtg-main@8d02800 {
86 compatible = "st,vtg";
87 reg = <0x8d02800 0x200>;
88 interrupts = <GIC_SPI 108 IRQ_TYPE_NONE>;
89 };
90
91 vtg_aux: sti-vtg-aux@8d00200 {
92 compatible = "st,vtg";
93 reg = <0x8d00200 0x100>;
94 interrupts = <GIC_SPI 109 IRQ_TYPE_NONE>;
95 };
96
97 sti-display-subsystem {
98 compatible = "st,sti-display-subsystem";
99 #address-cells = <1>;
100 #size-cells = <1>;
101
102 assigned-clocks = <&clk_s_d2_quadfs 0>,
103 <&clk_s_d2_quadfs 0>,
104 <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
105 <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
106 <&clk_s_d2_flexgen CLK_PIX_GDP1>,
107 <&clk_s_d2_flexgen CLK_PIX_GDP2>,
108 <&clk_s_d2_flexgen CLK_PIX_GDP3>,
109 <&clk_s_d2_flexgen CLK_PIX_GDP4>;
110
111 assigned-clock-parents = <0>,
112 <0>,
113 <&clk_s_d2_quadfs 0>,
114 <&clk_s_d2_quadfs 0>,
115 <&clk_s_d2_quadfs 0>,
116 <&clk_s_d2_quadfs 0>,
117 <&clk_s_d2_quadfs 0>,
118 <&clk_s_d2_quadfs 0>;
119
120 assigned-clock-rates = <297000000>, <297000000>;
121
122 ranges;
123
124 sti-compositor@9d11000 {
125 compatible = "st,stih407-compositor";
126 reg = <0x9d11000 0x1000>;
127
128 clock-names = "compo_main",
129 "compo_aux",
130 "pix_main",
131 "pix_aux",
132 "pix_gdp1",
133 "pix_gdp2",
134 "pix_gdp3",
135 "pix_gdp4",
136 "main_parent",
137 "aux_parent";
138
139 clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
140 <&clk_s_c0_flexgen CLK_COMPO_DVP>,
141 <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
142 <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
143 <&clk_s_d2_flexgen CLK_PIX_GDP1>,
144 <&clk_s_d2_flexgen CLK_PIX_GDP2>,
145 <&clk_s_d2_flexgen CLK_PIX_GDP3>,
146 <&clk_s_d2_flexgen CLK_PIX_GDP4>,
147 <&clk_s_d2_quadfs 0>,
148 <&clk_s_d2_quadfs 1>;
149
150 reset-names = "compo-main", "compo-aux";
151 resets = <&softreset STIH407_COMPO_SOFTRESET>,
152 <&softreset STIH407_COMPO_SOFTRESET>;
153 st,vtg = <&vtg_main>, <&vtg_aux>;
154 };
155
156 sti-tvout@8d08000 {
157 compatible = "st,stih407-tvout";
158 reg = <0x8d08000 0x1000>;
159 reg-names = "tvout-reg";
160 reset-names = "tvout";
161 resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
162 #address-cells = <1>;
163 #size-cells = <1>;
164 assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
165 <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
166 <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
167 <&clk_s_d0_flexgen CLK_PCM_0>,
168 <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
169 <&clk_s_d2_flexgen CLK_HDDAC>;
170
171 assigned-clock-parents = <&clk_s_d2_quadfs 0>,
172 <&clk_tmdsout_hdmi>,
173 <&clk_s_d2_quadfs 0>,
174 <&clk_s_d0_quadfs 0>,
175 <&clk_s_d2_quadfs 0>,
176 <&clk_s_d2_quadfs 0>;
177 ranges;
178
179 sti-hdmi@8d04000 {
180 compatible = "st,stih407-hdmi";
181 reg = <0x8d04000 0x1000>;
182 reg-names = "hdmi-reg";
183 interrupts = <GIC_SPI 106 IRQ_TYPE_NONE>;
184 interrupt-names = "irq";
185 clock-names = "pix",
186 "tmds",
187 "phy",
188 "audio",
189 "main_parent",
190 "aux_parent";
191
192 clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
193 <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
194 <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
195 <&clk_s_d0_flexgen CLK_PCM_0>,
196 <&clk_s_d2_quadfs 0>,
197 <&clk_s_d2_quadfs 1>;
198
199 hdmi,hpd-gpio = <&pio5 3>;
200 reset-names = "hdmi";
201 resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
202 ddc = <&hdmiddc>;
203
204 };
205
206 sti-hda@8d02000 {
207 compatible = "st,stih407-hda";
208 reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
209 reg-names = "hda-reg", "video-dacs-ctrl";
210 clock-names = "pix",
211 "hddac",
212 "main_parent",
213 "aux_parent";
214 clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
215 <&clk_s_d2_flexgen CLK_HDDAC>,
216 <&clk_s_d2_quadfs 0>,
217 <&clk_s_d2_quadfs 1>;
218 };
219 };
220 };
83 }; 221 };
84}; 222};
diff --git a/arch/arm/boot/dts/stih418-b2199.dts b/arch/arm/boot/dts/stih418-b2199.dts
new file mode 100644
index 000000000000..926235c08e4d
--- /dev/null
+++ b/arch/arm/boot/dts/stih418-b2199.dts
@@ -0,0 +1,78 @@
1/*
2 * Copyright (C) 2015 STMicroelectronics (R&D) Limited.
3 * Author: Maxime Coquelin <maxime.coquelin@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9/dts-v1/;
10#include "stih418.dtsi"
11/ {
12 model = "STiH418 B2199";
13 compatible = "st,stih418-b2199", "st,stih418";
14
15 chosen {
16 bootargs = "console=ttyAS0,115200 clk_ignore_unused";
17 linux,stdout-path = &sbc_serial0;
18 };
19
20 memory {
21 device_type = "memory";
22 reg = <0x40000000 0xc0000000>;
23 };
24
25 aliases {
26 ttyAS0 = &sbc_serial0;
27 };
28
29 soc {
30 sbc_serial0: serial@9530000 {
31 status = "okay";
32 };
33
34 leds {
35 compatible = "gpio-leds";
36 red {
37 #gpio-cells = <2>;
38 label = "Front Panel LED";
39 gpios = <&pio4 1 0>;
40 linux,default-trigger = "heartbeat";
41 };
42 green {
43 #gpio-cells = <2>;
44 gpios = <&pio1 3 0>;
45 default-state = "off";
46 };
47 };
48
49 i2c@9842000 {
50 status = "okay";
51 };
52
53 i2c@9843000 {
54 status = "okay";
55 };
56
57 i2c@9844000 {
58 status = "okay";
59 };
60
61 i2c@9845000 {
62 status = "okay";
63 };
64
65 i2c@9540000 {
66 status = "okay";
67 };
68
69 /* SSC11 to HDMI */
70 i2c@9541000 {
71 status = "okay";
72 /* HDMI V1.3a supports Standard mode only */
73 clock-frequency = <100000>;
74 st,i2c-min-scl-pulse-width-us = <0>;
75 st,i2c-min-sda-pulse-width-us = <5>;
76 };
77 };
78};
diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi
new file mode 100644
index 000000000000..0ab23daa2829
--- /dev/null
+++ b/arch/arm/boot/dts/stih418-clock.dtsi
@@ -0,0 +1,348 @@
1/*
2 * Copyright (C) 2015 STMicroelectronics R&D Limited
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8#include <dt-bindings/clock/stih418-clks.h>
9/ {
10 clocks {
11 #address-cells = <1>;
12 #size-cells = <1>;
13 ranges;
14
15 compatible = "st,stih418-clk", "simple-bus";
16
17 /*
18 * Fixed 30MHz oscillator inputs to SoC
19 */
20 clk_sysin: clk-sysin {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <30000000>;
24 clock-output-names = "CLK_SYSIN";
25 };
26
27 /*
28 * ARM Peripheral clock for timers
29 */
30 arm_periph_clk: clk-m-a9-periphs {
31 #clock-cells = <0>;
32 compatible = "fixed-factor-clock";
33 clocks = <&clk_m_a9>;
34 clock-div = <2>;
35 clock-mult = <1>;
36 };
37
38 /*
39 * A9 PLL.
40 */
41 clockgen-a9@92b0000 {
42 compatible = "st,clkgen-c32";
43 reg = <0x92b0000 0xffff>;
44
45 clockgen_a9_pll: clockgen-a9-pll {
46 #clock-cells = <1>;
47 compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32";
48
49 clocks = <&clk_sysin>;
50
51 clock-output-names = "clockgen-a9-pll-odf";
52 };
53 };
54
55 /*
56 * ARM CPU related clocks.
57 */
58 clk_m_a9: clk-m-a9@92b0000 {
59 #clock-cells = <0>;
60 compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
61 reg = <0x92b0000 0x10000>;
62
63 clocks = <&clockgen_a9_pll 0>,
64 <&clockgen_a9_pll 0>,
65 <&clk_s_c0_flexgen 13>,
66 <&clk_m_a9_ext2f_div2>;
67 };
68
69 /*
70 * ARM Peripheral clock for timers
71 */
72 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
73 #clock-cells = <0>;
74 compatible = "fixed-factor-clock";
75
76 clocks = <&clk_s_c0_flexgen 13>;
77
78 clock-output-names = "clk-m-a9-ext2f-div2";
79
80 clock-div = <2>;
81 clock-mult = <1>;
82 };
83
84 /*
85 * Bootloader initialized system infrastructure clock for
86 * serial devices.
87 */
88 clk_ext2f_a9: clockgen-c0@13 {
89 #clock-cells = <0>;
90 compatible = "fixed-clock";
91 clock-frequency = <200000000>;
92 clock-output-names = "clk-s-icn-reg-0";
93 };
94
95 clockgen-a@090ff000 {
96 compatible = "st,clkgen-c32";
97 reg = <0x90ff000 0x1000>;
98
99 clk_s_a0_pll: clk-s-a0-pll {
100 #clock-cells = <1>;
101 compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32";
102
103 clocks = <&clk_sysin>;
104
105 clock-output-names = "clk-s-a0-pll-ofd-0";
106 };
107
108 clk_s_a0_flexgen: clk-s-a0-flexgen {
109 compatible = "st,flexgen";
110
111 #clock-cells = <1>;
112
113 clocks = <&clk_s_a0_pll 0>,
114 <&clk_sysin>;
115
116 clock-output-names = "clk-ic-lmi0",
117 "clk-ic-lmi1";
118 };
119 };
120
121 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
122 #clock-cells = <1>;
123 compatible = "st,stih407-quadfs660-C", "st,quadfs";
124 reg = <0x9103000 0x1000>;
125
126 clocks = <&clk_sysin>;
127
128 clock-output-names = "clk-s-c0-fs0-ch0",
129 "clk-s-c0-fs0-ch1",
130 "clk-s-c0-fs0-ch2",
131 "clk-s-c0-fs0-ch3";
132 };
133
134 clk_s_c0: clockgen-c@09103000 {
135 compatible = "st,clkgen-c32";
136 reg = <0x9103000 0x1000>;
137
138 clk_s_c0_pll0: clk-s-c0-pll0 {
139 #clock-cells = <1>;
140 compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";
141
142 clocks = <&clk_sysin>;
143
144 clock-output-names = "clk-s-c0-pll0-odf-0";
145 };
146
147 clk_s_c0_pll1: clk-s-c0-pll1 {
148 #clock-cells = <1>;
149 compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";
150
151 clocks = <&clk_sysin>;
152
153 clock-output-names = "clk-s-c0-pll1-odf-0";
154 };
155
156 clk_s_c0_flexgen: clk-s-c0-flexgen {
157 #clock-cells = <1>;
158 compatible = "st,flexgen";
159
160 clocks = <&clk_s_c0_pll0 0>,
161 <&clk_s_c0_pll1 0>,
162 <&clk_s_c0_quadfs 0>,
163 <&clk_s_c0_quadfs 1>,
164 <&clk_s_c0_quadfs 2>,
165 <&clk_s_c0_quadfs 3>,
166 <&clk_sysin>;
167
168 clock-output-names = "clk-icn-gpu",
169 "clk-fdma",
170 "clk-nand",
171 "clk-hva",
172 "clk-proc-stfe",
173 "clk-tp",
174 "clk-rx-icn-dmu",
175 "clk-rx-icn-hva",
176 "clk-icn-cpu",
177 "clk-tx-icn-dmu",
178 "clk-mmc-0",
179 "clk-mmc-1",
180 "clk-jpegdec",
181 "clk-icn-reg",
182 "clk-proc-bdisp-0",
183 "clk-proc-bdisp-1",
184 "clk-pp-dmu",
185 "clk-vid-dmu",
186 "clk-dss-lpc",
187 "clk-st231-aud-0",
188 "clk-st231-gp-1",
189 "clk-st231-dmu",
190 "clk-icn-lmi",
191 "clk-tx-icn-1",
192 "clk-icn-sbc",
193 "clk-stfe-frc2",
194 "clk-eth-phyref",
195 "clk-eth-ref-phyclk",
196 "clk-flash-promip",
197 "clk-main-disp",
198 "clk-aux-disp",
199 "clk-compo-dvp",
200 "clk-tx-icn-hades",
201 "clk-rx-icn-hades",
202 "clk-icn-reg-16",
203 "clk-pp-hevc",
204 "clk-clust-hevc",
205 "clk-hwpe-hevc",
206 "clk-fc-hevc",
207 "clk-proc-mixer",
208 "clk-proc-sc",
209 "clk-avsp-hevc";
210 };
211 };
212
213 clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
214 #clock-cells = <1>;
215 compatible = "st,stih407-quadfs660-D", "st,quadfs";
216 reg = <0x9104000 0x1000>;
217
218 clocks = <&clk_sysin>;
219
220 clock-output-names = "clk-s-d0-fs0-ch0",
221 "clk-s-d0-fs0-ch1",
222 "clk-s-d0-fs0-ch2",
223 "clk-s-d0-fs0-ch3";
224 };
225
226 clockgen-d0@09104000 {
227 compatible = "st,clkgen-c32";
228 reg = <0x9104000 0x1000>;
229
230 clk_s_d0_flexgen: clk-s-d0-flexgen {
231 #clock-cells = <1>;
232 compatible = "st,flexgen";
233
234 clocks = <&clk_s_d0_quadfs 0>,
235 <&clk_s_d0_quadfs 1>,
236 <&clk_s_d0_quadfs 2>,
237 <&clk_s_d0_quadfs 3>,
238 <&clk_sysin>;
239
240 clock-output-names = "clk-pcm-0",
241 "clk-pcm-1",
242 "clk-pcm-2",
243 "clk-spdiff",
244 "clk-pcmr10-master",
245 "clk-usb2-phy";
246 };
247 };
248
249 clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
250 #clock-cells = <1>;
251 compatible = "st,stih407-quadfs660-D", "st,quadfs";
252 reg = <0x9106000 0x1000>;
253
254 clocks = <&clk_sysin>;
255
256 clock-output-names = "clk-s-d2-fs0-ch0",
257 "clk-s-d2-fs0-ch1",
258 "clk-s-d2-fs0-ch2",
259 "clk-s-d2-fs0-ch3";
260 };
261
262 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
263 #clock-cells = <0>;
264 compatible = "fixed-clock";
265 clock-frequency = <0>;
266 };
267
268 clockgen-d2@x9106000 {
269 compatible = "st,clkgen-c32";
270 reg = <0x9106000 0x1000>;
271
272 clk_s_d2_flexgen: clk-s-d2-flexgen {
273 #clock-cells = <1>;
274 compatible = "st,flexgen";
275
276 clocks = <&clk_s_d2_quadfs 0>,
277 <&clk_s_d2_quadfs 1>,
278 <&clk_s_d2_quadfs 2>,
279 <&clk_s_d2_quadfs 3>,
280 <&clk_sysin>,
281 <&clk_sysin>,
282 <&clk_tmdsout_hdmi>;
283
284 clock-output-names = "clk-pix-main-disp",
285 "",
286 "",
287 "",
288 "",
289 "clk-tmds-hdmi-div2",
290 "clk-pix-aux-disp",
291 "clk-denc",
292 "clk-pix-hddac",
293 "clk-hddac",
294 "clk-sddac",
295 "clk-pix-dvo",
296 "clk-dvo",
297 "clk-pix-hdmi",
298 "clk-tmds-hdmi",
299 "clk-ref-hdmiphy",
300 "", "", "", "", "",
301 "", "", "", "", "",
302 "", "", "", "", "",
303 "", "", "", "", "",
304 "", "", "", "", "",
305 "", "", "", "", "",
306 "", "clk-vp9";
307 };
308 };
309
310 clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
311 #clock-cells = <1>;
312 compatible = "st,stih407-quadfs660-D", "st,quadfs";
313 reg = <0x9107000 0x1000>;
314
315 clocks = <&clk_sysin>;
316
317 clock-output-names = "clk-s-d3-fs0-ch0",
318 "clk-s-d3-fs0-ch1",
319 "clk-s-d3-fs0-ch2",
320 "clk-s-d3-fs0-ch3";
321 };
322
323 clockgen-d3@9107000 {
324 compatible = "st,clkgen-c32";
325 reg = <0x9107000 0x1000>;
326
327 clk_s_d3_flexgen: clk-s-d3-flexgen {
328 #clock-cells = <1>;
329 compatible = "st,flexgen";
330
331 clocks = <&clk_s_d3_quadfs 0>,
332 <&clk_s_d3_quadfs 1>,
333 <&clk_s_d3_quadfs 2>,
334 <&clk_s_d3_quadfs 3>,
335 <&clk_sysin>;
336
337 clock-output-names = "clk-stfe-frc1",
338 "clk-tsout-0",
339 "clk-tsout-1",
340 "clk-mchi",
341 "clk-vsens-compo",
342 "clk-frc1-remote",
343 "clk-lpc-0",
344 "clk-lpc-1";
345 };
346 };
347 };
348};
diff --git a/arch/arm/boot/dts/stih418.dtsi b/arch/arm/boot/dts/stih418.dtsi
new file mode 100644
index 000000000000..354d90f521b6
--- /dev/null
+++ b/arch/arm/boot/dts/stih418.dtsi
@@ -0,0 +1,99 @@
1/*
2 * Copyright (C) 2014 STMicroelectronics Limited.
3 * Author: Peter Griffin <peter.griffin@linaro.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9#include "stih418-clock.dtsi"
10#include "stih407-family.dtsi"
11#include "stih410-pinctrl.dtsi"
12/ {
13 cpus {
14 #address-cells = <1>;
15 #size-cells = <0>;
16 cpu@2 {
17 device_type = "cpu";
18 compatible = "arm,cortex-a9";
19 reg = <2>;
20 };
21 cpu@3 {
22 device_type = "cpu";
23 compatible = "arm,cortex-a9";
24 reg = <3>;
25 };
26 };
27
28 soc {
29 usb2_picophy1: phy2 {
30 compatible = "st,stih407-usb2-phy";
31 #phy-cells = <0>;
32 st,syscfg = <&syscfg_core 0xf8 0xf4>;
33 resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
34 <&picophyreset STIH407_PICOPHY0_RESET>;
35 reset-names = "global", "port";
36 };
37
38 usb2_picophy2: phy3 {
39 compatible = "st,stih407-usb2-phy";
40 #phy-cells = <0>;
41 st,syscfg = <&syscfg_core 0xfc 0xf4>;
42 resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
43 <&picophyreset STIH407_PICOPHY1_RESET>;
44 reset-names = "global", "port";
45 };
46
47 ohci0: usb@9a03c00 {
48 compatible = "st,st-ohci-300x";
49 reg = <0x9a03c00 0x100>;
50 interrupts = <GIC_SPI 180 IRQ_TYPE_NONE>;
51 clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
52 resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
53 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
54 reset-names = "power", "softreset";
55 phys = <&usb2_picophy1>;
56 phy-names = "usb";
57 };
58
59 ehci0: usb@9a03e00 {
60 compatible = "st,st-ehci-300x";
61 reg = <0x9a03e00 0x100>;
62 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
63 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_usb0>;
65 clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
66 resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
67 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
68 reset-names = "power", "softreset";
69 phys = <&usb2_picophy1>;
70 phy-names = "usb";
71 };
72
73 ohci1: usb@9a83c00 {
74 compatible = "st,st-ohci-300x";
75 reg = <0x9a83c00 0x100>;
76 interrupts = <GIC_SPI 181 IRQ_TYPE_NONE>;
77 clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
78 resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
79 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
80 reset-names = "power", "softreset";
81 phys = <&usb2_picophy2>;
82 phy-names = "usb";
83 };
84
85 ehci1: usb@9a83e00 {
86 compatible = "st,st-ehci-300x";
87 reg = <0x9a83e00 0x100>;
88 interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
89 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_usb1>;
91 clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
92 resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
93 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
94 reset-names = "power", "softreset";
95 phys = <&usb2_picophy2>;
96 phy-names = "usb";
97 };
98 };
99};
diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi
index 0074bd49797c..c1d859092be7 100644
--- a/arch/arm/boot/dts/stihxxx-b2120.dtsi
+++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi
@@ -48,12 +48,23 @@
48 }; 48 };
49 49
50 /* SSC11 to HDMI */ 50 /* SSC11 to HDMI */
51 i2c@9541000 { 51 hdmiddc: i2c@9541000 {
52 status = "okay"; 52 status = "okay";
53 /* HDMI V1.3a supports Standard mode only */ 53 /* HDMI V1.3a supports Standard mode only */
54 clock-frequency = <100000>; 54 clock-frequency = <100000>;
55 st,i2c-min-scl-pulse-width-us = <0>; 55 st,i2c-min-scl-pulse-width-us = <0>;
56 st,i2c-min-sda-pulse-width-us = <5>; 56 st,i2c-min-sda-pulse-width-us = <5>;
57 }; 57 };
58
59 miphy28lp_phy: miphy28lp@9b22000 {
60
61 phy_port0: port@9b22000 {
62 st,osc-rdy;
63 };
64
65 phy_port1: port@9b2a000 {
66 st,osc-force-ext;
67 };
68 };
58 }; 69 };
59}; 70};
diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts
index 3bcfd81837f0..b67e5be618cf 100644
--- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
@@ -48,8 +48,11 @@
48 */ 48 */
49 49
50/dts-v1/; 50/dts-v1/;
51/include/ "sun4i-a10.dtsi" 51#include "sun4i-a10.dtsi"
52/include/ "sunxi-common-regulators.dtsi" 52#include "sunxi-common-regulators.dtsi"
53
54#include <dt-bindings/gpio/gpio.h>
55#include <dt-bindings/pinctrl/sun4i-a10.h>
53 56
54/ { 57/ {
55 model = "Mele A1000"; 58 model = "Mele A1000";
@@ -77,7 +80,7 @@
77 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; 80 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
78 vmmc-supply = <&reg_vcc3v3>; 81 vmmc-supply = <&reg_vcc3v3>;
79 bus-width = <4>; 82 bus-width = <4>;
80 cd-gpios = <&pio 7 1 0>; /* PH1 */ 83 cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
81 cd-inverted; 84 cd-inverted;
82 status = "okay"; 85 status = "okay";
83 }; 86 };
@@ -112,15 +115,15 @@
112 emac_power_pin_a1000: emac_power_pin@0 { 115 emac_power_pin_a1000: emac_power_pin@0 {
113 allwinner,pins = "PH15"; 116 allwinner,pins = "PH15";
114 allwinner,function = "gpio_out"; 117 allwinner,function = "gpio_out";
115 allwinner,drive = <0>; 118 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
116 allwinner,pull = <0>; 119 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
117 }; 120 };
118 121
119 led_pins_a1000: led_pins@0 { 122 led_pins_a1000: led_pins@0 {
120 allwinner,pins = "PH10", "PH20"; 123 allwinner,pins = "PH10", "PH20";
121 allwinner,function = "gpio_out"; 124 allwinner,function = "gpio_out";
122 allwinner,drive = <0>; 125 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
123 allwinner,pull = <0>; 126 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
124 }; 127 };
125 }; 128 };
126 129
@@ -159,12 +162,12 @@
159 162
160 red { 163 red {
161 label = "a1000:red:usr"; 164 label = "a1000:red:usr";
162 gpios = <&pio 7 10 0>; 165 gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>;
163 }; 166 };
164 167
165 blue { 168 blue {
166 label = "a1000:blue:usr"; 169 label = "a1000:blue:usr";
167 gpios = <&pio 7 20 0>; 170 gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
168 }; 171 };
169 }; 172 };
170 173
@@ -176,7 +179,7 @@
176 regulator-min-microvolt = <3300000>; 179 regulator-min-microvolt = <3300000>;
177 regulator-max-microvolt = <3300000>; 180 regulator-max-microvolt = <3300000>;
178 enable-active-high; 181 enable-active-high;
179 gpio = <&pio 7 15 0>; 182 gpio = <&pio 7 15 GPIO_ACTIVE_HIGH>;
180 }; 183 };
181 184
182 reg_usb1_vbus: usb1-vbus { 185 reg_usb1_vbus: usb1-vbus {
diff --git a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts
index f3f2974658e4..490b77c9bb36 100644
--- a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts
+++ b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts
@@ -46,8 +46,10 @@
46 */ 46 */
47 47
48/dts-v1/; 48/dts-v1/;
49/include/ "sun4i-a10.dtsi" 49#include "sun4i-a10.dtsi"
50/include/ "sunxi-common-regulators.dtsi" 50#include "sunxi-common-regulators.dtsi"
51
52#include <dt-bindings/gpio/gpio.h>
51 53
52/ { 54/ {
53 model = "BA10 tvbox"; 55 model = "BA10 tvbox";
@@ -74,7 +76,7 @@
74 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; 76 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
75 vmmc-supply = <&reg_vcc3v3>; 77 vmmc-supply = <&reg_vcc3v3>;
76 bus-width = <4>; 78 bus-width = <4>;
77 cd-gpios = <&pio 7 1 0>; /* PH1 */ 79 cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
78 cd-inverted; 80 cd-inverted;
79 status = "okay"; 81 status = "okay";
80 }; 82 };
@@ -140,7 +142,7 @@
140 }; 142 };
141 143
142 reg_usb2_vbus: usb2-vbus { 144 reg_usb2_vbus: usb2-vbus {
143 gpio = <&pio 7 12 0>; 145 gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>;
144 status = "okay"; 146 status = "okay";
145 }; 147 };
146}; 148};
diff --git a/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts b/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts
new file mode 100644
index 000000000000..58214f249598
--- /dev/null
+++ b/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts
@@ -0,0 +1,100 @@
1/*
2 * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48/dts-v1/;
49#include "sun4i-a10.dtsi"
50#include "sunxi-common-regulators.dtsi"
51#include <dt-bindings/gpio/gpio.h>
52
53/ {
54 model = "Chuwi V7 CW0825";
55 compatible = "chuwi,v7-cw0825", "allwinner,sun4i-a10";
56};
57
58&ehci1 {
59 status = "okay";
60};
61
62&i2c0 {
63 pinctrl-names = "default";
64 pinctrl-0 = <&i2c0_pins_a>;
65 status = "okay";
66
67 axp209: pmic@34 {
68 compatible = "x-powers,axp209";
69 reg = <0x34>;
70 interrupts = <0>;
71
72 interrupt-controller;
73 #interrupt-cells = <1>;
74 };
75};
76
77&mmc0 {
78 pinctrl-names = "default";
79 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
80 vmmc-supply = <&reg_vcc3v3>;
81 bus-width = <4>;
82 cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
83 cd-inverted;
84 status = "okay";
85};
86
87&reg_usb2_vbus {
88 status = "okay";
89};
90
91&uart0 {
92 pinctrl-names = "default";
93 pinctrl-0 = <&uart0_pins_a>;
94 status = "okay";
95};
96
97&usbphy {
98 usb2_vbus-supply = <&reg_usb2_vbus>;
99 status = "okay";
100};
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index 6a310da53f18..4260c2b47607 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -47,8 +47,11 @@
47 */ 47 */
48 48
49/dts-v1/; 49/dts-v1/;
50/include/ "sun4i-a10.dtsi" 50#include "sun4i-a10.dtsi"
51/include/ "sunxi-common-regulators.dtsi" 51#include "sunxi-common-regulators.dtsi"
52
53#include <dt-bindings/gpio/gpio.h>
54#include <dt-bindings/pinctrl/sun4i-a10.h>
52 55
53/ { 56/ {
54 model = "Cubietech Cubieboard"; 57 model = "Cubietech Cubieboard";
@@ -75,7 +78,7 @@
75 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; 78 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
76 vmmc-supply = <&reg_vcc3v3>; 79 vmmc-supply = <&reg_vcc3v3>;
77 bus-width = <4>; 80 bus-width = <4>;
78 cd-gpios = <&pio 7 1 0>; /* PH1 */ 81 cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
79 cd-inverted; 82 cd-inverted;
80 status = "okay"; 83 status = "okay";
81 }; 84 };
@@ -111,8 +114,8 @@
111 led_pins_cubieboard: led_pins@0 { 114 led_pins_cubieboard: led_pins@0 {
112 allwinner,pins = "PH20", "PH21"; 115 allwinner,pins = "PH20", "PH21";
113 allwinner,function = "gpio_out"; 116 allwinner,function = "gpio_out";
114 allwinner,drive = <1>; 117 allwinner,drive = <SUN4I_PINCTRL_20_MA>;
115 allwinner,pull = <0>; 118 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
116 }; 119 };
117 }; 120 };
118 121
@@ -134,12 +137,8 @@
134 status = "okay"; 137 status = "okay";
135 138
136 axp209: pmic@34 { 139 axp209: pmic@34 {
137 compatible = "x-powers,axp209";
138 reg = <0x34>; 140 reg = <0x34>;
139 interrupts = <0>; 141 interrupts = <0>;
140
141 interrupt-controller;
142 #interrupt-cells = <1>;
143 }; 142 };
144 }; 143 };
145 144
@@ -148,6 +147,12 @@
148 pinctrl-0 = <&i2c1_pins_a>; 147 pinctrl-0 = <&i2c1_pins_a>;
149 status = "okay"; 148 status = "okay";
150 }; 149 };
150
151 spi0: spi@01c05000 {
152 pinctrl-names = "default";
153 pinctrl-0 = <&spi0_pins_a>;
154 status = "okay";
155 };
151 }; 156 };
152 157
153 leds { 158 leds {
@@ -157,12 +162,12 @@
157 162
158 blue { 163 blue {
159 label = "cubieboard:blue:usr"; 164 label = "cubieboard:blue:usr";
160 gpios = <&pio 7 21 0>; /* LED1 */ 165 gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; /* LED1 */
161 }; 166 };
162 167
163 green { 168 green {
164 label = "cubieboard:green:usr"; 169 label = "cubieboard:green:usr";
165 gpios = <&pio 7 20 0>; /* LED2 */ 170 gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; /* LED2 */
166 linux,default-trigger = "heartbeat"; 171 linux,default-trigger = "heartbeat";
167 }; 172 };
168 }; 173 };
@@ -179,3 +184,34 @@
179 status = "okay"; 184 status = "okay";
180 }; 185 };
181}; 186};
187
188#include "axp209.dtsi"
189
190&cpu0 {
191 cpu-supply = <&reg_dcdc2>;
192};
193
194&reg_dcdc2 {
195 regulator-always-on;
196 regulator-min-microvolt = <1000000>;
197 regulator-max-microvolt = <1450000>;
198 regulator-name = "vdd-cpu";
199};
200
201&reg_dcdc3 {
202 regulator-always-on;
203 regulator-min-microvolt = <1000000>;
204 regulator-max-microvolt = <1400000>;
205 regulator-name = "vdd-int-dll";
206};
207
208&reg_ldo1 {
209 regulator-name = "vdd-rtc";
210};
211
212&reg_ldo2 {
213 regulator-always-on;
214 regulator-min-microvolt = <3000000>;
215 regulator-max-microvolt = <3000000>;
216 regulator-name = "avcc";
217};
diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
index efc116287e0f..d3f73ea25567 100644
--- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
+++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
@@ -48,8 +48,11 @@
48 */ 48 */
49 49
50/dts-v1/; 50/dts-v1/;
51/include/ "sun4i-a10.dtsi" 51#include "sun4i-a10.dtsi"
52/include/ "sunxi-common-regulators.dtsi" 52#include "sunxi-common-regulators.dtsi"
53
54#include <dt-bindings/gpio/gpio.h>
55#include <dt-bindings/pinctrl/sun4i-a10.h>
53 56
54/ { 57/ {
55 model = "Miniand Hackberry"; 58 model = "Miniand Hackberry";
@@ -77,7 +80,7 @@
77 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; 80 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
78 vmmc-supply = <&reg_vcc3v3>; 81 vmmc-supply = <&reg_vcc3v3>;
79 bus-width = <4>; 82 bus-width = <4>;
80 cd-gpios = <&pio 7 1 0>; /* PH1 */ 83 cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
81 cd-inverted; 84 cd-inverted;
82 status = "okay"; 85 status = "okay";
83 }; 86 };
@@ -111,15 +114,15 @@
111 hackberry_hogs: hogs@0 { 114 hackberry_hogs: hogs@0 {
112 allwinner,pins = "PH19"; 115 allwinner,pins = "PH19";
113 allwinner,function = "gpio_out"; 116 allwinner,function = "gpio_out";
114 allwinner,drive = <0>; 117 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
115 allwinner,pull = <0>; 118 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
116 }; 119 };
117 120
118 usb2_vbus_pin_hackberry: usb2_vbus_pin@0 { 121 usb2_vbus_pin_hackberry: usb2_vbus_pin@0 {
119 allwinner,pins = "PH12"; 122 allwinner,pins = "PH12";
120 allwinner,function = "gpio_out"; 123 allwinner,function = "gpio_out";
121 allwinner,drive = <0>; 124 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
122 allwinner,pull = <0>; 125 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
123 }; 126 };
124 }; 127 };
125 128
@@ -157,7 +160,7 @@
157 regulator-min-microvolt = <3300000>; 160 regulator-min-microvolt = <3300000>;
158 regulator-max-microvolt = <3300000>; 161 regulator-max-microvolt = <3300000>;
159 enable-active-high; 162 enable-active-high;
160 gpio = <&pio 7 19 0>; 163 gpio = <&pio 7 19 GPIO_ACTIVE_HIGH>;
161 }; 164 };
162 165
163 reg_usb1_vbus: usb1-vbus { 166 reg_usb1_vbus: usb1-vbus {
@@ -166,7 +169,7 @@
166 169
167 reg_usb2_vbus: usb2-vbus { 170 reg_usb2_vbus: usb2-vbus {
168 pinctrl-0 = <&usb2_vbus_pin_hackberry>; 171 pinctrl-0 = <&usb2_vbus_pin_hackberry>;
169 gpio = <&pio 7 12 0>; 172 gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>;
170 status = "okay"; 173 status = "okay";
171 }; 174 };
172}; 175};
diff --git a/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts b/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts
new file mode 100644
index 000000000000..c88382aacc36
--- /dev/null
+++ b/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts
@@ -0,0 +1,105 @@
1/*
2 * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48/dts-v1/;
49#include "sun4i-a10.dtsi"
50#include "sunxi-common-regulators.dtsi"
51#include <dt-bindings/gpio/gpio.h>
52
53/ {
54 model = "Hyundai A7HD";
55 compatible = "hyundai,a7hd", "allwinner,sun4i-a10";
56};
57
58&ehci1 {
59 status = "okay";
60};
61
62&i2c0 {
63 pinctrl-names = "default";
64 pinctrl-0 = <&i2c0_pins_a>;
65 status = "okay";
66
67 axp209: pmic@34 {
68 compatible = "x-powers,axp209";
69 reg = <0x34>;
70 interrupts = <0>;
71
72 interrupt-controller;
73 #interrupt-cells = <1>;
74 };
75};
76
77&mmc0 {
78 pinctrl-names = "default";
79 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
80 vmmc-supply = <&reg_vcc3v3>;
81 bus-width = <4>;
82 cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
83 cd-inverted;
84 status = "okay";
85};
86
87&reg_usb2_vbus {
88 gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
89 status = "okay";
90};
91
92&uart0 {
93 pinctrl-names = "default";
94 pinctrl-0 = <&uart0_pins_a>;
95 status = "okay";
96};
97
98&usb2_vbus_pin_a {
99 allwinner,pins = "PH6";
100};
101
102&usbphy {
103 usb2_vbus-supply = <&reg_usb2_vbus>;
104 status = "okay";
105};
diff --git a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
index 3e25ee4d3248..482914333bba 100644
--- a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
+++ b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
@@ -48,8 +48,10 @@
48 */ 48 */
49 49
50/dts-v1/; 50/dts-v1/;
51/include/ "sun4i-a10.dtsi" 51#include "sun4i-a10.dtsi"
52/include/ "sunxi-common-regulators.dtsi" 52#include "sunxi-common-regulators.dtsi"
53
54#include <dt-bindings/gpio/gpio.h>
53 55
54/ { 56/ {
55 model = "INet-97F Rev 02"; 57 model = "INet-97F Rev 02";
@@ -65,7 +67,7 @@
65 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; 67 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
66 vmmc-supply = <&reg_vcc3v3>; 68 vmmc-supply = <&reg_vcc3v3>;
67 bus-width = <4>; 69 bus-width = <4>;
68 cd-gpios = <&pio 7 1 0>; /* PH1 */ 70 cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
69 cd-inverted; 71 cd-inverted;
70 status = "okay"; 72 status = "okay";
71 }; 73 };
diff --git a/arch/arm/boot/dts/sun4i-a10-marsboard.dts b/arch/arm/boot/dts/sun4i-a10-marsboard.dts
new file mode 100644
index 000000000000..9ee86a700c2b
--- /dev/null
+++ b/arch/arm/boot/dts/sun4i-a10-marsboard.dts
@@ -0,0 +1,183 @@
1/*
2 * Copyright 2015 Aleksei Mamlin
3 * Aleksei Mamlin <mamlinav@gmail.com>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public
21 * License along with this file; if not, write to the Free
22 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
23 * MA 02110-1301 USA
24 *
25 * Or, alternatively,
26 *
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use,
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
34 * conditions:
35 *
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
38 *
39 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 * OTHER DEALINGS IN THE SOFTWARE.
47 */
48
49/dts-v1/;
50#include "sun4i-a10.dtsi"
51#include "sunxi-common-regulators.dtsi"
52
53#include <dt-bindings/gpio/gpio.h>
54#include <dt-bindings/pinctrl/sun4i-a10.h>
55
56/ {
57 model = "HAOYU Electronics Marsboard A10";
58 compatible = "haoyu,a10-marsboard", "allwinner,sun4i-a10";
59
60 leds {
61 compatible = "gpio-leds";
62 pinctrl-names = "default";
63 pinctrl-0 = <&led_pins_marsboard>;
64
65 red1 {
66 label = "marsboard:red1:usr";
67 gpios = <&pio 1 5 GPIO_ACTIVE_HIGH>;
68 };
69
70 red2 {
71 label = "marsboard:red2:usr";
72 gpios = <&pio 1 6 GPIO_ACTIVE_HIGH>;
73 };
74
75 red3 {
76 label = "marsboard:red3:usr";
77 gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>;
78 };
79
80 red4 {
81 label = "marsboard:red4:usr";
82 gpios = <&pio 1 8 GPIO_ACTIVE_HIGH>;
83 };
84 };
85};
86
87&ahci {
88 status = "okay";
89};
90
91&ehci0 {
92 status = "okay";
93};
94
95&ehci1 {
96 status = "okay";
97};
98
99&emac {
100 pinctrl-names = "default";
101 pinctrl-0 = <&emac_pins_a>;
102 phy = <&phy1>;
103 status = "okay";
104};
105
106&i2c0 {
107 pinctrl-names = "default";
108 pinctrl-0 = <&i2c0_pins_a>;
109 status = "okay";
110};
111
112&i2c1 {
113 pinctrl-names = "default";
114 pinctrl-0 = <&i2c1_pins_a>;
115 status = "okay";
116};
117
118&i2c2 {
119 pinctrl-names = "default";
120 pinctrl-0 = <&i2c2_pins_a>;
121 status = "okay";
122};
123
124&mdio {
125 status = "okay";
126
127 phy1: ethernet-phy@1 {
128 reg = <1>;
129 };
130};
131
132&mmc0 {
133 pinctrl-names = "default";
134 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
135 vmmc-supply = <&reg_vcc3v3>;
136 bus-width = <4>;
137 cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
138 cd-inverted;
139 status = "okay";
140};
141
142&ohci0 {
143 status = "okay";
144};
145
146&ohci1 {
147 status = "okay";
148};
149
150&pio {
151 led_pins_marsboard: led_pins@0 {
152 allwinner,pins = "PB5", "PB6", "PB7", "PB8";
153 allwinner,function = "gpio_out";
154 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
155 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
156 };
157};
158
159&reg_usb1_vbus {
160 status = "okay";
161};
162
163&reg_usb2_vbus {
164 status = "okay";
165};
166
167&spi0 {
168 pinctrl-names = "default";
169 pinctrl-0 = <&spi0_pins_a>;
170 status = "okay";
171};
172
173&uart0 {
174 pinctrl-names = "default";
175 pinctrl-0 = <&uart0_pins_a>;
176 status = "okay";
177};
178
179&usbphy {
180 usb1_vbus-supply = <&reg_usb1_vbus>;
181 usb2_vbus-supply = <&reg_usb2_vbus>;
182 status = "okay";
183};
diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
index 8b3f97470249..eb5fd6904a69 100644
--- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
+++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
@@ -48,8 +48,11 @@
48 */ 48 */
49 49
50/dts-v1/; 50/dts-v1/;
51/include/ "sun4i-a10.dtsi" 51#include "sun4i-a10.dtsi"
52/include/ "sunxi-common-regulators.dtsi" 52#include "sunxi-common-regulators.dtsi"
53
54#include <dt-bindings/gpio/gpio.h>
55#include <dt-bindings/pinctrl/sun4i-a10.h>
53 56
54/ { 57/ {
55 model = "PineRiver Mini X-Plus"; 58 model = "PineRiver Mini X-Plus";
@@ -61,7 +64,7 @@
61 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; 64 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
62 vmmc-supply = <&reg_vcc3v3>; 65 vmmc-supply = <&reg_vcc3v3>;
63 bus-width = <4>; 66 bus-width = <4>;
64 cd-gpios = <&pio 7 1 0>; /* PH1 */ 67 cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
65 cd-inverted; 68 cd-inverted;
66 status = "okay"; 69 status = "okay";
67 }; 70 };
@@ -91,7 +94,7 @@
91 pinctrl@01c20800 { 94 pinctrl@01c20800 {
92 ir0_pins_a: ir0@0 { 95 ir0_pins_a: ir0@0 {
93 /* The ir receiver is not always populated */ 96 /* The ir receiver is not always populated */
94 allwinner,pull = <1>; 97 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
95 }; 98 };
96 }; 99 };
97 100
diff --git a/arch/arm/boot/dts/sun4i-a10-mk802.dts b/arch/arm/boot/dts/sun4i-a10-mk802.dts
new file mode 100644
index 000000000000..e9a6886f0d51
--- /dev/null
+++ b/arch/arm/boot/dts/sun4i-a10-mk802.dts
@@ -0,0 +1,109 @@
1/*
2 * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48/dts-v1/;
49#include "sun4i-a10.dtsi"
50#include "sunxi-common-regulators.dtsi"
51#include <dt-bindings/gpio/gpio.h>
52
53/ {
54 model = "MK802";
55 compatible = "allwinner,mk802", "allwinner,sun4i-a10";
56};
57
58&ehci0 {
59 status = "okay";
60};
61
62&ehci1 {
63 status = "okay";
64};
65
66&mmc0 {
67 pinctrl-names = "default";
68 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
69 vmmc-supply = <&reg_vcc3v3>;
70 bus-width = <4>;
71 cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
72 cd-inverted;
73 status = "okay";
74};
75
76&ohci0 {
77 status = "okay";
78};
79
80&pio {
81 usb2_vbus_pin_mk802: usb2_vbus_pin@0 {
82 allwinner,pins = "PH12";
83 allwinner,function = "gpio_out";
84 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
85 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
86 };
87};
88
89&reg_usb1_vbus {
90 status = "okay";
91};
92
93&reg_usb2_vbus {
94 pinctrl-0 = <&usb2_vbus_pin_mk802>;
95 gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */
96 status = "okay";
97};
98
99&uart0 {
100 pinctrl-names = "default";
101 pinctrl-0 = <&uart0_pins_a>;
102 status = "okay";
103};
104
105&usbphy {
106 usb1_vbus-supply = <&reg_usb1_vbus>;
107 usb2_vbus-supply = <&reg_usb2_vbus>;
108 status = "okay";
109};
diff --git a/arch/arm/boot/dts/sun4i-a10-mk802ii.dts b/arch/arm/boot/dts/sun4i-a10-mk802ii.dts
new file mode 100644
index 000000000000..802eda494d1c
--- /dev/null
+++ b/arch/arm/boot/dts/sun4i-a10-mk802ii.dts
@@ -0,0 +1,113 @@
1/*
2 * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48/dts-v1/;
49#include "sun4i-a10.dtsi"
50#include "sunxi-common-regulators.dtsi"
51#include <dt-bindings/gpio/gpio.h>
52
53/ {
54 model = "MK802ii";
55 compatible = "allwinner,mk802ii", "allwinner,sun4i-a10";
56};
57
58&ehci0 {
59 status = "okay";
60};
61
62&ehci1 {
63 status = "okay";
64};
65
66&i2c0 {
67 pinctrl-names = "default";
68 pinctrl-0 = <&i2c0_pins_a>;
69 status = "okay";
70
71 axp209: pmic@34 {
72 compatible = "x-powers,axp209";
73 reg = <0x34>;
74 interrupts = <0>;
75
76 interrupt-controller;
77 #interrupt-cells = <1>;
78 };
79};
80
81&mmc0 {
82 pinctrl-names = "default";
83 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
84 vmmc-supply = <&reg_vcc3v3>;
85 bus-width = <4>;
86 cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
87 cd-inverted;
88 status = "okay";
89};
90
91&ohci0 {
92 status = "okay";
93};
94
95&reg_usb1_vbus {
96 status = "okay";
97};
98
99&reg_usb2_vbus {
100 status = "okay";
101};
102
103&uart0 {
104 pinctrl-names = "default";
105 pinctrl-0 = <&uart0_pins_a>;
106 status = "okay";
107};
108
109&usbphy {
110 usb1_vbus-supply = <&reg_usb1_vbus>;
111 usb2_vbus-supply = <&reg_usb2_vbus>;
112 status = "okay";
113};
diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
index 88cf1a531155..ab7891c43231 100644
--- a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
+++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
@@ -46,8 +46,11 @@
46 */ 46 */
47 47
48/dts-v1/; 48/dts-v1/;
49/include/ "sun4i-a10.dtsi" 49#include "sun4i-a10.dtsi"
50/include/ "sunxi-common-regulators.dtsi" 50#include "sunxi-common-regulators.dtsi"
51
52#include <dt-bindings/gpio/gpio.h>
53#include <dt-bindings/pinctrl/sun4i-a10.h>
51 54
52/ { 55/ {
53 model = "Olimex A10-OLinuXino-LIME"; 56 model = "Olimex A10-OLinuXino-LIME";
@@ -74,7 +77,7 @@
74 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; 77 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
75 vmmc-supply = <&reg_vcc3v3>; 78 vmmc-supply = <&reg_vcc3v3>;
76 bus-width = <4>; 79 bus-width = <4>;
77 cd-gpios = <&pio 7 1 0>; /* PH1 */ 80 cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
78 cd-inverted; 81 cd-inverted;
79 status = "okay"; 82 status = "okay";
80 }; 83 };
@@ -110,15 +113,15 @@
110 ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 { 113 ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 {
111 allwinner,pins = "PC3"; 114 allwinner,pins = "PC3";
112 allwinner,function = "gpio_out"; 115 allwinner,function = "gpio_out";
113 allwinner,drive = <0>; 116 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
114 allwinner,pull = <0>; 117 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
115 }; 118 };
116 119
117 led_pins_olinuxinolime: led_pins@0 { 120 led_pins_olinuxinolime: led_pins@0 {
118 allwinner,pins = "PH2"; 121 allwinner,pins = "PH2";
119 allwinner,function = "gpio_out"; 122 allwinner,function = "gpio_out";
120 allwinner,drive = <1>; 123 allwinner,drive = <SUN4I_PINCTRL_20_MA>;
121 allwinner,pull = <0>; 124 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
122 }; 125 };
123 }; 126 };
124 127
@@ -151,14 +154,14 @@
151 154
152 green { 155 green {
153 label = "a10-olinuxino-lime:green:usr"; 156 label = "a10-olinuxino-lime:green:usr";
154 gpios = <&pio 7 2 0>; 157 gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>;
155 default-state = "on"; 158 default-state = "on";
156 }; 159 };
157 }; 160 };
158 161
159 reg_ahci_5v: ahci-5v { 162 reg_ahci_5v: ahci-5v {
160 pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>; 163 pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>;
161 gpio = <&pio 2 3 0>; 164 gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>;
162 status = "okay"; 165 status = "okay";
163 }; 166 };
164 167
diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
index ce5994597407..9d1e5482cf82 100644
--- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts
+++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
@@ -47,8 +47,12 @@
47 */ 47 */
48 48
49/dts-v1/; 49/dts-v1/;
50/include/ "sun4i-a10.dtsi" 50#include "sun4i-a10.dtsi"
51/include/ "sunxi-common-regulators.dtsi" 51#include "sunxi-common-regulators.dtsi"
52
53#include <dt-bindings/gpio/gpio.h>
54#include <dt-bindings/input/input.h>
55#include <dt-bindings/pinctrl/sun4i-a10.h>
52 56
53/ { 57/ {
54 model = "LinkSprite pcDuino"; 58 model = "LinkSprite pcDuino";
@@ -62,6 +66,22 @@
62 status = "okay"; 66 status = "okay";
63 }; 67 };
64 68
69 pinctrl@01c20800 {
70 led_pins_pcduino: led_pins@0 {
71 allwinner,pins = "PH15", "PH16";
72 allwinner,function = "gpio_out";
73 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
74 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
75 };
76
77 key_pins_pcduino: key_pins@0 {
78 allwinner,pins = "PH17", "PH18", "PH19";
79 allwinner,function = "gpio_in";
80 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
81 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
82 };
83 };
84
65 mdio@01c0b080 { 85 mdio@01c0b080 {
66 status = "okay"; 86 status = "okay";
67 87
@@ -75,7 +95,7 @@
75 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; 95 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
76 vmmc-supply = <&reg_vcc3v3>; 96 vmmc-supply = <&reg_vcc3v3>;
77 bus-width = <4>; 97 bus-width = <4>;
78 cd-gpios = <&pio 7 1 0>; /* PH1 */ 98 cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
79 cd-inverted; 99 cd-inverted;
80 status = "okay"; 100 status = "okay";
81 }; 101 };
@@ -124,6 +144,48 @@
124 }; 144 };
125 }; 145 };
126 146
147 leds {
148 compatible = "gpio-leds";
149 pinctrl-names = "default";
150 pinctrl-0 = <&led_pins_pcduino>;
151
152 tx {
153 label = "pcduino:green:tx";
154 gpios = <&pio 7 15 GPIO_ACTIVE_LOW>;
155 };
156
157 rx {
158 label = "pcduino:green:rx";
159 gpios = <&pio 7 16 GPIO_ACTIVE_LOW>;
160 };
161 };
162
163 gpio_keys {
164 compatible = "gpio-keys";
165 pinctrl-names = "default";
166 pinctrl-0 = <&key_pins_pcduino>;
167 #address-cells = <1>;
168 #size-cells = <0>;
169
170 button@0 {
171 label = "Key Back";
172 linux,code = <KEY_BACK>;
173 gpios = <&pio 7 17 GPIO_ACTIVE_LOW>;
174 };
175
176 button@1 {
177 label = "Key Home";
178 linux,code = <KEY_HOME>;
179 gpios = <&pio 7 18 GPIO_ACTIVE_LOW>;
180 };
181
182 button@2 {
183 label = "Key Menu";
184 linux,code = <KEY_MENU>;
185 gpios = <&pio 7 19 GPIO_ACTIVE_LOW>;
186 };
187 };
188
127 reg_usb1_vbus: usb1-vbus { 189 reg_usb1_vbus: usb1-vbus {
128 status = "okay"; 190 status = "okay";
129 }; 191 };
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index d5c4669224b1..8ca3c1a2063d 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -10,7 +10,12 @@
10 * http://www.gnu.org/copyleft/gpl.html 10 * http://www.gnu.org/copyleft/gpl.html
11 */ 11 */
12 12
13/include/ "skeleton.dtsi" 13#include "skeleton.dtsi"
14
15#include <dt-bindings/thermal/thermal.h>
16
17#include <dt-bindings/dma/sun4i-a10.h>
18#include <dt-bindings/pinctrl/sun4i-a10.h>
14 19
15/ { 20/ {
16 interrupt-parent = <&intc>; 21 interrupt-parent = <&intc>;
@@ -39,15 +44,78 @@
39 <&ahb_gates 44>, <&ahb_gates 46>; 44 <&ahb_gates 44>, <&ahb_gates 46>;
40 status = "disabled"; 45 status = "disabled";
41 }; 46 };
47
48 framebuffer@2 {
49 compatible = "allwinner,simple-framebuffer",
50 "simple-framebuffer";
51 allwinner,pipeline = "de_fe0-de_be0-lcd0";
52 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
53 <&ahb_gates 46>;
54 status = "disabled";
55 };
56
57 framebuffer@3 {
58 compatible = "allwinner,simple-framebuffer",
59 "simple-framebuffer";
60 allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
61 clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
62 <&ahb_gates 44>, <&ahb_gates 46>;
63 status = "disabled";
64 };
42 }; 65 };
43 66
44 cpus { 67 cpus {
45 #address-cells = <1>; 68 #address-cells = <1>;
46 #size-cells = <0>; 69 #size-cells = <0>;
47 cpu@0 { 70 cpu0: cpu@0 {
48 device_type = "cpu"; 71 device_type = "cpu";
49 compatible = "arm,cortex-a8"; 72 compatible = "arm,cortex-a8";
50 reg = <0x0>; 73 reg = <0x0>;
74 clocks = <&cpu>;
75 clock-latency = <244144>; /* 8 32k periods */
76 operating-points = <
77 /* kHz uV */
78 1056000 1500000
79 1008000 1400000
80 912000 1350000
81 864000 1300000
82 624000 1250000
83 >;
84 #cooling-cells = <2>;
85 cooling-min-level = <0>;
86 cooling-max-level = <4>;
87 };
88 };
89
90 thermal-zones {
91 cpu_thermal {
92 /* milliseconds */
93 polling-delay-passive = <250>;
94 polling-delay = <1000>;
95 thermal-sensors = <&rtp>;
96
97 cooling-maps {
98 map0 {
99 trip = <&cpu_alert0>;
100 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
101 };
102 };
103
104 trips {
105 cpu_alert0: cpu_alert0 {
106 /* milliCelsius */
107 temperature = <850000>;
108 hysteresis = <2000>;
109 type = "passive";
110 };
111
112 cpu_crit: cpu_crit {
113 /* milliCelsius */
114 temperature = <100000>;
115 hysteresis = <2000>;
116 type = "critical";
117 };
118 };
51 }; 119 };
52 }; 120 };
53 121
@@ -359,7 +427,8 @@
359 interrupts = <10>; 427 interrupts = <10>;
360 clocks = <&ahb_gates 20>, <&spi0_clk>; 428 clocks = <&ahb_gates 20>, <&spi0_clk>;
361 clock-names = "ahb", "mod"; 429 clock-names = "ahb", "mod";
362 dmas = <&dma 1 27>, <&dma 1 26>; 430 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
431 <&dma SUN4I_DMA_DEDICATED 26>;
363 dma-names = "rx", "tx"; 432 dma-names = "rx", "tx";
364 status = "disabled"; 433 status = "disabled";
365 #address-cells = <1>; 434 #address-cells = <1>;
@@ -372,7 +441,8 @@
372 interrupts = <11>; 441 interrupts = <11>;
373 clocks = <&ahb_gates 21>, <&spi1_clk>; 442 clocks = <&ahb_gates 21>, <&spi1_clk>;
374 clock-names = "ahb", "mod"; 443 clock-names = "ahb", "mod";
375 dmas = <&dma 1 9>, <&dma 1 8>; 444 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
445 <&dma SUN4I_DMA_DEDICATED 8>;
376 dma-names = "rx", "tx"; 446 dma-names = "rx", "tx";
377 status = "disabled"; 447 status = "disabled";
378 #address-cells = <1>; 448 #address-cells = <1>;
@@ -387,7 +457,7 @@
387 status = "disabled"; 457 status = "disabled";
388 }; 458 };
389 459
390 mdio@01c0b080 { 460 mdio: mdio@01c0b080 {
391 compatible = "allwinner,sun4i-a10-mdio"; 461 compatible = "allwinner,sun4i-a10-mdio";
392 reg = <0x01c0b080 0x14>; 462 reg = <0x01c0b080 0x14>;
393 status = "disabled"; 463 status = "disabled";
@@ -469,7 +539,8 @@
469 interrupts = <12>; 539 interrupts = <12>;
470 clocks = <&ahb_gates 22>, <&spi2_clk>; 540 clocks = <&ahb_gates 22>, <&spi2_clk>;
471 clock-names = "ahb", "mod"; 541 clock-names = "ahb", "mod";
472 dmas = <&dma 1 29>, <&dma 1 28>; 542 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
543 <&dma SUN4I_DMA_DEDICATED 28>;
473 dma-names = "rx", "tx"; 544 dma-names = "rx", "tx";
474 status = "disabled"; 545 status = "disabled";
475 #address-cells = <1>; 546 #address-cells = <1>;
@@ -510,7 +581,8 @@
510 interrupts = <50>; 581 interrupts = <50>;
511 clocks = <&ahb_gates 23>, <&spi3_clk>; 582 clocks = <&ahb_gates 23>, <&spi3_clk>;
512 clock-names = "ahb", "mod"; 583 clock-names = "ahb", "mod";
513 dmas = <&dma 1 31>, <&dma 1 30>; 584 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
585 <&dma SUN4I_DMA_DEDICATED 30>;
514 dma-names = "rx", "tx"; 586 dma-names = "rx", "tx";
515 status = "disabled"; 587 status = "disabled";
516 #address-cells = <1>; 588 #address-cells = <1>;
@@ -538,57 +610,57 @@
538 pwm0_pins_a: pwm0@0 { 610 pwm0_pins_a: pwm0@0 {
539 allwinner,pins = "PB2"; 611 allwinner,pins = "PB2";
540 allwinner,function = "pwm"; 612 allwinner,function = "pwm";
541 allwinner,drive = <0>; 613 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
542 allwinner,pull = <0>; 614 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
543 }; 615 };
544 616
545 pwm1_pins_a: pwm1@0 { 617 pwm1_pins_a: pwm1@0 {
546 allwinner,pins = "PI3"; 618 allwinner,pins = "PI3";
547 allwinner,function = "pwm"; 619 allwinner,function = "pwm";
548 allwinner,drive = <0>; 620 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
549 allwinner,pull = <0>; 621 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
550 }; 622 };
551 623
552 uart0_pins_a: uart0@0 { 624 uart0_pins_a: uart0@0 {
553 allwinner,pins = "PB22", "PB23"; 625 allwinner,pins = "PB22", "PB23";
554 allwinner,function = "uart0"; 626 allwinner,function = "uart0";
555 allwinner,drive = <0>; 627 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
556 allwinner,pull = <0>; 628 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
557 }; 629 };
558 630
559 uart0_pins_b: uart0@1 { 631 uart0_pins_b: uart0@1 {
560 allwinner,pins = "PF2", "PF4"; 632 allwinner,pins = "PF2", "PF4";
561 allwinner,function = "uart0"; 633 allwinner,function = "uart0";
562 allwinner,drive = <0>; 634 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
563 allwinner,pull = <0>; 635 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
564 }; 636 };
565 637
566 uart1_pins_a: uart1@0 { 638 uart1_pins_a: uart1@0 {
567 allwinner,pins = "PA10", "PA11"; 639 allwinner,pins = "PA10", "PA11";
568 allwinner,function = "uart1"; 640 allwinner,function = "uart1";
569 allwinner,drive = <0>; 641 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
570 allwinner,pull = <0>; 642 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
571 }; 643 };
572 644
573 i2c0_pins_a: i2c0@0 { 645 i2c0_pins_a: i2c0@0 {
574 allwinner,pins = "PB0", "PB1"; 646 allwinner,pins = "PB0", "PB1";
575 allwinner,function = "i2c0"; 647 allwinner,function = "i2c0";
576 allwinner,drive = <0>; 648 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
577 allwinner,pull = <0>; 649 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
578 }; 650 };
579 651
580 i2c1_pins_a: i2c1@0 { 652 i2c1_pins_a: i2c1@0 {
581 allwinner,pins = "PB18", "PB19"; 653 allwinner,pins = "PB18", "PB19";
582 allwinner,function = "i2c1"; 654 allwinner,function = "i2c1";
583 allwinner,drive = <0>; 655 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
584 allwinner,pull = <0>; 656 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
585 }; 657 };
586 658
587 i2c2_pins_a: i2c2@0 { 659 i2c2_pins_a: i2c2@0 {
588 allwinner,pins = "PB20", "PB21"; 660 allwinner,pins = "PB20", "PB21";
589 allwinner,function = "i2c2"; 661 allwinner,function = "i2c2";
590 allwinner,drive = <0>; 662 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
591 allwinner,pull = <0>; 663 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
592 }; 664 };
593 665
594 emac_pins_a: emac0@0 { 666 emac_pins_a: emac0@0 {
@@ -598,36 +670,78 @@
598 "PA11", "PA12", "PA13", "PA14", 670 "PA11", "PA12", "PA13", "PA14",
599 "PA15", "PA16"; 671 "PA15", "PA16";
600 allwinner,function = "emac"; 672 allwinner,function = "emac";
601 allwinner,drive = <0>; 673 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
602 allwinner,pull = <0>; 674 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
603 }; 675 };
604 676
605 mmc0_pins_a: mmc0@0 { 677 mmc0_pins_a: mmc0@0 {
606 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; 678 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
607 allwinner,function = "mmc0"; 679 allwinner,function = "mmc0";
608 allwinner,drive = <2>; 680 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
609 allwinner,pull = <0>; 681 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
610 }; 682 };
611 683
612 mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { 684 mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
613 allwinner,pins = "PH1"; 685 allwinner,pins = "PH1";
614 allwinner,function = "gpio_in"; 686 allwinner,function = "gpio_in";
615 allwinner,drive = <0>; 687 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
616 allwinner,pull = <1>; 688 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
617 }; 689 };
618 690
619 ir0_pins_a: ir0@0 { 691 ir0_pins_a: ir0@0 {
620 allwinner,pins = "PB3","PB4"; 692 allwinner,pins = "PB3","PB4";
621 allwinner,function = "ir0"; 693 allwinner,function = "ir0";
622 allwinner,drive = <0>; 694 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
623 allwinner,pull = <0>; 695 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
624 }; 696 };
625 697
626 ir1_pins_a: ir1@0 { 698 ir1_pins_a: ir1@0 {
627 allwinner,pins = "PB22","PB23"; 699 allwinner,pins = "PB22","PB23";
628 allwinner,function = "ir1"; 700 allwinner,function = "ir1";
629 allwinner,drive = <0>; 701 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
630 allwinner,pull = <0>; 702 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
703 };
704
705 spi0_pins_a: spi0@0 {
706 allwinner,pins = "PI10", "PI11", "PI12", "PI13";
707 allwinner,function = "spi0";
708 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
709 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
710 };
711
712 spi1_pins_a: spi1@0 {
713 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
714 allwinner,function = "spi1";
715 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
716 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
717 };
718
719 spi2_pins_a: spi2@0 {
720 allwinner,pins = "PB14", "PB15", "PB16", "PB17";
721 allwinner,function = "spi2";
722 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
723 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
724 };
725
726 spi2_pins_b: spi2@1 {
727 allwinner,pins = "PC19", "PC20", "PC21", "PC22";
728 allwinner,function = "spi2";
729 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
730 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
731 };
732
733 ps20_pins_a: ps20@0 {
734 allwinner,pins = "PI20", "PI21";
735 allwinner,function = "ps2";
736 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
737 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
738 };
739
740 ps21_pins_a: ps21@0 {
741 allwinner,pins = "PH12", "PH13";
742 allwinner,function = "ps2";
743 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
744 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
631 }; 745 };
632 }; 746 };
633 747
@@ -675,6 +789,13 @@
675 status = "disabled"; 789 status = "disabled";
676 }; 790 };
677 791
792 lradc: lradc@01c22800 {
793 compatible = "allwinner,sun4i-a10-lradc-keys";
794 reg = <0x01c22800 0x100>;
795 interrupts = <31>;
796 status = "disabled";
797 };
798
678 sid: eeprom@01c23800 { 799 sid: eeprom@01c23800 {
679 compatible = "allwinner,sun4i-a10-sid"; 800 compatible = "allwinner,sun4i-a10-sid";
680 reg = <0x01c23800 0x10>; 801 reg = <0x01c23800 0x10>;
@@ -684,6 +805,7 @@
684 compatible = "allwinner,sun4i-a10-ts"; 805 compatible = "allwinner,sun4i-a10-ts";
685 reg = <0x01c25000 0x100>; 806 reg = <0x01c25000 0x100>;
686 interrupts = <29>; 807 interrupts = <29>;
808 #thermal-sensor-cells = <0>;
687 }; 809 };
688 810
689 uart0: serial@01c28000 { 811 uart0: serial@01c28000 {
@@ -795,5 +917,21 @@
795 #address-cells = <1>; 917 #address-cells = <1>;
796 #size-cells = <0>; 918 #size-cells = <0>;
797 }; 919 };
920
921 ps20: ps2@01c2a000 {
922 compatible = "allwinner,sun4i-a10-ps2";
923 reg = <0x01c2a000 0x400>;
924 interrupts = <62>;
925 clocks = <&apb1_gates 6>;
926 status = "disabled";
927 };
928
929 ps21: ps2@01c2a400 {
930 compatible = "allwinner,sun4i-a10-ps2";
931 reg = <0x01c2a400 0x400>;
932 interrupts = <63>;
933 clocks = <&apb1_gates 7>;
934 status = "disabled";
935 };
798 }; 936 };
799}; 937};
diff --git a/arch/arm/boot/dts/sun5i-a10s-mk802.dts b/arch/arm/boot/dts/sun5i-a10s-mk802.dts
new file mode 100644
index 000000000000..b21af87d9eae
--- /dev/null
+++ b/arch/arm/boot/dts/sun5i-a10s-mk802.dts
@@ -0,0 +1,125 @@
1/*
2 * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48/dts-v1/;
49#include "sun5i-a10s.dtsi"
50#include "sunxi-common-regulators.dtsi"
51#include <dt-bindings/gpio/gpio.h>
52
53/ {
54 model = "MK802-A10s";
55 compatible = "allwinner,a10s-mk802", "allwinner,sun5i-a10s";
56
57 leds {
58 compatible = "gpio-leds";
59 pinctrl-names = "default";
60 pinctrl-0 = <&led_pins_mk802>;
61
62 red {
63 label = "mk802:red:usr";
64 gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */
65 };
66 };
67};
68
69&ehci0 {
70 status = "okay";
71};
72
73&mmc0 {
74 pinctrl-names = "default";
75 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_mk802>;
76 vmmc-supply = <&reg_vcc3v3>;
77 bus-width = <4>;
78 cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
79 cd-inverted;
80 status = "okay";
81};
82
83&ohci0 {
84 status = "okay";
85};
86
87&pio {
88 led_pins_mk802: led_pins@0 {
89 allwinner,pins = "PB2";
90 allwinner,function = "gpio_out";
91 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
92 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
93 };
94
95 mmc0_cd_pin_mk802: mmc0_cd_pin@0 {
96 allwinner,pins = "PG1";
97 allwinner,function = "gpio_in";
98 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
99 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
100 };
101
102 usb1_vbus_pin_mk802: usb1_vbus_pin@0 {
103 allwinner,pins = "PB10";
104 allwinner,function = "gpio_out";
105 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
106 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
107 };
108};
109
110&reg_usb1_vbus {
111 pinctrl-0 = <&usb1_vbus_pin_mk802>;
112 gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */
113 status = "okay";
114};
115
116&uart0 {
117 pinctrl-names = "default";
118 pinctrl-0 = <&uart0_pins_a>;
119 status = "okay";
120};
121
122&usbphy {
123 usb1_vbus-supply = <&reg_usb1_vbus>;
124 status = "okay";
125};
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
index bfa742817690..2bbc93b935ca 100644
--- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
@@ -48,8 +48,12 @@
48 */ 48 */
49 49
50/dts-v1/; 50/dts-v1/;
51/include/ "sun5i-a10s.dtsi" 51#include "sun5i-a10s.dtsi"
52/include/ "sunxi-common-regulators.dtsi" 52#include "sunxi-common-regulators.dtsi"
53
54#include <dt-bindings/gpio/gpio.h>
55#include <dt-bindings/input/input.h>
56#include <dt-bindings/pinctrl/sun4i-a10.h>
53 57
54/ { 58/ {
55 model = "Olimex A10s-Olinuxino Micro"; 59 model = "Olimex A10s-Olinuxino Micro";
@@ -82,7 +86,7 @@
82 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino_micro>; 86 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino_micro>;
83 vmmc-supply = <&reg_vcc3v3>; 87 vmmc-supply = <&reg_vcc3v3>;
84 bus-width = <4>; 88 bus-width = <4>;
85 cd-gpios = <&pio 6 1 0>; /* PG1 */ 89 cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
86 cd-inverted; 90 cd-inverted;
87 status = "okay"; 91 status = "okay";
88 }; 92 };
@@ -92,7 +96,7 @@
92 pinctrl-0 = <&mmc1_pins_a>, <&mmc1_cd_pin_olinuxino_micro>; 96 pinctrl-0 = <&mmc1_pins_a>, <&mmc1_cd_pin_olinuxino_micro>;
93 vmmc-supply = <&reg_vcc3v3>; 97 vmmc-supply = <&reg_vcc3v3>;
94 bus-width = <4>; 98 bus-width = <4>;
95 cd-gpios = <&pio 6 13 0>; /* PG13 */ 99 cd-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */
96 cd-inverted; 100 cd-inverted;
97 status = "okay"; 101 status = "okay";
98 }; 102 };
@@ -114,29 +118,69 @@
114 mmc0_cd_pin_olinuxino_micro: mmc0_cd_pin@0 { 118 mmc0_cd_pin_olinuxino_micro: mmc0_cd_pin@0 {
115 allwinner,pins = "PG1"; 119 allwinner,pins = "PG1";
116 allwinner,function = "gpio_in"; 120 allwinner,function = "gpio_in";
117 allwinner,drive = <0>; 121 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
118 allwinner,pull = <1>; 122 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
119 }; 123 };
120 124
121 mmc1_cd_pin_olinuxino_micro: mmc1_cd_pin@0 { 125 mmc1_cd_pin_olinuxino_micro: mmc1_cd_pin@0 {
122 allwinner,pins = "PG13"; 126 allwinner,pins = "PG13";
123 allwinner,function = "gpio_in"; 127 allwinner,function = "gpio_in";
124 allwinner,drive = <0>; 128 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
125 allwinner,pull = <1>; 129 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
126 }; 130 };
127 131
128 led_pins_olinuxino: led_pins@0 { 132 led_pins_olinuxino: led_pins@0 {
129 allwinner,pins = "PE3"; 133 allwinner,pins = "PE3";
130 allwinner,function = "gpio_out"; 134 allwinner,function = "gpio_out";
131 allwinner,drive = <1>; 135 allwinner,drive = <SUN4I_PINCTRL_20_MA>;
132 allwinner,pull = <0>; 136 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
133 }; 137 };
134 138
135 usb1_vbus_pin_olinuxino_m: usb1_vbus_pin@0 { 139 usb1_vbus_pin_olinuxino_m: usb1_vbus_pin@0 {
136 allwinner,pins = "PB10"; 140 allwinner,pins = "PB10";
137 allwinner,function = "gpio_out"; 141 allwinner,function = "gpio_out";
138 allwinner,drive = <0>; 142 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
139 allwinner,pull = <0>; 143 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
144 };
145 };
146
147 lradc: lradc@01c22800 {
148 vref-supply = <&reg_vcc3v0>;
149 status = "okay";
150
151 button@191 {
152 label = "Volume Up";
153 linux,code = <KEY_VOLUMEUP>;
154 channel = <0>;
155 voltage = <191274>;
156 };
157
158 button@392 {
159 label = "Volume Down";
160 linux,code = <KEY_VOLUMEDOWN>;
161 channel = <0>;
162 voltage = <392644>;
163 };
164
165 button@601 {
166 label = "Menu";
167 linux,code = <KEY_MENU>;
168 channel = <0>;
169 voltage = <601151>;
170 };
171
172 button@795 {
173 label = "Enter";
174 linux,code = <KEY_ENTER>;
175 channel = <0>;
176 voltage = <795090>;
177 };
178
179 button@987 {
180 label = "Home";
181 linux,code = <KEY_HOMEPAGE>;
182 channel = <0>;
183 voltage = <987387>;
140 }; 184 };
141 }; 185 };
142 186
@@ -191,14 +235,14 @@
191 235
192 green { 236 green {
193 label = "a10s-olinuxino-micro:green:usr"; 237 label = "a10s-olinuxino-micro:green:usr";
194 gpios = <&pio 4 3 0>; 238 gpios = <&pio 4 3 GPIO_ACTIVE_HIGH>;
195 default-state = "on"; 239 default-state = "on";
196 }; 240 };
197 }; 241 };
198 242
199 reg_usb1_vbus: usb1-vbus { 243 reg_usb1_vbus: usb1-vbus {
200 pinctrl-0 = <&usb1_vbus_pin_olinuxino_m>; 244 pinctrl-0 = <&usb1_vbus_pin_olinuxino_m>;
201 gpio = <&pio 1 10 0>; 245 gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>;
202 status = "okay"; 246 status = "okay";
203 }; 247 };
204}; 248};
diff --git a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts
index 1fa2916eafc2..7deddfc9df8b 100644
--- a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts
@@ -46,8 +46,11 @@
46 */ 46 */
47 47
48/dts-v1/; 48/dts-v1/;
49/include/ "sun5i-a10s.dtsi" 49#include "sun5i-a10s.dtsi"
50/include/ "sunxi-common-regulators.dtsi" 50#include "sunxi-common-regulators.dtsi"
51
52#include <dt-bindings/gpio/gpio.h>
53#include <dt-bindings/pinctrl/sun4i-a10.h>
51 54
52/ { 55/ {
53 model = "R7 A10s hdmi tv-stick"; 56 model = "R7 A10s hdmi tv-stick";
@@ -59,7 +62,7 @@
59 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_r7>; 62 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_r7>;
60 vmmc-supply = <&reg_vcc3v3>; 63 vmmc-supply = <&reg_vcc3v3>;
61 bus-width = <4>; 64 bus-width = <4>;
62 cd-gpios = <&pio 6 1 0>; /* PG1 */ 65 cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
63 cd-inverted; 66 cd-inverted;
64 status = "okay"; 67 status = "okay";
65 }; 68 };
@@ -90,22 +93,22 @@
90 mmc0_cd_pin_r7: mmc0_cd_pin@0 { 93 mmc0_cd_pin_r7: mmc0_cd_pin@0 {
91 allwinner,pins = "PG1"; 94 allwinner,pins = "PG1";
92 allwinner,function = "gpio_in"; 95 allwinner,function = "gpio_in";
93 allwinner,drive = <0>; 96 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
94 allwinner,pull = <1>; 97 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
95 }; 98 };
96 99
97 led_pins_r7: led_pins@0 { 100 led_pins_r7: led_pins@0 {
98 allwinner,pins = "PB2"; 101 allwinner,pins = "PB2";
99 allwinner,function = "gpio_out"; 102 allwinner,function = "gpio_out";
100 allwinner,drive = <1>; 103 allwinner,drive = <SUN4I_PINCTRL_20_MA>;
101 allwinner,pull = <0>; 104 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
102 }; 105 };
103 106
104 usb1_vbus_pin_r7: usb1_vbus_pin@0 { 107 usb1_vbus_pin_r7: usb1_vbus_pin@0 {
105 allwinner,pins = "PG13"; 108 allwinner,pins = "PG13";
106 allwinner,function = "gpio_out"; 109 allwinner,function = "gpio_out";
107 allwinner,drive = <0>; 110 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
108 allwinner,pull = <0>; 111 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
109 }; 112 };
110 }; 113 };
111 114
@@ -123,14 +126,14 @@
123 126
124 green { 127 green {
125 label = "r7-tv-dongle:green:usr"; 128 label = "r7-tv-dongle:green:usr";
126 gpios = <&pio 1 2 0>; 129 gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>;
127 default-state = "on"; 130 default-state = "on";
128 }; 131 };
129 }; 132 };
130 133
131 reg_usb1_vbus: usb1-vbus { 134 reg_usb1_vbus: usb1-vbus {
132 pinctrl-0 = <&usb1_vbus_pin_r7>; 135 pinctrl-0 = <&usb1_vbus_pin_r7>;
133 gpio = <&pio 6 13 0>; 136 gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>;
134 status = "okay"; 137 status = "okay";
135 }; 138 };
136}; 139};
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 2e7d8263799d..905f84d141f0 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -11,7 +11,10 @@
11 * http://www.gnu.org/copyleft/gpl.html 11 * http://www.gnu.org/copyleft/gpl.html
12 */ 12 */
13 13
14/include/ "skeleton.dtsi" 14#include "skeleton.dtsi"
15
16#include <dt-bindings/dma/sun4i-a10.h>
17#include <dt-bindings/pinctrl/sun4i-a10.h>
15 18
16/ { 19/ {
17 interrupt-parent = <&intc>; 20 interrupt-parent = <&intc>;
@@ -32,6 +35,14 @@
32 <&ahb_gates 44>; 35 <&ahb_gates 44>;
33 status = "disabled"; 36 status = "disabled";
34 }; 37 };
38
39 framebuffer@1 {
40 compatible = "allwinner,simple-framebuffer",
41 "simple-framebuffer";
42 allwinner,pipeline = "de_be0-lcd0";
43 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
44 status = "disabled";
45 };
35 }; 46 };
36 47
37 cpus { 48 cpus {
@@ -316,7 +327,8 @@
316 interrupts = <10>; 327 interrupts = <10>;
317 clocks = <&ahb_gates 20>, <&spi0_clk>; 328 clocks = <&ahb_gates 20>, <&spi0_clk>;
318 clock-names = "ahb", "mod"; 329 clock-names = "ahb", "mod";
319 dmas = <&dma 1 27>, <&dma 1 26>; 330 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
331 <&dma SUN4I_DMA_DEDICATED 26>;
320 dma-names = "rx", "tx"; 332 dma-names = "rx", "tx";
321 status = "disabled"; 333 status = "disabled";
322 #address-cells = <1>; 334 #address-cells = <1>;
@@ -329,7 +341,8 @@
329 interrupts = <11>; 341 interrupts = <11>;
330 clocks = <&ahb_gates 21>, <&spi1_clk>; 342 clocks = <&ahb_gates 21>, <&spi1_clk>;
331 clock-names = "ahb", "mod"; 343 clock-names = "ahb", "mod";
332 dmas = <&dma 1 9>, <&dma 1 8>; 344 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
345 <&dma SUN4I_DMA_DEDICATED 8>;
333 dma-names = "rx", "tx"; 346 dma-names = "rx", "tx";
334 status = "disabled"; 347 status = "disabled";
335 #address-cells = <1>; 348 #address-cells = <1>;
@@ -344,7 +357,7 @@
344 status = "disabled"; 357 status = "disabled";
345 }; 358 };
346 359
347 mdio@01c0b080 { 360 mdio: mdio@01c0b080 {
348 compatible = "allwinner,sun4i-a10-mdio"; 361 compatible = "allwinner,sun4i-a10-mdio";
349 reg = <0x01c0b080 0x14>; 362 reg = <0x01c0b080 0x14>;
350 status = "disabled"; 363 status = "disabled";
@@ -417,7 +430,8 @@
417 interrupts = <12>; 430 interrupts = <12>;
418 clocks = <&ahb_gates 22>, <&spi2_clk>; 431 clocks = <&ahb_gates 22>, <&spi2_clk>;
419 clock-names = "ahb", "mod"; 432 clock-names = "ahb", "mod";
420 dmas = <&dma 1 29>, <&dma 1 28>; 433 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
434 <&dma SUN4I_DMA_DEDICATED 28>;
421 dma-names = "rx", "tx"; 435 dma-names = "rx", "tx";
422 status = "disabled"; 436 status = "disabled";
423 #address-cells = <1>; 437 #address-cells = <1>;
@@ -445,22 +459,22 @@
445 uart0_pins_a: uart0@0 { 459 uart0_pins_a: uart0@0 {
446 allwinner,pins = "PB19", "PB20"; 460 allwinner,pins = "PB19", "PB20";
447 allwinner,function = "uart0"; 461 allwinner,function = "uart0";
448 allwinner,drive = <0>; 462 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
449 allwinner,pull = <0>; 463 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
450 }; 464 };
451 465
452 uart2_pins_a: uart2@0 { 466 uart2_pins_a: uart2@0 {
453 allwinner,pins = "PC18", "PC19"; 467 allwinner,pins = "PC18", "PC19";
454 allwinner,function = "uart2"; 468 allwinner,function = "uart2";
455 allwinner,drive = <0>; 469 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
456 allwinner,pull = <0>; 470 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
457 }; 471 };
458 472
459 uart3_pins_a: uart3@0 { 473 uart3_pins_a: uart3@0 {
460 allwinner,pins = "PG9", "PG10"; 474 allwinner,pins = "PG9", "PG10";
461 allwinner,function = "uart3"; 475 allwinner,function = "uart3";
462 allwinner,drive = <0>; 476 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
463 allwinner,pull = <0>; 477 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
464 }; 478 };
465 479
466 emac_pins_a: emac0@0 { 480 emac_pins_a: emac0@0 {
@@ -470,43 +484,43 @@
470 "PA11", "PA12", "PA13", "PA14", 484 "PA11", "PA12", "PA13", "PA14",
471 "PA15", "PA16"; 485 "PA15", "PA16";
472 allwinner,function = "emac"; 486 allwinner,function = "emac";
473 allwinner,drive = <0>; 487 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
474 allwinner,pull = <0>; 488 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
475 }; 489 };
476 490
477 i2c0_pins_a: i2c0@0 { 491 i2c0_pins_a: i2c0@0 {
478 allwinner,pins = "PB0", "PB1"; 492 allwinner,pins = "PB0", "PB1";
479 allwinner,function = "i2c0"; 493 allwinner,function = "i2c0";
480 allwinner,drive = <0>; 494 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
481 allwinner,pull = <0>; 495 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
482 }; 496 };
483 497
484 i2c1_pins_a: i2c1@0 { 498 i2c1_pins_a: i2c1@0 {
485 allwinner,pins = "PB15", "PB16"; 499 allwinner,pins = "PB15", "PB16";
486 allwinner,function = "i2c1"; 500 allwinner,function = "i2c1";
487 allwinner,drive = <0>; 501 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
488 allwinner,pull = <0>; 502 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
489 }; 503 };
490 504
491 i2c2_pins_a: i2c2@0 { 505 i2c2_pins_a: i2c2@0 {
492 allwinner,pins = "PB17", "PB18"; 506 allwinner,pins = "PB17", "PB18";
493 allwinner,function = "i2c2"; 507 allwinner,function = "i2c2";
494 allwinner,drive = <0>; 508 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
495 allwinner,pull = <0>; 509 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
496 }; 510 };
497 511
498 mmc0_pins_a: mmc0@0 { 512 mmc0_pins_a: mmc0@0 {
499 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; 513 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
500 allwinner,function = "mmc0"; 514 allwinner,function = "mmc0";
501 allwinner,drive = <2>; 515 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
502 allwinner,pull = <0>; 516 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
503 }; 517 };
504 518
505 mmc1_pins_a: mmc1@0 { 519 mmc1_pins_a: mmc1@0 {
506 allwinner,pins = "PG3","PG4","PG5","PG6","PG7","PG8"; 520 allwinner,pins = "PG3","PG4","PG5","PG6","PG7","PG8";
507 allwinner,function = "mmc1"; 521 allwinner,function = "mmc1";
508 allwinner,drive = <2>; 522 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
509 allwinner,pull = <0>; 523 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
510 }; 524 };
511 }; 525 };
512 526
@@ -522,6 +536,13 @@
522 reg = <0x01c20c90 0x10>; 536 reg = <0x01c20c90 0x10>;
523 }; 537 };
524 538
539 lradc: lradc@01c22800 {
540 compatible = "allwinner,sun4i-a10-lradc-keys";
541 reg = <0x01c22800 0x100>;
542 interrupts = <31>;
543 status = "disabled";
544 };
545
525 sid: eeprom@01c23800 { 546 sid: eeprom@01c23800 {
526 compatible = "allwinner,sun4i-a10-sid"; 547 compatible = "allwinner,sun4i-a10-sid";
527 reg = <0x01c23800 0x10>; 548 reg = <0x01c23800 0x10>;
@@ -531,6 +552,7 @@
531 compatible = "allwinner,sun4i-a10-ts"; 552 compatible = "allwinner,sun4i-a10-ts";
532 reg = <0x01c25000 0x100>; 553 reg = <0x01c25000 0x100>;
533 interrupts = <29>; 554 interrupts = <29>;
555 #thermal-sensor-cells = <0>;
534 }; 556 };
535 557
536 uart0: serial@01c28000 { 558 uart0: serial@01c28000 {
diff --git a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
index c7be3abd9fcc..03aa04555630 100644
--- a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
+++ b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
@@ -46,8 +46,11 @@
46 */ 46 */
47 47
48/dts-v1/; 48/dts-v1/;
49/include/ "sun5i-a13.dtsi" 49#include "sun5i-a13.dtsi"
50/include/ "sunxi-common-regulators.dtsi" 50#include "sunxi-common-regulators.dtsi"
51
52#include <dt-bindings/gpio/gpio.h>
53#include <dt-bindings/pinctrl/sun4i-a10.h>
51 54
52/ { 55/ {
53 model = "HSG H702"; 56 model = "HSG H702";
@@ -63,17 +66,13 @@
63 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_h702>; 66 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_h702>;
64 vmmc-supply = <&reg_vcc3v3>; 67 vmmc-supply = <&reg_vcc3v3>;
65 bus-width = <4>; 68 bus-width = <4>;
66 cd-gpios = <&pio 6 0 0>; /* PG0 */ 69 cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
67 cd-inverted; 70 cd-inverted;
68 status = "okay"; 71 status = "okay";
69 }; 72 };
70 73
71 usbphy: phy@01c13400 { 74 usbphy: phy@01c13400 {
72 /* 75 usb1_vbus-supply = <&reg_ldo3>;
73 * There doesn't seem to be a GPIO for controlling
74 * usb1 vbus, despite the fex file saying otherwise.
75 */
76 usb1_vbus-supply = <&reg_vcc5v0>;
77 status = "okay"; 76 status = "okay";
78 }; 77 };
79 78
@@ -89,8 +88,8 @@
89 mmc0_cd_pin_h702: mmc0_cd_pin@0 { 88 mmc0_cd_pin_h702: mmc0_cd_pin@0 {
90 allwinner,pins = "PG0"; 89 allwinner,pins = "PG0";
91 allwinner,function = "gpio_in"; 90 allwinner,function = "gpio_in";
92 allwinner,drive = <0>; 91 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
93 allwinner,pull = <1>; 92 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
94 }; 93 };
95 }; 94 };
96 95
@@ -106,11 +105,8 @@
106 status = "okay"; 105 status = "okay";
107 106
108 axp209: pmic@34 { 107 axp209: pmic@34 {
109 compatible = "x-powers,axp209";
110 reg = <0x34>; 108 reg = <0x34>;
111 interrupts = <0>; 109 interrupts = <0>;
112 interrupt-controller;
113 #interrupt-cells = <1>;
114 }; 110 };
115 }; 111 };
116 112
@@ -132,3 +128,40 @@
132 }; 128 };
133 }; 129 };
134}; 130};
131
132#include "axp209.dtsi"
133
134&cpu0 {
135 cpu-supply = <&reg_dcdc2>;
136};
137
138&reg_dcdc2 {
139 regulator-always-on;
140 regulator-min-microvolt = <1000000>;
141 regulator-max-microvolt = <1500000>;
142 regulator-name = "vdd-cpu";
143};
144
145&reg_dcdc3 {
146 regulator-always-on;
147 regulator-min-microvolt = <1000000>;
148 regulator-max-microvolt = <1400000>;
149 regulator-name = "vdd-int-dll";
150};
151
152&reg_ldo1 {
153 regulator-name = "vdd-rtc";
154};
155
156&reg_ldo2 {
157 regulator-always-on;
158 regulator-min-microvolt = <3000000>;
159 regulator-max-microvolt = <3000000>;
160 regulator-name = "avcc";
161};
162
163&reg_ldo3 {
164 regulator-min-microvolt = <3300000>;
165 regulator-max-microvolt = <3300000>;
166 regulator-name = "vcc-wifi";
167};
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
index 3decefb3c37a..03deb84268ce 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
@@ -47,8 +47,11 @@
47 */ 47 */
48 48
49/dts-v1/; 49/dts-v1/;
50/include/ "sun5i-a13.dtsi" 50#include "sun5i-a13.dtsi"
51/include/ "sunxi-common-regulators.dtsi" 51#include "sunxi-common-regulators.dtsi"
52
53#include <dt-bindings/gpio/gpio.h>
54#include <dt-bindings/pinctrl/sun4i-a10.h>
52 55
53/ { 56/ {
54 model = "Olimex A13-Olinuxino Micro"; 57 model = "Olimex A13-Olinuxino Micro";
@@ -64,7 +67,7 @@
64 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxinom>; 67 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxinom>;
65 vmmc-supply = <&reg_vcc3v3>; 68 vmmc-supply = <&reg_vcc3v3>;
66 bus-width = <4>; 69 bus-width = <4>;
67 cd-gpios = <&pio 6 0 0>; /* PG0 */ 70 cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
68 cd-inverted; 71 cd-inverted;
69 status = "okay"; 72 status = "okay";
70 }; 73 };
@@ -86,22 +89,22 @@
86 mmc0_cd_pin_olinuxinom: mmc0_cd_pin@0 { 89 mmc0_cd_pin_olinuxinom: mmc0_cd_pin@0 {
87 allwinner,pins = "PG0"; 90 allwinner,pins = "PG0";
88 allwinner,function = "gpio_in"; 91 allwinner,function = "gpio_in";
89 allwinner,drive = <0>; 92 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
90 allwinner,pull = <1>; 93 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
91 }; 94 };
92 95
93 led_pins_olinuxinom: led_pins@0 { 96 led_pins_olinuxinom: led_pins@0 {
94 allwinner,pins = "PG9"; 97 allwinner,pins = "PG9";
95 allwinner,function = "gpio_out"; 98 allwinner,function = "gpio_out";
96 allwinner,drive = <1>; 99 allwinner,drive = <SUN4I_PINCTRL_20_MA>;
97 allwinner,pull = <0>; 100 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
98 }; 101 };
99 102
100 usb1_vbus_pin_olinuxinom: usb1_vbus_pin@0 { 103 usb1_vbus_pin_olinuxinom: usb1_vbus_pin@0 {
101 allwinner,pins = "PG11"; 104 allwinner,pins = "PG11";
102 allwinner,function = "gpio_out"; 105 allwinner,function = "gpio_out";
103 allwinner,drive = <0>; 106 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
104 allwinner,pull = <0>; 107 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
105 }; 108 };
106 }; 109 };
107 110
@@ -137,14 +140,14 @@
137 140
138 power { 141 power {
139 label = "a13-olinuxino-micro:green:power"; 142 label = "a13-olinuxino-micro:green:power";
140 gpios = <&pio 6 9 0>; 143 gpios = <&pio 6 9 GPIO_ACTIVE_HIGH>;
141 default-state = "on"; 144 default-state = "on";
142 }; 145 };
143 }; 146 };
144 147
145 reg_usb1_vbus: usb1-vbus { 148 reg_usb1_vbus: usb1-vbus {
146 pinctrl-0 = <&usb1_vbus_pin_olinuxinom>; 149 pinctrl-0 = <&usb1_vbus_pin_olinuxinom>;
147 gpio = <&pio 6 11 0>; 150 gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>;
148 status = "okay"; 151 status = "okay";
149 }; 152 };
150}; 153};
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index b421f7fa197b..6b24876ed462 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -48,8 +48,12 @@
48 */ 48 */
49 49
50/dts-v1/; 50/dts-v1/;
51/include/ "sun5i-a13.dtsi" 51#include "sun5i-a13.dtsi"
52/include/ "sunxi-common-regulators.dtsi" 52#include "sunxi-common-regulators.dtsi"
53
54#include <dt-bindings/gpio/gpio.h>
55#include <dt-bindings/input/input.h>
56#include <dt-bindings/pinctrl/sun4i-a10.h>
53 57
54/ { 58/ {
55 model = "Olimex A13-Olinuxino"; 59 model = "Olimex A13-Olinuxino";
@@ -65,7 +69,7 @@
65 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino>; 69 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino>;
66 vmmc-supply = <&reg_vcc3v3>; 70 vmmc-supply = <&reg_vcc3v3>;
67 bus-width = <4>; 71 bus-width = <4>;
68 cd-gpios = <&pio 6 0 0>; /* PG0 */ 72 cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
69 cd-inverted; 73 cd-inverted;
70 status = "okay"; 74 status = "okay";
71 }; 75 };
@@ -87,22 +91,62 @@
87 mmc0_cd_pin_olinuxino: mmc0_cd_pin@0 { 91 mmc0_cd_pin_olinuxino: mmc0_cd_pin@0 {
88 allwinner,pins = "PG0"; 92 allwinner,pins = "PG0";
89 allwinner,function = "gpio_in"; 93 allwinner,function = "gpio_in";
90 allwinner,drive = <0>; 94 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
91 allwinner,pull = <1>; 95 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
92 }; 96 };
93 97
94 led_pins_olinuxino: led_pins@0 { 98 led_pins_olinuxino: led_pins@0 {
95 allwinner,pins = "PG9"; 99 allwinner,pins = "PG9";
96 allwinner,function = "gpio_out"; 100 allwinner,function = "gpio_out";
97 allwinner,drive = <1>; 101 allwinner,drive = <SUN4I_PINCTRL_20_MA>;
98 allwinner,pull = <0>; 102 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
99 }; 103 };
100 104
101 usb1_vbus_pin_olinuxino: usb1_vbus_pin@0 { 105 usb1_vbus_pin_olinuxino: usb1_vbus_pin@0 {
102 allwinner,pins = "PG11"; 106 allwinner,pins = "PG11";
103 allwinner,function = "gpio_out"; 107 allwinner,function = "gpio_out";
104 allwinner,drive = <0>; 108 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
105 allwinner,pull = <0>; 109 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
110 };
111 };
112
113 lradc: lradc@01c22800 {
114 vref-supply = <&reg_vcc3v0>;
115 status = "okay";
116
117 button@191 {
118 label = "Volume Up";
119 linux,code = <KEY_VOLUMEUP>;
120 channel = <0>;
121 voltage = <191274>;
122 };
123
124 button@392 {
125 label = "Volume Down";
126 linux,code = <KEY_VOLUMEDOWN>;
127 channel = <0>;
128 voltage = <392644>;
129 };
130
131 button@601 {
132 label = "Menu";
133 linux,code = <KEY_MENU>;
134 channel = <0>;
135 voltage = <601151>;
136 };
137
138 button@795 {
139 label = "Enter";
140 linux,code = <KEY_ENTER>;
141 channel = <0>;
142 voltage = <795090>;
143 };
144
145 button@987 {
146 label = "Home";
147 linux,code = <KEY_HOMEPAGE>;
148 channel = <0>;
149 voltage = <987387>;
106 }; 150 };
107 }; 151 };
108 152
@@ -116,6 +160,15 @@
116 pinctrl-names = "default"; 160 pinctrl-names = "default";
117 pinctrl-0 = <&i2c0_pins_a>; 161 pinctrl-0 = <&i2c0_pins_a>;
118 status = "okay"; 162 status = "okay";
163
164 axp209: pmic@34 {
165 compatible = "x-powers,axp209";
166 reg = <0x34>;
167 interrupts = <0>;
168
169 interrupt-controller;
170 #interrupt-cells = <1>;
171 };
119 }; 172 };
120 173
121 i2c1: i2c@01c2b000 { 174 i2c1: i2c@01c2b000 {
@@ -137,14 +190,14 @@
137 pinctrl-0 = <&led_pins_olinuxino>; 190 pinctrl-0 = <&led_pins_olinuxino>;
138 191
139 power { 192 power {
140 gpios = <&pio 6 9 0>; 193 gpios = <&pio 6 9 GPIO_ACTIVE_HIGH>;
141 default-state = "on"; 194 default-state = "on";
142 }; 195 };
143 }; 196 };
144 197
145 reg_usb1_vbus: usb1-vbus { 198 reg_usb1_vbus: usb1-vbus {
146 pinctrl-0 = <&usb1_vbus_pin_olinuxino>; 199 pinctrl-0 = <&usb1_vbus_pin_olinuxino>;
147 gpio = <&pio 6 11 0>; 200 gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>;
148 status = "okay"; 201 status = "okay";
149 }; 202 };
150}; 203};
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index c556688f8b8b..4910393d1b09 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -11,18 +11,85 @@
11 * http://www.gnu.org/copyleft/gpl.html 11 * http://www.gnu.org/copyleft/gpl.html
12 */ 12 */
13 13
14/include/ "skeleton.dtsi" 14#include "skeleton.dtsi"
15
16#include <dt-bindings/thermal/thermal.h>
17
18#include <dt-bindings/dma/sun4i-a10.h>
19#include <dt-bindings/pinctrl/sun4i-a10.h>
15 20
16/ { 21/ {
17 interrupt-parent = <&intc>; 22 interrupt-parent = <&intc>;
18 23
24 chosen {
25 #address-cells = <1>;
26 #size-cells = <1>;
27 ranges;
28
29 framebuffer@0 {
30 compatible = "allwinner,simple-framebuffer",
31 "simple-framebuffer";
32 allwinner,pipeline = "de_be0-lcd0";
33 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
34 status = "disabled";
35 };
36 };
37
19 cpus { 38 cpus {
20 #address-cells = <1>; 39 #address-cells = <1>;
21 #size-cells = <0>; 40 #size-cells = <0>;
22 cpu@0 { 41
42 cpu0: cpu@0 {
23 device_type = "cpu"; 43 device_type = "cpu";
24 compatible = "arm,cortex-a8"; 44 compatible = "arm,cortex-a8";
25 reg = <0x0>; 45 reg = <0x0>;
46 clocks = <&cpu>;
47 clock-latency = <244144>; /* 8 32k periods */
48 operating-points = <
49 /* kHz uV */
50 1104000 1500000
51 1008000 1400000
52 912000 1350000
53 864000 1300000
54 624000 1200000
55 576000 1200000
56 432000 1200000
57 >;
58 #cooling-cells = <2>;
59 cooling-min-level = <0>;
60 cooling-max-level = <6>;
61 };
62 };
63
64 thermal-zones {
65 cpu_thermal {
66 /* milliseconds */
67 polling-delay-passive = <250>;
68 polling-delay = <1000>;
69 thermal-sensors = <&rtp>;
70
71 cooling-maps {
72 map0 {
73 trip = <&cpu_alert0>;
74 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
75 };
76 };
77
78 trips {
79 cpu_alert0: cpu_alert0 {
80 /* milliCelsius */
81 temperature = <850000>;
82 hysteresis = <2000>;
83 type = "passive";
84 };
85
86 cpu_crit: cpu_crit {
87 /* milliCelsius */
88 temperature = <100000>;
89 hysteresis = <2000>;
90 type = "critical";
91 };
92 };
26 }; 93 };
27 }; 94 };
28 95
@@ -299,7 +366,8 @@
299 interrupts = <10>; 366 interrupts = <10>;
300 clocks = <&ahb_gates 20>, <&spi0_clk>; 367 clocks = <&ahb_gates 20>, <&spi0_clk>;
301 clock-names = "ahb", "mod"; 368 clock-names = "ahb", "mod";
302 dmas = <&dma 1 27>, <&dma 1 26>; 369 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
370 <&dma SUN4I_DMA_DEDICATED 26>;
303 dma-names = "rx", "tx"; 371 dma-names = "rx", "tx";
304 status = "disabled"; 372 status = "disabled";
305 #address-cells = <1>; 373 #address-cells = <1>;
@@ -312,7 +380,8 @@
312 interrupts = <11>; 380 interrupts = <11>;
313 clocks = <&ahb_gates 21>, <&spi1_clk>; 381 clocks = <&ahb_gates 21>, <&spi1_clk>;
314 clock-names = "ahb", "mod"; 382 clock-names = "ahb", "mod";
315 dmas = <&dma 1 9>, <&dma 1 8>; 383 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
384 <&dma SUN4I_DMA_DEDICATED 8>;
316 dma-names = "rx", "tx"; 385 dma-names = "rx", "tx";
317 status = "disabled"; 386 status = "disabled";
318 #address-cells = <1>; 387 #address-cells = <1>;
@@ -375,7 +444,8 @@
375 interrupts = <12>; 444 interrupts = <12>;
376 clocks = <&ahb_gates 22>, <&spi2_clk>; 445 clocks = <&ahb_gates 22>, <&spi2_clk>;
377 clock-names = "ahb", "mod"; 446 clock-names = "ahb", "mod";
378 dmas = <&dma 1 29>, <&dma 1 28>; 447 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
448 <&dma SUN4I_DMA_DEDICATED 28>;
379 dma-names = "rx", "tx"; 449 dma-names = "rx", "tx";
380 status = "disabled"; 450 status = "disabled";
381 #address-cells = <1>; 451 #address-cells = <1>;
@@ -403,43 +473,43 @@
403 uart1_pins_a: uart1@0 { 473 uart1_pins_a: uart1@0 {
404 allwinner,pins = "PE10", "PE11"; 474 allwinner,pins = "PE10", "PE11";
405 allwinner,function = "uart1"; 475 allwinner,function = "uart1";
406 allwinner,drive = <0>; 476 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
407 allwinner,pull = <0>; 477 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
408 }; 478 };
409 479
410 uart1_pins_b: uart1@1 { 480 uart1_pins_b: uart1@1 {
411 allwinner,pins = "PG3", "PG4"; 481 allwinner,pins = "PG3", "PG4";
412 allwinner,function = "uart1"; 482 allwinner,function = "uart1";
413 allwinner,drive = <0>; 483 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
414 allwinner,pull = <0>; 484 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
415 }; 485 };
416 486
417 i2c0_pins_a: i2c0@0 { 487 i2c0_pins_a: i2c0@0 {
418 allwinner,pins = "PB0", "PB1"; 488 allwinner,pins = "PB0", "PB1";
419 allwinner,function = "i2c0"; 489 allwinner,function = "i2c0";
420 allwinner,drive = <0>; 490 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
421 allwinner,pull = <0>; 491 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
422 }; 492 };
423 493
424 i2c1_pins_a: i2c1@0 { 494 i2c1_pins_a: i2c1@0 {
425 allwinner,pins = "PB15", "PB16"; 495 allwinner,pins = "PB15", "PB16";
426 allwinner,function = "i2c1"; 496 allwinner,function = "i2c1";
427 allwinner,drive = <0>; 497 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
428 allwinner,pull = <0>; 498 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
429 }; 499 };
430 500
431 i2c2_pins_a: i2c2@0 { 501 i2c2_pins_a: i2c2@0 {
432 allwinner,pins = "PB17", "PB18"; 502 allwinner,pins = "PB17", "PB18";
433 allwinner,function = "i2c2"; 503 allwinner,function = "i2c2";
434 allwinner,drive = <0>; 504 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
435 allwinner,pull = <0>; 505 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
436 }; 506 };
437 507
438 mmc0_pins_a: mmc0@0 { 508 mmc0_pins_a: mmc0@0 {
439 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; 509 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
440 allwinner,function = "mmc0"; 510 allwinner,function = "mmc0";
441 allwinner,drive = <2>; 511 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
442 allwinner,pull = <0>; 512 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
443 }; 513 };
444 }; 514 };
445 515
@@ -455,6 +525,13 @@
455 reg = <0x01c20c90 0x10>; 525 reg = <0x01c20c90 0x10>;
456 }; 526 };
457 527
528 lradc: lradc@01c22800 {
529 compatible = "allwinner,sun4i-a10-lradc-keys";
530 reg = <0x01c22800 0x100>;
531 interrupts = <31>;
532 status = "disabled";
533 };
534
458 sid: eeprom@01c23800 { 535 sid: eeprom@01c23800 {
459 compatible = "allwinner,sun4i-a10-sid"; 536 compatible = "allwinner,sun4i-a10-sid";
460 reg = <0x01c23800 0x10>; 537 reg = <0x01c23800 0x10>;
@@ -464,6 +541,7 @@
464 compatible = "allwinner,sun4i-a10-ts"; 541 compatible = "allwinner,sun4i-a10-ts";
465 reg = <0x01c25000 0x100>; 542 reg = <0x01c25000 0x100>;
466 interrupts = <29>; 543 interrupts = <29>;
544 #thermal-sensor-cells = <0>;
467 }; 545 };
468 546
469 uart1: serial@01c28400 { 547 uart1: serial@01c28400 {
diff --git a/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts b/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts
index c74a63a39531..be9f5ee6b59e 100644
--- a/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts
+++ b/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts
@@ -48,8 +48,11 @@
48 */ 48 */
49 49
50/dts-v1/; 50/dts-v1/;
51/include/ "sun6i-a31.dtsi" 51#include "sun6i-a31.dtsi"
52/include/ "sunxi-common-regulators.dtsi" 52#include "sunxi-common-regulators.dtsi"
53
54#include <dt-bindings/gpio/gpio.h>
55#include <dt-bindings/pinctrl/sun4i-a10.h>
53 56
54/ { 57/ {
55 model = "Allwinner A31 APP4 EVB1 Evaluation Board"; 58 model = "Allwinner A31 APP4 EVB1 Evaluation Board";
@@ -64,8 +67,8 @@
64 usb1_vbus_pin_a: usb1_vbus_pin@0 { 67 usb1_vbus_pin_a: usb1_vbus_pin@0 {
65 allwinner,pins = "PH27"; 68 allwinner,pins = "PH27";
66 allwinner,function = "gpio_out"; 69 allwinner,function = "gpio_out";
67 allwinner,drive = <0>; 70 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
68 allwinner,pull = <0>; 71 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
69 }; 72 };
70 }; 73 };
71 74
@@ -87,7 +90,7 @@
87 90
88 reg_usb1_vbus: usb1-vbus { 91 reg_usb1_vbus: usb1-vbus {
89 pinctrl-0 = <&usb1_vbus_pin_a>; 92 pinctrl-0 = <&usb1_vbus_pin_a>;
90 gpio = <&pio 7 27 0>; 93 gpio = <&pio 7 27 GPIO_ACTIVE_HIGH>;
91 status = "okay"; 94 status = "okay";
92 }; 95 };
93}; 96};
diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/sun6i-a31-colombus.dts
index c36b4dc89c13..84630e56acd7 100644
--- a/arch/arm/boot/dts/sun6i-a31-colombus.dts
+++ b/arch/arm/boot/dts/sun6i-a31-colombus.dts
@@ -48,8 +48,11 @@
48 */ 48 */
49 49
50/dts-v1/; 50/dts-v1/;
51/include/ "sun6i-a31.dtsi" 51#include "sun6i-a31.dtsi"
52/include/ "sunxi-common-regulators.dtsi" 52#include "sunxi-common-regulators.dtsi"
53
54#include <dt-bindings/gpio/gpio.h>
55#include <dt-bindings/pinctrl/sun4i-a10.h>
53 56
54/ { 57/ {
55 model = "WITS A31 Colombus Evaluation Board"; 58 model = "WITS A31 Colombus Evaluation Board";
@@ -65,7 +68,7 @@
65 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_colombus>; 68 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_colombus>;
66 vmmc-supply = <&reg_vcc3v0>; 69 vmmc-supply = <&reg_vcc3v0>;
67 bus-width = <4>; 70 bus-width = <4>;
68 cd-gpios = <&pio 0 8 0>; /* PA8 */ 71 cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */
69 cd-inverted; 72 cd-inverted;
70 status = "okay"; 73 status = "okay";
71 }; 74 };
@@ -81,21 +84,21 @@
81 84
82 pio: pinctrl@01c20800 { 85 pio: pinctrl@01c20800 {
83 mmc0_pins_a: mmc0@0 { 86 mmc0_pins_a: mmc0@0 {
84 allwinner,pull = <1>; 87 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
85 }; 88 };
86 89
87 mmc0_cd_pin_colombus: mmc0_cd_pin@0 { 90 mmc0_cd_pin_colombus: mmc0_cd_pin@0 {
88 allwinner,pins = "PA8"; 91 allwinner,pins = "PA8";
89 allwinner,function = "gpio_in"; 92 allwinner,function = "gpio_in";
90 allwinner,drive = <0>; 93 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
91 allwinner,pull = <1>; 94 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
92 }; 95 };
93 96
94 usb2_vbus_pin_colombus: usb2_vbus_pin@0 { 97 usb2_vbus_pin_colombus: usb2_vbus_pin@0 {
95 allwinner,pins = "PH24"; 98 allwinner,pins = "PH24";
96 allwinner,function = "gpio_out"; 99 allwinner,function = "gpio_out";
97 allwinner,drive = <0>; 100 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
98 allwinner,pull = <0>; 101 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
99 }; 102 };
100 }; 103 };
101 104
@@ -127,7 +130,7 @@
127 reg_usb2_vbus: usb2-vbus { 130 reg_usb2_vbus: usb2-vbus {
128 pinctrl-names = "default"; 131 pinctrl-names = "default";
129 pinctrl-0 = <&usb2_vbus_pin_colombus>; 132 pinctrl-0 = <&usb2_vbus_pin_colombus>;
130 gpio = <&pio 7 24 0>; 133 gpio = <&pio 7 24 GPIO_ACTIVE_HIGH>;
131 status = "okay"; 134 status = "okay";
132 }; 135 };
133}; 136};
diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
index 6e924d9d2912..8b61b1b342e0 100644
--- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
+++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
@@ -48,8 +48,11 @@
48 */ 48 */
49 49
50/dts-v1/; 50/dts-v1/;
51/include/ "sun6i-a31.dtsi" 51#include "sun6i-a31.dtsi"
52/include/ "sunxi-common-regulators.dtsi" 52#include "sunxi-common-regulators.dtsi"
53
54#include <dt-bindings/gpio/gpio.h>
55#include <dt-bindings/pinctrl/sun4i-a10.h>
53 56
54/ { 57/ {
55 model = "Merrii A31 Hummingbird"; 58 model = "Merrii A31 Hummingbird";
@@ -58,98 +61,96 @@
58 chosen { 61 chosen {
59 bootargs = "earlyprintk console=ttyS0,115200"; 62 bootargs = "earlyprintk console=ttyS0,115200";
60 }; 63 };
64};
65
66&ehci0 {
67 status = "okay";
68};
61 69
62 soc@01c00000 { 70&gmac {
63 mmc0: mmc@01c0f000 { 71 pinctrl-names = "default";
64 pinctrl-names = "default"; 72 pinctrl-0 = <&gmac_pins_rgmii_a>;
65 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_hummingbird>; 73 phy = <&phy1>;
66 vmmc-supply = <&reg_vcc3v0>; 74 phy-mode = "rgmii";
67 bus-width = <4>; 75 snps,reset-gpio = <&pio 0 21 GPIO_ACTIVE_HIGH>;
68 cd-gpios = <&pio 0 8 0>; /* PA8 */ 76 snps,reset-active-low;
69 cd-inverted; 77 snps,reset-delays-us = <0 10000 30000>;
70 status = "okay"; 78 status = "okay";
71 }; 79
72 80 phy1: ethernet-phy@1 {
73 usbphy: phy@01c19400 { 81 reg = <1>;
74 usb1_vbus-supply = <&reg_usb1_vbus>;
75 status = "okay";
76 };
77
78 ehci0: usb@01c1a000 {
79 status = "okay";
80 };
81
82 ohci0: usb@01c1a400 {
83 status = "okay";
84 };
85
86 pio: pinctrl@01c20800 {
87 mmc0_pins_a: mmc0@0 {
88 /* external pull-ups missing for some pins */
89 allwinner,pull = <1>;
90 };
91
92 mmc0_cd_pin_hummingbird: mmc0_cd_pin@0 {
93 allwinner,pins = "PA8";
94 allwinner,function = "gpio_in";
95 allwinner,drive = <0>;
96 allwinner,pull = <1>;
97 };
98
99 usb1_vbus_pin_a: usb1_vbus_pin@0 {
100 allwinner,pins = "PH24";
101 allwinner,function = "gpio_out";
102 allwinner,drive = <0>;
103 allwinner,pull = <0>;
104 };
105 };
106
107 uart0: serial@01c28000 {
108 pinctrl-names = "default";
109 pinctrl-0 = <&uart0_pins_a>;
110 status = "okay";
111 };
112
113 i2c0: i2c@01c2ac00 {
114 pinctrl-names = "default";
115 pinctrl-0 = <&i2c0_pins_a>;
116 /* pull-ups and devices require AXP221 DLDO3 */
117 status = "failed";
118 };
119
120 i2c1: i2c@01c2b000 {
121 pinctrl-names = "default";
122 pinctrl-0 = <&i2c1_pins_a>;
123 status = "okay";
124 };
125
126 i2c2: i2c@01c2b400 {
127 pinctrl-names = "default";
128 pinctrl-0 = <&i2c2_pins_a>;
129 status = "okay";
130
131 pcf8563: rtc@51 {
132 compatible = "nxp,pcf8563";
133 reg = <0x51>;
134 };
135 };
136
137 gmac: ethernet@01c30000 {
138 pinctrl-names = "default";
139 pinctrl-0 = <&gmac_pins_rgmii_a>;
140 phy = <&phy1>;
141 phy-mode = "rgmii";
142 status = "okay";
143
144 phy1: ethernet-phy@1 {
145 reg = <1>;
146 };
147 };
148 }; 82 };
83};
84
85&i2c0 {
86 pinctrl-names = "default";
87 pinctrl-0 = <&i2c0_pins_a>;
88 /* pull-ups and devices require AXP221 DLDO3 */
89 status = "failed";
90};
149 91
150 reg_usb1_vbus: usb1-vbus { 92&i2c1 {
151 pinctrl-0 = <&usb1_vbus_pin_a>; 93 pinctrl-names = "default";
152 gpio = <&pio 7 24 0>; /* PH24 */ 94 pinctrl-0 = <&i2c1_pins_a>;
153 status = "okay"; 95 status = "okay";
96};
97
98&i2c2 {
99 pinctrl-names = "default";
100 pinctrl-0 = <&i2c2_pins_a>;
101 status = "okay";
102
103 pcf8563: rtc@51 {
104 compatible = "nxp,pcf8563";
105 reg = <0x51>;
154 }; 106 };
155}; 107};
108
109&mmc0 {
110 pinctrl-names = "default";
111 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_hummingbird>;
112 vmmc-supply = <&reg_vcc3v0>;
113 bus-width = <4>;
114 cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */
115 cd-inverted;
116 status = "okay";
117};
118
119&mmc0_pins_a {
120 /* external pull-ups missing for some pins */
121 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
122};
123
124&ohci0 {
125 status = "okay";
126};
127
128&pio {
129 mmc0_cd_pin_hummingbird: mmc0_cd_pin@0 {
130 allwinner,pins = "PA8";
131 allwinner,function = "gpio_in";
132 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
133 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
134 };
135};
136
137&reg_usb1_vbus {
138 gpio = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */
139 status = "okay";
140};
141
142&uart0 {
143 pinctrl-names = "default";
144 pinctrl-0 = <&uart0_pins_a>;
145 status = "okay";
146};
147
148&usb1_vbus_pin_a {
149 /* different pin from sunxi-common-regulators */
150 allwinner,pins = "PH24";
151};
152
153&usbphy {
154 usb1_vbus-supply = <&reg_usb1_vbus>;
155 status = "okay";
156};
diff --git a/arch/arm/boot/dts/sun6i-a31-m9.dts b/arch/arm/boot/dts/sun6i-a31-m9.dts
index 3ab544f3af4a..139a21e6b695 100644
--- a/arch/arm/boot/dts/sun6i-a31-m9.dts
+++ b/arch/arm/boot/dts/sun6i-a31-m9.dts
@@ -46,8 +46,11 @@
46 */ 46 */
47 47
48/dts-v1/; 48/dts-v1/;
49/include/ "sun6i-a31.dtsi" 49#include "sun6i-a31.dtsi"
50/include/ "sunxi-common-regulators.dtsi" 50#include "sunxi-common-regulators.dtsi"
51
52#include <dt-bindings/gpio/gpio.h>
53#include <dt-bindings/pinctrl/sun4i-a10.h>
51 54
52/ { 55/ {
53 model = "Mele M9 / A1000G Quad top set box"; 56 model = "Mele M9 / A1000G Quad top set box";
@@ -63,7 +66,7 @@
63 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_m9>; 66 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_m9>;
64 vmmc-supply = <&reg_vcc3v3>; 67 vmmc-supply = <&reg_vcc3v3>;
65 bus-width = <4>; 68 bus-width = <4>;
66 cd-gpios = <&pio 7 22 0>; /* PH22 */ 69 cd-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
67 cd-inverted; 70 cd-inverted;
68 status = "okay"; 71 status = "okay";
69 }; 72 };
@@ -85,22 +88,22 @@
85 led_pins_m9: led_pins@0 { 88 led_pins_m9: led_pins@0 {
86 allwinner,pins = "PH13"; 89 allwinner,pins = "PH13";
87 allwinner,function = "gpio_out"; 90 allwinner,function = "gpio_out";
88 allwinner,drive = <0>; 91 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
89 allwinner,pull = <0>; 92 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
90 }; 93 };
91 94
92 mmc0_cd_pin_m9: mmc0_cd_pin@0 { 95 mmc0_cd_pin_m9: mmc0_cd_pin@0 {
93 allwinner,pins = "PH22"; 96 allwinner,pins = "PH22";
94 allwinner,function = "gpio_in"; 97 allwinner,function = "gpio_in";
95 allwinner,drive = <0>; 98 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
96 allwinner,pull = <1>; 99 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
97 }; 100 };
98 101
99 usb1_vbus_pin_m9: usb1_vbus_pin@0 { 102 usb1_vbus_pin_m9: usb1_vbus_pin@0 {
100 allwinner,pins = "PC27"; 103 allwinner,pins = "PC27";
101 allwinner,function = "gpio_out"; 104 allwinner,function = "gpio_out";
102 allwinner,drive = <0>; 105 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
103 allwinner,pull = <0>; 106 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
104 }; 107 };
105 }; 108 };
106 109
@@ -121,6 +124,12 @@
121 reg = <1>; 124 reg = <1>;
122 }; 125 };
123 }; 126 };
127
128 ir@01f02000 {
129 pinctrl-names = "default";
130 pinctrl-0 = <&ir_pins_a>;
131 status = "okay";
132 };
124 }; 133 };
125 134
126 leds { 135 leds {
@@ -130,14 +139,14 @@
130 139
131 blue { 140 blue {
132 label = "m9:blue:usr"; 141 label = "m9:blue:usr";
133 gpios = <&pio 7 13 0>; 142 gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>;
134 }; 143 };
135 }; 144 };
136 145
137 reg_usb1_vbus: usb1-vbus { 146 reg_usb1_vbus: usb1-vbus {
138 pinctrl-names = "default"; 147 pinctrl-names = "default";
139 pinctrl-0 = <&usb1_vbus_pin_m9>; 148 pinctrl-0 = <&usb1_vbus_pin_m9>;
140 gpio = <&pio 2 27 0>; 149 gpio = <&pio 2 27 GPIO_ACTIVE_HIGH>;
141 status = "okay"; 150 status = "okay";
142 }; 151 };
143}; 152};
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 1e7e7bcf8307..47e557656993 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -47,7 +47,11 @@
47 * OTHER DEALINGS IN THE SOFTWARE. 47 * OTHER DEALINGS IN THE SOFTWARE.
48 */ 48 */
49 49
50/include/ "skeleton.dtsi" 50#include "skeleton.dtsi"
51
52#include <dt-bindings/interrupt-controller/arm-gic.h>
53
54#include <dt-bindings/pinctrl/sun4i-a10.h>
51 55
52/ { 56/ {
53 interrupt-parent = <&gic>; 57 interrupt-parent = <&gic>;
@@ -67,6 +71,24 @@
67 clocks = <&pll6 0>; 71 clocks = <&pll6 0>;
68 status = "disabled"; 72 status = "disabled";
69 }; 73 };
74
75 framebuffer@1 {
76 compatible = "allwinner,simple-framebuffer",
77 "simple-framebuffer";
78 allwinner,pipeline = "de_be0-lcd0";
79 clocks = <&pll6 0>;
80 status = "disabled";
81 };
82 };
83
84 timer {
85 compatible = "arm,armv7-timer";
86 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
87 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
88 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
89 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
90 clock-frequency = <24000000>;
91 arm,cpu-registers-not-fw-configured;
70 }; 92 };
71 93
72 cpus { 94 cpus {
@@ -105,10 +127,10 @@
105 127
106 pmu { 128 pmu {
107 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; 129 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
108 interrupts = <0 120 4>, 130 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
109 <0 121 4>, 131 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
110 <0 122 4>, 132 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
111 <0 123 4>; 133 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
112 }; 134 };
113 135
114 clocks { 136 clocks {
@@ -355,7 +377,7 @@
355 dma: dma-controller@01c02000 { 377 dma: dma-controller@01c02000 {
356 compatible = "allwinner,sun6i-a31-dma"; 378 compatible = "allwinner,sun6i-a31-dma";
357 reg = <0x01c02000 0x1000>; 379 reg = <0x01c02000 0x1000>;
358 interrupts = <0 50 4>; 380 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&ahb1_gates 6>; 381 clocks = <&ahb1_gates 6>;
360 resets = <&ahb1_rst 6>; 382 resets = <&ahb1_rst 6>;
361 #dma-cells = <1>; 383 #dma-cells = <1>;
@@ -372,7 +394,7 @@
372 clock-names = "ahb", "mmc"; 394 clock-names = "ahb", "mmc";
373 resets = <&ahb1_rst 8>; 395 resets = <&ahb1_rst 8>;
374 reset-names = "ahb"; 396 reset-names = "ahb";
375 interrupts = <0 60 4>; 397 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
376 status = "disabled"; 398 status = "disabled";
377 }; 399 };
378 400
@@ -383,7 +405,7 @@
383 clock-names = "ahb", "mmc"; 405 clock-names = "ahb", "mmc";
384 resets = <&ahb1_rst 9>; 406 resets = <&ahb1_rst 9>;
385 reset-names = "ahb"; 407 reset-names = "ahb";
386 interrupts = <0 61 4>; 408 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
387 status = "disabled"; 409 status = "disabled";
388 }; 410 };
389 411
@@ -394,7 +416,7 @@
394 clock-names = "ahb", "mmc"; 416 clock-names = "ahb", "mmc";
395 resets = <&ahb1_rst 10>; 417 resets = <&ahb1_rst 10>;
396 reset-names = "ahb"; 418 reset-names = "ahb";
397 interrupts = <0 62 4>; 419 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
398 status = "disabled"; 420 status = "disabled";
399 }; 421 };
400 422
@@ -405,7 +427,7 @@
405 clock-names = "ahb", "mmc"; 427 clock-names = "ahb", "mmc";
406 resets = <&ahb1_rst 11>; 428 resets = <&ahb1_rst 11>;
407 reset-names = "ahb"; 429 reset-names = "ahb";
408 interrupts = <0 63 4>; 430 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
409 status = "disabled"; 431 status = "disabled";
410 }; 432 };
411 433
@@ -436,7 +458,7 @@
436 ehci0: usb@01c1a000 { 458 ehci0: usb@01c1a000 {
437 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; 459 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
438 reg = <0x01c1a000 0x100>; 460 reg = <0x01c1a000 0x100>;
439 interrupts = <0 72 4>; 461 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&ahb1_gates 26>; 462 clocks = <&ahb1_gates 26>;
441 resets = <&ahb1_rst 26>; 463 resets = <&ahb1_rst 26>;
442 phys = <&usbphy 1>; 464 phys = <&usbphy 1>;
@@ -447,7 +469,7 @@
447 ohci0: usb@01c1a400 { 469 ohci0: usb@01c1a400 {
448 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; 470 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
449 reg = <0x01c1a400 0x100>; 471 reg = <0x01c1a400 0x100>;
450 interrupts = <0 73 4>; 472 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
451 clocks = <&ahb1_gates 29>, <&usb_clk 16>; 473 clocks = <&ahb1_gates 29>, <&usb_clk 16>;
452 resets = <&ahb1_rst 29>; 474 resets = <&ahb1_rst 29>;
453 phys = <&usbphy 1>; 475 phys = <&usbphy 1>;
@@ -458,7 +480,7 @@
458 ehci1: usb@01c1b000 { 480 ehci1: usb@01c1b000 {
459 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; 481 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
460 reg = <0x01c1b000 0x100>; 482 reg = <0x01c1b000 0x100>;
461 interrupts = <0 74 4>; 483 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&ahb1_gates 27>; 484 clocks = <&ahb1_gates 27>;
463 resets = <&ahb1_rst 27>; 485 resets = <&ahb1_rst 27>;
464 phys = <&usbphy 2>; 486 phys = <&usbphy 2>;
@@ -469,7 +491,7 @@
469 ohci1: usb@01c1b400 { 491 ohci1: usb@01c1b400 {
470 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; 492 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
471 reg = <0x01c1b400 0x100>; 493 reg = <0x01c1b400 0x100>;
472 interrupts = <0 75 4>; 494 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
473 clocks = <&ahb1_gates 30>, <&usb_clk 17>; 495 clocks = <&ahb1_gates 30>, <&usb_clk 17>;
474 resets = <&ahb1_rst 30>; 496 resets = <&ahb1_rst 30>;
475 phys = <&usbphy 2>; 497 phys = <&usbphy 2>;
@@ -480,7 +502,7 @@
480 ohci2: usb@01c1c400 { 502 ohci2: usb@01c1c400 {
481 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; 503 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
482 reg = <0x01c1c400 0x100>; 504 reg = <0x01c1c400 0x100>;
483 interrupts = <0 77 4>; 505 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
484 clocks = <&ahb1_gates 31>, <&usb_clk 18>; 506 clocks = <&ahb1_gates 31>, <&usb_clk 18>;
485 resets = <&ahb1_rst 31>; 507 resets = <&ahb1_rst 31>;
486 status = "disabled"; 508 status = "disabled";
@@ -489,10 +511,10 @@
489 pio: pinctrl@01c20800 { 511 pio: pinctrl@01c20800 {
490 compatible = "allwinner,sun6i-a31-pinctrl"; 512 compatible = "allwinner,sun6i-a31-pinctrl";
491 reg = <0x01c20800 0x400>; 513 reg = <0x01c20800 0x400>;
492 interrupts = <0 11 4>, 514 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
493 <0 15 4>, 515 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
494 <0 16 4>, 516 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
495 <0 17 4>; 517 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
496 clocks = <&apb1_gates 5>; 518 clocks = <&apb1_gates 5>;
497 gpio-controller; 519 gpio-controller;
498 interrupt-controller; 520 interrupt-controller;
@@ -503,36 +525,36 @@
503 uart0_pins_a: uart0@0 { 525 uart0_pins_a: uart0@0 {
504 allwinner,pins = "PH20", "PH21"; 526 allwinner,pins = "PH20", "PH21";
505 allwinner,function = "uart0"; 527 allwinner,function = "uart0";
506 allwinner,drive = <0>; 528 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
507 allwinner,pull = <0>; 529 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
508 }; 530 };
509 531
510 i2c0_pins_a: i2c0@0 { 532 i2c0_pins_a: i2c0@0 {
511 allwinner,pins = "PH14", "PH15"; 533 allwinner,pins = "PH14", "PH15";
512 allwinner,function = "i2c0"; 534 allwinner,function = "i2c0";
513 allwinner,drive = <0>; 535 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
514 allwinner,pull = <0>; 536 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
515 }; 537 };
516 538
517 i2c1_pins_a: i2c1@0 { 539 i2c1_pins_a: i2c1@0 {
518 allwinner,pins = "PH16", "PH17"; 540 allwinner,pins = "PH16", "PH17";
519 allwinner,function = "i2c1"; 541 allwinner,function = "i2c1";
520 allwinner,drive = <0>; 542 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
521 allwinner,pull = <0>; 543 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
522 }; 544 };
523 545
524 i2c2_pins_a: i2c2@0 { 546 i2c2_pins_a: i2c2@0 {
525 allwinner,pins = "PH18", "PH19"; 547 allwinner,pins = "PH18", "PH19";
526 allwinner,function = "i2c2"; 548 allwinner,function = "i2c2";
527 allwinner,drive = <0>; 549 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
528 allwinner,pull = <0>; 550 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
529 }; 551 };
530 552
531 mmc0_pins_a: mmc0@0 { 553 mmc0_pins_a: mmc0@0 {
532 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; 554 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
533 allwinner,function = "mmc0"; 555 allwinner,function = "mmc0";
534 allwinner,drive = <2>; 556 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
535 allwinner,pull = <0>; 557 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
536 }; 558 };
537 559
538 gmac_pins_mii_a: gmac_mii@0 { 560 gmac_pins_mii_a: gmac_mii@0 {
@@ -542,8 +564,8 @@
542 "PA20", "PA21", "PA22", "PA23", 564 "PA20", "PA21", "PA22", "PA23",
543 "PA24", "PA26", "PA27"; 565 "PA24", "PA26", "PA27";
544 allwinner,function = "gmac"; 566 allwinner,function = "gmac";
545 allwinner,drive = <0>; 567 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
546 allwinner,pull = <0>; 568 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
547 }; 569 };
548 570
549 gmac_pins_gmii_a: gmac_gmii@0 { 571 gmac_pins_gmii_a: gmac_gmii@0 {
@@ -559,8 +581,8 @@
559 * data lines in GMII mode run at 125MHz and 581 * data lines in GMII mode run at 125MHz and
560 * might need a higher signal drive strength 582 * might need a higher signal drive strength
561 */ 583 */
562 allwinner,drive = <2>; 584 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
563 allwinner,pull = <0>; 585 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
564 }; 586 };
565 587
566 gmac_pins_rgmii_a: gmac_rgmii@0 { 588 gmac_pins_rgmii_a: gmac_rgmii@0 {
@@ -573,8 +595,8 @@
573 * data lines in RGMII mode use DDR mode 595 * data lines in RGMII mode use DDR mode
574 * and need a higher signal drive strength 596 * and need a higher signal drive strength
575 */ 597 */
576 allwinner,drive = <3>; 598 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
577 allwinner,pull = <0>; 599 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
578 }; 600 };
579 }; 601 };
580 602
@@ -599,11 +621,11 @@
599 timer@01c20c00 { 621 timer@01c20c00 {
600 compatible = "allwinner,sun4i-a10-timer"; 622 compatible = "allwinner,sun4i-a10-timer";
601 reg = <0x01c20c00 0xa0>; 623 reg = <0x01c20c00 0xa0>;
602 interrupts = <0 18 4>, 624 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
603 <0 19 4>, 625 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
604 <0 20 4>, 626 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
605 <0 21 4>, 627 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
606 <0 22 4>; 628 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
607 clocks = <&osc24M>; 629 clocks = <&osc24M>;
608 }; 630 };
609 631
@@ -612,10 +634,17 @@
612 reg = <0x01c20ca0 0x20>; 634 reg = <0x01c20ca0 0x20>;
613 }; 635 };
614 636
637 rtp: rtp@01c25000 {
638 compatible = "allwinner,sun6i-a31-ts";
639 reg = <0x01c25000 0x100>;
640 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
641 #thermal-sensor-cells = <0>;
642 };
643
615 uart0: serial@01c28000 { 644 uart0: serial@01c28000 {
616 compatible = "snps,dw-apb-uart"; 645 compatible = "snps,dw-apb-uart";
617 reg = <0x01c28000 0x400>; 646 reg = <0x01c28000 0x400>;
618 interrupts = <0 0 4>; 647 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
619 reg-shift = <2>; 648 reg-shift = <2>;
620 reg-io-width = <4>; 649 reg-io-width = <4>;
621 clocks = <&apb2_gates 16>; 650 clocks = <&apb2_gates 16>;
@@ -628,7 +657,7 @@
628 uart1: serial@01c28400 { 657 uart1: serial@01c28400 {
629 compatible = "snps,dw-apb-uart"; 658 compatible = "snps,dw-apb-uart";
630 reg = <0x01c28400 0x400>; 659 reg = <0x01c28400 0x400>;
631 interrupts = <0 1 4>; 660 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
632 reg-shift = <2>; 661 reg-shift = <2>;
633 reg-io-width = <4>; 662 reg-io-width = <4>;
634 clocks = <&apb2_gates 17>; 663 clocks = <&apb2_gates 17>;
@@ -641,7 +670,7 @@
641 uart2: serial@01c28800 { 670 uart2: serial@01c28800 {
642 compatible = "snps,dw-apb-uart"; 671 compatible = "snps,dw-apb-uart";
643 reg = <0x01c28800 0x400>; 672 reg = <0x01c28800 0x400>;
644 interrupts = <0 2 4>; 673 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
645 reg-shift = <2>; 674 reg-shift = <2>;
646 reg-io-width = <4>; 675 reg-io-width = <4>;
647 clocks = <&apb2_gates 18>; 676 clocks = <&apb2_gates 18>;
@@ -654,7 +683,7 @@
654 uart3: serial@01c28c00 { 683 uart3: serial@01c28c00 {
655 compatible = "snps,dw-apb-uart"; 684 compatible = "snps,dw-apb-uart";
656 reg = <0x01c28c00 0x400>; 685 reg = <0x01c28c00 0x400>;
657 interrupts = <0 3 4>; 686 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
658 reg-shift = <2>; 687 reg-shift = <2>;
659 reg-io-width = <4>; 688 reg-io-width = <4>;
660 clocks = <&apb2_gates 19>; 689 clocks = <&apb2_gates 19>;
@@ -667,7 +696,7 @@
667 uart4: serial@01c29000 { 696 uart4: serial@01c29000 {
668 compatible = "snps,dw-apb-uart"; 697 compatible = "snps,dw-apb-uart";
669 reg = <0x01c29000 0x400>; 698 reg = <0x01c29000 0x400>;
670 interrupts = <0 4 4>; 699 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
671 reg-shift = <2>; 700 reg-shift = <2>;
672 reg-io-width = <4>; 701 reg-io-width = <4>;
673 clocks = <&apb2_gates 20>; 702 clocks = <&apb2_gates 20>;
@@ -680,7 +709,7 @@
680 uart5: serial@01c29400 { 709 uart5: serial@01c29400 {
681 compatible = "snps,dw-apb-uart"; 710 compatible = "snps,dw-apb-uart";
682 reg = <0x01c29400 0x400>; 711 reg = <0x01c29400 0x400>;
683 interrupts = <0 5 4>; 712 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
684 reg-shift = <2>; 713 reg-shift = <2>;
685 reg-io-width = <4>; 714 reg-io-width = <4>;
686 clocks = <&apb2_gates 21>; 715 clocks = <&apb2_gates 21>;
@@ -693,7 +722,7 @@
693 i2c0: i2c@01c2ac00 { 722 i2c0: i2c@01c2ac00 {
694 compatible = "allwinner,sun6i-a31-i2c"; 723 compatible = "allwinner,sun6i-a31-i2c";
695 reg = <0x01c2ac00 0x400>; 724 reg = <0x01c2ac00 0x400>;
696 interrupts = <0 6 4>; 725 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
697 clocks = <&apb2_gates 0>; 726 clocks = <&apb2_gates 0>;
698 resets = <&apb2_rst 0>; 727 resets = <&apb2_rst 0>;
699 status = "disabled"; 728 status = "disabled";
@@ -704,7 +733,7 @@
704 i2c1: i2c@01c2b000 { 733 i2c1: i2c@01c2b000 {
705 compatible = "allwinner,sun6i-a31-i2c"; 734 compatible = "allwinner,sun6i-a31-i2c";
706 reg = <0x01c2b000 0x400>; 735 reg = <0x01c2b000 0x400>;
707 interrupts = <0 7 4>; 736 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
708 clocks = <&apb2_gates 1>; 737 clocks = <&apb2_gates 1>;
709 resets = <&apb2_rst 1>; 738 resets = <&apb2_rst 1>;
710 status = "disabled"; 739 status = "disabled";
@@ -715,7 +744,7 @@
715 i2c2: i2c@01c2b400 { 744 i2c2: i2c@01c2b400 {
716 compatible = "allwinner,sun6i-a31-i2c"; 745 compatible = "allwinner,sun6i-a31-i2c";
717 reg = <0x01c2b400 0x400>; 746 reg = <0x01c2b400 0x400>;
718 interrupts = <0 8 4>; 747 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
719 clocks = <&apb2_gates 2>; 748 clocks = <&apb2_gates 2>;
720 resets = <&apb2_rst 2>; 749 resets = <&apb2_rst 2>;
721 status = "disabled"; 750 status = "disabled";
@@ -726,7 +755,7 @@
726 i2c3: i2c@01c2b800 { 755 i2c3: i2c@01c2b800 {
727 compatible = "allwinner,sun6i-a31-i2c"; 756 compatible = "allwinner,sun6i-a31-i2c";
728 reg = <0x01c2b800 0x400>; 757 reg = <0x01c2b800 0x400>;
729 interrupts = <0 9 4>; 758 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
730 clocks = <&apb2_gates 3>; 759 clocks = <&apb2_gates 3>;
731 resets = <&apb2_rst 3>; 760 resets = <&apb2_rst 3>;
732 status = "disabled"; 761 status = "disabled";
@@ -737,7 +766,7 @@
737 gmac: ethernet@01c30000 { 766 gmac: ethernet@01c30000 {
738 compatible = "allwinner,sun7i-a20-gmac"; 767 compatible = "allwinner,sun7i-a20-gmac";
739 reg = <0x01c30000 0x1054>; 768 reg = <0x01c30000 0x1054>;
740 interrupts = <0 82 4>; 769 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
741 interrupt-names = "macirq"; 770 interrupt-names = "macirq";
742 clocks = <&ahb1_gates 17>, <&gmac_tx_clk>; 771 clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
743 clock-names = "stmmaceth", "allwinner_gmac_tx"; 772 clock-names = "stmmaceth", "allwinner_gmac_tx";
@@ -754,10 +783,10 @@
754 timer@01c60000 { 783 timer@01c60000 {
755 compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer"; 784 compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer";
756 reg = <0x01c60000 0x1000>; 785 reg = <0x01c60000 0x1000>;
757 interrupts = <0 51 4>, 786 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
758 <0 52 4>, 787 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
759 <0 53 4>, 788 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
760 <0 54 4>; 789 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
761 clocks = <&ahb1_gates 19>; 790 clocks = <&ahb1_gates 19>;
762 resets = <&ahb1_rst 19>; 791 resets = <&ahb1_rst 19>;
763 }; 792 };
@@ -765,7 +794,7 @@
765 spi0: spi@01c68000 { 794 spi0: spi@01c68000 {
766 compatible = "allwinner,sun6i-a31-spi"; 795 compatible = "allwinner,sun6i-a31-spi";
767 reg = <0x01c68000 0x1000>; 796 reg = <0x01c68000 0x1000>;
768 interrupts = <0 65 4>; 797 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
769 clocks = <&ahb1_gates 20>, <&spi0_clk>; 798 clocks = <&ahb1_gates 20>, <&spi0_clk>;
770 clock-names = "ahb", "mod"; 799 clock-names = "ahb", "mod";
771 dmas = <&dma 23>, <&dma 23>; 800 dmas = <&dma 23>, <&dma 23>;
@@ -777,7 +806,7 @@
777 spi1: spi@01c69000 { 806 spi1: spi@01c69000 {
778 compatible = "allwinner,sun6i-a31-spi"; 807 compatible = "allwinner,sun6i-a31-spi";
779 reg = <0x01c69000 0x1000>; 808 reg = <0x01c69000 0x1000>;
780 interrupts = <0 66 4>; 809 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
781 clocks = <&ahb1_gates 21>, <&spi1_clk>; 810 clocks = <&ahb1_gates 21>, <&spi1_clk>;
782 clock-names = "ahb", "mod"; 811 clock-names = "ahb", "mod";
783 dmas = <&dma 24>, <&dma 24>; 812 dmas = <&dma 24>, <&dma 24>;
@@ -789,7 +818,7 @@
789 spi2: spi@01c6a000 { 818 spi2: spi@01c6a000 {
790 compatible = "allwinner,sun6i-a31-spi"; 819 compatible = "allwinner,sun6i-a31-spi";
791 reg = <0x01c6a000 0x1000>; 820 reg = <0x01c6a000 0x1000>;
792 interrupts = <0 67 4>; 821 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
793 clocks = <&ahb1_gates 22>, <&spi2_clk>; 822 clocks = <&ahb1_gates 22>, <&spi2_clk>;
794 clock-names = "ahb", "mod"; 823 clock-names = "ahb", "mod";
795 dmas = <&dma 25>, <&dma 25>; 824 dmas = <&dma 25>, <&dma 25>;
@@ -801,7 +830,7 @@
801 spi3: spi@01c6b000 { 830 spi3: spi@01c6b000 {
802 compatible = "allwinner,sun6i-a31-spi"; 831 compatible = "allwinner,sun6i-a31-spi";
803 reg = <0x01c6b000 0x1000>; 832 reg = <0x01c6b000 0x1000>;
804 interrupts = <0 68 4>; 833 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
805 clocks = <&ahb1_gates 23>, <&spi3_clk>; 834 clocks = <&ahb1_gates 23>, <&spi3_clk>;
806 clock-names = "ahb", "mod"; 835 clock-names = "ahb", "mod";
807 dmas = <&dma 26>, <&dma 26>; 836 dmas = <&dma 26>, <&dma 26>;
@@ -818,13 +847,14 @@
818 <0x01c86000 0x2000>; 847 <0x01c86000 0x2000>;
819 interrupt-controller; 848 interrupt-controller;
820 #interrupt-cells = <3>; 849 #interrupt-cells = <3>;
821 interrupts = <1 9 0xf04>; 850 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
822 }; 851 };
823 852
824 rtc: rtc@01f00000 { 853 rtc: rtc@01f00000 {
825 compatible = "allwinner,sun6i-a31-rtc"; 854 compatible = "allwinner,sun6i-a31-rtc";
826 reg = <0x01f00000 0x54>; 855 reg = <0x01f00000 0x54>;
827 interrupts = <0 40 4>, <0 41 4>; 856 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
857 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
828 }; 858 };
829 859
830 nmi_intc: interrupt-controller@01f00c0c { 860 nmi_intc: interrupt-controller@01f00c0c {
@@ -832,7 +862,7 @@
832 interrupt-controller; 862 interrupt-controller;
833 #interrupt-cells = <2>; 863 #interrupt-cells = <2>;
834 reg = <0x01f00c0c 0x38>; 864 reg = <0x01f00c0c 0x38>;
835 interrupts = <0 32 4>; 865 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
836 }; 866 };
837 867
838 prcm@01f01400 { 868 prcm@01f01400 {
@@ -872,6 +902,13 @@
872 "apb0_i2c"; 902 "apb0_i2c";
873 }; 903 };
874 904
905 ir_clk: ir_clk {
906 #clock-cells = <0>;
907 compatible = "allwinner,sun4i-a10-mod0-clk";
908 clocks = <&osc32k>, <&osc24M>;
909 clock-output-names = "ir";
910 };
911
875 apb0_rst: apb0_rst { 912 apb0_rst: apb0_rst {
876 compatible = "allwinner,sun6i-a31-clock-reset"; 913 compatible = "allwinner,sun6i-a31-clock-reset";
877 #reset-cells = <1>; 914 #reset-cells = <1>;
@@ -883,11 +920,21 @@
883 reg = <0x01f01c00 0x300>; 920 reg = <0x01f01c00 0x300>;
884 }; 921 };
885 922
923 ir: ir@01f02000 {
924 compatible = "allwinner,sun5i-a13-ir";
925 clocks = <&apb0_gates 1>, <&ir_clk>;
926 clock-names = "apb", "ir";
927 resets = <&apb0_rst 1>;
928 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
929 reg = <0x01f02000 0x40>;
930 status = "disabled";
931 };
932
886 r_pio: pinctrl@01f02c00 { 933 r_pio: pinctrl@01f02c00 {
887 compatible = "allwinner,sun6i-a31-r-pinctrl"; 934 compatible = "allwinner,sun6i-a31-r-pinctrl";
888 reg = <0x01f02c00 0x400>; 935 reg = <0x01f02c00 0x400>;
889 interrupts = <0 45 4>, 936 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
890 <0 46 4>; 937 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
891 clocks = <&apb0_gates 0>; 938 clocks = <&apb0_gates 0>;
892 resets = <&apb0_rst 0>; 939 resets = <&apb0_rst 0>;
893 gpio-controller; 940 gpio-controller;
@@ -895,6 +942,13 @@
895 #interrupt-cells = <2>; 942 #interrupt-cells = <2>;
896 #size-cells = <0>; 943 #size-cells = <0>;
897 #gpio-cells = <3>; 944 #gpio-cells = <3>;
945
946 ir_pins_a: ir@0 {
947 allwinner,pins = "PL4";
948 allwinner,function = "s_ir";
949 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
950 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
951 };
898 }; 952 };
899 }; 953 };
900}; 954};
diff --git a/arch/arm/boot/dts/sun6i-a31s-cs908.dts b/arch/arm/boot/dts/sun6i-a31s-cs908.dts
new file mode 100644
index 000000000000..bc3734f67cf0
--- /dev/null
+++ b/arch/arm/boot/dts/sun6i-a31s-cs908.dts
@@ -0,0 +1,104 @@
1/*
2 * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this library; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48/dts-v1/;
49#include "sun6i-a31s.dtsi"
50
51#include <dt-bindings/pinctrl/sun4i-a10.h>
52
53/ {
54 model = "CSQ CS908 top set box";
55 compatible = "csq,cs908", "allwinner,sun6i-a31s";
56};
57
58&usbphy {
59 status = "okay";
60};
61
62&ehci0 {
63 status = "okay";
64};
65
66&ehci1 {
67 status = "okay";
68};
69
70&ohci1 {
71 status = "okay";
72};
73
74&pio {
75 usb1_vbus_pin_csq908: usb1_vbus_pin@0 {
76 allwinner,pins = "PC27";
77 allwinner,function = "gpio_out";
78 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
79 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
80 };
81};
82
83&uart0 {
84 pinctrl-names = "default";
85 pinctrl-0 = <&uart0_pins_a>;
86 status = "okay";
87};
88
89&gmac {
90 pinctrl-names = "default";
91 pinctrl-0 = <&gmac_pins_mii_a>;
92 phy = <&phy1>;
93 phy-mode = "mii";
94 status = "okay";
95 phy1: ethernet-phy@1 {
96 reg = <1>;
97 };
98};
99
100&ir {
101 pinctrl-names = "default";
102 pinctrl-0 = <&ir_pins_a>;
103 status = "okay";
104};
diff --git a/arch/arm/boot/dts/sun6i-a31s.dtsi b/arch/arm/boot/dts/sun6i-a31s.dtsi
new file mode 100644
index 000000000000..eaf5ec8fd459
--- /dev/null
+++ b/arch/arm/boot/dts/sun6i-a31s.dtsi
@@ -0,0 +1,58 @@
1/*
2 * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this library; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48/*
49 * The A31s is the same die as the A31 in a different package, this is
50 * reflected by it having different pinctrl compatible everything else is
51 * identical.
52 */
53
54#include "sun6i-a31.dtsi"
55
56&pio {
57 compatible = "allwinner,sun6i-a31s-pinctrl";
58};
diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi.dts b/arch/arm/boot/dts/sun7i-a20-bananapi.dts
index bd7b15add697..5dd139e7792e 100644
--- a/arch/arm/boot/dts/sun7i-a20-bananapi.dts
+++ b/arch/arm/boot/dts/sun7i-a20-bananapi.dts
@@ -48,8 +48,12 @@
48 */ 48 */
49 49
50/dts-v1/; 50/dts-v1/;
51/include/ "sun7i-a20.dtsi" 51#include "sun7i-a20.dtsi"
52/include/ "sunxi-common-regulators.dtsi" 52#include "sunxi-common-regulators.dtsi"
53
54#include <dt-bindings/gpio/gpio.h>
55#include <dt-bindings/interrupt-controller/irq.h>
56#include <dt-bindings/pinctrl/sun4i-a10.h>
53 57
54/ { 58/ {
55 model = "LeMaker Banana Pi"; 59 model = "LeMaker Banana Pi";
@@ -73,7 +77,7 @@
73 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapi>; 77 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapi>;
74 vmmc-supply = <&reg_vcc3v3>; 78 vmmc-supply = <&reg_vcc3v3>;
75 bus-width = <4>; 79 bus-width = <4>;
76 cd-gpios = <&pio 7 10 0>; /* PH10 */ 80 cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
77 cd-inverted; 81 cd-inverted;
78 status = "okay"; 82 status = "okay";
79 }; 83 };
@@ -108,22 +112,22 @@
108 mmc0_cd_pin_bananapi: mmc0_cd_pin@0 { 112 mmc0_cd_pin_bananapi: mmc0_cd_pin@0 {
109 allwinner,pins = "PH10"; 113 allwinner,pins = "PH10";
110 allwinner,function = "gpio_in"; 114 allwinner,function = "gpio_in";
111 allwinner,drive = <0>; 115 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
112 allwinner,pull = <1>; 116 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
113 }; 117 };
114 118
115 gmac_power_pin_bananapi: gmac_power_pin@0 { 119 gmac_power_pin_bananapi: gmac_power_pin@0 {
116 allwinner,pins = "PH23"; 120 allwinner,pins = "PH23";
117 allwinner,function = "gpio_out"; 121 allwinner,function = "gpio_out";
118 allwinner,drive = <0>; 122 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
119 allwinner,pull = <0>; 123 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
120 }; 124 };
121 125
122 led_pins_bananapi: led_pins@0 { 126 led_pins_bananapi: led_pins@0 {
123 allwinner,pins = "PH24"; 127 allwinner,pins = "PH24";
124 allwinner,function = "gpio_out"; 128 allwinner,function = "gpio_out";
125 allwinner,drive = <0>; 129 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
126 allwinner,pull = <0>; 130 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
127 }; 131 };
128 }; 132 };
129 133
@@ -160,7 +164,7 @@
160 compatible = "x-powers,axp209"; 164 compatible = "x-powers,axp209";
161 reg = <0x34>; 165 reg = <0x34>;
162 interrupt-parent = <&nmi_intc>; 166 interrupt-parent = <&nmi_intc>;
163 interrupts = <0 8>; 167 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
164 168
165 interrupt-controller; 169 interrupt-controller;
166 #interrupt-cells = <1>; 170 #interrupt-cells = <1>;
@@ -194,7 +198,7 @@
194 198
195 green { 199 green {
196 label = "bananapi:green:usr"; 200 label = "bananapi:green:usr";
197 gpios = <&pio 7 24 0>; 201 gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>;
198 }; 202 };
199 }; 203 };
200 204
@@ -215,6 +219,6 @@
215 regulator-max-microvolt = <3300000>; 219 regulator-max-microvolt = <3300000>;
216 startup-delay-us = <100000>; 220 startup-delay-us = <100000>;
217 enable-active-high; 221 enable-active-high;
218 gpio = <&pio 7 23 0>; 222 gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>;
219 }; 223 };
220}; 224};
diff --git a/arch/arm/boot/dts/sun7i-a20-bananapro.dts b/arch/arm/boot/dts/sun7i-a20-bananapro.dts
new file mode 100644
index 000000000000..fb89fe7ed21b
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-bananapro.dts
@@ -0,0 +1,262 @@
1/*
2 * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48/dts-v1/;
49#include "sun7i-a20.dtsi"
50#include "sunxi-common-regulators.dtsi"
51#include <dt-bindings/gpio/gpio.h>
52#include <dt-bindings/interrupt-controller/arm-gic.h>
53
54/ {
55 model = "LeMaker Banana Pro";
56 compatible = "lemaker,bananapro", "allwinner,sun7i-a20";
57
58 leds {
59 compatible = "gpio-leds";
60 pinctrl-names = "default";
61 pinctrl-0 = <&led_pins_bananapro>;
62
63 blue {
64 label = "bananapro:blue:usr";
65 gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>;
66 };
67
68 green {
69 label = "bananapro:green:usr";
70 gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>;
71 };
72 };
73
74 reg_gmac_3v3: gmac-3v3 {
75 compatible = "regulator-fixed";
76 pinctrl-names = "default";
77 pinctrl-0 = <&gmac_power_pin_bananapro>;
78 regulator-name = "gmac-3v3";
79 regulator-min-microvolt = <3300000>;
80 regulator-max-microvolt = <3300000>;
81 startup-delay-us = <100000>;
82 enable-active-high;
83 gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>;
84 };
85
86 reg_vmmc3: vmmc3 {
87 compatible = "regulator-fixed";
88 pinctrl-names = "default";
89 pinctrl-0 = <&vmmc3_pin_bananapro>;
90 regulator-name = "vmmc3";
91 regulator-min-microvolt = <3300000>;
92 regulator-max-microvolt = <3300000>;
93 enable-active-high;
94 gpio = <&pio 7 22 GPIO_ACTIVE_HIGH>;
95 };
96};
97
98&ahci {
99 status = "okay";
100};
101
102&ehci0 {
103 status = "okay";
104};
105
106&ehci1 {
107 status = "okay";
108};
109
110&gmac {
111 pinctrl-names = "default";
112 pinctrl-0 = <&gmac_pins_rgmii_a>;
113 phy = <&phy1>;
114 phy-mode = "rgmii";
115 phy-supply = <&reg_gmac_3v3>;
116 status = "okay";
117
118 phy1: ethernet-phy@1 {
119 reg = <1>;
120 };
121};
122
123&i2c0 {
124 pinctrl-names = "default";
125 pinctrl-0 = <&i2c0_pins_a>;
126 status = "okay";
127
128 axp209: pmic@34 {
129 compatible = "x-powers,axp209";
130 reg = <0x34>;
131 interrupt-parent = <&nmi_intc>;
132 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
133
134 interrupt-controller;
135 #interrupt-cells = <1>;
136 };
137};
138
139&i2c2 {
140 pinctrl-names = "default";
141 pinctrl-0 = <&i2c2_pins_a>;
142 status = "okay";
143};
144
145&ir0 {
146 pinctrl-names = "default";
147 pinctrl-0 = <&ir0_pins_a>;
148 status = "okay";
149};
150
151&mmc0 {
152 pinctrl-names = "default";
153 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapro>;
154 vmmc-supply = <&reg_vcc3v3>;
155 bus-width = <4>;
156 cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
157 cd-inverted;
158 status = "okay";
159};
160
161&mmc3 {
162 pinctrl-names = "default";
163 pinctrl-0 = <&mmc3_pins_a>;
164 vmmc-supply = <&reg_vmmc3>;
165 bus-width = <4>;
166 non-removable;
167 status = "okay";
168};
169
170&ohci0 {
171 status = "okay";
172};
173
174&ohci1 {
175 status = "okay";
176};
177
178&pio {
179 gmac_power_pin_bananapro: gmac_power_pin@0 {
180 allwinner,pins = "PH23";
181 allwinner,function = "gpio_out";
182 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
183 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
184 };
185
186 led_pins_bananapro: led_pins@0 {
187 allwinner,pins = "PH24", "PG2";
188 allwinner,function = "gpio_out";
189 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
190 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
191 };
192
193 mmc0_cd_pin_bananapro: mmc0_cd_pin@0 {
194 allwinner,pins = "PH10";
195 allwinner,function = "gpio_in";
196 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
197 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
198 };
199
200 usb1_vbus_pin_bananapro: usb1_vbus_pin@0 {
201 allwinner,pins = "PH0";
202 allwinner,function = "gpio_out";
203 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
204 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
205 };
206
207 usb2_vbus_pin_bananapro: usb2_vbus_pin@0 {
208 allwinner,pins = "PH1";
209 allwinner,function = "gpio_out";
210 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
211 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
212 };
213
214 vmmc3_pin_bananapro: vmmc3_pin@0 {
215 allwinner,pins = "PH22";
216 allwinner,function = "gpio_out";
217 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
218 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
219 };
220};
221
222&reg_usb1_vbus {
223 pinctrl-0 = <&usb1_vbus_pin_bananapro>;
224 gpio = <&pio 7 0 GPIO_ACTIVE_HIGH>; /* PH0 */
225 status = "okay";
226};
227
228&reg_usb2_vbus {
229 pinctrl-0 = <&usb2_vbus_pin_bananapro>;
230 gpio = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
231 status = "okay";
232};
233
234&spi0 {
235 pinctrl-names = "default";
236 pinctrl-0 = <&spi0_pins_a>;
237 status = "okay";
238};
239
240&uart0 {
241 pinctrl-names = "default";
242 pinctrl-0 = <&uart0_pins_a>;
243 status = "okay";
244};
245
246&uart2 {
247 pinctrl-names = "default";
248 pinctrl-0 = <&uart2_pins_a>;
249 status = "okay";
250};
251
252&uart7 {
253 pinctrl-names = "default";
254 pinctrl-0 = <&uart7_pins_a>;
255 status = "okay";
256};
257
258&usbphy {
259 usb1_vbus-supply = <&reg_usb1_vbus>;
260 usb2_vbus-supply = <&reg_usb2_vbus>;
261 status = "okay";
262};
diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
index 53680983461a..c4ab6edb6f15 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
@@ -3,17 +3,57 @@
3 * 3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com> 4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 * 5 *
6 * The code contained herein is licensed under the GNU General Public 6 * This file is dual-licensed: you can use it either under the terms
7 * License. You may obtain a copy of the GNU General Public License 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * Version 2 or later at the following locations: 8 * licensing only applies to this file, and not this project as a
9 * whole.
9 * 10 *
10 * http://www.opensource.org/licenses/gpl-license.html 11 * a) This file is free software; you can redistribute it and/or
11 * http://www.gnu.org/copyleft/gpl.html 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
12 */ 48 */
13 49
14/dts-v1/; 50/dts-v1/;
15/include/ "sun7i-a20.dtsi" 51#include "sun7i-a20.dtsi"
16/include/ "sunxi-common-regulators.dtsi" 52#include "sunxi-common-regulators.dtsi"
53
54#include <dt-bindings/gpio/gpio.h>
55#include <dt-bindings/interrupt-controller/irq.h>
56#include <dt-bindings/pinctrl/sun4i-a10.h>
17 57
18/ { 58/ {
19 model = "Cubietech Cubieboard2"; 59 model = "Cubietech Cubieboard2";
@@ -25,7 +65,7 @@
25 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; 65 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
26 vmmc-supply = <&reg_vcc3v3>; 66 vmmc-supply = <&reg_vcc3v3>;
27 bus-width = <4>; 67 bus-width = <4>;
28 cd-gpios = <&pio 7 1 0>; /* PH1 */ 68 cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
29 cd-inverted; 69 cd-inverted;
30 status = "okay"; 70 status = "okay";
31 }; 71 };
@@ -61,8 +101,8 @@
61 led_pins_cubieboard2: led_pins@0 { 101 led_pins_cubieboard2: led_pins@0 {
62 allwinner,pins = "PH20", "PH21"; 102 allwinner,pins = "PH20", "PH21";
63 allwinner,function = "gpio_out"; 103 allwinner,function = "gpio_out";
64 allwinner,drive = <0>; 104 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
65 allwinner,pull = <0>; 105 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
66 }; 106 };
67 }; 107 };
68 108
@@ -84,13 +124,9 @@
84 status = "okay"; 124 status = "okay";
85 125
86 axp209: pmic@34 { 126 axp209: pmic@34 {
87 compatible = "x-powers,axp209";
88 reg = <0x34>; 127 reg = <0x34>;
89 interrupt-parent = <&nmi_intc>; 128 interrupt-parent = <&nmi_intc>;
90 interrupts = <0 8>; 129 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
91
92 interrupt-controller;
93 #interrupt-cells = <1>;
94 }; 130 };
95 }; 131 };
96 132
@@ -120,12 +156,12 @@
120 156
121 blue { 157 blue {
122 label = "cubieboard2:blue:usr"; 158 label = "cubieboard2:blue:usr";
123 gpios = <&pio 7 21 0>; 159 gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>;
124 }; 160 };
125 161
126 green { 162 green {
127 label = "cubieboard2:green:usr"; 163 label = "cubieboard2:green:usr";
128 gpios = <&pio 7 20 0>; 164 gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
129 }; 165 };
130 }; 166 };
131 167
@@ -141,3 +177,34 @@
141 status = "okay"; 177 status = "okay";
142 }; 178 };
143}; 179};
180
181#include "axp209.dtsi"
182
183&cpu0 {
184 cpu-supply = <&reg_dcdc2>;
185};
186
187&reg_dcdc2 {
188 regulator-always-on;
189 regulator-min-microvolt = <1000000>;
190 regulator-max-microvolt = <1450000>;
191 regulator-name = "vdd-cpu";
192};
193
194&reg_dcdc3 {
195 regulator-always-on;
196 regulator-min-microvolt = <1000000>;
197 regulator-max-microvolt = <1400000>;
198 regulator-name = "vdd-int-dll";
199};
200
201&reg_ldo1 {
202 regulator-name = "vdd-rtc";
203};
204
205&reg_ldo2 {
206 regulator-always-on;
207 regulator-min-microvolt = <3000000>;
208 regulator-max-microvolt = <3000000>;
209 regulator-name = "avcc";
210};
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index a281d259b9b8..8f74a649576d 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
@@ -3,17 +3,57 @@
3 * 3 *
4 * Oliver Schinagl <oliver@schinagl.nl> 4 * Oliver Schinagl <oliver@schinagl.nl>
5 * 5 *
6 * The code contained herein is licensed under the GNU General Public 6 * This file is dual-licensed: you can use it either under the terms
7 * License. You may obtain a copy of the GNU General Public License 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * Version 2 or later at the following locations: 8 * licensing only applies to this file, and not this project as a
9 * whole.
9 * 10 *
10 * http://www.opensource.org/licenses/gpl-license.html 11 * a) This file is free software; you can redistribute it and/or
11 * http://www.gnu.org/copyleft/gpl.html 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
12 */ 48 */
13 49
14/dts-v1/; 50/dts-v1/;
15/include/ "sun7i-a20.dtsi" 51#include "sun7i-a20.dtsi"
16/include/ "sunxi-common-regulators.dtsi" 52#include "sunxi-common-regulators.dtsi"
53
54#include <dt-bindings/gpio/gpio.h>
55#include <dt-bindings/interrupt-controller/irq.h>
56#include <dt-bindings/pinctrl/sun4i-a10.h>
17 57
18/ { 58/ {
19 model = "Cubietech Cubietruck"; 59 model = "Cubietech Cubietruck";
@@ -25,7 +65,7 @@
25 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; 65 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
26 vmmc-supply = <&reg_vcc3v3>; 66 vmmc-supply = <&reg_vcc3v3>;
27 bus-width = <4>; 67 bus-width = <4>;
28 cd-gpios = <&pio 7 1 0>; /* PH1 */ 68 cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
29 cd-inverted; 69 cd-inverted;
30 status = "okay"; 70 status = "okay";
31 }; 71 };
@@ -70,35 +110,35 @@
70 pinctrl@01c20800 { 110 pinctrl@01c20800 {
71 mmc3_pins_a: mmc3@0 { 111 mmc3_pins_a: mmc3@0 {
72 /* AP6210 requires pull-up */ 112 /* AP6210 requires pull-up */
73 allwinner,pull = <1>; 113 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
74 }; 114 };
75 115
76 vmmc3_pin_cubietruck: vmmc3_pin@0 { 116 vmmc3_pin_cubietruck: vmmc3_pin@0 {
77 allwinner,pins = "PH9"; 117 allwinner,pins = "PH9";
78 allwinner,function = "gpio_out"; 118 allwinner,function = "gpio_out";
79 allwinner,drive = <0>; 119 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
80 allwinner,pull = <0>; 120 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
81 }; 121 };
82 122
83 ahci_pwr_pin_cubietruck: ahci_pwr_pin@1 { 123 ahci_pwr_pin_cubietruck: ahci_pwr_pin@1 {
84 allwinner,pins = "PH12"; 124 allwinner,pins = "PH12";
85 allwinner,function = "gpio_out"; 125 allwinner,function = "gpio_out";
86 allwinner,drive = <0>; 126 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
87 allwinner,pull = <0>; 127 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
88 }; 128 };
89 129
90 led_pins_cubietruck: led_pins@0 { 130 led_pins_cubietruck: led_pins@0 {
91 allwinner,pins = "PH7", "PH11", "PH20", "PH21"; 131 allwinner,pins = "PH7", "PH11", "PH20", "PH21";
92 allwinner,function = "gpio_out"; 132 allwinner,function = "gpio_out";
93 allwinner,drive = <0>; 133 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
94 allwinner,pull = <0>; 134 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
95 }; 135 };
96 136
97 usb0_vbus_pin_a: usb0_vbus_pin@0 { 137 usb0_vbus_pin_a: usb0_vbus_pin@0 {
98 allwinner,pins = "PH17"; 138 allwinner,pins = "PH17";
99 allwinner,function = "gpio_out"; 139 allwinner,function = "gpio_out";
100 allwinner,drive = <0>; 140 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
101 allwinner,pull = <0>; 141 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
102 }; 142 };
103 }; 143 };
104 144
@@ -126,13 +166,9 @@
126 status = "okay"; 166 status = "okay";
127 167
128 axp209: pmic@34 { 168 axp209: pmic@34 {
129 compatible = "x-powers,axp209";
130 reg = <0x34>; 169 reg = <0x34>;
131 interrupt-parent = <&nmi_intc>; 170 interrupt-parent = <&nmi_intc>;
132 interrupts = <0 8>; 171 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
133
134 interrupt-controller;
135 #interrupt-cells = <1>;
136 }; 172 };
137 }; 173 };
138 174
@@ -168,34 +204,34 @@
168 204
169 blue { 205 blue {
170 label = "cubietruck:blue:usr"; 206 label = "cubietruck:blue:usr";
171 gpios = <&pio 7 21 0>; 207 gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>;
172 }; 208 };
173 209
174 orange { 210 orange {
175 label = "cubietruck:orange:usr"; 211 label = "cubietruck:orange:usr";
176 gpios = <&pio 7 20 0>; 212 gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
177 }; 213 };
178 214
179 white { 215 white {
180 label = "cubietruck:white:usr"; 216 label = "cubietruck:white:usr";
181 gpios = <&pio 7 11 0>; 217 gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>;
182 }; 218 };
183 219
184 green { 220 green {
185 label = "cubietruck:green:usr"; 221 label = "cubietruck:green:usr";
186 gpios = <&pio 7 7 0>; 222 gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>;
187 }; 223 };
188 }; 224 };
189 225
190 reg_ahci_5v: ahci-5v { 226 reg_ahci_5v: ahci-5v {
191 pinctrl-0 = <&ahci_pwr_pin_cubietruck>; 227 pinctrl-0 = <&ahci_pwr_pin_cubietruck>;
192 gpio = <&pio 7 12 0>; 228 gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>;
193 status = "okay"; 229 status = "okay";
194 }; 230 };
195 231
196 reg_usb0_vbus: usb0-vbus { 232 reg_usb0_vbus: usb0-vbus {
197 pinctrl-0 = <&usb0_vbus_pin_a>; 233 pinctrl-0 = <&usb0_vbus_pin_a>;
198 gpio = <&pio 7 17 0>; 234 gpio = <&pio 7 17 GPIO_ACTIVE_HIGH>;
199 status = "okay"; 235 status = "okay";
200 }; 236 };
201 237
@@ -215,6 +251,37 @@
215 regulator-min-microvolt = <3300000>; 251 regulator-min-microvolt = <3300000>;
216 regulator-max-microvolt = <3300000>; 252 regulator-max-microvolt = <3300000>;
217 enable-active-high; 253 enable-active-high;
218 gpio = <&pio 7 9 0>; 254 gpio = <&pio 7 9 GPIO_ACTIVE_HIGH>;
219 }; 255 };
220}; 256};
257
258#include "axp209.dtsi"
259
260&cpu0 {
261 cpu-supply = <&reg_dcdc2>;
262};
263
264&reg_dcdc2 {
265 regulator-always-on;
266 regulator-min-microvolt = <1000000>;
267 regulator-max-microvolt = <1450000>;
268 regulator-name = "vdd-cpu";
269};
270
271&reg_dcdc3 {
272 regulator-always-on;
273 regulator-min-microvolt = <1000000>;
274 regulator-max-microvolt = <1400000>;
275 regulator-name = "vdd-int-dll";
276};
277
278&reg_ldo1 {
279 regulator-name = "vdd-rtc";
280};
281
282&reg_ldo2 {
283 regulator-always-on;
284 regulator-min-microvolt = <3000000>;
285 regulator-max-microvolt = <3000000>;
286 regulator-name = "avcc";
287};
diff --git a/arch/arm/boot/dts/sun7i-a20-hummingbird.dts b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts
index 0bcefcbbb756..86a944ce19f8 100644
--- a/arch/arm/boot/dts/sun7i-a20-hummingbird.dts
+++ b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts
@@ -12,8 +12,12 @@
12 */ 12 */
13 13
14/dts-v1/; 14/dts-v1/;
15/include/ "sun7i-a20.dtsi" 15#include "sun7i-a20.dtsi"
16/include/ "sunxi-common-regulators.dtsi" 16#include "sunxi-common-regulators.dtsi"
17
18#include <dt-bindings/gpio/gpio.h>
19#include <dt-bindings/interrupt-controller/irq.h>
20#include <dt-bindings/pinctrl/sun4i-a10.h>
17 21
18/ { 22/ {
19 model = "Merrii A20 Hummingbird"; 23 model = "Merrii A20 Hummingbird";
@@ -33,7 +37,7 @@
33 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; 37 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
34 vmmc-supply = <&reg_vcc3v0>; 38 vmmc-supply = <&reg_vcc3v0>;
35 bus-width = <4>; 39 bus-width = <4>;
36 cd-gpios = <&pio 7 1 0>; /* PH1 */ 40 cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
37 cd-inverted; 41 cd-inverted;
38 status = "okay"; 42 status = "okay";
39 }; 43 };
@@ -78,29 +82,29 @@
78 ahci_pwr_pin_a20_hummingbird: ahci_pwr_pin@0 { 82 ahci_pwr_pin_a20_hummingbird: ahci_pwr_pin@0 {
79 allwinner,pins = "PH15"; 83 allwinner,pins = "PH15";
80 allwinner,function = "gpio_out"; 84 allwinner,function = "gpio_out";
81 allwinner,drive = <0>; 85 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
82 allwinner,pull = <0>; 86 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
83 }; 87 };
84 88
85 usb1_vbus_pin_a20_hummingbird: usb1_vbus_pin@0 { 89 usb1_vbus_pin_a20_hummingbird: usb1_vbus_pin@0 {
86 allwinner,pins = "PH2"; 90 allwinner,pins = "PH2";
87 allwinner,function = "gpio_out"; 91 allwinner,function = "gpio_out";
88 allwinner,drive = <0>; 92 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
89 allwinner,pull = <0>; 93 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
90 }; 94 };
91 95
92 mmc3_vdd_pin_a20_hummingbird: mmc3_vdd_pin@0 { 96 mmc3_vdd_pin_a20_hummingbird: mmc3_vdd_pin@0 {
93 allwinner,pins = "PH9"; 97 allwinner,pins = "PH9";
94 allwinner,function = "gpio_out"; 98 allwinner,function = "gpio_out";
95 allwinner,drive = <0>; 99 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
96 allwinner,pull = <0>; 100 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
97 }; 101 };
98 102
99 gmac_vdd_pin_a20_hummingbird: gmac_vdd_pin@0 { 103 gmac_vdd_pin_a20_hummingbird: gmac_vdd_pin@0 {
100 allwinner,pins = "PH16"; 104 allwinner,pins = "PH16";
101 allwinner,function = "gpio_out"; 105 allwinner,function = "gpio_out";
102 allwinner,drive = <0>; 106 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
103 allwinner,pull = <0>; 107 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
104 }; 108 };
105 }; 109 };
106 110
@@ -155,7 +159,7 @@
155 compatible = "x-powers,axp209"; 159 compatible = "x-powers,axp209";
156 reg = <0x34>; 160 reg = <0x34>;
157 interrupt-parent = <&nmi_intc>; 161 interrupt-parent = <&nmi_intc>;
158 interrupts = <0 8>; 162 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
159 interrupt-controller; 163 interrupt-controller;
160 #interrupt-cells = <1>; 164 #interrupt-cells = <1>;
161 }; 165 };
@@ -192,7 +196,7 @@
192 phy-mode = "rgmii"; 196 phy-mode = "rgmii";
193 phy-supply = <&reg_gmac_vdd>; 197 phy-supply = <&reg_gmac_vdd>;
194 /* phy reset config */ 198 /* phy reset config */
195 snps,reset-gpio = <&pio 0 17 0>; /* PA17 */ 199 snps,reset-gpio = <&pio 0 17 GPIO_ACTIVE_HIGH>; /* PA17 */
196 snps,reset-active-low; 200 snps,reset-active-low;
197 /* wait 1s after reset, otherwise fail to read phy id */ 201 /* wait 1s after reset, otherwise fail to read phy id */
198 snps,reset-delays-us = <0 10000 1000000>; 202 snps,reset-delays-us = <0 10000 1000000>;
@@ -206,13 +210,13 @@
206 210
207 reg_ahci_5v: ahci-5v { 211 reg_ahci_5v: ahci-5v {
208 pinctrl-0 = <&ahci_pwr_pin_a20_hummingbird>; 212 pinctrl-0 = <&ahci_pwr_pin_a20_hummingbird>;
209 gpio = <&pio 7 15 0>; /* PH15 */ 213 gpio = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */
210 status = "okay"; 214 status = "okay";
211 }; 215 };
212 216
213 reg_usb1_vbus: usb1-vbus { 217 reg_usb1_vbus: usb1-vbus {
214 pinctrl-0 = <&usb1_vbus_pin_a20_hummingbird>; 218 pinctrl-0 = <&usb1_vbus_pin_a20_hummingbird>;
215 gpio = <&pio 7 2 0>; /* PH2 */ 219 gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
216 status = "okay"; 220 status = "okay";
217 }; 221 };
218 222
@@ -228,7 +232,7 @@
228 regulator-min-microvolt = <3000000>; 232 regulator-min-microvolt = <3000000>;
229 regulator-max-microvolt = <3000000>; 233 regulator-max-microvolt = <3000000>;
230 enable-active-high; 234 enable-active-high;
231 gpio = <&pio 7 9 0>; /* PH9 */ 235 gpio = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
232 }; 236 };
233 237
234 reg_gmac_vdd: gmac_vdd { 238 reg_gmac_vdd: gmac_vdd {
@@ -239,6 +243,6 @@
239 regulator-min-microvolt = <3000000>; 243 regulator-min-microvolt = <3000000>;
240 regulator-max-microvolt = <3000000>; 244 regulator-max-microvolt = <3000000>;
241 enable-active-high; 245 enable-active-high;
242 gpio = <&pio 7 16 0>; /* PH16 */ 246 gpio = <&pio 7 16 GPIO_ACTIVE_HIGH>; /* PH16 */
243 }; 247 };
244}; 248};
diff --git a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
index f38bb1a6656c..06148b4d000f 100644
--- a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
+++ b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
@@ -46,8 +46,12 @@
46 */ 46 */
47 47
48/dts-v1/; 48/dts-v1/;
49/include/ "sun7i-a20.dtsi" 49#include "sun7i-a20.dtsi"
50/include/ "sunxi-common-regulators.dtsi" 50#include "sunxi-common-regulators.dtsi"
51
52#include <dt-bindings/gpio/gpio.h>
53#include <dt-bindings/interrupt-controller/irq.h>
54#include <dt-bindings/pinctrl/sun4i-a10.h>
51 55
52/ { 56/ {
53 model = "I12 / Q5 / QT840A A20 tvbox"; 57 model = "I12 / Q5 / QT840A A20 tvbox";
@@ -59,7 +63,7 @@
59 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; 63 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
60 vmmc-supply = <&reg_vcc3v3>; 64 vmmc-supply = <&reg_vcc3v3>;
61 bus-width = <4>; 65 bus-width = <4>;
62 cd-gpios = <&pio 7 1 0>; /* PH1 */ 66 cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
63 cd-inverted; 67 cd-inverted;
64 status = "okay"; 68 status = "okay";
65 }; 69 };
@@ -98,35 +102,35 @@
98 pinctrl@01c20800 { 102 pinctrl@01c20800 {
99 mmc3_pins_a: mmc3@0 { 103 mmc3_pins_a: mmc3@0 {
100 /* AP6210 / AP6330 requires pull-up */ 104 /* AP6210 / AP6330 requires pull-up */
101 allwinner,pull = <1>; 105 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
102 }; 106 };
103 107
104 vmmc3_pin_i12_tvbox: vmmc3_pin@0 { 108 vmmc3_pin_i12_tvbox: vmmc3_pin@0 {
105 allwinner,pins = "PH2"; 109 allwinner,pins = "PH2";
106 allwinner,function = "gpio_out"; 110 allwinner,function = "gpio_out";
107 allwinner,drive = <0>; 111 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
108 allwinner,pull = <0>; 112 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
109 }; 113 };
110 114
111 vmmc3_io_pin_i12_tvbox: vmmc3_io_pin@0 { 115 vmmc3_io_pin_i12_tvbox: vmmc3_io_pin@0 {
112 allwinner,pins = "PH12"; 116 allwinner,pins = "PH12";
113 allwinner,function = "gpio_out"; 117 allwinner,function = "gpio_out";
114 allwinner,drive = <0>; 118 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
115 allwinner,pull = <0>; 119 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
116 }; 120 };
117 121
118 gmac_power_pin_i12_tvbox: gmac_power_pin@0 { 122 gmac_power_pin_i12_tvbox: gmac_power_pin@0 {
119 allwinner,pins = "PH21"; 123 allwinner,pins = "PH21";
120 allwinner,function = "gpio_out"; 124 allwinner,function = "gpio_out";
121 allwinner,drive = <0>; 125 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
122 allwinner,pull = <0>; 126 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
123 }; 127 };
124 128
125 led_pins_i12_tvbox: led_pins@0 { 129 led_pins_i12_tvbox: led_pins@0 {
126 allwinner,pins = "PH9", "PH20"; 130 allwinner,pins = "PH9", "PH20";
127 allwinner,function = "gpio_out"; 131 allwinner,function = "gpio_out";
128 allwinner,drive = <0>; 132 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
129 allwinner,pull = <0>; 133 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
130 }; 134 };
131 }; 135 };
132 136
@@ -151,7 +155,7 @@
151 compatible = "x-powers,axp209"; 155 compatible = "x-powers,axp209";
152 reg = <0x34>; 156 reg = <0x34>;
153 interrupt-parent = <&nmi_intc>; 157 interrupt-parent = <&nmi_intc>;
154 interrupts = <0 8>; 158 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
155 159
156 interrupt-controller; 160 interrupt-controller;
157 #interrupt-cells = <1>; 161 #interrupt-cells = <1>;
@@ -179,12 +183,12 @@
179 183
180 red { 184 red {
181 label = "i12_tvbox:red:usr"; 185 label = "i12_tvbox:red:usr";
182 gpios = <&pio 7 9 1>; 186 gpios = <&pio 7 9 GPIO_ACTIVE_LOW>;
183 }; 187 };
184 188
185 blue { 189 blue {
186 label = "i12_tvbox:blue:usr"; 190 label = "i12_tvbox:blue:usr";
187 gpios = <&pio 7 20 0>; 191 gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
188 }; 192 };
189 }; 193 };
190 194
@@ -204,7 +208,7 @@
204 regulator-min-microvolt = <3300000>; 208 regulator-min-microvolt = <3300000>;
205 regulator-max-microvolt = <3300000>; 209 regulator-max-microvolt = <3300000>;
206 enable-active-high; 210 enable-active-high;
207 gpio = <&pio 7 2 0>; 211 gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>;
208 }; 212 };
209 213
210 reg_vmmc3_io: vmmc3-io { 214 reg_vmmc3_io: vmmc3-io {
@@ -217,7 +221,7 @@
217 /* This controls VCC-PI, must be always on! */ 221 /* This controls VCC-PI, must be always on! */
218 regulator-always-on; 222 regulator-always-on;
219 enable-active-high; 223 enable-active-high;
220 gpio = <&pio 7 12 0>; 224 gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>;
221 }; 225 };
222 226
223 reg_gmac_3v3: gmac-3v3 { 227 reg_gmac_3v3: gmac-3v3 {
@@ -229,6 +233,6 @@
229 regulator-max-microvolt = <3300000>; 233 regulator-max-microvolt = <3300000>;
230 startup-delay-us = <50000>; 234 startup-delay-us = <50000>;
231 enable-active-high; 235 enable-active-high;
232 gpio = <&pio 7 21 0>; 236 gpio = <&pio 7 21 GPIO_ACTIVE_HIGH>;
233 }; 237 };
234}; 238};
diff --git a/arch/arm/boot/dts/sun7i-a20-m3.dts b/arch/arm/boot/dts/sun7i-a20-m3.dts
index b8e568c55271..5add9f243ec3 100644
--- a/arch/arm/boot/dts/sun7i-a20-m3.dts
+++ b/arch/arm/boot/dts/sun7i-a20-m3.dts
@@ -48,8 +48,12 @@
48 */ 48 */
49 49
50/dts-v1/; 50/dts-v1/;
51/include/ "sun7i-a20.dtsi" 51#include "sun7i-a20.dtsi"
52/include/ "sunxi-common-regulators.dtsi" 52#include "sunxi-common-regulators.dtsi"
53
54#include <dt-bindings/gpio/gpio.h>
55#include <dt-bindings/interrupt-controller/irq.h>
56#include <dt-bindings/pinctrl/sun4i-a10.h>
53 57
54/ { 58/ {
55 model = "Mele M3"; 59 model = "Mele M3";
@@ -61,7 +65,7 @@
61 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; 65 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
62 vmmc-supply = <&reg_vcc3v3>; 66 vmmc-supply = <&reg_vcc3v3>;
63 bus-width = <4>; 67 bus-width = <4>;
64 cd-gpios = <&pio 7 1 0>; /* PH1 */ 68 cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
65 cd-inverted; 69 cd-inverted;
66 status = "okay"; 70 status = "okay";
67 }; 71 };
@@ -101,8 +105,8 @@
101 led_pins_m3: led_pins@0 { 105 led_pins_m3: led_pins@0 {
102 allwinner,pins = "PH20"; 106 allwinner,pins = "PH20";
103 allwinner,function = "gpio_out"; 107 allwinner,function = "gpio_out";
104 allwinner,drive = <0>; 108 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
105 allwinner,pull = <0>; 109 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
106 }; 110 };
107 }; 111 };
108 112
@@ -127,7 +131,7 @@
127 compatible = "x-powers,axp209"; 131 compatible = "x-powers,axp209";
128 reg = <0x34>; 132 reg = <0x34>;
129 interrupt-parent = <&nmi_intc>; 133 interrupt-parent = <&nmi_intc>;
130 interrupts = <0 8>; 134 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
131 135
132 interrupt-controller; 136 interrupt-controller;
133 #interrupt-cells = <1>; 137 #interrupt-cells = <1>;
@@ -154,7 +158,7 @@
154 158
155 blue { 159 blue {
156 label = "m3:blue:usr"; 160 label = "m3:blue:usr";
157 gpios = <&pio 7 20 0>; 161 gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
158 }; 162 };
159 }; 163 };
160 164
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
index 3f3ff9693992..12ded69d61eb 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
@@ -49,8 +49,12 @@
49 */ 49 */
50 50
51/dts-v1/; 51/dts-v1/;
52/include/ "sun7i-a20.dtsi" 52#include "sun7i-a20.dtsi"
53/include/ "sunxi-common-regulators.dtsi" 53#include "sunxi-common-regulators.dtsi"
54
55#include <dt-bindings/gpio/gpio.h>
56#include <dt-bindings/interrupt-controller/irq.h>
57#include <dt-bindings/pinctrl/sun4i-a10.h>
54 58
55/ { 59/ {
56 model = "Olimex A20-OLinuXino-LIME"; 60 model = "Olimex A20-OLinuXino-LIME";
@@ -62,7 +66,7 @@
62 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; 66 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
63 vmmc-supply = <&reg_vcc3v3>; 67 vmmc-supply = <&reg_vcc3v3>;
64 bus-width = <4>; 68 bus-width = <4>;
65 cd-gpios = <&pio 7 1 0>; /* PH1 */ 69 cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
66 cd-inverted; 70 cd-inverted;
67 status = "okay"; 71 status = "okay";
68 }; 72 };
@@ -98,15 +102,15 @@
98 ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 { 102 ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 {
99 allwinner,pins = "PC3"; 103 allwinner,pins = "PC3";
100 allwinner,function = "gpio_out"; 104 allwinner,function = "gpio_out";
101 allwinner,drive = <0>; 105 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
102 allwinner,pull = <0>; 106 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
103 }; 107 };
104 108
105 led_pins_olinuxinolime: led_pins@0 { 109 led_pins_olinuxinolime: led_pins@0 {
106 allwinner,pins = "PH2"; 110 allwinner,pins = "PH2";
107 allwinner,function = "gpio_out"; 111 allwinner,function = "gpio_out";
108 allwinner,drive = <1>; 112 allwinner,drive = <SUN4I_PINCTRL_20_MA>;
109 allwinner,pull = <0>; 113 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
110 }; 114 };
111 }; 115 };
112 116
@@ -125,7 +129,7 @@
125 compatible = "x-powers,axp209"; 129 compatible = "x-powers,axp209";
126 reg = <0x34>; 130 reg = <0x34>;
127 interrupt-parent = <&nmi_intc>; 131 interrupt-parent = <&nmi_intc>;
128 interrupts = <0 8>; 132 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
129 133
130 interrupt-controller; 134 interrupt-controller;
131 #interrupt-cells = <1>; 135 #interrupt-cells = <1>;
@@ -152,14 +156,14 @@
152 156
153 green { 157 green {
154 label = "a20-olinuxino-lime:green:usr"; 158 label = "a20-olinuxino-lime:green:usr";
155 gpios = <&pio 7 2 0>; 159 gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>;
156 default-state = "on"; 160 default-state = "on";
157 }; 161 };
158 }; 162 };
159 163
160 reg_ahci_5v: ahci-5v { 164 reg_ahci_5v: ahci-5v {
161 pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>; 165 pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>;
162 gpio = <&pio 2 3 0>; 166 gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>;
163 status = "okay"; 167 status = "okay";
164 }; 168 };
165 169
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
index ed364d5e755e..260dbd3bf29d 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
@@ -46,8 +46,12 @@
46 */ 46 */
47 47
48/dts-v1/; 48/dts-v1/;
49/include/ "sun7i-a20.dtsi" 49#include "sun7i-a20.dtsi"
50/include/ "sunxi-common-regulators.dtsi" 50#include "sunxi-common-regulators.dtsi"
51
52#include <dt-bindings/gpio/gpio.h>
53#include <dt-bindings/interrupt-controller/irq.h>
54#include <dt-bindings/pinctrl/sun4i-a10.h>
51 55
52/ { 56/ {
53 model = "Olimex A20-OLinuXino-LIME2"; 57 model = "Olimex A20-OLinuXino-LIME2";
@@ -59,7 +63,7 @@
59 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; 63 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
60 vmmc-supply = <&reg_vcc3v3>; 64 vmmc-supply = <&reg_vcc3v3>;
61 bus-width = <4>; 65 bus-width = <4>;
62 cd-gpios = <&pio 7 1 0>; /* PH1 */ 66 cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
63 cd-inverted; 67 cd-inverted;
64 status = "okay"; 68 status = "okay";
65 }; 69 };
@@ -95,15 +99,15 @@
95 ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 { 99 ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 {
96 allwinner,pins = "PC3"; 100 allwinner,pins = "PC3";
97 allwinner,function = "gpio_out"; 101 allwinner,function = "gpio_out";
98 allwinner,drive = <0>; 102 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
99 allwinner,pull = <0>; 103 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
100 }; 104 };
101 105
102 led_pins_olinuxinolime: led_pins@0 { 106 led_pins_olinuxinolime: led_pins@0 {
103 allwinner,pins = "PH2"; 107 allwinner,pins = "PH2";
104 allwinner,function = "gpio_out"; 108 allwinner,function = "gpio_out";
105 allwinner,drive = <1>; 109 allwinner,drive = <SUN4I_PINCTRL_20_MA>;
106 allwinner,pull = <0>; 110 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
107 }; 111 };
108 }; 112 };
109 113
@@ -122,7 +126,7 @@
122 compatible = "x-powers,axp209"; 126 compatible = "x-powers,axp209";
123 reg = <0x34>; 127 reg = <0x34>;
124 interrupt-parent = <&nmi_intc>; 128 interrupt-parent = <&nmi_intc>;
125 interrupts = <0 8>; 129 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
126 130
127 interrupt-controller; 131 interrupt-controller;
128 #interrupt-cells = <1>; 132 #interrupt-cells = <1>;
@@ -199,14 +203,14 @@
199 203
200 green { 204 green {
201 label = "a20-olinuxino-lime2:green:usr"; 205 label = "a20-olinuxino-lime2:green:usr";
202 gpios = <&pio 7 2 0>; 206 gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>;
203 default-state = "on"; 207 default-state = "on";
204 }; 208 };
205 }; 209 };
206 210
207 reg_ahci_5v: ahci-5v { 211 reg_ahci_5v: ahci-5v {
208 pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>; 212 pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>;
209 gpio = <&pio 2 3 0>; 213 gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>;
210 status = "okay"; 214 status = "okay";
211 }; 215 };
212 216
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
index 66cc77707198..714e15ac5416 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
@@ -12,8 +12,13 @@
12 */ 12 */
13 13
14/dts-v1/; 14/dts-v1/;
15/include/ "sun7i-a20.dtsi" 15#include "sun7i-a20.dtsi"
16/include/ "sunxi-common-regulators.dtsi" 16#include "sunxi-common-regulators.dtsi"
17
18#include <dt-bindings/gpio/gpio.h>
19#include <dt-bindings/input/input.h>
20#include <dt-bindings/interrupt-controller/irq.h>
21#include <dt-bindings/pinctrl/sun4i-a10.h>
17 22
18/ { 23/ {
19 model = "Olimex A20-Olinuxino Micro"; 24 model = "Olimex A20-Olinuxino Micro";
@@ -39,7 +44,7 @@
39 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; 44 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
40 vmmc-supply = <&reg_vcc3v3>; 45 vmmc-supply = <&reg_vcc3v3>;
41 bus-width = <4>; 46 bus-width = <4>;
42 cd-gpios = <&pio 7 1 0>; /* PH1 */ 47 cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
43 cd-inverted; 48 cd-inverted;
44 status = "okay"; 49 status = "okay";
45 }; 50 };
@@ -49,7 +54,7 @@
49 pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_olinuxinom>; 54 pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_olinuxinom>;
50 vmmc-supply = <&reg_vcc3v3>; 55 vmmc-supply = <&reg_vcc3v3>;
51 bus-width = <4>; 56 bus-width = <4>;
52 cd-gpios = <&pio 7 11 0>; /* PH11 */ 57 cd-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
53 cd-inverted; 58 cd-inverted;
54 status = "okay"; 59 status = "okay";
55 }; 60 };
@@ -91,15 +96,69 @@
91 mmc3_cd_pin_olinuxinom: mmc3_cd_pin@0 { 96 mmc3_cd_pin_olinuxinom: mmc3_cd_pin@0 {
92 allwinner,pins = "PH11"; 97 allwinner,pins = "PH11";
93 allwinner,function = "gpio_in"; 98 allwinner,function = "gpio_in";
94 allwinner,drive = <0>; 99 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
95 allwinner,pull = <1>; 100 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
96 }; 101 };
97 102
98 led_pins_olinuxino: led_pins@0 { 103 led_pins_olinuxino: led_pins@0 {
99 allwinner,pins = "PH2"; 104 allwinner,pins = "PH2";
100 allwinner,function = "gpio_out"; 105 allwinner,function = "gpio_out";
101 allwinner,drive = <1>; 106 allwinner,drive = <SUN4I_PINCTRL_20_MA>;
102 allwinner,pull = <0>; 107 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
108 };
109 };
110
111 lradc: lradc@01c22800 {
112 vref-supply = <&reg_vcc3v0>;
113 status = "okay";
114
115 button@191 {
116 label = "Volume Up";
117 linux,code = <KEY_VOLUMEUP>;
118 channel = <0>;
119 voltage = <191274>;
120 };
121
122 button@392 {
123 label = "Volume Down";
124 linux,code = <KEY_VOLUMEDOWN>;
125 channel = <0>;
126 voltage = <392644>;
127 };
128
129 button@601 {
130 label = "Menu";
131 linux,code = <KEY_MENU>;
132 channel = <0>;
133 voltage = <601151>;
134 };
135
136 button@795 {
137 label = "Search";
138 linux,code = <KEY_SEARCH>;
139 channel = <0>;
140 voltage = <795090>;
141 };
142
143 button@987 {
144 label = "Home";
145 linux,code = <KEY_HOMEPAGE>;
146 channel = <0>;
147 voltage = <987387>;
148 };
149
150 button@1184 {
151 label = "Esc";
152 linux,code = <KEY_ESC>;
153 channel = <0>;
154 voltage = <1184678>;
155 };
156
157 button@1398 {
158 label = "Enter";
159 linux,code = <KEY_ENTER>;
160 channel = <0>;
161 voltage = <1398804>;
103 }; 162 };
104 }; 163 };
105 164
@@ -130,7 +189,7 @@
130 compatible = "x-powers,axp209"; 189 compatible = "x-powers,axp209";
131 reg = <0x34>; 190 reg = <0x34>;
132 interrupt-parent = <&nmi_intc>; 191 interrupt-parent = <&nmi_intc>;
133 interrupts = <0 8>; 192 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
134 193
135 interrupt-controller; 194 interrupt-controller;
136 #interrupt-cells = <1>; 195 #interrupt-cells = <1>;
@@ -169,7 +228,7 @@
169 228
170 green { 229 green {
171 label = "a20-olinuxino-micro:green:usr"; 230 label = "a20-olinuxino-micro:green:usr";
172 gpios = <&pio 7 2 0>; 231 gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>;
173 default-state = "on"; 232 default-state = "on";
174 }; 233 };
175 }; 234 };
diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
index 8dca49b2477b..0a2c2aeb4687 100644
--- a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
+++ b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
@@ -47,10 +47,13 @@
47 */ 47 */
48 48
49/dts-v1/; 49/dts-v1/;
50/include/ "sun7i-a20.dtsi" 50#include "sun7i-a20.dtsi"
51/include/ "sunxi-common-regulators.dtsi" 51#include "sunxi-common-regulators.dtsi"
52
52#include <dt-bindings/gpio/gpio.h> 53#include <dt-bindings/gpio/gpio.h>
53#include <dt-bindings/input/input.h> 54#include <dt-bindings/input/input.h>
55#include <dt-bindings/interrupt-controller/irq.h>
56#include <dt-bindings/pinctrl/sun4i-a10.h>
54 57
55/ { 58/ {
56 model = "LinkSprite pcDuino3"; 59 model = "LinkSprite pcDuino3";
@@ -62,7 +65,7 @@
62 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; 65 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
63 vmmc-supply = <&reg_vcc3v3>; 66 vmmc-supply = <&reg_vcc3v3>;
64 bus-width = <4>; 67 bus-width = <4>;
65 cd-gpios = <&pio 7 1 0>; /* PH1 */ 68 cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
66 cd-inverted; 69 cd-inverted;
67 status = "okay"; 70 status = "okay";
68 }; 71 };
@@ -102,15 +105,15 @@
102 led_pins_pcduino3: led_pins@0 { 105 led_pins_pcduino3: led_pins@0 {
103 allwinner,pins = "PH15", "PH16"; 106 allwinner,pins = "PH15", "PH16";
104 allwinner,function = "gpio_out"; 107 allwinner,function = "gpio_out";
105 allwinner,drive = <0>; 108 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
106 allwinner,pull = <0>; 109 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
107 }; 110 };
108 111
109 key_pins_pcduino3: key_pins@0 { 112 key_pins_pcduino3: key_pins@0 {
110 allwinner,pins = "PH17", "PH18", "PH19"; 113 allwinner,pins = "PH17", "PH18", "PH19";
111 allwinner,function = "gpio_in"; 114 allwinner,function = "gpio_in";
112 allwinner,drive = <0>; 115 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
113 allwinner,pull = <0>; 116 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
114 }; 117 };
115 }; 118 };
116 119
@@ -135,7 +138,7 @@
135 compatible = "x-powers,axp209"; 138 compatible = "x-powers,axp209";
136 reg = <0x34>; 139 reg = <0x34>;
137 interrupt-parent = <&nmi_intc>; 140 interrupt-parent = <&nmi_intc>;
138 interrupts = <0 8>; 141 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
139 142
140 interrupt-controller; 143 interrupt-controller;
141 #interrupt-cells = <1>; 144 #interrupt-cells = <1>;
@@ -203,7 +206,7 @@
203 }; 206 };
204 207
205 reg_ahci_5v: ahci-5v { 208 reg_ahci_5v: ahci-5v {
206 gpio = <&pio 7 2 0>; 209 gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>;
207 status = "okay"; 210 status = "okay";
208 }; 211 };
209}; 212};
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 89749ce34a84..786d491542ac 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -47,7 +47,13 @@
47 * OTHER DEALINGS IN THE SOFTWARE. 47 * OTHER DEALINGS IN THE SOFTWARE.
48 */ 48 */
49 49
50/include/ "skeleton.dtsi" 50#include "skeleton.dtsi"
51
52#include <dt-bindings/interrupt-controller/arm-gic.h>
53#include <dt-bindings/thermal/thermal.h>
54
55#include <dt-bindings/dma/sun4i-a10.h>
56#include <dt-bindings/pinctrl/sun4i-a10.h>
51 57
52/ { 58/ {
53 interrupt-parent = <&gic>; 59 interrupt-parent = <&gic>;
@@ -68,16 +74,49 @@
68 <&ahb_gates 44>; 74 <&ahb_gates 44>;
69 status = "disabled"; 75 status = "disabled";
70 }; 76 };
77
78 framebuffer@1 {
79 compatible = "allwinner,simple-framebuffer",
80 "simple-framebuffer";
81 allwinner,pipeline = "de_be0-lcd0";
82 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
83 status = "disabled";
84 };
85
86 framebuffer@2 {
87 compatible = "allwinner,simple-framebuffer",
88 "simple-framebuffer";
89 allwinner,pipeline = "de_be0-lcd0-tve0";
90 clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
91 <&ahb_gates 44>;
92 status = "disabled";
93 };
71 }; 94 };
72 95
73 cpus { 96 cpus {
74 #address-cells = <1>; 97 #address-cells = <1>;
75 #size-cells = <0>; 98 #size-cells = <0>;
76 99
77 cpu@0 { 100 cpu0: cpu@0 {
78 compatible = "arm,cortex-a7"; 101 compatible = "arm,cortex-a7";
79 device_type = "cpu"; 102 device_type = "cpu";
80 reg = <0>; 103 reg = <0>;
104 clocks = <&cpu>;
105 clock-latency = <244144>; /* 8 32k periods */
106 operating-points = <
107 /* kHz uV */
108 1008000 1450000
109 960000 1400000
110 912000 1400000
111 864000 1300000
112 720000 1200000
113 528000 1100000
114 312000 1000000
115 144000 900000
116 >;
117 #cooling-cells = <2>;
118 cooling-min-level = <0>;
119 cooling-max-level = <7>;
81 }; 120 };
82 121
83 cpu@1 { 122 cpu@1 {
@@ -87,22 +126,54 @@
87 }; 126 };
88 }; 127 };
89 128
129 thermal-zones {
130 cpu_thermal {
131 /* milliseconds */
132 polling-delay-passive = <250>;
133 polling-delay = <1000>;
134 thermal-sensors = <&rtp>;
135
136 cooling-maps {
137 map0 {
138 trip = <&cpu_alert0>;
139 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
140 };
141 };
142
143 trips {
144 cpu_alert0: cpu_alert0 {
145 /* milliCelsius */
146 temperature = <75000>;
147 hysteresis = <2000>;
148 type = "passive";
149 };
150
151 cpu_crit: cpu_crit {
152 /* milliCelsius */
153 temperature = <100000>;
154 hysteresis = <2000>;
155 type = "critical";
156 };
157 };
158 };
159 };
160
90 memory { 161 memory {
91 reg = <0x40000000 0x80000000>; 162 reg = <0x40000000 0x80000000>;
92 }; 163 };
93 164
94 timer { 165 timer {
95 compatible = "arm,armv7-timer"; 166 compatible = "arm,armv7-timer";
96 interrupts = <1 13 0xf08>, 167 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
97 <1 14 0xf08>, 168 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
98 <1 11 0xf08>, 169 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
99 <1 10 0xf08>; 170 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
100 }; 171 };
101 172
102 pmu { 173 pmu {
103 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; 174 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
104 interrupts = <0 120 4>, 175 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
105 <0 121 4>; 176 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
106 }; 177 };
107 178
108 clocks { 179 clocks {
@@ -454,13 +525,13 @@
454 interrupt-controller; 525 interrupt-controller;
455 #interrupt-cells = <2>; 526 #interrupt-cells = <2>;
456 reg = <0x01c00030 0x0c>; 527 reg = <0x01c00030 0x0c>;
457 interrupts = <0 0 4>; 528 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
458 }; 529 };
459 530
460 dma: dma-controller@01c02000 { 531 dma: dma-controller@01c02000 {
461 compatible = "allwinner,sun4i-a10-dma"; 532 compatible = "allwinner,sun4i-a10-dma";
462 reg = <0x01c02000 0x1000>; 533 reg = <0x01c02000 0x1000>;
463 interrupts = <0 27 4>; 534 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&ahb_gates 6>; 535 clocks = <&ahb_gates 6>;
465 #dma-cells = <2>; 536 #dma-cells = <2>;
466 }; 537 };
@@ -468,10 +539,11 @@
468 spi0: spi@01c05000 { 539 spi0: spi@01c05000 {
469 compatible = "allwinner,sun4i-a10-spi"; 540 compatible = "allwinner,sun4i-a10-spi";
470 reg = <0x01c05000 0x1000>; 541 reg = <0x01c05000 0x1000>;
471 interrupts = <0 10 4>; 542 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&ahb_gates 20>, <&spi0_clk>; 543 clocks = <&ahb_gates 20>, <&spi0_clk>;
473 clock-names = "ahb", "mod"; 544 clock-names = "ahb", "mod";
474 dmas = <&dma 1 27>, <&dma 1 26>; 545 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
546 <&dma SUN4I_DMA_DEDICATED 26>;
475 dma-names = "rx", "tx"; 547 dma-names = "rx", "tx";
476 status = "disabled"; 548 status = "disabled";
477 #address-cells = <1>; 549 #address-cells = <1>;
@@ -481,10 +553,11 @@
481 spi1: spi@01c06000 { 553 spi1: spi@01c06000 {
482 compatible = "allwinner,sun4i-a10-spi"; 554 compatible = "allwinner,sun4i-a10-spi";
483 reg = <0x01c06000 0x1000>; 555 reg = <0x01c06000 0x1000>;
484 interrupts = <0 11 4>; 556 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&ahb_gates 21>, <&spi1_clk>; 557 clocks = <&ahb_gates 21>, <&spi1_clk>;
486 clock-names = "ahb", "mod"; 558 clock-names = "ahb", "mod";
487 dmas = <&dma 1 9>, <&dma 1 8>; 559 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
560 <&dma SUN4I_DMA_DEDICATED 8>;
488 dma-names = "rx", "tx"; 561 dma-names = "rx", "tx";
489 status = "disabled"; 562 status = "disabled";
490 #address-cells = <1>; 563 #address-cells = <1>;
@@ -494,12 +567,12 @@
494 emac: ethernet@01c0b000 { 567 emac: ethernet@01c0b000 {
495 compatible = "allwinner,sun4i-a10-emac"; 568 compatible = "allwinner,sun4i-a10-emac";
496 reg = <0x01c0b000 0x1000>; 569 reg = <0x01c0b000 0x1000>;
497 interrupts = <0 55 4>; 570 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&ahb_gates 17>; 571 clocks = <&ahb_gates 17>;
499 status = "disabled"; 572 status = "disabled";
500 }; 573 };
501 574
502 mdio@01c0b080 { 575 mdio: mdio@01c0b080 {
503 compatible = "allwinner,sun4i-a10-mdio"; 576 compatible = "allwinner,sun4i-a10-mdio";
504 reg = <0x01c0b080 0x14>; 577 reg = <0x01c0b080 0x14>;
505 status = "disabled"; 578 status = "disabled";
@@ -512,7 +585,7 @@
512 reg = <0x01c0f000 0x1000>; 585 reg = <0x01c0f000 0x1000>;
513 clocks = <&ahb_gates 8>, <&mmc0_clk>; 586 clocks = <&ahb_gates 8>, <&mmc0_clk>;
514 clock-names = "ahb", "mmc"; 587 clock-names = "ahb", "mmc";
515 interrupts = <0 32 4>; 588 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
516 status = "disabled"; 589 status = "disabled";
517 }; 590 };
518 591
@@ -521,7 +594,7 @@
521 reg = <0x01c10000 0x1000>; 594 reg = <0x01c10000 0x1000>;
522 clocks = <&ahb_gates 9>, <&mmc1_clk>; 595 clocks = <&ahb_gates 9>, <&mmc1_clk>;
523 clock-names = "ahb", "mmc"; 596 clock-names = "ahb", "mmc";
524 interrupts = <0 33 4>; 597 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
525 status = "disabled"; 598 status = "disabled";
526 }; 599 };
527 600
@@ -530,7 +603,7 @@
530 reg = <0x01c11000 0x1000>; 603 reg = <0x01c11000 0x1000>;
531 clocks = <&ahb_gates 10>, <&mmc2_clk>; 604 clocks = <&ahb_gates 10>, <&mmc2_clk>;
532 clock-names = "ahb", "mmc"; 605 clock-names = "ahb", "mmc";
533 interrupts = <0 34 4>; 606 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
534 status = "disabled"; 607 status = "disabled";
535 }; 608 };
536 609
@@ -539,7 +612,7 @@
539 reg = <0x01c12000 0x1000>; 612 reg = <0x01c12000 0x1000>;
540 clocks = <&ahb_gates 11>, <&mmc3_clk>; 613 clocks = <&ahb_gates 11>, <&mmc3_clk>;
541 clock-names = "ahb", "mmc"; 614 clock-names = "ahb", "mmc";
542 interrupts = <0 35 4>; 615 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
543 status = "disabled"; 616 status = "disabled";
544 }; 617 };
545 618
@@ -558,7 +631,7 @@
558 ehci0: usb@01c14000 { 631 ehci0: usb@01c14000 {
559 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; 632 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
560 reg = <0x01c14000 0x100>; 633 reg = <0x01c14000 0x100>;
561 interrupts = <0 39 4>; 634 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
562 clocks = <&ahb_gates 1>; 635 clocks = <&ahb_gates 1>;
563 phys = <&usbphy 1>; 636 phys = <&usbphy 1>;
564 phy-names = "usb"; 637 phy-names = "usb";
@@ -568,7 +641,7 @@
568 ohci0: usb@01c14400 { 641 ohci0: usb@01c14400 {
569 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; 642 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
570 reg = <0x01c14400 0x100>; 643 reg = <0x01c14400 0x100>;
571 interrupts = <0 64 4>; 644 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
572 clocks = <&usb_clk 6>, <&ahb_gates 2>; 645 clocks = <&usb_clk 6>, <&ahb_gates 2>;
573 phys = <&usbphy 1>; 646 phys = <&usbphy 1>;
574 phy-names = "usb"; 647 phy-names = "usb";
@@ -578,10 +651,11 @@
578 spi2: spi@01c17000 { 651 spi2: spi@01c17000 {
579 compatible = "allwinner,sun4i-a10-spi"; 652 compatible = "allwinner,sun4i-a10-spi";
580 reg = <0x01c17000 0x1000>; 653 reg = <0x01c17000 0x1000>;
581 interrupts = <0 12 4>; 654 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
582 clocks = <&ahb_gates 22>, <&spi2_clk>; 655 clocks = <&ahb_gates 22>, <&spi2_clk>;
583 clock-names = "ahb", "mod"; 656 clock-names = "ahb", "mod";
584 dmas = <&dma 1 29>, <&dma 1 28>; 657 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
658 <&dma SUN4I_DMA_DEDICATED 28>;
585 dma-names = "rx", "tx"; 659 dma-names = "rx", "tx";
586 status = "disabled"; 660 status = "disabled";
587 #address-cells = <1>; 661 #address-cells = <1>;
@@ -591,7 +665,7 @@
591 ahci: sata@01c18000 { 665 ahci: sata@01c18000 {
592 compatible = "allwinner,sun4i-a10-ahci"; 666 compatible = "allwinner,sun4i-a10-ahci";
593 reg = <0x01c18000 0x1000>; 667 reg = <0x01c18000 0x1000>;
594 interrupts = <0 56 4>; 668 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
595 clocks = <&pll6 0>, <&ahb_gates 25>; 669 clocks = <&pll6 0>, <&ahb_gates 25>;
596 status = "disabled"; 670 status = "disabled";
597 }; 671 };
@@ -599,7 +673,7 @@
599 ehci1: usb@01c1c000 { 673 ehci1: usb@01c1c000 {
600 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; 674 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
601 reg = <0x01c1c000 0x100>; 675 reg = <0x01c1c000 0x100>;
602 interrupts = <0 40 4>; 676 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&ahb_gates 3>; 677 clocks = <&ahb_gates 3>;
604 phys = <&usbphy 2>; 678 phys = <&usbphy 2>;
605 phy-names = "usb"; 679 phy-names = "usb";
@@ -609,7 +683,7 @@
609 ohci1: usb@01c1c400 { 683 ohci1: usb@01c1c400 {
610 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; 684 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
611 reg = <0x01c1c400 0x100>; 685 reg = <0x01c1c400 0x100>;
612 interrupts = <0 65 4>; 686 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
613 clocks = <&usb_clk 7>, <&ahb_gates 4>; 687 clocks = <&usb_clk 7>, <&ahb_gates 4>;
614 phys = <&usbphy 2>; 688 phys = <&usbphy 2>;
615 phy-names = "usb"; 689 phy-names = "usb";
@@ -619,10 +693,11 @@
619 spi3: spi@01c1f000 { 693 spi3: spi@01c1f000 {
620 compatible = "allwinner,sun4i-a10-spi"; 694 compatible = "allwinner,sun4i-a10-spi";
621 reg = <0x01c1f000 0x1000>; 695 reg = <0x01c1f000 0x1000>;
622 interrupts = <0 50 4>; 696 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
623 clocks = <&ahb_gates 23>, <&spi3_clk>; 697 clocks = <&ahb_gates 23>, <&spi3_clk>;
624 clock-names = "ahb", "mod"; 698 clock-names = "ahb", "mod";
625 dmas = <&dma 1 31>, <&dma 1 30>; 699 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
700 <&dma SUN4I_DMA_DEDICATED 30>;
626 dma-names = "rx", "tx"; 701 dma-names = "rx", "tx";
627 status = "disabled"; 702 status = "disabled";
628 #address-cells = <1>; 703 #address-cells = <1>;
@@ -632,7 +707,7 @@
632 pio: pinctrl@01c20800 { 707 pio: pinctrl@01c20800 {
633 compatible = "allwinner,sun7i-a20-pinctrl"; 708 compatible = "allwinner,sun7i-a20-pinctrl";
634 reg = <0x01c20800 0x400>; 709 reg = <0x01c20800 0x400>;
635 interrupts = <0 28 4>; 710 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
636 clocks = <&apb0_gates 5>; 711 clocks = <&apb0_gates 5>;
637 gpio-controller; 712 gpio-controller;
638 interrupt-controller; 713 interrupt-controller;
@@ -643,99 +718,99 @@
643 pwm0_pins_a: pwm0@0 { 718 pwm0_pins_a: pwm0@0 {
644 allwinner,pins = "PB2"; 719 allwinner,pins = "PB2";
645 allwinner,function = "pwm"; 720 allwinner,function = "pwm";
646 allwinner,drive = <0>; 721 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
647 allwinner,pull = <0>; 722 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
648 }; 723 };
649 724
650 pwm1_pins_a: pwm1@0 { 725 pwm1_pins_a: pwm1@0 {
651 allwinner,pins = "PI3"; 726 allwinner,pins = "PI3";
652 allwinner,function = "pwm"; 727 allwinner,function = "pwm";
653 allwinner,drive = <0>; 728 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
654 allwinner,pull = <0>; 729 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
655 }; 730 };
656 731
657 uart0_pins_a: uart0@0 { 732 uart0_pins_a: uart0@0 {
658 allwinner,pins = "PB22", "PB23"; 733 allwinner,pins = "PB22", "PB23";
659 allwinner,function = "uart0"; 734 allwinner,function = "uart0";
660 allwinner,drive = <0>; 735 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
661 allwinner,pull = <0>; 736 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
662 }; 737 };
663 738
664 uart2_pins_a: uart2@0 { 739 uart2_pins_a: uart2@0 {
665 allwinner,pins = "PI16", "PI17", "PI18", "PI19"; 740 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
666 allwinner,function = "uart2"; 741 allwinner,function = "uart2";
667 allwinner,drive = <0>; 742 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
668 allwinner,pull = <0>; 743 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
669 }; 744 };
670 745
671 uart3_pins_a: uart3@0 { 746 uart3_pins_a: uart3@0 {
672 allwinner,pins = "PG6", "PG7", "PG8", "PG9"; 747 allwinner,pins = "PG6", "PG7", "PG8", "PG9";
673 allwinner,function = "uart3"; 748 allwinner,function = "uart3";
674 allwinner,drive = <0>; 749 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
675 allwinner,pull = <0>; 750 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
676 }; 751 };
677 752
678 uart3_pins_b: uart3@1 { 753 uart3_pins_b: uart3@1 {
679 allwinner,pins = "PH0", "PH1"; 754 allwinner,pins = "PH0", "PH1";
680 allwinner,function = "uart3"; 755 allwinner,function = "uart3";
681 allwinner,drive = <0>; 756 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
682 allwinner,pull = <0>; 757 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
683 }; 758 };
684 759
685 uart4_pins_a: uart4@0 { 760 uart4_pins_a: uart4@0 {
686 allwinner,pins = "PG10", "PG11"; 761 allwinner,pins = "PG10", "PG11";
687 allwinner,function = "uart4"; 762 allwinner,function = "uart4";
688 allwinner,drive = <0>; 763 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
689 allwinner,pull = <0>; 764 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
690 }; 765 };
691 766
692 uart5_pins_a: uart5@0 { 767 uart5_pins_a: uart5@0 {
693 allwinner,pins = "PI10", "PI11"; 768 allwinner,pins = "PI10", "PI11";
694 allwinner,function = "uart5"; 769 allwinner,function = "uart5";
695 allwinner,drive = <0>; 770 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
696 allwinner,pull = <0>; 771 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
697 }; 772 };
698 773
699 uart6_pins_a: uart6@0 { 774 uart6_pins_a: uart6@0 {
700 allwinner,pins = "PI12", "PI13"; 775 allwinner,pins = "PI12", "PI13";
701 allwinner,function = "uart6"; 776 allwinner,function = "uart6";
702 allwinner,drive = <0>; 777 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
703 allwinner,pull = <0>; 778 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
704 }; 779 };
705 780
706 uart7_pins_a: uart7@0 { 781 uart7_pins_a: uart7@0 {
707 allwinner,pins = "PI20", "PI21"; 782 allwinner,pins = "PI20", "PI21";
708 allwinner,function = "uart7"; 783 allwinner,function = "uart7";
709 allwinner,drive = <0>; 784 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
710 allwinner,pull = <0>; 785 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
711 }; 786 };
712 787
713 i2c0_pins_a: i2c0@0 { 788 i2c0_pins_a: i2c0@0 {
714 allwinner,pins = "PB0", "PB1"; 789 allwinner,pins = "PB0", "PB1";
715 allwinner,function = "i2c0"; 790 allwinner,function = "i2c0";
716 allwinner,drive = <0>; 791 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
717 allwinner,pull = <0>; 792 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
718 }; 793 };
719 794
720 i2c1_pins_a: i2c1@0 { 795 i2c1_pins_a: i2c1@0 {
721 allwinner,pins = "PB18", "PB19"; 796 allwinner,pins = "PB18", "PB19";
722 allwinner,function = "i2c1"; 797 allwinner,function = "i2c1";
723 allwinner,drive = <0>; 798 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
724 allwinner,pull = <0>; 799 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
725 }; 800 };
726 801
727 i2c2_pins_a: i2c2@0 { 802 i2c2_pins_a: i2c2@0 {
728 allwinner,pins = "PB20", "PB21"; 803 allwinner,pins = "PB20", "PB21";
729 allwinner,function = "i2c2"; 804 allwinner,function = "i2c2";
730 allwinner,drive = <0>; 805 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
731 allwinner,pull = <0>; 806 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
732 }; 807 };
733 808
734 i2c3_pins_a: i2c3@0 { 809 i2c3_pins_a: i2c3@0 {
735 allwinner,pins = "PI0", "PI1"; 810 allwinner,pins = "PI0", "PI1";
736 allwinner,function = "i2c3"; 811 allwinner,function = "i2c3";
737 allwinner,drive = <0>; 812 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
738 allwinner,pull = <0>; 813 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
739 }; 814 };
740 815
741 emac_pins_a: emac0@0 { 816 emac_pins_a: emac0@0 {
@@ -745,22 +820,22 @@
745 "PA11", "PA12", "PA13", "PA14", 820 "PA11", "PA12", "PA13", "PA14",
746 "PA15", "PA16"; 821 "PA15", "PA16";
747 allwinner,function = "emac"; 822 allwinner,function = "emac";
748 allwinner,drive = <0>; 823 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
749 allwinner,pull = <0>; 824 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
750 }; 825 };
751 826
752 clk_out_a_pins_a: clk_out_a@0 { 827 clk_out_a_pins_a: clk_out_a@0 {
753 allwinner,pins = "PI12"; 828 allwinner,pins = "PI12";
754 allwinner,function = "clk_out_a"; 829 allwinner,function = "clk_out_a";
755 allwinner,drive = <0>; 830 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
756 allwinner,pull = <0>; 831 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
757 }; 832 };
758 833
759 clk_out_b_pins_a: clk_out_b@0 { 834 clk_out_b_pins_a: clk_out_b@0 {
760 allwinner,pins = "PI13"; 835 allwinner,pins = "PI13";
761 allwinner,function = "clk_out_b"; 836 allwinner,function = "clk_out_b";
762 allwinner,drive = <0>; 837 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
763 allwinner,pull = <0>; 838 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
764 }; 839 };
765 840
766 gmac_pins_mii_a: gmac_mii@0 { 841 gmac_pins_mii_a: gmac_mii@0 {
@@ -770,8 +845,8 @@
770 "PA11", "PA12", "PA13", "PA14", 845 "PA11", "PA12", "PA13", "PA14",
771 "PA15", "PA16"; 846 "PA15", "PA16";
772 allwinner,function = "gmac"; 847 allwinner,function = "gmac";
773 allwinner,drive = <0>; 848 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
774 allwinner,pull = <0>; 849 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
775 }; 850 };
776 851
777 gmac_pins_rgmii_a: gmac_rgmii@0 { 852 gmac_pins_rgmii_a: gmac_rgmii@0 {
@@ -785,90 +860,104 @@
785 * data lines in RGMII mode use DDR mode 860 * data lines in RGMII mode use DDR mode
786 * and need a higher signal drive strength 861 * and need a higher signal drive strength
787 */ 862 */
788 allwinner,drive = <3>; 863 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
789 allwinner,pull = <0>; 864 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
790 }; 865 };
791 866
792 spi0_pins_a: spi0@0 { 867 spi0_pins_a: spi0@0 {
793 allwinner,pins = "PI10", "PI11", "PI12", "PI13", "PI14"; 868 allwinner,pins = "PI10", "PI11", "PI12", "PI13", "PI14";
794 allwinner,function = "spi0"; 869 allwinner,function = "spi0";
795 allwinner,drive = <0>; 870 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
796 allwinner,pull = <0>; 871 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
797 }; 872 };
798 873
799 spi1_pins_a: spi1@0 { 874 spi1_pins_a: spi1@0 {
800 allwinner,pins = "PI16", "PI17", "PI18", "PI19"; 875 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
801 allwinner,function = "spi1"; 876 allwinner,function = "spi1";
802 allwinner,drive = <0>; 877 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
803 allwinner,pull = <0>; 878 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
804 }; 879 };
805 880
806 spi2_pins_a: spi2@0 { 881 spi2_pins_a: spi2@0 {
807 allwinner,pins = "PC19", "PC20", "PC21", "PC22"; 882 allwinner,pins = "PC19", "PC20", "PC21", "PC22";
808 allwinner,function = "spi2"; 883 allwinner,function = "spi2";
809 allwinner,drive = <0>; 884 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
810 allwinner,pull = <0>; 885 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
811 }; 886 };
812 887
813 spi2_pins_b: spi2@1 { 888 spi2_pins_b: spi2@1 {
814 allwinner,pins = "PB14", "PB15", "PB16", "PB17"; 889 allwinner,pins = "PB14", "PB15", "PB16", "PB17";
815 allwinner,function = "spi2"; 890 allwinner,function = "spi2";
816 allwinner,drive = <0>; 891 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
817 allwinner,pull = <0>; 892 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
818 }; 893 };
819 894
820 mmc0_pins_a: mmc0@0 { 895 mmc0_pins_a: mmc0@0 {
821 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; 896 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
822 allwinner,function = "mmc0"; 897 allwinner,function = "mmc0";
823 allwinner,drive = <2>; 898 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
824 allwinner,pull = <0>; 899 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
825 }; 900 };
826 901
827 mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { 902 mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
828 allwinner,pins = "PH1"; 903 allwinner,pins = "PH1";
829 allwinner,function = "gpio_in"; 904 allwinner,function = "gpio_in";
830 allwinner,drive = <0>; 905 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
831 allwinner,pull = <1>; 906 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
832 }; 907 };
833 908
834 mmc2_pins_a: mmc2@0 { 909 mmc2_pins_a: mmc2@0 {
835 allwinner,pins = "PC6","PC7","PC8","PC9","PC10","PC11"; 910 allwinner,pins = "PC6","PC7","PC8","PC9","PC10","PC11";
836 allwinner,function = "mmc2"; 911 allwinner,function = "mmc2";
837 allwinner,drive = <2>; 912 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
838 allwinner,pull = <1>; 913 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
839 }; 914 };
840 915
841 mmc3_pins_a: mmc3@0 { 916 mmc3_pins_a: mmc3@0 {
842 allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9"; 917 allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9";
843 allwinner,function = "mmc3"; 918 allwinner,function = "mmc3";
844 allwinner,drive = <2>; 919 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
845 allwinner,pull = <0>; 920 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
846 }; 921 };
847 922
848 ir0_pins_a: ir0@0 { 923 ir0_pins_a: ir0@0 {
849 allwinner,pins = "PB3","PB4"; 924 allwinner,pins = "PB3","PB4";
850 allwinner,function = "ir0"; 925 allwinner,function = "ir0";
851 allwinner,drive = <0>; 926 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
852 allwinner,pull = <0>; 927 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
853 }; 928 };
854 929
855 ir1_pins_a: ir1@0 { 930 ir1_pins_a: ir1@0 {
856 allwinner,pins = "PB22","PB23"; 931 allwinner,pins = "PB22","PB23";
857 allwinner,function = "ir1"; 932 allwinner,function = "ir1";
858 allwinner,drive = <0>; 933 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
859 allwinner,pull = <0>; 934 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
935 };
936
937 ps20_pins_a: ps20@0 {
938 allwinner,pins = "PI20", "PI21";
939 allwinner,function = "ps2";
940 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
941 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
942 };
943
944 ps21_pins_a: ps21@0 {
945 allwinner,pins = "PH12", "PH13";
946 allwinner,function = "ps2";
947 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
948 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
860 }; 949 };
861 }; 950 };
862 951
863 timer@01c20c00 { 952 timer@01c20c00 {
864 compatible = "allwinner,sun4i-a10-timer"; 953 compatible = "allwinner,sun4i-a10-timer";
865 reg = <0x01c20c00 0x90>; 954 reg = <0x01c20c00 0x90>;
866 interrupts = <0 22 4>, 955 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
867 <0 23 4>, 956 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
868 <0 24 4>, 957 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
869 <0 25 4>, 958 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
870 <0 67 4>, 959 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
871 <0 68 4>; 960 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
872 clocks = <&osc24M>; 961 clocks = <&osc24M>;
873 }; 962 };
874 963
@@ -880,7 +969,7 @@
880 rtc: rtc@01c20d00 { 969 rtc: rtc@01c20d00 {
881 compatible = "allwinner,sun7i-a20-rtc"; 970 compatible = "allwinner,sun7i-a20-rtc";
882 reg = <0x01c20d00 0x20>; 971 reg = <0x01c20d00 0x20>;
883 interrupts = <0 24 4>; 972 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
884 }; 973 };
885 974
886 pwm: pwm@01c20e00 { 975 pwm: pwm@01c20e00 {
@@ -895,7 +984,7 @@
895 compatible = "allwinner,sun4i-a10-ir"; 984 compatible = "allwinner,sun4i-a10-ir";
896 clocks = <&apb0_gates 6>, <&ir0_clk>; 985 clocks = <&apb0_gates 6>, <&ir0_clk>;
897 clock-names = "apb", "ir"; 986 clock-names = "apb", "ir";
898 interrupts = <0 5 4>; 987 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
899 reg = <0x01c21800 0x40>; 988 reg = <0x01c21800 0x40>;
900 status = "disabled"; 989 status = "disabled";
901 }; 990 };
@@ -904,11 +993,18 @@
904 compatible = "allwinner,sun4i-a10-ir"; 993 compatible = "allwinner,sun4i-a10-ir";
905 clocks = <&apb0_gates 7>, <&ir1_clk>; 994 clocks = <&apb0_gates 7>, <&ir1_clk>;
906 clock-names = "apb", "ir"; 995 clock-names = "apb", "ir";
907 interrupts = <0 6 4>; 996 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
908 reg = <0x01c21c00 0x40>; 997 reg = <0x01c21c00 0x40>;
909 status = "disabled"; 998 status = "disabled";
910 }; 999 };
911 1000
1001 lradc: lradc@01c22800 {
1002 compatible = "allwinner,sun4i-a10-lradc-keys";
1003 reg = <0x01c22800 0x100>;
1004 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1005 status = "disabled";
1006 };
1007
912 sid: eeprom@01c23800 { 1008 sid: eeprom@01c23800 {
913 compatible = "allwinner,sun7i-a20-sid"; 1009 compatible = "allwinner,sun7i-a20-sid";
914 reg = <0x01c23800 0x200>; 1010 reg = <0x01c23800 0x200>;
@@ -917,13 +1013,14 @@
917 rtp: rtp@01c25000 { 1013 rtp: rtp@01c25000 {
918 compatible = "allwinner,sun4i-a10-ts"; 1014 compatible = "allwinner,sun4i-a10-ts";
919 reg = <0x01c25000 0x100>; 1015 reg = <0x01c25000 0x100>;
920 interrupts = <0 29 4>; 1016 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1017 #thermal-sensor-cells = <0>;
921 }; 1018 };
922 1019
923 uart0: serial@01c28000 { 1020 uart0: serial@01c28000 {
924 compatible = "snps,dw-apb-uart"; 1021 compatible = "snps,dw-apb-uart";
925 reg = <0x01c28000 0x400>; 1022 reg = <0x01c28000 0x400>;
926 interrupts = <0 1 4>; 1023 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
927 reg-shift = <2>; 1024 reg-shift = <2>;
928 reg-io-width = <4>; 1025 reg-io-width = <4>;
929 clocks = <&apb1_gates 16>; 1026 clocks = <&apb1_gates 16>;
@@ -933,7 +1030,7 @@
933 uart1: serial@01c28400 { 1030 uart1: serial@01c28400 {
934 compatible = "snps,dw-apb-uart"; 1031 compatible = "snps,dw-apb-uart";
935 reg = <0x01c28400 0x400>; 1032 reg = <0x01c28400 0x400>;
936 interrupts = <0 2 4>; 1033 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
937 reg-shift = <2>; 1034 reg-shift = <2>;
938 reg-io-width = <4>; 1035 reg-io-width = <4>;
939 clocks = <&apb1_gates 17>; 1036 clocks = <&apb1_gates 17>;
@@ -943,7 +1040,7 @@
943 uart2: serial@01c28800 { 1040 uart2: serial@01c28800 {
944 compatible = "snps,dw-apb-uart"; 1041 compatible = "snps,dw-apb-uart";
945 reg = <0x01c28800 0x400>; 1042 reg = <0x01c28800 0x400>;
946 interrupts = <0 3 4>; 1043 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
947 reg-shift = <2>; 1044 reg-shift = <2>;
948 reg-io-width = <4>; 1045 reg-io-width = <4>;
949 clocks = <&apb1_gates 18>; 1046 clocks = <&apb1_gates 18>;
@@ -953,7 +1050,7 @@
953 uart3: serial@01c28c00 { 1050 uart3: serial@01c28c00 {
954 compatible = "snps,dw-apb-uart"; 1051 compatible = "snps,dw-apb-uart";
955 reg = <0x01c28c00 0x400>; 1052 reg = <0x01c28c00 0x400>;
956 interrupts = <0 4 4>; 1053 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
957 reg-shift = <2>; 1054 reg-shift = <2>;
958 reg-io-width = <4>; 1055 reg-io-width = <4>;
959 clocks = <&apb1_gates 19>; 1056 clocks = <&apb1_gates 19>;
@@ -963,7 +1060,7 @@
963 uart4: serial@01c29000 { 1060 uart4: serial@01c29000 {
964 compatible = "snps,dw-apb-uart"; 1061 compatible = "snps,dw-apb-uart";
965 reg = <0x01c29000 0x400>; 1062 reg = <0x01c29000 0x400>;
966 interrupts = <0 17 4>; 1063 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
967 reg-shift = <2>; 1064 reg-shift = <2>;
968 reg-io-width = <4>; 1065 reg-io-width = <4>;
969 clocks = <&apb1_gates 20>; 1066 clocks = <&apb1_gates 20>;
@@ -973,7 +1070,7 @@
973 uart5: serial@01c29400 { 1070 uart5: serial@01c29400 {
974 compatible = "snps,dw-apb-uart"; 1071 compatible = "snps,dw-apb-uart";
975 reg = <0x01c29400 0x400>; 1072 reg = <0x01c29400 0x400>;
976 interrupts = <0 18 4>; 1073 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
977 reg-shift = <2>; 1074 reg-shift = <2>;
978 reg-io-width = <4>; 1075 reg-io-width = <4>;
979 clocks = <&apb1_gates 21>; 1076 clocks = <&apb1_gates 21>;
@@ -983,7 +1080,7 @@
983 uart6: serial@01c29800 { 1080 uart6: serial@01c29800 {
984 compatible = "snps,dw-apb-uart"; 1081 compatible = "snps,dw-apb-uart";
985 reg = <0x01c29800 0x400>; 1082 reg = <0x01c29800 0x400>;
986 interrupts = <0 19 4>; 1083 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
987 reg-shift = <2>; 1084 reg-shift = <2>;
988 reg-io-width = <4>; 1085 reg-io-width = <4>;
989 clocks = <&apb1_gates 22>; 1086 clocks = <&apb1_gates 22>;
@@ -993,7 +1090,7 @@
993 uart7: serial@01c29c00 { 1090 uart7: serial@01c29c00 {
994 compatible = "snps,dw-apb-uart"; 1091 compatible = "snps,dw-apb-uart";
995 reg = <0x01c29c00 0x400>; 1092 reg = <0x01c29c00 0x400>;
996 interrupts = <0 20 4>; 1093 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
997 reg-shift = <2>; 1094 reg-shift = <2>;
998 reg-io-width = <4>; 1095 reg-io-width = <4>;
999 clocks = <&apb1_gates 23>; 1096 clocks = <&apb1_gates 23>;
@@ -1003,7 +1100,7 @@
1003 i2c0: i2c@01c2ac00 { 1100 i2c0: i2c@01c2ac00 {
1004 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; 1101 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1005 reg = <0x01c2ac00 0x400>; 1102 reg = <0x01c2ac00 0x400>;
1006 interrupts = <0 7 4>; 1103 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1007 clocks = <&apb1_gates 0>; 1104 clocks = <&apb1_gates 0>;
1008 status = "disabled"; 1105 status = "disabled";
1009 #address-cells = <1>; 1106 #address-cells = <1>;
@@ -1013,7 +1110,7 @@
1013 i2c1: i2c@01c2b000 { 1110 i2c1: i2c@01c2b000 {
1014 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; 1111 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1015 reg = <0x01c2b000 0x400>; 1112 reg = <0x01c2b000 0x400>;
1016 interrupts = <0 8 4>; 1113 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1017 clocks = <&apb1_gates 1>; 1114 clocks = <&apb1_gates 1>;
1018 status = "disabled"; 1115 status = "disabled";
1019 #address-cells = <1>; 1116 #address-cells = <1>;
@@ -1023,7 +1120,7 @@
1023 i2c2: i2c@01c2b400 { 1120 i2c2: i2c@01c2b400 {
1024 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; 1121 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1025 reg = <0x01c2b400 0x400>; 1122 reg = <0x01c2b400 0x400>;
1026 interrupts = <0 9 4>; 1123 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1027 clocks = <&apb1_gates 2>; 1124 clocks = <&apb1_gates 2>;
1028 status = "disabled"; 1125 status = "disabled";
1029 #address-cells = <1>; 1126 #address-cells = <1>;
@@ -1033,7 +1130,7 @@
1033 i2c3: i2c@01c2b800 { 1130 i2c3: i2c@01c2b800 {
1034 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; 1131 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1035 reg = <0x01c2b800 0x400>; 1132 reg = <0x01c2b800 0x400>;
1036 interrupts = <0 88 4>; 1133 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1037 clocks = <&apb1_gates 3>; 1134 clocks = <&apb1_gates 3>;
1038 status = "disabled"; 1135 status = "disabled";
1039 #address-cells = <1>; 1136 #address-cells = <1>;
@@ -1043,7 +1140,7 @@
1043 i2c4: i2c@01c2c000 { 1140 i2c4: i2c@01c2c000 {
1044 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; 1141 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1045 reg = <0x01c2c000 0x400>; 1142 reg = <0x01c2c000 0x400>;
1046 interrupts = <0 89 4>; 1143 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1047 clocks = <&apb1_gates 15>; 1144 clocks = <&apb1_gates 15>;
1048 status = "disabled"; 1145 status = "disabled";
1049 #address-cells = <1>; 1146 #address-cells = <1>;
@@ -1053,7 +1150,7 @@
1053 gmac: ethernet@01c50000 { 1150 gmac: ethernet@01c50000 {
1054 compatible = "allwinner,sun7i-a20-gmac"; 1151 compatible = "allwinner,sun7i-a20-gmac";
1055 reg = <0x01c50000 0x10000>; 1152 reg = <0x01c50000 0x10000>;
1056 interrupts = <0 85 4>; 1153 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1057 interrupt-names = "macirq"; 1154 interrupt-names = "macirq";
1058 clocks = <&ahb_gates 49>, <&gmac_tx_clk>; 1155 clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
1059 clock-names = "stmmaceth", "allwinner_gmac_tx"; 1156 clock-names = "stmmaceth", "allwinner_gmac_tx";
@@ -1068,10 +1165,10 @@
1068 hstimer@01c60000 { 1165 hstimer@01c60000 {
1069 compatible = "allwinner,sun7i-a20-hstimer"; 1166 compatible = "allwinner,sun7i-a20-hstimer";
1070 reg = <0x01c60000 0x1000>; 1167 reg = <0x01c60000 0x1000>;
1071 interrupts = <0 81 4>, 1168 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1072 <0 82 4>, 1169 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1073 <0 83 4>, 1170 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1074 <0 84 4>; 1171 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1075 clocks = <&ahb_gates 28>; 1172 clocks = <&ahb_gates 28>;
1076 }; 1173 };
1077 1174
@@ -1083,7 +1180,23 @@
1083 <0x01c86000 0x2000>; 1180 <0x01c86000 0x2000>;
1084 interrupt-controller; 1181 interrupt-controller;
1085 #interrupt-cells = <3>; 1182 #interrupt-cells = <3>;
1086 interrupts = <1 9 0xf04>; 1183 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1184 };
1185
1186 ps20: ps2@01c2a000 {
1187 compatible = "allwinner,sun4i-a10-ps2";
1188 reg = <0x01c2a000 0x400>;
1189 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1190 clocks = <&apb1_gates 6>;
1191 status = "disabled";
1192 };
1193
1194 ps21: ps2@01c2a400 {
1195 compatible = "allwinner,sun4i-a10-ps2";
1196 reg = <0x01c2a400 0x400>;
1197 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1198 clocks = <&apb1_gates 7>;
1199 status = "disabled";
1087 }; 1200 };
1088 }; 1201 };
1089}; 1202};
diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts
new file mode 100644
index 000000000000..dd31c53e2ab6
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts
@@ -0,0 +1,59 @@
1/*
2 * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48/*
49 * The Ippo Q8H v1.2 is almost identical to the v5, still it needs a separate
50 * dtb file since some gpio-s surrounding the wlan/bluetooth are different,
51 * and it uses different camera sensors.
52 */
53
54#include "sun8i-a23-ippo-q8h-v5.dts"
55
56/ {
57 model = "Ippo Q8H Dual Core Tablet (v1.2)";
58 compatible = "ippo,q8h-v1.2", "allwinner,sun8i-a23";
59};
diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
index 32ad80804dbb..623573e46080 100644
--- a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
+++ b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
@@ -48,8 +48,12 @@
48 */ 48 */
49 49
50/dts-v1/; 50/dts-v1/;
51/include/ "sun8i-a23.dtsi" 51#include "sun8i-a23.dtsi"
52/include/ "sunxi-common-regulators.dtsi" 52#include "sunxi-common-regulators.dtsi"
53
54#include <dt-bindings/gpio/gpio.h>
55#include <dt-bindings/input/input.h>
56#include <dt-bindings/pinctrl/sun4i-a10.h>
53 57
54/ { 58/ {
55 model = "Ippo Q8H Dual Core Tablet (v5)"; 59 model = "Ippo Q8H Dual Core Tablet (v5)";
@@ -69,7 +73,7 @@
69 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8h>; 73 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8h>;
70 vmmc-supply = <&reg_vcc3v0>; 74 vmmc-supply = <&reg_vcc3v0>;
71 bus-width = <4>; 75 bus-width = <4>;
72 cd-gpios = <&pio 1 4 0>; /* PB4 */ 76 cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
73 cd-inverted; 77 cd-inverted;
74 status = "okay"; 78 status = "okay";
75 }; 79 };
@@ -78,8 +82,27 @@
78 mmc0_cd_pin_q8h: mmc0_cd_pin@0 { 82 mmc0_cd_pin_q8h: mmc0_cd_pin@0 {
79 allwinner,pins = "PB4"; 83 allwinner,pins = "PB4";
80 allwinner,function = "gpio_in"; 84 allwinner,function = "gpio_in";
81 allwinner,drive = <0>; 85 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
82 allwinner,pull = <1>; 86 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
87 };
88 };
89
90 lradc: lradc@01c22800 {
91 vref-supply = <&reg_vcc3v0>;
92 status = "okay";
93
94 button@200 {
95 label = "Volume Up";
96 linux,code = <KEY_VOLUMEUP>;
97 channel = <0>;
98 voltage = <200000>;
99 };
100
101 button@400 {
102 label = "Volume Down";
103 linux,code = <KEY_VOLUMEDOWN>;
104 channel = <0>;
105 voltage = <400000>;
83 }; 106 };
84 }; 107 };
85 108
diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
index 86584fcf5e32..dd34527293e4 100644
--- a/arch/arm/boot/dts/sun8i-a23.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23.dtsi
@@ -47,11 +47,29 @@
47 * OTHER DEALINGS IN THE SOFTWARE. 47 * OTHER DEALINGS IN THE SOFTWARE.
48 */ 48 */
49 49
50/include/ "skeleton.dtsi" 50#include "skeleton.dtsi"
51
52#include <dt-bindings/interrupt-controller/arm-gic.h>
53
54#include <dt-bindings/pinctrl/sun4i-a10.h>
51 55
52/ { 56/ {
53 interrupt-parent = <&gic>; 57 interrupt-parent = <&gic>;
54 58
59 chosen {
60 #address-cells = <1>;
61 #size-cells = <1>;
62 ranges;
63
64 framebuffer@0 {
65 compatible = "allwinner,simple-framebuffer",
66 "simple-framebuffer";
67 allwinner,pipeline = "de_be0-lcd0";
68 clocks = <&pll6 0>;
69 status = "disabled";
70 };
71 };
72
55 cpus { 73 cpus {
56 #address-cells = <1>; 74 #address-cells = <1>;
57 #size-cells = <0>; 75 #size-cells = <0>;
@@ -233,7 +251,7 @@
233 dma: dma-controller@01c02000 { 251 dma: dma-controller@01c02000 {
234 compatible = "allwinner,sun8i-a23-dma"; 252 compatible = "allwinner,sun8i-a23-dma";
235 reg = <0x01c02000 0x1000>; 253 reg = <0x01c02000 0x1000>;
236 interrupts = <0 50 4>; 254 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&ahb1_gates 6>; 255 clocks = <&ahb1_gates 6>;
238 resets = <&ahb1_rst 6>; 256 resets = <&ahb1_rst 6>;
239 #dma-cells = <1>; 257 #dma-cells = <1>;
@@ -246,7 +264,7 @@
246 clock-names = "ahb", "mmc"; 264 clock-names = "ahb", "mmc";
247 resets = <&ahb1_rst 8>; 265 resets = <&ahb1_rst 8>;
248 reset-names = "ahb"; 266 reset-names = "ahb";
249 interrupts = <0 60 4>; 267 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
250 status = "disabled"; 268 status = "disabled";
251 }; 269 };
252 270
@@ -257,7 +275,7 @@
257 clock-names = "ahb", "mmc"; 275 clock-names = "ahb", "mmc";
258 resets = <&ahb1_rst 9>; 276 resets = <&ahb1_rst 9>;
259 reset-names = "ahb"; 277 reset-names = "ahb";
260 interrupts = <0 61 4>; 278 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
261 status = "disabled"; 279 status = "disabled";
262 }; 280 };
263 281
@@ -268,16 +286,16 @@
268 clock-names = "ahb", "mmc"; 286 clock-names = "ahb", "mmc";
269 resets = <&ahb1_rst 10>; 287 resets = <&ahb1_rst 10>;
270 reset-names = "ahb"; 288 reset-names = "ahb";
271 interrupts = <0 62 4>; 289 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
272 status = "disabled"; 290 status = "disabled";
273 }; 291 };
274 292
275 pio: pinctrl@01c20800 { 293 pio: pinctrl@01c20800 {
276 compatible = "allwinner,sun8i-a23-pinctrl"; 294 compatible = "allwinner,sun8i-a23-pinctrl";
277 reg = <0x01c20800 0x400>; 295 reg = <0x01c20800 0x400>;
278 interrupts = <0 11 4>, 296 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
279 <0 15 4>, 297 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
280 <0 17 4>; 298 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&apb1_gates 5>; 299 clocks = <&apb1_gates 5>;
282 gpio-controller; 300 gpio-controller;
283 interrupt-controller; 301 interrupt-controller;
@@ -288,43 +306,43 @@
288 uart0_pins_a: uart0@0 { 306 uart0_pins_a: uart0@0 {
289 allwinner,pins = "PF2", "PF4"; 307 allwinner,pins = "PF2", "PF4";
290 allwinner,function = "uart0"; 308 allwinner,function = "uart0";
291 allwinner,drive = <0>; 309 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
292 allwinner,pull = <0>; 310 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
293 }; 311 };
294 312
295 mmc0_pins_a: mmc0@0 { 313 mmc0_pins_a: mmc0@0 {
296 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; 314 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
297 allwinner,function = "mmc0"; 315 allwinner,function = "mmc0";
298 allwinner,drive = <2>; 316 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
299 allwinner,pull = <0>; 317 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
300 }; 318 };
301 319
302 mmc1_pins_a: mmc1@0 { 320 mmc1_pins_a: mmc1@0 {
303 allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5"; 321 allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5";
304 allwinner,function = "mmc1"; 322 allwinner,function = "mmc1";
305 allwinner,drive = <2>; 323 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
306 allwinner,pull = <0>; 324 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
307 }; 325 };
308 326
309 i2c0_pins_a: i2c0@0 { 327 i2c0_pins_a: i2c0@0 {
310 allwinner,pins = "PH2", "PH3"; 328 allwinner,pins = "PH2", "PH3";
311 allwinner,function = "i2c0"; 329 allwinner,function = "i2c0";
312 allwinner,drive = <0>; 330 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
313 allwinner,pull = <0>; 331 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
314 }; 332 };
315 333
316 i2c1_pins_a: i2c1@0 { 334 i2c1_pins_a: i2c1@0 {
317 allwinner,pins = "PH4", "PH5"; 335 allwinner,pins = "PH4", "PH5";
318 allwinner,function = "i2c1"; 336 allwinner,function = "i2c1";
319 allwinner,drive = <0>; 337 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
320 allwinner,pull = <0>; 338 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
321 }; 339 };
322 340
323 i2c2_pins_a: i2c2@0 { 341 i2c2_pins_a: i2c2@0 {
324 allwinner,pins = "PE12", "PE13"; 342 allwinner,pins = "PE12", "PE13";
325 allwinner,function = "i2c2"; 343 allwinner,function = "i2c2";
326 allwinner,drive = <0>; 344 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
327 allwinner,pull = <0>; 345 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
328 }; 346 };
329 }; 347 };
330 348
@@ -349,21 +367,28 @@
349 timer@01c20c00 { 367 timer@01c20c00 {
350 compatible = "allwinner,sun4i-a10-timer"; 368 compatible = "allwinner,sun4i-a10-timer";
351 reg = <0x01c20c00 0xa0>; 369 reg = <0x01c20c00 0xa0>;
352 interrupts = <0 18 4>, 370 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
353 <0 19 4>; 371 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
354 clocks = <&osc24M>; 372 clocks = <&osc24M>;
355 }; 373 };
356 374
357 wdt0: watchdog@01c20ca0 { 375 wdt0: watchdog@01c20ca0 {
358 compatible = "allwinner,sun6i-a31-wdt"; 376 compatible = "allwinner,sun6i-a31-wdt";
359 reg = <0x01c20ca0 0x20>; 377 reg = <0x01c20ca0 0x20>;
360 interrupts = <0 25 4>; 378 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
379 };
380
381 lradc: lradc@01c22800 {
382 compatible = "allwinner,sun4i-a10-lradc-keys";
383 reg = <0x01c22800 0x100>;
384 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
385 status = "disabled";
361 }; 386 };
362 387
363 uart0: serial@01c28000 { 388 uart0: serial@01c28000 {
364 compatible = "snps,dw-apb-uart"; 389 compatible = "snps,dw-apb-uart";
365 reg = <0x01c28000 0x400>; 390 reg = <0x01c28000 0x400>;
366 interrupts = <0 0 4>; 391 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
367 reg-shift = <2>; 392 reg-shift = <2>;
368 reg-io-width = <4>; 393 reg-io-width = <4>;
369 clocks = <&apb2_gates 16>; 394 clocks = <&apb2_gates 16>;
@@ -376,7 +401,7 @@
376 uart1: serial@01c28400 { 401 uart1: serial@01c28400 {
377 compatible = "snps,dw-apb-uart"; 402 compatible = "snps,dw-apb-uart";
378 reg = <0x01c28400 0x400>; 403 reg = <0x01c28400 0x400>;
379 interrupts = <0 1 4>; 404 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
380 reg-shift = <2>; 405 reg-shift = <2>;
381 reg-io-width = <4>; 406 reg-io-width = <4>;
382 clocks = <&apb2_gates 17>; 407 clocks = <&apb2_gates 17>;
@@ -389,7 +414,7 @@
389 uart2: serial@01c28800 { 414 uart2: serial@01c28800 {
390 compatible = "snps,dw-apb-uart"; 415 compatible = "snps,dw-apb-uart";
391 reg = <0x01c28800 0x400>; 416 reg = <0x01c28800 0x400>;
392 interrupts = <0 2 4>; 417 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
393 reg-shift = <2>; 418 reg-shift = <2>;
394 reg-io-width = <4>; 419 reg-io-width = <4>;
395 clocks = <&apb2_gates 18>; 420 clocks = <&apb2_gates 18>;
@@ -402,7 +427,7 @@
402 uart3: serial@01c28c00 { 427 uart3: serial@01c28c00 {
403 compatible = "snps,dw-apb-uart"; 428 compatible = "snps,dw-apb-uart";
404 reg = <0x01c28c00 0x400>; 429 reg = <0x01c28c00 0x400>;
405 interrupts = <0 3 4>; 430 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
406 reg-shift = <2>; 431 reg-shift = <2>;
407 reg-io-width = <4>; 432 reg-io-width = <4>;
408 clocks = <&apb2_gates 19>; 433 clocks = <&apb2_gates 19>;
@@ -415,7 +440,7 @@
415 uart4: serial@01c29000 { 440 uart4: serial@01c29000 {
416 compatible = "snps,dw-apb-uart"; 441 compatible = "snps,dw-apb-uart";
417 reg = <0x01c29000 0x400>; 442 reg = <0x01c29000 0x400>;
418 interrupts = <0 4 4>; 443 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
419 reg-shift = <2>; 444 reg-shift = <2>;
420 reg-io-width = <4>; 445 reg-io-width = <4>;
421 clocks = <&apb2_gates 20>; 446 clocks = <&apb2_gates 20>;
@@ -428,7 +453,7 @@
428 i2c0: i2c@01c2ac00 { 453 i2c0: i2c@01c2ac00 {
429 compatible = "allwinner,sun6i-a31-i2c"; 454 compatible = "allwinner,sun6i-a31-i2c";
430 reg = <0x01c2ac00 0x400>; 455 reg = <0x01c2ac00 0x400>;
431 interrupts = <0 6 4>; 456 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&apb2_gates 0>; 457 clocks = <&apb2_gates 0>;
433 resets = <&apb2_rst 0>; 458 resets = <&apb2_rst 0>;
434 status = "disabled"; 459 status = "disabled";
@@ -439,7 +464,7 @@
439 i2c1: i2c@01c2b000 { 464 i2c1: i2c@01c2b000 {
440 compatible = "allwinner,sun6i-a31-i2c"; 465 compatible = "allwinner,sun6i-a31-i2c";
441 reg = <0x01c2b000 0x400>; 466 reg = <0x01c2b000 0x400>;
442 interrupts = <0 7 4>; 467 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&apb2_gates 1>; 468 clocks = <&apb2_gates 1>;
444 resets = <&apb2_rst 1>; 469 resets = <&apb2_rst 1>;
445 status = "disabled"; 470 status = "disabled";
@@ -450,7 +475,7 @@
450 i2c2: i2c@01c2b400 { 475 i2c2: i2c@01c2b400 {
451 compatible = "allwinner,sun6i-a31-i2c"; 476 compatible = "allwinner,sun6i-a31-i2c";
452 reg = <0x01c2b400 0x400>; 477 reg = <0x01c2b400 0x400>;
453 interrupts = <0 8 4>; 478 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
454 clocks = <&apb2_gates 2>; 479 clocks = <&apb2_gates 2>;
455 resets = <&apb2_rst 2>; 480 resets = <&apb2_rst 2>;
456 status = "disabled"; 481 status = "disabled";
@@ -466,13 +491,14 @@
466 <0x01c86000 0x2000>; 491 <0x01c86000 0x2000>;
467 interrupt-controller; 492 interrupt-controller;
468 #interrupt-cells = <3>; 493 #interrupt-cells = <3>;
469 interrupts = <1 9 0xf04>; 494 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
470 }; 495 };
471 496
472 rtc: rtc@01f00000 { 497 rtc: rtc@01f00000 {
473 compatible = "allwinner,sun6i-a31-rtc"; 498 compatible = "allwinner,sun6i-a31-rtc";
474 reg = <0x01f00000 0x54>; 499 reg = <0x01f00000 0x54>;
475 interrupts = <0 40 4>, <0 41 4>; 500 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
501 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
476 }; 502 };
477 503
478 prcm@01f01400 { 504 prcm@01f01400 {
@@ -522,7 +548,7 @@
522 r_uart: serial@01f02800 { 548 r_uart: serial@01f02800 {
523 compatible = "snps,dw-apb-uart"; 549 compatible = "snps,dw-apb-uart";
524 reg = <0x01f02800 0x400>; 550 reg = <0x01f02800 0x400>;
525 interrupts = <0 38 4>; 551 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
526 reg-shift = <2>; 552 reg-shift = <2>;
527 reg-io-width = <4>; 553 reg-io-width = <4>;
528 clocks = <&apb0_gates 4>; 554 clocks = <&apb0_gates 4>;
@@ -533,7 +559,7 @@
533 r_pio: pinctrl@01f02c00 { 559 r_pio: pinctrl@01f02c00 {
534 compatible = "allwinner,sun8i-a23-r-pinctrl"; 560 compatible = "allwinner,sun8i-a23-r-pinctrl";
535 reg = <0x01f02c00 0x400>; 561 reg = <0x01f02c00 0x400>;
536 interrupts = <0 45 4>; 562 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
537 clocks = <&apb0_gates 0>; 563 clocks = <&apb0_gates 0>;
538 resets = <&apb0_rst 0>; 564 resets = <&apb0_rst 0>;
539 gpio-controller; 565 gpio-controller;
@@ -545,8 +571,8 @@
545 r_uart_pins_a: r_uart@0 { 571 r_uart_pins_a: r_uart@0 {
546 allwinner,pins = "PL2", "PL3"; 572 allwinner,pins = "PL2", "PL3";
547 allwinner,function = "s_uart"; 573 allwinner,function = "s_uart";
548 allwinner,drive = <0>; 574 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
549 allwinner,pull = <0>; 575 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
550 }; 576 };
551 }; 577 };
552 }; 578 };
diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts
index 11ec71072e81..a3fed2bdf620 100644
--- a/arch/arm/boot/dts/sun9i-a80-optimus.dts
+++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts
@@ -48,7 +48,11 @@
48 */ 48 */
49 49
50/dts-v1/; 50/dts-v1/;
51/include/ "sun9i-a80.dtsi" 51#include "sun9i-a80.dtsi"
52#include "sunxi-common-regulators.dtsi"
53
54#include <dt-bindings/gpio/gpio.h>
55#include <dt-bindings/pinctrl/sun4i-a10.h>
52 56
53/ { 57/ {
54 model = "Merrii A80 Optimus Board"; 58 model = "Merrii A80 Optimus Board";
@@ -63,45 +67,6 @@
63 bootargs = "earlyprintk console=ttyS0,115200"; 67 bootargs = "earlyprintk console=ttyS0,115200";
64 }; 68 };
65 69
66 soc {
67 pio: pinctrl@06000800 {
68 i2c3_pins_a: i2c3@0 {
69 /* Enable internal pull-up */
70 allwinner,pull = <1>;
71 };
72
73 led_pins_optimus: led-pins@0 {
74 allwinner,pins = "PH0", "PH1";
75 allwinner,function = "gpio_out";
76 allwinner,drive = <0>;
77 allwinner,pull = <0>;
78 };
79
80 uart4_pins_a: uart4@0 {
81 /* Enable internal pull-up */
82 allwinner,pull = <1>;
83 };
84 };
85
86 uart0: serial@07000000 {
87 pinctrl-names = "default";
88 pinctrl-0 = <&uart0_pins_a>;
89 status = "okay";
90 };
91
92 uart4: serial@07001000 {
93 pinctrl-names = "default";
94 pinctrl-0 = <&uart4_pins_a>;
95 status = "okay";
96 };
97
98 i2c3: i2c@07003400 {
99 pinctrl-names = "default";
100 pinctrl-0 = <&i2c3_pins_a>;
101 status = "okay";
102 };
103 };
104
105 leds { 70 leds {
106 compatible = "gpio-leds"; 71 compatible = "gpio-leds";
107 pinctrl-names = "default"; 72 pinctrl-names = "default";
@@ -111,14 +76,77 @@
111 76
112 led2 { 77 led2 {
113 label = "optimus:led2:usr"; 78 label = "optimus:led2:usr";
114 gpios = <&pio 7 1 0>; 79 gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>;
115 }; 80 };
116 81
117 /* led3 is on PM15, in R_PIO */ 82 /* led3 is on PM15, in R_PIO */
118 83
119 led4 { 84 led4 {
120 label = "optimus:led4:usr"; 85 label = "optimus:led4:usr";
121 gpios = <&pio 7 0 0>; 86 gpios = <&pio 7 0 GPIO_ACTIVE_HIGH>;
122 }; 87 };
123 }; 88 };
124}; 89};
90
91&i2c3 {
92 pinctrl-names = "default";
93 pinctrl-0 = <&i2c3_pins_a>;
94 status = "okay";
95};
96
97&i2c3_pins_a {
98 /* Enable internal pull-up */
99 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
100};
101
102&pio {
103 led_pins_optimus: led-pins@0 {
104 allwinner,pins = "PH0", "PH1";
105 allwinner,function = "gpio_out";
106 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
107 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
108 };
109
110 mmc0_cd_pin_optimus: mmc0_cd_pin@0 {
111 allwinner,pins = "PH18";
112 allwinner,function = "gpio_in";
113 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
114 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
115 };
116};
117
118&mmc0 {
119 pinctrl-names = "default";
120 pinctrl-0 = <&mmc0_pins>, <&mmc0_cd_pin_optimus>;
121 vmmc-supply = <&reg_vcc3v0>;
122 bus-width = <4>;
123 cd-gpios = <&pio 7 18 GPIO_ACTIVE_HIGH>; /* PH8 */
124 cd-inverted;
125 status = "okay";
126};
127
128&mmc2 {
129 pinctrl-names = "default";
130 pinctrl-0 = <&mmc2_8bit_pins>;
131 vmmc-supply = <&reg_vcc3v0>;
132 bus-width = <8>;
133 non-removable;
134 status = "okay";
135};
136
137&uart0 {
138 pinctrl-names = "default";
139 pinctrl-0 = <&uart0_pins_a>;
140 status = "okay";
141};
142
143&uart4 {
144 pinctrl-names = "default";
145 pinctrl-0 = <&uart4_pins_a>;
146 status = "okay";
147};
148
149&uart4_pins_a {
150 /* Enable internal pull-up */
151 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
152};
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index 9ef4438206a9..f0f6fb91f8c3 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -47,7 +47,11 @@
47 * OTHER DEALINGS IN THE SOFTWARE. 47 * OTHER DEALINGS IN THE SOFTWARE.
48 */ 48 */
49 49
50/include/ "skeleton64.dtsi" 50#include "skeleton64.dtsi"
51
52#include <dt-bindings/interrupt-controller/arm-gic.h>
53
54#include <dt-bindings/pinctrl/sun4i-a10.h>
51 55
52/ { 56/ {
53 interrupt-parent = <&gic>; 57 interrupt-parent = <&gic>;
@@ -205,11 +209,50 @@
205 clock-output-names = "cci400"; 209 clock-output-names = "cci400";
206 }; 210 };
207 211
212 mmc0_clk: clk@06000410 {
213 #clock-cells = <1>;
214 compatible = "allwinner,sun9i-a80-mmc-clk";
215 reg = <0x06000410 0x4>;
216 clocks = <&osc24M>, <&pll4>;
217 clock-output-names = "mmc0", "mmc0_output",
218 "mmc0_sample";
219 };
220
221 mmc1_clk: clk@06000414 {
222 #clock-cells = <1>;
223 compatible = "allwinner,sun9i-a80-mmc-clk";
224 reg = <0x06000414 0x4>;
225 clocks = <&osc24M>, <&pll4>;
226 clock-output-names = "mmc1", "mmc1_output",
227 "mmc1_sample";
228 };
229
230 mmc2_clk: clk@06000418 {
231 #clock-cells = <1>;
232 compatible = "allwinner,sun9i-a80-mmc-clk";
233 reg = <0x06000418 0x4>;
234 clocks = <&osc24M>, <&pll4>;
235 clock-output-names = "mmc2", "mmc2_output",
236 "mmc2_sample";
237 };
238
239 mmc3_clk: clk@0600041c {
240 #clock-cells = <1>;
241 compatible = "allwinner,sun9i-a80-mmc-clk";
242 reg = <0x0600041c 0x4>;
243 clocks = <&osc24M>, <&pll4>;
244 clock-output-names = "mmc3", "mmc3_output",
245 "mmc3_sample";
246 };
247
208 ahb0_gates: clk@06000580 { 248 ahb0_gates: clk@06000580 {
209 #clock-cells = <1>; 249 #clock-cells = <1>;
210 compatible = "allwinner,sun9i-a80-ahb0-gates-clk"; 250 compatible = "allwinner,sun9i-a80-ahb0-gates-clk";
211 reg = <0x06000580 0x4>; 251 reg = <0x06000580 0x4>;
212 clocks = <&ahb0>; 252 clocks = <&ahb0>;
253 clock-indices = <0>, <1>, <3>, <5>, <8>, <12>, <13>,
254 <14>, <15>, <16>, <18>, <20>, <21>,
255 <22>, <23>;
213 clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu", 256 clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu",
214 "ahb0_ss", "ahb0_sd", "ahb0_nand1", 257 "ahb0_ss", "ahb0_sd", "ahb0_nand1",
215 "ahb0_nand0", "ahb0_sdram", 258 "ahb0_nand0", "ahb0_sdram",
@@ -223,6 +266,7 @@
223 compatible = "allwinner,sun9i-a80-ahb1-gates-clk"; 266 compatible = "allwinner,sun9i-a80-ahb1-gates-clk";
224 reg = <0x06000584 0x4>; 267 reg = <0x06000584 0x4>;
225 clocks = <&ahb1>; 268 clocks = <&ahb1>;
269 clock-indices = <0>, <1>, <17>, <21>, <22>, <23>, <24>;
226 clock-output-names = "ahb1_usbotg", "ahb1_usbhci", 270 clock-output-names = "ahb1_usbotg", "ahb1_usbhci",
227 "ahb1_gmac", "ahb1_msgbox", 271 "ahb1_gmac", "ahb1_msgbox",
228 "ahb1_spinlock", "ahb1_hstimer", 272 "ahb1_spinlock", "ahb1_hstimer",
@@ -234,6 +278,8 @@
234 compatible = "allwinner,sun9i-a80-ahb2-gates-clk"; 278 compatible = "allwinner,sun9i-a80-ahb2-gates-clk";
235 reg = <0x06000588 0x4>; 279 reg = <0x06000588 0x4>;
236 clocks = <&ahb2>; 280 clocks = <&ahb2>;
281 clock-indices = <0>, <1>, <2>, <4>, <5>, <7>, <8>,
282 <11>;
237 clock-output-names = "ahb2_lcd0", "ahb2_lcd1", 283 clock-output-names = "ahb2_lcd0", "ahb2_lcd1",
238 "ahb2_edp", "ahb2_csi", "ahb2_hdmi", 284 "ahb2_edp", "ahb2_csi", "ahb2_hdmi",
239 "ahb2_de", "ahb2_mp", "ahb2_mipi_dsi"; 285 "ahb2_de", "ahb2_mp", "ahb2_mipi_dsi";
@@ -244,6 +290,8 @@
244 compatible = "allwinner,sun9i-a80-apb0-gates-clk"; 290 compatible = "allwinner,sun9i-a80-apb0-gates-clk";
245 reg = <0x06000590 0x4>; 291 reg = <0x06000590 0x4>;
246 clocks = <&apb0>; 292 clocks = <&apb0>;
293 clock-indices = <1>, <5>, <11>, <12>, <13>, <15>,
294 <17>, <18>, <19>;
247 clock-output-names = "apb0_spdif", "apb0_pio", 295 clock-output-names = "apb0_spdif", "apb0_pio",
248 "apb0_ac97", "apb0_i2s0", "apb0_i2s1", 296 "apb0_ac97", "apb0_i2s0", "apb0_i2s1",
249 "apb0_lradc", "apb0_gpadc", "apb0_twd", 297 "apb0_lradc", "apb0_gpadc", "apb0_twd",
@@ -255,6 +303,8 @@
255 compatible = "allwinner,sun9i-a80-apb1-gates-clk"; 303 compatible = "allwinner,sun9i-a80-apb1-gates-clk";
256 reg = <0x06000594 0x4>; 304 reg = <0x06000594 0x4>;
257 clocks = <&apb1>; 305 clocks = <&apb1>;
306 clock-indices = <0>, <1>, <2>, <3>, <4>,
307 <16>, <17>, <18>, <19>, <20>, <21>;
258 clock-output-names = "apb1_i2c0", "apb1_i2c1", 308 clock-output-names = "apb1_i2c0", "apb1_i2c1",
259 "apb1_i2c2", "apb1_i2c3", "apb1_i2c4", 309 "apb1_i2c2", "apb1_i2c3", "apb1_i2c4",
260 "apb1_uart0", "apb1_uart1", 310 "apb1_uart0", "apb1_uart1",
@@ -273,6 +323,67 @@
273 */ 323 */
274 ranges = <0 0 0 0x20000000>; 324 ranges = <0 0 0 0x20000000>;
275 325
326 mmc0: mmc@01c0f000 {
327 compatible = "allwinner,sun5i-a13-mmc";
328 reg = <0x01c0f000 0x1000>;
329 clocks = <&mmc_config_clk 0>, <&mmc0_clk 0>,
330 <&mmc0_clk 1>, <&mmc0_clk 2>;
331 clock-names = "ahb", "mmc", "output", "sample";
332 resets = <&mmc_config_clk 0>;
333 reset-names = "ahb";
334 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
335 status = "disabled";
336 };
337
338 mmc1: mmc@01c10000 {
339 compatible = "allwinner,sun5i-a13-mmc";
340 reg = <0x01c10000 0x1000>;
341 clocks = <&mmc_config_clk 1>, <&mmc1_clk 0>,
342 <&mmc1_clk 1>, <&mmc1_clk 2>;
343 clock-names = "ahb", "mmc", "output", "sample";
344 resets = <&mmc_config_clk 1>;
345 reset-names = "ahb";
346 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
347 status = "disabled";
348 };
349
350 mmc2: mmc@01c11000 {
351 compatible = "allwinner,sun5i-a13-mmc";
352 reg = <0x01c11000 0x1000>;
353 clocks = <&mmc_config_clk 2>, <&mmc2_clk 0>,
354 <&mmc2_clk 1>, <&mmc2_clk 2>;
355 clock-names = "ahb", "mmc", "output", "sample";
356 resets = <&mmc_config_clk 2>;
357 reset-names = "ahb";
358 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
359 status = "disabled";
360 };
361
362 mmc3: mmc@01c12000 {
363 compatible = "allwinner,sun5i-a13-mmc";
364 reg = <0x01c12000 0x1000>;
365 clocks = <&mmc_config_clk 3>, <&mmc3_clk 0>,
366 <&mmc3_clk 1>, <&mmc3_clk 2>;
367 clock-names = "ahb", "mmc", "output", "sample";
368 resets = <&mmc_config_clk 3>;
369 reset-names = "ahb";
370 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
371 status = "disabled";
372 };
373
374 mmc_config_clk: clk@01c13000 {
375 compatible = "allwinner,sun9i-a80-mmc-config-clk";
376 reg = <0x01c13000 0x10>;
377 clocks = <&ahb0_gates 8>;
378 clock-names = "ahb";
379 resets = <&ahb0_resets 8>;
380 reset-names = "ahb";
381 #clock-cells = <1>;
382 #reset-cells = <1>;
383 clock-output-names = "mmc0_config", "mmc1_config",
384 "mmc2_config", "mmc3_config";
385 };
386
276 gic: interrupt-controller@01c41000 { 387 gic: interrupt-controller@01c41000 {
277 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; 388 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
278 reg = <0x01c41000 0x1000>, 389 reg = <0x01c41000 0x1000>,
@@ -281,7 +392,7 @@
281 <0x01c46000 0x2000>; 392 <0x01c46000 0x2000>;
282 interrupt-controller; 393 interrupt-controller;
283 #interrupt-cells = <3>; 394 #interrupt-cells = <3>;
284 interrupts = <1 9 0xf04>; 395 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
285 }; 396 };
286 397
287 ahb0_resets: reset@060005a0 { 398 ahb0_resets: reset@060005a0 {
@@ -317,12 +428,12 @@
317 timer@06000c00 { 428 timer@06000c00 {
318 compatible = "allwinner,sun4i-a10-timer"; 429 compatible = "allwinner,sun4i-a10-timer";
319 reg = <0x06000c00 0xa0>; 430 reg = <0x06000c00 0xa0>;
320 interrupts = <0 18 4>, 431 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
321 <0 19 4>, 432 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
322 <0 20 4>, 433 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
323 <0 21 4>, 434 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
324 <0 22 4>, 435 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
325 <0 23 4>; 436 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
326 437
327 clocks = <&osc24M>; 438 clocks = <&osc24M>;
328 }; 439 };
@@ -330,11 +441,11 @@
330 pio: pinctrl@06000800 { 441 pio: pinctrl@06000800 {
331 compatible = "allwinner,sun9i-a80-pinctrl"; 442 compatible = "allwinner,sun9i-a80-pinctrl";
332 reg = <0x06000800 0x400>; 443 reg = <0x06000800 0x400>;
333 interrupts = <0 11 4>, 444 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
334 <0 15 4>, 445 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
335 <0 16 4>, 446 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
336 <0 17 4>, 447 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
337 <0 120 4>; 448 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&apb0_gates 5>; 449 clocks = <&apb0_gates 5>;
339 gpio-controller; 450 gpio-controller;
340 interrupt-controller; 451 interrupt-controller;
@@ -345,29 +456,46 @@
345 i2c3_pins_a: i2c3@0 { 456 i2c3_pins_a: i2c3@0 {
346 allwinner,pins = "PG10", "PG11"; 457 allwinner,pins = "PG10", "PG11";
347 allwinner,function = "i2c3"; 458 allwinner,function = "i2c3";
348 allwinner,drive = <0>; 459 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
349 allwinner,pull = <0>; 460 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
461 };
462
463 mmc0_pins: mmc0 {
464 allwinner,pins = "PF0", "PF1" ,"PF2", "PF3",
465 "PF4", "PF5";
466 allwinner,function = "mmc0";
467 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
468 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
469 };
470
471 mmc2_8bit_pins: mmc2_8bit {
472 allwinner,pins = "PC6", "PC7", "PC8", "PC9",
473 "PC10", "PC11", "PC12",
474 "PC13", "PC14", "PC15";
475 allwinner,function = "mmc2";
476 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
477 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
350 }; 478 };
351 479
352 uart0_pins_a: uart0@0 { 480 uart0_pins_a: uart0@0 {
353 allwinner,pins = "PH12", "PH13"; 481 allwinner,pins = "PH12", "PH13";
354 allwinner,function = "uart0"; 482 allwinner,function = "uart0";
355 allwinner,drive = <0>; 483 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
356 allwinner,pull = <0>; 484 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
357 }; 485 };
358 486
359 uart4_pins_a: uart4@0 { 487 uart4_pins_a: uart4@0 {
360 allwinner,pins = "PG12", "PG13", "PG14", "PG15"; 488 allwinner,pins = "PG12", "PG13", "PG14", "PG15";
361 allwinner,function = "uart4"; 489 allwinner,function = "uart4";
362 allwinner,drive = <0>; 490 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
363 allwinner,pull = <0>; 491 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
364 }; 492 };
365 }; 493 };
366 494
367 uart0: serial@07000000 { 495 uart0: serial@07000000 {
368 compatible = "snps,dw-apb-uart"; 496 compatible = "snps,dw-apb-uart";
369 reg = <0x07000000 0x400>; 497 reg = <0x07000000 0x400>;
370 interrupts = <0 0 4>; 498 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
371 reg-shift = <2>; 499 reg-shift = <2>;
372 reg-io-width = <4>; 500 reg-io-width = <4>;
373 clocks = <&apb1_gates 16>; 501 clocks = <&apb1_gates 16>;
@@ -378,7 +506,7 @@
378 uart1: serial@07000400 { 506 uart1: serial@07000400 {
379 compatible = "snps,dw-apb-uart"; 507 compatible = "snps,dw-apb-uart";
380 reg = <0x07000400 0x400>; 508 reg = <0x07000400 0x400>;
381 interrupts = <0 1 4>; 509 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
382 reg-shift = <2>; 510 reg-shift = <2>;
383 reg-io-width = <4>; 511 reg-io-width = <4>;
384 clocks = <&apb1_gates 17>; 512 clocks = <&apb1_gates 17>;
@@ -389,7 +517,7 @@
389 uart2: serial@07000800 { 517 uart2: serial@07000800 {
390 compatible = "snps,dw-apb-uart"; 518 compatible = "snps,dw-apb-uart";
391 reg = <0x07000800 0x400>; 519 reg = <0x07000800 0x400>;
392 interrupts = <0 2 4>; 520 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
393 reg-shift = <2>; 521 reg-shift = <2>;
394 reg-io-width = <4>; 522 reg-io-width = <4>;
395 clocks = <&apb1_gates 18>; 523 clocks = <&apb1_gates 18>;
@@ -400,7 +528,7 @@
400 uart3: serial@07000c00 { 528 uart3: serial@07000c00 {
401 compatible = "snps,dw-apb-uart"; 529 compatible = "snps,dw-apb-uart";
402 reg = <0x07000c00 0x400>; 530 reg = <0x07000c00 0x400>;
403 interrupts = <0 3 4>; 531 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
404 reg-shift = <2>; 532 reg-shift = <2>;
405 reg-io-width = <4>; 533 reg-io-width = <4>;
406 clocks = <&apb1_gates 19>; 534 clocks = <&apb1_gates 19>;
@@ -411,7 +539,7 @@
411 uart4: serial@07001000 { 539 uart4: serial@07001000 {
412 compatible = "snps,dw-apb-uart"; 540 compatible = "snps,dw-apb-uart";
413 reg = <0x07001000 0x400>; 541 reg = <0x07001000 0x400>;
414 interrupts = <0 4 4>; 542 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
415 reg-shift = <2>; 543 reg-shift = <2>;
416 reg-io-width = <4>; 544 reg-io-width = <4>;
417 clocks = <&apb1_gates 20>; 545 clocks = <&apb1_gates 20>;
@@ -422,7 +550,7 @@
422 uart5: serial@07001400 { 550 uart5: serial@07001400 {
423 compatible = "snps,dw-apb-uart"; 551 compatible = "snps,dw-apb-uart";
424 reg = <0x07001400 0x400>; 552 reg = <0x07001400 0x400>;
425 interrupts = <0 5 4>; 553 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
426 reg-shift = <2>; 554 reg-shift = <2>;
427 reg-io-width = <4>; 555 reg-io-width = <4>;
428 clocks = <&apb1_gates 21>; 556 clocks = <&apb1_gates 21>;
@@ -433,7 +561,7 @@
433 i2c0: i2c@07002800 { 561 i2c0: i2c@07002800 {
434 compatible = "allwinner,sun6i-a31-i2c"; 562 compatible = "allwinner,sun6i-a31-i2c";
435 reg = <0x07002800 0x400>; 563 reg = <0x07002800 0x400>;
436 interrupts = <0 6 4>; 564 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
437 clocks = <&apb1_gates 0>; 565 clocks = <&apb1_gates 0>;
438 resets = <&apb1_resets 0>; 566 resets = <&apb1_resets 0>;
439 status = "disabled"; 567 status = "disabled";
@@ -444,7 +572,7 @@
444 i2c1: i2c@07002c00 { 572 i2c1: i2c@07002c00 {
445 compatible = "allwinner,sun6i-a31-i2c"; 573 compatible = "allwinner,sun6i-a31-i2c";
446 reg = <0x07002c00 0x400>; 574 reg = <0x07002c00 0x400>;
447 interrupts = <0 7 4>; 575 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&apb1_gates 1>; 576 clocks = <&apb1_gates 1>;
449 resets = <&apb1_resets 1>; 577 resets = <&apb1_resets 1>;
450 status = "disabled"; 578 status = "disabled";
@@ -455,7 +583,7 @@
455 i2c2: i2c@07003000 { 583 i2c2: i2c@07003000 {
456 compatible = "allwinner,sun6i-a31-i2c"; 584 compatible = "allwinner,sun6i-a31-i2c";
457 reg = <0x07003000 0x400>; 585 reg = <0x07003000 0x400>;
458 interrupts = <0 8 4>; 586 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
459 clocks = <&apb1_gates 2>; 587 clocks = <&apb1_gates 2>;
460 resets = <&apb1_resets 2>; 588 resets = <&apb1_resets 2>;
461 status = "disabled"; 589 status = "disabled";
@@ -466,7 +594,7 @@
466 i2c3: i2c@07003400 { 594 i2c3: i2c@07003400 {
467 compatible = "allwinner,sun6i-a31-i2c"; 595 compatible = "allwinner,sun6i-a31-i2c";
468 reg = <0x07003400 0x400>; 596 reg = <0x07003400 0x400>;
469 interrupts = <0 9 4>; 597 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
470 clocks = <&apb1_gates 3>; 598 clocks = <&apb1_gates 3>;
471 resets = <&apb1_resets 3>; 599 resets = <&apb1_resets 3>;
472 status = "disabled"; 600 status = "disabled";
@@ -477,7 +605,7 @@
477 i2c4: i2c@07003800 { 605 i2c4: i2c@07003800 {
478 compatible = "allwinner,sun6i-a31-i2c"; 606 compatible = "allwinner,sun6i-a31-i2c";
479 reg = <0x07003800 0x400>; 607 reg = <0x07003800 0x400>;
480 interrupts = <0 10 4>; 608 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
481 clocks = <&apb1_gates 4>; 609 clocks = <&apb1_gates 4>;
482 resets = <&apb1_resets 4>; 610 resets = <&apb1_resets 4>;
483 status = "disabled"; 611 status = "disabled";
@@ -488,13 +616,13 @@
488 r_wdt: watchdog@08001000 { 616 r_wdt: watchdog@08001000 {
489 compatible = "allwinner,sun6i-a31-wdt"; 617 compatible = "allwinner,sun6i-a31-wdt";
490 reg = <0x08001000 0x20>; 618 reg = <0x08001000 0x20>;
491 interrupts = <0 36 4>; 619 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
492 }; 620 };
493 621
494 r_uart: serial@08002800 { 622 r_uart: serial@08002800 {
495 compatible = "snps,dw-apb-uart"; 623 compatible = "snps,dw-apb-uart";
496 reg = <0x08002800 0x400>; 624 reg = <0x08002800 0x400>;
497 interrupts = <0 38 4>; 625 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
498 reg-shift = <2>; 626 reg-shift = <2>;
499 reg-io-width = <4>; 627 reg-io-width = <4>;
500 clocks = <&osc24M>; 628 clocks = <&osc24M>;
diff --git a/arch/arm/boot/dts/sunxi-common-regulators.dtsi b/arch/arm/boot/dts/sunxi-common-regulators.dtsi
index d8876634f965..e02baa66b33c 100644
--- a/arch/arm/boot/dts/sunxi-common-regulators.dtsi
+++ b/arch/arm/boot/dts/sunxi-common-regulators.dtsi
@@ -47,39 +47,40 @@
47 * OTHER DEALINGS IN THE SOFTWARE. 47 * OTHER DEALINGS IN THE SOFTWARE.
48 */ 48 */
49 49
50/ { 50#include <dt-bindings/gpio/gpio.h>
51 soc@01c00000 { 51#include <dt-bindings/pinctrl/sun4i-a10.h>
52 pio: pinctrl@01c20800 {
53 ahci_pwr_pin_a: ahci_pwr_pin@0 {
54 allwinner,pins = "PB8";
55 allwinner,function = "gpio_out";
56 allwinner,drive = <0>;
57 allwinner,pull = <0>;
58 };
59 52
60 usb0_vbus_pin_a: usb0_vbus_pin@0 { 53&pio {
61 allwinner,pins = "PB9"; 54 ahci_pwr_pin_a: ahci_pwr_pin@0 {
62 allwinner,function = "gpio_out"; 55 allwinner,pins = "PB8";
63 allwinner,drive = <0>; 56 allwinner,function = "gpio_out";
64 allwinner,pull = <0>; 57 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
65 }; 58 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
59 };
66 60
67 usb1_vbus_pin_a: usb1_vbus_pin@0 { 61 usb0_vbus_pin_a: usb0_vbus_pin@0 {
68 allwinner,pins = "PH6"; 62 allwinner,pins = "PB9";
69 allwinner,function = "gpio_out"; 63 allwinner,function = "gpio_out";
70 allwinner,drive = <0>; 64 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
71 allwinner,pull = <0>; 65 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
72 }; 66 };
73 67
74 usb2_vbus_pin_a: usb2_vbus_pin@0 { 68 usb1_vbus_pin_a: usb1_vbus_pin@0 {
75 allwinner,pins = "PH3"; 69 allwinner,pins = "PH6";
76 allwinner,function = "gpio_out"; 70 allwinner,function = "gpio_out";
77 allwinner,drive = <0>; 71 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
78 allwinner,pull = <0>; 72 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
79 };
80 };
81 }; 73 };
82 74
75 usb2_vbus_pin_a: usb2_vbus_pin@0 {
76 allwinner,pins = "PH3";
77 allwinner,function = "gpio_out";
78 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
79 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
80 };
81};
82
83/ {
83 reg_ahci_5v: ahci-5v { 84 reg_ahci_5v: ahci-5v {
84 compatible = "regulator-fixed"; 85 compatible = "regulator-fixed";
85 pinctrl-names = "default"; 86 pinctrl-names = "default";
@@ -89,7 +90,7 @@
89 regulator-max-microvolt = <5000000>; 90 regulator-max-microvolt = <5000000>;
90 regulator-boot-on; 91 regulator-boot-on;
91 enable-active-high; 92 enable-active-high;
92 gpio = <&pio 1 8 0>; 93 gpio = <&pio 1 8 GPIO_ACTIVE_HIGH>;
93 status = "disabled"; 94 status = "disabled";
94 }; 95 };
95 96
@@ -101,7 +102,7 @@
101 regulator-min-microvolt = <5000000>; 102 regulator-min-microvolt = <5000000>;
102 regulator-max-microvolt = <5000000>; 103 regulator-max-microvolt = <5000000>;
103 enable-active-high; 104 enable-active-high;
104 gpio = <&pio 1 9 0>; 105 gpio = <&pio 1 9 GPIO_ACTIVE_HIGH>;
105 status = "disabled"; 106 status = "disabled";
106 }; 107 };
107 108
@@ -113,7 +114,7 @@
113 regulator-min-microvolt = <5000000>; 114 regulator-min-microvolt = <5000000>;
114 regulator-max-microvolt = <5000000>; 115 regulator-max-microvolt = <5000000>;
115 enable-active-high; 116 enable-active-high;
116 gpio = <&pio 7 6 0>; 117 gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>;
117 status = "disabled"; 118 status = "disabled";
118 }; 119 };
119 120
@@ -125,7 +126,7 @@
125 regulator-min-microvolt = <5000000>; 126 regulator-min-microvolt = <5000000>;
126 regulator-max-microvolt = <5000000>; 127 regulator-max-microvolt = <5000000>;
127 enable-active-high; 128 enable-active-high;
128 gpio = <&pio 7 3 0>; 129 gpio = <&pio 7 3 GPIO_ACTIVE_HIGH>;
129 status = "disabled"; 130 status = "disabled";
130 }; 131 };
131 132
diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts b/arch/arm/boot/dts/tegra124-nyan-big.dts
index 53181d310247..004e8e4e1c04 100644
--- a/arch/arm/boot/dts/tegra124-nyan-big.dts
+++ b/arch/arm/boot/dts/tegra124-nyan-big.dts
@@ -1131,6 +1131,8 @@
1131 clock-names = "pll_a", "pll_a_out0", "mclk"; 1131 clock-names = "pll_a", "pll_a_out0", "mclk";
1132 1132
1133 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>; 1133 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>;
1134 nvidia,mic-det-gpios =
1135 <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
1134 }; 1136 };
1135}; 1137};
1136 1138
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 8acf5d85c99d..e5527f742696 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -68,9 +68,9 @@
68 reset-names = "2d"; 68 reset-names = "2d";
69 }; 69 };
70 70
71 gr3d@54140000 { 71 gr3d@54180000 {
72 compatible = "nvidia,tegra20-gr3d"; 72 compatible = "nvidia,tegra20-gr3d";
73 reg = <0x54140000 0x00040000>; 73 reg = <0x54180000 0x00040000>;
74 clocks = <&tegra_car TEGRA20_CLK_GR3D>; 74 clocks = <&tegra_car TEGRA20_CLK_GR3D>;
75 resets = <&tegra_car 24>; 75 resets = <&tegra_car 24>;
76 reset-names = "3d"; 76 reset-names = "3d";
@@ -130,9 +130,9 @@
130 status = "disabled"; 130 status = "disabled";
131 }; 131 };
132 132
133 dsi@542c0000 { 133 dsi@54300000 {
134 compatible = "nvidia,tegra20-dsi"; 134 compatible = "nvidia,tegra20-dsi";
135 reg = <0x542c0000 0x00040000>; 135 reg = <0x54300000 0x00040000>;
136 clocks = <&tegra_car TEGRA20_CLK_DSI>; 136 clocks = <&tegra_car TEGRA20_CLK_DSI>;
137 resets = <&tegra_car 48>; 137 resets = <&tegra_car 48>;
138 reset-names = "dsi"; 138 reset-names = "dsi";
@@ -140,7 +140,7 @@
140 }; 140 };
141 }; 141 };
142 142
143 timer@50004600 { 143 timer@50040600 {
144 compatible = "arm,cortex-a9-twd-timer"; 144 compatible = "arm,cortex-a9-twd-timer";
145 reg = <0x50040600 0x20>; 145 reg = <0x50040600 0x20>;
146 interrupts = <GIC_PPI 13 146 interrupts = <GIC_PPI 13
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index cbf5a1ae0ca7..a1b682ea01bd 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -189,7 +189,7 @@
189 189
190 /* ALS and Proximity sensor */ 190 /* ALS and Proximity sensor */
191 isl29028@44 { 191 isl29028@44 {
192 compatible = "isl,isl29028"; 192 compatible = "isil,isl29028";
193 reg = <0x44>; 193 reg = <0x44>;
194 interrupt-parent = <&gpio>; 194 interrupt-parent = <&gpio>;
195 interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>; 195 interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 99475f6e76a3..db4810df142c 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -225,7 +225,7 @@
225 }; 225 };
226 }; 226 };
227 227
228 timer@50004600 { 228 timer@50040600 {
229 compatible = "arm,cortex-a9-twd-timer"; 229 compatible = "arm,cortex-a9-twd-timer";
230 reg = <0x50040600 0x20>; 230 reg = <0x50040600 0x20>;
231 interrupts = <GIC_PPI 13 231 interrupts = <GIC_PPI 13
diff --git a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
index 56a452bc326c..36cafbfa1bfa 100644
--- a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
@@ -35,7 +35,7 @@
35 regulator-name = "usbh_vbus"; 35 regulator-name = "usbh_vbus";
36 regulator-min-microvolt = <5000000>; 36 regulator-min-microvolt = <5000000>;
37 regulator-max-microvolt = <5000000>; 37 regulator-max-microvolt = <5000000>;
38 gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; 38 gpio = <&gpio2 19 GPIO_ACTIVE_LOW>;
39 vin-supply = <&sys_5v0_reg>; 39 vin-supply = <&sys_5v0_reg>;
40 }; 40 };
41 }; 41 };
diff --git a/arch/arm/boot/dts/vf-colibri.dtsi b/arch/arm/boot/dts/vf-colibri.dtsi
index 82f5728be5c9..5c2b7320856d 100644
--- a/arch/arm/boot/dts/vf-colibri.dtsi
+++ b/arch/arm/boot/dts/vf-colibri.dtsi
@@ -31,7 +31,7 @@
31 pinctrl-names = "default"; 31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_esdhc1>; 32 pinctrl-0 = <&pinctrl_esdhc1>;
33 bus-width = <4>; 33 bus-width = <4>;
34 cd-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; 34 cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
35}; 35};
36 36
37&fec1 { 37&fec1 {
@@ -121,6 +121,7 @@
121 121
122 pinctrl_fec1: fec1grp { 122 pinctrl_fec1: fec1grp {
123 fsl,pins = < 123 fsl,pins = <
124 VF610_PAD_PTA6__RMII_CLKOUT 0x30d2
124 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 125 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
125 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 126 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
126 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 127 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi
index de6700542714..1dbf8d2d1ddf 100644
--- a/arch/arm/boot/dts/vf500.dtsi
+++ b/arch/arm/boot/dts/vf500.dtsi
@@ -94,23 +94,23 @@
94 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 94 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
95}; 95};
96 96
97&gpio1 { 97&gpio0 {
98 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 98 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
99}; 99};
100 100
101&gpio2 { 101&gpio1 {
102 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 102 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
103}; 103};
104 104
105&gpio3 { 105&gpio2 {
106 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 106 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
107}; 107};
108 108
109&gpio4 { 109&gpio3 {
110 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 110 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
111}; 111};
112 112
113&gpio5 { 113&gpio4 {
114 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 114 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
115}; 115};
116 116
@@ -130,6 +130,14 @@
130 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 130 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
131}; 131};
132 132
133&snvsrtc {
134 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
135};
136
137&src {
138 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
139};
140
133&uart0 { 141&uart0 {
134 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 142 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
135}; 143};
@@ -169,3 +177,8 @@
169&usbphy1 { 177&usbphy1 {
170 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 178 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
171}; 179};
180
181&wdoga5 {
182 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
183 status = "okay";
184};
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts
index f2b64b1b00fa..f64fddce3e2a 100644
--- a/arch/arm/boot/dts/vf610-twr.dts
+++ b/arch/arm/boot/dts/vf610-twr.dts
@@ -123,7 +123,7 @@
123 pinctrl-names = "default"; 123 pinctrl-names = "default";
124 pinctrl-0 = <&pinctrl_esdhc1>; 124 pinctrl-0 = <&pinctrl_esdhc1>;
125 bus-width = <4>; 125 bus-width = <4>;
126 cd-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; 126 cd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
127 status = "okay"; 127 status = "okay";
128}; 128};
129 129
diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
index 505969ae8093..a29c7ce15eaf 100644
--- a/arch/arm/boot/dts/vfxxx.dtsi
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -22,11 +22,11 @@
22 serial3 = &uart3; 22 serial3 = &uart3;
23 serial4 = &uart4; 23 serial4 = &uart4;
24 serial5 = &uart5; 24 serial5 = &uart5;
25 gpio0 = &gpio1; 25 gpio0 = &gpio0;
26 gpio1 = &gpio2; 26 gpio1 = &gpio1;
27 gpio2 = &gpio3; 27 gpio2 = &gpio2;
28 gpio3 = &gpio4; 28 gpio3 = &gpio3;
29 gpio4 = &gpio5; 29 gpio4 = &gpio4;
30 usbphy0 = &usbphy0; 30 usbphy0 = &usbphy0;
31 usbphy1 = &usbphy1; 31 usbphy1 = &usbphy1;
32 }; 32 };
@@ -43,6 +43,13 @@
43 clock-frequency = <32768>; 43 clock-frequency = <32768>;
44 }; 44 };
45 45
46 reboot: syscon-reboot {
47 compatible = "syscon-reboot";
48 regmap = <&src>;
49 offset = <0x0>;
50 mask = <0x1000>;
51 };
52
46 soc { 53 soc {
47 #address-cells = <1>; 54 #address-cells = <1>;
48 #size-cells = <1>; 55 #size-cells = <1>;
@@ -184,7 +191,7 @@
184 status = "disabled"; 191 status = "disabled";
185 }; 192 };
186 193
187 wdog@4003e000 { 194 wdoga5: wdog@4003e000 {
188 compatible = "fsl,vf610-wdt", "fsl,imx21-wdt"; 195 compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
189 reg = <0x4003e000 0x1000>; 196 reg = <0x4003e000 0x1000>;
190 clocks = <&clks VF610_CLK_WDT>; 197 clocks = <&clks VF610_CLK_WDT>;
@@ -209,7 +216,7 @@
209 #gpio-range-cells = <3>; 216 #gpio-range-cells = <3>;
210 }; 217 };
211 218
212 gpio1: gpio@40049000 { 219 gpio0: gpio@40049000 {
213 compatible = "fsl,vf610-gpio"; 220 compatible = "fsl,vf610-gpio";
214 reg = <0x40049000 0x1000 0x400ff000 0x40>; 221 reg = <0x40049000 0x1000 0x400ff000 0x40>;
215 gpio-controller; 222 gpio-controller;
@@ -219,7 +226,7 @@
219 gpio-ranges = <&iomuxc 0 0 32>; 226 gpio-ranges = <&iomuxc 0 0 32>;
220 }; 227 };
221 228
222 gpio2: gpio@4004a000 { 229 gpio1: gpio@4004a000 {
223 compatible = "fsl,vf610-gpio"; 230 compatible = "fsl,vf610-gpio";
224 reg = <0x4004a000 0x1000 0x400ff040 0x40>; 231 reg = <0x4004a000 0x1000 0x400ff040 0x40>;
225 gpio-controller; 232 gpio-controller;
@@ -229,7 +236,7 @@
229 gpio-ranges = <&iomuxc 0 32 32>; 236 gpio-ranges = <&iomuxc 0 32 32>;
230 }; 237 };
231 238
232 gpio3: gpio@4004b000 { 239 gpio2: gpio@4004b000 {
233 compatible = "fsl,vf610-gpio"; 240 compatible = "fsl,vf610-gpio";
234 reg = <0x4004b000 0x1000 0x400ff080 0x40>; 241 reg = <0x4004b000 0x1000 0x400ff080 0x40>;
235 gpio-controller; 242 gpio-controller;
@@ -239,7 +246,7 @@
239 gpio-ranges = <&iomuxc 0 64 32>; 246 gpio-ranges = <&iomuxc 0 64 32>;
240 }; 247 };
241 248
242 gpio4: gpio@4004c000 { 249 gpio3: gpio@4004c000 {
243 compatible = "fsl,vf610-gpio"; 250 compatible = "fsl,vf610-gpio";
244 reg = <0x4004c000 0x1000 0x400ff0c0 0x40>; 251 reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
245 gpio-controller; 252 gpio-controller;
@@ -249,7 +256,7 @@
249 gpio-ranges = <&iomuxc 0 96 32>; 256 gpio-ranges = <&iomuxc 0 96 32>;
250 }; 257 };
251 258
252 gpio5: gpio@4004d000 { 259 gpio4: gpio@4004d000 {
253 compatible = "fsl,vf610-gpio"; 260 compatible = "fsl,vf610-gpio";
254 reg = <0x4004d000 0x1000 0x400ff100 0x40>; 261 reg = <0x4004d000 0x1000 0x400ff100 0x40>;
255 gpio-controller; 262 gpio-controller;
@@ -318,6 +325,11 @@
318 clocks = <&clks VF610_CLK_USBC0>; 325 clocks = <&clks VF610_CLK_USBC0>;
319 status = "disabled"; 326 status = "disabled";
320 }; 327 };
328
329 src: src@4006e000 {
330 compatible = "fsl,vf610-src", "syscon";
331 reg = <0x4006e000 0x1000>;
332 };
321 }; 333 };
322 334
323 aips1: aips-bus@40080000 { 335 aips1: aips-bus@40080000 {
@@ -339,6 +351,20 @@
339 status = "disabled"; 351 status = "disabled";
340 }; 352 };
341 353
354 snvs0: snvs@400a7000 {
355 compatible = "fsl,sec-v4.0-mon", "simple-bus";
356 #address-cells = <1>;
357 #size-cells = <1>;
358 ranges = <0 0x400a7000 0x2000>;
359
360 snvsrtc: snvs-rtc-lp@34 {
361 compatible = "fsl,sec-v4.0-mon-rtc-lp";
362 reg = <0x34 0x58>;
363 clocks = <&clks VF610_CLK_SNVS>;
364 clock-names = "snvs-rtc";
365 };
366 };
367
342 uart4: serial@400a9000 { 368 uart4: serial@400a9000 {
343 compatible = "fsl,vf610-lpuart"; 369 compatible = "fsl,vf610-lpuart";
344 reg = <0x400a9000 0x1000>; 370 reg = <0x400a9000 0x1000>;
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index ee3e5d675b05..a5cd2eda3edf 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -237,7 +237,7 @@
237 slcr: slcr@f8000000 { 237 slcr: slcr@f8000000 {
238 #address-cells = <1>; 238 #address-cells = <1>;
239 #size-cells = <1>; 239 #size-cells = <1>;
240 compatible = "xlnx,zynq-slcr", "syscon"; 240 compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
241 reg = <0xF8000000 0x1000>; 241 reg = <0xF8000000 0x1000>;
242 ranges; 242 ranges;
243 clkc: clkc@100 { 243 clkc: clkc@100 {
@@ -257,6 +257,12 @@
257 "dbg_trc", "dbg_apb"; 257 "dbg_trc", "dbg_apb";
258 reg = <0x100 0x100>; 258 reg = <0x100 0x100>;
259 }; 259 };
260
261 pinctrl0: pinctrl@700 {
262 compatible = "xlnx,pinctrl-zynq";
263 reg = <0x700 0x200>;
264 syscon = <&slcr>;
265 };
260 }; 266 };
261 267
262 dmac_s: dmac@f8003000 { 268 dmac_s: dmac@f8003000 {
@@ -314,14 +320,32 @@
314 clocks = <&clkc 4>; 320 clocks = <&clkc 4>;
315 }; 321 };
316 322
323 usb0: usb@e0002000 {
324 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
325 status = "disabled";
326 clocks = <&clkc 28>;
327 interrupt-parent = <&intc>;
328 interrupts = <0 21 4>;
329 reg = <0xe0002000 0x1000>;
330 phy_type = "ulpi";
331 };
332
333 usb1: usb@e0003000 {
334 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
335 status = "disabled";
336 clocks = <&clkc 29>;
337 interrupt-parent = <&intc>;
338 interrupts = <0 44 4>;
339 reg = <0xe0003000 0x1000>;
340 phy_type = "ulpi";
341 };
342
317 watchdog0: watchdog@f8005000 { 343 watchdog0: watchdog@f8005000 {
318 clocks = <&clkc 45>; 344 clocks = <&clkc 45>;
319 compatible = "xlnx,zynq-wdt-r1p2"; 345 compatible = "cdns,wdt-r1p2";
320 device_type = "watchdog";
321 interrupt-parent = <&intc>; 346 interrupt-parent = <&intc>;
322 interrupts = <0 9 1>; 347 interrupts = <0 9 1>;
323 reg = <0xf8005000 0x1000>; 348 reg = <0xf8005000 0x1000>;
324 reset = <0>;
325 timeout-sec = <10>; 349 timeout-sec = <10>;
326 }; 350 };
327 }; 351 };
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
index 280f02dd4ddc..1fc1d3911e9b 100644
--- a/arch/arm/boot/dts/zynq-zc702.dts
+++ b/arch/arm/boot/dts/zynq-zc702.dts
@@ -18,6 +18,12 @@
18 model = "Zynq ZC702 Development Board"; 18 model = "Zynq ZC702 Development Board";
19 compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; 19 compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
20 20
21 aliases {
22 ethernet0 = &gem0;
23 i2c0 = &i2c0;
24 serial0 = &uart1;
25 };
26
21 memory { 27 memory {
22 device_type = "memory"; 28 device_type = "memory";
23 reg = <0x0 0x40000000>; 29 reg = <0x0 0x40000000>;
@@ -36,10 +42,17 @@
36 linux,default-trigger = "heartbeat"; 42 linux,default-trigger = "heartbeat";
37 }; 43 };
38 }; 44 };
45
46 usb_phy0: phy0 {
47 compatible = "usb-nop-xceiv";
48 #phy-cells = <0>;
49 };
39}; 50};
40 51
41&can0 { 52&can0 {
42 status = "okay"; 53 status = "okay";
54 pinctrl-names = "default";
55 pinctrl-0 = <&pinctrl_can0_default>;
43}; 56};
44 57
45&clkc { 58&clkc {
@@ -50,15 +63,24 @@
50 status = "okay"; 63 status = "okay";
51 phy-mode = "rgmii-id"; 64 phy-mode = "rgmii-id";
52 phy-handle = <&ethernet_phy>; 65 phy-handle = <&ethernet_phy>;
66 pinctrl-names = "default";
67 pinctrl-0 = <&pinctrl_gem0_default>;
53 68
54 ethernet_phy: ethernet-phy@7 { 69 ethernet_phy: ethernet-phy@7 {
55 reg = <7>; 70 reg = <7>;
56 }; 71 };
57}; 72};
58 73
74&gpio0 {
75 pinctrl-names = "default";
76 pinctrl-0 = <&pinctrl_gpio0_default>;
77};
78
59&i2c0 { 79&i2c0 {
60 status = "okay"; 80 status = "okay";
61 clock-frequency = <400000>; 81 clock-frequency = <400000>;
82 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_i2c0_default>;
62 84
63 i2cswitch@74 { 85 i2cswitch@74 {
64 compatible = "nxp,pca9548"; 86 compatible = "nxp,pca9548";
@@ -132,10 +154,212 @@
132 }; 154 };
133}; 155};
134 156
157&pinctrl0 {
158 pinctrl_can0_default: can0-default {
159 mux {
160 function = "can0";
161 groups = "can0_9_grp";
162 };
163
164 conf {
165 groups = "can0_9_grp";
166 slew-rate = <0>;
167 io-standard = <1>;
168 };
169
170 conf-rx {
171 pins = "MIO46";
172 bias-high-impedance;
173 };
174
175 conf-tx {
176 pins = "MIO47";
177 bias-disable;
178 };
179 };
180
181 pinctrl_gem0_default: gem0-default {
182 mux {
183 function = "ethernet0";
184 groups = "ethernet0_0_grp";
185 };
186
187 conf {
188 groups = "ethernet0_0_grp";
189 slew-rate = <0>;
190 io-standard = <4>;
191 };
192
193 conf-rx {
194 pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
195 bias-high-impedance;
196 low-power-disable;
197 };
198
199 conf-tx {
200 pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
201 bias-disable;
202 low-power-enable;
203 };
204
205 mux-mdio {
206 function = "mdio0";
207 groups = "mdio0_0_grp";
208 };
209
210 conf-mdio {
211 groups = "mdio0_0_grp";
212 slew-rate = <0>;
213 io-standard = <1>;
214 bias-disable;
215 };
216 };
217
218 pinctrl_gpio0_default: gpio0-default {
219 mux {
220 function = "gpio0";
221 groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
222 "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
223 "gpio0_13_grp", "gpio0_14_grp";
224 };
225
226 conf {
227 groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
228 "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
229 "gpio0_13_grp", "gpio0_14_grp";
230 slew-rate = <0>;
231 io-standard = <1>;
232 };
233
234 conf-pull-up {
235 pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14";
236 bias-pull-up;
237 };
238
239 conf-pull-none {
240 pins = "MIO7", "MIO8";
241 bias-disable;
242 };
243 };
244
245 pinctrl_i2c0_default: i2c0-default {
246 mux {
247 groups = "i2c0_10_grp";
248 function = "i2c0";
249 };
250
251 conf {
252 groups = "i2c0_10_grp";
253 bias-pull-up;
254 slew-rate = <0>;
255 io-standard = <1>;
256 };
257 };
258
259 pinctrl_sdhci0_default: sdhci0-default {
260 mux {
261 groups = "sdio0_2_grp";
262 function = "sdio0";
263 };
264
265 conf {
266 groups = "sdio0_2_grp";
267 slew-rate = <0>;
268 io-standard = <1>;
269 bias-disable;
270 };
271
272 mux-cd {
273 groups = "gpio0_0_grp";
274 function = "sdio0_cd";
275 };
276
277 conf-cd {
278 groups = "gpio0_0_grp";
279 bias-high-impedance;
280 bias-pull-up;
281 slew-rate = <0>;
282 io-standard = <1>;
283 };
284
285 mux-wp {
286 groups = "gpio0_15_grp";
287 function = "sdio0_wp";
288 };
289
290 conf-wp {
291 groups = "gpio0_15_grp";
292 bias-high-impedance;
293 bias-pull-up;
294 slew-rate = <0>;
295 io-standard = <1>;
296 };
297 };
298
299 pinctrl_uart1_default: uart1-default {
300 mux {
301 groups = "uart1_10_grp";
302 function = "uart1";
303 };
304
305 conf {
306 groups = "uart1_10_grp";
307 slew-rate = <0>;
308 io-standard = <1>;
309 };
310
311 conf-rx {
312 pins = "MIO49";
313 bias-high-impedance;
314 };
315
316 conf-tx {
317 pins = "MIO48";
318 bias-disable;
319 };
320 };
321
322 pinctrl_usb0_default: usb0-default {
323 mux {
324 groups = "usb0_0_grp";
325 function = "usb0";
326 };
327
328 conf {
329 groups = "usb0_0_grp";
330 slew-rate = <0>;
331 io-standard = <1>;
332 };
333
334 conf-rx {
335 pins = "MIO29", "MIO31", "MIO36";
336 bias-high-impedance;
337 };
338
339 conf-tx {
340 pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
341 "MIO35", "MIO37", "MIO38", "MIO39";
342 bias-disable;
343 };
344 };
345};
346
135&sdhci0 { 347&sdhci0 {
136 status = "okay"; 348 status = "okay";
349 pinctrl-names = "default";
350 pinctrl-0 = <&pinctrl_sdhci0_default>;
137}; 351};
138 352
139&uart1 { 353&uart1 {
140 status = "okay"; 354 status = "okay";
355 pinctrl-names = "default";
356 pinctrl-0 = <&pinctrl_uart1_default>;
357};
358
359&usb0 {
360 status = "okay";
361 dr_mode = "host";
362 usb-phy = <&usb_phy0>;
363 pinctrl-names = "default";
364 pinctrl-0 = <&pinctrl_usb0_default>;
141}; 365};
diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts
index 34f7812d2ee8..850518d9b8ac 100644
--- a/arch/arm/boot/dts/zynq-zc706.dts
+++ b/arch/arm/boot/dts/zynq-zc706.dts
@@ -18,6 +18,12 @@
18 model = "Zynq ZC706 Development Board"; 18 model = "Zynq ZC706 Development Board";
19 compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; 19 compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
20 20
21 aliases {
22 ethernet0 = &gem0;
23 i2c0 = &i2c0;
24 serial0 = &uart1;
25 };
26
21 memory { 27 memory {
22 device_type = "memory"; 28 device_type = "memory";
23 reg = <0x0 0x40000000>; 29 reg = <0x0 0x40000000>;
@@ -27,6 +33,10 @@
27 bootargs = "console=ttyPS0,115200 earlyprintk"; 33 bootargs = "console=ttyPS0,115200 earlyprintk";
28 }; 34 };
29 35
36 usb_phy0: phy0 {
37 compatible = "usb-nop-xceiv";
38 #phy-cells = <0>;
39 };
30}; 40};
31 41
32&clkc { 42&clkc {
@@ -37,15 +47,24 @@
37 status = "okay"; 47 status = "okay";
38 phy-mode = "rgmii-id"; 48 phy-mode = "rgmii-id";
39 phy-handle = <&ethernet_phy>; 49 phy-handle = <&ethernet_phy>;
50 pinctrl-names = "default";
51 pinctrl-0 = <&pinctrl_gem0_default>;
40 52
41 ethernet_phy: ethernet-phy@7 { 53 ethernet_phy: ethernet-phy@7 {
42 reg = <7>; 54 reg = <7>;
43 }; 55 };
44}; 56};
45 57
58&gpio0 {
59 pinctrl-names = "default";
60 pinctrl-0 = <&pinctrl_gpio0_default>;
61};
62
46&i2c0 { 63&i2c0 {
47 status = "okay"; 64 status = "okay";
48 clock-frequency = <400000>; 65 clock-frequency = <400000>;
66 pinctrl-names = "default";
67 pinctrl-0 = <&pinctrl_i2c0_default>;
49 68
50 i2cswitch@74 { 69 i2cswitch@74 {
51 compatible = "nxp,pca9548"; 70 compatible = "nxp,pca9548";
@@ -111,10 +130,185 @@
111 }; 130 };
112}; 131};
113 132
133&pinctrl0 {
134 pinctrl_gem0_default: gem0-default {
135 mux {
136 function = "ethernet0";
137 groups = "ethernet0_0_grp";
138 };
139
140 conf {
141 groups = "ethernet0_0_grp";
142 slew-rate = <0>;
143 io-standard = <4>;
144 };
145
146 conf-rx {
147 pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
148 bias-high-impedance;
149 low-power-disable;
150 };
151
152 conf-tx {
153 pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
154 low-power-enable;
155 bias-disable;
156 };
157
158 mux-mdio {
159 function = "mdio0";
160 groups = "mdio0_0_grp";
161 };
162
163 conf-mdio {
164 groups = "mdio0_0_grp";
165 slew-rate = <0>;
166 io-standard = <1>;
167 bias-disable;
168 };
169 };
170
171 pinctrl_gpio0_default: gpio0-default {
172 mux {
173 function = "gpio0";
174 groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp";
175 };
176
177 conf {
178 groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp";
179 slew-rate = <0>;
180 io-standard = <1>;
181 };
182
183 conf-pull-up {
184 pins = "MIO46", "MIO47";
185 bias-pull-up;
186 };
187
188 conf-pull-none {
189 pins = "MIO7";
190 bias-disable;
191 };
192 };
193
194 pinctrl_i2c0_default: i2c0-default {
195 mux {
196 groups = "i2c0_10_grp";
197 function = "i2c0";
198 };
199
200 conf {
201 groups = "i2c0_10_grp";
202 bias-pull-up;
203 slew-rate = <0>;
204 io-standard = <1>;
205 };
206 };
207
208 pinctrl_sdhci0_default: sdhci0-default {
209 mux {
210 groups = "sdio0_2_grp";
211 function = "sdio0";
212 };
213
214 conf {
215 groups = "sdio0_2_grp";
216 slew-rate = <0>;
217 io-standard = <1>;
218 bias-disable;
219 };
220
221 mux-cd {
222 groups = "gpio0_14_grp";
223 function = "sdio0_cd";
224 };
225
226 conf-cd {
227 groups = "gpio0_14_grp";
228 bias-high-impedance;
229 bias-pull-up;
230 slew-rate = <0>;
231 io-standard = <1>;
232 };
233
234 mux-wp {
235 groups = "gpio0_15_grp";
236 function = "sdio0_wp";
237 };
238
239 conf-wp {
240 groups = "gpio0_15_grp";
241 bias-high-impedance;
242 bias-pull-up;
243 slew-rate = <0>;
244 io-standard = <1>;
245 };
246 };
247
248 pinctrl_uart1_default: uart1-default {
249 mux {
250 groups = "uart1_10_grp";
251 function = "uart1";
252 };
253
254 conf {
255 groups = "uart1_10_grp";
256 slew-rate = <0>;
257 io-standard = <1>;
258 };
259
260 conf-rx {
261 pins = "MIO49";
262 bias-high-impedance;
263 };
264
265 conf-tx {
266 pins = "MIO48";
267 bias-disable;
268 };
269 };
270
271 pinctrl_usb0_default: usb0-default {
272 mux {
273 groups = "usb0_0_grp";
274 function = "usb0";
275 };
276
277 conf {
278 groups = "usb0_0_grp";
279 slew-rate = <0>;
280 io-standard = <1>;
281 };
282
283 conf-rx {
284 pins = "MIO29", "MIO31", "MIO36";
285 bias-high-impedance;
286 };
287
288 conf-tx {
289 pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
290 "MIO35", "MIO37", "MIO38", "MIO39";
291 bias-disable;
292 };
293 };
294};
295
114&sdhci0 { 296&sdhci0 {
115 status = "okay"; 297 status = "okay";
298 pinctrl-names = "default";
299 pinctrl-0 = <&pinctrl_sdhci0_default>;
116}; 300};
117 301
118&uart1 { 302&uart1 {
119 status = "okay"; 303 status = "okay";
304 pinctrl-names = "default";
305 pinctrl-0 = <&pinctrl_uart1_default>;
306};
307
308&usb0 {
309 status = "okay";
310 dr_mode = "host";
311 usb-phy = <&usb_phy0>;
312 pinctrl-names = "default";
313 pinctrl-0 = <&pinctrl_usb0_default>;
120}; 314};
diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/zynq-zed.dts
index 1c7cc990b47a..5658bc8434de 100644
--- a/arch/arm/boot/dts/zynq-zed.dts
+++ b/arch/arm/boot/dts/zynq-zed.dts
@@ -18,6 +18,11 @@
18 model = "Zynq Zed Development Board"; 18 model = "Zynq Zed Development Board";
19 compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; 19 compatible = "xlnx,zynq-zed", "xlnx,zynq-7000";
20 20
21 aliases {
22 ethernet0 = &gem0;
23 serial0 = &uart1;
24 };
25
21 memory { 26 memory {
22 device_type = "memory"; 27 device_type = "memory";
23 reg = <0x0 0x20000000>; 28 reg = <0x0 0x20000000>;
@@ -27,6 +32,10 @@
27 bootargs = "console=ttyPS0,115200 earlyprintk"; 32 bootargs = "console=ttyPS0,115200 earlyprintk";
28 }; 33 };
29 34
35 usb_phy0: phy0 {
36 compatible = "usb-nop-xceiv";
37 #phy-cells = <0>;
38 };
30}; 39};
31 40
32&clkc { 41&clkc {
@@ -50,3 +59,9 @@
50&uart1 { 59&uart1 {
51 status = "okay"; 60 status = "okay";
52}; 61};
62
63&usb0 {
64 status = "okay";
65 dr_mode = "host";
66 usb-phy = <&usb_phy0>;
67};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-13 17:17:27 -0500