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Diffstat (limited to 'arch/arm/boot/dts/zynq-zc702.dts')
-rw-r--r--arch/arm/boot/dts/zynq-zc702.dts224
1 files changed, 224 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
index 280f02dd4ddc..1fc1d3911e9b 100644
--- a/arch/arm/boot/dts/zynq-zc702.dts
+++ b/arch/arm/boot/dts/zynq-zc702.dts
@@ -18,6 +18,12 @@
18 model = "Zynq ZC702 Development Board"; 18 model = "Zynq ZC702 Development Board";
19 compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; 19 compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
20 20
21 aliases {
22 ethernet0 = &gem0;
23 i2c0 = &i2c0;
24 serial0 = &uart1;
25 };
26
21 memory { 27 memory {
22 device_type = "memory"; 28 device_type = "memory";
23 reg = <0x0 0x40000000>; 29 reg = <0x0 0x40000000>;
@@ -36,10 +42,17 @@
36 linux,default-trigger = "heartbeat"; 42 linux,default-trigger = "heartbeat";
37 }; 43 };
38 }; 44 };
45
46 usb_phy0: phy0 {
47 compatible = "usb-nop-xceiv";
48 #phy-cells = <0>;
49 };
39}; 50};
40 51
41&can0 { 52&can0 {
42 status = "okay"; 53 status = "okay";
54 pinctrl-names = "default";
55 pinctrl-0 = <&pinctrl_can0_default>;
43}; 56};
44 57
45&clkc { 58&clkc {
@@ -50,15 +63,24 @@
50 status = "okay"; 63 status = "okay";
51 phy-mode = "rgmii-id"; 64 phy-mode = "rgmii-id";
52 phy-handle = <&ethernet_phy>; 65 phy-handle = <&ethernet_phy>;
66 pinctrl-names = "default";
67 pinctrl-0 = <&pinctrl_gem0_default>;
53 68
54 ethernet_phy: ethernet-phy@7 { 69 ethernet_phy: ethernet-phy@7 {
55 reg = <7>; 70 reg = <7>;
56 }; 71 };
57}; 72};
58 73
74&gpio0 {
75 pinctrl-names = "default";
76 pinctrl-0 = <&pinctrl_gpio0_default>;
77};
78
59&i2c0 { 79&i2c0 {
60 status = "okay"; 80 status = "okay";
61 clock-frequency = <400000>; 81 clock-frequency = <400000>;
82 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_i2c0_default>;
62 84
63 i2cswitch@74 { 85 i2cswitch@74 {
64 compatible = "nxp,pca9548"; 86 compatible = "nxp,pca9548";
@@ -132,10 +154,212 @@
132 }; 154 };
133}; 155};
134 156
157&pinctrl0 {
158 pinctrl_can0_default: can0-default {
159 mux {
160 function = "can0";
161 groups = "can0_9_grp";
162 };
163
164 conf {
165 groups = "can0_9_grp";
166 slew-rate = <0>;
167 io-standard = <1>;
168 };
169
170 conf-rx {
171 pins = "MIO46";
172 bias-high-impedance;
173 };
174
175 conf-tx {
176 pins = "MIO47";
177 bias-disable;
178 };
179 };
180
181 pinctrl_gem0_default: gem0-default {
182 mux {
183 function = "ethernet0";
184 groups = "ethernet0_0_grp";
185 };
186
187 conf {
188 groups = "ethernet0_0_grp";
189 slew-rate = <0>;
190 io-standard = <4>;
191 };
192
193 conf-rx {
194 pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
195 bias-high-impedance;
196 low-power-disable;
197 };
198
199 conf-tx {
200 pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
201 bias-disable;
202 low-power-enable;
203 };
204
205 mux-mdio {
206 function = "mdio0";
207 groups = "mdio0_0_grp";
208 };
209
210 conf-mdio {
211 groups = "mdio0_0_grp";
212 slew-rate = <0>;
213 io-standard = <1>;
214 bias-disable;
215 };
216 };
217
218 pinctrl_gpio0_default: gpio0-default {
219 mux {
220 function = "gpio0";
221 groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
222 "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
223 "gpio0_13_grp", "gpio0_14_grp";
224 };
225
226 conf {
227 groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
228 "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
229 "gpio0_13_grp", "gpio0_14_grp";
230 slew-rate = <0>;
231 io-standard = <1>;
232 };
233
234 conf-pull-up {
235 pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14";
236 bias-pull-up;
237 };
238
239 conf-pull-none {
240 pins = "MIO7", "MIO8";
241 bias-disable;
242 };
243 };
244
245 pinctrl_i2c0_default: i2c0-default {
246 mux {
247 groups = "i2c0_10_grp";
248 function = "i2c0";
249 };
250
251 conf {
252 groups = "i2c0_10_grp";
253 bias-pull-up;
254 slew-rate = <0>;
255 io-standard = <1>;
256 };
257 };
258
259 pinctrl_sdhci0_default: sdhci0-default {
260 mux {
261 groups = "sdio0_2_grp";
262 function = "sdio0";
263 };
264
265 conf {
266 groups = "sdio0_2_grp";
267 slew-rate = <0>;
268 io-standard = <1>;
269 bias-disable;
270 };
271
272 mux-cd {
273 groups = "gpio0_0_grp";
274 function = "sdio0_cd";
275 };
276
277 conf-cd {
278 groups = "gpio0_0_grp";
279 bias-high-impedance;
280 bias-pull-up;
281 slew-rate = <0>;
282 io-standard = <1>;
283 };
284
285 mux-wp {
286 groups = "gpio0_15_grp";
287 function = "sdio0_wp";
288 };
289
290 conf-wp {
291 groups = "gpio0_15_grp";
292 bias-high-impedance;
293 bias-pull-up;
294 slew-rate = <0>;
295 io-standard = <1>;
296 };
297 };
298
299 pinctrl_uart1_default: uart1-default {
300 mux {
301 groups = "uart1_10_grp";
302 function = "uart1";
303 };
304
305 conf {
306 groups = "uart1_10_grp";
307 slew-rate = <0>;
308 io-standard = <1>;
309 };
310
311 conf-rx {
312 pins = "MIO49";
313 bias-high-impedance;
314 };
315
316 conf-tx {
317 pins = "MIO48";
318 bias-disable;
319 };
320 };
321
322 pinctrl_usb0_default: usb0-default {
323 mux {
324 groups = "usb0_0_grp";
325 function = "usb0";
326 };
327
328 conf {
329 groups = "usb0_0_grp";
330 slew-rate = <0>;
331 io-standard = <1>;
332 };
333
334 conf-rx {
335 pins = "MIO29", "MIO31", "MIO36";
336 bias-high-impedance;
337 };
338
339 conf-tx {
340 pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
341 "MIO35", "MIO37", "MIO38", "MIO39";
342 bias-disable;
343 };
344 };
345};
346
135&sdhci0 { 347&sdhci0 {
136 status = "okay"; 348 status = "okay";
349 pinctrl-names = "default";
350 pinctrl-0 = <&pinctrl_sdhci0_default>;
137}; 351};
138 352
139&uart1 { 353&uart1 {
140 status = "okay"; 354 status = "okay";
355 pinctrl-names = "default";
356 pinctrl-0 = <&pinctrl_uart1_default>;
357};
358
359&usb0 {
360 status = "okay";
361 dr_mode = "host";
362 usb-phy = <&usb_phy0>;
363 pinctrl-names = "default";
364 pinctrl-0 = <&pinctrl_usb0_default>;
141}; 365};