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authorArnd Bergmann <arnd@arndb.de>2015-04-13 19:18:44 -0400
committerArnd Bergmann <arnd@arndb.de>2015-04-13 19:18:44 -0400
commit9705feacb778d2aa8bb868e8a9ab40557f7f7043 (patch)
tree1b375461706efeebd40ca653cf771e2fb975c08e /arch/arm/boot/dts
parent643ee0d50a7392671c0488912cdbb37549ac4cc7 (diff)
parent8e047c120fb2ccb7b7aba8f5e9224e463f86bebc (diff)
Merge tag 'imx-dt-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/late
Pull "The i.MX device tree updates for 4.1" from Shawn Guo: - Convert GPC controller to use stacked interrupt domains - Add power domain descriptions for i.MX6 platforms - Improve i.MX25 pin function defines - Disable PWM devices in <soc>.dtsi by default and enable it at board level dts where the device is actually available. - Define labels for SNVS RTC device to ease the board description, where an external RTC is available. - Add dr_mode host setting to all i.MX host-only USB instances - Support Miscellaneous System Control Module (MSCM) for VF610 - Add initial i.MX6SL WaRP Board support - Add i.MX6SX SDB revision B board support - A bunch of imx28-apf28dev board updates, including gpio polarity correction and CAN, AUART device support. - SolidRun iMX6 platform updates: dual-license of GPLv2/X11, PWM setup, PCF8523 RTC, GPIO key and SGTL5000 audio support. - A number of random device additions for boards: SPI and CAN for vf-colibri, MAX7310 GPIO expander for imx6qdl-sabreauto and LCD support for imx25-pdk. Note: Branch imx/cleanup was merged as the base to solve conflict on imx25 iomux header. Branch imx/soc was merged as the base to solve conflict on arch/arm/mach-imx/gpc.c. And Jason Cooper's irqchip/vybrid branch was pulled into the base as a run-time dependency. * tag 'imx-dt-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (69 commits) ARM: dts: hummingboard: add sgtl5000 support for Hummingboard Pro ARM: dts: imx25-pinfunc: Add several pinfunctions ARM: dts: vf610: fix missing irqs ARM: dts: cubox: Map gpio-keys to gpio3 8 ARM: dts: hummingboard: Setup pwm lines ARM: dts: hummingboard: enable PCF8523 RTC support ARM: dts: Re-license SolidRun iMX6 platform DT GPL v2/X11 ARM: dts: imx28: add alternative pinmuxing for spi3 ARM: dts: imx6sx: Add label snvs_rtc ARM: dts: imx6sl: Add label snvs_rtc ARM: imx6: Warn when an old DT is detected ARM: imx6: Allow GPC interrupts affinity to be changed ARM: imx6qdl-sabreauto.dtsi: add max7310 support ARM: dts: imx6sl-warp: Add BCM4330 support ARM: dts: imx28-apf28dev: add wakeup function to user button ARM: dts: imx28-apf28dev: fix user button polarity ARM: dts: imx25-pinfunc: remove input values for pinfuncs without input register ARM: dts: vf610: add Miscellaneous System Control Module (MSCM) ARM: dts: imx6sl-warp: Pass 'bus-width' property ARM: dts: imx6qdl: disable PWMs by default ...
Diffstat (limited to 'arch/arm/boot/dts')
-rw-r--r--arch/arm/boot/dts/Makefile4
-rw-r--r--arch/arm/boot/dts/imx25-pdk.dts58
-rw-r--r--arch/arm/boot/dts/imx25-pinfunc.h86
-rw-r--r--arch/arm/boot/dts/imx27.dtsi2
-rw-r--r--arch/arm/boot/dts/imx28-apf28.dts2
-rw-r--r--arch/arm/boot/dts/imx28-apf28dev.dts30
-rw-r--r--arch/arm/boot/dts/imx28.dtsi14
-rw-r--r--arch/arm/boot/dts/imx35.dtsi1
-rw-r--r--arch/arm/boot/dts/imx50.dtsi3
-rw-r--r--arch/arm/boot/dts/imx51.dtsi3
-rw-r--r--arch/arm/boot/dts/imx53.dtsi3
-rw-r--r--arch/arm/boot/dts/imx6dl-aristainetos_4.dts4
-rw-r--r--arch/arm/boot/dts/imx6dl-aristainetos_7.dts4
-rw-r--r--arch/arm/boot/dts/imx6dl-cubox-i.dts38
-rw-r--r--arch/arm/boot/dts/imx6dl-hummingboard.dts38
-rw-r--r--arch/arm/boot/dts/imx6q-cubox-i.dts38
-rw-r--r--arch/arm/boot/dts/imx6q-hummingboard.dts38
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi20
-rw-r--r--arch/arm/boot/dts/imx6qdl-cubox-i.dtsi62
-rw-r--r--arch/arm/boot/dts/imx6qdl-hummingboard.dtsi101
-rw-r--r--arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi38
-rw-r--r--arch/arm/boot/dts/imx6qdl-microsom.dtsi38
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabreauto.dtsi35
-rw-r--r--arch/arm/boot/dts/imx6qdl.dtsi49
-rw-r--r--arch/arm/boot/dts/imx6sl-warp.dts262
-rw-r--r--arch/arm/boot/dts/imx6sl.dtsi13
-rw-r--r--arch/arm/boot/dts/imx6sx-sdb-reva.dts143
-rw-r--r--arch/arm/boot/dts/imx6sx-sdb.dts603
-rw-r--r--arch/arm/boot/dts/imx6sx-sdb.dtsi562
-rw-r--r--arch/arm/boot/dts/imx6sx.dtsi9
-rw-r--r--arch/arm/boot/dts/vf-colibri-eval-v3.dtsi31
-rw-r--r--arch/arm/boot/dts/vf-colibri.dtsi15
-rw-r--r--arch/arm/boot/dts/vf500.dtsi137
-rw-r--r--arch/arm/boot/dts/vfxxx.dtsi64
34 files changed, 1789 insertions, 759 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index a1c776b8dcec..8e7b9d55905d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -299,9 +299,11 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
299 imx6q-wandboard.dtb \ 299 imx6q-wandboard.dtb \
300 imx6q-wandboard-revb1.dtb 300 imx6q-wandboard-revb1.dtb
301dtb-$(CONFIG_SOC_IMX6SL) += \ 301dtb-$(CONFIG_SOC_IMX6SL) += \
302 imx6sl-evk.dtb 302 imx6sl-evk.dtb \
303 imx6sl-warp.dtb
303dtb-$(CONFIG_SOC_IMX6SX) += \ 304dtb-$(CONFIG_SOC_IMX6SX) += \
304 imx6sx-sabreauto.dtb \ 305 imx6sx-sabreauto.dtb \
306 imx6sx-sdb-reva.dtb \
305 imx6sx-sdb.dtb 307 imx6sx-sdb.dtb
306dtb-$(CONFIG_SOC_LS1021A) += \ 308dtb-$(CONFIG_SOC_LS1021A) += \
307 ls1021a-qds.dtb \ 309 ls1021a-qds.dtb \
diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts
index 9c21b1583762..dd45e6971bc3 100644
--- a/arch/arm/boot/dts/imx25-pdk.dts
+++ b/arch/arm/boot/dts/imx25-pdk.dts
@@ -75,6 +75,27 @@
75 mux-int-port = <1>; 75 mux-int-port = <1>;
76 mux-ext-port = <4>; 76 mux-ext-port = <4>;
77 }; 77 };
78
79 wvga: display {
80 model = "CLAA057VC01CW";
81 bits-per-pixel = <16>;
82 fsl,pcr = <0xfa208b80>;
83 bus-width = <18>;
84 native-mode = <&wvga_timings>;
85 display-timings {
86 wvga_timings: 640x480 {
87 hactive = <640>;
88 vactive = <480>;
89 hback-porch = <45>;
90 hfront-porch = <114>;
91 hsync-len = <1>;
92 vback-porch = <33>;
93 vfront-porch = <11>;
94 vsync-len = <1>;
95 clock-frequency = <25200000>;
96 };
97 };
98 };
78}; 99};
79 100
80&audmux { 101&audmux {
@@ -190,6 +211,33 @@
190 >; 211 >;
191 }; 212 };
192 213
214 pinctrl_lcd: lcdgrp {
215 fsl,pins = <
216 MX25_PAD_LD0__LD0 0xe0
217 MX25_PAD_LD1__LD1 0xe0
218 MX25_PAD_LD2__LD2 0xe0
219 MX25_PAD_LD3__LD3 0xe0
220 MX25_PAD_LD4__LD4 0xe0
221 MX25_PAD_LD5__LD5 0xe0
222 MX25_PAD_LD6__LD6 0xe0
223 MX25_PAD_LD7__LD7 0xe0
224 MX25_PAD_LD8__LD8 0xe0
225 MX25_PAD_LD9__LD9 0xe0
226 MX25_PAD_LD10__LD10 0xe0
227 MX25_PAD_LD11__LD11 0xe0
228 MX25_PAD_LD12__LD12 0xe0
229 MX25_PAD_LD13__LD13 0xe0
230 MX25_PAD_LD14__LD14 0xe0
231 MX25_PAD_LD15__LD15 0xe0
232 MX25_PAD_GPIO_E__LD16 0xe0
233 MX25_PAD_GPIO_F__LD17 0xe0
234 MX25_PAD_HSYNC__HSYNC 0xe0
235 MX25_PAD_VSYNC__VSYNC 0xe0
236 MX25_PAD_LSCLK__LSCLK 0xe0
237 MX25_PAD_OE_ACD__OE_ACD 0xe0
238 MX25_PAD_CONTRAST__CONTRAST 0xe0
239 >;
240 };
193 241
194 pinctrl_uart1: uart1grp { 242 pinctrl_uart1: uart1grp {
195 fsl,pins = < 243 fsl,pins = <
@@ -202,6 +250,16 @@
202 }; 250 };
203}; 251};
204 252
253&lcdc {
254 display = <&wvga>;
255 fsl,lpccr = <0x00a903ff>;
256 fsl,lscr1 = <0x00120300>;
257 fsl,dmacr = <0x00020010>;
258 pinctrl-names = "default";
259 pinctrl-0 = <&pinctrl_lcd>;
260 status = "okay";
261};
262
205&nfc { 263&nfc {
206 nand-on-flash-bbt; 264 nand-on-flash-bbt;
207 status = "okay"; 265 status = "okay";
diff --git a/arch/arm/boot/dts/imx25-pinfunc.h b/arch/arm/boot/dts/imx25-pinfunc.h
index 88eebb15da6a..7c4b9f2f9aad 100644
--- a/arch/arm/boot/dts/imx25-pinfunc.h
+++ b/arch/arm/boot/dts/imx25-pinfunc.h
@@ -17,48 +17,69 @@
17 * <mux_reg conf_reg input_reg mux_mode input_val> 17 * <mux_reg conf_reg input_reg mux_mode input_val>
18 */ 18 */
19 19
20#define MX25_PAD_TDO__TDO 0x000 0x3e8 0x000 0x00 0x000
21
20#define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000 22#define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
21#define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000 23#define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
22 24
23#define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000 25#define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
24#define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000 26#define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
27#define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
25 28
26#define MX25_PAD_A14__A14 0x010 0x230 0x000 0x10 0x000 29#define MX25_PAD_A14__A14 0x010 0x230 0x000 0x10 0x000
27#define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x15 0x000 30#define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x15 0x000
31#define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x16 0x000
32#define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x17 0x000
28 33
29#define MX25_PAD_A15__A15 0x014 0x234 0x000 0x10 0x000 34#define MX25_PAD_A15__A15 0x014 0x234 0x000 0x10 0x000
30#define MX25_PAD_A15__GPIO_2_1 0x014 0x234 0x000 0x15 0x000 35#define MX25_PAD_A15__GPIO_2_1 0x014 0x234 0x000 0x15 0x000
36#define MX25_PAD_A15__SIM1_RST1 0x014 0x234 0x000 0x16 0x000
37#define MX25_PAD_A15__LCDC_PS 0x014 0x234 0x000 0x17 0x000
31 38
32#define MX25_PAD_A16__A16 0x018 0x000 0x000 0x10 0x000 39#define MX25_PAD_A16__A16 0x018 0x000 0x000 0x10 0x000
33#define MX25_PAD_A16__GPIO_2_2 0x018 0x000 0x000 0x15 0x000 40#define MX25_PAD_A16__GPIO_2_2 0x018 0x000 0x000 0x15 0x000
41#define MX25_PAD_A16__SIM1_VEN1 0x018 0x000 0x000 0x16 0x000
42#define MX25_PAD_A16__LCDC_REV 0x018 0x000 0x000 0x17 0x000
34 43
35#define MX25_PAD_A17__A17 0x01c 0x238 0x000 0x10 0x000 44#define MX25_PAD_A17__A17 0x01c 0x238 0x000 0x10 0x000
36#define MX25_PAD_A17__GPIO_2_3 0x01c 0x238 0x000 0x15 0x000 45#define MX25_PAD_A17__GPIO_2_3 0x01c 0x238 0x000 0x15 0x000
46#define MX25_PAD_A17__SIM1_TX 0x01c 0x238 0x554 0x16 0x000
47#define MX25_PAD_A17__FEC_TX_ERR 0x01c 0x238 0x000 0x17 0x000
37 48
38#define MX25_PAD_A18__A18 0x020 0x23c 0x000 0x10 0x000 49#define MX25_PAD_A18__A18 0x020 0x23c 0x000 0x10 0x000
39#define MX25_PAD_A18__GPIO_2_4 0x020 0x23c 0x000 0x15 0x000 50#define MX25_PAD_A18__GPIO_2_4 0x020 0x23c 0x000 0x15 0x000
51#define MX25_PAD_A18__SIM1_PD1 0x020 0x23c 0x550 0x16 0x000
40#define MX25_PAD_A18__FEC_COL 0x020 0x23c 0x504 0x17 0x000 52#define MX25_PAD_A18__FEC_COL 0x020 0x23c 0x504 0x17 0x000
41 53
42#define MX25_PAD_A19__A19 0x024 0x240 0x000 0x10 0x000 54#define MX25_PAD_A19__A19 0x024 0x240 0x000 0x10 0x000
43#define MX25_PAD_A19__FEC_RX_ER 0x024 0x240 0x518 0x17 0x000
44#define MX25_PAD_A19__GPIO_2_5 0x024 0x240 0x000 0x15 0x000 55#define MX25_PAD_A19__GPIO_2_5 0x024 0x240 0x000 0x15 0x000
56#define MX25_PAD_A19__SIM1_RX1 0x024 0x240 0x54c 0x16 0x000
57#define MX25_PAD_A19__FEC_RX_ERR 0x024 0x240 0x518 0x17 0x000
45 58
46#define MX25_PAD_A20__A20 0x028 0x244 0x000 0x10 0x000 59#define MX25_PAD_A20__A20 0x028 0x244 0x000 0x10 0x000
47#define MX25_PAD_A20__GPIO_2_6 0x028 0x244 0x000 0x15 0x000 60#define MX25_PAD_A20__GPIO_2_6 0x028 0x244 0x000 0x15 0x000
61#define MX25_PAD_A20__SIM2_CLK1 0x028 0x244 0x000 0x16 0x000
48#define MX25_PAD_A20__FEC_RDATA2 0x028 0x244 0x50c 0x17 0x000 62#define MX25_PAD_A20__FEC_RDATA2 0x028 0x244 0x50c 0x17 0x000
49 63
50#define MX25_PAD_A21__A21 0x02c 0x248 0x000 0x10 0x000 64#define MX25_PAD_A21__A21 0x02c 0x248 0x000 0x10 0x000
51#define MX25_PAD_A21__GPIO_2_7 0x02c 0x248 0x000 0x15 0x000 65#define MX25_PAD_A21__GPIO_2_7 0x02c 0x248 0x000 0x15 0x000
66#define MX25_PAD_A21__SIM2_RST1 0x02c 0x248 0x000 0x16 0x000
52#define MX25_PAD_A21__FEC_RDATA3 0x02c 0x248 0x510 0x17 0x000 67#define MX25_PAD_A21__FEC_RDATA3 0x02c 0x248 0x510 0x17 0x000
53 68
54#define MX25_PAD_A22__A22 0x030 0x000 0x000 0x10 0x000 69#define MX25_PAD_A22__A22 0x030 0x000 0x000 0x10 0x000
55#define MX25_PAD_A22__GPIO_2_8 0x030 0x000 0x000 0x15 0x000 70#define MX25_PAD_A22__GPIO_2_8 0x030 0x000 0x000 0x15 0x000
71#define MX25_PAD_A22__FEC_TDATA2 0x030 0x000 0x000 0x17 0x000
72#define MX25_PAD_A22__SIM2_VEN1 0x030 0x000 0x000 0x16 0x000
73#define MX25_PAD_A22__FEC_TDATA2 0x030 0x000 0x000 0x17 0x000
56 74
57#define MX25_PAD_A23__A23 0x034 0x24c 0x000 0x10 0x000 75#define MX25_PAD_A23__A23 0x034 0x24c 0x000 0x10 0x000
58#define MX25_PAD_A23__GPIO_2_9 0x034 0x24c 0x000 0x15 0x000 76#define MX25_PAD_A23__GPIO_2_9 0x034 0x24c 0x000 0x15 0x000
77#define MX25_PAD_A23__SIM2_TX1 0x034 0x24c 0x560 0x16 0x000
78#define MX25_PAD_A23__FEC_TDATA3 0x034 0x24c 0x000 0x17 0x000
59 79
60#define MX25_PAD_A24__A24 0x038 0x250 0x000 0x10 0x000 80#define MX25_PAD_A24__A24 0x038 0x250 0x000 0x10 0x000
61#define MX25_PAD_A24__GPIO_2_10 0x038 0x250 0x000 0x15 0x000 81#define MX25_PAD_A24__GPIO_2_10 0x038 0x250 0x000 0x15 0x000
82#define MX25_PAD_A24__SIM2_PD1 0x038 0x250 0x55c 0x16 0x000
62#define MX25_PAD_A24__FEC_RX_CLK 0x038 0x250 0x514 0x17 0x000 83#define MX25_PAD_A24__FEC_RX_CLK 0x038 0x250 0x514 0x17 0x000
63 84
64#define MX25_PAD_A25__A25 0x03c 0x254 0x000 0x10 0x000 85#define MX25_PAD_A25__A25 0x03c 0x254 0x000 0x10 0x000
@@ -133,20 +154,25 @@
133#define MX25_PAD_D15__D15 0x088 0x280 0x000 0x00 0x000 154#define MX25_PAD_D15__D15 0x088 0x280 0x000 0x00 0x000
134#define MX25_PAD_D15__LD16 0x088 0x280 0x000 0x01 0x000 155#define MX25_PAD_D15__LD16 0x088 0x280 0x000 0x01 0x000
135#define MX25_PAD_D15__GPIO_4_5 0x088 0x280 0x000 0x05 0x000 156#define MX25_PAD_D15__GPIO_4_5 0x088 0x280 0x000 0x05 0x000
157#define MX25_PAD_D15__SDHC1_DAT7 0x088 0x280 0x4d8 0x06 0x000
136 158
137#define MX25_PAD_D14__D14 0x08c 0x284 0x000 0x00 0x000 159#define MX25_PAD_D14__D14 0x08c 0x284 0x000 0x00 0x000
138#define MX25_PAD_D14__LD17 0x08c 0x284 0x000 0x01 0x000 160#define MX25_PAD_D14__LD17 0x08c 0x284 0x000 0x01 0x000
139#define MX25_PAD_D14__GPIO_4_6 0x08c 0x284 0x000 0x05 0x000 161#define MX25_PAD_D14__GPIO_4_6 0x08c 0x284 0x000 0x05 0x000
162#define MX25_PAD_D14__SDHC1_DAT6 0x08c 0x284 0x4d4 0x06 0x000
140 163
141#define MX25_PAD_D13__D13 0x090 0x288 0x000 0x00 0x000 164#define MX25_PAD_D13__D13 0x090 0x288 0x000 0x00 0x000
142#define MX25_PAD_D13__LD18 0x090 0x288 0x000 0x01 0x000 165#define MX25_PAD_D13__LD18 0x090 0x288 0x000 0x01 0x000
143#define MX25_PAD_D13__GPIO_4_7 0x090 0x288 0x000 0x05 0x000 166#define MX25_PAD_D13__GPIO_4_7 0x090 0x288 0x000 0x05 0x000
167#define MX25_PAD_D13__SDHC1_DAT5 0x090 0x288 0x4d0 0x06 0x000
144 168
145#define MX25_PAD_D12__D12 0x094 0x28c 0x000 0x00 0x000 169#define MX25_PAD_D12__D12 0x094 0x28c 0x000 0x00 0x000
146#define MX25_PAD_D12__GPIO_4_8 0x094 0x28c 0x000 0x05 0x000 170#define MX25_PAD_D12__GPIO_4_8 0x094 0x28c 0x000 0x05 0x000
171#define MX25_PAD_D12__SDHC1_DAT4 0x094 0x28c 0x4cc 0x06 0x000
147 172
148#define MX25_PAD_D11__D11 0x098 0x290 0x000 0x00 0x000 173#define MX25_PAD_D11__D11 0x098 0x290 0x000 0x00 0x000
149#define MX25_PAD_D11__GPIO_4_9 0x098 0x290 0x000 0x05 0x000 174#define MX25_PAD_D11__GPIO_4_9 0x098 0x290 0x000 0x05 0x000
175#define MX25_PAD_D11__USBOTG_PWR 0x098 0x290 0x000 0x06 0x000
150 176
151#define MX25_PAD_D10__D10 0x09c 0x294 0x000 0x00 0x000 177#define MX25_PAD_D10__D10 0x09c 0x294 0x000 0x00 0x000
152#define MX25_PAD_D10__GPIO_4_10 0x09c 0x294 0x000 0x05 0x000 178#define MX25_PAD_D10__GPIO_4_10 0x09c 0x294 0x000 0x05 0x000
@@ -212,26 +238,33 @@
212 238
213#define MX25_PAD_LD8__LD8 0x0e8 0x2e0 0x000 0x10 0x000 239#define MX25_PAD_LD8__LD8 0x0e8 0x2e0 0x000 0x10 0x000
214#define MX25_PAD_LD8__FEC_TX_ERR 0x0e8 0x2e0 0x000 0x15 0x000 240#define MX25_PAD_LD8__FEC_TX_ERR 0x0e8 0x2e0 0x000 0x15 0x000
241#define MX25_PAD_LD8__SDHC2_CMD 0x0e8 0x2e0 0x4e0 0x06 0x000
215 242
216#define MX25_PAD_LD9__LD9 0x0ec 0x2e4 0x000 0x10 0x000 243#define MX25_PAD_LD9__LD9 0x0ec 0x2e4 0x000 0x10 0x000
217#define MX25_PAD_LD9__FEC_COL 0x0ec 0x2e4 0x504 0x15 0x001 244#define MX25_PAD_LD9__FEC_COL 0x0ec 0x2e4 0x504 0x15 0x001
245#define MX25_PAD_LD9__SDHC2_CLK 0x0ec 0x2e4 0x4dc 0x06 0x000
218 246
219#define MX25_PAD_LD10__LD10 0x0f0 0x2e8 0x000 0x10 0x000 247#define MX25_PAD_LD10__LD10 0x0f0 0x2e8 0x000 0x10 0x000
220#define MX25_PAD_LD10__FEC_RX_ER 0x0f0 0x2e8 0x518 0x15 0x001 248#define MX25_PAD_LD10__FEC_RX_ERR 0x0f0 0x2e8 0x518 0x15 0x001
221 249
222#define MX25_PAD_LD11__LD11 0x0f4 0x2ec 0x000 0x10 0x000 250#define MX25_PAD_LD11__LD11 0x0f4 0x2ec 0x000 0x10 0x000
223#define MX25_PAD_LD11__FEC_RDATA2 0x0f4 0x2ec 0x50c 0x15 0x001 251#define MX25_PAD_LD11__FEC_RDATA2 0x0f4 0x2ec 0x50c 0x15 0x001
252#define MX25_PAD_LD11__SDHC2_DAT1 0x0f4 0x2ec 0x4e8 0x06 0x000
224 253
225#define MX25_PAD_LD12__LD12 0x0f8 0x2f0 0x000 0x10 0x000 254#define MX25_PAD_LD12__LD12 0x0f8 0x2f0 0x000 0x10 0x000
255#define MX25_PAD_LD12__CSPI2_MOSI 0x0f8 0x2f0 0x4a0 0x02 0x000
226#define MX25_PAD_LD12__FEC_RDATA3 0x0f8 0x2f0 0x510 0x15 0x001 256#define MX25_PAD_LD12__FEC_RDATA3 0x0f8 0x2f0 0x510 0x15 0x001
227 257
228#define MX25_PAD_LD13__LD13 0x0fc 0x2f4 0x000 0x10 0x000 258#define MX25_PAD_LD13__LD13 0x0fc 0x2f4 0x000 0x10 0x000
259#define MX25_PAD_LD13__CSPI2_MISO 0x0fc 0x2f4 0x49c 0x02 0x000
229#define MX25_PAD_LD13__FEC_TDATA2 0x0fc 0x2f4 0x000 0x15 0x000 260#define MX25_PAD_LD13__FEC_TDATA2 0x0fc 0x2f4 0x000 0x15 0x000
230 261
231#define MX25_PAD_LD14__LD14 0x100 0x2f8 0x000 0x10 0x000 262#define MX25_PAD_LD14__LD14 0x100 0x2f8 0x000 0x10 0x000
263#define MX25_PAD_LD14__CSPI2_SCLK 0x100 0x2f8 0x494 0x02 0x000
232#define MX25_PAD_LD14__FEC_TDATA3 0x100 0x2f8 0x000 0x15 0x000 264#define MX25_PAD_LD14__FEC_TDATA3 0x100 0x2f8 0x000 0x15 0x000
233 265
234#define MX25_PAD_LD15__LD15 0x104 0x2fc 0x000 0x10 0x000 266#define MX25_PAD_LD15__LD15 0x104 0x2fc 0x000 0x10 0x000
267#define MX25_PAD_LD15__CSPI2_RDY 0x104 0x2fc 0x498 0x02 0x000
235#define MX25_PAD_LD15__FEC_RX_CLK 0x104 0x2fc 0x514 0x15 0x001 268#define MX25_PAD_LD15__FEC_RX_CLK 0x104 0x2fc 0x514 0x15 0x001
236 269
237#define MX25_PAD_HSYNC__HSYNC 0x108 0x300 0x000 0x10 0x000 270#define MX25_PAD_HSYNC__HSYNC 0x108 0x300 0x000 0x10 0x000
@@ -244,6 +277,7 @@
244#define MX25_PAD_LSCLK__GPIO_1_24 0x110 0x308 0x000 0x15 0x000 277#define MX25_PAD_LSCLK__GPIO_1_24 0x110 0x308 0x000 0x15 0x000
245 278
246#define MX25_PAD_OE_ACD__OE_ACD 0x114 0x30c 0x000 0x10 0x000 279#define MX25_PAD_OE_ACD__OE_ACD 0x114 0x30c 0x000 0x10 0x000
280#define MX25_PAD_OE_ACD__CSPI2_SS0 0x114 0x30c 0x4a4 0x02 0x000
247#define MX25_PAD_OE_ACD__GPIO_1_25 0x114 0x30c 0x000 0x15 0x000 281#define MX25_PAD_OE_ACD__GPIO_1_25 0x114 0x30c 0x000 0x15 0x000
248 282
249#define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x10 0x000 283#define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x10 0x000
@@ -257,26 +291,31 @@
257 291
258#define MX25_PAD_CSI_D2__CSI_D2 0x120 0x318 0x000 0x10 0x000 292#define MX25_PAD_CSI_D2__CSI_D2 0x120 0x318 0x000 0x10 0x000
259#define MX25_PAD_CSI_D2__UART5_RXD_MUX 0x120 0x318 0x578 0x11 0x001 293#define MX25_PAD_CSI_D2__UART5_RXD_MUX 0x120 0x318 0x578 0x11 0x001
294#define MX25_PAD_CSI_D2__SIM1_CLK0 0x120 0x318 0x000 0x04 0x000
260#define MX25_PAD_CSI_D2__GPIO_1_27 0x120 0x318 0x000 0x15 0x000 295#define MX25_PAD_CSI_D2__GPIO_1_27 0x120 0x318 0x000 0x15 0x000
261#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x000 0x17 0x000 296#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x000 0x17 0x000
262 297
263#define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x10 0x000 298#define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x10 0x000
264#define MX25_PAD_CSI_D3__UART5_TXD_MUX 0x124 0x31c 0x000 0x11 0x000 299#define MX25_PAD_CSI_D3__UART5_TXD_MUX 0x124 0x31c 0x000 0x11 0x000
300#define MX25_PAD_CSI_D3__SIM1_RST0 0x124 0x31c 0x000 0x04 0x000
265#define MX25_PAD_CSI_D3__GPIO_1_28 0x124 0x31c 0x000 0x15 0x000 301#define MX25_PAD_CSI_D3__GPIO_1_28 0x124 0x31c 0x000 0x15 0x000
266#define MX25_PAD_CSI_D3__CSPI3_MISO 0x124 0x31c 0x4b4 0x17 0x001 302#define MX25_PAD_CSI_D3__CSPI3_MISO 0x124 0x31c 0x4b4 0x17 0x001
267 303
268#define MX25_PAD_CSI_D4__CSI_D4 0x128 0x320 0x000 0x10 0x000 304#define MX25_PAD_CSI_D4__CSI_D4 0x128 0x320 0x000 0x10 0x000
269#define MX25_PAD_CSI_D4__UART5_RTS 0x128 0x320 0x574 0x11 0x001 305#define MX25_PAD_CSI_D4__UART5_RTS 0x128 0x320 0x574 0x11 0x001
306#define MX25_PAD_CSI_D4__SIM1_VEN0 0x128 0x320 0x000 0x04 0x000
270#define MX25_PAD_CSI_D4__GPIO_1_29 0x128 0x320 0x000 0x15 0x000 307#define MX25_PAD_CSI_D4__GPIO_1_29 0x128 0x320 0x000 0x15 0x000
271#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x000 0x17 0x000 308#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x000 0x17 0x000
272 309
273#define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x10 0x000 310#define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x10 0x000
274#define MX25_PAD_CSI_D5__UART5_CTS 0x12c 0x324 0x000 0x11 0x001 311#define MX25_PAD_CSI_D5__UART5_CTS 0x12c 0x324 0x000 0x11 0x000
312#define MX25_PAD_CSI_D5__SIM1_TX0 0x12c 0x324 0x000 0x04 0x000
275#define MX25_PAD_CSI_D5__GPIO_1_30 0x12c 0x324 0x000 0x15 0x000 313#define MX25_PAD_CSI_D5__GPIO_1_30 0x12c 0x324 0x000 0x15 0x000
276#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x17 0x000 314#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x17 0x000
277 315
278#define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x10 0x000 316#define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x10 0x000
279#define MX25_PAD_CSI_D6__SDHC2_CMD 0x130 0x328 0x4e0 0x12 0x001 317#define MX25_PAD_CSI_D6__SDHC2_CMD 0x130 0x328 0x4e0 0x12 0x001
318#define MX25_PAD_CSI_D6__SIM1_PD0 0x130 0x328 0x000 0x04 0x000
280#define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x15 0x000 319#define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x15 0x000
281 320
282#define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x10 0x000 321#define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x10 0x000
@@ -284,32 +323,32 @@
284#define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x15 0x000 323#define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x15 0x000
285 324
286#define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x10 0x000 325#define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x10 0x000
287#define MX25_PAD_CSI_D8__AUD6_RXC 0x138 0x330 0x000 0x12 0x001 326#define MX25_PAD_CSI_D8__AUD6_RXC 0x138 0x330 0x000 0x12 0x000
288#define MX25_PAD_CSI_D8__GPIO_1_7 0x138 0x330 0x000 0x15 0x000 327#define MX25_PAD_CSI_D8__GPIO_1_7 0x138 0x330 0x000 0x15 0x000
289#define MX25_PAD_CSI_D8__CSPI3_SS2 0x138 0x330 0x4c4 0x17 0x000 328#define MX25_PAD_CSI_D8__CSPI3_SS2 0x138 0x330 0x4c4 0x17 0x000
290 329
291#define MX25_PAD_CSI_D9__CSI_D9 0x13c 0x334 0x000 0x10 0x000 330#define MX25_PAD_CSI_D9__CSI_D9 0x13c 0x334 0x000 0x10 0x000
292#define MX25_PAD_CSI_D9__AUD6_RXFS 0x13c 0x334 0x000 0x12 0x001 331#define MX25_PAD_CSI_D9__AUD6_RXFS 0x13c 0x334 0x000 0x12 0x000
293#define MX25_PAD_CSI_D9__GPIO_4_21 0x13c 0x334 0x000 0x15 0x000 332#define MX25_PAD_CSI_D9__GPIO_4_21 0x13c 0x334 0x000 0x15 0x000
294#define MX25_PAD_CSI_D9__CSPI3_SS3 0x13c 0x334 0x4c8 0x17 0x000 333#define MX25_PAD_CSI_D9__CSPI3_SS3 0x13c 0x334 0x4c8 0x17 0x000
295 334
296#define MX25_PAD_CSI_MCLK__CSI_MCLK 0x140 0x338 0x000 0x10 0x000 335#define MX25_PAD_CSI_MCLK__CSI_MCLK 0x140 0x338 0x000 0x10 0x000
297#define MX25_PAD_CSI_MCLK__AUD6_TXD 0x140 0x338 0x000 0x11 0x001 336#define MX25_PAD_CSI_MCLK__AUD6_TXD 0x140 0x338 0x000 0x11 0x000
298#define MX25_PAD_CSI_MCLK__SDHC2_DAT0 0x140 0x338 0x4e4 0x12 0x001 337#define MX25_PAD_CSI_MCLK__SDHC2_DAT0 0x140 0x338 0x4e4 0x12 0x001
299#define MX25_PAD_CSI_MCLK__GPIO_1_8 0x140 0x338 0x000 0x15 0x000 338#define MX25_PAD_CSI_MCLK__GPIO_1_8 0x140 0x338 0x000 0x15 0x000
300 339
301#define MX25_PAD_CSI_VSYNC__CSI_VSYNC 0x144 0x33c 0x000 0x10 0x000 340#define MX25_PAD_CSI_VSYNC__CSI_VSYNC 0x144 0x33c 0x000 0x10 0x000
302#define MX25_PAD_CSI_VSYNC__AUD6_RXD 0x144 0x33c 0x000 0x11 0x001 341#define MX25_PAD_CSI_VSYNC__AUD6_RXD 0x144 0x33c 0x000 0x11 0x000
303#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1 0x144 0x33c 0x4e8 0x12 0x001 342#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1 0x144 0x33c 0x4e8 0x12 0x001
304#define MX25_PAD_CSI_VSYNC__GPIO_1_9 0x144 0x33c 0x000 0x15 0x000 343#define MX25_PAD_CSI_VSYNC__GPIO_1_9 0x144 0x33c 0x000 0x15 0x000
305 344
306#define MX25_PAD_CSI_HSYNC__CSI_HSYNC 0x148 0x340 0x000 0x10 0x000 345#define MX25_PAD_CSI_HSYNC__CSI_HSYNC 0x148 0x340 0x000 0x10 0x000
307#define MX25_PAD_CSI_HSYNC__AUD6_TXC 0x148 0x340 0x000 0x11 0x001 346#define MX25_PAD_CSI_HSYNC__AUD6_TXC 0x148 0x340 0x000 0x11 0x000
308#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2 0x148 0x340 0x4ec 0x12 0x001 347#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2 0x148 0x340 0x4ec 0x12 0x001
309#define MX25_PAD_CSI_HSYNC__GPIO_1_10 0x148 0x340 0x000 0x15 0x000 348#define MX25_PAD_CSI_HSYNC__GPIO_1_10 0x148 0x340 0x000 0x15 0x000
310 349
311#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK 0x14c 0x344 0x000 0x10 0x000 350#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK 0x14c 0x344 0x000 0x10 0x000
312#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS 0x14c 0x344 0x000 0x11 0x001 351#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS 0x14c 0x344 0x000 0x11 0x000
313#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3 0x14c 0x344 0x4f0 0x12 0x001 352#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3 0x14c 0x344 0x4f0 0x12 0x001
314#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 0x14c 0x344 0x000 0x15 0x000 353#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 0x14c 0x344 0x000 0x15 0x000
315 354
@@ -369,8 +408,8 @@
369#define MX25_PAD_UART2_RTS__CC1 0x188 0x380 0x000 0x13 0x000 408#define MX25_PAD_UART2_RTS__CC1 0x188 0x380 0x000 0x13 0x000
370#define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x15 0x000 409#define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x15 0x000
371 410
372#define MX25_PAD_UART2_CTS__FEC_RX_ER 0x18c 0x384 0x518 0x12 0x002
373#define MX25_PAD_UART2_CTS__UART2_CTS 0x18c 0x384 0x000 0x10 0x000 411#define MX25_PAD_UART2_CTS__UART2_CTS 0x18c 0x384 0x000 0x10 0x000
412#define MX25_PAD_UART2_CTS__FEC_RX_ERR 0x18c 0x384 0x518 0x12 0x002
374#define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x15 0x000 413#define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x15 0x000
375 414
376#define MX25_PAD_SD1_CMD__SD1_CMD 0x190 0x388 0x000 0x10 0x000 415#define MX25_PAD_SD1_CMD__SD1_CMD 0x190 0x388 0x000 0x10 0x000
@@ -392,11 +431,11 @@
392#define MX25_PAD_SD1_DATA1__GPIO_2_26 0x19c 0x394 0x000 0x15 0x000 431#define MX25_PAD_SD1_DATA1__GPIO_2_26 0x19c 0x394 0x000 0x15 0x000
393 432
394#define MX25_PAD_SD1_DATA2__SD1_DATA2 0x1a0 0x398 0x000 0x10 0x000 433#define MX25_PAD_SD1_DATA2__SD1_DATA2 0x1a0 0x398 0x000 0x10 0x000
395#define MX25_PAD_SD1_DATA2__FEC_RX_CLK 0x1a0 0x398 0x514 0x15 0x002 434#define MX25_PAD_SD1_DATA2__FEC_RX_CLK 0x1a0 0x398 0x514 0x12 0x002
396#define MX25_PAD_SD1_DATA2__GPIO_2_27 0x1a0 0x398 0x000 0x15 0x000 435#define MX25_PAD_SD1_DATA2__GPIO_2_27 0x1a0 0x398 0x000 0x15 0x000
397 436
398#define MX25_PAD_SD1_DATA3__SD1_DATA3 0x1a4 0x39c 0x000 0x10 0x000 437#define MX25_PAD_SD1_DATA3__SD1_DATA3 0x1a4 0x39c 0x000 0x10 0x000
399#define MX25_PAD_SD1_DATA3__FEC_CRS 0x1a4 0x39c 0x508 0x10 0x002 438#define MX25_PAD_SD1_DATA3__FEC_CRS 0x1a4 0x39c 0x508 0x12 0x002
400#define MX25_PAD_SD1_DATA3__GPIO_2_28 0x1a4 0x39c 0x000 0x15 0x000 439#define MX25_PAD_SD1_DATA3__GPIO_2_28 0x1a4 0x39c 0x000 0x15 0x000
401 440
402#define MX25_PAD_KPP_ROW0__KPP_ROW0 0x1a8 0x3a0 0x000 0x10 0x000 441#define MX25_PAD_KPP_ROW0__KPP_ROW0 0x1a8 0x3a0 0x000 0x10 0x000
@@ -410,7 +449,7 @@
410#define MX25_PAD_KPP_ROW2__GPIO_2_31 0x1b0 0x3a8 0x000 0x15 0x000 449#define MX25_PAD_KPP_ROW2__GPIO_2_31 0x1b0 0x3a8 0x000 0x15 0x000
411 450
412#define MX25_PAD_KPP_ROW3__KPP_ROW3 0x1b4 0x3ac 0x000 0x10 0x000 451#define MX25_PAD_KPP_ROW3__KPP_ROW3 0x1b4 0x3ac 0x000 0x10 0x000
413#define MX25_PAD_KPP_ROW3__CSI_LD1 0x1b4 0x3ac 0x48c 0x13 0x002 452#define MX25_PAD_KPP_ROW3__CSI_D1 0x1b4 0x3ac 0x48c 0x13 0x002
414#define MX25_PAD_KPP_ROW3__GPIO_3_0 0x1b4 0x3ac 0x000 0x15 0x000 453#define MX25_PAD_KPP_ROW3__GPIO_3_0 0x1b4 0x3ac 0x000 0x15 0x000
415 454
416#define MX25_PAD_KPP_COL0__KPP_COL0 0x1b8 0x3b0 0x000 0x10 0x000 455#define MX25_PAD_KPP_COL0__KPP_COL0 0x1b8 0x3b0 0x000 0x10 0x000
@@ -455,9 +494,18 @@
455#define MX25_PAD_FEC_RDATA0__GPIO_3_10 0x1dc 0x3d4 0x000 0x15 0x000 494#define MX25_PAD_FEC_RDATA0__GPIO_3_10 0x1dc 0x3d4 0x000 0x15 0x000
456 495
457#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x1e0 0x3d8 0x000 0x10 0x000 496#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x1e0 0x3d8 0x000 0x10 0x000
497/*
498 * According to the i.MX25 Reference manual (IMX25RM, Rev. 2,
499 * 01/2011) this is CAN1_TX but that's wrong.
500 */
501#define MX25_PAD_FEC_RDATA1__CAN2_TX 0x1e0 0x3d8 0x000 0x14 0x000
458#define MX25_PAD_FEC_RDATA1__GPIO_3_11 0x1e0 0x3d8 0x000 0x15 0x000 502#define MX25_PAD_FEC_RDATA1__GPIO_3_11 0x1e0 0x3d8 0x000 0x15 0x000
459 503
460#define MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x1e4 0x3dc 0x000 0x10 0x000 504#define MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x1e4 0x3dc 0x000 0x10 0x000
505/*
506 * According to the i.MX25 Reference manual (IMX25RM, Rev. 2,
507 * 01/2011) this is CAN1_RX but that's wrong.
508 */
461#define MX25_PAD_FEC_RX_DV__CAN2_RX 0x1e4 0x3dc 0x484 0x14 0x000 509#define MX25_PAD_FEC_RX_DV__CAN2_RX 0x1e4 0x3dc 0x484 0x14 0x000
462#define MX25_PAD_FEC_RX_DV__GPIO_3_12 0x1e4 0x3dc 0x000 0x15 0x000 510#define MX25_PAD_FEC_RX_DV__GPIO_3_12 0x1e4 0x3dc 0x000 0x15 0x000
463 511
@@ -471,30 +519,34 @@
471#define MX25_PAD_DE_B__DE_B 0x1f0 0x3ec 0x000 0x10 0x000 519#define MX25_PAD_DE_B__DE_B 0x1f0 0x3ec 0x000 0x10 0x000
472#define MX25_PAD_DE_B__GPIO_2_20 0x1f0 0x3ec 0x000 0x15 0x000 520#define MX25_PAD_DE_B__GPIO_2_20 0x1f0 0x3ec 0x000 0x15 0x000
473 521
474#define MX25_PAD_TDO__TDO 0x000 0x3e8 0x000 0x00 0x000
475
476#define MX25_PAD_GPIO_A__GPIO_A 0x1f4 0x3f0 0x000 0x10 0x000 522#define MX25_PAD_GPIO_A__GPIO_A 0x1f4 0x3f0 0x000 0x10 0x000
477#define MX25_PAD_GPIO_A__CAN1_TX 0x1f4 0x3f0 0x000 0x16 0x000 523#define MX25_PAD_GPIO_A__CAN1_TX 0x1f4 0x3f0 0x000 0x16 0x000
478#define MX25_PAD_GPIO_A__USBOTG_PWR 0x1f4 0x3f0 0x000 0x12 0x000 524#define MX25_PAD_GPIO_A__USBOTG_PWR 0x1f4 0x3f0 0x000 0x12 0x000
479 525
480#define MX25_PAD_GPIO_B__GPIO_B 0x1f8 0x3f4 0x000 0x10 0x000 526#define MX25_PAD_GPIO_B__GPIO_B 0x1f8 0x3f4 0x000 0x10 0x000
481#define MX25_PAD_GPIO_B__CAN1_RX 0x1f8 0x3f4 0x480 0x16 0x001
482#define MX25_PAD_GPIO_B__USBOTG_OC 0x1f8 0x3f4 0x57c 0x12 0x001 527#define MX25_PAD_GPIO_B__USBOTG_OC 0x1f8 0x3f4 0x57c 0x12 0x001
528#define MX25_PAD_GPIO_B__CAN1_RX 0x1f8 0x3f4 0x480 0x16 0x001
483 529
484#define MX25_PAD_GPIO_C__GPIO_C 0x1fc 0x3f8 0x000 0x10 0x000 530#define MX25_PAD_GPIO_C__GPIO_C 0x1fc 0x3f8 0x000 0x10 0x000
531#define MX25_PAD_GPIO_C__PWM4_PWMO 0x1fc 0x3f8 0x000 0x11 0x000
532#define MX25_PAD_GPIO_C__I2C2_SCL 0x1fc 0x3f8 0x51c 0x12 0x001
533#define MX25_PAD_GPIO_C__KPP_COL4 0x1fc 0x3f8 0x52c 0x13 0x001
485#define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x16 0x000 534#define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x16 0x000
486 535
487#define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x10 0x000 536#define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x10 0x000
537#define MX25_PAD_GPIO_D__I2C2_SDA 0x200 0x3fc 0x520 0x12 0x001
488#define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x16 0x001 538#define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x16 0x001
489 539
490#define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x10 0x000 540#define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x10 0x000
491#define MX25_PAD_GPIO_E__I2C3_CLK 0x204 0x400 0x524 0x11 0x002 541#define MX25_PAD_GPIO_E__I2C3_CLK 0x204 0x400 0x524 0x11 0x002
492#define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x12 0x000 542#define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x12 0x000
493#define MX25_PAD_GPIO_E__AUD7_TXD 0x204 0x400 0x000 0x14 0x000 543#define MX25_PAD_GPIO_E__AUD7_TXD 0x204 0x400 0x000 0x14 0x000
544#define MX25_PAD_GPIO_E__UART4_RXD 0x204 0x400 0x570 0x16 0x002
494 545
495#define MX25_PAD_GPIO_F__GPIO_F 0x208 0x404 0x000 0x10 0x000 546#define MX25_PAD_GPIO_F__GPIO_F 0x208 0x404 0x000 0x10 0x000
496#define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x12 0x000 547#define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x12 0x000
497#define MX25_PAD_GPIO_F__AUD7_TXC 0x208 0x404 0x000 0x14 0x000 548#define MX25_PAD_GPIO_F__AUD7_TXC 0x208 0x404 0x000 0x14 0x000
549#define MX25_PAD_GPIO_F__UART4_TXD 0x208 0x404 0x000 0x16 0x000
498 550
499#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK 0x20c 0x000 0x000 0x10 0x000 551#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK 0x20c 0x000 0x000 0x10 0x000
500#define MX25_PAD_EXT_ARMCLK__GPIO_3_15 0x20c 0x000 0x000 0x15 0x000 552#define MX25_PAD_EXT_ARMCLK__GPIO_3_15 0x20c 0x000 0x000 0x15 0x000
@@ -505,6 +557,7 @@
505#define MX25_PAD_VSTBY_REQ__VSTBY_REQ 0x214 0x408 0x000 0x10 0x000 557#define MX25_PAD_VSTBY_REQ__VSTBY_REQ 0x214 0x408 0x000 0x10 0x000
506#define MX25_PAD_VSTBY_REQ__AUD7_TXFS 0x214 0x408 0x000 0x14 0x000 558#define MX25_PAD_VSTBY_REQ__AUD7_TXFS 0x214 0x408 0x000 0x14 0x000
507#define MX25_PAD_VSTBY_REQ__GPIO_3_17 0x214 0x408 0x000 0x15 0x000 559#define MX25_PAD_VSTBY_REQ__GPIO_3_17 0x214 0x408 0x000 0x15 0x000
560
508#define MX25_PAD_VSTBY_ACK__VSTBY_ACK 0x218 0x40c 0x000 0x10 0x000 561#define MX25_PAD_VSTBY_ACK__VSTBY_ACK 0x218 0x40c 0x000 0x10 0x000
509#define MX25_PAD_VSTBY_ACK__GPIO_3_18 0x218 0x40c 0x000 0x15 0x000 562#define MX25_PAD_VSTBY_ACK__GPIO_3_18 0x218 0x40c 0x000 0x15 0x000
510 563
@@ -517,6 +570,7 @@
517 570
518#define MX25_PAD_BOOT_MODE0__BOOT_MODE0 0x224 0x000 0x000 0x00 0x000 571#define MX25_PAD_BOOT_MODE0__BOOT_MODE0 0x224 0x000 0x000 0x00 0x000
519#define MX25_PAD_BOOT_MODE0__GPIO_4_30 0x224 0x000 0x000 0x05 0x000 572#define MX25_PAD_BOOT_MODE0__GPIO_4_30 0x224 0x000 0x000 0x05 0x000
573
520#define MX25_PAD_BOOT_MODE1__BOOT_MODE1 0x228 0x000 0x000 0x00 0x000 574#define MX25_PAD_BOOT_MODE1__BOOT_MODE1 0x228 0x000 0x000 0x00 0x000
521#define MX25_PAD_BOOT_MODE1__GPIO_4_31 0x228 0x000 0x000 0x05 0x000 575#define MX25_PAD_BOOT_MODE1__GPIO_4_31 0x228 0x000 0x000 0x05 0x000
522 576
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 4b063b68db44..6951b66d1ab7 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -488,6 +488,7 @@
488 interrupts = <54>; 488 interrupts = <54>;
489 clocks = <&clks IMX27_CLK_USB_IPG_GATE>; 489 clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
490 fsl,usbmisc = <&usbmisc 1>; 490 fsl,usbmisc = <&usbmisc 1>;
491 dr_mode = "host";
491 status = "disabled"; 492 status = "disabled";
492 }; 493 };
493 494
@@ -497,6 +498,7 @@
497 interrupts = <55>; 498 interrupts = <55>;
498 clocks = <&clks IMX27_CLK_USB_IPG_GATE>; 499 clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
499 fsl,usbmisc = <&usbmisc 2>; 500 fsl,usbmisc = <&usbmisc 2>;
501 dr_mode = "host";
500 status = "disabled"; 502 status = "disabled";
501 }; 503 };
502 504
diff --git a/arch/arm/boot/dts/imx28-apf28.dts b/arch/arm/boot/dts/imx28-apf28.dts
index 7198fe3798c6..070e59cbdd8b 100644
--- a/arch/arm/boot/dts/imx28-apf28.dts
+++ b/arch/arm/boot/dts/imx28-apf28.dts
@@ -78,7 +78,7 @@
78 phy-mode = "rmii"; 78 phy-mode = "rmii";
79 pinctrl-names = "default"; 79 pinctrl-names = "default";
80 pinctrl-0 = <&mac0_pins_a>; 80 pinctrl-0 = <&mac0_pins_a>;
81 phy-reset-gpios = <&gpio4 13 0>; 81 phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;
82 status = "okay"; 82 status = "okay";
83 }; 83 };
84 }; 84 };
diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts
index 1f38a052ad4b..7ac4f1af16ac 100644
--- a/arch/arm/boot/dts/imx28-apf28dev.dts
+++ b/arch/arm/boot/dts/imx28-apf28dev.dts
@@ -110,6 +110,13 @@
110 }; 110 };
111 }; 111 };
112 }; 112 };
113
114 can0: can@80032000 {
115 pinctrl-names = "default";
116 pinctrl-0 = <&can0_pins_a>;
117 xceiver-supply = <&reg_can0_vcc>;
118 status = "okay";
119 };
113 }; 120 };
114 121
115 apbx@80040000 { 122 apbx@80040000 {
@@ -130,6 +137,13 @@
130 status = "okay"; 137 status = "okay";
131 }; 138 };
132 139
140 auart0: serial@8006a000 {
141 pinctrl-names = "default";
142 pinctrl-0 = <&auart0_pins_a>;
143 fsl,uart-has-rtscts;
144 status = "okay";
145 };
146
133 usbphy0: usbphy@8007c000 { 147 usbphy0: usbphy@8007c000 {
134 status = "okay"; 148 status = "okay";
135 }; 149 };
@@ -143,7 +157,8 @@
143 ahb@80080000 { 157 ahb@80080000 {
144 usb0: usb@80080000 { 158 usb0: usb@80080000 {
145 pinctrl-names = "default"; 159 pinctrl-names = "default";
146 pinctrl-0 = <&usb0_otg_apf28dev>; 160 pinctrl-0 = <&usb0_otg_apf28dev
161 &usb0_id_pins_b>;
147 vbus-supply = <&reg_usb0_vbus>; 162 vbus-supply = <&reg_usb0_vbus>;
148 status = "okay"; 163 status = "okay";
149 }; 164 };
@@ -156,7 +171,7 @@
156 phy-mode = "rmii"; 171 phy-mode = "rmii";
157 pinctrl-names = "default"; 172 pinctrl-names = "default";
158 pinctrl-0 = <&mac1_pins_a>; 173 pinctrl-0 = <&mac1_pins_a>;
159 phy-reset-gpios = <&gpio0 23 0>; 174 phy-reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
160 status = "okay"; 175 status = "okay";
161 }; 176 };
162 }; 177 };
@@ -175,6 +190,14 @@
175 gpio = <&gpio1 23 1>; 190 gpio = <&gpio1 23 1>;
176 enable-active-high; 191 enable-active-high;
177 }; 192 };
193
194 reg_can0_vcc: regulator@1 {
195 compatible = "regulator-fixed";
196 reg = <1>;
197 regulator-name = "can0_vcc";
198 regulator-min-microvolt = <5000000>;
199 regulator-max-microvolt = <5000000>;
200 };
178 }; 201 };
179 202
180 leds { 203 leds {
@@ -200,8 +223,9 @@
200 223
201 user-button { 224 user-button {
202 label = "User button"; 225 label = "User button";
203 gpios = <&gpio0 17 0>; 226 gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
204 linux,code = <0x100>; 227 linux,code = <0x100>;
228 gpio-key,wakeup;
205 }; 229 };
206 }; 230 };
207}; 231};
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 47f68ac868d4..25e25f82fbae 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -829,6 +829,19 @@
829 fsl,pull-up = <MXS_PULL_DISABLE>; 829 fsl,pull-up = <MXS_PULL_DISABLE>;
830 }; 830 };
831 831
832 spi3_pins_b: spi3@1 {
833 reg = <1>;
834 fsl,pinmux-ids = <
835 MX28_PAD_SSP3_SCK__SSP3_SCK
836 MX28_PAD_SSP3_MOSI__SSP3_CMD
837 MX28_PAD_SSP3_MISO__SSP3_D0
838 MX28_PAD_SSP3_SS0__SSP3_D3
839 >;
840 fsl,drive-strength = <MXS_DRIVE_8mA>;
841 fsl,voltage = <MXS_VOLTAGE_HIGH>;
842 fsl,pull-up = <MXS_PULL_ENABLE>;
843 };
844
832 usb0_pins_a: usb0@0 { 845 usb0_pins_a: usb0@0 {
833 reg = <0>; 846 reg = <0>;
834 fsl,pinmux-ids = < 847 fsl,pinmux-ids = <
@@ -1197,6 +1210,7 @@
1197 interrupts = <92>; 1210 interrupts = <92>;
1198 clocks = <&clks 61>; 1211 clocks = <&clks 61>;
1199 fsl,usbphy = <&usbphy1>; 1212 fsl,usbphy = <&usbphy1>;
1213 dr_mode = "host";
1200 status = "disabled"; 1214 status = "disabled";
1201 }; 1215 };
1202 1216
diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi
index 6932928f3b45..b6478e97d6a7 100644
--- a/arch/arm/boot/dts/imx35.dtsi
+++ b/arch/arm/boot/dts/imx35.dtsi
@@ -318,6 +318,7 @@
318 clocks = <&clks 73>; 318 clocks = <&clks 73>;
319 fsl,usbmisc = <&usbmisc 1>; 319 fsl,usbmisc = <&usbmisc 1>;
320 fsl,usbphy = <&usbphy1>; 320 fsl,usbphy = <&usbphy1>;
321 dr_mode = "host";
321 status = "disabled"; 322 status = "disabled";
322 }; 323 };
323 324
diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi
index 620b0f030591..e2457138311f 100644
--- a/arch/arm/boot/dts/imx50.dtsi
+++ b/arch/arm/boot/dts/imx50.dtsi
@@ -197,6 +197,7 @@
197 reg = <0x53f80200 0x0200>; 197 reg = <0x53f80200 0x0200>;
198 interrupts = <14>; 198 interrupts = <14>;
199 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; 199 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
200 dr_mode = "host";
200 status = "disabled"; 201 status = "disabled";
201 }; 202 };
202 203
@@ -205,6 +206,7 @@
205 reg = <0x53f80400 0x0200>; 206 reg = <0x53f80400 0x0200>;
206 interrupts = <16>; 207 interrupts = <16>;
207 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 208 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
209 dr_mode = "host";
208 status = "disabled"; 210 status = "disabled";
209 }; 211 };
210 212
@@ -213,6 +215,7 @@
213 reg = <0x53f80600 0x0200>; 215 reg = <0x53f80600 0x0200>;
214 interrupts = <17>; 216 interrupts = <17>;
215 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 217 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
218 dr_mode = "host";
216 status = "disabled"; 219 status = "disabled";
217 }; 220 };
218 221
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index c0116cffc513..f46fe9bf0bcb 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -265,6 +265,7 @@
265 interrupts = <14>; 265 interrupts = <14>;
266 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 266 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
267 fsl,usbmisc = <&usbmisc 1>; 267 fsl,usbmisc = <&usbmisc 1>;
268 dr_mode = "host";
268 status = "disabled"; 269 status = "disabled";
269 }; 270 };
270 271
@@ -274,6 +275,7 @@
274 interrupts = <16>; 275 interrupts = <16>;
275 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 276 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
276 fsl,usbmisc = <&usbmisc 2>; 277 fsl,usbmisc = <&usbmisc 2>;
278 dr_mode = "host";
277 status = "disabled"; 279 status = "disabled";
278 }; 280 };
279 281
@@ -283,6 +285,7 @@
283 interrupts = <17>; 285 interrupts = <17>;
284 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 286 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
285 fsl,usbmisc = <&usbmisc 3>; 287 fsl,usbmisc = <&usbmisc 3>;
288 dr_mode = "host";
286 status = "disabled"; 289 status = "disabled";
287 }; 290 };
288 291
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index ff4fa7ecacd8..c3e3ca9362fb 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -309,6 +309,7 @@
309 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 309 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
310 fsl,usbmisc = <&usbmisc 1>; 310 fsl,usbmisc = <&usbmisc 1>;
311 fsl,usbphy = <&usbphy1>; 311 fsl,usbphy = <&usbphy1>;
312 dr_mode = "host";
312 status = "disabled"; 313 status = "disabled";
313 }; 314 };
314 315
@@ -318,6 +319,7 @@
318 interrupts = <16>; 319 interrupts = <16>;
319 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 320 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
320 fsl,usbmisc = <&usbmisc 2>; 321 fsl,usbmisc = <&usbmisc 2>;
322 dr_mode = "host";
321 status = "disabled"; 323 status = "disabled";
322 }; 324 };
323 325
@@ -327,6 +329,7 @@
327 interrupts = <17>; 329 interrupts = <17>;
328 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 330 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
329 fsl,usbmisc = <&usbmisc 3>; 331 fsl,usbmisc = <&usbmisc 3>;
332 dr_mode = "host";
330 status = "disabled"; 333 status = "disabled";
331 }; 334 };
332 335
diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts
index 9cd06e5e59f0..d4c4a22db488 100644
--- a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts
+++ b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts
@@ -83,3 +83,7 @@
83&ipu1_di0_disp0 { 83&ipu1_di0_disp0 {
84 remote-endpoint = <&display0_in>; 84 remote-endpoint = <&display0_in>;
85}; 85};
86
87&pwm1 {
88 status = "okay";
89};
diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts
index b413e24288dc..15203f0e9725 100644
--- a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts
+++ b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts
@@ -72,3 +72,7 @@
72&ipu1_di0_disp0 { 72&ipu1_di0_disp0 {
73 remote-endpoint = <&display0_in>; 73 remote-endpoint = <&display0_in>;
74}; 74};
75
76&pwm3 {
77 status = "okay";
78};
diff --git a/arch/arm/boot/dts/imx6dl-cubox-i.dts b/arch/arm/boot/dts/imx6dl-cubox-i.dts
index 58aa8f2b0f26..e0b7fe8e18f8 100644
--- a/arch/arm/boot/dts/imx6dl-cubox-i.dts
+++ b/arch/arm/boot/dts/imx6dl-cubox-i.dts
@@ -1,5 +1,43 @@
1/* 1/*
2 * Copyright (C) 2014 Russell King 2 * Copyright (C) 2014 Russell King
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License.
13 *
14 * This file is distributed in the hope that it will be useful
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
3 */ 41 */
4/dts-v1/; 42/dts-v1/;
5 43
diff --git a/arch/arm/boot/dts/imx6dl-hummingboard.dts b/arch/arm/boot/dts/imx6dl-hummingboard.dts
index 44a0e6736bb1..7369d2d7da3e 100644
--- a/arch/arm/boot/dts/imx6dl-hummingboard.dts
+++ b/arch/arm/boot/dts/imx6dl-hummingboard.dts
@@ -1,6 +1,44 @@
1/* 1/*
2 * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) 2 * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com)
3 * Based on dt work by Russell King 3 * Based on dt work by Russell King
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License.
14 *
15 * This file is distributed in the hope that it will be useful
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * Or, alternatively
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
4 */ 42 */
5/dts-v1/; 43/dts-v1/;
6 44
diff --git a/arch/arm/boot/dts/imx6q-cubox-i.dts b/arch/arm/boot/dts/imx6q-cubox-i.dts
index 9efd8b0c8011..670bd8c4c847 100644
--- a/arch/arm/boot/dts/imx6q-cubox-i.dts
+++ b/arch/arm/boot/dts/imx6q-cubox-i.dts
@@ -1,5 +1,43 @@
1/* 1/*
2 * Copyright (C) 2014 Russell King 2 * Copyright (C) 2014 Russell King
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License.
13 *
14 * This file is distributed in the hope that it will be useful
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
3 */ 41 */
4/dts-v1/; 42/dts-v1/;
5 43
diff --git a/arch/arm/boot/dts/imx6q-hummingboard.dts b/arch/arm/boot/dts/imx6q-hummingboard.dts
index c2bf8476ce45..0f6044553a24 100644
--- a/arch/arm/boot/dts/imx6q-hummingboard.dts
+++ b/arch/arm/boot/dts/imx6q-hummingboard.dts
@@ -1,6 +1,44 @@
1/* 1/*
2 * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) 2 * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com)
3 * Based on dt work by Russell King 3 * Based on dt work by Russell King
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License.
14 *
15 * This file is distributed in the hope that it will be useful
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * Or, alternatively
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
4 */ 42 */
5/dts-v1/; 43/dts-v1/;
6 44
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 93ec79bb6b35..399103b8e2c9 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -294,19 +294,21 @@
294}; 294};
295 295
296&mipi_dsi { 296&mipi_dsi {
297 port@2 { 297 ports {
298 reg = <2>; 298 port@2 {
299 reg = <2>;
299 300
300 mipi_mux_2: endpoint { 301 mipi_mux_2: endpoint {
301 remote-endpoint = <&ipu2_di0_mipi>; 302 remote-endpoint = <&ipu2_di0_mipi>;
303 };
302 }; 304 };
303 };
304 305
305 port@3 { 306 port@3 {
306 reg = <3>; 307 reg = <3>;
307 308
308 mipi_mux_3: endpoint { 309 mipi_mux_3: endpoint {
309 remote-endpoint = <&ipu2_di1_mipi>; 310 remote-endpoint = <&ipu2_di1_mipi>;
311 };
310 }; 312 };
311 }; 313 };
312}; 314};
diff --git a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
index 6a524ca011e7..d033bb182060 100644
--- a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
@@ -1,8 +1,48 @@
1/* 1/*
2 * Copyright (C) 2014 Russell King 2 * Copyright (C) 2014 Russell King
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License.
13 *
14 * This file is distributed in the hope that it will be useful
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
3 */ 41 */
4#include "imx6qdl-microsom.dtsi" 42#include "imx6qdl-microsom.dtsi"
5#include "imx6qdl-microsom-ar8035.dtsi" 43#include "imx6qdl-microsom-ar8035.dtsi"
44#include <dt-bindings/input/input.h>
45#include <dt-bindings/gpio/gpio.h>
6 46
7/ { 47/ {
8 ir_recv: ir-receiver { 48 ir_recv: ir-receiver {
@@ -66,6 +106,18 @@
66 spdif-controller = <&spdif>; 106 spdif-controller = <&spdif>;
67 spdif-out; 107 spdif-out;
68 }; 108 };
109
110 gpio-keys {
111 compatible = "gpio-keys";
112 pinctrl-0 = <&pinctrl_gpio_key>;
113 pinctrl-names = "default";
114
115 button_0 {
116 label = "Button 0";
117 gpios = <&gpio3 8 GPIO_ACTIVE_LOW>;
118 linux,code = <BTN_0>;
119 };
120 };
69}; 121};
70 122
71&hdmi { 123&hdmi {
@@ -170,9 +222,19 @@
170 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 222 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
171 >; 223 >;
172 }; 224 };
225
226 pinctrl_gpio_key: gpio-key {
227 fsl,pins = <
228 MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x17059
229 >;
230 };
173 }; 231 };
174}; 232};
175 233
234&pwm1 {
235 status = "okay";
236};
237
176&spdif { 238&spdif {
177 pinctrl-names = "default"; 239 pinctrl-names = "default";
178 pinctrl-0 = <&pinctrl_cubox_i_spdif>; 240 pinctrl-0 = <&pinctrl_cubox_i_spdif>;
diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi
index 62841e85a91e..151a3db2aea9 100644
--- a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi
@@ -1,5 +1,43 @@
1/* 1/*
2 * Copyright (C) 2013,2014 Russell King 2 * Copyright (C) 2013,2014 Russell King
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License.
13 *
14 * This file is distributed in the hope that it will be useful
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
3 */ 41 */
4#include "imx6qdl-microsom.dtsi" 42#include "imx6qdl-microsom.dtsi"
5#include "imx6qdl-microsom-ar8035.dtsi" 43#include "imx6qdl-microsom-ar8035.dtsi"
@@ -50,6 +88,19 @@
50 }; 88 };
51 }; 89 };
52 90
91 sound-sgtl5000 {
92 audio-codec = <&sgtl5000>;
93 audio-routing =
94 "MIC_IN", "Mic Jack",
95 "Mic Jack", "Mic Bias",
96 "Headphone Jack", "HP_OUT";
97 compatible = "fsl,imx-audio-sgtl5000";
98 model = "On-board Codec";
99 mux-ext-port = <5>;
100 mux-int-port = <1>;
101 ssi-controller = <&ssi1>;
102 };
103
53 sound-spdif { 104 sound-spdif {
54 compatible = "fsl,imx-audio-spdif"; 105 compatible = "fsl,imx-audio-spdif";
55 model = "On-board SPDIF"; 106 model = "On-board SPDIF";
@@ -59,6 +110,10 @@
59 }; 110 };
60}; 111};
61 112
113&audmux {
114 status = "okay";
115};
116
62&can1 { 117&can1 {
63 pinctrl-names = "default"; 118 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_hummingboard_flexcan1>; 119 pinctrl-0 = <&pinctrl_hummingboard_flexcan1>;
@@ -75,16 +130,24 @@
75&i2c1 { 130&i2c1 {
76 pinctrl-names = "default"; 131 pinctrl-names = "default";
77 pinctrl-0 = <&pinctrl_hummingboard_i2c1>; 132 pinctrl-0 = <&pinctrl_hummingboard_i2c1>;
78
79 /*
80 * Not fitted on Carrier-1 board... yet
81 status = "okay"; 133 status = "okay";
82 134
135 /* Pro baseboard model */
83 rtc: pcf8523@68 { 136 rtc: pcf8523@68 {
84 compatible = "nxp,pcf8523"; 137 compatible = "nxp,pcf8523";
85 reg = <0x68>; 138 reg = <0x68>;
86 }; 139 };
87 */ 140
141 /* Pro baseboard model */
142 sgtl5000: sgtl5000@0a {
143 clocks = <&clks IMX6QDL_CLK_CKO>;
144 compatible = "fsl,sgtl5000";
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_hummingboard_sgtl5000>;
147 reg = <0x0a>;
148 VDDA-supply = <&reg_3p3v>;
149 VDDIO-supply = <&reg_3p3v>;
150 };
88}; 151};
89 152
90&i2c2 { 153&i2c2 {
@@ -129,6 +192,20 @@
129 >; 192 >;
130 }; 193 };
131 194
195 pinctrl_hummingboard_pwm1: pwm1grp {
196 fsl,pins = <MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1>;
197 };
198
199 pinctrl_hummingboard_sgtl5000: hummingboard-sgtl5000 {
200 fsl,pins = <
201 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
202 MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
203 MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0
204 MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
205 MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0
206 >;
207 };
208
132 pinctrl_hummingboard_spdif: hummingboard-spdif { 209 pinctrl_hummingboard_spdif: hummingboard-spdif {
133 fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>; 210 fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
134 }; 211 };
@@ -168,12 +245,28 @@
168 }; 245 };
169}; 246};
170 247
248&pwm1 {
249 pinctrl-names = "default";
250 pinctrl-0 = <&pinctrl_hummingboard_pwm1>;
251 status = "okay";
252};
253
254&pwm2 {
255 pinctrl-names = "default";
256 status = "okay";
257};
258
171&spdif { 259&spdif {
172 pinctrl-names = "default"; 260 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_hummingboard_spdif>; 261 pinctrl-0 = <&pinctrl_hummingboard_spdif>;
174 status = "okay"; 262 status = "okay";
175}; 263};
176 264
265&ssi1 {
266 fsl,mode = "i2s-slave";
267 status = "okay";
268};
269
177&usbh1 { 270&usbh1 {
178 disable-over-current; 271 disable-over-current;
179 vbus-supply = <&reg_usbh1_vbus>; 272 vbus-supply = <&reg_usbh1_vbus>;
diff --git a/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi b/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
index db9f45b2c573..4a1820309cdb 100644
--- a/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
@@ -3,6 +3,44 @@
3 * 3 *
4 * This describes the hookup for an AR8035 to the iMX6 on the SolidRun 4 * This describes the hookup for an AR8035 to the iMX6 on the SolidRun
5 * MicroSOM. 5 * MicroSOM.
6 *
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
10 * whole.
11 *
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License.
16 *
17 * This file is distributed in the hope that it will be useful
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * Or, alternatively
23 *
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
31 * conditions:
32 *
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
35 *
36 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
6 */ 44 */
7&fec { 45&fec {
8 pinctrl-names = "default"; 46 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/imx6qdl-microsom.dtsi b/arch/arm/boot/dts/imx6qdl-microsom.dtsi
index 79eac6849d4c..349f82be816e 100644
--- a/arch/arm/boot/dts/imx6qdl-microsom.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-microsom.dtsi
@@ -1,5 +1,43 @@
1/* 1/*
2 * Copyright (C) 2013,2014 Russell King 2 * Copyright (C) 2013,2014 Russell King
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License.
13 *
14 * This file is distributed in the hope that it will be useful
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
3 */ 41 */
4 42
5&iomuxc { 43&iomuxc {
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 009abd69385d..46b2fed7c319 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -182,6 +182,34 @@
182 }; 182 };
183}; 183};
184 184
185&i2c3 {
186 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_i2c3>;
188 pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
189 status = "okay";
190
191 max7310_a: gpio@30 {
192 compatible = "maxim,max7310";
193 reg = <0x30>;
194 gpio-controller;
195 #gpio-cells = <2>;
196 };
197
198 max7310_b: gpio@32 {
199 compatible = "maxim,max7310";
200 reg = <0x32>;
201 gpio-controller;
202 #gpio-cells = <2>;
203 };
204
205 max7310_c: gpio@34 {
206 compatible = "maxim,max7310";
207 reg = <0x34>;
208 gpio-controller;
209 #gpio-cells = <2>;
210 };
211};
212
185&iomuxc { 213&iomuxc {
186 pinctrl-names = "default"; 214 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_hog>; 215 pinctrl-0 = <&pinctrl_hog>;
@@ -265,6 +293,13 @@
265 >; 293 >;
266 }; 294 };
267 295
296 pinctrl_i2c3: i2c3grp {
297 fsl,pins = <
298 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
299 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
300 >;
301 };
302
268 pinctrl_pwm3: pwm1grp { 303 pinctrl_pwm3: pwm1grp {
269 fsl,pins = < 304 fsl,pins = <
270 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 305 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index d6c69ec44314..f74a8ded515f 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -53,6 +53,7 @@
53 interrupt-controller; 53 interrupt-controller;
54 reg = <0x00a01000 0x1000>, 54 reg = <0x00a01000 0x1000>,
55 <0x00a00100 0x100>; 55 <0x00a00100 0x100>;
56 interrupt-parent = <&intc>;
56 }; 57 };
57 58
58 clocks { 59 clocks {
@@ -82,7 +83,7 @@
82 #address-cells = <1>; 83 #address-cells = <1>;
83 #size-cells = <1>; 84 #size-cells = <1>;
84 compatible = "simple-bus"; 85 compatible = "simple-bus";
85 interrupt-parent = <&intc>; 86 interrupt-parent = <&gpc>;
86 ranges; 87 ranges;
87 88
88 dma_apbh: dma-apbh@00110000 { 89 dma_apbh: dma-apbh@00110000 {
@@ -122,6 +123,7 @@
122 compatible = "arm,cortex-a9-twd-timer"; 123 compatible = "arm,cortex-a9-twd-timer";
123 reg = <0x00a00600 0x20>; 124 reg = <0x00a00600 0x20>;
124 interrupts = <1 13 0xf01>; 125 interrupts = <1 13 0xf01>;
126 interrupt-parent = <&intc>;
125 clocks = <&clks IMX6QDL_CLK_TWD>; 127 clocks = <&clks IMX6QDL_CLK_TWD>;
126 }; 128 };
127 129
@@ -357,6 +359,7 @@
357 clocks = <&clks IMX6QDL_CLK_IPG>, 359 clocks = <&clks IMX6QDL_CLK_IPG>,
358 <&clks IMX6QDL_CLK_PWM1>; 360 <&clks IMX6QDL_CLK_PWM1>;
359 clock-names = "ipg", "per"; 361 clock-names = "ipg", "per";
362 status = "disabled";
360 }; 363 };
361 364
362 pwm2: pwm@02084000 { 365 pwm2: pwm@02084000 {
@@ -367,6 +370,7 @@
367 clocks = <&clks IMX6QDL_CLK_IPG>, 370 clocks = <&clks IMX6QDL_CLK_IPG>,
368 <&clks IMX6QDL_CLK_PWM2>; 371 <&clks IMX6QDL_CLK_PWM2>;
369 clock-names = "ipg", "per"; 372 clock-names = "ipg", "per";
373 status = "disabled";
370 }; 374 };
371 375
372 pwm3: pwm@02088000 { 376 pwm3: pwm@02088000 {
@@ -377,6 +381,7 @@
377 clocks = <&clks IMX6QDL_CLK_IPG>, 381 clocks = <&clks IMX6QDL_CLK_IPG>,
378 <&clks IMX6QDL_CLK_PWM3>; 382 <&clks IMX6QDL_CLK_PWM3>;
379 clock-names = "ipg", "per"; 383 clock-names = "ipg", "per";
384 status = "disabled";
380 }; 385 };
381 386
382 pwm4: pwm@0208c000 { 387 pwm4: pwm@0208c000 {
@@ -387,6 +392,7 @@
387 clocks = <&clks IMX6QDL_CLK_IPG>, 392 clocks = <&clks IMX6QDL_CLK_IPG>,
388 <&clks IMX6QDL_CLK_PWM4>; 393 <&clks IMX6QDL_CLK_PWM4>;
389 clock-names = "ipg", "per"; 394 clock-names = "ipg", "per";
395 status = "disabled";
390 }; 396 };
391 397
392 can1: flexcan@02090000 { 398 can1: flexcan@02090000 {
@@ -598,7 +604,7 @@
598 regulator-name = "vddpu"; 604 regulator-name = "vddpu";
599 regulator-min-microvolt = <725000>; 605 regulator-min-microvolt = <725000>;
600 regulator-max-microvolt = <1450000>; 606 regulator-max-microvolt = <1450000>;
601 regulator-always-on; 607 regulator-enable-ramp-delay = <150>;
602 anatop-reg-offset = <0x140>; 608 anatop-reg-offset = <0x140>;
603 anatop-vol-bit-shift = <9>; 609 anatop-vol-bit-shift = <9>;
604 anatop-vol-bit-width = <5>; 610 anatop-vol-bit-width = <5>;
@@ -658,7 +664,7 @@
658 #size-cells = <1>; 664 #size-cells = <1>;
659 ranges = <0 0x020cc000 0x4000>; 665 ranges = <0 0x020cc000 0x4000>;
660 666
661 snvs-rtc-lp@34 { 667 snvs_rtc: snvs-rtc-lp@34 {
662 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 668 compatible = "fsl,sec-v4.0-mon-rtc-lp";
663 reg = <0x34 0x58>; 669 reg = <0x34 0x58>;
664 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, 670 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
@@ -693,8 +699,19 @@
693 gpc: gpc@020dc000 { 699 gpc: gpc@020dc000 {
694 compatible = "fsl,imx6q-gpc"; 700 compatible = "fsl,imx6q-gpc";
695 reg = <0x020dc000 0x4000>; 701 reg = <0x020dc000 0x4000>;
702 interrupt-controller;
703 #interrupt-cells = <3>;
696 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>, 704 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
697 <0 90 IRQ_TYPE_LEVEL_HIGH>; 705 <0 90 IRQ_TYPE_LEVEL_HIGH>;
706 interrupt-parent = <&intc>;
707 pu-supply = <&reg_pu>;
708 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
709 <&clks IMX6QDL_CLK_GPU3D_SHADER>,
710 <&clks IMX6QDL_CLK_GPU2D_CORE>,
711 <&clks IMX6QDL_CLK_GPU2D_AXI>,
712 <&clks IMX6QDL_CLK_OPENVG_AXI>,
713 <&clks IMX6QDL_CLK_VPU_AXI>;
714 #power-domain-cells = <1>;
698 }; 715 };
699 716
700 gpr: iomuxc-gpr@020e0000 { 717 gpr: iomuxc-gpr@020e0000 {
@@ -845,6 +862,7 @@
845 clocks = <&clks IMX6QDL_CLK_USBOH3>; 862 clocks = <&clks IMX6QDL_CLK_USBOH3>;
846 fsl,usbphy = <&usbphy2>; 863 fsl,usbphy = <&usbphy2>;
847 fsl,usbmisc = <&usbmisc 1>; 864 fsl,usbmisc = <&usbmisc 1>;
865 dr_mode = "host";
848 status = "disabled"; 866 status = "disabled";
849 }; 867 };
850 868
@@ -854,6 +872,7 @@
854 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; 872 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
855 clocks = <&clks IMX6QDL_CLK_USBOH3>; 873 clocks = <&clks IMX6QDL_CLK_USBOH3>;
856 fsl,usbmisc = <&usbmisc 2>; 874 fsl,usbmisc = <&usbmisc 2>;
875 dr_mode = "host";
857 status = "disabled"; 876 status = "disabled";
858 }; 877 };
859 878
@@ -863,6 +882,7 @@
863 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; 882 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
864 clocks = <&clks IMX6QDL_CLK_USBOH3>; 883 clocks = <&clks IMX6QDL_CLK_USBOH3>;
865 fsl,usbmisc = <&usbmisc 3>; 884 fsl,usbmisc = <&usbmisc 3>;
885 dr_mode = "host";
866 status = "disabled"; 886 status = "disabled";
867 }; 887 };
868 888
@@ -1022,19 +1042,24 @@
1022 reg = <0x021e0000 0x4000>; 1042 reg = <0x021e0000 0x4000>;
1023 status = "disabled"; 1043 status = "disabled";
1024 1044
1025 port@0 { 1045 ports {
1026 reg = <0>; 1046 #address-cells = <1>;
1047 #size-cells = <0>;
1048
1049 port@0 {
1050 reg = <0>;
1027 1051
1028 mipi_mux_0: endpoint { 1052 mipi_mux_0: endpoint {
1029 remote-endpoint = <&ipu1_di0_mipi>; 1053 remote-endpoint = <&ipu1_di0_mipi>;
1054 };
1030 }; 1055 };
1031 };
1032 1056
1033 port@1 { 1057 port@1 {
1034 reg = <1>; 1058 reg = <1>;
1035 1059
1036 mipi_mux_1: endpoint { 1060 mipi_mux_1: endpoint {
1037 remote-endpoint = <&ipu1_di1_mipi>; 1061 remote-endpoint = <&ipu1_di1_mipi>;
1062 };
1038 }; 1063 };
1039 }; 1064 };
1040 }; 1065 };
diff --git a/arch/arm/boot/dts/imx6sl-warp.dts b/arch/arm/boot/dts/imx6sl-warp.dts
new file mode 100644
index 000000000000..64f7decf1fdc
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sl-warp.dts
@@ -0,0 +1,262 @@
1/*
2 * Copyright 2014, 2015 O.S. Systems Software LTDA.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48/dts-v1/;
49
50#include <dt-bindings/gpio/gpio.h>
51#include "imx6sl.dtsi"
52
53/ {
54 model = "WaRP Board";
55 compatible = "warp,imx6sl-warp", "fsl,imx6sl";
56
57 memory {
58 reg = <0x80000000 0x20000000>;
59 };
60
61 regulators {
62 compatible = "simple-bus";
63 #address-cells = <1>;
64 #size-cells = <0>;
65
66 reg_usb_otg1_vbus: regulator@0 {
67 compatible = "regulator-fixed";
68 reg = <0>;
69 regulator-name = "usb_otg1_vbus";
70 regulator-min-microvolt = <5000000>;
71 regulator-max-microvolt = <5000000>;
72 gpio = <&gpio4 0 0>;
73 enable-active-high;
74 };
75
76 reg_usb_otg2_vbus: regulator@1 {
77 compatible = "regulator-fixed";
78 reg = <1>;
79 regulator-name = "usb_otg2_vbus";
80 regulator-min-microvolt = <5000000>;
81 regulator-max-microvolt = <5000000>;
82 gpio = <&gpio4 2 0>;
83 enable-active-high;
84 };
85
86 reg_1p8v: regulator@2 {
87 compatible = "regulator-fixed";
88 reg = <2>;
89 regulator-name = "1P8V";
90 regulator-min-microvolt = <1800000>;
91 regulator-max-microvolt = <1800000>;
92 };
93 };
94
95 usdhc3_pwrseq: usdhc3_pwrseq {
96 compatible = "mmc-pwrseq-simple";
97 reset-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>, /* WL_REG_ON */
98 <&gpio3 25 GPIO_ACTIVE_LOW>, /* BT_REG_ON */
99 <&gpio4 4 GPIO_ACTIVE_LOW>, /* BT_WAKE */
100 <&gpio4 6 GPIO_ACTIVE_LOW>; /* BT_RST_N */
101 };
102};
103
104&uart1 {
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_uart1>;
107 status = "okay";
108};
109
110&uart2 {
111 pinctrl-names = "default";
112 pinctrl-0 = <&pinctrl_uart2>;
113 fsl,uart-has-rtscts;
114 status = "okay";
115};
116
117&uart3 {
118 pinctrl-names = "default";
119 pinctrl-0 = <&pinctrl_uart3>;
120 status = "okay";
121};
122
123&usbotg1 {
124 vbus-supply = <&reg_usb_otg1_vbus>;
125 dr_mode = "host";
126 disable-over-current;
127 status = "okay";
128};
129
130&usbotg2 {
131 vbus-supply = <&reg_usb_otg2_vbus>;
132 disable-over-current;
133 status = "okay";
134};
135
136&usdhc2 {
137 pinctrl-names = "default", "state_100mhz", "state_200mhz";
138 pinctrl-0 = <&pinctrl_usdhc2>;
139 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
140 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
141 bus-width = <8>;
142 non-removable;
143 status = "okay";
144};
145
146&usdhc3 {
147 pinctrl-names = "default", "state_100mhz", "state_200mhz";
148 pinctrl-0 = <&pinctrl_usdhc3>;
149 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
150 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
151 bus-width = <4>;
152 non-removable;
153 keep-power-in-suspend;
154 enable-sdio-wakeup;
155 mmc-pwrseq = <&usdhc3_pwrseq>;
156 status = "okay";
157};
158
159&iomuxc {
160 imx6sl-warp {
161 pinctrl_uart1: uart1grp {
162 fsl,pins = <
163 MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x41b0b1
164 MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x41b0b1
165 >;
166 };
167
168 pinctrl_uart2: uart2grp {
169 fsl,pins = <
170 MX6SL_PAD_EPDC_D12__UART2_RX_DATA 0x41b0b1
171 MX6SL_PAD_EPDC_D13__UART2_TX_DATA 0x41b0b1
172 MX6SL_PAD_EPDC_D14__UART2_RTS_B 0x4130B1
173 MX6SL_PAD_EPDC_D15__UART2_CTS_B 0x4130B1
174 >;
175 };
176
177 pinctrl_uart3: uart3grp {
178 fsl,pins = <
179 MX6SL_PAD_AUD_RXC__UART3_RX_DATA 0x41b0b1
180 MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x41b0b1
181 >;
182 };
183
184 pinctrl_usdhc2: usdhc2grp {
185 fsl,pins = <
186 MX6SL_PAD_SD2_CMD__SD2_CMD 0x417059
187 MX6SL_PAD_SD2_CLK__SD2_CLK 0x410059
188 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x417059
189 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x417059
190 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x417059
191 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x417059
192 MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x417059
193 MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x417059
194 MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x417059
195 MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x417059
196 >;
197 };
198
199 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
200 fsl,pins = <
201 MX6SL_PAD_SD2_CMD__SD2_CMD 0x4170b9
202 MX6SL_PAD_SD2_CLK__SD2_CLK 0x4100b9
203 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x4170b9
204 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x4170b9
205 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x4170b9
206 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x4170b9
207 MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x4170b9
208 MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170b9
209 MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170b9
210 MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170b9
211 >;
212 };
213
214 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
215 fsl,pins = <
216 MX6SL_PAD_SD2_CMD__SD2_CMD 0x4170f9
217 MX6SL_PAD_SD2_CLK__SD2_CLK 0x4100f9
218 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x4170f9
219 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x4170f9
220 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x4170f9
221 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x4170f9
222 MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x4170f9
223 MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170f9
224 MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170f9
225 MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170f9
226 >;
227 };
228
229 pinctrl_usdhc3: usdhc3grp {
230 fsl,pins = <
231 MX6SL_PAD_SD3_CMD__SD3_CMD 0x417059
232 MX6SL_PAD_SD3_CLK__SD3_CLK 0x410059
233 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x417059
234 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x417059
235 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x417059
236 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x417059
237 >;
238 };
239
240 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
241 fsl,pins = <
242 MX6SL_PAD_SD3_CMD__SD3_CMD 0x4170b9
243 MX6SL_PAD_SD3_CLK__SD3_CLK 0x4100b9
244 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x4170b9
245 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x4170b9
246 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x4170b9
247 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x4170b9
248 >;
249 };
250
251 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
252 fsl,pins = <
253 MX6SL_PAD_SD3_CMD__SD3_CMD 0x4170f9
254 MX6SL_PAD_SD3_CLK__SD3_CLK 0x4100f9
255 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x4170f9
256 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x4170f9
257 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x4170f9
258 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x4170f9
259 >;
260 };
261 };
262};
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 36ab8e054cee..a78e715e3982 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -72,6 +72,7 @@
72 interrupt-controller; 72 interrupt-controller;
73 reg = <0x00a01000 0x1000>, 73 reg = <0x00a01000 0x1000>,
74 <0x00a00100 0x100>; 74 <0x00a00100 0x100>;
75 interrupt-parent = <&intc>;
75 }; 76 };
76 77
77 clocks { 78 clocks {
@@ -95,7 +96,7 @@
95 #address-cells = <1>; 96 #address-cells = <1>;
96 #size-cells = <1>; 97 #size-cells = <1>;
97 compatible = "simple-bus"; 98 compatible = "simple-bus";
98 interrupt-parent = <&intc>; 99 interrupt-parent = <&gpc>;
99 ranges; 100 ranges;
100 101
101 ocram: sram@00900000 { 102 ocram: sram@00900000 {
@@ -568,7 +569,7 @@
568 #size-cells = <1>; 569 #size-cells = <1>;
569 ranges = <0 0x020cc000 0x4000>; 570 ranges = <0 0x020cc000 0x4000>;
570 571
571 snvs-rtc-lp@34 { 572 snvs_rtc: snvs-rtc-lp@34 {
572 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 573 compatible = "fsl,sec-v4.0-mon-rtc-lp";
573 reg = <0x34 0x58>; 574 reg = <0x34 0x58>;
574 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, 575 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
@@ -603,7 +604,14 @@
603 gpc: gpc@020dc000 { 604 gpc: gpc@020dc000 {
604 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc"; 605 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
605 reg = <0x020dc000 0x4000>; 606 reg = <0x020dc000 0x4000>;
607 interrupt-controller;
608 #interrupt-cells = <3>;
606 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; 609 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
610 interrupt-parent = <&intc>;
611 pu-supply = <&reg_pu>;
612 clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
613 <&clks IMX6SL_CLK_GPU2D_PODF>;
614 #power-domain-cells = <1>;
607 }; 615 };
608 616
609 gpr: iomuxc-gpr@020e0000 { 617 gpr: iomuxc-gpr@020e0000 {
@@ -699,6 +707,7 @@
699 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; 707 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
700 clocks = <&clks IMX6SL_CLK_USBOH3>; 708 clocks = <&clks IMX6SL_CLK_USBOH3>;
701 fsl,usbmisc = <&usbmisc 2>; 709 fsl,usbmisc = <&usbmisc 2>;
710 dr_mode = "host";
702 status = "disabled"; 711 status = "disabled";
703 }; 712 };
704 713
diff --git a/arch/arm/boot/dts/imx6sx-sdb-reva.dts b/arch/arm/boot/dts/imx6sx-sdb-reva.dts
new file mode 100644
index 000000000000..c76b87cba275
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sx-sdb-reva.dts
@@ -0,0 +1,143 @@
1/*
2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include "imx6sx-sdb.dtsi"
10
11/ {
12 model = "Freescale i.MX6 SoloX SDB RevA Board";
13};
14
15&i2c1 {
16 clock-frequency = <100000>;
17 pinctrl-names = "default";
18 pinctrl-0 = <&pinctrl_i2c1>;
19 status = "okay";
20
21 pmic: pfuze100@08 {
22 compatible = "fsl,pfuze100";
23 reg = <0x08>;
24
25 regulators {
26 sw1a_reg: sw1ab {
27 regulator-min-microvolt = <300000>;
28 regulator-max-microvolt = <1875000>;
29 regulator-boot-on;
30 regulator-always-on;
31 regulator-ramp-delay = <6250>;
32 };
33
34 sw1c_reg: sw1c {
35 regulator-min-microvolt = <300000>;
36 regulator-max-microvolt = <1875000>;
37 regulator-boot-on;
38 regulator-always-on;
39 regulator-ramp-delay = <6250>;
40 };
41
42 sw2_reg: sw2 {
43 regulator-min-microvolt = <800000>;
44 regulator-max-microvolt = <3300000>;
45 regulator-boot-on;
46 regulator-always-on;
47 };
48
49 sw3a_reg: sw3a {
50 regulator-min-microvolt = <400000>;
51 regulator-max-microvolt = <1975000>;
52 regulator-boot-on;
53 regulator-always-on;
54 };
55
56 sw3b_reg: sw3b {
57 regulator-min-microvolt = <400000>;
58 regulator-max-microvolt = <1975000>;
59 regulator-boot-on;
60 regulator-always-on;
61 };
62
63 sw4_reg: sw4 {
64 regulator-min-microvolt = <800000>;
65 regulator-max-microvolt = <3300000>;
66 };
67
68 swbst_reg: swbst {
69 regulator-min-microvolt = <5000000>;
70 regulator-max-microvolt = <5150000>;
71 };
72
73 snvs_reg: vsnvs {
74 regulator-min-microvolt = <1000000>;
75 regulator-max-microvolt = <3000000>;
76 regulator-boot-on;
77 regulator-always-on;
78 };
79
80 vref_reg: vrefddr {
81 regulator-boot-on;
82 regulator-always-on;
83 };
84
85 vgen1_reg: vgen1 {
86 regulator-min-microvolt = <800000>;
87 regulator-max-microvolt = <1550000>;
88 regulator-always-on;
89 };
90
91 vgen2_reg: vgen2 {
92 regulator-min-microvolt = <800000>;
93 regulator-max-microvolt = <1550000>;
94 };
95
96 vgen3_reg: vgen3 {
97 regulator-min-microvolt = <1800000>;
98 regulator-max-microvolt = <3300000>;
99 regulator-always-on;
100 };
101
102 vgen4_reg: vgen4 {
103 regulator-min-microvolt = <1800000>;
104 regulator-max-microvolt = <3300000>;
105 regulator-always-on;
106 };
107
108 vgen5_reg: vgen5 {
109 regulator-min-microvolt = <1800000>;
110 regulator-max-microvolt = <3300000>;
111 regulator-always-on;
112 };
113
114 vgen6_reg: vgen6 {
115 regulator-min-microvolt = <1800000>;
116 regulator-max-microvolt = <3300000>;
117 regulator-always-on;
118 };
119 };
120 };
121};
122
123&qspi2 {
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_qspi2>;
126 status = "okay";
127
128 flash0: s25fl128s@0 {
129 reg = <0>;
130 #address-cells = <1>;
131 #size-cells = <1>;
132 compatible = "spansion,s25fl128s";
133 spi-max-frequency = <66000000>;
134 };
135
136 flash1: s25fl128s@1 {
137 reg = <1>;
138 #address-cells = <1>;
139 #size-cells = <1>;
140 compatible = "spansion,s25fl128s";
141 spi-max-frequency = <66000000>;
142 };
143};
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts
index 32f07d6b4042..0bfc4e7865b2 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb.dts
@@ -1,197 +1,40 @@
1/* 1/*
2 * Copyright (C) 2014 Freescale Semiconductor, Inc. 2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 */ 7 */
8 8
9/dts-v1/; 9#include "imx6sx-sdb.dtsi"
10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/input/input.h>
13#include "imx6sx.dtsi"
14 10
15/ { 11/ {
16 model = "Freescale i.MX6 SoloX SDB Board"; 12 model = "Freescale i.MX6 SoloX SDB RevB Board";
17 compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
18
19 chosen {
20 stdout-path = &uart1;
21 };
22
23 memory {
24 reg = <0x80000000 0x40000000>;
25 };
26
27 backlight {
28 compatible = "pwm-backlight";
29 pwms = <&pwm3 0 5000000>;
30 brightness-levels = <0 4 8 16 32 64 128 255>;
31 default-brightness-level = <6>;
32 };
33
34 gpio-keys {
35 compatible = "gpio-keys";
36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_gpio_keys>;
38
39 volume-up {
40 label = "Volume Up";
41 gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
42 linux,code = <KEY_VOLUMEUP>;
43 };
44
45 volume-down {
46 label = "Volume Down";
47 gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
48 linux,code = <KEY_VOLUMEDOWN>;
49 };
50 };
51
52 regulators {
53 compatible = "simple-bus";
54 #address-cells = <1>;
55 #size-cells = <0>;
56
57 vcc_sd3: regulator@0 {
58 compatible = "regulator-fixed";
59 reg = <0>;
60 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_vcc_sd3>;
62 regulator-name = "VCC_SD3";
63 regulator-min-microvolt = <3000000>;
64 regulator-max-microvolt = <3000000>;
65 gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
66 enable-active-high;
67 };
68
69 reg_usb_otg1_vbus: regulator@1 {
70 compatible = "regulator-fixed";
71 reg = <1>;
72 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_usb_otg1>;
74 regulator-name = "usb_otg1_vbus";
75 regulator-min-microvolt = <5000000>;
76 regulator-max-microvolt = <5000000>;
77 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
78 enable-active-high;
79 };
80
81 reg_usb_otg2_vbus: regulator@2 {
82 compatible = "regulator-fixed";
83 reg = <2>;
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_usb_otg2>;
86 regulator-name = "usb_otg2_vbus";
87 regulator-min-microvolt = <5000000>;
88 regulator-max-microvolt = <5000000>;
89 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
90 enable-active-high;
91 };
92
93 reg_psu_5v: regulator@3 {
94 compatible = "regulator-fixed";
95 reg = <3>;
96 regulator-name = "PSU-5V0";
97 regulator-min-microvolt = <5000000>;
98 regulator-max-microvolt = <5000000>;
99 };
100
101 reg_lcd_3v3: regulator@4 {
102 compatible = "regulator-fixed";
103 reg = <4>;
104 regulator-name = "lcd-3v3";
105 gpio = <&gpio3 27 0>;
106 enable-active-high;
107 };
108
109 reg_peri_3v3: regulator@5 {
110 compatible = "regulator-fixed";
111 reg = <5>;
112 pinctrl-names = "default";
113 pinctrl-0 = <&pinctrl_peri_3v3>;
114 regulator-name = "peri_3v3";
115 regulator-min-microvolt = <3300000>;
116 regulator-max-microvolt = <3300000>;
117 gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
118 enable-active-high;
119 regulator-always-on;
120 };
121
122 reg_enet_3v3: regulator@6 {
123 compatible = "regulator-fixed";
124 reg = <6>;
125 pinctrl-names = "default";
126 pinctrl-0 = <&pinctrl_enet_3v3>;
127 regulator-name = "enet_3v3";
128 regulator-min-microvolt = <3300000>;
129 regulator-max-microvolt = <3300000>;
130 gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
131 };
132 };
133
134 sound {
135 compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962";
136 model = "wm8962-audio";
137 ssi-controller = <&ssi2>;
138 audio-codec = <&codec>;
139 audio-routing =
140 "Headphone Jack", "HPOUTL",
141 "Headphone Jack", "HPOUTR",
142 "Ext Spk", "SPKOUTL",
143 "Ext Spk", "SPKOUTR",
144 "AMIC", "MICBIAS",
145 "IN3R", "AMIC";
146 mux-int-port = <2>;
147 mux-ext-port = <6>;
148 };
149};
150
151&audmux {
152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_audmux>;
154 status = "okay";
155}; 13};
156 14
157&fec1 { 15&cpu0 {
158 pinctrl-names = "default"; 16 operating-points = <
159 pinctrl-0 = <&pinctrl_enet1>; 17 /* kHz uV */
160 phy-supply = <&reg_enet_3v3>; 18 996000 1250000
161 phy-mode = "rgmii"; 19 792000 1175000
162 phy-handle = <&ethphy1>; 20 396000 1175000
163 status = "okay"; 21 >;
164 22 fsl,soc-operating-points = <
165 mdio { 23 /* ARM kHz SOC uV */
166 #address-cells = <1>; 24 996000 1250000
167 #size-cells = <0>; 25 792000 1175000
168 26 396000 1175000
169 ethphy1: ethernet-phy@1 { 27 >;
170 reg = <1>;
171 };
172
173 ethphy2: ethernet-phy@2 {
174 reg = <2>;
175 };
176 };
177}; 28};
178 29
179&fec2 { 30&i2c1 {
31 clock-frequency = <100000>;
180 pinctrl-names = "default"; 32 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_enet2>; 33 pinctrl-0 = <&pinctrl_i2c1>;
182 phy-mode = "rgmii";
183 phy-handle = <&ethphy2>;
184 status = "okay"; 34 status = "okay";
185};
186
187&i2c1 {
188 clock-frequency = <100000>;
189 pinctrl-names = "default";
190 pinctrl-0 = <&pinctrl_i2c1>;
191 status = "okay";
192 35
193 pmic: pfuze100@08 { 36 pmic: pfuze100@08 {
194 compatible = "fsl,pfuze100"; 37 compatible = "fsl,pfuze200";
195 reg = <0x08>; 38 reg = <0x08>;
196 39
197 regulators { 40 regulators {
@@ -203,14 +46,6 @@
203 regulator-ramp-delay = <6250>; 46 regulator-ramp-delay = <6250>;
204 }; 47 };
205 48
206 sw1c_reg: sw1c {
207 regulator-min-microvolt = <300000>;
208 regulator-max-microvolt = <1875000>;
209 regulator-boot-on;
210 regulator-always-on;
211 regulator-ramp-delay = <6250>;
212 };
213
214 sw2_reg: sw2 { 49 sw2_reg: sw2 {
215 regulator-min-microvolt = <800000>; 50 regulator-min-microvolt = <800000>;
216 regulator-max-microvolt = <3300000>; 51 regulator-max-microvolt = <3300000>;
@@ -232,11 +67,6 @@
232 regulator-always-on; 67 regulator-always-on;
233 }; 68 };
234 69
235 sw4_reg: sw4 {
236 regulator-min-microvolt = <800000>;
237 regulator-max-microvolt = <3300000>;
238 };
239
240 swbst_reg: swbst { 70 swbst_reg: swbst {
241 regulator-min-microvolt = <5000000>; 71 regulator-min-microvolt = <5000000>;
242 regulator-max-microvolt = <5150000>; 72 regulator-max-microvolt = <5150000>;
@@ -292,401 +122,24 @@
292 }; 122 };
293}; 123};
294 124
295&i2c4 {
296 clock-frequency = <100000>;
297 pinctrl-names = "default";
298 pinctrl-0 = <&pinctrl_i2c4>;
299 status = "okay";
300
301 codec: wm8962@1a {
302 compatible = "wlf,wm8962";
303 reg = <0x1a>;
304 clocks = <&clks IMX6SX_CLK_AUDIO>;
305 DCVDD-supply = <&vgen4_reg>;
306 DBVDD-supply = <&vgen4_reg>;
307 AVDD-supply = <&vgen4_reg>;
308 CPVDD-supply = <&vgen4_reg>;
309 MICVDD-supply = <&vgen3_reg>;
310 PLLVDD-supply = <&vgen4_reg>;
311 SPKVDD1-supply = <&reg_psu_5v>;
312 SPKVDD2-supply = <&reg_psu_5v>;
313 };
314};
315
316&lcdif1 {
317 pinctrl-names = "default";
318 pinctrl-0 = <&pinctrl_lcd>;
319 lcd-supply = <&reg_lcd_3v3>;
320 display = <&display0>;
321 status = "okay";
322
323 display0: display0 {
324 bits-per-pixel = <16>;
325 bus-width = <24>;
326
327 display-timings {
328 native-mode = <&timing0>;
329 timing0: timing0 {
330 clock-frequency = <33500000>;
331 hactive = <800>;
332 vactive = <480>;
333 hback-porch = <89>;
334 hfront-porch = <164>;
335 vback-porch = <23>;
336 vfront-porch = <10>;
337 hsync-len = <10>;
338 vsync-len = <10>;
339 hsync-active = <0>;
340 vsync-active = <0>;
341 de-active = <1>;
342 pixelclk-active = <0>;
343 };
344 };
345 };
346};
347
348&pwm3 {
349 pinctrl-names = "default";
350 pinctrl-0 = <&pinctrl_pwm3>;
351 status = "okay";
352};
353
354&snvs_poweroff {
355 status = "okay";
356};
357
358&qspi2 { 125&qspi2 {
359 pinctrl-names = "default"; 126 pinctrl-names = "default";
360 pinctrl-0 = <&pinctrl_qspi2>; 127 pinctrl-0 = <&pinctrl_qspi2>;
361 status = "okay"; 128 status = "okay";
362 129
363 flash0: s25fl128s@0 { 130 flash0: n25q256a@0 {
364 reg = <0>;
365 #address-cells = <1>; 131 #address-cells = <1>;
366 #size-cells = <1>; 132 #size-cells = <1>;
367 compatible = "spansion,s25fl128s"; 133 compatible = "micron,n25q256a";
368 spi-max-frequency = <66000000>; 134 spi-max-frequency = <29000000>;
135 reg = <0>;
369 }; 136 };
370 137
371 flash1: s25fl128s@1 { 138 flash1: n25q256a@1 {
372 reg = <1>;
373 #address-cells = <1>; 139 #address-cells = <1>;
374 #size-cells = <1>; 140 #size-cells = <1>;
375 compatible = "spansion,s25fl128s"; 141 compatible = "micron,n25q256a";
376 spi-max-frequency = <66000000>; 142 spi-max-frequency = <29000000>;
377 }; 143 reg = <1>;
378};
379
380&ssi2 {
381 status = "okay";
382};
383
384&uart1 {
385 pinctrl-names = "default";
386 pinctrl-0 = <&pinctrl_uart1>;
387 status = "okay";
388};
389
390&uart5 { /* for bluetooth */
391 pinctrl-names = "default";
392 pinctrl-0 = <&pinctrl_uart5>;
393 fsl,uart-has-rtscts;
394 status = "okay";
395};
396
397&usbotg1 {
398 vbus-supply = <&reg_usb_otg1_vbus>;
399 pinctrl-names = "default";
400 pinctrl-0 = <&pinctrl_usb_otg1_id>;
401 status = "okay";
402};
403
404&usbotg2 {
405 vbus-supply = <&reg_usb_otg2_vbus>;
406 dr_mode = "host";
407 status = "okay";
408};
409
410&usdhc2 {
411 pinctrl-names = "default";
412 pinctrl-0 = <&pinctrl_usdhc2>;
413 non-removable;
414 no-1-8-v;
415 keep-power-in-suspend;
416 enable-sdio-wakeup;
417 status = "okay";
418};
419
420&usdhc3 {
421 pinctrl-names = "default", "state_100mhz", "state_200mhz";
422 pinctrl-0 = <&pinctrl_usdhc3>;
423 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
424 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
425 bus-width = <8>;
426 cd-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
427 wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
428 keep-power-in-suspend;
429 enable-sdio-wakeup;
430 vmmc-supply = <&vcc_sd3>;
431 status = "okay";
432};
433
434&usdhc4 {
435 pinctrl-names = "default";
436 pinctrl-0 = <&pinctrl_usdhc4>;
437 cd-gpios = <&gpio6 21 GPIO_ACTIVE_HIGH>;
438 wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
439 status = "okay";
440};
441
442&iomuxc {
443 imx6x-sdb {
444 pinctrl_audmux: audmuxgrp {
445 fsl,pins = <
446 MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0
447 MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130b0
448 MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120b0
449 MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130b0
450 MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0
451 >;
452 };
453
454 pinctrl_enet1: enet1grp {
455 fsl,pins = <
456 MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
457 MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
458 MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1
459 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
460 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
461 MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
462 MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
463 MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
464 MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
465 MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
466 MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
467 MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
468 MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
469 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
470 MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91
471 >;
472 };
473
474 pinctrl_enet_3v3: enet3v3grp {
475 fsl,pins = <
476 MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x80000000
477 >;
478 };
479
480 pinctrl_enet2: enet2grp {
481 fsl,pins = <
482 MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9
483 MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
484 MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1
485 MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1
486 MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1
487 MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1
488 MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
489 MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
490 MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
491 MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
492 MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
493 MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
494 >;
495 };
496
497 pinctrl_gpio_keys: gpio_keysgrp {
498 fsl,pins = <
499 MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
500 MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
501 >;
502 };
503
504 pinctrl_i2c1: i2c1grp {
505 fsl,pins = <
506 MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
507 MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
508 >;
509 };
510
511 pinctrl_i2c4: i2c4grp {
512 fsl,pins = <
513 MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1
514 MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1
515 >;
516 };
517
518 pinctrl_lcd: lcdgrp {
519 fsl,pins = <
520 MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
521 MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
522 MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
523 MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
524 MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
525 MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
526 MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
527 MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
528 MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
529 MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
530 MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
531 MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
532 MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
533 MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
534 MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
535 MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
536 MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
537 MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
538 MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
539 MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
540 MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
541 MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
542 MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
543 MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
544 MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0
545 MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
546 MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
547 MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
548 MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
549 >;
550 };
551
552 pinctrl_peri_3v3: peri3v3grp {
553 fsl,pins = <
554 MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000
555 >;
556 };
557
558 pinctrl_pwm3: pwm3grp-1 {
559 fsl,pins = <
560 MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
561 >;
562 };
563
564 pinctrl_qspi2: qspi2grp {
565 fsl,pins = <
566 MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1
567 MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70f1
568 MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70f1
569 MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70f1
570 MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70f1
571 MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70f1
572 MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70f1
573 MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70f1
574 MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70f1
575 MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70f1
576 MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70f1
577 MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70f1
578 >;
579 };
580
581 pinctrl_vcc_sd3: vccsd3grp {
582 fsl,pins = <
583 MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
584 >;
585 };
586
587 pinctrl_uart1: uart1grp {
588 fsl,pins = <
589 MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
590 MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
591 >;
592 };
593
594 pinctrl_uart5: uart5grp {
595 fsl,pins = <
596 MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1
597 MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1
598 MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1
599 MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1
600 >;
601 };
602
603 pinctrl_usb_otg1: usbotg1grp {
604 fsl,pins = <
605 MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0
606 >;
607 };
608
609 pinctrl_usb_otg1_id: usbotg1idgrp {
610 fsl,pins = <
611 MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059
612 >;
613 };
614
615 pinctrl_usb_otg2: usbot2ggrp {
616 fsl,pins = <
617 MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x10b0
618 >;
619 };
620
621 pinctrl_usdhc2: usdhc2grp {
622 fsl,pins = <
623 MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059
624 MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059
625 MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
626 MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
627 MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
628 MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
629 >;
630 };
631
632 pinctrl_usdhc3: usdhc3grp {
633 fsl,pins = <
634 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
635 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
636 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
637 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
638 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
639 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
640 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
641 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
642 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
643 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
644 MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
645 MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
646 >;
647 };
648
649 pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
650 fsl,pins = <
651 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
652 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
653 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
654 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
655 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
656 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
657 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
658 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
659 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
660 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
661 >;
662 };
663
664 pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
665 fsl,pins = <
666 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
667 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
668 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
669 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
670 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
671 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
672 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
673 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
674 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
675 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
676 >;
677 };
678
679 pinctrl_usdhc4: usdhc4grp {
680 fsl,pins = <
681 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
682 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
683 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
684 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
685 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
686 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
687 MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
688 MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
689 >;
690 };
691 }; 144 };
692}; 145};
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi
new file mode 100644
index 000000000000..cef04cef3a80
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi
@@ -0,0 +1,562 @@
1/*
2 * Copyright (C) 2014 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/dts-v1/;
10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/input/input.h>
13#include "imx6sx.dtsi"
14
15/ {
16 model = "Freescale i.MX6 SoloX SDB Board";
17 compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
18
19 chosen {
20 stdout-path = &uart1;
21 };
22
23 memory {
24 reg = <0x80000000 0x40000000>;
25 };
26
27 backlight {
28 compatible = "pwm-backlight";
29 pwms = <&pwm3 0 5000000>;
30 brightness-levels = <0 4 8 16 32 64 128 255>;
31 default-brightness-level = <6>;
32 };
33
34 gpio-keys {
35 compatible = "gpio-keys";
36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_gpio_keys>;
38
39 volume-up {
40 label = "Volume Up";
41 gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
42 linux,code = <KEY_VOLUMEUP>;
43 };
44
45 volume-down {
46 label = "Volume Down";
47 gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
48 linux,code = <KEY_VOLUMEDOWN>;
49 };
50 };
51
52 regulators {
53 compatible = "simple-bus";
54 #address-cells = <1>;
55 #size-cells = <0>;
56
57 vcc_sd3: regulator@0 {
58 compatible = "regulator-fixed";
59 reg = <0>;
60 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_vcc_sd3>;
62 regulator-name = "VCC_SD3";
63 regulator-min-microvolt = <3000000>;
64 regulator-max-microvolt = <3000000>;
65 gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
66 enable-active-high;
67 };
68
69 reg_usb_otg1_vbus: regulator@1 {
70 compatible = "regulator-fixed";
71 reg = <1>;
72 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_usb_otg1>;
74 regulator-name = "usb_otg1_vbus";
75 regulator-min-microvolt = <5000000>;
76 regulator-max-microvolt = <5000000>;
77 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
78 enable-active-high;
79 };
80
81 reg_usb_otg2_vbus: regulator@2 {
82 compatible = "regulator-fixed";
83 reg = <2>;
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_usb_otg2>;
86 regulator-name = "usb_otg2_vbus";
87 regulator-min-microvolt = <5000000>;
88 regulator-max-microvolt = <5000000>;
89 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
90 enable-active-high;
91 };
92
93 reg_psu_5v: regulator@3 {
94 compatible = "regulator-fixed";
95 reg = <3>;
96 regulator-name = "PSU-5V0";
97 regulator-min-microvolt = <5000000>;
98 regulator-max-microvolt = <5000000>;
99 };
100
101 reg_lcd_3v3: regulator@4 {
102 compatible = "regulator-fixed";
103 reg = <4>;
104 regulator-name = "lcd-3v3";
105 gpio = <&gpio3 27 0>;
106 enable-active-high;
107 };
108
109 reg_peri_3v3: regulator@5 {
110 compatible = "regulator-fixed";
111 reg = <5>;
112 pinctrl-names = "default";
113 pinctrl-0 = <&pinctrl_peri_3v3>;
114 regulator-name = "peri_3v3";
115 regulator-min-microvolt = <3300000>;
116 regulator-max-microvolt = <3300000>;
117 gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
118 enable-active-high;
119 regulator-always-on;
120 };
121
122 reg_enet_3v3: regulator@6 {
123 compatible = "regulator-fixed";
124 reg = <6>;
125 pinctrl-names = "default";
126 pinctrl-0 = <&pinctrl_enet_3v3>;
127 regulator-name = "enet_3v3";
128 regulator-min-microvolt = <3300000>;
129 regulator-max-microvolt = <3300000>;
130 gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
131 };
132 };
133
134 sound {
135 compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962";
136 model = "wm8962-audio";
137 ssi-controller = <&ssi2>;
138 audio-codec = <&codec>;
139 audio-routing =
140 "Headphone Jack", "HPOUTL",
141 "Headphone Jack", "HPOUTR",
142 "Ext Spk", "SPKOUTL",
143 "Ext Spk", "SPKOUTR",
144 "AMIC", "MICBIAS",
145 "IN3R", "AMIC";
146 mux-int-port = <2>;
147 mux-ext-port = <6>;
148 };
149};
150
151&audmux {
152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_audmux>;
154 status = "okay";
155};
156
157&fec1 {
158 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_enet1>;
160 phy-supply = <&reg_enet_3v3>;
161 phy-mode = "rgmii";
162 phy-handle = <&ethphy1>;
163 status = "okay";
164
165 mdio {
166 #address-cells = <1>;
167 #size-cells = <0>;
168
169 ethphy1: ethernet-phy@1 {
170 reg = <1>;
171 };
172
173 ethphy2: ethernet-phy@2 {
174 reg = <2>;
175 };
176 };
177};
178
179&fec2 {
180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_enet2>;
182 phy-mode = "rgmii";
183 phy-handle = <&ethphy2>;
184 status = "okay";
185};
186
187&i2c4 {
188 clock-frequency = <100000>;
189 pinctrl-names = "default";
190 pinctrl-0 = <&pinctrl_i2c4>;
191 status = "okay";
192
193 codec: wm8962@1a {
194 compatible = "wlf,wm8962";
195 reg = <0x1a>;
196 clocks = <&clks IMX6SX_CLK_AUDIO>;
197 DCVDD-supply = <&vgen4_reg>;
198 DBVDD-supply = <&vgen4_reg>;
199 AVDD-supply = <&vgen4_reg>;
200 CPVDD-supply = <&vgen4_reg>;
201 MICVDD-supply = <&vgen3_reg>;
202 PLLVDD-supply = <&vgen4_reg>;
203 SPKVDD1-supply = <&reg_psu_5v>;
204 SPKVDD2-supply = <&reg_psu_5v>;
205 };
206};
207
208&lcdif1 {
209 pinctrl-names = "default";
210 pinctrl-0 = <&pinctrl_lcd>;
211 lcd-supply = <&reg_lcd_3v3>;
212 display = <&display0>;
213 status = "okay";
214
215 display0: display0 {
216 bits-per-pixel = <16>;
217 bus-width = <24>;
218
219 display-timings {
220 native-mode = <&timing0>;
221 timing0: timing0 {
222 clock-frequency = <33500000>;
223 hactive = <800>;
224 vactive = <480>;
225 hback-porch = <89>;
226 hfront-porch = <164>;
227 vback-porch = <23>;
228 vfront-porch = <10>;
229 hsync-len = <10>;
230 vsync-len = <10>;
231 hsync-active = <0>;
232 vsync-active = <0>;
233 de-active = <1>;
234 pixelclk-active = <0>;
235 };
236 };
237 };
238};
239
240&pwm3 {
241 pinctrl-names = "default";
242 pinctrl-0 = <&pinctrl_pwm3>;
243 status = "okay";
244};
245
246&snvs_poweroff {
247 status = "okay";
248};
249
250&ssi2 {
251 status = "okay";
252};
253
254&uart1 {
255 pinctrl-names = "default";
256 pinctrl-0 = <&pinctrl_uart1>;
257 status = "okay";
258};
259
260&uart5 { /* for bluetooth */
261 pinctrl-names = "default";
262 pinctrl-0 = <&pinctrl_uart5>;
263 fsl,uart-has-rtscts;
264 status = "okay";
265};
266
267&usbotg1 {
268 vbus-supply = <&reg_usb_otg1_vbus>;
269 pinctrl-names = "default";
270 pinctrl-0 = <&pinctrl_usb_otg1_id>;
271 status = "okay";
272};
273
274&usbotg2 {
275 vbus-supply = <&reg_usb_otg2_vbus>;
276 dr_mode = "host";
277 status = "okay";
278};
279
280&usdhc2 {
281 pinctrl-names = "default";
282 pinctrl-0 = <&pinctrl_usdhc2>;
283 non-removable;
284 no-1-8-v;
285 keep-power-in-suspend;
286 enable-sdio-wakeup;
287 status = "okay";
288};
289
290&usdhc3 {
291 pinctrl-names = "default", "state_100mhz", "state_200mhz";
292 pinctrl-0 = <&pinctrl_usdhc3>;
293 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
294 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
295 bus-width = <8>;
296 cd-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
297 wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
298 keep-power-in-suspend;
299 enable-sdio-wakeup;
300 vmmc-supply = <&vcc_sd3>;
301 status = "okay";
302};
303
304&usdhc4 {
305 pinctrl-names = "default";
306 pinctrl-0 = <&pinctrl_usdhc4>;
307 cd-gpios = <&gpio6 21 GPIO_ACTIVE_HIGH>;
308 wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
309 status = "okay";
310};
311
312&iomuxc {
313 imx6x-sdb {
314 pinctrl_audmux: audmuxgrp {
315 fsl,pins = <
316 MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0
317 MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130b0
318 MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120b0
319 MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130b0
320 MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0
321 >;
322 };
323
324 pinctrl_enet1: enet1grp {
325 fsl,pins = <
326 MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
327 MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
328 MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1
329 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
330 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
331 MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
332 MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
333 MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
334 MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
335 MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
336 MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
337 MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
338 MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
339 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
340 MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91
341 >;
342 };
343
344 pinctrl_enet_3v3: enet3v3grp {
345 fsl,pins = <
346 MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x80000000
347 >;
348 };
349
350 pinctrl_enet2: enet2grp {
351 fsl,pins = <
352 MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9
353 MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
354 MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1
355 MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1
356 MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1
357 MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1
358 MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
359 MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
360 MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
361 MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
362 MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
363 MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
364 >;
365 };
366
367 pinctrl_gpio_keys: gpio_keysgrp {
368 fsl,pins = <
369 MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
370 MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
371 >;
372 };
373
374 pinctrl_i2c1: i2c1grp {
375 fsl,pins = <
376 MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
377 MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
378 >;
379 };
380
381 pinctrl_i2c4: i2c4grp {
382 fsl,pins = <
383 MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1
384 MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1
385 >;
386 };
387
388 pinctrl_lcd: lcdgrp {
389 fsl,pins = <
390 MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
391 MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
392 MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
393 MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
394 MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
395 MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
396 MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
397 MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
398 MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
399 MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
400 MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
401 MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
402 MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
403 MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
404 MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
405 MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
406 MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
407 MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
408 MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
409 MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
410 MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
411 MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
412 MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
413 MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
414 MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0
415 MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
416 MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
417 MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
418 MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
419 >;
420 };
421
422 pinctrl_peri_3v3: peri3v3grp {
423 fsl,pins = <
424 MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000
425 >;
426 };
427
428 pinctrl_pwm3: pwm3grp-1 {
429 fsl,pins = <
430 MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
431 >;
432 };
433
434 pinctrl_qspi2: qspi2grp {
435 fsl,pins = <
436 MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1
437 MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70f1
438 MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70f1
439 MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70f1
440 MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70f1
441 MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70f1
442 MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70f1
443 MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70f1
444 MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70f1
445 MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70f1
446 MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70f1
447 MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70f1
448 >;
449 };
450
451 pinctrl_vcc_sd3: vccsd3grp {
452 fsl,pins = <
453 MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
454 >;
455 };
456
457 pinctrl_uart1: uart1grp {
458 fsl,pins = <
459 MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
460 MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
461 >;
462 };
463
464 pinctrl_uart5: uart5grp {
465 fsl,pins = <
466 MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1
467 MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1
468 MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1
469 MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1
470 >;
471 };
472
473 pinctrl_usb_otg1: usbotg1grp {
474 fsl,pins = <
475 MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0
476 >;
477 };
478
479 pinctrl_usb_otg1_id: usbotg1idgrp {
480 fsl,pins = <
481 MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059
482 >;
483 };
484
485 pinctrl_usb_otg2: usbot2ggrp {
486 fsl,pins = <
487 MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x10b0
488 >;
489 };
490
491 pinctrl_usdhc2: usdhc2grp {
492 fsl,pins = <
493 MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059
494 MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059
495 MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
496 MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
497 MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
498 MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
499 >;
500 };
501
502 pinctrl_usdhc3: usdhc3grp {
503 fsl,pins = <
504 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
505 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
506 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
507 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
508 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
509 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
510 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
511 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
512 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
513 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
514 MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
515 MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
516 >;
517 };
518
519 pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
520 fsl,pins = <
521 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
522 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
523 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
524 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
525 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
526 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
527 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
528 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
529 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
530 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
531 >;
532 };
533
534 pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
535 fsl,pins = <
536 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
537 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
538 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
539 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
540 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
541 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
542 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
543 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
544 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
545 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
546 >;
547 };
548
549 pinctrl_usdhc4: usdhc4grp {
550 fsl,pins = <
551 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
552 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
553 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
554 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
555 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
556 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
557 MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
558 MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
559 >;
560 };
561 };
562};
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 7a24fee1e7ae..708175d59b9c 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -88,6 +88,7 @@
88 interrupt-controller; 88 interrupt-controller;
89 reg = <0x00a01000 0x1000>, 89 reg = <0x00a01000 0x1000>,
90 <0x00a00100 0x100>; 90 <0x00a00100 0x100>;
91 interrupt-parent = <&intc>;
91 }; 92 };
92 93
93 clocks { 94 clocks {
@@ -131,7 +132,7 @@
131 #address-cells = <1>; 132 #address-cells = <1>;
132 #size-cells = <1>; 133 #size-cells = <1>;
133 compatible = "simple-bus"; 134 compatible = "simple-bus";
134 interrupt-parent = <&intc>; 135 interrupt-parent = <&gpc>;
135 ranges; 136 ranges;
136 137
137 pmu { 138 pmu {
@@ -666,7 +667,7 @@
666 #size-cells = <1>; 667 #size-cells = <1>;
667 ranges = <0 0x020cc000 0x4000>; 668 ranges = <0 0x020cc000 0x4000>;
668 669
669 snvs-rtc-lp@34 { 670 snvs_rtc: snvs-rtc-lp@34 {
670 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 671 compatible = "fsl,sec-v4.0-mon-rtc-lp";
671 reg = <0x34 0x58>; 672 reg = <0x34 0x58>;
672 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 673 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
@@ -700,7 +701,10 @@
700 gpc: gpc@020dc000 { 701 gpc: gpc@020dc000 {
701 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc"; 702 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
702 reg = <0x020dc000 0x4000>; 703 reg = <0x020dc000 0x4000>;
704 interrupt-controller;
705 #interrupt-cells = <3>;
703 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 706 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
707 interrupt-parent = <&intc>;
704 }; 708 };
705 709
706 iomuxc: iomuxc@020e0000 { 710 iomuxc: iomuxc@020e0000 {
@@ -763,6 +767,7 @@
763 fsl,usbmisc = <&usbmisc 2>; 767 fsl,usbmisc = <&usbmisc 2>;
764 phy_type = "hsic"; 768 phy_type = "hsic";
765 fsl,anatop = <&anatop>; 769 fsl,anatop = <&anatop>;
770 dr_mode = "host";
766 status = "disabled"; 771 status = "disabled";
767 }; 772 };
768 773
diff --git a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
index 36cafbfa1bfa..606753eb72c8 100644
--- a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
@@ -12,6 +12,12 @@
12 bootargs = "console=ttyLP0,115200"; 12 bootargs = "console=ttyLP0,115200";
13 }; 13 };
14 14
15 clk16m: clk16m {
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
18 clock-frequency = <16000000>;
19 };
20
15 regulators { 21 regulators {
16 compatible = "simple-bus"; 22 compatible = "simple-bus";
17 #address-cells = <1>; 23 #address-cells = <1>;
@@ -47,6 +53,21 @@
47 status = "okay"; 53 status = "okay";
48}; 54};
49 55
56&dspi1 {
57 status = "okay";
58
59 mcp2515can: can@0 {
60 compatible = "microchip,mcp2515";
61 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_can_int>;
63 reg = <0>;
64 clocks = <&clk16m>;
65 spi-max-frequency = <10000000>;
66 interrupt-parent = <&gpio1>;
67 interrupts = <11 GPIO_ACTIVE_LOW>;
68 };
69};
70
50&esdhc1 { 71&esdhc1 {
51 pinctrl-names = "default"; 72 pinctrl-names = "default";
52 pinctrl-0 = <&pinctrl_esdhc1>; 73 pinctrl-0 = <&pinctrl_esdhc1>;
@@ -94,3 +115,13 @@
94&usbh1 { 115&usbh1 {
95 vbus-supply = <&usbh_vbus_reg>; 116 vbus-supply = <&usbh_vbus_reg>;
96}; 117};
118
119&iomuxc {
120 vf610-colibri {
121 pinctrl_can_int: can_int {
122 fsl,pins = <
123 VF610_PAD_PTB21__GPIO_43 0x22ed
124 >;
125 };
126 };
127};
diff --git a/arch/arm/boot/dts/vf-colibri.dtsi b/arch/arm/boot/dts/vf-colibri.dtsi
index 5c2b7320856d..fbef0828e930 100644
--- a/arch/arm/boot/dts/vf-colibri.dtsi
+++ b/arch/arm/boot/dts/vf-colibri.dtsi
@@ -23,6 +23,12 @@
23 status = "okay"; 23 status = "okay";
24}; 24};
25 25
26&dspi1 {
27 bus-num = <1>;
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_dspi1>;
30};
31
26&edma0 { 32&edma0 {
27 status = "okay"; 33 status = "okay";
28}; 34};
@@ -107,6 +113,15 @@
107 >; 113 >;
108 }; 114 };
109 115
116 pinctrl_dspi1: dspi1grp {
117 fsl,pins = <
118 VF610_PAD_PTD5__DSPI1_CS0 0x33e2
119 VF610_PAD_PTD6__DSPI1_SIN 0x33e1
120 VF610_PAD_PTD7__DSPI1_SOUT 0x33e2
121 VF610_PAD_PTD8__DSPI1_SCK 0x33e2
122 >;
123 };
124
110 pinctrl_esdhc1: esdhc1grp { 125 pinctrl_esdhc1: esdhc1grp {
111 fsl,pins = < 126 fsl,pins = <
112 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef 127 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi
index 1dbf8d2d1ddf..e976d2fa1527 100644
--- a/arch/arm/boot/dts/vf500.dtsi
+++ b/arch/arm/boot/dts/vf500.dtsi
@@ -24,14 +24,13 @@
24 }; 24 };
25 25
26 soc { 26 soc {
27 interrupt-parent = <&intc>;
28
29 aips-bus@40000000 { 27 aips-bus@40000000 {
30 28
31 intc: interrupt-controller@40002000 { 29 intc: interrupt-controller@40002000 {
32 compatible = "arm,cortex-a9-gic"; 30 compatible = "arm,cortex-a9-gic";
33 #interrupt-cells = <3>; 31 #interrupt-cells = <3>;
34 interrupt-controller; 32 interrupt-controller;
33 interrupt-parent = <&intc>;
35 reg = <0x40003000 0x1000>, 34 reg = <0x40003000 0x1000>,
36 <0x40002100 0x100>; 35 <0x40002100 0x100>;
37 }; 36 };
@@ -40,145 +39,17 @@
40 compatible = "arm,cortex-a9-global-timer"; 39 compatible = "arm,cortex-a9-global-timer";
41 reg = <0x40002200 0x20>; 40 reg = <0x40002200 0x20>;
42 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; 41 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
42 interrupt-parent = <&intc>;
43 clocks = <&clks VF610_CLK_PLATFORM_BUS>; 43 clocks = <&clks VF610_CLK_PLATFORM_BUS>;
44 }; 44 };
45 }; 45 };
46 }; 46 };
47}; 47};
48 48
49&adc0 { 49&mscm_ir {
50 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 50 interrupt-parent = <&intc>;
51};
52
53&adc1 {
54 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
55};
56
57&can0 {
58 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
59};
60
61&can1 {
62 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
63};
64
65&dspi0 {
66 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
67};
68
69&edma0 {
70 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
71 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
72 interrupt-names = "edma-tx", "edma-err";
73};
74
75&edma1 {
76 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
77 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
78 interrupt-names = "edma-tx", "edma-err";
79};
80
81&esdhc1 {
82 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
83};
84
85&fec0 {
86 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
87};
88
89&fec1 {
90 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
91};
92
93&ftm {
94 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
95};
96
97&gpio0 {
98 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
99};
100
101&gpio1 {
102 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
103};
104
105&gpio2 {
106 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
107};
108
109&gpio3 {
110 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
111};
112
113&gpio4 {
114 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
115};
116
117&i2c0 {
118 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
119};
120
121&pit {
122 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
123};
124
125&qspi0 {
126 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
127};
128
129&sai2 {
130 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
131};
132
133&snvsrtc {
134 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
135};
136
137&src {
138 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
139};
140
141&uart0 {
142 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
143};
144
145&uart1 {
146 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
147};
148
149&uart2 {
150 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
151};
152
153&uart3 {
154 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
155};
156
157&uart4 {
158 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
159};
160
161&uart5 {
162 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
163};
164
165&usbdev0 {
166 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
167};
168
169&usbh1 {
170 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
171};
172
173&usbphy0 {
174 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
175};
176
177&usbphy1 {
178 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
179}; 51};
180 52
181&wdoga5 { 53&wdoga5 {
182 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
183 status = "okay"; 54 status = "okay";
184}; 55};
diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
index a29c7ce15eaf..4aa335166be7 100644
--- a/arch/arm/boot/dts/vfxxx.dtsi
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -54,6 +54,7 @@
54 #address-cells = <1>; 54 #address-cells = <1>;
55 #size-cells = <1>; 55 #size-cells = <1>;
56 compatible = "simple-bus"; 56 compatible = "simple-bus";
57 interrupt-parent = <&mscm_ir>;
57 ranges; 58 ranges;
58 59
59 aips0: aips-bus@40000000 { 60 aips0: aips-bus@40000000 {
@@ -62,6 +63,19 @@
62 #size-cells = <1>; 63 #size-cells = <1>;
63 ranges; 64 ranges;
64 65
66 mscm_cpucfg: cpucfg@40001000 {
67 compatible = "fsl,vf610-mscm-cpucfg", "syscon";
68 reg = <0x40001000 0x800>;
69 };
70
71 mscm_ir: interrupt-controller@40001800 {
72 compatible = "fsl,vf610-mscm-ir";
73 reg = <0x40001800 0x400>;
74 fsl,cpucfg = <&mscm_cpucfg>;
75 interrupt-controller;
76 #interrupt-cells = <2>;
77 };
78
65 edma0: dma-controller@40018000 { 79 edma0: dma-controller@40018000 {
66 #dma-cells = <2>; 80 #dma-cells = <2>;
67 compatible = "fsl,vf610-edma"; 81 compatible = "fsl,vf610-edma";
@@ -69,6 +83,9 @@
69 <0x40024000 0x1000>, 83 <0x40024000 0x1000>,
70 <0x40025000 0x1000>; 84 <0x40025000 0x1000>;
71 dma-channels = <32>; 85 dma-channels = <32>;
86 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>,
87 <9 IRQ_TYPE_LEVEL_HIGH>;
88 interrupt-names = "edma-tx", "edma-err";
72 clock-names = "dmamux0", "dmamux1"; 89 clock-names = "dmamux0", "dmamux1";
73 clocks = <&clks VF610_CLK_DMAMUX0>, 90 clocks = <&clks VF610_CLK_DMAMUX0>,
74 <&clks VF610_CLK_DMAMUX1>; 91 <&clks VF610_CLK_DMAMUX1>;
@@ -78,6 +95,7 @@
78 can0: flexcan@40020000 { 95 can0: flexcan@40020000 {
79 compatible = "fsl,vf610-flexcan"; 96 compatible = "fsl,vf610-flexcan";
80 reg = <0x40020000 0x4000>; 97 reg = <0x40020000 0x4000>;
98 interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
81 clocks = <&clks VF610_CLK_FLEXCAN0>, 99 clocks = <&clks VF610_CLK_FLEXCAN0>,
82 <&clks VF610_CLK_FLEXCAN0>; 100 <&clks VF610_CLK_FLEXCAN0>;
83 clock-names = "ipg", "per"; 101 clock-names = "ipg", "per";
@@ -87,6 +105,7 @@
87 uart0: serial@40027000 { 105 uart0: serial@40027000 {
88 compatible = "fsl,vf610-lpuart"; 106 compatible = "fsl,vf610-lpuart";
89 reg = <0x40027000 0x1000>; 107 reg = <0x40027000 0x1000>;
108 interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
90 clocks = <&clks VF610_CLK_UART0>; 109 clocks = <&clks VF610_CLK_UART0>;
91 clock-names = "ipg"; 110 clock-names = "ipg";
92 dmas = <&edma0 0 2>, 111 dmas = <&edma0 0 2>,
@@ -98,6 +117,7 @@
98 uart1: serial@40028000 { 117 uart1: serial@40028000 {
99 compatible = "fsl,vf610-lpuart"; 118 compatible = "fsl,vf610-lpuart";
100 reg = <0x40028000 0x1000>; 119 reg = <0x40028000 0x1000>;
120 interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
101 clocks = <&clks VF610_CLK_UART1>; 121 clocks = <&clks VF610_CLK_UART1>;
102 clock-names = "ipg"; 122 clock-names = "ipg";
103 dmas = <&edma0 0 4>, 123 dmas = <&edma0 0 4>,
@@ -109,6 +129,7 @@
109 uart2: serial@40029000 { 129 uart2: serial@40029000 {
110 compatible = "fsl,vf610-lpuart"; 130 compatible = "fsl,vf610-lpuart";
111 reg = <0x40029000 0x1000>; 131 reg = <0x40029000 0x1000>;
132 interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
112 clocks = <&clks VF610_CLK_UART2>; 133 clocks = <&clks VF610_CLK_UART2>;
113 clock-names = "ipg"; 134 clock-names = "ipg";
114 dmas = <&edma0 0 6>, 135 dmas = <&edma0 0 6>,
@@ -120,6 +141,7 @@
120 uart3: serial@4002a000 { 141 uart3: serial@4002a000 {
121 compatible = "fsl,vf610-lpuart"; 142 compatible = "fsl,vf610-lpuart";
122 reg = <0x4002a000 0x1000>; 143 reg = <0x4002a000 0x1000>;
144 interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
123 clocks = <&clks VF610_CLK_UART3>; 145 clocks = <&clks VF610_CLK_UART3>;
124 clock-names = "ipg"; 146 clock-names = "ipg";
125 dmas = <&edma0 0 8>, 147 dmas = <&edma0 0 8>,
@@ -133,15 +155,29 @@
133 #size-cells = <0>; 155 #size-cells = <0>;
134 compatible = "fsl,vf610-dspi"; 156 compatible = "fsl,vf610-dspi";
135 reg = <0x4002c000 0x1000>; 157 reg = <0x4002c000 0x1000>;
158 interrupts = <67 IRQ_TYPE_LEVEL_HIGH>;
136 clocks = <&clks VF610_CLK_DSPI0>; 159 clocks = <&clks VF610_CLK_DSPI0>;
137 clock-names = "dspi"; 160 clock-names = "dspi";
138 spi-num-chipselects = <5>; 161 spi-num-chipselects = <5>;
139 status = "disabled"; 162 status = "disabled";
140 }; 163 };
141 164
165 dspi1: dspi1@4002d000 {
166 #address-cells = <1>;
167 #size-cells = <0>;
168 compatible = "fsl,vf610-dspi";
169 reg = <0x4002d000 0x1000>;
170 interrupts = <68 IRQ_TYPE_LEVEL_HIGH>;
171 clocks = <&clks VF610_CLK_DSPI1>;
172 clock-names = "dspi";
173 spi-num-chipselects = <5>;
174 status = "disabled";
175 };
176
142 sai2: sai@40031000 { 177 sai2: sai@40031000 {
143 compatible = "fsl,vf610-sai"; 178 compatible = "fsl,vf610-sai";
144 reg = <0x40031000 0x1000>; 179 reg = <0x40031000 0x1000>;
180 interrupts = <86 IRQ_TYPE_LEVEL_HIGH>;
145 clocks = <&clks VF610_CLK_SAI2>; 181 clocks = <&clks VF610_CLK_SAI2>;
146 clock-names = "sai"; 182 clock-names = "sai";
147 dma-names = "tx", "rx"; 183 dma-names = "tx", "rx";
@@ -153,6 +189,7 @@
153 pit: pit@40037000 { 189 pit: pit@40037000 {
154 compatible = "fsl,vf610-pit"; 190 compatible = "fsl,vf610-pit";
155 reg = <0x40037000 0x1000>; 191 reg = <0x40037000 0x1000>;
192 interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
156 clocks = <&clks VF610_CLK_PIT>; 193 clocks = <&clks VF610_CLK_PIT>;
157 clock-names = "pit"; 194 clock-names = "pit";
158 }; 195 };
@@ -186,6 +223,7 @@
186 adc0: adc@4003b000 { 223 adc0: adc@4003b000 {
187 compatible = "fsl,vf610-adc"; 224 compatible = "fsl,vf610-adc";
188 reg = <0x4003b000 0x1000>; 225 reg = <0x4003b000 0x1000>;
226 interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
189 clocks = <&clks VF610_CLK_ADC0>; 227 clocks = <&clks VF610_CLK_ADC0>;
190 clock-names = "adc"; 228 clock-names = "adc";
191 status = "disabled"; 229 status = "disabled";
@@ -194,6 +232,7 @@
194 wdoga5: wdog@4003e000 { 232 wdoga5: wdog@4003e000 {
195 compatible = "fsl,vf610-wdt", "fsl,imx21-wdt"; 233 compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
196 reg = <0x4003e000 0x1000>; 234 reg = <0x4003e000 0x1000>;
235 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
197 clocks = <&clks VF610_CLK_WDT>; 236 clocks = <&clks VF610_CLK_WDT>;
198 clock-names = "wdog"; 237 clock-names = "wdog";
199 status = "disabled"; 238 status = "disabled";
@@ -204,6 +243,7 @@
204 #size-cells = <0>; 243 #size-cells = <0>;
205 compatible = "fsl,vf610-qspi"; 244 compatible = "fsl,vf610-qspi";
206 reg = <0x40044000 0x1000>; 245 reg = <0x40044000 0x1000>;
246 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&clks VF610_CLK_QSPI0_EN>, 247 clocks = <&clks VF610_CLK_QSPI0_EN>,
208 <&clks VF610_CLK_QSPI0>; 248 <&clks VF610_CLK_QSPI0>;
209 clock-names = "qspi_en", "qspi"; 249 clock-names = "qspi_en", "qspi";
@@ -213,7 +253,6 @@
213 iomuxc: iomuxc@40048000 { 253 iomuxc: iomuxc@40048000 {
214 compatible = "fsl,vf610-iomuxc"; 254 compatible = "fsl,vf610-iomuxc";
215 reg = <0x40048000 0x1000>; 255 reg = <0x40048000 0x1000>;
216 #gpio-range-cells = <3>;
217 }; 256 };
218 257
219 gpio0: gpio@40049000 { 258 gpio0: gpio@40049000 {
@@ -221,6 +260,7 @@
221 reg = <0x40049000 0x1000 0x400ff000 0x40>; 260 reg = <0x40049000 0x1000 0x400ff000 0x40>;
222 gpio-controller; 261 gpio-controller;
223 #gpio-cells = <2>; 262 #gpio-cells = <2>;
263 interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
224 interrupt-controller; 264 interrupt-controller;
225 #interrupt-cells = <2>; 265 #interrupt-cells = <2>;
226 gpio-ranges = <&iomuxc 0 0 32>; 266 gpio-ranges = <&iomuxc 0 0 32>;
@@ -231,6 +271,7 @@
231 reg = <0x4004a000 0x1000 0x400ff040 0x40>; 271 reg = <0x4004a000 0x1000 0x400ff040 0x40>;
232 gpio-controller; 272 gpio-controller;
233 #gpio-cells = <2>; 273 #gpio-cells = <2>;
274 interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
234 interrupt-controller; 275 interrupt-controller;
235 #interrupt-cells = <2>; 276 #interrupt-cells = <2>;
236 gpio-ranges = <&iomuxc 0 32 32>; 277 gpio-ranges = <&iomuxc 0 32 32>;
@@ -241,6 +282,7 @@
241 reg = <0x4004b000 0x1000 0x400ff080 0x40>; 282 reg = <0x4004b000 0x1000 0x400ff080 0x40>;
242 gpio-controller; 283 gpio-controller;
243 #gpio-cells = <2>; 284 #gpio-cells = <2>;
285 interrupts = <109 IRQ_TYPE_LEVEL_HIGH>;
244 interrupt-controller; 286 interrupt-controller;
245 #interrupt-cells = <2>; 287 #interrupt-cells = <2>;
246 gpio-ranges = <&iomuxc 0 64 32>; 288 gpio-ranges = <&iomuxc 0 64 32>;
@@ -251,6 +293,7 @@
251 reg = <0x4004c000 0x1000 0x400ff0c0 0x40>; 293 reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
252 gpio-controller; 294 gpio-controller;
253 #gpio-cells = <2>; 295 #gpio-cells = <2>;
296 interrupts = <110 IRQ_TYPE_LEVEL_HIGH>;
254 interrupt-controller; 297 interrupt-controller;
255 #interrupt-cells = <2>; 298 #interrupt-cells = <2>;
256 gpio-ranges = <&iomuxc 0 96 32>; 299 gpio-ranges = <&iomuxc 0 96 32>;
@@ -261,6 +304,7 @@
261 reg = <0x4004d000 0x1000 0x400ff100 0x40>; 304 reg = <0x4004d000 0x1000 0x400ff100 0x40>;
262 gpio-controller; 305 gpio-controller;
263 #gpio-cells = <2>; 306 #gpio-cells = <2>;
307 interrupts = <111 IRQ_TYPE_LEVEL_HIGH>;
264 interrupt-controller; 308 interrupt-controller;
265 #interrupt-cells = <2>; 309 #interrupt-cells = <2>;
266 gpio-ranges = <&iomuxc 0 128 7>; 310 gpio-ranges = <&iomuxc 0 128 7>;
@@ -274,6 +318,7 @@
274 usbphy0: usbphy@40050800 { 318 usbphy0: usbphy@40050800 {
275 compatible = "fsl,vf610-usbphy"; 319 compatible = "fsl,vf610-usbphy";
276 reg = <0x40050800 0x400>; 320 reg = <0x40050800 0x400>;
321 interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&clks VF610_CLK_USBPHY0>; 322 clocks = <&clks VF610_CLK_USBPHY0>;
278 fsl,anatop = <&anatop>; 323 fsl,anatop = <&anatop>;
279 status = "disabled"; 324 status = "disabled";
@@ -282,6 +327,7 @@
282 usbphy1: usbphy@40050c00 { 327 usbphy1: usbphy@40050c00 {
283 compatible = "fsl,vf610-usbphy"; 328 compatible = "fsl,vf610-usbphy";
284 reg = <0x40050c00 0x400>; 329 reg = <0x40050c00 0x400>;
330 interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&clks VF610_CLK_USBPHY1>; 331 clocks = <&clks VF610_CLK_USBPHY1>;
286 fsl,anatop = <&anatop>; 332 fsl,anatop = <&anatop>;
287 status = "disabled"; 333 status = "disabled";
@@ -292,6 +338,7 @@
292 #size-cells = <0>; 338 #size-cells = <0>;
293 compatible = "fsl,vf610-i2c"; 339 compatible = "fsl,vf610-i2c";
294 reg = <0x40066000 0x1000>; 340 reg = <0x40066000 0x1000>;
341 interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&clks VF610_CLK_I2C0>; 342 clocks = <&clks VF610_CLK_I2C0>;
296 clock-names = "ipg"; 343 clock-names = "ipg";
297 dmas = <&edma0 0 50>, 344 dmas = <&edma0 0 50>,
@@ -311,6 +358,7 @@
311 usbdev0: usb@40034000 { 358 usbdev0: usb@40034000 {
312 compatible = "fsl,vf610-usb", "fsl,imx27-usb"; 359 compatible = "fsl,vf610-usb", "fsl,imx27-usb";
313 reg = <0x40034000 0x800>; 360 reg = <0x40034000 0x800>;
361 interrupts = <75 IRQ_TYPE_LEVEL_HIGH>;
314 clocks = <&clks VF610_CLK_USBC0>; 362 clocks = <&clks VF610_CLK_USBC0>;
315 fsl,usbphy = <&usbphy0>; 363 fsl,usbphy = <&usbphy0>;
316 fsl,usbmisc = <&usbmisc0 0>; 364 fsl,usbmisc = <&usbmisc0 0>;
@@ -329,6 +377,7 @@
329 src: src@4006e000 { 377 src: src@4006e000 {
330 compatible = "fsl,vf610-src", "syscon"; 378 compatible = "fsl,vf610-src", "syscon";
331 reg = <0x4006e000 0x1000>; 379 reg = <0x4006e000 0x1000>;
380 interrupts = <96 IRQ_TYPE_LEVEL_HIGH>;
332 }; 381 };
333 }; 382 };
334 383
@@ -345,6 +394,9 @@
345 <0x400a1000 0x1000>, 394 <0x400a1000 0x1000>,
346 <0x400a2000 0x1000>; 395 <0x400a2000 0x1000>;
347 dma-channels = <32>; 396 dma-channels = <32>;
397 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
398 <11 IRQ_TYPE_LEVEL_HIGH>;
399 interrupt-names = "edma-tx", "edma-err";
348 clock-names = "dmamux0", "dmamux1"; 400 clock-names = "dmamux0", "dmamux1";
349 clocks = <&clks VF610_CLK_DMAMUX2>, 401 clocks = <&clks VF610_CLK_DMAMUX2>,
350 <&clks VF610_CLK_DMAMUX3>; 402 <&clks VF610_CLK_DMAMUX3>;
@@ -360,6 +412,7 @@
360 snvsrtc: snvs-rtc-lp@34 { 412 snvsrtc: snvs-rtc-lp@34 {
361 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 413 compatible = "fsl,sec-v4.0-mon-rtc-lp";
362 reg = <0x34 0x58>; 414 reg = <0x34 0x58>;
415 interrupts = <100 IRQ_TYPE_LEVEL_HIGH>;
363 clocks = <&clks VF610_CLK_SNVS>; 416 clocks = <&clks VF610_CLK_SNVS>;
364 clock-names = "snvs-rtc"; 417 clock-names = "snvs-rtc";
365 }; 418 };
@@ -368,6 +421,7 @@
368 uart4: serial@400a9000 { 421 uart4: serial@400a9000 {
369 compatible = "fsl,vf610-lpuart"; 422 compatible = "fsl,vf610-lpuart";
370 reg = <0x400a9000 0x1000>; 423 reg = <0x400a9000 0x1000>;
424 interrupts = <65 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&clks VF610_CLK_UART4>; 425 clocks = <&clks VF610_CLK_UART4>;
372 clock-names = "ipg"; 426 clock-names = "ipg";
373 status = "disabled"; 427 status = "disabled";
@@ -376,6 +430,7 @@
376 uart5: serial@400aa000 { 430 uart5: serial@400aa000 {
377 compatible = "fsl,vf610-lpuart"; 431 compatible = "fsl,vf610-lpuart";
378 reg = <0x400aa000 0x1000>; 432 reg = <0x400aa000 0x1000>;
433 interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&clks VF610_CLK_UART5>; 434 clocks = <&clks VF610_CLK_UART5>;
380 clock-names = "ipg"; 435 clock-names = "ipg";
381 status = "disabled"; 436 status = "disabled";
@@ -384,6 +439,7 @@
384 adc1: adc@400bb000 { 439 adc1: adc@400bb000 {
385 compatible = "fsl,vf610-adc"; 440 compatible = "fsl,vf610-adc";
386 reg = <0x400bb000 0x1000>; 441 reg = <0x400bb000 0x1000>;
442 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&clks VF610_CLK_ADC1>; 443 clocks = <&clks VF610_CLK_ADC1>;
388 clock-names = "adc"; 444 clock-names = "adc";
389 status = "disabled"; 445 status = "disabled";
@@ -392,6 +448,7 @@
392 esdhc1: esdhc@400b2000 { 448 esdhc1: esdhc@400b2000 {
393 compatible = "fsl,imx53-esdhc"; 449 compatible = "fsl,imx53-esdhc";
394 reg = <0x400b2000 0x1000>; 450 reg = <0x400b2000 0x1000>;
451 interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
395 clocks = <&clks VF610_CLK_IPG_BUS>, 452 clocks = <&clks VF610_CLK_IPG_BUS>,
396 <&clks VF610_CLK_PLATFORM_BUS>, 453 <&clks VF610_CLK_PLATFORM_BUS>,
397 <&clks VF610_CLK_ESDHC1>; 454 <&clks VF610_CLK_ESDHC1>;
@@ -402,6 +459,7 @@
402 usbh1: usb@400b4000 { 459 usbh1: usb@400b4000 {
403 compatible = "fsl,vf610-usb", "fsl,imx27-usb"; 460 compatible = "fsl,vf610-usb", "fsl,imx27-usb";
404 reg = <0x400b4000 0x800>; 461 reg = <0x400b4000 0x800>;
462 interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&clks VF610_CLK_USBC1>; 463 clocks = <&clks VF610_CLK_USBC1>;
406 fsl,usbphy = <&usbphy1>; 464 fsl,usbphy = <&usbphy1>;
407 fsl,usbmisc = <&usbmisc1 0>; 465 fsl,usbmisc = <&usbmisc1 0>;
@@ -420,6 +478,7 @@
420 ftm: ftm@400b8000 { 478 ftm: ftm@400b8000 {
421 compatible = "fsl,ftm-timer"; 479 compatible = "fsl,ftm-timer";
422 reg = <0x400b8000 0x1000 0x400b9000 0x1000>; 480 reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
481 interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
423 clock-names = "ftm-evt", "ftm-src", 482 clock-names = "ftm-evt", "ftm-src",
424 "ftm-evt-counter-en", "ftm-src-counter-en"; 483 "ftm-evt-counter-en", "ftm-src-counter-en";
425 clocks = <&clks VF610_CLK_FTM2>, 484 clocks = <&clks VF610_CLK_FTM2>,
@@ -432,6 +491,7 @@
432 fec0: ethernet@400d0000 { 491 fec0: ethernet@400d0000 {
433 compatible = "fsl,mvf600-fec"; 492 compatible = "fsl,mvf600-fec";
434 reg = <0x400d0000 0x1000>; 493 reg = <0x400d0000 0x1000>;
494 interrupts = <78 IRQ_TYPE_LEVEL_HIGH>;
435 clocks = <&clks VF610_CLK_ENET0>, 495 clocks = <&clks VF610_CLK_ENET0>,
436 <&clks VF610_CLK_ENET0>, 496 <&clks VF610_CLK_ENET0>,
437 <&clks VF610_CLK_ENET>; 497 <&clks VF610_CLK_ENET>;
@@ -442,6 +502,7 @@
442 fec1: ethernet@400d1000 { 502 fec1: ethernet@400d1000 {
443 compatible = "fsl,mvf600-fec"; 503 compatible = "fsl,mvf600-fec";
444 reg = <0x400d1000 0x1000>; 504 reg = <0x400d1000 0x1000>;
505 interrupts = <79 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&clks VF610_CLK_ENET1>, 506 clocks = <&clks VF610_CLK_ENET1>,
446 <&clks VF610_CLK_ENET1>, 507 <&clks VF610_CLK_ENET1>,
447 <&clks VF610_CLK_ENET>; 508 <&clks VF610_CLK_ENET>;
@@ -452,6 +513,7 @@
452 can1: flexcan@400d4000 { 513 can1: flexcan@400d4000 {
453 compatible = "fsl,vf610-flexcan"; 514 compatible = "fsl,vf610-flexcan";
454 reg = <0x400d4000 0x4000>; 515 reg = <0x400d4000 0x4000>;
516 interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&clks VF610_CLK_FLEXCAN1>, 517 clocks = <&clks VF610_CLK_FLEXCAN1>,
456 <&clks VF610_CLK_FLEXCAN1>; 518 <&clks VF610_CLK_FLEXCAN1>;
457 clock-names = "ipg", "per"; 519 clock-names = "ipg", "per";
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-31 21:43:05 -0400