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authorArnd Bergmann <arnd@arndb.de>2015-04-13 19:03:29 -0400
committerArnd Bergmann <arnd@arndb.de>2015-04-13 19:03:29 -0400
commit643ee0d50a7392671c0488912cdbb37549ac4cc7 (patch)
treec6264bd7ca5139f4f0183d12b0732bc96347b90f /arch/arm/boot/dts
parent13a7a6ac0a11197edcd0f756a035f472b42cdf8b (diff)
parent21295368367beaa563b310d5492166dba158b884 (diff)
Merge tag 'omap-for-v4.1/prcm-dts' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/late
Pull "Clean-up for omap PRCM (Power Reset Clock Management) and interconnects" from Tony Lindgren Patches originally from Tero Kristo <t-kristo@ti.com>. This sets gets us into a better position for further clean-up: - Gets PRCM code closer to being device drivers - Allows to move the remainig clock code to drivers/clk for v4.2 - Starts enforcing interconnect hierarchy in the SoC specific .dts files to enforce device drivers are only accesing registers in the related hardware module This patchset has seen quite a few revisions but did not come into mergeable shape until recently. As other patchsets for clock specific device drivers depend on this, it would be good to get this merged although it's a bit late for the v4.1 merge window. Note that as the device entries in the .dts files are moved around, this is based on earlier non-urgent fixes to avoid a non-trivial merge conflict. * tag 'omap-for-v4.1/prcm-dts' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (44 commits) ARM: OMAP4+: control: add support for initializing control module via DT ARM: dts: dra7: add minimal l4 bus layout with control module support ARM: dts: omap5: add minimal l4 bus layout with control module support ARM: OMAP4+: control: remove support for legacy pad read/write ARM: OMAP4: display: convert display to use syscon for dsi muxing ARM: dts: omap4: add minimal l4 bus layout with control module support ARM: dts: am4372: add minimal l4 bus layout with control module support ARM: dts: am43xx-epos-evm: fix pinmux node layout ARM: dts: am33xx: add minimal l4 bus layout with control module support ARM: dts: omap3: add minimal l4 bus layout with control module support ARM: dts: omap24xx: add minimal l4 bus layout with control module support ARM: OMAP2+: control: add syscon support for register accesses ARM: OMAP2+: id: cache omap_type value ARM: OMAP2+: control: remove API for getting control module base address ARM: OMAP2+: clock: add low-level support for regmap ARM: OMAP4+: PRM: get rid of cpu_is_omap44xx calls from interrupt init ARM: OMAP4+: PRM: setup prm_features from the PRM init time flags ARM: OMAP2+: CM: move SoC specific init calls within a generic API ARM: OMAP4+: PRM: determine prm_device_inst based on DT compatibility ARM: OMAP2+: PRM: move SoC specific init calls within a generic API ...
Diffstat (limited to 'arch/arm/boot/dts')
-rw-r--r--arch/arm/boot/dts/am33xx-clocks.dtsi2
-rw-r--r--arch/arm/boot/dts/am33xx.dtsi87
-rw-r--r--arch/arm/boot/dts/am3517.dtsi2
-rw-r--r--arch/arm/boot/dts/am35xx-clocks.dtsi2
-rw-r--r--arch/arm/boot/dts/am4372.dtsi89
-rw-r--r--arch/arm/boot/dts/am43x-epos-evm.dts84
-rw-r--r--arch/arm/boot/dts/am43xx-clocks.dtsi2
-rw-r--r--arch/arm/boot/dts/am57xx-beagle-x15.dts49
-rw-r--r--arch/arm/boot/dts/dra7.dtsi175
-rw-r--r--arch/arm/boot/dts/dra72x.dtsi5
-rw-r--r--arch/arm/boot/dts/dra74x.dtsi5
-rw-r--r--arch/arm/boot/dts/omap2420.dtsi80
-rw-r--r--arch/arm/boot/dts/omap2430-clocks.dtsi8
-rw-r--r--arch/arm/boot/dts/omap2430.dtsi107
-rw-r--r--arch/arm/boot/dts/omap24xx-clocks.dtsi6
-rw-r--r--arch/arm/boot/dts/omap3.dtsi96
-rw-r--r--arch/arm/boot/dts/omap3xxx-clocks.dtsi13
-rw-r--r--arch/arm/boot/dts/omap4-cpu-thermal.dtsi4
-rw-r--r--arch/arm/boot/dts/omap4.dtsi200
-rw-r--r--arch/arm/boot/dts/omap5.dtsi182
20 files changed, 730 insertions, 468 deletions
diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi
index 712edce7d6fb..236c78a3c6ca 100644
--- a/arch/arm/boot/dts/am33xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
@@ -7,7 +7,7 @@
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10&scrm_clocks { 10&scm_clocks {
11 sys_clkin_ck: sys_clkin_ck { 11 sys_clkin_ck: sys_clkin_ck {
12 #clock-cells = <0>; 12 #clock-cells = <0>;
13 compatible = "ti,mux-clock"; 13 compatible = "ti,mux-clock";
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index acd37057bca9..21fcc440fc1a 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -83,20 +83,6 @@
83 }; 83 };
84 }; 84 };
85 85
86 am33xx_control_module: control_module@4a002000 {
87 compatible = "syscon";
88 reg = <0x44e10000 0x7fc>;
89 };
90
91 am33xx_pinmux: pinmux@44e10800 {
92 compatible = "pinctrl-single";
93 reg = <0x44e10800 0x0238>;
94 #address-cells = <1>;
95 #size-cells = <0>;
96 pinctrl-single,register-width = <32>;
97 pinctrl-single,function-mask = <0x7f>;
98 };
99
100 /* 86 /*
101 * XXX: Use a flat representation of the AM33XX interconnect. 87 * XXX: Use a flat representation of the AM33XX interconnect.
102 * The real AM33XX interconnect network is quite complex. Since 88 * The real AM33XX interconnect network is quite complex. Since
@@ -111,37 +97,58 @@
111 ranges; 97 ranges;
112 ti,hwmods = "l3_main"; 98 ti,hwmods = "l3_main";
113 99
114 prcm: prcm@44e00000 { 100 l4_wkup: l4_wkup@44c00000 {
115 compatible = "ti,am3-prcm"; 101 compatible = "ti,am3-l4-wkup", "simple-bus";
116 reg = <0x44e00000 0x4000>; 102 #address-cells = <1>;
117 103 #size-cells = <1>;
118 prcm_clocks: clocks { 104 ranges = <0 0x44c00000 0x280000>;
119 #address-cells = <1>;
120 #size-cells = <0>;
121 };
122 105
123 prcm_clockdomains: clockdomains { 106 prcm: prcm@200000 {
124 }; 107 compatible = "ti,am3-prcm";
125 }; 108 reg = <0x200000 0x4000>;
126 109
127 scrm: scrm@44e10000 { 110 prcm_clocks: clocks {
128 compatible = "ti,am3-scrm"; 111 #address-cells = <1>;
129 reg = <0x44e10000 0x2000>; 112 #size-cells = <0>;
113 };
130 114
131 scrm_clocks: clocks { 115 prcm_clockdomains: clockdomains {
132 #address-cells = <1>; 116 };
133 #size-cells = <0>;
134 }; 117 };
135 118
136 scrm_clockdomains: clockdomains { 119 scm: scm@210000 {
120 compatible = "ti,am3-scm", "simple-bus";
121 reg = <0x210000 0x2000>;
122 #address-cells = <1>;
123 #size-cells = <1>;
124 ranges = <0 0x210000 0x2000>;
125
126 am33xx_pinmux: pinmux@800 {
127 compatible = "pinctrl-single";
128 reg = <0x800 0x238>;
129 #address-cells = <1>;
130 #size-cells = <0>;
131 pinctrl-single,register-width = <32>;
132 pinctrl-single,function-mask = <0x7f>;
133 };
134
135 scm_conf: scm_conf@0 {
136 compatible = "syscon";
137 reg = <0x0 0x800>;
138 #address-cells = <1>;
139 #size-cells = <1>;
140
141 scm_clocks: clocks {
142 #address-cells = <1>;
143 #size-cells = <0>;
144 };
145 };
146
147 scm_clockdomains: clockdomains {
148 };
137 }; 149 };
138 }; 150 };
139 151
140 cm: syscon@44e10000 {
141 compatible = "ti,am33xx-controlmodule", "syscon";
142 reg = <0x44e10000 0x800>;
143 };
144
145 intc: interrupt-controller@48200000 { 152 intc: interrupt-controller@48200000 {
146 compatible = "ti,am33xx-intc"; 153 compatible = "ti,am33xx-intc";
147 interrupt-controller; 154 interrupt-controller;
@@ -350,7 +357,7 @@
350 reg = <0x481cc000 0x2000>; 357 reg = <0x481cc000 0x2000>;
351 clocks = <&dcan0_fck>; 358 clocks = <&dcan0_fck>;
352 clock-names = "fck"; 359 clock-names = "fck";
353 syscon-raminit = <&am33xx_control_module 0x644 0>; 360 syscon-raminit = <&scm_conf 0x644 0>;
354 interrupts = <52>; 361 interrupts = <52>;
355 status = "disabled"; 362 status = "disabled";
356 }; 363 };
@@ -361,7 +368,7 @@
361 reg = <0x481d0000 0x2000>; 368 reg = <0x481d0000 0x2000>;
362 clocks = <&dcan1_fck>; 369 clocks = <&dcan1_fck>;
363 clock-names = "fck"; 370 clock-names = "fck";
364 syscon-raminit = <&am33xx_control_module 0x644 1>; 371 syscon-raminit = <&scm_conf 0x644 1>;
365 interrupts = <55>; 372 interrupts = <55>;
366 status = "disabled"; 373 status = "disabled";
367 }; 374 };
@@ -720,7 +727,7 @@
720 */ 727 */
721 interrupts = <40 41 42 43>; 728 interrupts = <40 41 42 43>;
722 ranges; 729 ranges;
723 syscon = <&cm>; 730 syscon = <&scm_conf>;
724 status = "disabled"; 731 status = "disabled";
725 732
726 davinci_mdio: mdio@4a101000 { 733 davinci_mdio: mdio@4a101000 {
diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
index c90724bded10..f164dce08755 100644
--- a/arch/arm/boot/dts/am3517.dtsi
+++ b/arch/arm/boot/dts/am3517.dtsi
@@ -31,7 +31,7 @@
31 status = "disabled"; 31 status = "disabled";
32 reg = <0x5c000000 0x30000>; 32 reg = <0x5c000000 0x30000>;
33 interrupts = <67 68 69 70>; 33 interrupts = <67 68 69 70>;
34 syscon = <&omap3_scm_general>; 34 syscon = <&scm_conf>;
35 ti,davinci-ctrl-reg-offset = <0x10000>; 35 ti,davinci-ctrl-reg-offset = <0x10000>;
36 ti,davinci-ctrl-mod-reg-offset = <0>; 36 ti,davinci-ctrl-mod-reg-offset = <0>;
37 ti,davinci-ctrl-ram-offset = <0x20000>; 37 ti,davinci-ctrl-ram-offset = <0x20000>;
diff --git a/arch/arm/boot/dts/am35xx-clocks.dtsi b/arch/arm/boot/dts/am35xx-clocks.dtsi
index df489d310b50..518b8fde88b0 100644
--- a/arch/arm/boot/dts/am35xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am35xx-clocks.dtsi
@@ -7,7 +7,7 @@
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10&scrm_clocks { 10&scm_clocks {
11 emac_ick: emac_ick { 11 emac_ick: emac_ick {
12 #clock-cells = <0>; 12 #clock-cells = <0>;
13 compatible = "ti,am35xx-gate-clock"; 13 compatible = "ti,am35xx-gate-clock";
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 1943fc333e7c..2f6f0c2040db 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -57,22 +57,6 @@
57 cache-level = <2>; 57 cache-level = <2>;
58 }; 58 };
59 59
60 am43xx_control_module: control_module@4a002000 {
61 compatible = "syscon";
62 reg = <0x44e10000 0x7f4>;
63 };
64
65 am43xx_pinmux: pinmux@44e10800 {
66 compatible = "ti,am437-padconf", "pinctrl-single";
67 reg = <0x44e10800 0x31c>;
68 #address-cells = <1>;
69 #size-cells = <0>;
70 #interrupt-cells = <1>;
71 interrupt-controller;
72 pinctrl-single,register-width = <32>;
73 pinctrl-single,function-mask = <0xffffffff>;
74 };
75
76 ocp { 60 ocp {
77 compatible = "ti,am4372-l3-noc", "simple-bus"; 61 compatible = "ti,am4372-l3-noc", "simple-bus";
78 #address-cells = <1>; 62 #address-cells = <1>;
@@ -84,29 +68,58 @@
84 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 68 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 69 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
86 70
87 prcm: prcm@44df0000 { 71 l4_wkup: l4_wkup@44c00000 {
88 compatible = "ti,am4-prcm"; 72 compatible = "ti,am4-l4-wkup", "simple-bus";
89 reg = <0x44df0000 0x11000>; 73 #address-cells = <1>;
90 74 #size-cells = <1>;
91 prcm_clocks: clocks { 75 ranges = <0 0x44c00000 0x287000>;
92 #address-cells = <1>;
93 #size-cells = <0>;
94 };
95 76
96 prcm_clockdomains: clockdomains { 77 prcm: prcm@1f0000 {
97 }; 78 compatible = "ti,am4-prcm";
98 }; 79 reg = <0x1f0000 0x11000>;
99 80
100 scrm: scrm@44e10000 { 81 prcm_clocks: clocks {
101 compatible = "ti,am4-scrm"; 82 #address-cells = <1>;
102 reg = <0x44e10000 0x2000>; 83 #size-cells = <0>;
84 };
103 85
104 scrm_clocks: clocks { 86 prcm_clockdomains: clockdomains {
105 #address-cells = <1>; 87 };
106 #size-cells = <0>;
107 }; 88 };
108 89
109 scrm_clockdomains: clockdomains { 90 scm: scm@210000 {
91 compatible = "ti,am4-scm", "simple-bus";
92 reg = <0x210000 0x4000>;
93 #address-cells = <1>;
94 #size-cells = <1>;
95 ranges = <0 0x210000 0x4000>;
96
97 am43xx_pinmux: pinmux@800 {
98 compatible = "ti,am437-padconf",
99 "pinctrl-single";
100 reg = <0x800 0x31c>;
101 #address-cells = <1>;
102 #size-cells = <0>;
103 #interrupt-cells = <1>;
104 interrupt-controller;
105 pinctrl-single,register-width = <32>;
106 pinctrl-single,function-mask = <0xffffffff>;
107 };
108
109 scm_conf: scm_conf@0 {
110 compatible = "syscon";
111 reg = <0x0 0x800>;
112 #address-cells = <1>;
113 #size-cells = <1>;
114
115 scm_clocks: clocks {
116 #address-cells = <1>;
117 #size-cells = <0>;
118 };
119 };
120
121 scm_clockdomains: clockdomains {
122 };
110 }; 123 };
111 }; 124 };
112 125
@@ -787,7 +800,7 @@
787 }; 800 };
788 801
789 ocp2scp0: ocp2scp@483a8000 { 802 ocp2scp0: ocp2scp@483a8000 {
790 compatible = "ti,omap-ocp2scp"; 803 compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
791 #address-cells = <1>; 804 #address-cells = <1>;
792 #size-cells = <1>; 805 #size-cells = <1>;
793 ranges; 806 ranges;
@@ -806,7 +819,7 @@
806 }; 819 };
807 820
808 ocp2scp1: ocp2scp@483e8000 { 821 ocp2scp1: ocp2scp@483e8000 {
809 compatible = "ti,omap-ocp2scp"; 822 compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
810 #address-cells = <1>; 823 #address-cells = <1>;
811 #size-cells = <1>; 824 #size-cells = <1>;
812 ranges; 825 ranges;
@@ -933,7 +946,7 @@
933 clocks = <&dcan0_fck>; 946 clocks = <&dcan0_fck>;
934 clock-names = "fck"; 947 clock-names = "fck";
935 reg = <0x481cc000 0x2000>; 948 reg = <0x481cc000 0x2000>;
936 syscon-raminit = <&am43xx_control_module 0x644 0>; 949 syscon-raminit = <&scm_conf 0x644 0>;
937 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 950 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
938 status = "disabled"; 951 status = "disabled";
939 }; 952 };
@@ -944,7 +957,7 @@
944 clocks = <&dcan1_fck>; 957 clocks = <&dcan1_fck>;
945 clock-names = "fck"; 958 clock-names = "fck";
946 reg = <0x481d0000 0x2000>; 959 reg = <0x481d0000 0x2000>;
947 syscon-raminit = <&am43xx_control_module 0x644 1>; 960 syscon-raminit = <&scm_conf 0x644 1>;
948 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 961 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
949 status = "disabled"; 962 status = "disabled";
950 }; 963 };
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index 257c099c347e..72f01bb5d61c 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -69,7 +69,48 @@
69 }; 69 };
70 }; 70 };
71 71
72 am43xx_pinmux: pinmux@44e10800 { 72 matrix_keypad: matrix_keypad@0 {
73 compatible = "gpio-matrix-keypad";
74 debounce-delay-ms = <5>;
75 col-scan-delay-us = <2>;
76
77 row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */
78 &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */
79 &gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */
80 &gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */
81
82 col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */
83 &gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */
84 &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */
85 &gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */
86
87 linux,keymap = <0x00000201 /* P1 */
88 0x01000204 /* P4 */
89 0x02000207 /* P7 */
90 0x0300020a /* NUMERIC_STAR */
91 0x00010202 /* P2 */
92 0x01010205 /* P5 */
93 0x02010208 /* P8 */
94 0x03010200 /* P0 */
95 0x00020203 /* P3 */
96 0x01020206 /* P6 */
97 0x02020209 /* P9 */
98 0x0302020b /* NUMERIC_POUND */
99 0x00030067 /* UP */
100 0x0103006a /* RIGHT */
101 0x0203006c /* DOWN */
102 0x03030069>; /* LEFT */
103 };
104
105 backlight {
106 compatible = "pwm-backlight";
107 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
108 brightness-levels = <0 51 53 56 62 75 101 152 255>;
109 default-brightness-level = <8>;
110 };
111};
112
113&am43xx_pinmux {
73 cpsw_default: cpsw_default { 114 cpsw_default: cpsw_default {
74 pinctrl-single,pins = < 115 pinctrl-single,pins = <
75 /* Slave 1 */ 116 /* Slave 1 */
@@ -279,47 +320,6 @@
279 0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 320 0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
280 >; 321 >;
281 }; 322 };
282 };
283
284 matrix_keypad: matrix_keypad@0 {
285 compatible = "gpio-matrix-keypad";
286 debounce-delay-ms = <5>;
287 col-scan-delay-us = <2>;
288
289 row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */
290 &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */
291 &gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */
292 &gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */
293
294 col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */
295 &gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */
296 &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */
297 &gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */
298
299 linux,keymap = <0x00000201 /* P1 */
300 0x01000204 /* P4 */
301 0x02000207 /* P7 */
302 0x0300020a /* NUMERIC_STAR */
303 0x00010202 /* P2 */
304 0x01010205 /* P5 */
305 0x02010208 /* P8 */
306 0x03010200 /* P0 */
307 0x00020203 /* P3 */
308 0x01020206 /* P6 */
309 0x02020209 /* P9 */
310 0x0302020b /* NUMERIC_POUND */
311 0x00030067 /* UP */
312 0x0103006a /* RIGHT */
313 0x0203006c /* DOWN */
314 0x03030069>; /* LEFT */
315 };
316
317 backlight {
318 compatible = "pwm-backlight";
319 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
320 brightness-levels = <0 51 53 56 62 75 101 152 255>;
321 default-brightness-level = <8>;
322 };
323}; 323};
324 324
325&mmc1 { 325&mmc1 {
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi
index c7dc9dab93a4..44869aa72642 100644
--- a/arch/arm/boot/dts/am43xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -7,7 +7,7 @@
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10&scrm_clocks { 10&scm_clocks {
11 sys_clkin_ck: sys_clkin_ck { 11 sys_clkin_ck: sys_clkin_ck {
12 #clock-cells = <0>; 12 #clock-cells = <0>;
13 compatible = "ti,mux-clock"; 13 compatible = "ti,mux-clock";
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index 6463f9ef2b54..31497a45afb0 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -87,6 +87,7 @@
87 gpios = <&tps659038_gpio 1 GPIO_ACTIVE_HIGH>; 87 gpios = <&tps659038_gpio 1 GPIO_ACTIVE_HIGH>;
88 gpio-fan,speed-map = <0 0>, 88 gpio-fan,speed-map = <0 0>,
89 <13000 1>; 89 <13000 1>;
90 #cooling-cells = <2>;
90 }; 91 };
91 92
92 extcon_usb1: extcon_usb1 { 93 extcon_usb1: extcon_usb1 {
@@ -442,6 +443,7 @@
442 pinctrl-0 = <&tmp102_pins_default>; 443 pinctrl-0 = <&tmp102_pins_default>;
443 interrupt-parent = <&gpio7>; 444 interrupt-parent = <&gpio7>;
444 interrupts = <16 IRQ_TYPE_LEVEL_LOW>; 445 interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
446 #thermal-sensor-cells = <1>;
445 }; 447 };
446}; 448};
447 449
@@ -552,3 +554,50 @@
552&usb2 { 554&usb2 {
553 dr_mode = "peripheral"; 555 dr_mode = "peripheral";
554}; 556};
557
558&cpu_trips {
559 cpu_alert1: cpu_alert1 {
560 temperature = <50000>; /* millicelsius */
561 hysteresis = <2000>; /* millicelsius */
562 type = "active";
563 };
564};
565
566&cpu_cooling_maps {
567 map1 {
568 trip = <&cpu_alert1>;
569 cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
570 };
571};
572
573&thermal_zones {
574 board_thermal: board_thermal {
575 polling-delay-passive = <1250>; /* milliseconds */
576 polling-delay = <1500>; /* milliseconds */
577
578 /* sensor ID */
579 thermal-sensors = <&tmp102 0>;
580
581 board_trips: trips {
582 board_alert0: board_alert {
583 temperature = <40000>; /* millicelsius */
584 hysteresis = <2000>; /* millicelsius */
585 type = "active";
586 };
587
588 board_crit: board_crit {
589 temperature = <105000>; /* millicelsius */
590 hysteresis = <0>; /* millicelsius */
591 type = "critical";
592 };
593 };
594
595 board_cooling_maps: cooling-maps {
596 map0 {
597 trip = <&board_alert0>;
598 cooling-device =
599 <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
600 };
601 };
602 };
603};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 127608d79033..ce3eb311da1e 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -94,17 +94,101 @@
94 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 94 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
95 <GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH>; 95 <GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH>;
96 96
97 prm: prm@4ae06000 { 97 l4_cfg: l4@4a000000 {
98 compatible = "ti,dra7-prm"; 98 compatible = "ti,dra7-l4-cfg", "simple-bus";
99 reg = <0x4ae06000 0x3000>; 99 #address-cells = <1>;
100 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 100 #size-cells = <1>;
101 ranges = <0 0x4a000000 0x22c000>;
101 102
102 prm_clocks: clocks { 103 scm: scm@2000 {
104 compatible = "ti,dra7-scm-core", "simple-bus";
105 reg = <0x2000 0x2000>;
103 #address-cells = <1>; 106 #address-cells = <1>;
104 #size-cells = <0>; 107 #size-cells = <1>;
108 ranges = <0 0x2000 0x2000>;
109
110 scm_conf: scm_conf@0 {
111 compatible = "syscon";
112 reg = <0x0 0x1400>;
113 #address-cells = <1>;
114 #size-cells = <1>;
115
116 pbias_regulator: pbias_regulator {
117 compatible = "ti,pbias-omap";
118 reg = <0xe00 0x4>;
119 syscon = <&scm_conf>;
120 pbias_mmc_reg: pbias_mmc_omap5 {
121 regulator-name = "pbias_mmc_omap5";
122 regulator-min-microvolt = <1800000>;
123 regulator-max-microvolt = <3000000>;
124 };
125 };
126 };
127
128 dra7_pmx_core: pinmux@1400 {
129 compatible = "ti,dra7-padconf",
130 "pinctrl-single";
131 reg = <0x1400 0x0464>;
132 #address-cells = <1>;
133 #size-cells = <0>;
134 #interrupt-cells = <1>;
135 interrupt-controller;
136 pinctrl-single,register-width = <32>;
137 pinctrl-single,function-mask = <0x3fffffff>;
138 };
139 };
140
141 cm_core_aon: cm_core_aon@5000 {
142 compatible = "ti,dra7-cm-core-aon";
143 reg = <0x5000 0x2000>;
144
145 cm_core_aon_clocks: clocks {
146 #address-cells = <1>;
147 #size-cells = <0>;
148 };
149
150 cm_core_aon_clockdomains: clockdomains {
151 };
152 };
153
154 cm_core: cm_core@8000 {
155 compatible = "ti,dra7-cm-core";
156 reg = <0x8000 0x3000>;
157
158 cm_core_clocks: clocks {
159 #address-cells = <1>;
160 #size-cells = <0>;
161 };
162
163 cm_core_clockdomains: clockdomains {
164 };
105 }; 165 };
166 };
106 167
107 prm_clockdomains: clockdomains { 168 l4_wkup: l4@4ae00000 {
169 compatible = "ti,dra7-l4-wkup", "simple-bus";
170 #address-cells = <1>;
171 #size-cells = <1>;
172 ranges = <0 0x4ae00000 0x3f000>;
173
174 counter32k: counter@4000 {
175 compatible = "ti,omap-counter32k";
176 reg = <0x4000 0x40>;
177 ti,hwmods = "counter_32k";
178 };
179
180 prm: prm@6000 {
181 compatible = "ti,dra7-prm";
182 reg = <0x6000 0x3000>;
183 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
184
185 prm_clocks: clocks {
186 #address-cells = <1>;
187 #size-cells = <0>;
188 };
189
190 prm_clockdomains: clockdomains {
191 };
108 }; 192 };
109 }; 193 };
110 194
@@ -177,36 +261,16 @@
177 }; 261 };
178 }; 262 };
179 263
180 cm_core_aon: cm_core_aon@4a005000 { 264 bandgap: bandgap@4a0021e0 {
181 compatible = "ti,dra7-cm-core-aon"; 265 reg = <0x4a0021e0 0xc
182 reg = <0x4a005000 0x2000>; 266 0x4a00232c 0xc
183 267 0x4a002380 0x2c
184 cm_core_aon_clocks: clocks { 268 0x4a0023C0 0x3c
185 #address-cells = <1>; 269 0x4a002564 0x8
186 #size-cells = <0>; 270 0x4a002574 0x50>;
187 }; 271 compatible = "ti,dra752-bandgap";
188 272 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
189 cm_core_aon_clockdomains: clockdomains { 273 #thermal-sensor-cells = <1>;
190 };
191 };
192
193 cm_core: cm_core@4a008000 {
194 compatible = "ti,dra7-cm-core";
195 reg = <0x4a008000 0x3000>;
196
197 cm_core_clocks: clocks {
198 #address-cells = <1>;
199 #size-cells = <0>;
200 };
201
202 cm_core_clockdomains: clockdomains {
203 };
204 };
205
206 counter32k: counter@4ae04000 {
207 compatible = "ti,omap-counter32k";
208 reg = <0x4ae04000 0x40>;
209 ti,hwmods = "counter_32k";
210 }; 274 };
211 275
212 dra7_ctrl_core: ctrl_core@4a002000 { 276 dra7_ctrl_core: ctrl_core@4a002000 {
@@ -219,28 +283,6 @@
219 reg = <0x4a002e00 0x7c>; 283 reg = <0x4a002e00 0x7c>;
220 }; 284 };
221 285
222 pbias_regulator: pbias_regulator {
223 compatible = "ti,pbias-omap";
224 reg = <0 0x4>;
225 syscon = <&dra7_ctrl_general>;
226 pbias_mmc_reg: pbias_mmc_omap5 {
227 regulator-name = "pbias_mmc_omap5";
228 regulator-min-microvolt = <1800000>;
229 regulator-max-microvolt = <3000000>;
230 };
231 };
232
233 dra7_pmx_core: pinmux@4a003400 {
234 compatible = "ti,dra7-padconf", "pinctrl-single";
235 reg = <0x4a003400 0x0464>;
236 #address-cells = <1>;
237 #size-cells = <0>;
238 #interrupt-cells = <1>;
239 interrupt-controller;
240 pinctrl-single,register-width = <32>;
241 pinctrl-single,function-mask = <0x3fffffff>;
242 };
243
244 sdma: dma-controller@4a056000 { 286 sdma: dma-controller@4a056000 {
245 compatible = "ti,omap4430-sdma"; 287 compatible = "ti,omap4430-sdma";
246 reg = <0x4a056000 0x1000>; 288 reg = <0x4a056000 0x1000>;
@@ -1410,7 +1452,7 @@
1410 compatible = "ti,dra7-d_can"; 1452 compatible = "ti,dra7-d_can";
1411 ti,hwmods = "dcan1"; 1453 ti,hwmods = "dcan1";
1412 reg = <0x4ae3c000 0x2000>; 1454 reg = <0x4ae3c000 0x2000>;
1413 syscon-raminit = <&dra7_ctrl_core 0x558 0>; 1455 syscon-raminit = <&scm_conf 0x558 0>;
1414 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 1456 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1415 clocks = <&dcan1_sys_clk_mux>; 1457 clocks = <&dcan1_sys_clk_mux>;
1416 status = "disabled"; 1458 status = "disabled";
@@ -1420,12 +1462,23 @@
1420 compatible = "ti,dra7-d_can"; 1462 compatible = "ti,dra7-d_can";
1421 ti,hwmods = "dcan2"; 1463 ti,hwmods = "dcan2";
1422 reg = <0x48480000 0x2000>; 1464 reg = <0x48480000 0x2000>;
1423 syscon-raminit = <&dra7_ctrl_core 0x558 1>; 1465 syscon-raminit = <&scm_conf 0x558 1>;
1424 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1466 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1425 clocks = <&sys_clkin1>; 1467 clocks = <&sys_clkin1>;
1426 status = "disabled"; 1468 status = "disabled";
1427 }; 1469 };
1428 }; 1470 };
1471
1472 thermal_zones: thermal-zones {
1473 #include "omap4-cpu-thermal.dtsi"
1474 #include "omap5-gpu-thermal.dtsi"
1475 #include "omap5-core-thermal.dtsi"
1476 };
1477
1478};
1479
1480&cpu_thermal {
1481 polling-delay = <500>; /* milliseconds */
1429}; 1482};
1430 1483
1431/include/ "dra7xx-clocks.dtsi" 1484/include/ "dra7xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi
index e5a3d23a3df1..6ac8e3601499 100644
--- a/arch/arm/boot/dts/dra72x.dtsi
+++ b/arch/arm/boot/dts/dra72x.dtsi
@@ -20,6 +20,11 @@
20 device_type = "cpu"; 20 device_type = "cpu";
21 compatible = "arm,cortex-a15"; 21 compatible = "arm,cortex-a15";
22 reg = <0>; 22 reg = <0>;
23
24 /* cooling options */
25 cooling-min-level = <0>;
26 cooling-max-level = <2>;
27 #cooling-cells = <2>; /* min followed by max */
23 }; 28 };
24 }; 29 };
25 30
diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi
index 10173fab1a15..eef981f4bcd5 100644
--- a/arch/arm/boot/dts/dra74x.dtsi
+++ b/arch/arm/boot/dts/dra74x.dtsi
@@ -31,6 +31,11 @@
31 clock-names = "cpu"; 31 clock-names = "cpu";
32 32
33 clock-latency = <300000>; /* From omap-cpufreq driver */ 33 clock-latency = <300000>; /* From omap-cpufreq driver */
34
35 /* cooling options */
36 cooling-min-level = <0>;
37 cooling-max-level = <2>;
38 #cooling-cells = <2>; /* min followed by max */
34 }; 39 };
35 cpu@1 { 40 cpu@1 {
36 device_type = "cpu"; 41 device_type = "cpu";
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index e2b2e93d7b61..5b9a376cc31e 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -14,47 +14,65 @@
14 compatible = "ti,omap2420", "ti,omap2"; 14 compatible = "ti,omap2420", "ti,omap2";
15 15
16 ocp { 16 ocp {
17 prcm: prcm@48008000 { 17 l4: l4@48000000 {
18 compatible = "ti,omap2-prcm"; 18 compatible = "ti,omap2-l4", "simple-bus";
19 reg = <0x48008000 0x1000>; 19 #address-cells = <1>;
20 #size-cells = <1>;
21 ranges = <0 0x48000000 0x100000>;
20 22
21 prcm_clocks: clocks { 23 prcm: prcm@8000 {
22 #address-cells = <1>; 24 compatible = "ti,omap2-prcm";
23 #size-cells = <0>; 25 reg = <0x8000 0x1000>;
24 };
25 26
26 prcm_clockdomains: clockdomains { 27 prcm_clocks: clocks {
27 }; 28 #address-cells = <1>;
28 }; 29 #size-cells = <0>;
30 };
29 31
30 scrm: scrm@48000000 { 32 prcm_clockdomains: clockdomains {
31 compatible = "ti,omap2-scrm"; 33 };
32 reg = <0x48000000 0x1000>; 34 };
33 35
34 scrm_clocks: clocks { 36 scm: scm@0 {
37 compatible = "ti,omap2-scm", "simple-bus";
38 reg = <0x0 0x1000>;
35 #address-cells = <1>; 39 #address-cells = <1>;
36 #size-cells = <0>; 40 #size-cells = <1>;
41 ranges = <0 0x0 0x1000>;
42
43 omap2420_pmx: pinmux@30 {
44 compatible = "ti,omap2420-padconf",
45 "pinctrl-single";
46 reg = <0x30 0x0113>;
47 #address-cells = <1>;
48 #size-cells = <0>;
49 pinctrl-single,register-width = <8>;
50 pinctrl-single,function-mask = <0x3f>;
51 };
52
53 scm_conf: scm_conf@270 {
54 compatible = "syscon";
55 reg = <0x270 0x100>;
56 #address-cells = <1>;
57 #size-cells = <1>;
58
59 scm_clocks: clocks {
60 #address-cells = <1>;
61 #size-cells = <0>;
62 };
63 };
64
65 scm_clockdomains: clockdomains {
66 };
37 }; 67 };
38 68
39 scrm_clockdomains: clockdomains { 69 counter32k: counter@4000 {
70 compatible = "ti,omap-counter32k";
71 reg = <0x4000 0x20>;
72 ti,hwmods = "counter_32k";
40 }; 73 };
41 }; 74 };
42 75
43 counter32k: counter@48004000 {
44 compatible = "ti,omap-counter32k";
45 reg = <0x48004000 0x20>;
46 ti,hwmods = "counter_32k";
47 };
48
49 omap2420_pmx: pinmux@48000030 {
50 compatible = "ti,omap2420-padconf", "pinctrl-single";
51 reg = <0x48000030 0x0113>;
52 #address-cells = <1>;
53 #size-cells = <0>;
54 pinctrl-single,register-width = <8>;
55 pinctrl-single,function-mask = <0x3f>;
56 };
57
58 gpio1: gpio@48018000 { 76 gpio1: gpio@48018000 {
59 compatible = "ti,omap2-gpio"; 77 compatible = "ti,omap2-gpio";
60 reg = <0x48018000 0x200>; 78 reg = <0x48018000 0x200>;
diff --git a/arch/arm/boot/dts/omap2430-clocks.dtsi b/arch/arm/boot/dts/omap2430-clocks.dtsi
index 805f75df1cf2..93fed68839b9 100644
--- a/arch/arm/boot/dts/omap2430-clocks.dtsi
+++ b/arch/arm/boot/dts/omap2430-clocks.dtsi
@@ -8,12 +8,12 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11&scrm_clocks { 11&scm_clocks {
12 mcbsp3_mux_fck: mcbsp3_mux_fck { 12 mcbsp3_mux_fck: mcbsp3_mux_fck {
13 #clock-cells = <0>; 13 #clock-cells = <0>;
14 compatible = "ti,composite-mux-clock"; 14 compatible = "ti,composite-mux-clock";
15 clocks = <&func_96m_ck>, <&mcbsp_clks>; 15 clocks = <&func_96m_ck>, <&mcbsp_clks>;
16 reg = <0x02e8>; 16 reg = <0x78>;
17 }; 17 };
18 18
19 mcbsp3_fck: mcbsp3_fck { 19 mcbsp3_fck: mcbsp3_fck {
@@ -27,7 +27,7 @@
27 compatible = "ti,composite-mux-clock"; 27 compatible = "ti,composite-mux-clock";
28 clocks = <&func_96m_ck>, <&mcbsp_clks>; 28 clocks = <&func_96m_ck>, <&mcbsp_clks>;
29 ti,bit-shift = <2>; 29 ti,bit-shift = <2>;
30 reg = <0x02e8>; 30 reg = <0x78>;
31 }; 31 };
32 32
33 mcbsp4_fck: mcbsp4_fck { 33 mcbsp4_fck: mcbsp4_fck {
@@ -41,7 +41,7 @@
41 compatible = "ti,composite-mux-clock"; 41 compatible = "ti,composite-mux-clock";
42 clocks = <&func_96m_ck>, <&mcbsp_clks>; 42 clocks = <&func_96m_ck>, <&mcbsp_clks>;
43 ti,bit-shift = <4>; 43 ti,bit-shift = <4>;
44 reg = <0x02e8>; 44 reg = <0x78>;
45 }; 45 };
46 46
47 mcbsp5_fck: mcbsp5_fck { 47 mcbsp5_fck: mcbsp5_fck {
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index 0dc8de2782b1..11a7963be003 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -14,60 +14,73 @@
14 compatible = "ti,omap2430", "ti,omap2"; 14 compatible = "ti,omap2430", "ti,omap2";
15 15
16 ocp { 16 ocp {
17 prcm: prcm@49006000 { 17 l4_wkup: l4_wkup@49000000 {
18 compatible = "ti,omap2-prcm"; 18 compatible = "ti,omap2-l4-wkup", "simple-bus";
19 reg = <0x49006000 0x1000>; 19 #address-cells = <1>;
20 #size-cells = <1>;
21 ranges = <0 0x49000000 0x31000>;
20 22
21 prcm_clocks: clocks { 23 prcm: prcm@6000 {
22 #address-cells = <1>; 24 compatible = "ti,omap2-prcm";
23 #size-cells = <0>; 25 reg = <0x6000 0x1000>;
24 };
25 26
26 prcm_clockdomains: clockdomains { 27 prcm_clocks: clocks {
27 }; 28 #address-cells = <1>;
28 }; 29 #size-cells = <0>;
29 30 };
30 scrm: scrm@49002000 {
31 compatible = "ti,omap2-scrm";
32 reg = <0x49002000 0x1000>;
33 31
34 scrm_clocks: clocks { 32 prcm_clockdomains: clockdomains {
35 #address-cells = <1>; 33 };
36 #size-cells = <0>;
37 }; 34 };
38 35
39 scrm_clockdomains: clockdomains { 36 scm: scm@2000 {
37 compatible = "ti,omap2-scm", "simple-bus";
38 reg = <0x2000 0x1000>;
39 #address-cells = <1>;
40 #size-cells = <1>;
41 ranges = <0 0x2000 0x1000>;
42
43 omap2430_pmx: pinmux@30 {
44 compatible = "ti,omap2430-padconf",
45 "pinctrl-single";
46 reg = <0x30 0x0154>;
47 #address-cells = <1>;
48 #size-cells = <0>;
49 pinctrl-single,register-width = <8>;
50 pinctrl-single,function-mask = <0x3f>;
51 };
52
53 scm_conf: scm_conf@270 {
54 compatible = "syscon";
55 reg = <0x270 0x240>;
56 #address-cells = <1>;
57 #size-cells = <1>;
58
59 scm_clocks: clocks {
60 #address-cells = <1>;
61 #size-cells = <0>;
62 };
63
64 pbias_regulator: pbias_regulator {
65 compatible = "ti,pbias-omap";
66 reg = <0x230 0x4>;
67 syscon = <&scm_conf>;
68 pbias_mmc_reg: pbias_mmc_omap2430 {
69 regulator-name = "pbias_mmc_omap2430";
70 regulator-min-microvolt = <1800000>;
71 regulator-max-microvolt = <3000000>;
72 };
73 };
74 };
75
76 scm_clockdomains: clockdomains {
77 };
40 }; 78 };
41 };
42
43 counter32k: counter@49020000 {
44 compatible = "ti,omap-counter32k";
45 reg = <0x49020000 0x20>;
46 ti,hwmods = "counter_32k";
47 };
48
49 omap2430_pmx: pinmux@49002030 {
50 compatible = "ti,omap2430-padconf", "pinctrl-single";
51 reg = <0x49002030 0x0154>;
52 #address-cells = <1>;
53 #size-cells = <0>;
54 pinctrl-single,register-width = <8>;
55 pinctrl-single,function-mask = <0x3f>;
56 };
57
58 omap2_scm_general: tisyscon@49002270 {
59 compatible = "syscon";
60 reg = <0x49002270 0x240>;
61 };
62 79
63 pbias_regulator: pbias_regulator { 80 counter32k: counter@20000 {
64 compatible = "ti,pbias-omap"; 81 compatible = "ti,omap-counter32k";
65 reg = <0x230 0x4>; 82 reg = <0x20000 0x20>;
66 syscon = <&omap2_scm_general>; 83 ti,hwmods = "counter_32k";
67 pbias_mmc_reg: pbias_mmc_omap2430 {
68 regulator-name = "pbias_mmc_omap2430";
69 regulator-min-microvolt = <1800000>;
70 regulator-max-microvolt = <3000000>;
71 }; 84 };
72 }; 85 };
73 86
diff --git a/arch/arm/boot/dts/omap24xx-clocks.dtsi b/arch/arm/boot/dts/omap24xx-clocks.dtsi
index a1365ca926eb..63965b876973 100644
--- a/arch/arm/boot/dts/omap24xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap24xx-clocks.dtsi
@@ -7,13 +7,13 @@
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10&scrm_clocks { 10&scm_clocks {
11 mcbsp1_mux_fck: mcbsp1_mux_fck { 11 mcbsp1_mux_fck: mcbsp1_mux_fck {
12 #clock-cells = <0>; 12 #clock-cells = <0>;
13 compatible = "ti,composite-mux-clock"; 13 compatible = "ti,composite-mux-clock";
14 clocks = <&func_96m_ck>, <&mcbsp_clks>; 14 clocks = <&func_96m_ck>, <&mcbsp_clks>;
15 ti,bit-shift = <2>; 15 ti,bit-shift = <2>;
16 reg = <0x0274>; 16 reg = <0x4>;
17 }; 17 };
18 18
19 mcbsp1_fck: mcbsp1_fck { 19 mcbsp1_fck: mcbsp1_fck {
@@ -27,7 +27,7 @@
27 compatible = "ti,composite-mux-clock"; 27 compatible = "ti,composite-mux-clock";
28 clocks = <&func_96m_ck>, <&mcbsp_clks>; 28 clocks = <&func_96m_ck>, <&mcbsp_clks>;
29 ti,bit-shift = <6>; 29 ti,bit-shift = <6>;
30 reg = <0x0274>; 30 reg = <0x4>;
31 }; 31 };
32 32
33 mcbsp2_fck: mcbsp2_fck { 33 mcbsp2_fck: mcbsp2_fck {
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index f4f78c40b564..02cd996d0b06 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -87,6 +87,60 @@
87 ranges; 87 ranges;
88 ti,hwmods = "l3_main"; 88 ti,hwmods = "l3_main";
89 89
90 l4_core: l4@48000000 {
91 compatible = "ti,omap3-l4-core", "simple-bus";
92 #address-cells = <1>;
93 #size-cells = <1>;
94 ranges = <0 0x48000000 0x1000000>;
95
96 scm: scm@2000 {
97 compatible = "ti,omap3-scm", "simple-bus";
98 reg = <0x2000 0x2000>;
99 #address-cells = <1>;
100 #size-cells = <1>;
101 ranges = <0 0x2000 0x2000>;
102
103 omap3_pmx_core: pinmux@30 {
104 compatible = "ti,omap3-padconf",
105 "pinctrl-single";
106 reg = <0x30 0x238>;
107 #address-cells = <1>;
108 #size-cells = <0>;
109 #interrupt-cells = <1>;
110 interrupt-controller;
111 pinctrl-single,register-width = <16>;
112 pinctrl-single,function-mask = <0xff1f>;
113 };
114
115 scm_conf: scm_conf@270 {
116 compatible = "syscon";
117 reg = <0x270 0x330>;
118 #address-cells = <1>;
119 #size-cells = <1>;
120
121 scm_clocks: clocks {
122 #address-cells = <1>;
123 #size-cells = <0>;
124 };
125 };
126
127 scm_clockdomains: clockdomains {
128 };
129
130 omap3_pmx_wkup: pinmux@a00 {
131 compatible = "ti,omap3-padconf",
132 "pinctrl-single";
133 reg = <0xa00 0x5c>;
134 #address-cells = <1>;
135 #size-cells = <0>;
136 #interrupt-cells = <1>;
137 interrupt-controller;
138 pinctrl-single,register-width = <16>;
139 pinctrl-single,function-mask = <0xff1f>;
140 };
141 };
142 };
143
90 aes: aes@480c5000 { 144 aes: aes@480c5000 {
91 compatible = "ti,omap3-aes"; 145 compatible = "ti,omap3-aes";
92 ti,hwmods = "aes"; 146 ti,hwmods = "aes";
@@ -121,19 +175,6 @@
121 }; 175 };
122 }; 176 };
123 177
124 scrm: scrm@48002000 {
125 compatible = "ti,omap3-scrm";
126 reg = <0x48002000 0x2000>;
127
128 scrm_clocks: clocks {
129 #address-cells = <1>;
130 #size-cells = <0>;
131 };
132
133 scrm_clockdomains: clockdomains {
134 };
135 };
136
137 counter32k: counter@48320000 { 178 counter32k: counter@48320000 {
138 compatible = "ti,omap-counter32k"; 179 compatible = "ti,omap-counter32k";
139 reg = <0x48320000 0x20>; 180 reg = <0x48320000 0x20>;
@@ -159,37 +200,10 @@
159 dma-requests = <96>; 200 dma-requests = <96>;
160 }; 201 };
161 202
162 omap3_pmx_core: pinmux@48002030 {
163 compatible = "ti,omap3-padconf", "pinctrl-single";
164 reg = <0x48002030 0x0238>;
165 #address-cells = <1>;
166 #size-cells = <0>;
167 #interrupt-cells = <1>;
168 interrupt-controller;
169 pinctrl-single,register-width = <16>;
170 pinctrl-single,function-mask = <0xff1f>;
171 };
172
173 omap3_pmx_wkup: pinmux@48002a00 {
174 compatible = "ti,omap3-padconf", "pinctrl-single";
175 reg = <0x48002a00 0x5c>;
176 #address-cells = <1>;
177 #size-cells = <0>;
178 #interrupt-cells = <1>;
179 interrupt-controller;
180 pinctrl-single,register-width = <16>;
181 pinctrl-single,function-mask = <0xff1f>;
182 };
183
184 omap3_scm_general: tisyscon@48002270 {
185 compatible = "syscon";
186 reg = <0x48002270 0x2f0>;
187 };
188
189 pbias_regulator: pbias_regulator { 203 pbias_regulator: pbias_regulator {
190 compatible = "ti,pbias-omap"; 204 compatible = "ti,pbias-omap";
191 reg = <0x2b0 0x4>; 205 reg = <0x2b0 0x4>;
192 syscon = <&omap3_scm_general>; 206 syscon = <&scm_conf>;
193 pbias_mmc_reg: pbias_mmc_omap2430 { 207 pbias_mmc_reg: pbias_mmc_omap2430 {
194 regulator-name = "pbias_mmc_omap2430"; 208 regulator-name = "pbias_mmc_omap2430";
195 regulator-min-microvolt = <1800000>; 209 regulator-min-microvolt = <1800000>;
diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
index 5c375003bad1..bbba5bdc4bc9 100644
--- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
@@ -79,13 +79,14 @@
79 clock-div = <1>; 79 clock-div = <1>;
80 }; 80 };
81}; 81};
82&scrm_clocks { 82
83&scm_clocks {
83 mcbsp5_mux_fck: mcbsp5_mux_fck { 84 mcbsp5_mux_fck: mcbsp5_mux_fck {
84 #clock-cells = <0>; 85 #clock-cells = <0>;
85 compatible = "ti,composite-mux-clock"; 86 compatible = "ti,composite-mux-clock";
86 clocks = <&core_96m_fck>, <&mcbsp_clks>; 87 clocks = <&core_96m_fck>, <&mcbsp_clks>;
87 ti,bit-shift = <4>; 88 ti,bit-shift = <4>;
88 reg = <0x02d8>; 89 reg = <0x68>;
89 }; 90 };
90 91
91 mcbsp5_fck: mcbsp5_fck { 92 mcbsp5_fck: mcbsp5_fck {
@@ -99,7 +100,7 @@
99 compatible = "ti,composite-mux-clock"; 100 compatible = "ti,composite-mux-clock";
100 clocks = <&core_96m_fck>, <&mcbsp_clks>; 101 clocks = <&core_96m_fck>, <&mcbsp_clks>;
101 ti,bit-shift = <2>; 102 ti,bit-shift = <2>;
102 reg = <0x0274>; 103 reg = <0x04>;
103 }; 104 };
104 105
105 mcbsp1_fck: mcbsp1_fck { 106 mcbsp1_fck: mcbsp1_fck {
@@ -113,7 +114,7 @@
113 compatible = "ti,composite-mux-clock"; 114 compatible = "ti,composite-mux-clock";
114 clocks = <&per_96m_fck>, <&mcbsp_clks>; 115 clocks = <&per_96m_fck>, <&mcbsp_clks>;
115 ti,bit-shift = <6>; 116 ti,bit-shift = <6>;
116 reg = <0x0274>; 117 reg = <0x04>;
117 }; 118 };
118 119
119 mcbsp2_fck: mcbsp2_fck { 120 mcbsp2_fck: mcbsp2_fck {
@@ -126,7 +127,7 @@
126 #clock-cells = <0>; 127 #clock-cells = <0>;
127 compatible = "ti,composite-mux-clock"; 128 compatible = "ti,composite-mux-clock";
128 clocks = <&per_96m_fck>, <&mcbsp_clks>; 129 clocks = <&per_96m_fck>, <&mcbsp_clks>;
129 reg = <0x02d8>; 130 reg = <0x68>;
130 }; 131 };
131 132
132 mcbsp3_fck: mcbsp3_fck { 133 mcbsp3_fck: mcbsp3_fck {
@@ -140,7 +141,7 @@
140 compatible = "ti,composite-mux-clock"; 141 compatible = "ti,composite-mux-clock";
141 clocks = <&per_96m_fck>, <&mcbsp_clks>; 142 clocks = <&per_96m_fck>, <&mcbsp_clks>;
142 ti,bit-shift = <2>; 143 ti,bit-shift = <2>;
143 reg = <0x02d8>; 144 reg = <0x68>;
144 }; 145 };
145 146
146 mcbsp4_fck: mcbsp4_fck { 147 mcbsp4_fck: mcbsp4_fck {
diff --git a/arch/arm/boot/dts/omap4-cpu-thermal.dtsi b/arch/arm/boot/dts/omap4-cpu-thermal.dtsi
index cb9458feb2e3..ab7f87ae96f0 100644
--- a/arch/arm/boot/dts/omap4-cpu-thermal.dtsi
+++ b/arch/arm/boot/dts/omap4-cpu-thermal.dtsi
@@ -18,7 +18,7 @@ cpu_thermal: cpu_thermal {
18 /* sensor ID */ 18 /* sensor ID */
19 thermal-sensors = <&bandgap 0>; 19 thermal-sensors = <&bandgap 0>;
20 20
21 trips { 21 cpu_trips: trips {
22 cpu_alert0: cpu_alert { 22 cpu_alert0: cpu_alert {
23 temperature = <100000>; /* millicelsius */ 23 temperature = <100000>; /* millicelsius */
24 hysteresis = <2000>; /* millicelsius */ 24 hysteresis = <2000>; /* millicelsius */
@@ -31,7 +31,7 @@ cpu_thermal: cpu_thermal {
31 }; 31 };
32 }; 32 };
33 33
34 cooling-maps { 34 cpu_cooling_maps: cooling-maps {
35 map0 { 35 map0 {
36 trip = <&cpu_alert0>; 36 trip = <&cpu_alert0>;
37 cooling-device = 37 cooling-device =
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 87401d9f4d8b..cf2681b2d173 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -114,99 +114,141 @@
114 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 114 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
115 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 115 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
116 116
117 cm1: cm1@4a004000 { 117 l4_cfg: l4@4a000000 {
118 compatible = "ti,omap4-cm1"; 118 compatible = "ti,omap4-l4-cfg", "simple-bus";
119 reg = <0x4a004000 0x2000>; 119 #address-cells = <1>;
120 120 #size-cells = <1>;
121 cm1_clocks: clocks { 121 ranges = <0 0x4a000000 0x1000000>;
122 #address-cells = <1>;
123 #size-cells = <0>;
124 };
125 122
126 cm1_clockdomains: clockdomains { 123 cm1: cm1@4000 {
127 }; 124 compatible = "ti,omap4-cm1";
128 }; 125 reg = <0x4000 0x2000>;
129 126
130 prm: prm@4a306000 { 127 cm1_clocks: clocks {
131 compatible = "ti,omap4-prm"; 128 #address-cells = <1>;
132 reg = <0x4a306000 0x3000>; 129 #size-cells = <0>;
133 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 130 };
134 131
135 prm_clocks: clocks { 132 cm1_clockdomains: clockdomains {
136 #address-cells = <1>; 133 };
137 #size-cells = <0>;
138 }; 134 };
139 135
140 prm_clockdomains: clockdomains { 136 cm2: cm2@8000 {
141 }; 137 compatible = "ti,omap4-cm2";
142 }; 138 reg = <0x8000 0x3000>;
143 139
144 cm2: cm2@4a008000 { 140 cm2_clocks: clocks {
145 compatible = "ti,omap4-cm2"; 141 #address-cells = <1>;
146 reg = <0x4a008000 0x3000>; 142 #size-cells = <0>;
143 };
147 144
148 cm2_clocks: clocks { 145 cm2_clockdomains: clockdomains {
149 #address-cells = <1>; 146 };
150 #size-cells = <0>;
151 }; 147 };
152 148
153 cm2_clockdomains: clockdomains { 149 omap4_scm_core: scm@2000 {
150 compatible = "ti,omap4-scm-core", "simple-bus";
151 reg = <0x2000 0x1000>;
152 #address-cells = <1>;
153 #size-cells = <1>;
154 ranges = <0 0x2000 0x1000>;
155
156 scm_conf: scm_conf@0 {
157 compatible = "syscon";
158 reg = <0x0 0x800>;
159 #address-cells = <1>;
160 #size-cells = <1>;
161 };
154 }; 162 };
155 };
156
157 scrm: scrm@4a30a000 {
158 compatible = "ti,omap4-scrm";
159 reg = <0x4a30a000 0x2000>;
160 163
161 scrm_clocks: clocks { 164 omap4_padconf_core: scm@100000 {
165 compatible = "ti,omap4-scm-padconf-core",
166 "simple-bus";
162 #address-cells = <1>; 167 #address-cells = <1>;
163 #size-cells = <0>; 168 #size-cells = <1>;
169 ranges = <0 0x100000 0x1000>;
170
171 omap4_pmx_core: pinmux@40 {
172 compatible = "ti,omap4-padconf",
173 "pinctrl-single";
174 reg = <0x40 0x0196>;
175 #address-cells = <1>;
176 #size-cells = <0>;
177 #interrupt-cells = <1>;
178 interrupt-controller;
179 pinctrl-single,register-width = <16>;
180 pinctrl-single,function-mask = <0x7fff>;
181 };
182
183 omap4_padconf_global: omap4_padconf_global@5a0 {
184 compatible = "syscon";
185 reg = <0x5a0 0x170>;
186 #address-cells = <1>;
187 #size-cells = <1>;
188
189 pbias_regulator: pbias_regulator {
190 compatible = "ti,pbias-omap";
191 reg = <0x60 0x4>;
192 syscon = <&omap4_padconf_global>;
193 pbias_mmc_reg: pbias_mmc_omap4 {
194 regulator-name = "pbias_mmc_omap4";
195 regulator-min-microvolt = <1800000>;
196 regulator-max-microvolt = <3000000>;
197 };
198 };
199 };
164 }; 200 };
165 201
166 scrm_clockdomains: clockdomains { 202 l4_wkup: l4@300000 {
167 }; 203 compatible = "ti,omap4-l4-wkup", "simple-bus";
168 }; 204 #address-cells = <1>;
169 205 #size-cells = <1>;
170 counter32k: counter@4a304000 { 206 ranges = <0 0x300000 0x40000>;
171 compatible = "ti,omap-counter32k"; 207
172 reg = <0x4a304000 0x20>; 208 counter32k: counter@4000 {
173 ti,hwmods = "counter_32k"; 209 compatible = "ti,omap-counter32k";
174 }; 210 reg = <0x4000 0x20>;
175 211 ti,hwmods = "counter_32k";
176 omap4_pmx_core: pinmux@4a100040 { 212 };
177 compatible = "ti,omap4-padconf", "pinctrl-single"; 213
178 reg = <0x4a100040 0x0196>; 214 prm: prm@6000 {
179 #address-cells = <1>; 215 compatible = "ti,omap4-prm";
180 #size-cells = <0>; 216 reg = <0x6000 0x3000>;
181 #interrupt-cells = <1>; 217 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
182 interrupt-controller; 218
183 pinctrl-single,register-width = <16>; 219 prm_clocks: clocks {
184 pinctrl-single,function-mask = <0x7fff>; 220 #address-cells = <1>;
185 }; 221 #size-cells = <0>;
186 omap4_pmx_wkup: pinmux@4a31e040 { 222 };
187 compatible = "ti,omap4-padconf", "pinctrl-single"; 223
188 reg = <0x4a31e040 0x0038>; 224 prm_clockdomains: clockdomains {
189 #address-cells = <1>; 225 };
190 #size-cells = <0>; 226 };
191 #interrupt-cells = <1>; 227
192 interrupt-controller; 228 scrm: scrm@a000 {
193 pinctrl-single,register-width = <16>; 229 compatible = "ti,omap4-scrm";
194 pinctrl-single,function-mask = <0x7fff>; 230 reg = <0xa000 0x2000>;
195 }; 231
196 232 scrm_clocks: clocks {
197 omap4_padconf_global: tisyscon@4a1005a0 { 233 #address-cells = <1>;
198 compatible = "syscon"; 234 #size-cells = <0>;
199 reg = <0x4a1005a0 0x170>; 235 };
200 }; 236
201 237 scrm_clockdomains: clockdomains {
202 pbias_regulator: pbias_regulator { 238 };
203 compatible = "ti,pbias-omap"; 239 };
204 reg = <0x60 0x4>; 240
205 syscon = <&omap4_padconf_global>; 241 omap4_pmx_wkup: pinmux@1e040 {
206 pbias_mmc_reg: pbias_mmc_omap4 { 242 compatible = "ti,omap4-padconf",
207 regulator-name = "pbias_mmc_omap4"; 243 "pinctrl-single";
208 regulator-min-microvolt = <1800000>; 244 reg = <0x1e040 0x0038>;
209 regulator-max-microvolt = <3000000>; 245 #address-cells = <1>;
246 #size-cells = <0>;
247 #interrupt-cells = <1>;
248 interrupt-controller;
249 pinctrl-single,register-width = <16>;
250 pinctrl-single,function-mask = <0x7fff>;
251 };
210 }; 252 };
211 }; 253 };
212 254
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index ddff674bd05e..3cdb5c22148d 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -129,99 +129,141 @@
129 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 129 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
130 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 130 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
131 131
132 prm: prm@4ae06000 { 132 l4_cfg: l4@4a000000 {
133 compatible = "ti,omap5-prm"; 133 compatible = "ti,omap5-l4-cfg", "simple-bus";
134 reg = <0x4ae06000 0x3000>; 134 #address-cells = <1>;
135 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 135 #size-cells = <1>;
136 ranges = <0 0x4a000000 0x22a000>;
136 137
137 prm_clocks: clocks { 138 scm_core: scm@2000 {
139 compatible = "ti,omap5-scm-core", "simple-bus";
140 reg = <0x2000 0x1000>;
138 #address-cells = <1>; 141 #address-cells = <1>;
139 #size-cells = <0>; 142 #size-cells = <1>;
143 ranges = <0 0x2000 0x800>;
144
145 scm_conf: scm_conf@0 {
146 compatible = "syscon";
147 reg = <0x0 0x800>;
148 #address-cells = <1>;
149 #size-cells = <1>;
150 };
140 }; 151 };
141 152
142 prm_clockdomains: clockdomains { 153 scm_padconf_core: scm@2800 {
154 compatible = "ti,omap5-scm-padconf-core",
155 "simple-bus";
156 #address-cells = <1>;
157 #size-cells = <1>;
158 ranges = <0 0x2800 0x800>;
159
160 omap5_pmx_core: pinmux@40 {
161 compatible = "ti,omap5-padconf",
162 "pinctrl-single";
163 reg = <0x40 0x01b6>;
164 #address-cells = <1>;
165 #size-cells = <0>;
166 #interrupt-cells = <1>;
167 interrupt-controller;
168 pinctrl-single,register-width = <16>;
169 pinctrl-single,function-mask = <0x7fff>;
170 };
171
172 omap5_padconf_global: omap5_padconf_global@5a0 {
173 compatible = "syscon";
174 reg = <0x5a0 0xec>;
175 #address-cells = <1>;
176 #size-cells = <1>;
177
178 pbias_regulator: pbias_regulator {
179 compatible = "ti,pbias-omap";
180 reg = <0x60 0x4>;
181 syscon = <&omap5_padconf_global>;
182 pbias_mmc_reg: pbias_mmc_omap5 {
183 regulator-name = "pbias_mmc_omap5";
184 regulator-min-microvolt = <1800000>;
185 regulator-max-microvolt = <3000000>;
186 };
187 };
188 };
143 }; 189 };
144 };
145 190
146 cm_core_aon: cm_core_aon@4a004000 { 191 cm_core_aon: cm_core_aon@4000 {
147 compatible = "ti,omap5-cm-core-aon"; 192 compatible = "ti,omap5-cm-core-aon";
148 reg = <0x4a004000 0x2000>; 193 reg = <0x4000 0x2000>;
149 194
150 cm_core_aon_clocks: clocks { 195 cm_core_aon_clocks: clocks {
151 #address-cells = <1>; 196 #address-cells = <1>;
152 #size-cells = <0>; 197 #size-cells = <0>;
153 }; 198 };
154 199
155 cm_core_aon_clockdomains: clockdomains { 200 cm_core_aon_clockdomains: clockdomains {
201 };
156 }; 202 };
157 };
158 203
159 scrm: scrm@4ae0a000 { 204 cm_core: cm_core@8000 {
160 compatible = "ti,omap5-scrm"; 205 compatible = "ti,omap5-cm-core";
161 reg = <0x4ae0a000 0x2000>; 206 reg = <0x8000 0x3000>;
162 207
163 scrm_clocks: clocks { 208 cm_core_clocks: clocks {
164 #address-cells = <1>; 209 #address-cells = <1>;
165 #size-cells = <0>; 210 #size-cells = <0>;
166 }; 211 };
167 212
168 scrm_clockdomains: clockdomains { 213 cm_core_clockdomains: clockdomains {
214 };
169 }; 215 };
170 }; 216 };
171 217
172 cm_core: cm_core@4a008000 { 218 l4_wkup: l4@4ae00000 {
173 compatible = "ti,omap5-cm-core"; 219 compatible = "ti,omap5-l4-wkup", "simple-bus";
174 reg = <0x4a008000 0x3000>; 220 #address-cells = <1>;
221 #size-cells = <1>;
222 ranges = <0 0x4ae00000 0x2b000>;
175 223
176 cm_core_clocks: clocks { 224 counter32k: counter@4000 {
177 #address-cells = <1>; 225 compatible = "ti,omap-counter32k";
178 #size-cells = <0>; 226 reg = <0x4000 0x40>;
227 ti,hwmods = "counter_32k";
179 }; 228 };
180 229
181 cm_core_clockdomains: clockdomains { 230 prm: prm@6000 {
231 compatible = "ti,omap5-prm";
232 reg = <0x6000 0x3000>;
233 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
234
235 prm_clocks: clocks {
236 #address-cells = <1>;
237 #size-cells = <0>;
238 };
239
240 prm_clockdomains: clockdomains {
241 };
182 }; 242 };
183 };
184 243
185 counter32k: counter@4ae04000 { 244 scrm: scrm@a000 {
186 compatible = "ti,omap-counter32k"; 245 compatible = "ti,omap5-scrm";
187 reg = <0x4ae04000 0x40>; 246 reg = <0xa000 0x2000>;
188 ti,hwmods = "counter_32k";
189 };
190 247
191 omap5_pmx_core: pinmux@4a002840 { 248 scrm_clocks: clocks {
192 compatible = "ti,omap5-padconf", "pinctrl-single"; 249 #address-cells = <1>;
193 reg = <0x4a002840 0x01b6>; 250 #size-cells = <0>;
194 #address-cells = <1>; 251 };
195 #size-cells = <0>;
196 #interrupt-cells = <1>;
197 interrupt-controller;
198 pinctrl-single,register-width = <16>;
199 pinctrl-single,function-mask = <0x7fff>;
200 };
201 omap5_pmx_wkup: pinmux@4ae0c840 {
202 compatible = "ti,omap5-padconf", "pinctrl-single";
203 reg = <0x4ae0c840 0x0038>;
204 #address-cells = <1>;
205 #size-cells = <0>;
206 #interrupt-cells = <1>;
207 interrupt-controller;
208 pinctrl-single,register-width = <16>;
209 pinctrl-single,function-mask = <0x7fff>;
210 };
211 252
212 omap5_padconf_global: tisyscon@4a002da0 { 253 scrm_clockdomains: clockdomains {
213 compatible = "syscon"; 254 };
214 reg = <0x4A002da0 0xec>; 255 };
215 };
216 256
217 pbias_regulator: pbias_regulator { 257 omap5_pmx_wkup: pinmux@c840 {
218 compatible = "ti,pbias-omap"; 258 compatible = "ti,omap5-padconf",
219 reg = <0x60 0x4>; 259 "pinctrl-single";
220 syscon = <&omap5_padconf_global>; 260 reg = <0xc840 0x0038>;
221 pbias_mmc_reg: pbias_mmc_omap5 { 261 #address-cells = <1>;
222 regulator-name = "pbias_mmc_omap5"; 262 #size-cells = <0>;
223 regulator-min-microvolt = <1800000>; 263 #interrupt-cells = <1>;
224 regulator-max-microvolt = <3000000>; 264 interrupt-controller;
265 pinctrl-single,register-width = <16>;
266 pinctrl-single,function-mask = <0x7fff>;
225 }; 267 };
226 }; 268 };
227 269
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-31 19:27:29 -0400