diff options
| author | Laxman Dewangan <ldewangan@nvidia.com> | 2013-12-05 05:44:09 -0500 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2013-12-16 16:09:20 -0500 |
| commit | a47c662aad72cbabdb0e8df6c25c47c68b400e40 (patch) | |
| tree | 08f552fd4229686cf54db0a06eb1d911c7aec563 /arch/arm/boot/dts/tegra30-cardhu.dtsi | |
| parent | ba4104e79470ae848a9f38029fe1371790dc0df9 (diff) | |
ARM: tegra: convert dts files of Tegra30 platforms to use pinctrl defines
Use Tegra pinconrol dt-binding macro to set the values of different pinmux
properties of Tegra30 platforms.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra30-cardhu.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/tegra30-cardhu.dtsi | 40 |
1 files changed, 20 insertions, 20 deletions
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 748b4ba945ee..f3aab9eb6453 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi | |||
| @@ -59,8 +59,8 @@ | |||
| 59 | sdmmc1_clk_pz0 { | 59 | sdmmc1_clk_pz0 { |
| 60 | nvidia,pins = "sdmmc1_clk_pz0"; | 60 | nvidia,pins = "sdmmc1_clk_pz0"; |
| 61 | nvidia,function = "sdmmc1"; | 61 | nvidia,function = "sdmmc1"; |
| 62 | nvidia,pull = <0>; | 62 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 63 | nvidia,tristate = <0>; | 63 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 64 | }; | 64 | }; |
| 65 | sdmmc1_cmd_pz1 { | 65 | sdmmc1_cmd_pz1 { |
| 66 | nvidia,pins = "sdmmc1_cmd_pz1", | 66 | nvidia,pins = "sdmmc1_cmd_pz1", |
| @@ -69,14 +69,14 @@ | |||
| 69 | "sdmmc1_dat2_py5", | 69 | "sdmmc1_dat2_py5", |
| 70 | "sdmmc1_dat3_py4"; | 70 | "sdmmc1_dat3_py4"; |
| 71 | nvidia,function = "sdmmc1"; | 71 | nvidia,function = "sdmmc1"; |
| 72 | nvidia,pull = <2>; | 72 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 73 | nvidia,tristate = <0>; | 73 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 74 | }; | 74 | }; |
| 75 | sdmmc3_clk_pa6 { | 75 | sdmmc3_clk_pa6 { |
| 76 | nvidia,pins = "sdmmc3_clk_pa6"; | 76 | nvidia,pins = "sdmmc3_clk_pa6"; |
| 77 | nvidia,function = "sdmmc3"; | 77 | nvidia,function = "sdmmc3"; |
| 78 | nvidia,pull = <0>; | 78 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 79 | nvidia,tristate = <0>; | 79 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 80 | }; | 80 | }; |
| 81 | sdmmc3_cmd_pa7 { | 81 | sdmmc3_cmd_pa7 { |
| 82 | nvidia,pins = "sdmmc3_cmd_pa7", | 82 | nvidia,pins = "sdmmc3_cmd_pa7", |
| @@ -85,15 +85,15 @@ | |||
| 85 | "sdmmc3_dat2_pb5", | 85 | "sdmmc3_dat2_pb5", |
| 86 | "sdmmc3_dat3_pb4"; | 86 | "sdmmc3_dat3_pb4"; |
| 87 | nvidia,function = "sdmmc3"; | 87 | nvidia,function = "sdmmc3"; |
| 88 | nvidia,pull = <2>; | 88 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 89 | nvidia,tristate = <0>; | 89 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 90 | }; | 90 | }; |
| 91 | sdmmc4_clk_pcc4 { | 91 | sdmmc4_clk_pcc4 { |
| 92 | nvidia,pins = "sdmmc4_clk_pcc4", | 92 | nvidia,pins = "sdmmc4_clk_pcc4", |
| 93 | "sdmmc4_rst_n_pcc3"; | 93 | "sdmmc4_rst_n_pcc3"; |
| 94 | nvidia,function = "sdmmc4"; | 94 | nvidia,function = "sdmmc4"; |
| 95 | nvidia,pull = <0>; | 95 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 96 | nvidia,tristate = <0>; | 96 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 97 | }; | 97 | }; |
| 98 | sdmmc4_dat0_paa0 { | 98 | sdmmc4_dat0_paa0 { |
| 99 | nvidia,pins = "sdmmc4_dat0_paa0", | 99 | nvidia,pins = "sdmmc4_dat0_paa0", |
| @@ -105,8 +105,8 @@ | |||
| 105 | "sdmmc4_dat6_paa6", | 105 | "sdmmc4_dat6_paa6", |
| 106 | "sdmmc4_dat7_paa7"; | 106 | "sdmmc4_dat7_paa7"; |
| 107 | nvidia,function = "sdmmc4"; | 107 | nvidia,function = "sdmmc4"; |
| 108 | nvidia,pull = <2>; | 108 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 109 | nvidia,tristate = <0>; | 109 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 110 | }; | 110 | }; |
| 111 | dap2_fs_pa2 { | 111 | dap2_fs_pa2 { |
| 112 | nvidia,pins = "dap2_fs_pa2", | 112 | nvidia,pins = "dap2_fs_pa2", |
| @@ -114,17 +114,17 @@ | |||
| 114 | "dap2_din_pa4", | 114 | "dap2_din_pa4", |
| 115 | "dap2_dout_pa5"; | 115 | "dap2_dout_pa5"; |
| 116 | nvidia,function = "i2s1"; | 116 | nvidia,function = "i2s1"; |
| 117 | nvidia,pull = <0>; | 117 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 118 | nvidia,tristate = <0>; | 118 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 119 | }; | 119 | }; |
| 120 | sdio3 { | 120 | sdio3 { |
| 121 | nvidia,pins = "drive_sdio3"; | 121 | nvidia,pins = "drive_sdio3"; |
| 122 | nvidia,high-speed-mode = <0>; | 122 | nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; |
| 123 | nvidia,schmitt = <0>; | 123 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; |
| 124 | nvidia,pull-down-strength = <46>; | 124 | nvidia,pull-down-strength = <46>; |
| 125 | nvidia,pull-up-strength = <42>; | 125 | nvidia,pull-up-strength = <42>; |
| 126 | nvidia,slew-rate-rising = <1>; | 126 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>; |
| 127 | nvidia,slew-rate-falling = <1>; | 127 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>; |
| 128 | }; | 128 | }; |
| 129 | uart3_txd_pw6 { | 129 | uart3_txd_pw6 { |
| 130 | nvidia,pins = "uart3_txd_pw6", | 130 | nvidia,pins = "uart3_txd_pw6", |
| @@ -132,8 +132,8 @@ | |||
| 132 | "uart3_rts_n_pc0", | 132 | "uart3_rts_n_pc0", |
| 133 | "uart3_rxd_pw7"; | 133 | "uart3_rxd_pw7"; |
| 134 | nvidia,function = "uartc"; | 134 | nvidia,function = "uartc"; |
| 135 | nvidia,pull = <0>; | 135 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 136 | nvidia,tristate = <0>; | 136 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 137 | }; | 137 | }; |
| 138 | }; | 138 | }; |
| 139 | }; | 139 | }; |