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authorLinus Walleij <linus.walleij@linaro.org>2014-09-30 06:16:25 -0400
committerLinus Walleij <linus.walleij@linaro.org>2014-10-20 03:08:26 -0400
commit1637d480f873ca305f7f090e3b3bc92430b5892f (patch)
treec254049d778fe41f11b35623561173873c6a1177 /arch/arm/boot/dts/ste-hrefv60plus.dtsi
parent51d39936acba666774b596829277db3e13e5e970 (diff)
pinctrl: nomadik: force-convert to generic config bindings
This converts the Nomadik pin controller and all associated device trees to use the standard, generic config bindings for pin controllers. There are no such device trees deployed in the wild so this is safe to do to set a good example. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/ste-hrefv60plus.dtsi')
-rw-r--r--arch/arm/boot/dts/ste-hrefv60plus.dtsi38
1 files changed, 19 insertions, 19 deletions
diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/ste-hrefv60plus.dtsi
index 2b4104ef07de..a4bc9e77d640 100644
--- a/arch/arm/boot/dts/ste-hrefv60plus.dtsi
+++ b/arch/arm/boot/dts/ste-hrefv60plus.dtsi
@@ -49,7 +49,7 @@
49 /* SD card detect GPIO pin, extend default state */ 49 /* SD card detect GPIO pin, extend default state */
50 sdi0_default_mode: sdi0_default { 50 sdi0_default_mode: sdi0_default {
51 default_hrefv60_cfg1 { 51 default_hrefv60_cfg1 {
52 ste,pins = "GPIO95_E8"; 52 pins = "GPIO95_E8";
53 ste,config = <&gpio_in_pu>; 53 ste,config = <&gpio_in_pu>;
54 }; 54 };
55 }; 55 };
@@ -68,15 +68,15 @@
68 groups = "ipgpio0_c_1", "ipgpio1_c_1", "ipgpio4_c_1"; 68 groups = "ipgpio0_c_1", "ipgpio1_c_1", "ipgpio4_c_1";
69 }; 69 };
70 hrefv60_cfg1 { 70 hrefv60_cfg1 {
71 ste,pins = "GPIO6_AF6", "GPIO7_AG5"; 71 pins = "GPIO6_AF6", "GPIO7_AG5";
72 ste,config = <&in_pu>; 72 ste,config = <&in_pu>;
73 }; 73 };
74 hrefv60_cfg2 { 74 hrefv60_cfg2 {
75 ste,pins = "GPIO21_AB3"; 75 pins = "GPIO21_AB3";
76 ste,config = <&gpio_out_lo>; 76 ste,config = <&gpio_out_lo>;
77 }; 77 };
78 hrefv60_cfg3 { 78 hrefv60_cfg3 {
79 ste,pins = "GPIO64_F3"; 79 pins = "GPIO64_F3";
80 ste,config = <&out_lo>; 80 ste,config = <&out_lo>;
81 }; 81 };
82 }; 82 };
@@ -89,7 +89,7 @@
89 */ 89 */
90 etm_hrefv60_mode: etm_hrefv60 { 90 etm_hrefv60_mode: etm_hrefv60 {
91 hrefv60_cfg1 { 91 hrefv60_cfg1 {
92 ste,pins = 92 pins =
93 "GPIO70_G5", 93 "GPIO70_G5",
94 "GPIO71_G4", 94 "GPIO71_G4",
95 "GPIO72_H4", 95 "GPIO72_H4",
@@ -103,11 +103,11 @@
103 nahj_hrefv60_mode: nahj_hrefv60 { 103 nahj_hrefv60_mode: nahj_hrefv60 {
104 /* NAHJ CTRL on GPIO76 to low, CTRL_INV on GPIO216 to high */ 104 /* NAHJ CTRL on GPIO76 to low, CTRL_INV on GPIO216 to high */
105 hrefv60_cfg1 { 105 hrefv60_cfg1 {
106 ste,pins = "GPIO76_J2"; 106 pins = "GPIO76_J2";
107 ste,config = <&gpio_out_lo>; 107 ste,config = <&gpio_out_lo>;
108 }; 108 };
109 hrefv60_cfg2 { 109 hrefv60_cfg2 {
110 ste,pins = "GPIO216_AG12"; 110 pins = "GPIO216_AG12";
111 ste,config = <&gpio_out_hi>; 111 ste,config = <&gpio_out_hi>;
112 }; 112 };
113 }; 113 };
@@ -116,13 +116,13 @@
116 nfc_hrefv60_mode: nfc_hrefv60 { 116 nfc_hrefv60_mode: nfc_hrefv60 {
117 /* NFC ENA and RESET to low, pulldown IRQ line */ 117 /* NFC ENA and RESET to low, pulldown IRQ line */
118 hrefv60_cfg1 { 118 hrefv60_cfg1 {
119 ste,pins = 119 pins =
120 "GPIO77_H1", /* NFC_ENA */ 120 "GPIO77_H1", /* NFC_ENA */
121 "GPIO142_C11"; /* NFC_RESET */ 121 "GPIO142_C11"; /* NFC_RESET */
122 ste,config = <&gpio_out_lo>; 122 ste,config = <&gpio_out_lo>;
123 }; 123 };
124 hrefv60_cfg2 { 124 hrefv60_cfg2 {
125 ste,pins = "GPIO144_B13"; /* NFC_IRQ */ 125 pins = "GPIO144_B13"; /* NFC_IRQ */
126 ste,config = <&gpio_in_pd>; 126 ste,config = <&gpio_in_pd>;
127 }; 127 };
128 }; 128 };
@@ -130,11 +130,11 @@
130 force { 130 force {
131 force_hrefv60_mode: force_hrefv60 { 131 force_hrefv60_mode: force_hrefv60 {
132 hrefv60_cfg1 { 132 hrefv60_cfg1 {
133 ste,pins = "GPIO91_B6"; /* FORCE_SENSING_INT */ 133 pins = "GPIO91_B6"; /* FORCE_SENSING_INT */
134 ste,config = <&gpio_in_pu>; 134 ste,config = <&gpio_in_pu>;
135 }; 135 };
136 hrefv60_cfg2 { 136 hrefv60_cfg2 {
137 ste,pins = 137 pins =
138 "GPIO92_D6", /* FORCE_SENSING_RST */ 138 "GPIO92_D6", /* FORCE_SENSING_RST */
139 "GPIO97_D9"; /* FORCE_SENSING_WU */ 139 "GPIO97_D9"; /* FORCE_SENSING_WU */
140 ste,config = <&gpio_out_lo>; 140 ste,config = <&gpio_out_lo>;
@@ -144,7 +144,7 @@
144 dipro { 144 dipro {
145 dipro_hrefv60_mode: dipro_hrefv60 { 145 dipro_hrefv60_mode: dipro_hrefv60 {
146 hrefv60_cfg1 { 146 hrefv60_cfg1 {
147 ste,pins = "GPIO139_C9"; /* DIPRO_INT */ 147 pins = "GPIO139_C9"; /* DIPRO_INT */
148 ste,config = <&gpio_in_pu>; 148 ste,config = <&gpio_in_pu>;
149 }; 149 };
150 }; 150 };
@@ -153,7 +153,7 @@
153 vaudio_hf_hrefv60_mode: vaudio_hf_hrefv60 { 153 vaudio_hf_hrefv60_mode: vaudio_hf_hrefv60 {
154 /* Audio Amplifier HF enable GPIO */ 154 /* Audio Amplifier HF enable GPIO */
155 hrefv60_cfg1 { 155 hrefv60_cfg1 {
156 ste,pins = "GPIO149_B14"; /* VAUDIO_HF_EN, enable MAX8968 */ 156 pins = "GPIO149_B14"; /* VAUDIO_HF_EN, enable MAX8968 */
157 ste,config = <&gpio_out_hi>; 157 ste,config = <&gpio_out_hi>;
158 }; 158 };
159 }; 159 };
@@ -165,7 +165,7 @@
165 * pull low to reset state 165 * pull low to reset state
166 */ 166 */
167 hrefv60_cfg1 { 167 hrefv60_cfg1 {
168 ste,pins = "GPIO171_D23"; /* GBF_ENA_RESET */ 168 pins = "GPIO171_D23"; /* GBF_ENA_RESET */
169 ste,config = <&gpio_out_lo>; 169 ste,config = <&gpio_out_lo>;
170 }; 170 };
171 }; 171 };
@@ -174,7 +174,7 @@
174 hdtv_hrefv60_mode: hdtv_hrefv60 { 174 hdtv_hrefv60_mode: hdtv_hrefv60 {
175 /* MSP : HDTV INTERFACE GPIO line */ 175 /* MSP : HDTV INTERFACE GPIO line */
176 hrefv60_cfg1 { 176 hrefv60_cfg1 {
177 ste,pins = "GPIO192_AJ27"; 177 pins = "GPIO192_AJ27";
178 ste,config = <&gpio_in_pd>; 178 ste,config = <&gpio_in_pd>;
179 }; 179 };
180 }; 180 };
@@ -187,11 +187,11 @@
187 * reset signals low. 187 * reset signals low.
188 */ 188 */
189 hrefv60_cfg1 { 189 hrefv60_cfg1 {
190 ste,pins = "GPIO143_D12", "GPIO146_D13"; 190 pins = "GPIO143_D12", "GPIO146_D13";
191 ste,config = <&gpio_out_lo>; 191 ste,config = <&gpio_out_lo>;
192 }; 192 };
193 hrefv60_cfg2 { 193 hrefv60_cfg2 {
194 ste,pins = "GPIO67_G2"; 194 pins = "GPIO67_G2";
195 ste,config = <&gpio_in_pu>; 195 ste,config = <&gpio_in_pu>;
196 }; 196 };
197 }; 197 };
@@ -204,11 +204,11 @@
204 * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset) 204 * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset)
205 */ 205 */
206 hrefv60_cfg1 { 206 hrefv60_cfg1 {
207 ste,pins ="GPIO65_F1"; 207 pins ="GPIO65_F1";
208 ste,config = <&gpio_out_hi>; 208 ste,config = <&gpio_out_hi>;
209 }; 209 };
210 hrefv60_cfg2 { 210 hrefv60_cfg2 {
211 ste,pins ="GPIO66_G3"; 211 pins ="GPIO66_G3";
212 ste,config = <&gpio_out_lo>; 212 ste,config = <&gpio_out_lo>;
213 }; 213 };
214 }; 214 };
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-28 02:21:30 -0500